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Sample records for circuits fully integrated

  1. Fully integrated current-mode CMOS gated baseline restorer circuits

    International Nuclear Information System (INIS)

    Design and performance results for three different fully-integrated gated baseline restorer (BLR) circuits used in a new PET current-mode front-end CMOS ASIC are presented. The BLR for each of the three gated integrator channels is a differential current-in to single ended current-out circuit with a correction bandwidth of 100 kHz set by a 40 pF on-chip capacitor using pole splitting techniques. The BLRs for the constant fraction discriminator (CFD) constant fraction and arming comparators are differential current-in to voltage-out circuits with correction bandwidths of 5 MHz and 1 MHz set by on-chip capacitors of 10 pF and 2.5 pF respectively. The BLR circuits are capable of correcting differential input current offsets of ±40 microA for the gated integrator circuits, ±100 microA for the CFD constant fraction comparator circuit, and ± 160 microA for the CFD arming comparator circuit. Use of the BLR circuits allows photomultiplier tube (PMT) detector inputs to be ac coupled and all slow (gated integrator) and fast (CFD timing) signal processing channels to be dc coupled. The BLR circuits correct for count-rate dependent baseline shifts due to detector ac coupling and correct for accumulated CMOS dc offsets in the signal processing channels. Gated integrator input offset currents are maintained below 50 nA, keeping the gated integrator output error below 10 mV for an 850 ns integration period. CFD constant fraction comparator input offset is maintained at sub millivolt levels, and arming comparator threshold is maintained at a 0--0.48 V level under on-board DAC control

  2. Fully integrated circuit chip of microelectronic neural bridge

    International Nuclear Information System (INIS)

    Nerve tracts interruption is one of the major reasons for dysfunction after spiral cord injury. The microelectronic neural bridge is a method to restore function of interrupted neural pathways, by making use of microelectronic chips to bypass the injured nerve tracts. A low-power fully integrated microelectronic neural bridge chip is designed, using CSMC 0.5-μm CMOS technology. The structure and the key points in the circuit design will be introduced in detail. In order to meet the requirement for implantation, the circuit was modified to avoid the use of off-chip components, and fully monolithic integration is achieved. The operating voltage of the circuit is ±2.5 V, and the chip area is 1.21 × 1.18 mm2. According to the characteristic of neural signal, the time-domain method is used in testing. The pass bandwidth of the microelectronic neural bridge system covers the whole frequency range of the neural signal, power consumption is 4.33 mW, and the gain is adjustable. The design goals are achieved. (semiconductor integrated circuits)

  3. Fully Integrated Solar Energy Harvester and Sensor Interface Circuits for Energy-Efficient Wireless Sensing Applications

    OpenAIRE

    Maher Kayal; François Krummenacher; Naser Khosro Pour

    2013-01-01

    This paper presents an energy-efficient solar energy harvesting and sensing microsystem that harvests solar energy from a micro-power photovoltaic module for autonomous operation of a gas sensor. A fully integrated solar energy harvester stores the harvested energy in a rechargeable NiMH microbattery. Hydrogen concentration and temperature are measured and converted to a digital value with 12-bit resolution using a fully integrated sensor interface circuit, and a wireless transceiver is used ...

  4. A compact picosecond pulsed laser source using a fully integrated CMOS driver circuit

    Science.gov (United States)

    He, Yuting; Li, Yuhua; Yadid-Pecht, Orly

    2016-03-01

    Picosecond pulsed laser source have applications in areas such as optical communications, biomedical imaging and supercontinuum generation. Direct modulation of a laser diode with ultrashort current pulses offers a compact and efficient approach to generate picosecond laser pulses. A fully integrated complementary metaloxide- semiconductor (CMOS) driver circuit is designed and applied to operate a 4 GHz distributed feedback laser (DFB). The CMOS driver circuit combines sub-circuits including a voltage-controlled ring oscillator, a voltagecontrolled delay line, an exclusive-or (XOR) circuit and a current source circuit. Ultrashort current pulses are generated by the XOR circuit when the delayed square wave is XOR'ed with the original square wave from the on-chip oscillator. Circuit post-layout simulation shows that output current pulses injected into an equivalent circuit load of the laser have a pulse full width at half maximum (FWHM) of 200 ps, a peak current of 80 mA and a repetition rate of 5.8 MHz. This driver circuit is designed in a 0.13 μm CMOS process and taped out on a 0.3 mm2 chip area. This CMOS chip is packaged and interconnected with the laser diode on a printed circuit board (PCB). The optical output waveform from the laser source is captured by a 5 GHz bandwidth photodiode and an 8 GHz bandwidth oscilloscope. Measured results show that the proposed laser source can output light pulses with a pulse FWHM of 151 ps, a peak power of 6.4 mW (55 mA laser peak forward current) and a repetition rate of 5.3 MHz.

  5. A multi-channel fully differential programmable integrated circuit for neural recording application

    International Nuclear Information System (INIS)

    A multi-channel, fully differential programmable chip for neural recording application is presented. The integrated circuit incorporates eight neural recording amplifiers with tunable bandwidth and gain, eight 4th-order Bessel switch capacitor filters, an 8-to-1 analog time-division multiplexer, a fully differential successive approximation register analog-to-digital converter (SAR ADC), and a serial peripheral interface for communication. The neural recording amplifier presents a programmable gain from 53 dB to 68 dB, a tunable low cut-off frequency from 0.1 Hz to 300 Hz, and 3.77 μVrms input-referred noise over a 5 kHz bandwidth. The SAR ADC digitizes signals at maximum sampling rate of 20 kS/s per channel and achieves an ENOB of 7.4. The integrated circuit is designed and fabricated in 0.18-μm CMOS mix-signal process. We successfully performed a multi-channel in-vivo recording experiment from a rat cortex using the neural recording chip. (semiconductor integrated circuits)

  6. A fully integral, differential, high-speed, low-power consumption CMOS recovery clock circuit

    Directory of Open Access Journals (Sweden)

    Daniel Pacheco Bautista

    2010-04-01

    Full Text Available The clock recovery circuit (CRC plays a fundamental role in electronic information recovery systems (hard disks, DVD and CD read/writeable units and baseband digital communication systems in recovering the clock signal contained in the received data. This signal is necessary for synchronising subsequent information processing. Nowadays, this task is difficult to achieve because of the data’s random nature and its high transfer rate. This paper presents the design of a high-performance integral CMOS technology clock recovery circuit (CRC wor-king at 1.2 Gbps and only consuming 17.4 mW using a 3.3V power supply. The circuit was fully differentially designed to obtain high performance. Circuit architecture was based on a conventional phase lock loop (PLL, current mode logic (MCML and a novel two stage ring-based voltage controlled oscillator (VCO. The design used 0.35 μm CMOS AMS process parameters. Hspice simulation results proved the circuit’s high performance, achieving tracking in less than 300 ns.

  7. PCSIM: a parallel simulation environment for neural circuits fully integrated with Python

    OpenAIRE

    Dejan Pecevski; Thomas Natschläger; Klaus Schuch

    2009-01-01

    The Parallel Circuit SIMulator (PCSIM) is a software package for simulation of neural circuits. It is primarily designed for distributed simulation of large scale networks of spiking point neurons. Although its computational core is written in C++, PCSIM's primary interface is implemented in the Python programming language, which is a powerful programming environment and allows the user to easily integrate the neural circuit simulator with data analysis and visualization tools to manage...

  8. PCSIM: A Parallel Simulation Environment for Neural Circuits Fully Integrated with Python

    OpenAIRE

    Pecevski, Dejan; Natschläger, Thomas; Schuch, Klaus

    2009-01-01

    The Parallel Circuit SIMulator (PCSIM) is a software package for simulation of neural circuits. It is primarily designed for distributed simulation of large scale networks of spiking point neurons. Although its computational core is written in C++, PCSIM's primary interface is implemented in the Python programming language, which is a powerful programming environment and allows the user to easily integrate the neural circuit simulator with data analysis and visualization tools to manage the f...

  9. Fully Integrated Low-Noise Readout Circuit with Automatic Offset Cancellation Loop for Capacitive Microsensors

    Directory of Open Access Journals (Sweden)

    Haryong Song

    2015-10-01

    Full Text Available Capacitive sensing schemes are widely used for various microsensors; however, such microsensors suffer from severe parasitic capacitance problems. This paper presents a fully integrated low-noise readout circuit with automatic offset cancellation loop (AOCL for capacitive microsensors. The output offsets of the capacitive sensing chain due to the parasitic capacitances and process variations are automatically removed using AOCL. The AOCL generates electrically equivalent offset capacitance and enables charge-domain fine calibration using a 10-bit R-2R digital-to-analog converter, charge-transfer switches, and a charge-storing capacitor. The AOCL cancels the unwanted offset by binary-search algorithm based on 10-bit successive approximation register (SAR logic. The chip is implemented using 0.18 μm complementary metal-oxide-semiconductor (CMOS process with an active area of 1.76 mm2. The power consumption is 220 μW with 3.3 V supply. The input parasitic capacitances within the range of −250 fF to 250 fF can be cancelled out automatically, and the required calibration time is lower than 10 ms.

  10. PCSIM: a parallel simulation environment for neural circuits fully integrated with Python

    Directory of Open Access Journals (Sweden)

    Dejan Pecevski

    2009-05-01

    Full Text Available The Parallel Circuit SIMulator (PCSIM is a software package for simulation of neural circuits. It is primarily designed for distributed simulation of large scale networks of spiking point neurons. Although its computational core is written in C++, PCSIM's primary interface is implemented in the Python programming language, which is a powerful programming environment and allows the user to easily integrate the neural circuit simulator with data analysis and visualization tools to manage the full neural modeling life cycle. The main focus of this paper is to describe PCSIM's full integration into Python and the benefits thereof. In particular we will investigate how the automatically generated bidirectional interface and PCSIM's object-oriented modular framework enable the user to adopt a hybrid modeling approach: using and extending PCSIM's functionality either employing pure Python or C++ and thus combining the advantages of both worlds. Furthermore, we describe several supplementary PCSIM packages written in pure Python and tailored towards setting up and analyzing neural simulations.

  11. Fully CMOS Memristor Based Chaotic Circuit

    OpenAIRE

    Yener, S. C.; H. H. Kuntman

    2014-01-01

    This paper demonstrates the design of a fully CMOS chaotic circuit consisting of only DDCC based memristor and inductance simulator. Our design is composed of these active blocks using CMOS 0.18 µm process technology with symmetric ±1.25 V supply voltages. A new single DDCC+ based topology is used as the inductance simulator. Simulation results verify that the design proposed satisfies both memristor properties and the chaotic behavior of the circuit. Simulations performed illustrate the succ...

  12. Fully CMOS Memristor Based Chaotic Circuit

    Directory of Open Access Journals (Sweden)

    S. C. Yener

    2014-12-01

    Full Text Available This paper demonstrates the design of a fully CMOS chaotic circuit consisting of only DDCC based memristor and inductance simulator. Our design is composed of these active blocks using CMOS 0.18 µm process technology with symmetric ±1.25 V supply voltages. A new single DDCC+ based topology is used as the inductance simulator. Simulation results verify that the design proposed satisfies both memristor properties and the chaotic behavior of the circuit. Simulations performed illustrate the success of the proposed design for the realization of CMOS based chaotic applications.

  13. Linear integrated circuits

    Science.gov (United States)

    Young, T.

    This book is intended to be used as a textbook in a one-semester course at a variety of levels. Because of self-study features incorporated, it may also be used by practicing electronic engineers as a formal and thorough introduction to the subject. The distinction between linear and digital integrated circuits is discussed, taking into account digital and linear signal characteristics, linear and digital integrated circuit characteristics, the definitions for linear and digital circuits, applications of digital and linear integrated circuits, aspects of fabrication, packaging, and classification and numbering. Operational amplifiers are considered along with linear integrated circuit (LIC) power requirements and power supplies, voltage and current regulators, linear amplifiers, linear integrated circuit oscillators, wave-shaping circuits, active filters, DA and AD converters, demodulators, comparators, instrument amplifiers, current difference amplifiers, analog circuits and devices, and aspects of troubleshooting.

  14. MOS integrated circuit design

    CERN Document Server

    Wolfendale, E

    2013-01-01

    MOS Integral Circuit Design aims to help in the design of integrated circuits, especially large-scale ones, using MOS Technology through teaching of techniques, practical applications, and examples. The book covers topics such as design equation and process parameters; MOS static and dynamic circuits; logic design techniques, system partitioning, and layout techniques. Also featured are computer aids such as logic simulation and mask layout, as well as examples on simple MOS design. The text is recommended for electrical engineers who would like to know how to use MOS for integral circuit desi

  15. Development for Germanium Blocked Impurity Band Far-Infrared Image Sensors with Fully-Depleted Silicon-On-Insulator CMOS Readout Integrated Circuit

    Science.gov (United States)

    Wada, T.; Arai, Y.; Baba, S.; Hanaoka, M.; Hattori, Y.; Ikeda, H.; Kaneda, H.; Kochi, C.; Miyachi, A.; Nagase, K.; Nakaya, H.; Ohno, M.; Oyabu, S.; Suzuki, T.; Ukai, S.; Watanabe, K.; Yamamoto, K.

    2016-07-01

    We are developing far-infrared (FIR) imaging sensors for low-background and high-sensitivity applications such as infrared astronomy. Previous FIR monolithic imaging sensors, such as an extrinsic germanium photo-conductor (Ge PC) with a PMOS readout integrated circuit (ROIC) hybridized by indium pixel-to-pixel interconnection, had three difficulties: (1) short cut-off wavelength (120 \\upmu m), (2) large power consumption (10 \\upmu W/pixel), and (3) large mismatch in thermal expansion between the Ge PC and the Si ROIC. In order to overcome these difficulties, we developed (1) a blocked impurity band detector fabricated by a surface- activated bond technology, whose cut-off wavelength is longer than 160 \\upmu m, (2) a fully-depleted silicon-on-insulator CMOS ROIC which works below 4 K with 1 \\upmu W/pixel operating power, and (3) a new concept, Si-supported Ge detector, which shows tolerance to thermal cycling down to 3 K. With these new techniques, we are now developing a 32 × 32 FIR imaging sensor.

  16. Compound semiconductor integrated circuits

    CERN Document Server

    Vu, Tho T

    2003-01-01

    This is the book version of a special issue of the International Journal of High Speed Electronics and Systems , reviewing recent work in the field of compound semiconductor integrated circuits. There are fourteen invited papers covering a wide range of applications, frequencies and materials. These papers deal with digital, analog, microwave and millimeter-wave technologies, devices and integrated circuits for wireline fiber-optic lightwave transmissions, and wireless radio-frequency microwave and millimeter-wave communications. In each case, the market is young and experiencing rapid growth

  17. Photonic Integrated Circuits

    Science.gov (United States)

    Merritt, Scott; Krainak, Michael

    2016-01-01

    Integrated photonics generally is the integration of multiple lithographically defined photonic and electronic components and devices (e.g. lasers, detectors, waveguides passive structures, modulators, electronic control and optical interconnects) on a single platform with nanometer-scale feature sizes. The development of photonic integrated circuits permits size, weight, power and cost reductions for spacecraft microprocessors, optical communication, processor buses, advanced data processing, and integrated optic science instrument optical systems, subsystems and components. This is particularly critical for small spacecraft platforms. We will give an overview of some NASA applications for integrated photonics.

  18. Radio frequency integrated circuit design

    CERN Document Server

    Rogers, John W M

    2010-01-01

    This newly revised and expanded edition of the 2003 Artech House classic, Radio Frequency Integrated Circuit Design, serves as an up-to-date, practical reference for complete RFIC know-how. The second edition includes numerous updates, including greater coverage of CMOS PA design, RFIC design with on-chip components, and more worked examples with simulation results. By emphasizing working designs, this book practically transports you into the authors' own RFIC lab so you can fully understand the function of each design detailed in this book. Among the RFIC designs examined are RF integrated LC

  19. Biophotonic integrated circuits

    Science.gov (United States)

    Cohen, Daniel A.; Nolde, Jill A.; Wang, Chad S.; Skogen, Erik J.; Rivlin, A.; Coldren, Larry A.

    2004-12-01

    Biosensors rely on optical techniques to obtain high sensitivity and speed, but almost all biochips still require external light sources, optics, and detectors, which limits the widespread use of these devices. The optoelectronics technology base now allows monolithic integration of versatile optical sources, novel sensing geometries, filters, spectrometers, and detectors, enabling highly integrated chip-scale sensors. We discuss biophotonic integrated circuits built on both GaAs and InP substrates, incorporating widely tunable lasers, novel evanescent field sensing waveguides, heterodyne spectrometers, and waveguide photodetectors, suitable for high sensitivity transduction of affinity assays.

  20. Integrated Circuit Immunity

    Science.gov (United States)

    Sketoe, J. G.; Clark, Anthony

    2000-01-01

    This paper presents a DOD E3 program overview on integrated circuit immunity. The topics include: 1) EMI Immunity Testing; 2) Threshold Definition; 3) Bias Tee Function; 4) Bias Tee Calibration Set-Up; 5) EDM Test Figure; 6) EMI Immunity Levels; 7) NAND vs. and Gate Immunity; 8) TTL vs. LS Immunity Levels; 9) TP vs. OC Immunity Levels; 10) 7805 Volt Reg Immunity; and 11) Seventies Chip Set. This paper is presented in viewgraph form.

  1. Semiconductor integrated circuits

    International Nuclear Information System (INIS)

    An improved method involving ion implantation to form non-epitaxial semiconductor integrated circuits. These are made by forming a silicon substrate of one conductivity type with a recessed silicon dioxide region extending into the substrate and enclosing a portion of the silicon substrate. A beam of ions of opposite conductivity type impurity is directed at the substrate at an energy and dosage level sufficient to form a first region of opposite conductivity within the silicon dioxide region. This impurity having a concentration peak below the surface of the substrate forms a region of the one conductivity type which extends from the substrate surface into the first opposite type region to a depth between the concentration peak and the surface and forms a second region of opposite conductivity type. The method, materials and ion beam conditions are detailed. Vertical bipolar integrated circuits can be made this way when the first opposite type conductivity region will function as a collector. Also circuits with inverted bipolar devices when this first region functions as a 'buried'' emitter region. (U.K.)

  2. Integrated circuit cell library

    Science.gov (United States)

    Whitaker, Sterling R. (Inventor); Miles, Lowell H. (Inventor)

    2005-01-01

    According to the invention, an ASIC cell library for use in creation of custom integrated circuits is disclosed. The ASIC cell library includes some first cells and some second cells. Each of the second cells includes two or more kernel cells. The ASIC cell library is at least 5% comprised of second cells. In various embodiments, the ASIC cell library could be 10% or more, 20% or more, 30% or more, 40% or more, 50% or more, 60% or more, 70% or more, 80% or more, 90% or more, or 95% or more comprised of second cells.

  3. Linear integrated circuits

    CERN Document Server

    Carr, Joseph

    1996-01-01

    The linear IC market is large and growing, as is the demand for well trained technicians and engineers who understand how these devices work and how to apply them. Linear Integrated Circuits provides in-depth coverage of the devices and their operation, but not at the expense of practical applications in which linear devices figure prominently. This book is written for a wide readership from FE and first degree students, to hobbyists and professionals.Chapter 1 offers a general introduction that will provide students with the foundations of linear IC technology. From chapter 2 onwa

  4. Adaptive synchronization of Chua's circuits with fully unknown parameters

    International Nuclear Information System (INIS)

    This study addresses adaptive synchronization of the original Chua's circuit and the modified Chua's circuit with x vertical bar x vertical bar when the parameters of the drive system are fully unknown and different with those of the response system. Based on Lyapunov stability theory, the sufficient conditions for the synchronization have been derived theoretically. Numerical simulations are presented to verify that synchronization can be achieved by using this approach

  5. Integrated coherent matter wave circuits

    International Nuclear Information System (INIS)

    An integrated coherent matter wave circuit is a single device, analogous to an integrated optical circuit, in which coherent de Broglie waves are created and then launched into waveguides where they can be switched, divided, recombined, and detected as they propagate. Applications of such circuits include guided atom interferometers, atomtronic circuits, and precisely controlled delivery of atoms. We report experiments demonstrating integrated circuits for guided coherent matter waves. The circuit elements are created with the painted potential technique, a form of time-averaged optical dipole potential in which a rapidly moving, tightly focused laser beam exerts forces on atoms through their electric polarizability. Moreover, the source of coherent matter waves is a Bose-Einstein condensate (BEC). Finally, we launch BECs into painted waveguides that guide them around bends and form switches, phase coherent beamsplitters, and closed circuits. These are the basic elements that are needed to engineer arbitrarily complex matter wave circuitry

  6. Postirradiation Effects In Integrated Circuits

    Science.gov (United States)

    Shaw, David C.; Barnes, Charles E.

    1993-01-01

    Two reports discuss postirradiation effects in integrated circuits. Presents examples of postirradiation measurements of performances of integrated circuits of five different types: dual complementary metal oxide/semiconductor (CMOS) flip-flop; CMOS analog multiplier; two CMOS multiplying digital-to-analog converters; electrically erasable programmable read-only memory; and semiconductor/oxide/semiconductor octal buffer driver.

  7. Synthetic Biology: Integrated Gene Circuits

    OpenAIRE

    Nandagopal, Nagarajan; Michael B Elowitz

    2011-01-01

    A major goal of synthetic biology is to develop a deeper understanding of biological design principles from the bottom up, by building circuits and studying their behavior in cells. Investigators initially sought to design circuits “from scratch” that functioned as independently as possible from the underlying cellular system. More recently, researchers have begun to develop a new generation of synthetic circuits that integrate more closely with endogenous cellular processes. These approaches...

  8. Electronic design with integrated circuits

    Science.gov (United States)

    Comer, D. J.

    The book is concerned with the application of integrated circuits and presents the material actually needed by the system designer to do an effective job. The operational amplifier (op amp) is discussed, taking into account the electronic amplifier, the basic op amp, the practical op amp, analog applications, and digital applications. Digital components are considered along with combinational logic, digital subsystems, the microprocessor, special circuits, communications, and integrated circuit building blocks. Attention is given to logic gates, logic families, multivibrators, the digital computer, digital methods, communicating with a computer, computer organization, register and timing circuits for data transfer, arithmetic circuits, memories, the microprocessor chip, the control unit, communicating with the microprocessor, examples of microprocessor architecture, programming a microprocessor, the voltage-controlled oscillator, the phase-locked loop, analog-to-digital conversion, amplitude modulation, frequency modulation, pulse and digital transmission, the semiconductor diode, the bipolar transistor, and the field-effect transistor.

  9. Dynamical properties of electrical circuits with fully nonlinear memristors

    CERN Document Server

    Riaza, Ricardo

    2010-01-01

    The recent design of a nanoscale device with a memristive characteristic has had a great impact in nonlinear circuit theory. Such a device, whose existence was predicted by Leon Chua in 1971, is governed by a charge-dependent voltage-current relation of the form $v=M(q)i$. In this paper we show that allowing for a fully nonlinear characteristic $v=\\eta(q, i)$ in memristive devices provides a general framework for modeling and analyzing a very broad family of electrical and electronic circuits; Chua's memristors are particular instances in which $\\eta(q,i)$ is linear in $i$. We examine several dynamical features of circuits with fully nonlinear memristors, accommodating not only charge-controlled but also flux-controlled ones, with a characteristic of the form $i=\\zeta(\\varphi, v)$. Our results apply in particular to Chua's memristive circuits; certain properties of these can be seen as a consequence of the special form of the elastance and reluctance matrices displayed by Chua's memristors.

  10. Variational integrators for electric circuits

    International Nuclear Information System (INIS)

    In this contribution, we develop a variational integrator for the simulation of (stochastic and multiscale) electric circuits. When considering the dynamics of an electric circuit, one is faced with three special situations: 1. The system involves external (control) forcing through external (controlled) voltage sources and resistors. 2. The system is constrained via the Kirchhoff current (KCL) and voltage laws (KVL). 3. The Lagrangian is degenerate. Based on a geometric setting, an appropriate variational formulation is presented to model the circuit from which the equations of motion are derived. A time-discrete variational formulation provides an iteration scheme for the simulation of the electric circuit. Dependent on the discretization, the intrinsic degeneracy of the system can be canceled for the discrete variational scheme. In this way, a variational integrator is constructed that gains several advantages compared to standard integration tools for circuits; in particular, a comparison to BDF methods (which are usually the method of choice for the simulation of electric circuits) shows that even for simple LCR circuits, a better energy behavior and frequency spectrum preservation can be observed using the developed variational integrator

  11. Is a fully heparin-bonded cardiopulmonary bypass circuit superior to a standard cardiopulmonary bypass circuit?

    OpenAIRE

    Mahmood, Sarah; Bilal, Haris; Zaman, Mahvash; Tang, Augustine

    2012-01-01

    A best-evidence topic in cardiac surgery was written according to a structured protocol. The question addressed was ‘Is a fully heparin bonded cardiopulmonary bypass circuit superior to a standard cardiopulmonary bypass circuit?’ Altogether more than 792 papers were found using the reported search, of which 13 represented the best evidence to answer the clinical question. The authors, journal, date and country of publication, patient group studied, study type, relevant outcomes and results of...

  12. Fully integrated, fully automated generation of short tandem repeat profiles

    OpenAIRE

    Tan, Eugene; Rosemary S. Turingan; Hogan, Catherine; Vasantgadkar, Sameer; Palombo, Luke; Schumm, James W.; Richard F Selden

    2013-01-01

    Background The generation of short tandem repeat profiles, also referred to as ‘DNA typing,’ is not currently performed outside the laboratory because the process requires highly skilled technical operators and a controlled laboratory environment and infrastructure with several specialized instruments. The goal of this work was to develop a fully integrated system for the automated generation of short tandem repeat profiles from buccal swab samples, to improve forensic laboratory process flow...

  13. GaAs Optoelectronic Integrated-Circuit Neurons

    Science.gov (United States)

    Lin, Steven H.; Kim, Jae H.; Psaltis, Demetri

    1992-01-01

    Monolithic GaAs optoelectronic integrated circuits developed for use as artificial neurons. Neural-network computer contains planar arrays of optoelectronic neurons, and variable synaptic connections between neurons effected by diffraction of light from volume hologram in photorefractive material. Basic principles of neural-network computers explained more fully in "Optoelectronic Integrated Circuits For Neural Networks" (NPO-17652). In present circuits, devices replaced by metal/semiconductor field effect transistors (MESFET's), which consume less power.

  14. Chip-scale fully reconfigurable optical add/drop multiplexing subsystem in polymer microphotonic circuits

    Science.gov (United States)

    Izuhara, Tomoyuki; Fujita, Junichiro; Radojevic, Antonije; Gerhardt, Reinald; Eldada, Louay A.

    2004-10-01

    We report on a highly integrated photonic circuit using a polymer-based planar waveguide system. The properties of the materials used in this work such as ultra-low optical loss, widely tunable refractive index, and large thermo-optic coefficient, enable a multi-functional chip-scale microphotonic circuit. We discuss the application of this technology to the fabrication of a fully reconfigurable optical add/drop multiplexer. This subsystem includes channel switching, power monitoring, load balancing, and wavelength shuffling functionalities that are required for agile wavelength-division multiplexing optical networks. Optical properties of our material systems and performance characteristics of the implemented optical passive/active elements are presented, and the integration schemes of the devices to achieve a fully integrated reconfigurable optical add/drop multiplexer are discussed.

  15. Vertically Integrated Circuits at Fermilab

    Energy Technology Data Exchange (ETDEWEB)

    Deptuch, Grzegorz; Demarteau, Marcel; Hoff, James; Lipton, Ronald; Shenai, Alpana; Trimpl, Marcel; Yarema, Raymond; Zimmerman, Tom; /Fermilab

    2009-01-01

    The exploration of the vertically integrated circuits, also commonly known as 3D-IC technology, for applications in radiation detection started at Fermilab in 2006. This paper examines the opportunities that vertical integration offers by looking at various 3D designs that have been completed by Fermilab. The emphasis is on opportunities that are presented by through silicon vias (TSV), wafer and circuit thinning and finally fusion bonding techniques to replace conventional bump bonding. Early work by Fermilab has led to an international consortium for the development of 3D-IC circuits for High Energy Physics. The consortium has submitted over 25 different designs for the Fermilab organized MPW run organized for the first time.

  16. Design automation for integrated circuits

    Science.gov (United States)

    Newell, S. B.; de Geus, A. J.; Rohrer, R. A.

    1983-04-01

    Consideration is given to the development status of the use of computers in automated integrated circuit design methods, which promise the minimization of both design time and design error incidence. Integrated circuit design encompasses two major tasks: error specification, in which the goal is a logic diagram that accurately represents the desired electronic function, and physical specification, in which the goal is an exact description of the physical locations of all circuit elements and their interconnections on the chip. Design automation not only saves money by reducing design and fabrication time, but also helps the community of systems and logic designers to work more innovatively. Attention is given to established design automation methodologies, programmable logic arrays, and design shortcuts.

  17. MOS integrated circuit fault modeling

    Science.gov (United States)

    Sievers, M.

    1985-01-01

    Three digital simulation techniques for MOS integrated circuit faults were examined. These techniques embody a hierarchy of complexity bracketing the range of simulation levels. The digital approaches are: transistor-level, connector-switch-attenuator level, and gate level. The advantages and disadvantages are discussed. Failure characteristics are also described.

  18. Testing Superconductor Logic Integrated Circuits

    OpenAIRE

    Joseph, Arun A.; Kerkhoff, Hans G.

    2005-01-01

    Superconductor logic has the potential of extremely low-power consumption and ultra-fast digital signal processing. Unfortunately, the obtained yield of the present processes is low and specific faults occur. This paper deals with fault-modelling, Design-for-Test structures, and ATPG for these integrated circuits.

  19. Circuit Theory for SPICE of Spintronic Integrated Circuits

    OpenAIRE

    Manipatruni, Sasikanth; Nikonov, Dmitri E.; Young, Ian A.

    2011-01-01

    We present a theoretical and a numerical formalism for analysis and design of spintronic integrated circuits (SPINICs). The formalism encompasses a generalized circuit theory for spintronic integrated circuits based on nanomagnetic dynamics and spin transport. We propose an extension to the Modified Nodal Analysis technique for the analysis of spin circuits based on the recently developed spin conduction matrices. We demonstrate the applicability of the framework using an example spin logic c...

  20. Delay locked loop integrated circuit.

    Energy Technology Data Exchange (ETDEWEB)

    Brocato, Robert Wesley

    2007-10-01

    This report gives a description of the development of a Delay Locked Loop (DLL) integrated circuit (IC). The DLL was developed and tested as a stand-alone IC test chip to be integrated into a larger application specific integrated circuit (ASIC), the Quadrature Digital Waveform Synthesizer (QDWS). The purpose of the DLL is to provide a digitally programmable delay to enable synchronization between an internal system clock and external peripherals with unknown clock skew. The DLL was designed and fabricated in the IBM 8RF process, a 0.13 {micro}m CMOS process. It was designed to operate with a 300MHz clock and has been tested up to 500MHz.

  1. Microcontroller based Integrated Circuit Tester

    OpenAIRE

    Yousif Taha Yousif Elamin; Abdelrasoul Jabar Alzubaidi

    2015-01-01

    The digital integrated circuit (IC) tester is implemented by using the ATmega32 microcontroller . The microcontroller processes the inputs and outputs and displays the results on a Liquid Crystal Display (LCD). The basic function of the digital IC tester is to test a digital IC for correct logical functioning as described in the truth table and/or function table. The designed model can test digital ICs having 14 pins. Since it is programmable, any number of ICs can be tested . Thi...

  2. Integrated circuits for multimedia applications

    DEFF Research Database (Denmark)

    Vandi, Luca

    2007-01-01

    This work presents several key aspects in the design of RF integrated circuits for portable multimedia devices. One chapter is dedicated to the application of negative-feedback topologies to receiver frontends. A novel feedback technique suitable for common multiplier-based mixers is described, and...... it is applied to a broad-band dual-loop receiver architecture in order to boost the linearity performances of the stage. A simplified noise- and linearity analysis of the circuit is derived, and a comparison is provided with a more traditional dual-loop topology (a broad-band stage based on shunt...... for the performances of the stage. Semi-ideal models are used in simulations to validate the derived calculations, and the fundamental limits of the basic structure are discussed. The design of a current-mode base-band output stage implemented in a 0.13um technology is presented: the amplifier draws...

  3. Fully integrated biochip platforms for advanced healthcare.

    Science.gov (United States)

    Carrara, Sandro; Ghoreishizadeh, Sara; Olivo, Jacopo; Taurino, Irene; Baj-Rossi, Camilla; Cavallini, Andrea; de Beeck, Maaike Op; Dehollain, Catherine; Burleson, Wayne; Moussy, Francis Gabriel; Guiseppi-Elie, Anthony; De Micheli, Giovanni

    2012-01-01

    Recent advances in microelectronics and biosensors are enabling developments of innovative biochips for advanced healthcare by providing fully integrated platforms for continuous monitoring of a large set of human disease biomarkers. Continuous monitoring of several human metabolites can be addressed by using fully integrated and minimally invasive devices located in the sub-cutis, typically in the peritoneal region. This extends the techniques of continuous monitoring of glucose currently being pursued with diabetic patients. However, several issues have to be considered in order to succeed in developing fully integrated and minimally invasive implantable devices. These innovative devices require a high-degree of integration, minimal invasive surgery, long-term biocompatibility, security and privacy in data transmission, high reliability, high reproducibility, high specificity, low detection limit and high sensitivity. Recent advances in the field have already proposed possible solutions for several of these issues. The aim of the present paper is to present a broad spectrum of recent results and to propose future directions of development in order to obtain fully implantable systems for the continuous monitoring of the human metabolism in advanced healthcare applications. PMID:23112644

  4. Fully Integrated Biochip Platforms for Advanced Healthcare

    Science.gov (United States)

    Carrara, Sandro; Ghoreishizadeh, Sara; Olivo, Jacopo; Taurino, Irene; Baj-Rossi, Camilla; Cavallini, Andrea; de Beeck, Maaike Op; Dehollain, Catherine; Burleson, Wayne; Moussy, Francis Gabriel; Guiseppi-Elie, Anthony; De Micheli, Giovanni

    2012-01-01

    Recent advances in microelectronics and biosensors are enabling developments of innovative biochips for advanced healthcare by providing fully integrated platforms for continuous monitoring of a large set of human disease biomarkers. Continuous monitoring of several human metabolites can be addressed by using fully integrated and minimally invasive devices located in the sub-cutis, typically in the peritoneal region. This extends the techniques of continuous monitoring of glucose currently being pursued with diabetic patients. However, several issues have to be considered in order to succeed in developing fully integrated and minimally invasive implantable devices. These innovative devices require a high-degree of integration, minimal invasive surgery, long-term biocompatibility, security and privacy in data transmission, high reliability, high reproducibility, high specificity, low detection limit and high sensitivity. Recent advances in the field have already proposed possible solutions for several of these issues. The aim of the present paper is to present a broad spectrum of recent results and to propose future directions of development in order to obtain fully implantable systems for the continuous monitoring of the human metabolism in advanced healthcare applications. PMID:23112644

  5. Integrated Circuit Electromagnetic Immunity Handbook

    Science.gov (United States)

    Sketoe, J. G.

    2000-08-01

    This handbook presents the results of the Boeing Company effort for NASA under contract NAS8-98217. Immunity level data for certain integrated circuit parts are discussed herein, along with analytical techniques for applying the data to electronics systems. This handbook is built heavily on the one produced in the seventies by McDonnell Douglas Astronautics Company (MDAC, MDC Report E1929 of 1 August 1978, entitled Integrated Circuit Electromagnetic Susceptibility Handbook, known commonly as the ICES Handbook, which has served countless systems designers for over 20 years). Sections 2 and 3 supplement the device susceptibility data presented in section 4 by presenting information on related material required to use the IC susceptibility information. Section 2 concerns itself with electromagnetic susceptibility analysis and serves as a guide in using the information contained in the rest of the handbook. A suggested system hardening requirements is presented in this chapter. Section 3 briefly discusses coupling and shielding considerations. For conservatism and simplicity, a worst case approach is advocated to determine the maximum amount of RF power picked up from a given field. This handbook expands the scope of the immunity data in this Handbook is to of 10 MHz to 10 GHz. However, the analytical techniques provided are applicable to much higher frequencies as well. It is expected however, that the upper frequency limit of concern is near 10 GHz. This is due to two factors; the pickup of microwave energy on system cables and wiring falls off as the square of the wavelength, and component response falls off at a rapid rate due to the effects of parasitic shunt paths for the RF energy. It should be noted also that the pickup on wires and cables does not approach infinity as the frequency decreases (as would be expected by extrapolating the square law dependence of the high frequency roll-off to lower frequencies) but levels off due to mismatch effects.

  6. Active components for integrated plasmonic circuits

    DEFF Research Database (Denmark)

    Krasavin, A.V.; Bolger, P.M.; Zayats, A.V.;

    2009-01-01

    We present a comprehensive study of highly efficient and compact passive and active components for integrated plasmonic circuit based on dielectric-loaded surface plasmon polariton waveguides.......We present a comprehensive study of highly efficient and compact passive and active components for integrated plasmonic circuit based on dielectric-loaded surface plasmon polariton waveguides....

  7. Post irradiation effects (PIE) in integrated circuits

    International Nuclear Information System (INIS)

    Post Irradiation Effects (PIE) ranging from normal recovery catastrophic failure have been observed in integrated circuits during the PIE period. These variations indicate that a rebound or PIE recipe used for radiation hardness assurance must be chosen with care. In this paper, the authors provide examples of PIE in a variety of integrated circuits of importance to spacecraft electronics

  8. Microcontroller based Integrated Circuit Tester

    Directory of Open Access Journals (Sweden)

    Yousif Taha Yousif Elamin

    2015-02-01

    Full Text Available The digital integrated circuit (IC tester is implemented by using the ATmega32 microcontroller . The microcontroller processes the inputs and outputs and displays the results on a Liquid Crystal Display (LCD. The basic function of the digital IC tester is to test a digital IC for correct logical functioning as described in the truth table and/or function table. The designed model can test digital ICs having 14 pins. Since it is programmable, any number of ICs can be tested . This model applies the necessary signals to the inputs of the IC, monitoring the outputs at each stage and comparing them with the outputs in the truth table. Any discrepancy in the functioning of the IC results in a fail indication, displays the faulty and good gates on the LCD. The testing procedure is accomplished with the help of keypad keys present on the main board design. The test has been accomplished with most commonly used digital IC's, mainly belonging to the 74 series. Digital IC tester tests three samples of IC's ( NAND, NOT, NOR. The design is flexible . We can add extra IC bases and subroutines to test any other IC in the 74 series.

  9. Analog VLSI neural network integrated circuits

    Science.gov (United States)

    Kub, F. J.; Moon, K. K.; Just, E. A.

    1991-01-01

    Two analog very large scale integration (VLSI) vector matrix multiplier integrated circuit chips were designed, fabricated, and partially tested. They can perform both vector-matrix and matrix-matrix multiplication operations at high speeds. The 32 by 32 vector-matrix multiplier chip and the 128 by 64 vector-matrix multiplier chip were designed to perform 300 million and 3 billion multiplications per second, respectively. An additional circuit that has been developed is a continuous-time adaptive learning circuit. The performance achieved thus far for this circuit is an adaptivity of 28 dB at 300 KHz and 11 dB at 15 MHz. This circuit has demonstrated greater than two orders of magnitude higher frequency of operation than any previous adaptive learning circuit.

  10. Integrated-Circuit Pseudorandom-Number Generator

    Science.gov (United States)

    Steelman, James E.; Beasley, Jeff; Aragon, Michael; Ramirez, Francisco; Summers, Kenneth L.; Knoebel, Arthur

    1992-01-01

    Integrated circuit produces 8-bit pseudorandom numbers from specified probability distribution, at rate of 10 MHz. Use of Boolean logic, circuit implements pseudorandom-number-generating algorithm. Circuit includes eight 12-bit pseudorandom-number generators, outputs are uniformly distributed. 8-bit pseudorandom numbers satisfying specified nonuniform probability distribution are generated by processing uniformly distributed outputs of eight 12-bit pseudorandom-number generators through "pipeline" of D flip-flops, comparators, and memories implementing conditional probabilities on zeros and ones.

  11. Semiconductors integrated circuit design for manufacturability

    CERN Document Server

    Balasinki, Artur

    2011-01-01

    Because of the continuous evolution of integrated circuit manufacturing (ICM) and design for manufacturability (DfM), most books on the subject are obsolete before they even go to press. That's why the field requires a reference that takes the focus off of numbers and concentrates more on larger economic concepts than on technical details. Semiconductors: Integrated Circuit Design for Manufacturability covers the gradual evolution of integrated circuit design (ICD) as a basis to propose strategies for improving return-on-investment (ROI) for ICD in manufacturing. Where most books put the spotl

  12. LC Quadrature Generation in Integrated Circuits

    DEFF Research Database (Denmark)

    Christensen, Kåre Tais

    2001-01-01

    Today quadrature signals for IQ demodulation are provided through RC polyphase networks, quadrature oscillators or double frequency VCOs. This paper presents a new method for generating quadrature signals in integrated circuits using only inductors and capacitors. This LC quadrature generation...

  13. Lateral power transistors in integrated circuits

    CERN Document Server

    Erlbacher, Tobias

    2014-01-01

    This book details and compares recent advancements in the development of novel lateral power transistors (LDMOS devices) for integrated circuits in power electronic applications. It includes the state-of-the-art concept of double-acting RESURF topologies.

  14. Bottom-up organic integrated circuits

    OpenAIRE

    Smits, Edsger C. P; Mathijssen, Simon G. J.; van Hal, Paul A.; Setayesh, Sepas; Geuns, Thomas C. T.; Mutsaers, Kees A. H. A.; Cantatore, Eugenio; Wondergem, Harry J.; Werzer, Oliver; Resel, Roland; Kemerink, Martijn; Kirchmeyer, Stephan; Muzafarov, Aziz M.; Ponomarenko, Sergei A.; de Boer, Bert

    2008-01-01

    Self- assembly - the autonomous organization of components into patterns and structures(1) - is a promising technology for the mass production of organic electronics. Making integrated circuits using a bottom- up approach involving self- assembling molecules was proposed(2) in the 1970s. The basic building block of such an integrated circuit is the self- assembled- monolayer field- effect transistor ( SAMFET), where the semiconductor is a monolayer spontaneously formed on the gate dielectric....

  15. Integrated Circuit Stellar Magnitude Simulator

    Science.gov (United States)

    Blackburn, James A.

    1978-01-01

    Describes an electronic circuit which can be used to demonstrate the stellar magnitude scale. Six rectangular light-emitting diodes with independently adjustable duty cycles represent stars of magnitudes 1 through 6. Experimentally verifies the logarithmic response of the eye. (Author/GA)

  16. Radio-frequency integrated-circuit engineering

    CERN Document Server

    Nguyen, Cam

    2015-01-01

    Radio-Frequency Integrated-Circuit Engineering addresses the theory, analysis and design of passive and active RFIC's using Si-based CMOS and Bi-CMOS technologies, and other non-silicon based technologies. The materials covered are self-contained and presented in such detail that allows readers with only undergraduate electrical engineering knowledge in EM, RF, and circuits to understand and design RFICs. Organized into sixteen chapters, blending analog and microwave engineering, Radio-Frequency Integrated-Circuit Engineering emphasizes the microwave engineering approach for RFICs. Provide

  17. Monolithic microwave integrated circuit with integral array antenna

    International Nuclear Information System (INIS)

    A monolithic microwave integrated circuit including an integral array antenna. The system includes radiating elements, feed network, phasing network, active and/or passive semiconductor devices, digital logic interface circuits and a microcomputer controller simultaneously incorporated on a single substrate by means of a controlled fabrication process sequence

  18. Progress in organic integrated circuit manufacture

    Science.gov (United States)

    Taylor, D. Martin

    2016-02-01

    This review article focuses on the development of processes for the manufacture of organic electronic circuits. Beginning with the first report of an organic transistor it highlights the key developments leading to the successful manufacture of microprocessors and other complex circuits incorporating organic transistors. Both batch processing (based on silicon integrated circuit technology) as well as mass-printing, roll-to-roll (R2R) approaches are discussed. Currently, the best circuit performances are achieved using batch processing. It is suggested that an emerging, large mass-market for electronic tags may dictate that R2R manufacture will likely be required to meet the high throughput rates needed. However, significant improvements in resolution and registration are necessary to achieve increased circuit operating speeds.

  19. Vertical interconnection of SOI photonic integrated circuits

    NARCIS (Netherlands)

    Hagen, R.; Pozo Torres, J.M.; Kazmierczak, A.; Westerveld, W.J.; Harmsma, P.J.; Berg, J.H. van den; Schmits, R.; Yousefi, M.; Cabezon, M.; Villafranca, A.; Izquierdo, D.; Garces, J.I.

    2011-01-01

    One of the important issues of System-on-a-package integration is the interconnection between independent Photonic Integrated Circuits (PICs). In this work, this issue is addressed by the use of Vertical Grating Couplers (VGCs) as the element for the interconnection between two Silicon-on-Insulator

  20. Integrated circuit design using design automation

    International Nuclear Information System (INIS)

    Although the use of computer aids to develop integrated circuits is relatively new at Sandia, the program has been very successful. The results have verified the utility of the in-house CAD design capability. Custom IC's have been developed in much shorter times than available through semiconductor device manufacturers. In addition, security problems were minimized and a saving was realized in circuit cost. The custom CMOS IC's were designed at less than half the cost of designing with conventional techniques. In addition to the computer aided design, the prototype fabrication and testing capability provided by the semiconductor development laboratory and microelectronics computer network allows the circuits to be fabricated and evaluated before the designs are transferred to the commercial semiconductor manufacturers for production. The Sandia design and prototype fabrication facilities provide the capability of complete custom integrated circuit development entirely within the ERDA laboratories

  1. Electronic circuits and systems: A compilation. [including integrated circuits, logic circuits, varactor diode circuits, low pass filters, and optical equipment circuits

    Science.gov (United States)

    1975-01-01

    Technological information is presented electronic circuits and systems which have potential utility outside the aerospace community. Topics discussed include circuit components such as filters, converters, and integrators, circuits designed for use with specific equipment or systems, and circuits designed primarily for use with optical equipment or displays.

  2. Displacement Damage in Bipolar Linear Integrated Circuits

    Science.gov (United States)

    Rax, B. G.; Johnston, A. H.; Miyahira, T.

    2000-01-01

    Although many different processes can be used to manufacture linear integrated circuits, the process that is used for most circuits is optimized for high voltage -- a total power supply voltage of about 40 V -- and low cost. This process, which has changed little during the last twenty years, uses lateral and substrate p-n-p transistors. These p-n-p transistors have very wide base regions, increasing their sensitivity to displacement damage from electrons and protons. Although displacement damage effects can be easily treated for individual transistors, the net effect on linear circuits can be far more complex because circuit operation often depends on the interaction of several internal transistors. Note also that some circuits are made with more advanced processes with much narrower base widths. Devices fabricated with these newer processes are not expected to be significantly affected by displacement damage for proton fluences below 1 x 10(exp 12) p/sq cm. This paper discusses displacement damage in linear integrated circuits with more complex failure modes than those exhibited by simpler devices, such as the LM111 comparator, where the dominant response mode is gain degradation of the input transistor. Some circuits fail catastrophically at much lower equivalent total dose levels compared to tests with gamma rays. The device works satisfactorily up to nearly 1 Mrad(Si) when it is irradiated with gamma rays, but fails catastrophically between 50 and 70 krad(Si) when it is irradiated with protons.

  3. Solution methods for very highly integrated circuits.

    Energy Technology Data Exchange (ETDEWEB)

    Nong, Ryan; Thornquist, Heidi K.; Chen, Yao; Mei, Ting; Santarelli, Keith R.; Tuminaro, Raymond Stephen

    2010-12-01

    While advances in manufacturing enable the fabrication of integrated circuits containing tens-to-hundreds of millions of devices, the time-sensitive modeling and simulation necessary to design these circuits poses a significant computational challenge. This is especially true for mixed-signal integrated circuits where detailed performance analyses are necessary for the individual analog/digital circuit components as well as the full system. When the integrated circuit has millions of devices, performing a full system simulation is practically infeasible using currently available Electrical Design Automation (EDA) tools. The principal reason for this is the time required for the nonlinear solver to compute the solutions of large linearized systems during the simulation of these circuits. The research presented in this report aims to address the computational difficulties introduced by these large linearized systems by using Model Order Reduction (MOR) to (i) generate specialized preconditioners that accelerate the computation of the linear system solution and (ii) reduce the overall dynamical system size. MOR techniques attempt to produce macromodels that capture the desired input-output behavior of larger dynamical systems and enable substantial speedups in simulation time. Several MOR techniques that have been developed under the LDRD on 'Solution Methods for Very Highly Integrated Circuits' will be presented in this report. Among those presented are techniques for linear time-invariant dynamical systems that either extend current approaches or improve the time-domain performance of the reduced model using novel error bounds and a new approach for linear time-varying dynamical systems that guarantees dimension reduction, which has not been proven before. Progress on preconditioning power grid systems using multi-grid techniques will be presented as well as a framework for delivering MOR techniques to the user community using Trilinos and the Xyce circuit

  4. Integrated Circuit (Ic) And Photomask Images Processing Technology

    OpenAIRE

    Doudkin, A.; Vershok, D.

    2004-01-01

    The integrated circuit and photomask images processing technology is proposed. This technology allows to perform the restoration of the integrated-circuit metallization layout and the mask artwork from the images of IC metallization layers or photomask set correspondingly. It can be applied for the tasks of integrated circuits redesign and automated visual inspection of integrated circuits and photomask production.

  5. Integrated circuits and their application. Mikroskhemy i ikh primenenie

    Energy Technology Data Exchange (ETDEWEB)

    Batushev, V.A.; Veniaminov, V.N.; Kovalev, V.G.; Lebedev, O.N.; Miroshnichenko, A.I.

    1978-01-01

    The subject is covered in eight chapters, namely: (1) General Information on Integrated Circuits; (2) Analog Integrated Circuits and Standard Functional Devices; (3) Application of Analog Integrated Circuits; (4) Digital Integrated Circuits and Standard Functional Devices; (5) Microprocessors and Memory Integrated Circuits; (6) Digital-to-Analog and Analog-to-Digital Converters Using Integrated Circuits; (7) Application of Digital Integrated Circuits in Electronic Equipment; and (8) Design of Radio Electronic Components Based on ICs. An addenum, system for IC Designations, is included. 55 references.

  6. VISA Final Report: Fully Integrated Power Electronic Systems in Automotive Electronics

    OpenAIRE

    Waffenschmidt, E

    2011-01-01

    This report summarizes the activities related to the public funded project “Vollintegrierte leistungselektronische Systeme in der Automobilelektronik – VISA” (Fully Integrated Power Electronic Systems in Automotive Electronics). Aim of the project is to investigate the integration of components into printed circuit boards (PCB) for automotive power applications. For Philips, this technology is interesting for integrated LED drivers as used e.g. in automotive head lamps. The project is funded ...

  7. Integrated microsphere planar lightwave circuits

    OpenAIRE

    J. S. Wilkinson; Murugan, G.S.; Hewak, D. W.; M. N. Zervas; Panitchob, Y.; Elliott, G. R.; Bartlett, P. N.; Tull, E.J.; Ryan, K R

    2010-01-01

    Multicomponent glass microspheres self-assembled on optical waveguides combine tailored optical properties with strong light/material interaction potentially leading to compact low-power photonic devices. Progress and prospects for microsphere/waveguide integration will be described

  8. Photonic integrated circuits for radar beam control

    OpenAIRE

    Stulemeijer, J.; Smit, M. K.; Vliet, F.E. van; Bogaart, F.L.M. van den

    1999-01-01

    Photonic integrated circuits have the potential to reduce the volume and weight of optical beamforming networks for phased-array radar antennae by more than one order of magnitude, and will drastically reduce packaging and interconnection costs by integrating subcircuits, consisting of many components, on a single chip. Most work on optical beamforming networks reported so far has been based on discrete optical components. Here we describe a first realization of an integrated optical chip wit...

  9. Laboratory experiments in integrated circuit fabrication

    Science.gov (United States)

    Jenkins, Thomas J.; Kolesar, Edward S.

    1993-06-01

    The objectives of the experiment are fourfold: to provide practical experience implementing the fundamental processes and technology associated with the science and art of integrated circuit (IC) fabrication; to afford the opportunity for the student to apply the theory associated with IC fabrication and semiconductor device operation; to motivate the student to exercise engineering decisions associated with fabricating integrated circuits; and to complement the theory of n-channel MOS and diffused devices that are presented in the classroom by actually fabricating and testing them. Therefore, a balance between theory and practice can be realized in the education of young engineers, whose education is often criticized as lacking sufficient design and practical content.

  10. Test Structures For Bumpy Integrated Circuits

    Science.gov (United States)

    Buehler, Martin G.; Sayah, Hoshyar R.

    1989-01-01

    Cross-bridge resistors added to comb and serpentine patterns. Improved combination of test structures built into integrated circuit used to evaluate design rules, fabrication processes, and quality of interconnections. Consist of meshing serpentines and combs, and cross bridge. Structures used to make electrical measurements revealing defects in design or fabrication. Combination of test structures includes three comb arrays, two serpentine arrays, and cross bridge. Made of aluminum or polycrystalline silicon, depending on material in integrated-circuit layers evaluated. Aluminum combs and serpentine arrays deposited over steps made by polycrystalline silicon and diffusion layers, while polycrystalline silicon versions of these structures used to cross over steps made by thick oxide layer.

  11. Millimeter And Submillimeter-Wave Integrated Circuits On Quartz

    Science.gov (United States)

    Mehdi, Imran; Mazed, Mohammad; Siegel, Peter; Smith, R. Peter

    1995-01-01

    Proposed Quartz substrate Upside-down Integrated Device (QUID) relies on UV-curable adhesive to bond semiconductor with quartz. Integrated circuits including planar GaAs Schottky diodes and passive circuit elements (such as bandpass filters) fabricated on quartz substrates. Circuits designed to operate as mixers in waveguide circuit at millimeter and submillimeter wavelengths. Integrated circuits mechanically more robust, larger, and easier to handle than planar Schottky diode chips. Quartz substrate more suitable for waveguide circuits than GaAs substrate.

  12. Microwave integrated circuits for space applications

    Science.gov (United States)

    Leonard, Regis F.; Romanofsky, Robert R.

    1991-01-01

    Monolithic microwave integrated circuits (MMIC), which incorporate all the elements of a microwave circuit on a single semiconductor substrate, offer the potential for drastic reductions in circuit weight and volume and increased reliability, all of which make many new concepts in electronic circuitry for space applications feasible, including phased array antennas. NASA has undertaken an extensive program aimed at development of MMICs for space applications. The first such circuits targeted for development were an extension of work in hybrid (discrete component) technology in support of the Advanced Communication Technology Satellite (ACTS). It focused on power amplifiers, receivers, and switches at ACTS frequencies. More recent work, however, focused on frequencies appropriate for other NASA programs and emphasizes advanced materials in an effort to enhance efficiency, power handling capability, and frequency of operation or noise figure to meet the requirements of space systems.

  13. Microwave integrated circuit for Josephson voltage standards

    Science.gov (United States)

    Holdeman, L. B.; Toots, J.; Chang, C. C. (Inventor)

    1980-01-01

    A microwave integrated circuit comprised of one or more Josephson junctions and short sections of microstrip or stripline transmission line is fabricated from thin layers of superconducting metal on a dielectric substrate. The short sections of transmission are combined to form the elements of the circuit and particularly, two microwave resonators. The Josephson junctions are located between the resonators and the impedance of the Josephson junctions forms part of the circuitry that couples the two resonators. The microwave integrated circuit has an application in Josephson voltage standards. In this application, the device is asymmetrically driven at a selected frequency (approximately equal to the resonance frequency of the resonators), and a d.c. bias is applied to the junction. By observing the current voltage characteristic of the junction, a precise voltage, proportional to the frequency of the microwave drive signal, is obtained.

  14. An integrated circuit/packet switched video conferencing system

    International Nuclear Information System (INIS)

    The HEP Network Resource Center (HEPNRC) at Fermilab and the Collider Detector Facility (CDF) collaboration have evolved a flexible, cost-effective, widely accessible video conferencing system for use by high energy physics collaborations and others wishing to use video conferencing. No current systems seemed to fully meet the needs of high energy physics collaborations. However, two classes of video conferencing technology: circuit-switched and packet-switched, if integrated, might encompass most of HEPS's needs. It was also realized that, even with this integration, some additional functions were needed and some of the existing functions were not always wanted. HEPNRC with the help of members of the CDF collaboration set out to develop such an integrated system using as many existing subsystems and components as possible. This system is called VUPAC (Video conferencing Using Packets and Circuits). This paper begins with brief descriptions of the circuit-switched and packet-switched video conferencing systems. Following this, issues and limitations of these systems are considered. Next the VUPAC system is described. Integration is accomplished primarily by a circuit/packet video conferencing interface. Augmentation is centered in another subsystem called MSB (Multiport MultiSession Bridge). Finally, there is a discussion of the future work needed in the evolution of this system. (author)

  15. Fully Integral, Flexible Composite Driveshaft Project

    Data.gov (United States)

    National Aeronautics and Space Administration — An all-composite driveshaft incorporating integral flexible diaphragms is described and proposed for phase II prime conractor testing. The approach obsoletes the...

  16. Fully Integral, Flexible Composite Driveshaft Project

    Data.gov (United States)

    National Aeronautics and Space Administration — An all-composite driveshaft incorporating integral flexible diaphragms is described and proposed for further refinement. An approach is explored which obsoletes the...

  17. Modeling "Soft" Errors in Bipolar Integrated Circuits

    Science.gov (United States)

    Zoutendyk, J.; Benumof, R.; Vonroos, O.

    1985-01-01

    Mathematical models represent single-event upset in bipolar memory chips. Physics of single-event upset in integrated circuits discussed in theoretical paper. Pair of companion reports present mathematical models to predict critical charges for producing single-event upset in bipolar randomaccess memory (RAM) chips.

  18. Hybrid integrated circuits for sound signal processing

    OpenAIRE

    Koval’chuk V. A.; Sevast’yanov V. V.

    2011-01-01

    Developed hybrid integrated circuit with rated supply voltage of 1,4 V, current consumption 0,7 mA and overall dimensions 8×4×3 mm provides soft processing of the audio signal in analog microelectronic equipment. Given its konstruktorsko-technological and electrical parameters.

  19. Package Holds Five Monolithic Microwave Integrated Circuits

    Science.gov (United States)

    Mysoor, Narayan R.; Decker, D. Richard; Olson, Hilding M.

    1996-01-01

    Packages protect and hold monolithic microwave integrated circuit (MMIC) chips while providing dc and radio-frequency (RF) electrical connections for chips undergoing development. Required to be compact, lightweight, and rugged. Designed to minimize undesired resonances, reflections, losses, and impedance mismatches.

  20. Integrated Circuits in the Introductory Electronics Laboratory

    Science.gov (United States)

    English, Thomas C.; Lind, David A.

    1973-01-01

    Discusses the use of an integrated circuit operational amplifier in an introductory electronics laboratory course for undergraduate science majors. The advantages of this approach and the implications for scientific instrumentation are identified. Describes a number of experiments suitable for the undergraduate laboratory. (Author/DF)

  1. Silicon Photonic Integrated Circuit Mode Multiplexer

    DEFF Research Database (Denmark)

    Ding, Yunhong; Ou, Haiyan; Xu, Jing;

    2013-01-01

    We propose and demonstrate a novel silicon photonic integrated circuit enabling multiplexing of orthogonal modes in a few-mode fiber (FMF). By selectively launching light to four vertical grating couplers, all six orthogonal spatial and polarization modes supported by the FMF are successfully...

  2. Integrated Circuits for Linear and Efficient Receivers

    OpenAIRE

    Östman, Kim

    2014-01-01

    This dissertation presents original research contributions in the form of five integrated circuit (IC) implementations and seven scientific publications. They present advances related to high-Q resonators, DC-DC converters, and programmable RF front-ends for integrated wireless receivers. Because these three building blocks have traditionally required implementations that are partly external to the IC, the ultimate target is to reduce system size, cost, and complexity. Wireless receivers u...

  3. Data readout system utilizing photonic integrated circuit

    International Nuclear Information System (INIS)

    We describe a novel optical solution for data readout systems. The core of the system is an Indium-Phosphide photonic integrated circuit performing as a front-end readout unit. It functions as an optical serializer in which the serialization of the input signal is provided by means of on-chip optical delay lines. The circuit employs electro-optic phase shifters to build amplitude modulators, power splitters for signal distribution, semiconductor optical amplifiers for signal amplification as well as on-chip reflectors. We present the concept of the system, the design and first characterization results of the devices that were fabricated in a multi-project wafer run

  4. Conductus makes high-Tc integrated circuit

    International Nuclear Information System (INIS)

    This paper reports that researchers at Conductus have successfully demonstrated what the company says is the world's first integrated circuit containing active devices made from high-temperature superconductors. The circuit is a SQUID magnetometer made from seven layers of material: three layers of yttrium-barium-copper oxide, two layers of insulating material, a seed layer to create grain boundaries for the Josephson junctions, and a layer of silver for making electrical contact to the device. The chip also contains vias, or pathways that make a superconducting contact between the superconducting layers otherwise separated by insulators. Conductus had previously announced the development of a SQUID magnetometer that featured a SQUID sensor and a flux transformer manufactured on separate chips. What makes this achievement important is that the company was able to put both components on the same chip, thus creating a simple integrated circuit on a single chip. This is still a long way from conventional semiconductor technology, with as many as a million components per chip, or even the sophisticated low-Tc superconducting chips made by the Japanese, but the SQUID magnetometer demonstrates all the elements and techniques necessary to build more complex high-temperature superconductor integrated circuits, making this an important first step

  5. Power management techniques for integrated circuit design

    CERN Document Server

    Chen, Ke-Horng

    2016-01-01

    This book begins with the premise that energy demands are directing scientists towards ever-greener methods of power management, so highly integrated power control ICs (integrated chip/circuit) are increasingly in demand for further reducing power consumption. * A timely and comprehensive reference guide for IC designers dealing with the increasingly widespread demand for integrated low power management * Includes new topics such as LED lighting, fast transient response, DVS-tracking and design with advanced technology nodes * Leading author (Chen) is an active and renowned contributor to the power management IC design field, and has extensive industry experience * Accompanying website includes presentation files with book illustrations, lecture notes, simulation circuits, solution manuals, instructors manuals, and program downloads.

  6. Applying analog integrated circuits for HERO protection

    Science.gov (United States)

    Willis, Kenneth E.; Blachowski, Thomas J.

    1994-01-01

    One of the most efficient methods for protecting electro-explosive devices (EED's) from HERO and ESD is to shield the EED in a conducting shell (Faraday cage). Electrical energy is transferred to the bridge by means of a magnetic coupling which passes through a portion of the conducting shell that is made from a magnetically permeable but electrically conducting material. This technique was perfected by ML Aviation, a U.K. company, in the early 80's, and was called a Radio Frequency Attenuation Connector (RFAC). It is now in wide use in the U.K. Previously, the disadvantage of RFAC over more conventional methods was its relatively high cost, largely driven by a thick film hybrid circuit used to switch the primary of the transformer. Recently, through a licensing agreement, this technology has been transferred to the U.S. and significant cost reductions and performance improvements have been achieved by the introduction of analog integrated circuits. An integrated circuit performs the following functions: (1) Chops the DC input to a signal suitable for driving the primary of the transformer; (2) Verifies the input voltage is above a threshold; (3) Verifies the input voltage is valid for a pre set time before enabling the device; (4) Provides thermal protection of the circuit; and (5) Provides an external input for independent logic level enabling of the power transfer mechanism. This paper describes the new RFAC product and its applications.

  7. Design of Integrated Circuits Approaching Terahertz Frequencies

    OpenAIRE

    Yan, Lei; Johansen, Tom Keinicke

    2013-01-01

    In this thesis, monolithic microwave integrated circuits(MMICs) are presented for millimeter-wave and submillimeter-wave or terahertz(THz) applications. Millimeter-wave power generation from solid state devices is not only crucial for the emerging high data rate wireless communications but also important for driving THz signal sources. To meet the requirement of high output power, amplifiers based on InP double heterojunction bipolar transistor (DHBT) devices from the III-V Lab in Marcoussic,...

  8. Progress in radiation immune thermionic integrated circuits

    International Nuclear Information System (INIS)

    This report describes the results of a program directed at evaluating the thermionic integrated circuit (TIC) technology for applicability to military systems. Previous programs under the sponsorship of the Department of Energy, Office of Basic Energy Sciences, have developed an initial TIC technology base and demonstrated operation in high-temperature and high-radiation environments. The program described in this report has two parts: (1) a technical portion in which experiments and analyses were conducted to refine perceptions of near-term as well as ultimate performance levels of the TIC technology and (2) an applications portion in which the technical conclusions were to be evaluated against potential military applications. This report draws several conclusions that strongly suggest that (1) useful radiation-hard/high-temperature operable integrated circuits can be developed using the TIC technology; (2) because of their ability to survive and operate in hostile environments, a variety of potential military applications have been projected for this technology; and (3) based on the above two conclusions, an aggressive TIC development program should be initiated to provide the designers of future systems with integrated circuits and devices with the unique features of the TICs

  9. Progress in radiation immune thermionic integrated circuits

    Science.gov (United States)

    Lynn, D. K.; McCormick, J. B.

    1985-08-01

    This report describes the results of a program directed at evaluating the thermionic integrated circuit (TIC) technology for applicability to military systems. Previous programs under the sponsorship of the Department of Energy, Office of Basic Energy Sciences, have developed an initial TIC technology base and demonstrated operation in high-temperature and high-radiation environments. The program described in this report has two parts: (1) a technical portion in which experiments and analyses were conducted to refine perceptions of near-term as well as ultimate performance levels of the TIC technology and (2) an applications portion in which the technical conclusions were to be evaluated against potential military applications. This report draws several conclusions that strongly suggest that (1) useful radiation-hard/high-temperature operable integrated circuits can be developed using the TIC technology; (2) because of their ability to survive and operate in hostile environments, a variety of potential military applications have been projected for this technology; and (3) based on the above two conclusions, an aggressive TIC development program should be initiated to provide the designers of future systems with integrated circuits and devices with the unique features of the TICs.

  10. Two Stage Fully Differential Sample and Hold Circuit Using .18µm Technology

    Directory of Open Access Journals (Sweden)

    Dharmendra Dongardiye

    2014-05-01

    Full Text Available This paper presents a well-established Fully Differential sample & hold circuitry, implemented in 180-nm CMOS technology. In this two stage method the first stage give us very high gain and second stage gives large voltage swing. The proposed opamp provides 149MHz unity-gain bandwidth , 78 degree phase margin and a differential peak to peak output swing more than 2.4v. using the improved fully differential two stage operational amplifier of 76.7dB gain. Although the sample and hold circuit meets the requirements of SNR specifications.

  11. Power system with an integrated lubrication circuit

    Science.gov (United States)

    Hoff, Brian D.; Akasam, Sivaprasad; Algrain, Marcelo C.; Johnson, Kris W.; Lane, William H.

    2009-11-10

    A power system includes an engine having a first lubrication circuit and at least one auxiliary power unit having a second lubrication circuit. The first lubrication circuit is in fluid communication with the second lubrication circuit.

  12. Sequential circuit design for radiation hardened multiple voltage integrated circuits

    Science.gov (United States)

    Clark, Lawrence T.; McIver, III, John K.

    2009-11-24

    The present invention includes a radiation hardened sequential circuit, such as a bistable circuit, flip-flop or other suitable design that presents substantial immunity to ionizing radiation while simultaneously maintaining a low operating voltage. In one embodiment, the circuit includes a plurality of logic elements that operate on relatively low voltage, and a master and slave latches each having storage elements that operate on a relatively high voltage.

  13. Integrated Circuits for Analog Signal Processing

    CERN Document Server

    2013-01-01

      This book presents theory, design methods and novel applications for integrated circuits for analog signal processing.  The discussion covers a wide variety of active devices, active elements and amplifiers, working in voltage mode, current mode and mixed mode.  This includes voltage operational amplifiers, current operational amplifiers, operational transconductance amplifiers, operational transresistance amplifiers, current conveyors, current differencing transconductance amplifiers, etc.  Design methods and challenges posed by nanometer technology are discussed and applications described, including signal amplification, filtering, data acquisition systems such as neural recording, sensor conditioning such as biomedical implants, actuator conditioning, noise generators, oscillators, mixers, etc.   Presents analysis and synthesis methods to generate all circuit topologies from which the designer can select the best one for the desired application; Includes design guidelines for active devices/elements...

  14. Laser applications in integrated circuit packaging

    Science.gov (United States)

    Lu, Yongfeng; Song, Wen D.; Ren, ZhongMin; An, Chengwu; Ye, Kaidong D.; Liu, DaMing; Wang, Weijie; Hong, Ming Hui; Chong, Tow Chong

    2002-06-01

    Laser processing has large potential in the packaging of integrated circuits (IC). It can be used in many applications such as laser cleaning of IC mold tools, laser deflash to remove mold flash form heat sinks and lead wires of IC packages, laser singulation of BGA and CSP, laser reflow of solder ball on GBA, laser marking on packages and on SI wafers. During the implementation of all these applications, laser parameters, material issues, throughput, yield, reliability and monitoring techniques have to b taken into account. Monitoring of laser-induced plasma and laser induced acoustic wave has been used to understand and to control the processes involved in these applications.

  15. Diode lasers and photonic integrated circuits

    CERN Document Server

    Coldren, Larry A; Mashanovitch, Milan L

    2011-01-01

    Diode Lasers and Photonic Integrated Circuits, Second Edition provides a comprehensive treatment of optical communication technology, its principles and theory, treating students as well as experienced engineers to an in-depth exploration of this field. Diode lasers are still of significant importance in the areas of optical communication, storage, and sensing. Using the the same well received theoretical foundations of the first edition, the Second Edition now introduces timely updates in the technology and in focus of the book. After 15 years of development in the field, this book wil

  16. Thermoelectricity from wasted heat of integrated circuits

    KAUST Repository

    Fahad, Hossain M.

    2012-05-22

    We demonstrate that waste heat from integrated circuits especially computer microprocessors can be recycled as valuable electricity to power up a portion of the circuitry or other important accessories such as on-chip cooling modules, etc. This gives a positive spin to a negative effect of ever increasing heat dissipation associated with increased power consumption aligned with shrinking down trend of transistor dimension. This concept can also be used as an important vehicle for self-powered systemson- chip. We provide theoretical analysis supported by simulation data followed by experimental verification of on-chip thermoelectricity generation from dissipated (otherwise wasted) heat of a microprocessor.

  17. Accelerating functional verification of an integrated circuit

    Energy Technology Data Exchange (ETDEWEB)

    Deindl, Michael; Ruedinger, Jeffrey Joseph; Zoellin, Christian G.

    2015-10-27

    Illustrative embodiments include a method, system, and computer program product for accelerating functional verification in simulation testing of an integrated circuit (IC). Using a processor and a memory, a serial operation is replaced with a direct register access operation, wherein the serial operation is configured to perform bit shifting operation using a register in a simulation of the IC. The serial operation is blocked from manipulating the register in the simulation of the IC. Using the register in the simulation of the IC, the direct register access operation is performed in place of the serial operation.

  18. Long-wavelength III-V/silicon photonic integrated circuits

    OpenAIRE

    Roelkens, Günther; Kuyken, Bart; Leo, François; Hattasan, Nannicha; Ryckeboer, Eva; Muneeb, Muhammad; Hu, Chen; Malik, Aditya Singh; Hens, Zeger; Baets, Roel; Shimura, Y; F. Gencarelli; Vincent, B.; Loo, R.; Verheyen, P

    2013-01-01

    We review our work in the field of short-wave infrared and mid-infrared photonic integrated circuits for applications in spectroscopic sensing systems. Passive silicon waveguide circuits, GeSn photodetectors, the integration of III-V and IV-VI semiconductors on these circuits, and silicon nonlinear optics are discussed.

  19. Implementation of a Fully Integrated and Risk Based Management System

    International Nuclear Information System (INIS)

    Mr Erik Wiig presented the implementation of a fully integrated and risk based management system at NSEP. He described the overall objectives of the system and the business model. During his presentation, Mr Wiig deployed some management and execution/support processes. He finally gave an overview of the main elements of the risk and opportunities management systems

  20. A fully integrated 16 channel digitally trimmed pulse shaping amplifier

    International Nuclear Information System (INIS)

    A fully integrated CMOS pulse shaping amplifier has been developed at LBL. All frequency dependent networks are included on the chip. Provision is made for tuning to compensate for process variations. The overall architecture and details of the circuitry are discussed. Test results are presented

  1. A Fully Integrated Humidity Sensor System-on-Chip Fabricated by Micro-Stamping Technology

    OpenAIRE

    Chih-Ting Lin; Shey-Shi Lu; Yu-Jie Huang; Che-Wei Huang

    2012-01-01

    A fully integrated humidity sensor chip was designed, implemented, and tested. Utilizing the micro-stamping technology, the pseudo-3D sensor system-on-chip (SSoC) architecture can be implemented by stacking sensing materials directly on the top of a CMOS-fabricated chip. The fabricated sensor system-on-chip (2.28 mm × 2.48 mm) integrated a humidity sensor, an interface circuit, a digital controller, and an On-Off Keying (OOK) wireless transceiver. With low power consumption, i.e.<...

  2. Development, integration and testing of automated triggering circuit for hybrid DC circuit breaker

    International Nuclear Information System (INIS)

    A novel concept of Hybrid DC circuit breaker having combination of mechanical switch and static switch provides arc-less current commutation into the dump resistor during quench in superconducting magnet operation. The triggering of mechanical and static switches in Hybrid DC breaker can be automatized which can effectively reduce the overall current commutation time of hybrid DC circuit breaker and make the operation independent of opening time of mechanical switch. With this view, a dedicated control circuit (auto-triggering circuit) has been developed which can decide the timing and pulse duration for mechanical switch as well as static switch from the operating parameters. This circuit has been tested with dummy parameters and thereafter integrated with the actual test set up of hybrid DC circuit breaker. This paper deals with the conceptual design of the auto-triggering circuit, its control logic and operation. The test results of Hybrid DC circuit breaker using this circuit have also been discussed. (author)

  3. Microwaves integrated circuits: hybrids and monolithics - fabrication technology

    International Nuclear Information System (INIS)

    Several types of microwave integrated circuits are presented together with comments about technologies and fabrication processes; advantages and disadvantages in their utilization are analysed. Basic structures, propagation modes, materials used and major steps in the construction of hybrid thin film and monolithic microwave integrated circuits are described. Important technological applications are revised and main activities of the microelectronics lab. of the University of Sao Paulo (Brazil) in the field of hybrid and monolithic microwave integrated circuits are summarized. (C.L.B.)

  4. RD53A Integrated Circuit Specifications

    CERN Document Server

    Garcia-Sciveres, Mauricio

    2015-01-01

    Specifications for the RD53 collaboration’s first engineering wafer run of an integrated circuit (IC) for hybrid pixel detector readout, called RD53A. RD53A is intended to demonstrate in a large format IC the suitability of the technology (including radiation tolerance), the stable low threshold operation, and the high hit and trigger rate capabilities, required for HL-LHC upgrades of ATLAS and CMS. The wafer scale production will permit the experiments to prototype bump bonding assembly with realistic sensors in this new technology and to measure the performance of hybrid assemblies. RD53A is not intended to be a final production IC for use in an experiment, and will contain design variations for testing purposes, making the pixel matrix non-uniform.

  5. Broadband plasmonic absorber for photonic integrated circuits

    CERN Document Server

    Xiong, Xiao; Ren, Xi-Feng; Guo, Guang-Can

    2013-01-01

    The loss of surface plasmon polaritons has long been considered as a fatal shortcoming in information transport. Here we propose a plasmonic absorber utilizing this "shortcoming" to absorb the stray light in photonic integrated circuits (PICs). Based on adiabatic mode evolution, its performance is insensitive to incident wavelength with bandwidth larger than 300nm, and robust against surrounding environment and temperature. Besides, the use of metal enables it to be very compact and beneficial to thermal dissipation. With this 40um-long absorber, the absorption efficiency can be over 99.8% at 1550nm, with both the reflectivity and transmittance of incident light reduced to less than 0.1%. Such device may find various applications in PICs, to eliminate the residual strong pump laser or stray light.

  6. Integrated optical circuits for numerical computation

    Science.gov (United States)

    Verber, C. M.; Kenan, R. P.

    1983-01-01

    The development of integrated optical circuits (IOC) for numerical-computation applications is reviewed, with a focus on the use of systolic architectures. The basic architecture criteria for optical processors are shown to be the same as those proposed by Kung (1982) for VLSI design, and the advantages of IOCs over bulk techniques are indicated. The operation and fabrication of electrooptic grating structures are outlined, and the application of IOCs of this type to an existing 32-bit, 32-Mbit/sec digital correlator, a proposed matrix multiplier, and a proposed pipeline processor for polynomial evaluation is discussed. The problems arising from the inherent nonlinearity of electrooptic gratings are considered. Diagrams and drawings of the application concepts are provided.

  7. Parallel Jacobi EVD Methods on Integrated Circuits

    Directory of Open Access Journals (Sweden)

    Chi-Chia Sun

    2014-01-01

    Full Text Available Design strategies for parallel iterative algorithms are presented. In order to further study different tradeoff strategies in design criteria for integrated circuits, A 10 × 10 Jacobi Brent-Luk-EVD array with the simplified μ-CORDIC processor is used as an example. The experimental results show that using the μ-CORDIC processor is beneficial for the design criteria as it yields a smaller area, faster overall computation time, and less energy consumption than the regular CORDIC processor. It is worth to notice that the proposed parallel EVD method can be applied to real-time and low-power array signal processing algorithms performing beamforming or DOA estimation.

  8. Post irradiation effects (PIE) in integrated circuits

    Science.gov (United States)

    Shaw, D. C.; Lowry, L.; Barnes, C.; Zakharia, M.; Agarwal, S.; Rax, B.

    1991-01-01

    Post-irradiation effects (PIE) ranging from normal recovery to catastrophic failure have been observed in integrated circuits during the PIE period. Data presented show failure due to rebound after a 10 krad(Si) dose. In particular, five device types are investigated with varying PIE response. Special attention has been given to the HI1-507A analog multiplexer because its PIE response is extreme. X-ray diffraction has been uniquely employed to measure physical stress in the HI1-507A metallization. An attempt has been made to show a relationship between stress relaxation and radiation effects. All data presented support the current MIL-STD Method 1019.4 but demonstrate the importance of performing PIE measurements, even when mission doses are as low as 10 krad(Si).

  9. Plug-in integrated/hybrid circuit

    Science.gov (United States)

    Stringer, E. J.

    1974-01-01

    Hybrid circuitry can be installed into standard round bayonet connectors, to eliminate wiring from connector to circuit. Circuits can be connected directly into either section of connector pair, eliminating need for hard wiring to that section.

  10. Silicon Photonics Integrated Circuits for Flexible Optical Systems

    OpenAIRE

    Orlandi, Piero

    2014-01-01

    This dissertation deals with the design and the characterization of novel reconfigurable silicon-on-insulator (SOI) devices to filter and route optical signals on-chip. Design is carried out through circuit simulations based on basic circuit elements (Building Blocks, BBs) in order to prove the feasibility of an approach allowing to move the design of Photonic Integrated Circuits (PICs) toward the system level. CMOS compatibility and large integration scale make SOI one of the most promis...

  11. Topology Optimization of Building Blocks for Photonic Integrated Circuits

    DEFF Research Database (Denmark)

    Jensen, Jakob Søndergaard; Sigmund, Ole

    2005-01-01

    Photonic integrated circuits are likely candidates as high speed replacements for the standard electrical integrated circuits of today. However, in order to obtain a satisfactorily performance many design prob- lems that up until now have resulted in too high losses must be resolved. In this work...... we demonstrate how the method of topology optimization can be used to design a variety of high performance building blocks for the future circuits....

  12. Performance Analysis of 3-D Monolithic Integrated Circuits

    OpenAIRE

    Bobba, Shashikanth; Chakraborthy, Ashutosh; Olivier THOMAS (LEREPS-GRES); Batude, Perrine; Pavlidis, Vasileios; Micheli, Giovanni De

    2010-01-01

    3-D monolithic integration (3DMI), also termed as sequential integration, is a potential technology for future gigascale circuits. Since the device layers are processed in sequential order, the size of the vertical contacts is similar to traditional contacts unlike in the case of parallel 3-D integration with through silicon vias (TSVs). Given the advantage of such small contacts, 3DMI supports stacking active layers such that fine-grain integration of 3-D circuits can be implemented. This pa...

  13. Low-power CMOS fully-folding ADC with a mixed-averaging distributed T/H circuit

    Institute of Scientific and Technical Information of China (English)

    Liu Zhen; Jia Song; Wang Yuan; Ji Lijiu; Zhang Xing

    2009-01-01

    This paper describes an 8-bit 125 Mhzlow-powerCMOS fully-foldinganalog-to-digital converter(ADC).A novel mixed-averaging distributed T/H circuit is proposed to improve the accuracy. Folding circuits are not only used in the fine converter but also in the coarse one and in the bit synchronization block to reduce the number of comparators for low power. This ADC is implemented in 0.5μm CMOS technology and occupies a die area of 2 × 1.5 mm~2. The measured differential nonlinearity and integral nonlinearity are 0.6 LSB/-0.8 LSB and 0.9 LSB/-1.2 LSB, respectively. The ADC exhibits 44.3 dB of signal-to-noise plus distortion ratio and 53.5 dB of spurious-free dynamic range for 1 MHz input sine-wave. The power dissipation is 138 mW at a sampling rate of 125 MHz at a 5 V supply.

  14. Counterfeit integrated circuits detection and avoidance

    CERN Document Server

    Tehranipoor, Mark (Mohammad); Forte, Domenic

    2015-01-01

    This timely and exhaustive study offers a much-needed examination of the scope and consequences of the electronic counterfeit trade.  The authors describe a variety of shortcomings and vulnerabilities in the electronic component supply chain, which can result in counterfeit integrated circuits (ICs).  Not only does this book provide an assessment of the current counterfeiting problems facing both the public and private sectors, it also offers practical, real-world solutions for combatting this substantial threat.   ·      Helps beginners and practitioners in the field by providing a comprehensive background on the counterfeiting problem; ·      Presents innovative taxonomies for counterfeit types, test methods, and counterfeit defects, which allows for a detailed analysis of counterfeiting and its mitigation; ·      Provides step-by-step solutions for detecting different types of counterfeit ICs; ·      Offers pragmatic and practice-oriented, realistic solutions to counterfeit IC d...

  15. Securing health sensing using integrated circuit metric.

    Science.gov (United States)

    Tahir, Ruhma; Tahir, Hasan; McDonald-Maier, Klaus

    2015-01-01

    Convergence of technologies from several domains of computing and healthcare have aided in the creation of devices that can help health professionals in monitoring their patients remotely. An increase in networked healthcare devices has resulted in incidents related to data theft, medical identity theft and insurance fraud. In this paper, we discuss the design and implementation of a secure lightweight wearable health sensing system. The proposed system is based on an emerging security technology called Integrated Circuit Metric (ICMetric) that extracts the inherent features of a device to generate a unique device identification. In this paper, we provide details of how the physical characteristics of a health sensor can be used for the generation of hardware "fingerprints". The obtained fingerprints are used to deliver security services like authentication, confidentiality, secure admission and symmetric key generation. The generated symmetric key is used to securely communicate the health records and data of the patient. Based on experimental results and the security analysis of the proposed scheme, it is apparent that the proposed system enables high levels of security for health monitoring in resource optimized manner. PMID:26492250

  16. Designing TSVs for 3D Integrated Circuits

    CERN Document Server

    Khan, Nauman

    2013-01-01

    This book explores the challenges and presents best strategies for designing Through-Silicon Vias (TSVs) for 3D integrated circuits.  It describes a novel technique to mitigate TSV-induced noise, the GND Plug, which is superior to others adapted from 2-D planar technologies, such as a backside ground plane and traditional substrate contacts. The book also investigates, in the form of a comparative study, the impact of TSV size and granularity, spacing of C4 connectors, off-chip power delivery network, shared and dedicated TSVs, and coaxial TSVs on the quality of power delivery in 3-D ICs. The authors provide detailed best design practices for designing 3-D power delivery networks.  Since TSVs occupy silicon real-estate and impact device density, this book provides four iterative algorithms to minimize the number of TSVs in a power delivery network. Unlike other existing methods, these algorithms can be applied in early design stages when only functional block- level behaviors and a floorplan are available....

  17. Solar cells from wastes of integrated circuits

    Energy Technology Data Exchange (ETDEWEB)

    Knev, S.; Lakova, M.; Stoyanov, V.; Vlayev, Kh.

    1981-01-01

    Results are presented from using a defective silicon plates for making solar cells with reduces cost and satisfactory characteristics. These monocrystal plates were exposed to high-temperature processes for the formation of crystals of integrated circuits and subsequent mechanical and chemical procedures for removal of the diffusion transitions and to thin the plates. All of this could promote the manifestation of dislocations, fractures and as a result deteriorate the parameters of the current carriers in the initial plates, making them unsuitable for purposes of photoelectrical transformation of solar light. Data are presented which indicate the successful use of wastes for the fabrication of solar cells. Experiments were conducted on plates 50 X 76mm, structures of type n/sup +/-p, n/sup +/-p-p/sup +/, p/sup +/-n, p/sup +/-n-n/sup +/ were made. Studies were made of their main characteristics and it is indicated that the formed transitions have qualities suitable for creating solar cells with good parameters comparable to the solar cells made on the basis of new plates. This was illustrated by samples with efficiency to 15% under conditions of AM2. Decrease in the cost is due to the reduction in technological operation.

  18. F-Paris: integrated electronic circuits [Tender

    CERN Multimedia

    2003-01-01

    "Fourniture, montage et tests des circuits imprimes et modules multi composants pour le trajectographe central de CMS. Maximum de 12 000 circuits imprimes et modules multi-composants necessaires au trajectographe central de l'experience CMS aupres du Large Hadron Collider" (1 page).

  19. Design of 3D integrated circuits and systems

    CERN Document Server

    Sharma, Rohit

    2014-01-01

    Three-dimensional (3D) integration of microsystems and subsystems has become essential to the future of semiconductor technology development. 3D integration requires a greater understanding of several interconnected systems stacked over each other. While this vertical growth profoundly increases the system functionality, it also exponentially increases the design complexity. Design of 3D Integrated Circuits and Systems tackles all aspects of 3D integration, including 3D circuit and system design, new processes and simulation techniques, alternative communication schemes for 3D circuits and sys

  20. Integrated differential high-voltage transmitting circuit for CMUTs

    DEFF Research Database (Denmark)

    Llimos Muntal, Pere; Larsen, Dennis Øland; Farch, Kjartan;

    2015-01-01

    In this paper an integrated differential high-voltage transmitting circuit for capacitive micromachined ultrasonic transducers (CMUTs) used in portable ultrasound scanners is designed and implemented in a 0.35 μm high-voltage process. Measurements are performed on the integrated circuit in order...... to assess its performance. The circuit generates pulses at differential voltage levels of 60V, 80V and 100 V, a frequency up to 5MHz and a measured driving strength of 1.75 V/ns with the CMUT connected. The total on-chip area occupied by the transmitting circuit is 0.18 mm2 and the power consumption...

  1. Stochastic Simulation of Integrated Circuits with Nonlinear Black-Box Components via Augmented Deterministic Equivalents

    Directory of Open Access Journals (Sweden)

    MANFREDI, P.

    2014-11-01

    Full Text Available This paper extends recent literature results concerning the statistical simulation of circuits affected by random electrical parameters by means of the polynomial chaos framework. With respect to previous implementations, based on the generation and simulation of augmented and deterministic circuit equivalents, the modeling is extended to generic and ?black-box? multi-terminal nonlinear subcircuits describing complex devices, like those found in integrated circuits. Moreover, based on recently-published works in this field, a more effective approach to generate the deterministic circuit equivalents is implemented, thus yielding more compact and efficient models for nonlinear components. The approach is fully compatible with commercial (e.g., SPICE-type circuit simulators and is thoroughly validated through the statistical analysis of a realistic interconnect structure with a 16-bit memory chip. The accuracy and the comparison against previous approaches are also carefully established.

  2. A fully integrated 3.5 GHz CMOS differential power amplifier driver

    International Nuclear Information System (INIS)

    A fully integrated CMOS differential power amplifier driver (PAD) is proposed for WiMAX applications. In order to fulfill the differential application requirements, a transmission line transformer is used as the output matching network. A differential inductance constitutes an inter-stage matching network. Meanwhile, an on chip balun realizes input matching as well as single-end to differential conversion. The PAD is fabricated in a 0.13 μm RFCMOS process. The chip size is 1.1 × 1.1 mm2 with all of the matching network integrated on chip. The saturated power is around 10 dBm and power gain is about 12 dB. (semiconductor integrated circuits)

  3. Scaling of electroresistance effect in fully integrated ferroelectric tunnel junctions

    Science.gov (United States)

    Abuwasib, Mohammad; Lu, Haidong; Li, Tao; Buragohain, Pratyush; Lee, Hyungwoo; Eom, Chang-Beom; Gruverman, Alexei; Singisetti, Uttam

    2016-04-01

    Systematic investigation of the scalability for tunneling electroresistance (TER) of integrated Co/BaTiO3/SrRuO3 ferroelectric tunnel junctions (FTJs) has been performed from micron to deep submicron dimensions. Pulsed measurements of the transient currents confirm the ferroelectric switching behavior of the FTJs, while the hysteresis loops measured by means of piezoresponse force microscopy verify the scalability of these structures. Fully integrated functional FTJ devices with the size of 300 × 300 nm2 exhibiting a tunneling electroresistance (TER) effect of the order of 2.7 × 104% have been fabricated and tested. Measured current density of 75 A/cm2 for the ON state and a long polarization retention time of ON state (>10 h) show a lot of promise for implementation of high-density BaTiO3-based FTJ memory devices in future.

  4. 35 GHz integrated circuit rectifying antenna with 33 percent efficiency

    Science.gov (United States)

    Yoo, T.-W.; Chang, K.

    1991-01-01

    A 35 GHz integrated circuit rectifying antenna (rectenna) has been developed using a microstrip dipole antenna and beam-lead mixer diode. Greater than 33 percent conversion efficiency has been achieved. The circuit should have applications in microwave/millimeter-wave power transmission and detection.

  5. An improved fully integrated, high-speed, dual-modulus divider

    International Nuclear Information System (INIS)

    A fully integrated 2n/2n+1 dual-modulus divider in GHz frequency range is presented. The improved structure can make all separated logic gates embed into correlative D flip—flops completely. In this way, the complex logic functions can be performed with a minimum number of devices and with maximum speed, so that lower power consumption and faster speed are obtained. In addition, the low-voltage bandgap reference needed by the frequency divider is specifically designed to provide a 1.0 V output. According to the design demand, the circuit is fabricated in 0.18 μm standard CMOS process, and the measured results show that its operating frequency range is 1.1–2.5 GHz. The dual-modulus divider dissipates 1.1 mA from a 1.8 V power supply. The temperature coefficient of the reference voltage circuit is 8.3 ppm/°C when the temperature varies from −40 to +125 °C. By comparison, the dual-modulus divide designed in this paper can possess better performance and flexibility. (semiconductor integrated circuits)

  6. 77 FR 33486 - Certain Integrated Circuit Packages Provided With Multiple Heat-Conducting Paths and Products...

    Science.gov (United States)

    2012-06-06

    ... COMMISSION Certain Integrated Circuit Packages Provided With Multiple Heat- Conducting Paths and Products.... International Trade Commission has received a complaint entitled Certain Integrated Circuit Packages Provided... sale within the United States after importation of certain integrated circuit packages provided...

  7. Radiation-hardened transistor and integrated circuit

    Science.gov (United States)

    Ma, Kwok K.

    2007-11-20

    A composite transistor is disclosed for use in radiation hardening a CMOS IC formed on an SOI or bulk semiconductor substrate. The composite transistor has a circuit transistor and a blocking transistor connected in series with a common gate connection. A body terminal of the blocking transistor is connected only to a source terminal thereof, and to no other connection point. The blocking transistor acts to prevent a single-event transient (SET) occurring in the circuit transistor from being coupled outside the composite transistor. Similarly, when a SET occurs in the blocking transistor, the circuit transistor prevents the SET from being coupled outside the composite transistor. N-type and P-type composite transistors can be used for each and every transistor in the CMOS IC to radiation harden the IC, and can be used to form inverters and transmission gates which are the building blocks of CMOS ICs.

  8. On the Behavioral Modeling of Integrated Circuit Output Buffers

    OpenAIRE

    Canavero, Flavio; Stievano, Igor Simone; Maio, Ivano Adolfo

    2003-01-01

    The properties of common behavioral macromodels for single ended CMOS integrated circuits output buffers are discussed with the aim of providing criteria for an effective use of possible modeling options

  9. Superconducting single photon detectors integrated with diamond nanophotonic circuits

    CERN Document Server

    Rath, Patrik; Ferrari, Simone; Sproll, Fabian; Lewes-Malandrakis, Georgia; Brink, Dietmar; Ilin, Konstantin; Siegel, Michael; Nebel, Christoph; Pernice, Wolfram

    2015-01-01

    Photonic quantum technologies promise to repeat the success of integrated nanophotonic circuits in non-classical applications. Using linear optical elements, quantum optical computations can be performed with integrated optical circuits and thus allow for overcoming existing limitations in terms of scalability. Besides passive optical devices for realizing photonic quantum gates, active elements such as single photon sources and single photon detectors are essential ingredients for future optical quantum circuits. Material systems which allow for the monolithic integration of all components are particularly attractive, including III-V semiconductors, silicon and also diamond. Here we demonstrate nanophotonic integrated circuits made from high quality polycrystalline diamond thin films in combination with on-chip single photon detectors. Using superconducting nanowires coupled evanescently to travelling waves we achieve high detection efficiencies up to 66 % combined with low dark count rates and timing resolu...

  10. Vertically integrated circuit development at Fermilab for detectors

    International Nuclear Information System (INIS)

    Today vertically integrated circuits, (a.k.a. 3D integrated circuits) is a popular topic in many trade journals. The many advantages of these circuits have been described such as higher speed due to shorter trace lenghts, the ability to reduce cross talk by placing analog and digital circuits on different levels, higher circuit density without the going to smaller feature sizes, lower interconnect capacitance leading to lower power, reduced chip size, and different processing for the various layers to optimize performance. There are some added advantages specifically for MAPS (Monolithic Active Pixel Sensors) in High Energy Physics: four side buttable pixel arrays, 100% diode fill factor, the ability to move PMOS transistors out of the diode sensing layer, and a increase in channel density. Fermilab began investigating 3D circuits in 2006. Many different bonding processes have been described for fabricating 3D circuits [1]. Fermilab has used three different processes to fabricate several circuits for specific applications in High Energy Physics and X-ray imaging. This paper covers some of the early 3D work at Fermilab and then moves to more recent activities. The major processes we have used are discussed and some of the problems encountered are described. An overview of pertinent 3D circuit designs is presented along with test results thus far.

  11. An approach towards fully integration of CAD and CAM technologies

    Directory of Open Access Journals (Sweden)

    M. Tolouei-Rad

    2006-08-01

    Full Text Available Purpose: An integrated CAD/CAM system for milling operations has been developed which helps designers tosolve machining problems at the design stage.Design/methodology/approach: A methodology has been employed which provides all necessary informationfor machining products automatically. Use of these system results in reduced machining leadtimes and costthrough designing machinable components; using available cutting tools; improving machining efficiency. Thesystem is menu driven with a user friendly interface.Findings: Different components for developing such a system have been identified and various problems thatarose in the development of this system have been dealt with The system developed leads to an adequate basisfor fully integration of CAD and CAM technologies in one system. It allows simultaneous generation of allinformation required to satisfy machining requirements of the design such as its machinability and availabilityof the required tooling resources.Research limitations/implications: Different components required for developing such systems have beenidentified and various problems that arose in the development of these systems have been dealt with, leadingto an adequate basis for complete integration of CAD and CAM technologies. Although much of the workdescribed here goes beyond the scope of published literature, however, it should be noted that the systemdeveloped couldn’t be considered as a complete solution to the CAD/CAM integration problem. Further workrequires including other manufacturing activities that are considered in concurrent engineering concept. In thisdirection, further integration of the system developed with systems such as MRP, MRP II and assembly sequenceplanning packages are highly desirable.Originality/value: CAD/CAM integration is regarded as a solution for bridging the gap between design andmanufacturing, one of the ultimate goals for concurrent engineering. Since the advent of CAD and CAMnumerous

  12. A fully integrated direct-conversion digital satellite tuner in 0.18 {mu}m CMOS

    Energy Technology Data Exchange (ETDEWEB)

    Chen Si; Yang Zengwang; Gu Mingliang, E-mail: chensism@126.com [Xuzhou Normal University, Xuzhou 221116 (China)

    2011-04-15

    A fully integrated direct-conversion digital satellite tuner for DVB-S/S2 and ABS-S applications is presented. A broadband noise-canceling Balun-LNA and passive quadrature mixers provided a high-linearity low noise RF front-end, while the synthesizer integrated the loop filter to reduce the solution cost and system debug time. Fabricated in 0.18 {mu}m CMOS, the chip achieves a less than 7.6 dB noise figure over a 900-2150 MHz L-band, while the measured sensitivity for 4.42 MS/s QPSK-3/4 mode is -91 dBm at the PCB connector. The fully integrated integer-N synthesizer operating from 2150 to 4350 MHz achieves less than 1 deg. C integrated phase error. The chip consumes about 145 mA at a 3.3 V supply with internal integrated LDOs. (semiconductor integrated circuits)

  13. A fully integrated direct-conversion digital satellite tuner in 0.18 μm CMOS

    International Nuclear Information System (INIS)

    A fully integrated direct-conversion digital satellite tuner for DVB-S/S2 and ABS-S applications is presented. A broadband noise-canceling Balun-LNA and passive quadrature mixers provided a high-linearity low noise RF front-end, while the synthesizer integrated the loop filter to reduce the solution cost and system debug time. Fabricated in 0.18 μm CMOS, the chip achieves a less than 7.6 dB noise figure over a 900-2150 MHz L-band, while the measured sensitivity for 4.42 MS/s QPSK-3/4 mode is -91 dBm at the PCB connector. The fully integrated integer-N synthesizer operating from 2150 to 4350 MHz achieves less than 1 deg. C integrated phase error. The chip consumes about 145 mA at a 3.3 V supply with internal integrated LDOs. (semiconductor integrated circuits)

  14. Fully integrated aerodynamic/dynamic optimization of helicopter rotor blades

    Science.gov (United States)

    Walsh, Joanne L.; Lamarsh, William J., II; Adelman, Howard M.

    1992-01-01

    A fully integrated aerodynamic/dynamic optimization procedure is described for helicopter rotor blades. The procedure combines performance and dynamic analyses with a general purpose optimizer. The procedure minimizes a linear combination of power required (in hover, forward flight, and maneuver) and vibratory hub shear. The design variables include pretwist, taper initiation, taper ratio, root chord, blade stiffnesses, tuning masses, and tuning mass locations. Aerodynamic constraints consist of limits on power required in hover, forward flight and maneuvers; airfoil section stall; drag divergence Mach number; minimum tip chord; and trim. Dynamic constraints are on frequencies, minimum autorotational inertia, and maximum blade weight. The procedure is demonstrated for two cases. In the first case, the objective function involves power required (in hover, forward flight and maneuver) and dynamics. The second case involves only hover power and dynamics. The designs from the integrated procedure are compared with designs from a sequential optimization approach in which the blade is first optimized for performance and then for dynamics. In both cases, the integrated approach is superior.

  15. Novel Empty Substrate Integrated Waveguide for High Performance Microwave Integrated Circuits

    OpenAIRE

    BELENGUER MARTÍNEZ, ÁNGEL; Esteban González, Héctor; Boria Esbert, Vicente Enrique

    2014-01-01

    Abstract Over the last years, a great number of substrate integrated circuits has been developed. These new circuits are a compromise between the advantages of classical waveguide technologies, such as high quality factor and low losses, and the advantages of planar circuits, such as low cost and easy compact integration. Although their quality factor and losses are better than for planar circuits, these characteristics are worse than in the case of waveguides, mainly due...

  16. Providing Reliability of Physical Systems: Fully Delay Testable Logical Circuit Design with Compact Representation of all PDF Test Pairs

    Science.gov (United States)

    Matrosova, A. Yu.; Mitrofanov, E. V.; Akhynova, D. I.

    2016-01-01

    Functional reliability is one of the important properties of physical systems provided by reliability of system components, in particular, control logical components. The new approach to fully delay testable circuit design oriented to cut overheads and lengths of circuit paths has been developed. Compact representation of all PDF test pairs is reduced to keeping the corresponding generative vector pairs. The number of generative vector pairs does not exceed the doubled number of internal ROBDD nodes originating from the circuit, while the number of the circuit paths can exponentially depend on the number of these internal nodes. The algorithm of involving the PDF test pair from the proper generative vector pair is suggested. This procedure does not require essential calculations. The algorithm of deriving the generative vector pair has a polynomial complexity.

  17. A fully integrated IQ-receiver for NMR microscopy

    Science.gov (United States)

    Anders, Jens; SanGiorgio, Paul; Boero, Giovanni

    2011-03-01

    We present a fully integrated CMOS receiver for micro-magnetic resonance imaging together with a custom-made micro-gradient system. The receiver is designed for an operating frequency of 300 MHz. The chip consists of an on-chip detection coil and tuning capacitor as well as a low-noise amplifier and a quadrature downconversion mixer with corresponding low-frequency amplification stages. The design is realized in a 0.13 μm CMOS technology, it occupies a chip area of 950 × 800 μm 2 and it draws 50 mA from a supply voltage of 1.8 V. The achieved time-domain spin sensitivity is 5 × 10 14spins/ √{Hz}. Images of phantoms obtained in our custom-made gradient system with 8 μm isotropic resolution are reported.

  18. Microwave GaAs Integrated Circuits On Quartz Substrates

    Science.gov (United States)

    Siegel, Peter H.; Mehdi, Imran; Wilson, Barbara

    1994-01-01

    Integrated circuits for use in detecting electromagnetic radiation at millimeter and submillimeter wavelengths constructed by bonding GaAs-based integrated circuits onto quartz-substrate-based stripline circuits. Approach offers combined advantages of high-speed semiconductor active devices made only on epitaxially deposited GaAs substrates with low-dielectric-loss, mechanically rugged quartz substrates. Other potential applications include integration of antenna elements with active devices, using carrier substrates other than quartz to meet particular requirements using lifted-off GaAs layer in membrane configuration with quartz substrate supporting edges only, and using lift-off technique to fabricate ultrathin discrete devices diced separately and inserted into predefined larger circuits. In different device concept, quartz substrate utilized as transparent support for GaAs devices excited from back side by optical radiation.

  19. Optical integrated circuits and networks on microscale/nanoscale

    Science.gov (United States)

    Lee, El-Hang; Lee, S. G.; O, B. H.; Park, S. G.; Kim, K. H.; Song, S. H.

    2007-02-01

    We present an overview of our work on the design and fabrication of micro/nano-scale photonic circuits and networks on what we call "optical printed circuit boards" (O-PCBs) and "VLSI photonic integrated circuit chips"(VLSI-PICs) of generic and application-specific nature. The O-PCBs and photonic chips consist of 2-dimensional planar arrays of optical wires, circuits, and networks of micro/nano-scale to perform the functions of sensing, storing, transporting, processing, switching, routing, and distributing optical signals on flat boards or chips. We describe and discuss scientific and technological issues concerning the miniaturization, interconnection and integration of micro/nano-scale photonic devices, circuits, and networks leading to small and very large scale integration in terms of photonic scaling rules and discuss their use for the design and fabrication of the photonic integrated circuits and networks. Design rules for the miniaturization and integration of the micro/nano-photonic systems are discussed in comparison with those of the micro/nano-electronic systems. Materials include polymer/organic materials and silicon materials. Structural bases include photonic crystals, ring resonators, and plasmonic structures. Compatibility issues between diverse materials and devices are discussed especially in regard to applications. Recent progresses and examples are presented.

  20. Fully Integrated Biopotential Acquisition Analog Front-End IC

    Directory of Open Access Journals (Sweden)

    Haryong Song

    2015-09-01

    Full Text Available A biopotential acquisition analog front-end (AFE integrated circuit (IC is presented. The biopotential AFE includes a capacitively coupled chopper instrumentation amplifier (CCIA to achieve low input referred noise (IRN and to block unwanted DC potential signals. A DC servo loop (DSL is designed to minimize the offset voltage in the chopper amplifier and low frequency respiration artifacts. An AC coupled ripple rejection loop (RRL is employed to reduce ripple due to chopper stabilization. A capacitive impedance boosting loop (CIBL is designed to enhance the input impedance and common mode rejection ratio (CMRR without additional power consumption, even under an external electrode mismatch. The AFE IC consists of two-stage CCIA that include three compensation loops (DSL, RRL, and CIBL at each CCIA stage. The biopotential AFE is fabricated using a 0.18 μm one polysilicon and six metal layers (1P6M complementary metal oxide semiconductor (CMOS process. The core chip size of the AFE without input/output (I/O pads is 10.5 mm2. A fourth-order band-pass filter (BPF with a pass-band in the band-width from 1 Hz to 100 Hz was integrated to attenuate unwanted signal and noise. The overall gain and band-width are reconfigurable by using programmable capacitors. The IRN is measured to be 0.94 μVRMS in the pass band. The maximum amplifying gain of the pass-band was measured as 71.9 dB. The CIBL enhances the CMRR from 57.9 dB to 67 dB at 60 Hz under electrode mismatch conditions.

  1. Fully Integrated Biopotential Acquisition Analog Front-End IC.

    Science.gov (United States)

    Song, Haryong; Park, Yunjong; Kim, Hyungseup; Ko, Hyoungho

    2015-01-01

    A biopotential acquisition analog front-end (AFE) integrated circuit (IC) is presented. The biopotential AFE includes a capacitively coupled chopper instrumentation amplifier (CCIA) to achieve low input referred noise (IRN) and to block unwanted DC potential signals. A DC servo loop (DSL) is designed to minimize the offset voltage in the chopper amplifier and low frequency respiration artifacts. An AC coupled ripple rejection loop (RRL) is employed to reduce ripple due to chopper stabilization. A capacitive impedance boosting loop (CIBL) is designed to enhance the input impedance and common mode rejection ratio (CMRR) without additional power consumption, even under an external electrode mismatch. The AFE IC consists of two-stage CCIA that include three compensation loops (DSL, RRL, and CIBL) at each CCIA stage. The biopotential AFE is fabricated using a 0.18 μm one polysilicon and six metal layers (1P6M) complementary metal oxide semiconductor (CMOS) process. The core chip size of the AFE without input/output (I/O) pads is 10.5 mm². A fourth-order band-pass filter (BPF) with a pass-band in the band-width from 1 Hz to 100 Hz was integrated to attenuate unwanted signal and noise. The overall gain and band-width are reconfigurable by using programmable capacitors. The IRN is measured to be 0.94 μVRMS in the pass band. The maximum amplifying gain of the pass-band was measured as 71.9 dB. The CIBL enhances the CMRR from 57.9 dB to 67 dB at 60 Hz under electrode mismatch conditions. PMID:26437404

  2. Aiming for a fully integrated computerized procedure system

    International Nuclear Information System (INIS)

    A fully integrated Computerized Procedure System must provide, at a minimum, a) Specification: access to design basis procedures, b) Monitoring: incorporation of real-time plant status, c) Advise: highlighting likely decision paths, and d) Reporting: logging conditions and actions taken. The CPS plays a critical role in overcoming the human factors that lead to accidents. At the same time it can be an essential tool in providing the information and automation to augment what humans do best, identify patterns and make associative leaps in the presence of ambiguous data. Timeliner and TaskGuide are examples of CPS that have evolved from projects in the aerospace industry. They illustrate certain common characteristics of a CPS, namely the knowledge base, user interface, and traceability features. The complexity and number of procedures for a current nuclear project has led to the development of two tools, the Power Generation Control System (PGCS) and the Online Procedure System (OLPS). Together, these systems address the knowledge-base and user interface aspects of a CPS and go a long way in addressing other areas. PGCS and OLPS contain full configuration management capabilities for procedures and the operating recipe. They include administrative functions for online and offline management of documents and data. Some lessons learned from this pair of programs developed by Invensys is the need for more integrated recording mechanisms. The future of CPS is likely to see higher integration of the document access, system status, decision support and logging capabilities. The CPS may evolve into the standard operational interface. Internet technologies that are common-place today have made the possibility of the Active Document a reality. The OPC Foundation is pursuing standards that may accelerate such developments. (authors)

  3. Study of CMOS integrated signal processing circuit in capacitive sensors

    Institute of Scientific and Technical Information of China (English)

    CAO Yi-jiang; YU Xiang; WANG Lei

    2007-01-01

    A CMOS integrated signal processing circuit based on capacitance resonance principle whose structure is simple in capacitive sensors is designed. The waveform of output voltage is improved by choosing bootstrap reference current mirror with initiate circuit, CMOS analogy switch and positive feedback of double-stage inverter in the circuit. Output voltage of this circuit is a symmetric square wave signal. The variation of sensitive capacitance, which is part of the capacitive sensors, can be denoted by the change of output voltage's frequency. The whole circuit is designed with 1.5 μm P-well CMOS process and simulated by PSpice software.Output frequency varies from 261.05 kHz to 47.93 kHz if capacitance varies in the range of 1PF~15PF. And the variation of frequency can be easily detected using counter or SCU.

  4. 77 FR 19032 - Certain Semiconductor Integrated Circuit Devices and Products Containing Same Notice of Receipt...

    Science.gov (United States)

    2012-03-29

    ... COMMISSION Certain Semiconductor Integrated Circuit Devices and Products Containing Same Notice of Receipt of... received a complaint entitled Certain Semiconductor Integrated Circuit Devices and Products Containing Same... circuit devices and products containing same. The complaint names as respondents Intersil Corporation...

  5. Simulation of proton-induced energy deposition in integrated circuits

    Science.gov (United States)

    Fernald, Kenneth W.; Kerns, Sherra E.

    1988-01-01

    A time-efficient simulation technique was developed for modeling the energy deposition by incident protons in modern integrated circuits. To avoid the excessive computer time required by many proton-effects simulators, a stochastic method was chosen to model the various physical effects responsible for energy deposition by incident protons. Using probability density functions to describe the nuclear reactions responsible for most proton-induced memory upsets, the simulator determines the probability of a proton hit depositing the energy necessary for circuit destabilization. This factor is combined with various circuit parameters to determine the expected error-rate in a given proton environment. An analysis of transient or dose-rate effects is also performed. A comparison to experimental energy-disposition data proves the simulator to be quite accurate for predicting the expected number of events in certain integrated circuits.

  6. Dielectric isolation for power integrated circuits; Isolation dielectrique enterree pour les circuits integres de puissance

    Energy Technology Data Exchange (ETDEWEB)

    Zerrouk, D.

    1997-07-18

    Considerable efforts have been recently directed towards integrating onto the same chip, sense or protection elements that is low voltage analog and/or digital control circuitry together with high voltage/high current devices. Most of these so called `smart power` devices use either self isolation, junction isolation or Silicon-On-Insulator (SOI) to integrate low voltage elements with vertical power devices. Dielectric isolation is superior to the other isolation techniques such as self isolation or junction isolation. Thesis work consists of the study of the feasibility of a dielectric technology based on the melting and the solidification in a Rapid Thermal Processing furnace (RTP), of thick polysilicon films deposited on oxide. The purpose of this technique is to obtain substrate with localized SOI structures for smart power applications. SOI technology offers significant potential advantages, such as non-occurrence of latch-up in CMOS structures, high packaging density, low parasitic capacitance and the possibility of 3D structures. In addition, SOI technology using thick silicon films (10-100 {mu}m) offers special advantages for high voltage integrated circuits. Several techniques have been developed to form SOI films. Zone melting recrystallization is one of the most promising for localized SOI. The SOI structures have first been analyzed in term of extended defects. N-channel MOSFET`s transistors have also been fabricated in the SOI substrates and electrically characterized (threshold voltages, off-state leakage current, mobilities,...). The SOI transistors exhibit good characteristics, although inferior to witness transistors. The recrystallized silicon films are therefore found to be suitable for the fabrication of SOI devices. (author) 106 refs.

  7. Micro-relay technology for energy-efficient integrated circuits

    CERN Document Server

    Kam, Hei

    2015-01-01

    This book describes the design of relay-based circuit systems from device fabrication to circuit micro-architectures. This book is ideal for both device engineers as well as circuit system designers and highlights the importance of co-design across design hierarchies when optimizing system performance (in this case, energy-efficiency). This book is ideal for researchers and engineers focused on semiconductors, integrated circuits, and energy efficient electronics. This book also: ·         Covers microsystem fabrication, MEMS device design, circuit design, circuit micro-architecture, and CAD ·         Describes work previously done in the field and also lays the groundwork and criteria for future energy-efficient device and system design ·         Maximizes reader insights into the design and modeling of micro-relay, micro-relay reliability, integrated circuit design with micro-relays, and more

  8. Integrated digital superconducting logic circuits for the quantum synthesizer. Report

    International Nuclear Information System (INIS)

    This report presents the results, which were reached in the framework of the BMBF cooperative plan ''Quantum Synthesizer'' in the partial plan ''Integrated Digital Superconducting Logic Circuits''. As essential goal of the plan a novel instrument on the base of quantum-coherent superconducting circuits should be developed. which allows to generate praxis-relevant wave forms with quantum accuracy, the quantum synthesizer. The main topics of development of the reported partial plan lied at the one hand in the development of integrated, digital, superconducting circuit in rapid-single-flux (RSFQ) quantum logics for the pattern generator of the quantum synthesizer, at the other hand in the further development of the fabrication technology for the aiming of high circuit complexity. In order to fulfil these requirements at the PTB a new design system was implemented, based on the software of Cadence. Together with the required RSFQ extensions for the design of digital superconducting circuits was a platform generated, on which the reachable circuit complexity is exclusively limited by the technology parameters of the available fabrication technology: Physical simulations are with PSCAN up to a complexity of more than 1000 circuit elements possible; furthermore VHDL allows the verification of arbitrarily large circuit architectures. In accordance for this the production line at the PTB was brought to a level, which allows in Nb/Al-AlxOy/Nb SIS technology implementation the fabrication of highly integrable RSFQ circuit architectures. The developed and fabricated basic circuits of the pattern generator have proved correct functionality and reliability in the measuring operation. Thereby for the circular RSFQ shift registers a key role as local memories in the construction of the pattern generator is devolved upon. The registers were realized with the aimed bit lengths up to 128 bit and with reachable signal-processing speeds of above 10 GHz. At the interface RSFQ

  9. Advances in Silicon Based Millimeter-Wave Monolithic Integrated Circuits

    OpenAIRE

    Han-Chih Yeh; Ching-Chau Chiong; Ming-Tang Chen; Huei Wang

    2014-01-01

    In this paper, the advances of the silicon-based millimeter-wave (MMW) monolithic integrated circuits (MMICs) are reported. The silicon-based technologies for MMW MMICs are briefly introduced. In addition, the current status of the MMW MMICs is surveyed and novel circuit topologies are summarized. Some representative MMW MMICs are illustrated as design examples in the categories of their functions in a MMW system. Finally, there is a conclusion and description of the future trend of the devel...

  10. Advances in organic field-effect transistors and integrated circuits

    Institute of Scientific and Technical Information of China (English)

    2009-01-01

    Organic field-effect transistors (OFETs) have received significant research interest because of their promising applications in low cast, lager area, plastic circuits, and tremendous progress has been made in materials, device performance, OFETs based circuits in recent years. In this article we introduce the advances in organic semiconductor materials, OFETs based integrating techniques, and in particular highlight the recent progress. Finally, the prospects and problems of OFETs are discussed.

  11. Silicon-based optical integrated circuits for terabit communication networks

    International Nuclear Information System (INIS)

    A brief review is presented of the development of silicon-based optical integrated circuits used as components in modern all-optical communication networks with the terabit-per-second transmission capacity. The designs and technologies for manufacturing these circuits are described and the problems related to their development and application in WDM communication systems are considered. (special issue devoted to the memory of academician a m prokhorov)

  12. Superconductive passive phase shifter for integrated RSFQ digital circuits

    International Nuclear Information System (INIS)

    A vital precondition for the realization of rapid single-flux quantum (RSFQ) digital circuits with reduced critical currents of the Josephson junctions is the implementation of an efficient technique for superconductive phase dropping. In this paper, we present a novel phase shifting element consisting of a miniature superconductive ring located over a ground plane hole. Contrary to the solutions reported up to now, this topology can be simply integrated within complex digital RSFQ circuits realized with conventional fabrication technology

  13. Design and implementation of a high sensitivity fully integrated passive UHF RFID tag

    International Nuclear Information System (INIS)

    A fully integrated passive UHF RFID tag complying with the ISO18000-6B protocol is presented, which includes an analog front-end, a baseband processor, and an EEPROM memory. To extend the communication range, a high efficiency differential-drive CMOS rectifier is adopted. A novel high performance voltage limiter is used to provide a stable limiting voltage, with a 172 mV voltage variation against temperature variation and process dispersion. The dynamic band-enhancement technique is used in the regulator circuit to improve the regulating capacity. A rail-to-rail hysteresis comparator is adopted to demodulate the signal correctly in any condition. The whole transponder chip is implemented in a 0.18 μm CMOS process, with a die size of 900 × 800 μm2. Our measurement results show that the total power consumption of the tag chip is only 6.8 μW, with a sensitivity of −13.5 dBm (semiconductor integrated circuits)

  14. Single Event Transients in Linear Integrated Circuits

    Science.gov (United States)

    Buchner, Stephen; McMorrow, Dale

    2005-01-01

    On November 5, 2001, a processor reset occurred on board the Microwave Anisotropy Probe (MAP), a NASA mission to measure the anisotropy of the microwave radiation left over from the Big Bang. The reset caused the spacecraft to enter a safehold mode from which it took several days to recover. Were that to happen regularly, the entire mission would be compromised, so it was important to find the cause of the reset and, if possible, to mitigate it. NASA assembled a team of engineers that included experts in radiation effects to tackle the problem. The first clue was the observation that the processor reset occurred during a solar event characterized by large increases in the proton and heavy ion fluxes emitted by the sun. To the radiation effects engineers on the team, this strongly suggested that particle radiation might be the culprit, particularly when it was discovered that the reset circuit contained three voltage comparators (LM139). Previous testing revealed that large voltage transients, or glitches appeared at the output of the LM139 when it was exposed to a beam of heavy ions [NI96]. The function of the reset circuit was to monitor the supply voltage and to issue a reset command to the processor should the voltage fall below a reference of 2.5 V [PO02]. Eventually, the team of engineers concluded that ionizing particle radiation from the solar event produced a negative voltage transient on the output of one of the LM139s sufficiently large to reset the processor on MAP. Fortunately, as of the end of 2004, only two such resets have occurred. The reset on MAP was not the first malfunction on a spacecraft attributed to a transient. That occurred shortly after the launch of NASA s TOPEX/Poseidon satellite in 1992. It was suspected, and later confirmed, that an anomaly in the Earth Sensor was caused by a transient in an operational amplifier (OP-15) [KO93]. Over the next few years, problems on TDRS, CASSINI, [PR02] SOHO [HA99,HA01] and TERRA were also attributed

  15. The fully integrated engineer combining technical ability and leadership prowess

    CERN Document Server

    Cerri, Steven T

    2016-01-01

    College teaches you to be a good engineer. But it's likely that your college engineering courses didn't have time to teach you how to effectively contribute your ideas or how to transition to management or leadership. This book provides you with those missing tools. This book addresses the differences between being proficient as a technical individual and effectively contributing to and leading a team to effectively contribute to various projects. The Fully Integrated Engineer: Combining Technical Ability and Leadership Prowess shines a light on how the habits learned in school, while contributing to individual short-term success, actually become hindrances in the modern engineering workplace if your goal is to achieve long-term success as either an engineer, a team lead, manager, or leader. The author offers specific ways to address those limiting habits, turning you into an effective team contributor and leader building toward long-term career succes . The author’s approach to retooling less-than-op...

  16. Radiation effects in semiconductors: technologies for hardened integrated circuits

    International Nuclear Information System (INIS)

    Various technologies are used to manufacture integrated circuits for electronic systems. But for specific applications, including those with radiation environment, it is necessary to choose an appropriate technologie or to improve a specific one in order to reach a definite hardening level. The aim of this paper is to present the main effects induced by radiation (neutrons and gamma rays) into the basic semiconductor devices, to explain some physical degradation mechanisms and to propose solutions for hardened integrated circuit fabrication. The analysis involves essentially the monolithic structure of the integrated circuits and the isolation technology of active elements. In conclusion, the advantages of EPIC and SOS technologies are described and the potentialities of new technologies (GaAs and SOI) are presented

  17. Performance Analysis of Various Readout Circuits for Monitoring Quality of Water Using Analog Integrated Circuits

    Directory of Open Access Journals (Sweden)

    Pawan Whig

    2012-10-01

    Full Text Available This paper presents a comparative performance study of various analog integrated circuits (namely CC-II, DVCC, CDBA and CDTA used with ISFET for monitoring the quality of water. The use of these active components makes the implementation simple and attractive. The functionality of the circuits are tested using Tanner simulator version 15 for a 70nm CMOS process model also the transfer functions realization for each is done on MATLAB R2011a version, the Very high speed integrated circuit Hardware description language(VHDL code for all scheme is simulated on Xilinx ISE 10.1 and various simulation results are obtained and its is found that DVCC is most stable and consume maximum power whereas CC-II is the least stable and consumes minimum power amongst all the four deployed analog IC’s. Detailed simulation results are included in the paper to give insight into the research work carried out.

  18. Programmable delay unit incorporating a semi-custom integrated circuit

    International Nuclear Information System (INIS)

    The synchronization of SLC accelerator control and monitoring functions is realized by a CAMAC module, the PDU II (Programmable Delay Unit II, SLAC 253-002), which includes a semi-custom gate array integrated circuit. The PDU II distributes 16 channels of independently programmable delayed pulses to other modules within the same CAMAC crate. The delays are programmable in increments of 8.4 ns. Functional descriptions of both the module and the semi-custom integrated circuit used to generate the output pulses are given

  19. Silicon integrated circuits advances in materials and device research

    CERN Document Server

    Kahng, Dawon

    1981-01-01

    Silicon Integrated Circuits, Part B covers the special considerations needed to achieve high-power Si-integrated circuits. The book presents articles about the most important operations needed for the high-power circuitry, namely impurity diffusion and oxidation; crystal defects under thermal equilibrium in silicon and the development of high-power device physics; and associated technology. The text also describes the ever-evolving processing technology and the most promising approaches, along with the understanding of processing-related areas of physics and chemistry. Physicists, chemists, an

  20. Highly resolved spatial and temporal photoemission analysis of integrated circuits

    International Nuclear Information System (INIS)

    We develop an optical system for highly resolved photoemission analysis of integrated circuits. Photons emitted by switching transistors allow the operation of an integrated circuit to be observed by recording the individual photoemission acts. The ongoing feature size reduction makes the space–time-resolved detection of these extremely weak photoemissions challenging. We combine different optical and photonic solutions to achieve both a high spatial and temporal resolution in a compact analysis system. Imaging and detection modules capture photons through the substrate during normal chip operation and perform highly resolved optical analysis. We demonstrate the system capability by photoemission records of a real-world IC device. (paper)

  1. 3D circuit integration for Vertex and other detectors

    Energy Technology Data Exchange (ETDEWEB)

    Yarema, Ray; /Fermilab

    2007-09-01

    High Energy Physics continues to push the technical boundaries for electronics. There is no area where this is truer than for vertex detectors. Lower mass and power along with higher resolution and radiation tolerance are driving forces. New technologies such as SOI CMOS detectors and three dimensional (3D) integrated circuits offer new opportunities to meet these challenges. The fundamentals for SOI CMOS detectors and 3D integrated circuits are discussed. Examples of each approach for physics applications are presented. Cost issues and ways to reduce development costs are discussed.

  2. Practical applications of digital integrated circuits. Part 3: Practical sequential theory and synchronous circuits

    Science.gov (United States)

    1973-01-01

    Here, the 7400 line of transistor to transistor logic (TTL) devices is emphasized almost exclusively where hardware is concerned. However, it should be noted that the logic theory contained herein applies to all hardware. Discussed here are synchronous binary UP counters, synchronous DOWN and UP/DOWN counters, integrated circuit counters, shift registers, sequential techniques, and designing sequential counting machines.

  3. Integrated CMOS photodetectors and signal processing for very low-level chemical sensing with the bioluminescent bioreporter integrated circuit

    Science.gov (United States)

    Bolton, Eric K.; Sayler, Gary S.; Nivens, David E.; Rochelle, James M.; Ripp, Steven; Simpson, Michael L.

    2002-01-01

    We report an integrated CMOS microluminometer optimized for the detection of low-level bioluminescence as part of the bioluminescent bioreporter integrated circuit (BBIC). This microluminometer improves on previous devices through careful management of the sub-femtoampere currents, both signal and leakage, that flow in the front-end processing circuitry. In particular, the photodiode is operated with a reverse bias of only a few mV, requiring special attention to the reset circuitry of the current-to-frequency converter (CFC) that forms the front-end circuit. We report a sub-femtoampere leakage current and a minimum detectable signal (MDS) of 0.15 fA (1510 s integration time) using a room temperature 1.47 mm2 CMOS photodiode. This microluminometer can detect luminescence from as few as 5000 fully induced Pseudomonas fluorescens 5RL bacterial cells. c2002 Elsevier Science B.V. All rights reserved.

  4. Optimal low-order fully integrated solid-shell elements

    Science.gov (United States)

    Rah, K.; Paepegem, W. Van; Habraken, A. M.; Degrieck, J.; de Sousa, R. J. Alves; Valente, R. A. F.

    2013-03-01

    This paper presents three optimal low-order fully integrated geometrically nonlinear solid-shell elements based on the enhanced assumed strain (EAS) method and the assumed natural strain method for different types of structural analyses, e.g. analysis of thin homogeneous isotropic and multilayer anisotropic composite shell-like structures and the analysis of (near) incompressible materials. The proposed solid-shell elements possess eight nodes with only displacement degrees of freedom and a few internal EAS parameters. Due to the 3D geometric description of the proposed elements, 3D constitutive laws can directly be employed in these formulations. The present formulations are based on the well-known Fraeijs de Veubeke-Hu-Washizu multifield variational principle. In terms of accuracy as well as efficiency point of view, the choice of the optimal EAS parameters plays a very critical role in the EAS method, therefore a systematic numerical study has been carried out to find out the optimal EAS parameters to alleviate different locking phenomena for the proposed solid-shell formulations. To assess the accuracy of the proposed solid-shell elements, a variety of popular numerical benchmark examples related to element convergence, mesh distortions, element aspect ratios and different locking phenomena are investigated and the results are compared with the well-known solid-shell formulations available in the literature. The results of our numerical assessment show that the proposed solid-shell formulations provide very accurate results, without showing any numerical problems, for a variety of geometrically linear and nonlinear structural problems.

  5. Biochips: The Integrated Circuit of Biology

    DEFF Research Database (Denmark)

    Madsen, Jan

    2012-01-01

    Microfluidic biochips integrate different biochemical analysis functionalities (e.g., dispensers, filters, mixers, separators, detectors) on-chip, miniaturizing the macroscopic chemical and biological processes often processed by lab-robots, to a sub-millimeter scale. These microsystems offer sev...

  6. Integrated logic circuits using single-atom transistors.

    Science.gov (United States)

    Mol, J A; Verduijn, J; Levine, R D; Remacle, F; Rogge, S

    2011-08-23

    Scaling down the size of computing circuits is about to reach the limitations imposed by the discrete atomic structure of matter. Reducing the power requirements and thereby dissipation of integrated circuits is also essential. New paradigms are needed to sustain the rate of progress that society has become used to. Single-atom transistors, SATs, cascaded in a circuit are proposed as a promising route that is compatible with existing technology. We demonstrate the use of quantum degrees of freedom to perform logic operations in a complementary-metal-oxide-semiconductor device. Each SAT performs multilevel logic by electrically addressing the electronic states of a dopant atom. A single electron transistor decodes the physical multivalued output into the conventional binary output. A robust scalable circuit of two concatenated full adders is reported, where by utilizing charge and quantum degrees of freedom, the functionality of the transistor is pushed far beyond that of a simple switch. PMID:21808050

  7. Printed organic thin-film transistor-based integrated circuits

    International Nuclear Information System (INIS)

    Organic electronics is moving ahead on its journey towards reality. However, this technology will only be possible when it is able to meet specific criteria including flexibility, transparency, disposability and low cost. Printing is one of the conventional techniques to deposit thin films from solution-based ink. It is used worldwide for visual modes of information, and it is now poised to enter into the manufacturing processes of various consumer electronics. The continuous progress made in the field of functional organic semiconductors has achieved high solubility in common solvents as well as high charge carrier mobility, which offers ample opportunity for organic-based printed integrated circuits. In this paper, we present a comprehensive review of all-printed organic thin-film transistor-based integrated circuits, mainly ring oscillators. First, the necessity of all-printed organic integrated circuits is discussed; we consider how the gap between printed electronics and real applications can be bridged. Next, various materials for printed organic integrated circuits are discussed. The features of these circuits and their suitability for electronics using different printing and coating techniques follow. Interconnection technology is equally important to make this product industrially viable; much attention in this review is placed here. For high-frequency operation, channel length should be sufficiently small; this could be achievable with a combination of surface treatment-assisted printing or laser writing. Registration is also an important issue related to printing; the printed gate should be perfectly aligned with the source and drain to minimize parasitic capacitances. All-printed organic inverters and ring oscillators are discussed here, along with their importance. Finally, future applications of all-printed organic integrated circuits are highlighted. (paper)

  8. Three-dimensional integrated circuit design

    CERN Document Server

    Xie, Yuan; Sapatnekar, Sachin S

    2009-01-01

    This book presents an overview of the field of 3D IC design, with an emphasis on electronic design automation (EDA) tools and algorithms that can enable the adoption of 3D ICs, and the architectural implementation and potential for future 3D system design. The aim of this book is to provide the reader with a complete understanding of: the promise of 3D ICs in building novel systems that enable the chip industry to continue along the path of performance scaling, the state of the art in fabrication technologies for 3D integration, the most prominent 3D-specific EDA challenges, along with solutio

  9. Performance of digital integrated circuit technologies at very high temperatures

    Energy Technology Data Exchange (ETDEWEB)

    Prince, J.L.; Draper, B.L.; Rapp, E.A.; Kromberg, J.N.; Fitch, L.T.

    1980-01-01

    Results of investigations of the performance and reliability of digital bipolar and CMOS integrated circuits over the 25 to 340/sup 0/C range are reported. Included in these results are both parametric variation information and analysis of the functional failure mechanisms. Although most of the work was done using commercially available circuits (TTL and CMOS) and test chips from commercially compatible processes, some results of experimental simulations of dielectrically isolated CMOS are also discussed. It was found that commercial Schottky clamped TTL, and dielectrically isolated, low power Schottky-clamped TTL, functioned to junction temperatures in excess of 325/sup 0/C. Standard gold doped TTL functioned only to 250/sup 0/C, while commercial, isolated I/sup 2/L functioned to the range 250/sup 0/C to 275/sup 0/C. Commercial junction isolated CMOS, buffered and unbuffered, functioned to the range 280/sup 0/C to 310/sup 0/C/sup +/, depending on the manufacturer. Experimental simulations of simple dielectrically isolated CMOS integrated circuits, fabricated with heavier doping levels than normal, functioned to temperatures in excess of 340/sup 0/C. High temperature life testing of experimental, silicone-encapsulated simple TTL and CMOS integrated circuits have shown no obvious life limiting problems to date. No barrier to reliable functionality of TTL bipolar or CMOS integrated ciruits at temperatures in excess of 300/sup 0/C has been found.

  10. FUZZY NEURAL NETWORK FOR OBJECT IDENTIFICATION ON INTEGRATED CIRCUIT LAYOUTS

    OpenAIRE

    Doudkin, A. A.

    2016-01-01

    Fuzzy neural network model based on neocognitron is proposed to identify layout objects on images of topological layers of integrated circuits. Testing of the model on images of real chip layouts was showed a highеr degree of identification of the proposed neural network in comparison to base neocognitron.

  11. A study of radiation hardness screening techniques of integrated circuits

    International Nuclear Information System (INIS)

    The principle and operational procedure of Integrated Circuits (ICs) screening with irradiation-and-anneal and multicomponent regression analysis are discussed. The key technology, advantages and shortcomings of the two methods are described in contrast, and some advices are given with the state-of-the-art of the screening technology

  12. Fully integrated wearable sensor arrays for multiplexed in situ perspiration analysis

    Science.gov (United States)

    Gao, Wei; Emaminejad, Sam; Nyein, Hnin Yin Yin; Challa, Samyuktha; Chen, Kevin; Peck, Austin; Fahad, Hossain M.; Ota, Hiroki; Shiraki, Hiroshi; Kiriya, Daisuke; Lien, Der-Hsien; Brooks, George A.; Davis, Ronald W.; Javey, Ali

    2016-01-01

    Wearable sensor technologies are essential to the realization of personalized medicine through continuously monitoring an individual’s state of health. Sampling human sweat, which is rich in physiological information, could enable non-invasive monitoring. Previously reported sweat-based and other non-invasive biosensors either can only monitor a single analyte at a time or lack on-site signal processing circuitry and sensor calibration mechanisms for accurate analysis of the physiological state. Given the complexity of sweat secretion, simultaneous and multiplexed screening of target biomarkers is critical and requires full system integration to ensure the accuracy of measurements. Here we present a mechanically flexible and fully integrated (that is, no external analysis is needed) sensor array for multiplexed in situ perspiration analysis, which simultaneously and selectively measures sweat metabolites (such as glucose and lactate) and electrolytes (such as sodium and potassium ions), as well as the skin temperature (to calibrate the response of the sensors). Our work bridges the technological gap between signal transduction, conditioning (amplification and filtering), processing and wireless transmission in wearable biosensors by merging plastic-based sensors that interface with the skin with silicon integrated circuits consolidated on a flexible circuit board for complex signal processing. This application could not have been realized using either of these technologies alone owing to their respective inherent limitations. The wearable system is used to measure the detailed sweat profile of human subjects engaged in prolonged indoor and outdoor physical activities, and to make a real-time assessment of the physiological state of the subjects. This platform enables a wide range of personalized diagnostic and physiological monitoring applications.

  13. Fabrication-process-induced variations of Nb/Al/AlOx/Nb Josephson junctions in superconductor integrated circuits

    International Nuclear Information System (INIS)

    Currently, superconductor digital integrated circuits fabricated at HYPRES, Inc. can operate at clock frequencies approaching 40 GHz. The circuits present multilayered structures containing tens of thousands of Nb/Al/AlOx/Nb Josephson junctions (JJs) of various sizes interconnected by four Nb wiring layers, resistors, and other circuit elements. In order to be fully operational, the integrated circuits should be fabricated such that the critical currents of the JJs are within the tight design margins and the proper relationships between the critical currents of JJs of different sizes are preserved. We present experimental data and discuss mechanisms of process-induced variations of the critical current and energy gap of Nb/Al/AlOx/Nb JJs in integrated circuits. We demonstrate that the Josephson critical current may depend on the type and area of circuit elements connected to the junction, on the circuit pattern, and on the step in the fabrication process at which the connection is made. In particular, we discuss the influence of (a) the junction base electrode connection to the ground plane, (b) the junction counter electrode connection to the ground plane, and (c) the counter electrode connection to the Ti/Au or Ti/Pd/Au contact pads by Nb wiring. We show that the process-induced changes of the properties of Nb/Al/AlOx/Nb junctions are caused by migration of impurity atoms (hydrogen) between the different layers comprising the integrated circuits.

  14. Digital pixel readout integrated circuit architectures for LWIR

    OpenAIRE

    Shafique, Atia; Yazıcı, Melik; Yazici, Melik; Kayahan, Hüseyin; Kayahan, Huseyin; Ceylan, Ömer; Ceylan, Omer; Gürbüz, Yaşar; Gurbuz, Yasar

    2015-01-01

    This paper presents and discusses digital pixel readout integrated circuit architectures for long wavelength infrared (LWIR) in CMOS technology. Presented architectures are designed for scanning and staring arrays type detectors respectively. For scanning arrays, digital time delay integration (TDI) is implemented on 8 pixels with sampling rate up to 3 using CMOS 180nm technology. Input referred noise of ROIC is below 750 rms electron meanwhile power dissipation is appreciably under 30mW. ROI...

  15. Radio frequency integrated circuit design for cognitive radio systems

    CERN Document Server

    Fahim, Amr

    2015-01-01

    This book fills a disconnect in the literature between Cognitive Radio systems and a detailed account of the circuit implementation and architectures required to implement such systems.  Throughout the book, requirements and constraints imposed by cognitive radio systems are emphasized when discussing the circuit implementation details.  In addition, this book details several novel concepts that advance state-of-the-art cognitive radio systems.  This is a valuable reference for anybody with background in analog and radio frequency (RF) integrated circuit design, needing to learn more about integrated circuits requirements and implementation for cognitive radio systems. ·         Describes in detail cognitive radio systems, as well as the circuit implementation and architectures required to implement them; ·         Serves as an excellent reference to state-of-the-art wideband transceiver design; ·         Emphasizes practical requirements and constraints imposed by cognitive radi...

  16. Flexible circuits with integrated switches for robotic shape sensing

    Science.gov (United States)

    Harnett, C. K.

    2016-05-01

    Digital switches are commonly used for detecting surface contact and limb-position limits in robotics. The typical momentary-contact digital switch is a mechanical device made from metal springs, designed to connect with a rigid printed circuit board (PCB). However, flexible printed circuits are taking over from the rigid PCB in robotics because the circuits can bend while carrying signals and power through moving joints. This project is motivated by a previous work where an array of surface-mount momentary contact switches on a flexible circuit acted as an all-digital shape sensor compatible with the power resources of energy harvesting systems. Without a rigid segment, the smallest commercially-available surface-mount switches would detach from the flexible circuit after several bending cycles, sometimes violently. This report describes a low-cost, conductive fiber based method to integrate electromechanical switches into flexible circuits and other soft, bendable materials. Because the switches are digital (on/off), they differ from commercially-available continuous-valued bend/flex sensors. No amplification or analog-to-digital conversion is needed to read the signal, but the tradeoff is that the digital switches only give a threshold curvature value. Boundary conditions on the edges of the flexible circuit are key to setting the threshold curvature value for switching. This presentation will discuss threshold-setting, size scaling of the design, automation for inserting a digital switch into the flexible circuit fabrication process, and methods for reconstructing a shape from an array of digital switch states.

  17. The 128-channel fully differential digital integrated neural recording and stimulation interface.

    Science.gov (United States)

    Shahrokhi, Farzaneh; Abdelhalim, Karim; Serletis, Demitre; Carlen, Peter L; Genov, Roman

    2010-06-01

    We present a fully differential 128-channel integrated neural interface. It consists of an array of 8 X 16 low-power low-noise signal-recording and generation circuits for electrical neural activity monitoring and stimulation, respectively. The recording channel has two stages of signal amplification and conditioning with and a fully differential 8-b column-parallel successive approximation (SAR) analog-to-digital converter (ADC). The total measured power consumption of each recording channel, including the SAR ADC, is 15.5 ¿W. The measured input-referred noise is 6.08 ¿ Vrms over a 5-kHz bandwidth, resulting in a noise efficiency factor of 5.6. The stimulation channel performs monophasic or biphasic voltage-mode stimulation, with a maximum stimulation current of 5 mA and a quiescent power dissipation of 51.5 ¿W. The design is implemented in 0.35-¿m complementary metal-oxide semiconductor technology with the channel pitch of 200 ¿m for a total die size of 3.4 mm × 2.5 mm and a total power consumption of 9.33 mW. The neural interface was validated in in vitro recording of a low-Mg(2+)/high-K(+) epileptic seizure model in an intact hippocampus of a mouse. PMID:23853339

  18. Advances in Silicon Based Millimeter-Wave Monolithic Integrated Circuits

    Directory of Open Access Journals (Sweden)

    Han-Chih Yeh

    2014-12-01

    Full Text Available In this paper, the advances of the silicon-based millimeter-wave (MMW monolithic integrated circuits (MMICs are reported. The silicon-based technologies for MMW MMICs are briefly introduced. In addition, the current status of the MMW MMICs is surveyed and novel circuit topologies are summarized. Some representative MMW MMICs are illustrated as design examples in the categories of their functions in a MMW system. Finally, there is a conclusion and description of the future trend of the development of the MMW ICs.

  19. Modeling of single-event upset in bipolar integrated circuits

    Science.gov (United States)

    Zoutendyk, J. A.

    1983-01-01

    The results of work done on the quantitative characterization of single-event upset (SEU) in bipolar random-access memories (RAMs) have been obtained through computer simulation of SEU in RAM cells that contain circuit models for bipolar transistors. The models include current generators that emulate the charge collected from ion tracks. The computer simulation results are compared with test data obtained from a RAM in a bipolar microprocessor chip. This methodology is applicable to other bipolar integrated circuit constructions in addition to RAM cells.

  20. Digital integrated circuit design using Verilog and SystemVerilog

    CERN Document Server

    Mehler, Ronald W

    2014-01-01

    For those with a basic understanding of digital design, this book teaches the essential skills to design digital integrated circuits using Verilog and the relevant extensions of SystemVerilog. In addition to covering the syntax of Verilog and SystemVerilog, the author provides an appreciation of design challenges and solutions for producing working circuits. The book covers not only the syntax and limitations of HDL coding, but deals extensively with design problems such as partitioning and synchronization, helping you to produce designs that are not only logically correct, but will actually

  1. Flexible, High-Speed CdSe Nanocrystal Integrated Circuits.

    Science.gov (United States)

    Stinner, F Scott; Lai, Yuming; Straus, Daniel B; Diroll, Benjamin T; Kim, David K; Murray, Christopher B; Kagan, Cherie R

    2015-10-14

    We report large-area, flexible, high-speed analog and digital colloidal CdSe nanocrystal integrated circuits operating at low voltages. Using photolithography and a newly developed process to fabricate vertical interconnect access holes, we scale down device dimensions, reducing parasitic capacitances and increasing the frequency of circuit operation, and scale up device fabrication over 4 in. flexible substrates. We demonstrate amplifiers with ∼7 kHz bandwidth, ring oscillators with <10 μs stage delays, and NAND and NOR logic gates. PMID:26407206

  2. Classical Conditioning with Pulsed Integrated Neural Networks: Circuits and System

    DEFF Research Database (Denmark)

    Lehmann, Torsten

    1998-01-01

    In this paper we investigate on-chip learning for pulsed, integrated neural networks. We discuss the implementational problems the technology imposes on learning systems and we find that abiologically inspired approach using simple circuit structures is most likely to bring success. We develop a...... suitable learning algorithm -- a continuous-time version of a temporal differential Hebbian learning algorithm for pulsed neural systems with non-linear synapses -- as well as circuits for the electronic implementation. Measurements from an experimental CMOS chip are presented. Finally, we use our test...... chip to solve simple classical conditioning tasks, thus verifying the design methodologies put forward in the paper....

  3. Multi-Objective Optimization in Physical Synthesis of Integrated Circuits

    CERN Document Server

    A Papa, David

    2013-01-01

    This book introduces techniques that advance the capabilities and strength of modern software tools for physical synthesis, with the ultimate goal to improve the quality of leading-edge semiconductor products.  It provides a comprehensive introduction to physical synthesis and takes the reader methodically from first principles through state-of-the-art optimizations used in cutting edge industrial tools. It explains how to integrate chip optimizations in novel ways to create powerful circuit transformations that help satisfy performance requirements. Broadens the scope of physical synthesis optimization to include accurate transformations operating between the global and local scales; Integrates groups of related transformations to break circular dependencies and increase the number of circuit elements that can be jointly optimized to escape local minima;  Derives several multi-objective optimizations from first observations through complete algorithms and experiments; Describes integrated optimization te...

  4. Series-connected substrate-integrated lead-carbon hybrid ultracapacitors with voltage-management circuit

    Indian Academy of Sciences (India)

    A Banerjee; R Srinivasan; A K Shukla

    2015-02-01

    Cell voltage for a fully charged-substrate-integrated lead-carbon hybrid ultracapacitor is about 2.3 V. Therefore, for applications requiring higher DC voltage, several of these ultracapacitors need to be connected in series. However, voltage distribution across each series-connected ultracapacitor tends to be uneven due to tolerance in capacitance and parasitic parallel-resistance values. Accordingly, voltage-management circuit is required to protect constituent ultracapacitors from exceeding their rated voltage. In this study, the design and characterization of the substrate-integrated lead-carbon hybrid ultracapacitor with co-located terminals is discussed. Voltage-management circuit for the ultracapacitor is presented, and its effectiveness is validated experimentally.

  5. RF and microwave integrated circuit development technology, packaging and testing

    CERN Document Server

    Gamand, Patrice; Kelma, Christophe

    2017-01-01

    RF and Microwave Integrated Circuit Development bridges the gap between existing literature, which focus mainly on the 'front-end' part of a product development (system, architecture, design techniques), by providing the reader with an insight into the 'back-end' part of product development. In addition, the authors provide practical answers and solutions regarding the choice of technology, the packaging solutions and the effects on the performance on the circuit and to the industrial testing strategy. It will also discuss future trends and challenges and includes case studies to illustrate examples. * Offers an overview of the challenges in RF/microwave product design * Provides practical answers to packaging issues and evaluates its effect on the performance of the circuit * Includes industrial testing strategies * Examines relevant RF MIC technologies and the factors which affect the choice of technology for a particular application, e.g. technical performance and cost * Discusses future trends and challen...

  6. Short circuit analysis of distribution system with integration of DG

    DEFF Research Database (Denmark)

    Su, Chi; Liu, Zhou; Chen, Zhe;

    2014-01-01

    currents during both balanced and unbalanced faults. Major factors such as external grid short circuit power capacity, WT integration location, connection type of WT integration transformer are taken into account. In turn, the challenges brought to the protection system in the distribution network are...... a result bring challenges to the network protection system. This problem has been frequently discussed in the literature, but mostly considering only the balanced fault situation. This paper presents an investigation on the influence of full converter based wind turbine (WT) integration on fault...... presented as well. The results in this paper are based on mathematical analysis and simulation study in DIgSILENT PowerFactory....

  7. The two independent equations of circuits in integral form of field theory: The fundamental law of circuits

    Institute of Scientific and Technical Information of China (English)

    CHEN Shennian

    2005-01-01

    Circuit theory is an extremely important basic theory in electrical and electronic sciences and technologies. Over more than a century, researchers have come to the conclusion that a fundamental law of circuits needs to satisfy the following three conditions: (1) Independency. It must be able to solve independently the basic problems of general solutions to the distribution of current and voltage in circuits. (2)Fundamentality. It cannot be derived from circuit theory and it must be the starting point for the establishment of circuit theory; it deduces the problem relevant to circuit theory by using purely logical inference, and establishes circuit theory into an independent deductive system. (3) Applicability. It must be widely applicable to all spheres of circuits,which includes sinusoidal steady-state linear and nonlinear networks, non-sinusoidal steady-state linear and nonlinear networks, transient-state processes, etc. From all networks to which the fundamental law of circuits applies, sinusoidal steady-state linear network is chosen as the most basic one to demonstrate that the two independent equations of circuits in integral form derived from Maxwell equations are able to meet these three conditions. Consequently, it is believed to be the fundamental law of circuits newly recognized today. This paper also makes the initiative to establish a circuit theory by which the basic rules of electromagnetic field govern the circuits, and the unity of electromagnetic fields and circuits is achieved.

  8. Attachment method for stacked integrated circuit (IC) chips

    Science.gov (United States)

    Bernhardt, Anthony F.; Malba, Vincent

    1999-01-01

    An attachment method for stacked integrated circuit (IC) chips. The method involves connecting stacked chips, such as DRAM memory chips, to each other and/or to a circuit board. Pads on the individual chips are rerouted to form pads on the side of the chip, after which the chips are stacked on top of each other whereby desired interconnections to other chips or a circuit board can be accomplished via the side-located pads. The pads on the side of a chip are connected to metal lines on a flexible plastic tape (flex) by anisotropically conductive adhesive (ACA). Metal lines on the flex are likewise connected to other pads on chips and/or to pads on a circuit board. In the case of a stack of DRAM chips, pads to corresponding address lines on the various chips may be connected to the same metal line on the flex to form an address bus. This method has the advantage of reducing the number of connections required to be made to the circuit board due to bussing; the flex can accommodate dimensional variation in the alignment of chips in the stack; bonding of the ACA is accomplished at low temperature and is otherwise simpler and less expensive than solder bonding; chips can be bonded to the ACA all at once if the sides of the chips are substantially coplanar, as in the case for stacks of identical chips, such as DRAM.

  9. A fully integrated frequency synthesizer for a dual-mode GPS and Compass receiver

    International Nuclear Information System (INIS)

    This paper presents a fully integrated frequency synthesizer for a dual-mode GPS and Compass receiver fabricated in a 0.13 μm CMOS technology. The frequency synthesizer is implemented with an on-chip symmetric inductor and an on-chip loop filter. A capacitance multiplying approach is proposed in the on-chip loop filter design for area-saving consideration. Pulse-swallow topology with a multistage noise shaping ΔΣ modulator is adopted in the frequency divider design. The synthesizer generates local oscillating signals at 1571.328 MHz and 1568.259 MHz with a 16.368 MHz reference clock by working in integer and fractional modes. Measurement results show that the phase noise of the synthesizer achieves −91.3 dBc/Hz and −117 dBc/Hz out of band at 100 kHz and 1 MHz frequency offset, separately. The proposed frequency synthesizer consumes 8.6 mA from a 1.2 V power supply and occupies an area of 0.92 mm2. (semiconductor integrated circuits)

  10. A Fully Integrated Humidity Sensor System-on-Chip Fabricated by Micro-Stamping Technology

    Directory of Open Access Journals (Sweden)

    Chih-Ting Lin

    2012-08-01

    Full Text Available A fully integrated humidity sensor chip was designed, implemented, and tested. Utilizing the micro-stamping technology, the pseudo-3D sensor system-on-chip (SSoC architecture can be implemented by stacking sensing materials directly on the top of a CMOS-fabricated chip. The fabricated sensor system-on-chip (2.28 mm × 2.48 mm integrated a humidity sensor, an interface circuit, a digital controller, and an On-Off Keying (OOK wireless transceiver. With low power consumption, i.e., 750 μW without RF operation, the sensitivity of developed sensor chip was experimentally verified in the relative humidity (RH range from 32% to 60%. The response time of the chip was also experimentally verified to be within 5 seconds from RH 36% to RH 64%. As a consequence, the implemented humidity SSoC paves the way toward the an ultra-small sensor system for various applications.

  11. A fully integrated multi-standard frequency synthesizer for GNSS receivers with cellular network positioning capability

    International Nuclear Information System (INIS)

    A fully integrated hybrid integer/fractional frequency synthesizer is presented. With a single multiband voltage-controlled-oscillator (VCO), the frequency synthesizer can support GPS, Galileo, Compass and TD-SCDMA standards. Design is carefully performed to trade off power, die area and phase noise performance. By reconfiguring between the integer mode and fractional mode, different frequency resolution requirements and a constant loop bandwidth for each standard can be achieved simultaneously. Moreover, a long sequence length, reduced hardware complexity multi-stage-noise-shaping (MASH) Δ−Σ modulator is employed to reduce fractional spur in the fractional mode. Fabricated in a 0.18 μm CMOS technology, the frequency synthesizer occupies an active area of 1.48 mm2 and draws a current of 13.4–16.2 mA from a 1.8 V power supply. The measured phase noise is lower than −80 dBc/Hz at 100 kHz offset and −113 to −124 dBc/Hz at 1 MHz offset respectively, while the measured reference spur is −71 dBc in integer mode and the fractional spur is −65 dBc in fractional mode. (semiconductor integrated circuits)

  12. Fully integrated hybrid silicon free-space beam steering source with 32-channel phased array

    Science.gov (United States)

    Hulme, J. C.; Doylend, J. K.; Heck, M. J. R.; Peters, J. D.; Davenport, M. L.; Bovington, J. T.; Coldren, L. A.; Bowers, J. E.

    2014-03-01

    Free-space beam steering using optical phased arrays is a promising method for implementing free-space communication links and Light Detection and Ranging (LIDAR) without the sensitivity to inertial forces and long latencies which characterize moving parts. Implementing this approach on a silicon-based photonic integrated circuit adds the additional advantage of working with highly developed CMOS processing techniques. In this work we discuss our progress in the development of a fully integrated 32 channel PIC with a widely tunable diode laser, a waveguide phased array, an array of fast phase modulators, an array of hybrid III-V/silicon amplifiers, surface gratings, and a graded index lens (GRIN) feeding an array of photodiodes for feedback control. The PIC has been designed to provide beam steering across a 15°x5° field of view with 0.6°x0.6° beam width and background peaks suppressed 15 dB relative to the main lobe within the field of view for arbitrarily chosen beam directions. Fabrication follows the hybrid silicon process developed at UCSB with modifications to incorporate silicon diodes and a GRIN lens.

  13. Radiation Testing and Evaluation Issues for Modern Integrated Circuits

    Science.gov (United States)

    LaBel, Kenneth A.; Cohn, Lew M.

    2005-01-01

    Abstract. Changes in modern integrated circuit (IC) technologies have modified the way we approach and conduct radiation tolerance and testing of electronics. These changes include scaling of geometries, new materials, new packaging technologies, and overall speed and device complexity challenges. In this short course section, we will identify and discuss these issues as they impact radiation testing, modeling, and effects mitigation of modern integrated circuits. The focus will be on CMOS-based technologies, however, other high performance technologies will be discussed where appropriate. The effects of concern will be: Single-Event Effects (SEE) and steady state total ionizing dose (TID) IC response. However, due to the growing use of opto-electronics in space systems issues concerning displacement damage testing will also be considered. This short course section is not intended to provide detailed "how-to-test" information, but simply provide a snapshot of current challenges and some of the approaches being considered.

  14. Millimeter-wave and optoelectronic applications of heterostructure integrated circuits

    Science.gov (United States)

    Pavlidis, Dimitris

    1991-01-01

    The properties are reviewed of heterostructure devices for microwave-monolithic-integrated circuits (MMICs) and optoelectronic integrated circuits (OICs). Specific devices examined include lattice-matched and pseudomorphic InAlAs/InGaAs high-electron mobility transistors (HEMTs), mixer/multiplier diodes, and heterojunction bipolar transistors (HBTs) developed with a number of materials. MMICs are reviewed that can be employed for amplification, mixing, and signal generation, and receiver/transmitter applications are set forth for OICs based on GaAs and InP heterostructure designs. HEMTs, HBTs, and junction-FETs can be utilized in combination with PIN, MSM, and laser diodes to develop novel communication systems based on technologies that combine microwave and photonic capabilities.

  15. Total Dose Effects on Bipolar Integrated Circuits at Low Temperature

    Science.gov (United States)

    Johnston, A. H.; Swimm, R. T.; Thorbourn, D. O.

    2012-01-01

    Total dose damage in bipolar integrated circuits is investigated at low temperature, along with the temperature dependence of the electrical parameters of internal transistors. Bandgap narrowing causes the gain of npn transistors to decrease far more at low temperature compared to pnp transistors, due to the large difference in emitter doping concentration. When irradiations are done at temperatures of -140 deg C, no damage occurs until devices are warmed to temperatures above -50 deg C. After warm-up, subsequent cooling shows that damage is then present at low temperature. This can be explained by the very strong temperature dependence of dispersive transport in the continuous-time-random-walk model for hole transport. For linear integrated circuits, low temperature operation is affected by the strong temperature dependence of npn transistors along with the higher sensitivity of lateral and substrate pnp transistors to radiation damage.

  16. Neural Networks Integrated Circuit for Biomimetics MEMS Microrobot

    OpenAIRE

    Ken Saito; Kazuaki Maezumi; Yuka Naito; Tomohiro Hidaka; Kei Iwata; Yuki Okane; Hirozumi Oku; Minami Takato; Fumio Uchikoba

    2014-01-01

    In this paper, we will propose the neural networks integrated circuit (NNIC) which is the driving waveform generator of the 4.0, 2.7, 2.5 mm, width, length, height in size biomimetics microelectromechanical systems (MEMS) microrobot. The microrobot was made from silicon wafer fabricated by micro fabrication technology. The mechanical system of the robot was equipped with small size rotary type actuators, link mechanisms and six legs to realize the ant-like switching behavior. The NNIC generat...

  17. Plasmonic nanopatch array for optical integrated circuit applications

    OpenAIRE

    Shi-Wei Qu; Zai-Ping Nie

    2013-01-01

    Future plasmonic integrated circuits with the capability of extremely high-speed data processing at optical frequencies will be dominated by the efficient optical emission (excitation) from (of) plasmonic waveguides. Towards this goal, plasmonic nanoantennas, currently a hot topic in the field of plasmonics, have potential to bridge the mismatch between the wave vector of free-space photonics and that of the guided plasmonics. To manipulate light at will, plasmonic nanoantenna arrays will def...

  18. Bioimpedance Measurements Using the Integrated Circuit AD5933

    OpenAIRE

    2008-01-01

    This thesis gives a description of a prototype bioimpedance measurement system based on the integrated circuit AD5933. The prototype operates from 5 - 100 kHz and covers the impedance range 0.1k - 10 M in six subranges. The system is operated from a PC, and the software required for operation and control has been developed. Verification testing on R/C modules have shown that the calibration process and the signal level are critical issues with regard to operationa...

  19. Highly focused ion beams in integrated circuit testing

    International Nuclear Information System (INIS)

    The nuclear microprobe has proven to be a useful tool in radiation testing of integrated circuits. This paper reviews single event upset (SEU) and ion beam induced charge collection (IBICC) imaging techniques, with special attention to damage-dependent effects. Comparisons of IBICC measurements with three-dimensional charge transport simulations of charge collection are then presented for isolated p-channel field effect transistors under conducting and non-conducting bias conditions

  20. Optimization of Segmentation Quality of Integrated Circuit Images

    Directory of Open Access Journals (Sweden)

    Gintautas Mušketas

    2012-04-01

    Full Text Available The paper presents investigation into the application of genetic algorithms for the segmentation of the active regions of integrated circuit images. This article is dedicated to a theoretical examination of the applied methods (morphological dilation, erosion, hit-and-miss, threshold and describes genetic algorithms, image segmentation as optimization problem. The genetic optimization of the predefined filter sequence parameters is carried out. Improvement to segmentation accuracy using a non optimized filter sequence makes 6%.Artcile in Lithuanian

  1. Study of integrated circuits in natural space environment

    International Nuclear Information System (INIS)

    In this thesis we study one of the critical phenomena induced by the radiation of integrated circuits in the natural space environment: the so-called upset phenomenon. This phenomenon, caused by a heavy-ion strike on circuit sensitive areas, result in the modification of the information stored in a memory element. Upsets may then perturb the functioning of satellite-borne complex processors with serious consequences on the control of equipments operating in space. As commonly used processes or design hardening techniques cannot guarantee a total immunity against upsets, provisional methods are generally adopted to select the less sensitive circuits among components to be used in a space application. These methods consist in the simulation of the irradiated environment by means of particle accelerators, to get experimental figures about the upset sensitivity of the considered circuit, and the use of these measures to estimate the in orbit circuit vulnerability. To implement such experiments on different processor types, we have designed and developed a dedicated test system, the FUTE 16 tester. This tester has been used in several test experiments where irradiated environment was simulated by means of particle accelerators. The activity of the target circuit during the irradiation could have a great influence on the measured upset sensitivity. Generally used test sequences so-called ''register test'', consist on the initialization of accessible registers with known data, and the observation of their content after a given delay to detect errors due to upsets. The main goal of this thesis is to compare in orbit error rate estimations obtained with register tests, to those obtained with ''application like'' test sequences. Both kinds of test sequences have been used during heavy-ion test experiments performed on commercially available CISC and RISC processors. The results obtained clearly show that using ''register tests'' may lead to wrong decisions in the selections

  2. Reconfigurable SDM Switching Using Novel Silicon Photonic Integrated Circuit

    CERN Document Server

    Ding, Yunhong; Dalgaard, Kjeld; Ye, Feihong; Asif, Rameez; Gross, Simon; Withford, Michael J; Galili, Michael; Morioka, Toshio; Oxenlowe, Leif Katsuo

    2016-01-01

    Space division multiplexing using multicore fibers is becoming a more and more promising technology. In space-division multiplexing fiber network, the reconfigurable switch is one of the most critical components in network nodes. In this paper we for the first time demonstrate reconfigurable space-division multiplexing switching using silicon photonic integrated circuit, which is fabricated on a novel silicon-on-insulator platform with buried Al mirror. The silicon photonic integrated circuit is composed of a 7x7 switch and low loss grating coupler array based multicore fiber couplers. Thanks to the Al mirror, grating couplers with ultra-low coupling loss with optical multicore fibers is achieved. The lowest total insertion loss of the silicon integrated circuit is as low as 4.5 dB, with low crosstalk lower than -30 dB. Excellent performances in terms of low insertion loss and low crosstalk are obtained for the whole C-band. 1 Tb/s/core transmission over a 2-km 7-core fiber and space-division multiplexing swi...

  3. A Integrated Circuit for a Biomedical Capacitive Pressure Transducer

    Science.gov (United States)

    Smith, Michael John Sebastian

    Medical research has an urgent need for a small, accurate, stable, low-power, biocompatible and inexpensive pressure sensor with a zero to full-scale range of 0-300 mmHg. An integrated circuit (IC) for use with a capacitive pressure transducer was designed, built and tested. The random pressure measurement error due to resolution and non-linearity is (+OR-)0.4 mmHg (at mid-range with a full -scale of 300 mmHg). The long-term systematic error due to falling battery voltage is (+OR-)0.6 mmHg. These figures were calculated from measurements of temperature, supply dependence and non-linearity on completed integrated circuits. The sensor IC allows measurement of temperature to (+OR-)0.1(DEGREES)C to allow for temperature compensation of the transducer. Novel micropower circuit design of the system components enabled these levels of accuracy to be reached. Capacitance is measured by a new ratiometric scheme employing an on -chip reference capacitor. This method greatly reduces the effects of voltage supply, temperature and manufacturing variations on the sensor circuit performance. The limits on performance of the bandgap reference circuit fabricated with a standard bipolar process using ion-implanted resistors were determined. Measurements confirm the limits of temperature stability as approximately (+OR-)300 ppm/(DEGREES)C. An exact analytical expression for the period of the Schmitt trigger oscillator, accounting for non-constant capacitor charging current, was formulated. Experiments to test agreement with theory showed that prediction of the oscillator period was very accurate. The interaction of fundamental and practical limits on the scaling of the transducer size was investigated including a correction to previous theoretical analysis of jitter in an RC oscillator. An areal reduction of 4 times should be achievable.

  4. The integrated circuit IC EMP transient state disturbance effect experiment method investigates

    International Nuclear Information System (INIS)

    Transient state disturbance characteristic study on the integrated circuit, IC, need from its coupling path outset. Through cable (aerial) coupling, EMP converts to an pulse current voltage and results in the impact to the integrated circuit I/O orifice passing the cable. Aiming at the armament system construction feature, EMP effect to the integrated circuit, IC inside the system is analyzed. The integrated circuit, IC EMP effect experiment current injection method is investigated and a few experiments method is given. (authors)

  5. Arbitrary modeling of TSVs for 3D integrated circuits

    CERN Document Server

    Salah, Khaled; El-Rouby, Alaa

    2014-01-01

    This book presents a wide-band and technology independent, SPICE-compatible RLC model for through-silicon vias (TSVs) in 3D integrated circuits. This model accounts for a variety of effects, including skin effect, depletion capacitance and nearby contact effects. Readers will benefit from in-depth coverage of concepts and technology such as 3D integration, Macro modeling, dimensional analysis and compact modeling, as well as closed form equations for the through silicon via parasitics. Concepts covered are demonstrated by using TSVs in applications such as a spiral inductor?and inductive-based

  6. Diamond electro-optomechanical resonators integrated in nanophotonic circuits

    International Nuclear Information System (INIS)

    Diamond integrated photonic devices are promising candidates for emerging applications in nanophotonics and quantum optics. Here, we demonstrate active modulation of diamond nanophotonic circuits by exploiting mechanical degrees of freedom in free-standing diamond electro-optomechanical resonators. We obtain high quality factors up to 9600, allowing us to read out the driven nanomechanical response with integrated optical interferometers with high sensitivity. We are able to excite higher order mechanical modes up to 115 MHz and observe the nanomechanical response also under ambient conditions

  7. Neuromorphic opto-electronic integrated circuits for optical signal processing

    Science.gov (United States)

    Romeira, B.; Javaloyes, J.; Balle, S.; Piro, O.; Avó, R.; Figueiredo, J. M. L.

    2014-08-01

    The ability to produce narrow optical pulses has been extensively investigated in laser systems with promising applications in photonics such as clock recovery, pulse reshaping, and recently in photonics artificial neural networks using spiking signal processing. Here, we investigate a neuromorphic opto-electronic integrated circuit (NOEIC) comprising a semiconductor laser driven by a resonant tunneling diode (RTD) photo-detector operating at telecommunication (1550 nm) wavelengths capable of excitable spiking signal generation in response to optical and electrical control signals. The RTD-NOEIC mimics biologically inspired neuronal phenomena and possesses high-speed response and potential for monolithic integration for optical signal processing applications.

  8. 75 FR 43553 - In the Matter of Certain Encapsulated Integrated Circuit Devices and Products Containing Same...

    Science.gov (United States)

    2010-07-26

    ... COMMISSION In the Matter of Certain Encapsulated Integrated Circuit Devices and Products Containing Same..., and sale within the United States after importation of certain encapsulated integrated circuit devices... encapsulated integrated circuit devices and products contains same in connection with claims 1- 4, 7, 17,...

  9. FDTD-SPICE for Characterizing Metamaterials Integrated with Electronic Circuits

    Directory of Open Access Journals (Sweden)

    Zhengwei Hao

    2012-01-01

    Full Text Available A powerful time-domain FDTD-SPICE simulator is implemented and applied to the broadband analysis of metamaterials integrated with active and tunable circuit elements. First, the FDTD-SPICE modeling theory is studied and details of interprocess communication and hybridization of the two techniques are discussed. To verify the model, some simple cases are simulated with results in both time domain and frequency domain. Then, simulation of a metamaterial structure constructed from periodic resonant loops integrated with lumped capacitor elements is studied, which demonstrates tuning resonance frequency of medium by changing the capacitance of the integrated elements. To increase the bandwidth of the metamaterial, non-Foster transistor configurations are integrated with the loops and FDTD-SPICE is applied to successfully bridge the physics of electromagnetic and circuit topologies and to model the whole composite structure. Our model is also applied to the design and simulation of a metasurface integrated with nonlinear varactors featuring tunable reflection phase characteristic.

  10. Universal discrete Fourier optics RF photonic integrated circuit architecture.

    Science.gov (United States)

    Hall, Trevor J; Hasan, Mehedi

    2016-04-01

    This paper describes a coherent electro-optic circuit architecture that generates a frequency comb consisting of N spatially separated orders using a generalised Mach-Zenhder interferometer (MZI) with its N × 1 combiner replaced by an optical N × N Discrete Fourier Transform (DFT). Advantage may be taken of the tight optical path-length control, component and circuit symmetries and emerging trimming algorithms offered by photonic integration in any platform that offers linear electro-optic phase modulation such as LiNbO3, silicon, III-V or hybrid technology. The circuit architecture subsumes all MZI-based RF photonic circuit architectures in the prior art given an appropriate choice of output port(s) and dimension N although the principal application envisaged is phase correlated subcarrier generation for all optical orthogonal frequency division multiplexing. A transfer matrix approach is used to model the operation of the architecture. The predictions of the model are validated by simulations performed using an industry standard software tool. Implementation is found to be practical. PMID:27137048

  11. Hardware-Efficient and Fully Autonomous Quantum Error Correction in Superconducting Circuits

    Science.gov (United States)

    Kapit, Eliot

    2016-04-01

    Superconducting qubits are among the most promising platforms for building a quantum computer. However, individual qubit coherence times are not far past the scalability threshold for quantum error correction, meaning that millions of physical devices would be required to construct a useful quantum computer. Consequently, further increases in coherence time are very desirable. In this Letter, we blueprint a simple circuit consisting of two transmon qubits and two additional lossy qubits or resonators, which is passively protected against all single-qubit quantum error channels through a combination of continuous driving and engineered dissipation. Photon losses are rapidly corrected through two-photon drive fields implemented with driven superconducting quantum interference device couplings, and dephasing from random potential fluctuations is heavily suppressed by the drive fields used to implement the multiqubit Hamiltonian. Comparing our theoretical model to published noise estimates from recent experiments on flux and transmon qubits, we find that logical state coherence could be improved by a factor of 40 or more compared to the individual qubit T1 and T2 using this technique. We thus demonstrate that there is substantial headroom for improving the coherence of modern superconducting qubits with a fairly modest increase in device complexity.

  12. An approach towards fully integration of CAD and CAM technologies

    OpenAIRE

    M. Tolouei-Rad

    2006-01-01

    Purpose: An integrated CAD/CAM system for milling operations has been developed which helps designers tosolve machining problems at the design stage.Design/methodology/approach: A methodology has been employed which provides all necessary informationfor machining products automatically. Use of these system results in reduced machining leadtimes and costthrough designing machinable components; using available cutting tools; improving machining efficiency. Thesystem is menu driven with a user f...

  13. ERP Systems - Fully Integrated Solution or a Transactional Platform?

    OpenAIRE

    Sandberg, Johan

    2008-01-01

    This paper addresses the question of how to make use of Enterprise Resource Planning (ERP) systems in companies in the process industry were there is a pervasive need of process standardization. ERP systems have the potential to contribute with standardization and integration of organizational data through an of-the-shelf solution. In practice results of ERP systems implementation has varied greatly. Considering their implications on business processes and the complexity of the systems this s...

  14. Fully integrated safeguards and security for reprocessing plant monitoring.

    Energy Technology Data Exchange (ETDEWEB)

    Duran, Felicia Angelica; Ward, Rebecca; Cipiti, Benjamin B.; Middleton, Bobby D.

    2011-10-01

    Nuclear fuel reprocessing plants contain a wealth of plant monitoring data including material measurements, process monitoring, administrative procedures, and physical protection elements. Future facilities are moving in the direction of highly-integrated plant monitoring systems that make efficient use of the plant data to improve monitoring and reduce costs. The Separations and Safeguards Performance Model (SSPM) is an analysis tool that is used for modeling advanced monitoring systems and to determine system response under diversion scenarios. This report both describes the architecture for such a future monitoring system and present results under various diversion scenarios. Improvements made in the past year include the development of statistical tests for detecting material loss, the integration of material balance alarms to improve physical protection, and the integration of administrative procedures. The SSPM has been used to demonstrate how advanced instrumentation (as developed in the Material Protection, Accounting, and Control Technologies campaign) can benefit the overall safeguards system as well as how all instrumentation is tied into the physical protection system. This concept has the potential to greatly improve the probability of detection for both abrupt and protracted diversion of nuclear material.

  15. Design automation for integrated nonlinear logic circuits (Conference Presentation)

    Science.gov (United States)

    Van Vaerenbergh, Thomas; Pelc, Jason; Santori, Charles; Bose, Ranojoy; Kielpinski, Dave; Beausoleil, Raymond G.

    2016-05-01

    A key enabler of the IT revolution of the late 20th century was the development of electronic design automation (EDA) tools allowing engineers to manage the complexity of electronic circuits with transistor counts now reaching into the billions. Recently, we have been developing large-scale nonlinear photonic integrated logic circuits for next generation all-optical information processing. At this time a sufficiently powerful EDA-style software tool chain to design this type of complex circuits does not yet exist. Here we describe a hierarchical approach to automating the design and validation of photonic integrated circuits, which can scale to several orders of magnitude higher complexity than the state of the art. Most photonic integrated circuits developed today consist of a small number of components, and only limited hierarchy. For example, a simple photonic transceiver may contain on the order of 10 building-block components, consisting of grating couplers for photonic I/O, modulators, and signal splitters/combiners. Because this is relatively easy to lay out by hand (or simple script) existing photonic design tools have relatively little automation in comparison to electronics tools. But demonstrating all-optical logic will require significantly more complex photonic circuits containing up to 1,000 components, hence becoming infeasible to design manually. Our design framework is based off Python-based software from Luceda Photonics which provides an environment to describe components, simulate their behavior, and export design files (GDS) to foundries for fabrication. At a fundamental level, a photonic component is described as a parametric cell (PCell) similarly to electronics design. PCells are described by geometric characteristics of their layout. A critical part of the design framework is the implementation of PCells as Python objects. PCell objects can then use inheritance to simplify design, and hierarchical designs can be made by creating composite

  16. Design and implementation of a high sensitivity fully integrated passive UHF RFID tag

    Science.gov (United States)

    Shoucheng, Li; Xin'an, Wang; Ke, Lin; Jinpeng, Shen; Jinhai, Zhang

    2014-10-01

    A fully integrated passive UHF RFID tag complying with the ISO18000-6B protocol is presented, which includes an analog front-end, a baseband processor, and an EEPROM memory. To extend the communication range, a high efficiency differential-drive CMOS rectifier is adopted. A novel high performance voltage limiter is used to provide a stable limiting voltage, with a 172 mV voltage variation against temperature variation and process dispersion. The dynamic band-enhancement technique is used in the regulator circuit to improve the regulating capacity. A rail-to-rail hysteresis comparator is adopted to demodulate the signal correctly in any condition. The whole transponder chip is implemented in a 0.18 μm CMOS process, with a die size of 900 × 800 μm2. Our measurement results show that the total power consumption of the tag chip is only 6.8 μW, with a sensitivity of -13.5 dBm

  17. Wireless programmable electrochemical drug delivery micropump with fully integrated electrochemical dosing sensors.

    Science.gov (United States)

    Sheybani, Roya; Cobo, Angelica; Meng, Ellis

    2015-08-01

    We present a fully integrated implantable electrolysis-based micropump with incorporated EI dosing sensors. Wireless powering and data telemetry (through amplitude and frequency modulation) were utilized to achieve variable flow control and a bi-directional data link with the sensors. Wireless infusion rate control (0.14-1.04 μL/min) and dose sensing (bolus resolution of 0.55-2 μL) were each calibrated separately with the final circuit architecture and then simultaneous wireless flow control and dose sensing were demonstrated. Recombination detection using the dosing system, as well as, effects of coil separation distance and misalignment in wireless power and data transfer were studied. A custom-made normally closed spring-loaded ball check valve was designed and incorporated at the reservoir outlet to prevent backflow of fluids as a result of the reverse pressure gradient caused by recombination of electrolysis gases. Successful delivery, infusion rate control, and dose sensing were achieved in simulated brain tissue. PMID:26149696

  18. InP-based three-dimensional photonic integrated circuits

    Science.gov (United States)

    Tsou, Diana; Zaytsev, Sergey; Pauchard, Alexandre; Hummel, Steve; Lo, Yu-Hwa

    2001-10-01

    Fast-growing internet traffic volumes require high data communication bandwidth over longer distances than short wavelength (850 nm) multi-mode fiber systems can provide. Access network bottlenecks put pressure on short-range (SR) telecommunication systems. To effectively address these datacom and telecom market needs, low cost, high-speed laser modules at 1310 and 1550 nm wavelengths are required. The great success of GaAs 850 nm VCSELs for Gb/s Ethernet has motivated efforts to extend VCSEL technology to longer wavelengths in the 1310 and 1550 nm regimes. However, the technological challenges associated with available intrinsic materials for long wavelength VCSELs are tremendous. Even with recent advances in this area, it is believed that significant additional development is necessary before long wavelength VCSELs that meet commercial specifications will be widely available. In addition, the more stringent OC192 and OC768 specifications for single-mode fiber (SMF) datacom may require more than just a long wavelength laser diode, VCSEL or not, to address numerous cost and performance issues. We believe that photonic integrated circuits, which compactly integrate surface-emitting lasers with additional active and passive optical components with extended functionality, will provide the best solutions to today's problems. Photonic integrated circuits (PICs) have been investigated for more than a decade. However, they have produced limited commercial impact to date primarily because the highly complicated fabrication processes produce significant yield and device performance issues. In this presentation, we will discuss a new technology platform for fabricating InP-based photonic integrated circuits compatible with surface-emitting laser technology. Employing InP transparency at 1310 and 1550 nm wavelengths, we have created 3-D photonic integrated circuits (PICs) by utilizing light beams in both surface normal and in-plane directions within the InP-based structure

  19. Millimeter wave planar integrated circuit developments for communication applications

    Science.gov (United States)

    Chang, K.; Sun, C.

    Millimeter wave communication systems offer certain advantages over lower frequency systems. These advantages are related to wider bandwidth, larger data handling capacity, covert operation, and better immunity to jamming. Newer developments in the area of component technology for systems operating at millimeter wavelengths have utilized planar integrated circuits. Such circuits provide benefits of light weight, small size, and inherent low cost due to ease of high volume manufacturing. The present paper is concerned with a number of key IC components which have been developed. These components are ideally suited for direct application in advanced tactical, radar, and satellite communication systems. Attention is given to a rat-race microstrip balanced mixer, a crossbar stripline balanced mixer, and various subsystems developments.

  20. Mnemonic Functions for Nonlinear Dendritic Integration in Hippocampal Pyramidal Circuits.

    Science.gov (United States)

    Kaifosh, Patrick; Losonczy, Attila

    2016-05-01

    We present a model for neural circuit mechanisms underlying hippocampal memory. Central to this model are nonlinear interactions between anatomically and functionally segregated inputs onto dendrites of pyramidal cells in hippocampal areas CA3 and CA1. We study the consequences of such interactions using model neurons in which somatic burst-firing and synaptic plasticity are controlled by conjunctive processing of these separately integrated input pathways. We find that nonlinear dendritic input processing enhances the model's capacity to store and retrieve large numbers of similar memories. During memory encoding, CA3 stores heavily decorrelated engrams to prevent interference between similar memories, while CA1 pairs these engrams with information-rich memory representations that will later provide meaningful output signals during memory recall. While maintaining mathematical tractability, this model brings theoretical study of memory operations closer to the hippocampal circuit's anatomical and physiological properties, thus providing a framework for future experimental and theoretical study of hippocampal function. PMID:27146266

  1. Monocrystalline silicon used for integrated circuits: still on the way

    Institute of Scientific and Technical Information of China (English)

    Jia-he CHEN; De-ren YANG; Duan-lin QUE

    2008-01-01

    With the rapid development of semiconductor technology, highly integrated circuits (ICs) and future nano-scale devices require large diameter and defect-free monocrystalline silicon wafers. The ongoing innovation from silicon materials is one of the driving forces in future micro and nano-technologies. In this work, the recent developments in the controlling of large diameter silicon crystal growth processes, the improvement of material features by co-doping with the intend-introduced impur-ities, and the progress of defect engineered silicon wafers (epitaxial silicon wafer, strained silicon, silicon on insu-lator) are reviewed. It is proposed that the silicon man-ufacturing infrastructure could still meet the increasingly stringent requirements arising from ULSI circuits and will expand Moore's law into a couple of decades.

  2. Synthetic circuits integrating logic and memory in living cells.

    Science.gov (United States)

    Siuti, Piro; Yazbek, John; Lu, Timothy K

    2013-05-01

    Logic and memory are essential functions of circuits that generate complex, state-dependent responses. Here we describe a strategy for efficiently assembling synthetic genetic circuits that use recombinases to implement Boolean logic functions with stable DNA-encoded memory of events. Application of this strategy allowed us to create all 16 two-input Boolean logic functions in living Escherichia coli cells without requiring cascades comprising multiple logic gates. We demonstrate long-term maintenance of memory for at least 90 cell generations and the ability to interrogate the states of these synthetic devices with fluorescent reporters and PCR. Using this approach we created two-bit digital-to-analog converters, which should be useful in biotechnology applications for encoding multiple stable gene expression outputs using transient inputs of inducers. We envision that this integrated logic and memory system will enable the implementation of complex cellular state machines, behaviors and pathways for therapeutic, diagnostic and basic science applications. PMID:23396014

  3. Advances in integrated photonic circuits for packet-switched interconnection

    Science.gov (United States)

    Williams, Kevin A.; Stabile, Ripalta

    2014-03-01

    Sustained increases in capacity and connectivity are needed to overcome congestion in a range of broadband communication network nodes. Packet routing and switching in the electronic domain are leading to unsustainable energy- and bandwidth-densities, motivating research into hybrid solutions: optical switching engines are introduced for massive-bandwidth data transport while the electronic domain is clocked at more modest GHz rates to manage routing. Commercially-deployed optical switching engines using MEMS technologies are unwieldy and too slow to reconfigure for future packet-based networking. Optoelectronic packet-compliant switch technologies have been demonstrated as laboratory prototypes, but they have so far mostly used discretely pigtailed components, which are impractical for control plane development and product assembly. Integrated photonics has long held the promise of reduced hardware complexity and may be the critical step towards packet-compliant optical switching engines. Recently a number of laboratories world-wide have prototyped optical switching circuits using monolithic integration technology with up to several hundreds of integrated optical components per chip. Our own work has focused on multi-input to multi-output switching matrices. Recently we have demonstrated 8×8×8λ space and wavelength selective switches using gated cyclic routers and 16×16 broadband switching chips using monolithic multi-stage networks. We now operate these advanced circuits with custom control planes implemented with FPGAs to explore real time packet routing in multi-wavelength, multi-port test-beds. We review our contributions in the context of state of the art photonic integrated circuit technology and packet optical switching hardware demonstrations.

  4. Network of fully integrated multispecialty hospital imaging systems

    Science.gov (United States)

    Dayhoff, Ruth E.; Kuzmak, Peter M.

    1994-05-01

    The Department of Veterans Affairs (VA) DHCP Imaging System records clinically significant diagnostic images selected by medical specialists in a variety of departments, including radiology, cardiology, gastroenterology, pathology, dermatology, hematology, surgery, podiatry, dental clinic, and emergency room. These images are displayed on workstations located throughout a medical center. All images are managed by the VA's hospital information system, allowing integrated displays of text and image data across medical specialties. Clinicians can view screens of `thumbnail' images for all studies or procedures performed on a selected patient. Two VA medical centers currently have DHCP Imaging Systems installed, and others are planned. All VA medical centers and other VA facilities are connected by a wide area packet-switched network. The VA's electronic mail software has been modified to allow inclusion of binary data such as images in addition to the traditional text data. Testing of this multimedia electronic mail system is underway for medical teleconsultation.

  5. High speed integrated circuit technology towards 100 GHz logic

    CERN Document Server

    Rodwell, Mark

    2001-01-01

    This book reviews the state of the art of very high speed digital integrated circuits. Commercial applications are in fiber optic transmission systems operating at 10, 40, and 100 Gb/s, while the military application is ADCs and DACs for microwave radar. The book contains detailed descriptions of the design, fabrication, and performance of wideband Si/SiGe-, GaAs-, and InP-based bipolar transistors. The analysis, design, and performance of high speed CMOS, silicon bipolar, and III-V digital ICs are presented in detail, with emphasis on application in optical fiber transmission and mixed signal

  6. Integrated circuit authentication hardware Trojans and counterfeit detection

    CERN Document Server

    Tehranipoor, Mohammad; Zhang, Xuehui

    2013-01-01

    This book describes techniques to verify the authenticity of integrated circuits (ICs). It focuses on hardware Trojan detection and prevention and counterfeit detection and prevention. The authors discuss a variety of detection schemes and design methodologies for improving Trojan detection techniques, as well as various attempts at developing hardware Trojans in IP cores and ICs. While describing existing Trojan detection methods, the authors also analyze their effectiveness in disclosing various types of Trojans, and demonstrate several architecture-level solutions. 

  7. Inspection of integrated circuits through the microfocus radiography technique

    International Nuclear Information System (INIS)

    The application of microfocus radiography technique for integrated circuits inspection is evaluated. The experiments were performed according to the international standards for micro-electronic components. In order to define the operational parameters, factors such as contrast and image definition were considered, and by varying the voltage and amperage applied to the X-ray apparatus it was tried to obtain radiographic images with an adequate resolution. the results show that this technique is a promising tool for evaluating these components. 17 refs., 16 figs., 2 tabs

  8. Fabrication Of High-Tc Superconducting Integrated Circuits

    Science.gov (United States)

    Bhasin, Kul B.; Warner, Joseph D.

    1992-01-01

    Microwave ring resonator fabricated to demonstrate process for fabrication of passive integrated circuits containing high-transition-temperature superconductors. Superconductors increase efficiencies of communication systems, particularly microwave communication systems, by reducing ohmic losses and dispersion of signals. Used to reduce sizes and masses and increase aiming accuracies and tracking speeds of millimeter-wavelength, electronically steerable antennas. High-Tc superconductors preferable for such applications because they operate at higher temperatures than low-Tc superconductors do, therefore, refrigeration systems needed to maintain superconductivity designed smaller and lighter and to consume less power.

  9. A novel voltage output integrated circuit temperature sensor

    Institute of Scientific and Technical Information of China (English)

    吴晓波; 方志刚; 等

    2002-01-01

    The novel integrated circuit(IC) temperature sensor presented in this paper works similarly as a two-terminal Zener,has breakdown voltage directly proportional to Kelvin temperature at 10mV/℃,with typical error of less tha ±1.0℃ over a temperature range from-50℃to +120℃ .In addition to all the features that conventional IC temperature sensors have,the new device also has very low static power dissipation(0.5mW),low output impedance(less than 1Ω),execllent stability,high reproducibility,and high precision.The sensor's circuit design and layout are discussed in detail.Applications of the sensor include almost and type of temperature sensing over the range of -50℃-+125℃。The low impedance and linear output of the device make interfacing the readout or control circuitry especially easy.Due to the excellent performance and low cost of this sensor.more application of the sensor over wide temperature range are expected.

  10. Chemistry integrated circuit: chemical system on a complementary metal oxide semiconductor integrated circuit.

    Science.gov (United States)

    Nakazato, Kazuo

    2014-03-28

    By integrating chemical reactions on a large-scale integration (LSI) chip, new types of device can be created. For biomedical applications, monolithically integrated sensor arrays for potentiometric, amperometric and impedimetric sensing of biomolecules have been developed. The potentiometric sensor array detects pH and redox reaction as a statistical distribution of fluctuations in time and space. For the amperometric sensor array, a microelectrode structure for measuring multiple currents at high speed has been proposed. The impedimetric sensor array is designed to measure impedance up to 10 MHz. The multimodal sensor array will enable synthetic analysis and make it possible to standardize biosensor chips. Another approach is to create new functional devices by integrating molecular systems with LSI chips, for example image sensors that incorporate biological materials with a sensor array. The quantum yield of the photoelectric conversion of photosynthesis is 100%, which is extremely difficult to achieve by artificial means. In a recently developed process, a molecular wire is plugged directly into a biological photosynthetic system to efficiently conduct electrons to a gold electrode. A single photon can be detected at room temperature using such a system combined with a molecular single-electron transistor. PMID:24567475

  11. Design and application of multilayer monolithic microwave integrated circuit transformers

    International Nuclear Information System (INIS)

    standard foundry processes. With careful modelling it is also feasible to integrate the two couplers into a single tri-filar transformer structure. This is a robust balun topology, which could be widely adopted. A push-pull MESFET amplifier with 8 dB gain demonstrated this at 12 GHz, using the balun chips connected to amplifier circuits. (author)

  12. Intelligent switches of integrated lightwave circuits with core telecommunication functions

    Science.gov (United States)

    Izhaky, Nahum; Duer, Reuven; Berns, Neil; Tal, Eran; Vinikman, Shirly; Schoenwald, Jeffrey S.; Shani, Yosi

    2001-05-01

    We present a brief overview of a promising switching technology based on Silica on Silicon thermo-optic integrated circuits. This is basically a 2D solid-state optical device capable of non-blocking switching operation. Except of its excellent performance (insertion lossmarket segments appropriate for the switch size and technology, followed by a discussion of the basic features of the technology. The discussion is focused on important requirements from the switch and the technology (e.g., insertion loss, power consumption, channel isolation, extinction ratio, switching time, and heat dissipation). The mechanical design is also considered. It must take into account integration of optical fiber, optical planar wafer, analog electronics and digital microprocessor controls, embedded software, and heating power dissipation. The Lynx Photon.8x8 switch is compared to competing technologies, in terms of typical market performance requirements.

  13. Mixed signal custom integrated circuit development for physics instrumentation

    International Nuclear Information System (INIS)

    The Monolithic Systems Development Group at the Oak Ridge National Laboratory has been greatly involved in custom mixed-mode integrated circuit development for the PHENIX detector at the Relativistic Heavy Ion collider (RHIC) at Brookhaven National Laboratory and position-sensitive germanium spectrometer front-ends for the Naval Research Laboratory (NRL). This paper will outline the work done for both PHENIX and the Naval Research Laboratory in the area of full-custom, mixed-signal CMOS integrated electronics. This paper presents the architectures chosen for the various PHENIX detectors which include position-sensitive silicon, capacitive pixel, and phototube detectors, and performance results for the subsystems as well as a system description of the NRL germanium strip system and its performance. The performance of the custom preamplifiers, discriminators, analog memories, analog-digital converters, and control circuitry for all systems will be presented

  14. Integrated optoelectronic materials and circuits for optical interconnects

    International Nuclear Information System (INIS)

    Conventional interconnect and switching technology is rapidly becoming a critical issue in the realization of systems using high speed silicon and GaAs based technologies. In recent years clock speeds and on-chip density for VLSI/VHSIC technology has made packaging these high speed chips extremely difficult. A strong case can be made for using optical interconnects for on-chip/on-wafer, chip-to-chip and board-to-board high speed communications. GaAs integrated optoelectronic circuits (IOC's) are being developed in a number of laboratories for performing Input/Output functions at all levels. In this paper integrated optoelectronic materials, electronics and optoelectronic devices are presented. IOC's are examined from the standpoint of what it takes to fabricate the devices and what performance can be expected

  15. Flexible high-performance carbon nanotube integrated circuits.

    Science.gov (United States)

    Sun, Dong-ming; Timmermans, Marina Y; Tian, Ying; Nasibulin, Albert G; Kauppinen, Esko I; Kishimoto, Shigeru; Mizutani, Takashi; Ohno, Yutaka

    2011-03-01

    Carbon nanotube thin-film transistors are expected to enable the fabrication of high-performance, flexible and transparent devices using relatively simple techniques. However, as-grown nanotube networks usually contain both metallic and semiconducting nanotubes, which leads to a trade-off between charge-carrier mobility (which increases with greater metallic tube content) and on/off ratio (which decreases). Many approaches to separating metallic nanotubes from semiconducting nanotubes have been investigated, but most lead to contamination and shortening of the nanotubes, thus reducing performance. Here, we report the fabrication of high-performance thin-film transistors and integrated circuits on flexible and transparent substrates using floating-catalyst chemical vapour deposition followed by a simple gas-phase filtration and transfer process. The resulting nanotube network has a well-controlled density and a unique morphology, consisting of long (~10 µm) nanotubes connected by low-resistance Y-shaped junctions. The transistors simultaneously demonstrate a mobility of 35 cm(2) V(-1) s(-1) and an on/off ratio of 6 × 10(6). We also demonstrate flexible integrated circuits, including a 21-stage ring oscillator and master-slave delay flip-flops that are capable of sequential logic. Our fabrication procedure should prove to be scalable, for example, by using high-throughput printing techniques. PMID:21297625

  16. Electronic-photonic integrated circuits on the CMOS platform

    Science.gov (United States)

    Kimerling, L. C.; Ahn, D.; Apsel, A. B.; Beals, M.; Carothers, D.; Chen, Y.-K.; Conway, T.; Gill, D. M.; Grove, M.; Hong, C.-Y.; Lipson, M.; Liu, J.; Michel, J.; Pan, D.; Patel, S. S.; Pomerene, A. T.; Rasras, M.; Sparacin, D. K.; Tu, K.-Y.; White, A. E.; Wong, C. W.

    2006-02-01

    The optical components industry stands at the threshold of a major expansion that will restructure its business processes and sustain its profitability for the next three decades. This growth will establish a cost effective platform for the partitioning of electronic and photonic functionality to extend the processing power of integrated circuits. BAE Systems, Lucent Technologies, Massachusetts Institute of Technology, and Applied Wave Research are participating in a high payoff research and development program for the Microsystems Technology Office (MTO) of DARPA. The goal of the program is the development of technologies and design tools necessary to fabricate an application-specific, electronicphotonic integrated circuit (AS-EPIC). As part of the development of this demonstration platform we are exploring selected functions normally associated with the front end of mixed signal receivers such as modulation, detection, and filtering. The chip will be fabricated in the BAE Systems CMOS foundry and at MIT's Microphotonics Center. We will present the latest results on the performance of multi-layer deposited High Index Contrast Waveguides, CMOS compatible modulators and detectors, and optical filter slices. These advances will be discussed in the context of the Communications Technology Roadmap that was recently released by the MIT Microphotonics Center Industry Consortium.

  17. Graphene/Si CMOS Hybrid Hall Integrated Circuits

    Science.gov (United States)

    Huang, Le; Xu, Huilong; Zhang, Zhiyong; Chen, Chengying; Jiang, Jianhua; Ma, Xiaomeng; Chen, Bingyan; Li, Zishen; Zhong, Hua; Peng, Lian-Mao

    2014-07-01

    Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal amplifying/process ICs are manufactured via commercial 0.18 um silicon CMOS technology, and graphene Hall elements (GHEs) are fabricated on top of the passivation layer of the CMOS chip via a low-temperature micro-fabrication process. The sensitivity of the GHE on CMOS chip is further improved by integrating the GHE with the CMOS amplifier on the Si chip. This work not only paves the way to fabricate graphene/Si CMOS Hall ICs with much higher performance than that of conventional Hall ICs, but also provides a general method for scalable integration of graphene devices with silicon CMOS ICs via a low-temperature process.

  18. Control technology for integrated circuit fabrication at Micro-Circuit Engineering, Incorporated, West Palm Beach, Florida

    Science.gov (United States)

    Mihlan, G. I.; Mitchell, R. I.; Smith, R. K.

    1984-07-01

    A survey to assess control technology for integrated circuit fabrication was conducted. Engineering controls included local and general exhaust ventilation, shielding, and personal protective equipment. Devices or work stations that contained toxic materials that were potentially dangerous were controlled by local exhaust ventilation. Less hazardous areas were controlled by general exhaust ventilation. Process isolation was used in the plasma etching, low pressure chemical vapor deposition, and metallization operations. Shielding was used in ion implantation units to control X-ray emissions, in contact mask alignes to limit ultraviolet (UV) emissions, and in plasma etching units to control radiofrequency and UV emissions. Most operations were automated. Use of personal protective equipment varied by job function.

  19. Sub-10 nm colloidal lithography for circuit-integrated spin-photo-electronic devices

    Directory of Open Access Journals (Sweden)

    Adrian Iovan

    2012-12-01

    Full Text Available Patterning of materials at sub-10 nm dimensions is at the forefront of nanotechnology and employs techniques of various complexity, efficiency, areal scale, and cost. Colloid-based patterning is known to be capable of producing individual sub-10 nm objects. However, ordered, large-area nano-arrays, fully integrated into photonic or electronic devices have remained a challenging task. In this work, we extend the practice of colloidal lithography to producing large-area sub-10 nm point-contact arrays and demonstrate their circuit integration into spin-photo-electronic devices. The reported nanofabrication method should have broad application areas in nanotechnology as it allows ballistic-injection devices, even for metallic materials with relatively short characteristic relaxation lengths.

  20. Long-wavelength photonic integrated circuits and avalanche photodetectors

    Science.gov (United States)

    Tsou, Yi-Jen D.; Zaytsev, Sergey; Pauchard, Alexandre; Hummel, Steve; Lo, Yu-Hwa

    2001-10-01

    Fast-growing internet traffic volume require high data communication bandwidth over longer distances. Access network bottlenecks put pressure on short-range (SR) telecommunication systems. To effectively address these datacom and telecom market needs, low-cost, high-speed laser modules at 1310 to 1550 nm wavelengths and avalanche photodetectors are required. The great success of GaAs 850nm VCSEls for Gb/s Ethernet has motivated efforts to extend VCSEL technology to longer wavelengths in the 1310 and 1550 nm regimes. However, the technological challenges associated with materials for long wavelength VCSELs are tremendous. Even with recent advances in this area, it is believed that significant additional development is necessary before long wavelength VCSELs that meet commercial specifications will be widely available. In addition, the more stringent OC192 and OC768 specifications for single-mode fiber (SMF) datacom may require more than just a long wavelength laser diode, VCSEL or not, to address numerous cost and performance issues. We believe that photonic integrated circuits (PICs), which compactly integrate surface-emitting lasers with additional active and passive optical components with extended functionality, will provide the best solutions to today's problems. Photonic integrated circuits have been investigated for more than a decade. However, they have produced limited commercial impact to date primarily because the highly complicated fabrication processes produce significant yield and device performance issues. In this presentation, we will discuss a new technology platform of InP-based PICs compatible with surface-emitting laser technology, as well as a high data rate externally modulated laser module. Avalanche photodetectors (APDs) are the key component in the receiver to achieve high data rate over long transmission distance because of their high sensitivity and large gain- bandwidth product. We have used wafer fusion technology to achieve In

  1. Digital pixel readout integrated circuit architectures for LWIR

    Science.gov (United States)

    Shafique, Atia; Yazici, Melik; Kayahan, Huseyin; Ceylan, Omer; Gurbuz, Yasar

    2015-06-01

    This paper presents and discusses digital pixel readout integrated circuit architectures for long wavelength infrared (LWIR) in CMOS technology. Presented architectures are designed for scanning and staring arrays type detectors respectively. For scanning arrays, digital time delay integration (TDI) is implemented on 8 pixels with sampling rate up to 3 using CMOS 180nm technology. Input referred noise of ROIC is below 750 rms electron meanwhile power dissipation is appreciably under 30mW. ROIC design is optimized to perform at room as well as cryogenic temperatures. For staring type arrays, a digital pixel architecture relying on coarse quantization with pulse frequency modulation (PFM) and novel approach of extended integration is presented. It can achieve extreme charge handling capacity of 2.04Ge- with 20 bit output resolution and power dissipation below 350 nW in CMOS 90nm technology. Efficient mechanism of measuring the time to estimate the remaining charge on integration capacitor in order to achieve low SNR has employed.

  2. VISA Final Report: Fully Integrated Power Electronic Systems in Automotive Electronics

    NARCIS (Netherlands)

    Waffenschmidt, E.

    2011-01-01

    This report summarizes the activities related to the public funded project “Vollintegrierte leistungselektronische Systeme in der Automobilelektronik – VISA” (Fully Integrated Power Electronic Systems in Automotive Electronics). Aim of the project is to investigate the integration of components into

  3. Single event soft error in advanced integrated circuit

    International Nuclear Information System (INIS)

    As technology feature size decreases, single event upset (SEU), and single event transient (SET) dominate the radiation response of microcircuits. Multiple bit upset (MBU) (or multi cell upset) effects, digital single event transient (DSET) and analogue single event transient (ASET) cause serious problems for advanced integrated circuits (ICs) applied in a radiation environment and have become a pressing issue. To face this challenge, a lot of work has been put into the single event soft error mechanism and mitigation schemes. This paper presents a review of SEU and SET, including: a brief historical overview, which summarizes the historical development of the SEU and SET since their first observation in the 1970's; effects prominent in advanced technology, which reviews the effects such as MBU, MSET as well as SET broadening and quenching with the influence of temperature, device structure etc.; the present understanding of single event soft error mechanisms, which review the basic mechanism of single event generation including various component of charge collection; and a discussion of various SEU and SET mitigation schemes divided as circuit hardening and layout hardening that could help the designer meet his goals. (review)

  4. A novel voltage output integrated circuit temperature sensor

    Institute of Scientific and Technical Information of China (English)

    吴晓波; 赵梦恋; 严晓浪; 方志刚

    2002-01-01

    The novel integrated circuit (IC) temperature sensor presented in this paper works similarly as a two-terminal Zener, has breakdown voltage directly proportional to Kelvin temperature at 10 mV/℃, with typical error of less than ±1.0℃ over a temperature range from -50℃ to +125℃. In addition to all the features that conventional IC temperature sensors have, the new device also has very low static power dissipation ( 0.5 mW ) , low output impedance ( less than 1Ω), excellent stability, high reproducibility, and high precision. The sensor's circuit design and layout are discussed in detail. Applications of the sensor include almost any type of temperature sensing over the range of -50℃-+125℃. The low impedance and linear output of the device make interfacing the readout or control circuitry especially easy. Due to the excellent performance and low cost of this sensor, more applications of the sensor over wide temperature range are expected.

  5. Integrated circuit for processing a low-frequency signal from a seismic detector

    Energy Technology Data Exchange (ETDEWEB)

    Malashevich, N. I.; Roslyakov, A. S.; Polomoshnov, S. A., E-mail: S.Polomoshnov@tsen.ru; Fedorov, R. A. [Research and Production Complex ' Technological Center' of the Moscow Institute of Electronic Technology (Russian Federation)

    2011-12-15

    Specific features for the detection and processing of a low-frequency signal from a seismic detector are considered in terms of an integrated circuit based on a large matrix crystal of the 5507 series. This integrated circuit is designed for the detection of human movements. The specific features of the information signal, obtained at the output of the seismic detector, and the main characteristics of the integrated circuit and its structure are reported.

  6. Design and testing of integrated circuits for reactor protection channels

    International Nuclear Information System (INIS)

    Custom and semicustom application-specific integrated circuit design and testing methods are investigated for use in research and commercial nuclear reactor safety systems. The Electric Power Research Institute and Oak Ridge National Laboratory are working together through a cooperative research and development agreement to apply modern technology to a nuclear reactor protection system. Purpose of this project is to demonstrate to the nuclear industry an alternative approach for new or upgrade reactor protection and safety system signal processing and voting logic. Motivation for this project stems from (1) the difficulty of proving that software-based protection systems are adequately reliable, (2) the obsolescence of the original equipment, and (3) the improved performance of digital processing

  7. Plasmonic nanopatch array for optical integrated circuit applications.

    Science.gov (United States)

    Qu, Shi-Wei; Nie, Zai-Ping

    2013-01-01

    Future plasmonic integrated circuits with the capability of extremely high-speed data processing at optical frequencies will be dominated by the efficient optical emission (excitation) from (of) plasmonic waveguides. Towards this goal, plasmonic nanoantennas, currently a hot topic in the field of plasmonics, have potential to bridge the mismatch between the wave vector of free-space photonics and that of the guided plasmonics. To manipulate light at will, plasmonic nanoantenna arrays will definitely be more efficient than isolated nanoantennas. In this article, the concepts of microwave antenna arrays are applied to efficiently convert plasmonic waves in the plasmonic waveguides into free-space optical waves or vice versa. The proposed plasmonic nanoantenna array, with nanopatch antennas and a coupled wedge plasmon waveguide, can also act as an efficient spectrometer to project different wavelengths into different directions, or as a spatial filter to absorb a specific wavelength at a specified incident angle. PMID:24201454

  8. Infrared transparent graphene heater for silicon photonic integrated circuits.

    Science.gov (United States)

    Schall, Daniel; Mohsin, Muhammad; Sagade, Abhay A; Otto, Martin; Chmielak, Bartos; Suckow, Stephan; Giesecke, Anna Lena; Neumaier, Daniel; Kurz, Heinrich

    2016-04-18

    Thermo-optical tuning of the refractive index is one of the pivotal operations performed in integrated silicon photonic circuits for thermal stabilization, compensation of fabrication tolerances, and implementation of photonic operations. Currently, heaters based on metal wires provide the temperature control in the silicon waveguide. The strong interaction of metal and light, however, necessitates a certain gap between the heater and the photonic structure to avoid significant transmission loss. Here we present a graphene heater that overcomes this constraint and enables an energy efficient tuning of the refractive index. We achieve a tuning power as low as 22 mW per free spectral range and fast response time of 3 µs, outperforming metal based waveguide heaters. Simulations support the experimental results and suggest that for graphene heaters the spacing to the silicon can be further reduced yielding the best possible energy efficiency and operation speed. PMID:27137229

  9. Uncertain behaviours of integrated circuits improve computational performance.

    Science.gov (United States)

    Yoshimura, Chihiro; Yamaoka, Masanao; Hayashi, Masato; Okuyama, Takuya; Aoki, Hidetaka; Kawarabayashi, Ken-ichi; Mizuno, Hiroyuki

    2015-01-01

    Improvements to the performance of conventional computers have mainly been achieved through semiconductor scaling; however, scaling is reaching its limitations. Natural phenomena, such as quantum superposition and stochastic resonance, have been introduced into new computing paradigms to improve performance beyond these limitations. Here, we explain that the uncertain behaviours of devices due to semiconductor scaling can improve the performance of computers. We prototyped an integrated circuit by performing a ground-state search of the Ising model. The bit errors of memory cell devices holding the current state of search occur probabilistically by inserting fluctuations into dynamic device characteristics, which will be actualised in the future to the chip. As a result, we observed more improvements in solution accuracy than that without fluctuations. Although the uncertain behaviours of devices had been intended to be eliminated in conventional devices, we demonstrate that uncertain behaviours has become the key to improving computational performance. PMID:26586362

  10. Further on integrator circuit analogy for natural convection

    Energy Technology Data Exchange (ETDEWEB)

    Khane, Vaibhav [Nuclear Engineering, Missouri University of Science and Technology, 225 Fulton Hall, 300W. 13th St., Rolla, MO-65409 (United States); Usman, Shoaib, E-mail: usmans@mst.ed [Nuclear Engineering, Missouri University of Science and Technology, 225 Fulton Hall, 300W. 13th St., Rolla, MO-65409 (United States)

    2010-03-15

    This research is an extension of the previous work on the development of an integrator (RC) circuit analogy for natural convection. This analogy has been proven experimentally as well as by numerical simulations. Additional Rayleigh-Benard convection numerical simulations were performed to investigate DELTAT (temperature difference between source and sink) dependence of the thermal resistance of a natural convection system. Our results suggest that analogous to voltage dependent resistor (VDR) in electrical engineering, DELTAT dependent thermal resistance is observed in natural convection system. This DELTAT dependent thermal resistance leads to a variable time constant. Moreover, this research also suggests that for a natural convection system, in addition to the thermal capacitance a kinetic energy capacitance also exists. The relative contribution of kinetic energy capacitance depends on Rayleigh number. These results provide significant step forward towards development of a new inexpensive modeling and transient analysis tool for a natural convection system.

  11. Further on integrator circuit analogy for natural convection

    International Nuclear Information System (INIS)

    This research is an extension of the previous work on the development of an integrator (RC) circuit analogy for natural convection. This analogy has been proven experimentally as well as by numerical simulations. Additional Rayleigh-Benard convection numerical simulations were performed to investigate ΔT (temperature difference between source and sink) dependence of the thermal resistance of a natural convection system. Our results suggest that analogous to voltage dependent resistor (VDR) in electrical engineering, ΔT dependent thermal resistance is observed in natural convection system. This ΔT dependent thermal resistance leads to a variable time constant. Moreover, this research also suggests that for a natural convection system, in addition to the thermal capacitance a kinetic energy capacitance also exists. The relative contribution of kinetic energy capacitance depends on Rayleigh number. These results provide significant step forward towards development of a new inexpensive modeling and transient analysis tool for a natural convection system.

  12. Printed Circuit Board Integrated Toroidal Radio Frequency Inductors

    DEFF Research Database (Denmark)

    Kamby, Peter; Knott, Arnold; Andersen, Michael A. E.

    2012-01-01

    Modern power semiconductors allow for switching frequencies of power converters in the very high frequency (VHF) band (30 MHz to 300 MHz). The major advantage of this frequency increase is a remarkable reduction of the size of power converters due to smaller passive components. However crucial...... attention needs to be payed to switching losses, so that the size reduction in electrical components does not get consumed by a major increase in heatsink size. This paper is investigating the major size limiting component in power converters: the inductor. In the VHF range, inductors are typically...... implemented as solenoids, either in spiral or cylindrical form. Those have the disadvantage of excessive stray fields, which can cause losses and disturbances in adjacent circuitry. Therefore this paper presents the analysis, design and realization of a printed circuit board (PCB) integrated inductor under...

  13. An integrated energy-efficient capacitive sensor digital interface circuit

    KAUST Repository

    Omran, Hesham

    2014-06-19

    In this paper, we propose an energy-efficient 13-bit capacitive sensor interface circuit. The proposed design fully relies on successive approximation algorithm, which eliminates the need for oversampling and digital decimation filtering, and thus low-power consumption is achieved. The proposed architecture employs a charge amplifier stage to acheive parasitic insensitive operation and fine absolute resolution. Moreover, the output code is not affected by offset voltages or charge injection. The successive approximation algorithm is implemented in the capacitance-domain using a coarse-fine programmable capacitor array, which allows digitizing wide capacitance range in compact area. Analysis for the maximum achievable resolution due to mismatch is provided. The proposed design is insensitive to any reference voltage or current which translates to low temperature sensitivity. The operation of a prototype fabricated in a standard CMOS technology is experimentally verified using both on-chip and off-chip capacitive sensors. Compared to similar prior work, the fabricated prototype achieves and excellent energy efficiency of 34 pJ/step.

  14. Automated CNC Micromachining for Integrated THz Waveguide Circuits

    OpenAIRE

    Groppi, Christopher E.; Love, Brian; Underhill, Matthew; Walker, Christopher

    2010-01-01

    Computer Numerically Controlled (CNC) machining of splitblock waveguide circuits has become the primary method of constructing terahertz waveguide circuits. The majority of these circuits have been made on traditional CNC machining centers or on custom-made laboratory machining systems. At both the University of Arizona and Arizona State University, we have developed techniques for machining splitblock waveguide circuits using purpose-built ultra high precision CNC mac...

  15. Leaky Integrate-and-Fire Neuron Circuit Based on Floating-Gate Integrator

    Science.gov (United States)

    Kornijcuk, Vladimir; Lim, Hyungkwang; Seok, Jun Yeong; Kim, Guhyun; Kim, Seong Keun; Kim, Inho; Choi, Byung Joon; Jeong, Doo Seok

    2016-01-01

    The artificial spiking neural network (SNN) is promising and has been brought to the notice of the theoretical neuroscience and neuromorphic engineering research communities. In this light, we propose a new type of artificial spiking neuron based on leaky integrate-and-fire (LIF) behavior. A distinctive feature of the proposed FG-LIF neuron is the use of a floating-gate (FG) integrator rather than a capacitor-based one. The relaxation time of the charge on the FG relies mainly on the tunnel barrier profile, e.g., barrier height and thickness (rather than the area). This opens up the possibility of large-scale integration of neurons. The circuit simulation results offered biologically plausible spiking activity (circuit was subject to possible types of noise, e.g., thermal noise and burst noise. The simulation results indicated remarkable distributional features of interspike intervals that are fitted to Gamma distribution functions, similar to biological neurons in the neocortex. PMID:27242416

  16. Computation Reduction for Statistical Analysis of the Effect of Nano-CMOS Variability on Integrated Circuits

    OpenAIRE

    Xie, Zheng

    2012-01-01

    The intrinsic atomistic variability of nano-scale integrated circuit (IC) technology must be taken into account when analysing circuit designs to predict likely yield. These ‘atomistic’ variabilities are random in nature and are so great that new circuit analysis techniques are needed which adopt a statistical treatment of the variability of device performances. Monte Carlo (MC) based statistical techniques aim to do this by analysing many randomized copies of the circuit. The randomization ...

  17. Effects of total dose of ionizing radiation on integrated circuits

    International Nuclear Information System (INIS)

    Full text: The study of ionizing radiation effects on materials used in electronic devices is of great relevance for the progress of global technological development and, particularly, it is a necessity in some strategic areas in Brazil. Electronic circuits are strongly influenced by radiation and the need for IC's featuring radiation hardness is largely growing to meet the stringent environment in space electronics. On the other hand, aerospace agencies are encouraging both scientific community and semiconductors industry to develop hardened-by-design components using standard manufacturing processes to achieve maximum performance, while significantly reducing costs. To understand the physical phenomena responsible for changes in devices exposed to ionizing radiation several kinds of radiation should then be considered, among them alpha particles, protons, gamma and X-rays. Radiation effects on the integrated circuits are usually divided into two categories: total ionizing dose (TID), a cumulative dose that shifts the threshold voltage and increases transistor's off-state current; single events effects (SEE), a transient effect which can deposit charge directly into the device and disturb the properties of electronic circuits. TID is one of the most common effects and may generate degradation in some parameters of the CMOS electronic devices, such as the threshold voltage oscillation, increase of the sub-threshold slope and increase of the off-state current. The effects of ionizing radiation are the creation of electron-hole pairs in the oxide layer changing operation mode parameters of the electronic device. Indirectly, there will be also changes in the device due to the formation of secondary electrons from the interaction of electromagnetic radiation with the material, since the charge carriers can be trapped both in the oxide layer and in the interface with the oxide. In this work we have investigated the behavior of MOSFET devices fabricated with different

  18. Focused ion beam damage to MOS integrated circuits

    International Nuclear Information System (INIS)

    Commercial focused ion beam (FIB) systems are commonly used to image integrated circuits (ICS) after device processing, especially in failure analysis applications. FIB systems are also often employed to repair faults in metal lines for otherwise functioning ICS, and are being evaluated for applications in film deposition and nanofabrication. A problem that is often seen in FIB imaging and repair is that ICS can be damaged during the exposure process. This can result in degraded response or out-right circuit failure. Because FIB processes typically require the surface of an IC to be exposed to an intense beam of 30--50 keV Ga+ ions, both charging and secondary radiation damage are potential concerns. In previous studies, both types of effects have been suggested as possible causes of device degradation, depending on the type of device examined and/or the bias conditions. Understanding the causes of this damage is important for ICS that are imaged or repaired by a FIB between manufacture and operation, since the performance and reliability of a given IC is otherwise at risk in subsequent system application. In this summary, the authors discuss the relative roles of radiation damage and charging effects during FIB imaging. Data from exposures of packaged parts under controlled bias indicate the possibility for secondary radiation damage during FIB exposure. On the other hand, FIB exposure of unbiased wafers (a more common application) typically results in damage caused by high-voltage stress or electrostatic discharge. Implications for FIB exposure and subsequent IC use are discussed

  19. Fully 3D-Integrated Pixel Detectors for X-Rays

    Energy Technology Data Exchange (ETDEWEB)

    Deptuch, Grzegorz W. [Fermi National Accelerator Lab. (FNAL), Batavia, IL (United States); Gabriella, Carini [SLAC National Accelerator Lab., Menlo Park, CA (United States); Enquist, Paul [Fermi National Accelerator Lab. (FNAL), Batavia, IL (United States); Grybos, Pawel [Fermi National Accelerator Lab. (FNAL), Batavia, IL (United States); Holm, Scott [Fermi National Accelerator Lab. (FNAL), Batavia, IL (United States); Lipton, Ronald [Fermi National Accelerator Lab. (FNAL), Batavia, IL (United States); Maj, Piotr [Fermi National Accelerator Lab. (FNAL), Batavia, IL (United States); Patti, Robert [Fermi National Accelerator Lab. (FNAL), Batavia, IL (United States); Siddons, David Peter [Fermi National Accelerator Lab. (FNAL), Batavia, IL (United States); Szczygiel, Robert [Fermi National Accelerator Lab. (FNAL), Batavia, IL (United States); Yarema, Raymond [Fermi National Accelerator Lab. (FNAL), Batavia, IL (United States)

    2016-01-01

    The vertically integrated photon imaging chip (VIPIC1) pixel detector is a stack consisting of a 500-μm-thick silicon sensor, a two-tier 34-μm-thick integrated circuit, and a host printed circuit board (PCB). The integrated circuit tiers were bonded using the direct bonding technology with copper, and each tier features 1-μm-diameter through-silicon vias that were used for connections to the sensor on one side, and to the host PCB on the other side. The 80-μm-pixel-pitch sensor was the direct bonding technology with nickel bonded to the integrated circuit. The stack was mounted on the board using Sn–Pb balls placed on a 320-μm pitch, yielding an entirely wire-bond-less structure. The analog front-end features a pulse response peaking at below 250 ns, and the power consumption per pixel is 25 μW. We successful completed the 3-D integration and have reported here. Additionally, all pixels in the matrix of 64 × 64 pixels were responding on well-bonded devices. Correct operation of the sparsified readout, allowing a single 153-ns bunch timing resolution, was confirmed in the tests on a synchrotron beam of 10-keV X-rays. An equivalent noise charge of 36.2 e- rms and a conversion gain of 69.5 μV/e- with 2.6 e- rms and 2.7 μV/e- rms pixel-to-pixel variations, respectively, were measured.

  20. Liquid crystal waveguide technologies for a new generation of low-power photonic integrated circuits

    Science.gov (United States)

    d'Alessandro, Antonio; Martini, Luca; Civita, Luca; Beccherelli, Romeo; Asquini, Rita

    2015-03-01

    In this paper we show two approaches to fabricate photonic channels on different substrate technology platforms, in particular silicon and polydimethylsiloxane (PDMS), for flexible photonic integrated circuits. The electro-optic effect and nonlinear optical properties of liquid crystals (LC) allow the realization of low cost and low energy consumption optoelectronic devices operating at both visible and near-infrared wavelengths. High extinction ratio and large tuning range guided wave devices will be presented to be used for both optofluidic and datacom applications, in which both low realization costs and low power consumption are key features. In particular we will show our recent results on polarization independent light propagation in waveguides whose core consists of LC infiltrated in PDMS channels (LC:PDMS waveguides) fully compatible with optofluidic and lab-on-chip microsystems.

  1. Development of wide range charge integration application specified integrated circuit for photo-sensor

    International Nuclear Information System (INIS)

    A front-end application specified integrated circuit (ASIC) is developed with a wide dynamic range amplifier (WDAMP) to read-out signals from a photo-sensor like a photodiode. The WDAMP ASIC consists of a charge sensitive preamplifier, four wave-shaping circuits with different amplification factors and Wilkinson-type analog-to-digital converter (ADC). To realize a wider range, the integrating capacitor in the preamplifier can be changed from 4 pF to 16 pF by a two-bit switch. The output of a preamplifier is shared by the four wave-shaping circuits with four gains of 1, 4, 16 and 64 to adapt the input range of ADC. A 0.25-μm CMOS process (of UMC electronics CO., LTD) is used to fabricate the ASIC with four-channels. The dynamic range of four orders of magnitude is achieved with the maximum range over 20 pC and the noise performance of 0.46 fC + 6.4×10−4 fC/pF. -- Highlights: ► A front-end ASIC is developed with a wide dynamic range amplifier. ► The ASIC consists of a CSA, four wave-shaping circuits and pulse-height-to-time converters. ► The dynamic range of four orders of magnitude is achieved with the maximum range over 20 pC.

  2. Modern approaches to the design of analog-digit integrated circuits based on multilevel simulation methods

    International Nuclear Information System (INIS)

    Modern methods for the design of analog and analog-digit integrated circuits have been analyzed. “Top-down” and “bottom-up” design methods are compared. The advantages of the “top-down” method in the rate of the development and verification of integrated circuits have been demonstrated

  3. 77 FR 74027 - Certain Integrated Circuit Packages Provided with Multiple Heat-Conducting Paths and Products...

    Science.gov (United States)

    2012-12-12

    ..., California (collectively, ``ITRI''). 77 FR 39735 (Jul. 5, 2012). The complaint, as amended, alleges... COMMISSION Certain Integrated Circuit Packages Provided with Multiple Heat- Conducting Paths and Products... integrated circuit packages provided with multiple heat-conducting paths and products containing same...

  4. 75 FR 51843 - In the Matter of Certain Large Scale Integrated Circuit Semiconductor Chips and Products...

    Science.gov (United States)

    2010-08-23

    ..., based on a complaint filed by Panasonic Corporation (``Panasonic'') of Japan. 75 FR 24742-43. The... COMMISSION In the Matter of Certain Large Scale Integrated Circuit Semiconductor Chips and Products... importation of certain large scale integrated circuit semiconductor chips and products containing same...

  5. A Fully Integrated Nanosystem of Semiconductor Nanowires for Direct Solar Water Splitting

    OpenAIRE

    Liu, Chong

    2014-01-01

    Artificial photosynthesis, the biomimetic approach to converting sunlight?s energy directly into chemical fuels, aims to imitate nature by using an integrated system of nanostructures, each of which plays a specific role in the sunlight-to-fuel conversion process. Here we describe a fully integrated system of nanoscale photoelectrodes assembled from inorganic nanowires for direct solar water splitting. Similar to the photosynthetic system in a chloroplast, the artificial photosynthetic system...

  6. High-speed coherent silicon modulator module using photonic integrated circuits: from circuit design to packaged module

    Science.gov (United States)

    Bernabé, S.; Olivier, S.; Myko, A.; Fournier, M.; Blampey, B.; Abraham, A.; Menezo, S.; Hauden, J.; Mottet, A.; Frigui, K.; Ngoho, S.; Frigui, B.; Bila, S.; Marris-Morini, D.; Pérez-Galacho, D.; Brindel, P.; Charlet, G.

    2016-05-01

    Silicon photonics technology is an enabler for the integration of complex circuits on a single chip, for various optical link applications such as routing, optical networks on chip, short range links and long haul transmitters. Quadrature Phase Shift Keying (QPSK) transmitters is one of the typical circuits that can be achieved using silicon photonics integrated circuits. The achievement of 25GBd QPSK transmitter modules requires several building blocks to be optimized: the pn junction used to build a BPSK (Binary Shift Phase Keying) modulator, the RF access and the optical interconnect at the package level. In this paper, we describe the various design steps of a BPSK module and the related tests that are needed at every stage of the fabrication process.

  7. Fully-integrated, bezel-less transistor arrays using reversibly foldable interconnects and stretchable origami substrates.

    Science.gov (United States)

    Kim, Mijung; Park, Jihun; Ji, Sangyoon; Shin, Sung-Ho; Kim, So-Yun; Kim, Young-Cheon; Kim, Ju-Young; Park, Jang-Ung

    2016-05-14

    Here we demonstrate fully-integrated, bezel-less transistor arrays using stretchable origami substrates and foldable conducting interconnects. Reversible folding of these arrays is enabled by origami substrates which are composed of rigid support fixtures and foldable elastic joints. In addition, hybrid structures of thin metal films and metallic nanowires worked as foldable interconnects which are located on the elastomeric joints. PMID:27101972

  8. Integrated reconfigurable high-voltage transmitting circuit for CMUTs

    DEFF Research Database (Denmark)

    Llimos Muntal, Pere; Larsen, Dennis Øland; Jørgensen, Ivan Harald Holger;

    2015-01-01

    In this paper a high-voltage transmitting circuit aimed for capacitive micromachined ultrasonic transducers (CMUTs) used in scanners for medical applications is designed and implemented in a 0.35 μm high-voltage CMOS process. The transmitting circuit is reconfigurable externally making it able...... to drive a wide variety of CMUTs. The transmitting circuit can generate several pulse shapes with voltages up to 100 V, maximum pulse range of 50 V, frequencies up to 5 MHz and different driving slew rates. Measurements are performed on the circuit in order to assess its functionality and power consumption...

  9. Monolithic Microwave Integrated Circuit (MMIC) Phased Array Demonstrated With ACTS

    Science.gov (United States)

    1996-01-01

    Monolithic Microwave Integrated Circuit (MMIC) arrays developed by the NASA Lewis Research Center and the Air Force Rome Laboratory were demonstrated in aeronautical terminals and in mobile or fixed Earth terminals linked with NASA's Advanced Communications Technology Satellite (ACTS). Four K/Ka-band experimental arrays were demonstrated between May 1994 and May 1995. Each array had GaAs MMIC devices at each radiating element for electronic beam steering and distributed power amplification. The 30-GHz transmit array used in uplinks to ACTS was developed by Lewis and Texas Instruments. The three 20-GHz receive arrays used in downlinks from ACTS were developed in cooperation with the Air Force Rome Laboratory, taking advantage of existing Air Force integrated-circuit, active-phased-array development contracts with the Boeing Company and Lockheed Martin Corporation. Four demonstrations, each related to an application of high interest to both commercial and Department of Defense organizations, were conducted. The location, type of link, and the data rate achieved for each of the applications is shown. In one demonstration-- an aeronautical terminal experiment called AERO-X--a duplex voice link between an aeronautical terminal on the Lewis Learjet and ACTS was achieved. Two others demonstrated duplex voice links (and in one case, interactive video links as well) between ACTS and an Army high-mobility, multipurpose wheeled vehicle (HMMWV, or "humvee"). In the fourth demonstration, the array was on a fixed mount and was electronically steered toward ACTS. Lewis served as project manager for all demonstrations and as overall system integrator. Lewis engineers developed the array system including a controller for open-loop tracking of ACTS during flight and HMMWV motion, as well as a laptop data display and recording system used in all demonstrations. The Jet Propulsion Laboratory supported the AERO-X program, providing elements of the ACTS Mobile Terminal. The successful

  10. Laser applications in integrated circuits and photonics packaging

    Science.gov (United States)

    Lu, Yong Feng; Li, L. P.; Mendu, K.; Shi, J.

    2004-07-01

    Laser processing has large potential in the packaging of integrated circuits (IC). It can be used in many applications such as laser cleaning of IC mold tools, laser deflash to remove mold flash from heat sinks and lead wires of IC packages, laser singulation of BGA (ball grid array) and CSP (chip scale packages), laser reflow of solder ball on GBA, laser peeling for CSP, laser marking on packages and on Si wafers. Laser nanoimprinting of self-assembled nanoparticles has been recently developed to fabricate hemispherical cavity arrays on semiconductor surfaces. This process has the potential applications in fabrication and packaging of photonic devices such as waveguides and optical interconnections. During the implementation of all these applications, laser parameters, material issues, throughput, yield, reliability and monitoring techniques have to be taken into account. Monitoring of laser-induced plasma and laser induced acoustic wave has been used to understand and to control the processes involved in these applications. Numerical simulations can provide useful information on process analysis and optimization.

  11. Integrated circuits and electrode interfaces for noninvasive physiological monitoring.

    Science.gov (United States)

    Ha, Sohmyung; Kim, Chul; Chi, Yu M; Akinin, Abraham; Maier, Christoph; Ueno, Akinori; Cauwenberghs, Gert

    2014-05-01

    This paper presents an overview of the fundamentals and state of the-art in noninvasive physiological monitoring instrumentation with a focus on electrode and optrode interfaces to the body, and micropower-integrated circuit design for unobtrusive wearable applications. Since the electrode/optrode-body interface is a performance limiting factor in noninvasive monitoring systems, practical interface configurations are offered for biopotential acquisition, electrode-tissue impedance measurement, and optical biosignal sensing. A systematic approach to instrumentation amplifier (IA) design using CMOS transistors operating in weak inversion is shown to offer high energy and noise efficiency. Practical methodologies to obviate 1/f noise, counteract electrode offset drift, improve common-mode rejection ratio, and obtain subhertz high-pass cutoff are illustrated with a survey of the state-of-the-art IAs. Furthermore, fundamental principles and state-of-the-art technologies for electrode-tissue impedance measurement, photoplethysmography, functional near-infrared spectroscopy, and signal coding and quantization are reviewed, with additional guidelines for overall power management including wireless transmission. Examples are presented of practical dry-contact and noncontact cardiac, respiratory, muscle and brain monitoring systems, and their clinical applications. PMID:24759282

  12. Neural Networks Integrated Circuit for Biomimetics MEMS Microrobot

    Directory of Open Access Journals (Sweden)

    Ken Saito

    2014-06-01

    Full Text Available In this paper, we will propose the neural networks integrated circuit (NNIC which is the driving waveform generator of the 4.0, 2.7, 2.5 mm, width, length, height in size biomimetics microelectromechanical systems (MEMS microrobot. The microrobot was made from silicon wafer fabricated by micro fabrication technology. The mechanical system of the robot was equipped with small size rotary type actuators, link mechanisms and six legs to realize the ant-like switching behavior. The NNIC generates the driving waveform using synchronization phenomena such as biological neural networks. The driving waveform can operate the actuators of the MEMS microrobot directly. Therefore, the NNIC bare chip realizes the robot control without using any software programs or A/D converters. The microrobot performed forward and backward locomotion, and also changes direction by inputting an external single trigger pulse. The locomotion speed of the microrobot was 26.4 mm/min when the step width was 0.88 mm. The power consumption of the system was 250 mWh when the room temperature was 298 K.

  13. PETRIC - A positron emission tomography readout integrated circuit

    Energy Technology Data Exchange (ETDEWEB)

    Pedrali-Noy, Marzio; Gruber, Gregory; Krieger, Bradley; Mandelli, Emmanuele; Meddeler, Gerrit; Moses, William; Rosso, Valeria

    2000-11-05

    We present architecture, critical design issues and performance measurements of PETRIC, a 64-channel mixed signal front-end integrated circuit (IC) for reading out a photodiode (PD) array coupled with LSO scintillator crystals for a medical imaging application (PET). Each channel consists of a low noise charge sensitive pre-amplifier (CSA), an RC-CR pulse shaper and a winner-take-all (WTA) multiplexer that selects the channel with the largest input signal. Triggered by an external timing signal, a switch opens and a capacitor stores the peak voltage of the winner channel. The shaper rise and fall times are adjustable by means of external current inputs over a continuous range of 0.7 (mu)s to 9 (mu)s. Power consumption is 5.4 mW per channel, measured Equivalent Noise Charge (ENC) at 1 (mu)s peaking time. Zero leakage current is 33 rms electrons plus 7.3 rms electrons per pF of input capacitance. Design is fabricated in 0.5 (mu)m 3.3V CMOS technology.

  14. Efficient Fingerprint Matching Algorithm for Integrated Circuit Cards

    Institute of Scientific and Technical Information of China (English)

    Jian-Wei Yang; Li-Feng Liu; Tian-Zi Jiang

    2004-01-01

    Fingerprint matching is a crucial step in fingerprint identification.Recently,a variety of algorithms for this issue have been developed.Each of them is application situation specific and has its advantages and disadvantages.It is highly desired to develop an efficient fingerprint verification technology for Integrated Circuit(IC)Cards or chips.IC cards have some special characteristics,such as very small storage space and slow processing speed,which hinder the use of most fingerprint matching algorithms in such situations.In order to solve this problem,the paper presents an improved minutia-pattern(minutiae-based)matching algorithm by employing the orientation field of the fingerprint as a new feature.Our algorithm not only inherits the advantages of the general minutia-pattern matching algorithms,but also overcomes their disadvantages.Experimental results show that the proposed algorithm can greatly improve the performance of fingerprint matching in both accuracy and efficiency,and it is very suitable for applications in IC cards.

  15. PETRIC - A positron emission tomography readout integrated circuit

    International Nuclear Information System (INIS)

    We present architecture, critical design issues and performance measurements of PETRIC, a 64-channel mixed signal front-end integrated circuit (IC) for reading out a photodiode (PD) array coupled with LSO scintillator crystals for a medical imaging application (PET). Each channel consists of a low noise charge sensitive pre-amplifier (CSA), an RC-CR pulse shaper and a winner-take-all (WTA) multiplexer that selects the channel with the largest input signal. Triggered by an external timing signal, a switch opens and a capacitor stores the peak voltage of the winner channel. The shaper rise and fall times are adjustable by means of external current inputs over a continuous range of 0.7 (mu)s to 9 (mu)s. Power consumption is 5.4 mW per channel, measured Equivalent Noise Charge (ENC) at 1 (mu)s peaking time. Zero leakage current is 33 rms electrons plus 7.3 rms electrons per pF of input capacitance. Design is fabricated in 0.5 (mu)m 3.3V CMOS technology

  16. Microcoil Spring Interconnects for Ceramic Grid Array Integrated Circuits

    Science.gov (United States)

    Strickland, S. M.; Hester, J. D.; Gowan, A. K.; Montgomery, R. K.; Geist, D. L.; Blanche, J. F.; McGuire, G. D.; Nash, T. S.

    2011-01-01

    As integrated circuit miniaturization trends continue, they drive the need for smaller higher input/output (I/O) packages. Hermetically sealed ceramic area array parts are the package of choice by the space community for high reliability space flight electronic hardware. Unfortunately, the coefficient of thermal expansion mismatch between the ceramic area array package and the epoxy glass printed wiring board limits the life of the interconnecting solder joint. This work presents the results of an investigation by Marshall Space Flight Center into a method to increase the life of this second level interconnection by the use of compliant microcoil springs. The design of the spring and its attachment process are presented along with thermal cycling results of microcoil springs (MCS) compared with state-of-the-art ball and column interconnections. Vibration testing has been conducted on MCS and high lead column parts. Radio frequency simulation and measurements have been made and the MCS has been modeled and a stress analysis performed. Thermal cycling and vibration testing have shown MCS interconnects to be significantly more reliable than solder columns. Also, MCS interconnects are less prone to handling damage than solder columns. Future work that includes shock testing, incorporation into a digital signal processor board, and process evaluation of expansion from a 400 I/O device to a device with over 1,100 I/O is identified.

  17. Reactor protection system design using application specific integrated circuits

    International Nuclear Information System (INIS)

    Implementing reactor protection systems (RPS) or other engineering safeguard systems with application specific integrated circuits (ASICs) offers significant advantages over conventional analog or software based RPSs. Conventional analog RPSs suffer from setpoints drifts and large numbers of discrete analog electronics, hardware logic, and relays which reduce reliability because of the large number of potential failures of components or interconnections. To resolve problems associated with conventional discrete RPSs and proposed software based RPS systems, a hybrid analog and digital RPS system implemented with custom ASICs is proposed. The actual design of the ASIC RPS resembles a software based RPS but the programmable software portion of each channel is implemented in a fixed digital logic design including any input variable computations. Set point drifts are zero as in proposed software systems, but the verification and validation of the computations is made easier since the computational logic an be exhaustively tested. The functionality is assured fixed because there can be no future changes to the ASIC without redesign and fabrication. Subtle error conditions caused by out of order evaluation or time dependent evaluation of system variables against protection criteria are eliminated by implementing all evaluation computations in parallel for simultaneous results. On- chip redundancy within each RPS channel and continuous self-testing of all channels provided enhanced assurance that a particular channel is available and faults are identified as soon as possible for corrective actions. The use of highly integrated ASICs to implement channel electronics rather than the use of discrete electronics greatly reduces the total number of components and interconnections in the RPS to further increase system reliability. A prototype ASIC RPS channel design and the design environment used for ASIC RPS systems design is discussed

  18. GaAs Photonic Integrated Circuit (PIC) development for high performance communications

    Energy Technology Data Exchange (ETDEWEB)

    Sullivan, C.T.

    1998-03-01

    Sandia has established a foundational technology in photonic integrated circuits (PICs) based on the (Al,Ga,In)As material system for optical communication, radar control and testing, and network switching applications at the important 1.3{mu}m/1.55{mu}m wavelengths. We investigated the optical, electrooptical, and microwave performance characteristics of the fundamental building-block PIC elements designed to be as simple and process-tolerant as possible, with particular emphasis placed on reducing optical insertion loss. Relatively conventional device array and circuit designs were built using these PIC elements: (1) to establish a baseline performance standard; (2) to assess the impact of epitaxial growth accuracy and uniformity, and of fabrication uniformity and yield; (3) to validate our theoretical and numerical models; and (4) to resolve the optical and microwave packaging issues associated with building fully packaged prototypes. Novel and more complex PIC designs and fabrication processes, viewed as higher payoff but higher risk, were explored in a parallel effort with the intention of meshing those advances into our baseline higher-yield capability as they mature. The application focus targeted the design and fabrication of packaged solitary modulators meeting the requirements of future wideband and high-speed analog and digital data links. Successfully prototyped devices are expected to feed into more complex PICs solving specific problems in high-performance communications, such as optical beamforming networks for phased array antennas.

  19. A fully integrated high-Q Whispering-Gallery Wedge Resonator

    CERN Document Server

    Ramiro-Manzano, F; Pavesi, L; Pucker, G; Ghulinyan, M

    2012-01-01

    Microresonator devices which posses ultra-high quality factors are essential for fundamental investigations and applications. Microsphere and microtoroid resonators support remarkably high Q's at optical frequencies, while planarity constrains preclude their integration into functional lightwave circuits. Conventional semiconductor processing can also be used to realize ultra-high-Q's with planar wedge-resonators. Still, their full integration with side-coupled dielectric waveguides remains an issue. Here we show the full monolithic integration of a wedge-resonator/waveguide vertically-coupled system on a silicon chip. In this approach the cavity and the waveguide lay in different planes. This permits to realize the shallow-angle wedge while the waveguide remains intact, allowing therefore to engineer a coupling of arbitrary strength between these two. The precise size-control and the robustness against post-processing operation due to its monolithic integration makes this system a prominent platform for indu...

  20. On the design of fully-integrated charge preamplifiers for the Superconducting Super Collider

    International Nuclear Information System (INIS)

    The specifications imposed on the charge preamplifiers, to be used in the Superconducting Supercollider are very demanding: the rise time should be less than 100 nsec and noise should be less than 1,000 electrons RMS for a total power consumption of less than 80 mWatt. Furthermore, several hundreds of thousands (or even millions) of channels have to be manufactured. Hence, integrated circuit (IC) implementations can be more economical than discrete implementations, due to the compact size and ease of manufacturing. BiFET IC technology is currently the most attractive technology, because it is a mature IC technology, and readily available from several industrial vendors. As a case study, a BiFET prototype preamplifier is presented, where circuit performance has been tested for total radiation doses up to 1.4 MegaRads

  1. Diffusion stop-layers for superconducting integrated circuits and qubits with Nb-based Josephson junctions

    OpenAIRE

    Tolpygo, Sergey K.; Amparo, Denis; Hunt, Richard T.; Vivalda, John A.; Yohannes, Daniel T.

    2010-01-01

    New technology for superconductor integrated circuits has been developed and is presented. It employs diffusion stoplayers (DSLs) to protect Josephson junctions (JJs) from interlayer migration of impurities, improve JJ critical current (Ic) targeting and reproducibility, eliminate aging, and eliminate pattern-dependent effects in Ic and tunneling characteristics of Nb/Al/AlOx/Nb junctions in integrated circuits. The latter effects were recently found in Nb-based JJs integrated into multilayer...

  2. Resonance modes in coplanar lines with integrated Josephson circuits

    Science.gov (United States)

    Shvetsov, A. V.; Satanin, A. M.; Mironov, V. A.; Il'ichev, E.

    2013-11-01

    The propagation of microwave radiation in co-planar superconducting lines with Josephson circuits (microresonators) of various configurations is investigated. It is shown that dips in the frequency dependence of the transmission power of the waveguide line modes are associated with local modes of the circuit. The dependencies of shape and position of the dips on an external magnetic field and applied power are found. The calculation results can be used for developing modern cryoelectronic microwave superconducting devices.

  3. RF CMOS Integrated Circuit: History, Current Status and Future Prospects

    OpenAIRE

    Ishihara, Noboru; Amakawa, Shuhei; Masu, Kazuya

    2011-01-01

    As great advancements have been made in CMOS process technology over the past 20 years, RF CMOS circuits operating in the microwave band have rapidly developed from component circuit levels to multiband/multimode transceiver levels. In the next ten years, it is highly likely that the following devices will be realized: (i) versatile transceivers such as those used in software-defined radios (SDR), cognitive radios (CR), and reconfigurable radios (RR); (ii) systems that operate in the millimet...

  4. Integrated Power Flow and Short Circuit Calculation Method for Distribution Network with Inverter Based Distributed Generation

    OpenAIRE

    Shan Yang; Xiangqian Tong

    2016-01-01

    Power flow calculation and short circuit calculation are the basis of theoretical research for distribution network with inverter based distributed generation. The similarity of equivalent model for inverter based distributed generation during normal and fault conditions of distribution network and the differences between power flow and short circuit calculation are analyzed in this paper. Then an integrated power flow and short circuit calculation method for distribution network with inverte...

  5. 22.8 GHz Substrate Integrated Waveguide Analog Frequency Divide-by-3 Circuit

    OpenAIRE

    Georgiadis, Apostolos; Collado, Ana; Niotaki, Kyriaki

    2015-01-01

    A 22.8 GHz analog frequency divide-by-3 circuit is presented based on an injection locked oscillator. Substrate integrated waveguide (SIW) technology is used to implement the input and output sections of the frequency divider circuit. The input SIW section at the gate of the active device permits the introduction of the injection signal at the third harmonic frequency of the oscillator, while the output section is designed to maximize the DC-RF conversion efficiency of the oscillator circuit....

  6. Fully-integrated, bezel-less transistor arrays using reversibly foldable interconnects and stretchable origami substrates

    Science.gov (United States)

    Kim, Mijung; Park, Jihun; Ji, Sangyoon; Shin, Sung-Ho; Kim, So-Yun; Kim, Young-Cheon; Kim, Ju-Young; Park, Jang-Ung

    2016-05-01

    Here we demonstrate fully-integrated, bezel-less transistor arrays using stretchable origami substrates and foldable conducting interconnects. Reversible folding of these arrays is enabled by origami substrates which are composed of rigid support fixtures and foldable elastic joints. In addition, hybrid structures of thin metal films and metallic nanowires worked as foldable interconnects which are located on the elastomeric joints.Here we demonstrate fully-integrated, bezel-less transistor arrays using stretchable origami substrates and foldable conducting interconnects. Reversible folding of these arrays is enabled by origami substrates which are composed of rigid support fixtures and foldable elastic joints. In addition, hybrid structures of thin metal films and metallic nanowires worked as foldable interconnects which are located on the elastomeric joints. Electronic supplementary information (ESI) available. See DOI: 10.1039/c6nr02041k

  7. A Novel Analog Integrated Circuit Design Course Covering Design, Layout, and Resulting Chip Measurement

    Science.gov (United States)

    Lin, Wei-Liang; Cheng, Wang-Chuan; Wu, Chen-Hao; Wu, Hai-Ming; Wu, Chang-Yu; Ho, Kuan-Hsuan; Chan, Chueh-An

    2010-01-01

    This work describes a novel, first-year graduate-level analog integrated circuit (IC) design course. The course teaches students analog circuit design; an external manufacturer then produces their designs in three different silicon chips. The students, working in pairs, then test these chips to verify their success. All work is completed within…

  8. 77 FR 60721 - Certain Semiconductor Integrated Circuit Devices and Products Containing Same; Notice of...

    Science.gov (United States)

    2012-10-04

    ... (``Microchip''). 77 FR 25747-48 (May 1, 2012). The complaint alleges violations of section 337 of the Tariff... COMMISSION Certain Semiconductor Integrated Circuit Devices and Products Containing Same; Notice of... circuit devices and products containing same by reason of infringement of certain claims of U.S....

  9. A Fully Integrated Nanosystem of Semiconductor Nanowires for Direct Solar Water Splitting

    Energy Technology Data Exchange (ETDEWEB)

    Liu, Chong; Tang, Jinyao; Chen, HaoMing; Liu, Bin; Yang, Peidong

    2013-02-21

    Artificial photosynthesis, the biomimetic approach to converting sunlight?s energy directly into chemical fuels, aims to imitate nature by using an integrated system of nanostructures, each of which plays a specific role in the sunlight-to-fuel conversion process. Here we describe a fully integrated system of nanoscale photoelectrodes assembled from inorganic nanowires for direct solar water splitting. Similar to the photosynthetic system in a chloroplast, the artificial photosynthetic system comprises two semiconductor light absorbers with large surface area, an interfacial layer for charge transport, and spatially separated cocatalysts to facilitate the water reduction and oxidation. Under simulated sunlight, a 0.12percent solar-to-fuel conversion efficiency is achieved, which is comparable to that of natural photosynthesis. The result demonstrates the possibility of integrating material components into a functional system that mimics the nanoscopic integration in chloroplasts. It also provides a conceptual blueprint of modular design that allows incorporation of newly discovered components for improved performance.

  10. Waveguide Phase Modulator for Integrated Planar Lightwave Circuits in KTP Project

    Data.gov (United States)

    National Aeronautics and Space Administration — This SBIR Phase II effort proposes the development and integration of a Planar Lightwave Circuit (PLC) into an all fiber-based seed laser system used in high...

  11. Supermode control in integrated hybrid Si/III–V optoelectronic circuits for modal gain enhancement

    OpenAIRE

    Sun, Xiankai; Yariv, Amnon

    2009-01-01

    We propose using supermode control to enhance the modal gain in integrated hybrid Si/III–V optoelectronic circuits. Numerical simulations predict that a 4-fold enhancement in modal gain can be achieved with optimal design.

  12. An Integrated-Circuit Temperature Sensor for Calorimetry and Differential Temperature Measurement.

    Science.gov (United States)

    Muyskens, Mark A.

    1997-01-01

    Describes the application of an integrated-circuit (IC) chip which provides an easy-to-use, inexpensive, rugged, computer-interfaceable temperature sensor for calorimetry and differential temperature measurement. Discusses its design and advantages. (JRH)

  13. A review of the technology and process on integrated circuits failure analysis applied in communications products

    Science.gov (United States)

    Ming, Zhimao; Ling, Xiaodong; Bai, Xiaoshu; Zong, Bo

    2016-02-01

    The failure analysis of integrated circuits plays a very important role in the improvement of the reliability in communications products. This paper intends to mainly introduce the failure analysis technology and process of integrated circuits applied in the communication products. There are many technologies for failure analysis, include optical microscopic analysis, infrared microscopic analysis, acoustic microscopy analysis, liquid crystal hot spot detection technology, optical microscopic analysis technology, micro analysis technology, electrical measurement, microprobe technology, chemical etching technology and ion etching technology. The integrated circuit failure analysis depends on the accurate confirmation and analysis of chip failure mode, the search of the root failure cause, the summary of failure mechanism and the implement of the improvement measures. Through the failure analysis, the reliability of integrated circuit and rate of good products can improve.

  14. Fully integrated patterned carbon nanotube strain sensors on flexible sensing skin substrates for structural health monitoring

    Science.gov (United States)

    Burton, Andrew R.; Kurata, Masahiro; Nishino, Hiromichi; Lynch, Jerome P.

    2016-04-01

    New advances in nanotechnology and material processing is creating opportunities for the design and fabrication of a new generation of thin film sensors that can used to assess structural health. In particular, thin film sensors attached to large areas of the structure surface has the potential to provide spatially rich data on the performance and health of a structure. This study focuses on the development of a fully integrated strain sensor that is fabricated on a flexible substrate for potentially use in sensing skins. This is completed using a carbon nanotube-polymer composite material that is patterned on a flexible polyimide substrate using optical lithography. The piezoresistive carbon nanotube elements are integrated into a complete sensing system by patterning copper electrodes and integrating off-the-shelf electrical components on the flexible film for expanded functionality. This diverse material utilization is realized in a versatile process flow to illustrate a powerful toolbox for sensing severity, location, and failure mode of damage on structural components. The fully integrated patterned carbon nanotube strain sensor is tested on a quarter-scale, composite beam column connection. The results and implications for future structural damage detection are discussed.

  15. A NEW TRANSISTOR SIZING APPROACH FOR DIGITAL INTEGRATED CIRCUITS USING FIREFLY ALGORITHM

    Directory of Open Access Journals (Sweden)

    Nima Talebpour Anaraki

    2015-12-01

    Full Text Available Due to the fact that, the power consumption and speed of a VLSI circuit are dependent on the transistor sizes, efficient transistor sizing is a new challenge for VLSI circuit designers. However, evolutionary computation can be successfully used for complex VLSI transistor sizing which reduces the time to market and enables the designer to find the optimized solutions for a non-linear and complex circuit design process. In this paper, a new digital integrated circuit design approach is proposed based on the firefly artificial intelligence optimization algorithm. In order to justify the effectiveness of the proposed algorithm in the design of VLSI circuits, an inverter (NOT gate is designed and optimized by the proposed algorithm. As the simulation results show, the inverter circuit has a very good performance for power and delay parameters.

  16. Design of a semi-custom integrated circuit for the SLAC SLC timing control system

    International Nuclear Information System (INIS)

    A semi-custom (gate array) integrated circuit has been designed for use in the SLAC Linear Collider timing and control system. The design process and SLAC's experiences during the phases of the design cycle are described. Issues concerning the partitioning of the design into semi-custom and standard components are discussed. Functional descriptions of the semi-custom integrated circuit and the timing module in which it is used are given

  17. Real Time Automated Counterfeit Integrated Circuit Detection using X-ray Microscopy

    OpenAIRE

    Mahmood, Kaleel; Latorre Carmona, Pedro; Shahbazmohamadi, Sina; Pla Bañón, Filiberto; Javidi, Bahram

    2015-01-01

    Determining the authenticity of integrated circuits is paramount to preventing counterfeit and malicious hardware from being used in critical military, healthcare, aerospace, consumer, and industry applications. Existing techniques to distinguish between authentic and counterfeit integrated circuits (ICs) often include destructive testing requiring subject matter experts. We present a nondestructive technique to detect ICs using x-ray microscopy and advanced imaging analysis with different pa...

  18. Automatic recloser circuit breaker integrated with GSM technology for power system notification

    Science.gov (United States)

    Lada, M. Y.; Khiar, M. S. A.; Ghani, S. A.; Nawawi, M. R. M.; Rahim, N. H.; Sinar, L. O. M.

    2015-05-01

    Lightning is one type of transient faults that usually cause the circuit breaker in the distribution board trip due to overload current detection. The instant tripping condition in the circuit breakers clears the fault in the system. Unfortunately most circuit breakers system is manually operated. The power line will be effectively re-energized after the clearing fault process is finished. Auto-reclose circuit is used on the transmission line to carry out the duty of supplying quality electrical power to customers. In this project, an automatic reclose circuit breaker for low voltage usage is designed. The product description is the Auto Reclose Circuit Breaker (ARCB) will trip if the current sensor detects high current which exceeds the rated current for the miniature circuit breaker (MCB) used. Then the fault condition will be cleared automatically and return the power line to normal condition. The Global System for Mobile Communication (GSM) system will send SMS to the person in charge if the tripping occurs. If the over current occurs in three times, the system will fully trip (open circuit) and at the same time will send an SMS to the person in charge. In this project a 1 A is set as the rated current and any current exceeding a 1 A will cause the system to trip or interrupted. This system also provides an additional notification for user such as the emergency light and warning system.

  19. Integrated-Circuit Controller For Brushless dc Motor

    Science.gov (United States)

    Le, Dong Tuan

    1994-01-01

    Generic circuit performs commutation-logic and power-switching functions for control of brushless dc motor. Controller includes commutation-logic and associated control circuitry, power supply, and inverters containing power transistors. Major advantages of controller are size, weight, and power consumption can be made less than other brushless-dc-motor controllers.

  20. Principal working group 3 on primary circuit integrity

    International Nuclear Information System (INIS)

    The main themes of this conference (13 papers) are: operating experience on leakages and failures in nuclear power plant piping, coolant circuits and steam generator tubes, probabilistic estimation and risk assessment, system failure analysis, leakage events and frequency, leak rate models and crack propagation mechanics, damage mechanisms and rupture probability

  1. Sensors, Circuits, and Satellites - NGSS at it's best: the integration of three dimensions with NASA science

    Science.gov (United States)

    Butcher, G. J.; Roberts-Harris, D.

    2013-12-01

    A set of innovative classroom lessons were developed based on informal learning activities in the 'Sensors, Circuits, and Satellites' kit manufactured by littleBits™ Electronics that are designed to lead students through a logical science content storyline about energy using sound and light and fully implements an integrated approach to the three dimensions of the Next Generation of Science Standards (NGSS). This session will illustrate the integration of NGSS into curriculum by deconstructing lesson design to parse out the unique elements of the 3 dimensions of NGSS. We will demonstrate ways in which we have incorporated the NGSS as we believe they were intended. According to the NGSS, 'The real innovation in the NGSS is the requirement that students are required to operate at the intersection of practice, content, and connection. Performance expectations are the right way to integrate the three dimensions. It provides specificity for educators, but it also sets the tone for how science instruction should look in classrooms. (p. 3). The 'Sensors, Circuits, and Satellites' series of lessons accomplishes this by going beyond just focusing on the conceptual knowledge (the disciplinary core ideas) - traditionally approached by mapping lessons to standards. These lessons incorporate the other 2 dimensions -cross-cutting concepts and the 8-practices of Sciences and Engineering-via an authentic and exciting connection to NASA science, thus implementing the NGSS in the way they were designed to be used: practices and content with the crosscutting concepts. When the NGSS are properly integrated, students are engaged in science and engineering content through the coupling of practice, content and connection. In the past, these two dimensions have been separated as distinct entities. We know now that coupling content and practices better demonstrates what goes on in real world science and engineering. We set out to accomplish what is called for in NGSS by integrating these

  2. CMOS analog integrated circuits high-speed and power-efficient design

    CERN Document Server

    Ndjountche, Tertulien

    2011-01-01

    High-speed, power-efficient analog integrated circuits can be used as standalone devices or to interface modern digital signal processors and micro-controllers in various applications, including multimedia, communication, instrumentation, and control systems. New architectures and low device geometry of complementary metaloxidesemiconductor (CMOS) technologies have accelerated the movement toward system on a chip design, which merges analog circuits with digital, and radio-frequency components. CMOS: Analog Integrated Circuits: High-Speed and Power-Efficient Design describes the important tren

  3. A fully integrated low-power CMOS particle detector front-end for space applications

    International Nuclear Information System (INIS)

    A fully integrated low-power complementary metal-oxide-semiconductor (CMOS) particle detector front-end (PDFE), optimized for space applications, is presented. The front-end comprises a charge sensitive amplifier and a four-stage semi-Gaussian pulse-shaping amplifier. The chip was custom synthesized with an analog synthesis environment. With a power consumption of only 10 mW and a chip area less than 1 mm2, the chip is very well suited for the stringent demands in space applications. Measurements show a peaking time of 1.2 micros and a total equivalent noise charge of less than 1000 erms-. Although a standard 0.7-microm CMOS was used, little performance degradation was observed after exposure to a total dose irradiation of 50 kRad. All tested chips fully recovered within specifications, after 24 h of annealing at room temperature

  4. Development of plasmonic isolator for integration into photonic integrated circuits (Presentation Recording)

    Science.gov (United States)

    Zayets, Vadym; Saito, Hidekazu; Ando, Koji; Yuasa, Shinji

    2015-09-01

    An optical isolator is an important component of an optical network. At present, there is a significant commercial demand for an optical isolator, which can be integrated into the Photonic Integrated Circuits (PIC). A new design of an integrated optical isolator, which utilizes unique non-reciprocal properties of surface plasmons, has been proposed [1]. The main obstacle for a practical realization of the proposed design is a substantial propagation loss of the surface plasmons in structures containing a ferromagnetic metal. The reduction of the propagation loss of a surface plasmon is the key to make the plasmonic isolator competitive with other designs of the integrated isolator. We studied experimentally optical and magneto-optical properties of a Fe plasmonic waveguide integrated with an AlGaAs rib waveguides and a Co plasmonic waveguide integrated with Si nanowire waveguides. It was demonstrated experimentally that by utilizing a double-dielectric plasmonic waveguide it is possible to reduce significantly the optical loss in a plasmonic waveguide. For Fe/SiO2/AlGaAs double-dielectric plasmonic waveguide the low optical loss of 0.03 dB/um is obtained. As far as we know at present it is a lowest optical loss demonstrated for a plasmon propagating at a surface of a ferromagnetic metal. For Co/Ti2O3/SiO2 double-dielectric plasmonic waveguide integrated with a Si nanowire waveguide on a Si substrate the optical loss of 0.7 dB/um was demonstrated. The designs of the plasmonic isolator utilizing a ring resonator or a non-reciprocal coupler were studied. [1] V. Zayets, H. Saito, S. Yuasa, and K. Ando,, Materials 5, 857 (2012).

  5. A BIST GENERATOR CAD TOOL FOR NUMERIC INTEGRATED CIRCUITS

    Directory of Open Access Journals (Sweden)

    Chiraz Khedhiri

    2011-06-01

    Full Text Available This paper describes a training and research tool for learning basic issues related to BIST (Built-In Self-Test generator. The main didactic aim of the tool is presenting complicated concepts in a comprehensive graphical and analytical way. The paper describes a computer-aided design (CAD that is used to generate automatically the BIST to any digital circuit. This software technique attempts to reduce the amount of extra hardware and cost of the circuit.In order to make our software being easily available, we used the Java platform, which is supported by most operating systems. The multi-platform JAVA run time environment allows for easy access and usage of the tool.

  6. High-speed Integrated Circuits for electrical/Optical Interfaces

    DEFF Research Database (Denmark)

    Jespersen, Christoffer Felix

    2008-01-01

    This thesis is a continuation of the effort to increase the bandwidth of communicationnetworks. The thesis presents the results of the design of several high-speed electrical ircuits for an electrical/optical interface. These circuits have been a contribution to the ESTA project in collaboration...... with the OptCom project. The aim of the ESTA project was to investigate issues at 100 Gb/s and beyond, such as architecture and components. The OptCom project had a more tangible purpose; to create a 100 Gb/s optical/electrical transceiver demonstrator. The thesis focuses on the design of VCO, LA and...... process represents the avant-garde of InP technology, with ft and fmax well above 300 GHz. Principles of high speed design are presented and described as a useful background before proceeding to circuits. A static divider is used as an example to illustrate many of the design principles. Theory and...

  7. Cryogenic readout integrated circuits for submillimeter-wave camera

    International Nuclear Information System (INIS)

    The development of cryogenic readout circuits for Superconducting Tunneling Junction (Sj) direct detectors for submillimeter wave is presented. A SONY n-channel depletion-mode GaAs Junction Field Effect Transistor (JFET) is a candidate for circuit elements of the preamplifier. We measured electrical characteristics of the GaAs JFETs in the temperature range between 0.3 and 4.2K, and found that the GaAs JFETs work with low power consumption of a few microwatts, and show good current-voltage characteristics without cryogenic anomalies such as kink phenomena or hysteresis behaviors. Furthermore, measurements at 0.3K show that the input referred noise is as low as 0.6μV/Hz at 1Hz. Based on these results and noise calculations, we estimate that a Capacitive Transimpedance Amplifier with the GaAs JFETs will have low noise and STJ detectors will operate below background noise limit

  8. Assessment of Lightning Shielding Performance of a 400 kV Double-Circuit Fully Composite Pylon

    DEFF Research Database (Denmark)

    Jahangirl, Tohid; Bak, Claus Leth; Silva, Filipe Miguel Faria da;

    2016-01-01

    and therefore, the lightning shielding of pylon requires a ground potential access to shield wires which can be achieved by utilizing ground cable inside the hollow cross-arm and pylon body. However, efficient assigning of lightning shielding system for the fully composite pylon is one of the major...... electro-geometric model (EGM) to improve the lightning performance of the pylon....

  9. A Trainable Neuromorphic Integrated Circuit that Exploits Device Mismatch

    OpenAIRE

    Thakur, Chetan Singh; Wang, Runchun; Hamilton, Tara Julia; Tapson, Jonathan; van Schaik, Andre

    2015-01-01

    Random device mismatch that arises as a result of scaling of the CMOS (complementary metal-oxide semi-conductor) technology into the deep submicron regime degrades the accuracy of analogue circuits. Methods to combat this increase the complexity of design. We have developed a novel neuromorphic system called a Trainable Analogue Block (TAB), which exploits device mismatch as a means for random projections of the input to a higher dimensional space. The TAB framework is inspired by the princip...

  10. Integrated optical and electronic interconnect printed circuit board manufacturing

    OpenAIRE

    Selviah, D. R.; Fernández, F. A.; Papakonstantinou, I.; Wang, K.; Bagshiahi, H.; Walker, A. C.; McCarthy, A.; Suyal, H; Hutt, D.A.; Conway, P. P.; Chappell, J.; Zakariyah, S. S.; Milward, D

    2008-01-01

    Introduction: At high bit rates copper tracks in printed circuit boards (PCBs) suffer severe loss and pulse distortion due to radiation of electromagnetic waves, dispersion and bandwidth limitations. The loss can be overcome to some extent by transmitting higher power pulses and by changing the dielectric constant and loss tangent of the PCB substrate material. However, high power pulses consume power and can cause electro-migration which reduces the board lifetime, although the copper tracks...

  11. A novel fully-integrated miniature six-axis force/torque sensor

    Institute of Scientific and Technical Information of China (English)

    Wang Jiali; Xie Zongwu; Liu Hong; Jiang Li; Gao Xiaohui

    2006-01-01

    This paper presents a new designed miniature six DOF (degree of freedom) force/torque sensor.This sensor is fully integrated with a micro DSP (digital signal processor), so all the signal conditioning,A/D, decoupling, digital-signals serial output are performed in the sensor. Some experimental results are presented to demonstrate the capability of the proposed design. Finally, a neural network was used for decoupling the interacting signals, compared with the conventional method using the inverse matrix, this new method is more accurate.

  12. Fully transparent quantum dot light-emitting diode integrated with graphene anode and cathode.

    Science.gov (United States)

    Seo, Jung-Tak; Han, Junebeom; Lim, Taekyung; Lee, Ki-Heon; Hwang, Jungseek; Yang, Heesun; Ju, Sanghyun

    2014-12-23

    A fully transparent quantum dot light-emitting diode (QD-LED) was fabricated by incorporating two types (anode and cathode) of graphene-based electrodes, which were controlled in their work functions and sheet resistances. Either gold nanoparticles or silver nanowires were inserted between layers of graphene to control the work function, whereas the sheet resistance was determined by the number of graphene layers. The inserted gold nanoparticles or silver nanowires in graphene films caused a charge transfer and changed the work function to 4.9 and 4.3 eV, respectively, from the original work function (4.5 eV) of pristine graphene. Moreover the sheet resistance values for the anode and cathode electrodes were improved from ∼63,000 to ∼110 Ω/sq and from ∼100,000 to ∼741 Ω/sq as the number of graphene layers increased from 1 to 12 and from 1 to 8, respectively. The main peak wavelength, luminance, current efficiency, and optical transmittance of the fully transparent QD-LED integrated with graphene anode and cathode were 535 nm, ∼358 cd/m2, ∼0.45 cd/A, and 70-80%, respectively. The findings of the study are expected to lay a foundation for the production of high-efficiency, fully transparent, and flexible displays using graphene-based electrodes. PMID:25426762

  13. Note: Fully integrated 3.2 Gbps quantum random number generator with real-time extraction

    Science.gov (United States)

    Zhang, Xiao-Guang; Nie, You-Qi; Zhou, Hongyi; Liang, Hao; Ma, Xiongfeng; Zhang, Jun; Pan, Jian-Wei

    2016-07-01

    We present a real-time and fully integrated quantum random number generator (QRNG) by measuring laser phase fluctuations. The QRNG scheme based on laser phase fluctuations is featured for its capability of generating ultra-high-speed random numbers. However, the speed bottleneck of a practical QRNG lies on the limited speed of randomness extraction. To close the gap between the fast randomness generation and the slow post-processing, we propose a pipeline extraction algorithm based on Toeplitz matrix hashing and implement it in a high-speed field-programmable gate array. Further, all the QRNG components are integrated into a module, including a compact and actively stabilized interferometer, high-speed data acquisition, and real-time data post-processing and transmission. The final generation rate of the QRNG module with real-time extraction can reach 3.2 Gbps.

  14. A fully integrated 3.5 GHz CMOS differential power amplifier driver

    Science.gov (United States)

    Xiaodong, Xu; Haigang, Yang; Tongqiang, Gao; Hongfeng, Zhang

    2013-07-01

    A fully integrated CMOS differential power amplifier driver (PAD) is proposed for WiMAX applications. In order to fulfill the differential application requirements, a transmission line transformer is used as the output matching network. A differential inductance constitutes an inter-stage matching network. Meanwhile, an on chip balun realizes input matching as well as single-end to differential conversion. The PAD is fabricated in a 0.13 μm RFCMOS process. The chip size is 1.1 × 1.1 mm2 with all of the matching network integrated on chip. The saturated power is around 10 dBm and power gain is about 12 dB.

  15. Fully Integrated Approach to Compute Vibrationally Resolved Optical Spectra: From Small Molecules to Macrosystems.

    Science.gov (United States)

    Barone, Vincenzo; Bloino, Julien; Biczysko, Malgorzata; Santoro, Fabrizio

    2009-03-10

    A general and effective time-independent approach to compute vibrationally resolved electronic spectra from first principles has been integrated into the Gaussian computational chemistry package. This computational tool offers a simple and easy-to-use way to compute theoretical spectra starting from geometry optimization and frequency calculations for each electronic state. It is shown that in such a way it is straightforward to combine calculation of Franck-Condon integrals with any electronic computational model. The given examples illustrate the calculation of absorption and emission spectra, all in the UV-vis region, of various systems from small molecules to large ones, in gas as well as in condensed phases. The computational models applied range from fully quantum mechanical descriptions to discrete/continuum quantum mechanical/molecular mechanical/polarizable continuum models. PMID:26610221

  16. CMOS readout integrated circuit involving pixel-level ADC for microbolometer FPAs

    Science.gov (United States)

    Hwang, C. H.; Kwon, I. W.; Lee, Y. S.; Lee, H. C.

    2008-04-01

    The function of most readout integrated circuits (ROIC) for microbolometer focal plane arrays (FPAs) is supplying a bias voltage to a microbolometer of each pixel, integrating the current of a microbolometer, and transferring the signals from pixels to the output of a chip. However, the scale down of CMOS technology allows the integration of other functions. In this paper, we proposed a CMOS ROIC involving a pixel-level analog-to-digital converter (ADC) for 320 × 240 microbolometer FPAs. Such integration would improve the performance of a ROIC at the reduced system cost and power consumption. The noise performance of a microbolometer is improved by using the pixelwise readout structure because integration time can be increased up to 1ms. A Pixel circuit is consisted of a background skimming circuit, a differential amplifier, an integration capacitor and a 10-bit DRAM. First, the microbolometer current is integrated for 1ms after the skimming current correction. The differential amplifier operates as an op-Amp and the integration capacitor makes negative feedback loop between an output and a negative input of the op-Amp. And then, the integrated signal voltage is converted to digital signals using a modified single slope ADC in a pixel when the differential amplifier operates as a comparator and the 10-bit DRAM stores values of a counter. This readout circuit is designed and fabricated using a standard 0.35μm 2-poly 3-metal CMOS technology.

  17. Implementing the theories: A fully integrated project control system that's implemented and works

    International Nuclear Information System (INIS)

    Using the theories presented in DOE Orders 4700.1, 1332.1A, and Notice 4700.5 as the basis for system design, the Fernald Environmental Restoration Management Corporation (FERMCO) has developed and implemented a Project Control System (PCS) that complies with requirements and provides DOE and FERMCO management with timely performance measurement information. To this extent, the FERMCO PCS probably is similar to the systems of the majority of the contractors in the DOE complex. In fact. this facet of the FERMCO PCS generally mirrors those used on projects around the world by FERMCO's parent company, Fluor Daniel. Starting with this open-quotes platformclose quotes, the vision and challenge of creating a fully integrated system commenced. An open-architecture systems approach is the factor that most greatly influenced and enabled the successful development and implementation of the Project Control System for the Fernald Environmental Management Project. All aspects of a fully integrated system were considered during the design phase. The architecture of the FERMCO system enables seamless, near real-time, transfer of data both from and to the Project Control System with all other related systems. The primary systems that provide and share data with the Project Control System include those used by the Payroll, Accounting, Procurement, and Human Resources organizations. To enable data linking with these organizations, the resource codes were designed to map many-to-one from their detailed codes to the summarized codes used in the PCS

  18. Scalable Integration of Long-Lived Quantum Memories into a Photonic Circuit

    Science.gov (United States)

    Mouradian, Sara L.; Schröder, Tim; Poitras, Carl B.; Li, Luozhou; Goldstein, Jordan; Chen, Edward H.; Walsh, Michael; Cardenas, Jaime; Markham, Matthew L.; Twitchen, Daniel J.; Lipson, Michal; Englund, Dirk

    2015-07-01

    We demonstrate a photonic circuit with integrated long-lived quantum memories. Precharacterized quantum nodes—diamond microwaveguides containing single, stable, negatively charged nitrogen-vacancy centers—are deterministically integrated into low-loss silicon nitride waveguides. These quantum nodes efficiently couple into the single-mode waveguides with >1 Mcps collected into the waveguide, have narrow single-scan linewidths below 400 MHz, and exhibit long electron spin coherence times up to 120 μ s . Our system facilitates the assembly of multiple quantum nodes with preselected properties into a photonic integrated circuit with near unity yield, paving the way towards the scalable fabrication of quantum information processors.

  19. In-situ fabrication of flexible vertically integrated electronic circuits by inkjet printing

    International Nuclear Information System (INIS)

    In this paper, a facile approach for fabricating flexible vertically integrated electronic circuits is demonstrated. A desktop inkjet printer was modified and employed to print silver precursor on a polymer-coated buffer substrates. In-situ reaction was taken place and a conducting line was formed without need of a high temperature treatment. Through this process, several layers of metal integrated circuits were deposited sequentially with polymer buffer layers sandwiched between each layer. Hence, vertically integrated electronic components of diodes, solar cells, flexible flat panel displays, and electrochromic devices can be built with this simple and low-cost technique.

  20. 2D and 3D heterogeneous photonic integrated circuits

    Science.gov (United States)

    Yoo, S. J. Ben

    2014-03-01

    Exponential increases in the amount of data that need to be sensed, communicated, and processed are continuing to drive the complexity of our computing, networking, and sensing systems. High degrees of integration is essential in scalable, practical, and cost-effective microsystems. In electronics, high-density 2D integration has naturally evolved towards 3D integration by stacking of memory and processor chips with through-silicon-vias. In photonics, too, we anticipate highdegrees of 3D integration of photonic components to become a prevailing method in realizing future microsystems for information and communication technologies. However, compared to electronics, photonic 3D integration face a number of challenges. This paper will review two methods of 3D photonic integration --- fs laser inscription and layer stacking, and discuss applications and future prospects.

  1. Heat management in integrated circuits on-chip and system-level monitoring and cooling

    CERN Document Server

    Ogrenci-Memik, Seda

    2016-01-01

    This essential overview covers the subject of thermal monitoring and management in integrated circuits. Specifically, it focuses on devices and materials that are intimately integrated on-chip (as opposed to in-package or on-board) for the purposes of thermal monitoring and thermal management.

  2. Rapid mapping of digital integrated circuit logic gates via multi-spectral backside imaging

    CERN Document Server

    Adato, Ronen; Zangeneh, Mahmoud; Zhou, Boyou; Joshi, Ajay; Goldberg, Bennett; Unlu, M Selim

    2016-01-01

    Modern semiconductor integrated circuits are increasingly fabricated at untrusted third party foundries. There now exist myriad security threats of malicious tampering at the hardware level and hence a clear and pressing need for new tools that enable rapid, robust and low-cost validation of circuit layouts. Optical backside imaging offers an attractive platform, but its limited resolution and throughput cannot cope with the nanoscale sizes of modern circuitry and the need to image over a large area. We propose and demonstrate a multi-spectral imaging approach to overcome these obstacles by identifying key circuit elements on the basis of their spectral response. This obviates the need to directly image the nanoscale components that define them, thereby relaxing resolution and spatial sampling requirements by 1 and 2 - 4 orders of magnitude respectively. Our results directly address critical security needs in the integrated circuit supply chain and highlight the potential of spectroscopic techniques to addres...

  3. Thermal Sizing of Printed Circuit Steam Generator for Integral Reactor

    International Nuclear Information System (INIS)

    SMART aims at achieving enhanced safety and improved economics; the enhancement of safety and reliability is realized by incorporating inherent safety-improving features and reliable passive safety systems. The improvement in the economics is achieved through a system simplification, component modularization, reduction of construction time, and high plant availability. The standard design approval assures the safety of the SMART system. The capital cost of the major plant equipment has a significant effect on the overall economics of the nuclear plant. Minimizing the cost of manufacturing of the nuclear plant components is important to reduce the cost of the reactor. It is necessary to reduce the size of the steam generator in order to design a smaller reactor vessel, which is substantial for the overall construction cost, with the required thermal capacity preserved. The Printed Circuit Heat Exchanger is a type of compact heat exchangers that provides high power density along with a low pressure drop and reduced maintenance requirements. This paper describes the approach we used while determining the size of the Printed Circuit Steam Generator (PCSG) and resultant smaller reactor vessel. Thermal hydraulic and geometric parameters for the PCSG were studied. The results show that the overall volume of the steam generator can be significantly reduced. On the basis of this calculation, we can design a smaller reactor vessel with the PCSG

  4. The single-event effect evaluation technology for nano integrated circuits

    International Nuclear Information System (INIS)

    Single-event effects of nano scale integrated circuits are investigated. Evaluation methods for single-event transients, single-event upsets, and single-event functional interrupts in nano circuits are summarized and classified in detail. The difficulties in SEE testing are discussed as well as the development direction of test technology, with emphasis placed on the experimental evaluation of a nano circuit under heavy ion, proton, and laser irradiation. The conclusions in this paper are based on many years of testing at accelerator facilities and our present understanding of the mechanisms for SEEs, which have been well verified experimentally. (paper)

  5. A circuit method to integrate metamaterial and graphene in absorber design

    Science.gov (United States)

    Wang, Zuojia; Zhou, Min; Lin, Xiao; Liu, Huixia; Wang, Huaping; Yu, Faxin; Lin, Shisheng; Li, Erping; Chen, Hongsheng

    2014-10-01

    We theoretically investigate a circuit analog approach to integrate graphene and metamaterial in electromagnetic wave absorber design. In multilayer graphene-metamaterial (GM) absorbers, ultrathin metamaterial elements are theoretically modeled as equivalent loads which attached to the junctions between two transmission lines. Combining with the benefits of tunable chemical potential in graphene, an optimized GM absorber is proposed as a proof of the circuit method. Numerical simulation results demonstrate the effectiveness of the circuit analytical model. The operating frequency of the GM absorber can be varied in terahertz frequency, indicating the potential applications of the GM absorber in sensors, modulators, and filters.

  6. Precision Instrumentation Amplifiers and Read-Out Integrated Circuits

    CERN Document Server

    Wu, Rong; Makinwa, Kofi A A

    2013-01-01

    This book presents innovative solutions in the design of precision instrumentation amplifier and read-out ICs, which can be used to boost millivolt-level signals transmitted by modern sensors, to levels compatible with the input ranges of typical Analog-to-Digital Converters (ADCs).  The discussion includes the theory, design and realization of interface electronics for bridge transducers and thermocouples. It describes the use of power efficient techniques to mitigate low frequency errors, resulting in interface electronics with high accuracy, low noise and low drift. Since this book is mainly about techniques for eliminating low frequency errors, it describes the nature of these errors and the associated dynamic offset cancellation techniques used to mitigate them.  Surveys comprehensively offset cancellation and accuracy improvement techniques applied in precision amplifier designs; Presents techniques in precision circuit design to mitigate low frequency errors in millivolt-level signals transmitted by ...

  7. Single-Chip Fully Integrated Direct-Modulation CMOS RF Transmitters for Short-Range Wireless Applications

    OpenAIRE

    M. Jamal Deen; Mohammed BenSaleh; Syed Manzoor Qasim; El-Desouki, Munir M.

    2013-01-01

    Ultra-low power radio frequency (RF) transceivers used in short-range application such as wireless sensor networks (WSNs) require efficient, reliable and fully integrated transmitter architectures with minimal building blocks. This paper presents the design, implementation and performance evaluation of single-chip, fully integrated 2.4 GHz and 433 MHz RF transmitters using direct-modulation power voltage-controlled oscillators (PVCOs) in addition to a 2.0 GHz phase-locked loop (PLL) based tra...

  8. Detection of orbital angular momentum using a photonic integrated circuit

    OpenAIRE

    Guanghao Rui; Bing Gu; Yiping Cui; Qiwen Zhan

    2016-01-01

    Orbital angular momentum (OAM) state of photons offer an attractive additional degree of freedom that has found a variety of applications. Measurement of OAM state, which is a critical task of these applications, demands photonic integrated devices for improved fidelity, miniaturization, and reconfiguration. Here we report the design of a silicon-integrated OAM receiver that is capable of detecting distinct and variable OAM states. Furthermore, the reconfiguration capability of the detector i...

  9. Fully integrated time-to-amplitude converter for multidimensional TCSPC applications

    Science.gov (United States)

    Crotti, Matteo; Rech, Ivan; Ghioni, Massimo; Labanca, Ivan

    2011-06-01

    Over the past years an always growing interest has arisen about the measurement technique of time-correlated single photon counting (TCSPC), since it allows the analysis of extremely fast and weak light waveforms with a picoseconds resolution. Consequently, many applications exploiting TCSPC have been developing in several fields such as medicine and chemistry. Moreover, the use of multianode PMT and of single photon avalanche diode arrays led to the development of multichannel acquisition systems, employed in even more applications. Since TCSPC basically consists of the measurement of the arrival time of a photon, a high resolution and high linearity time measurement block is of the utmost importance, and in order to realize multidimensional systems, it has to be integrated to reduce both cost and area. We have designed and fabricated a 4 channel fully integrated time-to-amplitude converter (TAC), built in 0.35 μm Si-Ge technology, characterized by a very good time resolution (less than 50 ps), low differential nonlinearity (better than 2% peak-peak and less than 0.1% rms), high counting rate (16 MHz), low and constant power dissipation (50 mW), and low area occupation (2.58x1.28 mm2). Moreover our measurements show a very little crosstalk between the converters integrated on the same chip; this feature together with low power and low area make the fabricated converter suitable for parallelization, so it can be the starting point for future large scale multi-channel acquisition chains.

  10. Object Orientated Programmable Integrated Circuit (OOPIC) upgrade and evaluation for Autonomous Ground Vehicle (AGV)

    OpenAIRE

    Hoffman, Andrew J.

    2006-01-01

    A small, low-power Object-Oriented Programmable integrated circuit (OOPic) microcontroller was integrated and tested with the architecture for an autonomous ground vehicle (AGV). Sensors with the OOPic, and the XBee Wireless Suite were included in the integration. Tests were conducted, including range and time operation analysis for wireless communications for comparison with the legacy BL2000 microcontroller. Results demonstrated long battery life for the electronics of the robot, as well as...

  11. Micromorph silicon tandem solar cells with fully integrated 3D photonic crystal intermediate reflectors

    Science.gov (United States)

    Üpping, J.; Bielawny, A.; Fahr, S.; Rockstuhl, C.; Lederer, F.; Steidl, L.; Zentel, R.; Beckers, T.; Lambertz, A.; Carius, R.; Wehrspohn, R. B.

    2010-05-01

    A 3D photonic intermediate reflector for textured micromorph silicon tandem solar cells has been investigated. In thin-film silicon tandem solar cells consisting of amorphous and microcrystalline silicon with two junctions of a-Si/c-Si, efficiency enhancements can be achieved by increasing the current density in the a-Si top cell providing an optimized current matching at high current densities. For an ideal photon-management between top and bottom cell, a spectrally-selective intermediate reflective layer (IRL) is necessary. We present the first fully-integrated 3D photonic thin-film IRL device incorporated on a planar substrate. Using a ZnO inverted opal structure the external quantum efficiency of the top cell in the spectral region of interest could be enhanced. As an outlook we present the design and the preparation of a 3D self organized photonic crystal structure in a textured micromorph tandem solar cell.

  12. Fully integrated micro-separator with soft-magnetic micro-pillar arrays for filtrating lymphocytes.

    Science.gov (United States)

    Dong, Tao; Su, Qianhua; Yang, Zhaochu; Karlsen, Frank; Jakobsen, Henrik; Egeland, Eirik Bentzen; Hjelseth, Snorre

    2010-01-01

    A fully integrated micro-separator with soft-magnetic micro-pillar arrays has been developed, which merely employs one independent Lab-On-Chip to realize the lymphocytes isolation from the human whole blood. The simulation, fabrication and experiment are executed to realize this novel microseparator. The simulation results show that, the soft-magnetic micro-pillars array can amplify and redistribute the electromagnetic field generated by the microcoils. The tests certify desirable separation efficiency can be realized using this new separator at low current. No extra cooling system is required for such a micro-separator. This micro-separator can also be used to separate other target cells or particles with the same principle. PMID:21096497

  13. Detection of orbital angular momentum using a photonic integrated circuit

    Science.gov (United States)

    Rui, Guanghao; Gu, Bing; Cui, Yiping; Zhan, Qiwen

    2016-01-01

    Orbital angular momentum (OAM) state of photons offer an attractive additional degree of freedom that has found a variety of applications. Measurement of OAM state, which is a critical task of these applications, demands photonic integrated devices for improved fidelity, miniaturization, and reconfiguration. Here we report the design of a silicon-integrated OAM receiver that is capable of detecting distinct and variable OAM states. Furthermore, the reconfiguration capability of the detector is achieved by applying voltage to the GeSe film to form gratings with alternate states. The resonant wavelength for arbitrary OAM state is demonstrated to be tunable in a quasi-linear manner through adjusting the duty cycle of the gratings. This work provides a viable approach for the realization of a compact integrated OAM detection device with enhanced functionality that may find important applications in optical communications and information processing with OAM states. PMID:27321916

  14. Pixelwise readout integrated circuits with pixel-level ADC for microbolometers

    Science.gov (United States)

    Hwang, C. H.; Kim, C. B.; Lee, Y. S.; Yu, B. G.; Lee, H. C.

    2007-04-01

    Pixelwise integrated circuits involving a pixel-level analog-to-digital converter (ADC) are studied for 320 × 240 microbolometer focal plane arrays (FPAs). It is necessary to use the pixelwise readout architecture for decreasing the thermal noise. However, it is hard to locate a sufficiently large integration capacitor in a unit pixel of FPAs because of the area limitation. To effectively overcome this problem, a two step integration method is proposed. First, after integrating the current of the microbolometer for 32μs, upper 5bits of the 13bit digital signal are output through a pixel-level ADC. Then, the current of the microbolometer is integrated during 1ms after the skimming current correction using upper 5bits in a field-programmable gate array (FPGA), and then lower 8bits are obtained through a pixel-level ADC. Finally, upper 5bits and lower 8bits are combined into the digital image signal after the gain and offset correction in digital signal processor (DSP) Each 2×2 pixel shares an readout circuit, including a current-mode background skimming circuit, an operational amplifier(op-Amp), an integration capacitor and a single slope ADC. When the current of a microbolometer is integrated, the integration capacitor is connected between a negative input and an output of the op-Amp. Therefore a capacitive transimpedance amplifier (CTIA) has been employed as the input circuit of the microbolometer. When the output of a microbolometer is converted to digital signal, the Op-Amp is used as a comparator of the single slope ADC. This readout circuit is designed to achieve 35×35μm2 pixel size in 0.35μm 2-poly 3-metal CMOS technology.

  15. Wafer-level testing and test during burn-in for integrated circuits

    CERN Document Server

    Bahukudumbi, Sudarshan

    2010-01-01

    Wafer-level testing refers to a critical process of subjecting integrated circuits and semiconductor devices to electrical testing while they are still in wafer form. Burn-in is a temperature/bias reliability stress test used in detecting and screening out potential early life device failures. This hands-on resource provides a comprehensive analysis of these methods, showing how wafer-level testing during burn-in (WLTBI) helps lower product cost in semiconductor manufacturing.Engineers learn how to implement the testing of integrated circuits at the wafer-level under various resource constrain

  16. Integrated Circuit Interconnect Lines on Lossy Silicon Substrate with Finite Element Method

    Directory of Open Access Journals (Sweden)

    Sarhan M. Musa,

    2014-01-01

    Full Text Available The silicon substrate has a significant effect on the inductance parameter of a lossy interconnect line on integrated circuit. It is essential to take this into account in determining the transmission line electrical parameters. In this paper, a new quasi-TEM capacitance and inductance analysis of multiconductor multilayer interconnects is successfully demonstrated using finite element method (FEM. We specifically illustrate the electrostatic modeling of single and coupled interconnected lines on a silicon-silicon oxide substrate. Also, we determine the quasi-static spectral for the potential distribution of the silicon-integrated circuit.

  17. Relay Protection and Automation Systems Based on Programmable Logic Integrated Circuits

    International Nuclear Information System (INIS)

    One of the most promising forms of developing the apparatus part of relay protection and automation devices is considered. The advantages of choosing programmable logic integrated circuits to obtain adaptive technological algorithms in power system protection and control systems are pointed out. The technical difficulties in the problems which today stand in the way of using relay protection and automation systems are indicated and a new technology for solving these problems is presented. Particular attention is devoted to the possibility of reconfiguring the logic of these devices, using programmable logic integrated circuits

  18. Experimental Demonstration of 7 Tb/s Switching Using Novel Silicon Photonic Integrated Circuit

    DEFF Research Database (Denmark)

    Ding, Yunhong; Kamchevska, Valerija; Dalgaard, Kjeld;

    2016-01-01

    We demonstrate BER performance <10^-9 for a 1 Tb/s/core transmission over 7-core fiber and SDM switching using a novel silicon photonic integrated circuit composed of a 7x7 fiber switch and low loss SDM couplers.......We demonstrate BER performance <10^-9 for a 1 Tb/s/core transmission over 7-core fiber and SDM switching using a novel silicon photonic integrated circuit composed of a 7x7 fiber switch and low loss SDM couplers....

  19. System and method for interfacing large-area electronics with integrated circuit devices

    Energy Technology Data Exchange (ETDEWEB)

    Verma, Naveen; Glisic, Branko; Sturm, James; Wagner, Sigurd

    2016-07-12

    A system and method for interfacing large-area electronics with integrated circuit devices is provided. The system may be implemented in an electronic device including a large area electronic (LAE) device disposed on a substrate. An integrated circuit IC is disposed on the substrate. A non-contact interface is disposed on the substrate and coupled between the LAE device and the IC. The non-contact interface is configured to provide at least one of a data acquisition path or control path between the LAE device and the IC.

  20. Readout integrated circuit for microbolometer with an analog non-uniformity correction

    Science.gov (United States)

    Hwang, C. H.; Woo, D. H.; Lee, Y. S.; Lee, H. C.

    2005-10-01

    We have developed a microbolometer readout integrated circuit (ROIC) that corrects the non-uniformity in analog operation and acts in both normal mode and edge detection mode. A capacitive transimpedance amplifier (CTIA) has been employed as the input circuit of the microbolometer. Generally, when fabricating microbolometer focal plane arrays (FPAs), offset-error and gain-error in the inter-microbolometer are induced by fabrication error. They are shown as fixed pattern noise (FPN) in the infrared image. In the present study, a circuit correcting the offset-error and the gain-error in the normal mode by controlling the bias and the integration capacitance of the CTIA is proposed. This circuit does not require an additional DSP chip, and the non-uniformity is corrected before the analog to digital conversion (ADC). Thus, it can utilize 3-4 bits lower ADC compared to the conventional readout circuit. In the edge detection mode, after correcting the gain-error in two adjacent pixels, edge detection can be realized by subtracting their signal without the DSP. We have designed the suggested circuit to output a 10bit level effective infrared signal using 0.35um 2-poly 3-metal CMOS technology.

  1. An adjustable RF tuning element for microwave, millimeter wave, and submillimeter wave integrated circuits

    Science.gov (United States)

    Lubecke, Victor M.; Mcgrath, William R.; Rutledge, David B.

    1991-01-01

    Planar RF circuits are used in a wide range of applications from 1 GHz to 300 GHz, including radar, communications, commercial RF test instruments, and remote sensing radiometers. These circuits, however, provide only fixed tuning elements. This lack of adjustability puts severe demands on circuit design procedures and materials parameters. We have developed a novel tuning element which can be incorporated into the design of a planar circuit in order to allow active, post-fabrication tuning by varying the electrical length of a coplanar strip transmission line. It consists of a series of thin plates which can slide in unison along the transmission line, and the size and spacing of the plates are designed to provide a large reflection of RF power over a useful frequency bandwidth. Tests of this structure at 1 GHz to 3 Ghz showed that it produced a reflection coefficient greater than 0.90 over a 20 percent bandwidth. A 2 GHz circuit incorporating this tuning element was also tested to demonstrate practical tuning ranges. This structure can be fabricated for frequencies as high as 1000 GHz using existing micromachining techniques. Many commercial applications can benefit from this micromechanical RF tuning element, as it will aid in extending microwave integrated circuit technology into the high millimeter wave and submillimeter wave bands by easing constraints on circuit technology.

  2. Piezojunction effect in silicon integrated circuits and sensors

    CERN Document Server

    Fruett, Fabiano

    2002-01-01

    Mechanical stress affects the magnitude of base-emitter voltages of forward biased bipolar transistors. This phenomenon is called the piezojunction effect. The piezojunction effect is the main cause of inaccuracy and drift in integrated temperature sensors and bandgap voltage references.

  3. A UVLO Circuit in SiC Compatible with Power MOSFET Integration (pending entry)

    Energy Technology Data Exchange (ETDEWEB)

    Ericson, Milton Nance [ORNL; Frank, Steven Shane [ORNL; Glover, Dr. Michael [University of Arkansas; Britton, Charles [Oak Ridge National Laboratory (ORNL); Francis, Dr. Matt [University of Arkansas; Mantooth, Alan [University of Arkansas; Marlino, Laura D [ORNL; Mcnutt, Tyler [APEI, Inc.; Mudholkar, Dr. Mihir [University of Arkansas; Shepherd, Dr. Paul [University of Arkansas; Whitaker, Mr. Bret [APEI, Inc.; Barkley, Dr. Adam [APEI, Inc.; Lotstetter, Alex [APEI, Inc.

    2014-01-01

    The design and test of the first undervoltage lock-out circuit implemented in a low-voltage 4H silicon carbide process capable of single-chip integration with power MOSFETs is presented. The lock-out circuit, a block of the protection circuitry of a single-chip gate driver topology designed for use in a plug-in hybrid vehicle charger, was demonstrated to have rise/fall times compatible with a MOSFET switching speed of 250 kHz while operating over the targeted operating temperature range between 0 C and 200 C. Captured data show the circuit to be functional over a temperature range from -55 C to 300 C. The design of the circuit and test results is presented.

  4. A UVLO Circuit in SiC Compatible with Power MOSFET Integration

    Energy Technology Data Exchange (ETDEWEB)

    Glover, Michael [APEI, Inc.; Shepherd, Paul [APEI, Inc.; Francis, Matt [APEI, Inc.; Mudholkar, Dr. Mihir [University of Arkansas; Mantooth, Alan [University of Arkansas; Ericson, Milton Nance [ORNL; Frank, Steven [ORNL; Britton Jr, Charles L [ORNL; Marlino, Laura D [ORNL; Mcnutt, Tyler [APEI, Inc.; Barkley, Dr. Adam [APEI, Inc.; Whitaker, Mr. Bret [APEI, Inc.; Lostetter, Dr. Alex [APEI, Inc.

    2014-01-01

    The design and test of the first undervoltage lock-out circuit implemented in a low voltage 4H silicon carbide process capable of single-chip integration with power MOSFETs is presented. The lock-out circuit, a block of the protection circuitry of a single-chip gate driver topology designed for use in a plug-in hybrid vehicle charger, was demonstrated to have rise/fall times compatible with a MOSFET switching speed of 250 kHz while operating over the targeted operating temperature range between 0 C and 200 C. Captured data shows the circuit to be functional over a temperature range from -55 C to 300 C. The design of the circuit and test results is presented.

  5. W-band Phased Array Systems using Silicon Integrated Circuits

    Science.gov (United States)

    Kim, Sang Young

    This thesis presents the silicon-based on-chip W-band phased array systems. An improved quadrature all-pass filter (QAF) and its implementation in 60--80 GHz active phase shifter using 0.13 microm SiGe BiCMOS technology is presented. It is demonstrated that with the inclusion of an Rs/R in the high Q branches of C and L, the sensitivity to the loading capacitance, therefore the I/Q phase and amplitude errors are minimized. This technique is especially suited for wideband millimeter-wave circuits where the loading capacitance (CL) is comparable to the filter capacitance (C). A prototype 60--80 GHz active phased shifter using the improved QAF is demonstrated. The overall chip size is 1.15 x 0.92 mm2 with the power consumption of 108 mW. The measured S11 and S22 are switches is demonstrated. The phase shifter is based on a low-pass pi-network. The chip size is 0.45 x 0.3 mm2 without pads and consumes virtually no power. The measured S11 and S22 is 8 dBm and the simulated IIP3 is > 22 dBm. A low-power 76--84 GHz 4-element phased array receiver using the designed passive phase shifter is presented. The power consumption is minimized by using a single-ended design and alternating the amplifiers and phase shifter cells to result in a low noise figure at a low power consumption. A variable gain amplifier and the 11° phase shifter are used to correct for the rms gain and phase errors at different operating frequencies. The overall chip size is 2.0 x 2.7 mm2 with the current consumption of 18 mA/channel with 1.8 V supply voltage. The measured S11 and S 22 is chip coupling is circuits are designed differentially to result in less sensitivity to packaging effect and high channel-to-channel isolation. The overall chip size is 5.0 x 5.8 mm 2 with the power consumption of 500--600 mA from 2 V supply voltage. The measured S11 and S22 for all 16 phase states is 10 dB for 76.4--90 GHz with the rms gain error of -45 dB. The measured NF is 11.2--13 dB at 77--87 GHz at the maximum

  6. Fully integrated system-on-chip for pixel-based 3D depth and scene mapping

    Science.gov (United States)

    Popp, Martin; De Coi, Beat; Thalmann, Markus; Gancarz, Radoslav; Ferrat, Pascal; Dürmüller, Martin; Britt, Florian; Annese, Marco; Ledergerber, Markus; Catregn, Gion-Pol

    2012-03-01

    We present for the first time a fully integrated system-on-chip (SoC) for pixel-based 3D range detection suited for commercial applications. It is based on the time-of-flight (ToF) principle, i.e. measuring the phase difference of a reflected pulse train. The product epc600 is fabricated using a dedicated process flow, called Espros Photonic CMOS. This integration makes it possible to achieve a Quantum Efficiency (QE) of >80% in the full wavelength band from 520nm up to 900nm as well as very high timing precision in the sub-ns range which is needed for exact detection of the phase delay. The SoC features 8x8 pixels and includes all necessary sub-components such as ToF pixel array, voltage generation and regulation, non-volatile memory for configuration, LED driver for active illumination, digital SPI interface for easy communication, column based 12bit ADC converters, PLL and digital data processing with temporary data storage. The system can be operated at up to 100 frames per second.

  7. Note: Fully integrated time-to-amplitude converter in Si-Ge technology

    Science.gov (United States)

    Crotti, M.; Rech, I.; Ghioni, M.

    2010-10-01

    Over the past years an always growing interest has arisen about the measurement technique of time-correlated single photon counting TCSPC), since it allows the analysis of extremely fast and weak light waveforms with a picoseconds resolution. Consequently, many applications exploiting TCSPC have been developed in several fields such as medicine and chemistry. Moreover, the development of multianode PMT and of single photon avalanche diode arrays led to the realization of acquisition systems with several parallel channels to employ the TCSPC technique in even more applications. Since TCSPC basically consists of the measurement of the arrival time of a photon, the most important part of an acquisition chain is the time measurement block, which must have high resolution and low differential nonlinearity, and in order to realize multidimensional systems, it has to be integrated to reduce both cost and area. In this paper we present a fully integrated time-to-amplitude converter, built in 0.35 μm Si-Ge technology, characterized by a good time resolution (60 ps), low differential nonlinearity (better than 3% peak to peak), high counting rate (16 MHz), low and constant power dissipation (40 mW), and low area occupation (1.38×1.28 mm2).

  8. Fully automated and colorimetric foodborne pathogen detection on an integrated centrifugal microfluidic device.

    Science.gov (United States)

    Oh, Seung Jun; Park, Byung Hyun; Choi, Goro; Seo, Ji Hyun; Jung, Jae Hwan; Choi, Jong Seob; Kim, Do Hyun; Seo, Tae Seok

    2016-05-21

    This work describes fully automated and colorimetric foodborne pathogen detection on an integrated centrifugal microfluidic device, which is called a lab-on-a-disc. All the processes for molecular diagnostics including DNA extraction and purification, DNA amplification and amplicon detection were integrated on a single disc. Silica microbeads incorporated in the disc enabled extraction and purification of bacterial genomic DNA from bacteria-contaminated milk samples. We targeted four kinds of foodborne pathogens (Escherichia coli O157:H7, Salmonella typhimurium, Vibrio parahaemolyticus and Listeria monocytogenes) and performed loop-mediated isothermal amplification (LAMP) to amplify the specific genes of the targets. Colorimetric detection mediated by a metal indicator confirmed the results of the LAMP reactions with the colour change of the LAMP mixtures from purple to sky blue. The whole process was conducted in an automated manner using the lab-on-a-disc and a miniaturized rotary instrument equipped with three heating blocks. We demonstrated that a milk sample contaminated with foodborne pathogens can be automatically analysed on the centrifugal disc even at the 10 bacterial cell level in 65 min. The simplicity and portability of the proposed microdevice would provide an advanced platform for point-of-care diagnostics of foodborne pathogens, where prompt confirmation of food quality is needed. PMID:27112702

  9. An Overview of Solid-State Integrated Circuit Amplifiers in the Submillimeter-Wave and THz Regime

    OpenAIRE

    Samoska, Lorene A.

    2011-01-01

    We present an overview of solid-state integrated circuit amplifiers approaching terahertz frequencies based on the latest device technologies which have emerged in the past several years. Highlights include the best reported data from heterojunction bipolar transistor (HBT) circuits, high electron mobility transistor (HEMT) circuits, and metamorphic HEMT (mHEMT) amplifier circuits. We discuss packaging techniques for the various technologies in waveguide modules and describe the best reported...

  10. Fully Integrated Microfluidic Device for Direct Sample-to-Answer Genetic Analysis

    Science.gov (United States)

    Liu, Robin H.; Grodzinski, Piotr

    Integration of microfluidics technology with DNA microarrays enables building complete sample-to-answer systems that are useful in many applications such as clinic diagnostics. In this chapter, a fully integrated microfluidic device [1] that consists of microfluidic mixers, valves, pumps, channels, chambers, heaters, and a DNA microarray sensor to perform DNA analysis of complex biological sample solutions is present. This device can perform on-chip sample preparation (including magnetic bead-based cell capture, cell preconcentration and purification, and cell lysis) of complex biological sample solutions (such as whole blood), polymerase chain reaction, DNA hybridization, and electrochemical detection. A few novel microfluidic techniques were developed and employed. A micromix-ing technique based on a cavitation microstreaming principle was implemented to enhance target cell capture from whole blood samples using immunomagnetic beads. This technique was also employed to accelerate DNA hybridization reaction. Thermally actuated paraffin-based microvalves were developed to regulate flows. Electrochemical pumps and thermopneumatic pumps were integrated on the chip to provide pumping of liquid solutions. The device is completely self-contained: no external pressure sources, fluid storage, mechanical pumps, or valves are necessary for fluid manipulation, thus eliminating possible sample contamination and simplifying device operation. Pathogenic bacteria detection from ~mL whole blood samples and single-nucleotide polymorphism analysis directly from diluted blood were demonstrated. The device provides a cost-effective solution to direct sample-to-answer genetic analysis, and thus has a potential impact in the fields of point-of-care genetic analysis, environmental testing, and biological warfare agent detection.

  11. A microfabricated fringing field capacitive pH sensor with an integrated readout circuit

    Energy Technology Data Exchange (ETDEWEB)

    Arefin, Md Shamsul, E-mail: md.arefin@monash.edu; Redoute, Jean-Michel; Rasit Yuce, Mehmet [Electrical and Computer Systems Engineering, Monash University, Melbourne (Australia); Bulut Coskun, M.; Alan, Tuncay; Neild, Adrian [Mechanical and Aerospace Engineering, Monash University, Melbourne (Australia)

    2014-06-02

    This work presents a microfabricated fringe-field capacitive pH sensor using interdigitated electrodes and an integrated modulation-based readout circuit. The changes in capacitance of the sensor result from the permittivity changes due to pH variations and are converted to frequency shifts using a crossed-coupled voltage controlled oscillator readout circuit. The shift in resonant frequency of the readout circuit is 30.96 MHz for a change in pH of 1.0–5.0. The sensor can be used for the measurement of low pH levels, such as gastric acid, and can be integrated with electronic pills. The measurement results show high repeatability, low noise, and a stable output.

  12. A microfabricated fringing field capacitive pH sensor with an integrated readout circuit

    International Nuclear Information System (INIS)

    This work presents a microfabricated fringe-field capacitive pH sensor using interdigitated electrodes and an integrated modulation-based readout circuit. The changes in capacitance of the sensor result from the permittivity changes due to pH variations and are converted to frequency shifts using a crossed-coupled voltage controlled oscillator readout circuit. The shift in resonant frequency of the readout circuit is 30.96 MHz for a change in pH of 1.0–5.0. The sensor can be used for the measurement of low pH levels, such as gastric acid, and can be integrated with electronic pills. The measurement results show high repeatability, low noise, and a stable output.

  13. Geiger-Mode Avalanche Photodiode Arrays Integrated to All-Digital CMOS Circuits

    OpenAIRE

    Brian Aull

    2016-01-01

    This article reviews MIT Lincoln Laboratory's work over the past 20 years to develop photon-sensitive image sensors based on arrays of silicon Geiger-mode avalanche photodiodes. Integration of these detectors to all-digital CMOS readout circuits enable exquisitely sensitive solid-state imagers for lidar, wavefront sensing, and passive imaging.

  14. Geiger-Mode Avalanche Photodiode Arrays Integrated to All-Digital CMOS Circuits

    Science.gov (United States)

    Aull, Brian

    2016-01-01

    This article reviews MIT Lincoln Laboratory's work over the past 20 years to develop photon-sensitive image sensors based on arrays of silicon Geiger-mode avalanche photodiodes. Integration of these detectors to all-digital CMOS readout circuits enable exquisitely sensitive solid-state imagers for lidar, wavefront sensing, and passive imaging. PMID:27070609

  15. Experimental simulation of ionizing radiation effects on integrated circuits using ultra-short laser pulses

    International Nuclear Information System (INIS)

    This thesis presents the elaboration of an experimental test bench for integrated circuits by pulsed laser beam, to simulate the radiation effects on electronic components. A model of the interaction laser pulse and silicon has been developed. An electrical model of a MOS transistor transient response to an irradiation is proposed. The test bench automation is detailed. (A.L.B.)

  16. Geiger-Mode Avalanche Photodiode Arrays Integrated to All-Digital CMOS Circuits.

    Science.gov (United States)

    Aull, Brian

    2016-01-01

    This article reviews MIT Lincoln Laboratory's work over the past 20 years to develop photon-sensitive image sensors based on arrays of silicon Geiger-mode avalanche photodiodes. Integration of these detectors to all-digital CMOS readout circuits enable exquisitely sensitive solid-state imagers for lidar, wavefront sensing, and passive imaging. PMID:27070609

  17. Geiger-Mode Avalanche Photodiode Arrays Integrated to All-Digital CMOS Circuits

    Directory of Open Access Journals (Sweden)

    Brian Aull

    2016-04-01

    Full Text Available This article reviews MIT Lincoln Laboratory's work over the past 20 years to develop photon-sensitive image sensors based on arrays of silicon Geiger-mode avalanche photodiodes. Integration of these detectors to all-digital CMOS readout circuits enable exquisitely sensitive solid-state imagers for lidar, wavefront sensing, and passive imaging.

  18. Effective Teaching of the Physical Design of Integrated Circuits Using Educational Tools

    Science.gov (United States)

    Aziz, Syed Mahfuzul; Sicard, Etienne; Ben Dhia, Sonia

    2010-01-01

    This paper presents the strategies used for effective teaching and skill development in integrated circuit (IC) design using project-based learning (PBL) methodologies. It presents the contexts in which these strategies are applied to IC design courses at the University of South Australia, Adelaide, Australia, and the National Institute of Applied…

  19. InP HEMT Integrated Circuits for Submillimeter Wave Radiometers in Earth Remote Sensing

    Science.gov (United States)

    Deal, William R.; Chattopadhyay, Goutam

    2012-01-01

    The operating frequency of InP integrated circuits has pushed well into the Submillimeter Wave frequency band, with amplification reported as high as 670 GHz. This paper provides an overview of current performance and potential application of InP HEMT to Submillimeter Wave radiometers for earth remote sensing.

  20. Ultraprecise phase manipulation in integrated photonic quantum circuits with generalized directional couplers

    International Nuclear Information System (INIS)

    We present an innovative approach for ultra-precise phase manipulation in integrated photonic quantum circuits. To this end, we employ generalized directional couplers that utilize a detuning of the propagation constant in optical waveguides by the overlap of adjacent waveguide modes. We demonstrate our findings in experiments with classical as well as quantum light

  1. 76 FR 76434 - Certain Integrated Circuits, Chipsets, and Products Containing Same Including Televisions...

    Science.gov (United States)

    2011-12-07

    ...Notice is hereby given that the U.S. International Trade Commission has received a complaint entitled In Re Certain Integrated Circuits, Chipsets, And Products Containing Same including Televisions, DN 2860; the Commission is soliciting comments on any public interest issues raised by the...

  2. 77 FR 57589 - Certain Integrated Circuits, Chipsets, and Products Containing Same Including Televisions...

    Science.gov (United States)

    2012-09-18

    ... Semiconductor, Inc. of Austin, Texas (``Freescale''). 76 FR 41521-2 (July 14, 2011). The complaint alleges...) or in response to the post-RD Commission Notice issued on July 16, 2012, were filed. See 77 FR 42764... `` data processor within an integrated circuit package comprising: * * * a plurality of bus...

  3. Horn Antennas and Dual-Polarized Circuits in Substrate Integrated Waveguide (SIW) Technology

    OpenAIRE

    Esquius Morote, Marc

    2014-01-01

    The Substrate Integrated Waveguide (SIW) technology is a very promising candidate to provide widespread commercial solutions for modern communications systems. Its main advantage is the possibility to integrate passive/active components and antennas in the same substrate by using standard manufacturing processes, such as the Printed Circuits Board (PCB) processing technique. Nevertheless, the production of low-cost SIW devices is inherently linked to commercially available substrates and fabr...

  4. Silicon based millimeterwave integrated circuits for multi giga-bits-per-second wireless data

    OpenAIRE

    Kodkani, Rahul M.

    2009-01-01

    This research focuses on the design of silicon based millimeterwave integrated circuits for Multi Giga bits-per -second wireless communications. The use of Active sub- harmonic Mixers(ASHM) and Passive Sub-harmonic Mixers (PSHM) for millimeterwave receivers was explored for their advantages over fundamental order mixers. A multi-phase active sub-harmonic mixer/downconverter with an on-chip integrated ring Voltage Controlled Oscillator(VCO) was designed for millimeterwave wireless systems in a...

  5. Probe modeling for millimeter-wave integrated-circuit horn antennas

    OpenAIRE

    Guo, Yong; Chiao, Jung-Chih; Potter, Kent A.; Rutledge, David B.

    1992-01-01

    Integrated-circuit probe-excited horn-antenna arrays etched in silicon are well developed. They are a very promising class of antenna arrays for milli-meter and submillimeter applications. Further development of this technology involves integrating mixers and amplifiers into the antenna arrays. In an effort to develop an antenna-mixer array based on the existing technology, various antenna probes inside the pyramidal horns have been examined on scaled model-horns at the micr...

  6. Flexible packaging of solid-state integrated circuit chips with elastomeric microfluidics

    OpenAIRE

    Bowei Zhang; Quan Dong; Korman, Can E.; Zhenyu Li; Zaghloul, Mona E.

    2013-01-01

    A flexible technology is proposed to integrate smart electronics and microfluidics all embedded in an elastomer package. The microfluidic channels are used to deliver both liquid samples and liquid metals to the integrated circuits (ICs). The liquid metals are used to realize electrical interconnects to the IC chip. This avoids the traditional IC packaging challenges, such as wire-bonding and flip-chip bonding, which are not compatible with current microfluidic technologies. As a demonstratio...

  7. Modeling the cosmic-ray-induced soft-error rate in integrated circuits: An overview

    International Nuclear Information System (INIS)

    This paper is an overview of the concepts and methodologies used to predict soft-error rates (SER) due to cosmic and high-energy particle radiation in integrated circuit chips. The paper emphasizes the need for the SER simulation using the actual chip circuit model which includes device, process, and technology parameters as opposed to using either the discrete device simulation or generic circuit simulation that is commonly employed in SER modeling. Concepts such as funneling, event-by-event simulation, nuclear history files, critical charge, and charge sharing are examined. Also discussed are the relative importance of elastic and inelastic nuclear collisions, rare event statistics, and device vs. circuit simulations. The semi-empirical methodologies used in the aerospace community to arrive at SERs [also referred to as single-event upset (SEU) rates] in integrated circuit chips are reviewed. This paper is one of four in this special issue relating to SER modeling. Together, they provide a comprehensive account of this modeling effort, which has resulted in a unique modeling tool called the Soft-Error Monte Carlo Model, or SEMM

  8. A Novel Optimization Tool for Automated Design of Integrated Circuits based on MOSGA

    Directory of Open Access Journals (Sweden)

    Maryam Dehbashian

    2011-11-01

    Full Text Available In this paper a novel optimization method based on Multi-Objective Gravitational Search Algorithm (MOGSA is presented for automated design of analog integrated circuits. The recommended method firstly simulates a selected circuit using a simulator and then simulated results are optimized by MOGSA algorithm. Finally this process continues to meet its optimum result. The main programs of the proposed method have been implemented in MATLAB while analog circuits are simulated by HSPICE software. To show the capability of this method, its proficiency will be examined in the optimization of analog integrated circuits design. In this paper, an analog circuit sizing scheme -Optimum Automated Design of a Temperature independent Differential Op-amp using Widlar Current Source- is illustrated as a case study. The computer results obtained from implementing this method indicate that the design specifications are closely met. Moreover, according to various design criteria, this tool by proposing a varied set of answers can give more options to designers to choose a desirable scheme among other suggested results. MOGSA, the proposal algorithm, introduces a novel method in multi objective optimization on the basis of Gravitational Search Algorithm in which the concept of “Pareto-optimality” is used to determine “non-dominated” positions as well as an external repository to keep these positions. To ensure the accuracy of MOGSA performance, this algorithm is validated using several standard test functions from some specialized literatures. Final results indicate that our method is highly competitive with current multi objective optimization algorithms.

  9. Study and realization of ultra-rapid logic circuits in middle scale integration

    International Nuclear Information System (INIS)

    We associate middle scale integration with sub-nanosecond logic in order to realize ultra-rapid logic circuits, characterized by a 40 gates complexity for a dissipation lower than 1 watt. For this purpose, we must find a high special and low power gates family. With use of current mode logic, and sharing of the logic circuit between an internal part and interfaces, mean dissipation can be lowered to 20 mW while mean propagation time is 1 ns by gate. So, circuits present a speed-power product of 20 mW x ns giving to them one of the best places among the other types of ultra-rapid logic. Another interesting aspect of the work is the use of diffused components master slice including specialized integrated cells, fitting well complex circuits. With this master slice and the different gates, settlement of mean complexity circuits family is foreseen. The elements of this family would be able to reply to the main needs of rapid electronics. (author)

  10. A High-Temperature Piezoresistive Pressure Sensor with an Integrated Signal-Conditioning Circuit.

    Science.gov (United States)

    Yao, Zong; Liang, Ting; Jia, Pinggang; Hong, Yingping; Qi, Lei; Lei, Cheng; Zhang, Bin; Xiong, Jijun

    2016-01-01

    This paper focuses on the design and fabrication of a high-temperature piezoresistive pressure sensor with an integrated signal-conditioning circuit, which consists of an encapsulated pressure-sensitive chip, a temperature compensation circuit and a signal-conditioning circuit. A silicon on insulation (SOI) material and a standard MEMS process are used in the pressure-sensitive chip fabrication, and high-temperature electronic components are adopted in the temperature-compensation and signal-conditioning circuits. The entire pressure sensor achieves a hermetic seal and can be operated long-term in the range of -50 °C to 220 °C. Unlike traditional pressure sensor output voltage ranges (in the dozens to hundreds of millivolts), the output voltage of this sensor is from 0 V to 5 V, which can significantly improve the signal-to-noise ratio and measurement accuracy in practical applications of long-term transmission based on experimental verification. Furthermore, because this flexible sensor's output voltage is adjustable, general follow-up pressure transmitter devices for voltage converters need not be used, which greatly reduces the cost of the test system. Thus, the proposed high-temperature piezoresistive pressure sensor with an integrated signal-conditioning circuit is expected to be highly applicable to pressure measurements in harsh environments. PMID:27322288

  11. An analog integrated signal processing circuit for on-chip diffusion-based gas analysis

    International Nuclear Information System (INIS)

    In diffusion-based gas analysis, the transient of gas diffusion process is recorded by a generic gas sensor to serve as a fingerprint for qualitative and quantitative analysis of gaseous samples. Following the acquisition of these specific signals, any standalone gas analyzer requires a pattern recognition system for pattern classification. The classic digital pattern recognition methods require computing hardware of adequate computational throughput. In this paper, we have followed a straightforward mathematical procedure to relate the signals to their associated target gases. We have shown that the procedure can be implemented by a set of analog functions. Based on the results, we have designed an analog integrated circuit, in 0.18 µm standard CMOS process, for processing the diffusion-based transient signals. The main circuit components are a low-pass filter, the differentiator, the feature extractor and an artificial neural network. The output of the circuit is a 2-bit binary code that specifies the target gas. The circuit successfully classified four alcoholic vapors by processing the experimentally obtained response patterns. The proposed signal processing circuit, the semiconductor gas sensor and the diffusion channel can all be implemented on a single substrate to fabricate an integrated micro gas analyzer. (paper)

  12. A METHOD AND AN APPARATUS FOR PROVIDING TIMING SIGNALS TO A NUMBER OF CIRCUITS, AN INTEGRATED CIRCUIT AND A NODE

    DEFF Research Database (Denmark)

    2006-01-01

    A method of providing or transporting a timing signal between a number of circuits, electrical or optical, where each circuit is fed by a node. The nodes forward timing signals between each other, and at least one node is adapted to not transmit a timing signal before having received a timing...... signal from at least two nodes. In this manner, the direction of the timing skew between nodes and circuits is known and data transport between the circuits made easier....

  13. Fully integrated on-chip nano-electrochemical devices for electroanalytical applications

    International Nuclear Information System (INIS)

    In this work, we report a fully integrated nanowire-based electrochemical device that enables a suite of highly sensitive electroanalytical techniques in small sample volumes at silicon chip substrates. A hybrid wafer-level lithography approach is employed whereby an array of twelve individually addressable discrete gold nanowire electrodes, written by electron beam lithography, along with on-chip gold counter and silver pseudo-reference electrodes are deposited on silicon chips. An inorganic silicon nitride passivation ensures the devices are compatible with both aqueous and organic media. Peripherally located probe pads enables facile and direct electrical connection to electrodes using a reusable push-pin interface within a bespoke sample holder. This approach eliminates the requirement for costly microelectronic packaging techniques and also the requirement for large volume sample analysis. Nanowire electrodes with highly reproducible dimensions and low surface roughness are routinely fabricated and display characteristic Ohmic responses during two-point I–V measurements. The magnitude and shape of the voltammetric responses of a model molecule ferrocene monocarboxylic acid at nanowire electrodes were found to be highly reproducible on different electrodes and chips from multiple wafers and fabrication runs. Quasi-steady-state electrochemical behaviour was demonstrated for scan rates up to 5000 mV s−1, without any observed changes to the voltammetric shape, enabling the potential for reliable electroanalysis with a millisecond response time. Square wave voltammetry was applied to the detection of 2,4-dinitrotoluene in the absence of a supporting electrolyte. Devices exhibited excellent limit of detection of 7 ng mL−1 using pristine unmodified nanowire electrodes. Consequently, these integrated nano-electrochemical devices represent a platform excellently positioned for providing reliable, rapid electroanalytical sensing suitable for a wide range of

  14. The One-Water Hydrologic Flow Model - The next generation in fully integrated hydrologic simulation software

    Science.gov (United States)

    Boyce, S. E.; Hanson, R. T.

    2015-12-01

    The One-Water Hydrologic Flow Model (MF-OWHM) is a MODFLOW-based integrated hydrologic flow model that is the most complete version, to date, of the MODFLOW family of hydrologic simulators needed for the analysis of a broad range of conjunctive-use issues. MF-OWHM fully links the movement and use of groundwater, surface water, and imported water for consumption by agriculture and natural vegetation on the landscape, and for potable and other uses within a supply-and-demand framework. MF-OWHM is based on the Farm Process for MODFLOW-2005 combined with Local Grid Refinement, Streamflow Routing, Surface-water Routing Process, Seawater Intrusion, Riparian Evapotranspiration, and the Newton-Raphson solver. MF-OWHM also includes linkages for deformation-, flow-, and head-dependent flows; additional observation and parameter options for higher-order calibrations; and redesigned code for facilitation of self-updating models and faster simulation run times. The next version of MF-OWHM, currently under development, will include a new surface-water operations module that simulates dynamic reservoir operations, the conduit flow process for karst aquifers and leaky pipe networks, a new subsidence and aquifer compaction package, and additional features and enhancements to enable more integration and cross communication between traditional MODFLOW packages. By retaining and tracking the water within the hydrosphere, MF-OWHM accounts for "all of the water everywhere and all of the time." This philosophy provides more confidence in the water accounting by the scientific community and provides the public a foundation needed to address wider classes of problems such as evaluation of conjunctive-use alternatives and sustainability analysis, including potential adaptation and mitigation strategies, and best management practices. By Scott E. Boyce and Randall T. Hanson

  15. Design of multilayered grating couplers as key elements of a fully integrated IR-absorption sensor

    Science.gov (United States)

    Kasberger, Juergen; Jakoby, Bernhard

    2008-08-01

    For the online characterization of fluids regarding their chemical composition, the miniaturization of an IR-absorption sensor at application-specific distinguished wavelengths for the mid-IR-region promises outstanding features. Utilizing micromachining technology facilitates the integration of all required components (including thermal emitter and detector) into a complete sensor system. The absorption is sensed in the evanescent field of an appropriately designed slab mono-mode waveguide (ZnSe, n=2.42) residing on a BaF2-substrate (n=1.44), which represents the central element of the system. A typical application for such a system is, e.g., the characterization of engine oil oxidation in terms of the absorption at 5.85 μm as an indicator for deterioration. The thermal generation and detection of mid-IR-radiation is preferred over expensive and sophisticated quantum well devices. However, the spatial and non-coherent character of thermally generated IR-radiation requires an extension of the numerical methods established for coherent light sources for a proper design of the system's grating couplers, which act as key elements determining the system performance. These couplers yield efficient coupling into and out of the sensing waveguide and provide the required spectral filtering at the same time. In the actually projected implementation, a multilayer waveguide Si/BaF2/ZnSe is used, where the silicon substrate practically represents a rear-reflector in the grating region featuring several advantages compared to simpler grating couplers. In this contribution we discuss the modelling of the coupling of non-coherent, thermally generated and detected IR-radiation by means of these multilayer grating couplers in the context of a fully integrated IR-absorption sensor system.

  16. Application of a fully-integrated groundwater-surface water flow model in municipal asset management

    Science.gov (United States)

    Bowman, L. K.; Unger, A.; Jones, J. P.

    2014-12-01

    Access to affordable potable water is critical in the development and maintenance of urban centres. Given that water is a public good in Canada, all funds related to operation and maintenance of the drinking water and wastewater networks must come from consumers. An asset management system can be put in place by municipalities to more efficiently manage their water and wastewater distribution system to ensure proper use of these funds. The system works at the operational, tactical, and strategic levels, thus ensuring optimal scheduling of operation and maintenance activities, as well as prediction of future water demand scenarios. At the operational level, a fully integrated model is used to simulate the groundwater-surface water interaction of the Laurel Creek Watershed, of which 80% is urbanized by the City of Waterloo. Canadian municipalities typically lose 13% of their potable water through leaks in watermains and sanitary sewers, and sanitary sewers often generate substantial inflows from fractures in pipe walls. The City of Waterloo sanitary sewers carry an additional 10,000 cubic meters of water to wastewater treatment plants. Therefore, watermain and sanitary sewers present a significant impact on the groundwater-surface water interaction, as well as the affordability of the drinking water and wastewater networks as a whole. To determine areas of concern within the network, the integrated groundwater-surface water model also simulates flow through the City of Waterloo's watermain and sanitary sewer networks. The final model will be used to assess the interaction between measured losses of water from the City of Waterloo's watermain system, infiltration into the sanitary sewer system adjacent to the watermains, and the response of the groundwater system to deteriorated sanitary sewers or to pipes that have been recently renovated. This will ultimately contribute to the City of Waterloo's municipal asset management plan.

  17. A 160 μA biopotential acquisition IC with fully integrated IA and motion artifact suppression.

    Science.gov (United States)

    Van Helleputte, Nick; Kim, Sunyoung; Kim, Hyejung; Kim, Jong Pal; Van Hoof, Chris; Yazicioglu, Refet Firat

    2012-12-01

    This paper proposes a 3-channel biopotential monitoring ASIC with simultaneous electrode-tissue impedance measurements which allows real-time estimation of motion artifacts on each channel using an an external μC. The ASIC features a high performance instrumentation amplifier with fully integrated sub-Hz HPF rejecting rail-to-rail electrode-offset voltages. Each readout channel further has a programmable gain amplifier and programmable 4th order low-pass filter. Time-multiplexed 12 b SAR-ADCs are used to convert all the analog data to digital. The ASIC achieves >; 115 dB of CMRR (at 50/60 Hz), a high input impedance of >; 1 GΩ and low noise (1.3 μVrms in 100 Hz). Unlike traditional methods, the ASIC is capable of actual motion artifact suppression in the analog domain before final amplification. The complete ASIC core operates from 1.2 V with 2 V digital IOs and consumes 200 μW when all 3 channels are active. PMID:23853256

  18. Mechatronic design of a fully integrated camera for mini-invasive surgery.

    Science.gov (United States)

    Zazzarini, C C; Patete, P; Baroni, G; Cerveri, P

    2013-06-01

    This paper describes the design features of an innovative fully integrated camera candidate for mini-invasive abdominal surgery with single port or transluminal access. The apparatus includes a CMOS imaging sensor, a light-emitting diode (LED)-based unit for scene illumination, a photodiode for luminance detection, an optical system designed according to the mechanical compensation paradigm, an actuation unit for enabling autofocus and optical zoom, and a control logics based on microcontroller. The bulk of the apparatus is characterized by a tubular shape with a diameter of 10 mm and a length of 35 mm. The optical system, composed of four lens groups, of which two are mobile, has a total length of 13.46 mm and an effective focal length ranging from 1.61 to 4.44 mm with a zoom factor of 2.75×, with a corresponding angular field of view ranging from 16° to 40°. The mechatronics unit, devoted to move the zoom and the focus lens groups, is implemented adopting miniature piezoelectric motors. The control logics implements a closed-loop mechanism, between the LEDs and photodiode, to attain automatic control light. Bottlenecks of the design and some potential issues of the realization are discussed. A potential clinical scenario is introduced. PMID:23314768

  19. Design and Verification of Application Specific Integrated Circuits in a Network of Online Labs

    Directory of Open Access Journals (Sweden)

    A.Y. Al-Zoubi

    2009-08-01

    Full Text Available A solution to implement a remote laboratory for testing and designing analog Application-Specific Integrated Circuits of the type (ispPAC10 is presented. The application allows electrical engineering students to access and perform measurements and conduct analog electronics experiments over the internet. PAC-Designer software, running on a Citrix server, is used in the circuit design in which the signals are generated and the responses are acquired by a data acquisition board controlled by LabVIEW. Three interconnected remote labs located in three different continents will be implementing the proposed system.

  20. Measurements of complex impedance in microwave high power systems with a new bluetooth integrated circuit.

    Science.gov (United States)

    Roussy, Georges; Dichtel, Bernard; Chaabane, Haykel

    2003-01-01

    By using a new integrated circuit, which is marketed for bluetooth applications, it is possible to simplify the method of measuring the complex impedance, complex reflection coefficient and complex transmission coefficient in an industrial microwave setup. The Analog Devices circuit AD 8302, which measures gain and phase up to 2.7 GHz, operates with variable level input signals and is less sensitive to both amplitude and frequency fluctuations of the industrial magnetrons than are mixers and AM crystal detectors. Therefore, accurate gain and phase measurements can be performed with low stability generators. A mechanical setup with an AD 8302 is described; the calibration procedure and its performance are presented. PMID:15078067

  1. Hydrogenated Amorphous Silicon Sensor Deposited on Integrated Circuit for Radiation Detection

    OpenAIRE

    Despeisse, M; Anelli, G.; Jarron, P.; Kaplon, J; Moraes, D.; A. Nardulli(Institute for Particle Physics, ETH Zurich, Zurich, Switzerland); Powolny, F; Wyrsch, N

    2008-01-01

    Radiation detectors based on the deposition of a 10 to 30 μm thick hydrogenated amorphous silicon (a-Si:H) sensor directly on top of integrated circuits have been developed. The performance of this detector technology has been assessed for the first time in the context of particle detectors. Three different circuits were designed in a quarter micron CMOS technology for these studies. The so-called TFA (Thin-Film on ASIC) detectors obtained after deposition of a-Si:H sensors on the developed c...

  2. A novel high voltage start up circuit for an integrated switched mode power supply

    International Nuclear Information System (INIS)

    A novel high voltage start up circuit for providing an initial bias voltage to an integrated switched mode power supply (SMPS) is presented. An enhanced mode VDMOS transistor, the gate of which is biased by a floating p-island, is used to provide start up current and sustain high voltage. An NMOS transistor having a high source to ground breakdown voltage is included to extend the bias voltage range to the SMPS. Simulation results indicate that the high voltage start up circuit can start and restart as designed. The proposed structure is believed to be more energy saving and cost-effective compared with other solutions. (semiconductor devices)

  3. 4H-SiC JFET Multilayer Integrated Circuit Technologies Tested Up to 1000 K

    Science.gov (United States)

    Spry, D. J.; Neudeck, P. G.; Chen, L.; Chang, C. W.; Lukco, D.; Beheim, G. M.

    2015-01-01

    Testing of semiconductor electronics at temperatures above their designed operating envelope is recognized as vital to qualification and lifetime prediction of circuits. This work describes the high temperature electrical testing of prototype 4H silicon carbide (SiC) junction field effect transistor (JFET) integrated circuits (ICs) technology implemented with multilayer interconnects; these ICs are intended for prolonged operation at temperatures up to 773K (500 C). A 50 mm diameter sapphire wafer was used in place of the standard NASA packaging for this experiment. Testing was carried out between 300K (27 C) and 1150K (877 C) with successful electrical operation of all devices observed up to 1000K (727 C).

  4. Combined Self-Test of Analog Portion and ADCs in Integrated Mixed-Signal Circuits

    Science.gov (United States)

    Hu, Geng; Wang, Hong; Yang, Shiyuan

    Testing is a critical stage in integrated circuits production in order to guarantee reliability. The complexity and high integration level of mixed-signal ICs has put forward new challenges to circuit testing. This paper describes an oscillation-based combined self-test strategy for the analog portion and analog-to-digital converters (ADCs) in integrated mixed-signal circuits. In test mode, the analog portion under test is reconfigured into an oscillator, generating periodic signals as the test stimulus of ADC. By analyzing the A/D conversion results, a histogram test of ADC can be performed, and the oscillation frequency as well as amplitude can be checked, and in this way the oscillation test of the analog portion is realized simultaneously. For an analog benchmark circuit combined with an ADC, triangle oscillation and sinusoid oscillation schemes are both given to test their faults. Experimental results show that fault coverage of the analog portion is 92.2% and 94.3% in the two schemes respectively, and faults in the ADC can also be tested.

  5. A fully integrated direct-conversion digital satellite tuner in 0.18 μm CMOS

    Science.gov (United States)

    Si, Chen; Zengwang, Yang; Mingliang, Gu

    2011-04-01

    A fully integrated direct-conversion digital satellite tuner for DVB-S/S2 and ABS-S applications is presented. A broadband noise-canceling Balun-LNA and passive quadrature mixers provided a high-linearity low noise RF front-end, while the synthesizer integrated the loop filter to reduce the solution cost and system debug time. Fabricated in 0.18 μm CMOS, the chip achieves a less than 7.6 dB noise figure over a 900-2150 MHz L-band, while the measured sensitivity for 4.42 MS/s QPSK-3/4 mode is -91 dBm at the PCB connector. The fully integrated integer-N synthesizer operating from 2150 to 4350 MHz achieves less than 1 °C integrated phase error. The chip consumes about 145 mA at a 3.3 V supply with internal integrated LDOs.

  6. Sublacustrine groundwater discharge in esker aquifers; fully integrated groundwater flow modeling compared with novel field techniques

    Science.gov (United States)

    Ala-aho, Pertti; Rossi, Pekka M.; Isokangas, Elina; Kløve, Bjørn

    2015-04-01

    Groundwater (GW) discharge to surface water bodies such as streams, lakes and wetlands can greatly affect their water quantity, quality and related aquatic ecology. Therefore better understanding of GW - surface water interaction is needed in integrated management of water resources. Sublacustrine groundwater discharge (SGD) to lakes was studied in a complex unconfined Rokua esker aquifer system. SGD was studied for 12 lakes in the area to better understand water and solute inputs through lake beds and thereby the role of GW on lake water budget and solute concentrations. The locations and fluxes of SGD were simulated using a fully integrated groundwater flow model HydroGeoSphere. The used hydrological simulator allows water to flow and partition into overland and stream flow, evaporation, infiltration, and subsurface discharge into surface water features in a physically-based way, which was needed in simulating SGD of the complex aquifer system. The model was first calibrated for subsurface hydraulic conductivity in steady state using data of measured long-term average groundwater and lake levels and stream baseflow. The model performance in transient simulations was then examined against recorded hydrographs for lake and groundwater levels and stream flow. After model performance was verified, the simulated locations and fluxes of SGD were extracted from the model and compared with results from three independent field methods: airborne thermal imaging, stable isotope water balance and seepage meter measurements. Airborne thermal imaging was used to infer locations of SGD into lakes based on temperature anomalies at lakes shorelines due to discharging cold groundwater. Isotopic composition (H2 and O18) was analysed for lake water, groundwater and the data was used to estimate SGD flux into lakes. Finally, seepage meter measurements were conducted for one of the lakes to establish both locations and fluxes of SGD in detail. The simulated and field-based estimated

  7. Influence on measuring ionization chamber's time response speed with charge integration amplifying circuit

    International Nuclear Information System (INIS)

    The time response speed of measuring amplifier directly influences the research on ionization chamber's time response speed. The reasons why the measuring circuit was designed with charge integration amplifier were presented. The mechanism of emerging stepped current signal of ionization chamber unit irradiated by a stable radiation source was analyzed. The method of studying amplifier time response by measuring the changing process of current signal was proposed. The relationship of the amplifier's time response speed with the detector unit interelectrode capacitance, the amplifier's input protecting resistance and its feedback integral capacitance was studied through experiment. It is concluded that the amplifier's time response speed is concerned with the constant time of ionization chamber unit interelectrode capacitance and protecting resistance. And it is not concerned with the feedback integral capacitance. It provides theoretical guidance on designing ionization chamber and measuring circuit. (authors)

  8. Micro-coolers fabricated as a component in an integrated circuit

    International Nuclear Information System (INIS)

    The packing density and power capacity of integrated electronics is increasing resulting in higher thermal flux densities. Improved thermal management techniques are required and one approach is to include thermoelectric coolers as part of the integrated circuit. An analysis will be described showing that the supporting substrate will have a large influence on the cooling capacity of the thermoelectric cooler. In particular, for materials with a low ZT figure of merit (for example gallium arsenide (GaAs) based compounds) the substrate will have to be substantially thinned to obtain cooling, which may preclude the use of thermoelectric coolers, for example, as part of a GaAs based integrated circuit. Further, using experimental techniques to measure only the small positive cooling temperature difference (ΔT) between the anode (Th) and the cathode (Tc) contacts can be misinterpreted as cooling when in fact it is heating. (paper)

  9. A 330-500 GHz Zero-Biased Broadband Tripler Based on Terahertz Monolithic Integrated Circuits

    Science.gov (United States)

    Ren, Tian-Hao; Zhang, Yong; Yan, Bo; Xu, Rui-Min; Yang, Cheng-Yue; Zhou, Jing-Tao; Jin, Zhi

    2015-02-01

    A 330-500 GHz zero-biased broadband monolithic integrated tripler is reported. The measured results show that the maximum efficiency and the maximum output power are 2% and 194 μW at 348 GHz. The saturation characteristic test shows that the output 1 dB compression point is about -8.5 dBm at 334 GHz and the maximum efficiency is obtained at the point, which is slightly below the 1 dB compression point. Compared with the conventional hybrid integrated circuit, a major advantage of the monolithic integrated circuit is the significant improvement of reliability and consistency. In this work, a terahertz monolithic frequency multiplier at this band is designed and fabricated.

  10. The simulation of a readout integrated circuit with high dynamic range for long wave infrared FPA

    Science.gov (United States)

    Zhai, Yongcheng; Ding, Rui-jun; Chen, Guo-qiang; Wang, Pan; Hao, Li-chao

    2013-12-01

    This paper describes the simulation results of a high performance readout integrated circuit (ROIC) designed for long wave infrared (LWIR) detectors, which has high dynamic range (HDR). A special architecture is used to the input unit cell to accommodate the wide scene dynamic range requirement, thus providing over a factor of 70dB dynamic range. A capacitive feedback transimpedance amplifier (CTIA) provides a low noise detector interface circuit capable of operating at low input currents and a folded cascade amplifier with a gain of 73dB is designed. A 6.4pF integration capacitor is used for supporting a wide scene dynamic range, which can store 80Me. Because of the restriction of the layout area, four unit cells will share an integration capacitor. A sample and hold capacitor is also part of the input unit cell architecture, which allows the infrared focal plane arrays (IRFPA) to be operated in full frame snapshot mode and provides the maximum integration time available. The integration time is electronically controlled by an external clock pulse. The simulation results show that the circuit works well under 5V power supply and the nonlinearity is calculated less than 0.1%. The total power dissipation is less than 150mW.

  11. Integrated circuits and molecular components for stress and feeding: implications for eating disorders

    Science.gov (United States)

    Hardaway, J. A.; Crowley, N. A.; Bulik, C. M.; Kash, T. L.

    2015-01-01

    Eating disorders are complex brain disorders that afflict millions of individuals worldwide. The etiology of these diseases is not fully understood, but a growing body of literature suggests that stress and anxiety may play a critical role in their development. As our understanding of the genetic and environmental factors that contribute to disease in clinical populations like anorexia nervosa, bulimia nervosa and binge eating disorder continue to grow, neuroscientists are using animal models to understand the neurobiology of stress and feeding. We hypothesize that eating disorder clinical phenotypes may result from stress-induced maladaptive alterations in neural circuits that regulate feeding, and that these circuits can be neurochemically isolated using animal model of eating disorders. PMID:25366309

  12. Analysis of cylindrical proportional counter pulses transmission through differentiating and integrating circuits

    International Nuclear Information System (INIS)

    The numerical estimations of the effect of the length and orientation of the charged particle track on the shape and amplitude of pulses, passed tough the shaping circuits, are presented. The results are calculated for the following parameters of a counter with the argon-methane gaseous mixture: the anode radius is 0.001 cm, the cathode radius is 4.5 cm, the filling gas pressure is 760 mm Hg, the anode filament voltage is 1800 V, the gaseous ion mobility is 1.6 cm2 V-1s-1. The pulse amplitudes, corresponding to point and extended ionization, which have passed through the differentiating and integrating circuits. It is shown that tracks, having equal energy releases but different orientation with respect to the counter anode filament, can lead to formation of such pulses at the shaping circuit output, which considerably differ in amplitudes and have different pulse rise times. These effects can worsen the spectrometer resolution

  13. Study on Pulse Skip Modulation Mode in Smart Power Integrated Circuits and Its Test Technology

    Institute of Scientific and Technical Information of China (English)

    LUO Ping

    2005-01-01

    @@ Up to now, the popular control modes for smart power integrated circuit (SPIC) are PWM and PFM.PWM bases on constant frequency variable width (CFVW) control pulse, whereas, PFM bases on constant width variable frequency (CWVF) control pulse. PWM converter has low efficiency with light loads and high amplitude harmonic. On the other hand,the control circuit and filter for PFM are much complex. This dissertation proposes a novel modulation mode named pulse skip modulation (PSM)for SPIC converter, which bases on constant width constant frequency (CWCF) control pulse. It is shown that PSM converter would improve its efficiency and suppress EMI. It also has quick response speed, good interfere rejection and strong robust. Furthermore, it is easy to realize PSM control circuit. The modulating theories of PSM are firstly studied in the world according to the author's investigation.

  14. Towards scalable networks of solid-state quantum memories in a photonic integrated circuit (Presentation Recording)

    Science.gov (United States)

    Englund, Dirk R.

    2015-09-01

    A central goal of quantum information science is the entanglement of multiple quantum memories that can be individually controlled. Here, we discuss progress towards photonic integrated circuits designed to enable efficient optical interactions between multiple spin qubits in nitrogen vacancy (NV) centers in diamond. We describe NV-nanocavity systems in the strong Purcell regime with optical quality factors approaching 10,000 and electron spin coherence times exceeding 200 μs implantation of NVs with nanometer-scale apertures, including into cavity field maxima; hybrid on-chip networks for integration of multiple functional NV-cavity systems; and scalable integration of superconducting nanowire single photon detectors on-chip.

  15. A wirelessly readable and resettable shock recorder through the integration of LC circuits and MEMS devices

    International Nuclear Information System (INIS)

    This paper presents a passive shock recorder to record shock events for tens of Gs with wireless reading and wireless resetting capabilities through the integration of LC circuits and two MEMS devices. With a micro mechanical-latch shock switch electrically connected to the sensing LC circuit, the shock event that leads to different latching states can be recorded and wirelessly read through the LC resonant frequency. With a micro electro-thermal actuator electrically connected to a wirelessly powered actuating LC circuit, the energy can be wirelessly sent to the micro actuator to provide the necessary unlatched force. By integrating the mechanical-latch shock switch and actuator with LC circuits, the latching state can be reset through the wireless actuation. Therefore, the shock recorder can be used repeatedly. Here, the mechanical-latch shock switch is designed to have a two-level shock recording capability. The fabrication of the shock switch and actuator are achieved by a Ni-based surface micromachining process. When the acceleration reaches 28.06 G, the latching state changes from the original state to the first latching state. The resonant frequency of sensing for the LC circuit is found to switch from 10.14 MHz to 9.16 MHz, correspondingly. By further applying acceleration up to 37.10 G, the latching state changes from the first latching state to the second state, and the resonant frequency shifts to 7.83 MHz. Then, with a current of 2.07 AAC wirelessly induced in the actuating LC circuit, the micro electro-thermal actuator is shown to provide sufficient displacement to reset the shock switch from a latched state back to the original unlatched state, and the resonant frequency is switched back to 10.14 MHz. The fabricated shock recorder is repeatedly tested five times. The wireless reading, resetting and shock recording capabilities are successfully verified. (paper)

  16. A new circuit model of HgCdTe photodiode for SPICE simulation of integrated IRFPA

    Science.gov (United States)

    Saxena, Raghvendra Sahai; Saini, Navneet Kaur; Bhan, R. K.; Sharma, R. K.

    2014-11-01

    We propose a novel sub circuit model to simulate HgCdTe infrared photodiodes in a circuit simulator, like PSPICE. We have used two diodes of opposite polarity in parallel to represent the forward biased and the reverse biased behavior of an HgCdTe photodiode separately. We also connected a resistor in parallel with them to represent the ohmic shunt and a constant current source to represent photocurrent. We show that by adjusting the parameters in standard diode models and the resistor and current values, we could actually fit the measured data of our various HgCdTe photodiodes having different characteristics. This is a very efficient model that can be used for simulation of readout integrated circuit (ROIC) for HgCdTe IR photodiode arrays. This model also allows circuit level Monte Carlo simulation on a complete IRFPA at a single circuit simulator platform to estimate the non-uniformity for given processes of HgCdTe device fabrication and Si ROIC fabrication.

  17. A smart fully integrated micromachined separator with soft magnetic micro-pillar arrays for cell isolation

    Science.gov (United States)

    Dong, Tao; Su, Qianhua; Yang, Zhaochu; Zhang, Yulong; Egeland, Eirik B.; Gu, Dan D.; Calabrese, Paolo; Kapiris, Matteo J.; Karlsen, Frank; Minh, Nhut T.; Wang, K.; Jakobsen, Henrik

    2010-11-01

    A smart fully integrated micromachined separator with soft magnetic micro-pillar arrays has been developed and demonstrated, which can merely employ one independent lab-on-chip to realize cell isolation. The simulation, design, microfabrication and test for the new electromagnetic micro separator were executed. The simulation results of the electromagnetic field in the separator show that special soft magnetic micro-pillar arrays can amplify and redistribute the electromagnetic field generated by the micro-coils. The separator can be equipped with a strong magnetic field to isolate the target cells with a considerably low input current. The micro separator was fabricated by micro-processing technology. An electroplating bath was hired to deposit NiCo/NiFe to fabricate the micro-pillar arrays. An experimental system was set up to verify the function of the micro separator by isolating the lymphocytes, in which the human whole blood mixed with Dynabeads® FlowComp Flexi and monoclonal antibody MHCD2704 was used as the sample. The results show that the electromagnetic micro separator with an extremely low input current can recognize and capture the target lymphocytes with a high efficiency, the separation ratio reaching more than 90% at a lower flow rate. For the electromagnetic micro separator, there is no external magnetizing field required, and there is no extra cooling system because there is less Joule heat generated due to the lower current. The magnetic separator is totally reusable, and it can be used to separate cells or proteins with common antigens.

  18. A fully integrated UHF RFID reader SoC for handheld applications in the 0.18 μm CMOS process

    International Nuclear Information System (INIS)

    A low cost fully integrated single-chip UHF radio frequency identification (RFID) reader SoC for short distance handheld applications is presented. The SoC integrates all building blocks-including an RF transceiver, a PLL frequency synthesizer, a digital baseband and an MCU-in a 0.18 μm CMOS process. A high-linearity RX front-end is designed to handle the large self-interferer. A class-E power amplifier with high power efficiency is also integrated to fulfill the function of a UHF passive RFID reader. The measured maximum output power of the transmitter is 20.28 dBm and the measured receiver sensitivity is -60 dBm. The digital baseband including MCU core consumes 3.91 mW with a clock of 10 MHz and the analog part including power amplifier consumes 368.4 mW. The chip has a die area of 5.1 x 3.8 mm2 including pads. (semiconductor integrated circuits)

  19. A fully integrated UHF RFID reader SoC for handheld applications in the 0.18 {mu}m CMOS process

    Energy Technology Data Exchange (ETDEWEB)

    Wang Jingchao; Zhang Chun; Wang Zhihua, E-mail: wangjc@gmail.co [Institute of Microelectronics, Tsinghua University, Beijing 100084 (China)

    2010-08-15

    A low cost fully integrated single-chip UHF radio frequency identification (RFID) reader SoC for short distance handheld applications is presented. The SoC integrates all building blocks-including an RF transceiver, a PLL frequency synthesizer, a digital baseband and an MCU-in a 0.18 {mu}m CMOS process. A high-linearity RX front-end is designed to handle the large self-interferer. A class-E power amplifier with high power efficiency is also integrated to fulfill the function of a UHF passive RFID reader. The measured maximum output power of the transmitter is 20.28 dBm and the measured receiver sensitivity is -60 dBm. The digital baseband including MCU core consumes 3.91 mW with a clock of 10 MHz and the analog part including power amplifier consumes 368.4 mW. The chip has a die area of 5.1 x 3.8 mm{sup 2} including pads. (semiconductor integrated circuits)

  20. Photolithography-Based Patterning of Liquid Metal Interconnects for Monolithically Integrated Stretchable Circuits.

    Science.gov (United States)

    Park, Chan Woo; Moon, Yu Gyeong; Seong, Hyejeong; Jung, Soon Won; Oh, Ji-Young; Na, Bock Soon; Park, Nae-Man; Lee, Sang Seok; Im, Sung Gap; Koo, Jae Bon

    2016-06-22

    We demonstrate a new patterning technique for gallium-based liquid metals on flat substrates, which can provide both high pattern resolution (∼20 μm) and alignment precision as required for highly integrated circuits. In a very similar manner as in the patterning of solid metal films by photolithography and lift-off processes, the liquid metal layer painted over the whole substrate area can be selectively removed by dissolving the underlying photoresist layer, leaving behind robust liquid patterns as defined by the photolithography. This quick and simple method makes it possible to integrate fine-scale interconnects with preformed devices precisely, which is indispensable for realizing monolithically integrated stretchable circuits. As a way for constructing stretchable integrated circuits, we propose a hybrid configuration composed of rigid device regions and liquid interconnects, which is constructed on a rigid substrate first but highly stretchable after being transferred onto an elastomeric substrate. This new method can be useful in various applications requiring both high-resolution and precisely aligned patterning of gallium-based liquid metals. PMID:27250997

  1. Integrated Power Flow and Short Circuit Calculation Method for Distribution Network with Inverter Based Distributed Generation

    Directory of Open Access Journals (Sweden)

    Shan Yang

    2016-01-01

    Full Text Available Power flow calculation and short circuit calculation are the basis of theoretical research for distribution network with inverter based distributed generation. The similarity of equivalent model for inverter based distributed generation during normal and fault conditions of distribution network and the differences between power flow and short circuit calculation are analyzed in this paper. Then an integrated power flow and short circuit calculation method for distribution network with inverter based distributed generation is proposed. The proposed method let the inverter based distributed generation be equivalent to Iθ bus, which makes it suitable to calculate the power flow of distribution network with a current limited inverter based distributed generation. And the low voltage ride through capability of inverter based distributed generation can be considered as well in this paper. Finally, some tests of power flow and short circuit current calculation are performed on a 33-bus distribution network. The calculated results from the proposed method in this paper are contrasted with those by the traditional method and the simulation method, whose results have verified the effectiveness of the integrated method suggested in this paper.

  2. 2.3 µm range InP-based type-II quantum well Fabry-Perot lasers heterogeneously integrated on a silicon photonic integrated circuit.

    Science.gov (United States)

    Wang, Ruijun; Sprengel, Stephan; Boehm, Gerhard; Muneeb, Muhammad; Baets, Roel; Amann, Markus-Christian; Roelkens, Gunther

    2016-09-01

    Heterogeneously integrated InP-based type-II quantum well Fabry-Perot lasers on a silicon waveguide circuit emitting in the 2.3 µm wavelength range are demonstrated. The devices consist of a "W"-shaped InGaAs/GaAsSb multi-quantum-well gain section, III-V/silicon spot size converters and two silicon Bragg grating reflectors to form the laser cavity. In continuous-wave (CW) operation, we obtain a threshold current density of 2.7 kA/cm2 and output power of 1.3 mW at 5 °C for 2.35 μm lasers. The lasers emit over 3.7 mW of peak power with a threshold current density of 1.6 kA/cm2 in pulsed regime at room temperature. This demonstration of heterogeneously integrated lasers indicates that the material system and heterogeneous integration method are promising to realize fully integrated III-V/silicon photonics spectroscopic sensors in the 2 µm wavelength range. PMID:27607711

  3. Back End of Line Nanorelays for Ultra-low Power Monolithic Integrated NEMS-CMOS Circuits

    KAUST Repository

    Lechuga Aranda, Jesus Javier

    2016-05-01

    Since the introduction of Complementary-Metal-Oxide-Semiconductor (CMOS) technology, the chip industry has enjoyed many benefits of transistor feature size scaling, including higher speed and device density and improved energy efficiency. However, in the recent years, the IC designers have encountered a few roadblocks, namely reaching the physical limits of scaling and also increased device leakage which has resulted in a slow-down of supply voltage and power density scaling. Therefore, there has been an extensive hunt for alternative circuit architectures and switching devices that can alleviate or eliminate the current crisis in the semiconductor industry. The Nano-Electro-Mechanical (NEM) relay is a promising alternative switch that offers zero leakage and abrupt turn-on behaviour. Even though these devices are intrinsically slower than CMOS transistors, new circuit design techniques tailored for the electromechanical properties of such devices can be leveraged to design medium performance, ultra-low power integrated circuits. In this thesis, we deal with a new generation of such devices that is built in the back end of line (BEOL) CMOS process and is an ideal option for full integration with current CMOS transistor technology. Simulation and verification at the circuit and system level is a critical step in the design flow of microelectronic circuits, and this is especially important for new technologies that lack the standard design infrastructure and well-known verification platforms. Although most of the physical and electrical properties of NEM structures can be simulated using standard electronic automation software, there is no report of a reliable behavioural model for NEMS switches that enable large circuit simulations. In this work, we present an optimised model of a BEOL nano relay that encompasses all the electromechanical characteristics of the device and is robust and lightweight enough for VLSI applications that require simulation of thousands of

  4. Advanced field-solver techniques for RC extraction of integrated circuits

    CERN Document Server

    Yu, Wenjian

    2014-01-01

    Resistance and capacitance (RC) extraction is an essential step in modeling the interconnection wires and substrate coupling effect in nanometer-technology integrated circuits (IC). The field-solver techniques for RC extraction guarantee the accuracy of modeling, and are becoming increasingly important in meeting the demand for accurate modeling and simulation of VLSI designs. Advanced Field-Solver Techniques for RC Extraction of Integrated Circuits presents a systematic introduction to, and treatment of, the key field-solver methods for RC extraction of VLSI interconnects and substrate coupling in mixed-signal ICs. Various field-solver techniques are explained in detail, with real-world examples to illustrate the advantages and disadvantages of each algorithm. This book will benefit graduate students and researchers in the field of electrical and computer engineering, as well as engineers working in the IC design and design automation industries. Dr. Wenjian Yu is an Associate Professor at the Department of ...

  5. Integrated bistable generator for wideband energy harvesting with optimized synchronous electric charge extraction circuit

    International Nuclear Information System (INIS)

    Bistable generators have been proposed as potential solutions to the challenge of variable vibration frequencies. In the authors' previous works, a specific BSM (Buckled-Spring-Mass) harvester architecture has been suggested. It presents some properties of interests: simplicity, compactness and wide bandwidth. Using a normalized model of the BSM generator for design and optimization at different scales, this paper presents a new integrated BSM bistable generator design with the OSECE (Optimized Synchronous Electric Charge Extraction) technique which is used for broadband energy harvesting. The experimental results obtained from an initial prototype device show that the BSM generator with the OSECE circuit exhibits better performance for low coupling cases or reverse sweep excitations. This is also confirmed by simulations for the proposed integrated generator. Good applications prospective is expected for the bistable generator with the nonlinear OSECE circuit

  6. Photonic crystal ring resonator based optical filters for photonic integrated circuits

    International Nuclear Information System (INIS)

    In this paper, a two Dimensional (2D) Photonic Crystal Ring Resonator (PCRR) based optical Filters namely Add Drop Filter, Bandpass Filter, and Bandstop Filter are designed for Photonic Integrated Circuits (PICs). The normalized output response of the filters is obtained using 2D Finite Difference Time Domain (FDTD) method and the band diagram of periodic and non-periodic structure is attained by Plane Wave Expansion (PWE) method. The size of the device is minimized from a scale of few tens of millimeters to the order of micrometers. The overall size of the filters is around 11.4 μm × 11.4 μm which is highly suitable of photonic integrated circuits

  7. Heavy-ion induced single-event upset in integrated circuits

    Science.gov (United States)

    Zoutendyk, J. A.

    1991-01-01

    The cosmic ray environment in space can affect the operation of Integrated Circuit (IC) devices via the phenomenon of Single Event Upset (SEU). In particular, heavy ions passing through an IC can induce sufficient integrated current (charge) to alter the state of a bistable circuit, for example a memory cell. The SEU effect is studied in great detail in both static and dynamic memory devices, as well as microprocessors fabricated from bipolar, Complementary Metal Oxide Semiconductor (CMOS) and N channel Metal Oxide Semiconductor (NMOS) technologies. Each device/process reflects its individual characteristics (minimum scale geometry/process parameters) via a unique response to the direct ionization of electron hole pairs by heavy ion tracks. A summary of these analytical and experimental SEU investigations is presented.

  8. Photonic crystal ring resonator based optical filters for photonic integrated circuits

    Energy Technology Data Exchange (ETDEWEB)

    Robinson, S., E-mail: mail2robinson@gmail.com [Department of Electronics and Communication Engineering, Mount Zion College of Engineering and Technology, Pudukkottai-622507, Tamil Nadu (India)

    2014-10-15

    In this paper, a two Dimensional (2D) Photonic Crystal Ring Resonator (PCRR) based optical Filters namely Add Drop Filter, Bandpass Filter, and Bandstop Filter are designed for Photonic Integrated Circuits (PICs). The normalized output response of the filters is obtained using 2D Finite Difference Time Domain (FDTD) method and the band diagram of periodic and non-periodic structure is attained by Plane Wave Expansion (PWE) method. The size of the device is minimized from a scale of few tens of millimeters to the order of micrometers. The overall size of the filters is around 11.4 μm × 11.4 μm which is highly suitable of photonic integrated circuits.

  9. Amorphous Zinc Oxide Integrated Wavy Channel Thin Film Transistor Based High Performance Digital Circuits

    KAUST Repository

    Hanna, Amir

    2015-12-04

    High performance thin film transistor (TFT) can be a great driving force for display, sensor/actuator, integrated electronics, and distributed computation for Internet of Everything applications. While semiconducting oxides like zinc oxide (ZnO) present promising opportunity in that regard, still wide area of improvement exists to increase the performance further. Here, we show a wavy channel (WC) architecture for ZnO integrated TFT which increases transistor width without chip area penalty, enabling high performance in material agnostic way. We further demonstrate digital logic NAND circuit using the WC architecture and compare it to the conventional planar architecture. The WC architecture circuits have shown 2× higher peak-to-peak output voltage for the same input voltage. They also have 3× lower high-to-low propagation delay times, respectively, when compared to the planar architecture. The performance enhancement is attributed to both extra device width and enhanced field effect mobility due to higher gate field electrostatics control.

  10. Reduction of EMC Emissions in Mixed Signal Integrated Circuits with Embedded LIN Driver

    OpenAIRE

    Hartl, P; M. Kuban; P. Horsky

    2016-01-01

    This paper describes several methods for reduction of electromagnetic emissions (EME) of mixed signal integrated circuits (IC). The focus is on the impact that a LIN bus communication block has on a complex IC which contains analog blocks, noisy digital block, micro-core (µC) and several types of memories. It is used in an automotive environment, where EMC emission reduction is one of the key success factors. Several proposed methods for EME reduction are described and implemented on three te...

  11. Digital measuring scheme for half-wave voltage of Y-tap multiple integrated optical circuit

    Institute of Scientific and Technical Information of China (English)

    Yuanhong Yang(杨远洪); Hongtao Yu(于洪涛)

    2004-01-01

    A high-precision digital measuring scheme for half-wave voltage of Y-tap multiple integrated optical circuits is proposed. This scheme is based on Sagnac interferometer modulated with digital step waveform whose frequency is half of eigen frequency of the interferometer. The technology and measuring precision are discussed. An experimental setup is made and the temperature-dependences of half-wave voltage of two samples are studied. Analysis and experimental study prove that this scheme is convenient and accurate.

  12. Tolerant polarization converter for InGaAsP-InP photonic integrated circuits.

    Science.gov (United States)

    Dzibrou, Dzmitry O; van der Tol, Jos J G M; Smit, Meint K

    2013-09-15

    We report the fabrication and characterization of a new polarization converter for InGaAsP-InP photonic integrated circuits. The converter consists of two right trapezoidal sections with the angled sidewalls etched wetly. The converters show a greatly improved tolerance to variations of the fabrication, an averaged efficiency of polarization conversion of 99.8% and a loss of about 0.7 dB at a wavelength of 1.535 μm. PMID:24104793

  13. Wideband Monolithic Microwave Integrated Circuit Frequency Converters with GaAs mHEMT Technology

    DEFF Research Database (Denmark)

    Krozer, Viktor; Johansen, Tom Keinicke; Djurhuus, Torsten; Vidkjær, Jens

    We present monolithic microwave integrated circuit (MMIC) frequency converter, which can be used for up and down conversion, due to the large RF and IF port bandwidth. The MMIC converters are based on commercially available GaAs mHEMT technology and are comprised of a Gilbert mixer cell core......B. Simulated results are supported by experimental characterization. Good agreement is found between simulations and experiment is found after adjustment of technology parameters....

  14. The Effected Oxide Capacitor in CMOS Structure of Integrated Circuit Level 5 Micrometer Technology

    OpenAIRE

    Rodthong, S.; Burapattanasiri, B.

    2009-01-01

    This article is present the effected oxide capacitor in CMOS structure of integrated circuit level 5 micrometer technology. It has designed and basic structure of MOS diode. It establish with aluminum metallization layer by sputtering method, oxide insulator layer mode from silicon dioxide, n+ and p+ semiconductor layer, it has high capacitance concentrate. From the MOS diode structure silicon dioxide thickness 0.5 micrometer, it will get capacitance between aluminum metal layer and p+ semico...

  15. Terahertz applications of integrated circuits based on intrinsic Josephson junctions in high Tc superconductors

    Science.gov (United States)

    Wang, Huabing; Wu, Peiheng; Yamashita, Tsutomu

    2001-10-01

    Using a newly developed double-side fabrication method, an IJJ stack plus a bow-tie antenna and chokes were integrated in a slice 200 nm thick and singled out from inside a bulk Bi2Sr2CaCu2O8+x (BSCCO) single crystal. The junctions in the fabricated stack were very uniform, and the number of junctions involved was rather controllable. In addition to this method, which can be used to fabricate integrated circuits based on intrinsic Josephson junctions in high temperature (Tc) superconductors, also reported will be terahertz responses of IJJs, and the possible applications in quantum voltage standard, spectroscopy, and so on.

  16. Analog integrated circuits for the Lotka-Volterra competitive neural networks.

    Science.gov (United States)

    Asai, T; Ohtani, M; Yonezu, H

    1999-01-01

    A subthreshold MOS integrated circuit (IC) is designed and fabricated for implementing a competitive neural network of the Lotka-Volterra (LV) type which is derived from conventional membrane dynamics of neurons and is used for the selection of external inputs. The steady-state solutions to the LV equation can be classified into three types, each of which represents qualitatively different selection behavior. Among the solutions, the winners-share-all (WSA) solution in which a certain number of neurons remain activated in steady states is particularly useful owing to robustness in the selection of inputs from a noisy environment. The measured results of the fabricated LV IC's agree well with the theoretical prediction as long as the influence of device mismatches is small. Furthermore, results of extensive circuit simulations prove that the large-scale LV circuit producing the WSA solution does exhibit a reliable selection compared with winner-take-all circuits, in the possible presence of device mismatches. PMID:18252623

  17. A fully integrated BPSK amplitude and spectrum tunable transmitter for IR-UWB system

    International Nuclear Information System (INIS)

    A 3-5 GHz low power BPSK modulated impulse radio UWB transmitter is implemented in 0.13 μm CMOS technology. In this design the amplitude and spectrum of the output impulse are both tunable to solve the special problem in IR-UWB, where it is difficult to control the spectrum. Measurement results indicate that, by changing the control bits in the gain control circuit and differential circuit, the 3-step peak-to-peak voltage amplitudes are 240, 170 and 115 mV and the center frequency of the impulse can be tuned from 3.2 to 4.1 GHz. A power controlled output buffer is designed to drive the antenna. The total power consumption is only 4.44 mW when transmitting a baseband signal of 100 MHz. The chip area is 1.2 x 1.4 mm2.

  18. 76 FR 19174 - In the Matter of Circuit Systems, Inc., Global Energy Group, Inc., Integrated Medical Resources...

    Science.gov (United States)

    2011-04-06

    ... From the Federal Register Online via the Government Publishing Office SECURITIES AND EXCHANGE COMMISSION File No. 500-1 In the Matter of Circuit Systems, Inc., Global Energy Group, Inc., Integrated... information concerning the securities of Circuit Systems, Inc. because it has not filed any periodic...

  19. Erbium-doped zinc-oxide waveguide amplifiers for hybrid photonic integrated circuits

    Science.gov (United States)

    O'Neal, Lawrence; Anthony, Deion; Bonner, Carl; Geddis, Demetris

    2016-02-01

    CMOS logic circuits have entered the sub-100nm regime, and research is on-going to investigate the quantum effects that are apparent at this dimension. To avoid some of the constraints imposed by fabrication, entropy, energy, and interference considerations for nano-scale devices, many have begun designing hybrid and/or photonic integrated circuits. These circuits consist of transistors, light emitters, photodetectors, and electrical and optical waveguides. As attenuation is a limiting factor in any communications system, it is advantageous to integrate a signal amplifier. There are numerous examples of electrical amplifiers, but in order to take advantage of the benefits provided by optically integrated systems, optical amplifiers are necessary. The erbium doped fiber amplifier is an example of an optical amplifier which is commercially available now, but the distance between the amplifier and the device benefitting from amplification can be decreased and provide greater functionality by providing local, on-chip amplification. Zinc oxide is an attractive material due to its electrical and optical properties. Its wide bandgap (≍3.4 eV) and high refractive index (≍2) make it an excellent choice for integrated optics systems. Moreover, erbium doped zinc oxide (Er:ZnO) is a suitable candidate for optical waveguide amplifiers because of its compatibility with semiconductor processing technology, 1.54 μm luminescence, transparency, low resistivity, and amplification characteristics. This research presents the characterization of radio frequency magnetron sputtered Er:ZnO, the design and fabrication of integrated waveguide amplifiers, and device analysis.

  20. Deterministic separation of arbitrary photon pair states in integrated quantum circuits

    CERN Document Server

    Marchildon, Ryan P

    2015-01-01

    Entangled photon pairs generated within integrated devices must often be spatially separated for their subsequent manipulation in quantum circuits. Separation that is both deterministic and universal can in principle be achieved through anti-coalescent two-photon quantum interference. However, such interference-facilitated pair separation (IFPS) has not been extensively studied in the integrated setting, where the strong polarization and wavelength dependencies of integrated couplers -- as opposed to bulk-optics beamsplitters -- can have important implications for performance beyond the identical-photon regime. This paper provides a detailed review of IFPS and examines how these dependencies impact separation fidelity and interference visibility. Focus is given to IFPS mediated by an integrated directional coupler. The analysis applies equally to both on-chip and in-fiber implementations, and can be expanded to other coupler architectures such as multimode interferometers. When coupler dispersion is present, ...

  1. I-RaCM: A Fully Integrated Risk and Lifecycle Cost Model Project

    Data.gov (United States)

    National Aeronautics and Space Administration — SpaceWorks Engineering, Inc. (SEI) proposes development of the Integrated Risk and Cost Model I-RaCM, as the innovation to meet the need for integrated cost and...

  2. A contact lens with integrated telecommunication circuit and sensors for wireless and continuous tear glucose monitoring

    International Nuclear Information System (INIS)

    We present an integrated functional contact lens, composed of a differential glucose sensor module, metal interconnects, sensor read-out circuit, antenna and telecommunication circuit, to monitor tear glucose levels wirelessly, continuously and non-invasively. The electrochemical differential sensor module is based on immobilization of activated and de-activated glucose oxidase. We characterized the sensor on a model polymer eye and determined that it showed good repeatability, molecular interference rejection and linearity in the range of 0–2 mM glucose, covering normal tear glucose concentrations (0.1–0.6 mM). We also report the temperature, ageing and protein-fouling sensitivity of the sensor. We report the design and implementation of a low-power (3 µW) sensor read-out and telecommunication circuit to deliver wireless power and transmit data for the sensor module. Using this small chip (0.36 mm2), we produced an integrated contact lens with sensors and demonstrated wireless operation of the system and glucose read-out over the distance of several centimeters. (paper)

  3. The functional significance of newly born neurons integrated into olfactory bulb circuits

    Directory of Open Access Journals (Sweden)

    Masayuki eSakamoto

    2014-05-01

    Full Text Available The olfactory bulb (OB is the first central processing center for olfactory information connecting with higher areas in the brain, and this neuronal circuitry mediates a variety of odor-evoked behavioral responses. In the adult mammalian brain, continuous neurogenesis occurs in two restricted regions, the subventricular zone (SVZ of the lateral ventricle and the hippocampal dentate gyrus. New neurons born in the SVZ migrate through the rostral migratory stream and are integrated into the neuronal circuits of the OB throughout life. The significance of this continuous supply of new neurons in the OB has been implicated in plasticity and memory regulation. Two decades of huge investigation in adult neurogenesis revealed the biological importance of integration of new neurons into the olfactory circuits. In this review, we highlight the recent findings about the physiological functions of newly generated neurons in rodent OB circuits and then discuss the contribution of neurogenesis in the brain function. Finally, we introduce cutting edge technologies to monitor and manipulate the activity of new neurons.

  4. 6H-SiC Transistor Integrated Circuits Demonstrating Prolonged Operation at 500 C

    Science.gov (United States)

    Neudeck, Philip G.; Spry, David J.; Chen, Liang-Yu; Chang, Carl W.; Beheim, Glenn M.; Okojie, Robert S.; Evans, Laura J.; Meredith, Roger; Ferrier, Terry; Krasowski, Michael J.; Prokop, Norman F.

    2008-01-01

    The NASA Glenn Research Center is developing very high temperature semiconductor integrated circuits (ICs) for use in the hot sections of aircraft engines and for Venus exploration where ambient temperatures are well above the approximately 300 degrees Centigrade effective limit of silicon-on-insulator IC technology. In order for beneficial technology insertion to occur, such transistor ICs must be capable of prolonged operation in such harsh environments. This paper reports on the fabrication and long-term 500 degrees Centigrade operation of 6H-SiC integrated circuits based on epitaxial 6H-SiC junction field effect transistors (JFETs). Simple analog amplifier and digital logic gate ICs have now demonstrated thousands of hours of continuous 500 degrees Centigrade operation in oxidizing air atmosphere with minimal changes in relevant electrical parameters. Electrical characterization and modeling of transistors and circuits at temperatures from 24 degrees Centigrade to 500 degrees Centigrade is also described. Desired analog and digital IC functionality spanning this temperature range was demonstrated without changing the input signals or power supply voltages.

  5. A contact lens with integrated telecommunication circuit and sensors for wireless and continuous tear glucose monitoring

    Science.gov (United States)

    Yao, H.; Liao, Y.; Lingley, A. R.; Afanasiev, A.; Lähdesmäki, I.; Otis, B. P.; Parviz, B. A.

    2012-07-01

    We present an integrated functional contact lens, composed of a differential glucose sensor module, metal interconnects, sensor read-out circuit, antenna and telecommunication circuit, to monitor tear glucose levels wirelessly, continuously and non-invasively. The electrochemical differential sensor module is based on immobilization of activated and de-activated glucose oxidase. We characterized the sensor on a model polymer eye and determined that it showed good repeatability, molecular interference rejection and linearity in the range of 0-2 mM glucose, covering normal tear glucose concentrations (0.1-0.6 mM). We also report the temperature, ageing and protein-fouling sensitivity of the sensor. We report the design and implementation of a low-power (3 µW) sensor read-out and telecommunication circuit to deliver wireless power and transmit data for the sensor module. Using this small chip (0.36 mm2), we produced an integrated contact lens with sensors and demonstrated wireless operation of the system and glucose read-out over the distance of several centimeters.

  6. A prediction technique for single-event effects on complex integrated circuits

    International Nuclear Information System (INIS)

    The sensitivity of complex integrated circuits to single-event effects is investigated. Sensitivity depends not only on the cross section of physical modules but also on the behavior of data patterns running on the system. A method dividing the main functional modules is proposed. The intrinsic cross section and the duty cycles of different sensitive modules are obtained during the execution of data patterns. A method for extracting the duty cycle is presented and a set of test patterns with different duty cycles are implemented experimentally. By combining the intrinsic cross section and the duty cycle of different sensitive modules, a universal method to predict SEE sensitivities of different test patterns is proposed, which is verified by experiments based on the target circuit of a microprocessor. Experimental results show that the deviation between prediction and experiment is less than 20%. (paper)

  7. Single-Event Upset and Snapback in Silicon-on-Insulator Devices and Integrated Circuits

    Energy Technology Data Exchange (ETDEWEB)

    DODD,PAUL E.; SHANEYFELT,MARTY R.; WALSH,DAVID S.; SCHWANK,JAMES R.; HASH,GERALD L.; LOEMKER,RHONDA ANN; DRAPER,BRUCE L.; WINOKUR,PETER S.

    2000-08-15

    The characteristics Of ion-induced charge collection and single-event upset are studied in SOI transistors and circuits with various body tie structures. Impact ionization effects including single-event snapback are shown to be very important. Focused ion microbeam experiments are used to find single-event snapback drain voltage thresholds in n-channel SOI transistors as a function of device width. Three-Dimensional device simulations are used to determine single-event upset and snapback thresholds in SOI SRAMS, and to study design tradeoffs for various body-tie structures. A window of vulnerability to single-event snapback is shown to exist below the single-event upset threshold. The presence of single-event snapback in commercial SOI SRAMS is confirmed through broadbeam ion testing, and implications for hardness assurance testing of SOI integrated circuits are discussed.

  8. Monolithically mode division multiplexing photonic integrated circuit for large-capacity optical interconnection.

    Science.gov (United States)

    Chen, Guanyu; Yu, Yu; Zhang, Xinliang

    2016-08-01

    We propose and fabricate an on-chip mode division multiplexed (MDM) photonic interconnection system. Such a monolithically photonic integrated circuit (PIC) is composed of a grating coupler, two micro-ring modulators, mode multiplexer/demultiplexer, and two germanium photodetectors. The signals' generation, multiplexing, transmission, demultiplexing, and detection are successfully demonstrated on the same chip. Twenty Gb/s MDM signals are successfully processed with clear and open eye diagrams, validating the feasibility of the proposed circuit. The measured power penalties show a good performance of the MDM link. The proposed on-chip MDM system can be potentially used for large-capacity optical interconnection in future high-performance computers and big data centers. PMID:27472614

  9. Optical devices for ultra-compact photonic integrated circuits based on III-V/polymer nanowires

    Science.gov (United States)

    Lauvernier, D.; Garidel, S.; Zegaoui, M.; Vilcot, J. P.; Harari, J.; Magnin, V.; Decoster, D.

    2007-04-01

    We demonstrated the potential application of III-V/polymer nanowires for photonic integrated circuits in a previous paper. Hereby, we report the use of a spot size converter based on 2D reverse nanotaper structure in order to improve the coupling efficiency between the nanowire and optical fiber. A total coupling enhancement of up to a factor 60 has been measured from an 80 nm × 300 nm cross-section tip which feeds an 300 nm-side square nanowire at its both ends. Simultaneously, micro-radius bends have been fabricated to increase the circuit density; for a radius of 5 µm, the 90º bend losses were measured as low as 0.60 dB and 0.80 dB for TE and TM polarizations respectively.

  10. Charge Yield at Low Electric Fields: Considerations for Bipolar Integrated Circuits

    Science.gov (United States)

    Johnston, A. H.; Swimm, R. T.; Thorbourn, D. O.

    2013-01-01

    A significant reduction in total dose damage is observed when bipolar integrated circuits are irradiated at low temperature. This can be partially explained by the Onsager theory of recombination, which predicts a strong temperature dependence for charge yield under low-field conditions. Reduced damage occurs for biased as well as unbiased devices because the weak fringing field in thick bipolar oxides only affects charge yield near the Si/SiO2 interface, a relatively small fraction of the total oxide thickness. Lowering the temperature of bipolar ICs - either continuously, or for time periods when they are exposed to high radiation levels - provides an additional degree of freedom to improve total dose performance of bipolar circuits, particularly in space applications.

  11. A SQUID gradiometer module with wire-wound pickup antenna and integrated voltage feedback circuit

    International Nuclear Information System (INIS)

    The performance of the direct readout schemes for dc SQUID, Additional Positive Feedback (APF), noise cancellation (NC) and SQUID bootstrap circuit (SBC), have been studied in conjunction with planar SQUID magnetometers. In this paper, we examine the NC technique applied to a niobium SQUID gradiometer module with an Nb wire-wound antenna connecting to a dual-loop SQUID chip with an integrated voltage feedback circuit for suppression of the preamplifier noise contribution. The sensitivity of the SQUID gradiometer module is measured to be about 1 fT/(cm √Hz) in the white noise range in a magnetically shielded room. Using such gradiometer, both MCG and MEG signals are recorded.

  12. A complementary metal oxide semiconductor—integrable conditioning circuit for resistive chemical sensor management

    International Nuclear Information System (INIS)

    This paper presents a new interface circuit (for MOX-based resistive chemical sensors) capable of overcoming the main limit of the circuits based on the resistance-to-time approach, i.e. the long measuring time with high-value resistances. The system is designed to operate with a single supply of 3.3 V, thus facilitating an ASIC implementation together with digital electronics for a first data analysis and transmission. This is particularly advantageous when the elaboration process requires a large computational load and a data pre-elaboration is advisable. Simulations of the integrable solution of the system have shown the feasibility of the proposed approach. A prototype with discrete components has been furthermore fabricated and experimentally tested, showing good performance in the range 0.5 MΩ to 10 GΩ with a maximum measuring time of 60 ms

  13. A Zinc Oxide Nanorod Ammonia Microsensor Integrated with a Readout Circuit on-a-Chip

    Directory of Open Access Journals (Sweden)

    Chyan-Chyi Wu

    2011-11-01

    Full Text Available A zinc oxide nanorod ammonia microsensor integrated with a readout circuit on-a-chip fabricated using the commercial 0.35 mm complementary metal oxide semiconductor (CMOS process was investigated. The structure of the ammonia sensor is composed of a sensitive film and polysilicon electrodes. The ammonia sensor requires a post-process to etch the sacrificial layer, and to coat the sensitive film on the polysilicon electrodes. The sensitive film that is prepared by a hydrothermal method is made of zinc oxide. The sensor resistance changes when the sensitive film adsorbs or desorbs ammonia gas. The readout circuit is used to convert the sensor resistance into the voltage output. Experiments show that the ammonia sensor has a sensitivity of about 1.5 mV/ppm at room temperature.

  14. Design and implementation of Gm-APD array readout integrated circuit for infrared 3D imaging

    Science.gov (United States)

    Zheng, Li-xia; Yang, Jun-hao; Liu, Zhao; Dong, Huai-peng; Wu, Jin; Sun, Wei-feng

    2013-09-01

    A single-photon detecting array of readout integrated circuit (ROIC) capable of infrared 3D imaging by photon detection and time-of-flight measurement is presented in this paper. The InGaAs avalanche photon diodes (APD) dynamic biased under Geiger operation mode by gate controlled active quenching circuit (AQC) are used here. The time-of-flight is accurately measured by a high accurate time-to-digital converter (TDC) integrated in the ROIC. For 3D imaging, frame rate controlling technique is utilized to the pixel's detection, so that the APD related to each pixel should be controlled by individual AQC to sense and quench the avalanche current, providing a digital CMOS-compatible voltage pulse. After each first sense, the detector is reset to wait for next frame operation. We employ counters of a two-segmental coarse-fine architecture, where the coarse conversion is achieved by a 10-bit pseudo-random linear feedback shift register (LFSR) in each pixel and a 3-bit fine conversion is realized by a ring delay line shared by all pixels. The reference clock driving the LFSR counter can be generated within the ring delay line Oscillator or provided by an external clock source. The circuit is designed and implemented by CSMC 0.5μm standard CMOS technology and the total chip area is around 2mm×2mm for 8×8 format ROIC with 150μm pixel pitch. The simulation results indicate that the relative time resolution of the proposed ROIC can achieve less than 1ns, and the preliminary test results show that the circuit function is correct.

  15. Long-Term Characterization of 6H-SiC Transistor Integrated Circuit Technology Operating at 500 C

    Science.gov (United States)

    Neudeck, Philip G.; Spry, David J.; Chen, Liang-Yu; Chang, Carl W.; Beheim, Glenn M.; Okojie, Robert S.; Evans, Laura J.; Meredith Roger D.; Ferrier, Terry L.; Krasowski, Michael J.; Prokop, Norman F.

    2008-01-01

    NASA has been developing very high temperature semiconductor integrated circuits for use in the hot sections of aircraft engines and for Venus exploration. This paper reports on long-term 500 C electrical operation of prototype 6H-SiC integrated circuits based on epitaxial 6H-SiC junction field effect transistors (JFETs). As of this writing, some devices have surpassed 4000 hours of continuous 500 C electrical operation in oxidizing air atmosphere with minimal change in relevant electrical parameters.

  16. SmartStep: A Fully Integrated, Low-Power Insole Monitor

    OpenAIRE

    Nagaraj Hegde; Edward Sazonov

    2014-01-01

    Shoe-mounted wearable sensors can be used in applications, such as activity monitoring, gait analysis, post-stroke rehabilitation, body weight measurements and energy expenditure studies. Such wearable sensors typically require the modification or alteration of the shoe, which is not typically feasible for large populations without the direct involvement of shoe manufacturers. This article presents an insole-based wearable sensor (SmartStep) that has its electronics fully embedded into a gene...

  17. QIE10: a new front-end custom integrated circuit for high-rate experiments

    International Nuclear Information System (INIS)

    We present results on a new version of the QIE (Charge Integrator and Encoder), a custom Application Specific Integrated Circuit (ASIC) designed at Fermilab. Developed specifically for the measurement of charge from photo-detectors in high-rate environments, this most recent addition to the QIE family features 3 fC sensitivity, 17-bits of dynamic range with logarithmic response, a Time-to-Digital Converter (TDC) with sub-nanosecond resolution, and internal charge injection. The device is capable of dead-timeless operation at 40 MHz, making it ideal for calorimetry at the Large hadron Collider (LHC). We present bench measurements and integration studies that characterize the performance, radiation tolerance measurements, and plans for deployment in the Atlas and CMS detectors as part of the Phase 1 and Phase 2 upgrades

  18. Large-scale photonic integrated circuits for long-haul transmission and switching

    Science.gov (United States)

    Nagarajan, Radhakrishnan; Kato, Masaki; Pleumeekers, Jacco; Evans, Peter; Lambert, Damien; Chen, Arnold; Dominic, Vince; Mathur, Atul; Chavarkar, Prashant; Missey, Mark; Dentai, Andrew; Hurtt, Sheila; Bã¤Ck, Johan; Muthiah, Ranjani; Murthy, Sanjeev; Salvatore, Randal; Joyner, Charles; Rossi, Jon; Schneider, Richard; Ziari, Mehrdad; Tsai, Huan-Shang; Bostak, Jeffrey; Kauffman, Michael; Pennypacker, Stephen; Butrie, Timothy; Reffle, Michael; Mehuys, Dave; Mitchell, Matthew; Nilsson, Alan; Grubb, Stephen; Kish, Fred; Welch, David

    2007-02-01

    Dense wavelength division multiplexed (DWDM) large-scale, single-chip transmitter and receiver photonic integrated circuits (PICs), each capable of operating at 100 Gbits/s, have been deployed in the field since the end of 2004. These highly integrated InP chips have significantly changed the economics of long-haul optical transport networks. First, a review of the ten-channel, 100 Gbits/s PIC is presented. Then two extensions of the technology are demonstrated; first is wide temperature, coolerless operation of the 100 Gbits/s PIC, and second is a single integrated chip with 40 channels operating at 40 Gbits/s, capable of an aggregate data rate of 1.6 Tbits/s.

  19. Analysis and Design of Fully Integrated Planar Magnetics for Primary-Parallel Isolated Boost Converter

    DEFF Research Database (Denmark)

    Ouyang, Ziwei; Sen, Gökhan; Thomsen, Ole Cornelius;

    2013-01-01

    independently. Due to the low reluctance path provided by the shared I-core, the two input inductors can be integrated independently, and also the two transformers can be partially coupled each other. Detailed characteristics of the integrated structure have been studied in this paper. AC losses in the windings...

  20. Separate Brain Circuits Support Integrative and Semantic Priming in the Human Language System.

    Science.gov (United States)

    Feng, Gangyi; Chen, Qi; Zhu, Zude; Wang, Suiping

    2016-07-01

    Semantic priming is a crucial phenomenon to study the organization of semantic memory. A novel type of priming effect, integrative priming, has been identified behaviorally, whereby a prime word facilitates recognition of a target word when the 2 concepts can be combined to form a unitary representation. We used both functional and anatomical imaging approaches to investigate the neural substrates supporting such integrative priming, and compare them with those in semantic priming. Similar behavioral priming effects for both semantic (Bread-Cake) and integrative conditions (Cherry-Cake) were observed when compared with an unrelated condition. However, a clearly dissociated brain response was observed between these 2 types of priming. The semantic-priming effect was localized to the posterior superior temporal and middle temporal gyrus. In contrast, the integrative-priming effect localized to the left anterior inferior frontal gyrus and left anterior temporal cortices. Furthermore, fiber tractography showed that the integrative-priming regions were connected via uncinate fasciculus fiber bundle forming an integrative circuit, whereas the semantic-priming regions connected to the posterior frontal cortex via separated pathways. The results point to dissociable neural pathways underlying the 2 distinct types of priming, illuminating the neural circuitry organization of semantic representation and integration. PMID:26209843

  1. Vertical optical ring resonators fully integrated with nanophotonic waveguides on silicon-on-insulator substrates

    CERN Document Server

    Madani, Abbas; Stolarek, David; Zimmermann, Lars; Ma, Libo; Schmidt, Oliver G

    2015-01-01

    We demonstrate full integration of vertical optical ring resonators with silicon nanophotonic waveguides on silicon-on-insulator substrates to accomplish a significant step towards 3D photonic integration. The on-chip integration is realized by rolling up 2D differentially strained TiO2 nanomembranes into 3D microtube cavities on a nanophotonic microchip. The integration configuration allows for out of plane optical coupling between the in-plane nanowaveguides and the vertical microtube cavities as a compact and mechanically stable optical unit, which could enable refined vertical light transfer in 3D stacks of multiple photonic layers. In this vertical transmission scheme, resonant filtering of optical signals at telecommunication wavelengths is demonstrated based on subwavelength thick walled microcavities. Moreover, an array of microtube cavities is prepared and each microtube cavity is integrated with multiple waveguides which opens up interesting perspectives towards parallel and multi-routing through a ...

  2. A fully integrated, monolithic, cryogenic charge sensitive preamplifier using N-channel JFETs and polysilicon resistors

    International Nuclear Information System (INIS)

    In this paper, an integrated charge preamplifier to be used with small (10--30 mm2) Si(Li) and Ge(Li) X-ray detectors is described. The preamplifier is designed to operate at cryogenic temperatures (∼100 K to 160 K) for the best performance. An N-channel JFET process technology for integrated charge sensitive preamplifiers has been developed. The process integrates multiple pinch-off voltage JFETs fabricated in an n-type epitaxial layer on a low resistivity p-type substrate. The process also incorporates polysilicon resistors integrated on the same die as the JFETs. The optimized polysilicon resistors exhibit 1/f noise nearly as good as metal film resistors at the same current. Results for integrated amplifier are discussed

  3. Spherical particles and voids effect on current and potential distribution in integrated circuit leads

    International Nuclear Information System (INIS)

    Relationships of resistance with a width of 0.1 μm for different heights and currents at a given volt drop are plotted for a 0.2 μm length smooth copper lead. The lead is specified to connect with the integrated circuit AD8622 with its Isr = 0.350 mA to determine the volt drop = 0.2 mV. The total current is computed according to the total resistance of the lead for the different void radius at this volt drop. The current density value at the right boundary is determined by Ohm’s law. After combining the integration of the total current as a prerequisite with the interpolation of current density values from the left, i.e. void edge to the right boundaries, their distribution is obtained, showing current crowding outside of their edges and a great resistance with the increase of their radius. The calculation errors for comparison with the Laplace equation are calculated, mainly located on the corners of void. The potential distribution can be obtained by multiplying sheet resistance to current density distribution. At last, the relationship between resistance, total current, current crowding and calculation errors with the different void radius and lead length are offered in several forms for use in the integrated circuit design. (paper)

  4. Spherical particles and voids effect on current and potential distribution in integrated circuit leads

    Science.gov (United States)

    Pang, Dongqing; Sun, Yicai

    2015-06-01

    Relationships of resistance with a width of 0.1 μm for different heights and currents at a given volt drop are plotted for a 0.2 μm length smooth copper lead. The lead is specified to connect with the integrated circuit AD8622 with its Isr = 0.350 mA to determine the volt drop = 0.2 mV. The total current is computed according to the total resistance of the lead for the different void radius at this volt drop. The current density value at the right boundary is determined by Ohm’s law. After combining the integration of the total current as a prerequisite with the interpolation of current density values from the left, i.e. void edge to the right boundaries, their distribution is obtained, showing current crowding outside of their edges and a great resistance with the increase of their radius. The calculation errors for comparison with the Laplace equation are calculated, mainly located on the corners of void. The potential distribution can be obtained by multiplying sheet resistance to current density distribution. At last, the relationship between resistance, total current, current crowding and calculation errors with the different void radius and lead length are offered in several forms for use in the integrated circuit design.

  5. Multi-channel integrated circuits for the detection and measurement of ionizing radiation

    Energy Technology Data Exchange (ETDEWEB)

    Engel, G.L., E-mail: gengel@siue.edu [Department of Electrical and Computer Engineering, VLSI Design Research Laboratory, Engineering Building, Room 3043, Southern Illinois University Edwardsville, IL 62026 (United States); Duggireddi, N.; Vangapally, V. [Department of Electrical and Computer Engineering, VLSI Design Research Laboratory, Engineering Building, Room 3043, Southern Illinois University Edwardsville, IL 62026 (United States); Elson, J.M.; Sobotka, L.G.; Charity, R.J. [Departments of Chemistry and Physics, Washington University, Saint Louis, MO 63130 (United States)

    2011-10-01

    The Integrated Circuits (IC) Design Research Laboratory at Southern Illinois University Edwardsville (SIUE) has collaborated with the Nuclear Reactions Group at Washington University (WU) to develop a family of multi-channel integrated circuits. To date, the collaboration has successfully produced two micro-chips. The first was an analog shaped and peak sensing chip with on-board constant-fraction discriminators and sparsified readout. This chip is known as Heavy-Ion Nuclear Physics-16 Channel (HINP16C). The second chip, christened PSD8C, was designed to logically complement (in terms of detector types) the HINP16C chip. Pulse Shape Discrimination-8 Channel (PSD8C), featuring three settable charge integration windows per channel, performs pulse shape discrimination (PSD). This paper summarizes the design, capabilities, and features of the HINP16C and PSD8C ICs. It proceeds to discuss the modifications, made to the ICs and their associated systems, which have attempted to improve ease of use, increase performance, and extend capabilities. The paper concludes with a brief discussion of what may be the next chip (employing a multi-sampling scheme) to be added to our CMOS ASIC 'tool box' for radiation detection instrumentation.

  6. Evaluation of crud behavior in primary circuit of integral reactor by multi-region model

    International Nuclear Information System (INIS)

    In order to evaluate behavior of deposited crud from structural materials surfaces, multi-region model dealing with radioactive corrosion products behavior has been developed to describe crud behavior in primary circuit of the integral reactor. The primary circuit of the integral reactor, which was adopted ammoniated water chemistry, was divided into nine control volumes. The transportation of the radioactive nuclei by the sedimentation, washing-out, and release of corrosion products were considered between ths control volumes and its associated surfaces in the model. Specific activities of separate radionuclides in the primary coolant as well as on the surfaces of structural materials that were washed by the coolant throughout fuel cycle were also simulated with operation mode. As a result, this multi-regional model was capable of evaluating the behavior of crud more exactly than the two or three nodes model simulation codes. From this evaluation the integral reactor showed lower activities than the other commercial reactor because this was introduced the titanium alloy to the SG tube material and the avoidance of boric acid. (author)

  7. A metastable phase of tin in 3D integrated circuit solder microbumps

    International Nuclear Information System (INIS)

    A metastable phase of Sn has been found to co-exist with β-Sn in Pb-free SnAg microbumps in 3D integrated circuit technology. Synchrotron microbeam X-ray diffraction, high-resolution TEM imaging and selected-area electron diffraction were used to confirm the metastable phase, which has an orthorhombic lattice, with lattice parameter a = 0.635 nm, b = 0.639 nm, and c = 1.147 nm. Its composition is Sn containing a few percent of Ni. A higher rate of nucleation might have enabled its formation

  8. Two-dimensional parasitic capacitance extraction for integrated circuit with dual discrete geometric methods

    International Nuclear Information System (INIS)

    Capacitance extraction is one of the key issues in integrated circuits and also a typical electrostatic problem. The dual discrete geometric method (DGM) is investigated to provide relative solutions in two-dimensional unstructured mesh space. The energy complementary characteristic and quick field energy computation thereof based on it are emphasized. Contrastive analysis between the dual finite element methods and the dual DGMs are presented both from theoretical derivation and through case studies. The DGM, taking the scalar potential as unknown on dual interlocked meshes, with simple form and good accuracy, is expected to be one of the mainstreaming methods in associated areas. (paper)

  9. Reliability assessment of power plant instrumentation and control systems with monolithic integrated circuits

    International Nuclear Information System (INIS)

    The application of present generation of digital and analog monolithic integrated circuits (ICs) to operating nuclear power plant systems has resulted in components scaled down to less than 1/10th of the area of conventional components, and still function faster and more efficiently. Microprocessors and digital/analog ICs in monitoring and control systems have emerged as the preferred choice for power plant systems. This paper develops a reliability analysis for power plant systems with IC components assuming constant failure rate. A variable failure rate model is also developed for analyzing observed failure data to ascertain probable cause

  10. Report on the Minisession ''New developments in Flash ADC integrated circuits''

    International Nuclear Information System (INIS)

    New developments are taking place in the Flash Analog to Digital Converter marketplace. The big news is the digitization of VIDEO. It is expected to be a very large market and the merchant semiconductor and consumer electronics companies will be competing in selling these devices. The companies expect the initial selling price to be in the range of $ 7 - $15 for quantities of 10,000 units or more. This session was organized to expose the community to the new developments in FADC integrated circuits and the needs of physics instrumentation

  11. Rolled-up inductor structure for a radiofrequency integrated circuit (RFIC)

    Science.gov (United States)

    Li, Xiuling; Huang, Wen; Ferreira, Placid M.; Yu, Xin

    2015-12-29

    A rolled-up inductor structure for a radiofrequency integrated circuit (RFIC) comprises a multilayer sheet in a rolled configuration comprising multiple turns about a longitudinal axis. The multilayer sheet comprises a conductive pattern layer on a strain-relieved layer, and the conductive pattern layer comprises at least one conductive strip having a length extending in a rolling direction. The at least one conductive strip thereby wraps around the longitudinal axis in the rolled configuration. The conductive pattern layer may also comprise two conductive feed lines connected to the conductive strip for passage of electrical current therethrough. The conductive strip serves as an inductor cell of the rolled-up inductor structure.

  12. Optically controlled phased array antenna concepts using GaAs monolithic microwave integrated circuits

    Science.gov (United States)

    Kunath, R. R.; Bhasin, K. B.

    1986-01-01

    The desire for rapid beam reconfigurability and steering has led to the exploration of new techniques. Optical techniques have been suggested as potential candidates for implementing these needs. Candidates generally fall into one of two areas: those using fiber optic Beam Forming Networks (BFNs) and those using optically processed BFNs. Both techniques utilize GaAs Monolithic Microwave Integrated Circuits (MMICs) in the BFN, but the role of the MMIC for providing phase and amplitude variations is largely eliminated by some new optical processing techniques. This paper discusses these two types of optical BFN designs and provides conceptual designs of both systems.

  13. High-performance packaging for monolithic microwave and millimeter-wave integrated circuits

    Science.gov (United States)

    Shalkhauser, K. A.; Li, K.; Shih, Y. C.

    1992-01-01

    Packaging schemes are developed that provide low-loss, hermetic enclosure for enhanced monolithic microwave and millimeter-wave integrated circuits. These package schemes are based on a fused quartz substrate material offering improved RF performance through 44 GHz. The small size and weight of the packages make them useful for a number of applications, including phased array antenna systems. As part of the packaging effort, a test fixture was developed to interface the single chip packages to conventional laboratory instrumentation for characterization of the packaged devices.

  14. High-speed optical transceivers integrated circuits designs and optical devices techniques

    CERN Document Server

    Liu, Yuyu

    2006-01-01

    This book explores the unique advantages and large inherent transmission capacity of optical fiber communication systems. The long-term and high-risk research challenges of optical transceivers are analyzed with a view to sustaining the seemingly insatiable demand for bandwidth. A broad coverage of topics relating to the design of high-speed optical devices and integrated circuits, oriented to low power, low cost, and small area, is discussed. Written by specialists with many years of research and engineering experience in the field of optical fiber communication, this book is essential for an

  15. Analysis and optimization of TSV–TSV coupling in three-dimensional integrated circuits

    International Nuclear Information System (INIS)

    Through silicon via (TSV)–TSV coupling is detrimental to the performance of three-dimensional (3D) integrated circuits (ICs) with the major negative effect of introducing coupling noise. In order to obtain an accurate estimation of the coupling level from TSV–TSV in the early design stage, this paper first proposes an impedance-level model of the coupling channel between TSVs based on a two-port network, and then derives the formula of the coupling coefficient to describe the TSV–TSV coupling effect. The accuracy of the formula is validated by comparing the results with 3D full-wave simulations. Furthermore, a design technique for optimizing the coupling between adjacent coupled signal TSVs is proposed. Through SPICE simulations, the proposed technique shows its feasibility to reduce the coupling noise for both a simple TSV–TSV circuit and a complicated circuit with more TSVs, and demonstrates its potential for designers in achieving the goal of improving the electrical performance of 3D ICs. (paper)

  16. Hydrogenated Amorphous Silicon Sensor Deposited on Integrated Circuit for Radiation Detection

    CERN Document Server

    Despeisse, M; Jarron, P; Kaplon, J; Moraes, D; Nardulli, A; Powolny, F; Wyrsch, N

    2008-01-01

    Radiation detectors based on the deposition of a 10 to 30 mum thick hydrogenated amorphous silicon (a-Si:H) sensor directly on top of integrated circuits have been developed. The performance of this detector technology has been assessed for the first time in the context of particle detectors. Three different circuits were designed in a quarter micron CMOS technology for these studies. The so-called TFA (Thin-Film on ASIC) detectors obtained after deposition of a-Si:H sensors on the developed circuits are presented. High internal electric fields (104 to 105 V/cm) can be built in the a-Si:H sensor and overcome the low mobility of electrons and holes in this amorphous material. However, the deposited sensor's leakage current at such fields turns out to be an important parameter which limits the performance of a TFA detector. Its detailed study is presented as well as the detector's pixel segmentation. Signal induction by generated free carrier motion in the a-Si:H sensor has been characterized using a 660 nm pul...

  17. A space-qualified experiment integrating HTS digital circuits and small cryocoolers

    International Nuclear Information System (INIS)

    High temperature superconductors (HTS) promise to achieve electrical performance superior to that of conventional electronics. For application in space systems, HTS systems must simultaneously achieve lower power, weight, and volume than conventional electronics, and meet stringent space qualification and reliability requirements. Most effort to date has focused on passive RF/microwave applications. However, incorporation of active microwave components such as amplifiers, mixers, and phase shifters, and on-board high data rate digital signal processing is limited by the power and weight of their spacecraft electronic and support modules. Absence of data on active HTS components will prevent their utilization in space. To validate the feasibility in space of HTS circuits and components based on Josephson junctions, one needs to demonstrate HTS circuits and critical supporting technologies, such as space-qualified packaging and interconnects, closed-cycle cryocooling, and interface electronics. This paper describes the packaging, performance, and space test plan of an integrated, space-qualified experimental package consisting of HTS Josephson junction circuits and all the supporting components for NRL's high temperature superconductor space experiment (HTSSE-II). Most of the technical challenges and approaches are equally applicable to passive and active RF/microwave and digital electronic components, and this experiment will provide valuable validation data

  18. Analysis and optimization of TSV-TSV coupling in three-dimensional integrated circuits

    Science.gov (United States)

    Yingbo, Zhao; Gang, Dong; Yintang, Yang

    2015-04-01

    Through silicon via (TSV)-TSV coupling is detrimental to the performance of three-dimensional (3D) integrated circuits (ICs) with the major negative effect of introducing coupling noise. In order to obtain an accurate estimation of the coupling level from TSV-TSV in the early design stage, this paper first proposes an impedance-level model of the coupling channel between TSVs based on a two-port network, and then derives the formula of the coupling coefficient to describe the TSV-TSV coupling effect. The accuracy of the formula is validated by comparing the results with 3D full-wave simulations. Furthermore, a design technique for optimizing the coupling between adjacent coupled signal TSVs is proposed. Through SPICE simulations, the proposed technique shows its feasibility to reduce the coupling noise for both a simple TSV-TSV circuit and a complicated circuit with more TSVs, and demonstrates its potential for designers in achieving the goal of improving the electrical performance of 3D ICs. Project supported by the National Natural Science Foundation of China (No. 61334003).

  19. Integrated plasticity at inhibitory and excitatory synapses in the cerebellar circuit

    Directory of Open Access Journals (Sweden)

    Lisa eMapelli

    2015-05-01

    Full Text Available The way long-term potentiation (LTP and depression (LTD are integrated within the different synapses of brain neuronal circuits is poorly understood. In order to progress beyond the identification of specific molecular mechanisms, a system in which multiple forms of plasticity can be correlated with large-scale neural processing is required. In this paper we take as an example the cerebellar network , in which extensive investigations have revealed LTP and LTD at several excitatory and inhibitory synapses. Cerebellar LTP and LTD occur in all three main cerebellar subcircuits (granular layer, molecular layer, deep cerebellar nuclei and correspondingly regulate the function of their three main neurons: granule cells (GrCs, Purkinje cells (PCs and deep cerebellar nuclear (DCN cells. All these neurons, in addition to be excited, are reached by feed-forward and feed-back inhibitory connections, in which LTP and LTD may either operate synergistically or homeostatically in order to control information flow through the circuit. Although the investigation of individual synaptic plasticities in vitro is essential to prove their existence and mechanisms, it is insufficient to generate a coherent view of their impact on network functioning in vivo. Recent computational models and cell-specific genetic mutations in mice are shedding light on how plasticity at multiple excitatory and inhibitory synapses might regulate neuronal activities in the cerebellar circuit and contribute to learning and memory and behavioral control.

  20. Modeling for infrared readout integrated circuit based on Verilog-A

    Science.gov (United States)

    Wang, Xiao; Shi, Zelin

    2015-04-01

    Infrared detectors are the core of infrared imaging systems, while readout integrated circuits are the key components of detectors. In order to grasp the performance of circuits quickly and accurately, a method of circuit modeling using Verilog-A language is proposed, which present a behavioral simulation model for the ROIC. At first, a typical capacitor trans-impedance amplifier(CTIA) ROIC unit is showed, then the two essential parts of it,operational amplifier and switch are modeled on behavioral level. The op amp model concludes these non-ideal factors, such as finite gain-bandwidth product, input and output offset, output resistance and so on. Non-deal factors that affect switches are considered in the switch behavioral model, such as rise and fall time, on-resistance and so on. At last time-domain modeling method for noise is presented, which is compared with the classical frequency domain method for difference. The analysis results shows that in the situation that noise interested bandwidth(NIBW) is more than 5MHz, the difference between the two methods leads to less than 1% if the sample rate of noise is larger 4 times of the NIBW

  1. Fully integrated planar magnetics for primary-parallel isolated boost converter

    DEFF Research Database (Denmark)

    Ouyang, Ziwei; Sen, Gökhan; Thomsen, Ole Cornelius;

    2011-01-01

    -I-E core geometry. Due to a low reluctance path provided by the shared I-core, the two transformers as well as the two input inductors can be integrated independently, reducing the total ferrite volume and core loss. AC losses in the windings and the leakage inductance of the transformer are kept low by......A high efficient planar integrated magnetics (PIM) design approach for primary parallel isolated boost converters is presented. All magnetic components in the converter including two input inductors and two transformers with primary-parallel and secondary-series windings are integrated into an E...

  2. A Framework for Robust Multivariable Optimization of Integrated Circuits in Space Applications

    Science.gov (United States)

    DuMonthier, Jeffrey; Suarez, George

    2013-01-01

    Application Specific Integrated Circuit (ASIC) design for space applications involves multiple challenges of maximizing performance, minimizing power and ensuring reliable operation in extreme environments. This is a complex multidimensional optimization problem which must be solved early in the development cycle of a system due to the time required for testing and qualification severely limiting opportunities to modify and iterate. Manual design techniques which generally involve simulation at one or a small number of corners with a very limited set of simultaneously variable parameters in order to make the problem tractable are inefficient and not guaranteed to achieve the best possible results within the performance envelope defined by the process and environmental requirements. What is required is a means to automate design parameter variation, allow the designer to specify operational constraints and performance goals, and to analyze the results in a way which facilitates identifying the tradeoffs defining the performance envelope over the full set of process and environmental corner cases. The system developed by the Mixed Signal ASIC Group (MSAG) at the Goddard Space Flight Center is implemented as framework of software modules, templates and function libraries. It integrates CAD tools and a mathematical computing environment, and can be customized for new circuit designs with only a modest amount of effort as most common tasks are already encapsulated. Customization is required for simulation test benches to determine performance metrics and for cost function computation. Templates provide a starting point for both while toolbox functions minimize the code required. Once a test bench has been coded to optimize a particular circuit, it is also used to verify the final design. The combination of test bench and cost function can then serve as a template for similar circuits or be re-used to migrate the design to different processes by re-running it with the

  3. 75 FR 75694 - Certain Semiconductor Integration Circuits Using Tungsten Metallization and Products Containing...

    Science.gov (United States)

    2010-12-06

    ... determination to the U.S. Court of Appeals for the Federal Circuit (``Federal Circuit''). While the appeal was... responded. On November 15, 2010, the Federal Circuit issued an order vacating the Commission's...

  4. Vertical optical ring resonators fully integrated with nanophotonic waveguides on silicon-on-insulator substrates

    Science.gov (United States)

    Madani, Abbas; Kleinert, Moritz; Stolarek, David; Zimmermann, Lars; Ma, Libo; Schmidt, Oliver G.

    2015-08-01

    We demonstrate full integration of vertical optical ring resonators with silicon nanophotonic waveguides on silicon-on-insulator substrates to accomplish a significant step towards 3D photonic integration. The on-chip integration is realized by rolling up 2D differentially strained TiO2 nanomembranes into 3D microtube cavities on a nanophotonic microchip. The integration configuration allows for out of plane optical coupling between the in-plane nanowaveguides and the vertical microtube cavities as a compact and mechanically stable optical unit, which could enable refined vertical light transfer in 3D stacks of multiple photonic layers. In this vertical transmission scheme, resonant filtering of optical signals at telecommunication wavelengths is demonstrated based on subwavelength thick walled microcavities. Moreover, an array of microtube cavities is prepared and each microtube cavity is integrated with multiple waveguides which opens up interesting perspectives towards parallel and multi-routing through a single cavity device as well as high-throughput optofluidic sensing schemes.

  5. Demonstration of a fully integrated superconducting receiver with a 2.7 THz quantum cascade laser.

    Science.gov (United States)

    Miao, Wei; Lou, Zheng; Xu, Gang-Yi; Hu, Jie; Li, Shao-Liang; Zhang, Wen; Zhou, Kang-Min; Yao, Qi-Jun; Zhang, Kun; Duan, Wen-Ying; Shi, Sheng-Cai; Colombelli, Raffaele; Beere, Harvey E; Ritchie, David A

    2015-02-23

    We demonstrate for the first time the integration of a superconducting hot electron bolometer (HEB) mixer and a quantum cascade laser (QCL) on the same 4-K stage of a single cryostat, which is of particular interest for terahertz (THz) HEB/QCL integrated heterodyne receivers for practical applications. Two key issues are addressed. Firstly, a low power consumption QCL is adopted for preventing its heat dissipation from destroying the HEB's superconductivity. Secondly, a simple spherical lens located on the same 4-K stage is introduced to optimize the coupling between the HEB and the QCL, which has relatively limited output power owing to low input direct current (DC) power. Note that simulation techniques are used to design the HEB/QCL integrated heterodyne receiver to avoid the need for mechanical tuning. The integrated HEB/QCL receiver shows an uncorrected noise temperature of 1500 K at 2.7 THz, which is better than the performance of the same receiver with all the components not integrated. PMID:25836482

  6. Progress on the development of a fully integrated HTR code package

    International Nuclear Information System (INIS)

    A variety of computer codes have been developed, validated and optimized to simulate the different safety and operational aspects of HTRs. In order to overcome the present limitations of these codes and to exploit the advantages of modern computer clusters, a project has been initiated to integrate these individual programs into a consistent code package applying state-of-the-art programming techniques and standards. The HTR code package couples the related and recently applied physics models in a highly integrated manner. This will allow the steady-state and transient operating conditions of a full 3D reactor model to be simulated including new features such as fission product release calculations for each core zone or dust production and transport simulations. In this paper we report on the basic software architecture and the current status of this new integrated code system currently under development.

  7. Analog and VLSI circuits

    CERN Document Server

    Chen, Wai-Kai

    2009-01-01

    Featuring hundreds of illustrations and references, this book provides the information on analog and VLSI circuits. It focuses on analog integrated circuits, presenting the knowledge on monolithic device models, analog circuit cells, high performance analog circuits, RF communication circuits, and PLL circuits.

  8. Focal plane array readout integrated circuit with per-pixel analog-to-digital and digital-to-analog conversion

    Science.gov (United States)

    Kleinfelder, Stuart; Hottes, Alison; Pease, R. Fabian W.

    2000-07-01

    A pixel array readout integrated circuit (ROIC) containing per-pixel analog-to-digital conversion (ADC) and digital-to- analog conversion (DAC) for infrared detectors is presented with design and test result details. Fabricated in a standard 0.35 micron, 3.3 volt CMOS technology. the prototype consists of a linear array of 64 pixels, containing over 100 transistors per 30 by 30 micron pixel. The 8-bit per-pixel ADC is a Nyquist-rate single-slope design consisting of a three stage comparator and an 8 bit memory. This fully pixel- parallel ADC architecture operates in full-frame 'snapshot' mode and can reach over 1,000 frames per second. Each pixel also contains cascoded current source, globally biased to subtract an identical, fixed amount of current from each pixel in order to remove a common background signal by 'charge skimming.' It operates over more than 3 decades of current cancellation (approximately 10 pA to > 10 nA). As well, each pixel contains a 4 to 6+ bit current-mode DAC, intended to trim-out pixel-to-pixel variations in background current. It consists of 16 unit-cells of switched cascoded current sources per pixel, organized as two separately biased weights and controlled by a 16-bit per-pixel memory. The DAC operates over more than 4 decades of current cancellation (< 10 pA to approximately equals 100 nA) per least significant bit (LSB).

  9. Operational Excellence through Schedule Optimization and Production Simulation of Application Specific Integrated Circuits.

    Energy Technology Data Exchange (ETDEWEB)

    Flory, John Andrew [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Padilla, Denise D. [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Gauthier, John H. [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Zwerneman, April Marie [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Miller, Steven P [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)

    2016-05-01

    Upcoming weapon programs require an aggressive increase in Application Specific Integrated Circuit (ASIC) production at Sandia National Laboratories (SNL). SNL has developed unique modeling and optimization tools that have been instrumental in improving ASIC production productivity and efficiency, identifying optimal operational and tactical execution plans under resource constraints, and providing confidence in successful mission execution. With ten products and unprecedented levels of demand, a single set of shared resources, highly variable processes, and the need for external supplier task synchronization, scheduling is an integral part of successful manufacturing. The scheduler uses an iterative multi-objective genetic algorithm and a multi-dimensional performance evaluator. Schedule feasibility is assessed using a discrete event simulation (DES) that incorporates operational uncertainty, variability, and resource availability. The tools provide rapid scenario assessments and responses to variances in the operational environment, and have been used to inform major equipment investments and workforce planning decisions in multiple SNL facilities.

  10. Design optimization of integrated BiDi triplexer optical filter based on planar lightwave circuit

    Science.gov (United States)

    Xu, Chenglin; Hong, Xiaobin; Huang, Wei-Ping

    2006-05-01

    Design optimization of a novel integrated bi-directional (BiDi) triplexer filter based on planar lightwave circuit (PLC) for fiber-to-the premise (FTTP) applications is described. A multi-mode interference (MMI) device is used to filter the up-stream 1310nm signal from the down-stream 1490nm and 1555nm signals. An array waveguide grating (AWG) device performs the dense WDM function by further separating the two down-stream signals. The MMI and AWG are built on the same substrate with monolithic integration. The design is validated by simulation, which shows excellent performance in terms of filter spectral characteristics (e.g., bandwidth, cross-talk, etc.) as well as insertion loss.

  11. Capacitive Micro Pressure Sensor Integrated with a Ring Oscillator Circuit on Chip

    Directory of Open Access Journals (Sweden)

    Cheng-Yang Liu

    2009-12-01

    Full Text Available The study investigates a capacitive micro pressure sensor integrated with a ring oscillator circuit on a chip. The integrated capacitive pressure sensor is fabricated using the commercial CMOS (complementary metal oxide semiconductor process and a post-process. The ring oscillator is employed to convert the capacitance of the pressure sensor into the frequency output. The pressure sensor consists of 16 sensing cells in parallel. Each sensing cell contains a top electrode and a lower electrode, and the top electrode is a sandwich membrane. The pressure sensor needs a post-CMOS process to release the membranes after completion of the CMOS process. The post-process uses etchants to etch the sacrificial layers, and to release the membranes. The advantages of the post-process include easy execution and low cost. Experimental results reveal that the pressure sensor has a high sensitivity of 7 Hz/Pa in the pressure range of 0–300 kPa.

  12. A quantum entropy source on an InP photonic integrated circuit for random number generation

    CERN Document Server

    Abellan, Carlos; Domenech, David; Muñoz, Pascual; Capmany, Jose; Longhi, Stefano; Mitchell, Morgan W; Pruneri, Valerio

    2016-01-01

    Random number generators are essential to ensure performance in information technologies, including cryptography, stochastic simulations and massive data processing. The quality of random numbers ultimately determines the security and privacy that can be achieved, while the speed at which they can be generated poses limits to the utilisation of the available resources. In this work we propose and demonstrate a quantum entropy source for random number generation on an indium phosphide photonic integrated circuit made possible by a new design using two-laser interference and heterodyne detection. The resulting device offers high-speed operation with unprecedented security guarantees and reduced form factor. It is also compatible with complementary metal-oxide semiconductor technology, opening the path to its integration in computation and communication electronic cards, which is particularly relevant for the intensive migration of information processing and storage tasks from local premises to cloud data centre...

  13. New readout integrated circuit using continuous time fixed pattern noise correction

    Science.gov (United States)

    Dupont, Bertrand; Chammings, G.; Rapellin, G.; Mandier, C.; Tchagaspanian, M.; Dupont, Benoit; Peizerat, A.; Yon, J. J.

    2008-04-01

    LETI has been involved in IRFPA development since 1978; the design department (LETI/DCIS) has focused its work on new ROIC architecture since many years. The trend is to integrate advanced functions into the CMOS design to achieve cost efficient sensors production. Thermal imaging market is today more and more demanding of systems with instant ON capability and low power consumption. The purpose of this paper is to present the latest developments of fixed pattern noise continuous time correction. Several architectures are proposed, some are based on hardwired digital processing and some are purely analog. Both are using scene based algorithms. Moreover a new method is proposed for simultaneous correction of pixel offsets and sensitivities. In this scope, a new architecture of readout integrated circuit has been implemented; this architecture is developed with 0.18μm CMOS technology. The specification and the application of the ROIC are discussed in details.

  14. Through-silicon-via crosstalk model and optimization design for three-dimensional integrated circuits

    International Nuclear Information System (INIS)

    Through-silicon-via (TSV) to TSV crosstalk noise is one of the key factors affecting the signal integrity of three-dimensional integrated circuits (3D ICs). Based on the frequency dependent equivalent electrical parameters for the TSV channel, an analytical crosstalk noise model is established to capture the TSV induced crosstalk noise. The impact of various design parameters including insulation dielectric, via pitch, via height, silicon conductivity, and terminal impedance on the crosstalk noise is analyzed with the proposed model. Two approaches are proposed to alleviate the TSV noise, namely, driver sizing and via shielding, and the SPICE results show 241 mV and 379 mV reductions in the peak noise voltage, respectively

  15. DrugOn: a fully integrated pharmacophore modeling and structure optimization toolkit

    Directory of Open Access Journals (Sweden)

    Dimitrios Vlachakis

    2015-01-01

    Full Text Available During the past few years, pharmacophore modeling has become one of the key components in computer-aided drug design and in modern drug discovery. DrugOn is a fully interactive pipeline designed to exploit the advantages of modern programming and overcome the command line barrier with two friendly environments for the user (either novice or experienced in the field of Computer Aided Drug Design to perform pharmacophore modeling through an efficient combination of the PharmACOphore, Gromacs, Ligbuilder and PDB2PQR suites. Our platform features a novel workflow that guides the user through each logical step of the iterative 3D structural optimization setup and drug design process. For the pharmacophore modeling we are focusing on either the characteristics of the receptor or the full molecular system, including a set of selected ligands. DrugOn can be freely downloaded from our dedicated server system at www.bioacademy.gr/bioinformatics/drugon/.

  16. Simultaneous detection of lactate and glucose by integrated printed circuit board based array sensing chip

    Energy Technology Data Exchange (ETDEWEB)

    Li, Xuelian [Institute for Clean Energy and Advanced Materials, Southwest University, Chongqing 400715 (China); School of Chemistry and Chemical Engineering, Southwest University, Chongqing 400715 (China); Zang, Jianfeng [Department of Mechanical Engineering and Materials Science, Duke University, Durham, NC 27708 (United States); Liu, Yingshuai; Lu, Zhisong [Institute for Clean Energy and Advanced Materials, Southwest University, Chongqing 400715 (China); Li, Qing, E-mail: Qli@swu.edu.cn [School of Chemistry and Chemical Engineering, Southwest University, Chongqing 400715 (China); Li, Chang Ming, E-mail: ecmli@swu.edu.cn [Institute for Clean Energy and Advanced Materials, Southwest University, Chongqing 400715 (China)

    2013-04-10

    Highlights: ► An integrated printed circuit board (PCB) based array sensing chip was developed. ► Simultaneous detection of lactate and glucose in serum has been demonstrated. ► The array electronic biochip has high signal to noise ratio and high sensitivity. ► Additional electrodes were designed on the chip to correct interferences. -- Abstract: An integrated printed circuit board (PCB) based array sensing chip was developed to simultaneously detect lactate and glucose in mouse serum. The novelty of the chip relies on a concept demonstration of inexpensive high-throughput electronic biochip, a chip design for high signal to noise ratio and high sensitivity by construction of positively charged chitosan/redox polymer Polyvinylimidazole-Os (PVI-Os)/carbon nanotube (CNT) composite sensing platform, in which the positively charged chitosan/PVI-Os is mediator and electrostatically immobilizes the negatively charged enzyme, while CNTs function as an essential cross-linker to network PVI-Os and chitosan due to its negative charged nature. Additional electrodes on the chip with the same sensing layer but without enzymes were prepared to correct the interferences for high specificity. Low detection limits of 0.6 μM and 5 μM were achieved for lactate and glucose, respectively. This work could be extended to inexpensive array sensing chips with high sensitivity, good specificity and high reproducibility for various sensor applications.

  17. Three-dimensional multi-terminal superconductive integrated circuit inductance extraction

    International Nuclear Information System (INIS)

    Accurate inductance calculations are critical for the design of both digital and analogue superconductive integrated circuits, and three-dimensional calculations are gaining importance with the advent of inductive biasing, inductive coupling and sky plane shielding for RSFQ cells. InductEx, an extraction programme based on the three-dimensional calculation software FastHenry, was proposed earlier. InductEx uses segmentation techniques designed to accurately model the geometries of superconductive integrated circuit structures. Inductance extraction for complex multi-terminal three-dimensional structures from current distributions calculated by FastHenry is discussed. Results for both a reflection plane modelling an infinite ground plane and a finite segmented ground plane that allows inductive elements to extend over holes in the ground plane are shown. Several SQUIDs were designed for and fabricated with IPHT's 1 kA cm−2 RSFQ1D niobium process. These SQUIDs implement a number of loop structures that span different layers, include vias, inductively coupled control lines and ground plane holes. We measured the loop inductance of these SQUIDs and show how the results are used to calibrate the layer parameters in InductEx and verify the extraction accuracy. We also show that, with proper modelling, FastHenry can be fast enough to be used for the extraction of typical RSFQ cell inductances.

  18. Design and technological peculiarities of making vacuum integrated circuit of a thermocathode-based AC amplifier

    Science.gov (United States)

    Grigorishin, I. L.; Kotova, I. F.; Mukhurov, N. I.

    1997-02-01

    Despite promising prospects and comprehensive nature of contemporary studies aimed at developing autoemission cathodes, only thermoemitter-based vacuum integrated circuits (VIC) have been realized by now. Here, the results are presented of building and testing, in extreme environment, thermoemission VICs of a RF active oscillator and multivibrator. The microcircuits made have limited functional capabilities. To expand their capabilities the VIC of an AC amplifier was developed. This paper deals with circuit design aspects of making the AC amplifier based on the potentialities and specific features of the process of anodic oxidation of aluminium to form dielectric substrates of cathode-heating assemblies (CHA) and anode-grid assemblies (AGA). Design and technological methods are described that are used to make active (five vacuum microtriodes) and passive (resistors, capacitors, commutation) film elements. As compared to earlier devices, the AC amplifier VIC is more economical and has better characteristics in terms of miniaturization and integration. Its fundamental peculiarities are two-sided obtained through anodizing to form dielectric substrates with microrelief and superfine-structure grids of microtriodes. Some characteristics of the AC amplifier VIC are given and ways of improving them are discussed.

  19. Simultaneous detection of lactate and glucose by integrated printed circuit board based array sensing chip

    International Nuclear Information System (INIS)

    Highlights: ► An integrated printed circuit board (PCB) based array sensing chip was developed. ► Simultaneous detection of lactate and glucose in serum has been demonstrated. ► The array electronic biochip has high signal to noise ratio and high sensitivity. ► Additional electrodes were designed on the chip to correct interferences. -- Abstract: An integrated printed circuit board (PCB) based array sensing chip was developed to simultaneously detect lactate and glucose in mouse serum. The novelty of the chip relies on a concept demonstration of inexpensive high-throughput electronic biochip, a chip design for high signal to noise ratio and high sensitivity by construction of positively charged chitosan/redox polymer Polyvinylimidazole-Os (PVI-Os)/carbon nanotube (CNT) composite sensing platform, in which the positively charged chitosan/PVI-Os is mediator and electrostatically immobilizes the negatively charged enzyme, while CNTs function as an essential cross-linker to network PVI-Os and chitosan due to its negative charged nature. Additional electrodes on the chip with the same sensing layer but without enzymes were prepared to correct the interferences for high specificity. Low detection limits of 0.6 μM and 5 μM were achieved for lactate and glucose, respectively. This work could be extended to inexpensive array sensing chips with high sensitivity, good specificity and high reproducibility for various sensor applications

  20. Micro/nano-scale fabrication of integrated polymer optical wire circuit arrays for optical printed circuit board (O-PCB) application

    Science.gov (United States)

    Lee, El-Hang; Lee, Seung G.; Park, Se G.; Kim, Kyong H.; Kang, Jin K.; Chin, In J.; Kwon, Y. K.; Choi, Young W.

    2005-02-01

    We report on the results of our study on the micro/nano-scale design, fabrication and integration of waveguide arrays for optical printed circuit boards (O-PCBs) and VLSI micro/nano-photonic applications. The O-PCBs are designed to perform the functions of transporting, switching, routing and distributing optical signals on flat modular boards or substrates. We have assembled O-PCBs using optical waveguide arrays and circuits made of polymer materials and have examined information handling performances. We also designed power beam splitters and waveguide filters, using nano-scale photonic band-gap crystals, for VLSI photonic integration application. We discuss potential applications of polymer optical waveguide devices and arrays for O-PCB and VLSI micro/nano-photonics for computers, telecommunications, and transportation systems.

  1. On the Basis of Synaptic Integration Constancy during Growth of a Neuronal Circuit.

    Science.gov (United States)

    De-La-Rosa Tovar, Adriana; Mishra, Prashant K; De-Miguel, Francisco F

    2016-01-01

    We studied how a neuronal circuit composed of two neuron types connected by chemical and electrical synapses maintains constant its integrative capacities as neurons grow. For this we combined electrophysiological experiments with mathematical modeling in pairs of electrically-coupled Retzius neurons from postnatal to adult leeches. The electrically-coupled dendrites of both Retzius neurons receive a common chemical input, which produces excitatory postsynaptic potentials (EPSPs) with varying amplitudes. Each EPSP spreads to the soma, but also crosses the electrical synapse to arrive at the soma of the coupled neuron. The leak of synaptic current across the electrical synapse reduces the amplitude of the EPSPs in proportion to the coupling ratio. In addition, summation of EPSPs generated in both neurons generates the baseline action potentials of these serotonergic neurons. To study how integration is adjusted as neurons grow, we first studied the characteristics of the chemical and electrical connections onto the coupled dendrites of neuron pairs with soma diameters ranging from 21 to 75 μm. Then by feeding a mathematical model with the neuronal voltage responses to pseudorandom noise currents we obtained the values of the coupling ratio, the membrane resistance of the soma (rm ) and dendrites (r dend), the space constant (λ) and the characteristic dendritic length (L = l/λ). We found that the EPSPs recorded from the somata were similar regardless on the neuron size. However, the amplitude of the EPSPs and the firing frequency of the neurons were inversely proportional to the coupling ratio of the neuron pair, which also was independent from the neuronal size. This data indicated that the integrative constancy relied on the passive membrane properties. We show that the growth of Retzius neurons was compensated by increasing the membrane resistance of the dendrites and therefore the λ value. By solely increasing the dendrite resistance this circuit maintains

  2. Cooley building opens in Houston. Demonstrates value of fully integrated marketing communications.

    Science.gov (United States)

    Rees, Tom

    2002-01-01

    The Texas Heart Institute at St. Luke's Episcopal HospiTal in Houston dedicated its new 10-story Denton A. Cooley Building in January. The structure opened with a fanfare, thanks to a well-integrated marketing communications program. PMID:11915203

  3. Toward a fully integrated wireless wearable EEG-NIRS bimodal acquisition system

    Science.gov (United States)

    Safaie, J.; Grebe, R.; Abrishami Moghaddam, H.; Wallois, F.

    2013-10-01

    Objective. Interactions between neuronal electrical activity and regional changes in microcirculation are assumed to play a major role in physiological brain activity and the development of pathological disorders, but have been poorly elucidated to date. There is a need for advanced diagnostic tools to investigate the relationships between these two physiological processes.Approach. To meet these needs, a wireless wearable system has been developed, which combines a near infrared spectroscopy (NIRS) system using light emitting diodes (LEDs) as a light source and silicon photodiodes as a detector with an integrated electroencephalography (EEG) system. Main results. The main advantages over currently available devices are miniaturization and integration of a real-time electrical and hemodynamic activity monitor into one wearable device. For patient distributed monitoring and creating a body-area network, up to seven same devices can be connected to a single base station (PC) synchronously. Each node presents enhanced portability due to the wireless communication and highly integrated components resulting in a small, lightweight signal acquisition device. Further progress includes the individual control of LEDs output to automatically or interactively adjust emitted light to the actual local situation online, the use of silicon photodiodes with a safe low-voltage power supply, and an integrated three dimensional accelerometer for movement detection for the identification of motion artifacts. Significance. The device was tested and validated using our enhanced EEG-NIRS tissue mimicking fluid phantom for sensitivity mapping. Typical somatotopic electrical evoked potential experiments were performed to verify clinical applicability.

  4. Ultrasensitive mass sensor fully integrated with complementary metal-oxide-semiconductor circuitry

    DEFF Research Database (Denmark)

    Forsén, Esko Sebastian; Abadal, G.; Ghatnekar-Nilsson, S.;

    2005-01-01

    Nanomechanical resonators have been monolithically integrated on preprocessed complementary metal-oxide-semiconductor (CMOS) chips. Fabricated resonator systems have been designed to have resonance frequencies up to 1.5 MHz. The systems have been characterized in ambient air and vacuum conditions...... excitation, capacitive detection, and amplification of the resonance signal directly on the chip. (c) 2005 American Institute of Physics....

  5. Falcon Gold - High Altitude Balloon Flight Test of a Fully Integrated Spacecraft

    OpenAIRE

    O'Brien, Catherine; Smith, James; Eisenreich, Jason; Humble, Ronald; Parker, Dewey

    1997-01-01

    Students at the University of Colorado Springs (UCCS) and the United States Air Force Academy are designing, building and testing a spacecraft scheduled to fly on a Lockheed Martin Atlas/Centaur in October, 1997. The mission objective is to characterize the Global Positioning system (GPS) signal for use in orbit determination above the GPS constellation. An important step in this program is validating the design and functionality of the integrated spacecraft to reduce risk and ensure mission ...

  6. Fully Integrated Applications of Thin Films on Low Temperature Cofired Ceramic (LTCC)

    Energy Technology Data Exchange (ETDEWEB)

    Ambrose Wolf; Ken Peterson; Matt O' Keefe; Wayne Huebner; Bill Kuhn

    2012-04-19

    Thin film multilayers have previously been introduced on multilayer low temperature cofired ceramic (LTCC), as well as initial thin film capacitors on LTCC. The ruggedness of a multipurpose Ti-Cu-Pt-Au stack for connectivity and RF conductivity has continued to benefit fabrication and reliability in state of-the-art modules, while the capacitors have followed the traditional Metal-Insulator-Metal (MIM) style. The full integration of thin film passives with thin film connectivity traces is presented. Certain passives, such as capacitors, require specifically tailored and separately patterned thin film (multi-)layers, including a dielectric. Different capacitance values are achieved by variation of both the insulator layer thickness and the active area of the capacitor. Other passives, such as filters, require only the conductor - a single thin film multilayer. This can be patterned from the same connectivity thin film material (Ti-Cu-Pt-Au), or a specially tailored thin film material (e.g. Ti-Cu-Au) can be deposited. Both versions are described, including process and integration details. Examples are discussed, ranging from patterning for maximum tolerances, to space and performance-optimized designs. Cross-sectional issues associated with integration are also highlighted in the discussion.

  7. Lock-in range of PLL-based circuits with proportionally-integrating filter and sinusoidal phase detector characteristic

    OpenAIRE

    Aleksandrov, K. D.; Kuznetsov, N. V.; Leonov, G. A.; Yuldashev, M. V.; Yuldashev, R. V.

    2016-01-01

    In the present work PLL-based circuits with sinusoidal phase detector characteristic and active proportionally-integrating (PI) filter are considered. The notion of lock-in range -- an important characteristic of PLL-based circuits, which corresponds to the synchronization without cycle slipping, is studied. For the lock-in range a rigorous mathematical definition is discussed. Numerical and analytical estimates for the lock-in range are obtained.

  8. Test and diagnosis of analogue, mixed-signal and RF integrated circuits the system on chip approach

    CERN Document Server

    Sun, Yichuang

    2008-01-01

    This book provides a comprehensive discussion of automatic testing, diagnosis and tuning of analogue, mixed-signal and RF integrated circuits, and systems in a single source. The book contains eleven chapters written by leading researchers worldwide. As well as fundamental concepts and techniques, the book reports systematically the state of the arts and future research directions of these areas. A complete range of circuit components are covered and test issues are also addressed from the SoC perspective.

  9. Fully Integrated, Miniature, High-Frequency Flow Probe Utilizing MEMS Leadless SOI Technology

    Science.gov (United States)

    Ned, Alex; Kurtz, Anthony; Shang, Tonghuo; Goodman, Scott; Giemette. Gera (d)

    2013-01-01

    This work focused on developing, fabricating, and fully calibrating a flowangle probe for aeronautics research by utilizing the latest microelectromechanical systems (MEMS), leadless silicon on insulator (SOI) sensor technology. While the concept of angle probes is not new, traditional devices had been relatively large due to fabrication constraints; often too large to resolve flow structures necessary for modern aeropropulsion measurements such as inlet flow distortions and vortices, secondary flows, etc. Mea surements of this kind demanded a new approach to probe design to achieve sizes on the order of 0.1 in. (.3 mm) diameter or smaller, and capable of meeting demanding requirements for accuracy and ruggedness. This approach invoked the use of stateof- the-art processing techniques to install SOI sensor chips directly onto the probe body, thus eliminating redundancy in sensor packaging and probe installation that have historically forced larger probe size. This also facilitated a better thermal match between the chip and its mount, improving stability and accuracy. Further, the leadless sensor technology with which the SOI sensing element is fabricated allows direct mounting and electrical interconnecting of the sensor to the probe body. This leadless technology allowed a rugged wire-out approach that is performed at the sensor length scale, thus achieving substantial sensor size reductions. The technology is inherently capable of high-frequency and high-accuracy performance in high temperatures and harsh environments.

  10. Modeling, Simulation, and Fabrication of a Fully Integrated, Acid-stable, Scalable Solar-Driven Water-Splitting System

    OpenAIRE

    Walczak, Karl; Chen, Yikai; Karp, Christoph; Beeman, Jeffrey W.; Shaner, Matthew; Spurgeon, Joshua; Sharp, Ian D.; Amashukeli, Xenia; West, William; Jin, Jian; Lewis, Nathan S.; Xiang, Chengxiang

    2015-01-01

    A fully integrated solar-driven water-splitting system comprised of WO3/FTO/p^(+)n Si as the photoanode, Pt/TiO_2/Ti/n^(+)p Si as the photocathode, and Nafion as the membrane separator, was simulated, assembled, operated in 1.0 M HClO_4, and evaluated for performance and safety characteristics under dual side illumination. A multi-physics model that accounted for the performance of the photoabsorbers and electrocatalysts, ion transport in the solution electrolyte, and gaseous product crossove...

  11. Fully integrated InGaAs/InP single-photon detector module with gigahertz sine wave gating

    OpenAIRE

    Liang, Xiao-Lei; Liu, Jian-Hong; Wang, Quan; Du, De-Bing; Ma, Jian; Jin, Ge; Chen, Zeng-Bing; Zhang, Jun; Pan, Jian-Wei

    2012-01-01

    InGaAs/InP single-photon avalanche diodes (SPADs) working in the regime of GHz clock rates are crucial components for the high-speed quantum key distribution (QKD). We have developed for the first time a compact, stable and user-friendly tabletop InGaAs/InP single-photon detector system operating at a 1.25 GHz gate rate that fully integrates functions for controlling and optimizing SPAD performance. We characterize the key parameters of the detector system and test the long-term stability of ...

  12. Fully Integrated On-Chip Coil in 0.13 μm CMOS for Wireless Power Transfer Through Biological Media.

    Science.gov (United States)

    Zargham, Meysam; Gulak, P Glenn

    2015-04-01

    Delivering milliwatts of wireless power at centimeter distances is advantageous to many existing and emerging biomedical applications. It is highly desirable to fully integrate the receiver on a single chip in standard CMOS with no additional post-processing steps or external components. This paper presents a 2 × 2.18 mm(2) on-chip wireless power transfer (WPT) receiver (Rx) coil fabricated in 0.13 μm CMOS. The WPT system utilizes a 14.5 × 14.5 mm(2) transmitter (Tx) coil that is fabricated on a standard FR4 substrate. The on-chip power harvester demonstrates a peak WPT efficiency of -18.47 dB , -20.96 dB and -20.15 dB at 10 mm of separation through air, bovine muscle and 0.2 molar NaCl, respectively. The achieved efficiency enables the delivery of milliwatts of power to application circuits while staying below safe power density and electromagnetic (EM) exposure limits. PMID:25099630

  13. Fully integrated optical system for lab-on-a-chip applications

    DEFF Research Database (Denmark)

    Balslev, Søren; Olsen, Brian Bilenberg; Geschke, Oliver; Jørgensen, Anders Michael; Kristensen, Anders; Kutter, Jörg Peter; Mogensen, Klaus Bo; Snakenborg, Detlef

    We present a lab-on-a-chip device featuring a microfluidic dye laser, wave-guides, microfluidic components and photo-detectors integrated on the chip. The microsystem is designed for wavelength selective absorption measurements in the visible range on a fluidic sample, which can be prepared....../mixed on-chip. The laser structures, wave-guides and micro-fluidic handling system are defined in a single UV-lithography step on a 10 μm thick SU-8 layer on top of the substrate. The SU-8 structures are sealed by a Borofloat glass lid, using polymethylmethacrylate (PMMA) adhesive bonding....

  14. SmartStep: A Fully Integrated, Low-Power Insole Monitor

    Directory of Open Access Journals (Sweden)

    Nagaraj Hegde

    2014-06-01

    Full Text Available Shoe-mounted wearable sensors can be used in applications, such as activity monitoring, gait analysis, post-stroke rehabilitation, body weight measurements and energy expenditure studies. Such wearable sensors typically require the modification or alteration of the shoe, which is not typically feasible for large populations without the direct involvement of shoe manufacturers. This article presents an insole-based wearable sensor (SmartStep that has its electronics fully embedded into a generic insole, which is usable with a large variety of shoes and, thus, resolves the need for shoe modification. The SmartStep is an always-on electronic device that comprises a 3D accelerometer, a 3D gyroscope and resistive pressure sensors implemented around a CC2540 system-on-chip with an 8051 processor core, Bluetooth low energy (BLE connectivity and flash memory buffer. The SmartStep is wirelessly interfaced to an Android smart phone application with data logging and visualization capabilities. This article focuses on low-power implementation methods and on the method developed for reliable data buffering, alleviating intermittent connectivity resulting from the user leaving the vicinity of the smart phone. The conducted tests illustrate the power consumption for several possible usage scenarios and the reliability of the data retention method. The trade-off between the power consumption and supported functionality is discussed, demonstrating that SmartStep can be worn for more than two days between battery recharges. The results of the mechanical reliability test on the SmartStep indicate that the pressure sensors in the SmartStep tolerated prolonged human wear. The SmartStep system collected more than 98.5% of the sensor data, in real usage scenarios, having intermittent connectivity with the smart phone.

  15. Flexible low-voltage organic integrated circuits with megahertz switching frequencies (Presentation Recording)

    Science.gov (United States)

    Zschieschang, Ute; Takimiya, Kazuo; Zaki, Tarek; Letzkus, Florian; Richter, Harald; Burghartz, Joachim N.; Klauk, Hagen

    2015-09-01

    A process for the fabrication of integrated circuits based on bottom-gate, top-contact organic thin-film transistors (TFTs) with channel lengths as short as 1 µm on flexible plastic substrates has been developed. In this process, all TFT layers (gate electrodes, organic semiconductors, source/drain contacts) are patterned with the help of high-resolution silicon stencil masks, thus eliminating the need for subtractive patterning and avoiding the exposure of the organic semiconductors to potentially harmful organic solvents or resists. The TFTs employ a low-temperature-processed gate dielectric that is sufficiently thin to allow the TFTs and circuits to operate with voltages of about 3 V. Using the vacuum-deposited small-molecule organic semiconductor 2,9-didecyl-dinaphtho[2,3-b:2',3'-f]thieno[3,2-b]thiophene (C10 DNTT), TFTs with an effective field-effect mobility of 1.2 cm2/Vs, an on/off current ratio of 107, a width-normalized transconductance of 1.2 S/m (with a standard deviation of 6%), and a signal propagation delay (measured in 11-stage ring oscillators) of 420 nsec per stage at a supply voltage of 3 V have been obtained. To our knowledge, this is the first time that megahertz operation has been achieved in flexible organic transistors at supply voltages of less than 10 V. In addition to flexible ring oscillators, we have also demonstrated a 6-bit digital-to-analog converter (DAC) in a binary-weighted current-steering architecture, based on TFTs with a channel length of 4 µm and fabricated on a glass substrate. This DAC has a supply voltage of 3.3 V, a circuit area of 2.6 × 4.6 mm2, and a maximum sampling rate of 100 kS/s.

  16. Application of lock-in thermography for failure analysis in integrated circuits using quantitative phase shift analysis

    International Nuclear Information System (INIS)

    Lock-in thermography (LIT), which is a well established technique for non-destructive evaluation, can also be used to identify and locate thermal active electrically defects like shorts and resistive opens in microelectronic devices. Defect localization on the level of the integrated circuits (IC) requires a μm resolution. But LIT can also be applied to locate buried thermal active defects within fully packaged microelectronic devices by analysing the thermal signal detected at the surface of the device. In addition to the lateral localization of the hot spot, its depth can also be determined by analysing the phase shift of the thermal signal. This is especially valued for non destructive defect localization in complex 3D integrated system in package devices (3D SiP). In comparison to competitive thermal imaging techniques, like liquid crystal imaging or fluorescent micro thermal imaging, LIT is easier to apply since it does not need any foreign thermal sensitive layer at the surface of the device. Also, the sensitivity limit of this technique within μK range is significantly better. In addition the dynamic character of LIT reduces thermal blurring, and the problem of inhomogeneous IR emissivity can be overcome by using the phase image or the 0°/−90° image. The spatial resolution limit of the used microscopic thermal imaging setup performed in the mid-wavelength range is about 5 μm, but can be improved to 1.5 μm by applying solid immersion lenses. Within the paper, the principle theory of LIT and the practical use for both, single and multiple IC devices is presented.

  17. Ultra-Low Loss Waveguides with Application to Photonic Integrated Circuits

    Science.gov (United States)

    Bauters, Jared F.

    The integration of photonic components using a planar platform promises advantages in cost, size, weight, and power consumption for optoelectronic systems. Yet, the typical propagation loss of 5-10 dB/m in a planar silica waveguide is nearly five orders-of-magnitude larger than that in low loss optical fibers. For some applications, the miniaturization of the photonic system and resulting smaller propagation lengths from integration are enough to overcome the increase in propagation loss. For other more demanding systems or applications, such as those requiring long optical time delays or high-quality-factor (Q factor) resonators, the high propagation loss can degrade system performance to a degree that trumps the potential advantages offered by integration. Thus, the reduction of planar waveguide propagation loss in a Si3-N4 based waveguide platform is a primary focus of this dissertation. The ultra-low loss stoichiometric Si3-N4 waveguide platform offers the additional advantages of fabrication process stability and repeatability. Yet, active devices such as lasers, amplifiers, and photodetectors have not been monolithically integrated with ultra-low loss waveguides due to the incompatibility of the active and ultra-low loss processing thermal budgets (ultra-low loss waveguides are annealed at temperatures exceeding 1000 °C in order to drive out impurities). So a platform that enables the integration of active devices with the ultra-low losses of the Si3- N4 waveguide platform is this dissertation's second focus. The work enables the future fabrication of sensor, gyroscope, true time delay, and low phase noise oscillator photonic integrated circuits.

  18. Carbon Nanotube Self-Gating Diode and Application in Integrated Circuits.

    Science.gov (United States)

    Si, Jia; Liu, Lijun; Wang, Fanglin; Zhang, Zhiyong; Peng, Lian-Mao

    2016-07-26

    A nano self-gating diode (SGD) based on nanoscale semiconducting material is proposed, simulated, and realized on semiconducting carbon nanotubes (CNTs) through a doping-free fabrication process. The relationships between the performance and material/structural parameters of the SGD are explored through numerical simulation and verified by experiment results. Based on these results, performance optimization strategy is outlined, and high performance CNT SGDs are fabricated and demonstrated to surpass other published CNT diodes. In particular the CNT SGD exhibits high rectifier factor of up to 1.4 × 10(6) while retains large on-state current. Benefiting from high yield and stability, CNT SGDs are used for constructing logic and analog integrated circuits. Two kinds of basic digital gates (AND and OR) have been realized on chip through using CNT SGDs and on-chip Ti wire resistances, and a full wave rectifier circuit has been demonstrated through using two CNT SGDs. Although demonstrated here using CNT SGDs, this device structure may in principle be implemented using other semiconducting nanomaterials, to provide ideas and building blocks for electronic applications based on nanoscale materials. PMID:27322134

  19. Polypyrrole Porous Micro Humidity Sensor Integrated with a Ring Oscillator Circuit on Chip

    Directory of Open Access Journals (Sweden)

    De-Hao Lu

    2010-11-01

    Full Text Available This study presents the design and fabrication of a capacitive micro humidity sensor integrated with a five-stage ring oscillator circuit on chip using the complimentary metal oxide semiconductor (CMOS process. The area of the humidity sensor chip is about 1 mm2. The humidity sensor consists of a sensing capacitor and a sensing film. The sensing capacitor is constructed from spiral interdigital electrodes that can enhance the sensitivity of the sensor. The sensing film of the sensor is polypyrrole, which is prepared by the chemical polymerization method, and the film has a porous structure. The sensor needs a post-CMOS process to coat the sensing film. The post-CMOS process uses a wet etching to etch the sacrificial layers, and then the polypyrrole is coated on the sensing capacitor. The sensor generates a change in capacitance when the sensing film absorbs or desorbs vapor. The ring oscillator circuit converts the capacitance variation of the sensor into the oscillation frequency output. Experimental results show that the sensitivity of the humidity sensor is about 99 kHz/%RH at 25 °C.

  20. Gallium arsenide digital integrated circuits for controlling SLAC CW-RF systems

    International Nuclear Information System (INIS)

    In order to fill the PEP and SPEAR storage rings with beams from the SLC linac and damping rings, precise control of the linac subharmonic buncher and the damping ring RF is required. Recently several companies have developed resettable GaAs master/slave D-type flip-flops which are capable of operating at frequencies of 3 GHz and higher. Using these digital devices as frequency dividers, one can phase shift the SLAC CW-RF systems to optimize the timing for filling the storage rings. We have evaluated the performance of integrated circuits from two vendors for our particular application. Using microstrip circuit techniques, we have built and operated in the accelerator several chassis to synchronize a reset signal from the storage rings to the SLAC 2.856 GHz RF and to phase shift divide-by-four and divide-by-sixteen frequency dividers to the nearest 350 psec bucket required for filling. 4 refs., 4 figs., 2 tabs