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Sample records for circuits fully integrated

  1. Fully integrated current-mode CMOS gated baseline restorer circuits

    International Nuclear Information System (INIS)

    Design and performance results for three different fully-integrated gated baseline restorer (BLR) circuits used in a new PET current-mode front-end CMOS ASIC are presented. The BLR for each of the three gated integrator channels is a differential current-in to single ended current-out circuit with a correction bandwidth of 100 kHz set by a 40 pF on-chip capacitor using pole splitting techniques. The BLRs for the constant fraction discriminator (CFD) constant fraction and arming comparators are differential current-in to voltage-out circuits with correction bandwidths of 5 MHz and 1 MHz set by on-chip capacitors of 10 pF and 2.5 pF respectively. The BLR circuits are capable of correcting differential input current offsets of ±40 microA for the gated integrator circuits, ±100 microA for the CFD constant fraction comparator circuit, and ± 160 microA for the CFD arming comparator circuit. Use of the BLR circuits allows photomultiplier tube (PMT) detector inputs to be ac coupled and all slow (gated integrator) and fast (CFD timing) signal processing channels to be dc coupled. The BLR circuits correct for count-rate dependent baseline shifts due to detector ac coupling and correct for accumulated CMOS dc offsets in the signal processing channels. Gated integrator input offset currents are maintained below 50 nA, keeping the gated integrator output error below 10 mV for an 850 ns integration period. CFD constant fraction comparator input offset is maintained at sub millivolt levels, and arming comparator threshold is maintained at a 0--0.48 V level under on-board DAC control

  2. Fully integrated circuit chip of microelectronic neural bridge

    International Nuclear Information System (INIS)

    Nerve tracts interruption is one of the major reasons for dysfunction after spiral cord injury. The microelectronic neural bridge is a method to restore function of interrupted neural pathways, by making use of microelectronic chips to bypass the injured nerve tracts. A low-power fully integrated microelectronic neural bridge chip is designed, using CSMC 0.5-μm CMOS technology. The structure and the key points in the circuit design will be introduced in detail. In order to meet the requirement for implantation, the circuit was modified to avoid the use of off-chip components, and fully monolithic integration is achieved. The operating voltage of the circuit is ±2.5 V, and the chip area is 1.21 × 1.18 mm2. According to the characteristic of neural signal, the time-domain method is used in testing. The pass bandwidth of the microelectronic neural bridge system covers the whole frequency range of the neural signal, power consumption is 4.33 mW, and the gain is adjustable. The design goals are achieved. (semiconductor integrated circuits)

  3. A compact picosecond pulsed laser source using a fully integrated CMOS driver circuit

    Science.gov (United States)

    He, Yuting; Li, Yuhua; Yadid-Pecht, Orly

    2016-03-01

    Picosecond pulsed laser source have applications in areas such as optical communications, biomedical imaging and supercontinuum generation. Direct modulation of a laser diode with ultrashort current pulses offers a compact and efficient approach to generate picosecond laser pulses. A fully integrated complementary metaloxide- semiconductor (CMOS) driver circuit is designed and applied to operate a 4 GHz distributed feedback laser (DFB). The CMOS driver circuit combines sub-circuits including a voltage-controlled ring oscillator, a voltagecontrolled delay line, an exclusive-or (XOR) circuit and a current source circuit. Ultrashort current pulses are generated by the XOR circuit when the delayed square wave is XOR'ed with the original square wave from the on-chip oscillator. Circuit post-layout simulation shows that output current pulses injected into an equivalent circuit load of the laser have a pulse full width at half maximum (FWHM) of 200 ps, a peak current of 80 mA and a repetition rate of 5.8 MHz. This driver circuit is designed in a 0.13 μm CMOS process and taped out on a 0.3 mm2 chip area. This CMOS chip is packaged and interconnected with the laser diode on a printed circuit board (PCB). The optical output waveform from the laser source is captured by a 5 GHz bandwidth photodiode and an 8 GHz bandwidth oscilloscope. Measured results show that the proposed laser source can output light pulses with a pulse FWHM of 151 ps, a peak power of 6.4 mW (55 mA laser peak forward current) and a repetition rate of 5.3 MHz.

  4. PCSIM: A Parallel Simulation Environment for Neural Circuits Fully Integrated with Python

    OpenAIRE

    Pecevski, Dejan; Natschläger, Thomas; Schuch, Klaus

    2009-01-01

    The Parallel Circuit SIMulator (PCSIM) is a software package for simulation of neural circuits. It is primarily designed for distributed simulation of large scale networks of spiking point neurons. Although its computational core is written in C++, PCSIM's primary interface is implemented in the Python programming language, which is a powerful programming environment and allows the user to easily integrate the neural circuit simulator with data analysis and visualization tools to manage the f...

  5. PCSIM: a parallel simulation environment for neural circuits fully integrated with Python

    OpenAIRE

    Dejan Pecevski; Thomas Natschläger; Klaus Schuch

    2009-01-01

    The Parallel Circuit SIMulator (PCSIM) is a software package for simulation of neural circuits. It is primarily designed for distributed simulation of large scale networks of spiking point neurons. Although its computational core is written in C++, PCSIM's primary interface is implemented in the Python programming language, which is a powerful programming environment and allows the user to easily integrate the neural circuit simulator with data analysis and visualization tools to manage...

  6. Fully integrated low-noise readout circuit with automatic offset cancellation loop for capacitive microsensors.

    Science.gov (United States)

    Song, Haryong; Park, Yunjong; Kim, Hyungseup; Cho, Dong-Il Dan; Ko, Hyoungho

    2015-10-14

    Capacitive sensing schemes are widely used for various microsensors; however, such microsensors suffer from severe parasitic capacitance problems. This paper presents a fully integrated low-noise readout circuit with automatic offset cancellation loop (AOCL) for capacitive microsensors. The output offsets of the capacitive sensing chain due to the parasitic capacitances and process variations are automatically removed using AOCL. The AOCL generates electrically equivalent offset capacitance and enables charge-domain fine calibration using a 10-bit R-2R digital-to-analog converter, charge-transfer switches, and a charge-storing capacitor. The AOCL cancels the unwanted offset by binary-search algorithm based on 10-bit successive approximation register (SAR) logic. The chip is implemented using 0.18 μm complementary metal-oxide-semiconductor (CMOS) process with an active area of 1.76 mm². The power consumption is 220 μW with 3.3 V supply. The input parasitic capacitances within the range of -250 fF to 250 fF can be cancelled out automatically, and the required calibration time is lower than 10 ms.

  7. Fully Integrated Low-Noise Readout Circuit with Automatic Offset Cancellation Loop for Capacitive Microsensors

    Directory of Open Access Journals (Sweden)

    Haryong Song

    2015-10-01

    Full Text Available Capacitive sensing schemes are widely used for various microsensors; however, such microsensors suffer from severe parasitic capacitance problems. This paper presents a fully integrated low-noise readout circuit with automatic offset cancellation loop (AOCL for capacitive microsensors. The output offsets of the capacitive sensing chain due to the parasitic capacitances and process variations are automatically removed using AOCL. The AOCL generates electrically equivalent offset capacitance and enables charge-domain fine calibration using a 10-bit R-2R digital-to-analog converter, charge-transfer switches, and a charge-storing capacitor. The AOCL cancels the unwanted offset by binary-search algorithm based on 10-bit successive approximation register (SAR logic. The chip is implemented using 0.18 μm complementary metal-oxide-semiconductor (CMOS process with an active area of 1.76 mm2. The power consumption is 220 μW with 3.3 V supply. The input parasitic capacitances within the range of −250 fF to 250 fF can be cancelled out automatically, and the required calibration time is lower than 10 ms.

  8. PCSIM: a parallel simulation environment for neural circuits fully integrated with Python

    Directory of Open Access Journals (Sweden)

    Dejan Pecevski

    2009-05-01

    Full Text Available The Parallel Circuit SIMulator (PCSIM is a software package for simulation of neural circuits. It is primarily designed for distributed simulation of large scale networks of spiking point neurons. Although its computational core is written in C++, PCSIM's primary interface is implemented in the Python programming language, which is a powerful programming environment and allows the user to easily integrate the neural circuit simulator with data analysis and visualization tools to manage the full neural modeling life cycle. The main focus of this paper is to describe PCSIM's full integration into Python and the benefits thereof. In particular we will investigate how the automatically generated bidirectional interface and PCSIM's object-oriented modular framework enable the user to adopt a hybrid modeling approach: using and extending PCSIM's functionality either employing pure Python or C++ and thus combining the advantages of both worlds. Furthermore, we describe several supplementary PCSIM packages written in pure Python and tailored towards setting up and analyzing neural simulations.

  9. Fully CMOS Memristor Based Chaotic Circuit

    OpenAIRE

    Yener, S. C.; H. H. Kuntman

    2014-01-01

    This paper demonstrates the design of a fully CMOS chaotic circuit consisting of only DDCC based memristor and inductance simulator. Our design is composed of these active blocks using CMOS 0.18 µm process technology with symmetric ±1.25 V supply voltages. A new single DDCC+ based topology is used as the inductance simulator. Simulation results verify that the design proposed satisfies both memristor properties and the chaotic behavior of the circuit. Simulations performed illustrate the succ...

  10. Fully CMOS Memristor Based Chaotic Circuit

    Directory of Open Access Journals (Sweden)

    S. C. Yener

    2014-12-01

    Full Text Available This paper demonstrates the design of a fully CMOS chaotic circuit consisting of only DDCC based memristor and inductance simulator. Our design is composed of these active blocks using CMOS 0.18 µm process technology with symmetric ±1.25 V supply voltages. A new single DDCC+ based topology is used as the inductance simulator. Simulation results verify that the design proposed satisfies both memristor properties and the chaotic behavior of the circuit. Simulations performed illustrate the success of the proposed design for the realization of CMOS based chaotic applications.

  11. MOS integrated circuit design

    CERN Document Server

    Wolfendale, E

    2013-01-01

    MOS Integral Circuit Design aims to help in the design of integrated circuits, especially large-scale ones, using MOS Technology through teaching of techniques, practical applications, and examples. The book covers topics such as design equation and process parameters; MOS static and dynamic circuits; logic design techniques, system partitioning, and layout techniques. Also featured are computer aids such as logic simulation and mask layout, as well as examples on simple MOS design. The text is recommended for electrical engineers who would like to know how to use MOS for integral circuit desi

  12. Development for Germanium Blocked Impurity Band Far-Infrared Image Sensors with Fully-Depleted Silicon-On-Insulator CMOS Readout Integrated Circuit

    Science.gov (United States)

    Wada, T.; Arai, Y.; Baba, S.; Hanaoka, M.; Hattori, Y.; Ikeda, H.; Kaneda, H.; Kochi, C.; Miyachi, A.; Nagase, K.; Nakaya, H.; Ohno, M.; Oyabu, S.; Suzuki, T.; Ukai, S.; Watanabe, K.; Yamamoto, K.

    2016-07-01

    We are developing far-infrared (FIR) imaging sensors for low-background and high-sensitivity applications such as infrared astronomy. Previous FIR monolithic imaging sensors, such as an extrinsic germanium photo-conductor (Ge PC) with a PMOS readout integrated circuit (ROIC) hybridized by indium pixel-to-pixel interconnection, had three difficulties: (1) short cut-off wavelength (120 \\upmu m), (2) large power consumption (10 \\upmu W/pixel), and (3) large mismatch in thermal expansion between the Ge PC and the Si ROIC. In order to overcome these difficulties, we developed (1) a blocked impurity band detector fabricated by a surface- activated bond technology, whose cut-off wavelength is longer than 160 \\upmu m, (2) a fully-depleted silicon-on-insulator CMOS ROIC which works below 4 K with 1 \\upmu W/pixel operating power, and (3) a new concept, Si-supported Ge detector, which shows tolerance to thermal cycling down to 3 K. With these new techniques, we are now developing a 32 × 32 FIR imaging sensor.

  13. Monolithic microwave integrated circuits

    Science.gov (United States)

    Pucel, R. A.

    Monolithic microwave integrated circuits (MMICs), a new microwave technology which is expected to exert a profound influence on microwave circuit designs for future military systems as well as for the commercial and consumer markets, is discussed. The book contains an historical discussion followed by a comprehensive review presenting the current status in the field. The general topics of the volume are: design considerations, materials and processing considerations, monolithic circuit applications, and CAD, measurement, and packaging techniques. All phases of MMIC technology are covered, from design to testing.

  14. Photonic Integrated Circuits

    Science.gov (United States)

    Merritt, Scott; Krainak, Michael

    2016-01-01

    Integrated photonics generally is the integration of multiple lithographically defined photonic and electronic components and devices (e.g. lasers, detectors, waveguides passive structures, modulators, electronic control and optical interconnects) on a single platform with nanometer-scale feature sizes. The development of photonic integrated circuits permits size, weight, power and cost reductions for spacecraft microprocessors, optical communication, processor buses, advanced data processing, and integrated optic science instrument optical systems, subsystems and components. This is particularly critical for small spacecraft platforms. We will give an overview of some NASA applications for integrated photonics.

  15. Graphene radio frequency receiver integrated circuit.

    Science.gov (United States)

    Han, Shu-Jen; Garcia, Alberto Valdes; Oida, Satoshi; Jenkins, Keith A; Haensch, Wilfried

    2014-01-01

    Graphene has attracted much interest as a future channel material in radio frequency electronics because of its superior electrical properties. Fabrication of a graphene integrated circuit without significantly degrading transistor performance has proven to be challenging, posing one of the major bottlenecks to compete with existing technologies. Here we present a fabrication method fully preserving graphene transistor quality, demonstrated with the implementation of a high-performance three-stage graphene integrated circuit. The circuit operates as a radio frequency receiver performing signal amplification, filtering and downconversion mixing. All circuit components are integrated into 0.6 mm(2) area and fabricated on 200 mm silicon wafers, showing the unprecedented graphene circuit complexity and silicon complementary metal-oxide-semiconductor process compatibility. The demonstrated circuit performance allow us to use graphene integrated circuit to perform practical wireless communication functions, receiving and restoring digital text transmitted on a 4.3-GHz carrier signal.

  16. Bioluminescent bioreporter integrated circuit

    Energy Technology Data Exchange (ETDEWEB)

    Simpson, Michael L. (Knoxville, TN); Sayler, Gary S. (Blaine, TN); Paulus, Michael J. (Knoxville, TN)

    2000-01-01

    Disclosed are monolithic bioelectronic devices comprising a bioreporter and an OASIC. These bioluminescent bioreporter integrated circuit are useful in detecting substances such as pollutants, explosives, and heavy-metals residing in inhospitable areas such as groundwater, industrial process vessels, and battlefields. Also disclosed are methods and apparatus for environmental pollutant detection, oil exploration, drug discovery, industrial process control, and hazardous chemical monitoring.

  17. Radio frequency integrated circuit design

    CERN Document Server

    Rogers, John W M

    2010-01-01

    This newly revised and expanded edition of the 2003 Artech House classic, Radio Frequency Integrated Circuit Design, serves as an up-to-date, practical reference for complete RFIC know-how. The second edition includes numerous updates, including greater coverage of CMOS PA design, RFIC design with on-chip components, and more worked examples with simulation results. By emphasizing working designs, this book practically transports you into the authors' own RFIC lab so you can fully understand the function of each design detailed in this book. Among the RFIC designs examined are RF integrated LC

  18. Linear integrated circuits

    CERN Document Server

    Carr, Joseph

    1996-01-01

    The linear IC market is large and growing, as is the demand for well trained technicians and engineers who understand how these devices work and how to apply them. Linear Integrated Circuits provides in-depth coverage of the devices and their operation, but not at the expense of practical applications in which linear devices figure prominently. This book is written for a wide readership from FE and first degree students, to hobbyists and professionals.Chapter 1 offers a general introduction that will provide students with the foundations of linear IC technology. From chapter 2 onwa

  19. Nano integrated circuit process

    Energy Technology Data Exchange (ETDEWEB)

    Yoon, Yung Sup

    2004-02-15

    This book contains nine chapters, which are introduction of manufacture of semiconductor chip, oxidation such as Dry-oxidation, wet oxidation, oxidation model and oxide film, diffusion like diffusion process, diffusion equation, diffusion coefficient and diffusion system, ion implantation, including ion distribution, channeling, multiimplantation and masking and its system, sputtering such as CVD and PVD, lithography, wet etch and dry etch, interconnection and flattening like metal-silicon connection, silicide, multiple layer metal process and flattening, an integrated circuit process, including MOSFET and CMOS.

  20. A 2.5-Gb/s fully-integrated, low-power clock and recovery circuit in 0.18-{mu}m CMOS

    Energy Technology Data Exchange (ETDEWEB)

    Zhang Changchun; Wang Zhigong; Shi Si; Guo Yufeng, E-mail: zgwang@seu.edu.c [Institute of RF- and OE-ICs, Southeast University, Nanjing 210096 (China)

    2010-03-15

    Based on the devised system-level design methodology, a 2.5-Gb/s monolithic bang-bang phase-locked clock and data recovery (CDR) circuit has been designed and fabricated in SMIC's 0.18-{mu}m CMOS technology. The Pottbaecker phase frequency detector and a differential 4-stage inductorless ring VCO are adopted, where an additional current source is added to the VCO cell to improve the linearity of the VCO characteristic. The CDR has an active area of 340 x 440 {mu}m{sup 2}, and consumes apower of only about 60 mW from a 1.8 V supply voltage, with an input sensitivity of less than 25 mV, and an output single-ended swing of more than 300 mV It has a pull-in range of 800 MHz, and a phase noise of -111.54 dBc/Hz at 10 kHz offset. The CDR works reliably at any input data rate between 1.8 Gb/s and 2.6 Gb/s without any need for reference clock, off-chip tuning, or external components. (semiconductor integrated circuits)

  1. Diamond Integrated Optomechanical Circuits

    CERN Document Server

    Rath, Patrik; Nebel, Christoph; Wild, Christoph; Pernice, Wolfram H P

    2013-01-01

    Diamond offers unique material advantages for the realization of micro- and nanomechanical resonators due to its high Young's modulus, compatibility with harsh environments and superior thermal properties. At the same time, the wide electronic bandgap of 5.45eV makes diamond a suitable material for integrated optics because of broadband transparency and the absence of free-carrier absorption commonly encountered in silicon photonics. Here we take advantage of both to engineer full-scale optomechanical circuits in diamond thin films. We show that polycrystalline diamond films fabricated by chemical vapour deposition provide a convenient waferscale substrate for the realization of high quality nanophotonic devices. Using free-standing nanomechanical resonators embedded in on-chip Mach-Zehnder interferometers, we demonstrate efficient optomechanical transduction via gradient optical forces. Fabricated diamond resonators reproducibly show high mechanical quality factors up to 11,200. Our low cost, wideband, carri...

  2. Integrated coherent matter wave circuits

    International Nuclear Information System (INIS)

    An integrated coherent matter wave circuit is a single device, analogous to an integrated optical circuit, in which coherent de Broglie waves are created and then launched into waveguides where they can be switched, divided, recombined, and detected as they propagate. Applications of such circuits include guided atom interferometers, atomtronic circuits, and precisely controlled delivery of atoms. We report experiments demonstrating integrated circuits for guided coherent matter waves. The circuit elements are created with the painted potential technique, a form of time-averaged optical dipole potential in which a rapidly moving, tightly focused laser beam exerts forces on atoms through their electric polarizability. Moreover, the source of coherent matter waves is a Bose-Einstein condensate (BEC). Finally, we launch BECs into painted waveguides that guide them around bends and form switches, phase coherent beamsplitters, and closed circuits. These are the basic elements that are needed to engineer arbitrarily complex matter wave circuitry

  3. Synthetic Biology: Integrated Gene Circuits

    OpenAIRE

    Nandagopal, Nagarajan; Michael B Elowitz

    2011-01-01

    A major goal of synthetic biology is to develop a deeper understanding of biological design principles from the bottom up, by building circuits and studying their behavior in cells. Investigators initially sought to design circuits “from scratch” that functioned as independently as possible from the underlying cellular system. More recently, researchers have begun to develop a new generation of synthetic circuits that integrate more closely with endogenous cellular processes. These approaches...

  4. Secure integrated circuits and systems

    CERN Document Server

    Verbauwhede, Ingrid MR

    2010-01-01

    On any advanced integrated circuit or 'system-on-chip' there is a need for security. In many applications the actual implementation has become the weakest link in security rather than the algorithms or protocols. The purpose of the book is to give the integrated circuits and systems designer an insight into the basics of security and cryptography from the implementation point of view. As a designer of integrated circuits and systems it is important to know both the state-of-the-art attacks as well as the countermeasures. Optimizing for security is different from optimizations for speed, area,

  5. Variational integrators for electric circuits

    CERN Document Server

    Ober-Blöbaum, Sina; Cheng, Mulin; Owhadi, Houman; Marsden, Jerrold E

    2011-01-01

    In this contribution, we develop a variational integrator for the simulation of (stochastic and multiscale) electric circuits. When considering the dynamics of an electrical circuit, one is faced with three special situations: 1. The system involves external (control) forcing through external (controlled) voltage sources and resistors. 2. The system is constrained via the Kirchhoff current (KCL) and voltage laws (KVL). 3. The Lagrangian is degenerate. Based on a geometric setting, an appropriate variational formulation is presented to model the circuit from which the equations of motion are derived. A time-discrete variational formulation provides an iteration scheme for the simulation of the electric circuit. Dependent on the discretization, the intrinsic degeneracy of the system can be canceled for the discrete variational scheme. In this way, a variational integrator is constructed that gains several advantages compared to standard integration tools for circuits; in particular, a comparison to BDF methods ...

  6. Dynamical properties of electrical circuits with fully nonlinear memristors

    CERN Document Server

    Riaza, Ricardo

    2010-01-01

    The recent design of a nanoscale device with a memristive characteristic has had a great impact in nonlinear circuit theory. Such a device, whose existence was predicted by Leon Chua in 1971, is governed by a charge-dependent voltage-current relation of the form $v=M(q)i$. In this paper we show that allowing for a fully nonlinear characteristic $v=\\eta(q, i)$ in memristive devices provides a general framework for modeling and analyzing a very broad family of electrical and electronic circuits; Chua's memristors are particular instances in which $\\eta(q,i)$ is linear in $i$. We examine several dynamical features of circuits with fully nonlinear memristors, accommodating not only charge-controlled but also flux-controlled ones, with a characteristic of the form $i=\\zeta(\\varphi, v)$. Our results apply in particular to Chua's memristive circuits; certain properties of these can be seen as a consequence of the special form of the elastance and reluctance matrices displayed by Chua's memristors.

  7. CADAT integrated circuit mask analysis

    Science.gov (United States)

    1981-01-01

    CADAT System Mask Analysis Program (MAPS2) is automated software tool for analyzing integrated-circuit mask design. Included in MAPS2 functions are artwork verification, device identification, nodal analysis, capacitance calculation, and logic equation generation.

  8. Electronic design with integrated circuits

    Science.gov (United States)

    Comer, D. J.

    The book is concerned with the application of integrated circuits and presents the material actually needed by the system designer to do an effective job. The operational amplifier (op amp) is discussed, taking into account the electronic amplifier, the basic op amp, the practical op amp, analog applications, and digital applications. Digital components are considered along with combinational logic, digital subsystems, the microprocessor, special circuits, communications, and integrated circuit building blocks. Attention is given to logic gates, logic families, multivibrators, the digital computer, digital methods, communicating with a computer, computer organization, register and timing circuits for data transfer, arithmetic circuits, memories, the microprocessor chip, the control unit, communicating with the microprocessor, examples of microprocessor architecture, programming a microprocessor, the voltage-controlled oscillator, the phase-locked loop, analog-to-digital conversion, amplitude modulation, frequency modulation, pulse and digital transmission, the semiconductor diode, the bipolar transistor, and the field-effect transistor.

  9. Is a fully heparin-bonded cardiopulmonary bypass circuit superior to a standard cardiopulmonary bypass circuit?

    OpenAIRE

    Mahmood, Sarah; Bilal, Haris; Zaman, Mahvash; Tang, Augustine

    2012-01-01

    A best-evidence topic in cardiac surgery was written according to a structured protocol. The question addressed was ‘Is a fully heparin bonded cardiopulmonary bypass circuit superior to a standard cardiopulmonary bypass circuit?’ Altogether more than 792 papers were found using the reported search, of which 13 represented the best evidence to answer the clinical question. The authors, journal, date and country of publication, patient group studied, study type, relevant outcomes and results of...

  10. Fully integrated, fully automated generation of short tandem repeat profiles

    OpenAIRE

    Tan, Eugene; Rosemary S. Turingan; Hogan, Catherine; Vasantgadkar, Sameer; Palombo, Luke; Schumm, James W.; Richard F Selden

    2013-01-01

    Background The generation of short tandem repeat profiles, also referred to as ‘DNA typing,’ is not currently performed outside the laboratory because the process requires highly skilled technical operators and a controlled laboratory environment and infrastructure with several specialized instruments. The goal of this work was to develop a fully integrated system for the automated generation of short tandem repeat profiles from buccal swab samples, to improve forensic laboratory process flow...

  11. GaAs Optoelectronic Integrated-Circuit Neurons

    Science.gov (United States)

    Lin, Steven H.; Kim, Jae H.; Psaltis, Demetri

    1992-01-01

    Monolithic GaAs optoelectronic integrated circuits developed for use as artificial neurons. Neural-network computer contains planar arrays of optoelectronic neurons, and variable synaptic connections between neurons effected by diffraction of light from volume hologram in photorefractive material. Basic principles of neural-network computers explained more fully in "Optoelectronic Integrated Circuits For Neural Networks" (NPO-17652). In present circuits, devices replaced by metal/semiconductor field effect transistors (MESFET's), which consume less power.

  12. Chip-scale fully reconfigurable optical add/drop multiplexing subsystem in polymer microphotonic circuits

    Science.gov (United States)

    Izuhara, Tomoyuki; Fujita, Junichiro; Radojevic, Antonije; Gerhardt, Reinald; Eldada, Louay A.

    2004-10-01

    We report on a highly integrated photonic circuit using a polymer-based planar waveguide system. The properties of the materials used in this work such as ultra-low optical loss, widely tunable refractive index, and large thermo-optic coefficient, enable a multi-functional chip-scale microphotonic circuit. We discuss the application of this technology to the fabrication of a fully reconfigurable optical add/drop multiplexer. This subsystem includes channel switching, power monitoring, load balancing, and wavelength shuffling functionalities that are required for agile wavelength-division multiplexing optical networks. Optical properties of our material systems and performance characteristics of the implemented optical passive/active elements are presented, and the integration schemes of the devices to achieve a fully integrated reconfigurable optical add/drop multiplexer are discussed.

  13. Vertically Integrated Circuits at Fermilab

    Energy Technology Data Exchange (ETDEWEB)

    Deptuch, Grzegorz; Demarteau, Marcel; Hoff, James; Lipton, Ronald; Shenai, Alpana; Trimpl, Marcel; Yarema, Raymond; Zimmerman, Tom; /Fermilab

    2009-01-01

    The exploration of the vertically integrated circuits, also commonly known as 3D-IC technology, for applications in radiation detection started at Fermilab in 2006. This paper examines the opportunities that vertical integration offers by looking at various 3D designs that have been completed by Fermilab. The emphasis is on opportunities that are presented by through silicon vias (TSV), wafer and circuit thinning and finally fusion bonding techniques to replace conventional bump bonding. Early work by Fermilab has led to an international consortium for the development of 3D-IC circuits for High Energy Physics. The consortium has submitted over 25 different designs for the Fermilab organized MPW run organized for the first time.

  14. Design automation for integrated circuits

    Science.gov (United States)

    Newell, S. B.; de Geus, A. J.; Rohrer, R. A.

    1983-04-01

    Consideration is given to the development status of the use of computers in automated integrated circuit design methods, which promise the minimization of both design time and design error incidence. Integrated circuit design encompasses two major tasks: error specification, in which the goal is a logic diagram that accurately represents the desired electronic function, and physical specification, in which the goal is an exact description of the physical locations of all circuit elements and their interconnections on the chip. Design automation not only saves money by reducing design and fabrication time, but also helps the community of systems and logic designers to work more innovatively. Attention is given to established design automation methodologies, programmable logic arrays, and design shortcuts.

  15. Delay locked loop integrated circuit.

    Energy Technology Data Exchange (ETDEWEB)

    Brocato, Robert Wesley

    2007-10-01

    This report gives a description of the development of a Delay Locked Loop (DLL) integrated circuit (IC). The DLL was developed and tested as a stand-alone IC test chip to be integrated into a larger application specific integrated circuit (ASIC), the Quadrature Digital Waveform Synthesizer (QDWS). The purpose of the DLL is to provide a digitally programmable delay to enable synchronization between an internal system clock and external peripherals with unknown clock skew. The DLL was designed and fabricated in the IBM 8RF process, a 0.13 {micro}m CMOS process. It was designed to operate with a 300MHz clock and has been tested up to 500MHz.

  16. Fully integrated, fully automated generation of short tandem repeat profiles

    Science.gov (United States)

    2013-01-01

    Background The generation of short tandem repeat profiles, also referred to as ‘DNA typing,’ is not currently performed outside the laboratory because the process requires highly skilled technical operators and a controlled laboratory environment and infrastructure with several specialized instruments. The goal of this work was to develop a fully integrated system for the automated generation of short tandem repeat profiles from buccal swab samples, to improve forensic laboratory process flow as well as to enable short tandem repeat profile generation to be performed in police stations and in field-forward military, intelligence, and homeland security settings. Results An integrated system was developed consisting of an injection-molded microfluidic BioChipSet cassette, a ruggedized instrument, and expert system software. For each of five buccal swabs, the system purifies DNA using guanidinium-based lysis and silica binding, amplifies 15 short tandem repeat loci and the amelogenin locus, electrophoretically separates the resulting amplicons, and generates a profile. No operator processing of the samples is required, and the time from swab insertion to profile generation is 84 minutes. All required reagents are contained within the BioChipSet cassette; these consist of a lyophilized polymerase chain reaction mix and liquids for purification and electrophoretic separation. Profiles obtained from fully automated runs demonstrate that the integrated system generates concordant short tandem repeat profiles. The system exhibits single-base resolution from 100 to greater than 500 bases, with inter-run precision with a standard deviation of ±0.05 - 0.10 bases for most alleles. The reagents are stable for at least 6 months at 22°C, and the instrument has been designed and tested to Military Standard 810F for shock and vibration ruggedization. A nontechnical user can operate the system within or outside the laboratory. Conclusions The integrated system represents the

  17. Microcontroller based Integrated Circuit Tester

    OpenAIRE

    Yousif Taha Yousif Elamin; Abdelrasoul Jabar Alzubaidi

    2015-01-01

    The digital integrated circuit (IC) tester is implemented by using the ATmega32 microcontroller . The microcontroller processes the inputs and outputs and displays the results on a Liquid Crystal Display (LCD). The basic function of the digital IC tester is to test a digital IC for correct logical functioning as described in the truth table and/or function table. The designed model can test digital ICs having 14 pins. Since it is programmable, any number of ICs can be tested . Thi...

  18. Fully integrated biochip platforms for advanced healthcare.

    Science.gov (United States)

    Carrara, Sandro; Ghoreishizadeh, Sara; Olivo, Jacopo; Taurino, Irene; Baj-Rossi, Camilla; Cavallini, Andrea; de Beeck, Maaike Op; Dehollain, Catherine; Burleson, Wayne; Moussy, Francis Gabriel; Guiseppi-Elie, Anthony; De Micheli, Giovanni

    2012-01-01

    Recent advances in microelectronics and biosensors are enabling developments of innovative biochips for advanced healthcare by providing fully integrated platforms for continuous monitoring of a large set of human disease biomarkers. Continuous monitoring of several human metabolites can be addressed by using fully integrated and minimally invasive devices located in the sub-cutis, typically in the peritoneal region. This extends the techniques of continuous monitoring of glucose currently being pursued with diabetic patients. However, several issues have to be considered in order to succeed in developing fully integrated and minimally invasive implantable devices. These innovative devices require a high-degree of integration, minimal invasive surgery, long-term biocompatibility, security and privacy in data transmission, high reliability, high reproducibility, high specificity, low detection limit and high sensitivity. Recent advances in the field have already proposed possible solutions for several of these issues. The aim of the present paper is to present a broad spectrum of recent results and to propose future directions of development in order to obtain fully implantable systems for the continuous monitoring of the human metabolism in advanced healthcare applications. PMID:23112644

  19. Fully Integrated Biochip Platforms for Advanced Healthcare

    Science.gov (United States)

    Carrara, Sandro; Ghoreishizadeh, Sara; Olivo, Jacopo; Taurino, Irene; Baj-Rossi, Camilla; Cavallini, Andrea; de Beeck, Maaike Op; Dehollain, Catherine; Burleson, Wayne; Moussy, Francis Gabriel; Guiseppi-Elie, Anthony; De Micheli, Giovanni

    2012-01-01

    Recent advances in microelectronics and biosensors are enabling developments of innovative biochips for advanced healthcare by providing fully integrated platforms for continuous monitoring of a large set of human disease biomarkers. Continuous monitoring of several human metabolites can be addressed by using fully integrated and minimally invasive devices located in the sub-cutis, typically in the peritoneal region. This extends the techniques of continuous monitoring of glucose currently being pursued with diabetic patients. However, several issues have to be considered in order to succeed in developing fully integrated and minimally invasive implantable devices. These innovative devices require a high-degree of integration, minimal invasive surgery, long-term biocompatibility, security and privacy in data transmission, high reliability, high reproducibility, high specificity, low detection limit and high sensitivity. Recent advances in the field have already proposed possible solutions for several of these issues. The aim of the present paper is to present a broad spectrum of recent results and to propose future directions of development in order to obtain fully implantable systems for the continuous monitoring of the human metabolism in advanced healthcare applications. PMID:23112644

  20. Integrated circuits for multimedia applications

    DEFF Research Database (Denmark)

    Vandi, Luca

    2007-01-01

    , and it is applied to a broad-band dual-loop receiver architecture in order to boost the linearity performances of the stage. A simplified noise- and linearity analysis of the circuit is derived, and a comparison is provided with a more traditional dual-loop topology (a broad-band stage based on shunt......This work presents several key aspects in the design of RF integrated circuits for portable multimedia devices. One chapter is dedicated to the application of negative-feedback topologies to receiver frontends. A novel feedback technique suitable for common multiplier-based mixers is described......-series feedback), showing a difference in compression point in the order of 10dBm for the same power consumption. The same principle is also applied to a more conventional narrow-band stage in which a single loop is employed in order to enhance noise performances. Noise analysis shows sensible improvements...

  1. Integrated Circuit Electromagnetic Immunity Handbook

    Science.gov (United States)

    Sketoe, J. G.

    2000-08-01

    This handbook presents the results of the Boeing Company effort for NASA under contract NAS8-98217. Immunity level data for certain integrated circuit parts are discussed herein, along with analytical techniques for applying the data to electronics systems. This handbook is built heavily on the one produced in the seventies by McDonnell Douglas Astronautics Company (MDAC, MDC Report E1929 of 1 August 1978, entitled Integrated Circuit Electromagnetic Susceptibility Handbook, known commonly as the ICES Handbook, which has served countless systems designers for over 20 years). Sections 2 and 3 supplement the device susceptibility data presented in section 4 by presenting information on related material required to use the IC susceptibility information. Section 2 concerns itself with electromagnetic susceptibility analysis and serves as a guide in using the information contained in the rest of the handbook. A suggested system hardening requirements is presented in this chapter. Section 3 briefly discusses coupling and shielding considerations. For conservatism and simplicity, a worst case approach is advocated to determine the maximum amount of RF power picked up from a given field. This handbook expands the scope of the immunity data in this Handbook is to of 10 MHz to 10 GHz. However, the analytical techniques provided are applicable to much higher frequencies as well. It is expected however, that the upper frequency limit of concern is near 10 GHz. This is due to two factors; the pickup of microwave energy on system cables and wiring falls off as the square of the wavelength, and component response falls off at a rapid rate due to the effects of parasitic shunt paths for the RF energy. It should be noted also that the pickup on wires and cables does not approach infinity as the frequency decreases (as would be expected by extrapolating the square law dependence of the high frequency roll-off to lower frequencies) but levels off due to mismatch effects.

  2. Towards Fully Integrated Wireless Impedimetric Sensors

    Directory of Open Access Journals (Sweden)

    Fredy Segura-Quijano

    2010-04-01

    Full Text Available We report on the design and characterization of the building blocks of a single-chip wireless chemical sensor fabricated with a commercial complementary metal-oxide-silicon (CMOS technology, which includes two types of transducers for impedimetric measurements (4-electrode array and two interdigitated electrodes, instrumentation circuits, and a metal coil and circuits for inductive power and data transfer. The electrodes have been formed with a polycrystalline silicon layer of the technology by a simple post-process that does not require additional deposition or lithography steps, but just etching steps. A linear response to both conductivity and permittivity of solutions has been obtained. Wireless communication of the sensor chip with a readout unit has been demonstrated. The design of the chip was prepared for individual block characterization and not for full system characterization. The integration of chemical transducers within monolithic wireless platforms will lead to smaller, cheaper, and more reliable chemical microsensors, and will open up the door to numerous new applications where liquid mediums that are enclosed in sealed receptacles have to be measured.

  3. A novel fully integrated handheld gamma camera

    Science.gov (United States)

    Massari, R.; Ucci, A.; Campisi, C.; Scopinaro, F.; Soluri, A.

    2016-10-01

    In this paper, we present an innovative, fully integrated handheld gamma camera, namely designed to gather in the same device the gamma ray detector with the display and the embedded computing system. The low power consumption allows the prototype to be battery operated. To be useful in radioguided surgery, an intraoperative gamma camera must be very easy to handle since it must be moved to find a suitable view. Consequently, we have developed the first prototype of a fully integrated, compact and lightweight gamma camera for radiopharmaceuticals fast imaging. The device can operate without cables across the sterile field, so it may be easily used in the operating theater for radioguided surgery. The prototype proposed consists of a Silicon Photomultiplier (SiPM) array coupled with a proprietary scintillation structure based on CsI(Tl) crystals. To read the SiPM output signals, we have developed a very low power readout electronics and a dedicated analog to digital conversion system. One of the most critical aspects we faced designing the prototype was the low power consumption, which is mandatory to develop a battery operated device. We have applied this detection device in the lymphoscintigraphy technique (sentinel lymph node mapping) comparing the results obtained with those of a commercial gamma camera (Philips SKYLight). The results obtained confirm a rapid response of the device and an adequate spatial resolution for the use in the scintigraphic imaging. This work confirms the feasibility of a small gamma camera with an integrated display. This device is designed for radioguided surgery and small organ imaging, but it could be easily combined into surgical navigation systems.

  4. Active components for integrated plasmonic circuits

    DEFF Research Database (Denmark)

    Krasavin, A.V.; Bolger, P.M.; Zayats, A.V.;

    2009-01-01

    We present a comprehensive study of highly efficient and compact passive and active components for integrated plasmonic circuit based on dielectric-loaded surface plasmon polariton waveguides.......We present a comprehensive study of highly efficient and compact passive and active components for integrated plasmonic circuit based on dielectric-loaded surface plasmon polariton waveguides....

  5. Post irradiation effects (PIE) in integrated circuits

    International Nuclear Information System (INIS)

    Post Irradiation Effects (PIE) ranging from normal recovery catastrophic failure have been observed in integrated circuits during the PIE period. These variations indicate that a rebound or PIE recipe used for radiation hardness assurance must be chosen with care. In this paper, the authors provide examples of PIE in a variety of integrated circuits of importance to spacecraft electronics

  6. Microcontroller based Integrated Circuit Tester

    Directory of Open Access Journals (Sweden)

    Yousif Taha Yousif Elamin

    2015-02-01

    Full Text Available The digital integrated circuit (IC tester is implemented by using the ATmega32 microcontroller . The microcontroller processes the inputs and outputs and displays the results on a Liquid Crystal Display (LCD. The basic function of the digital IC tester is to test a digital IC for correct logical functioning as described in the truth table and/or function table. The designed model can test digital ICs having 14 pins. Since it is programmable, any number of ICs can be tested . This model applies the necessary signals to the inputs of the IC, monitoring the outputs at each stage and comparing them with the outputs in the truth table. Any discrepancy in the functioning of the IC results in a fail indication, displays the faulty and good gates on the LCD. The testing procedure is accomplished with the help of keypad keys present on the main board design. The test has been accomplished with most commonly used digital IC's, mainly belonging to the 74 series. Digital IC tester tests three samples of IC's ( NAND, NOT, NOR. The design is flexible . We can add extra IC bases and subroutines to test any other IC in the 74 series.

  7. Wafer-scale graphene integrated circuit.

    Science.gov (United States)

    Lin, Yu-Ming; Valdes-Garcia, Alberto; Han, Shu-Jen; Farmer, Damon B; Meric, Inanc; Sun, Yanning; Wu, Yanqing; Dimitrakopoulos, Christos; Grill, Alfred; Avouris, Phaedon; Jenkins, Keith A

    2011-06-10

    A wafer-scale graphene circuit was demonstrated in which all circuit components, including graphene field-effect transistor and inductors, were monolithically integrated on a single silicon carbide wafer. The integrated circuit operates as a broadband radio-frequency mixer at frequencies up to 10 gigahertz. These graphene circuits exhibit outstanding thermal stability with little reduction in performance (less than 1 decibel) between 300 and 400 kelvin. These results open up possibilities of achieving practical graphene technology with more complex functionality and performance.

  8. Semiconductors integrated circuit design for manufacturability

    CERN Document Server

    Balasinki, Artur

    2011-01-01

    Because of the continuous evolution of integrated circuit manufacturing (ICM) and design for manufacturability (DfM), most books on the subject are obsolete before they even go to press. That's why the field requires a reference that takes the focus off of numbers and concentrates more on larger economic concepts than on technical details. Semiconductors: Integrated Circuit Design for Manufacturability covers the gradual evolution of integrated circuit design (ICD) as a basis to propose strategies for improving return-on-investment (ROI) for ICD in manufacturing. Where most books put the spotl

  9. Silicon integrated circuits part A : supplement 2

    CERN Document Server

    Kahng, Dawon

    1981-01-01

    Applied Solid State Science, Supplement 2: Silicon Integrated Circuits, Part A focuses on MOS device physics. This book is divided into three chapters-physics of the MOS transistor; nonvolatile memories; and properties of silicon-on-sapphire substrates devices, and integrated circuits. The topics covered include the short channel effects, MOSFET structures, floating gate devices, technology for nonvolatile semiconductor memories, sapphire substrates, and SOS integrated circuits and systems. The MOS capacitor, MIOS devices, and SOS process and device technology are also deliberated. This public

  10. Lateral power transistors in integrated circuits

    CERN Document Server

    Erlbacher, Tobias

    2014-01-01

    This book details and compares recent advancements in the development of novel lateral power transistors (LDMOS devices) for integrated circuits in power electronic applications. It includes the state-of-the-art concept of double-acting RESURF topologies.

  11. LC Quadrature Generation in Integrated Circuits

    DEFF Research Database (Denmark)

    Christensen, Kåre Tais

    2001-01-01

    Today quadrature signals for IQ demodulation are provided through RC polyphase networks, quadrature oscillators or double frequency VCOs. This paper presents a new method for generating quadrature signals in integrated circuits using only inductors and capacitors. This LC quadrature generation...

  12. Integrated Circuit Stellar Magnitude Simulator

    Science.gov (United States)

    Blackburn, James A.

    1978-01-01

    Describes an electronic circuit which can be used to demonstrate the stellar magnitude scale. Six rectangular light-emitting diodes with independently adjustable duty cycles represent stars of magnitudes 1 through 6. Experimentally verifies the logarithmic response of the eye. (Author/GA)

  13. Radio-frequency integrated-circuit engineering

    CERN Document Server

    Nguyen, Cam

    2015-01-01

    Radio-Frequency Integrated-Circuit Engineering addresses the theory, analysis and design of passive and active RFIC's using Si-based CMOS and Bi-CMOS technologies, and other non-silicon based technologies. The materials covered are self-contained and presented in such detail that allows readers with only undergraduate electrical engineering knowledge in EM, RF, and circuits to understand and design RFICs. Organized into sixteen chapters, blending analog and microwave engineering, Radio-Frequency Integrated-Circuit Engineering emphasizes the microwave engineering approach for RFICs. Provide

  14. Handbook of microwave integrated circuits

    Science.gov (United States)

    Hoffmann, Reinmut K.

    The design and operation of ICs for use in the 0.5-20-GHz range are described in an introductory and reference work for industrial engineers. Chapters are devoted to an overview of microwave IC (MIC) technology, general stripline characteristics, microwave transmission line (MTL) parameters for microstrips with isotropic dielectric substrates, higher-order modes on a microstrip, the effects of metallic enclosure on MTL transmission parameters, losses in microstrips, the measurement of MTL parameters, and MTLs on anisotropic dielectric substrates. Consideration is given to coupled microstrips on dielectric substrates, microstrip discontinuities, radiation from microstrip circuits, MTL variations, coplanar MTLs, slotlines, and spurious modes in MTL circuits. Diagrams, drawings, graphs, and a glossary of symbols are provided.

  15. Progress in organic integrated circuit manufacture

    Science.gov (United States)

    Taylor, D. Martin

    2016-02-01

    This review article focuses on the development of processes for the manufacture of organic electronic circuits. Beginning with the first report of an organic transistor it highlights the key developments leading to the successful manufacture of microprocessors and other complex circuits incorporating organic transistors. Both batch processing (based on silicon integrated circuit technology) as well as mass-printing, roll-to-roll (R2R) approaches are discussed. Currently, the best circuit performances are achieved using batch processing. It is suggested that an emerging, large mass-market for electronic tags may dictate that R2R manufacture will likely be required to meet the high throughput rates needed. However, significant improvements in resolution and registration are necessary to achieve increased circuit operating speeds.

  16. Electronic circuits and systems: A compilation. [including integrated circuits, logic circuits, varactor diode circuits, low pass filters, and optical equipment circuits

    Science.gov (United States)

    1975-01-01

    Technological information is presented electronic circuits and systems which have potential utility outside the aerospace community. Topics discussed include circuit components such as filters, converters, and integrators, circuits designed for use with specific equipment or systems, and circuits designed primarily for use with optical equipment or displays.

  17. Integrated circuit design using design automation

    International Nuclear Information System (INIS)

    Although the use of computer aids to develop integrated circuits is relatively new at Sandia, the program has been very successful. The results have verified the utility of the in-house CAD design capability. Custom IC's have been developed in much shorter times than available through semiconductor device manufacturers. In addition, security problems were minimized and a saving was realized in circuit cost. The custom CMOS IC's were designed at less than half the cost of designing with conventional techniques. In addition to the computer aided design, the prototype fabrication and testing capability provided by the semiconductor development laboratory and microelectronics computer network allows the circuits to be fabricated and evaluated before the designs are transferred to the commercial semiconductor manufacturers for production. The Sandia design and prototype fabrication facilities provide the capability of complete custom integrated circuit development entirely within the ERDA laboratories

  18. Vertical interconnection of SOI photonic integrated circuits

    NARCIS (Netherlands)

    Hagen, R.; Pozo Torres, J.M.; Kazmierczak, A.; Westerveld, W.J.; Harmsma, P.J.; Berg, J.H. van den; Schmits, R.; Yousefi, M.; Cabezon, M.; Villafranca, A.; Izquierdo, D.; Garces, J.I.

    2011-01-01

    One of the important issues of System-on-a-package integration is the interconnection between independent Photonic Integrated Circuits (PICs). In this work, this issue is addressed by the use of Vertical Grating Couplers (VGCs) as the element for the interconnection between two Silicon-on-Insulator

  19. VISA Final Report: Fully Integrated Power Electronic Systems in Automotive Electronics

    OpenAIRE

    Waffenschmidt, E

    2011-01-01

    This report summarizes the activities related to the public funded project “Vollintegrierte leistungselektronische Systeme in der Automobilelektronik – VISA” (Fully Integrated Power Electronic Systems in Automotive Electronics). Aim of the project is to investigate the integration of components into printed circuit boards (PCB) for automotive power applications. For Philips, this technology is interesting for integrated LED drivers as used e.g. in automotive head lamps. The project is funded ...

  20. Solution methods for very highly integrated circuits.

    Energy Technology Data Exchange (ETDEWEB)

    Nong, Ryan; Thornquist, Heidi K.; Chen, Yao; Mei, Ting; Santarelli, Keith R.; Tuminaro, Raymond Stephen

    2010-12-01

    While advances in manufacturing enable the fabrication of integrated circuits containing tens-to-hundreds of millions of devices, the time-sensitive modeling and simulation necessary to design these circuits poses a significant computational challenge. This is especially true for mixed-signal integrated circuits where detailed performance analyses are necessary for the individual analog/digital circuit components as well as the full system. When the integrated circuit has millions of devices, performing a full system simulation is practically infeasible using currently available Electrical Design Automation (EDA) tools. The principal reason for this is the time required for the nonlinear solver to compute the solutions of large linearized systems during the simulation of these circuits. The research presented in this report aims to address the computational difficulties introduced by these large linearized systems by using Model Order Reduction (MOR) to (i) generate specialized preconditioners that accelerate the computation of the linear system solution and (ii) reduce the overall dynamical system size. MOR techniques attempt to produce macromodels that capture the desired input-output behavior of larger dynamical systems and enable substantial speedups in simulation time. Several MOR techniques that have been developed under the LDRD on 'Solution Methods for Very Highly Integrated Circuits' will be presented in this report. Among those presented are techniques for linear time-invariant dynamical systems that either extend current approaches or improve the time-domain performance of the reduced model using novel error bounds and a new approach for linear time-varying dynamical systems that guarantees dimension reduction, which has not been proven before. Progress on preconditioning power grid systems using multi-grid techniques will be presented as well as a framework for delivering MOR techniques to the user community using Trilinos and the Xyce circuit

  1. Integrated circuits and their application. Mikroskhemy i ikh primenenie

    Energy Technology Data Exchange (ETDEWEB)

    Batushev, V.A.; Veniaminov, V.N.; Kovalev, V.G.; Lebedev, O.N.; Miroshnichenko, A.I.

    1978-01-01

    The subject is covered in eight chapters, namely: (1) General Information on Integrated Circuits; (2) Analog Integrated Circuits and Standard Functional Devices; (3) Application of Analog Integrated Circuits; (4) Digital Integrated Circuits and Standard Functional Devices; (5) Microprocessors and Memory Integrated Circuits; (6) Digital-to-Analog and Analog-to-Digital Converters Using Integrated Circuits; (7) Application of Digital Integrated Circuits in Electronic Equipment; and (8) Design of Radio Electronic Components Based on ICs. An addenum, system for IC Designations, is included. 55 references.

  2. Integrated microsphere planar lightwave circuits

    OpenAIRE

    J. S. Wilkinson; Murugan, G.S.; Hewak, D. W.; M. N. Zervas; Panitchob, Y.; Elliott, G. R.; Bartlett, P. N.; Tull, E.J.; Ryan, K R

    2010-01-01

    Multicomponent glass microspheres self-assembled on optical waveguides combine tailored optical properties with strong light/material interaction potentially leading to compact low-power photonic devices. Progress and prospects for microsphere/waveguide integration will be described

  3. Laboratory experiments in integrated circuit fabrication

    Science.gov (United States)

    Jenkins, Thomas J.; Kolesar, Edward S.

    1993-06-01

    The objectives of the experiment are fourfold: to provide practical experience implementing the fundamental processes and technology associated with the science and art of integrated circuit (IC) fabrication; to afford the opportunity for the student to apply the theory associated with IC fabrication and semiconductor device operation; to motivate the student to exercise engineering decisions associated with fabricating integrated circuits; and to complement the theory of n-channel MOS and diffused devices that are presented in the classroom by actually fabricating and testing them. Therefore, a balance between theory and practice can be realized in the education of young engineers, whose education is often criticized as lacking sufficient design and practical content.

  4. Test Structures For Bumpy Integrated Circuits

    Science.gov (United States)

    Buehler, Martin G.; Sayah, Hoshyar R.

    1989-01-01

    Cross-bridge resistors added to comb and serpentine patterns. Improved combination of test structures built into integrated circuit used to evaluate design rules, fabrication processes, and quality of interconnections. Consist of meshing serpentines and combs, and cross bridge. Structures used to make electrical measurements revealing defects in design or fabrication. Combination of test structures includes three comb arrays, two serpentine arrays, and cross bridge. Made of aluminum or polycrystalline silicon, depending on material in integrated-circuit layers evaluated. Aluminum combs and serpentine arrays deposited over steps made by polycrystalline silicon and diffusion layers, while polycrystalline silicon versions of these structures used to cross over steps made by thick oxide layer.

  5. Fully Integral, Flexible Composite Driveshaft Project

    Data.gov (United States)

    National Aeronautics and Space Administration — An all-composite driveshaft incorporating integral flexible diaphragms is described and proposed for phase II prime conractor testing. The approach obsoletes the...

  6. Fully Integral, Flexible Composite Driveshaft Project

    Data.gov (United States)

    National Aeronautics and Space Administration — An all-composite driveshaft incorporating integral flexible diaphragms is described and proposed for further refinement. An approach is explored which obsoletes the...

  7. An integrated circuit/packet switched video conferencing system

    International Nuclear Information System (INIS)

    The HEP Network Resource Center (HEPNRC) at Fermilab and the Collider Detector Facility (CDF) collaboration have evolved a flexible, cost-effective, widely accessible video conferencing system for use by high energy physics collaborations and others wishing to use video conferencing. No current systems seemed to fully meet the needs of high energy physics collaborations. However, two classes of video conferencing technology: circuit-switched and packet-switched, if integrated, might encompass most of HEPS's needs. It was also realized that, even with this integration, some additional functions were needed and some of the existing functions were not always wanted. HEPNRC with the help of members of the CDF collaboration set out to develop such an integrated system using as many existing subsystems and components as possible. This system is called VUPAC (Video conferencing Using Packets and Circuits). This paper begins with brief descriptions of the circuit-switched and packet-switched video conferencing systems. Following this, issues and limitations of these systems are considered. Next the VUPAC system is described. Integration is accomplished primarily by a circuit/packet video conferencing interface. Augmentation is centered in another subsystem called MSB (Multiport MultiSession Bridge). Finally, there is a discussion of the future work needed in the evolution of this system. (author)

  8. Microwave integrated circuit for Josephson voltage standards

    Science.gov (United States)

    Holdeman, L. B.; Toots, J.; Chang, C. C. (Inventor)

    1980-01-01

    A microwave integrated circuit comprised of one or more Josephson junctions and short sections of microstrip or stripline transmission line is fabricated from thin layers of superconducting metal on a dielectric substrate. The short sections of transmission are combined to form the elements of the circuit and particularly, two microwave resonators. The Josephson junctions are located between the resonators and the impedance of the Josephson junctions forms part of the circuitry that couples the two resonators. The microwave integrated circuit has an application in Josephson voltage standards. In this application, the device is asymmetrically driven at a selected frequency (approximately equal to the resonance frequency of the resonators), and a d.c. bias is applied to the junction. By observing the current voltage characteristic of the junction, a precise voltage, proportional to the frequency of the microwave drive signal, is obtained.

  9. Modeling "Soft" Errors in Bipolar Integrated Circuits

    Science.gov (United States)

    Zoutendyk, J.; Benumof, R.; Vonroos, O.

    1985-01-01

    Mathematical models represent single-event upset in bipolar memory chips. Physics of single-event upset in integrated circuits discussed in theoretical paper. Pair of companion reports present mathematical models to predict critical charges for producing single-event upset in bipolar randomaccess memory (RAM) chips.

  10. Integrated Circuits in the Introductory Electronics Laboratory

    Science.gov (United States)

    English, Thomas C.; Lind, David A.

    1973-01-01

    Discusses the use of an integrated circuit operational amplifier in an introductory electronics laboratory course for undergraduate science majors. The advantages of this approach and the implications for scientific instrumentation are identified. Describes a number of experiments suitable for the undergraduate laboratory. (Author/DF)

  11. Bioluminescent bioreporter integrated circuit detection methods

    Energy Technology Data Exchange (ETDEWEB)

    Simpson, Michael L.; Paulus, Michael J.; Sayler, Gary S.; Applegate, Bruce M.; Ripp, Steven A.

    2005-06-14

    Disclosed are monolithic bioelectronic devices comprising a bioreporter and an OASIC. These bioluminescent bioreporter integrated circuit are useful in detecting substances such as pollutants, explosives, and heavy-metals residing in inhospitable areas such as groundwater, industrial process vessels, and battlefields. Also disclosed are methods and apparatus for detection of particular analytes, including ammonia and estrogen compounds.

  12. Silicon Photonic Integrated Circuit Mode Multiplexer

    DEFF Research Database (Denmark)

    Ding, Yunhong; Ou, Haiyan; Xu, Jing;

    2013-01-01

    We propose and demonstrate a novel silicon photonic integrated circuit enabling multiplexing of orthogonal modes in a few-mode fiber (FMF). By selectively launching light to four vertical grating couplers, all six orthogonal spatial and polarization modes supported by the FMF are successfully...

  13. Bottom-up organic integrated circuits

    NARCIS (Netherlands)

    Smits, Edsger C. P.; Mathijssen, Simon G. J.; van Hal, Paul A.; Setayesh, Sepas; Geuns, Thomas C. T.; Mutsaers, Kees A. H. A.; Cantatore, Eugenio; Wondergem, Harry J.; Werzer, Oliver; Resel, Roland; Kemerink, Martijn; Kirchmeyer, Stephan; Muzafarov, Aziz M.; Ponomarenko, Sergei A.; de Boer, Bert; Blom, Paul W. M.; de Leeuw, Dago M.

    2008-01-01

    Self- assembly - the autonomous organization of components into patterns and structures(1) - is a promising technology for the mass production of organic electronics. Making integrated circuits using a bottom- up approach involving self- assembling molecules was proposed(2) in the 1970s. The basic b

  14. Accurate Electromagnetic Modeling Methods for Integrated Circuits

    NARCIS (Netherlands)

    Sheng, Z.

    2010-01-01

    The present development of modern integrated circuits (IC’s) is characterized by a number of critical factors that make their design and verification considerably more difficult than before. This dissertation addresses the important questions of modeling all electromagnetic behavior of features on t

  15. A fully integrated neural recording amplifier with DC input stabilization.

    Science.gov (United States)

    Mohseni, Pedram; Najafi, Khalil

    2004-05-01

    This paper presents a low-power low-noise fully integrated bandpass operational amplifier for a variety of biomedical neural recording applications. A standard two-stage CMOS amplifier in a closed-loop resistive feedback configuration provides a stable ac gain of 39.3 dB at 1 kHz. A subthreshold PMOS input transistor is utilized to clamp the large and random dc open circuit potentials that normally exist at the electrode-electrolyte interface. The low cutoff frequency of the amplifier is programmable up to 50 Hz, while its high cutoff frequency is measured to be 9.1 kHz. The tolerable dc input range is measured to be at least +/- 0.25 V with a dc rejection factor of at least 29 dB. The amplifier occupies 0.107 mm2 in die area, and dissipates 115 microW from a 3 V power supply. The total measured input-referred noise voltage in the frequency range of 0.1-10 kHz is 7.8 microVrms. It is fabricated using AMI 1.5 microm double-poly double-metal n-well CMOS process. This paper presents full characterization of the dc, ac, and noise performance of this amplifier through in vitro measurements in saline using two different neural recording electrodes. PMID:15132510

  16. Data readout system utilizing photonic integrated circuit

    International Nuclear Information System (INIS)

    We describe a novel optical solution for data readout systems. The core of the system is an Indium-Phosphide photonic integrated circuit performing as a front-end readout unit. It functions as an optical serializer in which the serialization of the input signal is provided by means of on-chip optical delay lines. The circuit employs electro-optic phase shifters to build amplitude modulators, power splitters for signal distribution, semiconductor optical amplifiers for signal amplification as well as on-chip reflectors. We present the concept of the system, the design and first characterization results of the devices that were fabricated in a multi-project wafer run

  17. Data readout system utilizing photonic integrated circuit

    Energy Technology Data Exchange (ETDEWEB)

    Stopiński, S., E-mail: S.Stopinski@tue.nl [COBRA Research Institute, Eindhoven University of Technology (Netherlands); Institute of Microelectronics and Optoelectronics, Warsaw University of Technology (Poland); Malinowski, M.; Piramidowicz, R. [Institute of Microelectronics and Optoelectronics, Warsaw University of Technology (Poland); Smit, M.K.; Leijtens, X.J.M. [COBRA Research Institute, Eindhoven University of Technology (Netherlands)

    2013-10-11

    We describe a novel optical solution for data readout systems. The core of the system is an Indium-Phosphide photonic integrated circuit performing as a front-end readout unit. It functions as an optical serializer in which the serialization of the input signal is provided by means of on-chip optical delay lines. The circuit employs electro-optic phase shifters to build amplitude modulators, power splitters for signal distribution, semiconductor optical amplifiers for signal amplification as well as on-chip reflectors. We present the concept of the system, the design and first characterization results of the devices that were fabricated in a multi-project wafer run.

  18. Power management techniques for integrated circuit design

    CERN Document Server

    Chen, Ke-Horng

    2016-01-01

    This book begins with the premise that energy demands are directing scientists towards ever-greener methods of power management, so highly integrated power control ICs (integrated chip/circuit) are increasingly in demand for further reducing power consumption. * A timely and comprehensive reference guide for IC designers dealing with the increasingly widespread demand for integrated low power management * Includes new topics such as LED lighting, fast transient response, DVS-tracking and design with advanced technology nodes * Leading author (Chen) is an active and renowned contributor to the power management IC design field, and has extensive industry experience * Accompanying website includes presentation files with book illustrations, lecture notes, simulation circuits, solution manuals, instructors manuals, and program downloads.

  19. Applying analog integrated circuits for HERO protection

    Science.gov (United States)

    Willis, Kenneth E.; Blachowski, Thomas J.

    1994-01-01

    One of the most efficient methods for protecting electro-explosive devices (EED's) from HERO and ESD is to shield the EED in a conducting shell (Faraday cage). Electrical energy is transferred to the bridge by means of a magnetic coupling which passes through a portion of the conducting shell that is made from a magnetically permeable but electrically conducting material. This technique was perfected by ML Aviation, a U.K. company, in the early 80's, and was called a Radio Frequency Attenuation Connector (RFAC). It is now in wide use in the U.K. Previously, the disadvantage of RFAC over more conventional methods was its relatively high cost, largely driven by a thick film hybrid circuit used to switch the primary of the transformer. Recently, through a licensing agreement, this technology has been transferred to the U.S. and significant cost reductions and performance improvements have been achieved by the introduction of analog integrated circuits. An integrated circuit performs the following functions: (1) Chops the DC input to a signal suitable for driving the primary of the transformer; (2) Verifies the input voltage is above a threshold; (3) Verifies the input voltage is valid for a pre set time before enabling the device; (4) Provides thermal protection of the circuit; and (5) Provides an external input for independent logic level enabling of the power transfer mechanism. This paper describes the new RFAC product and its applications.

  20. Tomographic reconstruction of an integrated circuit interconnect

    Energy Technology Data Exchange (ETDEWEB)

    Levine, Z.H. [National Institute of Standards and Technology, Gaithersburg, Maryland 20899 (United States); Kalukin, A.R. [Physics Department, Rensselaer Polytechnic Institute, Troy, New York 12180-3590 (United States); Frigo, S.P.; McNulty, I. [Advanced Photon Source, Argonne National Laboratory, Argonne, Illinois 60439 (United States); Kuhn, M. [Digital Equipment Corporation, Hudson, Massachusetts 01749 (United States)

    1999-01-01

    An Al{endash}W-silica integrated circuit interconnect sample was thinned to several {mu}m and scanned across a 200 nm focal spot of a Fresnel zone plate operating at photon energy of 1573 eV. The experiment was performed on beamline 2-ID-B of the Advanced Photon Source, a third-generation synchrotron facility. Thirteen scanned projections of the sample were acquired over the angular range {plus_minus}69.2{degree}. At least 301{times}301 pixels were acquired at each angle with a step size of 77{times}57 nm. A three-dimensional image with an approximate uncertainty of 400 nm was reconstructed from projection data using a standard algorithm. The two layers of the integrated circuit and the presence of the focused ion beam markers on the surface of the sample are clearly shown in the reconstruction. {copyright} {ital 1999 American Institute of Physics.}

  1. Viewing Integrated-Circuit Interconnections By SEM

    Science.gov (United States)

    Lawton, Russel A.; Gauldin, Robert E.; Ruiz, Ronald P.

    1990-01-01

    Back-scattering of energetic electrons reveals hidden metal layers. Experiment shows that with suitable operating adjustments, scanning electron microscopy (SEM) used to look for defects in aluminum interconnections in integrated circuits. Enables monitoring, in situ, of changes in defects caused by changes in temperature. Gives truer picture of defects, as etching can change stress field of metal-and-passivation pattern, causing changes in defects.

  2. Progress in radiation immune thermionic integrated circuits

    International Nuclear Information System (INIS)

    This report describes the results of a program directed at evaluating the thermionic integrated circuit (TIC) technology for applicability to military systems. Previous programs under the sponsorship of the Department of Energy, Office of Basic Energy Sciences, have developed an initial TIC technology base and demonstrated operation in high-temperature and high-radiation environments. The program described in this report has two parts: (1) a technical portion in which experiments and analyses were conducted to refine perceptions of near-term as well as ultimate performance levels of the TIC technology and (2) an applications portion in which the technical conclusions were to be evaluated against potential military applications. This report draws several conclusions that strongly suggest that (1) useful radiation-hard/high-temperature operable integrated circuits can be developed using the TIC technology; (2) because of their ability to survive and operate in hostile environments, a variety of potential military applications have been projected for this technology; and (3) based on the above two conclusions, an aggressive TIC development program should be initiated to provide the designers of future systems with integrated circuits and devices with the unique features of the TICs

  3. Progress in radiation immune thermionic integrated circuits

    Energy Technology Data Exchange (ETDEWEB)

    Lynn, D.K.; McCormick, J.B. (comps.)

    1985-08-01

    This report describes the results of a program directed at evaluating the thermionic integrated circuit (TIC) technology for applicability to military systems. Previous programs under the sponsorship of the Department of Energy, Office of Basic Energy Sciences, have developed an initial TIC technology base and demonstrated operation in high-temperature and high-radiation environments. The program described in this report has two parts: (1) a technical portion in which experiments and analyses were conducted to refine perceptions of near-term as well as ultimate performance levels of the TIC technology and (2) an applications portion in which the technical conclusions were to be evaluated against potential military applications. This report draws several conclusions that strongly suggest that (1) useful radiation-hard/high-temperature operable integrated circuits can be developed using the TIC technology; (2) because of their ability to survive and operate in hostile environments, a variety of potential military applications have been projected for this technology; and (3) based on the above two conclusions, an aggressive TIC development program should be initiated to provide the designers of future systems with integrated circuits and devices with the unique features of the TICs.

  4. Power system with an integrated lubrication circuit

    Energy Technology Data Exchange (ETDEWEB)

    Hoff, Brian D. (East Peoria, IL); Akasam, Sivaprasad (Peoria, IL); Algrain, Marcelo C. (Peoria, IL); Johnson, Kris W. (Washington, IL); Lane, William H. (Chillicothe, IL)

    2009-11-10

    A power system includes an engine having a first lubrication circuit and at least one auxiliary power unit having a second lubrication circuit. The first lubrication circuit is in fluid communication with the second lubrication circuit.

  5. Design of Integrated Circuits Approaching Terahertz Frequencies

    DEFF Research Database (Denmark)

    Yan, Lei

    In this thesis, monolithic microwave integrated circuits(MMICs) are presented for millimeter-wave and submillimeter-wave or terahertz(THz) applications. Millimeter-wave power generation from solid state devices is not only crucial for the emerging high data rate wireless communications but also...... heterodyne receivers with requirements of room temperature operation, low system complexity, and high sensitivity, monolithic integrated Schottky diode technology is chosen for the implementation of submillimeterwave components. The corresponding subharmonic mixer and multiplier for a THz radiometer system...

  6. Sequential circuit design for radiation hardened multiple voltage integrated circuits

    Energy Technology Data Exchange (ETDEWEB)

    Clark, Lawrence T. (Phoenix, AZ); McIver, III, John K. (Albuquerque, NM)

    2009-11-24

    The present invention includes a radiation hardened sequential circuit, such as a bistable circuit, flip-flop or other suitable design that presents substantial immunity to ionizing radiation while simultaneously maintaining a low operating voltage. In one embodiment, the circuit includes a plurality of logic elements that operate on relatively low voltage, and a master and slave latches each having storage elements that operate on a relatively high voltage.

  7. Integrated Circuits for Analog Signal Processing

    CERN Document Server

    2013-01-01

      This book presents theory, design methods and novel applications for integrated circuits for analog signal processing.  The discussion covers a wide variety of active devices, active elements and amplifiers, working in voltage mode, current mode and mixed mode.  This includes voltage operational amplifiers, current operational amplifiers, operational transconductance amplifiers, operational transresistance amplifiers, current conveyors, current differencing transconductance amplifiers, etc.  Design methods and challenges posed by nanometer technology are discussed and applications described, including signal amplification, filtering, data acquisition systems such as neural recording, sensor conditioning such as biomedical implants, actuator conditioning, noise generators, oscillators, mixers, etc.   Presents analysis and synthesis methods to generate all circuit topologies from which the designer can select the best one for the desired application; Includes design guidelines for active devices/elements...

  8. Biquadratic Filter Applications Using a Fully-Differential Active-Only Integrator

    Directory of Open Access Journals (Sweden)

    H. A. Yildiz

    2013-04-01

    Full Text Available A new class of active filters, real active-only filters is described and possible implementation issues of these filters are discussed. To remedy these issues, a fully-differential active-only integrator block built around current controlled current conveyors is presented. The integration frequency of the proposed circuit is adjustable over a wide frequency range. As an application, a real active-only filter based on the classical two-integrator loop topology is presented and designed. The feasibility of this filter in a 0.35µm CMOS process is verified through SPECTRE simulation program in the CADENCE design tool.

  9. Thermoelectricity from wasted heat of integrated circuits

    KAUST Repository

    Fahad, Hossain M.

    2012-05-22

    We demonstrate that waste heat from integrated circuits especially computer microprocessors can be recycled as valuable electricity to power up a portion of the circuitry or other important accessories such as on-chip cooling modules, etc. This gives a positive spin to a negative effect of ever increasing heat dissipation associated with increased power consumption aligned with shrinking down trend of transistor dimension. This concept can also be used as an important vehicle for self-powered systemson- chip. We provide theoretical analysis supported by simulation data followed by experimental verification of on-chip thermoelectricity generation from dissipated (otherwise wasted) heat of a microprocessor.

  10. Diode lasers and photonic integrated circuits

    CERN Document Server

    Coldren, Larry A; Mashanovitch, Milan L

    2011-01-01

    Diode Lasers and Photonic Integrated Circuits, Second Edition provides a comprehensive treatment of optical communication technology, its principles and theory, treating students as well as experienced engineers to an in-depth exploration of this field. Diode lasers are still of significant importance in the areas of optical communication, storage, and sensing. Using the the same well received theoretical foundations of the first edition, the Second Edition now introduces timely updates in the technology and in focus of the book. After 15 years of development in the field, this book wil

  11. Accelerating functional verification of an integrated circuit

    Energy Technology Data Exchange (ETDEWEB)

    Deindl, Michael; Ruedinger, Jeffrey Joseph; Zoellin, Christian G.

    2015-10-27

    Illustrative embodiments include a method, system, and computer program product for accelerating functional verification in simulation testing of an integrated circuit (IC). Using a processor and a memory, a serial operation is replaced with a direct register access operation, wherein the serial operation is configured to perform bit shifting operation using a register in a simulation of the IC. The serial operation is blocked from manipulating the register in the simulation of the IC. Using the register in the simulation of the IC, the direct register access operation is performed in place of the serial operation.

  12. Microwave plasmatrons for giant integrated circuit processing

    Energy Technology Data Exchange (ETDEWEB)

    Petrin, A.B.

    2000-02-01

    A method for calculating the interaction of a powerful microwave with a plane layer of magnetoactive low-pressure plasma under conditions of electron cyclotron resonance is presented. In this paper, the plasma layer is situated between a plane dielectric layer and a plane metal screen. The calculation model contains the microwave energy balance, particle balance, and electron energy balance. The equation that expressed microwave properties of nonuniform magnetoactive plasma is found. The numerical calculations of the microwave-plasma interaction for a one-dimensional model of the problem are considered. Applications of the results for microwave plasmatrons designed for processing giant integrated circuits are suggested.

  13. Application prof iles of integrated circuits in various industry fields

    Institute of Scientific and Technical Information of China (English)

    Hongjing Zhang

    2014-01-01

    Integrated circuits play an increasingly important role in various fields. The aging effects, which lead to robustness problems in integrated circuits, has gained more attention. Therefore, during the design process the robustness problem must already be calculated. Generally, the time-dependent influences such as NBTI (negative bias temperature instability) and HCI (hot carrier injection) contribute to circuit aging problems [1] .

  14. A fully integrated 16 channel digitally trimmed pulse shaping amplifier

    International Nuclear Information System (INIS)

    A fully integrated CMOS pulse shaping amplifier has been developed at LBL. All frequency dependent networks are included on the chip. Provision is made for tuning to compensate for process variations. The overall architecture and details of the circuitry are discussed. Test results are presented

  15. Development, integration and testing of automated triggering circuit for hybrid DC circuit breaker

    International Nuclear Information System (INIS)

    A novel concept of Hybrid DC circuit breaker having combination of mechanical switch and static switch provides arc-less current commutation into the dump resistor during quench in superconducting magnet operation. The triggering of mechanical and static switches in Hybrid DC breaker can be automatized which can effectively reduce the overall current commutation time of hybrid DC circuit breaker and make the operation independent of opening time of mechanical switch. With this view, a dedicated control circuit (auto-triggering circuit) has been developed which can decide the timing and pulse duration for mechanical switch as well as static switch from the operating parameters. This circuit has been tested with dummy parameters and thereafter integrated with the actual test set up of hybrid DC circuit breaker. This paper deals with the conceptual design of the auto-triggering circuit, its control logic and operation. The test results of Hybrid DC circuit breaker using this circuit have also been discussed. (author)

  16. Accurate pattern registration for integrated circuit tomography

    Energy Technology Data Exchange (ETDEWEB)

    Levine, Zachary H.; Grantham, Steven; Neogi, Suneeta; Frigo, Sean P.; McNulty, Ian; Retsch, Cornelia C.; Wang, Yuxin; Lucatorto, Thomas B.

    2001-07-15

    As part of an effort to develop high resolution microtomography for engineered structures, a two-level copper integrated circuit interconnect was imaged using 1.83 keV x rays at 14 angles employing a full-field Fresnel zone plate microscope. A major requirement for high resolution microtomography is the accurate registration of the reference axes in each of the many views needed for a reconstruction. A reconstruction with 100 nm resolution would require registration accuracy of 30 nm or better. This work demonstrates that even images that have strong interference fringes can be used to obtain accurate fiducials through the use of Radon transforms. We show that we are able to locate the coordinates of the rectilinear circuit patterns to 28 nm. The procedure is validated by agreement between an x-ray parallax measurement of 1.41{+-}0.17 {mu}m and a measurement of 1.58{+-}0.08 {mu}m from a scanning electron microscope image of a cross section.

  17. Parallel Jacobi EVD Methods on Integrated Circuits

    Directory of Open Access Journals (Sweden)

    Chi-Chia Sun

    2014-01-01

    Full Text Available Design strategies for parallel iterative algorithms are presented. In order to further study different tradeoff strategies in design criteria for integrated circuits, A 10 × 10 Jacobi Brent-Luk-EVD array with the simplified μ-CORDIC processor is used as an example. The experimental results show that using the μ-CORDIC processor is beneficial for the design criteria as it yields a smaller area, faster overall computation time, and less energy consumption than the regular CORDIC processor. It is worth to notice that the proposed parallel EVD method can be applied to real-time and low-power array signal processing algorithms performing beamforming or DOA estimation.

  18. RD53A Integrated Circuit Specifications

    CERN Document Server

    Garcia-Sciveres, Mauricio

    2015-01-01

    Specifications for the RD53 collaboration’s first engineering wafer run of an integrated circuit (IC) for hybrid pixel detector readout, called RD53A. RD53A is intended to demonstrate in a large format IC the suitability of the technology (including radiation tolerance), the stable low threshold operation, and the high hit and trigger rate capabilities, required for HL-LHC upgrades of ATLAS and CMS. The wafer scale production will permit the experiments to prototype bump bonding assembly with realistic sensors in this new technology and to measure the performance of hybrid assemblies. RD53A is not intended to be a final production IC for use in an experiment, and will contain design variations for testing purposes, making the pixel matrix non-uniform.

  19. Broadband plasmonic absorber for photonic integrated circuits

    CERN Document Server

    Xiong, Xiao; Ren, Xi-Feng; Guo, Guang-Can

    2013-01-01

    The loss of surface plasmon polaritons has long been considered as a fatal shortcoming in information transport. Here we propose a plasmonic absorber utilizing this "shortcoming" to absorb the stray light in photonic integrated circuits (PICs). Based on adiabatic mode evolution, its performance is insensitive to incident wavelength with bandwidth larger than 300nm, and robust against surrounding environment and temperature. Besides, the use of metal enables it to be very compact and beneficial to thermal dissipation. With this 40um-long absorber, the absorption efficiency can be over 99.8% at 1550nm, with both the reflectivity and transmittance of incident light reduced to less than 0.1%. Such device may find various applications in PICs, to eliminate the residual strong pump laser or stray light.

  20. Integrated Reconfigurable High-Voltage Transmitting Circuit for CMUTs

    DEFF Research Database (Denmark)

    Llimos Muntal, Pere; Larsen, Dennis Øland; Jørgensen, Ivan Harald Holger;

    2014-01-01

    -out and measurements are performed on the integrated circuit. The transmitting circuit is reconfigurable externally making it able to drive a wide variety of CMUTs. The transmitting circuit can generate several pulse shapes, pulse voltages up to 100 V, maximum pulse range of 50 V and frequencies up to 5 MHz. The area...

  1. Plug-in integrated/hybrid circuit

    Science.gov (United States)

    Stringer, E. J.

    1974-01-01

    Hybrid circuitry can be installed into standard round bayonet connectors, to eliminate wiring from connector to circuit. Circuits can be connected directly into either section of connector pair, eliminating need for hard wiring to that section.

  2. Silicon Photonics Integrated Circuits for Flexible Optical Systems

    OpenAIRE

    Orlandi, Piero

    2014-01-01

    This dissertation deals with the design and the characterization of novel reconfigurable silicon-on-insulator (SOI) devices to filter and route optical signals on-chip. Design is carried out through circuit simulations based on basic circuit elements (Building Blocks, BBs) in order to prove the feasibility of an approach allowing to move the design of Photonic Integrated Circuits (PICs) toward the system level. CMOS compatibility and large integration scale make SOI one of the most promis...

  3. Model GC1312S Multifunction Integrated Optical Circuit Devices

    Institute of Scientific and Technical Information of China (English)

    2001-01-01

    Model GC1312S multifunction integrated optical circuit device (MIOC) used in inertial-grade interferometric fiber optics gyroscopes (IFOGs) is fabricated by annealing and proton exchange process (APE). The unique feature of the device is the incorporation of the beat detection circuit besides all the features the conventional single Y-branch multifunction integrated optical circuit devices have. The device structure, operation principle and typical characteristics, etc., are briefly presented in this paper.

  4. Topology Optimization of Building Blocks for Photonic Integrated Circuits

    DEFF Research Database (Denmark)

    Jensen, Jakob Søndergaard; Sigmund, Ole

    2005-01-01

    Photonic integrated circuits are likely candidates as high speed replacements for the standard electrical integrated circuits of today. However, in order to obtain a satisfactorily performance many design prob- lems that up until now have resulted in too high losses must be resolved. In this work...... we demonstrate how the method of topology optimization can be used to design a variety of high performance building blocks for the future circuits....

  5. Low-power CMOS fully-folding ADC with a mixed-averaging distributed T/H circuit

    Institute of Scientific and Technical Information of China (English)

    Liu Zhen; Jia Song; Wang Yuan; Ji Lijiu; Zhang Xing

    2009-01-01

    This paper describes an 8-bit 125 Mhzlow-powerCMOS fully-foldinganalog-to-digital converter(ADC).A novel mixed-averaging distributed T/H circuit is proposed to improve the accuracy. Folding circuits are not only used in the fine converter but also in the coarse one and in the bit synchronization block to reduce the number of comparators for low power. This ADC is implemented in 0.5μm CMOS technology and occupies a die area of 2 × 1.5 mm~2. The measured differential nonlinearity and integral nonlinearity are 0.6 LSB/-0.8 LSB and 0.9 LSB/-1.2 LSB, respectively. The ADC exhibits 44.3 dB of signal-to-noise plus distortion ratio and 53.5 dB of spurious-free dynamic range for 1 MHz input sine-wave. The power dissipation is 138 mW at a sampling rate of 125 MHz at a 5 V supply.

  6. Securing Health Sensing Using Integrated Circuit Metric

    Directory of Open Access Journals (Sweden)

    Ruhma Tahir

    2015-10-01

    Full Text Available Convergence of technologies from several domains of computing and healthcare have aided in the creation of devices that can help health professionals in monitoring their patients remotely. An increase in networked healthcare devices has resulted in incidents related to data theft, medical identity theft and insurance fraud. In this paper, we discuss the design and implementation of a secure lightweight wearable health sensing system. The proposed system is based on an emerging security technology called Integrated Circuit Metric (ICMetric that extracts the inherent features of a device to generate a unique device identification. In this paper, we provide details of how the physical characteristics of a health sensor can be used for the generation of hardware “fingerprints”. The obtained fingerprints are used to deliver security services like authentication, confidentiality, secure admission and symmetric key generation. The generated symmetric key is used to securely communicate the health records and data of the patient. Based on experimental results and the security analysis of the proposed scheme, it is apparent that the proposed system enables high levels of security for health monitoring in resource optimized manner.

  7. Securing health sensing using integrated circuit metric.

    Science.gov (United States)

    Tahir, Ruhma; Tahir, Hasan; McDonald-Maier, Klaus

    2015-10-20

    Convergence of technologies from several domains of computing and healthcare have aided in the creation of devices that can help health professionals in monitoring their patients remotely. An increase in networked healthcare devices has resulted in incidents related to data theft, medical identity theft and insurance fraud. In this paper, we discuss the design and implementation of a secure lightweight wearable health sensing system. The proposed system is based on an emerging security technology called Integrated Circuit Metric (ICMetric) that extracts the inherent features of a device to generate a unique device identification. In this paper, we provide details of how the physical characteristics of a health sensor can be used for the generation of hardware "fingerprints". The obtained fingerprints are used to deliver security services like authentication, confidentiality, secure admission and symmetric key generation. The generated symmetric key is used to securely communicate the health records and data of the patient. Based on experimental results and the security analysis of the proposed scheme, it is apparent that the proposed system enables high levels of security for health monitoring in resource optimized manner.

  8. Designing TSVs for 3D Integrated Circuits

    CERN Document Server

    Khan, Nauman

    2013-01-01

    This book explores the challenges and presents best strategies for designing Through-Silicon Vias (TSVs) for 3D integrated circuits.  It describes a novel technique to mitigate TSV-induced noise, the GND Plug, which is superior to others adapted from 2-D planar technologies, such as a backside ground plane and traditional substrate contacts. The book also investigates, in the form of a comparative study, the impact of TSV size and granularity, spacing of C4 connectors, off-chip power delivery network, shared and dedicated TSVs, and coaxial TSVs on the quality of power delivery in 3-D ICs. The authors provide detailed best design practices for designing 3-D power delivery networks.  Since TSVs occupy silicon real-estate and impact device density, this book provides four iterative algorithms to minimize the number of TSVs in a power delivery network. Unlike other existing methods, these algorithms can be applied in early design stages when only functional block- level behaviors and a floorplan are available....

  9. Counterfeit integrated circuits detection and avoidance

    CERN Document Server

    Tehranipoor, Mark (Mohammad); Forte, Domenic

    2015-01-01

    This timely and exhaustive study offers a much-needed examination of the scope and consequences of the electronic counterfeit trade.  The authors describe a variety of shortcomings and vulnerabilities in the electronic component supply chain, which can result in counterfeit integrated circuits (ICs).  Not only does this book provide an assessment of the current counterfeiting problems facing both the public and private sectors, it also offers practical, real-world solutions for combatting this substantial threat.   ·      Helps beginners and practitioners in the field by providing a comprehensive background on the counterfeiting problem; ·      Presents innovative taxonomies for counterfeit types, test methods, and counterfeit defects, which allows for a detailed analysis of counterfeiting and its mitigation; ·      Provides step-by-step solutions for detecting different types of counterfeit ICs; ·      Offers pragmatic and practice-oriented, realistic solutions to counterfeit IC d...

  10. F-Paris: integrated electronic circuits [Tender

    CERN Multimedia

    2003-01-01

    "Fourniture, montage et tests des circuits imprimes et modules multi composants pour le trajectographe central de CMS. Maximum de 12 000 circuits imprimes et modules multi-composants necessaires au trajectographe central de l'experience CMS aupres du Large Hadron Collider" (1 page).

  11. Design of 3D integrated circuits and systems

    CERN Document Server

    Sharma, Rohit

    2014-01-01

    Three-dimensional (3D) integration of microsystems and subsystems has become essential to the future of semiconductor technology development. 3D integration requires a greater understanding of several interconnected systems stacked over each other. While this vertical growth profoundly increases the system functionality, it also exponentially increases the design complexity. Design of 3D Integrated Circuits and Systems tackles all aspects of 3D integration, including 3D circuit and system design, new processes and simulation techniques, alternative communication schemes for 3D circuits and sys

  12. Integrated differential high-voltage transmitting circuit for CMUTs

    DEFF Research Database (Denmark)

    Llimos Muntal, Pere; Larsen, Dennis Øland; Farch, Kjartan;

    2015-01-01

    In this paper an integrated differential high-voltage transmitting circuit for capacitive micromachined ultrasonic transducers (CMUTs) used in portable ultrasound scanners is designed and implemented in a 0.35 μm high-voltage process. Measurements are performed on the integrated circuit in order...... to assess its performance. The circuit generates pulses at differential voltage levels of 60V, 80V and 100 V, a frequency up to 5MHz and a measured driving strength of 1.75 V/ns with the CMUT connected. The total on-chip area occupied by the transmitting circuit is 0.18 mm2 and the power consumption...

  13. A fully integrated 3.5 GHz CMOS differential power amplifier driver

    International Nuclear Information System (INIS)

    A fully integrated CMOS differential power amplifier driver (PAD) is proposed for WiMAX applications. In order to fulfill the differential application requirements, a transmission line transformer is used as the output matching network. A differential inductance constitutes an inter-stage matching network. Meanwhile, an on chip balun realizes input matching as well as single-end to differential conversion. The PAD is fabricated in a 0.13 μm RFCMOS process. The chip size is 1.1 × 1.1 mm2 with all of the matching network integrated on chip. The saturated power is around 10 dBm and power gain is about 12 dB. (semiconductor integrated circuits)

  14. An approach towards fully integration of CAD and CAM technologies

    Directory of Open Access Journals (Sweden)

    M. Tolouei-Rad

    2006-08-01

    Full Text Available Purpose: An integrated CAD/CAM system for milling operations has been developed which helps designers tosolve machining problems at the design stage.Design/methodology/approach: A methodology has been employed which provides all necessary informationfor machining products automatically. Use of these system results in reduced machining leadtimes and costthrough designing machinable components; using available cutting tools; improving machining efficiency. Thesystem is menu driven with a user friendly interface.Findings: Different components for developing such a system have been identified and various problems thatarose in the development of this system have been dealt with The system developed leads to an adequate basisfor fully integration of CAD and CAM technologies in one system. It allows simultaneous generation of allinformation required to satisfy machining requirements of the design such as its machinability and availabilityof the required tooling resources.Research limitations/implications: Different components required for developing such systems have beenidentified and various problems that arose in the development of these systems have been dealt with, leadingto an adequate basis for complete integration of CAD and CAM technologies. Although much of the workdescribed here goes beyond the scope of published literature, however, it should be noted that the systemdeveloped couldn’t be considered as a complete solution to the CAD/CAM integration problem. Further workrequires including other manufacturing activities that are considered in concurrent engineering concept. In thisdirection, further integration of the system developed with systems such as MRP, MRP II and assembly sequenceplanning packages are highly desirable.Originality/value: CAD/CAM integration is regarded as a solution for bridging the gap between design andmanufacturing, one of the ultimate goals for concurrent engineering. Since the advent of CAD and CAMnumerous

  15. Fully integrated aerodynamic/dynamic optimization of helicopter rotor blades

    Science.gov (United States)

    Walsh, Joanne L.; Lamarsh, William J., II; Adelman, Howard M.

    1992-01-01

    A fully integrated aerodynamic/dynamic optimization procedure is described for helicopter rotor blades. The procedure combines performance and dynamic analyses with a general purpose optimizer. The procedure minimizes a linear combination of power required (in hover, forward flight, and maneuver) and vibratory hub shear. The design variables include pretwist, taper initiation, taper ratio, root chord, blade stiffnesses, tuning masses, and tuning mass locations. Aerodynamic constraints consist of limits on power required in hover, forward flight and maneuvers; airfoil section stall; drag divergence Mach number; minimum tip chord; and trim. Dynamic constraints are on frequencies, minimum autorotational inertia, and maximum blade weight. The procedure is demonstrated for two cases. In the first case, the objective function involves power required (in hover, forward flight and maneuver) and dynamics. The second case involves only hover power and dynamics. The designs from the integrated procedure are compared with designs from a sequential optimization approach in which the blade is first optimized for performance and then for dynamics. In both cases, the integrated approach is superior.

  16. Radiation-hardened transistor and integrated circuit

    Energy Technology Data Exchange (ETDEWEB)

    Ma, Kwok K. (Albuquerque, NM)

    2007-11-20

    A composite transistor is disclosed for use in radiation hardening a CMOS IC formed on an SOI or bulk semiconductor substrate. The composite transistor has a circuit transistor and a blocking transistor connected in series with a common gate connection. A body terminal of the blocking transistor is connected only to a source terminal thereof, and to no other connection point. The blocking transistor acts to prevent a single-event transient (SET) occurring in the circuit transistor from being coupled outside the composite transistor. Similarly, when a SET occurs in the blocking transistor, the circuit transistor prevents the SET from being coupled outside the composite transistor. N-type and P-type composite transistors can be used for each and every transistor in the CMOS IC to radiation harden the IC, and can be used to form inverters and transmission gates which are the building blocks of CMOS ICs.

  17. Superconducting single photon detectors integrated with diamond nanophotonic circuits

    CERN Document Server

    Rath, Patrik; Ferrari, Simone; Sproll, Fabian; Lewes-Malandrakis, Georgia; Brink, Dietmar; Ilin, Konstantin; Siegel, Michael; Nebel, Christoph; Pernice, Wolfram

    2015-01-01

    Photonic quantum technologies promise to repeat the success of integrated nanophotonic circuits in non-classical applications. Using linear optical elements, quantum optical computations can be performed with integrated optical circuits and thus allow for overcoming existing limitations in terms of scalability. Besides passive optical devices for realizing photonic quantum gates, active elements such as single photon sources and single photon detectors are essential ingredients for future optical quantum circuits. Material systems which allow for the monolithic integration of all components are particularly attractive, including III-V semiconductors, silicon and also diamond. Here we demonstrate nanophotonic integrated circuits made from high quality polycrystalline diamond thin films in combination with on-chip single photon detectors. Using superconducting nanowires coupled evanescently to travelling waves we achieve high detection efficiencies up to 66 % combined with low dark count rates and timing resolu...

  18. On the Behavioral Modeling of Integrated Circuit Output Buffers

    OpenAIRE

    Canavero, Flavio; Stievano, Igor Simone; Maio, Ivano Adolfo

    2003-01-01

    The properties of common behavioral macromodels for single ended CMOS integrated circuits output buffers are discussed with the aim of providing criteria for an effective use of possible modeling options

  19. Vertically integrated circuit development at Fermilab for detectors

    International Nuclear Information System (INIS)

    Today vertically integrated circuits, (a.k.a. 3D integrated circuits) is a popular topic in many trade journals. The many advantages of these circuits have been described such as higher speed due to shorter trace lenghts, the ability to reduce cross talk by placing analog and digital circuits on different levels, higher circuit density without the going to smaller feature sizes, lower interconnect capacitance leading to lower power, reduced chip size, and different processing for the various layers to optimize performance. There are some added advantages specifically for MAPS (Monolithic Active Pixel Sensors) in High Energy Physics: four side buttable pixel arrays, 100% diode fill factor, the ability to move PMOS transistors out of the diode sensing layer, and a increase in channel density. Fermilab began investigating 3D circuits in 2006. Many different bonding processes have been described for fabricating 3D circuits [1]. Fermilab has used three different processes to fabricate several circuits for specific applications in High Energy Physics and X-ray imaging. This paper covers some of the early 3D work at Fermilab and then moves to more recent activities. The major processes we have used are discussed and some of the problems encountered are described. An overview of pertinent 3D circuit designs is presented along with test results thus far.

  20. A fully integrated IQ-receiver for NMR microscopy

    Science.gov (United States)

    Anders, Jens; SanGiorgio, Paul; Boero, Giovanni

    2011-03-01

    We present a fully integrated CMOS receiver for micro-magnetic resonance imaging together with a custom-made micro-gradient system. The receiver is designed for an operating frequency of 300 MHz. The chip consists of an on-chip detection coil and tuning capacitor as well as a low-noise amplifier and a quadrature downconversion mixer with corresponding low-frequency amplification stages. The design is realized in a 0.13 μm CMOS technology, it occupies a chip area of 950 × 800 μm 2 and it draws 50 mA from a supply voltage of 1.8 V. The achieved time-domain spin sensitivity is 5 × 10 14spins/ √{Hz}. Images of phantoms obtained in our custom-made gradient system with 8 μm isotropic resolution are reported.

  1. A fully integrated standalone portable cavity ringdown breath acetone analyzer

    Science.gov (United States)

    Sun, Meixiu; Jiang, Chenyu; Gong, Zhiyong; Zhao, Xiaomeng; Chen, Zhuying; Wang, Zhennan; Kang, Meiling; Li, Yingxin; Wang, Chuji

    2015-09-01

    Breath analysis is a promising new technique for nonintrusive disease diagnosis and metabolic status monitoring. One challenging issue in using a breath biomarker for potential particular disease screening is to find a quantitative relationship between the concentration of the breath biomarker and clinical diagnostic parameters of the specific disease. In order to address this issue, we need a new instrument that is capable of conducting real-time, online breath analysis with high data throughput, so that a large scale of clinical test (more subjects) can be achieved in a short period of time. In this work, we report a fully integrated, standalone, portable analyzer based on the cavity ringdown spectroscopy technique for near-real time, online breath acetone measurements. The performance of the portable analyzer in measurements of breath acetone was interrogated and validated by using the certificated gas chromatography-mass spectrometry. The results show that this new analyzer is useful for reliable online (online introduction of a breath sample without pre-treatment) breath acetone analysis with high sensitivity (57 ppb) and high data throughput (one data per second). Subsequently, the validated breath analyzer was employed for acetone measurements in 119 human subjects under various situations. The instrument design, packaging, specifications, and future improvements were also described. From an optical ringdown cavity operated by the lab-set electronics reported previously to this fully integrated standalone new instrument, we have enabled a new scientific tool suited for large scales of breath acetone analysis and created an instrument platform that can even be adopted for study of other breath biomarkers by using different lasers and ringdown mirrors covering corresponding spectral fingerprints.

  2. Providing Reliability of Physical Systems: Fully Delay Testable Logical Circuit Design with Compact Representation of all PDF Test Pairs

    Science.gov (United States)

    Matrosova, A. Yu.; Mitrofanov, E. V.; Akhynova, D. I.

    2016-01-01

    Functional reliability is one of the important properties of physical systems provided by reliability of system components, in particular, control logical components. The new approach to fully delay testable circuit design oriented to cut overheads and lengths of circuit paths has been developed. Compact representation of all PDF test pairs is reduced to keeping the corresponding generative vector pairs. The number of generative vector pairs does not exceed the doubled number of internal ROBDD nodes originating from the circuit, while the number of the circuit paths can exponentially depend on the number of these internal nodes. The algorithm of involving the PDF test pair from the proper generative vector pair is suggested. This procedure does not require essential calculations. The algorithm of deriving the generative vector pair has a polynomial complexity.

  3. Optical integrated circuits and networks on microscale/nanoscale

    Science.gov (United States)

    Lee, El-Hang; Lee, S. G.; O, B. H.; Park, S. G.; Kim, K. H.; Song, S. H.

    2007-02-01

    We present an overview of our work on the design and fabrication of micro/nano-scale photonic circuits and networks on what we call "optical printed circuit boards" (O-PCBs) and "VLSI photonic integrated circuit chips"(VLSI-PICs) of generic and application-specific nature. The O-PCBs and photonic chips consist of 2-dimensional planar arrays of optical wires, circuits, and networks of micro/nano-scale to perform the functions of sensing, storing, transporting, processing, switching, routing, and distributing optical signals on flat boards or chips. We describe and discuss scientific and technological issues concerning the miniaturization, interconnection and integration of micro/nano-scale photonic devices, circuits, and networks leading to small and very large scale integration in terms of photonic scaling rules and discuss their use for the design and fabrication of the photonic integrated circuits and networks. Design rules for the miniaturization and integration of the micro/nano-photonic systems are discussed in comparison with those of the micro/nano-electronic systems. Materials include polymer/organic materials and silicon materials. Structural bases include photonic crystals, ring resonators, and plasmonic structures. Compatibility issues between diverse materials and devices are discussed especially in regard to applications. Recent progresses and examples are presented.

  4. Innovative devices for integrated circuits - A design perspective

    Science.gov (United States)

    Schmitt-Landsiedel, D.; Werner, C.

    2009-04-01

    MOS devices go 3D, new quantum effect devices appear in the research labs. This paper discusses the impact of various innovative device architectures on circuit design. Examples of circuits with FinFETs or Multi-Gate-FETs are shown and their performance is compared with classically scaled CMOS circuits both for digital and analog applications. As an example for novel quantum effect devices beyond CMOS we discuss circuits with Tunneling Field Effect Transistors and their combination with classical MOSFETs and MuGFETs. Finally the potential of more substantial paradigm changes in circuit design will be exploited for the example of magnetic quantum cellular automata using a novel integrated magnetic field clocking scheme.

  5. Study of CMOS integrated signal processing circuit in capacitive sensors

    Institute of Scientific and Technical Information of China (English)

    CAO Yi-jiang; YU Xiang; WANG Lei

    2007-01-01

    A CMOS integrated signal processing circuit based on capacitance resonance principle whose structure is simple in capacitive sensors is designed. The waveform of output voltage is improved by choosing bootstrap reference current mirror with initiate circuit, CMOS analogy switch and positive feedback of double-stage inverter in the circuit. Output voltage of this circuit is a symmetric square wave signal. The variation of sensitive capacitance, which is part of the capacitive sensors, can be denoted by the change of output voltage's frequency. The whole circuit is designed with 1.5 μm P-well CMOS process and simulated by PSpice software.Output frequency varies from 261.05 kHz to 47.93 kHz if capacitance varies in the range of 1PF~15PF. And the variation of frequency can be easily detected using counter or SCU.

  6. Multi-channel detector readout method and integrated circuit

    Energy Technology Data Exchange (ETDEWEB)

    Moses, William W.; Beuville, Eric; Pedrali-Noy, Marzio

    2004-05-18

    An integrated circuit which provides multi-channel detector readout from a detector array. The circuit receives multiple signals from the elements of a detector array and compares the sampled amplitudes of these signals against a noise-floor threshold and against one another. A digital signal is generated which corresponds to the location of the highest of these signal amplitudes which exceeds the noise floor threshold. The digital signal is received by a multiplexing circuit which outputs an analog signal corresponding the highest of the input signal amplitudes. In addition a digital control section provides for programmatic control of the multiplexer circuit, amplifier gain, amplifier reset, masking selection, and test circuit functionality on each input thereof.

  7. Multi-channel detector readout method and integrated circuit

    Energy Technology Data Exchange (ETDEWEB)

    Moses, William W.; Beuville, Eric; Pedrali-Noy, Marzio

    2006-12-12

    An integrated circuit which provides multi-channel detector readout from a detector array. The circuit receives multiple signals from the elements of a detector array and compares the sampled amplitudes of these signals against a noise-floor threshold and against one another. A digital signal is generated which corresponds to the location of the highest of these signal amplitudes which exceeds the noise floor threshold. The digital signal is received by a multiplexing circuit which outputs an analog signal corresponding the highest of the input signal amplitudes. In addition a digital control section provides for programmatic control of the multiplexer circuit, amplifier gain, amplifier reset, masking selection, and test circuit functionality on each input thereof.

  8. The fully integrated engineer combining technical ability and leadership prowess

    CERN Document Server

    Cerri, Steven T

    2016-01-01

    College teaches you to be a good engineer. But it's likely that your college engineering courses didn't have time to teach you how to effectively contribute your ideas or how to transition to management or leadership. This book provides you with those missing tools. This book addresses the differences between being proficient as a technical individual and effectively contributing to and leading a team to effectively contribute to various projects. The Fully Integrated Engineer: Combining Technical Ability and Leadership Prowess shines a light on how the habits learned in school, while contributing to individual short-term success, actually become hindrances in the modern engineering workplace if your goal is to achieve long-term success as either an engineer, a team lead, manager, or leader. The author offers specific ways to address those limiting habits, turning you into an effective team contributor and leader building toward long-term career succes . The author’s approach to retooling less-than-op...

  9. Science Letters:The Moore's Law for photonic integrated circuits

    Institute of Scientific and Technical Information of China (English)

    THYL(E)N L.; HE Sai-ling; WOSINSKI L.; DAI Dao-xin

    2006-01-01

    We formulate a "Moore's law" for photonic integrated circuits (PICs) and their spatial integration density using two methods. One is decomposing the integrated photonics devices of diverse types into equivalent basic elements, which makes a comparison with the generic elements of electronic integrated circuits more meaningful. The other is making a complex component equivalent to a series of basic elements of the same functionality, which is used to calculate the integration density for functional components realized with different structures. The results serve as a benchmark of the evolution of PICs and we can conclude that the density of integration measured in this way roughly increases by a factor of 2 per year. The prospects for a continued increase of spatial integration density are discussed.

  10. Micro-relay technology for energy-efficient integrated circuits

    CERN Document Server

    Kam, Hei

    2015-01-01

    This book describes the design of relay-based circuit systems from device fabrication to circuit micro-architectures. This book is ideal for both device engineers as well as circuit system designers and highlights the importance of co-design across design hierarchies when optimizing system performance (in this case, energy-efficiency). This book is ideal for researchers and engineers focused on semiconductors, integrated circuits, and energy efficient electronics. This book also: ·         Covers microsystem fabrication, MEMS device design, circuit design, circuit micro-architecture, and CAD ·         Describes work previously done in the field and also lays the groundwork and criteria for future energy-efficient device and system design ·         Maximizes reader insights into the design and modeling of micro-relay, micro-relay reliability, integrated circuit design with micro-relays, and more

  11. Advances in organic field-effect transistors and integrated circuits

    Institute of Scientific and Technical Information of China (English)

    2009-01-01

    Organic field-effect transistors (OFETs) have received significant research interest because of their promising applications in low cast, lager area, plastic circuits, and tremendous progress has been made in materials, device performance, OFETs based circuits in recent years. In this article we introduce the advances in organic semiconductor materials, OFETs based integrating techniques, and in particular highlight the recent progress. Finally, the prospects and problems of OFETs are discussed.

  12. Advances in organic field-effect transistors and integrated circuits

    Institute of Scientific and Technical Information of China (English)

    WANG Hong; JI ZhuoYu; LIU Ming; SHANG LiWei; LIU Ge; LIU XingHua; LIU Jiang; PENG YingQuan

    2009-01-01

    Organic field-effect transistors (OFETs) have received significant research interest because of their promising applications in low cast, lager area, plastic circuits, and tremendous progress has been made in materials, device performance, OFETs based circuits in recent years.In this article we intro-duce the advances in organic semiconductor materials, OFETs based integrating techniques, and in particular highlight the recent progress.Finally, the prospects and problems of OFETs are discussed.

  13. Dielectric isolation for power integrated circuits; Isolation dielectrique enterree pour les circuits integres de puissance

    Energy Technology Data Exchange (ETDEWEB)

    Zerrouk, D.

    1997-07-18

    Considerable efforts have been recently directed towards integrating onto the same chip, sense or protection elements that is low voltage analog and/or digital control circuitry together with high voltage/high current devices. Most of these so called `smart power` devices use either self isolation, junction isolation or Silicon-On-Insulator (SOI) to integrate low voltage elements with vertical power devices. Dielectric isolation is superior to the other isolation techniques such as self isolation or junction isolation. Thesis work consists of the study of the feasibility of a dielectric technology based on the melting and the solidification in a Rapid Thermal Processing furnace (RTP), of thick polysilicon films deposited on oxide. The purpose of this technique is to obtain substrate with localized SOI structures for smart power applications. SOI technology offers significant potential advantages, such as non-occurrence of latch-up in CMOS structures, high packaging density, low parasitic capacitance and the possibility of 3D structures. In addition, SOI technology using thick silicon films (10-100 {mu}m) offers special advantages for high voltage integrated circuits. Several techniques have been developed to form SOI films. Zone melting recrystallization is one of the most promising for localized SOI. The SOI structures have first been analyzed in term of extended defects. N-channel MOSFET`s transistors have also been fabricated in the SOI substrates and electrically characterized (threshold voltages, off-state leakage current, mobilities,...). The SOI transistors exhibit good characteristics, although inferior to witness transistors. The recrystallized silicon films are therefore found to be suitable for the fabrication of SOI devices. (author) 106 refs.

  14. Process Variations and Probabilistic Integrated Circuit Design

    CERN Document Server

    Haase, Joachim

    2012-01-01

    Uncertainty in key parameters within a chip and between different chips in the deep sub micron era plays a more and more important role. As a result, manufacturing process spreads need to be considered during the design process.  Quantitative methodology is needed to ensure faultless functionality, despite existing process variations within given bounds, during product development.   This book presents the technological, physical, and mathematical fundamentals for a design paradigm shift, from a deterministic process to a probability-orientated design process for microelectronic circuits.  Readers will learn to evaluate the different sources of variations in the design flow in order to establish different design variants, while applying appropriate methods and tools to evaluate and optimize their design.  Trains IC designers to recognize problems caused by parameter variations during manufacturing and to choose the best methods available to mitigate these issues during the design process; Offers both qual...

  15. Biochips: The Integrated Circuit of Biology

    DEFF Research Database (Denmark)

    Madsen, Jan

    2012-01-01

    Microfluidic biochips integrate different biochemical analysis functionalities (e.g., dispensers, filters, mixers, separators, detectors) on-chip, miniaturizing the macroscopic chemical and biological processes often processed by lab-robots, to a sub-millimeter scale. These microsystems offer...... the conventional biochemical analyzers, and areable to integrate on-chip all the necessary functions for biochemical analysis. Microfluidic biochips have an immense potential in multiple application areas, such as clinical diagnostics, advanced sequencing, drug discovery, and environmental monitoring, to name...

  16. Silicon integrated circuits advances in materials and device research

    CERN Document Server

    Kahng, Dawon

    1981-01-01

    Silicon Integrated Circuits, Part B covers the special considerations needed to achieve high-power Si-integrated circuits. The book presents articles about the most important operations needed for the high-power circuitry, namely impurity diffusion and oxidation; crystal defects under thermal equilibrium in silicon and the development of high-power device physics; and associated technology. The text also describes the ever-evolving processing technology and the most promising approaches, along with the understanding of processing-related areas of physics and chemistry. Physicists, chemists, an

  17. 3D circuit integration for Vertex and other detectors

    Energy Technology Data Exchange (ETDEWEB)

    Yarema, Ray; /Fermilab

    2007-09-01

    High Energy Physics continues to push the technical boundaries for electronics. There is no area where this is truer than for vertex detectors. Lower mass and power along with higher resolution and radiation tolerance are driving forces. New technologies such as SOI CMOS detectors and three dimensional (3D) integrated circuits offer new opportunities to meet these challenges. The fundamentals for SOI CMOS detectors and 3D integrated circuits are discussed. Examples of each approach for physics applications are presented. Cost issues and ways to reduce development costs are discussed.

  18. Thermally-induced voltage alteration for integrated circuit analysis

    Energy Technology Data Exchange (ETDEWEB)

    Cole, Jr., Edward I. (Albuquerque, NM)

    2000-01-01

    A thermally-induced voltage alteration (TIVA) apparatus and method are disclosed for analyzing an integrated circuit (IC) either from a device side of the IC or through the IC substrate to locate any open-circuit or short-circuit defects therein. The TIVA apparatus uses constant-current biasing of the IC while scanning a focused laser beam over electrical conductors (i.e. a patterned metallization) in the IC to produce localized heating of the conductors. This localized heating produces a thermoelectric potential due to the Seebeck effect in any conductors with open-circuit defects and a resistance change in any conductors with short-circuit defects, both of which alter the power demand by the IC and thereby change the voltage of a source or power supply providing the constant-current biasing. By measuring the change in the supply voltage and the position of the focused and scanned laser beam over time, any open-circuit or short-circuit defects in the IC can be located and imaged. The TIVA apparatus can be formed in part from a scanning optical microscope, and has applications for qualification testing or failure analysis of ICs.

  19. Thermally-induced voltage alteration for integrated circuit analysis

    Energy Technology Data Exchange (ETDEWEB)

    Cole, E.I. Jr.

    2000-06-20

    A thermally-induced voltage alteration (TIVA) apparatus and method are disclosed for analyzing an integrated circuit (IC) either from a device side of the IC or through the IC substrate to locate any open-circuit or short-circuit defects therein. The TIVA apparatus uses constant-current biasing of the IC while scanning a focused laser beam over electrical conductors (i.e. a patterned metallization) in the IC to produce localized heating of the conductors. This localized heating produces a thermoelectric potential due to the Seebeck effect in any conductors with open-circuit defects and a resistance change in any conductors with short-circuit defects, both of which alter the power demand by the IC and thereby change the voltage of a source or power supply providing the constant-current biasing. By measuring the change in the supply voltage and the position of the focused and scanned laser beam over time, any open-circuit or short-circuit defects in the IC can be located and imaged. The TIVA apparatus can be formed in part from a scanning optical microscope, and has applications for qualification testing or failure analysis of ICs.

  20. Integrated CMOS photodetectors and signal processing for very low-level chemical sensing with the bioluminescent bioreporter integrated circuit

    Science.gov (United States)

    Bolton, Eric K.; Sayler, Gary S.; Nivens, David E.; Rochelle, James M.; Ripp, Steven; Simpson, Michael L.

    2002-01-01

    We report an integrated CMOS microluminometer optimized for the detection of low-level bioluminescence as part of the bioluminescent bioreporter integrated circuit (BBIC). This microluminometer improves on previous devices through careful management of the sub-femtoampere currents, both signal and leakage, that flow in the front-end processing circuitry. In particular, the photodiode is operated with a reverse bias of only a few mV, requiring special attention to the reset circuitry of the current-to-frequency converter (CFC) that forms the front-end circuit. We report a sub-femtoampere leakage current and a minimum detectable signal (MDS) of 0.15 fA (1510 s integration time) using a room temperature 1.47 mm2 CMOS photodiode. This microluminometer can detect luminescence from as few as 5000 fully induced Pseudomonas fluorescens 5RL bacterial cells. c2002 Elsevier Science B.V. All rights reserved.

  1. DESIGN OF LOW-VOLTAGE AND LOW-POWER FULLY INTEGRATED FILTER BASED ON LOG-DOMAIN CURRENT-MODE INTEGRATOR

    Institute of Scientific and Technical Information of China (English)

    Li Shutao; Wang Yaonan; Wu Jie

    2001-01-01

    In this paper a novel log-domain current-mode integrator based on MOS transistors in subthreshold is proposed. The integrator's time-constant is tunable by varying a reference bias current. By use of the integrator, a fifth-order Chebyshev lowpass filter with 0.1dB ripples is designed. The simulation results demonstrate that the proposed filter has such advantages as low power supply(1.5V), very low power dissipation (μW level), nearly ideal frequency response, very small sensitivity to components in passband, and adjustable cut-off frequency over a wide range.The circuit is composed of NMOS transistors and grounded capacitors which make it suitable for fully integrated circuit implementation.

  2. Integrated logic circuits using single-atom transistors.

    Science.gov (United States)

    Mol, J A; Verduijn, J; Levine, R D; Remacle, F; Rogge, S

    2011-08-23

    Scaling down the size of computing circuits is about to reach the limitations imposed by the discrete atomic structure of matter. Reducing the power requirements and thereby dissipation of integrated circuits is also essential. New paradigms are needed to sustain the rate of progress that society has become used to. Single-atom transistors, SATs, cascaded in a circuit are proposed as a promising route that is compatible with existing technology. We demonstrate the use of quantum degrees of freedom to perform logic operations in a complementary-metal-oxide-semiconductor device. Each SAT performs multilevel logic by electrically addressing the electronic states of a dopant atom. A single electron transistor decodes the physical multivalued output into the conventional binary output. A robust scalable circuit of two concatenated full adders is reported, where by utilizing charge and quantum degrees of freedom, the functionality of the transistor is pushed far beyond that of a simple switch. PMID:21808050

  3. An improved fully integrated, high-speed, dual-modulus divider

    Science.gov (United States)

    Zheng, Sun; Yong, Xu; Guangyan, Ma; Hui, Shi; Fei, Zhao; Ying, Lin

    2014-11-01

    A fully integrated 2n/2n+1 dual-modulus divider in GHz frequency range is presented. The improved structure can make all separated logic gates embed into correlative D flip—flops completely. In this way, the complex logic functions can be performed with a minimum number of devices and with maximum speed, so that lower power consumption and faster speed are obtained. In addition, the low-voltage bandgap reference needed by the frequency divider is specifically designed to provide a 1.0 V output. According to the design demand, the circuit is fabricated in 0.18 μm standard CMOS process, and the measured results show that its operating frequency range is 1.1-2.5 GHz. The dual-modulus divider dissipates 1.1 mA from a 1.8 V power supply. The temperature coefficient of the reference voltage circuit is 8.3 ppm/°C when the temperature varies from -40 to +125 °C. By comparison, the dual-modulus divide designed in this paper can possess better performance and flexibility.

  4. Printed organic thin-film transistor-based integrated circuits

    International Nuclear Information System (INIS)

    Organic electronics is moving ahead on its journey towards reality. However, this technology will only be possible when it is able to meet specific criteria including flexibility, transparency, disposability and low cost. Printing is one of the conventional techniques to deposit thin films from solution-based ink. It is used worldwide for visual modes of information, and it is now poised to enter into the manufacturing processes of various consumer electronics. The continuous progress made in the field of functional organic semiconductors has achieved high solubility in common solvents as well as high charge carrier mobility, which offers ample opportunity for organic-based printed integrated circuits. In this paper, we present a comprehensive review of all-printed organic thin-film transistor-based integrated circuits, mainly ring oscillators. First, the necessity of all-printed organic integrated circuits is discussed; we consider how the gap between printed electronics and real applications can be bridged. Next, various materials for printed organic integrated circuits are discussed. The features of these circuits and their suitability for electronics using different printing and coating techniques follow. Interconnection technology is equally important to make this product industrially viable; much attention in this review is placed here. For high-frequency operation, channel length should be sufficiently small; this could be achievable with a combination of surface treatment-assisted printing or laser writing. Registration is also an important issue related to printing; the printed gate should be perfectly aligned with the source and drain to minimize parasitic capacitances. All-printed organic inverters and ring oscillators are discussed here, along with their importance. Finally, future applications of all-printed organic integrated circuits are highlighted. (paper)

  5. Fully integrated wearable sensor arrays for multiplexed in situ perspiration analysis

    Science.gov (United States)

    Gao, Wei; Emaminejad, Sam; Nyein, Hnin Yin Yin; Challa, Samyuktha; Chen, Kevin; Peck, Austin; Fahad, Hossain M.; Ota, Hiroki; Shiraki, Hiroshi; Kiriya, Daisuke; Lien, Der-Hsien; Brooks, George A.; Davis, Ronald W.; Javey, Ali

    2016-01-01

    Wearable sensor technologies are essential to the realization of personalized medicine through continuously monitoring an individual’s state of health. Sampling human sweat, which is rich in physiological information, could enable non-invasive monitoring. Previously reported sweat-based and other non-invasive biosensors either can only monitor a single analyte at a time or lack on-site signal processing circuitry and sensor calibration mechanisms for accurate analysis of the physiological state. Given the complexity of sweat secretion, simultaneous and multiplexed screening of target biomarkers is critical and requires full system integration to ensure the accuracy of measurements. Here we present a mechanically flexible and fully integrated (that is, no external analysis is needed) sensor array for multiplexed in situ perspiration analysis, which simultaneously and selectively measures sweat metabolites (such as glucose and lactate) and electrolytes (such as sodium and potassium ions), as well as the skin temperature (to calibrate the response of the sensors). Our work bridges the technological gap between signal transduction, conditioning (amplification and filtering), processing and wireless transmission in wearable biosensors by merging plastic-based sensors that interface with the skin with silicon integrated circuits consolidated on a flexible circuit board for complex signal processing. This application could not have been realized using either of these technologies alone owing to their respective inherent limitations. The wearable system is used to measure the detailed sweat profile of human subjects engaged in prolonged indoor and outdoor physical activities, and to make a real-time assessment of the physiological state of the subjects. This platform enables a wide range of personalized diagnostic and physiological monitoring applications.

  6. The 128-channel fully differential digital integrated neural recording and stimulation interface.

    Science.gov (United States)

    Shahrokhi, Farzaneh; Abdelhalim, Karim; Serletis, Demitre; Carlen, Peter L; Genov, Roman

    2010-06-01

    We present a fully differential 128-channel integrated neural interface. It consists of an array of 8 X 16 low-power low-noise signal-recording and generation circuits for electrical neural activity monitoring and stimulation, respectively. The recording channel has two stages of signal amplification and conditioning with and a fully differential 8-b column-parallel successive approximation (SAR) analog-to-digital converter (ADC). The total measured power consumption of each recording channel, including the SAR ADC, is 15.5 ¿W. The measured input-referred noise is 6.08 ¿ Vrms over a 5-kHz bandwidth, resulting in a noise efficiency factor of 5.6. The stimulation channel performs monophasic or biphasic voltage-mode stimulation, with a maximum stimulation current of 5 mA and a quiescent power dissipation of 51.5 ¿W. The design is implemented in 0.35-¿m complementary metal-oxide semiconductor technology with the channel pitch of 200 ¿m for a total die size of 3.4 mm × 2.5 mm and a total power consumption of 9.33 mW. The neural interface was validated in in vitro recording of a low-Mg(2+)/high-K(+) epileptic seizure model in an intact hippocampus of a mouse. PMID:23853339

  7. Three-dimensional integrated circuit design

    CERN Document Server

    Xie, Yuan; Sapatnekar, Sachin S

    2009-01-01

    This book presents an overview of the field of 3D IC design, with an emphasis on electronic design automation (EDA) tools and algorithms that can enable the adoption of 3D ICs, and the architectural implementation and potential for future 3D system design. The aim of this book is to provide the reader with a complete understanding of: the promise of 3D ICs in building novel systems that enable the chip industry to continue along the path of performance scaling, the state of the art in fabrication technologies for 3D integration, the most prominent 3D-specific EDA challenges, along with solutio

  8. Plasma Etching for Failure Analysis of Integrated Circuit Packages

    NARCIS (Netherlands)

    Tang, J.; Schelen, J.B.J.; Beenakker, C.I.M.

    2011-01-01

    Plastic integrated circuit packages with copper wire bonds are decapsulated by a Microwave Induced Plasma system. Improvements on microwave coupling of the system are achieved by frequency tuning and antenna modification. Plasmas with a mixture of O2 and CF4 showed a high etching rate around 2 mm3/m

  9. Bioluminescent bioreporter integrated circuit devices and methods for detecting ammonia

    Energy Technology Data Exchange (ETDEWEB)

    Simpson, Michael L [Knoxville, TN; Paulus, Michael J [Knoxville, TN; Sayler, Gary S [Blaine, TN; Applegate, Bruce M [West Lafayette, IN; Ripp, Steven A [Knoxville, TN

    2007-04-24

    Monolithic bioelectronic devices for the detection of ammonia includes a microorganism that metabolizes ammonia and which harbors a lux gene fused with a heterologous promoter gene stably incorporated into the chromosome of the microorganism and an Optical Application Specific Integrated Circuit (OASIC). The microorganism is generally a bacterium.

  10. Photonic Integrated Circuits for mmW Systems

    DEFF Research Database (Denmark)

    Vegas Olmos, Juan José; Heck, M. J. R.; Tafur Monroy, Idelfonso

    and carrier frequencies required for high- capacity wireless networks and remote sensing applications. In this paper, we will introduce our e®orts to leverage the advantages of microwave photonics and photonic integrated circuits to de- velop low-cost and ubiquitous wireless technology enabled by silicon...

  11. FUZZY NEURAL NETWORK FOR OBJECT IDENTIFICATION ON INTEGRATED CIRCUIT LAYOUTS

    Directory of Open Access Journals (Sweden)

    A. A. Doudkin

    2015-01-01

    Full Text Available Fuzzy neural network model based on neocognitron is proposed to identify layout objects on images of topological layers of integrated circuits. Testing of the model on images of real chip layouts was showed a highеr degree of identification of the proposed neural network in comparison to base neocognitron.

  12. FUZZY NEURAL NETWORK FOR OBJECT IDENTIFICATION ON INTEGRATED CIRCUIT LAYOUTS

    OpenAIRE

    Doudkin, A. A.

    2016-01-01

    Fuzzy neural network model based on neocognitron is proposed to identify layout objects on images of topological layers of integrated circuits. Testing of the model on images of real chip layouts was showed a highеr degree of identification of the proposed neural network in comparison to base neocognitron.

  13. Classical Conditioning with Pulsed Integrated Neural Networks: Circuits and System

    DEFF Research Database (Denmark)

    Lehmann, Torsten

    1998-01-01

    In this paper we investigate on-chip learning for pulsed, integrated neural networks. We discuss the implementational problems the technology imposes on learning systems and we find that abiologically inspired approach using simple circuit structures is most likely to bring success. We develop a ...... chip to solve simple classical conditioning tasks, thus verifying the design methodologies put forward in the paper....

  14. Digital pixel readout integrated circuit architectures for LWIR

    OpenAIRE

    Shafique, Atia; Yazıcı, Melik; Yazici, Melik; Kayahan, Hüseyin; Kayahan, Huseyin; Ceylan, Ömer; Ceylan, Omer; Gürbüz, Yaşar; Gurbuz, Yasar

    2015-01-01

    This paper presents and discusses digital pixel readout integrated circuit architectures for long wavelength infrared (LWIR) in CMOS technology. Presented architectures are designed for scanning and staring arrays type detectors respectively. For scanning arrays, digital time delay integration (TDI) is implemented on 8 pixels with sampling rate up to 3 using CMOS 180nm technology. Input referred noise of ROIC is below 750 rms electron meanwhile power dissipation is appreciably under 30mW. ROI...

  15. Radio frequency integrated circuit design for cognitive radio systems

    CERN Document Server

    Fahim, Amr

    2015-01-01

    This book fills a disconnect in the literature between Cognitive Radio systems and a detailed account of the circuit implementation and architectures required to implement such systems.  Throughout the book, requirements and constraints imposed by cognitive radio systems are emphasized when discussing the circuit implementation details.  In addition, this book details several novel concepts that advance state-of-the-art cognitive radio systems.  This is a valuable reference for anybody with background in analog and radio frequency (RF) integrated circuit design, needing to learn more about integrated circuits requirements and implementation for cognitive radio systems. ·         Describes in detail cognitive radio systems, as well as the circuit implementation and architectures required to implement them; ·         Serves as an excellent reference to state-of-the-art wideband transceiver design; ·         Emphasizes practical requirements and constraints imposed by cognitive radi...

  16. Flexible circuits with integrated switches for robotic shape sensing

    Science.gov (United States)

    Harnett, C. K.

    2016-05-01

    Digital switches are commonly used for detecting surface contact and limb-position limits in robotics. The typical momentary-contact digital switch is a mechanical device made from metal springs, designed to connect with a rigid printed circuit board (PCB). However, flexible printed circuits are taking over from the rigid PCB in robotics because the circuits can bend while carrying signals and power through moving joints. This project is motivated by a previous work where an array of surface-mount momentary contact switches on a flexible circuit acted as an all-digital shape sensor compatible with the power resources of energy harvesting systems. Without a rigid segment, the smallest commercially-available surface-mount switches would detach from the flexible circuit after several bending cycles, sometimes violently. This report describes a low-cost, conductive fiber based method to integrate electromechanical switches into flexible circuits and other soft, bendable materials. Because the switches are digital (on/off), they differ from commercially-available continuous-valued bend/flex sensors. No amplification or analog-to-digital conversion is needed to read the signal, but the tradeoff is that the digital switches only give a threshold curvature value. Boundary conditions on the edges of the flexible circuit are key to setting the threshold curvature value for switching. This presentation will discuss threshold-setting, size scaling of the design, automation for inserting a digital switch into the flexible circuit fabrication process, and methods for reconstructing a shape from an array of digital switch states.

  17. Modeling of single-event upset in bipolar integrated circuits

    Science.gov (United States)

    Zoutendyk, J. A.

    1983-01-01

    The results of work done on the quantitative characterization of single-event upset (SEU) in bipolar random-access memories (RAMs) have been obtained through computer simulation of SEU in RAM cells that contain circuit models for bipolar transistors. The models include current generators that emulate the charge collected from ion tracks. The computer simulation results are compared with test data obtained from a RAM in a bipolar microprocessor chip. This methodology is applicable to other bipolar integrated circuit constructions in addition to RAM cells.

  18. Digital integrated circuit design using Verilog and SystemVerilog

    CERN Document Server

    Mehler, Ronald W

    2014-01-01

    For those with a basic understanding of digital design, this book teaches the essential skills to design digital integrated circuits using Verilog and the relevant extensions of SystemVerilog. In addition to covering the syntax of Verilog and SystemVerilog, the author provides an appreciation of design challenges and solutions for producing working circuits. The book covers not only the syntax and limitations of HDL coding, but deals extensively with design problems such as partitioning and synchronization, helping you to produce designs that are not only logically correct, but will actually

  19. Quantum dot rolled-up microtube optoelectronic integrated circuit.

    Science.gov (United States)

    Bhowmick, Sishir; Frost, Thomas; Bhattacharya, Pallab

    2013-05-15

    A rolled-up microtube optoelectronic integrated circuit operating as a phototransceiver is demonstrated. The microtube is made of a InGaAs/GaAs strained bilayer with InAs self-organized quantum dots inserted in the GaAs layer. The phototransceiver consists of an optically pumped microtube laser and a microtube photoconductive detector connected by an a-Si/SiO2 waveguide. The loss in the waveguide and responsivity of the entire phototransceiver circuit are 7.96 dB/cm and 34 mA/W, respectively.

  20. Millimeter-wave and terahertz integrated circuit antennas

    Science.gov (United States)

    Rebeiz, Gabriel M.

    1992-11-01

    This paper presents a comprehensive review of integrated circuit antennas suitable for millimeter and terahertz applications. A great deal of research was done on integrated circuit antennas in the last decade and many of the problems associated with electrically thick dielectric substrates, such as substrate modes and poor radiation patterns, have been understood and solved. Several new antennas, such as the integrated horn antenna, the dielectric-filled parabola, the Fresnel plate antenna, the dual-slot antenna, and the log-periodic and spiral antennas on extended hemispherical lenses, have resulted in excellent performance at millimeter-wave frequencies, and are covered in detail in this paper. Also, a review of the efficiency definitions used with planar antennas is given in detail in the appendix.

  1. Multi-Objective Optimization in Physical Synthesis of Integrated Circuits

    CERN Document Server

    A Papa, David

    2013-01-01

    This book introduces techniques that advance the capabilities and strength of modern software tools for physical synthesis, with the ultimate goal to improve the quality of leading-edge semiconductor products.  It provides a comprehensive introduction to physical synthesis and takes the reader methodically from first principles through state-of-the-art optimizations used in cutting edge industrial tools. It explains how to integrate chip optimizations in novel ways to create powerful circuit transformations that help satisfy performance requirements. Broadens the scope of physical synthesis optimization to include accurate transformations operating between the global and local scales; Integrates groups of related transformations to break circular dependencies and increase the number of circuit elements that can be jointly optimized to escape local minima;  Derives several multi-objective optimizations from first observations through complete algorithms and experiments; Describes integrated optimization te...

  2. Development of a viable 3D integrated circuit technology

    Institute of Scientific and Technical Information of China (English)

    陈文新; 高秉强

    2001-01-01

    Three_dimensional integrated circuit technology with transistors stacked on top of one another in multi-layer silicon film has always been a vision in the future technology direction. While the idea is simple, the technique to obtain high performance multi-layer transistors is extraordinarily difficult. Not until recently does such technology become feasible. In this paper, the background and various techniques to form three-dimensional circuits will be reviewed. Recent development of a simple and promising technology to achieve three-dimensional integration using Metal-Induced-Lateral-Crystallization will be described. Preliminary results of 3D inverters will also be provided to demonstrate the viability for 3D integration.

  3. Series-connected substrate-integrated lead-carbon hybrid ultracapacitors with voltage-management circuit

    Indian Academy of Sciences (India)

    A Banerjee; R Srinivasan; A K Shukla

    2015-02-01

    Cell voltage for a fully charged-substrate-integrated lead-carbon hybrid ultracapacitor is about 2.3 V. Therefore, for applications requiring higher DC voltage, several of these ultracapacitors need to be connected in series. However, voltage distribution across each series-connected ultracapacitor tends to be uneven due to tolerance in capacitance and parasitic parallel-resistance values. Accordingly, voltage-management circuit is required to protect constituent ultracapacitors from exceeding their rated voltage. In this study, the design and characterization of the substrate-integrated lead-carbon hybrid ultracapacitor with co-located terminals is discussed. Voltage-management circuit for the ultracapacitor is presented, and its effectiveness is validated experimentally.

  4. Integrated microchannel cooling in a three dimensional integrated circuit: A thermal management

    Directory of Open Access Journals (Sweden)

    Wang Kang-Jia

    2016-01-01

    Full Text Available Microchannel cooling is a promising technology for solving the three-dimensional integrated circuit thermal problems. However, the relationship between the microchannel cooling parameters and thermal behavior of the three dimensional integrated circuit is complex and difficult to understand. In this paper, we perform a detailed evaluation of the influence of the microchannel structure and the parameters of the cooling liquid on steady-state temperature profiles. The results presented in this paper are expected to aid in the development of thermal design guidelines for three dimensional integrated circuit with microchannel cooling.

  5. A fully integrated multi-standard frequency synthesizer for GNSS receivers with cellular network positioning capability

    International Nuclear Information System (INIS)

    A fully integrated hybrid integer/fractional frequency synthesizer is presented. With a single multiband voltage-controlled-oscillator (VCO), the frequency synthesizer can support GPS, Galileo, Compass and TD-SCDMA standards. Design is carefully performed to trade off power, die area and phase noise performance. By reconfiguring between the integer mode and fractional mode, different frequency resolution requirements and a constant loop bandwidth for each standard can be achieved simultaneously. Moreover, a long sequence length, reduced hardware complexity multi-stage-noise-shaping (MASH) Δ−Σ modulator is employed to reduce fractional spur in the fractional mode. Fabricated in a 0.18 μm CMOS technology, the frequency synthesizer occupies an active area of 1.48 mm2 and draws a current of 13.4–16.2 mA from a 1.8 V power supply. The measured phase noise is lower than −80 dBc/Hz at 100 kHz offset and −113 to −124 dBc/Hz at 1 MHz offset respectively, while the measured reference spur is −71 dBc in integer mode and the fractional spur is −65 dBc in fractional mode. (semiconductor integrated circuits)

  6. RF and microwave integrated circuit development technology, packaging and testing

    CERN Document Server

    Gamand, Patrice; Kelma, Christophe

    2017-01-01

    RF and Microwave Integrated Circuit Development bridges the gap between existing literature, which focus mainly on the 'front-end' part of a product development (system, architecture, design techniques), by providing the reader with an insight into the 'back-end' part of product development. In addition, the authors provide practical answers and solutions regarding the choice of technology, the packaging solutions and the effects on the performance on the circuit and to the industrial testing strategy. It will also discuss future trends and challenges and includes case studies to illustrate examples. * Offers an overview of the challenges in RF/microwave product design * Provides practical answers to packaging issues and evaluates its effect on the performance of the circuit * Includes industrial testing strategies * Examines relevant RF MIC technologies and the factors which affect the choice of technology for a particular application, e.g. technical performance and cost * Discusses future trends and challen...

  7. The two independent equations of circuits in integral form of field theory: The fundamental law of circuits

    Institute of Scientific and Technical Information of China (English)

    CHEN; Shennian

    2005-01-01

    Circuit theory is an extremely important basic theory in electrical and electronic sciences and technologies. Over more than a century, researchers have come to the conclusion that a fundamental law of circuits needs to satisfy the following three conditions: (1) Independency. It must be able to solve independently the basic problems of general solutions to the distribution of current and voltage in circuits. (2)Fundamentality. It cannot be derived from circuit theory and it must be the starting point for the establishment of circuit theory; it deduces the problem relevant to circuit theory by using purely logical inference, and establishes circuit theory into an independent deductive system. (3) Applicability. It must be widely applicable to all spheres of circuits,which includes sinusoidal steady-state linear and nonlinear networks, non-sinusoidal steady-state linear and nonlinear networks, transient-state processes, etc. From all networks to which the fundamental law of circuits applies, sinusoidal steady-state linear network is chosen as the most basic one to demonstrate that the two independent equations of circuits in integral form derived from Maxwell equations are able to meet these three conditions. Consequently, it is believed to be the fundamental law of circuits newly recognized today. This paper also makes the initiative to establish a circuit theory by which the basic rules of electromagnetic field govern the circuits, and the unity of electromagnetic fields and circuits is achieved.

  8. Power-Integrated Circuit Active Leakage Current Detector

    Directory of Open Access Journals (Sweden)

    M. F. Bulacio

    2012-01-01

    Full Text Available Most of the failures of induction motors become insulation faults, causing a permanent damage. Using differential current transformers, a system capable of insulation fault detection was developed, based on the differential relay protection scheme. Both signal injection and fault detection circuitry were integrated in a single chip. The proposed scheme is faster than other existing protection and not restricted to protect induction motors, but several other devices (such as IGBTs and systems. This paper explains the principle of operation of fault protection scheme and analyzes an integrated implementation through simulations and experimental results. A power-integrated circuit (PIC implementation is presented.

  9. Attachment method for stacked integrated circuit (IC) chips

    Energy Technology Data Exchange (ETDEWEB)

    Bernhardt, Anthony F. (Berkeley, CA); Malba, Vincent (Livermore, CA)

    1999-01-01

    An attachment method for stacked integrated circuit (IC) chips. The method involves connecting stacked chips, such as DRAM memory chips, to each other and/or to a circuit board. Pads on the individual chips are rerouted to form pads on the side of the chip, after which the chips are stacked on top of each other whereby desired interconnections to other chips or a circuit board can be accomplished via the side-located pads. The pads on the side of a chip are connected to metal lines on a flexible plastic tape (flex) by anisotropically conductive adhesive (ACA). Metal lines on the flex are likewise connected to other pads on chips and/or to pads on a circuit board. In the case of a stack of DRAM chips, pads to corresponding address lines on the various chips may be connected to the same metal line on the flex to form an address bus. This method has the advantage of reducing the number of connections required to be made to the circuit board due to bussing; the flex can accommodate dimensional variation in the alignment of chips in the stack; bonding of the ACA is accomplished at low temperature and is otherwise simpler and less expensive than solder bonding; chips can be bonded to the ACA all at once if the sides of the chips are substantially coplanar, as in the case for stacks of identical chips, such as DRAM.

  10. Attachment method for stacked integrated circuit (IC) chips

    Energy Technology Data Exchange (ETDEWEB)

    Bernhardt, A.F.; Malba, V.

    1999-08-03

    An attachment method for stacked integrated circuit (IC) chips is disclosed. The method involves connecting stacked chips, such as DRAM memory chips, to each other and/or to a circuit board. Pads on the individual chips are rerouted to form pads on the side of the chip, after which the chips are stacked on top of each other whereby desired interconnections to other chips or a circuit board can be accomplished via the side-located pads. The pads on the side of a chip are connected to metal lines on a flexible plastic tape (flex) by anisotropically conductive adhesive (ACA). Metal lines on the flex are likewise connected to other pads on chips and/or to pads on a circuit board. In the case of a stack of DRAM chips, pads to corresponding address lines on the various chips may be connected to the same metal line on the flex to form an address bus. This method has the advantage of reducing the number of connections required to be made to the circuit board due to bussing; the flex can accommodate dimensional variation in the alignment of chips in the stack; bonding of the ACA is accomplished at low temperature and is otherwise simpler and less expensive than solder bonding; chips can be bonded to the ACA all at once if the sides of the chips are substantially coplanar, as in the case for stacks of identical chips, such as DRAM. 12 figs.

  11. Wirelessly powered, fully internal optogenetics for brain, spinal and peripheral circuits in mice.

    Science.gov (United States)

    Montgomery, Kate L; Yeh, Alexander J; Ho, John S; Tsao, Vivien; Mohan Iyer, Shrivats; Grosenick, Logan; Ferenczi, Emily A; Tanabe, Yuji; Deisseroth, Karl; Delp, Scott L; Poon, Ada S Y

    2015-10-01

    To enable sophisticated optogenetic manipulation of neural circuits throughout the nervous system with limited disruption of animal behavior, light-delivery systems beyond fiber optic tethering and large, head-mounted wireless receivers are desirable. We report the development of an easy-to-construct, implantable wireless optogenetic device. Our smallest version (20 mg, 10 mm(3)) is two orders of magnitude smaller than previously reported wireless optogenetic systems, allowing the entire device to be implanted subcutaneously. With a radio-frequency (RF) power source and controller, this implant produces sufficient light power for optogenetic stimulation with minimal tissue heating (optogenetic control throughout the nervous system (brain, spinal cord and peripheral nerve endings) of behaving mice. This technology opens the door for optogenetic experiments in which animals are able to behave naturally with optogenetic manipulation of both central and peripheral targets.

  12. 75 FR 75694 - Certain Semiconductor Integration Circuits Using Tungsten Metallization and Products Containing...

    Science.gov (United States)

    2010-12-06

    ... COMMISSION Certain Semiconductor Integration Circuits Using Tungsten Metallization and Products Containing... United States after importation of certain semiconductor integrated circuits using tungsten metallization... following six respondents ] remained in the investigation: Tower Semiconductor, Ltd. of Israel;...

  13. Radiation Testing and Evaluation Issues for Modern Integrated Circuits

    Science.gov (United States)

    LaBel, Kenneth A.; Cohn, Lew M.

    2005-01-01

    Abstract. Changes in modern integrated circuit (IC) technologies have modified the way we approach and conduct radiation tolerance and testing of electronics. These changes include scaling of geometries, new materials, new packaging technologies, and overall speed and device complexity challenges. In this short course section, we will identify and discuss these issues as they impact radiation testing, modeling, and effects mitigation of modern integrated circuits. The focus will be on CMOS-based technologies, however, other high performance technologies will be discussed where appropriate. The effects of concern will be: Single-Event Effects (SEE) and steady state total ionizing dose (TID) IC response. However, due to the growing use of opto-electronics in space systems issues concerning displacement damage testing will also be considered. This short course section is not intended to provide detailed "how-to-test" information, but simply provide a snapshot of current challenges and some of the approaches being considered.

  14. Total Dose Effects on Bipolar Integrated Circuits at Low Temperature

    Science.gov (United States)

    Johnston, A. H.; Swimm, R. T.; Thorbourn, D. O.

    2012-01-01

    Total dose damage in bipolar integrated circuits is investigated at low temperature, along with the temperature dependence of the electrical parameters of internal transistors. Bandgap narrowing causes the gain of npn transistors to decrease far more at low temperature compared to pnp transistors, due to the large difference in emitter doping concentration. When irradiations are done at temperatures of -140 deg C, no damage occurs until devices are warmed to temperatures above -50 deg C. After warm-up, subsequent cooling shows that damage is then present at low temperature. This can be explained by the very strong temperature dependence of dispersive transport in the continuous-time-random-walk model for hole transport. For linear integrated circuits, low temperature operation is affected by the strong temperature dependence of npn transistors along with the higher sensitivity of lateral and substrate pnp transistors to radiation damage.

  15. Printed Circuit Board Integrated Toroidal Radio Frequency Inductors

    DEFF Research Database (Denmark)

    Kamby, Peter; Knott, Arnold; Andersen, Michael A. E.

    2012-01-01

    implemented as solenoids, either in spiral or cylindrical form. Those have the disadvantage of excessive stray fields, which can cause losses and disturbances in adjacent circuitry. Therefore this paper presents the analysis, design and realization of a printed circuit board (PCB) integrated inductor under...... significant consideration of the losses in the inductor. The analysis results in a general design tool which is verified by a prototype inductor. Its inductance is 50 nH and has a quality of 149 at 100 MHz....

  16. Bioimpedance Measurements Using the Integrated Circuit AD5933

    OpenAIRE

    2008-01-01

    This thesis gives a description of a prototype bioimpedance measurement system based on the integrated circuit AD5933. The prototype operates from 5 - 100 kHz and covers the impedance range 0.1k - 10 M in six subranges. The system is operated from a PC, and the software required for operation and control has been developed. Verification testing on R/C modules have shown that the calibration process and the signal level are critical issues with regard to operationa...

  17. Optimization of Segmentation Quality of Integrated Circuit Images

    Directory of Open Access Journals (Sweden)

    Gintautas Mušketas

    2012-04-01

    Full Text Available The paper presents investigation into the application of genetic algorithms for the segmentation of the active regions of integrated circuit images. This article is dedicated to a theoretical examination of the applied methods (morphological dilation, erosion, hit-and-miss, threshold and describes genetic algorithms, image segmentation as optimization problem. The genetic optimization of the predefined filter sequence parameters is carried out. Improvement to segmentation accuracy using a non optimized filter sequence makes 6%.Artcile in Lithuanian

  18. Plasmonic nanopatch array for optical integrated circuit applications

    OpenAIRE

    Shi-Wei Qu; Zai-Ping Nie

    2013-01-01

    Future plasmonic integrated circuits with the capability of extremely high-speed data processing at optical frequencies will be dominated by the efficient optical emission (excitation) from (of) plasmonic waveguides. Towards this goal, plasmonic nanoantennas, currently a hot topic in the field of plasmonics, have potential to bridge the mismatch between the wave vector of free-space photonics and that of the guided plasmonics. To manipulate light at will, plasmonic nanoantenna arrays will def...

  19. Neural Networks Integrated Circuit for Biomimetics MEMS Microrobot

    OpenAIRE

    Ken Saito; Kazuaki Maezumi; Yuka Naito; Tomohiro Hidaka; Kei Iwata; Yuki Okane; Hirozumi Oku; Minami Takato; Fumio Uchikoba

    2014-01-01

    In this paper, we will propose the neural networks integrated circuit (NNIC) which is the driving waveform generator of the 4.0, 2.7, 2.5 mm, width, length, height in size biomimetics microelectromechanical systems (MEMS) microrobot. The microrobot was made from silicon wafer fabricated by micro fabrication technology. The mechanical system of the robot was equipped with small size rotary type actuators, link mechanisms and six legs to realize the ant-like switching behavior. The NNIC generat...

  20. Experimental study of surface crystallization on integrated circuit chips

    Institute of Scientific and Technical Information of China (English)

    Zhang Xin; Liu Meng-Xin; Gao Yong; Wang Cai-Lin; Wang Zhi-Wei; Zhang Xian

    2006-01-01

    A surface crystallization phenomenon on bonding pads and wires of integrated circuit chip is reported in this paper. Through a lot of experiments, an unknown failure effect caused by mixed crystalline matter is revealed, whereas non-plasma fluorine contamination cannot cause the failure of bonding pads. By experiments combined with infrared spectroscopy analysis, the surface crystallization effect is studied. The conclusion of the study can provide the guidance for IC fabrication, modelling and analysis.

  1. Advances in Developing Transitions in Microwave Integrated Circuits

    Institute of Scientific and Technical Information of China (English)

    ZHANG Yun-chuan; WANG Bing-zhong

    2005-01-01

    Advances in developing transitions in microwave integrated circuits during the last ten years are reviewed. Some typical structures of transition are introduced. Transition structures can be classified into two basic types: one is transition between the same kind of transmission lines on different planes of a common substrate, the other transition between different types of transmission lines.Furthermore, future development of transition structures is discussed.

  2. A fully integrated microbattery for an implantable microelectromechanical system

    Energy Technology Data Exchange (ETDEWEB)

    Albano, F. [Department of Material Science Engineering, University of Michigan, Ann Arbor, MI 48109 (United States); Department of Mechanical Engineering, University of Michigan, Ann Arbor, MI 48109 (United States); Lin, Y.S.; Blaauw, D.; Sylvester, D.M. [Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, MI 48109 (United States); Wise, K.D. [Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, MI 48109 (United States); Department of Biomedical Engineering, University of Michigan, Ann Arbor, MI 48109 (United States); Sastry, A.M. [Department of Material Science Engineering, University of Michigan, Ann Arbor, MI 48109 (United States); Department of Biomedical Engineering, University of Michigan, Ann Arbor, MI 48109 (United States); Department of Mechanical Engineering, University of Michigan, Ann Arbor, MI 48109 (United States)

    2008-12-01

    The Wireless Integrated Microsystems Engineering Research Center's Intraocular Sensor (WIMS-ERC IOS) was studied as a model system for an integrated, autonomous implantable device. In the present study, we had four objectives: (1) select and designing an optimized power supply for the WIMS-IOS; (2) develop a fabrication technique allowing small scale, low-cost, and integrable fabrication for CMOS systems, and experimentally demonstrate a microscopic power source; (3) map capacity and lifetime of several fabricated microbatteries; (4) determine the effects of miniaturization on capacity, lifetime and device architecture. Physical vapor deposition (PVD) was used to deposit thin layers ({<=}1 {mu}m) of metal sequentially onto glass substrates (SiO{sub 2}, as used in the device). To map the influence of size over cell capacity and cycle life, we fabricated and tested five stand-alone cells using a Solartron {sup registered} 1470E battery tester and a Maccor {sup registered} 4000 series tester. A sixth battery was fabricated to investigate the effects of system integration, variable discharge rate and size reduction simultaneously. The highest experimental capacity among the larger cells O(cm{sup 2}) was 100 {mu}Ah, achieved by IOS-C-1 at 250 {mu}A (1.4 C) discharge. Among O(mm{sup 2}) cells, IOS-M-1 achieved the highest capacity (2.75 {mu}Ah, {proportional_to}76% of theoretical) at 2.5 {mu}A discharge (0.7 C rate). (author)

  3. Fully Integrated SAW-Less Discrete-Time Superheterodyne Receiver

    NARCIS (Netherlands)

    Madadi, I.

    2015-01-01

    There are nowadays strong business and technical demands to integrate radio- frequency (RF) receivers (RX) into a complete system-on-chip (SoC) realized in scaled digital processes technology. As a consequence, the RF circuitry has to function well in face of reduced power supply ( V DD ) while the

  4. The integrated circuit IC EMP transient state disturbance effect experiment method investigates

    International Nuclear Information System (INIS)

    Transient state disturbance characteristic study on the integrated circuit, IC, need from its coupling path outset. Through cable (aerial) coupling, EMP converts to an pulse current voltage and results in the impact to the integrated circuit I/O orifice passing the cable. Aiming at the armament system construction feature, EMP effect to the integrated circuit, IC inside the system is analyzed. The integrated circuit, IC EMP effect experiment current injection method is investigated and a few experiments method is given. (authors)

  5. Reconfigurable SDM Switching Using Novel Silicon Photonic Integrated Circuit

    CERN Document Server

    Ding, Yunhong; Dalgaard, Kjeld; Ye, Feihong; Asif, Rameez; Gross, Simon; Withford, Michael J; Galili, Michael; Morioka, Toshio; Oxenlowe, Leif Katsuo

    2016-01-01

    Space division multiplexing using multicore fibers is becoming a more and more promising technology. In space-division multiplexing fiber network, the reconfigurable switch is one of the most critical components in network nodes. In this paper we for the first time demonstrate reconfigurable space-division multiplexing switching using silicon photonic integrated circuit, which is fabricated on a novel silicon-on-insulator platform with buried Al mirror. The silicon photonic integrated circuit is composed of a 7x7 switch and low loss grating coupler array based multicore fiber couplers. Thanks to the Al mirror, grating couplers with ultra-low coupling loss with optical multicore fibers is achieved. The lowest total insertion loss of the silicon integrated circuit is as low as 4.5 dB, with low crosstalk lower than -30 dB. Excellent performances in terms of low insertion loss and low crosstalk are obtained for the whole C-band. 1 Tb/s/core transmission over a 2-km 7-core fiber and space-division multiplexing swi...

  6. A Integrated Circuit for a Biomedical Capacitive Pressure Transducer

    Science.gov (United States)

    Smith, Michael John Sebastian

    Medical research has an urgent need for a small, accurate, stable, low-power, biocompatible and inexpensive pressure sensor with a zero to full-scale range of 0-300 mmHg. An integrated circuit (IC) for use with a capacitive pressure transducer was designed, built and tested. The random pressure measurement error due to resolution and non-linearity is (+OR-)0.4 mmHg (at mid-range with a full -scale of 300 mmHg). The long-term systematic error due to falling battery voltage is (+OR-)0.6 mmHg. These figures were calculated from measurements of temperature, supply dependence and non-linearity on completed integrated circuits. The sensor IC allows measurement of temperature to (+OR-)0.1(DEGREES)C to allow for temperature compensation of the transducer. Novel micropower circuit design of the system components enabled these levels of accuracy to be reached. Capacitance is measured by a new ratiometric scheme employing an on -chip reference capacitor. This method greatly reduces the effects of voltage supply, temperature and manufacturing variations on the sensor circuit performance. The limits on performance of the bandgap reference circuit fabricated with a standard bipolar process using ion-implanted resistors were determined. Measurements confirm the limits of temperature stability as approximately (+OR-)300 ppm/(DEGREES)C. An exact analytical expression for the period of the Schmitt trigger oscillator, accounting for non-constant capacitor charging current, was formulated. Experiments to test agreement with theory showed that prediction of the oscillator period was very accurate. The interaction of fundamental and practical limits on the scaling of the transducer size was investigated including a correction to previous theoretical analysis of jitter in an RC oscillator. An areal reduction of 4 times should be achievable.

  7. Flexible packaging of solid-state integrated circuit chips with elastomeric microfluidics

    Science.gov (United States)

    Zhang, Bowei; Dong, Quan; Korman, Can E.; Li, Zhenyu; Zaghloul, Mona E.

    2013-01-01

    A flexible technology is proposed to integrate smart electronics and microfluidics all embedded in an elastomer package. The microfluidic channels are used to deliver both liquid samples and liquid metals to the integrated circuits (ICs). The liquid metals are used to realize electrical interconnects to the IC chip. This avoids the traditional IC packaging challenges, such as wire-bonding and flip-chip bonding, which are not compatible with current microfluidic technologies. As a demonstration we integrated a CMOS magnetic sensor chip and associate microfluidic channels on a polydimethylsiloxane (PDMS) substrate that allows precise delivery of small liquid samples to the sensor. Furthermore, the packaged system is fully functional under bending curvature radius of one centimetre and uniaxial strain of 15%. The flexible integration of solid-state ICs with microfluidics enables compact flexible electronic and lab-on-a-chip systems, which hold great potential for wearable health monitoring, point-of-care diagnostics and environmental sensing among many other applications.

  8. An approach towards fully integration of CAD and CAM technologies

    OpenAIRE

    M. Tolouei-Rad

    2006-01-01

    Purpose: An integrated CAD/CAM system for milling operations has been developed which helps designers tosolve machining problems at the design stage.Design/methodology/approach: A methodology has been employed which provides all necessary informationfor machining products automatically. Use of these system results in reduced machining leadtimes and costthrough designing machinable components; using available cutting tools; improving machining efficiency. Thesystem is menu driven with a user f...

  9. ERP Systems - Fully Integrated Solution or a Transactional Platform?

    OpenAIRE

    Sandberg, Johan

    2008-01-01

    This paper addresses the question of how to make use of Enterprise Resource Planning (ERP) systems in companies in the process industry were there is a pervasive need of process standardization. ERP systems have the potential to contribute with standardization and integration of organizational data through an of-the-shelf solution. In practice results of ERP systems implementation has varied greatly. Considering their implications on business processes and the complexity of the systems this s...

  10. Diamond electro-optomechanical resonators integrated in nanophotonic circuits

    CERN Document Server

    Rath, P; Diewald, S; Lewes-Malandrakis, G; Brink, D; Heidrich, N; Nebel, C; Pernice, W H P

    2014-01-01

    Diamond integrated photonic devices are promising candidates for emerging applications in nanophotonics and quantum optics. Here we demonstrate active modulation of diamond nanophotonic circuits by exploiting mechanical degrees of freedom in free-standing diamond electro-optomechanical resonators. We obtain high quality factors up to 9600, allowing us to read out the driven nanomechanical response with integrated optical interferometers with high sensitivity. We are able to excite higher order mechanical modes up to 115 MHz and observe the nanomechanical response also under ambient conditions.

  11. Photonic-integrated circuit for continuous-wave THz generation.

    Science.gov (United States)

    Theurer, Michael; Göbel, Thorsten; Stanze, Dennis; Troppenz, Ute; Soares, Francisco; Grote, Norbert; Schell, Martin

    2013-10-01

    We demonstrate a photonic-integrated circuit for continuous-wave (cw) terahertz (THz) generation. By comprising two lasers and an optical phase modulator on a single chip, the full control of the THz signal is enabled via a unique bidirectional operation technique. Integrated heaters allow for continuous tuning of the THz frequency over 570 GHz. Applied to a coherent cw THz photomixing system operated at 1.5 μm optical wavelength, we reach a signal-to-noise ratio of 44 dB at 1.25 THz, which is identical to the performance of a standard system based on discrete components.

  12. Neuromorphic opto-electronic integrated circuits for optical signal processing

    Science.gov (United States)

    Romeira, B.; Javaloyes, J.; Balle, S.; Piro, O.; Avó, R.; Figueiredo, J. M. L.

    2014-08-01

    The ability to produce narrow optical pulses has been extensively investigated in laser systems with promising applications in photonics such as clock recovery, pulse reshaping, and recently in photonics artificial neural networks using spiking signal processing. Here, we investigate a neuromorphic opto-electronic integrated circuit (NOEIC) comprising a semiconductor laser driven by a resonant tunneling diode (RTD) photo-detector operating at telecommunication (1550 nm) wavelengths capable of excitable spiking signal generation in response to optical and electrical control signals. The RTD-NOEIC mimics biologically inspired neuronal phenomena and possesses high-speed response and potential for monolithic integration for optical signal processing applications.

  13. Arbitrary modeling of TSVs for 3D integrated circuits

    CERN Document Server

    Salah, Khaled; El-Rouby, Alaa

    2014-01-01

    This book presents a wide-band and technology independent, SPICE-compatible RLC model for through-silicon vias (TSVs) in 3D integrated circuits. This model accounts for a variety of effects, including skin effect, depletion capacitance and nearby contact effects. Readers will benefit from in-depth coverage of concepts and technology such as 3D integration, Macro modeling, dimensional analysis and compact modeling, as well as closed form equations for the through silicon via parasitics. Concepts covered are demonstrated by using TSVs in applications such as a spiral inductor?and inductive-based

  14. Fully integrated safeguards and security for reprocessing plant monitoring.

    Energy Technology Data Exchange (ETDEWEB)

    Duran, Felicia Angelica; Ward, Rebecca; Cipiti, Benjamin B.; Middleton, Bobby D.

    2011-10-01

    Nuclear fuel reprocessing plants contain a wealth of plant monitoring data including material measurements, process monitoring, administrative procedures, and physical protection elements. Future facilities are moving in the direction of highly-integrated plant monitoring systems that make efficient use of the plant data to improve monitoring and reduce costs. The Separations and Safeguards Performance Model (SSPM) is an analysis tool that is used for modeling advanced monitoring systems and to determine system response under diversion scenarios. This report both describes the architecture for such a future monitoring system and present results under various diversion scenarios. Improvements made in the past year include the development of statistical tests for detecting material loss, the integration of material balance alarms to improve physical protection, and the integration of administrative procedures. The SSPM has been used to demonstrate how advanced instrumentation (as developed in the Material Protection, Accounting, and Control Technologies campaign) can benefit the overall safeguards system as well as how all instrumentation is tied into the physical protection system. This concept has the potential to greatly improve the probability of detection for both abrupt and protracted diversion of nuclear material.

  15. Fully Integrated Hydrocarbon Reservoir Studies: Myth or Reality?

    Directory of Open Access Journals (Sweden)

    Christoforos Benetatos

    2010-01-01

    Full Text Available Problem statement: In the petroleum industry and especially during reservoir studies, data coming from different disciplines must be combined in order to generate a model that is representative of the reservoir being studied and can be used for defining the most viable development strategy of the field from both an economic and technical standpoint. Each of these disciplines represents an independent piece of a puzzle that is solved by professionals from various scientific fields who have different educational backgrounds. Integration among geophysics, geology, fluid dynamics and geomechanics is truly essential, but requires specific approaches and procedures for generating and calibrating a reservoir model capable of dealing with all and each of these aspects. Approach: Independent workflows were examined for each of the disciplines involved so as to highlight unavoidable interdependencies between static, dynamic and geomechanical models, even when the goal is to tackle each issue separately. Then, the traditional working method was compared to the integrated approach that supports the generation and calibration of models based on data and interpretation results from all the disciplines involved in the entire project. Results: The construction of a reservoir model should be regarded as a dynamic process, subject to repeated updates as new data is made available and by frequent modifications when inconsistencies are found between the understanding that different specialists have of the same system. This approach has exhibited great advantages in terms of improvement in the quality and flexibility of the model, reduction of working time and generation of a single final model that can be adapted or used for any kind of simulation problem. Conclusion: An integrated approach is necessary for reservoir modeling purposes. Modern reservoir studies should be designed accordingly to permit the full integration of static, dynamic and geomechanical data

  16. Universal discrete Fourier optics RF photonic integrated circuit architecture.

    Science.gov (United States)

    Hall, Trevor J; Hasan, Mehedi

    2016-04-01

    This paper describes a coherent electro-optic circuit architecture that generates a frequency comb consisting of N spatially separated orders using a generalised Mach-Zenhder interferometer (MZI) with its N × 1 combiner replaced by an optical N × N Discrete Fourier Transform (DFT). Advantage may be taken of the tight optical path-length control, component and circuit symmetries and emerging trimming algorithms offered by photonic integration in any platform that offers linear electro-optic phase modulation such as LiNbO3, silicon, III-V or hybrid technology. The circuit architecture subsumes all MZI-based RF photonic circuit architectures in the prior art given an appropriate choice of output port(s) and dimension N although the principal application envisaged is phase correlated subcarrier generation for all optical orthogonal frequency division multiplexing. A transfer matrix approach is used to model the operation of the architecture. The predictions of the model are validated by simulations performed using an industry standard software tool. Implementation is found to be practical. PMID:27137048

  17. Universal discrete Fourier optics RF photonic integrated circuit architecture.

    Science.gov (United States)

    Hall, Trevor J; Hasan, Mehedi

    2016-04-01

    This paper describes a coherent electro-optic circuit architecture that generates a frequency comb consisting of N spatially separated orders using a generalised Mach-Zenhder interferometer (MZI) with its N × 1 combiner replaced by an optical N × N Discrete Fourier Transform (DFT). Advantage may be taken of the tight optical path-length control, component and circuit symmetries and emerging trimming algorithms offered by photonic integration in any platform that offers linear electro-optic phase modulation such as LiNbO3, silicon, III-V or hybrid technology. The circuit architecture subsumes all MZI-based RF photonic circuit architectures in the prior art given an appropriate choice of output port(s) and dimension N although the principal application envisaged is phase correlated subcarrier generation for all optical orthogonal frequency division multiplexing. A transfer matrix approach is used to model the operation of the architecture. The predictions of the model are validated by simulations performed using an industry standard software tool. Implementation is found to be practical.

  18. FDTD-SPICE for Characterizing Metamaterials Integrated with Electronic Circuits

    Directory of Open Access Journals (Sweden)

    Zhengwei Hao

    2012-01-01

    Full Text Available A powerful time-domain FDTD-SPICE simulator is implemented and applied to the broadband analysis of metamaterials integrated with active and tunable circuit elements. First, the FDTD-SPICE modeling theory is studied and details of interprocess communication and hybridization of the two techniques are discussed. To verify the model, some simple cases are simulated with results in both time domain and frequency domain. Then, simulation of a metamaterial structure constructed from periodic resonant loops integrated with lumped capacitor elements is studied, which demonstrates tuning resonance frequency of medium by changing the capacitance of the integrated elements. To increase the bandwidth of the metamaterial, non-Foster transistor configurations are integrated with the loops and FDTD-SPICE is applied to successfully bridge the physics of electromagnetic and circuit topologies and to model the whole composite structure. Our model is also applied to the design and simulation of a metasurface integrated with nonlinear varactors featuring tunable reflection phase characteristic.

  19. Integrating anatomy and function for zebrafish circuit analysis.

    Science.gov (United States)

    Arrenberg, Aristides B; Driever, Wolfgang

    2013-01-01

    Due to its transparency, virtually every brain structure of the larval zebrafish is accessible to light-based interrogation of circuit function. Advanced stimulation techniques allow the activation of optogenetic actuators at different resolution levels, and genetically encoded calcium indicators report the activity of a large proportion of neurons in the CNS. Large datasets result and need to be analyzed to identify cells that have specific properties-e.g., activity correlation to sensory stimulation or behavior. Advances in three-dimensional (3D) functional mapping in zebrafish are promising; however, the mere coordinates of implicated neurons are not sufficient. To comprehensively understand circuit function, these functional maps need to be placed into the proper context of morphological features and projection patterns, neurotransmitter phenotypes, and key anatomical landmarks. We discuss the prospect of merging functional and anatomical data in an integrated atlas from the perspective of our work on long-range dopaminergic neuromodulation and the oculomotor system. We propose that such a resource would help researchers to surpass current hurdles in circuit analysis to achieve an integrated understanding of anatomy and function.

  20. Design automation for integrated nonlinear logic circuits (Conference Presentation)

    Science.gov (United States)

    Van Vaerenbergh, Thomas; Pelc, Jason; Santori, Charles; Bose, Ranojoy; Kielpinski, Dave; Beausoleil, Raymond G.

    2016-05-01

    A key enabler of the IT revolution of the late 20th century was the development of electronic design automation (EDA) tools allowing engineers to manage the complexity of electronic circuits with transistor counts now reaching into the billions. Recently, we have been developing large-scale nonlinear photonic integrated logic circuits for next generation all-optical information processing. At this time a sufficiently powerful EDA-style software tool chain to design this type of complex circuits does not yet exist. Here we describe a hierarchical approach to automating the design and validation of photonic integrated circuits, which can scale to several orders of magnitude higher complexity than the state of the art. Most photonic integrated circuits developed today consist of a small number of components, and only limited hierarchy. For example, a simple photonic transceiver may contain on the order of 10 building-block components, consisting of grating couplers for photonic I/O, modulators, and signal splitters/combiners. Because this is relatively easy to lay out by hand (or simple script) existing photonic design tools have relatively little automation in comparison to electronics tools. But demonstrating all-optical logic will require significantly more complex photonic circuits containing up to 1,000 components, hence becoming infeasible to design manually. Our design framework is based off Python-based software from Luceda Photonics which provides an environment to describe components, simulate their behavior, and export design files (GDS) to foundries for fabrication. At a fundamental level, a photonic component is described as a parametric cell (PCell) similarly to electronics design. PCells are described by geometric characteristics of their layout. A critical part of the design framework is the implementation of PCells as Python objects. PCell objects can then use inheritance to simplify design, and hierarchical designs can be made by creating composite

  1. InP-based three-dimensional photonic integrated circuits

    Science.gov (United States)

    Tsou, Diana; Zaytsev, Sergey; Pauchard, Alexandre; Hummel, Steve; Lo, Yu-Hwa

    2001-10-01

    Fast-growing internet traffic volumes require high data communication bandwidth over longer distances than short wavelength (850 nm) multi-mode fiber systems can provide. Access network bottlenecks put pressure on short-range (SR) telecommunication systems. To effectively address these datacom and telecom market needs, low cost, high-speed laser modules at 1310 and 1550 nm wavelengths are required. The great success of GaAs 850 nm VCSELs for Gb/s Ethernet has motivated efforts to extend VCSEL technology to longer wavelengths in the 1310 and 1550 nm regimes. However, the technological challenges associated with available intrinsic materials for long wavelength VCSELs are tremendous. Even with recent advances in this area, it is believed that significant additional development is necessary before long wavelength VCSELs that meet commercial specifications will be widely available. In addition, the more stringent OC192 and OC768 specifications for single-mode fiber (SMF) datacom may require more than just a long wavelength laser diode, VCSEL or not, to address numerous cost and performance issues. We believe that photonic integrated circuits, which compactly integrate surface-emitting lasers with additional active and passive optical components with extended functionality, will provide the best solutions to today's problems. Photonic integrated circuits (PICs) have been investigated for more than a decade. However, they have produced limited commercial impact to date primarily because the highly complicated fabrication processes produce significant yield and device performance issues. In this presentation, we will discuss a new technology platform for fabricating InP-based photonic integrated circuits compatible with surface-emitting laser technology. Employing InP transparency at 1310 and 1550 nm wavelengths, we have created 3-D photonic integrated circuits (PICs) by utilizing light beams in both surface normal and in-plane directions within the InP-based structure

  2. Millimeter wave planar integrated circuit developments for communication applications

    Science.gov (United States)

    Chang, K.; Sun, C.

    Millimeter wave communication systems offer certain advantages over lower frequency systems. These advantages are related to wider bandwidth, larger data handling capacity, covert operation, and better immunity to jamming. Newer developments in the area of component technology for systems operating at millimeter wavelengths have utilized planar integrated circuits. Such circuits provide benefits of light weight, small size, and inherent low cost due to ease of high volume manufacturing. The present paper is concerned with a number of key IC components which have been developed. These components are ideally suited for direct application in advanced tactical, radar, and satellite communication systems. Attention is given to a rat-race microstrip balanced mixer, a crossbar stripline balanced mixer, and various subsystems developments.

  3. Integrated Circuit Design in US High-Energy Physics

    CERN Document Server

    De Geronimo, G; Bebek, C; Garcia-Sciveres, M; Von der Lippe, H; Haller, G; Grillo, A A; Newcomer, M

    2013-01-01

    This whitepaper summarizes the status, plans, and challenges in the area of integrated circuit design in the United States for future High Energy Physics (HEP) experiments. It has been submitted to CPAD (Coordinating Panel for Advanced Detectors) and the HEP Community Summer Study 2013(Snowmass on the Mississippi) held in Minnesota July 29 to August 6, 2013. A workshop titled: US Workshop on IC Design for High Energy Physics, HEPIC2013 was held May 30 to June 1, 2013 at Lawrence Berkeley National Laboratory (LBNL). A draft of the whitepaper was distributed to the attendees before the workshop, the content was discussed at the meeting, and this document is the resulting final product. The scope of the whitepaper includes the following topics: Needs for IC technologies to enable future experiments in the three HEP frontiers Energy, Cosmic and Intensity Frontiers; Challenges in the different technology and circuit design areas and the related R&D needs; Motivation for using different fabrication technologies...

  4. Monocrystalline silicon used for integrated circuits: still on the way

    Institute of Scientific and Technical Information of China (English)

    Jia-he CHEN; De-ren YANG; Duan-lin QUE

    2008-01-01

    With the rapid development of semiconductor technology, highly integrated circuits (ICs) and future nano-scale devices require large diameter and defect-free monocrystalline silicon wafers. The ongoing innovation from silicon materials is one of the driving forces in future micro and nano-technologies. In this work, the recent developments in the controlling of large diameter silicon crystal growth processes, the improvement of material features by co-doping with the intend-introduced impur-ities, and the progress of defect engineered silicon wafers (epitaxial silicon wafer, strained silicon, silicon on insu-lator) are reviewed. It is proposed that the silicon man-ufacturing infrastructure could still meet the increasingly stringent requirements arising from ULSI circuits and will expand Moore's law into a couple of decades.

  5. Advances in integrated photonic circuits for packet-switched interconnection

    Science.gov (United States)

    Williams, Kevin A.; Stabile, Ripalta

    2014-03-01

    Sustained increases in capacity and connectivity are needed to overcome congestion in a range of broadband communication network nodes. Packet routing and switching in the electronic domain are leading to unsustainable energy- and bandwidth-densities, motivating research into hybrid solutions: optical switching engines are introduced for massive-bandwidth data transport while the electronic domain is clocked at more modest GHz rates to manage routing. Commercially-deployed optical switching engines using MEMS technologies are unwieldy and too slow to reconfigure for future packet-based networking. Optoelectronic packet-compliant switch technologies have been demonstrated as laboratory prototypes, but they have so far mostly used discretely pigtailed components, which are impractical for control plane development and product assembly. Integrated photonics has long held the promise of reduced hardware complexity and may be the critical step towards packet-compliant optical switching engines. Recently a number of laboratories world-wide have prototyped optical switching circuits using monolithic integration technology with up to several hundreds of integrated optical components per chip. Our own work has focused on multi-input to multi-output switching matrices. Recently we have demonstrated 8×8×8λ space and wavelength selective switches using gated cyclic routers and 16×16 broadband switching chips using monolithic multi-stage networks. We now operate these advanced circuits with custom control planes implemented with FPGAs to explore real time packet routing in multi-wavelength, multi-port test-beds. We review our contributions in the context of state of the art photonic integrated circuit technology and packet optical switching hardware demonstrations.

  6. Implantable neurotechnologies: a review of integrated circuit neural amplifiers.

    Science.gov (United States)

    Ng, Kian Ann; Greenwald, Elliot; Xu, Yong Ping; Thakor, Nitish V

    2016-01-01

    Neural signal recording is critical in modern day neuroscience research and emerging neural prosthesis programs. Neural recording requires the use of precise, low-noise amplifier systems to acquire and condition the weak neural signals that are transduced through electrode interfaces. Neural amplifiers and amplifier-based systems are available commercially or can be designed in-house and fabricated using integrated circuit (IC) technologies, resulting in very large-scale integration or application-specific integrated circuit solutions. IC-based neural amplifiers are now used to acquire untethered/portable neural recordings, as they meet the requirements of a miniaturized form factor, light weight and low power consumption. Furthermore, such miniaturized and low-power IC neural amplifiers are now being used in emerging implantable neural prosthesis technologies. This review focuses on neural amplifier-based devices and is presented in two interrelated parts. First, neural signal recording is reviewed, and practical challenges are highlighted. Current amplifier designs with increased functionality and performance and without penalties in chip size and power are featured. Second, applications of IC-based neural amplifiers in basic science experiments (e.g., cortical studies using animal models), neural prostheses (e.g., brain/nerve machine interfaces) and treatment of neuronal diseases (e.g., DBS for treatment of epilepsy) are highlighted. The review concludes with future outlooks of this technology and important challenges with regard to neural signal amplification.

  7. High-precision analog circuit technology for power supply integrated circuits; Dengen IC yo koseido anarogu kairo gijutsu

    Energy Technology Data Exchange (ETDEWEB)

    Nakamori, A.; Suzuki, T.; Mizoe, K. [Fuji Electric Corporate Research and Development,Ltd., Kanagawa (Japan)

    2000-08-10

    With the recent rapid spread of portable electronic appliances, specification requirements such as compact power supply and long operation with batteries have become severer. Power supply ICs (integrated circuits) are required to reduce power consumption in the circuit and perform high-precision control. To meet these requirements, Fuji Electric develops high-precision CMOS (complementary metal-oxide semiconductor) analog technology. This paper describes three analog circuit technologies of a voltage reference, an operational amplifier and a comparator as circuit components particularly important for the precision of power supply ICs. (author)

  8. Integrated circuit authentication hardware Trojans and counterfeit detection

    CERN Document Server

    Tehranipoor, Mohammad; Zhang, Xuehui

    2013-01-01

    This book describes techniques to verify the authenticity of integrated circuits (ICs). It focuses on hardware Trojan detection and prevention and counterfeit detection and prevention. The authors discuss a variety of detection schemes and design methodologies for improving Trojan detection techniques, as well as various attempts at developing hardware Trojans in IP cores and ICs. While describing existing Trojan detection methods, the authors also analyze their effectiveness in disclosing various types of Trojans, and demonstrate several architecture-level solutions. 

  9. Noise estimation for deep sub-micron integrated circuits

    Institute of Scientific and Technical Information of China (English)

    陈彬; 杨华中; 汪惠

    2001-01-01

    Noise analysis and avoidance are an increasingly critical step in the design of deep submicron (DSM) integrated circuits (Ics). The crosstalk between neighboring interconnects gradually becomes the main noise sources in DSM Ics. We introduce an efficient and accurate noise-evaluation method for capacitively coupled nets of Ics. The method holds for a victim net with arbitrary number of aggressive nets under ramp input excitation. For common RC nets extracted by electronic design automation (EDA) tools, the deviation between our method and HSPICE is under 10%.

  10. Investigation of Optimal Integrated Circuit Raster Image Vectorization Method

    Directory of Open Access Journals (Sweden)

    Leonas Jasevičius

    2011-03-01

    Full Text Available Visual analysis of integrated circuit layer requires raster image vectorization stage to extract layer topology data to CAD tools. In this paper vectorization problems of raster IC layer images are presented. Various line extraction from raster images algorithms and their properties are discussed. Optimal raster image vectorization method was developed which allows utilization of common vectorization algorithms to achieve the best possible extracted vector data match with perfect manual vectorization results. To develop the optimal method, vectorized data quality dependence on initial raster image skeleton filter selection was assessed.Article in Lithuanian

  11. The FE-I4 pixel readout integrated circuit

    Energy Technology Data Exchange (ETDEWEB)

    Garcia-Sciveres, M., E-mail: mgarcia-sciveres@bl.gov [Lawrence Berkeley National Laboratory, Berkeley, CA (United States); Arutinov, D.; Barbero, M. [University of Bonn, Bonn (Germany); Beccherle, R. [Istituto Nazionale di Fisica Nucleare Sezione di Genova, Genova (Italy); Dube, S.; Elledge, D. [Lawrence Berkeley National Laboratory, Berkeley, CA (United States); Fleury, J. [Laboratoire de l' Accelerateur Lineaire, Orsay (France); Fougeron, D.; Gensolen, F. [Centre de Physique des Particules de Marseille, Marseille (France); Gnani, D. [Lawrence Berkeley National Laboratory, Berkeley, CA (United States); Gromov, V. [Nationaal Instituut voor Subatomaire Fysica, Amsterdam (Netherlands); Hemperek, T.; Karagounis, M. [University of Bonn, Bonn (Germany); Kluit, R. [Nationaal Instituut voor Subatomaire Fysica, Amsterdam (Netherlands); Kruth, A. [University of Bonn, Bonn (Germany); Mekkaoui, A. [Lawrence Berkeley National Laboratory, Berkeley, CA (United States); Menouni, M. [Centre de Physique des Particules de Marseille, Marseille (France); Schipper, J.-D. [Nationaal Instituut voor Subatomaire Fysica, Amsterdam (Netherlands)

    2011-04-21

    A new pixel readout integrated circuit denominated FE-I4 is being designed to meet the requirements of ATLAS experiment upgrades. It will be the largest readout IC produced to date for particle physics applications, filling the maximum allowed reticle area. This will significantly reduce the cost of future hybrid pixel detectors. In addition, FE-I4 will have smaller pixels and higher rate capability than the present generation of LHC pixel detectors. Design features are described along with simulation and test results, including low power and high rate readout architecture, mixed signal design strategy, and yield hardening.

  12. CALCULATIONS OF DOUBLE IMPURITY DIFFUSION IN INTEGRATED CIRCUIT PRODUCTION

    Directory of Open Access Journals (Sweden)

    V. A. Bondarev

    2005-01-01

    Full Text Available Analytical formulae for calculating simultaneous diffusion of two impurities in silicon are presented. The formulae are based on analytical solutions of diffusion equations that have been obtained for the first time by the author while using some special mathematical functions. In contrast to usual formal mathematical approaches, new functions are determined in the process of investigation of real physical models. Algorithms involve some important relations from thermodynamics of irreversible processes and also variational thermodynamic functionals that were previously obtained by the author for transfer processes. Calculations considerably reduce the time required for development of new integrated circuits

  13. Cycles of self-pulsations in a photonic integrated circuit.

    Science.gov (United States)

    Karsaklian Dal Bosco, Andreas; Kanno, Kazutaka; Uchida, Atsushi; Sciamanna, Marc; Harayama, Takahisa; Yoshimura, Kazuyuki

    2015-12-01

    We report experimentally on the bifurcation cascade leading to the appearance of self-pulsation in a photonic integrated circuit in which a laser diode is subjected to delayed optical feedback. We study the evolution of the self-pulsing frequency with the increase of both the feedback strength and the injection current. Experimental observations show good qualitative accordance with numerical results carried out with the Lang-Kobayashi rate equation model. We explain the mechanism underlying the self-pulsations by a phenomenon of beating between successive pairs of external cavity modes and antimodes.

  14. Transient-induced latchup in CMOS integrated circuits

    CERN Document Server

    Ker, Ming-Dou

    2009-01-01

    "Transient-Induced Latchup in CMOS Integrated Circuits equips the practicing engineer with all the tools needed to address this regularly occurring problem while becoming more proficient at IC layout. Ker and Hsu introduce the phenomenon and basic physical mechanism of latchup, explaining the critical issues that have resurfaced for CMOS technologies. Once readers can gain an understanding of the standard practices for TLU, Ker and Hsu discuss the physical mechanism of TLU under a system-level ESD test, while introducing an efficient component-level TLU measurement setup. The authors then present experimental methodologies to extract safe and area-efficient compact layout rules for latchup prevention, including layout rules for I/O cells, internal circuits, and between I/O and internal circuits. The book concludes with an appendix giving a practical example of extracting layout rules and guidelines for latchup prevention in a 0.18-micrometer 1.8V/3.3V silicided CMOS process."--Publisher's description.

  15. A novel voltage output integrated circuit temperature sensor

    Institute of Scientific and Technical Information of China (English)

    吴晓波; 方志刚; 等

    2002-01-01

    The novel integrated circuit(IC) temperature sensor presented in this paper works similarly as a two-terminal Zener,has breakdown voltage directly proportional to Kelvin temperature at 10mV/℃,with typical error of less tha ±1.0℃ over a temperature range from-50℃to +120℃ .In addition to all the features that conventional IC temperature sensors have,the new device also has very low static power dissipation(0.5mW),low output impedance(less than 1Ω),execllent stability,high reproducibility,and high precision.The sensor's circuit design and layout are discussed in detail.Applications of the sensor include almost and type of temperature sensing over the range of -50℃-+125℃。The low impedance and linear output of the device make interfacing the readout or control circuitry especially easy.Due to the excellent performance and low cost of this sensor.more application of the sensor over wide temperature range are expected.

  16. Design and application of multilayer monolithic microwave integrated circuit transformers

    International Nuclear Information System (INIS)

    standard foundry processes. With careful modelling it is also feasible to integrate the two couplers into a single tri-filar transformer structure. This is a robust balun topology, which could be widely adopted. A push-pull MESFET amplifier with 8 dB gain demonstrated this at 12 GHz, using the balun chips connected to amplifier circuits. (author)

  17. Design and application of multilayer monolithic microwave integrated circuit transformers

    Energy Technology Data Exchange (ETDEWEB)

    Economides, S.B

    1999-07-01

    fabricated on standard foundry processes. With careful modelling it is also feasible to integrate the two couplers into a single tri-filar transformer structure. This is a robust balun topology, which could be widely adopted. A push-pull MESFET amplifier with 8 dB gain demonstrated this at 12 GHz, using the balun chips connected to amplifier circuits. (author)

  18. Chemistry integrated circuit: chemical system on a complementary metal oxide semiconductor integrated circuit.

    Science.gov (United States)

    Nakazato, Kazuo

    2014-03-28

    By integrating chemical reactions on a large-scale integration (LSI) chip, new types of device can be created. For biomedical applications, monolithically integrated sensor arrays for potentiometric, amperometric and impedimetric sensing of biomolecules have been developed. The potentiometric sensor array detects pH and redox reaction as a statistical distribution of fluctuations in time and space. For the amperometric sensor array, a microelectrode structure for measuring multiple currents at high speed has been proposed. The impedimetric sensor array is designed to measure impedance up to 10 MHz. The multimodal sensor array will enable synthetic analysis and make it possible to standardize biosensor chips. Another approach is to create new functional devices by integrating molecular systems with LSI chips, for example image sensors that incorporate biological materials with a sensor array. The quantum yield of the photoelectric conversion of photosynthesis is 100%, which is extremely difficult to achieve by artificial means. In a recently developed process, a molecular wire is plugged directly into a biological photosynthetic system to efficiently conduct electrons to a gold electrode. A single photon can be detected at room temperature using such a system combined with a molecular single-electron transistor. PMID:24567475

  19. Chemistry integrated circuit: chemical system on a complementary metal oxide semiconductor integrated circuit.

    Science.gov (United States)

    Nakazato, Kazuo

    2014-03-28

    By integrating chemical reactions on a large-scale integration (LSI) chip, new types of device can be created. For biomedical applications, monolithically integrated sensor arrays for potentiometric, amperometric and impedimetric sensing of biomolecules have been developed. The potentiometric sensor array detects pH and redox reaction as a statistical distribution of fluctuations in time and space. For the amperometric sensor array, a microelectrode structure for measuring multiple currents at high speed has been proposed. The impedimetric sensor array is designed to measure impedance up to 10 MHz. The multimodal sensor array will enable synthetic analysis and make it possible to standardize biosensor chips. Another approach is to create new functional devices by integrating molecular systems with LSI chips, for example image sensors that incorporate biological materials with a sensor array. The quantum yield of the photoelectric conversion of photosynthesis is 100%, which is extremely difficult to achieve by artificial means. In a recently developed process, a molecular wire is plugged directly into a biological photosynthetic system to efficiently conduct electrons to a gold electrode. A single photon can be detected at room temperature using such a system combined with a molecular single-electron transistor.

  20. Chemistry integrated circuit: chemical system on a complementary metal oxide semiconductor integrated circuit

    Science.gov (United States)

    Nakazato, Kazuo

    2014-01-01

    By integrating chemical reactions on a large-scale integration (LSI) chip, new types of device can be created. For biomedical applications, monolithically integrated sensor arrays for potentiometric, amperometric and impedimetric sensing of biomolecules have been developed. The potentiometric sensor array detects pH and redox reaction as a statistical distribution of fluctuations in time and space. For the amperometric sensor array, a microelectrode structure for measuring multiple currents at high speed has been proposed. The impedimetric sensor array is designed to measure impedance up to 10 MHz. The multimodal sensor array will enable synthetic analysis and make it possible to standardize biosensor chips. Another approach is to create new functional devices by integrating molecular systems with LSI chips, for example image sensors that incorporate biological materials with a sensor array. The quantum yield of the photoelectric conversion of photosynthesis is 100%, which is extremely difficult to achieve by artificial means. In a recently developed process, a molecular wire is plugged directly into a biological photosynthetic system to efficiently conduct electrons to a gold electrode. A single photon can be detected at room temperature using such a system combined with a molecular single-electron transistor. PMID:24567475

  1. Ultra-low power integrated circuit design circuits, systems, and applications

    CERN Document Server

    Li, Dongmei; Wang, Zhihua

    2014-01-01

    This book describes the design of CMOS circuits for ultra-low power consumption including analog, radio frequency (RF), and digital signal processing circuits (DSP). The book addresses issues from circuit and system design to production design, and applies the ultra-low power circuits described to systems for digital hearing aids and capsule endoscope devices. Provides a valuable introduction to ultra-low power circuit design, aimed at practicing design engineers; Describes all key building blocks of ultra-low power circuits, from a systems perspective; Applies circuits and systems described to real product examples such as hearing aids and capsule endoscopes.

  2. Assessment of Lightning Shielding Performance of a 400 kV Double-Circuit Fully Composite Pylon

    DEFF Research Database (Denmark)

    Jahangirl, Tohid; Bak, Claus Leth; Silva, Filipe Miguel Faria da;

    2016-01-01

    pylons that are easier to erect, less costly, smaller and better looking than the old ones, which is important to get public acceptance. In this regard, a fully composite-based pylon for 400 kV lines is presented with a new innovative design concept shown in Fig. 1. The integration of insulators in cross......-arm design is the prominent feature of the fully composite pylon in comparison with conventional towers. The unibody cross-arm of the pylon has 30 degree inclination and all of conductors are fixed on the cross-arm by cable clamps. Thus, the configuration of phase conductors on the cross-arm is in the form...... of diagonal and differs from other widely used configurations in overhead transmission lines i.e. horizontal, delta and vertical configurations. On the other hand, unlike traditional steel lattice towers, the pylon removes access to ground potential due to its non-conductive materials and therefore...

  3. Intelligent switches of integrated lightwave circuits with core telecommunication functions

    Science.gov (United States)

    Izhaky, Nahum; Duer, Reuven; Berns, Neil; Tal, Eran; Vinikman, Shirly; Schoenwald, Jeffrey S.; Shani, Yosi

    2001-05-01

    We present a brief overview of a promising switching technology based on Silica on Silicon thermo-optic integrated circuits. This is basically a 2D solid-state optical device capable of non-blocking switching operation. Except of its excellent performance (insertion lossmarket segments appropriate for the switch size and technology, followed by a discussion of the basic features of the technology. The discussion is focused on important requirements from the switch and the technology (e.g., insertion loss, power consumption, channel isolation, extinction ratio, switching time, and heat dissipation). The mechanical design is also considered. It must take into account integration of optical fiber, optical planar wafer, analog electronics and digital microprocessor controls, embedded software, and heating power dissipation. The Lynx Photon.8x8 switch is compared to competing technologies, in terms of typical market performance requirements.

  4. Mixed signal custom integrated circuit development for physics instrumentation

    Energy Technology Data Exchange (ETDEWEB)

    Britton, C.L. Jr.; Bryan, W.L.; Emery, M.S. [and others

    1998-10-01

    The Monolithic Systems Development Group at the Oak Ridge National Laboratory has been greatly involved in custom mixed-mode integrated circuit development for the PHENIX detector at the Relativistic Heavy Ion collider (RHIC) at Brookhaven National Laboratory and position-sensitive germanium spectrometer front-ends for the Naval Research Laboratory (NRL). This paper will outline the work done for both PHENIX and the Naval Research Laboratory in the area of full-custom, mixed-signal CMOS integrated electronics. This paper presents the architectures chosen for the various PHENIX detectors which include position-sensitive silicon, capacitive pixel, and phototube detectors, and performance results for the subsystems as well as a system description of the NRL germanium strip system and its performance. The performance of the custom preamplifiers, discriminators, analog memories, analog-digital converters, and control circuitry for all systems will be presented.

  5. Integrated optoelectronic materials and circuits for optical interconnects

    International Nuclear Information System (INIS)

    Conventional interconnect and switching technology is rapidly becoming a critical issue in the realization of systems using high speed silicon and GaAs based technologies. In recent years clock speeds and on-chip density for VLSI/VHSIC technology has made packaging these high speed chips extremely difficult. A strong case can be made for using optical interconnects for on-chip/on-wafer, chip-to-chip and board-to-board high speed communications. GaAs integrated optoelectronic circuits (IOC's) are being developed in a number of laboratories for performing Input/Output functions at all levels. In this paper integrated optoelectronic materials, electronics and optoelectronic devices are presented. IOC's are examined from the standpoint of what it takes to fabricate the devices and what performance can be expected

  6. Development of optical packet and circuit integrated ring network testbed.

    Science.gov (United States)

    Furukawa, Hideaki; Harai, Hiroaki; Miyazawa, Takaya; Shinada, Satoshi; Kawasaki, Wataru; Wada, Naoya

    2011-12-12

    We developed novel integrated optical packet and circuit switch-node equipment. Compared with our previous equipment, a polarization-independent 4 × 4 semiconductor optical amplifier switch subsystem, gain-controlled optical amplifiers, and one 100 Gbps optical packet transponder and seven 10 Gbps optical path transponders with 10 Gigabit Ethernet (10GbE) client-interfaces were newly installed in the present system. The switch and amplifiers can provide more stable operation without equipment adjustments for the frequent polarization-rotations and dynamic packet-rate changes of optical packets. We constructed an optical packet and circuit integrated ring network testbed consisting of two switch nodes for accelerating network development, and we demonstrated 66 km fiber transmission and switching operation of multiplexed 14-wavelength 10 Gbps optical paths and 100 Gbps optical packets encapsulating 10GbE frames. Error-free (frame error rate < 1×10(-4)) operation was achieved with optical packets of various packet lengths and packet rates, and stable operation of the network testbed was confirmed. In addition, 4K uncompressed video streaming over OPS links was successfully demonstrated.

  7. Sub-10 nm colloidal lithography for circuit-integrated spin-photo-electronic devices.

    Science.gov (United States)

    Iovan, Adrian; Fischer, Marco; Lo Conte, Roberto; Korenivski, Vladislav

    2012-01-01

    Patterning of materials at sub-10 nm dimensions is at the forefront of nanotechnology and employs techniques of various complexity, efficiency, areal scale, and cost. Colloid-based patterning is known to be capable of producing individual sub-10 nm objects. However, ordered, large-area nano-arrays, fully integrated into photonic or electronic devices have remained a challenging task. In this work, we extend the practice of colloidal lithography to producing large-area sub-10 nm point-contact arrays and demonstrate their circuit integration into spin-photo-electronic devices. The reported nanofabrication method should have broad application areas in nanotechnology as it allows ballistic-injection devices, even for metallic materials with relatively short characteristic relaxation lengths.

  8. Sub-10 nm colloidal lithography for circuit-integrated spin-photo-electronic devices

    Directory of Open Access Journals (Sweden)

    Adrian Iovan

    2012-12-01

    Full Text Available Patterning of materials at sub-10 nm dimensions is at the forefront of nanotechnology and employs techniques of various complexity, efficiency, areal scale, and cost. Colloid-based patterning is known to be capable of producing individual sub-10 nm objects. However, ordered, large-area nano-arrays, fully integrated into photonic or electronic devices have remained a challenging task. In this work, we extend the practice of colloidal lithography to producing large-area sub-10 nm point-contact arrays and demonstrate their circuit integration into spin-photo-electronic devices. The reported nanofabrication method should have broad application areas in nanotechnology as it allows ballistic-injection devices, even for metallic materials with relatively short characteristic relaxation lengths.

  9. Sub-10 nm colloidal lithography for circuit-integrated spin-photo-electronic devices

    Science.gov (United States)

    Iovan, Adrian; Fischer, Marco; Lo Conte, Roberto

    2012-01-01

    Summary Patterning of materials at sub-10 nm dimensions is at the forefront of nanotechnology and employs techniques of various complexity, efficiency, areal scale, and cost. Colloid-based patterning is known to be capable of producing individual sub-10 nm objects. However, ordered, large-area nano-arrays, fully integrated into photonic or electronic devices have remained a challenging task. In this work, we extend the practice of colloidal lithography to producing large-area sub-10 nm point-contact arrays and demonstrate their circuit integration into spin-photo-electronic devices. The reported nanofabrication method should have broad application areas in nanotechnology as it allows ballistic-injection devices, even for metallic materials with relatively short characteristic relaxation lengths. PMID:23365801

  10. Control technology for integrated circuit fabrication at Micro-Circuit Engineering, Incorporated, West Palm Beach, Florida

    Science.gov (United States)

    Mihlan, G. I.; Mitchell, R. I.; Smith, R. K.

    1984-07-01

    A survey to assess control technology for integrated circuit fabrication was conducted. Engineering controls included local and general exhaust ventilation, shielding, and personal protective equipment. Devices or work stations that contained toxic materials that were potentially dangerous were controlled by local exhaust ventilation. Less hazardous areas were controlled by general exhaust ventilation. Process isolation was used in the plasma etching, low pressure chemical vapor deposition, and metallization operations. Shielding was used in ion implantation units to control X-ray emissions, in contact mask alignes to limit ultraviolet (UV) emissions, and in plasma etching units to control radiofrequency and UV emissions. Most operations were automated. Use of personal protective equipment varied by job function.

  11. VISA Final Report: Fully Integrated Power Electronic Systems in Automotive Electronics

    NARCIS (Netherlands)

    Waffenschmidt, E.

    2011-01-01

    This report summarizes the activities related to the public funded project “Vollintegrierte leistungselektronische Systeme in der Automobilelektronik – VISA” (Fully Integrated Power Electronic Systems in Automotive Electronics). Aim of the project is to investigate the integration of components into

  12. Removal of Gross Air Embolization from Cardiopulmonary Bypass Circuits with Integrated Arterial Line Filters: A Comparison of Circuit Designs.

    Science.gov (United States)

    Reagor, James A; Holt, David W

    2016-03-01

    Advances in technology, the desire to minimize blood product transfusions, and concerns relating to inflammatory mediators have lead many practitioners and manufacturers to minimize cardiopulmonary bypass (CBP) circuit designs. The oxygenator and arterial line filter (ALF) have been integrated into one device as a method of attaining a reduction in prime volume and surface area. The instructions for use of a currently available oxygenator with integrated ALF recommends incorporating a recirculation line distal to the oxygenator. However, according to an unscientific survey, 70% of respondents utilize CPB circuits incorporating integrated ALFs without a path of recirculation distal to the oxygenator outlet. Considering this circuit design, the ability to quickly remove a gross air bolus in the blood path distal to the oxygenator may be compromised. This in vitro study was designed to determine if the time required to remove a gross air bolus from a CPB circuit without a path of recirculation distal to the oxygenator will be significantly longer than that of a circuit with a path of recirculation distal to the oxygenator. A significant difference was found in the mean time required to remove a gross air bolus between the circuit designs (p = .0003). Additionally, There was found to be a statistically significant difference in the mean time required to remove a gross air bolus between Trial 1 and Trials 4 (p = .015) and 5 (p =.014) irrespective of the circuit design. Under the parameters of this study, a recirculation line distal to an oxygenator with an integrated ALF significantly decreases the time it takes to remove an air bolus from the CPB circuit and may be safer for clinical use than the same circuit without a recirculation line.

  13. Long-wavelength photonic integrated circuits and avalanche photodetectors

    Science.gov (United States)

    Tsou, Yi-Jen D.; Zaytsev, Sergey; Pauchard, Alexandre; Hummel, Steve; Lo, Yu-Hwa

    2001-10-01

    Fast-growing internet traffic volume require high data communication bandwidth over longer distances. Access network bottlenecks put pressure on short-range (SR) telecommunication systems. To effectively address these datacom and telecom market needs, low-cost, high-speed laser modules at 1310 to 1550 nm wavelengths and avalanche photodetectors are required. The great success of GaAs 850nm VCSEls for Gb/s Ethernet has motivated efforts to extend VCSEL technology to longer wavelengths in the 1310 and 1550 nm regimes. However, the technological challenges associated with materials for long wavelength VCSELs are tremendous. Even with recent advances in this area, it is believed that significant additional development is necessary before long wavelength VCSELs that meet commercial specifications will be widely available. In addition, the more stringent OC192 and OC768 specifications for single-mode fiber (SMF) datacom may require more than just a long wavelength laser diode, VCSEL or not, to address numerous cost and performance issues. We believe that photonic integrated circuits (PICs), which compactly integrate surface-emitting lasers with additional active and passive optical components with extended functionality, will provide the best solutions to today's problems. Photonic integrated circuits have been investigated for more than a decade. However, they have produced limited commercial impact to date primarily because the highly complicated fabrication processes produce significant yield and device performance issues. In this presentation, we will discuss a new technology platform of InP-based PICs compatible with surface-emitting laser technology, as well as a high data rate externally modulated laser module. Avalanche photodetectors (APDs) are the key component in the receiver to achieve high data rate over long transmission distance because of their high sensitivity and large gain- bandwidth product. We have used wafer fusion technology to achieve In

  14. Digital pixel readout integrated circuit architectures for LWIR

    Science.gov (United States)

    Shafique, Atia; Yazici, Melik; Kayahan, Huseyin; Ceylan, Omer; Gurbuz, Yasar

    2015-06-01

    This paper presents and discusses digital pixel readout integrated circuit architectures for long wavelength infrared (LWIR) in CMOS technology. Presented architectures are designed for scanning and staring arrays type detectors respectively. For scanning arrays, digital time delay integration (TDI) is implemented on 8 pixels with sampling rate up to 3 using CMOS 180nm technology. Input referred noise of ROIC is below 750 rms electron meanwhile power dissipation is appreciably under 30mW. ROIC design is optimized to perform at room as well as cryogenic temperatures. For staring type arrays, a digital pixel architecture relying on coarse quantization with pulse frequency modulation (PFM) and novel approach of extended integration is presented. It can achieve extreme charge handling capacity of 2.04Ge- with 20 bit output resolution and power dissipation below 350 nW in CMOS 90nm technology. Efficient mechanism of measuring the time to estimate the remaining charge on integration capacitor in order to achieve low SNR has employed.

  15. Highly efficient integrated rectifier and voltage boosting circuits for energy harvesting applications

    Directory of Open Access Journals (Sweden)

    D. Maurath

    2008-05-01

    Full Text Available This paper presents novel circuit concepts for integrated rectifiers and voltage converting interfaces for energy harvesting micro-generators. In the context of energy harvesting, usually only small voltages are supplied by vibration-driven generators. Therefore, rectification with minimum voltage losses and low reverse currents is an important issue. This is realized by novel integrated rectifiers which were fabricated and are presented in this article. Additionally, there is a crucial need for dynamic load adaptation as well as voltage up-conversion. A circuit concept is presented, which is able to obtain both requirements. This generator interface adapts its input impedance for an optimal energy transfer efficiency. Furthermore, this generator interface provides implicit voltage up-conversion, whereas the generator output energy is stored on a buffer, which is connected to the output of the voltage converting interface. As simulations express, this fully integrated converter is able to boost ac-voltages greater than |0.35 V| to an output dc-voltage of 2.0 V–2.5 V. Thereby, high harvesting efficiencies above 80% are possible within the entire operational range.

  16. Single event soft error in advanced integrated circuit

    International Nuclear Information System (INIS)

    As technology feature size decreases, single event upset (SEU), and single event transient (SET) dominate the radiation response of microcircuits. Multiple bit upset (MBU) (or multi cell upset) effects, digital single event transient (DSET) and analogue single event transient (ASET) cause serious problems for advanced integrated circuits (ICs) applied in a radiation environment and have become a pressing issue. To face this challenge, a lot of work has been put into the single event soft error mechanism and mitigation schemes. This paper presents a review of SEU and SET, including: a brief historical overview, which summarizes the historical development of the SEU and SET since their first observation in the 1970's; effects prominent in advanced technology, which reviews the effects such as MBU, MSET as well as SET broadening and quenching with the influence of temperature, device structure etc.; the present understanding of single event soft error mechanisms, which review the basic mechanism of single event generation including various component of charge collection; and a discussion of various SEU and SET mitigation schemes divided as circuit hardening and layout hardening that could help the designer meet his goals. (review)

  17. Single event soft error in advanced integrated circuit

    Science.gov (United States)

    Yuanfu, Zhao; Suge, Yue; Xinyuan, Zhao; Shijin, Lu; Qiang, Bian; Liang, Wang; Yongshu, Sun

    2015-11-01

    As technology feature size decreases, single event upset (SEU), and single event transient (SET) dominate the radiation response of microcircuits. Multiple bit upset (MBU) (or multi cell upset) effects, digital single event transient (DSET) and analogue single event transient (ASET) cause serious problems for advanced integrated circuits (ICs) applied in a radiation environment and have become a pressing issue. To face this challenge, a lot of work has been put into the single event soft error mechanism and mitigation schemes. This paper presents a review of SEU and SET, including: a brief historical overview, which summarizes the historical development of the SEU and SET since their first observation in the 1970's; effects prominent in advanced technology, which reviews the effects such as MBU, MSET as well as SET broadening and quenching with the influence of temperature, device structure etc.; the present understanding of single event soft error mechanisms, which review the basic mechanism of single event generation including various component of charge collection; and a discussion of various SEU and SET mitigation schemes divided as circuit hardening and layout hardening that could help the designer meet his goals.

  18. A novel voltage output integrated circuit temperature sensor

    Institute of Scientific and Technical Information of China (English)

    吴晓波; 赵梦恋; 严晓浪; 方志刚

    2002-01-01

    The novel integrated circuit (IC) temperature sensor presented in this paper works similarly as a two-terminal Zener, has breakdown voltage directly proportional to Kelvin temperature at 10 mV/℃, with typical error of less than ±1.0℃ over a temperature range from -50℃ to +125℃. In addition to all the features that conventional IC temperature sensors have, the new device also has very low static power dissipation ( 0.5 mW ) , low output impedance ( less than 1Ω), excellent stability, high reproducibility, and high precision. The sensor's circuit design and layout are discussed in detail. Applications of the sensor include almost any type of temperature sensing over the range of -50℃-+125℃. The low impedance and linear output of the device make interfacing the readout or control circuitry especially easy. Due to the excellent performance and low cost of this sensor, more applications of the sensor over wide temperature range are expected.

  19. CMOS analog integrated circuit design technology; CMOS anarogu IC sekkei gijutsu

    Energy Technology Data Exchange (ETDEWEB)

    Fujimoto, H.; Fujisawa, A. [Fuji Electric Co. Ltd., Tokyo (Japan)

    2000-08-10

    In the field of the LSI (large scale integrated circuit) in rapid progress toward high integration and advanced functions, CAD (computer-aided design) technology has become indispensable to LSI development within a short period. Fuji Electric has developed design technologies and automatic design system to develop high-quality analog ICs (integrated circuits), including power supply ICs. within a short period. This paper describes CMOS (complementary metal-oxide semiconductor) analog macro cell, circuit simulation, automatic routing, and backannotation technologies. (author)

  20. Integrated circuit for processing a low-frequency signal from a seismic detector

    Energy Technology Data Exchange (ETDEWEB)

    Malashevich, N. I.; Roslyakov, A. S.; Polomoshnov, S. A., E-mail: S.Polomoshnov@tsen.ru; Fedorov, R. A. [Research and Production Complex ' Technological Center' of the Moscow Institute of Electronic Technology (Russian Federation)

    2011-12-15

    Specific features for the detection and processing of a low-frequency signal from a seismic detector are considered in terms of an integrated circuit based on a large matrix crystal of the 5507 series. This integrated circuit is designed for the detection of human movements. The specific features of the information signal, obtained at the output of the seismic detector, and the main characteristics of the integrated circuit and its structure are reported.

  1. Uncertain behaviours of integrated circuits improve computational performance.

    Science.gov (United States)

    Yoshimura, Chihiro; Yamaoka, Masanao; Hayashi, Masato; Okuyama, Takuya; Aoki, Hidetaka; Kawarabayashi, Ken-ichi; Mizuno, Hiroyuki

    2015-01-01

    Improvements to the performance of conventional computers have mainly been achieved through semiconductor scaling; however, scaling is reaching its limitations. Natural phenomena, such as quantum superposition and stochastic resonance, have been introduced into new computing paradigms to improve performance beyond these limitations. Here, we explain that the uncertain behaviours of devices due to semiconductor scaling can improve the performance of computers. We prototyped an integrated circuit by performing a ground-state search of the Ising model. The bit errors of memory cell devices holding the current state of search occur probabilistically by inserting fluctuations into dynamic device characteristics, which will be actualised in the future to the chip. As a result, we observed more improvements in solution accuracy than that without fluctuations. Although the uncertain behaviours of devices had been intended to be eliminated in conventional devices, we demonstrate that uncertain behaviours has become the key to improving computational performance. PMID:26586362

  2. Applications of Data Mining in Integrated Circuits Manufacturing

    Directory of Open Access Journals (Sweden)

    Sidda Reddy Kurakula

    2014-09-01

    Full Text Available Integrated circuits (a.k.a chips or IC’s are some of the most complex devices manufactured. Making chips is a complex process requiring hundreds of precisely controlled steps such as film deposition, etching and patterning of various materials until the final device structure is realized. Also, each chip goes through a huge number of complicated tests and inspection steps to ensure quality. In IC manufacturing, yield is defined as the percentage of chips in a finished wafer that pass all tests and function properly. Yield improvement translates directly into increased revenues. A humongous amount of data (Terabytes per day is logged from the equipment in the fab. This paper describes some applications of advanced data mining techniques used by chip makers and equipment suppliers in order to improve yield, match equipment, increase equipment output and also to predict the change in equipment performance before and after maintenance activities.

  3. Plasmonic nanopatch array for optical integrated circuit applications.

    Science.gov (United States)

    Qu, Shi-Wei; Nie, Zai-Ping

    2013-01-01

    Future plasmonic integrated circuits with the capability of extremely high-speed data processing at optical frequencies will be dominated by the efficient optical emission (excitation) from (of) plasmonic waveguides. Towards this goal, plasmonic nanoantennas, currently a hot topic in the field of plasmonics, have potential to bridge the mismatch between the wave vector of free-space photonics and that of the guided plasmonics. To manipulate light at will, plasmonic nanoantenna arrays will definitely be more efficient than isolated nanoantennas. In this article, the concepts of microwave antenna arrays are applied to efficiently convert plasmonic waves in the plasmonic waveguides into free-space optical waves or vice versa. The proposed plasmonic nanoantenna array, with nanopatch antennas and a coupled wedge plasmon waveguide, can also act as an efficient spectrometer to project different wavelengths into different directions, or as a spatial filter to absorb a specific wavelength at a specified incident angle. PMID:24201454

  4. Wireless Neural Recording With Single Low-Power Integrated Circuit

    Science.gov (United States)

    Harrison, Reid R.; Kier, Ryan J.; Chestek, Cynthia A.; Gilja, Vikash; Nuyujukian, Paul; Ryu, Stephen; Greger, Bradley; Solzbacher, Florian; Shenoy, Krishna V.

    2010-01-01

    We present benchtop and in vivo experimental results from an integrated circuit designed for wireless implantable neural recording applications. The chip, which was fabricated in a commercially available 0.6-μm 2P3M BiCMOS process, contains 100 amplifiers, a 10-bit analog-to-digital converter (ADC), 100 threshold-based spike detectors, and a 902–928 MHz frequency-shift-keying (FSK) transmitter. Neural signals from a selected amplifier are sampled by the ADC at 15.7 kSps and telemetered over the FSK wireless data link. Power, clock, and command signals are sent to the chip wirelessly over a 2.765-MHz inductive (coil-to-coil) link. The chip is capable of operating with only two off-chip components: a power/command receiving coil and a 100-nF capacitor. PMID:19497825

  5. Plasmonic nanopatch array for optical integrated circuit applications.

    Science.gov (United States)

    Qu, Shi-Wei; Nie, Zai-Ping

    2013-11-08

    Future plasmonic integrated circuits with the capability of extremely high-speed data processing at optical frequencies will be dominated by the efficient optical emission (excitation) from (of) plasmonic waveguides. Towards this goal, plasmonic nanoantennas, currently a hot topic in the field of plasmonics, have potential to bridge the mismatch between the wave vector of free-space photonics and that of the guided plasmonics. To manipulate light at will, plasmonic nanoantenna arrays will definitely be more efficient than isolated nanoantennas. In this article, the concepts of microwave antenna arrays are applied to efficiently convert plasmonic waves in the plasmonic waveguides into free-space optical waves or vice versa. The proposed plasmonic nanoantenna array, with nanopatch antennas and a coupled wedge plasmon waveguide, can also act as an efficient spectrometer to project different wavelengths into different directions, or as a spatial filter to absorb a specific wavelength at a specified incident angle.

  6. Plasmonic nanopatch array for optical integrated circuit applications

    Science.gov (United States)

    Qu, Shi-Wei; Nie, Zai-Ping

    2013-01-01

    Future plasmonic integrated circuits with the capability of extremely high-speed data processing at optical frequencies will be dominated by the efficient optical emission (excitation) from (of) plasmonic waveguides. Towards this goal, plasmonic nanoantennas, currently a hot topic in the field of plasmonics, have potential to bridge the mismatch between the wave vector of free-space photonics and that of the guided plasmonics. To manipulate light at will, plasmonic nanoantenna arrays will definitely be more efficient than isolated nanoantennas. In this article, the concepts of microwave antenna arrays are applied to efficiently convert plasmonic waves in the plasmonic waveguides into free-space optical waves or vice versa. The proposed plasmonic nanoantenna array, with nanopatch antennas and a coupled wedge plasmon waveguide, can also act as an efficient spectrometer to project different wavelengths into different directions, or as a spatial filter to absorb a specific wavelength at a specified incident angle. PMID:24201454

  7. An integrated energy-efficient capacitive sensor digital interface circuit

    KAUST Repository

    Omran, Hesham

    2014-06-19

    In this paper, we propose an energy-efficient 13-bit capacitive sensor interface circuit. The proposed design fully relies on successive approximation algorithm, which eliminates the need for oversampling and digital decimation filtering, and thus low-power consumption is achieved. The proposed architecture employs a charge amplifier stage to acheive parasitic insensitive operation and fine absolute resolution. Moreover, the output code is not affected by offset voltages or charge injection. The successive approximation algorithm is implemented in the capacitance-domain using a coarse-fine programmable capacitor array, which allows digitizing wide capacitance range in compact area. Analysis for the maximum achievable resolution due to mismatch is provided. The proposed design is insensitive to any reference voltage or current which translates to low temperature sensitivity. The operation of a prototype fabricated in a standard CMOS technology is experimentally verified using both on-chip and off-chip capacitive sensors. Compared to similar prior work, the fabricated prototype achieves and excellent energy efficiency of 34 pJ/step.

  8. Fully 3D-Integrated Pixel Detectors for X-Rays

    Energy Technology Data Exchange (ETDEWEB)

    Deptuch, Grzegorz W. [Fermi National Accelerator Lab. (FNAL), Batavia, IL (United States); Gabriella, Carini [SLAC National Accelerator Lab., Menlo Park, CA (United States); Enquist, Paul [Fermi National Accelerator Lab. (FNAL), Batavia, IL (United States); Grybos, Pawel [Fermi National Accelerator Lab. (FNAL), Batavia, IL (United States); Holm, Scott [Fermi National Accelerator Lab. (FNAL), Batavia, IL (United States); Lipton, Ronald [Fermi National Accelerator Lab. (FNAL), Batavia, IL (United States); Maj, Piotr [Fermi National Accelerator Lab. (FNAL), Batavia, IL (United States); Patti, Robert [Fermi National Accelerator Lab. (FNAL), Batavia, IL (United States); Siddons, David Peter [Fermi National Accelerator Lab. (FNAL), Batavia, IL (United States); Szczygiel, Robert [Fermi National Accelerator Lab. (FNAL), Batavia, IL (United States); Yarema, Raymond [Fermi National Accelerator Lab. (FNAL), Batavia, IL (United States)

    2016-01-01

    The vertically integrated photon imaging chip (VIPIC1) pixel detector is a stack consisting of a 500-μm-thick silicon sensor, a two-tier 34-μm-thick integrated circuit, and a host printed circuit board (PCB). The integrated circuit tiers were bonded using the direct bonding technology with copper, and each tier features 1-μm-diameter through-silicon vias that were used for connections to the sensor on one side, and to the host PCB on the other side. The 80-μm-pixel-pitch sensor was the direct bonding technology with nickel bonded to the integrated circuit. The stack was mounted on the board using Sn–Pb balls placed on a 320-μm pitch, yielding an entirely wire-bond-less structure. The analog front-end features a pulse response peaking at below 250 ns, and the power consumption per pixel is 25 μW. We successful completed the 3-D integration and have reported here. Additionally, all pixels in the matrix of 64 × 64 pixels were responding on well-bonded devices. Correct operation of the sparsified readout, allowing a single 153-ns bunch timing resolution, was confirmed in the tests on a synchrotron beam of 10-keV X-rays. An equivalent noise charge of 36.2 e- rms and a conversion gain of 69.5 μV/e- with 2.6 e- rms and 2.7 μV/e- rms pixel-to-pixel variations, respectively, were measured.

  9. Computation Reduction for Statistical Analysis of the Effect of Nano-CMOS Variability on Integrated Circuits

    OpenAIRE

    Xie, Zheng

    2012-01-01

    The intrinsic atomistic variability of nano-scale integrated circuit (IC) technology must be taken into account when analysing circuit designs to predict likely yield. These ‘atomistic’ variabilities are random in nature and are so great that new circuit analysis techniques are needed which adopt a statistical treatment of the variability of device performances. Monte Carlo (MC) based statistical techniques aim to do this by analysing many randomized copies of the circuit. The randomization ...

  10. Assessment of Lightning Shielding Performance of a 400 kV Double-Circuit Fully Composite Transmission Line Pylon

    DEFF Research Database (Denmark)

    Jahangiri, Tohid; Bak, Claus Leth; Silva, Filipe Miguel Faria da;

    2016-01-01

    . The integration of insulators in the cross-arm design is the prominent feature of the fully composite pylon in comparison with conventional towers. The unibody cross-arm of the pylon is expected to have 30 degree inclination and all conductors are fixed to the top of the cross-arm by cable clamps or special high...... not provide access to ground potential due to its non-conductive materials. Therefore, the lightning shielding of pylon and conductors requires a ground potential access to shield wires by utilizing a ground cable inside the hollow cross-arm and pylon body. Efficient design of a lightning shielding system......-quality insulation sections. Thus, the configuration of phase conductors on the cross-arm is in the form of diagonal and differs from other widely used configurations in overhead transmission lines i.e. horizontal, delta and vertical configurations. Unlike traditional steel lattice towers, the composite pylon does...

  11. SDN architecture for optical packet and circuit integrated networks

    Science.gov (United States)

    Furukawa, Hideaki; Miyazawa, Takaya

    2016-02-01

    We have been developing an optical packet and circuit integrated (OPCI) network, which realizes dynamic optical path, high-density packet multiplexing, and flexible wavelength resource allocation. In the OPCI networks, a best-effort service and a QoS-guaranteed service are provided by employing optical packet switching (OPS) and optical circuit switching (OCS) respectively, and users can select these services. Different wavelength resources are assigned for OPS and OCS links, and the amount of their wavelength resources are dynamically changed in accordance with the service usage conditions. To apply OPCI networks into wide-area (core/metro) networks, we have developed an OPCI node with a distributed control mechanism. Moreover, our OPCI node works with a centralized control mechanism as well as a distributed one. It is therefore possible to realize SDN-based OPCI networks, where resource requests and a centralized configuration are carried out. In this paper, we show our SDN architecture for an OPS system that configures mapping tables between IP addresses and optical packet addresses and switching tables according to the requests from multiple users via a web interface. While OpenFlow-based centralized control protocol is coming into widespread use especially for single-administrative, small-area (LAN/data-center) networks. Here, we also show an interworking mechanism between OpenFlow-based networks (OFNs) and the OPCI network for constructing a wide-area network, and a control method of wavelength resource selection to automatically transfer diversified flows from OFNs to the OPCI network.

  12. The TNF receptor and Ig superfamily members form an integrated signaling circuit controlling dendritic cell homeostasis

    Science.gov (United States)

    De Trez, Carl; Ware, Carl F.

    2008-01-01

    Dendritic cells (DC) constitute the most potent antigen presenting cells of the immune system, playing a key role bridging innate and adaptive immune responses. Specialized DC subsets differ depending on their origin, tissue location and the influence of trophic factors, the latter remain to be fully understood. Stromal cell and myeloid-associated Lymphotoxin-β receptor (LTβR) signaling is required for the local proliferation of lymphoid tissue DC. This review focuses the LTβR signaling cascade as a crucial positive trophic signal in the homeostasis of DC subsets. The noncanonical coreceptor pathway comprised of the Immunoglobulin (Ig) superfamily member, B and T lymphocyte attenuator (BTLA) and TNFR superfamily member, Herpesvirus entry mediator (HVEM) counter regulates the trophic signaling by LTβR. Together both pathways form an integrated signaling circuit achieving homeostasis of DC subsets. PMID:18511331

  13. A fully automated data reduction pipeline for the FRODOSpec integral field spectrograph

    CERN Document Server

    Barnsley, R M; Steele, I A

    2011-01-01

    A fully autonomous data reduction pipeline has been developed for FRODOSpec, an optical fibre-fed integral field spectrograph currently in use at the Liverpool Telescope. This paper details the process required for the reduction of data taken using an integral field spectrograph and presents an overview of the computational methods implemented to create the pipeline. Analysis of errors and possible future enhancements are also discussed.

  14. Development of wide range charge integration application specified integrated circuit for photo-sensor

    International Nuclear Information System (INIS)

    A front-end application specified integrated circuit (ASIC) is developed with a wide dynamic range amplifier (WDAMP) to read-out signals from a photo-sensor like a photodiode. The WDAMP ASIC consists of a charge sensitive preamplifier, four wave-shaping circuits with different amplification factors and Wilkinson-type analog-to-digital converter (ADC). To realize a wider range, the integrating capacitor in the preamplifier can be changed from 4 pF to 16 pF by a two-bit switch. The output of a preamplifier is shared by the four wave-shaping circuits with four gains of 1, 4, 16 and 64 to adapt the input range of ADC. A 0.25-μm CMOS process (of UMC electronics CO., LTD) is used to fabricate the ASIC with four-channels. The dynamic range of four orders of magnitude is achieved with the maximum range over 20 pC and the noise performance of 0.46 fC + 6.4×10−4 fC/pF. -- Highlights: ► A front-end ASIC is developed with a wide dynamic range amplifier. ► The ASIC consists of a CSA, four wave-shaping circuits and pulse-height-to-time converters. ► The dynamic range of four orders of magnitude is achieved with the maximum range over 20 pC.

  15. Development of wide range charge integration application specified integrated circuit for photo-sensor

    Energy Technology Data Exchange (ETDEWEB)

    Katayose, Yusaku, E-mail: katayose@ynu.ac.jp [Department of Physics, Yokohama National University, 79-5 Tokiwadai, Hodogaya-ku, Yokohama, Kanagawa 240-8501 (Japan); Ikeda, Hirokazu [Institute of Space and Astronautical Science (ISAS)/Japan Aerospace Exploration Agency (JAXA), 3-1-1 Yoshinodai, Chuo-ku, Sagamihara, Kanagawa 252-5210 (Japan); Tanaka, Manobu [National Laboratory for High Energy Physics, KEK, 1-1 Oho, Tsukuba, Ibaraki 305-0801 (Japan); Shibata, Makio [Department of Physics, Yokohama National University, 79-5 Tokiwadai, Hodogaya-ku, Yokohama, Kanagawa 240-8501 (Japan)

    2013-01-21

    A front-end application specified integrated circuit (ASIC) is developed with a wide dynamic range amplifier (WDAMP) to read-out signals from a photo-sensor like a photodiode. The WDAMP ASIC consists of a charge sensitive preamplifier, four wave-shaping circuits with different amplification factors and Wilkinson-type analog-to-digital converter (ADC). To realize a wider range, the integrating capacitor in the preamplifier can be changed from 4 pF to 16 pF by a two-bit switch. The output of a preamplifier is shared by the four wave-shaping circuits with four gains of 1, 4, 16 and 64 to adapt the input range of ADC. A 0.25-μm CMOS process (of UMC electronics CO., LTD) is used to fabricate the ASIC with four-channels. The dynamic range of four orders of magnitude is achieved with the maximum range over 20 pC and the noise performance of 0.46 fC + 6.4×10{sup −4} fC/pF. -- Highlights: ► A front-end ASIC is developed with a wide dynamic range amplifier. ► The ASIC consists of a CSA, four wave-shaping circuits and pulse-height-to-time converters. ► The dynamic range of four orders of magnitude is achieved with the maximum range over 20 pC.

  16. Experimental Demonstration of 7 Tb/s Switching Using Novel Silicon Photonic Integrated Circuit

    DEFF Research Database (Denmark)

    Ding, Yunhong; Kamchevska, Valerija; Dalgaard, Kjeld;

    2016-01-01

    We demonstrate BER performance <10^-9 for a 1 Tb/s/core transmission over 7-core fiber and SDM switching using a novel silicon photonic integrated circuit composed of a 7x7 fiber switch and low loss SDM couplers.......We demonstrate BER performance integrated circuit composed of a 7x7 fiber switch and low loss SDM couplers....

  17. Modern approaches to the design of analog-digit integrated circuits based on multilevel simulation methods

    International Nuclear Information System (INIS)

    Modern methods for the design of analog and analog-digit integrated circuits have been analyzed. “Top-down” and “bottom-up” design methods are compared. The advantages of the “top-down” method in the rate of the development and verification of integrated circuits have been demonstrated

  18. 75 FR 51843 - In the Matter of Certain Large Scale Integrated Circuit Semiconductor Chips and Products...

    Science.gov (United States)

    2010-08-23

    ..., based on a complaint filed by Panasonic Corporation (``Panasonic'') of Japan. 75 FR 24742-43. The... COMMISSION In the Matter of Certain Large Scale Integrated Circuit Semiconductor Chips and Products... importation of certain large scale integrated circuit semiconductor chips and products containing same...

  19. A fully-integrated high-compliance voltage SoC for epi-retinal and neural prostheses.

    Science.gov (United States)

    Lo, Yi-Kai; Chen, Kuanfu; Gad, Parag; Liu, Wentai

    2013-12-01

    This paper presents a fully functionally integrated 1024-channel mixed-mode and mixed-voltage system-on-a-chip (SoC) for epi-retinal and neural prostheses. Taking an AC input, an integrated power telemetry circuits is capable of generating multiple DC voltages with a voltage conversion efficiency of 83% at a load of 100 mW without external diodes or separate power integrated circuits, reducing the form factor of the prosthetic device. A wireless DPSK receiver with a novel noise reduction scheme supports a data rate of 2 Mb/s at a bit-error-rate of 2 ×10⁻⁷. The 1024-channel stimulator array meets an output compliance voltage of ±10 V and provides flexible stimulation waveforms. Through chip-clustering, the stimulator array can be further expanded to 4096 channels. This SoC is designed and fabricated in TSMC 0.18 μm high-voltage 32 V CMOS process and occupies a chip area of 5.7 mm × 6.6 mm. Using this SoC, a retinal implant bench-top test system is set up with real-time visual verification. In-vitro experiment conducted in artificial vitreous humor is designed and set-up to investigate stimulation waveforms for better visual resolution. In our in-vivo experiment, a hind-limb paralyzed rat with spinal cord transection and implanted chronic epidural electrodes has been shown to regain stepping and standing abilities using stimulus provided by the SoC. PMID:24473541

  20. High-speed coherent silicon modulator module using photonic integrated circuits: from circuit design to packaged module

    Science.gov (United States)

    Bernabé, S.; Olivier, S.; Myko, A.; Fournier, M.; Blampey, B.; Abraham, A.; Menezo, S.; Hauden, J.; Mottet, A.; Frigui, K.; Ngoho, S.; Frigui, B.; Bila, S.; Marris-Morini, D.; Pérez-Galacho, D.; Brindel, P.; Charlet, G.

    2016-05-01

    Silicon photonics technology is an enabler for the integration of complex circuits on a single chip, for various optical link applications such as routing, optical networks on chip, short range links and long haul transmitters. Quadrature Phase Shift Keying (QPSK) transmitters is one of the typical circuits that can be achieved using silicon photonics integrated circuits. The achievement of 25GBd QPSK transmitter modules requires several building blocks to be optimized: the pn junction used to build a BPSK (Binary Shift Phase Keying) modulator, the RF access and the optical interconnect at the package level. In this paper, we describe the various design steps of a BPSK module and the related tests that are needed at every stage of the fabrication process.

  1. A fully integrated high-Q Whispering-Gallery Wedge Resonator

    CERN Document Server

    Ramiro-Manzano, F; Pavesi, L; Pucker, G; Ghulinyan, M

    2012-01-01

    Microresonator devices which posses ultra-high quality factors are essential for fundamental investigations and applications. Microsphere and microtoroid resonators support remarkably high Q's at optical frequencies, while planarity constrains preclude their integration into functional lightwave circuits. Conventional semiconductor processing can also be used to realize ultra-high-Q's with planar wedge-resonators. Still, their full integration with side-coupled dielectric waveguides remains an issue. Here we show the full monolithic integration of a wedge-resonator/waveguide vertically-coupled system on a silicon chip. In this approach the cavity and the waveguide lay in different planes. This permits to realize the shallow-angle wedge while the waveguide remains intact, allowing therefore to engineer a coupling of arbitrary strength between these two. The precise size-control and the robustness against post-processing operation due to its monolithic integration makes this system a prominent platform for indu...

  2. A monolithic, standard CMOS, fully differential optical receiver with an integrated MSM photodetector

    Institute of Scientific and Technical Information of China (English)

    Yu Changliang; Mao Luhong; Xiao Xindong; Xie Sheng; Zhang Shilin

    2009-01-01

    This paper presents a realization of a silicon-based standard CMOS, fully differential optoelectronic inte grated receiver based on a metal-semiconductor-metal light detector (MSM photodetector). In the optical receiver, two MSM photodetectors are integrated to convert the incident light signal into a pair of fully differential photo generated currents. The optoelectronic integrated receiver was designed and implemented in a chartered 0.35 μm, 3.3 V standard CMOS process. For 850 nm wavelength, it achieves a 1 GHz 3 dB bandwidth due to the MSM pho todetector's low capacitance and high intrinsic bandwidth. In addition, it has a transimpedance gain of 98.75 dBΩ, and an equivalent input integrated referred noise current of 283 nA from 1 Hz up to -3 dB frequency.

  3. Monolithic Microwave Integrated Circuit (MMIC) Phased Array Demonstrated With ACTS

    Science.gov (United States)

    1996-01-01

    Monolithic Microwave Integrated Circuit (MMIC) arrays developed by the NASA Lewis Research Center and the Air Force Rome Laboratory were demonstrated in aeronautical terminals and in mobile or fixed Earth terminals linked with NASA's Advanced Communications Technology Satellite (ACTS). Four K/Ka-band experimental arrays were demonstrated between May 1994 and May 1995. Each array had GaAs MMIC devices at each radiating element for electronic beam steering and distributed power amplification. The 30-GHz transmit array used in uplinks to ACTS was developed by Lewis and Texas Instruments. The three 20-GHz receive arrays used in downlinks from ACTS were developed in cooperation with the Air Force Rome Laboratory, taking advantage of existing Air Force integrated-circuit, active-phased-array development contracts with the Boeing Company and Lockheed Martin Corporation. Four demonstrations, each related to an application of high interest to both commercial and Department of Defense organizations, were conducted. The location, type of link, and the data rate achieved for each of the applications is shown. In one demonstration-- an aeronautical terminal experiment called AERO-X--a duplex voice link between an aeronautical terminal on the Lewis Learjet and ACTS was achieved. Two others demonstrated duplex voice links (and in one case, interactive video links as well) between ACTS and an Army high-mobility, multipurpose wheeled vehicle (HMMWV, or "humvee"). In the fourth demonstration, the array was on a fixed mount and was electronically steered toward ACTS. Lewis served as project manager for all demonstrations and as overall system integrator. Lewis engineers developed the array system including a controller for open-loop tracking of ACTS during flight and HMMWV motion, as well as a laptop data display and recording system used in all demonstrations. The Jet Propulsion Laboratory supported the AERO-X program, providing elements of the ACTS Mobile Terminal. The successful

  4. GaAs integrated circuits and heterojunction devices

    Science.gov (United States)

    Fowlis, Colin

    1986-06-01

    The state of the art of GaAs technology in the U.S. as it applies to digital and analog integrated circuits is examined. In a market projection, it is noted that whereas analog ICs now largely dominate the market, in 1994 they will amount to only 39 percent vs. 57 percent for digital ICs. The military segment of the market will remain the largest (42 percent in 1994 vs. 70 percent today). ICs using depletion-mode-only FETs can be constructed in various forms, the closest to production being BFL or buffered FET logic. Schottky diode FET logic - a lower power approach - can reach higher complexities and strong efforts are being made in this direction. Enhancement type devices appear essential to reach LSI and VLSI complexity, but process control is still very difficult; strong efforts are under way, both in the U.S. and in Japan. Heterojunction devices appear very promising, although structures are fairly complex, and special fabrication techniques, such as molecular beam epitaxy and MOCVD, are necessary. High-electron-mobility-transistor (HEMT) devices show significant performance advantages over MESFETs at low temperatures. Initial results of heterojunction bipolar transistor devices show promise for high speed A/D converter applications.

  5. Efficient Fingerprint Matching Algorithm for Integrated Circuit Cards

    Institute of Scientific and Technical Information of China (English)

    Jian-Wei Yang; Li-Feng Liu; Tian-Zi Jiang

    2004-01-01

    Fingerprint matching is a crucial step in fingerprint identification.Recently,a variety of algorithms for this issue have been developed.Each of them is application situation specific and has its advantages and disadvantages.It is highly desired to develop an efficient fingerprint verification technology for Integrated Circuit(IC)Cards or chips.IC cards have some special characteristics,such as very small storage space and slow processing speed,which hinder the use of most fingerprint matching algorithms in such situations.In order to solve this problem,the paper presents an improved minutia-pattern(minutiae-based)matching algorithm by employing the orientation field of the fingerprint as a new feature.Our algorithm not only inherits the advantages of the general minutia-pattern matching algorithms,but also overcomes their disadvantages.Experimental results show that the proposed algorithm can greatly improve the performance of fingerprint matching in both accuracy and efficiency,and it is very suitable for applications in IC cards.

  6. High Voltage Dielectrophoretic and Magnetophoretic Hybrid Integrated Circuit / Microfluidic Chip

    Science.gov (United States)

    Issadore, David; Franke, Thomas; Brown, Keith A.; Hunt, Thomas P.; Westervelt, Robert M.

    2010-01-01

    A hybrid integrated circuit (IC) / microfluidic chip is presented that independently and simultaneously traps and moves microscopic objects suspended in fluid using both electric and magnetic fields. This hybrid chip controls the location of dielectric objects, such as living cells and drops of fluid, on a 60 × 61 array of pixels that are 30 × 38 μm2 in size, each of which can be individually addressed with a 50 V peak-to-peak, DC to 10 MHz radio frequency voltage. These high voltage pixels produce electric fields above the chip’s surface with a magnitude , resulting in strong dielectrophoresis (DEP) forces . Underneath the array of DEP pixels there is a magnetic matrix that consists of two perpendicular sets of 60 metal wires running across the chip. Each wire can be sourced with 120 mA to trap and move magnetically susceptible objects using magnetophoresis (MP). The DEP pixel array and magnetic matrix can be used simultaneously to apply forces to microscopic objects, such as living cells or lipid vesicles, that are tagged with magnetic nanoparticles. The capabilities of the hybrid IC / microfluidic chip demonstrated in this paper provide important building blocks for a platform for biological and chemical applications. PMID:20625468

  7. Wireless Amperometric Neurochemical Monitoring Using an Integrated Telemetry Circuit

    Science.gov (United States)

    Roham, Masoud; Halpern, Jeffrey M.; Martin, Heidi B.; Chiel, Hillel J.

    2015-01-01

    An integrated circuit for wireless real-time monitoring of neurochemical activity in the nervous system is described. The chip is capable of conducting high-resolution amperometric measurements in four settings of the input current. The chip architecture includes a first-order ΔΣ modulator (ΔΣM) and a frequency-shift-keyed (FSK) voltage-controlled oscillator (VCO) operating near 433 MHz. It is fabricated using the AMI 0.5 μm double-poly triple-metal n-well CMOS process, and requires only one off-chip component for operation. Measured dc current resolutions of ~250 fA, ~1.5 pA, ~4.5 pA, and ~17 pA were achieved for input currents in the range of ±5, ±37, ±150, and ±600 nA, respectively. The chip has been interfaced with a diamond-coated, quartz-insulated, microneedle, tungsten electrode, and successfully recorded dopamine concentration levels as low as 0.5 μM wirelessly over a transmission distance of ~0.5 m in flow injection analysis experiments. PMID:18990633

  8. Tomography of integrated circuit interconnect with an electromigration void

    Energy Technology Data Exchange (ETDEWEB)

    Levine, Zachary H. [National Institute of Standards and Technology, Gaithersburg, Maryland 20899-8410 (United States); Rensselaer Polytechnic Institute, Troy, New York 12180-3590 (United States); Kalukin, Andrew R. [National Institute of Standards and Technology, Gaithersburg, Maryland 20899-8410 (United States); Kuhn, Markus [Intel Corporation RA1-329, 5200 Northeast Elam Young Parkway, Hillsboro, Oregon 74124 (United States); Frigo, Sean P. [Advanced Photon Source, Argonne National Laboratory, 9700 South Cass Avenue, Argonne, Illinois 60439 (United States); McNulty, Ian [Advanced Photon Source, Argonne National Laboratory, 9700 South Cass Avenue, Argonne, Illinois 60439 (United States); Retsch, Cornelia C. [Advanced Photon Source, Argonne National Laboratory, 9700 South Cass Avenue, Argonne, Illinois 60439 (United States); Wang, Yuxin [Advanced Photon Source, Argonne National Laboratory, 9700 South Cass Avenue, Argonne, Illinois 60439 (United States); Arp, Uwe [National Institute of Standards and Technology, Gaithersburg, Maryland 20899-8410 (United States); Lucatorto, Thomas B. [National Institute of Standards and Technology, Gaithersburg, Maryland 20899-8410 (United States); Ravel, Bruce D. [National Institute of Standards and Technology, Gaithersburg, Maryland 20899-8410 (United States)] (and others)

    2000-05-01

    An integrated circuit interconnect was subject to accelerated-life test conditions to induce an electromigration void. The silicon substrate was removed, leaving only the interconnect test structure encased in silica. We imaged the sample with 1750 eV photons using the 2-ID-B scanning transmission x-ray microscope at the Advanced Photon Source, a third-generation synchrotron facility. Fourteen views through the sample were obtained over a 170 degree sign range of angles (with a 40 degree sign gap) about a single rotation axis. Two sampled regions were selected for three-dimensional reconstruction: one of the ragged end of a wire depleted by the void, the other of the adjacent interlevel connection (or ''via''). We applied two reconstruction techniques: the simultaneous iterative reconstruction technique and a Bayesian reconstruction technique, the generalized Gaussian Markov random field method. The stated uncertainties are total, with one standard deviation, which resolved the sample to 200{+-}70 and 140{+-}30 nm, respectively. The tungsten via is distinguished from the aluminum wire by higher absorption. Within the void, the aluminum is entirely depleted from under the tungsten via. The reconstructed data show the applicability of this technique to three-dimensional imaging of buried defects in submicrometer structures relevant to the microelectronics industry. (c) 2000 American Institute of Physics.

  9. PETRIC - A positron emission tomography readout integrated circuit

    Energy Technology Data Exchange (ETDEWEB)

    Pedrali-Noy, Marzio; Gruber, Gregory; Krieger, Bradley; Mandelli, Emmanuele; Meddeler, Gerrit; Moses, William; Rosso, Valeria

    2000-11-05

    We present architecture, critical design issues and performance measurements of PETRIC, a 64-channel mixed signal front-end integrated circuit (IC) for reading out a photodiode (PD) array coupled with LSO scintillator crystals for a medical imaging application (PET). Each channel consists of a low noise charge sensitive pre-amplifier (CSA), an RC-CR pulse shaper and a winner-take-all (WTA) multiplexer that selects the channel with the largest input signal. Triggered by an external timing signal, a switch opens and a capacitor stores the peak voltage of the winner channel. The shaper rise and fall times are adjustable by means of external current inputs over a continuous range of 0.7 (mu)s to 9 (mu)s. Power consumption is 5.4 mW per channel, measured Equivalent Noise Charge (ENC) at 1 (mu)s peaking time. Zero leakage current is 33 rms electrons plus 7.3 rms electrons per pF of input capacitance. Design is fabricated in 0.5 (mu)m 3.3V CMOS technology.

  10. Neural Networks Integrated Circuit for Biomimetics MEMS Microrobot

    Directory of Open Access Journals (Sweden)

    Ken Saito

    2014-06-01

    Full Text Available In this paper, we will propose the neural networks integrated circuit (NNIC which is the driving waveform generator of the 4.0, 2.7, 2.5 mm, width, length, height in size biomimetics microelectromechanical systems (MEMS microrobot. The microrobot was made from silicon wafer fabricated by micro fabrication technology. The mechanical system of the robot was equipped with small size rotary type actuators, link mechanisms and six legs to realize the ant-like switching behavior. The NNIC generates the driving waveform using synchronization phenomena such as biological neural networks. The driving waveform can operate the actuators of the MEMS microrobot directly. Therefore, the NNIC bare chip realizes the robot control without using any software programs or A/D converters. The microrobot performed forward and backward locomotion, and also changes direction by inputting an external single trigger pulse. The locomotion speed of the microrobot was 26.4 mm/min when the step width was 0.88 mm. The power consumption of the system was 250 mWh when the room temperature was 298 K.

  11. Full Wave Simulation of Integrated Circuits Using Hybrid Numerical Methods

    Science.gov (United States)

    Tan, Jilin

    Transmission lines play an important role in digital electronics, and in microwave and millimeter-wave circuits. Analysis, modeling, and design of transmission lines are critical to the development of the circuitry in the chip, subsystem, and system levels. In the past several decays, at the EM modeling level, the quasi-static approximation has been widely used due to its great simplicity. As the clock rates increase, the inter-connect effects such as signal delay, distortion, dispersion, reflection, and crosstalk, limit the performance of microwave systems. Meanwhile, the quasi-static approach loses its validity for some complex system structures. Since the successful system design of the PCB, MCM, and the chip packaging, rely very much on the computer aided EM level modeling and simulation, many new methods have been developed, such as the full wave approach, to guarantee the successful design. Many difficulties exist in the rigorous EM level analysis. Some of these include the difficulties in describing the behavior of the conductors with finite thickness and finite conductivity, the field singularity, and the arbitrary multilayered multi-transmission lines structures. This dissertation concentrates on the full wave study of the multi-conductor transmission lines with finite conductivity and finite thickness buried in an arbitrary lossy multilayered environment. Two general approaches have been developed. The first one is the integral equation method in which the dyadic Green's function for arbitrary layered media has been correctly formulated and has been tested both analytically and numerically. By applying this method, the double layered high dielectric permitivitty problem and the heavy dielectrical lossy problem in multilayered media in the CMOS circuit design have been solved. The second approach is the edge element method. In this study, the correct functional for the two dimensional propagation problem has been successfully constructed in a rigorous way

  12. Diagnosis of soft faults in analog integrated circuits based on fractional correlation

    Institute of Scientific and Technical Information of China (English)

    Deng Yong; Shi Yibing; Zhang Wei

    2012-01-01

    Aiming at the problem of diagnosing soft faults in analog integrated circuits,an approach based on fractional correlation is proposed.First,the Volterra series of the circuit under test (CUT) decomposed by the fractional wavelet packet are used to calculate the fractional correlation functions.Then,the calculated fractional correlation functions are used to form the fault signatures of the CUT.By comparing the fault signatures,the different soft faulty conditions of the CUT are identified and the faults are located.Simulations of benchmark circuits illustrate the proposed method and validate its effectiveness in diagnosing soft faults in analog integrated circuits.

  13. Integrated reconfigurable high-voltage transmitting circuit for CMUTs

    DEFF Research Database (Denmark)

    Llimos Muntal, Pere; Larsen, Dennis Øland; Jørgensen, Ivan Harald Holger;

    2015-01-01

    In this paper a high-voltage transmitting circuit aimed for capacitive micromachined ultrasonic transducers (CMUTs) used in scanners for medical applications is designed and implemented in a 0.35 μm high-voltage CMOS process. The transmitting circuit is reconfigurable externally making it able...... to drive a wide variety of CMUTs. The transmitting circuit can generate several pulse shapes with voltages up to 100 V, maximum pulse range of 50 V, frequencies up to 5 MHz and different driving slew rates. Measurements are performed on the circuit in order to assess its functionality and power consumption...... performance. The design occupies an on-chip area of 0.938 mm2 and the power consumption of a 128-element transmitting circuit array that would be used in an portable ultrasound scanner is found to be a maximum of 181 mW....

  14. Hybrid Integration of Graphene Analog and Silicon Complementary Metal-Oxide-Semiconductor Digital Circuits.

    Science.gov (United States)

    Hong, Seul Ki; Kim, Choong Sun; Hwang, Wan Sik; Cho, Byung Jin

    2016-07-26

    We demonstrate a hybrid integration of a graphene-based analog circuit and a silicon-based digital circuit in order to exploit the strengths of both graphene and silicon devices. This mixed signal circuit integration was achieved using a three-dimensional (3-D) integration technique where a graphene FET multimode phase shifter is fabricated on top of a silicon complementary metal-oxide-semiconductor field-effect transistor (CMOS FET) ring oscillator. The process integration scheme presented here is compatible with the conventional silicon CMOS process, and thus the graphene circuit can successfully be integrated on current semiconductor technology platforms for various applications. This 3-D integration technique allows us to take advantage of graphene's excellent inherent properties and the maturity of current silicon CMOS technology for future electronics. PMID:27403730

  15. Electrothermal Analysis of Three-Dimensional Integrated Circuits

    Science.gov (United States)

    Harris, Theodore Robert

    2011-12-01

    Transient electro-thermal simulation of a three dimensional integrated circuit (3DIC) is reported that uses a cell-based simulation to provide a selected transistor thermal profile while providing advantages of hierarchical simulation. Due to CPU and memory limitations, full transistor electro-thermal simulations on a useful scale are not possible. Standard cells are considered on a per-instance basis and modeled with electro-thermal macro-models developed in a multi-physics simulator. Simulations are compared favorably to measurements for a token-generating 3DIC clocking at a maximum of 1 GHz. The 3DIC, which is composed of 9 by 3 layers of repetitive frequency multipliers and dividers, was fabricated with the Massachusetts Institute of Technology Lincoln Laboratory (MITLL) 3DIC process. Measurements indicated a linear rise in temperature of the active areas over a range of applied background ambient temperatures. An average of 7.5 K change in temperature was measured across dense areas of circuitry. For thermal simulation, the physical characteristics of the 3DIC were extracted from flattened OpenAccess layout files. Material parameters, connections, and geometries were considered in order to create a more physically accurate resistive thermal mesh. Physical thermal networks extracted with resolutions of 10 mum and 5 mum connect thermal terminals of the electrothermal macromodel cell elements to active layers yielding temporal and spatial simulated dynamic thermal results in three dimensions. Coupled with model-order reduction techniques, hierarchical dynamic electrothermal simulation of large 3DICs is shown to be tractable, yielding spatial and temporal selected transistor-level thermal profiles.

  16. Integrated Power Flow and Short Circuit Calculation Method for Distribution Network with Inverter Based Distributed Generation

    OpenAIRE

    Shan Yang; Xiangqian Tong

    2016-01-01

    Power flow calculation and short circuit calculation are the basis of theoretical research for distribution network with inverter based distributed generation. The similarity of equivalent model for inverter based distributed generation during normal and fault conditions of distribution network and the differences between power flow and short circuit calculation are analyzed in this paper. Then an integrated power flow and short circuit calculation method for distribution network with inverte...

  17. 22.8 GHz Substrate Integrated Waveguide Analog Frequency Divide-by-3 Circuit

    OpenAIRE

    Georgiadis, Apostolos; Collado, Ana; Niotaki, Kyriaki

    2015-01-01

    A 22.8 GHz analog frequency divide-by-3 circuit is presented based on an injection locked oscillator. Substrate integrated waveguide (SIW) technology is used to implement the input and output sections of the frequency divider circuit. The input SIW section at the gate of the active device permits the introduction of the injection signal at the third harmonic frequency of the oscillator, while the output section is designed to maximize the DC-RF conversion efficiency of the oscillator circuit....

  18. High-speed Integrated Circuits for electrical/Optical Interfaces

    DEFF Research Database (Denmark)

    Jespersen, Christoffer Felix

    2008-01-01

    This thesis is a continuation of the effort to increase the bandwidth of communicationnetworks. The thesis presents the results of the design of several high-speed electrical ircuits for an electrical/optical interface. These circuits have been a contribution to the ESTA project in collaboration...... circuits at the receiver interface, though VCOs are also found in the transmitter where a multitude of independent sources have to be mutually synchronized before multiplexing. The circuits are based on an InP DHBT process (VIP-2) supplied by Vitesse and made publicly available as MPW. The VIP-2 process...... represents the avant-garde of InP technology, with ft and fmax well above 300 GHz. Principles of high speed design are presented and described as a useful background before proceeding to circuits. A static divider is used as an example to illustrate many of the design principles. Theory and fundamentals...

  19. Resonance modes in coplanar lines with integrated Josephson circuits

    Science.gov (United States)

    Shvetsov, A. V.; Satanin, A. M.; Mironov, V. A.; Il'ichev, E.

    2013-11-01

    The propagation of microwave radiation in co-planar superconducting lines with Josephson circuits (microresonators) of various configurations is investigated. It is shown that dips in the frequency dependence of the transmission power of the waveguide line modes are associated with local modes of the circuit. The dependencies of shape and position of the dips on an external magnetic field and applied power are found. The calculation results can be used for developing modern cryoelectronic microwave superconducting devices.

  20. A Fully Integrated Nanosystem of Semiconductor Nanowires for Direct Solar Water Splitting

    Energy Technology Data Exchange (ETDEWEB)

    Liu, Chong; Tang, Jinyao; Chen, HaoMing; Liu, Bin; Yang, Peidong

    2013-02-21

    Artificial photosynthesis, the biomimetic approach to converting sunlight?s energy directly into chemical fuels, aims to imitate nature by using an integrated system of nanostructures, each of which plays a specific role in the sunlight-to-fuel conversion process. Here we describe a fully integrated system of nanoscale photoelectrodes assembled from inorganic nanowires for direct solar water splitting. Similar to the photosynthetic system in a chloroplast, the artificial photosynthetic system comprises two semiconductor light absorbers with large surface area, an interfacial layer for charge transport, and spatially separated cocatalysts to facilitate the water reduction and oxidation. Under simulated sunlight, a 0.12percent solar-to-fuel conversion efficiency is achieved, which is comparable to that of natural photosynthesis. The result demonstrates the possibility of integrating material components into a functional system that mimics the nanoscopic integration in chloroplasts. It also provides a conceptual blueprint of modular design that allows incorporation of newly discovered components for improved performance.

  1. Flip-chip integration of tilted VCSELs onto a silicon photonic integrated circuit.

    Science.gov (United States)

    Lu, Huihui; Lee, Jun Su; Zhao, Yan; Scarcella, Carmelo; Cardile, Paolo; Daly, Aidan; Ortsiefer, Markus; Carroll, Lee; O'Brien, Peter

    2016-07-25

    In this article we describe a cost-effective approach for hybrid laser integration, in which vertical cavity surface emitting lasers (VCSELs) are passively-aligned and flip-chip bonded to a Si photonic integrated circuit (PIC), with a tilt-angle optimized for optical-insertion into standard grating-couplers. A tilt-angle of 10° is achieved by controlling the reflow of the solder ball deposition used for the electrical-contacting and mechanical-bonding of the VCSEL to the PIC. After flip-chip integration, the VCSEL-to-PIC insertion loss is -11.8 dB, indicating an excess coupling penalty of -5.9 dB, compared to Fibre-to-PIC coupling. Finite difference time domain simulations indicate that the penalty arises from the relatively poor match between the VCSEL mode and the grating-coupler. PMID:27464079

  2. Flip-chip integration of tilted VCSELs onto a silicon photonic integrated circuit.

    Science.gov (United States)

    Lu, Huihui; Lee, Jun Su; Zhao, Yan; Scarcella, Carmelo; Cardile, Paolo; Daly, Aidan; Ortsiefer, Markus; Carroll, Lee; O'Brien, Peter

    2016-07-25

    In this article we describe a cost-effective approach for hybrid laser integration, in which vertical cavity surface emitting lasers (VCSELs) are passively-aligned and flip-chip bonded to a Si photonic integrated circuit (PIC), with a tilt-angle optimized for optical-insertion into standard grating-couplers. A tilt-angle of 10° is achieved by controlling the reflow of the solder ball deposition used for the electrical-contacting and mechanical-bonding of the VCSEL to the PIC. After flip-chip integration, the VCSEL-to-PIC insertion loss is -11.8 dB, indicating an excess coupling penalty of -5.9 dB, compared to Fibre-to-PIC coupling. Finite difference time domain simulations indicate that the penalty arises from the relatively poor match between the VCSEL mode and the grating-coupler.

  3. A Novel Analog Integrated Circuit Design Course Covering Design, Layout, and Resulting Chip Measurement

    Science.gov (United States)

    Lin, Wei-Liang; Cheng, Wang-Chuan; Wu, Chen-Hao; Wu, Hai-Ming; Wu, Chang-Yu; Ho, Kuan-Hsuan; Chan, Chueh-An

    2010-01-01

    This work describes a novel, first-year graduate-level analog integrated circuit (IC) design course. The course teaches students analog circuit design; an external manufacturer then produces their designs in three different silicon chips. The students, working in pairs, then test these chips to verify their success. All work is completed within…

  4. Design and Fabrication of a Monolithic Optoelectronic Integrated Circuit Chip Based on CMOS Compatible Technology

    Institute of Scientific and Technical Information of China (English)

    GUO Wei-Feng; ZHAO Yong; WANG Wan-Jun; SHAO Hai-Feng; YANG Jian-Yi; JIANG Xiao-Qing

    2012-01-01

    A monolithic optoelectronic integrated circuit chip on a silicon-on-insulator is designed and fabricated based on complementary metal oxide semiconductor compatible technology.The chip integrates an optical Mach-Zehnder modulator (MZM) and a CMOS driving circuit with the amplification function.Test results show that the extinction ratio of the MZM is close to 20dB and the small-signal gain of the CMOS driving circuit is about 26.9dB.A 50m V 10 MHz sine wave signal is amplified by the driving circuit,and then drives the MZM successfully.%A monolithic optoelectronic integrated circuit chip on a silicon-on-insulator is designed and fabricated based on complementary metal oxide semiconductor compatible technology. The chip integrates an optical Mach-Zehnder modulator (MZM) and a CMOS driving circuit with the amplification function. Test results show that the extinction ratio of the MZM is close to 20 dB and the small-signal gain of the CMOS driving circuit is about 26.9dB. A 50mV 10MHz sine wave signal is amplified by the driving circuit, and then drives the MZM successfully.

  5. Fully integrated patterned carbon nanotube strain sensors on flexible sensing skin substrates for structural health monitoring

    Science.gov (United States)

    Burton, Andrew R.; Kurata, Masahiro; Nishino, Hiromichi; Lynch, Jerome P.

    2016-04-01

    New advances in nanotechnology and material processing is creating opportunities for the design and fabrication of a new generation of thin film sensors that can used to assess structural health. In particular, thin film sensors attached to large areas of the structure surface has the potential to provide spatially rich data on the performance and health of a structure. This study focuses on the development of a fully integrated strain sensor that is fabricated on a flexible substrate for potentially use in sensing skins. This is completed using a carbon nanotube-polymer composite material that is patterned on a flexible polyimide substrate using optical lithography. The piezoresistive carbon nanotube elements are integrated into a complete sensing system by patterning copper electrodes and integrating off-the-shelf electrical components on the flexible film for expanded functionality. This diverse material utilization is realized in a versatile process flow to illustrate a powerful toolbox for sensing severity, location, and failure mode of damage on structural components. The fully integrated patterned carbon nanotube strain sensor is tested on a quarter-scale, composite beam column connection. The results and implications for future structural damage detection are discussed.

  6. RNA signal amplifier circuit with integrated fluorescence output.

    Science.gov (United States)

    Akter, Farhima; Yokobayashi, Yohei

    2015-05-15

    We designed an in vitro signal amplification circuit that takes a short RNA input that catalytically activates the Spinach RNA aptamer to produce a fluorescent output. The circuit consists of three RNA strands: an internally blocked Spinach aptamer, a fuel strand, and an input strand (catalyst), as well as the Spinach aptamer ligand 3,5-difluoro-4-hydroxylbenzylidene imidazolinone (DFHBI). The input strand initially displaces the internal inhibitory strand to activate the fluorescent aptamer while exposing a toehold to which the fuel strand can bind to further displace and recycle the input strand. Under a favorable condition, one input strand was able to activate up to five molecules of the internally blocked Spinach aptamer in 185 min at 30 °C. The simple RNA circuit reported here serves as a model for catalytic activation of arbitrary RNA effectors by chemical triggers.

  7. Waveguide Phase Modulator for Integrated Planar Lightwave Circuits in KTP Project

    Data.gov (United States)

    National Aeronautics and Space Administration — This SBIR Phase II effort proposes the development and integration of a Planar Lightwave Circuit (PLC) into an all fiber-based seed laser system used in high...

  8. Development of pixel readout integrated circuits for extreme rate and radiation

    CERN Document Server

    Garcia-Sciveres, M; CERN. Geneva. The LHC experiments Committee; LHCC

    2013-01-01

    Letter of Intent for RD Collaboration Proposal focused on development of a next generation pixel readout integrated circuits needed for high luminosity LHC detector upgrades. Brings together ATLAS and CMS pixel chip design communities.

  9. An Integrated-Circuit Temperature Sensor for Calorimetry and Differential Temperature Measurement.

    Science.gov (United States)

    Muyskens, Mark A.

    1997-01-01

    Describes the application of an integrated-circuit (IC) chip which provides an easy-to-use, inexpensive, rugged, computer-interfaceable temperature sensor for calorimetry and differential temperature measurement. Discusses its design and advantages. (JRH)

  10. A review of the technology and process on integrated circuits failure analysis applied in communications products

    Science.gov (United States)

    Ming, Zhimao; Ling, Xiaodong; Bai, Xiaoshu; Zong, Bo

    2016-02-01

    The failure analysis of integrated circuits plays a very important role in the improvement of the reliability in communications products. This paper intends to mainly introduce the failure analysis technology and process of integrated circuits applied in the communication products. There are many technologies for failure analysis, include optical microscopic analysis, infrared microscopic analysis, acoustic microscopy analysis, liquid crystal hot spot detection technology, optical microscopic analysis technology, micro analysis technology, electrical measurement, microprobe technology, chemical etching technology and ion etching technology. The integrated circuit failure analysis depends on the accurate confirmation and analysis of chip failure mode, the search of the root failure cause, the summary of failure mechanism and the implement of the improvement measures. Through the failure analysis, the reliability of integrated circuit and rate of good products can improve.

  11. A BIST GENERATOR CAD TOOL FOR NUMERIC INTEGRATED CIRCUITS

    Directory of Open Access Journals (Sweden)

    Chiraz Khedhiri

    2011-07-01

    Full Text Available This paper describes a training and research tool for learning basic issues related to BIST (Built-In Self-Test generator. The main didactic aim of the tool is presenting complicated concepts in a comprehensivegraphical and analytical way. The paper describes a computer-aided design (CAD that is used to generateautomatically the BIST to any digital circuit. This software technique attempts to reduce the amount ofextra hardware and cost of the circuit.In order to make our software being easily available, we used the Java platform, which is supported bymost operating systems. The multi-platform JAVA runtime environment allows for easy access and usage ofthe tool.

  12. A NEW TRANSISTOR SIZING APPROACH FOR DIGITAL INTEGRATED CIRCUITS USING FIREFLY ALGORITHM

    Directory of Open Access Journals (Sweden)

    Nima Talebpour Anaraki

    2015-12-01

    Full Text Available Due to the fact that, the power consumption and speed of a VLSI circuit are dependent on the transistor sizes, efficient transistor sizing is a new challenge for VLSI circuit designers. However, evolutionary computation can be successfully used for complex VLSI transistor sizing which reduces the time to market and enables the designer to find the optimized solutions for a non-linear and complex circuit design process. In this paper, a new digital integrated circuit design approach is proposed based on the firefly artificial intelligence optimization algorithm. In order to justify the effectiveness of the proposed algorithm in the design of VLSI circuits, an inverter (NOT gate is designed and optimized by the proposed algorithm. As the simulation results show, the inverter circuit has a very good performance for power and delay parameters.

  13. Real Time Automated Counterfeit Integrated Circuit Detection using X-ray Microscopy

    OpenAIRE

    Mahmood, Kaleel; Latorre Carmona, Pedro; Shahbazmohamadi, Sina; Pla Bañón, Filiberto; Javidi, Bahram

    2015-01-01

    Determining the authenticity of integrated circuits is paramount to preventing counterfeit and malicious hardware from being used in critical military, healthcare, aerospace, consumer, and industry applications. Existing techniques to distinguish between authentic and counterfeit integrated circuits (ICs) often include destructive testing requiring subject matter experts. We present a nondestructive technique to detect ICs using x-ray microscopy and advanced imaging analysis with different pa...

  14. Sensors, Circuits, and Satellites - NGSS at it's best: the integration of three dimensions with NASA science

    Science.gov (United States)

    Butcher, G. J.; Roberts-Harris, D.

    2013-12-01

    A set of innovative classroom lessons were developed based on informal learning activities in the 'Sensors, Circuits, and Satellites' kit manufactured by littleBits™ Electronics that are designed to lead students through a logical science content storyline about energy using sound and light and fully implements an integrated approach to the three dimensions of the Next Generation of Science Standards (NGSS). This session will illustrate the integration of NGSS into curriculum by deconstructing lesson design to parse out the unique elements of the 3 dimensions of NGSS. We will demonstrate ways in which we have incorporated the NGSS as we believe they were intended. According to the NGSS, 'The real innovation in the NGSS is the requirement that students are required to operate at the intersection of practice, content, and connection. Performance expectations are the right way to integrate the three dimensions. It provides specificity for educators, but it also sets the tone for how science instruction should look in classrooms. (p. 3). The 'Sensors, Circuits, and Satellites' series of lessons accomplishes this by going beyond just focusing on the conceptual knowledge (the disciplinary core ideas) - traditionally approached by mapping lessons to standards. These lessons incorporate the other 2 dimensions -cross-cutting concepts and the 8-practices of Sciences and Engineering-via an authentic and exciting connection to NASA science, thus implementing the NGSS in the way they were designed to be used: practices and content with the crosscutting concepts. When the NGSS are properly integrated, students are engaged in science and engineering content through the coupling of practice, content and connection. In the past, these two dimensions have been separated as distinct entities. We know now that coupling content and practices better demonstrates what goes on in real world science and engineering. We set out to accomplish what is called for in NGSS by integrating these

  15. Principal working group 3 on primary circuit integrity

    International Nuclear Information System (INIS)

    The main themes of this conference (13 papers) are: operating experience on leakages and failures in nuclear power plant piping, coolant circuits and steam generator tubes, probabilistic estimation and risk assessment, system failure analysis, leakage events and frequency, leak rate models and crack propagation mechanics, damage mechanisms and rupture probability

  16. CMOS analog integrated circuits high-speed and power-efficient design

    CERN Document Server

    Ndjountche, Tertulien

    2011-01-01

    High-speed, power-efficient analog integrated circuits can be used as standalone devices or to interface modern digital signal processors and micro-controllers in various applications, including multimedia, communication, instrumentation, and control systems. New architectures and low device geometry of complementary metaloxidesemiconductor (CMOS) technologies have accelerated the movement toward system on a chip design, which merges analog circuits with digital, and radio-frequency components. CMOS: Analog Integrated Circuits: High-Speed and Power-Efficient Design describes the important tren

  17. A novel fully-integrated miniature six-axis force/torque sensor

    Institute of Scientific and Technical Information of China (English)

    Wang Jiali; Xie Zongwu; Liu Hong; Jiang Li; Gao Xiaohui

    2006-01-01

    This paper presents a new designed miniature six DOF (degree of freedom) force/torque sensor.This sensor is fully integrated with a micro DSP (digital signal processor), so all the signal conditioning,A/D, decoupling, digital-signals serial output are performed in the sensor. Some experimental results are presented to demonstrate the capability of the proposed design. Finally, a neural network was used for decoupling the interacting signals, compared with the conventional method using the inverse matrix, this new method is more accurate.

  18. SEMICONDUCTOR INTEGRATED CIRCUITS: Accurate metamodels of device parameters and their applications in performance modeling and optimization of analog integrated circuits

    Science.gov (United States)

    Tao, Liang; Xinzhang, Jia; Junfeng, Chen

    2009-11-01

    Techniques for constructing metamodels of device parameters at BSIM3v3 level accuracy are presented to improve knowledge-based circuit sizing optimization. Based on the analysis of the prediction error of analytical performance expressions, operating point driven (OPD) metamodels of MOSFETs are introduced to capture the circuit's characteristics precisely. In the algorithm of metamodel construction, radial basis functions are adopted to interpolate the scattered multivariate data obtained from a well tailored data sampling scheme designed for MOSFETs. The OPD metamodels can be used to automatically bias the circuit at a specific DC operating point. Analytical-based performance expressions composed by the OPD metamodels show obvious improvement for most small-signal performances compared with simulation-based models. Both operating-point variables and transistor dimensions can be optimized in our nesting-loop optimization formulation to maximize design flexibility. The method is successfully applied to a low-voltage low-power amplifier.

  19. High-voltage integrated transmitting circuit with differential driving for CMUTs

    DEFF Research Database (Denmark)

    Llimos Muntal, Pere; Larsen, Dennis Øland; Færch, Kjartan Ullitz;

    2016-01-01

    In this paper, a high-voltage integrated differential transmitting circuit for capacitive micromachined ultrasonic transducers (CMUTs) used in portable ultrasound scanners is presented. Due to its application, area and power consumption are critical and need to be minimized. The circuitry...... is designed and implemented in AMS 0.35 μ m high-voltage process. Measurements are performed on the fabricated integrated circuit in order to assess its performance. The transmitting circuit consists of a low-voltage control logic, pulse-triggered level shifters and a differential output stage that generates...... conditions is 0.936 mW including the load. The integrated circuits measured prove to be consistent and robust to local process variations by measurements....

  20. Fully transparent quantum dot light-emitting diode integrated with graphene anode and cathode.

    Science.gov (United States)

    Seo, Jung-Tak; Han, Junebeom; Lim, Taekyung; Lee, Ki-Heon; Hwang, Jungseek; Yang, Heesun; Ju, Sanghyun

    2014-12-23

    A fully transparent quantum dot light-emitting diode (QD-LED) was fabricated by incorporating two types (anode and cathode) of graphene-based electrodes, which were controlled in their work functions and sheet resistances. Either gold nanoparticles or silver nanowires were inserted between layers of graphene to control the work function, whereas the sheet resistance was determined by the number of graphene layers. The inserted gold nanoparticles or silver nanowires in graphene films caused a charge transfer and changed the work function to 4.9 and 4.3 eV, respectively, from the original work function (4.5 eV) of pristine graphene. Moreover the sheet resistance values for the anode and cathode electrodes were improved from ∼63,000 to ∼110 Ω/sq and from ∼100,000 to ∼741 Ω/sq as the number of graphene layers increased from 1 to 12 and from 1 to 8, respectively. The main peak wavelength, luminance, current efficiency, and optical transmittance of the fully transparent QD-LED integrated with graphene anode and cathode were 535 nm, ∼358 cd/m2, ∼0.45 cd/A, and 70-80%, respectively. The findings of the study are expected to lay a foundation for the production of high-efficiency, fully transparent, and flexible displays using graphene-based electrodes. PMID:25426762

  1. Note: Fully integrated 3.2 Gbps quantum random number generator with real-time extraction

    Science.gov (United States)

    Zhang, Xiao-Guang; Nie, You-Qi; Zhou, Hongyi; Liang, Hao; Ma, Xiongfeng; Zhang, Jun; Pan, Jian-Wei

    2016-07-01

    We present a real-time and fully integrated quantum random number generator (QRNG) by measuring laser phase fluctuations. The QRNG scheme based on laser phase fluctuations is featured for its capability of generating ultra-high-speed random numbers. However, the speed bottleneck of a practical QRNG lies on the limited speed of randomness extraction. To close the gap between the fast randomness generation and the slow post-processing, we propose a pipeline extraction algorithm based on Toeplitz matrix hashing and implement it in a high-speed field-programmable gate array. Further, all the QRNG components are integrated into a module, including a compact and actively stabilized interferometer, high-speed data acquisition, and real-time data post-processing and transmission. The final generation rate of the QRNG module with real-time extraction can reach 3.2 Gbps.

  2. A fully integrated 3.5 GHz CMOS differential power amplifier driver

    Science.gov (United States)

    Xiaodong, Xu; Haigang, Yang; Tongqiang, Gao; Hongfeng, Zhang

    2013-07-01

    A fully integrated CMOS differential power amplifier driver (PAD) is proposed for WiMAX applications. In order to fulfill the differential application requirements, a transmission line transformer is used as the output matching network. A differential inductance constitutes an inter-stage matching network. Meanwhile, an on chip balun realizes input matching as well as single-end to differential conversion. The PAD is fabricated in a 0.13 μm RFCMOS process. The chip size is 1.1 × 1.1 mm2 with all of the matching network integrated on chip. The saturated power is around 10 dBm and power gain is about 12 dB.

  3. Fully Integrated Approach to Compute Vibrationally Resolved Optical Spectra: From Small Molecules to Macrosystems.

    Science.gov (United States)

    Barone, Vincenzo; Bloino, Julien; Biczysko, Malgorzata; Santoro, Fabrizio

    2009-03-10

    A general and effective time-independent approach to compute vibrationally resolved electronic spectra from first principles has been integrated into the Gaussian computational chemistry package. This computational tool offers a simple and easy-to-use way to compute theoretical spectra starting from geometry optimization and frequency calculations for each electronic state. It is shown that in such a way it is straightforward to combine calculation of Franck-Condon integrals with any electronic computational model. The given examples illustrate the calculation of absorption and emission spectra, all in the UV-vis region, of various systems from small molecules to large ones, in gas as well as in condensed phases. The computational models applied range from fully quantum mechanical descriptions to discrete/continuum quantum mechanical/molecular mechanical/polarizable continuum models. PMID:26610221

  4. A BIST GENERATOR CAD TOOL FOR NUMERIC INTEGRATED CIRCUITS

    Directory of Open Access Journals (Sweden)

    Chiraz Khedhiri

    2011-06-01

    Full Text Available This paper describes a training and research tool for learning basic issues related to BIST (Built-In Self-Test generator. The main didactic aim of the tool is presenting complicated concepts in a comprehensive graphical and analytical way. The paper describes a computer-aided design (CAD that is used to generate automatically the BIST to any digital circuit. This software technique attempts to reduce the amount of extra hardware and cost of the circuit.In order to make our software being easily available, we used the Java platform, which is supported by most operating systems. The multi-platform JAVA run time environment allows for easy access and usage of the tool.

  5. Cryogenic readout integrated circuits for submillimeter-wave camera

    International Nuclear Information System (INIS)

    The development of cryogenic readout circuits for Superconducting Tunneling Junction (Sj) direct detectors for submillimeter wave is presented. A SONY n-channel depletion-mode GaAs Junction Field Effect Transistor (JFET) is a candidate for circuit elements of the preamplifier. We measured electrical characteristics of the GaAs JFETs in the temperature range between 0.3 and 4.2K, and found that the GaAs JFETs work with low power consumption of a few microwatts, and show good current-voltage characteristics without cryogenic anomalies such as kink phenomena or hysteresis behaviors. Furthermore, measurements at 0.3K show that the input referred noise is as low as 0.6μV/Hz at 1Hz. Based on these results and noise calculations, we estimate that a Capacitive Transimpedance Amplifier with the GaAs JFETs will have low noise and STJ detectors will operate below background noise limit

  6. A Multi-Gigahertz Analog Transient Recorder Integrated Circuit

    CERN Document Server

    Kleinfelder, Stuart A

    2015-01-01

    A monolithic multi-channel analog transient recorder, implemented using switched capacitor sample-and-hold circuits and a high-speed analogically-adjustable delay-line-based write clock, has been designed, fabricated and tested. The 2.1 by 6.9 mm layout, in 1.2 micron CMOS, includes over 31,000 transistors and 2048 double polysilicon capacitors. The circuit contains four parallel channels, each with a 512 deep switched-capacitor sample-and-hold system. A 512 deep edge sensitive tapped active delay line uses look-ahead and 16 way interleaving to develop the 512 sample and hold clocks, each as little as 3.2 ns wide and 200 ps apart. Measurements of the device have demonstrated 5 GHz maximum sample rate, at least 350 MHz bandwidth, an extrapolated rms aperture uncertainty per sample of 0.7 ps, and a signal to rms noise ratio of 2000:1.

  7. Integrated optical and electronic interconnect printed circuit board manufacturing

    OpenAIRE

    Selviah, D. R.; Fernández, F. A.; Papakonstantinou, I.; Wang, K.; Bagshiahi, H.; Walker, A. C.; McCarthy, A.; Suyal, H; Hutt, D.A.; Conway, P. P.; Chappell, J.; Zakariyah, S. S.; Milward, D

    2008-01-01

    Introduction: At high bit rates copper tracks in printed circuit boards (PCBs) suffer severe loss and pulse distortion due to radiation of electromagnetic waves, dispersion and bandwidth limitations. The loss can be overcome to some extent by transmitting higher power pulses and by changing the dielectric constant and loss tangent of the PCB substrate material. However, high power pulses consume power and can cause electro-migration which reduces the board lifetime, although the copper tracks...

  8. A Trainable Neuromorphic Integrated Circuit that Exploits Device Mismatch

    OpenAIRE

    Thakur, Chetan Singh; Wang, Runchun; Hamilton, Tara Julia; Tapson, Jonathan; van Schaik, Andre

    2015-01-01

    Random device mismatch that arises as a result of scaling of the CMOS (complementary metal-oxide semi-conductor) technology into the deep submicron regime degrades the accuracy of analogue circuits. Methods to combat this increase the complexity of design. We have developed a novel neuromorphic system called a Trainable Analogue Block (TAB), which exploits device mismatch as a means for random projections of the input to a higher dimensional space. The TAB framework is inspired by the princip...

  9. CMOS readout integrated circuit involving pixel-level ADC for microbolometer FPAs

    Science.gov (United States)

    Hwang, C. H.; Kwon, I. W.; Lee, Y. S.; Lee, H. C.

    2008-04-01

    The function of most readout integrated circuits (ROIC) for microbolometer focal plane arrays (FPAs) is supplying a bias voltage to a microbolometer of each pixel, integrating the current of a microbolometer, and transferring the signals from pixels to the output of a chip. However, the scale down of CMOS technology allows the integration of other functions. In this paper, we proposed a CMOS ROIC involving a pixel-level analog-to-digital converter (ADC) for 320 × 240 microbolometer FPAs. Such integration would improve the performance of a ROIC at the reduced system cost and power consumption. The noise performance of a microbolometer is improved by using the pixelwise readout structure because integration time can be increased up to 1ms. A Pixel circuit is consisted of a background skimming circuit, a differential amplifier, an integration capacitor and a 10-bit DRAM. First, the microbolometer current is integrated for 1ms after the skimming current correction. The differential amplifier operates as an op-Amp and the integration capacitor makes negative feedback loop between an output and a negative input of the op-Amp. And then, the integrated signal voltage is converted to digital signals using a modified single slope ADC in a pixel when the differential amplifier operates as a comparator and the 10-bit DRAM stores values of a counter. This readout circuit is designed and fabricated using a standard 0.35μm 2-poly 3-metal CMOS technology.

  10. Technological and Physical Compatibilities in Hybrid Integration of Laser and Monolithic Integration of Waveguide, Photodetector and CMOS Circuits on Silicon

    NARCIS (Netherlands)

    Zhou, M.J.; Ikkink, T.; Chalmers, J.; Kranenburg, H. van; Albers, H.; Holleman, J.; Lambeck, P.V.; Joppe, J.L.; Bekman, H.H.P.T.; Krijger, A.J.T. de

    1994-01-01

    In this paper, technological and physical compatibilities in hybrid integration of AlInGaP laser and monolithic integration of ZnO monomode waveguide, pin-photodetector, CMOS circuits for laser power control and signal amplification on silicon substrate are studied. Prospective problems and their po

  11. Technological and physical compatibilities in hybrid integration of laser and monolithic integration of waveguide, photodetector and CMOS circuits on silicon

    NARCIS (Netherlands)

    Zhou, Ming-Jiang; Ikkink, Ton; Chalmers, John; Kranenburg, van Herma; Albers, Hans; Holleman, Jisk; Lambeck, Paul; Joppe, Jan Leendert; Bekman, Herman; Krijger, de Ton; Lambeck, P.V.

    1994-01-01

    In this paper, technological and physical compatibilities in hybrid integration of AlInGaP laser and monolithic integration of ZnO monomode waveguide, pin-photodetector, CMOS circuits for laser power control and signal amplification on silicon substrate are studied. Prospective problems and their po

  12. A numerical integration-based yield estimation method for integrated circuits

    Institute of Scientific and Technical Information of China (English)

    Liang Tao; Jia Xinzhang

    2011-01-01

    A novel integration-based yield estimation method is developed for yield optimization of integrated circuits. This method tries to integrate the joint probability density function on the acceptability region directly.To achieve this goal, the simulated performance data of unknown distribution should be converted to follow a multivariate normal distribution by using Box-Cox transformation (BCT). In order to reduce the estimation variances of the model parameters of the density function, orthogonal array-based modified Latin hypercube sampling (OA-MLHS) is presented to generate samples in the disturbance space during simulations. The principle of variance reduction of model parameters estimation through OA-MLHS together with BCT is also discussed. Two yield estimation examples, a fourth-order OTA-C filter and a three-dimensional (3D) quadratic function are used for comparison of our method with Monte Carlo based methods including Latin hypercube sampling and importance sampling under several combinations of sample sizes and yield values. Extensive simulations show that our method is superior to other methods with respect to accuracy and efficiency under all of the given cases. Therefore, our method is more suitable for parametric yield optimization.

  13. The Scalable Integration of long-lived quantum memories into a photonic circuit

    CERN Document Server

    Mouradian, Sara L; Poitras, Carl B; Li, Luozhou; Goldstein, Jordan; Chen, Edward H; Cardenas, Jaime; Markham, Matthew L; Twitchen, Daniel J; Lipson, Michal; Englund, Dirk

    2014-01-01

    We demonstrate a photonic circuit with integrated long-lived quantum memories. Pre-selected quantum nodes - diamond micro-waveguides containing single, stable, and negatively charged nitrogen vacancy centers - are deterministically integrated into low-loss silicon nitride waveguides. Each quantum memory node efficiently couples into the single-mode waveguide (> 1 Mcps collected into the waveguide) and exhibits long spin coherence times of up to 120 {\\mu}s. Our system facilitates the assembly of multiple quantum memories into a photonic integrated circuit with near unity yield, paving the way towards scalable quantum information processing.

  14. Rapid mapping of digital integrated circuit logic gates via multi-spectral backside imaging

    CERN Document Server

    Adato, Ronen; Zangeneh, Mahmoud; Zhou, Boyou; Joshi, Ajay; Goldberg, Bennett; Unlu, M Selim

    2016-01-01

    Modern semiconductor integrated circuits are increasingly fabricated at untrusted third party foundries. There now exist myriad security threats of malicious tampering at the hardware level and hence a clear and pressing need for new tools that enable rapid, robust and low-cost validation of circuit layouts. Optical backside imaging offers an attractive platform, but its limited resolution and throughput cannot cope with the nanoscale sizes of modern circuitry and the need to image over a large area. We propose and demonstrate a multi-spectral imaging approach to overcome these obstacles by identifying key circuit elements on the basis of their spectral response. This obviates the need to directly image the nanoscale components that define them, thereby relaxing resolution and spatial sampling requirements by 1 and 2 - 4 orders of magnitude respectively. Our results directly address critical security needs in the integrated circuit supply chain and highlight the potential of spectroscopic techniques to addres...

  15. Heat management in integrated circuits on-chip and system-level monitoring and cooling

    CERN Document Server

    Ogrenci-Memik, Seda

    2016-01-01

    This essential overview covers the subject of thermal monitoring and management in integrated circuits. Specifically, it focuses on devices and materials that are intimately integrated on-chip (as opposed to in-package or on-board) for the purposes of thermal monitoring and thermal management.

  16. 77 FR 39510 - Certain Semiconductor Integrated Circuit Devices and Products Containing Same; Determination Not...

    Science.gov (United States)

    2012-07-03

    ... FR 25747-48 (May 1, 2012). The complaint alleges violations of section 337 of the Tariff Act of 1930... COMMISSION Certain Semiconductor Integrated Circuit Devices and Products Containing Same; Determination Not... the sale within the United States after importation of certain semiconductor integrated...

  17. 2D and 3D heterogeneous photonic integrated circuits

    Science.gov (United States)

    Yoo, S. J. Ben

    2014-03-01

    Exponential increases in the amount of data that need to be sensed, communicated, and processed are continuing to drive the complexity of our computing, networking, and sensing systems. High degrees of integration is essential in scalable, practical, and cost-effective microsystems. In electronics, high-density 2D integration has naturally evolved towards 3D integration by stacking of memory and processor chips with through-silicon-vias. In photonics, too, we anticipate highdegrees of 3D integration of photonic components to become a prevailing method in realizing future microsystems for information and communication technologies. However, compared to electronics, photonic 3D integration face a number of challenges. This paper will review two methods of 3D photonic integration --- fs laser inscription and layer stacking, and discuss applications and future prospects.

  18. Cascaded all-optical operations in a hybrid integrated 80-Gb/s logic circuit.

    Science.gov (United States)

    LeGrange, J D; Dinu, M; Sochor, T; Bollond, P; Kasper, A; Cabot, S; Johnson, G S; Kang, I; Grant, A; Kay, J; Jaques, J

    2014-06-01

    We demonstrate logic functionalities in a high-speed all-optical logic circuit based on differential Mach-Zehnder interferometers with semiconductor optical amplifiers as the nonlinear optical elements. The circuit, implemented by hybrid integration of the semiconductor optical amplifiers on a planar lightwave circuit platform fabricated in silica glass, can be flexibly configured to realize a variety of Boolean logic gates. We present both simulations and experimental demonstrations of cascaded all-optical operations for 80-Gb/s on-off keyed data.

  19. The single-event effect evaluation technology for nano integrated circuits

    International Nuclear Information System (INIS)

    Single-event effects of nano scale integrated circuits are investigated. Evaluation methods for single-event transients, single-event upsets, and single-event functional interrupts in nano circuits are summarized and classified in detail. The difficulties in SEE testing are discussed as well as the development direction of test technology, with emphasis placed on the experimental evaluation of a nano circuit under heavy ion, proton, and laser irradiation. The conclusions in this paper are based on many years of testing at accelerator facilities and our present understanding of the mechanisms for SEEs, which have been well verified experimentally. (paper)

  20. Micromorph silicon tandem solar cells with fully integrated 3D photonic crystal intermediate reflectors

    Science.gov (United States)

    Üpping, J.; Bielawny, A.; Fahr, S.; Rockstuhl, C.; Lederer, F.; Steidl, L.; Zentel, R.; Beckers, T.; Lambertz, A.; Carius, R.; Wehrspohn, R. B.

    2010-05-01

    A 3D photonic intermediate reflector for textured micromorph silicon tandem solar cells has been investigated. In thin-film silicon tandem solar cells consisting of amorphous and microcrystalline silicon with two junctions of a-Si/c-Si, efficiency enhancements can be achieved by increasing the current density in the a-Si top cell providing an optimized current matching at high current densities. For an ideal photon-management between top and bottom cell, a spectrally-selective intermediate reflective layer (IRL) is necessary. We present the first fully-integrated 3D photonic thin-film IRL device incorporated on a planar substrate. Using a ZnO inverted opal structure the external quantum efficiency of the top cell in the spectral region of interest could be enhanced. As an outlook we present the design and the preparation of a 3D self organized photonic crystal structure in a textured micromorph tandem solar cell.

  1. Fully integrated micro-separator with soft-magnetic micro-pillar arrays for filtrating lymphocytes.

    Science.gov (United States)

    Dong, Tao; Su, Qianhua; Yang, Zhaochu; Karlsen, Frank; Jakobsen, Henrik; Egeland, Eirik Bentzen; Hjelseth, Snorre

    2010-01-01

    A fully integrated micro-separator with soft-magnetic micro-pillar arrays has been developed, which merely employs one independent Lab-On-Chip to realize the lymphocytes isolation from the human whole blood. The simulation, fabrication and experiment are executed to realize this novel microseparator. The simulation results show that, the soft-magnetic micro-pillars array can amplify and redistribute the electromagnetic field generated by the microcoils. The tests certify desirable separation efficiency can be realized using this new separator at low current. No extra cooling system is required for such a micro-separator. This micro-separator can also be used to separate other target cells or particles with the same principle. PMID:21096497

  2. Precision Instrumentation Amplifiers and Read-Out Integrated Circuits

    CERN Document Server

    Wu, Rong; Makinwa, Kofi A A

    2013-01-01

    This book presents innovative solutions in the design of precision instrumentation amplifier and read-out ICs, which can be used to boost millivolt-level signals transmitted by modern sensors, to levels compatible with the input ranges of typical Analog-to-Digital Converters (ADCs).  The discussion includes the theory, design and realization of interface electronics for bridge transducers and thermocouples. It describes the use of power efficient techniques to mitigate low frequency errors, resulting in interface electronics with high accuracy, low noise and low drift. Since this book is mainly about techniques for eliminating low frequency errors, it describes the nature of these errors and the associated dynamic offset cancellation techniques used to mitigate them.  Surveys comprehensively offset cancellation and accuracy improvement techniques applied in precision amplifier designs; Presents techniques in precision circuit design to mitigate low frequency errors in millivolt-level signals transmitted by ...

  3. Dictionary-based image reconstruction for superresolution in integrated circuit imaging.

    Science.gov (United States)

    Cilingiroglu, T Berkin; Uyar, Aydan; Tuysuzoglu, Ahmet; Karl, W Clem; Konrad, Janusz; Goldberg, Bennett B; Ünlü, M Selim

    2015-06-01

    Resolution improvement through signal processing techniques for integrated circuit imaging is becoming more crucial as the rapid decrease in integrated circuit dimensions continues. Although there is a significant effort to push the limits of optical resolution for backside fault analysis through the use of solid immersion lenses, higher order laser beams, and beam apodization, signal processing techniques are required for additional improvement. In this work, we propose a sparse image reconstruction framework which couples overcomplete dictionary-based representation with a physics-based forward model to improve resolution and localization accuracy in high numerical aperture confocal microscopy systems for backside optical integrated circuit analysis. The effectiveness of the framework is demonstrated on experimental data.

  4. Detection of orbital angular momentum using a photonic integrated circuit

    OpenAIRE

    Guanghao Rui; Bing Gu; Yiping Cui; Qiwen Zhan

    2016-01-01

    Orbital angular momentum (OAM) state of photons offer an attractive additional degree of freedom that has found a variety of applications. Measurement of OAM state, which is a critical task of these applications, demands photonic integrated devices for improved fidelity, miniaturization, and reconfiguration. Here we report the design of a silicon-integrated OAM receiver that is capable of detecting distinct and variable OAM states. Furthermore, the reconfiguration capability of the detector i...

  5. Short circuit analysis of distribution system with integration of DG

    DEFF Research Database (Denmark)

    Su, Chi; Liu, Zhou; Chen, Zhe;

    2014-01-01

    Integration of distributed generation (DG) such as wind turbines into distribution system is increasing all around the world, because of the flexible and environmentally friendly characteristics. However, DG integration may change the pattern of the fault currents in the distribution system and a...... as well. The results in this paper are based on mathematical analysis and simulation study in DIgSILENT PowerFactory....

  6. Object Orientated Programmable Integrated Circuit (OOPIC) upgrade and evaluation for Autonomous Ground Vehicle (AGV)

    OpenAIRE

    Hoffman, Andrew J.

    2006-01-01

    A small, low-power Object-Oriented Programmable integrated circuit (OOPic) microcontroller was integrated and tested with the architecture for an autonomous ground vehicle (AGV). Sensors with the OOPic, and the XBee Wireless Suite were included in the integration. Tests were conducted, including range and time operation analysis for wireless communications for comparison with the legacy BL2000 microcontroller. Results demonstrated long battery life for the electronics of the robot, as well as...

  7. Fully integrated system-on-chip for pixel-based 3D depth and scene mapping

    Science.gov (United States)

    Popp, Martin; De Coi, Beat; Thalmann, Markus; Gancarz, Radoslav; Ferrat, Pascal; Dürmüller, Martin; Britt, Florian; Annese, Marco; Ledergerber, Markus; Catregn, Gion-Pol

    2012-03-01

    We present for the first time a fully integrated system-on-chip (SoC) for pixel-based 3D range detection suited for commercial applications. It is based on the time-of-flight (ToF) principle, i.e. measuring the phase difference of a reflected pulse train. The product epc600 is fabricated using a dedicated process flow, called Espros Photonic CMOS. This integration makes it possible to achieve a Quantum Efficiency (QE) of >80% in the full wavelength band from 520nm up to 900nm as well as very high timing precision in the sub-ns range which is needed for exact detection of the phase delay. The SoC features 8x8 pixels and includes all necessary sub-components such as ToF pixel array, voltage generation and regulation, non-volatile memory for configuration, LED driver for active illumination, digital SPI interface for easy communication, column based 12bit ADC converters, PLL and digital data processing with temporary data storage. The system can be operated at up to 100 frames per second.

  8. Fully integrated reflection-mode photoacoustic, two-photon, and second harmonic generation microscopy in vivo

    Science.gov (United States)

    Song, Wei; Xu, Qiang; Zhang, Yang; Zhan, Yang; Zheng, Wei; Song, Liang

    2016-08-01

    The ability to obtain comprehensive structural and functional information from intact biological tissue in vivo is highly desirable for many important biomedical applications, including cancer and brain studies. Here, we developed a fully integrated multimodal microscopy that can provide photoacoustic (optical absorption), two-photon (fluorescence), and second harmonic generation (SHG) information from tissue in vivo, with intrinsically co-registered images. Moreover, using a delicately designed optical-acoustic coupling configuration, a high-frequency miniature ultrasonic transducer was integrated into a water-immersion optical objective, thus allowing all three imaging modalities to provide a high lateral resolution of ~290 nm with reflection-mode imaging capability, which is essential for studying intricate anatomy, such as that of the brain. Taking advantage of the complementary and comprehensive contrasts of the system, we demonstrated high-resolution imaging of various tissues in living mice, including microvasculature (by photoacoustics), epidermis cells, cortical neurons (by two-photon fluorescence), and extracellular collagen fibers (by SHG). The intrinsic image co-registration of the three modalities conveniently provided improved visualization and understanding of the tissue microarchitecture. The reported results suggest that, by revealing complementary tissue microstructures in vivo, this multimodal microscopy can potentially facilitate a broad range of biomedical studies, such as imaging of the tumor microenvironment and neurovascular coupling.

  9. Fully integrated reflection-mode photoacoustic, two-photon, and second harmonic generation microscopy in vivo

    Science.gov (United States)

    Song, Wei; Xu, Qiang; Zhang, Yang; Zhan, Yang; Zheng, Wei; Song, Liang

    2016-01-01

    The ability to obtain comprehensive structural and functional information from intact biological tissue in vivo is highly desirable for many important biomedical applications, including cancer and brain studies. Here, we developed a fully integrated multimodal microscopy that can provide photoacoustic (optical absorption), two-photon (fluorescence), and second harmonic generation (SHG) information from tissue in vivo, with intrinsically co-registered images. Moreover, using a delicately designed optical-acoustic coupling configuration, a high-frequency miniature ultrasonic transducer was integrated into a water-immersion optical objective, thus allowing all three imaging modalities to provide a high lateral resolution of ~290 nm with reflection-mode imaging capability, which is essential for studying intricate anatomy, such as that of the brain. Taking advantage of the complementary and comprehensive contrasts of the system, we demonstrated high-resolution imaging of various tissues in living mice, including microvasculature (by photoacoustics), epidermis cells, cortical neurons (by two-photon fluorescence), and extracellular collagen fibers (by SHG). The intrinsic image co-registration of the three modalities conveniently provided improved visualization and understanding of the tissue microarchitecture. The reported results suggest that, by revealing complementary tissue microstructures in vivo, this multimodal microscopy can potentially facilitate a broad range of biomedical studies, such as imaging of the tumor microenvironment and neurovascular coupling. PMID:27576922

  10. Pixelwise readout integrated circuits with pixel-level ADC for microbolometers

    Science.gov (United States)

    Hwang, C. H.; Kim, C. B.; Lee, Y. S.; Yu, B. G.; Lee, H. C.

    2007-04-01

    Pixelwise integrated circuits involving a pixel-level analog-to-digital converter (ADC) are studied for 320 × 240 microbolometer focal plane arrays (FPAs). It is necessary to use the pixelwise readout architecture for decreasing the thermal noise. However, it is hard to locate a sufficiently large integration capacitor in a unit pixel of FPAs because of the area limitation. To effectively overcome this problem, a two step integration method is proposed. First, after integrating the current of the microbolometer for 32μs, upper 5bits of the 13bit digital signal are output through a pixel-level ADC. Then, the current of the microbolometer is integrated during 1ms after the skimming current correction using upper 5bits in a field-programmable gate array (FPGA), and then lower 8bits are obtained through a pixel-level ADC. Finally, upper 5bits and lower 8bits are combined into the digital image signal after the gain and offset correction in digital signal processor (DSP) Each 2×2 pixel shares an readout circuit, including a current-mode background skimming circuit, an operational amplifier(op-Amp), an integration capacitor and a single slope ADC. When the current of a microbolometer is integrated, the integration capacitor is connected between a negative input and an output of the op-Amp. Therefore a capacitive transimpedance amplifier (CTIA) has been employed as the input circuit of the microbolometer. When the output of a microbolometer is converted to digital signal, the Op-Amp is used as a comparator of the single slope ADC. This readout circuit is designed to achieve 35×35μm2 pixel size in 0.35μm 2-poly 3-metal CMOS technology.

  11. Integrated Circuit Interconnect Lines on Lossy Silicon Substrate with Finite Element Method

    Directory of Open Access Journals (Sweden)

    Sarhan M. Musa,

    2014-01-01

    Full Text Available The silicon substrate has a significant effect on the inductance parameter of a lossy interconnect line on integrated circuit. It is essential to take this into account in determining the transmission line electrical parameters. In this paper, a new quasi-TEM capacitance and inductance analysis of multiconductor multilayer interconnects is successfully demonstrated using finite element method (FEM. We specifically illustrate the electrostatic modeling of single and coupled interconnected lines on a silicon-silicon oxide substrate. Also, we determine the quasi-static spectral for the potential distribution of the silicon-integrated circuit.

  12. System and method for interfacing large-area electronics with integrated circuit devices

    Energy Technology Data Exchange (ETDEWEB)

    Verma, Naveen; Glisic, Branko; Sturm, James; Wagner, Sigurd

    2016-07-12

    A system and method for interfacing large-area electronics with integrated circuit devices is provided. The system may be implemented in an electronic device including a large area electronic (LAE) device disposed on a substrate. An integrated circuit IC is disposed on the substrate. A non-contact interface is disposed on the substrate and coupled between the LAE device and the IC. The non-contact interface is configured to provide at least one of a data acquisition path or control path between the LAE device and the IC.

  13. Sub-micron imaging of buried integrated circuit structures using scanning confocal electron microscopy.

    Energy Technology Data Exchange (ETDEWEB)

    Frigo, S. P.; Levine, Z.; Zaluzec, N. J.; Materials Science Division; Northern Arizona Univ.; NIST

    2002-09-09

    Two-dimensional images of model integrated circuit components were collected using the technique of scanning confocal electron microscopy. For structures embedded about 5 {mu}m below the surface of a silicon oxide dielectric, a lateral resolution of 76{+-}9 nm was measured. Elemental mapping via x-ray emission spectrometry is demonstrated. A parallax analysis of images taken for various tilt angles to the electron beam allowed determination of the spacing between two wiring planes. The results show that scanning confocal electron microscopy is capable of probing buried structures at resolutions that will be necessary for the inspection of next-generation integrated circuit technology.

  14. Wafer-level testing and test during burn-in for integrated circuits

    CERN Document Server

    Bahukudumbi, Sudarshan

    2010-01-01

    Wafer-level testing refers to a critical process of subjecting integrated circuits and semiconductor devices to electrical testing while they are still in wafer form. Burn-in is a temperature/bias reliability stress test used in detecting and screening out potential early life device failures. This hands-on resource provides a comprehensive analysis of these methods, showing how wafer-level testing during burn-in (WLTBI) helps lower product cost in semiconductor manufacturing.Engineers learn how to implement the testing of integrated circuits at the wafer-level under various resource constrain

  15. Readout integrated circuit for microbolometer with an analog non-uniformity correction

    Science.gov (United States)

    Hwang, C. H.; Woo, D. H.; Lee, Y. S.; Lee, H. C.

    2005-10-01

    We have developed a microbolometer readout integrated circuit (ROIC) that corrects the non-uniformity in analog operation and acts in both normal mode and edge detection mode. A capacitive transimpedance amplifier (CTIA) has been employed as the input circuit of the microbolometer. Generally, when fabricating microbolometer focal plane arrays (FPAs), offset-error and gain-error in the inter-microbolometer are induced by fabrication error. They are shown as fixed pattern noise (FPN) in the infrared image. In the present study, a circuit correcting the offset-error and the gain-error in the normal mode by controlling the bias and the integration capacitance of the CTIA is proposed. This circuit does not require an additional DSP chip, and the non-uniformity is corrected before the analog to digital conversion (ADC). Thus, it can utilize 3-4 bits lower ADC compared to the conventional readout circuit. In the edge detection mode, after correcting the gain-error in two adjacent pixels, edge detection can be realized by subtracting their signal without the DSP. We have designed the suggested circuit to output a 10bit level effective infrared signal using 0.35um 2-poly 3-metal CMOS technology.

  16. Detection of orbital angular momentum using a photonic integrated circuit

    Science.gov (United States)

    Rui, Guanghao; Gu, Bing; Cui, Yiping; Zhan, Qiwen

    2016-01-01

    Orbital angular momentum (OAM) state of photons offer an attractive additional degree of freedom that has found a variety of applications. Measurement of OAM state, which is a critical task of these applications, demands photonic integrated devices for improved fidelity, miniaturization, and reconfiguration. Here we report the design of a silicon-integrated OAM receiver that is capable of detecting distinct and variable OAM states. Furthermore, the reconfiguration capability of the detector is achieved by applying voltage to the GeSe film to form gratings with alternate states. The resonant wavelength for arbitrary OAM state is demonstrated to be tunable in a quasi-linear manner through adjusting the duty cycle of the gratings. This work provides a viable approach for the realization of a compact integrated OAM detection device with enhanced functionality that may find important applications in optical communications and information processing with OAM states. PMID:27321916

  17. Detection of orbital angular momentum using a photonic integrated circuit

    Science.gov (United States)

    Rui, Guanghao; Gu, Bing; Cui, Yiping; Zhan, Qiwen

    2016-06-01

    Orbital angular momentum (OAM) state of photons offer an attractive additional degree of freedom that has found a variety of applications. Measurement of OAM state, which is a critical task of these applications, demands photonic integrated devices for improved fidelity, miniaturization, and reconfiguration. Here we report the design of a silicon-integrated OAM receiver that is capable of detecting distinct and variable OAM states. Furthermore, the reconfiguration capability of the detector is achieved by applying voltage to the GeSe film to form gratings with alternate states. The resonant wavelength for arbitrary OAM state is demonstrated to be tunable in a quasi-linear manner through adjusting the duty cycle of the gratings. This work provides a viable approach for the realization of a compact integrated OAM detection device with enhanced functionality that may find important applications in optical communications and information processing with OAM states.

  18. Detection of orbital angular momentum using a photonic integrated circuit.

    Science.gov (United States)

    Rui, Guanghao; Gu, Bing; Cui, Yiping; Zhan, Qiwen

    2016-06-20

    Orbital angular momentum (OAM) state of photons offer an attractive additional degree of freedom that has found a variety of applications. Measurement of OAM state, which is a critical task of these applications, demands photonic integrated devices for improved fidelity, miniaturization, and reconfiguration. Here we report the design of a silicon-integrated OAM receiver that is capable of detecting distinct and variable OAM states. Furthermore, the reconfiguration capability of the detector is achieved by applying voltage to the GeSe film to form gratings with alternate states. The resonant wavelength for arbitrary OAM state is demonstrated to be tunable in a quasi-linear manner through adjusting the duty cycle of the gratings. This work provides a viable approach for the realization of a compact integrated OAM detection device with enhanced functionality that may find important applications in optical communications and information processing with OAM states.

  19. Analog integrated circuits for the Lotka-Volterra competitive neural networks.

    Science.gov (United States)

    Asai, T; Ohtani, M; Yonezu, H

    1999-01-01

    A subthreshold MOS integrated circuit (IC) is designed and fabricated for implementing a competitive neural network of the Lotka-Volterra (LV) type which is derived from conventional membrane dynamics of neurons and is used for the selection of external inputs. The steady-state solutions to the LV equation can be classified into three types, each of which represents qualitatively different selection behavior. Among the solutions, the winners-share-all (WSA) solution in which a certain number of neurons remain activated in steady states is particularly useful owing to robustness in the selection of inputs from a noisy environment. The measured results of the fabricated LV IC's agree well with the theoretical prediction as long as the influence of device mismatches is small. Furthermore, results of extensive circuit simulations prove that the large-scale LV circuit producing the WSA solution does exhibit a reliable selection compared with winner-take-all circuits, in the possible presence of device mismatches.

  20. A UVLO Circuit in SiC Compatible with Power MOSFET Integration (pending entry)

    Energy Technology Data Exchange (ETDEWEB)

    Ericson, Milton Nance [ORNL; Frank, Steven Shane [ORNL; Glover, Dr. Michael [University of Arkansas; Britton, Charles [Oak Ridge National Laboratory (ORNL); Francis, Dr. Matt [University of Arkansas; Mantooth, Alan [University of Arkansas; Marlino, Laura D [ORNL; Mcnutt, Tyler [APEI, Inc.; Mudholkar, Dr. Mihir [University of Arkansas; Shepherd, Dr. Paul [University of Arkansas; Whitaker, Mr. Bret [APEI, Inc.; Barkley, Dr. Adam [APEI, Inc.; Lotstetter, Alex [APEI, Inc.

    2014-01-01

    The design and test of the first undervoltage lock-out circuit implemented in a low-voltage 4H silicon carbide process capable of single-chip integration with power MOSFETs is presented. The lock-out circuit, a block of the protection circuitry of a single-chip gate driver topology designed for use in a plug-in hybrid vehicle charger, was demonstrated to have rise/fall times compatible with a MOSFET switching speed of 250 kHz while operating over the targeted operating temperature range between 0 C and 200 C. Captured data show the circuit to be functional over a temperature range from -55 C to 300 C. The design of the circuit and test results is presented.

  1. A UVLO Circuit in SiC Compatible with Power MOSFET Integration

    Energy Technology Data Exchange (ETDEWEB)

    Glover, Michael [APEI, Inc.; Shepherd, Paul [APEI, Inc.; Francis, Matt [APEI, Inc.; Mudholkar, Dr. Mihir [University of Arkansas; Mantooth, Alan [University of Arkansas; Ericson, Milton Nance [ORNL; Frank, Steven [ORNL; Britton Jr, Charles L [ORNL; Marlino, Laura D [ORNL; Mcnutt, Tyler [APEI, Inc.; Barkley, Dr. Adam [APEI, Inc.; Whitaker, Mr. Bret [APEI, Inc.; Lostetter, Dr. Alex [APEI, Inc.

    2014-01-01

    The design and test of the first undervoltage lock-out circuit implemented in a low voltage 4H silicon carbide process capable of single-chip integration with power MOSFETs is presented. The lock-out circuit, a block of the protection circuitry of a single-chip gate driver topology designed for use in a plug-in hybrid vehicle charger, was demonstrated to have rise/fall times compatible with a MOSFET switching speed of 250 kHz while operating over the targeted operating temperature range between 0 C and 200 C. Captured data shows the circuit to be functional over a temperature range from -55 C to 300 C. The design of the circuit and test results is presented.

  2. Fully Integrated Microfluidic Device for Direct Sample-to-Answer Genetic Analysis

    Science.gov (United States)

    Liu, Robin H.; Grodzinski, Piotr

    Integration of microfluidics technology with DNA microarrays enables building complete sample-to-answer systems that are useful in many applications such as clinic diagnostics. In this chapter, a fully integrated microfluidic device [1] that consists of microfluidic mixers, valves, pumps, channels, chambers, heaters, and a DNA microarray sensor to perform DNA analysis of complex biological sample solutions is present. This device can perform on-chip sample preparation (including magnetic bead-based cell capture, cell preconcentration and purification, and cell lysis) of complex biological sample solutions (such as whole blood), polymerase chain reaction, DNA hybridization, and electrochemical detection. A few novel microfluidic techniques were developed and employed. A micromix-ing technique based on a cavitation microstreaming principle was implemented to enhance target cell capture from whole blood samples using immunomagnetic beads. This technique was also employed to accelerate DNA hybridization reaction. Thermally actuated paraffin-based microvalves were developed to regulate flows. Electrochemical pumps and thermopneumatic pumps were integrated on the chip to provide pumping of liquid solutions. The device is completely self-contained: no external pressure sources, fluid storage, mechanical pumps, or valves are necessary for fluid manipulation, thus eliminating possible sample contamination and simplifying device operation. Pathogenic bacteria detection from ~mL whole blood samples and single-nucleotide polymorphism analysis directly from diluted blood were demonstrated. The device provides a cost-effective solution to direct sample-to-answer genetic analysis, and thus has a potential impact in the fields of point-of-care genetic analysis, environmental testing, and biological warfare agent detection.

  3. Design of integrated readout circuit with enhanced capacitance mechanism for dual-band infrared detector

    Science.gov (United States)

    Sun, Tai-Ping; Lu, Yi-Chuan; Shieh, Hsiu-Li; Shiu, Shiuan-Shuo; Liu, Yi-Ting; Tang, Shiang-Feng; Lin, Wen-Jen

    2011-10-01

    This study proposes a solution for an excessive dark current by a sharing capacitor, which avoids output signal distortion due to integration voltage saturation. Integration capacitance can be changed by adding a switch in the pixel circuit, which will increase the capacitance by two times the original. This circuit also provides output functions of either single-band or dual-band by switching to different sensor. This integrated readout circuit design adopts the TSMC 0.35um 2P4M CMOS 5V process, run on a 5V power supply and operated at a 3MHz clock rate. The dual-band pixel circuit uses an interlace structure, the pixel circuit areas of the two wavelengths are both 30um x 30um. The mid-wave and long-wave sensor currents are from 1nA to 2nA and 6nA to 8nA, respectively, and output swing is 2.8V.

  4. W-band Phased Array Systems using Silicon Integrated Circuits

    Science.gov (United States)

    Kim, Sang Young

    This thesis presents the silicon-based on-chip W-band phased array systems. An improved quadrature all-pass filter (QAF) and its implementation in 60--80 GHz active phase shifter using 0.13 microm SiGe BiCMOS technology is presented. It is demonstrated that with the inclusion of an Rs/R in the high Q branches of C and L, the sensitivity to the loading capacitance, therefore the I/Q phase and amplitude errors are minimized. This technique is especially suited for wideband millimeter-wave circuits where the loading capacitance (CL) is comparable to the filter capacitance (C). A prototype 60--80 GHz active phased shifter using the improved QAF is demonstrated. The overall chip size is 1.15 x 0.92 mm2 with the power consumption of 108 mW. The measured S11 and S22 are switches is demonstrated. The phase shifter is based on a low-pass pi-network. The chip size is 0.45 x 0.3 mm2 without pads and consumes virtually no power. The measured S11 and S22 is 8 dBm and the simulated IIP3 is > 22 dBm. A low-power 76--84 GHz 4-element phased array receiver using the designed passive phase shifter is presented. The power consumption is minimized by using a single-ended design and alternating the amplifiers and phase shifter cells to result in a low noise figure at a low power consumption. A variable gain amplifier and the 11° phase shifter are used to correct for the rms gain and phase errors at different operating frequencies. The overall chip size is 2.0 x 2.7 mm2 with the current consumption of 18 mA/channel with 1.8 V supply voltage. The measured S11 and S 22 is chip coupling is circuits are designed differentially to result in less sensitivity to packaging effect and high channel-to-channel isolation. The overall chip size is 5.0 x 5.8 mm 2 with the power consumption of 500--600 mA from 2 V supply voltage. The measured S11 and S22 for all 16 phase states is 10 dB for 76.4--90 GHz with the rms gain error of -45 dB. The measured NF is 11.2--13 dB at 77--87 GHz at the maximum

  5. Tunable quantum interference in a 3D integrated circuit.

    Science.gov (United States)

    Chaboyer, Zachary; Meany, Thomas; Helt, L G; Withford, Michael J; Steel, M J

    2015-04-27

    Integrated photonics promises solutions to questions of stability, complexity, and size in quantum optics. Advances in tunable and non-planar integrated platforms, such as laser-inscribed photonics, continue to bring the realisation of quantum advantages in computation and metrology ever closer, perhaps most easily seen in multi-path interferometry. Here we demonstrate control of two-photon interference in a chip-scale 3D multi-path interferometer, showing a reduced periodicity and enhanced visibility compared to single photon measurements. Observed non-classical visibilities are widely tunable, and explained well by theoretical predictions based on classical measurements. With these predictions we extract Fisher information approaching a theoretical maximum. Our results open a path to quantum enhanced phase measurements.

  6. A microfabricated fringing field capacitive pH sensor with an integrated readout circuit

    Energy Technology Data Exchange (ETDEWEB)

    Arefin, Md Shamsul, E-mail: md.arefin@monash.edu; Redoute, Jean-Michel; Rasit Yuce, Mehmet [Electrical and Computer Systems Engineering, Monash University, Melbourne (Australia); Bulut Coskun, M.; Alan, Tuncay; Neild, Adrian [Mechanical and Aerospace Engineering, Monash University, Melbourne (Australia)

    2014-06-02

    This work presents a microfabricated fringe-field capacitive pH sensor using interdigitated electrodes and an integrated modulation-based readout circuit. The changes in capacitance of the sensor result from the permittivity changes due to pH variations and are converted to frequency shifts using a crossed-coupled voltage controlled oscillator readout circuit. The shift in resonant frequency of the readout circuit is 30.96 MHz for a change in pH of 1.0–5.0. The sensor can be used for the measurement of low pH levels, such as gastric acid, and can be integrated with electronic pills. The measurement results show high repeatability, low noise, and a stable output.

  7. The One-Water Hydrologic Flow Model - The next generation in fully integrated hydrologic simulation software

    Science.gov (United States)

    Boyce, S. E.; Hanson, R. T.

    2015-12-01

    The One-Water Hydrologic Flow Model (MF-OWHM) is a MODFLOW-based integrated hydrologic flow model that is the most complete version, to date, of the MODFLOW family of hydrologic simulators needed for the analysis of a broad range of conjunctive-use issues. MF-OWHM fully links the movement and use of groundwater, surface water, and imported water for consumption by agriculture and natural vegetation on the landscape, and for potable and other uses within a supply-and-demand framework. MF-OWHM is based on the Farm Process for MODFLOW-2005 combined with Local Grid Refinement, Streamflow Routing, Surface-water Routing Process, Seawater Intrusion, Riparian Evapotranspiration, and the Newton-Raphson solver. MF-OWHM also includes linkages for deformation-, flow-, and head-dependent flows; additional observation and parameter options for higher-order calibrations; and redesigned code for facilitation of self-updating models and faster simulation run times. The next version of MF-OWHM, currently under development, will include a new surface-water operations module that simulates dynamic reservoir operations, the conduit flow process for karst aquifers and leaky pipe networks, a new subsidence and aquifer compaction package, and additional features and enhancements to enable more integration and cross communication between traditional MODFLOW packages. By retaining and tracking the water within the hydrosphere, MF-OWHM accounts for "all of the water everywhere and all of the time." This philosophy provides more confidence in the water accounting by the scientific community and provides the public a foundation needed to address wider classes of problems such as evaluation of conjunctive-use alternatives and sustainability analysis, including potential adaptation and mitigation strategies, and best management practices. By Scott E. Boyce and Randall T. Hanson

  8. Application of a fully-integrated groundwater-surface water flow model in municipal asset management

    Science.gov (United States)

    Bowman, L. K.; Unger, A.; Jones, J. P.

    2014-12-01

    Access to affordable potable water is critical in the development and maintenance of urban centres. Given that water is a public good in Canada, all funds related to operation and maintenance of the drinking water and wastewater networks must come from consumers. An asset management system can be put in place by municipalities to more efficiently manage their water and wastewater distribution system to ensure proper use of these funds. The system works at the operational, tactical, and strategic levels, thus ensuring optimal scheduling of operation and maintenance activities, as well as prediction of future water demand scenarios. At the operational level, a fully integrated model is used to simulate the groundwater-surface water interaction of the Laurel Creek Watershed, of which 80% is urbanized by the City of Waterloo. Canadian municipalities typically lose 13% of their potable water through leaks in watermains and sanitary sewers, and sanitary sewers often generate substantial inflows from fractures in pipe walls. The City of Waterloo sanitary sewers carry an additional 10,000 cubic meters of water to wastewater treatment plants. Therefore, watermain and sanitary sewers present a significant impact on the groundwater-surface water interaction, as well as the affordability of the drinking water and wastewater networks as a whole. To determine areas of concern within the network, the integrated groundwater-surface water model also simulates flow through the City of Waterloo's watermain and sanitary sewer networks. The final model will be used to assess the interaction between measured losses of water from the City of Waterloo's watermain system, infiltration into the sanitary sewer system adjacent to the watermains, and the response of the groundwater system to deteriorated sanitary sewers or to pipes that have been recently renovated. This will ultimately contribute to the City of Waterloo's municipal asset management plan.

  9. Geiger-Mode Avalanche Photodiode Arrays Integrated to All-Digital CMOS Circuits

    Science.gov (United States)

    Aull, Brian

    2016-01-01

    This article reviews MIT Lincoln Laboratory's work over the past 20 years to develop photon-sensitive image sensors based on arrays of silicon Geiger-mode avalanche photodiodes. Integration of these detectors to all-digital CMOS readout circuits enable exquisitely sensitive solid-state imagers for lidar, wavefront sensing, and passive imaging. PMID:27070609

  10. Geiger-Mode Avalanche Photodiode Arrays Integrated to All-Digital CMOS Circuits

    OpenAIRE

    Brian Aull

    2016-01-01

    This article reviews MIT Lincoln Laboratory's work over the past 20 years to develop photon-sensitive image sensors based on arrays of silicon Geiger-mode avalanche photodiodes. Integration of these detectors to all-digital CMOS readout circuits enable exquisitely sensitive solid-state imagers for lidar, wavefront sensing, and passive imaging.

  11. Silicon Compatible Materials, Processes, and Technologies for Advanced Integrated Circuits and Emerging Applications 6

    NARCIS (Netherlands)

    Roozeboom, F.; Narayanan, V.; Kakushima, K.; Timans, P.J.; Gusev, E.P.; Karim, Z.; Gendt, S. De

    2016-01-01

    The topics of this annual symposium continue to describe the evolution of traditional scaling in CMOS integrated circuit manufacturing (More Moore for short), combined with the opportunities from growing diversification and embedded functionality (More than Moore). Once again, the main objective was

  12. Geiger-Mode Avalanche Photodiode Arrays Integrated to All-Digital CMOS Circuits

    Directory of Open Access Journals (Sweden)

    Brian Aull

    2016-04-01

    Full Text Available This article reviews MIT Lincoln Laboratory's work over the past 20 years to develop photon-sensitive image sensors based on arrays of silicon Geiger-mode avalanche photodiodes. Integration of these detectors to all-digital CMOS readout circuits enable exquisitely sensitive solid-state imagers for lidar, wavefront sensing, and passive imaging.

  13. Geiger-Mode Avalanche Photodiode Arrays Integrated to All-Digital CMOS Circuits.

    Science.gov (United States)

    Aull, Brian

    2016-01-01

    This article reviews MIT Lincoln Laboratory's work over the past 20 years to develop photon-sensitive image sensors based on arrays of silicon Geiger-mode avalanche photodiodes. Integration of these detectors to all-digital CMOS readout circuits enable exquisitely sensitive solid-state imagers for lidar, wavefront sensing, and passive imaging. PMID:27070609

  14. Experimental simulation of ionizing radiation effects on integrated circuits using ultra-short laser pulses

    International Nuclear Information System (INIS)

    This thesis presents the elaboration of an experimental test bench for integrated circuits by pulsed laser beam, to simulate the radiation effects on electronic components. A model of the interaction laser pulse and silicon has been developed. An electrical model of a MOS transistor transient response to an irradiation is proposed. The test bench automation is detailed. (A.L.B.)

  15. Wideband Monolithic Microwave Integrated Circuit Frequency Converters with GaAs mHEMT Technology

    DEFF Research Database (Denmark)

    Krozer, Viktor; Johansen, Tom Keinicke; Djurhuus, Torsten;

    2005-01-01

    We present monolithic microwave integrated circuit (MMIC) frequency converter, which can be used for up and down conversion, due to the large RF and IF port bandwidth. The MMIC converters are based on commercially available GaAs mHEMT technology and are comprised of a Gilbert mixer cell core...

  16. Development of Application-specific Integrated Circuit for Detector Signal Readout

    Institute of Scientific and Technical Information of China (English)

    LIU; Hai-feng; WAN; Yu-qing; TIAN; Hua-yang

    2013-01-01

    In general,the development of nuclear electronics was mainly promoted by nuclear physics,high energy physics and other disciplines.As nuclear physics research developed,the requirement of detection equipment which contained a large number of detectors gave birth to nuclear electronics ASIC(application-specific integrated circuit).The institutions such as European Organization for Nuclear

  17. 77 FR 19032 - Certain Semiconductor Integrated Circuit Devices and Products Containing Same Notice of Receipt...

    Science.gov (United States)

    2012-03-29

    ...Notice is hereby given that the U.S. International Trade Commission has received a complaint entitled Certain Semiconductor Integrated Circuit Devices and Products Containing Same, DN 2888; the Commission is soliciting comments on any public interest issues raised by the complaint or complainant's filing under section 210.8(b) of the Commission's Rules of Practice and Procedure (19 CFR......

  18. 77 FR 42764 - Certain Integrated Circuits, Chipsets, & Products Containing Same Including Televisions; Notice...

    Science.gov (United States)

    2012-07-20

    ...Notice is hereby given that the presiding administrative law judge has issued a Final Initial Determination and Recommended Determination on Remedy and Bonding in the above-captioned investigation. The Commission is soliciting comments on public interest issues raised by the recommended relief, specifically a limited exclusion order against certain integrated circuits, chipsets, and products......

  19. 78 FR 10635 - Certain Integrated Circuit Devices and Products Containing the Same; Notice of Receipt of...

    Science.gov (United States)

    2013-02-14

    ...Notice is hereby given that the U.S. International Trade Commission has received a complaint entitled Certain Integrated Circuit Devices and Products Containing the Same, DN 2938; the Commission is soliciting comments on any public interest issues raised by the complaint or complainant's filing under section 210.8(b) of the Commission's Rules of Practice and Procedure (19 CFR...

  20. 76 FR 76434 - Certain Integrated Circuits, Chipsets, and Products Containing Same Including Televisions...

    Science.gov (United States)

    2011-12-07

    ...Notice is hereby given that the U.S. International Trade Commission has received a complaint entitled In Re Certain Integrated Circuits, Chipsets, And Products Containing Same including Televisions, DN 2860; the Commission is soliciting comments on any public interest issues raised by the...

  1. 77 FR 33486 - Certain Integrated Circuit Packages Provided With Multiple Heat-Conducting Paths and Products...

    Science.gov (United States)

    2012-06-06

    ...Notice is hereby given that the U.S. International Trade Commission has received a complaint entitled Certain Integrated Circuit Packages Provided With Multiple Heat-Conducting Paths and Products Containing Same, DN 2899; the Commission is soliciting comments on any public interest issues raised by the complaint or complainant's filing under section 210.8(b) of the Commission's Rules of......

  2. Effective Teaching of the Physical Design of Integrated Circuits Using Educational Tools

    Science.gov (United States)

    Aziz, Syed Mahfuzul; Sicard, Etienne; Ben Dhia, Sonia

    2010-01-01

    This paper presents the strategies used for effective teaching and skill development in integrated circuit (IC) design using project-based learning (PBL) methodologies. It presents the contexts in which these strategies are applied to IC design courses at the University of South Australia, Adelaide, Australia, and the National Institute of Applied…

  3. 77 FR 60721 - Certain Semiconductor Integrated Circuit Devices and Products Containing Same; Notice of...

    Science.gov (United States)

    2012-10-04

    ... (``Microchip''). 77 FR 25747-48 (May 1, 2012). The complaint alleges violations of section 337 of the Tariff... COMMISSION Certain Semiconductor Integrated Circuit Devices and Products Containing Same; Notice of... importation, and the sale within the United States after importation of certain semiconductor...

  4. A 160 μA biopotential acquisition IC with fully integrated IA and motion artifact suppression.

    Science.gov (United States)

    Van Helleputte, Nick; Kim, Sunyoung; Kim, Hyejung; Kim, Jong Pal; Van Hoof, Chris; Yazicioglu, Refet Firat

    2012-12-01

    This paper proposes a 3-channel biopotential monitoring ASIC with simultaneous electrode-tissue impedance measurements which allows real-time estimation of motion artifacts on each channel using an an external μC. The ASIC features a high performance instrumentation amplifier with fully integrated sub-Hz HPF rejecting rail-to-rail electrode-offset voltages. Each readout channel further has a programmable gain amplifier and programmable 4th order low-pass filter. Time-multiplexed 12 b SAR-ADCs are used to convert all the analog data to digital. The ASIC achieves >; 115 dB of CMRR (at 50/60 Hz), a high input impedance of >; 1 GΩ and low noise (1.3 μVrms in 100 Hz). Unlike traditional methods, the ASIC is capable of actual motion artifact suppression in the analog domain before final amplification. The complete ASIC core operates from 1.2 V with 2 V digital IOs and consumes 200 μW when all 3 channels are active. PMID:23853256

  5. Fully Integrated Passive UHF RFID Tag for Hash-Based Mutual Authentication Protocol

    Directory of Open Access Journals (Sweden)

    Shugo Mikami

    2015-01-01

    Full Text Available Passive radio-frequency identification (RFID tag has been used in many applications. While the RFID market is expected to grow, concerns about security and privacy of the RFID tag should be overcome for the future use. To overcome these issues, privacy-preserving authentication protocols based on cryptographic algorithms have been designed. However, to the best of our knowledge, evaluation of the whole tag, which includes an antenna, an analog front end, and a digital processing block, that runs authentication protocols has not been studied. In this paper, we present an implementation and evaluation of a fully integrated passive UHF RFID tag that runs a privacy-preserving mutual authentication protocol based on a hash function. We design a single chip including the analog front end and the digital processing block. We select a lightweight hash function supporting 80-bit security strength and a standard hash function supporting 128-bit security strength. We show that when the lightweight hash function is used, the tag completes the protocol with a reader-tag distance of 10 cm. Similarly, when the standard hash function is used, the tag completes the protocol with the distance of 8.5 cm. We discuss the impact of the peak power consumption of the tag on the distance of the tag due to the hash function.

  6. Silicon based millimeterwave integrated circuits for multi giga-bits-per-second wireless data

    OpenAIRE

    Kodkani, Rahul M.

    2009-01-01

    This research focuses on the design of silicon based millimeterwave integrated circuits for Multi Giga bits-per -second wireless communications. The use of Active sub- harmonic Mixers(ASHM) and Passive Sub-harmonic Mixers (PSHM) for millimeterwave receivers was explored for their advantages over fundamental order mixers. A multi-phase active sub-harmonic mixer/downconverter with an on-chip integrated ring Voltage Controlled Oscillator(VCO) was designed for millimeterwave wireless systems in a...

  7. Flexible packaging of solid-state integrated circuit chips with elastomeric microfluidics

    OpenAIRE

    Bowei Zhang; Quan Dong; Korman, Can E.; Zhenyu Li; Zaghloul, Mona E.

    2013-01-01

    A flexible technology is proposed to integrate smart electronics and microfluidics all embedded in an elastomer package. The microfluidic channels are used to deliver both liquid samples and liquid metals to the integrated circuits (ICs). The liquid metals are used to realize electrical interconnects to the IC chip. This avoids the traditional IC packaging challenges, such as wire-bonding and flip-chip bonding, which are not compatible with current microfluidic technologies. As a demonstratio...

  8. An analog integrated signal processing circuit for on-chip diffusion-based gas analysis

    International Nuclear Information System (INIS)

    In diffusion-based gas analysis, the transient of gas diffusion process is recorded by a generic gas sensor to serve as a fingerprint for qualitative and quantitative analysis of gaseous samples. Following the acquisition of these specific signals, any standalone gas analyzer requires a pattern recognition system for pattern classification. The classic digital pattern recognition methods require computing hardware of adequate computational throughput. In this paper, we have followed a straightforward mathematical procedure to relate the signals to their associated target gases. We have shown that the procedure can be implemented by a set of analog functions. Based on the results, we have designed an analog integrated circuit, in 0.18 µm standard CMOS process, for processing the diffusion-based transient signals. The main circuit components are a low-pass filter, the differentiator, the feature extractor and an artificial neural network. The output of the circuit is a 2-bit binary code that specifies the target gas. The circuit successfully classified four alcoholic vapors by processing the experimentally obtained response patterns. The proposed signal processing circuit, the semiconductor gas sensor and the diffusion channel can all be implemented on a single substrate to fabricate an integrated micro gas analyzer. (paper)

  9. A High-Temperature Piezoresistive Pressure Sensor with an Integrated Signal-Conditioning Circuit

    Directory of Open Access Journals (Sweden)

    Zong Yao

    2016-06-01

    Full Text Available This paper focuses on the design and fabrication of a high-temperature piezoresistive pressure sensor with an integrated signal-conditioning circuit, which consists of an encapsulated pressure-sensitive chip, a temperature compensation circuit and a signal-conditioning circuit. A silicon on insulation (SOI material and a standard MEMS process are used in the pressure-sensitive chip fabrication, and high-temperature electronic components are adopted in the temperature-compensation and signal-conditioning circuits. The entire pressure sensor achieves a hermetic seal and can be operated long-term in the range of −50 °C to 220 °C. Unlike traditional pressure sensor output voltage ranges (in the dozens to hundreds of millivolts, the output voltage of this sensor is from 0 V to 5 V, which can significantly improve the signal-to-noise ratio and measurement accuracy in practical applications of long-term transmission based on experimental verification. Furthermore, because this flexible sensor’s output voltage is adjustable, general follow-up pressure transmitter devices for voltage converters need not be used, which greatly reduces the cost of the test system. Thus, the proposed high-temperature piezoresistive pressure sensor with an integrated signal-conditioning circuit is expected to be highly applicable to pressure measurements in harsh environments.

  10. A High-Temperature Piezoresistive Pressure Sensor with an Integrated Signal-Conditioning Circuit.

    Science.gov (United States)

    Yao, Zong; Liang, Ting; Jia, Pinggang; Hong, Yingping; Qi, Lei; Lei, Cheng; Zhang, Bin; Xiong, Jijun

    2016-06-18

    This paper focuses on the design and fabrication of a high-temperature piezoresistive pressure sensor with an integrated signal-conditioning circuit, which consists of an encapsulated pressure-sensitive chip, a temperature compensation circuit and a signal-conditioning circuit. A silicon on insulation (SOI) material and a standard MEMS process are used in the pressure-sensitive chip fabrication, and high-temperature electronic components are adopted in the temperature-compensation and signal-conditioning circuits. The entire pressure sensor achieves a hermetic seal and can be operated long-term in the range of -50 °C to 220 °C. Unlike traditional pressure sensor output voltage ranges (in the dozens to hundreds of millivolts), the output voltage of this sensor is from 0 V to 5 V, which can significantly improve the signal-to-noise ratio and measurement accuracy in practical applications of long-term transmission based on experimental verification. Furthermore, because this flexible sensor's output voltage is adjustable, general follow-up pressure transmitter devices for voltage converters need not be used, which greatly reduces the cost of the test system. Thus, the proposed high-temperature piezoresistive pressure sensor with an integrated signal-conditioning circuit is expected to be highly applicable to pressure measurements in harsh environments.

  11. A METHOD AND AN APPARATUS FOR PROVIDING TIMING SIGNALS TO A NUMBER OF CIRCUITS, AN INTEGRATED CIRCUIT AND A NODE

    DEFF Research Database (Denmark)

    2006-01-01

    A method of providing or transporting a timing signal between a number of circuits, electrical or optical, where each circuit is fed by a node. The nodes forward timing signals between each other, and at least one node is adapted to not transmit a timing signal before having received a timing...... signal from at least two nodes. In this manner, the direction of the timing skew between nodes and circuits is known and data transport between the circuits made easier....

  12. Hydrogenated Amorphous Silicon Sensor Deposited on Integrated Circuit for Radiation Detection

    OpenAIRE

    Despeisse, M; Anelli, G.; Jarron, P.; Kaplon, J; Moraes, D.; A. Nardulli(Institute for Particle Physics, ETH Zurich, Zurich, Switzerland); Powolny, F; Wyrsch, N

    2008-01-01

    Radiation detectors based on the deposition of a 10 to 30 μm thick hydrogenated amorphous silicon (a-Si:H) sensor directly on top of integrated circuits have been developed. The performance of this detector technology has been assessed for the first time in the context of particle detectors. Three different circuits were designed in a quarter micron CMOS technology for these studies. The so-called TFA (Thin-Film on ASIC) detectors obtained after deposition of a-Si:H sensors on the developed c...

  13. Design and Verification of Application Specific Integrated Circuits in a Network of Online Labs

    Directory of Open Access Journals (Sweden)

    A.Y. Al-Zoubi

    2009-08-01

    Full Text Available A solution to implement a remote laboratory for testing and designing analog Application-Specific Integrated Circuits of the type (ispPAC10 is presented. The application allows electrical engineering students to access and perform measurements and conduct analog electronics experiments over the internet. PAC-Designer software, running on a Citrix server, is used in the circuit design in which the signals are generated and the responses are acquired by a data acquisition board controlled by LabVIEW. Three interconnected remote labs located in three different continents will be implementing the proposed system.

  14. Measurements of complex impedance in microwave high power systems with a new bluetooth integrated circuit.

    Science.gov (United States)

    Roussy, Georges; Dichtel, Bernard; Chaabane, Haykel

    2003-01-01

    By using a new integrated circuit, which is marketed for bluetooth applications, it is possible to simplify the method of measuring the complex impedance, complex reflection coefficient and complex transmission coefficient in an industrial microwave setup. The Analog Devices circuit AD 8302, which measures gain and phase up to 2.7 GHz, operates with variable level input signals and is less sensitive to both amplitude and frequency fluctuations of the industrial magnetrons than are mixers and AM crystal detectors. Therefore, accurate gain and phase measurements can be performed with low stability generators. A mechanical setup with an AD 8302 is described; the calibration procedure and its performance are presented. PMID:15078067

  15. A novel high voltage start up circuit for an integrated switched mode power supply

    Energy Technology Data Exchange (ETDEWEB)

    Hu Hao; Chen Xingbi, E-mail: huhao21@uestc.edu.c [State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054 (China)

    2010-09-15

    A novel high voltage start up circuit for providing an initial bias voltage to an integrated switched mode power supply (SMPS) is presented. An enhanced mode VDMOS transistor, the gate of which is biased by a floating p-island, is used to provide start up current and sustain high voltage. An NMOS transistor having a high source to ground breakdown voltage is included to extend the bias voltage range to the SMPS. Simulation results indicate that the high voltage start up circuit can start and restart as designed. The proposed structure is believed to be more energy saving and cost-effective compared with other solutions. (semiconductor devices)

  16. LARGE-SCALE PHOTONIC INTEGRATED CIRCUIT FOR QPSK REGENERATION AND WAVELENGTH CONVERSION USING SOA-MZI

    Directory of Open Access Journals (Sweden)

    V.BHARATHI

    2013-06-01

    Full Text Available We investigate through numerical studies and experiments the performance of QPSK regeneration and wavelength-conversion of a large scale, silica-on-silicon photonic integrated circuit using cross phase modulation in a semiconductor optical amplifier(SOA. The phase changing is obtained because of the XPM in SOA. The QPSK signal is generated from 10 Gb/s two NRZ- OOK signals and RZ clock pulse signal. Simulation studies reveal the wavelength conversion potential of the circuit with enhanced regenerative capability of QPSK modulation. The tolerance power, BER, and Q factor value is analytically evaluated. Also calculate the power penalty.

  17. 4H-SiC JFET Multilayer Integrated Circuit Technologies Tested Up to 1000 K

    Science.gov (United States)

    Spry, D. J.; Neudeck, P. G.; Chen, L.; Chang, C. W.; Lukco, D.; Beheim, G. M.

    2015-01-01

    Testing of semiconductor electronics at temperatures above their designed operating envelope is recognized as vital to qualification and lifetime prediction of circuits. This work describes the high temperature electrical testing of prototype 4H silicon carbide (SiC) junction field effect transistor (JFET) integrated circuits (ICs) technology implemented with multilayer interconnects; these ICs are intended for prolonged operation at temperatures up to 773K (500 C). A 50 mm diameter sapphire wafer was used in place of the standard NASA packaging for this experiment. Testing was carried out between 300K (27 C) and 1150K (877 C) with successful electrical operation of all devices observed up to 1000K (727 C).

  18. Combined Self-Test of Analog Portion and ADCs in Integrated Mixed-Signal Circuits

    Science.gov (United States)

    Hu, Geng; Wang, Hong; Yang, Shiyuan

    Testing is a critical stage in integrated circuits production in order to guarantee reliability. The complexity and high integration level of mixed-signal ICs has put forward new challenges to circuit testing. This paper describes an oscillation-based combined self-test strategy for the analog portion and analog-to-digital converters (ADCs) in integrated mixed-signal circuits. In test mode, the analog portion under test is reconfigured into an oscillator, generating periodic signals as the test stimulus of ADC. By analyzing the A/D conversion results, a histogram test of ADC can be performed, and the oscillation frequency as well as amplitude can be checked, and in this way the oscillation test of the analog portion is realized simultaneously. For an analog benchmark circuit combined with an ADC, triangle oscillation and sinusoid oscillation schemes are both given to test their faults. Experimental results show that fault coverage of the analog portion is 92.2% and 94.3% in the two schemes respectively, and faults in the ADC can also be tested.

  19. Impact-Based Area Allocation for Yield Optimization in Integrated Circuits

    Science.gov (United States)

    Abraham, Billion; Widodo, Arif; Chen, Poki

    2016-06-01

    In analog integrated circuit (IC) layout, area allocation is a very important issue for achieving good mismatch cancellation. However, most IC layout papers focus only on layout strategy to reduce systematic mismatch. In 2006, an outstanding paper presenting area allocation strategy was published to introduce technique for random mismatch reduction. Instead of using general theoretical study to prove the strategy, this research presented close-to-optimum simulations only on case-bycase basis. The impact-based area allocation for yield optimization in integrated circuits is proposed in this chapter. To demonstrate the corresponding strategy, not only a theoretical analysis but also an integral nonlinearity-based yield simulation will be given to derive optimum area allocation for binary weighted current steering digital-to-analog converter (DAC). The result will be concluded to convince IC designers how to allocate area for critical devices in an optimum way.

  20. The simulation of a readout integrated circuit with high dynamic range for long wave infrared FPA

    Science.gov (United States)

    Zhai, Yongcheng; Ding, Rui-jun; Chen, Guo-qiang; Wang, Pan; Hao, Li-chao

    2013-12-01

    This paper describes the simulation results of a high performance readout integrated circuit (ROIC) designed for long wave infrared (LWIR) detectors, which has high dynamic range (HDR). A special architecture is used to the input unit cell to accommodate the wide scene dynamic range requirement, thus providing over a factor of 70dB dynamic range. A capacitive feedback transimpedance amplifier (CTIA) provides a low noise detector interface circuit capable of operating at low input currents and a folded cascade amplifier with a gain of 73dB is designed. A 6.4pF integration capacitor is used for supporting a wide scene dynamic range, which can store 80Me. Because of the restriction of the layout area, four unit cells will share an integration capacitor. A sample and hold capacitor is also part of the input unit cell architecture, which allows the infrared focal plane arrays (IRFPA) to be operated in full frame snapshot mode and provides the maximum integration time available. The integration time is electronically controlled by an external clock pulse. The simulation results show that the circuit works well under 5V power supply and the nonlinearity is calculated less than 0.1%. The total power dissipation is less than 150mW.

  1. A smart fully integrated micromachined separator with soft magnetic micro-pillar arrays for cell isolation

    Science.gov (United States)

    Dong, Tao; Su, Qianhua; Yang, Zhaochu; Zhang, Yulong; Egeland, Eirik B.; Gu, Dan D.; Calabrese, Paolo; Kapiris, Matteo J.; Karlsen, Frank; Minh, Nhut T.; Wang, K.; Jakobsen, Henrik

    2010-11-01

    A smart fully integrated micromachined separator with soft magnetic micro-pillar arrays has been developed and demonstrated, which can merely employ one independent lab-on-chip to realize cell isolation. The simulation, design, microfabrication and test for the new electromagnetic micro separator were executed. The simulation results of the electromagnetic field in the separator show that special soft magnetic micro-pillar arrays can amplify and redistribute the electromagnetic field generated by the micro-coils. The separator can be equipped with a strong magnetic field to isolate the target cells with a considerably low input current. The micro separator was fabricated by micro-processing technology. An electroplating bath was hired to deposit NiCo/NiFe to fabricate the micro-pillar arrays. An experimental system was set up to verify the function of the micro separator by isolating the lymphocytes, in which the human whole blood mixed with Dynabeads® FlowComp Flexi and monoclonal antibody MHCD2704 was used as the sample. The results show that the electromagnetic micro separator with an extremely low input current can recognize and capture the target lymphocytes with a high efficiency, the separation ratio reaching more than 90% at a lower flow rate. For the electromagnetic micro separator, there is no external magnetizing field required, and there is no extra cooling system because there is less Joule heat generated due to the lower current. The magnetic separator is totally reusable, and it can be used to separate cells or proteins with common antigens.

  2. Integrated circuits and molecular components for stress and feeding: implications for eating disorders

    Science.gov (United States)

    Hardaway, J. A.; Crowley, N. A.; Bulik, C. M.; Kash, T. L.

    2015-01-01

    Eating disorders are complex brain disorders that afflict millions of individuals worldwide. The etiology of these diseases is not fully understood, but a growing body of literature suggests that stress and anxiety may play a critical role in their development. As our understanding of the genetic and environmental factors that contribute to disease in clinical populations like anorexia nervosa, bulimia nervosa and binge eating disorder continue to grow, neuroscientists are using animal models to understand the neurobiology of stress and feeding. We hypothesize that eating disorder clinical phenotypes may result from stress-induced maladaptive alterations in neural circuits that regulate feeding, and that these circuits can be neurochemically isolated using animal model of eating disorders. PMID:25366309

  3. SINIS fabrication process for realizing integrated circuits in RSFQ impulse logic

    Energy Technology Data Exchange (ETDEWEB)

    Balashov, D.; Khabipov, M.I.; Buchholz, F-Im.; Kessel, W.; Niemeyer, J. [Physikalisch-Technische Bundesanstalt, Bundesallee 100, D-38116 Braunschweig (Germany)

    1999-11-01

    At PTB, a new type of fabrication process has been developed to verify rapid single flux quantum (RSFQ) integrated circuits based on intrinsically shunted two-tunnel Josephson junctions (JJs). The process has been realized in LTS implementation using SINIS technology. A variety of single JJs, junction arrays and test circuits have been fabricated and experimentally investigated. The critical current densities of the junctions were set to a nominal value of j{sub C} = 500 A cm{sup -2}, with values of the characteristic voltage V{sub C} equal to or larger than 160 {mu}V. The JJs show nearly hysteresis-free behaviour (less than 10%); the intrawafer parameter spread is smaller than {+-}10%. Various basic RSFQ circuits have been realized with operation margins of bias currents of larger than {+-}20%. (author)

  4. Moving the boundary between wavelength resources in optical packet and circuit integrated ring network.

    Science.gov (United States)

    Furukawa, Hideaki; Miyazawa, Takaya; Wada, Naoya; Harai, Hiroaki

    2014-01-13

    Optical packet and circuit integrated (OPCI) networks provide both optical packet switching (OPS) and optical circuit switching (OCS) links on the same physical infrastructure using a wavelength multiplexing technique in order to deal with best-effort services and quality-guaranteed services. To immediately respond to changes in user demand for OPS and OCS links, OPCI networks should dynamically adjust the amount of wavelength resources for each link. We propose a resource-adjustable hybrid optical packet/circuit switch and transponder. We also verify that distributed control of resource adjustments can be applied to the OPCI ring network testbed we developed. In cooperation with the resource adjustment mechanism and the hybrid switch and transponder, we demonstrate that automatically allocating a shared resource and moving the wavelength resource boundary between OPS and OCS links can be successfully executed, depending on the number of optical paths in use.

  5. Study on Pulse Skip Modulation Mode in Smart Power Integrated Circuits and Its Test Technology

    Institute of Scientific and Technical Information of China (English)

    LUO Ping

    2005-01-01

    @@ Up to now, the popular control modes for smart power integrated circuit (SPIC) are PWM and PFM.PWM bases on constant frequency variable width (CFVW) control pulse, whereas, PFM bases on constant width variable frequency (CWVF) control pulse. PWM converter has low efficiency with light loads and high amplitude harmonic. On the other hand,the control circuit and filter for PFM are much complex. This dissertation proposes a novel modulation mode named pulse skip modulation (PSM)for SPIC converter, which bases on constant width constant frequency (CWCF) control pulse. It is shown that PSM converter would improve its efficiency and suppress EMI. It also has quick response speed, good interfere rejection and strong robust. Furthermore, it is easy to realize PSM control circuit. The modulating theories of PSM are firstly studied in the world according to the author's investigation.

  6. A wirelessly readable and resettable shock recorder through the integration of LC circuits and MEMS devices

    International Nuclear Information System (INIS)

    This paper presents a passive shock recorder to record shock events for tens of Gs with wireless reading and wireless resetting capabilities through the integration of LC circuits and two MEMS devices. With a micro mechanical-latch shock switch electrically connected to the sensing LC circuit, the shock event that leads to different latching states can be recorded and wirelessly read through the LC resonant frequency. With a micro electro-thermal actuator electrically connected to a wirelessly powered actuating LC circuit, the energy can be wirelessly sent to the micro actuator to provide the necessary unlatched force. By integrating the mechanical-latch shock switch and actuator with LC circuits, the latching state can be reset through the wireless actuation. Therefore, the shock recorder can be used repeatedly. Here, the mechanical-latch shock switch is designed to have a two-level shock recording capability. The fabrication of the shock switch and actuator are achieved by a Ni-based surface micromachining process. When the acceleration reaches 28.06 G, the latching state changes from the original state to the first latching state. The resonant frequency of sensing for the LC circuit is found to switch from 10.14 MHz to 9.16 MHz, correspondingly. By further applying acceleration up to 37.10 G, the latching state changes from the first latching state to the second state, and the resonant frequency shifts to 7.83 MHz. Then, with a current of 2.07 AAC wirelessly induced in the actuating LC circuit, the micro electro-thermal actuator is shown to provide sufficient displacement to reset the shock switch from a latched state back to the original unlatched state, and the resonant frequency is switched back to 10.14 MHz. The fabricated shock recorder is repeatedly tested five times. The wireless reading, resetting and shock recording capabilities are successfully verified. (paper)

  7. Towards scalable networks of solid-state quantum memories in a photonic integrated circuit (Presentation Recording)

    Science.gov (United States)

    Englund, Dirk R.

    2015-09-01

    A central goal of quantum information science is the entanglement of multiple quantum memories that can be individually controlled. Here, we discuss progress towards photonic integrated circuits designed to enable efficient optical interactions between multiple spin qubits in nitrogen vacancy (NV) centers in diamond. We describe NV-nanocavity systems in the strong Purcell regime with optical quality factors approaching 10,000 and electron spin coherence times exceeding 200 μs implantation of NVs with nanometer-scale apertures, including into cavity field maxima; hybrid on-chip networks for integration of multiple functional NV-cavity systems; and scalable integration of superconducting nanowire single photon detectors on-chip.

  8. A new circuit model of HgCdTe photodiode for SPICE simulation of integrated IRFPA

    Science.gov (United States)

    Saxena, Raghvendra Sahai; Saini, Navneet Kaur; Bhan, R. K.; Sharma, R. K.

    2014-11-01

    We propose a novel sub circuit model to simulate HgCdTe infrared photodiodes in a circuit simulator, like PSPICE. We have used two diodes of opposite polarity in parallel to represent the forward biased and the reverse biased behavior of an HgCdTe photodiode separately. We also connected a resistor in parallel with them to represent the ohmic shunt and a constant current source to represent photocurrent. We show that by adjusting the parameters in standard diode models and the resistor and current values, we could actually fit the measured data of our various HgCdTe photodiodes having different characteristics. This is a very efficient model that can be used for simulation of readout integrated circuit (ROIC) for HgCdTe IR photodiode arrays. This model also allows circuit level Monte Carlo simulation on a complete IRFPA at a single circuit simulator platform to estimate the non-uniformity for given processes of HgCdTe device fabrication and Si ROIC fabrication.

  9. Integrated Power Flow and Short Circuit Calculation Method for Distribution Network with Inverter Based Distributed Generation

    Directory of Open Access Journals (Sweden)

    Shan Yang

    2016-01-01

    Full Text Available Power flow calculation and short circuit calculation are the basis of theoretical research for distribution network with inverter based distributed generation. The similarity of equivalent model for inverter based distributed generation during normal and fault conditions of distribution network and the differences between power flow and short circuit calculation are analyzed in this paper. Then an integrated power flow and short circuit calculation method for distribution network with inverter based distributed generation is proposed. The proposed method let the inverter based distributed generation be equivalent to Iθ bus, which makes it suitable to calculate the power flow of distribution network with a current limited inverter based distributed generation. And the low voltage ride through capability of inverter based distributed generation can be considered as well in this paper. Finally, some tests of power flow and short circuit current calculation are performed on a 33-bus distribution network. The calculated results from the proposed method in this paper are contrasted with those by the traditional method and the simulation method, whose results have verified the effectiveness of the integrated method suggested in this paper.

  10. High-voltage integrated active quenching circuit for single photon count rate up to 80 Mcounts/s.

    Science.gov (United States)

    Acconcia, Giulia; Rech, Ivan; Gulinatti, Angelo; Ghioni, Massimo

    2016-08-01

    Single photon avalanche diodes (SPADs) have been subject to a fast improvement in recent years. In particular, custom technologies specifically developed to fabricate SPAD devices give the designer the freedom to pursue the best detector performance required by applications. A significant breakthrough in this field is represented by the recent introduction of a red enhanced SPAD (RE-SPAD) technology, capable of attaining a good photon detection efficiency in the near infrared range (e.g. 40% at a wavelength of 800 nm) while maintaining a remarkable timing resolution of about 100ps full width at half maximum. Being planar, the RE-SPAD custom technology opened the way to the development of SPAD arrays particularly suited for demanding applications in the field of life sciences. However, to achieve such excellent performance custom SPAD detectors must be operated with an external active quenching circuit (AQC) designed on purpose. Next steps toward the development of compact and practical multichannel systems will require a new generation of monolithically integrated AQC arrays. In this paper we present a new, fully integrated AQC fabricated in a high-voltage 0.18 µm CMOS technology able to provide quenching pulses up to 50 Volts with fast leading and trailing edges. Although specifically designed for optimal operation of RE-SPAD devices, the new AQC is quite versatile: it can be used with any SPAD detector, regardless its fabrication technology, reaching remarkable count rates up to 80 Mcounts/s and generating a photon detection pulse with a timing jitter as low as 119 ps full width at half maximum. The compact design of our circuit has been specifically laid out to make this IC a suitable building block for monolithically integrated AQC arrays.

  11. 2.3 µm range InP-based type-II quantum well Fabry-Perot lasers heterogeneously integrated on a silicon photonic integrated circuit.

    Science.gov (United States)

    Wang, Ruijun; Sprengel, Stephan; Boehm, Gerhard; Muneeb, Muhammad; Baets, Roel; Amann, Markus-Christian; Roelkens, Gunther

    2016-09-01

    Heterogeneously integrated InP-based type-II quantum well Fabry-Perot lasers on a silicon waveguide circuit emitting in the 2.3 µm wavelength range are demonstrated. The devices consist of a "W"-shaped InGaAs/GaAsSb multi-quantum-well gain section, III-V/silicon spot size converters and two silicon Bragg grating reflectors to form the laser cavity. In continuous-wave (CW) operation, we obtain a threshold current density of 2.7 kA/cm2 and output power of 1.3 mW at 5 °C for 2.35 μm lasers. The lasers emit over 3.7 mW of peak power with a threshold current density of 1.6 kA/cm2 in pulsed regime at room temperature. This demonstration of heterogeneously integrated lasers indicates that the material system and heterogeneous integration method are promising to realize fully integrated III-V/silicon photonics spectroscopic sensors in the 2 µm wavelength range. PMID:27607711

  12. 2.3 µm range InP-based type-II quantum well Fabry-Perot lasers heterogeneously integrated on a silicon photonic integrated circuit.

    Science.gov (United States)

    Wang, Ruijun; Sprengel, Stephan; Boehm, Gerhard; Muneeb, Muhammad; Baets, Roel; Amann, Markus-Christian; Roelkens, Gunther

    2016-09-01

    Heterogeneously integrated InP-based type-II quantum well Fabry-Perot lasers on a silicon waveguide circuit emitting in the 2.3 µm wavelength range are demonstrated. The devices consist of a "W"-shaped InGaAs/GaAsSb multi-quantum-well gain section, III-V/silicon spot size converters and two silicon Bragg grating reflectors to form the laser cavity. In continuous-wave (CW) operation, we obtain a threshold current density of 2.7 kA/cm2 and output power of 1.3 mW at 5 °C for 2.35 μm lasers. The lasers emit over 3.7 mW of peak power with a threshold current density of 1.6 kA/cm2 in pulsed regime at room temperature. This demonstration of heterogeneously integrated lasers indicates that the material system and heterogeneous integration method are promising to realize fully integrated III-V/silicon photonics spectroscopic sensors in the 2 µm wavelength range.

  13. Back End of Line Nanorelays for Ultra-low Power Monolithic Integrated NEMS-CMOS Circuits

    KAUST Repository

    Lechuga Aranda, Jesus Javier

    2016-05-01

    Since the introduction of Complementary-Metal-Oxide-Semiconductor (CMOS) technology, the chip industry has enjoyed many benefits of transistor feature size scaling, including higher speed and device density and improved energy efficiency. However, in the recent years, the IC designers have encountered a few roadblocks, namely reaching the physical limits of scaling and also increased device leakage which has resulted in a slow-down of supply voltage and power density scaling. Therefore, there has been an extensive hunt for alternative circuit architectures and switching devices that can alleviate or eliminate the current crisis in the semiconductor industry. The Nano-Electro-Mechanical (NEM) relay is a promising alternative switch that offers zero leakage and abrupt turn-on behaviour. Even though these devices are intrinsically slower than CMOS transistors, new circuit design techniques tailored for the electromechanical properties of such devices can be leveraged to design medium performance, ultra-low power integrated circuits. In this thesis, we deal with a new generation of such devices that is built in the back end of line (BEOL) CMOS process and is an ideal option for full integration with current CMOS transistor technology. Simulation and verification at the circuit and system level is a critical step in the design flow of microelectronic circuits, and this is especially important for new technologies that lack the standard design infrastructure and well-known verification platforms. Although most of the physical and electrical properties of NEM structures can be simulated using standard electronic automation software, there is no report of a reliable behavioural model for NEMS switches that enable large circuit simulations. In this work, we present an optimised model of a BEOL nano relay that encompasses all the electromechanical characteristics of the device and is robust and lightweight enough for VLSI applications that require simulation of thousands of

  14. Photonic crystal ring resonator based optical filters for photonic integrated circuits

    Energy Technology Data Exchange (ETDEWEB)

    Robinson, S., E-mail: mail2robinson@gmail.com [Department of Electronics and Communication Engineering, Mount Zion College of Engineering and Technology, Pudukkottai-622507, Tamil Nadu (India)

    2014-10-15

    In this paper, a two Dimensional (2D) Photonic Crystal Ring Resonator (PCRR) based optical Filters namely Add Drop Filter, Bandpass Filter, and Bandstop Filter are designed for Photonic Integrated Circuits (PICs). The normalized output response of the filters is obtained using 2D Finite Difference Time Domain (FDTD) method and the band diagram of periodic and non-periodic structure is attained by Plane Wave Expansion (PWE) method. The size of the device is minimized from a scale of few tens of millimeters to the order of micrometers. The overall size of the filters is around 11.4 μm × 11.4 μm which is highly suitable of photonic integrated circuits.

  15. Amorphous Zinc Oxide Integrated Wavy Channel Thin Film Transistor Based High Performance Digital Circuits

    KAUST Repository

    Hanna, Amir

    2015-12-04

    High performance thin film transistor (TFT) can be a great driving force for display, sensor/actuator, integrated electronics, and distributed computation for Internet of Everything applications. While semiconducting oxides like zinc oxide (ZnO) present promising opportunity in that regard, still wide area of improvement exists to increase the performance further. Here, we show a wavy channel (WC) architecture for ZnO integrated TFT which increases transistor width without chip area penalty, enabling high performance in material agnostic way. We further demonstrate digital logic NAND circuit using the WC architecture and compare it to the conventional planar architecture. The WC architecture circuits have shown 2× higher peak-to-peak output voltage for the same input voltage. They also have 3× lower high-to-low propagation delay times, respectively, when compared to the planar architecture. The performance enhancement is attributed to both extra device width and enhanced field effect mobility due to higher gate field electrostatics control.

  16. Localization and Imaging of Integrated Circuit Defect Using Simple Optical Feedback Detection

    Directory of Open Access Journals (Sweden)

    Vernon Julius Cemine

    2004-12-01

    Full Text Available High-contrast microscopy of semiconductor and metal edifices in integrated circuits is demonstrated by combining laser-scanning confocal reflectance microscopy, one-photon optical-beam-induced current (1P-OBIC imaging, and optical feedback detection via a commercially available semiconductor laser that also serves as the excitation source. The confocal microscope has a compact in-line arrangement with no external photodetector. Confocal and 1P-OBIC images are obtained simultaneously from the same focused beam that is scanned across the sample plane. Image pairs are processed to generate exclusive high-contrast distributions of the semiconductor, metal, and dielectric sites in a GaAs photodiode array sample. The method is then utilized to demonstrate defect localization and imaging in an integrated circuit.

  17. A multi-ring optical packet and circuit integrated network with optical buffering.

    Science.gov (United States)

    Furukawa, Hideaki; Shinada, Satoshi; Miyazawa, Takaya; Harai, Hiroaki; Kawasaki, Wataru; Saito, Tatsuhiko; Matsunaga, Koji; Toyozumi, Tatuya; Wada, Naoya

    2012-12-17

    We newly developed a 3 × 3 integrated optical packet and circuit switch-node. Optical buffers and burst-mode erbium-doped fiber amplifiers with the gain flatness are installed in the 3 × 3 switch-node. The optical buffer can prevent packet collisions and decrease packet loss. We constructed a multi-ring optical packet and circuit integrated network testbed connecting two single-ring networks and a client network by the 3 × 3 switch-node. For the first time, we demonstrated 244 km fiber transmission and 5-node hopping of multiplexed 14-wavelength 10 Gbps optical paths and 100 Gbps optical packets encapsulating 10 Gigabit Ethernet frames on the testbed. Error-free (frame error rate < 1 × 10(-4)) operation was achieved with optical packets of various packet lengths. In addition, successful avoidance of packet collisions by optical buffers was confirmed.

  18. Advanced field-solver techniques for RC extraction of integrated circuits

    CERN Document Server

    Yu, Wenjian

    2014-01-01

    Resistance and capacitance (RC) extraction is an essential step in modeling the interconnection wires and substrate coupling effect in nanometer-technology integrated circuits (IC). The field-solver techniques for RC extraction guarantee the accuracy of modeling, and are becoming increasingly important in meeting the demand for accurate modeling and simulation of VLSI designs. Advanced Field-Solver Techniques for RC Extraction of Integrated Circuits presents a systematic introduction to, and treatment of, the key field-solver methods for RC extraction of VLSI interconnects and substrate coupling in mixed-signal ICs. Various field-solver techniques are explained in detail, with real-world examples to illustrate the advantages and disadvantages of each algorithm. This book will benefit graduate students and researchers in the field of electrical and computer engineering, as well as engineers working in the IC design and design automation industries. Dr. Wenjian Yu is an Associate Professor at the Department of ...

  19. Integrated Circuit-Based Biofabrication with Common Biomaterials for Probing Cellular Biomechanics.

    Science.gov (United States)

    Sung, Chun-Yen; Yang, Chung-Yao; Yeh, J Andrew; Cheng, Chao-Min

    2016-02-01

    Recent advances in bioengineering have enabled the development of biomedical tools with modifiable surface features (small-scale architecture) to mimic extracellular matrices and aid in the development of well-controlled platforms that allow for the application of mechanical stimulation for studying cellular biomechanics. An overview of recent developments in common biomaterials that can be manufactured using integrated circuit-based biofabrication is presented. Integrated circuit-based biofabrication possesses advantages including mass and diverse production capacities for fabricating in vitro biomedical devices. This review highlights the use of common biomaterials that have been most frequently used to study cellular biomechanics. In addition, the influence of various small-scale characteristics on common biomaterial surfaces for a range of different cell types is discussed.

  20. Tolerant polarization converter for InGaAsP-InP photonic integrated circuits.

    Science.gov (United States)

    Dzibrou, Dzmitry O; van der Tol, Jos J G M; Smit, Meint K

    2013-09-15

    We report the fabrication and characterization of a new polarization converter for InGaAsP-InP photonic integrated circuits. The converter consists of two right trapezoidal sections with the angled sidewalls etched wetly. The converters show a greatly improved tolerance to variations of the fabrication, an averaged efficiency of polarization conversion of 99.8% and a loss of about 0.7 dB at a wavelength of 1.535 μm. PMID:24104793

  1. Reduction of EMC Emissions in Mixed Signal Integrated Circuits with Embedded LIN Driver

    OpenAIRE

    Hartl, P; M. Kuban; P. Horsky

    2016-01-01

    This paper describes several methods for reduction of electromagnetic emissions (EME) of mixed signal integrated circuits (IC). The focus is on the impact that a LIN bus communication block has on a complex IC which contains analog blocks, noisy digital block, micro-core (µC) and several types of memories. It is used in an automotive environment, where EMC emission reduction is one of the key success factors. Several proposed methods for EME reduction are described and implemented on three te...

  2. Whispering-gallery microcavity semiconductor lasers suitable for photonic integrated circuits and optical interconnects

    Institute of Scientific and Technical Information of China (English)

    2009-01-01

    The characteristics of whispering-gallery-like modes in the equilateral triangle and square microresonators are introduced,including directional emission triangle and square microlasers connected to an output waveguide.We propose a photonic interconnect scheme by connecting two directional emission microlasers with an optical waveguide on silicon integrated circuit chip.The measurement indicates that the triangle microlasers can work as a resonance enhanced photodetector for optical interconnect.

  3. Digital measuring scheme for half-wave voltage of Y-tap multiple integrated optical circuit

    Institute of Scientific and Technical Information of China (English)

    Yuanhong Yang(杨远洪); Hongtao Yu(于洪涛)

    2004-01-01

    A high-precision digital measuring scheme for half-wave voltage of Y-tap multiple integrated optical circuits is proposed. This scheme is based on Sagnac interferometer modulated with digital step waveform whose frequency is half of eigen frequency of the interferometer. The technology and measuring precision are discussed. An experimental setup is made and the temperature-dependences of half-wave voltage of two samples are studied. Analysis and experimental study prove that this scheme is convenient and accurate.

  4. The Effected Oxide Capacitor in CMOS Structure of Integrated Circuit Level 5 Micrometer Technology

    OpenAIRE

    Rodthong, S.; Burapattanasiri, B.

    2009-01-01

    This article is present the effected oxide capacitor in CMOS structure of integrated circuit level 5 micrometer technology. It has designed and basic structure of MOS diode. It establish with aluminum metallization layer by sputtering method, oxide insulator layer mode from silicon dioxide, n+ and p+ semiconductor layer, it has high capacitance concentrate. From the MOS diode structure silicon dioxide thickness 0.5 micrometer, it will get capacitance between aluminum metal layer and p+ semico...

  5. Self-contained sub-millimeter wave rectifying antenna integrated circuit

    Science.gov (United States)

    Siegel, Peter H. (Inventor)

    2004-01-01

    The invention is embodied in a monolithic semiconductor integrated circuit in which is formed an antenna, such as a slot dipole antenna, connected across a rectifying diode. In the preferred embodiment, the antenna is tuned to received an electromagnetic wave of about 2500 GHz so that the device is on the order of a wavelength in size, or about 200 microns across and 30 microns thick. This size is ideal for mounting on a microdevice such as a microrobot for example. The antenna is endowed with high gain in the direction of the incident radiation by providing a quarter-wavelength (30 microns) thick resonant cavity below the antenna, the cavity being formed as part of the monolithic integrated circuit. Preferably, the integrated circuit consists of a thin gallium arsenide membrane overlying the resonant cavity and supporting an epitaxial Gallium Arsenide semiconductor layer. The rectifying diode is a Schottky diode formed in the GaAs semiconductor layer and having an area that is a very small fraction of the wavelength of the 2500 GHz incident radiation. The cavity provides high forward gain in the antenna and isolation from surrounding structure.

  6. I-RaCM: A Fully Integrated Risk and Lifecycle Cost Model Project

    Data.gov (United States)

    National Aeronautics and Space Administration — SpaceWorks Engineering, Inc. (SEI) proposes development of the Integrated Risk and Cost Model I-RaCM, as the innovation to meet the need for integrated cost and...

  7. Terahertz applications of integrated circuits based on intrinsic Josephson junctions in high Tc superconductors

    Science.gov (United States)

    Wang, Huabing; Wu, Peiheng; Yamashita, Tsutomu

    2001-10-01

    Using a newly developed double-side fabrication method, an IJJ stack plus a bow-tie antenna and chokes were integrated in a slice 200 nm thick and singled out from inside a bulk Bi2Sr2CaCu2O8+x (BSCCO) single crystal. The junctions in the fabricated stack were very uniform, and the number of junctions involved was rather controllable. In addition to this method, which can be used to fabricate integrated circuits based on intrinsic Josephson junctions in high temperature (Tc) superconductors, also reported will be terahertz responses of IJJs, and the possible applications in quantum voltage standard, spectroscopy, and so on.

  8. Optoelectronic cross-injection locking of a dual-wavelength photonic integrated circuit for low-phase-noise millimeter-wave generation.

    Science.gov (United States)

    Kervella, Gaël; Van Dijk, Frederic; Pillet, Grégoire; Lamponi, Marco; Chtioui, Mourad; Morvan, Loïc; Alouini, Mehdi

    2015-08-01

    We report on the stabilization of a 90-GHz millimeter-wave signal generated from a fully integrated photonic circuit. The chip consists of two DFB single-mode lasers whose optical signals are combined on a fast photodiode to generate a largely tunable heterodyne beat note. We generate an optical comb from each laser with a microwave synthesizer, and by self-injecting the resulting signal, we mutually correlate the phase noise of each DFB and stabilize the beatnote on a multiple of the frequency delivered by the synthesizer. The performances achieved beat note linewidth below 30 Hz.

  9. Deterministic separation of arbitrary photon pair states in integrated quantum circuits

    CERN Document Server

    Marchildon, Ryan P

    2015-01-01

    Entangled photon pairs generated within integrated devices must often be spatially separated for their subsequent manipulation in quantum circuits. Separation that is both deterministic and universal can in principle be achieved through anti-coalescent two-photon quantum interference. However, such interference-facilitated pair separation (IFPS) has not been extensively studied in the integrated setting, where the strong polarization and wavelength dependencies of integrated couplers -- as opposed to bulk-optics beamsplitters -- can have important implications for performance beyond the identical-photon regime. This paper provides a detailed review of IFPS and examines how these dependencies impact separation fidelity and interference visibility. Focus is given to IFPS mediated by an integrated directional coupler. The analysis applies equally to both on-chip and in-fiber implementations, and can be expanded to other coupler architectures such as multimode interferometers. When coupler dispersion is present, ...

  10. A contact lens with integrated telecommunication circuit and sensors for wireless and continuous tear glucose monitoring

    Science.gov (United States)

    Yao, H.; Liao, Y.; Lingley, A. R.; Afanasiev, A.; Lähdesmäki, I.; Otis, B. P.; Parviz, B. A.

    2012-07-01

    We present an integrated functional contact lens, composed of a differential glucose sensor module, metal interconnects, sensor read-out circuit, antenna and telecommunication circuit, to monitor tear glucose levels wirelessly, continuously and non-invasively. The electrochemical differential sensor module is based on immobilization of activated and de-activated glucose oxidase. We characterized the sensor on a model polymer eye and determined that it showed good repeatability, molecular interference rejection and linearity in the range of 0-2 mM glucose, covering normal tear glucose concentrations (0.1-0.6 mM). We also report the temperature, ageing and protein-fouling sensitivity of the sensor. We report the design and implementation of a low-power (3 µW) sensor read-out and telecommunication circuit to deliver wireless power and transmit data for the sensor module. Using this small chip (0.36 mm2), we produced an integrated contact lens with sensors and demonstrated wireless operation of the system and glucose read-out over the distance of several centimeters.

  11. The functional significance of newly born neurons integrated into olfactory bulb circuits

    Directory of Open Access Journals (Sweden)

    Masayuki eSakamoto

    2014-05-01

    Full Text Available The olfactory bulb (OB is the first central processing center for olfactory information connecting with higher areas in the brain, and this neuronal circuitry mediates a variety of odor-evoked behavioral responses. In the adult mammalian brain, continuous neurogenesis occurs in two restricted regions, the subventricular zone (SVZ of the lateral ventricle and the hippocampal dentate gyrus. New neurons born in the SVZ migrate through the rostral migratory stream and are integrated into the neuronal circuits of the OB throughout life. The significance of this continuous supply of new neurons in the OB has been implicated in plasticity and memory regulation. Two decades of huge investigation in adult neurogenesis revealed the biological importance of integration of new neurons into the olfactory circuits. In this review, we highlight the recent findings about the physiological functions of newly generated neurons in rodent OB circuits and then discuss the contribution of neurogenesis in the brain function. Finally, we introduce cutting edge technologies to monitor and manipulate the activity of new neurons.

  12. A contact lens with integrated telecommunication circuit and sensors for wireless and continuous tear glucose monitoring

    International Nuclear Information System (INIS)

    We present an integrated functional contact lens, composed of a differential glucose sensor module, metal interconnects, sensor read-out circuit, antenna and telecommunication circuit, to monitor tear glucose levels wirelessly, continuously and non-invasively. The electrochemical differential sensor module is based on immobilization of activated and de-activated glucose oxidase. We characterized the sensor on a model polymer eye and determined that it showed good repeatability, molecular interference rejection and linearity in the range of 0–2 mM glucose, covering normal tear glucose concentrations (0.1–0.6 mM). We also report the temperature, ageing and protein-fouling sensitivity of the sensor. We report the design and implementation of a low-power (3 µW) sensor read-out and telecommunication circuit to deliver wireless power and transmit data for the sensor module. Using this small chip (0.36 mm2), we produced an integrated contact lens with sensors and demonstrated wireless operation of the system and glucose read-out over the distance of several centimeters. (paper)

  13. 6H-SiC Transistor Integrated Circuits Demonstrating Prolonged Operation at 500 C

    Science.gov (United States)

    Neudeck, Philip G.; Spry, David J.; Chen, Liang-Yu; Chang, Carl W.; Beheim, Glenn M.; Okojie, Robert S.; Evans, Laura J.; Meredith, Roger; Ferrier, Terry; Krasowski, Michael J.; Prokop, Norman F.

    2008-01-01

    The NASA Glenn Research Center is developing very high temperature semiconductor integrated circuits (ICs) for use in the hot sections of aircraft engines and for Venus exploration where ambient temperatures are well above the approximately 300 degrees Centigrade effective limit of silicon-on-insulator IC technology. In order for beneficial technology insertion to occur, such transistor ICs must be capable of prolonged operation in such harsh environments. This paper reports on the fabrication and long-term 500 degrees Centigrade operation of 6H-SiC integrated circuits based on epitaxial 6H-SiC junction field effect transistors (JFETs). Simple analog amplifier and digital logic gate ICs have now demonstrated thousands of hours of continuous 500 degrees Centigrade operation in oxidizing air atmosphere with minimal changes in relevant electrical parameters. Electrical characterization and modeling of transistors and circuits at temperatures from 24 degrees Centigrade to 500 degrees Centigrade is also described. Desired analog and digital IC functionality spanning this temperature range was demonstrated without changing the input signals or power supply voltages.

  14. Development of a universal serial bus interface circuit for ion beam current integrators.

    Science.gov (United States)

    Suresh, K; Panigrahi, B K; Nair, K G M

    2007-08-01

    A universal serial bus (USB) interface circuit has been developed to enable easy interfacing of commercial as well as custom-built ion beam current integrators to personal computer (PC) based automated experimental setups. Built using the popular PIC16F877A reduced instruction set computer and a USB-universal asynchronous receiver-transmitter/first in, first out controller, DLP2232, this USB interface circuit virtually emulates the ion beam current integrators on a host PC and uses USB 2.0 protocol to implement high speed bidirectional data transfer. Using this interface, many tedious and labor intensive ion beam irradiation and characterization experiments can be redesigned into PC based automated ones with advantages of improved accuracy, rapidity, and ease of use and control. This interface circuit was successfully used in carrying out online in situ resistivity measurement of 70 keV O(+) ion irradiated tin thin films using four probe method. In situ electrical resistance measurement showed the formation of SnO(2) phase during ion implantation.

  15. Silicon CMOS optical receiver circuits with integrated thin-film compound semiconductor detectors

    Science.gov (United States)

    Brooke, Martin A.; Lee, Myunghee; Jokerst, Nan Marie; Camperi-Ginestet, C.

    1995-04-01

    While many circuit designers have tackled the problem of CMOS digital communications receiver design, few have considered the problem of circuitry suitable for an all CMOS digital IC fabrication process. Faced with a high speed receiver design the circuit designer will soon conclude that a high speed analog-oriented fabrication process provides superior performance advantages to a digital CMOS process. However, for applications where there are overwhelming reasons to integrate the receivers on the same IC as large amounts of conventional digital circuitry, the low yield and high cost of the exotic analog-oriented fabrication is no longer an option. The issues that result from a requirement to use a digital CMOS IC process cut across all aspects of receiver design, and result in significant differences in circuit design philosophy and topology. Digital ICs are primarily designed to yield small, fast CMOS devices for digital logic gates, thus no effort is put into providing accurate or high speed resistances, or capacitors. This lack of any reliable resistance or capacitance has a significant impact on receiver design. Since resistance optimization is not a prerogative of the digital IC process engineer, the wisest option is thus to not use these elements, opting instead for active circuitry to replace the functions normally ascribed to resistance and capacitance. Depending on the application receiver noise may be a dominant design constraint. The noise performance of CMOS amplifiers is different than bipolar or GaAs MESFET circuits, shot noise is generally insignificant when compared to channel thermal noise. As a result the optimal input stage topology is significantly different for the different technologies. It is found that, at speeds of operation approaching the limits of the digital CMOS process, open loop designs have noise-power-gain-bandwidth tradeoff performance superior to feedback designs. Furthermore, the lack of good resisters and capacitors

  16. SmartStep: A Fully Integrated, Low-Power Insole Monitor

    OpenAIRE

    Nagaraj Hegde; Edward Sazonov

    2014-01-01

    Shoe-mounted wearable sensors can be used in applications, such as activity monitoring, gait analysis, post-stroke rehabilitation, body weight measurements and energy expenditure studies. Such wearable sensors typically require the modification or alteration of the shoe, which is not typically feasible for large populations without the direct involvement of shoe manufacturers. This article presents an insole-based wearable sensor (SmartStep) that has its electronics fully embedded into a gene...

  17. Charge Yield at Low Electric Fields: Considerations for Bipolar Integrated Circuits

    Science.gov (United States)

    Johnston, A. H.; Swimm, R. T.; Thorbourn, D. O.

    2013-01-01

    A significant reduction in total dose damage is observed when bipolar integrated circuits are irradiated at low temperature. This can be partially explained by the Onsager theory of recombination, which predicts a strong temperature dependence for charge yield under low-field conditions. Reduced damage occurs for biased as well as unbiased devices because the weak fringing field in thick bipolar oxides only affects charge yield near the Si/SiO2 interface, a relatively small fraction of the total oxide thickness. Lowering the temperature of bipolar ICs - either continuously, or for time periods when they are exposed to high radiation levels - provides an additional degree of freedom to improve total dose performance of bipolar circuits, particularly in space applications.

  18. Optical devices for ultra-compact photonic integrated circuits based on III-V/polymer nanowires

    Science.gov (United States)

    Lauvernier, D.; Garidel, S.; Zegaoui, M.; Vilcot, J. P.; Harari, J.; Magnin, V.; Decoster, D.

    2007-04-01

    We demonstrated the potential application of III-V/polymer nanowires for photonic integrated circuits in a previous paper. Hereby, we report the use of a spot size converter based on 2D reverse nanotaper structure in order to improve the coupling efficiency between the nanowire and optical fiber. A total coupling enhancement of up to a factor 60 has been measured from an 80 nm × 300 nm cross-section tip which feeds an 300 nm-side square nanowire at its both ends. Simultaneously, micro-radius bends have been fabricated to increase the circuit density; for a radius of 5 µm, the 90º bend losses were measured as low as 0.60 dB and 0.80 dB for TE and TM polarizations respectively.

  19. A complementary metal oxide semiconductor—integrable conditioning circuit for resistive chemical sensor management

    International Nuclear Information System (INIS)

    This paper presents a new interface circuit (for MOX-based resistive chemical sensors) capable of overcoming the main limit of the circuits based on the resistance-to-time approach, i.e. the long measuring time with high-value resistances. The system is designed to operate with a single supply of 3.3 V, thus facilitating an ASIC implementation together with digital electronics for a first data analysis and transmission. This is particularly advantageous when the elaboration process requires a large computational load and a data pre-elaboration is advisable. Simulations of the integrable solution of the system have shown the feasibility of the proposed approach. A prototype with discrete components has been furthermore fabricated and experimentally tested, showing good performance in the range 0.5 MΩ to 10 GΩ with a maximum measuring time of 60 ms

  20. Monolithically mode division multiplexing photonic integrated circuit for large-capacity optical interconnection.

    Science.gov (United States)

    Chen, Guanyu; Yu, Yu; Zhang, Xinliang

    2016-08-01

    We propose and fabricate an on-chip mode division multiplexed (MDM) photonic interconnection system. Such a monolithically photonic integrated circuit (PIC) is composed of a grating coupler, two micro-ring modulators, mode multiplexer/demultiplexer, and two germanium photodetectors. The signals' generation, multiplexing, transmission, demultiplexing, and detection are successfully demonstrated on the same chip. Twenty Gb/s MDM signals are successfully processed with clear and open eye diagrams, validating the feasibility of the proposed circuit. The measured power penalties show a good performance of the MDM link. The proposed on-chip MDM system can be potentially used for large-capacity optical interconnection in future high-performance computers and big data centers. PMID:27472614

  1. A SQUID gradiometer module with wire-wound pickup antenna and integrated voltage feedback circuit

    Energy Technology Data Exchange (ETDEWEB)

    Zhang Guofeng [State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Microsystem and Information Technology (SIMIT), Chinese Academy of Sciences (CAS), Shanghai 200050 (China); Peter Gruenberg Institute (PGI-8), Forschungszentrum Juelich (FZJ), D-52425 Juelich (Germany); Joint Research Laboratory on Superconductivity and Bioelectronics, Collaboration between CAS-Shanghai and FZJ, Shanghai 200050 (China); Graduate University of the Chinese Academy of Sciences, Beijing 100049 (China); Zhang, Yi, E-mail: y.zhang@fz-juelich.de [Peter Gruenberg Institute (PGI-8), Forschungszentrum Juelich (FZJ), D-52425 Juelich (Germany); Joint Research Laboratory on Superconductivity and Bioelectronics, Collaboration between CAS-Shanghai and FZJ, Shanghai 200050 (China); Zhang Shulin [State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Microsystem and Information Technology (SIMIT), Chinese Academy of Sciences (CAS), Shanghai 200050 (China); Joint Research Laboratory on Superconductivity and Bioelectronics, Collaboration between CAS-Shanghai and FZJ, Shanghai 200050 (China); Krause, Hans-Joachim [Peter Gruenberg Institute (PGI-8), Forschungszentrum Juelich (FZJ), D-52425 Juelich (Germany); Joint Research Laboratory on Superconductivity and Bioelectronics, Collaboration between CAS-Shanghai and FZJ, Shanghai 200050 (China); and others

    2012-10-15

    The performance of the direct readout schemes for dc SQUID, Additional Positive Feedback (APF), noise cancellation (NC) and SQUID bootstrap circuit (SBC), have been studied in conjunction with planar SQUID magnetometers. In this paper, we examine the NC technique applied to a niobium SQUID gradiometer module with an Nb wire-wound antenna connecting to a dual-loop SQUID chip with an integrated voltage feedback circuit for suppression of the preamplifier noise contribution. The sensitivity of the SQUID gradiometer module is measured to be about 1 fT/(cm {radical}Hz) in the white noise range in a magnetically shielded room. Using such gradiometer, both MCG and MEG signals are recorded.

  2. Neural CMOS-integrated circuit and its application to data classification.

    Science.gov (United States)

    Göknar, Izzet Cem; Yildiz, Merih; Minaei, Shahram; Deniz, Engin

    2012-05-01

    Implementation and new applications of a tunable complementary metal-oxide-semiconductor-integrated circuit (CMOS-IC) of a recently proposed classifier core-cell (CC) are presented and tested with two different datasets. With two algorithms-one based on Fisher's linear discriminant analysis and the other based on perceptron learning, used to obtain CCs' tunable parameters-the Haberman and Iris datasets are classified. The parameters so obtained are used for hard-classification of datasets with a neural network structured circuit. Classification performance and coefficient calculation times for both algorithms are given. The CC has 6-ns response time and 1.8-mW power consumption. The fabrication parameters used for the IC are taken from CMOS AMS 0.35-μm technology.

  3. A Zinc Oxide Nanorod Ammonia Microsensor Integrated with a Readout Circuit on-a-Chip

    Directory of Open Access Journals (Sweden)

    Chyan-Chyi Wu

    2011-11-01

    Full Text Available A zinc oxide nanorod ammonia microsensor integrated with a readout circuit on-a-chip fabricated using the commercial 0.35 mm complementary metal oxide semiconductor (CMOS process was investigated. The structure of the ammonia sensor is composed of a sensitive film and polysilicon electrodes. The ammonia sensor requires a post-process to etch the sacrificial layer, and to coat the sensitive film on the polysilicon electrodes. The sensitive film that is prepared by a hydrothermal method is made of zinc oxide. The sensor resistance changes when the sensitive film adsorbs or desorbs ammonia gas. The readout circuit is used to convert the sensor resistance into the voltage output. Experiments show that the ammonia sensor has a sensitivity of about 1.5 mV/ppm at room temperature.

  4. A zinc oxide nanorod ammonia microsensor integrated with a readout circuit on-a-chip.

    Science.gov (United States)

    Yang, Ming-Zhi; Dai, Ching-Liang; Wu, Chyan-Chyi

    2011-01-01

    A zinc oxide nanorod ammonia microsensor integrated with a readout circuit on-a-chip fabricated using the commercial 0.35 μm complementary metal oxide semiconductor (CMOS) process was investigated. The structure of the ammonia sensor is composed of a sensitive film and polysilicon electrodes. The ammonia sensor requires a post-process to etch the sacrificial layer, and to coat the sensitive film on the polysilicon electrodes. The sensitive film that is prepared by a hydrothermal method is made of zinc oxide. The sensor resistance changes when the sensitive film adsorbs or desorbs ammonia gas. The readout circuit is used to convert the sensor resistance into the voltage output. Experiments show that the ammonia sensor has a sensitivity of about 1.5 mV/ppm at room temperature.

  5. A flexible and robust soft-error testing system for microelectronic devices and integrated circuits

    Institute of Scientific and Technical Information of China (English)

    王晓辉; 杨振雷; 童腾; 苏弘; 刘杰; 张战刚; 古松; 刘天奇; 孔洁; 赵兴文

    2015-01-01

    Single event effects (SEEs) induced by radiations become a significant reliability challenge for modern elec-tronic systems. To evaluate SEEs susceptibility for microelectronic devices and integrated circuits (ICs), an SEE testing system with flexibility and robustness was developed at Heavy Ion Research Facility in Lanzhou (HIRFL). The system is compatible with various types of microelectronic devices and ICs, and supports plenty of complex and high-speed test schemes and plans for the irradiated devices under test (DUTs). Thanks to the combination of meticulous circuit design and the hardened logic design, the system has additional performances to avoid an overheated situation and irradiations by stray radiations. The system has been tested and verified by experiments for irradiating devices at HIRFL.

  6. Monolithically mode division multiplexing photonic integrated circuit for large-capacity optical interconnection.

    Science.gov (United States)

    Chen, Guanyu; Yu, Yu; Zhang, Xinliang

    2016-08-01

    We propose and fabricate an on-chip mode division multiplexed (MDM) photonic interconnection system. Such a monolithically photonic integrated circuit (PIC) is composed of a grating coupler, two micro-ring modulators, mode multiplexer/demultiplexer, and two germanium photodetectors. The signals' generation, multiplexing, transmission, demultiplexing, and detection are successfully demonstrated on the same chip. Twenty Gb/s MDM signals are successfully processed with clear and open eye diagrams, validating the feasibility of the proposed circuit. The measured power penalties show a good performance of the MDM link. The proposed on-chip MDM system can be potentially used for large-capacity optical interconnection in future high-performance computers and big data centers.

  7. A Zinc Oxide Nanorod Ammonia Microsensor Integrated with a Readout Circuit on-a-Chip

    Science.gov (United States)

    Yang, Ming-Zhi; Dai, Ching-Liang; Wu, Chyan-Chyi

    2011-01-01

    A zinc oxide nanorod ammonia microsensor integrated with a readout circuit on-a-chip fabricated using the commercial 0.35 μm complementary metal oxide semiconductor (CMOS) process was investigated. The structure of the ammonia sensor is composed of a sensitive film and polysilicon electrodes. The ammonia sensor requires a post-process to etch the sacrificial layer, and to coat the sensitive film on the polysilicon electrodes. The sensitive film that is prepared by a hydrothermal method is made of zinc oxide. The sensor resistance changes when the sensitive film adsorbs or desorbs ammonia gas. The readout circuit is used to convert the sensor resistance into the voltage output. Experiments show that the ammonia sensor has a sensitivity of about 1.5 mV/ppm at room temperature. PMID:22247656

  8. A prediction technique for single-event effects on complex integrated circuits

    International Nuclear Information System (INIS)

    The sensitivity of complex integrated circuits to single-event effects is investigated. Sensitivity depends not only on the cross section of physical modules but also on the behavior of data patterns running on the system. A method dividing the main functional modules is proposed. The intrinsic cross section and the duty cycles of different sensitive modules are obtained during the execution of data patterns. A method for extracting the duty cycle is presented and a set of test patterns with different duty cycles are implemented experimentally. By combining the intrinsic cross section and the duty cycle of different sensitive modules, a universal method to predict SEE sensitivities of different test patterns is proposed, which is verified by experiments based on the target circuit of a microprocessor. Experimental results show that the deviation between prediction and experiment is less than 20%. (paper)

  9. Segregated cholinergic transmission modulates dopamine neurons integrated in distinct functional circuits.

    Science.gov (United States)

    Dautan, Daniel; Souza, Albert S; Huerta-Ocampo, Icnelia; Valencia, Miguel; Assous, Maxime; Witten, Ilana B; Deisseroth, Karl; Tepper, James M; Bolam, J Paul; Gerdjikov, Todor V; Mena-Segovia, Juan

    2016-08-01

    Dopamine neurons in the ventral tegmental area (VTA) receive cholinergic innervation from brainstem structures that are associated with either movement or reward. Whereas cholinergic neurons of the pedunculopontine nucleus (PPN) carry an associative/motor signal, those of the laterodorsal tegmental nucleus (LDT) convey limbic information. We used optogenetics and in vivo juxtacellular recording and labeling to examine the influence of brainstem cholinergic innervation of distinct neuronal subpopulations in the VTA. We found that LDT cholinergic axons selectively enhanced the bursting activity of mesolimbic dopamine neurons that were excited by aversive stimulation. In contrast, PPN cholinergic axons activated and changed the discharge properties of VTA neurons that were integrated in distinct functional circuits and were inhibited by aversive stimulation. Although both structures conveyed a reinforcing signal, they had opposite roles in locomotion. Our results demonstrate that two modes of cholinergic transmission operate in the VTA and segregate the neurons involved in different reward circuits.

  10. Long-Term Characterization of 6H-SiC Transistor Integrated Circuit Technology Operating at 500 C

    Science.gov (United States)

    Neudeck, Philip G.; Spry, David J.; Chen, Liang-Yu; Chang, Carl W.; Beheim, Glenn M.; Okojie, Robert S.; Evans, Laura J.; Meredith Roger D.; Ferrier, Terry L.; Krasowski, Michael J.; Prokop, Norman F.

    2008-01-01

    NASA has been developing very high temperature semiconductor integrated circuits for use in the hot sections of aircraft engines and for Venus exploration. This paper reports on long-term 500 C electrical operation of prototype 6H-SiC integrated circuits based on epitaxial 6H-SiC junction field effect transistors (JFETs). As of this writing, some devices have surpassed 4000 hours of continuous 500 C electrical operation in oxidizing air atmosphere with minimal change in relevant electrical parameters.

  11. A 200 C Universal Gate Driver Integrated Circuit for Extreme Environment Applications

    Energy Technology Data Exchange (ETDEWEB)

    Tolbert, Leon M [ORNL; Huque, Mohammad A [ORNL; Islam, Syed K [ORNL; Blalock, Benjamin J [ORNL

    2012-01-01

    High-temperature power converters (dc-dc, dc-ac, etc.) have enormous potential in extreme environment applications, including automotive, aerospace, geothermal, nuclear, and well logging. For successful realization of such high-temperature power conversion modules, the associated control electronics also need to perform at high temperature. This paper presents a silicon-on-insulator (SOI) based high-temperature gate driver integrated circuit (IC) incorporating an on-chip low-power temperature sensor and demonstrating an improved peak output current drive over our previously reported work. This driver IC has been primarily designed for automotive applications, where the underhood temperature can reach 200 C. This new gate driver prototype has been designed and implemented in a 0.8 {micro}m, 2-poly, and 3-metal bipolar CMOS-DMOS (Double-Diffused Metal-Oxide Semiconductor) on SOI process and has been successfully tested for up to 200 C ambient temperature driving a SiC MOSFET and a SiC normally-ON JFET. The salient feature of the proposed universal gate driver is its ability to drive power switches over a wide range of gate turn-ON voltages such as MOSFET (0 to 20 V), normally-OFF JFET (-7 to 3 V), and normally-ON JFET (-20 to 0 V). The measured peak output current capability of the driver is around 5 A and is thus capable of driving several power switches connected in parallel. An ultralow-power on-chip temperature supervisory circuit has also been integrated into the die to safeguard the driver circuit against excessive die temperature ({ge}220 C). This approach utilizes increased diode leakage current at higher temperature to monitor the die temperature. The power consumption of the proposed temperature sensor circuit is below 10 {micro}W for operating temperature up to 200 C.

  12. Design and implementation of Gm-APD array readout integrated circuit for infrared 3D imaging

    Science.gov (United States)

    Zheng, Li-xia; Yang, Jun-hao; Liu, Zhao; Dong, Huai-peng; Wu, Jin; Sun, Wei-feng

    2013-09-01

    A single-photon detecting array of readout integrated circuit (ROIC) capable of infrared 3D imaging by photon detection and time-of-flight measurement is presented in this paper. The InGaAs avalanche photon diodes (APD) dynamic biased under Geiger operation mode by gate controlled active quenching circuit (AQC) are used here. The time-of-flight is accurately measured by a high accurate time-to-digital converter (TDC) integrated in the ROIC. For 3D imaging, frame rate controlling technique is utilized to the pixel's detection, so that the APD related to each pixel should be controlled by individual AQC to sense and quench the avalanche current, providing a digital CMOS-compatible voltage pulse. After each first sense, the detector is reset to wait for next frame operation. We employ counters of a two-segmental coarse-fine architecture, where the coarse conversion is achieved by a 10-bit pseudo-random linear feedback shift register (LFSR) in each pixel and a 3-bit fine conversion is realized by a ring delay line shared by all pixels. The reference clock driving the LFSR counter can be generated within the ring delay line Oscillator or provided by an external clock source. The circuit is designed and implemented by CSMC 0.5μm standard CMOS technology and the total chip area is around 2mm×2mm for 8×8 format ROIC with 150μm pixel pitch. The simulation results indicate that the relative time resolution of the proposed ROIC can achieve less than 1ns, and the preliminary test results show that the circuit function is correct.

  13. Cascade photonic integrated circuit architecture for electro-optic in-phase quadrature/single sideband modulation or frequency conversion.

    Science.gov (United States)

    Hasan, Mehedi; Hall, Trevor

    2015-11-01

    A photonic integrated circuit architecture for implementing frequency upconversion is proposed. The circuit consists of a 1×2 splitter and 2×1 combiner interconnected by two stages of differentially driven phase modulators having 2×2 multimode interference coupler between the stages. A transfer matrix approach is used to model the operation of the architecture. The predictions of the model are validated by simulations performed using an industry standard software tool. The intrinsic conversion efficiency of the proposed design is improved by 6 dB over the alternative functionally equivalent circuit based on dual parallel Mach-Zehnder modulators known in the prior art. A two-tone analysis is presented to study the linearity of the proposed circuit, and a comparison is provided over the alternative. The proposed circuit is suitable for integration in any platform that offers linear electro-optic phase modulation such as LiNbO(3), silicon, III-V, or hybrid technology.

  14. Vertical optical ring resonators fully integrated with nanophotonic waveguides on silicon-on-insulator substrates

    CERN Document Server

    Madani, Abbas; Stolarek, David; Zimmermann, Lars; Ma, Libo; Schmidt, Oliver G

    2015-01-01

    We demonstrate full integration of vertical optical ring resonators with silicon nanophotonic waveguides on silicon-on-insulator substrates to accomplish a significant step towards 3D photonic integration. The on-chip integration is realized by rolling up 2D differentially strained TiO2 nanomembranes into 3D microtube cavities on a nanophotonic microchip. The integration configuration allows for out of plane optical coupling between the in-plane nanowaveguides and the vertical microtube cavities as a compact and mechanically stable optical unit, which could enable refined vertical light transfer in 3D stacks of multiple photonic layers. In this vertical transmission scheme, resonant filtering of optical signals at telecommunication wavelengths is demonstrated based on subwavelength thick walled microcavities. Moreover, an array of microtube cavities is prepared and each microtube cavity is integrated with multiple waveguides which opens up interesting perspectives towards parallel and multi-routing through a ...

  15. A fully integrated, monolithic, cryogenic charge sensitive preamplifier using N-channel JFETs and polysilicon resistors

    International Nuclear Information System (INIS)

    In this paper, an integrated charge preamplifier to be used with small (10--30 mm2) Si(Li) and Ge(Li) X-ray detectors is described. The preamplifier is designed to operate at cryogenic temperatures (∼100 K to 160 K) for the best performance. An N-channel JFET process technology for integrated charge sensitive preamplifiers has been developed. The process integrates multiple pinch-off voltage JFETs fabricated in an n-type epitaxial layer on a low resistivity p-type substrate. The process also incorporates polysilicon resistors integrated on the same die as the JFETs. The optimized polysilicon resistors exhibit 1/f noise nearly as good as metal film resistors at the same current. Results for integrated amplifier are discussed

  16. Large-scale photonic integrated circuits for long-haul transmission and switching

    Science.gov (United States)

    Nagarajan, Radhakrishnan; Kato, Masaki; Pleumeekers, Jacco; Evans, Peter; Lambert, Damien; Chen, Arnold; Dominic, Vince; Mathur, Atul; Chavarkar, Prashant; Missey, Mark; Dentai, Andrew; Hurtt, Sheila; Bã¤Ck, Johan; Muthiah, Ranjani; Murthy, Sanjeev; Salvatore, Randal; Joyner, Charles; Rossi, Jon; Schneider, Richard; Ziari, Mehrdad; Tsai, Huan-Shang; Bostak, Jeffrey; Kauffman, Michael; Pennypacker, Stephen; Butrie, Timothy; Reffle, Michael; Mehuys, Dave; Mitchell, Matthew; Nilsson, Alan; Grubb, Stephen; Kish, Fred; Welch, David

    2007-02-01

    Dense wavelength division multiplexed (DWDM) large-scale, single-chip transmitter and receiver photonic integrated circuits (PICs), each capable of operating at 100 Gbits/s, have been deployed in the field since the end of 2004. These highly integrated InP chips have significantly changed the economics of long-haul optical transport networks. First, a review of the ten-channel, 100 Gbits/s PIC is presented. Then two extensions of the technology are demonstrated; first is wide temperature, coolerless operation of the 100 Gbits/s PIC, and second is a single integrated chip with 40 channels operating at 40 Gbits/s, capable of an aggregate data rate of 1.6 Tbits/s.

  17. Open access to technology platforms for InP-based photonic integrated circuits

    Science.gov (United States)

    Ławniczuk, Katarzyna; Augustin, Luc M.; Grote, Norbert; Wale, Michael J.; Smit, Meint K.; Williams, Kevin A.

    2015-04-01

    Open access to generic technology platforms for photonic integrated circuit manufacturing enables low-cost development of application-specific photonic chips for novel or improved products. It brings photonic ICs within reach for many industrial users and research institutes, by moving toward a fabless business model. In the current status, InP-based open access manufacturing services are offered through multi-project wafer runs by Fraunhofer Heinrich Hertz Institut, SMART Photonics, and Oclaro. In this paper, we review state-of-the-art InP photonic integration technology platforms, present examples of complex InP photonic ICs developed in the generic technologies, and give a prospect for further development of these photonic integration platforms.

  18. QIE10: a new front-end custom integrated circuit for high-rate experiments

    International Nuclear Information System (INIS)

    We present results on a new version of the QIE (Charge Integrator and Encoder), a custom Application Specific Integrated Circuit (ASIC) designed at Fermilab. Developed specifically for the measurement of charge from photo-detectors in high-rate environments, this most recent addition to the QIE family features 3 fC sensitivity, 17-bits of dynamic range with logarithmic response, a Time-to-Digital Converter (TDC) with sub-nanosecond resolution, and internal charge injection. The device is capable of dead-timeless operation at 40 MHz, making it ideal for calorimetry at the Large hadron Collider (LHC). We present bench measurements and integration studies that characterize the performance, radiation tolerance measurements, and plans for deployment in the Atlas and CMS detectors as part of the Phase 1 and Phase 2 upgrades

  19. Cooley building opens in Houston. Demonstrates value of fully integrated marketing communications.

    Science.gov (United States)

    Rees, Tom

    2002-01-01

    The Texas Heart Institute at St. Luke's Episcopal HospiTal in Houston dedicated its new 10-story Denton A. Cooley Building in January. The structure opened with a fanfare, thanks to a well-integrated marketing communications program.

  20. Spherical particles and voids effect on current and potential distribution in integrated circuit leads

    Science.gov (United States)

    Pang, Dongqing; Sun, Yicai

    2015-06-01

    Relationships of resistance with a width of 0.1 μm for different heights and currents at a given volt drop are plotted for a 0.2 μm length smooth copper lead. The lead is specified to connect with the integrated circuit AD8622 with its Isr = 0.350 mA to determine the volt drop = 0.2 mV. The total current is computed according to the total resistance of the lead for the different void radius at this volt drop. The current density value at the right boundary is determined by Ohm’s law. After combining the integration of the total current as a prerequisite with the interpolation of current density values from the left, i.e. void edge to the right boundaries, their distribution is obtained, showing current crowding outside of their edges and a great resistance with the increase of their radius. The calculation errors for comparison with the Laplace equation are calculated, mainly located on the corners of void. The potential distribution can be obtained by multiplying sheet resistance to current density distribution. At last, the relationship between resistance, total current, current crowding and calculation errors with the different void radius and lead length are offered in several forms for use in the integrated circuit design.

  1. Spherical particles and voids effect on current and potential distribution in integrated circuit leads

    International Nuclear Information System (INIS)

    Relationships of resistance with a width of 0.1 μm for different heights and currents at a given volt drop are plotted for a 0.2 μm length smooth copper lead. The lead is specified to connect with the integrated circuit AD8622 with its Isr = 0.350 mA to determine the volt drop = 0.2 mV. The total current is computed according to the total resistance of the lead for the different void radius at this volt drop. The current density value at the right boundary is determined by Ohm’s law. After combining the integration of the total current as a prerequisite with the interpolation of current density values from the left, i.e. void edge to the right boundaries, their distribution is obtained, showing current crowding outside of their edges and a great resistance with the increase of their radius. The calculation errors for comparison with the Laplace equation are calculated, mainly located on the corners of void. The potential distribution can be obtained by multiplying sheet resistance to current density distribution. At last, the relationship between resistance, total current, current crowding and calculation errors with the different void radius and lead length are offered in several forms for use in the integrated circuit design. (paper)

  2. Evaluation of crud behavior in primary circuit of integral reactor by multi-region model

    International Nuclear Information System (INIS)

    In order to evaluate behavior of deposited crud from structural materials surfaces, multi-region model dealing with radioactive corrosion products behavior has been developed to describe crud behavior in primary circuit of the integral reactor. The primary circuit of the integral reactor, which was adopted ammoniated water chemistry, was divided into nine control volumes. The transportation of the radioactive nuclei by the sedimentation, washing-out, and release of corrosion products were considered between ths control volumes and its associated surfaces in the model. Specific activities of separate radionuclides in the primary coolant as well as on the surfaces of structural materials that were washed by the coolant throughout fuel cycle were also simulated with operation mode. As a result, this multi-regional model was capable of evaluating the behavior of crud more exactly than the two or three nodes model simulation codes. From this evaluation the integral reactor showed lower activities than the other commercial reactor because this was introduced the titanium alloy to the SG tube material and the avoidance of boric acid. (author)

  3. SEM analysis of ionizing radiation effects in linear integrated circuits. [Scanning Electron Microscope

    Science.gov (United States)

    Stanley, A. G.; Gauthier, M. K.

    1977-01-01

    A successful diagnostic technique was developed using a scanning electron microscope (SEM) as a precision tool to determine ionization effects in integrated circuits. Previous SEM methods radiated the entire semiconductor chip or major areas. The large area exposure methods do not reveal the exact components which are sensitive to radiation. To locate these sensitive components a new method was developed, which consisted in successively irradiating selected components on the device chip with equal doses of electrons /10 to the 6th rad (Si)/, while the whole device was subjected to representative bias conditions. A suitable device parameter was measured in situ after each successive irradiation with the beam off.

  4. All-fiber hybrid photon-plasmon circuits: integrating nanowire plasmonics with fiber optics.

    Science.gov (United States)

    Li, Xiyuan; Li, Wei; Guo, Xin; Lou, Jingyi; Tong, Limin

    2013-07-01

    We demonstrate all-fiber hybrid photon-plasmon circuits by integrating Ag nanowires with optical fibers. Relying on near-field coupling, we realize a photon-to-plasmon conversion efficiency up to 92% in a fiber-based nanowire plasmonic probe. Around optical communication band, we assemble an all-fiber resonator and a Mach-Zehnder interferometer (MZI) with Q-factor of 6 × 10(6) and extinction ratio up to 30 dB, respectively. Using the MZI, we demonstrate fiber-compatible plasmonic sensing with high sensitivity and low optical power.

  5. Rolled-up inductor structure for a radiofrequency integrated circuit (RFIC)

    Energy Technology Data Exchange (ETDEWEB)

    Li, Xiuling; Huang, Wen; Ferreira, Placid M.; Yu, Xin

    2015-12-29

    A rolled-up inductor structure for a radiofrequency integrated circuit (RFIC) comprises a multilayer sheet in a rolled configuration comprising multiple turns about a longitudinal axis. The multilayer sheet comprises a conductive pattern layer on a strain-relieved layer, and the conductive pattern layer comprises at least one conductive strip having a length extending in a rolling direction. The at least one conductive strip thereby wraps around the longitudinal axis in the rolled configuration. The conductive pattern layer may also comprise two conductive feed lines connected to the conductive strip for passage of electrical current therethrough. The conductive strip serves as an inductor cell of the rolled-up inductor structure.

  6. Performance evaluation of a burst-mode EDFA in an optical packet and circuit integrated network.

    Science.gov (United States)

    Shiraiwa, Masaki; Awaji, Yoshinari; Furukawa, Hideaki; Shinada, Satoshi; Puttnam, Benjamin J; Wada, Naoya

    2013-12-30

    We experimentally investigate the performance of burst-mode EDFA in an optical packet and circuit integrated system. In such networks, packets and light paths can be dynamically assigned to the same fibers, resulting in gain transients in EDFAs throughout the network that can limit network performance. Here, we compare the performance of a 'burst-mode' EDFA (BM-EDFA), employing transient suppression techniques and optical feedback, with conventional EDFAs, and those using automatic gain control and previous BM-EDFA implementations. We first measure gain transients and other impairments in a simplified set-up before making frame error-rate measurements in a network demonstration.

  7. Nonlinearity characterization of temperature sensing systems for integrated circuit testing by intermodulation products monitoring.

    Science.gov (United States)

    Altet, J; Mateo, D; Perpiñà, X; Grauby, S; Dilhaire, S; Jordà, X

    2011-09-01

    This work presents an alternative characterization strategy to quantify the nonlinear behavior of temperature sensing systems. The proposed approach relies on measuring the temperature under thermal sinusoidal steady state and observing the intermodulation products that are generated within the sensing system itself due to its nonlinear temperature-output voltage characteristics. From such intermodulation products, second-order interception points can be calculated as a figure of merit of the measuring system nonlinear behavior. In this scenario, the present work first shows a theoretical analysis. Second, it reports the experimental results obtained with three thermal sensing techniques used in integrated circuits.

  8. A metastable phase of tin in 3D integrated circuit solder microbumps

    International Nuclear Information System (INIS)

    A metastable phase of Sn has been found to co-exist with β-Sn in Pb-free SnAg microbumps in 3D integrated circuit technology. Synchrotron microbeam X-ray diffraction, high-resolution TEM imaging and selected-area electron diffraction were used to confirm the metastable phase, which has an orthorhombic lattice, with lattice parameter a = 0.635 nm, b = 0.639 nm, and c = 1.147 nm. Its composition is Sn containing a few percent of Ni. A higher rate of nucleation might have enabled its formation

  9. Two-dimensional parasitic capacitance extraction for integrated circuit with dual discrete geometric methods

    International Nuclear Information System (INIS)

    Capacitance extraction is one of the key issues in integrated circuits and also a typical electrostatic problem. The dual discrete geometric method (DGM) is investigated to provide relative solutions in two-dimensional unstructured mesh space. The energy complementary characteristic and quick field energy computation thereof based on it are emphasized. Contrastive analysis between the dual finite element methods and the dual DGMs are presented both from theoretical derivation and through case studies. The DGM, taking the scalar potential as unknown on dual interlocked meshes, with simple form and good accuracy, is expected to be one of the mainstreaming methods in associated areas. (paper)

  10. Hydrogenated Amorphous Silicon Sensor Deposited on Integrated Circuit for Radiation Detection

    CERN Document Server

    Despeisse, M; Jarron, P; Kaplon, J; Moraes, D; Nardulli, A; Powolny, F; Wyrsch, N

    2008-01-01

    Radiation detectors based on the deposition of a 10 to 30 mum thick hydrogenated amorphous silicon (a-Si:H) sensor directly on top of integrated circuits have been developed. The performance of this detector technology has been assessed for the first time in the context of particle detectors. Three different circuits were designed in a quarter micron CMOS technology for these studies. The so-called TFA (Thin-Film on ASIC) detectors obtained after deposition of a-Si:H sensors on the developed circuits are presented. High internal electric fields (104 to 105 V/cm) can be built in the a-Si:H sensor and overcome the low mobility of electrons and holes in this amorphous material. However, the deposited sensor's leakage current at such fields turns out to be an important parameter which limits the performance of a TFA detector. Its detailed study is presented as well as the detector's pixel segmentation. Signal induction by generated free carrier motion in the a-Si:H sensor has been characterized using a 660 nm pul...

  11. Integrated plasticity at inhibitory and excitatory synapses in the cerebellar circuit

    Directory of Open Access Journals (Sweden)

    Lisa eMapelli

    2015-05-01

    Full Text Available The way long-term potentiation (LTP and depression (LTD are integrated within the different synapses of brain neuronal circuits is poorly understood. In order to progress beyond the identification of specific molecular mechanisms, a system in which multiple forms of plasticity can be correlated with large-scale neural processing is required. In this paper we take as an example the cerebellar network , in which extensive investigations have revealed LTP and LTD at several excitatory and inhibitory synapses. Cerebellar LTP and LTD occur in all three main cerebellar subcircuits (granular layer, molecular layer, deep cerebellar nuclei and correspondingly regulate the function of their three main neurons: granule cells (GrCs, Purkinje cells (PCs and deep cerebellar nuclear (DCN cells. All these neurons, in addition to be excited, are reached by feed-forward and feed-back inhibitory connections, in which LTP and LTD may either operate synergistically or homeostatically in order to control information flow through the circuit. Although the investigation of individual synaptic plasticities in vitro is essential to prove their existence and mechanisms, it is insufficient to generate a coherent view of their impact on network functioning in vivo. Recent computational models and cell-specific genetic mutations in mice are shedding light on how plasticity at multiple excitatory and inhibitory synapses might regulate neuronal activities in the cerebellar circuit and contribute to learning and memory and behavioral control.

  12. Integrated plasticity at inhibitory and excitatory synapses in the cerebellar circuit.

    Science.gov (United States)

    Mapelli, Lisa; Pagani, Martina; Garrido, Jesus A; D'Angelo, Egidio

    2015-01-01

    The way long-term potentiation (LTP) and depression (LTD) are integrated within the different synapses of brain neuronal circuits is poorly understood. In order to progress beyond the identification of specific molecular mechanisms, a system in which multiple forms of plasticity can be correlated with large-scale neural processing is required. In this paper we take as an example the cerebellar network, in which extensive investigations have revealed LTP and LTD at several excitatory and inhibitory synapses. Cerebellar LTP and LTD occur in all three main cerebellar subcircuits (granular layer, molecular layer, deep cerebellar nuclei) and correspondingly regulate the function of their three main neurons: granule cells (GrCs), Purkinje cells (PCs) and deep cerebellar nuclear (DCN) cells. All these neurons, in addition to be excited, are reached by feed-forward and feed-back inhibitory connections, in which LTP and LTD may either operate synergistically or homeostatically in order to control information flow through the circuit. Although the investigation of individual synaptic plasticities in vitro is essential to prove their existence and mechanisms, it is insufficient to generate a coherent view of their impact on network functioning in vivo. Recent computational models and cell-specific genetic mutations in mice are shedding light on how plasticity at multiple excitatory and inhibitory synapses might regulate neuronal activities in the cerebellar circuit and contribute to learning and memory and behavioral control.

  13. Modeling for infrared readout integrated circuit based on Verilog-A

    Science.gov (United States)

    Wang, Xiao; Shi, Zelin

    2015-04-01

    Infrared detectors are the core of infrared imaging systems, while readout integrated circuits are the key components of detectors. In order to grasp the performance of circuits quickly and accurately, a method of circuit modeling using Verilog-A language is proposed, which present a behavioral simulation model for the ROIC. At first, a typical capacitor trans-impedance amplifier(CTIA) ROIC unit is showed, then the two essential parts of it,operational amplifier and switch are modeled on behavioral level. The op amp model concludes these non-ideal factors, such as finite gain-bandwidth product, input and output offset, output resistance and so on. Non-deal factors that affect switches are considered in the switch behavioral model, such as rise and fall time, on-resistance and so on. At last time-domain modeling method for noise is presented, which is compared with the classical frequency domain method for difference. The analysis results shows that in the situation that noise interested bandwidth(NIBW) is more than 5MHz, the difference between the two methods leads to less than 1% if the sample rate of noise is larger 4 times of the NIBW

  14. Analysis and optimization of TSV–TSV coupling in three-dimensional integrated circuits

    International Nuclear Information System (INIS)

    Through silicon via (TSV)–TSV coupling is detrimental to the performance of three-dimensional (3D) integrated circuits (ICs) with the major negative effect of introducing coupling noise. In order to obtain an accurate estimation of the coupling level from TSV–TSV in the early design stage, this paper first proposes an impedance-level model of the coupling channel between TSVs based on a two-port network, and then derives the formula of the coupling coefficient to describe the TSV–TSV coupling effect. The accuracy of the formula is validated by comparing the results with 3D full-wave simulations. Furthermore, a design technique for optimizing the coupling between adjacent coupled signal TSVs is proposed. Through SPICE simulations, the proposed technique shows its feasibility to reduce the coupling noise for both a simple TSV–TSV circuit and a complicated circuit with more TSVs, and demonstrates its potential for designers in achieving the goal of improving the electrical performance of 3D ICs. (paper)

  15. Fully integrated planar magnetics for primary-parallel isolated boost converter

    DEFF Research Database (Denmark)

    Ouyang, Ziwei; Sen, Gökhan; Thomsen, Ole Cornelius;

    2011-01-01

    by interleaving the primary and secondary turns of the transformers. To verify the validity of the design approach, a 1-kW prototype converter with two primary power stages is implemented for a fuel cell fed battery charger application with 20–40 V input and 170–230 V output. An efficiency of 96% can be achieved......A high efficient planar integrated magnetics (PIM) design approach for primary parallel isolated boost converters is presented. All magnetic components in the converter including two input inductors and two transformers with primary-parallel and secondary-series windings are integrated into an E......-I-E core geometry. Due to a low reluctance path provided by the shared I-core, the two transformers as well as the two input inductors can be integrated independently, reducing the total ferrite volume and core loss. AC losses in the windings and the leakage inductance of the transformer are kept low...

  16. Analysis and Design of Fully Integrated Planar Magnetics for Primary-Parallel Isolated Boost Converter

    DEFF Research Database (Denmark)

    Ouyang, Ziwei; Sen, Gökhan; Thomsen, Ole Cornelius;

    2013-01-01

    A high efficient planar integrated magnetics (PIM) design approach for primary-parallel isolated boost converters is presented. All magnetic components in the converter including two input inductors and two transformers with primary-parallel and secondary-series windings are integrated into an E...... and switching loss of MOSFETs are analyzed in-depth in this work as well. To verify the validity of the design approach, a 2-kW prototype converter with two primary power stages is implemented for a fuel cell fed traction applications with 20-50 V input and 400-V output. An efficiency of 95.9% can be achieved...

  17. DrugOn: a fully integrated pharmacophore modeling and structure optimization toolkit

    Directory of Open Access Journals (Sweden)

    Dimitrios Vlachakis

    2015-01-01

    Full Text Available During the past few years, pharmacophore modeling has become one of the key components in computer-aided drug design and in modern drug discovery. DrugOn is a fully interactive pipeline designed to exploit the advantages of modern programming and overcome the command line barrier with two friendly environments for the user (either novice or experienced in the field of Computer Aided Drug Design to perform pharmacophore modeling through an efficient combination of the PharmACOphore, Gromacs, Ligbuilder and PDB2PQR suites. Our platform features a novel workflow that guides the user through each logical step of the iterative 3D structural optimization setup and drug design process. For the pharmacophore modeling we are focusing on either the characteristics of the receptor or the full molecular system, including a set of selected ligands. DrugOn can be freely downloaded from our dedicated server system at www.bioacademy.gr/bioinformatics/drugon/.

  18. Integration of Morphology and Graph-based Techniques for Fully Automatic Liver Segmentation

    Directory of Open Access Journals (Sweden)

    Hans Burkhardt

    2010-09-01

    Full Text Available Here a fully 3D algorithm for automatic liver segmentation from CT volumetric datasets is presented. The algorithm starts by smoothing the original volume using anisotropic diffusion. The coarse liver region is obtained from the threshold process that is based on a priori knowledge. Then, several morphological operations is performed such as operating the liver to detach the unwanted region connected to the liver and finding the largest component using the connected component labeling (CCL algorithm. At this stage, both 3D and 2D CCL is done subsequently. However, in 2D CCL, the adjacent slices are also affected from current slice changes. Finally, the boundary of the liver is refined using graph-cuts solver. Our algorithm does not require any user interaction or training datasets to be used. The algorithm has been evaluated on 10 CT scans of the liver and the results are encouraging to poor quality of images.

  19. Cooley building opens in Houston. Demonstrates value of fully integrated marketing communications.

    Science.gov (United States)

    Rees, Tom

    2002-01-01

    The Texas Heart Institute at St. Luke's Episcopal HospiTal in Houston dedicated its new 10-story Denton A. Cooley Building in January. The structure opened with a fanfare, thanks to a well-integrated marketing communications program. PMID:11915203

  20. Fully integrated optical system for lab-on-a-chip applications

    DEFF Research Database (Denmark)

    Balslev, Søren; Olsen, Brian Bilenberg; Geschke, Oliver;

    2004-01-01

    We present a lab-on-a-chip device featuring a microfluidic dye laser, wave-guides, microfluidic components and photo-detectors integrated on the chip. The microsystem is designed for wavelength selective absorption measurements in the visible range on a fluidic sample, which can be prepared...

  1. Ultrasensitive mass sensor fully integrated with complementary metal-oxide-semiconductor circuitry

    DEFF Research Database (Denmark)

    Forsén, Esko Sebastian; Abadal, G.; Ghatnekar-Nilsson, S.;

    2005-01-01

    Nanomechanical resonators have been monolithically integrated on preprocessed complementary metal-oxide-semiconductor (CMOS) chips. Fabricated resonator systems have been designed to have resonance frequencies up to 1.5 MHz. The systems have been characterized in ambient air and vacuum conditions...... excitation, capacitive detection, and amplification of the resonance signal directly on the chip. (c) 2005 American Institute of Physics....

  2. Analog and VLSI circuits

    CERN Document Server

    Chen, Wai-Kai

    2009-01-01

    Featuring hundreds of illustrations and references, this book provides the information on analog and VLSI circuits. It focuses on analog integrated circuits, presenting the knowledge on monolithic device models, analog circuit cells, high performance analog circuits, RF communication circuits, and PLL circuits.

  3. Focal plane array readout integrated circuit with per-pixel analog-to-digital and digital-to-analog conversion

    Science.gov (United States)

    Kleinfelder, Stuart; Hottes, Alison; Pease, R. Fabian W.

    2000-07-01

    A pixel array readout integrated circuit (ROIC) containing per-pixel analog-to-digital conversion (ADC) and digital-to- analog conversion (DAC) for infrared detectors is presented with design and test result details. Fabricated in a standard 0.35 micron, 3.3 volt CMOS technology. the prototype consists of a linear array of 64 pixels, containing over 100 transistors per 30 by 30 micron pixel. The 8-bit per-pixel ADC is a Nyquist-rate single-slope design consisting of a three stage comparator and an 8 bit memory. This fully pixel- parallel ADC architecture operates in full-frame 'snapshot' mode and can reach over 1,000 frames per second. Each pixel also contains cascoded current source, globally biased to subtract an identical, fixed amount of current from each pixel in order to remove a common background signal by 'charge skimming.' It operates over more than 3 decades of current cancellation (approximately 10 pA to > 10 nA). As well, each pixel contains a 4 to 6+ bit current-mode DAC, intended to trim-out pixel-to-pixel variations in background current. It consists of 16 unit-cells of switched cascoded current sources per pixel, organized as two separately biased weights and controlled by a 16-bit per-pixel memory. The DAC operates over more than 4 decades of current cancellation (< 10 pA to approximately equals 100 nA) per least significant bit (LSB).

  4. Operational Excellence through Schedule Optimization and Production Simulation of Application Specific Integrated Circuits.

    Energy Technology Data Exchange (ETDEWEB)

    Flory, John Andrew [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Padilla, Denise D. [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Gauthier, John H. [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Zwerneman, April Marie [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Miller, Steven P [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)

    2016-05-01

    Upcoming weapon programs require an aggressive increase in Application Specific Integrated Circuit (ASIC) production at Sandia National Laboratories (SNL). SNL has developed unique modeling and optimization tools that have been instrumental in improving ASIC production productivity and efficiency, identifying optimal operational and tactical execution plans under resource constraints, and providing confidence in successful mission execution. With ten products and unprecedented levels of demand, a single set of shared resources, highly variable processes, and the need for external supplier task synchronization, scheduling is an integral part of successful manufacturing. The scheduler uses an iterative multi-objective genetic algorithm and a multi-dimensional performance evaluator. Schedule feasibility is assessed using a discrete event simulation (DES) that incorporates operational uncertainty, variability, and resource availability. The tools provide rapid scenario assessments and responses to variances in the operational environment, and have been used to inform major equipment investments and workforce planning decisions in multiple SNL facilities.

  5. A quantum entropy source on an InP photonic integrated circuit for random number generation

    CERN Document Server

    Abellan, Carlos; Domenech, David; Muñoz, Pascual; Capmany, Jose; Longhi, Stefano; Mitchell, Morgan W; Pruneri, Valerio

    2016-01-01

    Random number generators are essential to ensure performance in information technologies, including cryptography, stochastic simulations and massive data processing. The quality of random numbers ultimately determines the security and privacy that can be achieved, while the speed at which they can be generated poses limits to the utilisation of the available resources. In this work we propose and demonstrate a quantum entropy source for random number generation on an indium phosphide photonic integrated circuit made possible by a new design using two-laser interference and heterodyne detection. The resulting device offers high-speed operation with unprecedented security guarantees and reduced form factor. It is also compatible with complementary metal-oxide semiconductor technology, opening the path to its integration in computation and communication electronic cards, which is particularly relevant for the intensive migration of information processing and storage tasks from local premises to cloud data centre...

  6. EQUIPMENT FOR NONDESTRUCTIVE TESTING OF SILICON WAFERS SUBMICRON TOPOLOGY DURING THE FABRICATION OF INTEGRATED CIRCUITS

    Directory of Open Access Journals (Sweden)

    S. A. Chizhik

    2013-01-01

    Full Text Available The advantages of using an atomic force microscopy in manufacturing of submicron integrated circuits are described. The possibilities of characterizing the surface morphology and the etching profile for silicon substrate and bus lines, estimation of the periodicity and size of bus lines, geometrical stability for elementary bus line are shown. Methods of optical and atomic force microcopies are combined in one diagnostic unit. Scanning  probe  microscope  (SPM  200  is  designed  and  produced.  Complex  SPM  200  realizes  nondestructive control of microelectronics elements made on silicon wafers up to 200 mm in diameter and it is introduced by JSC «Integral» for the purpose of operational control, metrology and acceptance of the final product.

  7. Waveguide photon-number-resolving detectors for quantum photonic integrated circuits

    CERN Document Server

    Sahin, D; Zhou, Z; Jahanmirinejad, S; Mattioli, F; Leoni, R; Beetz, J; Lermer, M; Kamp, M; Höfling, S; Fiore, A

    2013-01-01

    Quantum photonic integration circuits are a promising approach to scalable quantum processing with photons. Waveguide single-photon-detectors (WSPDs) based on superconducting nanowires have been recently shown to be compatible with single-photon sources for a monolithic integration. While standard WSPDs offer single-photon sensitivity, more complex superconducting nanowire structures can be configured to have photon-number-resolving capability. In this work, we present waveguide photon-number-resolving detectors (WPNRDs) on GaAs/Al0.75Ga0.25As ridge waveguides based on a series connection of nanowires. The detection of 0-4 photons has been demonstrated with a four-wire WPNRD, having a single electrical read-out. A device quantum efficiency ~24 % is reported at 1310 nm for the TE polarization.

  8. Capacitive Micro Pressure Sensor Integrated with a Ring Oscillator Circuit on Chip

    Science.gov (United States)

    Dai, Ching-Liang; Lu, Po-Wei; Chang, Chienliu; Liu, Cheng-Yang

    2009-01-01

    The study investigates a capacitive micro pressure sensor integrated with a ring oscillator circuit on a chip. The integrated capacitive pressure sensor is fabricated using the commercial CMOS (complementary metal oxide semiconductor) process and a post-process. The ring oscillator is employed to convert the capacitance of the pressure sensor into the frequency output. The pressure sensor consists of 16 sensing cells in parallel. Each sensing cell contains a top electrode and a lower electrode, and the top electrode is a sandwich membrane. The pressure sensor needs a post-CMOS process to release the membranes after completion of the CMOS process. The post-process uses etchants to etch the sacrificial layers, and to release the membranes. The advantages of the post-process include easy execution and low cost. Experimental results reveal that the pressure sensor has a high sensitivity of 7 Hz/Pa in the pressure range of 0–300 kPa. PMID:22303167

  9. Capacitive Micro Pressure Sensor Integrated with a Ring Oscillator Circuit on Chip

    Directory of Open Access Journals (Sweden)

    Cheng-Yang Liu

    2009-12-01

    Full Text Available The study investigates a capacitive micro pressure sensor integrated with a ring oscillator circuit on a chip. The integrated capacitive pressure sensor is fabricated using the commercial CMOS (complementary metal oxide semiconductor process and a post-process. The ring oscillator is employed to convert the capacitance of the pressure sensor into the frequency output. The pressure sensor consists of 16 sensing cells in parallel. Each sensing cell contains a top electrode and a lower electrode, and the top electrode is a sandwich membrane. The pressure sensor needs a post-CMOS process to release the membranes after completion of the CMOS process. The post-process uses etchants to etch the sacrificial layers, and to release the membranes. The advantages of the post-process include easy execution and low cost. Experimental results reveal that the pressure sensor has a high sensitivity of 7 Hz/Pa in the pressure range of 0–300 kPa.

  10. Simultaneous detection of lactate and glucose by integrated printed circuit board based array sensing chip

    International Nuclear Information System (INIS)

    Highlights: ► An integrated printed circuit board (PCB) based array sensing chip was developed. ► Simultaneous detection of lactate and glucose in serum has been demonstrated. ► The array electronic biochip has high signal to noise ratio and high sensitivity. ► Additional electrodes were designed on the chip to correct interferences. -- Abstract: An integrated printed circuit board (PCB) based array sensing chip was developed to simultaneously detect lactate and glucose in mouse serum. The novelty of the chip relies on a concept demonstration of inexpensive high-throughput electronic biochip, a chip design for high signal to noise ratio and high sensitivity by construction of positively charged chitosan/redox polymer Polyvinylimidazole-Os (PVI-Os)/carbon nanotube (CNT) composite sensing platform, in which the positively charged chitosan/PVI-Os is mediator and electrostatically immobilizes the negatively charged enzyme, while CNTs function as an essential cross-linker to network PVI-Os and chitosan due to its negative charged nature. Additional electrodes on the chip with the same sensing layer but without enzymes were prepared to correct the interferences for high specificity. Low detection limits of 0.6 μM and 5 μM were achieved for lactate and glucose, respectively. This work could be extended to inexpensive array sensing chips with high sensitivity, good specificity and high reproducibility for various sensor applications

  11. Mode converter based on an inverse taper for multimode silicon nanophotonic integrated circuits.

    Science.gov (United States)

    Dai, Daoxin; Mao, Mao

    2015-11-01

    An inverse taper on silicon is proposed and designed to realize an efficient mode converter available for the connection between multimode silicon nanophotonic integrated circuits and few-mode fibers. The present mode converter has a silicon-on-insulator inverse taper buried in a 3 × 3μm(2) SiN strip waveguide to deal with not only for the fundamental mode but also for the higher-order modes. The designed inverse taper enables the conversion between the six modes (i.e., TE(11), TE(21), TE(31), TE(41), TM(11), TM(12)) in a 1.4 × 0.22μm(2) multimode SOI waveguide and the six modes (like the LP(01), LP(11a), LP(11b) modes in a few-mode fiber) in a 3 × 3μm(2) SiN strip waveguide. The conversion efficiency for any desired mode is higher than 95.6% while any undesired mode excitation ratio is lower than 0.5%. This is helpful to make multimode silicon nanophotonic integrated circuits (e.g., the on-chip mode (de)multiplexers developed well) available to work together with few-mode fibers in the future. PMID:26561108

  12. Simultaneous detection of lactate and glucose by integrated printed circuit board based array sensing chip

    Energy Technology Data Exchange (ETDEWEB)

    Li, Xuelian [Institute for Clean Energy and Advanced Materials, Southwest University, Chongqing 400715 (China); School of Chemistry and Chemical Engineering, Southwest University, Chongqing 400715 (China); Zang, Jianfeng [Department of Mechanical Engineering and Materials Science, Duke University, Durham, NC 27708 (United States); Liu, Yingshuai; Lu, Zhisong [Institute for Clean Energy and Advanced Materials, Southwest University, Chongqing 400715 (China); Li, Qing, E-mail: Qli@swu.edu.cn [School of Chemistry and Chemical Engineering, Southwest University, Chongqing 400715 (China); Li, Chang Ming, E-mail: ecmli@swu.edu.cn [Institute for Clean Energy and Advanced Materials, Southwest University, Chongqing 400715 (China)

    2013-04-10

    Highlights: ► An integrated printed circuit board (PCB) based array sensing chip was developed. ► Simultaneous detection of lactate and glucose in serum has been demonstrated. ► The array electronic biochip has high signal to noise ratio and high sensitivity. ► Additional electrodes were designed on the chip to correct interferences. -- Abstract: An integrated printed circuit board (PCB) based array sensing chip was developed to simultaneously detect lactate and glucose in mouse serum. The novelty of the chip relies on a concept demonstration of inexpensive high-throughput electronic biochip, a chip design for high signal to noise ratio and high sensitivity by construction of positively charged chitosan/redox polymer Polyvinylimidazole-Os (PVI-Os)/carbon nanotube (CNT) composite sensing platform, in which the positively charged chitosan/PVI-Os is mediator and electrostatically immobilizes the negatively charged enzyme, while CNTs function as an essential cross-linker to network PVI-Os and chitosan due to its negative charged nature. Additional electrodes on the chip with the same sensing layer but without enzymes were prepared to correct the interferences for high specificity. Low detection limits of 0.6 μM and 5 μM were achieved for lactate and glucose, respectively. This work could be extended to inexpensive array sensing chips with high sensitivity, good specificity and high reproducibility for various sensor applications.

  13. Efficient Hierarchical Algorithm for Mixed Mode Placement in Three Dimensional Integrated Circuit Chip Designs

    Institute of Scientific and Technical Information of China (English)

    YAN Haixia; ZHOU Qiang; HONG Xianlong; LI Zhuoyuan

    2009-01-01

    Hierarchical art was used to solve the mixed mode placement for three dimensional (3-D) inte-grated circuit design. The 3-D placement flow stream includes hierarchical clustering, hierarchical 3-D floor-planning, vertical via mapping, and recursive two dimensional (2-D) global/detailed placement phases. With state-of-the-art clustering and de-clustering phases, the design complexity was reduced to enhance the placement algorithm efficiency and capacity. The 3-D floorplanning phase solved the layer assignment problem and controlled the number of vertical vias. The vertical via mapping transformed the 3-D placement problem to a set of 2-D placement sub-problems, which not only simplifies the original 3-D placement prob-lem, but also generates the vertical via assignment solution for the routing phase. The design optimizes both the wire length and the thermal load in the floorplan and placement phases to improve the performance and reliability of 3-D integrate circuits. Experiments on IBM benchmarks show that the total wire length is reduced from 15% to 35% relative to 2-D placement with two to four stacked layers, with the number of vertical vias minimized to satisfy a pre-defined upper bound constraint. The maximum temperature is reduced by 16% with two-stage optimization on four stacked layers.

  14. Fully Integrated Applications of Thin Films on Low Temperature Cofired Ceramic (LTCC)

    Energy Technology Data Exchange (ETDEWEB)

    Ambrose Wolf; Ken Peterson; Matt O' Keefe; Wayne Huebner; Bill Kuhn

    2012-04-19

    Thin film multilayers have previously been introduced on multilayer low temperature cofired ceramic (LTCC), as well as initial thin film capacitors on LTCC. The ruggedness of a multipurpose Ti-Cu-Pt-Au stack for connectivity and RF conductivity has continued to benefit fabrication and reliability in state of-the-art modules, while the capacitors have followed the traditional Metal-Insulator-Metal (MIM) style. The full integration of thin film passives with thin film connectivity traces is presented. Certain passives, such as capacitors, require specifically tailored and separately patterned thin film (multi-)layers, including a dielectric. Different capacitance values are achieved by variation of both the insulator layer thickness and the active area of the capacitor. Other passives, such as filters, require only the conductor - a single thin film multilayer. This can be patterned from the same connectivity thin film material (Ti-Cu-Pt-Au), or a specially tailored thin film material (e.g. Ti-Cu-Au) can be deposited. Both versions are described, including process and integration details. Examples are discussed, ranging from patterning for maximum tolerances, to space and performance-optimized designs. Cross-sectional issues associated with integration are also highlighted in the discussion.

  15. Fully Integrated, Miniature, High-Frequency Flow Probe Utilizing MEMS Leadless SOI Technology

    Science.gov (United States)

    Ned, Alex; Kurtz, Anthony; Shang, Tonghuo; Goodman, Scott; Giemette. Gera (d)

    2013-01-01

    This work focused on developing, fabricating, and fully calibrating a flowangle probe for aeronautics research by utilizing the latest microelectromechanical systems (MEMS), leadless silicon on insulator (SOI) sensor technology. While the concept of angle probes is not new, traditional devices had been relatively large due to fabrication constraints; often too large to resolve flow structures necessary for modern aeropropulsion measurements such as inlet flow distortions and vortices, secondary flows, etc. Mea surements of this kind demanded a new approach to probe design to achieve sizes on the order of 0.1 in. (.3 mm) diameter or smaller, and capable of meeting demanding requirements for accuracy and ruggedness. This approach invoked the use of stateof- the-art processing techniques to install SOI sensor chips directly onto the probe body, thus eliminating redundancy in sensor packaging and probe installation that have historically forced larger probe size. This also facilitated a better thermal match between the chip and its mount, improving stability and accuracy. Further, the leadless sensor technology with which the SOI sensing element is fabricated allows direct mounting and electrical interconnecting of the sensor to the probe body. This leadless technology allowed a rugged wire-out approach that is performed at the sensor length scale, thus achieving substantial sensor size reductions. The technology is inherently capable of high-frequency and high-accuracy performance in high temperatures and harsh environments.

  16. On the Basis of Synaptic Integration Constancy during Growth of a Neuronal Circuit

    Science.gov (United States)

    De-La-Rosa Tovar, Adriana; Mishra, Prashant K.; De-Miguel, Francisco F.

    2016-01-01

    We studied how a neuronal circuit composed of two neuron types connected by chemical and electrical synapses maintains constant its integrative capacities as neurons grow. For this we combined electrophysiological experiments with mathematical modeling in pairs of electrically-coupled Retzius neurons from postnatal to adult leeches. The electrically-coupled dendrites of both Retzius neurons receive a common chemical input, which produces excitatory postsynaptic potentials (EPSPs) with varying amplitudes. Each EPSP spreads to the soma, but also crosses the electrical synapse to arrive at the soma of the coupled neuron. The leak of synaptic current across the electrical synapse reduces the amplitude of the EPSPs in proportion to the coupling ratio. In addition, summation of EPSPs generated in both neurons generates the baseline action potentials of these serotonergic neurons. To study how integration is adjusted as neurons grow, we first studied the characteristics of the chemical and electrical connections onto the coupled dendrites of neuron pairs with soma diameters ranging from 21 to 75 μm. Then by feeding a mathematical model with the neuronal voltage responses to pseudorandom noise currents we obtained the values of the coupling ratio, the membrane resistance of the soma (rm) and dendrites (rdend), the space constant (λ) and the characteristic dendritic length (L = l/λ). We found that the EPSPs recorded from the somata were similar regardless on the neuron size. However, the amplitude of the EPSPs and the firing frequency of the neurons were inversely proportional to the coupling ratio of the neuron pair, which also was independent from the neuronal size. This data indicated that the integrative constancy relied on the passive membrane properties. We show that the growth of Retzius neurons was compensated by increasing the membrane resistance of the dendrites and therefore the λ value. By solely increasing the dendrite resistance this circuit maintains

  17. ON THE BASIS OF SYNAPTIC INTEGRATION CONSTANCY DURING GROWTH OF A NEURONAL CIRCUIT

    Directory of Open Access Journals (Sweden)

    Adriana De la Rosa

    2016-08-01

    Full Text Available We studied how a neuronal circuit composed of two neuron types connected by chemical and electrical synapses maintains constant its integrative capacities as neurons grow. For this we combined electrophysiological experiments with mathematical modeling in pairs of electrically-coupled Retzius neurons from postnatal to adult leeches. The electrically-coupled dendrites of both Retzius neurons receive a common chemical input, which produces EPSPs with varying amplitudes. Each EPSP spreads to the soma, but also crosses the electrical synapse to arrive at the soma of the coupled neuron. The leak of synaptic current across the electrical synapse reduces the amplitude of the EPSPs in proportion to the coupling ratio. In addition, summation of EPSPs generated in both neurons generates the baseline action potentials of these serotonergic neurons. To study how integration is adjusted as neurons grow we first studied the characteristics of the chemical and electrical connections onto the coupled dendrites of neuron pairs with soma diameters ranging from 21 to 75 µm. Then by feeding a mathematical model with the neuronal voltage responses to pseudorandom noise currents we obtained the values of the coupling ratio, the membrane resistance of the soma (rm and dendrites (rdend, the space constant (λ and the characteristic dendritic length (L=l/λ . We found that the EPSPs recorded from the somata were similar regardless on the neuron size. However, the amplitude of the EPSPs and the firing frequency of the neurons were inversely proportional to the coupling ratio of the neuron pair, which also was independent form the neuronal size. This data indicated that the integrative constancy relied on the passive membrane properties. We show that the growth of Retzius neurons was compensated by increasing the membrane resistance of the dendrites and therefore the λ value. By solely increasing the dendrite resistance this circuit maintains constant its integrative

  18. On the Basis of Synaptic Integration Constancy during Growth of a Neuronal Circuit.

    Science.gov (United States)

    De-La-Rosa Tovar, Adriana; Mishra, Prashant K; De-Miguel, Francisco F

    2016-01-01

    We studied how a neuronal circuit composed of two neuron types connected by chemical and electrical synapses maintains constant its integrative capacities as neurons grow. For this we combined electrophysiological experiments with mathematical modeling in pairs of electrically-coupled Retzius neurons from postnatal to adult leeches. The electrically-coupled dendrites of both Retzius neurons receive a common chemical input, which produces excitatory postsynaptic potentials (EPSPs) with varying amplitudes. Each EPSP spreads to the soma, but also crosses the electrical synapse to arrive at the soma of the coupled neuron. The leak of synaptic current across the electrical synapse reduces the amplitude of the EPSPs in proportion to the coupling ratio. In addition, summation of EPSPs generated in both neurons generates the baseline action potentials of these serotonergic neurons. To study how integration is adjusted as neurons grow, we first studied the characteristics of the chemical and electrical connections onto the coupled dendrites of neuron pairs with soma diameters ranging from 21 to 75 μm. Then by feeding a mathematical model with the neuronal voltage responses to pseudorandom noise currents we obtained the values of the coupling ratio, the membrane resistance of the soma (rm ) and dendrites (r dend), the space constant (λ) and the characteristic dendritic length (L = l/λ). We found that the EPSPs recorded from the somata were similar regardless on the neuron size. However, the amplitude of the EPSPs and the firing frequency of the neurons were inversely proportional to the coupling ratio of the neuron pair, which also was independent from the neuronal size. This data indicated that the integrative constancy relied on the passive membrane properties. We show that the growth of Retzius neurons was compensated by increasing the membrane resistance of the dendrites and therefore the λ value. By solely increasing the dendrite resistance this circuit maintains

  19. Fully integrated InGaAs/InP single-photon detector module with gigahertz sine wave gating

    OpenAIRE

    Liang, Xiao-Lei; Liu, Jian-Hong; Wang, Quan; Du, De-Bing; Ma, Jian; Jin, Ge; Chen, Zeng-Bing; Zhang, Jun; Pan, Jian-Wei

    2012-01-01

    InGaAs/InP single-photon avalanche diodes (SPADs) working in the regime of GHz clock rates are crucial components for the high-speed quantum key distribution (QKD). We have developed for the first time a compact, stable and user-friendly tabletop InGaAs/InP single-photon detector system operating at a 1.25 GHz gate rate that fully integrates functions for controlling and optimizing SPAD performance. We characterize the key parameters of the detector system and test the long-term stability of ...

  20. Design and performance of a multi-channel, multi-sampling, PSD-enabling integrated circuit

    Energy Technology Data Exchange (ETDEWEB)

    Engel, G.L., E-mail: gengel@siue.ed [Department of Electrical and Computer Engineering, VLSI Design Research Laboratory, Southern Illinois University Edwardsville, Engineering Building, Room 3043 Edwardsville, IL 62026 1081 (United States); Hall, M.J.; Proctor, J.M. [Department of Electrical and Computer Engineering, VLSI Design Research Laboratory, Southern Illinois University Edwardsville, Engineering Building, Room 3043 Edwardsville, IL 62026 1081 (United States); Elson, J.M.; Sobotka, L.G.; Shane, R.; Charity, R.J. [Departments of Chemistry and Physics, Washington University, Saint Louis, MO 63130 (United States)

    2009-12-21

    This paper presents the design and test results of an eight-channel prototype integrated circuit chip intended to greatly simplify the pulse-processing electronics needed for large arrays of scintillation detectors. Because the chip design employs (user-controlled) multi-region charge integration, particle identification is incorporated into the basic design. Each channel on the chip also contains a time-to-voltage converter which provides relative time information. The pulse-height integrals and the relative time are all stored on capacitors and are either reset, after a user controlled time, or sequentially read out if acquisition of the event is desired. Each of the three pulse-height sub-channels consists of a gated integrator with eight programmable charging rates and an externally programmable gate generator that defines the start (with four time ranges) and width (with four time ranges) of the gate relative to an external discriminator signal. The chip supports three triggering modes, two time ranges, two power modes, and produces four sparsified analog pulse trains (three for the integrators and another for the time) with synchronized addresses for off-chip digitization with a pipelined ADC. The eight-channel prototype chip occupies an area of 2.8 mmx5.7 mm, dissipates 60 mW (low-power mode), and was fabricated in the AMI 0.5-mum process (C5N).

  1. Disposable photonic integrated circuits for evanescent wave sensors by ultra-high volume roll-to-roll method.

    Science.gov (United States)

    Aikio, Sanna; Hiltunen, Jussi; Hiitola-Keinänen, Johanna; Hiltunen, Marianne; Kontturi, Ville; Siitonen, Samuli; Puustinen, Jarkko; Karioja, Pentti

    2016-02-01

    Flexible photonic integrated circuit technology is an emerging field expanding the usage possibilities of photonics, particularly in sensor applications, by enabling the realization of conformable devices and introduction of new alternative production methods. Here, we demonstrate that disposable polymeric photonic integrated circuit devices can be produced in lengths of hundreds of meters by ultra-high volume roll-to-roll methods on a flexible carrier. Attenuation properties of hundreds of individual devices were measured confirming that waveguides with good and repeatable performance were fabricated. We also demonstrate the applicability of the devices for the evanescent wave sensing of ambient refractive index. The production of integrated photonic devices using ultra-high volume fabrication, in a similar manner as paper is produced, may inherently expand methods of manufacturing low-cost disposable photonic integrated circuits for a wide range of sensor applications. PMID:26906827

  2. Multi-format all-optical processing based on a large-scale, hybridly integrated photonic circuit.

    Science.gov (United States)

    Bougioukos, M; Kouloumentas, Ch; Spyropoulou, M; Giannoulis, G; Kalavrouziotis, D; Maziotis, A; Bakopoulos, P; Harmon, R; Rogers, D; Harrison, J; Poustie, A; Maxwell, G; Avramopoulos, H

    2011-06-01

    We investigate through numerical studies and experiments the performance of a large scale, silica-on-silicon photonic integrated circuit for multi-format regeneration and wavelength-conversion. The circuit encompasses a monolithically integrated array of four SOAs inside two parallel Mach-Zehnder structures, four delay interferometers and a large number of silica waveguides and couplers. Exploiting phase-incoherent techniques, the circuit is capable of processing OOK signals at variable bit rates, DPSK signals at 22 or 44 Gb/s and DQPSK signals at 44 Gbaud. Simulation studies reveal the wavelength-conversion potential of the circuit with enhanced regenerative capabilities for OOK and DPSK modulation formats and acceptable quality degradation for DQPSK format. Regeneration of 22 Gb/s OOK signals with amplified spontaneous emission (ASE) noise and DPSK data signals degraded with amplitude, phase and ASE noise is experimentally validated demonstrating a power penalty improvement up to 1.5 dB.

  3. 3D knife-edge characterization of two-photon absorption volume in silicon for integrated circuit testing.

    Science.gov (United States)

    Shao, K; Morisset, A; Pouget, V; Faraud, E; Larue, C; Lewis, D; McMorrow, D

    2011-11-01

    We have performed three-dimensional characterization of the TPA effective laser spot size in silicon using an integrated knife-edge sensor. The TPA-induced response of a CMOS integrated circuit is analyzed based on these results and compared to simulation; we have found that the charge injection capacity in IC's active layer could be influenced by irradiance energy and focus depth.

  4. A fully coupled regional atmospheric numerical model for integrated air quality and weather forecasting.

    Science.gov (United States)

    Freitas, S. R.; Longo, K. M.; Marecal, V.; Pirre, M.; Gmai, T.

    2012-04-01

    A new numerical modelling tool devoted to local and regional studies of atmospheric chemistry from surface to the lower stratosphere designed for both operational and research purposes will be presented. This model is based on the limited-area model CATT-BRAMS (Coupled Aerosol-Tracer Transport model to the Brazilian developments on the Regional Atmospheric Modeling System, Freitas et al. 2009, Longo et al. 2010) which is a meteorological model (BRAMS) including transport processes of gaseous and aerosols (CATT model). BRAMS is a version of the RAMS model (Walko et al. 2000) adapted to better represent tropical and subtropical processes and several new features. CATT-BRAMS has been used operationally at CPTEC (Brazilian Center for Weather Prediction and Climate Studies) since 2003 providing coupled weather and air quality forecast. In the Chemistry-CATT-BRAMS (called hereafter CCATT-BRAMS) a chemical module is fully coupled to the meteorological/tracer transport model CATT-BRAMS. This module includes gaseous chemistry, photochemistry, scavenging and dry deposition. The CCATT-BRAMS model takes advantages of the BRAMS specific development for the tropics/subtropics and of the recent availability of preprocessing tools for chemical mechanisms and of fast codes for photolysis rates. Similarly to BRAMS this model is conceived to run for horizontal resolutions ranging from a few meters to more than a hundred kilometres depending on the chosen scientific objective. In the last decade CCATT-BRAMS has being broadly (or extensively) used for applications mainly over South America, with strong emphasis over the Amazonia area and the main South American megacities. An overview of the model development and main applications will be presented.

  5. SmartStep: A Fully Integrated, Low-Power Insole Monitor

    Directory of Open Access Journals (Sweden)

    Nagaraj Hegde

    2014-06-01

    Full Text Available Shoe-mounted wearable sensors can be used in applications, such as activity monitoring, gait analysis, post-stroke rehabilitation, body weight measurements and energy expenditure studies. Such wearable sensors typically require the modification or alteration of the shoe, which is not typically feasible for large populations without the direct involvement of shoe manufacturers. This article presents an insole-based wearable sensor (SmartStep that has its electronics fully embedded into a generic insole, which is usable with a large variety of shoes and, thus, resolves the need for shoe modification. The SmartStep is an always-on electronic device that comprises a 3D accelerometer, a 3D gyroscope and resistive pressure sensors implemented around a CC2540 system-on-chip with an 8051 processor core, Bluetooth low energy (BLE connectivity and flash memory buffer. The SmartStep is wirelessly interfaced to an Android smart phone application with data logging and visualization capabilities. This article focuses on low-power implementation methods and on the method developed for reliable data buffering, alleviating intermittent connectivity resulting from the user leaving the vicinity of the smart phone. The conducted tests illustrate the power consumption for several possible usage scenarios and the reliability of the data retention method. The trade-off between the power consumption and supported functionality is discussed, demonstrating that SmartStep can be worn for more than two days between battery recharges. The results of the mechanical reliability test on the SmartStep indicate that the pressure sensors in the SmartStep tolerated prolonged human wear. The SmartStep system collected more than 98.5% of the sensor data, in real usage scenarios, having intermittent connectivity with the smart phone.

  6. Lock-in range of PLL-based circuits with proportionally-integrating filter and sinusoidal phase detector characteristic

    OpenAIRE

    Aleksandrov, K. D.; Kuznetsov, N. V.; Leonov, G. A.; Yuldashev, M. V.; Yuldashev, R. V.

    2016-01-01

    In the present work PLL-based circuits with sinusoidal phase detector characteristic and active proportionally-integrating (PI) filter are considered. The notion of lock-in range -- an important characteristic of PLL-based circuits, which corresponds to the synchronization without cycle slipping, is studied. For the lock-in range a rigorous mathematical definition is discussed. Numerical and analytical estimates for the lock-in range are obtained.

  7. Test and diagnosis of analogue, mixed-signal and RF integrated circuits the system on chip approach

    CERN Document Server

    Sun, Yichuang

    2008-01-01

    This book provides a comprehensive discussion of automatic testing, diagnosis and tuning of analogue, mixed-signal and RF integrated circuits, and systems in a single source. The book contains eleven chapters written by leading researchers worldwide. As well as fundamental concepts and techniques, the book reports systematically the state of the arts and future research directions of these areas. A complete range of circuit components are covered and test issues are also addressed from the SoC perspective.

  8. Fully integrated reflection-mode photoacoustic/two-photon microscopy in vivo (Conference Presentation)

    Science.gov (United States)

    Song, Liang; Song, Wei; Zhang, Yang; Zheng, Wei

    2016-03-01

    Using a water-immersion optical objective in conjunction with a miniature 40-MHz ultrasonic transducer, we developed reflection-mode photoacoustic microscopy with a transverse resolution as high as 320 nm. Here, we further integrated two-photon microscopy capability into the system to enable multimodality in vivo biomedical imaging at submicron resolution. As a result, the system is capable of tri-modality label-free imaging of microvasculature, collagen, and cell morphology, based on the contrast of optical absorption, second-harmonic generation, and autofluorescence, respectively. In addition, we demonstrated simultaneous microscopic imaging of neuron and microvasculature in the brain cortex of a living mouse, which may offer new opportunities for studying the mechanisms of neurovascular coupling.

  9. Design, fabrication, and characterisation of fully etched TM grating coupler for photonic integrated system-in-package

    Science.gov (United States)

    Gili-de-Villasante, Oriol; Tcheg, Paul; Wang, Bei; Suna, Alpaslan; Giannoulis, Giannis; Lazarou, Ioannis; Apostolopoulos, Dimitrios; Avramopoulos, Hercules; Pleros, Nikos; Baus, Matthias; Karl, Matthias; Tekin, Tolga

    2012-06-01

    Grating couplers are the best solution for testing nano-photonic circuits. Their main benefit is that they allow access via an optical fiber from the top and therefore there is no need to dice the chip and prepare the facets crucially. In the PLATON project grating couplers were designed to couple TM mode into and out of the SOI waveguides. Simulations came up with a grating coupler layout capable of theoretical coupling losses lower than 3dB for 1550 nm in TM configuration. A fully etched grating structure was chosen for fabrication simplicity and the optimal filling factor was found. The structures were fabricated using proximity error correction (PEC) and show a uniform coupling efficiency for all couplers. Therefore they are well-suited for all applications which demand for stable fiber-to-chip coupling. The spectral response of the structures was measured from 1500 to 1580 nm with 2 nm step and measuring the fiber-tofiber losses of three straight waveguides equipped with three grating couplers with different gap widths. The optimal grating period exhibits adequate coupling losses of 3.23 dB per coupler at 1557 nm, being therefore the most promising design.

  10. A Fully Integrated and Miniaturized Heavy-metal-detection Sensor Based on Micro-patterned Reduced Graphene Oxide.

    Science.gov (United States)

    Xuan, Xing; Hossain, Md Faruk; Park, Jae Yeong

    2016-01-01

    For this paper, a fully integrated and highly miniaturized electrochemical sensor was designed and fabricated on a silicon substrate. A solvothermal-assisted reduced graphene oxide named "TRGO" was then successfully micro-patterned using a lithography technique, followed by the electrodeposition of bismuth (Bi) on the surface of the micro-patterned TRGO for the electrochemical detection of heavy metal ions. The fully integrated electrochemical micro-sensor was then measured and evaluated for the detection of cadmium and lead-heavy metal ions in an acetic-acid buffered solution using the square wave anodic stripping voltammetry (SWASV) technique. The fabricated micro-sensor exhibited a linear detection range of 1.0 μg L(-1) to 120.0 μg L(-1) for both of the metal ions, and detection limits of 0.4 μg L(-1) and 1.0 μg L(-1) were recorded for the lead and cadmium (S/N = 3), respectively. Drinking-water samples were used for the practical assessment of the fabricated micro-sensor, and it showed an acceptable detection performance regarding the metal ions. PMID:27616629

  11. Single-chip fully integrated direct-modulation CMOS RF transmitters for short-range wireless applications.

    Science.gov (United States)

    El-Desouki, Munir M; Qasim, Syed Manzoor; BenSaleh, Mohammed; Deen, M Jamal

    2013-01-01

    Ultra-low power radio frequency (RF) transceivers used in short-range application such as wireless sensor networks (WSNs) require efficient, reliable and fully integrated transmitter architectures with minimal building blocks. This paper presents the design, implementation and performance evaluation of single-chip, fully integrated 2.4 GHz and 433 MHz RF transmitters using direct-modulation power voltage-controlled oscillators (PVCOs) in addition to a 2.0 GHz phase-locked loop (PLL) based transmitter. All three RF transmitters have been fabricated in a standard mixed-signal CMOS 0.18 µm technology. Measurement results of the 2.4 GHz transmitter show an improvement in drain efficiency from 27% to 36%. The 2.4 GHz and 433 MHz transmitters deliver an output power of 8 dBm with a phase noise of -122 dBc/Hz at 1 MHz offset, while drawing 15.4 mA of current and an output power of 6.5 dBm with a phase noise of -120 dBc/Hz at 1 MHz offset, while drawing 20.8 mA of current from 1.5 V power supplies, respectively. The PLL transmitter delivers an output power of 9 mW with a locking range of 128 MHz and consumes 26 mA from 1.8 V power supply. The experimental results demonstrate that the RF transmitters can be efficiently used in low power WSN applications. PMID:23917260

  12. A Fully Integrated and Miniaturized Heavy-metal-detection Sensor Based on Micro-patterned Reduced Graphene Oxide

    Science.gov (United States)

    Xuan, Xing; Hossain, Md. Faruk; Park, Jae Yeong

    2016-09-01

    For this paper, a fully integrated and highly miniaturized electrochemical sensor was designed and fabricated on a silicon substrate. A solvothermal-assisted reduced graphene oxide named “TRGO” was then successfully micro-patterned using a lithography technique, followed by the electrodeposition of bismuth (Bi) on the surface of the micro-patterned TRGO for the electrochemical detection of heavy metal ions. The fully integrated electrochemical micro-sensor was then measured and evaluated for the detection of cadmium and lead-heavy metal ions in an acetic-acid buffered solution using the square wave anodic stripping voltammetry (SWASV) technique. The fabricated micro-sensor exhibited a linear detection range of 1.0 μg L-1 to 120.0 μg L-1 for both of the metal ions, and detection limits of 0.4 μg L-1 and 1.0 μg L-1 were recorded for the lead and cadmium (S/N = 3), respectively. Drinking-water samples were used for the practical assessment of the fabricated micro-sensor, and it showed an acceptable detection performance regarding the metal ions.

  13. Integrated hydrometeorological predictions with the fully-coupled WRF-Hydro modeling system in western North America

    Science.gov (United States)

    Gochis, D. J.; Yu, W.

    2013-12-01

    Prediction of heavy rainfall and associated streamflow responses remain as critical hydrometeorological challenges and require improved understanding of the linkages between atmospheric and land surface processes. Streamflow prediction skill is intrinsically liked to quantitative precipitation forecast skill, which emphasizes the need to produce mesoscale predictions of rainfall of high fidelity. However, in many cases land surface parameters can also exert significant control on the runoff response to heavy rainfall and on the formation or localization of heavy rainfall as well. A new generation of integrated atmospheric-hydrologic modeling systems is emerging from different groups around the world to meet the challenge of integrated water cycle predictions. In this talk the community WRF-Hydro modeling system will be presented. After a brief reviewing the architectural features of the WRF-Hydro system short-term forecasting and regional hydroclimate prediction applications of the model from western North America will be presented. In these applications, analyses will present results from observation-validated prediction experiments where atmospheric and terrestrial hydrologic model components are run in both a fully coupled mode and separately without two-way interactions. Emphasis is placed on illustrating an assessment framework using an initial state perturbation methodology to quantify the role of land-atmosphere energy and moisture flux partitioning in controlling precipitation and runoff forecast skill. Issues related to experimental design of fully-coupled model prediction experiments will also be discussed as will issues related to computational performance.

  14. Flexible low-voltage organic integrated circuits with megahertz switching frequencies (Presentation Recording)

    Science.gov (United States)

    Zschieschang, Ute; Takimiya, Kazuo; Zaki, Tarek; Letzkus, Florian; Richter, Harald; Burghartz, Joachim N.; Klauk, Hagen

    2015-09-01

    A process for the fabrication of integrated circuits based on bottom-gate, top-contact organic thin-film transistors (TFTs) with channel lengths as short as 1 µm on flexible plastic substrates has been developed. In this process, all TFT layers (gate electrodes, organic semiconductors, source/drain contacts) are patterned with the help of high-resolution silicon stencil masks, thus eliminating the need for subtractive patterning and avoiding the exposure of the organic semiconductors to potentially harmful organic solvents or resists. The TFTs employ a low-temperature-processed gate dielectric that is sufficiently thin to allow the TFTs and circuits to operate with voltages of about 3 V. Using the vacuum-deposited small-molecule organic semiconductor 2,9-didecyl-dinaphtho[2,3-b:2',3'-f]thieno[3,2-b]thiophene (C10 DNTT), TFTs with an effective field-effect mobility of 1.2 cm2/Vs, an on/off current ratio of 107, a width-normalized transconductance of 1.2 S/m (with a standard deviation of 6%), and a signal propagation delay (measured in 11-stage ring oscillators) of 420 nsec per stage at a supply voltage of 3 V have been obtained. To our knowledge, this is the first time that megahertz operation has been achieved in flexible organic transistors at supply voltages of less than 10 V. In addition to flexible ring oscillators, we have also demonstrated a 6-bit digital-to-analog converter (DAC) in a binary-weighted current-steering architecture, based on TFTs with a channel length of 4 µm and fabricated on a glass substrate. This DAC has a supply voltage of 3.3 V, a circuit area of 2.6 × 4.6 mm2, and a maximum sampling rate of 100 kS/s.

  15. Novel fully integrated computer system for custom footwear: from 3D digitization to manufacturing

    Science.gov (United States)

    Houle, Pascal-Simon; Beaulieu, Eric; Liu, Zhaoheng

    1998-03-01

    This paper presents a recently developed custom footwear system, which integrates 3D digitization technology, range image fusion techniques, a 3D graphical environment for corrective actions, parametric curved surface representation and computer numerical control (CNC) machining. In this system, a support designed with the help of biomechanics experts can stabilize the foot in a correct and neutral position. The foot surface is then captured by a 3D camera using active ranging techniques. A software using a library of documented foot pathologies suggests corrective actions on the orthosis. Three kinds of deformations can be achieved. The first method uses previously scanned pad surfaces by our 3D scanner, which can be easily mapped onto the foot surface to locally modify the surface shape. The second kind of deformation is construction of B-Spline surfaces by manipulating control points and modifying knot vectors in a 3D graphical environment to build desired deformation. The last one is a manual electronic 3D pen, which may be of different shapes and sizes, and has an adjustable 'pressure' information. All applied deformations should respect a G1 surface continuity, which ensure that the surface can accustom a foot. Once the surface modification process is completed, the resulting data is sent to manufacturing software for CNC machining.

  16. A fully integrated microfluidic genetic analysis system with sample-in-answer-out capability.

    Science.gov (United States)

    Easley, Christopher J; Karlinsey, James M; Bienvenue, Joan M; Legendre, Lindsay A; Roper, Michael G; Feldman, Sanford H; Hughes, Molly A; Hewlett, Erik L; Merkel, Tod J; Ferrance, Jerome P; Landers, James P

    2006-12-19

    We describe a microfluidic genetic analysis system that represents a previously undescribed integrated microfluidic device capable of accepting whole blood as a crude biological sample with the endpoint generation of a genetic profile. Upon loading the sample, the glass microfluidic genetic analysis system device carries out on-chip DNA purification and PCR-based amplification, followed by separation and detection in a manner that allows for microliter samples to be screened for infectious pathogens with sample-in-answer-out results in pump delivers sample/reagents to the chip for nucleic acid purification from a biological sample. Elastomeric membrane valving isolates each distinct functional region of the device and, together with resistive flow, directs purified DNA and PCR reagents from the extraction domain into a 550-nl chamber for rapid target sequence PCR amplification. Repeated pressure-based injections of nanoliter aliquots of amplicon (along with the DNA sizing standard) allow electrophoretic separation and detection to provide DNA fragment size information. The presence of Bacillus anthracis (anthrax) in 750 nl of whole blood from living asymptomatic infected mice and of Bordetella pertussis in 1 microl of nasal aspirate from a patient suspected of having whooping cough are confirmed by the resultant genetic profile. PMID:17159153

  17. Carbon Nanotube Self-Gating Diode and Application in Integrated Circuits.

    Science.gov (United States)

    Si, Jia; Liu, Lijun; Wang, Fanglin; Zhang, Zhiyong; Peng, Lian-Mao

    2016-07-26

    A nano self-gating diode (SGD) based on nanoscale semiconducting material is proposed, simulated, and realized on semiconducting carbon nanotubes (CNTs) through a doping-free fabrication process. The relationships between the performance and material/structural parameters of the SGD are explored through numerical simulation and verified by experiment results. Based on these results, performance optimization strategy is outlined, and high performance CNT SGDs are fabricated and demonstrated to surpass other published CNT diodes. In particular the CNT SGD exhibits high rectifier factor of up to 1.4 × 10(6) while retains large on-state current. Benefiting from high yield and stability, CNT SGDs are used for constructing logic and analog integrated circuits. Two kinds of basic digital gates (AND and OR) have been realized on chip through using CNT SGDs and on-chip Ti wire resistances, and a full wave rectifier circuit has been demonstrated through using two CNT SGDs. Although demonstrated here using CNT SGDs, this device structure may in principle be implemented using other semiconducting nanomaterials, to provide ideas and building blocks for electronic applications based on nanoscale materials. PMID:27322134

  18. Cobalt Oxide Nanosheet and CNT Micro Carbon Monoxide Sensor Integrated with Readout Circuit on Chip

    Science.gov (United States)

    Dai, Ching-Liang; Chen, Yen-Chi; Wu, Chyan-Chyi; Kuo, Chin-Fu

    2010-01-01

    The study presents a micro carbon monoxide (CO) sensor integrated with a readout circuit-on-a-chip manufactured by the commercial 0.35 μm complementary metal oxide semiconductor (CMOS) process and a post-process. The sensing film of the sensor is a composite cobalt oxide nanosheet and carbon nanotube (CoOOH/CNT) film that is prepared by a precipitation-oxidation method. The structure of the CO sensor is composed of a polysilicon resistor and a sensing film. The sensor, which is of a resistive type, changes its resistance when the sensing film adsorbs or desorbs CO gas. The readout circuit is used to convert the sensor resistance into the voltage output. The post-processing of the sensor includes etching the sacrificial layers and coating the sensing film. The advantages of the sensor include room temperature operation, short response/recovery times and easy post-processing. Experimental results show that the sensitivity of the CO sensor is about 0.19 mV/ppm, and the response and recovery times are 23 s and 34 s for 200 ppm CO, respectively. PMID:22294897

  19. Polypyrrole Porous Micro Humidity Sensor Integrated with a Ring Oscillator Circuit on Chip

    Directory of Open Access Journals (Sweden)

    De-Hao Lu

    2010-11-01

    Full Text Available This study presents the design and fabrication of a capacitive micro humidity sensor integrated with a five-stage ring oscillator circuit on chip using the complimentary metal oxide semiconductor (CMOS process. The area of the humidity sensor chip is about 1 mm2. The humidity sensor consists of a sensing capacitor and a sensing film. The sensing capacitor is constructed from spiral interdigital electrodes that can enhance the sensitivity of the sensor. The sensing film of the sensor is polypyrrole, which is prepared by the chemical polymerization method, and the film has a porous structure. The sensor needs a post-CMOS process to coat the sensing film. The post-CMOS process uses a wet etching to etch the sacrificial layers, and then the polypyrrole is coated on the sensing capacitor. The sensor generates a change in capacitance when the sensing film absorbs or desorbs vapor. The ring oscillator circuit converts the capacitance variation of the sensor into the oscillation frequency output. Experimental results show that the sensitivity of the humidity sensor is about 99 kHz/%RH at 25 °C.

  20. Polypyrrole Porous Micro Humidity Sensor Integrated with a Ring Oscillator Circuit on Chip

    Science.gov (United States)

    Yang, Ming-Zhi; Dai, Ching-Liang; Lu, De-Hao

    2010-01-01

    This study presents the design and fabrication of a capacitive micro humidity sensor integrated with a five-stage ring oscillator circuit on chip using the complimentary metal oxide semiconductor (CMOS) process. The area of the humidity sensor chip is about 1 mm2. The humidity sensor consists of a sensing capacitor and a sensing film. The sensing capacitor is constructed from spiral interdigital electrodes that can enhance the sensitivity of the sensor. The sensing film of the sensor is polypyrrole, which is prepared by the chemical polymerization method, and the film has a porous structure. The sensor needs a post-CMOS process to coat the sensing film. The post-CMOS process uses a wet etching to etch the sacrificial layers, and then the polypyrrole is coated on the sensing capacitor. The sensor generates a change in capacitance when the sensing film absorbs or desorbs vapor. The ring oscillator circuit converts the capacitance variation of the sensor into the oscillation frequency output. Experimental results show that the sensitivity of the humidity sensor is about 99 kHz/%RH at 25 °C. PMID:22163459