WorldWideScience

Sample records for chip scale package

  1. Advanced flip chip packaging

    CERN Document Server

    Lai, Yi-Shao; Wong, CP

    2013-01-01

    Advanced Flip Chip Packaging presents past, present and future advances and trends in areas such as substrate technology, material development, and assembly processes. Flip chip packaging is now in widespread use in computing, communications, consumer and automotive electronics, and the demand for flip chip technology is continuing to grow in order to meet the need for products that offer better performance, are smaller, and are environmentally sustainable. This book also: Offers broad-ranging chapters with a focus on IC-package-system integration Provides viewpoints from leading industry executives and experts Details state-of-the-art achievements in process technologies and scientific research Presents a clear development history and touches on trends in the industry while also discussing up-to-date technology information Advanced Flip Chip Packaging is an ideal book for engineers, researchers, and graduate students interested in the field of flip chip packaging.

  2. Validation and reliability assessment of board level drop test of chip-scale-packaging

    Science.gov (United States)

    Hung, Tuan-Yu; Chou, Chan-Yen; Yew, Ming-Chih; Chiang, Kuo-Ning

    2008-11-01

    The main objective of this study is to develop a stress-buffer-improved package that is subjected to a board level drop test under a specific-G impact level. In this regard, both the drop test experiment and the ANSYS/LS-DYNA simulations are carried out. Several studies have shown that the solder joints having the brittle intermetallic compound (IMC) layers within the wafer level chip scale packaging (WLCSP) are the weakest part. For the most part, this is due to the large relative motion occurring between the board and the chip. In addition, the stress buffer layer exhibiting a relatively large elongation which reduces the impact on the solder balls. Meanwhile, the novel stress-buffer-improve package's failure mode is different from the convention WLCSP structure which shifts to the trace damage of the chip side. The leading concern between the solder ball and trace damage is the critical region where failure occurred owing to the stress concentration effect. During the drop test experiment, the proposed stress-buffer-improved package is able to survive over 100 drops (most packages survived at above 200 drops). Hence, this drop performance very much surpasses the Joint Electron Device Engineering Council (JEDEC) criterion (drop number is 30 times). Nevertheless, the metal traces which are embedded in the stress buffer layer suffered relatively larger deformation. Generally, the stress concentration occurs at a single position, much like the trace/pad connecting junction in the analysis of detailed stress-buffer-improved package. Finally, the predict result in finite element (FE) analysis is similar to the broken metal trace's failure analysis in the drop test experiment.

  3. Wafer-level chip-scale packaging analog and power semiconductor applications

    CERN Document Server

    Qu, Shichun

    2015-01-01

    This book presents a state-of-art and in-depth overview in analog and power WLCSP design, material characterization, reliability, and modeling. Recent advances in analog and power electronic WLCSP packaging are presented based on the development of analog technology and power device integration. The book covers in detail how advances in semiconductor content, analog and power advanced WLCSP design, assembly, materials, and reliability have co-enabled significant advances in fan-in and fan-out with redistributed layer (RDL) of analog and power device capability during recent years. Along with new analog and power WLCSP development, the role of modeling is a key to assure successful package design. An overview of the analog and power WLCSP modeling and typical thermal, electrical, and stress modeling methodologies is also provided. This book also: ·         Covers the development of wafer-level power discrete packaging with regular wafer-level design concepts and directly bumping technology ·    �...

  4. Self-adaptive phosphor coating technology for wafer-level scale chip packaging

    Institute of Scientific and Technical Information of China (English)

    Zhou Linsong; Rao Haibo; Wang Wei; Wan Xianlong; Liao Junyuan; Wang Xuemei; Zhou Da

    2013-01-01

    A new self-adaptive phosphor coating technology has been successfully developed,which adopted a slurry method combined with a self-exposure process.A phosphor suspension in the water-soluble photoresist was applied and exposed to LED blue light itself and developed to form a conformal phosphor coating with selfadaptability to the angular distribution of intensity of blue light and better-performing spatial color uniformity.The self-adaptive phosphor coating technology had been successfully adopted in the wafer surface to realize a waferlevel scale phosphor conformal coating.The first-stage experiments show satisfying results and give an adequate demonstration of the flexibility of self-adaptive coating technology on application of WLSCP.

  5. The extended Beer-Lambert theory for ray tracing modeling of LED chip-scaled packaging application with multiple luminescence materials

    Science.gov (United States)

    Yuan, Cadmus C. A.

    2015-12-01

    Optical ray tracing modeling applied Beer-Lambert method in the single luminescence material system to model the white light pattern from blue LED light source. This paper extends such algorithm to a mixed multiple luminescence material system by introducing the equivalent excitation and emission spectrum of individual luminescence materials. The quantum efficiency numbers of individual material and self-absorption of the multiple luminescence material system are considered as well. By this combination, researchers are able to model the luminescence characteristics of LED chip-scaled packaging (CSP), which provides simple process steps and the freedom of the luminescence material geometrical dimension. The method will be first validated by the experimental results. Afterward, a further parametric investigation has been then conducted.

  6. Microstructural Evolution of SAC305 Solder Joints in Wafer Level Chip-Scale Packaging (WLCSP) with Continuous and Interrupted Accelerated Thermal Cycling

    Science.gov (United States)

    Zhou, Quan; Zhou, Bite; Lee, Tae-Kyu; Bieler, Thomas

    2016-06-01

    Four high-strain design wafer level chip scale packages were given accelerated thermal cycling with a 10°C/min ramp rate and 10 min hold times between 0°C and 100°C to examine the effects of continuous and interrupted thermal cycling on the number of cycles to failure. The interruptions given two of the samples were the result of periodic examinations using electron backscattered pattern mapping, leading to room temperature aging of 30 days-2.5 years after increments of about 100 cycles at several stages of the cycling history. The continuous thermal cycling resulted in solder joints with a much larger degree of recrystallization, whereas the interrupted thermal cycling tests led to much less recrystallization, which was more localized near the package side, and the crack was more localized near the interface and had less branching. The failure mode for both conditions was still the same, with cracks nucleating along the high angle grain boundaries formed during recrystallization. In conditions where there were few recrystallized grains, recovery led to formation of subgrains that strengthened the solder, and the higher strength led to a larger driving force for crack growth through the solder, leading to failure after less than half of the cycles in the continuous accelerated thermal cycling condition. This work shows that there is a critical point where sufficient strain energy accumulation will trigger recrystallization, but this point depends on the rate of strain accumulation in each cycle and various recovery processes, which further depends on local crystal orientations, stress state evolution, and specific activated slip and twinning systems.

  7. Dry-film polymer waveguide for silicon photonics chip packaging.

    Science.gov (United States)

    Hsu, Hsiang-Han; Nakagawa, Shigeru

    2014-09-22

    Polymer waveguide made by dry film process is demonstrated for silicon photonics chip packaging. With 8 μm × 11.5 μm core waveguide, little penalty is observed up to 25 Gbps before or after the light propagate through a 10-km long single-mode fiber (SMF). Coupling loss to SMF is 0.24 dB and 1.31 dB at the polymer waveguide input and output ends, respectively. Alignment tolerance for 0.5 dB loss increase is +/- 1.0 μm along both vertical and horizontal directions for the coupling from the polymer waveguide to SMF. The dry-film polymer waveguide demonstrates promising performance for silicon photonics chip packaging used in next generation optical multi-chip module.

  8. Fully additive chip packaging: science or fiction?

    NARCIS (Netherlands)

    Oosterhuis, G.; Zon, C.M.B. van der; Maalderink, H.H.

    2011-01-01

    The current trend in IC packaging towards an ever increasing degree of integration, combined with a high level of production flexibility calls for novel approaches in manufacturing. To address these challenges in a flexible manufacturing setting, TNO investigated to what extend mask-less additive ma

  9. Identifying Professional Competencies of the Flip-Chip Packaging Engineer in Taiwan

    Science.gov (United States)

    Guu, Y. H.; Lin, Kuen-Yi; Lee, Lung-Sheng

    2014-01-01

    This study employed a literature review, expert interviews, and a questionnaire survey to construct a set of two-tier competencies for a flip-chip packaging engineer. The fuzzy Delphi questionnaire was sent to 12 flip-chip engineering experts to identify professional competencies that a flip-chip packaging engineer must have. Four competencies,…

  10. The Numerical Analysis of Strain Behavior at Solder Joint and Interface of Flip Chip Package

    Institute of Scientific and Technical Information of China (English)

    S; C; Chen; Y; C; Lin

    2002-01-01

    The flip chip package is a kind of advanced electri ca l packages. Due to the requirement of miniaturization, lower weight, higher dens ity and higher performance in the advanced electric package, it is expected that flip chip package will soon be a mainstream technology. The silicon chip is dir ectly connected to printing circuit substrate by SnPb solder joints. Also, the u nderfill, a composite of polymer and silica particles, is filled in the gap betw een the chip and substrate around the solder joint...

  11. 75 FR 447 - In the Matter of Certain Semiconductor Chips With Minimized Chip Package Size and Products...

    Science.gov (United States)

    2010-01-05

    ..., 2007. 73 FR 2276 (Jan. 14, 2008). The complaint alleged violations of section 337 of the Tariff Act of... it determined to review, and on remedy, the public interest and bonding. 74 FR 57192 (Nov. 4, 2009... COMMISSION In the Matter of Certain Semiconductor Chips With Minimized Chip Package Size and...

  12. Concurrent chip and package design for radio and mixed-signal systems

    OpenAIRE

    Shen, Meigen

    2005-01-01

    The advances in VLSI and packaging technologies enable us to integrate a whole system on a single chip (SoC) or on a package module. In these systems, analog/RF electronics, digital circuitries, and memories coexist. This new technology brings us new freedom for system integration as well as new challenges in system design and implementation. To fully utilize the benefits of these new hardware technologies, concurrent design of system, chip, and package is necessary. This research aims to exp...

  13. Flexible packaging of solid-state integrated circuit chips with elastomeric microfluidics

    OpenAIRE

    Bowei Zhang; Quan Dong; Korman, Can E.; Zhenyu Li; Zaghloul, Mona E.

    2013-01-01

    A flexible technology is proposed to integrate smart electronics and microfluidics all embedded in an elastomer package. The microfluidic channels are used to deliver both liquid samples and liquid metals to the integrated circuits (ICs). The liquid metals are used to realize electrical interconnects to the IC chip. This avoids the traditional IC packaging challenges, such as wire-bonding and flip-chip bonding, which are not compatible with current microfluidic technologies. As a demonstratio...

  14. Flexible packaging of solid-state integrated circuit chips with elastomeric microfluidics

    Science.gov (United States)

    Zhang, Bowei; Dong, Quan; Korman, Can E.; Li, Zhenyu; Zaghloul, Mona E.

    2013-01-01

    A flexible technology is proposed to integrate smart electronics and microfluidics all embedded in an elastomer package. The microfluidic channels are used to deliver both liquid samples and liquid metals to the integrated circuits (ICs). The liquid metals are used to realize electrical interconnects to the IC chip. This avoids the traditional IC packaging challenges, such as wire-bonding and flip-chip bonding, which are not compatible with current microfluidic technologies. As a demonstration we integrated a CMOS magnetic sensor chip and associate microfluidic channels on a polydimethylsiloxane (PDMS) substrate that allows precise delivery of small liquid samples to the sensor. Furthermore, the packaged system is fully functional under bending curvature radius of one centimetre and uniaxial strain of 15%. The flexible integration of solid-state ICs with microfluidics enables compact flexible electronic and lab-on-a-chip systems, which hold great potential for wearable health monitoring, point-of-care diagnostics and environmental sensing among many other applications.

  15. Storage stability of banana chips in polypropylene based nanocomposite packaging films

    OpenAIRE

    Manikantan, M. R.; Sharma, Rajiv; Kasturi, R.; Varadharaju, N.

    2012-01-01

    In this study, polypropylene (PP) based nanocomposite films of 15 different compositions of nanoclay, compatibilizer and thickness were developed and used for packaging and storage of banana chips. The effect of nanocomposite films on the quality characteristics viz. moisture content (MC), water activity (WA), total color difference(TCD), breaking force (BF), free fatty acid (FFA), peroxide value(PV), total plate count (TPC) and overall acceptability score of banana chips under ambient condit...

  16. New IC package, assembly technique by means of a "blind" alignment "flip-chip" method and assembling facilities

    Institute of Scientific and Technical Information of China (English)

    Vladimir V. Novikov

    2004-01-01

    @@ In spite of a long period of the development ofmicroelectronic components base, the problem of the creation of IC package design, providing minimal area losses in contrast with area of a chip, remains unsolved [1]Area losses can be described by the parameter P,which is equal to the ratio between the package area in plan and the chip area:

  17. The IronChip evaluation package: a package of perl modules for robust analysis of custom microarrays

    Directory of Open Access Journals (Sweden)

    Brazma Alvis

    2010-03-01

    Full Text Available Abstract Background Gene expression studies greatly contribute to our understanding of complex relationships in gene regulatory networks. However, the complexity of array design, production and manipulations are limiting factors, affecting data quality. The use of customized DNA microarrays improves overall data quality in many situations, however, only if for these specifically designed microarrays analysis tools are available. Results The IronChip Evaluation Package (ICEP is a collection of Perl utilities and an easy to use data evaluation pipeline for the analysis of microarray data with a focus on data quality of custom-designed microarrays. The package has been developed for the statistical and bioinformatical analysis of the custom cDNA microarray IronChip but can be easily adapted for other cDNA or oligonucleotide-based designed microarray platforms. ICEP uses decision tree-based algorithms to assign quality flags and performs robust analysis based on chip design properties regarding multiple repetitions, ratio cut-off, background and negative controls. Conclusions ICEP is a stand-alone Windows application to obtain optimal data quality from custom-designed microarrays and is freely available here (see "Additional Files" section and at: http://www.alice-dsl.net/evgeniy.vainshtein/ICEP/

  18. Method of Images for the Fast Calculation of Temperature Distributions in Packaged VLSI Chips

    CERN Document Server

    Hériz, Virginia Martín; Kemper, T; Kang, S -M; Shakouri, A

    2008-01-01

    Thermal aware routing and placement algorithms are important in industry. Currently, there are reasonably fast Green's function based algorithms that calculate the temperature distribution in a chip made from a stack of different materials. However, the layers are all assumed to have the same size, thus neglecting the important fact that the thermal mounts which are placed underneath the chip can be significantly larger than the chip itself. In an earlier publication, we showed that the image blurring technique can be used to calculate quickly temperature distribution in realistic packages. For this method to be effective, temperature distribution for several point heat sources at the center and at the corner and edges of the chip should be calculated using finite element analysis (FEA) or measured. In addition, more accurate results require correction by a weighting function that will need several FEA simulations. In this paper, we introduce the method of images that take the symmetry of the thermal boundary...

  19. Sub-Kelvin single flux quantum control circuits and multi-chip packaging for supporting superconducting qubit

    International Nuclear Information System (INIS)

    Superconducting single flux quantum (SFQ) circuit can operate at very low temperature. This is suitable for controlling a quantum computing system with Josephson junctions. However, it is difficult to integrate both SFQ circuits and qubits into a single-chip, because of the dissipative characteristics of SFQ circuits. Therefore, we have developed a multi-chip packaging technology for a qubit control module. The module consists of SFQ circuit chips, qubit chips, and a substrate all of which are fabricated with Nb and Al technology. The chips are flip-chip bonded with superconducting solder bumps. We also investigated SFQ control circuits for superconducting qubits and circuit parameter optimization for sub-Kelvin temperature operation. Using both multi-chip packaging and optimized SFQ control circuit makes the design of qubit control module more flexible

  20. Compact Shorted Stacked-Patch Antenna Integrated with Chip-Package Based on LTCC Technology

    Directory of Open Access Journals (Sweden)

    Yongjiu Li

    2014-01-01

    Full Text Available A low profile chip-package stacked-patch antenna is proposed by using low temperature cofired ceramic (LTCC technology. The proposed antenna employs a stacked-patch to achieve two operating frequency bands and enhance the bandwidth. The height of the antenna is decreased to 4.09 mm (about λ/25 at 2.45 GHz due to the shorted pin. The package is mounted on a 44 × 44 mm2 ground plane to miniaturize the volume of the system. The design parameters of the antenna and the effect of the antenna on chip-package cavity are carefully analyzed. The designed antenna operates at a center frequency of 2.45 GHz and its impedance bandwidth (S11< -10 dB is 200 MHz, resulting from two neighboring resonant frequencies at 2.41 and 2.51 GHz, respectively. The average gain across the frequency band is about 5.28 dBi.

  1. BGX: a Bioconductor package for the Bayesian integrated analysis of Affymetrix GeneChips

    Directory of Open Access Journals (Sweden)

    Hein Anne-Mette K

    2007-11-01

    Full Text Available Abstract Background Affymetrix 3' GeneChip microarrays are widely used to profile the expression of thousands of genes simultaneously. They differ from many other microarray types in that GeneChips are hybridised using a single labelled extract and because they contain multiple 'match' and 'mismatch' sequences for each transcript. Most algorithms extract the signal from GeneChip experiments in a sequence of separate steps, including background correction and normalisation, which inhibits the simultaneous use of all available information. They principally provide a point estimate of gene expression and, in contrast to BGX, do not fully integrate the uncertainty arising from potentially heterogeneous responses of the probes. Results BGX is a new Bioconductor R package that implements an integrated Bayesian approach to the analysis of 3' GeneChip data. The software takes into account additive and multiplicative error, non-specific hybridisation and replicate summarisation in the spirit of the model outlined in 1. It also provides a posterior distribution for the expression of each gene. Moreover, BGX can take into account probe affinity effects from probe sequence information where available. The package employs a novel adaptive Markov chain Monte Carlo (MCMC algorithm that raises considerably the efficiency with which the posterior distributions are sampled from. Finally, BGX incorporates various ways to analyse the results, such as ranking genes by expression level as well as statistically based methods for estimating the amount of up and down regulated genes between two conditions. Conclusion BGX performs well relative to other widely used methods at estimating expression levels and fold changes. It has the advantage that it provides a statistically sound measure of uncertainty for its estimates. BGX includes various analysis functions to visualise and exploit the rich output that is produced by the Bayesian model.

  2. Microelectronic packaging

    CERN Document Server

    Datta, M; Schultze, J Walter

    2004-01-01

    Microelectronic Packaging analyzes the massive impact of electrochemical technologies on various levels of microelectronic packaging. Traditionally, interconnections within a chip were considered outside the realm of packaging technologies, but this book emphasizes the importance of chip wiring as a key aspect of microelectronic packaging, and focuses on electrochemical processing as an enabler of advanced chip metallization.Divided into five parts, the book begins by outlining the basics of electrochemical processing, defining the microelectronic packaging hierarchy, and emphasizing the impac

  3. External efficiency and thermal reliability enhanced multi-chip package design for light emitting diodes

    Science.gov (United States)

    Tang, Meng-Han; Wu, Tsung-Han; Su, Guo-Dung J.

    2008-08-01

    With the power of light emitting diodes (LEDs) getting higher and higher, the issue of thermal management is getting much more important. In this paper, we discussed a new idea to get white light without using traditional phosphor and to enhance its extraction efficiency. Microlens is used for increasing external efficiency and shaping light pattern. The location of micro-lens is designed carefully by considering cup reflection. We also revealed that it is important to consider the angle of exit light from LEDs. The result shows our design is suitable for high color rendering index (CRI) application. At the same time, the uniform white light is approached as the light has been strongly diffused. Furthermore, we try to decrease the junction temperature as low as possible so as to increase stability and lifetime of LEDs. In order to maintain color mixing and dissipate heat, multi-chip or four pairs of electrodes which are electroplated with copper after bulk micromachining process within a silicon-based package are used. This novel packaging technique needs just a few processing steps and could be mass produced for nowadays high brightness light emitting diodes (HBLEDs).

  4. Crossmodal correspondences in product packaging. Assessing color-flavor correspondences for potato chips (crisps).

    Science.gov (United States)

    Piqueras-Fiszman, Betina; Spence, Charles

    2011-12-01

    We report a study designed to investigate consumers' crossmodal associations between the color of packaging and flavor varieties in crisps (potato chips). This product category was chosen because of the long-established but conflicting color-flavor conventions that exist for the salt and vinegar and cheese and onion flavor varieties in the UK. The use of both implicit and explicit measures of this crossmodal association revealed that consumers responded more slowly, and made more errors, when they had to pair the color and flavor that they implicitly thought of as being "incongruent" with the same response key. Furthermore, clustering consumers by the brand that they normally purchased revealed that the main reason why this pattern of results was observed could be their differing acquaintance with one brand versus another. In addition, when participants tried the two types of crisps from "congruently" and "incongruently" colored packets, some were unable to guess the flavor correctly in the latter case. These strong crossmodal associations did not have a significant effect on participants' hedonic appraisal of the crisps, but did arouse confusion. These results are relevant in terms of R&D, since ascertaining the appropriate color of the packaging across flavor varieties ought normally to help achieve immediate product recognition and consumer satisfaction. PMID:21824502

  5. New Polymer Materials for Microelectronics Packaging

    Institute of Scientific and Technical Information of China (English)

    2005-01-01

    @@ Researchers at the CAS Institute of Chemistry (ICCAS) have made breakthrough progress in developing the manufacturing technology of advanced polymer materials for microelectronics packaging applications. The advanced integrated circuit (IC) packaging polymer materials, including photoimageable polyimide resins and liquid epoxy underfills, are a key issue for FC-BGA/CSP(flip chip-ball grill array/chip scale packaging) which is the main stream for the next generation of microelectronics devices. With the down-sizing, thinning and high I/O (input/output) of IC chips, microelectronics packaging is now facing a big technology challenge.

  6. Packaging a free-space intra-chip optical interconnect module: Monte Carlo tolerance study and assembly results

    Science.gov (United States)

    Vervaeke, Michael; Lahti, Markku; Karpinnen, Mikko; Debaes, Christof; Volckaerts, Bart; Karioja, Pentti; Thienpont, Hugo

    2006-04-01

    In this paper we give an overview of the fabrication and assembly induced performance degradation of an intra-multi-chip-module free-space optical interconnect, integrating micro-lenses and a deflection prism above a dense opto-electronic chip. The proposed component is used to demonstrate the capabilities of an accurate micro-optical rapid prototype technique, namely the Deep Proton Writing (DPW). To evaluate the accuracy of DPW and to assess whether our assembly scheme will provide us with a reasonable process yield, we have built a simulation framework combining mechanical Monte Carlo analysis with optical simulations. Both the technological requirements to ensure a high process yield, and the specifications of our in-house DPW technology are discussed. Therefore, we first conduct a sensitivity analysis and we subsequently simulate the effect of combined errors using a Monte Carlo simulation. We are able to investigate the effect of a technology accuracy enhancement on the fabrication and assembly yield by scaling the standard deviation of the errors proportionally to each sensitivity interval. We estimate that 40% of the systems fabricated with DPW will show an optical transmission efficiency above -4.32 dB, which is -3 dB below the theoretical obtainable value. We also discuss our efforts to implement an opto-mechanical Monte Carlo simulator. It enables us to address specific issues not directly related with the micro-optical or DPW components, such as the influence of glueing layers and structures that allow for self-alignment, by combining mechanical tolerancing algorithms with optical simulation software. More in particular we determined that DPW provides ample accuracy to meet the requirements to obtain a high manufacturing yield. Finally, we shortly highlight the basic layout of a completed demonstrator. The adhesive bonding of opto-electronic devices in their package is subject to further improvement to enhance the tilt accuracy of the devices with

  7. Development of Equivalent Material Properties of Microbump for Simulating Chip Stacking Packaging

    Directory of Open Access Journals (Sweden)

    Chang-Chun Lee

    2015-08-01

    Full Text Available three-dimensional integrated circuit (3D-IC structure with a significant scale mismatch causes difficulty in analytic model construction. This paper proposes a simulation technique to introduce an equivalent material composed of microbumps and their surrounding wafer level underfill (WLUF. The mechanical properties of this equivalent material, including Young’s modulus (E, Poisson’s ratio, shear modulus, and coefficient of thermal expansion (CTE, are directly obtained by applying either a tensile load or a constant displacement, and by increasing the temperature during simulations, respectively. Analytic results indicate that at least eight microbumps at the outermost region of the chip stacking structure need to be considered as an accurate stress/strain contour in the concerned region. In addition, a factorial experimental design with analysis of variance is proposed to optimize chip stacking structure reliability with four factors: chip thickness, substrate thickness, CTE, and E-value. Analytic results show that the most significant factor is CTE of WLUF. This factor affects microbump reliability and structural warpage under a temperature cycling load and high-temperature bonding process. WLUF with low CTE and high E-value are recommended to enhance the assembly reliability of the 3D-IC architecture.

  8. Active Solar Sail Designs for Chip-Scale Spacecraft

    OpenAIRE

    Weis, Lorraine; Peck, Mason

    2014-01-01

    Centimeter-scale spacecraft, known as ”Chipsats,” have very high surface-area-to-mass ratios, which accentuates solar radiation pressure (SRP) effects. In contrast to traditional. large solar sails, chip-scale solar sails have the potential to be highly agile in terms of attitude because of their structural rigidity and low moments of inertia. This ability to easily reorient a solar sail greatly expands the orbits that a solar-sail spacecraft can achieve. Solar sail actuation through electroc...

  9. Semiconductor Yield Analysis and Multi-Chip Package (MCP) Die Pairing Optimization using Machine Learning

    Institute of Scientific and Technical Information of China (English)

    Randall Goodwin; Russell Miller; Eugene Tuv; Alexander Borisov

    2006-01-01

    Machine Learning, Artificial Intelligence (AI) and Statistical Learning are related mathematical fields which utilize computer algorithms to create models for the purposes of data description and/or prediction. Some well known examples include biometric identification and authorization systems, speech recognition and user targeted internet advertising. Statistical Learning, which we will use in this paper, also has many applications in semiconductor manufacturing.Some of the challenging characteristics of semiconductor data include high dimensionality, mixtures of categorical and numeric data, non-randomly missing data, non-Gaussian and multimodal distributions, nonlinear complex relationships, noise, outliers and temporal dependencies. These challenges are becoming particularly acute as the quantity of available data increases and the ability to trace lots, wafers, die, and packages throughout the full fab, wafer test, assembly and final test manufacturing flow improves. Statistical-learning techniques are applied to address these challenges. In this paper we discuss the advancement and applications of Tree based classification and regression methods to semiconductor data. We begin the paper with a description of the problem, followed by and overview of the statistical-learning techniques we use in our case studies. We then describe how the challenges presented by semiconductor data were addressed with original extensions to tree-based and kernel-based methods. Next, we review four case studies: home sales price prediction, signal identification/separation, final speed bin classification and die pairing optimization for Multi-Chip Packages (MCP). Results from the case studies demonstrate how statistical-learning addresses the challenges presented by semiconductor manufacturing data and enables improved data discovery and prediction when compared to traditional statistical approaches.

  10. Chip-scale cavity optomechanics in lithium niobate

    OpenAIRE

    Jiang, Wei C.; LIN, QIANG

    2016-01-01

    We develop a chip-scale cavity optomechanical system in single-crystal lithium niobate that exhibits high optical quality factors and a large frequency-quality product as high as $3.6\\times 10^{12}$ Hz at room temperature and atmosphere. The excellent optical and mechanical properties together with the strong optomechanical coupling allow us to efficiently excite the coherent regenerative optomechanical oscillation operating at 375.8 MHz with a threshold power of 174 ${\\rm \\mu W}$ in the air....

  11. Chip-scale cavity optomechanics in lithium niobate

    CERN Document Server

    Jiang, Wei C

    2016-01-01

    We develop a chip-scale cavity optomechanical system in single-crystal lithium niobate that exhibits high optical quality factors and a large frequency-quality product as high as $3.6\\times 10^{12}$ Hz at room temperature and atmosphere. The excellent optical and mechanical properties together with the strong optomechanical coupling allow us to efficiently excite the coherent regenerative optomechanical oscillation operating at 375.8 MHz with a threshold power of 174 ${\\rm \\mu W}$ in the air. The demonstrated lithium niobate optomechanical device enables great potential for achieving electro-optic-mechanical hybrid systems for broad applications in sensing, metrology, and quantum physics.

  12. 75 FR 51843 - In the Matter of Certain Large Scale Integrated Circuit Semiconductor Chips and Products...

    Science.gov (United States)

    2010-08-23

    ..., based on a complaint filed by Panasonic Corporation (``Panasonic'') of Japan. 75 FR 24742-43. The... COMMISSION In the Matter of Certain Large Scale Integrated Circuit Semiconductor Chips and Products... importation of certain large scale integrated circuit semiconductor chips and products containing same...

  13. FlexiChip package: an universal microarray with a dedicated analysis software for high-thoughput SNPs detection linked to anti-malarial drug resistance

    Directory of Open Access Journals (Sweden)

    Dondorp Arjen M

    2009-10-01

    Full Text Available Abstract Background A number of molecular tools have been developed to monitor the emergence and spread of anti-malarial drug resistance to Plasmodium falciparum. One of the major obstacles to the wider implementation of these tools is the absence of practical methods enabling high throughput analysis. Here a new Zip-code array is described, called FlexiChip, linked to a dedicated software program, which largely overcomes this problem. Methods Previously published microarray probes detecting single-nucleotide polymorphisms (SNP associated with parasite resistance to anti-malarial drugs (ResMalChip were adapted for a universal microarray FlexiChip format. To evaluate the overall sensitivity of the FlexiChip package (microarray + software, the results of FlexiChip were compared to ResMalChip microarray, using the same extension probes and with the same PCR products. In both cases, sequence results were used as gold standard to calculate sensitivity and specificity. FlexiChip results obtained with a set of field isolates were then compared to those assessed in an independent reference laboratory. Results The FlexiChip package gave results identical to the ResMalChip results in 92.7% of samples (kappa coefficient 0.8491, with a standard error 0.021 and had a sensitivity of 95.88% and a specificity of 97.68% compared to the sequencing as the reference method. Moreover the method performed well compared to the results obtained in the reference laboratories, with 99.7% of identical results (kappa coefficient 0.9923, S.E. 0.0523. Conclusion Microarrays could be employed to monitor P. falciparum drug resistance markers with greater cost effectiveness and the possibility for high throughput analysis. The FlexiChip package is a promising tool for use in poor resource settings of malaria endemic countries.

  14. Co-Design Method and Wafer-Level Packaging Technique of Thin-Film Flexible Antenna and Silicon CMOS Rectifier Chips for Wireless-Powered Neural Interface Systems.

    Science.gov (United States)

    Okabe, Kenji; Jeewan, Horagodage Prabhath; Yamagiwa, Shota; Kawano, Takeshi; Ishida, Makoto; Akita, Ippei

    2015-01-01

    In this paper, a co-design method and a wafer-level packaging technique of a flexible antenna and a CMOS rectifier chip for use in a small-sized implantable system on the brain surface are proposed. The proposed co-design method optimizes the system architecture, and can help avoid the use of external matching components, resulting in the realization of a small-size system. In addition, the technique employed to assemble a silicon large-scale integration (LSI) chip on the very thin parylene film (5 μm) enables the integration of the rectifier circuits and the flexible antenna (rectenna). In the demonstration of wireless power transmission (WPT), the fabricated flexible rectenna achieved a maximum efficiency of 0.497% with a distance of 3 cm between antennas. In addition, WPT with radio waves allows a misalignment of 185% against antenna size, implying that the misalignment has a less effect on the WPT characteristics compared with electromagnetic induction. PMID:26694407

  15. Co-Design Method and Wafer-Level Packaging Technique of Thin-Film Flexible Antenna and Silicon CMOS Rectifier Chips for Wireless-Powered Neural Interface Systems

    Directory of Open Access Journals (Sweden)

    Kenji Okabe

    2015-12-01

    Full Text Available In this paper, a co-design method and a wafer-level packaging technique of a flexible antenna and a CMOS rectifier chip for use in a small-sized implantable system on the brain surface are proposed. The proposed co-design method optimizes the system architecture, and can help avoid the use of external matching components, resulting in the realization of a small-size system. In addition, the technique employed to assemble a silicon large-scale integration (LSI chip on the very thin parylene film (5 μm enables the integration of the rectifier circuits and the flexible antenna (rectenna. In the demonstration of wireless power transmission (WPT, the fabricated flexible rectenna achieved a maximum efficiency of 0.497% with a distance of 3 cm between antennas. In addition, WPT with radio waves allows a misalignment of 185% against antenna size, implying that the misalignment has a less effect on the WPT characteristics compared with electromagnetic induction.

  16. Reliability of an ultra-fine-pitch COF flip-chip package using non-conductive paste

    Science.gov (United States)

    Kim, Hae-Yeon; Min, Kyung-Eun; Lee, Jun-Sik; Lee, So-Jeong; Lee, Sung-Soo; Kim, Jun-Ki

    2016-01-01

    Ultra-fine-pitch chip-on-film (COF) packages such as display-drive-integrated circuit (DDI) modules are manufactured through an underfill process following Au-to-Sn thermo-compression bonding. As the interconnection pitch becomes finer and is reduced to less than 25 um, however, an alternative flip-chip technology, such as non-conductive paste (NCP) bonding, is needed in place of the capillary underfill process. In this study, new NCP formulations are investigated to achieve rapid curing at a temperature high enough to form a metallic bond between the bump and the pad. An appropriate curing agent was determined through a dielectric analysis (DEA). COF samples were prepared with a DDI chip 11,772 × 924 um in size and with a 38 um-thick polyimide flexible printed circuit by both NCP bonding and thermo-compressionunderfill processes. Pressure cooker tests lasting as long as 192 h revealed that the reliability of the NCP sample against high temperatures and high humidity levels exceeded somewhat that of the underfill sample. In thermal cycling test up to 500 cycles, however, the reliability of the NCP sample was inferior to that of the underfill sample. It was considered that unbonded faults and NCP trapping at the bump-to-pad joint were responsible for the premature failure of the NCP sample under a thermal cycling condition. [Figure not available: see fulltext.

  17. Exploring massive, genome scale datasets with the genometricorr package

    KAUST Repository

    Favorov, Alexander

    2012-05-31

    We have created a statistically grounded tool for determining the correlation of genomewide data with other datasets or known biological features, intended to guide biological exploration of high-dimensional datasets, rather than providing immediate answers. The software enables several biologically motivated approaches to these data and here we describe the rationale and implementation for each approach. Our models and statistics are implemented in an R package that efficiently calculates the spatial correlation between two sets of genomic intervals (data and/or annotated features), for use as a metric of functional interaction. The software handles any type of pointwise or interval data and instead of running analyses with predefined metrics, it computes the significance and direction of several types of spatial association; this is intended to suggest potentially relevant relationships between the datasets. Availability and implementation: The package, GenometriCorr, can be freely downloaded at http://genometricorr.sourceforge.net/. Installation guidelines and examples are available from the sourceforge repository. The package is pending submission to Bioconductor. © 2012 Favorov et al.

  18. The Investigation of Die Back Edge Cracking in Flip Chip Ceramic Ball Grid Array Package (FC-CBGA

    Directory of Open Access Journals (Sweden)

    Zainudin Kornain

    2011-09-01

    Full Text Available The cracking between die back edge and top fillet for Flip Chip Ceramic Ball Grid Array (FC-CBGA package due to thermal cycling have been investigated in this study. Finite Element Analysis (FEA model was used to analyze the effect of fillet geometry and material properties of underfill upon stresses along the die back edge. The thermo-mechanical properties of commercial underfill were obtained by using Thermal Mechanical Analyzer (TMA and Dynamic Mechanical Analyzer (DMA as the input for the simulation. Die stress distribution for different fillet height and width were generated to depict variation of stress due thermal loading and the variations of tensile stress were discussed for parameter optimization. The effect of different underfill material properties were discussed as well for thermal stress reliability improvement.

  19. Scale-up considerations relevant to experimental studies of nuclear waste-package behavior

    International Nuclear Information System (INIS)

    Results from a study that investigated whether testing large-scale nuclear waste-package assemblages was technically warranted are reported. It was recognized that the majority of the investigations for predicting waste-package performance to date have relied primarily on laboratory-scale experimentation. However, methods for the successful extrapolation of the results from such experiments, both geometrically and over time, to actual repository conditions have not been well defined. Because a well-developed scaling technology exists in the chemical-engineering discipline, it was presupposed that much of this technology could be applicable to the prediction of waste-package performance. A review of existing literature documented numerous examples where a consideration of scaling technology was important. It was concluded that much of the existing scale-up technology is applicable to the prediction of waste-package performance for both size and time extrapolations and that conducting scale-up studies may be technically merited. However, the applicability for investigating the complex chemical interactions needs further development. It was recognized that the complexity of the system, and the long time periods involved, renders a completely theoretical approach to performance prediction almost hopeless. However, a theoretical and experimental study was defined for investigating heat and fluid flow. It was concluded that conducting scale-up modeling and experimentation for waste-package performance predictions is possible using existing technology. A sequential series of scaling studies, both theoretical and experimental, will be required to formulate size and time extrapolations of waste-package performance

  20. Scale-up considerations relevant to experimental studies of nuclear waste-package behavior

    Energy Technology Data Exchange (ETDEWEB)

    Coles, D.G.; Peters, R.D.

    1986-04-01

    Results from a study that investigated whether testing large-scale nuclear waste-package assemblages was technically warranted are reported. It was recognized that the majority of the investigations for predicting waste-package performance to date have relied primarily on laboratory-scale experimentation. However, methods for the successful extrapolation of the results from such experiments, both geometrically and over time, to actual repository conditions have not been well defined. Because a well-developed scaling technology exists in the chemical-engineering discipline, it was presupposed that much of this technology could be applicable to the prediction of waste-package performance. A review of existing literature documented numerous examples where a consideration of scaling technology was important. It was concluded that much of the existing scale-up technology is applicable to the prediction of waste-package performance for both size and time extrapolations and that conducting scale-up studies may be technically merited. However, the applicability for investigating the complex chemical interactions needs further development. It was recognized that the complexity of the system, and the long time periods involved, renders a completely theoretical approach to performance prediction almost hopeless. However, a theoretical and experimental study was defined for investigating heat and fluid flow. It was concluded that conducting scale-up modeling and experimentation for waste-package performance predictions is possible using existing technology. A sequential series of scaling studies, both theoretical and experimental, will be required to formulate size and time extrapolations of waste-package performance.

  1. Simulation and analysis of effects of Young's modulus of isolation material on natural frequencies of the sensor package and displacement of the chip

    Institute of Scientific and Technical Information of China (English)

    YIN Jing-hua; LV Guang-jun; LIU Xiao-wei; LEI Qing-quan

    2005-01-01

    For the first time an anti-shock packaging model of an acoustic-vibration sensor system has been designed by using the shocking isolation principle. The finite element analysis has been applied for design and simulation of the model. The effects of Young's modulus of anti-shock rubber on naturally occurring frequencies of the combination of rubber and an acoustic sensor chip were analyzed. The displacement of the acoustic sensor chip is loaded with force. The results of static analysis and harmonic analysis show that while increasing Young's modulus of anti-chock rubber, the first five natural frequencies of the package body also increases. Yet the displacement of the acoustic sensor chip around the resonant frequency decreases. The results of static and transient analysis show that the displacement of the acoustic sensor chip decreases with the increase of Young's modulus of anti-chock rubber being loaded with either transient force or static force at the bottom of the combination of rubber and acoustic sensor chip.

  2. Insight into economies of scale for waste packaging sorting plants

    DEFF Research Database (Denmark)

    Cimpan, Ciprian; Wenzel, Henrik; Maul, Anja;

    2015-01-01

    of economies of scale and discussed complementary relations occurring between capacity size, technology level and operational practice. Processing costs (capital and operational expenditure) per unit waste input were found to decrease from above 100 € for small plants with a basic technology level to 60...

  3. Micron-Scale Differential Scanning Calorimeter on a Chip

    Science.gov (United States)

    Cavicchi, Richard E; Poirier, Gregory Ernest; Suehle, John S; Gaitan, Michael; Tea, Nim H

    1998-06-30

    A differential scanning microcalorimeter produced on a silicon chip enables microscopic scanning calorimetry measurements of small samples and thin films. The chip may be fabricated using standard CMOS processes. The microcalorimeter includes a reference zone and a sample zone. The reference and sample zones may be at opposite ends of a suspended platform or may reside on separate platforms. An integrated polysilicon heater provides heat to each zone. A thermopile consisting of a succession of thermocouple junctions generates a voltage representing the temperature difference between the reference and sample zones. Temperature differences between the zones provide information about the chemical reactions and phase transitions that occur in a sample placed in the sample zone.

  4. MEMS Direct Chip Attach Packaging Methodologies and Apparatuses for Harsh Environments

    Science.gov (United States)

    Okojie, Robert S. (Inventor)

    2009-01-01

    Methods of bulk manufacturing high temperature sensor subassembly packages are disclosed and claimed. Sensors are sandwiched between a top cover and a bottom cover so as to enable the peripheries of the top covers, sensors and bottom covers to be sealed and bound securely together are disclosed and claimed. Sensors are placed on the bottom covers leaving the periphery of the bottom cover exposed. Likewise, top covers are placed on the sensors leaving the periphery of the sensor exposed. Individual sensor sub-assemblies are inserted into final packaging elements which are also disclosed and claimed. Methods of directly attaching wires or pins to contact pads on the sensors are disclosed and claimed. Sensors, such as pressure sensors and accelerometers, and headers made out of silicon carbide and aluminum nitride are disclosed and claimed. Reference cavities are formed in some embodiments disclosed and claimed herein where top covers are not employed.

  5. 罐装薯片包装的生命周期评价%LCA of Canned Potato Chip Packaging

    Institute of Scientific and Technical Information of China (English)

    谢勇; 王凯丽; 谭海湖

    2015-01-01

    The life cycle assessment(LCA) of canned potato chip packaging was conducted covering the phases of acquisition and processing of raw materials, transportation from manufactures to consumers, use of packaging containers, recycling and waste disposal etc., with the energy consumption and environmental impact also being evaluated. The conclu-sion showed: environmental impact of the composite packaging is mainly in the material acquisition phase, i.e. the fuel consumption. The environmental impact of paper processing is much greater than those of plastic and aluminum. The impact of three disposal methods of landfill, incineration and recycling were focused on fossil fuel consumption, land occupation and inorganic substances damage to human body. Therefore, material reduction and container lightweight are the most direct and effective ways to improving packaging environmental adaptability while maintaining the existing structure.%对罐装薯片包装进行了生命周期评价,包括从原材料的获取、生产加工,工厂、消费者的运输,到包装容器的使用、二次回收使用,废弃物处理等包装的生命周期环节,对其能量消耗、环境影响等进行了评价.分析结果表明:纸铝塑复合包装的环境负荷主要体现在原材料的获取阶段,集中在燃料能源的消耗,其中纸材料加工的环境负荷要大于塑料与铝;填埋、焚烧、再利用这3种处置方式对环境的影响主要集中在化石燃料的消耗、土地占用和无机物对人体的损害上.因此,在维持现有结构的情况下,实行材料减量化和容器轻量化是提高包装环保适性最直接、有效的途径.

  6. Photonic-crystal lasers on silicon for chip-scale optical interconnects

    Science.gov (United States)

    Takeda, Koji; Fujii, Takuro; Shinya, Akihiko; Kuramochi, Eiichi; Notomi, Masaya; Hasebe, Koichi; Kakitsuka, Takaaki; Matsuo, Shinji

    2016-03-01

    Optical interconnects are expected to reduce the power consumption of ICT instruments. To realize chip-to-chip or chip-scale optical interconnects, it is essential to fabricate semiconductor lasers with a smaller energy cost. In this context, we are developing lambda-scale embedded active-region photonic-crystal (LEAP) lasers as light sources for chip-scale optical interconnects. We demonstrated the first continuous-wave (CW) operation of LEAP lasers in 2012 and reported a record low threshold current and energy cost of 4.8 μA and 4.4 fJ/bit at 10 Gbit/s in 2013. We have also integrated photonic crystal photodetectors on the same InP chip and demonstrated waveform transfer along 500-μm-long waveguides. Although LEAP lasers exhibit excellent performance, they have to be integrated on Si wafers for use as light sources for chip-scale optical interconnects. In this paper, we give a brief overview of our LEAP lasers on InP and report our recent progress in fabricating them on Si. We bonded the InP wafers with quantum-well gain layers directly on thermally oxidized Si wafers and performed all process steps on the Si wafer, including high-temperature regrowth. After this process modification, we again achieved CW operation and obtained a threshold current of 57 μA with a maximum output power of more than 3.5 μW at the output waveguides. An output light was successfully guided through 500 × 250-nm InP waveguides.

  7. Photonic packaging sourcebook fiber-chip coupling for optical components, basic calculations, modules

    CERN Document Server

    Fischer-Hirchert, Ulrich H P

    2015-01-01

    This book serves as a guide on photonic assembly techniques. It provides an overview of today's state-of-the-art technologies for photonic packaging experts and professionals in the field. The text guides the readers to the practical use of optical connectors. It also assists engineers to find a way to an effective and inexpensive set-up for their own needs. In addition, many types of current industrial modules and state-of-the-art applications from single fiber to multi fiber are described in detail. Simulation techniques such as FEM, BPM and ray tracing are explained in depth. Finally, all recent reliability test procedures for datacom and telecom modules are illustrated in combination with related standardization aspects.

  8. Ultrasonic power features of wire bonding and thermosonic flip chip bonding in microelectronics packaging

    Institute of Scientific and Technical Information of China (English)

    LI Jun-hui; HAN Lei; ZHONG Jue

    2008-01-01

    The driving voltage and current signals of piezoeeramie transducer (PZT) were measured directly by designing circuits from ultrasonic generator and using a data acquisition software system. The input impedance and power of PZT were investigated by using root mean square (RMS) calculation. The vibration driven by high frequency was tested by laser Doppler vibrometer (PSV-400-M2). And the thermosonic bonding features were observed by scanning electron microscope (JSM-6360LV). The results show that the input power of bonding is lower than that of no load. The input impedance of bonding is greater than that of no load.Nonlinear phase, plastic flow and expansion period, and strengthening bonding process are shown in the impedance and power curves. The ultrasonic power is in direct proportion to the vibration displacement driven by the power, and greater displacements driven by high power (5W) result in welding failure phenomena, such as crack, break, and peeling off in wedge bonding. For thermosonic flip chip bonding, the high power decreases position precision of bonding or results in slippage and rotation phenomena of bumps. To improve reliability and precision of thermosonic bonding, the low ultrasonic power (about 1-5W) should be chosen.

  9. Leadless chip carrier packaging and cad/cam-supported wire wrap interconnect technology for subnanosecond ecl. Interim report 1 jul 80-30 jun 81

    Energy Technology Data Exchange (ETDEWEB)

    Gilbert, B.K.

    1981-11-01

    This report describes the results of work conducted to develop rapid methods for designing and prototyping high-speed digital processor systems using subnanosecond emitter coupled logic (ECL). In Task I, we have begun a conversion of the design rules, interconnection protocols, special components, and standard logic panels developed during the first year for high-speed ECL-based digital processors from a technology based upon dual-in-line packages (DIP) to a technology based upon specially designed leadless ceramic chip carriers. This conversion was undertaken since it was learned during the first year that the DIP packages themselves are compromising the maximum performance levels of which the ECL dice are capable. We have also undertaken an extensive investigation of several possible approaches to increasing these operational maxima to an even greater extent than with our present design for new Leadless Ceramic Chip Carriers. Task 2 was to continue development of a comprehensive computer-aided design/computer-aided manufacturing (CAD/CAM) software package which would be specifically tailored to support the peculiar design requirements of processors operating in a high clock rate, transmission line environment. The CAD/CAM software package has been structured to be sufficiently flexible to assimilate advances in device and component technology, and to accept new sets of design rules resulting from advances in engineering design practice.

  10. Preliminary evaluation of waste package releases using drift-scale thermo-hydrologic analyses

    International Nuclear Information System (INIS)

    In a 1993 performance assessment, the uncertainty associated with using panel-scale thermo-hydrologic analyses to define the near-field environment in the vicinity of the waste packages was identified as one of the major factors impacting the predicted performance. This was because of the impact of the thermo-hydrologic regime on the initiation of aqueous corrosion as well as the rate of corrosion, rate of waste form dissolution (due to the uncertainty in the percent of the waste form surface covered by water film), solubility limits, and the effective diffusion through the waste package and engineered barrier. This document presents an initial attempt to incorporate, in a more representative fashion, the anticipated thermo-hydrologic response in the vicinity of in-drift emplaced waste packages into the post-closure performance assessment. It illustrates some of the issues which must be resolved prior to justifying the inclusion of these representations into the assessment

  11. Towards Chip Scale Liquid Chromatography and High Throughput Immunosensing

    Energy Technology Data Exchange (ETDEWEB)

    Ni, J.

    2000-09-21

    This work describes several research projects aimed towards developing new instruments and novel methods for high throughput chemical and biological analysis. Approaches are taken in two directions. The first direction takes advantage of well-established semiconductor fabrication techniques and applies them to miniaturize instruments that are workhorses in analytical laboratories. Specifically, the first part of this work focused on the development of micropumps and microvalves for controlled fluid delivery. The mechanism of these micropumps and microvalves relies on the electrochemically-induced surface tension change at a mercury/electrolyte interface. A miniaturized flow injection analysis device was integrated and flow injection analyses were demonstrated. In the second part of this work, microfluidic chips were also designed, fabricated, and tested. Separations of two fluorescent dyes were demonstrated in microfabricated channels, based on an open-tubular liquid chromatography (OT LC) or an electrochemically-modulated liquid chromatography (EMLC) format. A reduction in instrument size can potentially increase analysis speed, and allow exceedingly small amounts of sample to be analyzed under diverse separation conditions. The second direction explores the surface enhanced Raman spectroscopy (SERS) as a signal transduction method for immunoassay analysis. It takes advantage of the improved detection sensitivity as a result of surface enhancement on colloidal gold, the narrow width of Raman band, and the stability of Raman scattering signals to distinguish several different species simultaneously without exploiting spatially-separated addresses on a biochip. By labeling gold nanoparticles with different Raman reporters in conjunction with different detection antibodies, a simultaneous detection of a dual-analyte immunoassay was demonstrated. Using this scheme for quantitative analysis was also studied and preliminary dose-response curves from an immunoassay of a

  12. GaN-on-Si blue/white LEDs: epitaxy, chip, and package

    Science.gov (United States)

    Qian, Sun; Wei, Yan; Meixin, Feng; Zengcheng, Li; Bo, Feng; Hanmin, Zhao; Hui, Yang

    2016-04-01

    The dream of epitaxially integrating III-nitride semiconductors on large diameter silicon is being fulfilled through the joint R&D efforts of academia and industry, which is driven by the great potential of GaN-on-silicon technology in improving the efficiency yet at a much reduced manufacturing cost for solid state lighting and power electronics. It is very challenging to grow high quality GaN on Si substrates because of the huge mismatch in the coefficient of thermal expansion (CTE) and the large mismatch in lattice constant between GaN and silicon, often causing a micro-crack network and a high density of threading dislocations (TDs) in the GaN film. Al-composition graded AlGaN/AlN buffer layers have been utilized to not only build up a compressive strain during the high temperature growth for compensating the tensile stress generated during the cool down, but also filter out the TDs to achieve crack-free high-quality n-GaN film on Si substrates, with an X-ray rocking curve linewidth below 300 arcsec for both (0002) and (101¯2) diffractions. Upon the GaN-on-Si templates, prior to the deposition of p-AlGaN and p-GaN layers, high quality InGaN/GaN multiple quantum wells (MQWs) are overgrown with well-engineered V-defects intentionally incorporated to shield the TDs as non-radiative recombination centers and to enhance the hole injection into the MQWs through the via-like structures. The as-grown GaN-on-Si LED wafers are processed into vertical structure thin film LED chips with a reflective p-electrode and the N-face surface roughened after the removal of the epitaxial Si(111) substrates, to enhance the light extraction efficiency. We have commercialized GaN-on-Si LEDs with an average efficacy of 150-160 lm/W for 1mm2 LED chips at an injection current of 350 mA, which have passed the 10000-h LM80 reliability test. The as-produced GaN-on-Si LEDs featured with a single-side uniform emission and a nearly Lambertian distribution can adopt the wafer-level phosphor

  13. Terabit/s communications using chip-scale frequency comb sources

    Science.gov (United States)

    Koos, Christian; Kippenberg, Tobias J.; Barry, Liam P.; Dalton, Larry; Freude, Wolfgang; Leuthold, Juerg; Pfeifle, Joerg; Weimann, Claudius; Lauermann, Matthias; Kemal, Juned N.; Palmer, Robert; Koeber, Sebastian; Schindler, Philipp C.; Herr, Tobias; Brasch, Victor; Watts, Regan T.; Elder, Delwin

    2015-03-01

    High-speed optical interconnects rely on advanced wavelength-division multiplexing (WDM) schemes. However, while photonic-electronic interfaces can be efficiently realized on silicon-on-insulator chips, dense integration of the necessary light sources still represents a major challenge. Chip-scale frequency comb sources present an attractive alternative for providing a multitude of optical carriers for WDM transmission. In this paper, we give an overview of our recent progress towards terabit communications with chip-scale frequency comb sources. In a first set of experiments, we demonstrate frequency comb generation based on silicon-organic hybrid (SOH) electro-optic modulators, enabling line rates up to 1.152 Tbit/s. In a second set of experiments, we use injection locking of a gain-switched laser diode to enerate frequency combs. This approach leads to line rates of more than 2 Tbit/s. A third set of experiments is finally dedicated to using Kerr nonlinearities in integrated nonlinear microcavities for frequency comb generation. We demonstrate coherent communication using Kerr frequency comb sources, thereby achieving line rates up to 1.44 Tbit/s. Our experiments show that frequency comb generation in chip-scale devices represents a viable approach to terabit communications.

  14. Chip scale low dimensional materials: optoelectronics & nonlinear optics

    Science.gov (United States)

    Gu, Tingyi

    The CMOS foundry infrastructure enables integration of high density, high performance optical transceivers. We developed integrated devices that assemble resonators, waveguide, tapered couplers, pn junction and electrodes. Not only the volume standard manufacture in silicon foundry is promising to low-lost optical components operating at IR and mid-IR range, it also provides a robust platform for revealing new physical phenomenon. The thesis starts from comparison between photonic crystal and micro-ring resonators based on chip routers, showing photonic crystal switches have small footprint, consume low operation power, but its higher linear loss may require extra energy for signal amplification. Different designs are employed in their implementation in optical signal routing on chip. The second part of chapter 2 reviews the graphene based optoelectronic devices, such as modulators, lasers, switches and detectors, potential for group IV optoelectronic integrated circuits (OEIC). In chapter 3, the highly efficient thermal optic control could act as on-chip switches and (transmittance) tunable filters. Local temperature tuning compensates the wavelength differences between two resonances, and separate electrode is used for fine tuning of optical pathways between two resonators. In frequency domain, the two cavity system also serves as an optical analogue of Autler-Towns splitting, where the cavity-cavity resonance detuning is controlled by the length of pathway (phase) between them. The high thermal sensitivity of cavity resonance also effectively reflects the heat distribution around the nanoheaters, and thus derives the thermal conductivity in the planar porous suspended silicon membrane. Chapter 4 & 5 analyze graphene-silicon photonic crystal cavities with high Q and small mode volume. With negligible nonlinear response to the milliwatt laser excitation, the monolithic silicon PhC turns into highly nonlinear after transferring the single layer graphene with

  15. A Comparative Study of Inspection Techniques for Array Packages

    Science.gov (United States)

    Mohammed, Jelila; Green, Christopher

    2008-01-01

    This viewgraph presentation reviews the inspection techniques for Column Grid Array (CGA) packages. The CGA is a method of chip scale packaging using high temperature solder columns to attach part to board. It is becoming more popular over other techniques (i.e. quad flat pack (QFP) or ball grid array (BGA)). However there are environmental stresses and workmanship challenges that require good inspection techniques for these packages.

  16. User-Loaded SlipChip for Equipment-Free Multiplexed Nanoliter-Scale Experiments

    Energy Technology Data Exchange (ETDEWEB)

    Li, Liang; Du, Wenbin; Ismagilov, Rustem (UC)

    2010-08-04

    This paper describes a microfluidic approach to perform multiplexed nanoliter-scale experiments by combining a sample with multiple different reagents, each at multiple mixing ratios. This approach employs a user-loaded, equipment-free SlipChip. The mixing ratios, characterized by diluting a fluorescent dye, could be controlled by the volume of each of the combined wells. The SlipChip design was validated on an {approx}12 nL scale by screening the conditions for crystallization of glutaryl-CoA dehydrogenase from Burkholderia pseudomallei against 48 different reagents; each reagent was tested at 11 different mixing ratios, for a total of 528 crystallization trials. The total consumption of the protein sample was {approx}10 {micro}L. Conditions for crystallization were successfully identified. The crystallization experiments were successfully scaled up in well plates using the conditions identified in the SlipChip. Crystals were characterized by X-ray diffraction and provided a protein structure in a different space group and at a higher resolution than the structure obtained by conventional methods. In this work, this user-loaded SlipChip has been shown to reliably handle fluids of diverse physicochemical properties, such as viscosities and surface tensions. Quantitative measurements of fluorescent intensities and high-resolution imaging were straighforward to perform in these glass SlipChips. Surface chemistry was controlled using fluorinated lubricating fluid, analogous to the fluorinated carrier fluid used in plug-based crystallization. Thus, we expect this approach to be valuable in a number of areas beyond protein crystallization, especially those areas where droplet-based microfluidic systems have demonstrated successes, including measurements of enzyme kinetics and blood coagulation, cell-based assays, and chemical reactions.

  17. Characterization of integrated circuit packaging materials

    CERN Document Server

    Moore, Thomas

    1993-01-01

    Chapters in this volume address important characteristics of IC packages. Analytical techniques appropriate for IC package characterization are demonstrated through examples of the measurement of critical performance parameters and the analysis of key technological problems of IC packages. Issues are discussed which affect a variety of package types, including plastic surface-mount packages, hermetic packages, and advanced designs such as flip-chip, chip-on-board and multi-chip models.

  18. Miniature stick-packaging--an industrial technology for pre-storage and release of reagents in lab-on-a-chip systems.

    Science.gov (United States)

    van Oordt, Thomas; Barb, Yannick; Smetana, Jan; Zengerle, Roland; von Stetten, Felix

    2013-08-01

    Stick-packaging of goods in tubular-shaped composite-foil pouches has become a popular technology for food and drug packaging. We miniaturized stick-packaging for use in lab-on-a-chip (LOAC) systems to pre-store and on-demand release the liquid and dry reagents in a volume range of 80-500 μl. An integrated frangible seal enables the pressure-controlled release of reagents and simplifies the layout of LOAC systems, thereby making the package a functional microfluidic release unit. The frangible seal is adjusted to defined burst pressures ranging from 20 to 140 kPa. The applied ultrasonic welding process allows the packaging of temperature sensitive reagents. Stick-packs have been successfully tested applying recovery tests (where 99% (STDV = 1%) of 250 μl pre-stored liquid is released), long-term storage tests (where there is loss of only simulated 2 years) and air transport simulation tests. The developed technology enables the storage of a combination of liquid and dry reagents. It is a scalable technology suitable for rapid prototyping and low-cost mass production.

  19. Analytical investigation of the feasibility of sacrificial microchannel sealing for Chip-Scale Atomic Magnetometers

    OpenAIRE

    Tsujimoto, Kazuya; Hirai, Yoshikazu; Sugano, Koji; Tsuchiya, Toshiyuki; TABATA, Osamu

    2014-01-01

    An alkali metal vapor cell is a crucial component of the highly sensitive Chip Scale Atomic Magnetometers (CSAMs) that are increasingly deployed in a variety of electronic devices. Herein, we propose a novel microfabrication technique utilizing an array of microchannels at a bonded interface, to enable gas feedthrough for evacuation of unwanted gases from a vapor cell and subsequent introduction of an inert gas, followed by permanent sealing of the microchannels by reflow of a glass frit. The...

  20. Using Synchrotron Radiation Microtomography to Investigate Multi-scale Three-dimensional Microelectronic Packages.

    Science.gov (United States)

    Carlton, Holly D; Elmer, John W; Li, Yan; Pacheco, Mario; Goyal, Deepak; Parkinson, Dilworth Y; MacDowell, Alastair A

    2016-01-01

    Synchrotron radiation micro-tomography (SRµT) is a non-destructive three-dimensional (3D) imaging technique that offers high flux for fast data acquisition times with high spatial resolution. In the electronics industry there is serious interest in performing failure analysis on 3D microelectronic packages, many which contain multiple levels of high-density interconnections. Often in tomography there is a trade-off between image resolution and the volume of a sample that can be imaged. This inverse relationship limits the usefulness of conventional computed tomography (CT) systems since a microelectronic package is often large in cross sectional area 100-3,600 mm(2), but has important features on the micron scale. The micro-tomography beamline at the Advanced Light Source (ALS), in Berkeley, CA USA, has a setup which is adaptable and can be tailored to a sample's properties, i.e., density, thickness, etc., with a maximum allowable cross-section of 36 x 36 mm. This setup also has the option of being either monochromatic in the energy range ~7-43 keV or operating with maximum flux in white light mode using a polychromatic beam. Presented here are details of the experimental steps taken to image an entire 16 x 16 mm system within a package, in order to obtain 3D images of the system with a spatial resolution of 8.7 µm all within a scan time of less than 3 min. Also shown are results from packages scanned in different orientations and a sectioned package for higher resolution imaging. In contrast a conventional CT system would take hours to record data with potentially poorer resolution. Indeed, the ratio of field-of-view to throughput time is much higher when using the synchrotron radiation tomography setup. The description below of the experimental setup can be implemented and adapted for use with many other multi-materials. PMID:27167469

  1. Chip-Scale Continuously Tunable Optical Orbital Angular Momentum Generator

    CERN Document Server

    Sun, Jie; Moresco, Michele; Coolbaugh, Douglas; Watts, Michael R

    2014-01-01

    Light carrying orbital angular momentum (OAM) has potential to impact a wide variety of applications ranging from optical communications to quantum information and optical forces for the excitation and manipulation of atoms, molecules, and micro-particles. The unique advantage of utilizing OAM in these applications relies, to a large extent, on the use of multiple different OAM states. Therefore, it is desirable to have a device that is able to gen- erate light with freely adjustable OAM states in an integrated form for large- scale integration. We propose and demonstrate a compact silicon photonic integrated circuit to generate a free-space optical beam with OAM state con- tinuously tuned from a single electrical input signal, realizing both integer and non-integer OAM states. The compactness and flexibility of the device and its compatibility with complementary metal-oxide-semiconductor (CMOS) pro- cessing hold promise for integration with other silicon photonic components for wide-ranging applications.

  2. Surface Tension Directed Fluidic Self-Assembly of Semiconductor Chips across Length Scales and Material Boundaries

    Directory of Open Access Journals (Sweden)

    Shantonu Biswas

    2016-03-01

    Full Text Available This publication provides an overview and discusses some challenges of surface tension directed fluidic self-assembly of semiconductor chips which are transported in a liquid medium. The discussion is limited to surface tension directed self-assembly where the capture, alignment, and electrical connection process is driven by the surface free energy of molten solder bumps where the authors have made a contribution. The general context is to develop a massively parallel and scalable assembly process to overcome some of the limitations of current robotic pick and place and serial wire bonding concepts. The following parts will be discussed: (2 Single-step assembly of LED arrays containing a repetition of a single component type; (3 Multi-step assembly of more than one component type adding a sequence and geometrical shape confinement to the basic concept to build more complex structures; demonstrators contain (3.1 self-packaging surface mount devices, and (3.2 multi-chip assemblies with unique angular orientation. Subsequently, measures are discussed (4 to enable the assembly of microscopic chips (10 μm–1 mm; a different transport method is introduced; demonstrators include the assembly of photovoltaic modules containing microscopic silicon tiles. Finally, (5 the extension to enable large area assembly is presented; a first reel-to-reel assembly machine is realized; the machine is applied to the field of solid state lighting and the emerging field of stretchable electronics which requires the assembly and electrical connection of semiconductor devices over exceedingly large area substrates.

  3. Stabilized chip-scale Kerr frequency comb via a high-Q reference photonic microresonator

    Science.gov (United States)

    Lim, Jinkang; Huang, Shu-Wei; Vinod, Abhinav K.; Mortazavian, Parastou; Yu, Mingbin; Kwong, Dim-Lee; Savchenkov, Anatoliy A.; Matsko, Andrey B.; Maleki, Lute; Wong, Chee Wei

    2016-08-01

    We stabilize a chip-scale Si3N4 phase-locked Kerr frequency comb via locking the pump laser to an independent stable high-Q reference microresonator and locking the comb spacing to an external microwave oscillator. In this comb, the pump laser shift induces negligible impact on the comb spacing change. This scheme is a step towards miniaturization of the stabilized Kerr comb system as the microresonator reference can potentially be integrated on-chip. Fractional instability of the optical harmonics of the stabilized comb is limited by the microwave oscillator used for comb spacing lock below 1 s averaging time and coincides with the pump laser drift in the long term.

  4. A stabilized chip-scale Kerr frequency comb via a high-Q reference photonic microresonator

    CERN Document Server

    Lim, Jinkang; Vinod, Abhinav K; Mortazavian, Parastou; Yu, Mingbin; Kwong, Dim-Lee; Savchenkov, Anatoliy A; Matsko, Andrey B; Maleki, Lute; Wong, Chee Wei

    2016-01-01

    We stabilize a chip-scale Si3N4 phase-locked Kerr frequency comb via locking the pump laser to an independent stable high-Q reference microresonator and locking the comb spacing to an external microwave oscillator. In this comb, the pump laser shift induces negligible impact on the comb spacing change. This scheme is a step towards miniaturization of the stabilized Kerr comb system as the microresonator reference can potentially be integrated on-chip. Fractional instability of the optical harmonics of the stabilized comb is limited by the microwave oscillator used for comb spacing lock below 1 s averaging time and coincides with the pump laser drift in the long term.

  5. Nature-Inspired Interconnects for Self-Assembled Large-Scale Network-on-Chip Designs

    CERN Document Server

    Teuscher, Christof

    2007-01-01

    Future nano-scale electronics built up from an Avogadro number of components needs efficient, highly scalable, and robust means of communication in order to be competitive with traditional silicon approaches. In recent years, the Networks-on-Chip (NoC) paradigm emerged as a promising solution to interconnect challenges in silicon-based electronics. Current NoC architectures are either highly regular or fully customized, both of which represent implausible assumptions for emerging bottom-up self-assembled molecular electronics that are generally assumed to have a high degree of irregularity and imperfection. Here, we pragmatically and experimentally investigate important design trade-offs and properties of an irregular, abstract, yet physically plausible 3D small-world interconnect fabric that is inspired by modern network-on-chip paradigms. We vary the framework's key parameters, such as the connectivity, the number of switch nodes, the distribution of long- versus short-range connections, and measure the net...

  6. Monitoring CO2 invasion processes at the pore scale using geological labs on chip.

    Science.gov (United States)

    Morais, S; Liu, N; Diouf, A; Bernard, D; Lecoutre, C; Garrabos, Y; Marre, S

    2016-09-21

    In order to investigate at the pore scale the mechanisms involved during CO2 injection in a water saturated pore network, a series of displacement experiments is reported using high pressure micromodels (geological labs on chip - GLoCs) working under real geological conditions (25 < T (°C) < 75 and 4.5 < p (MPa) < 8). The experiments were focused on the influence of three experimental parameters: (i) the p, T conditions, (ii) the injection flow rates and (iii) the pore network characteristics. By using on-chip optical characterization and imaging approaches, the CO2 saturation curves as a function of either time or the number of pore volume injected were determined. Three main mechanisms were observed during CO2 injection, namely, invasion, percolation and drying, which are discussed in this paper. Interestingly, besides conventional mechanisms, two counterintuitive situations were observed during the invasion and drying processes.

  7. A Batch Wafer Scale LIGA Assembly and Packaging Technique vai Diffusion Bonding

    Energy Technology Data Exchange (ETDEWEB)

    Christenson, T.R.; Schmale, D.T.

    1999-01-27

    A technique using diffusion bonding (or solid-state welding) has been used to achieve batch fabrication of two- level nickel LIGA structures. Interlayer alignment accuracy of less than 1 micron is achieved using press-fit gauge pins. A mini-scale torsion tester was built to measure the diffusion bond strength of LIGA formed specimens that has shown successful bonding at temperatures of 450"C at 7 ksi pressure with bond strength greater than 100 Mpa. Extensions to this basic process to allow for additional layers and thereby more complex assemblies as well as commensurate packaging are discussed.

  8. Electrical performance analysis of IC package for the high-end memory device

    Science.gov (United States)

    Lee, Dong H.; Han, Chan M.

    1997-08-01

    The developments of processing technology and design make it possible to increase the clock speed and the number of input outputs (I/Os) in memory devices. The interconnections of IC package are considered as an important factor to decide the performance of the memory devices. In order to overcome the limitations of the conventional package, new types of package such as Ball Grid Array (BGA), chip scale package or flip chip bonding are adopted by many IC manufacturers. The present work has compared the electrical performances of 3 different packages to provide deign guide for IC packages of the high performance memory devices in the future. Those packages are designed for the same memory devices to confront to the diversity of memory market demand. The conventional package using lead frame, wire bonded BGA using printed circuit board substrate and flip chip bonded BGA are analyzed. Their electrical performances are compared in the area of signal delay and coupling effect between signal interconnections. The electrical package modeling is built by extracting parasitic of interconnections in IC package through electro-magnetic simulations. The electrical package modeling is built by extracting parasitic of interconnections in IC package through electro-magnetic simulations. The analysis of electrical behavior is performed using SPICE model which is made to represent the real situation. The methodology presented is also capable of determining the most suitable memory package for a particular device based on the electrical performance.

  9. New Latency Model for Dynamic Frequency Scaling on Network-on-Chip

    Institute of Scientific and Technical Information of China (English)

    Sheng-Nan Li; Wen-Ming Pan

    2014-01-01

    Modulating both the clock frequency and supply voltage of the network-on-chip (NoC) during runtime can reduce the power consumption and heat flux, but will lead to the increase of the latency of NoC. It is necessary to find a tradeoff between power consumption and communication latency. So we propose an analytical latency model which can show us the relationship of them. The proposed model to analyze latency is based on the M/G/1 queuing model, which is suitable for dynamic frequency scaling. The experiment results show that the accuracy of this model is more than 90%.

  10. Global review of open access risk assessment software packages valid for global or continental scale analysis

    Science.gov (United States)

    Daniell, James; Simpson, Alanna; Gunasekara, Rashmin; Baca, Abigail; Schaefer, Andreas; Ishizawa, Oscar; Murnane, Rick; Tijssen, Annegien; Deparday, Vivien; Forni, Marc; Himmelfarb, Anne; Leder, Jan

    2015-04-01

    -defined exposure and vulnerability. Without this function, many tools can only be used regionally and not at global or continental scale. It is becoming increasingly easy to use multiple packages for a single region and/or hazard to characterize the uncertainty in the risk, or use as checks for the sensitivities in the analysis. There is a potential for valuable synergy between existing software. A number of open source software packages could be combined to generate a multi-risk model with multiple views of a hazard. This extensive review has simply attempted to provide a platform for dialogue between all open source and open access software packages and to hopefully inspire collaboration between developers, given the great work done by all open access and open source developers.

  11. GMATA: An Integrated Software Package for Genome-Scale SSR Mining, Marker Development and Viewing

    Science.gov (United States)

    Wang, Xuewen; Wang, Le

    2016-01-01

    Simple sequence repeats (SSRs), also referred to as microsatellites, are highly variable tandem DNAs that are widely used as genetic markers. The increasing availability of whole-genome and transcript sequences provides information resources for SSR marker development. However, efficient software is required to efficiently identify and display SSR information along with other gene features at a genome scale. We developed novel software package Genome-wide Microsatellite Analyzing Tool Package (GMATA) integrating SSR mining, statistical analysis and plotting, marker design, polymorphism screening and marker transferability, and enabled simultaneously display SSR markers with other genome features. GMATA applies novel strategies for SSR analysis and primer design in large genomes, which allows GMATA to perform faster calculation and provides more accurate results than existing tools. Our package is also capable of processing DNA sequences of any size on a standard computer. GMATA is user friendly, only requires mouse clicks or types inputs on the command line, and is executable in multiple computing platforms. We demonstrated the application of GMATA in plants genomes and reveal a novel distribution pattern of SSRs in 15 grass genomes. The most abundant motifs are dimer GA/TC, the A/T monomer and the GCG/CGC trimer, rather than the rich G/C content in DNA sequence. We also revealed that SSR count is a linear to the chromosome length in fully assembled grass genomes. GMATA represents a powerful application tool that facilitates genomic sequence analyses. GAMTA is freely available at http://sourceforge.net/projects/gmata/?source=navbar. PMID:27679641

  12. 集成电路封装芯片弹坑问题浅探%Analysis and Solving on Crater Issue of IC Chip Packaging

    Institute of Scientific and Technical Information of China (English)

    周金成

    2011-01-01

    The damage of the chip crater located on the aluminum pad and the main reasons of the crater problem were investigated in details. The methods to prevente the crater problem were proposed by considering the wire bonding process, facilities and materials, etc. According to the results in the longterm practice, the application of these methods can reduce the occurrence of the chip crater effectively,which is of considerable referential importance for IC design and packaging process to prevent the crater problem. With the extensive use of the IC chip with smaller size, more functionality, as well as the widely used copper technology and ball bonding process in packaging technology, the crater problem can be better solved with the efforts of people employed in the IC design, optimization of packaging materials and process technology.%论述了集成电路封装过程中因芯片铝垫出现弹坑造成的危害,分析和总结出了造成芯片弹坑问题的主要原因,通过从工艺、设备、制具、材料、方法等综合考虑,提出了预防芯片表面产生弹坑的方法和对策.根据长期实践跟踪的结果,这些方法的应用能够对预防和改善弹坑的发生起到很好的效果,为集成电路设计及封装过程如何预防弹坑问题提供了参考.伴随集成电路芯片小型化、多功能化和铜线工艺、植球工艺等封装技术的广泛应用,通过各级人士在集成电路的设计、封装材料的优化、制程工艺的优化等各方面共同努力,弹坑问题会得到更好的预防和解决.

  13. Network Partitioning Domain Knowledge Multiobjective Application Mapping for Large-Scale Network-on-Chip

    Directory of Open Access Journals (Sweden)

    Yin Zhen Tei

    2014-01-01

    Full Text Available This paper proposes a multiobjective application mapping technique targeted for large-scale network-on-chip (NoC. As the number of intellectual property (IP cores in multiprocessor system-on-chip (MPSoC increases, NoC application mapping to find optimum core-to-topology mapping becomes more challenging. Besides, the conflicting cost and performance trade-off makes multiobjective application mapping techniques even more complex. This paper proposes an application mapping technique that incorporates domain knowledge into genetic algorithm (GA. The initial population of GA is initialized with network partitioning (NP while the crossover operator is guided with knowledge on communication demands. NP reduces the large-scale application mapping complexity and provides GA with a potential mapping search space. The proposed genetic operator is compared with state-of-the-art genetic operators in terms of solution quality. In this work, multiobjective optimization of energy and thermal-balance is considered. Through simulation, knowledge-based initial mapping shows significant improvement in Pareto front compared to random initial mapping that is widely used. The proposed knowledge-based crossover also shows better Pareto front compared to state-of-the-art knowledge-based crossover.

  14. A chip tuneable laser developed for on-line micro–nano scale surface measurements

    International Nuclear Information System (INIS)

    The demand for accuracy and precision at the micro–nano level is constantly increasing in the manufacture of high added value products. This requires control and measurement of the surface structure since surface properties at such tiny scales are the dominant functional determinant. Many commercial instruments have been used for surface measurements. However, these devices are almost always operated in an off-line environment, and are not suitable for on-line application. This paper presents a new interferometry system consisting of a chip tuneable laser for future on-line micro–nano scale surface measurements. It is simple, compact and robust as most environmental noise and disturbance can be eliminated without any servo control system due to the near common path configuration and the compact construction. The experimental results show that this system has good performance, and there is scope to improve this if the performance of the laser is enhanced

  15. Large-field-of-view Chip-scale Talbot-grid-based Fluorescence Microscopy

    CERN Document Server

    Pang, Shuo; Kato, Mihoko; Sternberg, Paul W; Yang, Changhuei

    2012-01-01

    The fluorescence microscope is one of the most important tools in modern clinical diagnosis and biological science. However, its expense, size and limited field-of-view (FOV) are becoming bottlenecks in key applications such as large-scale phenotyping and low-resource-setting diagnostics. Here we report a low-cost, compact chip-scale fluorescence-imaging platform, termed the Fluorescence Talbot Microscopy (FTM), which utilizes the Talbot self-imaging effect to enable efficient fluorescence imaging over a large and directly-scalable FOV. The FTM prototype has a resolution of 1.2 microns and an FOV of 3.9 mm x 3.5 mm. We demonstrate the imaging capability of FTM on fluorescently labeled breast cancer cells (SK-BR-3) and HEK cells expressing green fluorescent protein.

  16. Small-Scale High Temperature Melter-1 (SSHTM-1) Data Package. Appendix A

    International Nuclear Information System (INIS)

    This appendix provides the data for Alternate HTM Flowsheet 1 (No Reductant Addition, Nitric Acid) melter feed preparation activities in both the laboratory and small-scale testing. The first section provides an outline of this appendix. The melter feed preparation data are presented in the next two main sections, laboratory welter feed preparation data and small-scale melter feed preparation data. Section 3.0 provides the laboratory data which is discussed in the main body of the Small-Scale High Temperature-1 (SSHTM-1) Data Package, milestone C95-02.02Y. Section 3.1 gives the flowsheet in outline form as used in the laboratory-scale tests. This section also includes the ''Laboratory Melter Feed Preparation Activity Log'' which gives a chronological account of the test in terms of time, temperature, slurry pH, and specific observations about slurry appearance, acid addition rates, and samples taken. The ''Laboratory Melter Feed Preparation Activity Log'' provides a road map to the reader by which all the activity and data from the laboratory can be easily accessed. A summary of analytical data is presented next, section 3.2, which covers starting materials and progresses to the analysis of the melter feed. The next section, 3.3, characterizes the off-gas generation that occurs during the slurry processing. The following section, 3.4, provides the rheology data gathered including gram waste oxide loading information for the various slurries tested. The final section, 3.5. includes data from standard crucible redox testing. Section 4.0 provides the small-scale data tn parallel form to section 3.0. Section 5.0 concludes with the references for this appendix

  17. Small-Scale High Temperature Melter-1 (SSHTM-1) Data Package. Appendix B

    Energy Technology Data Exchange (ETDEWEB)

    NONE

    1996-03-01

    This appendix provides the data for Alternate HTM Flowsheet 2 (Glycolic Acid) melter feed preparation activities in both the laboratory- and small-scale testing. The first section provides an outline of this appendix. The melter feed preparation data are presented in the next two main sections, laboratory melter feed preparation data and small-scale melter feed preparation data. Section 3.0 provides the laboratory data which is discussed in the main body of the Small-Scale High Temperature-1 (SSHTM-1) Data Package, milestone C95-02.02Y. Section 3.1 gives the flowsheet in outline form as used in the laboratory-scale tests. This section also includes the ``Laboratory Melter Feed Preparation Activity Log`` which gives A chronological account of the test in terms of time, temperature, slurry pH, and specific observations about slurry appearance, acid addition rates, and samples taken. The ``Laboratory Melter Feed Preparation Activity Log`` provides a road map to the reader by which all the activity and data from the laboratory can be easily accessed. A summary of analytical data is presented next, section 3.2, which covers starting materials and progresses to the analysis of the melter feed. The next section, 3.3, characterizes the off-gas generation that occurs during the slurry processing. The following section, 3.4, provides the rheology data gathered including gram waste oxide loading information for the various slurries tested. The final section, 3.5, includes data from standard crucible redox testing. Section 4.0 provides the small-scale data in parallel form to section 3.0. Section 5.0 concludes with the references for this appendix.

  18. Development of the large-scale oligonucleotide chip for the diagnosis of plant viruses and its practical use.

    Science.gov (United States)

    Nam, Moon; Kim, Jeong-Seon; Lim, Seungmo; Park, Chung Youl; Kim, Jeong-Gyu; Choi, Hong-Soo; Lim, Hyoun-Sub; Moon, Jae Sun; Lee, Su-Heon

    2014-03-01

    A large-scale oligonucleotide (LSON) chip was developed for the detection of the plant viruses with known genetic information. The LSON chip contains two sets of 3,978 probes for 538 species of targets including plant viruses, satellite RNAs and viroids. A hundred forty thousand probes, consisting of isolate-, species- and genus-specific probes respectively, are designed from 20,000 of independent nucleotide sequence of plant viruses. Based on the economic importance, the amount of genome information, and the number of strains and/or isolates, one to fifty-one probes for each target virus are selected and spotted on the chip. The standard and field samples for the analysis of the LSON chip have been prepared and tested by RT-PCR. The probe's specific and/or nonspecific reaction patterns by LSON chip allow us to diagnose the unidentified viruses. Thus, the LSON chip in this study could be highly useful for the detection of unexpected plant viruses, the monitoring of emerging viruses and the fluctuation of the population of major viruses in each plant.

  19. Development of Generalized Perturbation Theory Capability within the SCALE Code Package

    International Nuclear Information System (INIS)

    Computational capability has been developed to calculate sensitivity coefficients of generalized responses with respect to cross-section data in the SCALE code system. The focus of this paper is the implementation of generalized perturbation theory (GPT) for one-dimensional and two-dimensional deterministic neutron transport calculations. GPT is briefly summarized for computing sensitivity coefficients for reaction rate ratio responses within the existing framework of the TSUNAMI sensitivity and uncertainty (S/U) analysis code package in SCALE. GPT provides the capability to analyze generalized responses related to reactor analysis, such as homogenized cross-sections, relative powers, and conversion ratios, as well as measured experimental parameters such as 28 (epithermal/thermal 238U capture rates) in thermal benchmarks and fission ratios such as 239Pu(n,f)/235U(n,f) in fast benchmarks. The S/U analysis of these experimental integral responses can be used to augment the existing TSUNAMI S/U analysis capabilities for system similarity assessment and data adjustment. S/U analysis is provided for boiling water reactor pin cell as part of the Organization for Economic Cooperation and Development Uncertainty Analysis in Modeling benchmark.

  20. Development of generalized perturbation theory capability within the scale code package

    International Nuclear Information System (INIS)

    Computational capability has been developed to calculate sensitivity coefficients of generalized responses with respect to cross-section data in the SCALE code system. The focus of this paper is the implementation of generalized perturbation theory (GPT) for one-dimensional and two-dimensional deterministic neutron transport calculations. GPT is briefly summarized for computing sensitivity coefficients for reaction rate ratio responses within the existing framework of the TSUNAMI sensitivity and uncertainty (S/U) analysis code package in SCALE. GPT provides the capability to analyze generalized responses related to reactor analysis, such as homogenized cross-sections, relative powers, and conversion ratios, as well as measured experimental parameters such as 28ρ(epithermal/thermal 238U capture rates) in thermal benchmarks and fission ratios such as 239U(n,f)/235U(n,f) in fast benchmarks. The S/U analysis of these experimental integral responses can be used to augment the existing TSUNAMI S/U analysis capabilities for system similarity assessment and data adjustment. S/U analysis is provided for boiling water reactor pin cell as part of the Organization for Economic Cooperation and Development Uncertainty Analysis in Modeling benchmark. (authors)

  1. 倒装芯片封装技术及内部应力检测技术探析%The technology of flip chip packaging and internal stress detection

    Institute of Scientific and Technical Information of China (English)

    宣慧

    2015-01-01

    当前,倒装芯片封装技术已经成为相关领域的主流方法,但由于芯片、基板、焊球、下填料等材料具有差异化的热膨胀系数,导致封装过程中极易引入热应力,不利于保持芯片的性能及其可靠性。采用有效方法能够对倒装封装过程中所产生的应力进行检测,对于完善封装参数,提高产品可靠性,具有重要的现实意义。%At present,flip chip packaging technology has become the mainstream method in related fields, but due to the chip,a substrate,solder ball, filler materials with different thermal expansion coefficient, resulting in the encapsulation process is very easy to introduce heat stress,is not conducive to maintaining the performance and reliability of the chip.The effective method can be used to detect the stress generated in the flip chip packaging process,and has important practical significance for improving the packaging parameters and improving the reliability of the product.

  2. ESTABLISHMENT OF DESIGN CRITERIA FOR OPTIMUM BURNERS FOR APPLICATION TO HEAVY FUEL FIRED PACKAGE BOILERS. VOLUME 2. PILOT SCALE TESTS

    Science.gov (United States)

    The report gives results of a research program to develop low-NOx heavy oil burners for application to industrial package boilers. Volume I documents Phase 1 of the program, bench scale studies which defined optimum conditions for two-stage combustion. The information led to a co...

  3. ESTABLISHMENT OF DESIGN CRITERIA FOR OPTIMUM BURNERS FOR APPLICATION TO HEAVY FUEL FIRED PACKAGE BOILERS. VOLUME 1. LABORATORY SCALE TESTS

    Science.gov (United States)

    The report gives results of a research program to develop low-NOx heavy oil burners for application to industrial package boilers. Volume I documents Phase 1 of the program, bench scale studies which defined optimum conditions for two-stage combustion. The information led to a co...

  4. Wafer-level packaging and laser bonding as an approach for silicon-into-lab-on-chip integration

    Science.gov (United States)

    Brettschneider, T.; Dorrer, C.; Bründel, M.; Zengerle, R.; Daub, M.

    2013-05-01

    A novel approach for the integration of silicon biosensors into microfluidics is presented. Our approach is based on wafer-level packaging of the silicon die and a laser-bonding process of the resulting mold package into a polymer-multilayer stack. The introduction of a flexible and 40 μm thin hot melt foil as an intermediate layer enables laser bonding between materials with different melting temperatures, where standard laser welding processes cannot be employed. All process steps are suitable for mass production, e.g. the approach does not involve any dispensing steps for glue or underfiller. The integration approach was demonstrated and evaluated regarding process technology by wafer-level redistribution of daisy chain silicon dies representing a generic biosensor. Electrical connection was successfully established and laser-bonding tensile strength of 5.7 N mm-2 and burst pressure of 587 kPa at a temperature of 100 °C were achieved for the new material combination. The feasibility of the complete packaging approach was shown by the fabrication of a microfluidic flow cell with embedded mold package.

  5. Chip-scale fully reconfigurable optical add/drop multiplexing subsystem in polymer microphotonic circuits

    Science.gov (United States)

    Izuhara, Tomoyuki; Fujita, Junichiro; Radojevic, Antonije; Gerhardt, Reinald; Eldada, Louay A.

    2004-10-01

    We report on a highly integrated photonic circuit using a polymer-based planar waveguide system. The properties of the materials used in this work such as ultra-low optical loss, widely tunable refractive index, and large thermo-optic coefficient, enable a multi-functional chip-scale microphotonic circuit. We discuss the application of this technology to the fabrication of a fully reconfigurable optical add/drop multiplexer. This subsystem includes channel switching, power monitoring, load balancing, and wavelength shuffling functionalities that are required for agile wavelength-division multiplexing optical networks. Optical properties of our material systems and performance characteristics of the implemented optical passive/active elements are presented, and the integration schemes of the devices to achieve a fully integrated reconfigurable optical add/drop multiplexer are discussed.

  6. Sacrificial Microchannel Sealing by Glass-Frit Reflow for Chip Scale Atomic Magnetometer

    Science.gov (United States)

    Tsujimoto, Kazuya; Hirai, Yoshikazu; Sugano, Koji; Tsuchiya, Toshiyuki; Tabata, Osamu

    A novel sealing technique using sacrificial microchannels was proposed for atmosphere control in a micromachined alkali gas-filled cell for a chip scale atomic magnetometer. The microchannels act as feedthrough connecting the cell to outside atmosphere during evacuation and gas-filling steps, and eventually they are sealed by glass-frit reflow. Si microchannel dedicated as a sacrificial microchannel was proposed and its feasibility was successfully demonstrated by experiments. The simulation results clarified the glass-frit reflow characteristics and its dependence on cross-sectional shape of the microchannel. Hermeticity of the proposed sealing technique of less than 10-12Pa·m3/s leak rate was verified by a high resolution helium leak test.

  7. Integrated chip-scale Si3N4 wavemeter with narrow free spectral range and high stability.

    Science.gov (United States)

    Xiang, Chao; Tran, Minh A; Komljenovic, Tin; Hulme, Jared; Davenport, Michael; Baney, Doug; Szafraniec, Bogdan; Bowers, John E

    2016-07-15

    We designed, fabricated, and characterized an integrated chip-scale wavemeter based on an unbalanced Mach-Zehnder interferometer with 300 MHz free spectral range. The wavemeter is realized in the Si3N4 platform, allowing for low loss with ∼62  cm of on-chip delay. We also integrated an optical hybrid to provide phase information. The main benefit of a fully integrated wavemeter, beside its small dimensions, is increased robustness to vibrations and temperature variations and much improved stability over fiber-based solutions. PMID:27420522

  8. Thermal chip fabrication with arrays of sensors and heaters for micro-scale impingement cooling heat transfer analysis and measurements.

    Science.gov (United States)

    Shen, C H; Gau, C

    2004-07-30

    The design and fabrication for a thermal chip with an array of temperature sensors and heaters for study of micro-jet impingement cooling heat transfer process are presented. This thermal chip can minimize the heat loss from the system to the ambient and provide a uniform heat flux along the wall, thus local heat transfer processes along the wall can be measured and obtained. The fabrication procedure presented can reach a chip yield of 100%, and every one of the sensors and heaters on the chip is in good condition. In addition, micro-jet impingement cooling experiments are performed to obtain the micro-scale local heat transfer Nusselt number along the wall. Flow visualization for the micro-impinging jet is also made. The experimental results indicate that both the micro-scale impinging jet flow structure and the heat transfer process along the wall is significantly different from the case of large-scale jet impingement cooling process. PMID:15142582

  9. Chip integration using inkjet-printed silver conductive tracks reinforced by electroless plating for flexible board packages

    OpenAIRE

    Cauchois, Romain; Saadaoui, Mohamed; Legeleux, Jacques; Malia, Thierry; Dubois-Bonvalot, Béatrice; Inal, Karim; Fidalgo, Jean-Christophe

    2012-01-01

    International audience Inkjet-printing of interconnects is a maskless technology that has attracted great interest for printed electronics and packaging applications. Gemalto is expecting by motivated and developing skills and knowledge in this area to be at the forefront of European Security innovation and to answer to a continuous market pressure for higher security, lower cost and more secure complex systems. With an increasing need for flexible and mass deliveries of advanced secure pe...

  10. Development of a small-scale protope of the GOSSIPO-2 chip in 0.13 um CMOS technology

    CERN Document Server

    Kluit, R; Gromov, V

    2007-01-01

    The GOSSIP (Gas On Slimmed Silicon Pixel) detector is a proposed alternative for silicon based pixel detectors. The Gossip Prototype (GOSSIPO) chip is being developed to serve as a prototype read-out chip for such a gas-filled detector. Thanks to the very low capacitance at the preamplifier input, the front-end of the chip demonstrates low-noise performance in combination with a fast peaking time and low analog power dissipation. Measurement of the drift time of every primary electron in the gas volume enables 3D reconstruction of the particle tracks. For this purpose a Time-to- Digital converter must be placed in each pixel. A small-scale prototype of the GOSSIP chip has been developed in the 0.13 μm CMOS technology. The prototype includes a 16 by 16 pixel array where each pixel is equipped with a front-end circuit, threshold DAC, and a 4-bit TDC. The chip is available for testing in May 2007 and after initial tests it will be postprocessed to build a prototype detector. This paper describes the detector de...

  11. 一种数字微镜器件的倒装封装设计%Design of the Flip-Chip Package for Digital Micromirror Devices

    Institute of Scientific and Technical Information of China (English)

    李中楠; 王淑仙

    2012-01-01

    数字微镜器件是由MEMS工艺制成的数字式光反射开关阵列组成,其I/O管脚工作频率高达800 MHz.针对数字微镜器件的对光电两方面性能的严格要求,设计了一种数字微镜器件的封装结构.首先选择倒装封装技术来减小寄生参数,提高器件响应速度;其次优化了板层结构,采用玻璃基底和遮光层来满足光学要求;最后通过对信号完整性和电源完整性问题的仿真设计,满足了电学性能要求,完善了封装基板设计流程.对制作出的微镜器件封装进行测试,在800 MHz的数据频率下,眼图结果与仿真结果较为吻合,降低了封装对信号完整性的影响,达到封装设计要求的指标.%Digital micromirror device is composed of arrays of fast reflective digital light switches which are made by the MEMS fabrication technology, and the highest frequency of I/O pins can be up to 800 MHz. According to the characteristics of this device, a special package design for the advanced digital micromirror device was proposed. This package used the flip-chip technology for smaller parasitic parameter and higher speed. An optimized package structure which used the glass substrate and light shield was adopted to satisfy the optical requests. An appropriate simulation method for signal integrity and power integrity was adopted to satisfy the electrical requests and improved the substrate design flow. The test for the device which has been produced indicates that the eyediagram tally well with the simulation waveform when the frequency of I/O pins is 800 MHz. It reduces the influence of the package on signal integrity problems and meets the requirement of this design.

  12. Demonstration of structural performance of IP-2 packages by advanced analytical simulation and full-scale drop test

    International Nuclear Information System (INIS)

    Two new types of IP-2 (Industrial Package Type 2) to transport low and intermediate level radioactive waste (LILW) steel drums from nuclear power plants to a disposal facility have been developed in accordance with the IAEA and Korean regulations for radioactive materials. According to the regulations, both packages must preserve their structural performance after they are subjected to 0.9 m free drop tests, which are prescribed as normal conditions. In this study, an advanced analytical simulation and an evaluation process using the finite element (FE) method have been developed for the design assessment of the newly developed IP-2s. Then, analytical simulations for the various drop orientations were performed to evaluate the structural performance of the packages and demonstrate their compliance with the regulatory requirements. Also, full-scale drop tests were carried out to verify the numerical tools and modeling methodology used in the analyses and to confirm the performance of the IP-2s. In addition, parametric studies are carried out to investigate the sensitivity of the analytical variables, such as the material model and modeling methodology. In addition, this paper intends to provide basic guidance on the analytical simulation and evaluation process specifically for Korean types of transport packages, because numerous transport packages must now be developed for the various kinds of LILW that have accumulated in temporary storage facilities in Korea.

  13. Scaling and automation of a high-throughput single-cell-derived tumor sphere assay chip.

    Science.gov (United States)

    Cheng, Yu-Heng; Chen, Yu-Chih; Brien, Riley; Yoon, Euisik

    2016-10-01

    Recent research suggests that cancer stem-like cells (CSCs) are the key subpopulation for tumor relapse and metastasis. Due to cancer plasticity in surface antigen and enzymatic activity markers, functional tumorsphere assays are promising alternatives for CSC identification. To reliably quantify rare CSCs (1-5%), thousands of single-cell suspension cultures are required. While microfluidics is a powerful tool in handling single cells, previous works provide limited throughput and lack automatic data analysis capability required for high-throughput studies. In this study, we present the scaling and automation of high-throughput single-cell-derived tumor sphere assay chips, facilitating the tracking of up to ∼10 000 cells on a chip with ∼76.5% capture rate. The presented cell capture scheme guarantees sampling a representative population from the bulk cells. To analyze thousands of single-cells with a variety of fluorescent intensities, a highly adaptable analysis program was developed for cell/sphere counting and size measurement. Using a Pluronic® F108 (poly(ethylene glycol)-block-poly(propylene glycol)-block-poly(ethylene glycol)) coating on polydimethylsiloxane (PDMS), a suspension culture environment was created to test a controversial hypothesis: whether larger or smaller cells are more stem-like defined by the capability to form single-cell-derived spheres. Different cell lines showed different correlations between sphere formation rate and initial cell size, suggesting heterogeneity in pathway regulation among breast cancer cell lines. More interestingly, by monitoring hundreds of spheres, we identified heterogeneity in sphere growth dynamics, indicating the cellular heterogeneity even within CSCs. These preliminary results highlight the power of unprecedented high-throughput and automation in CSC studies.

  14. Thermal simulation for the chip model based on RCP package%基于RCP封装的芯片模型电热模拟

    Institute of Scientific and Technical Information of China (English)

    张路

    2015-01-01

    基于集成电路重分布封装技术(redistributed chip packaging,RCP)的发展,通过提取芯片封装体的具体参数,建立并优化了RCP芯片的热学模型.采用有限元的方法计算了该模型在一定热耗散功率下,施加不同风速条件时的温度分布情况,结果表明:强制对流条件的施加显著增强了RCP芯片封装体的散热能力,4m/s的风速可使其系统热阻降低58%,但是随着风速的增大,其影响不断减弱.所得出的具体风速与芯片结温的关系,可为RCP封装技术的散热设计提供有价值的参考.

  15. A broadband chip-scale optical frequency synthesizer at 2.7 × 10−16 relative uncertainty

    OpenAIRE

    Huang, Shu-Wei; Yang, Jinghui; Yu, Mingbin; McGuyer, Bart H.; Kwong, Dim-Lee; Zelevinsky, Tanya; Wong, Chee Wei

    2016-01-01

    Optical frequency combs—coherent light sources that connect optical frequencies with microwave oscillations—have become the enabling tool for precision spectroscopy, optical clockwork, and attosecond physics over the past decades. Current benchmark systems are self-referenced femtosecond mode-locked lasers, but Kerr nonlinear dynamics in high-Q solid-state microresonators has recently demonstrated promising features as alternative platforms. The advance not only fosters studies of chip-scale ...

  16. Development of 3D human intestinal equivalents for substance testing in microliter-scale on a multi-organ-chip

    OpenAIRE

    Jaenicke, Annika; Tordy, Dominique; Groeber, Florian; Hansmann, Jan; Nietzer, Sarah; Tripp, Carolin; Walles, Heike; Lauster, Roland; Marx, Uwe

    2013-01-01

    First published by BioMed Central: Jaenicke, Annika; Tordy, Dominique; Groeber, Florian; Hansmann, Jan; Nietzer, Sarah; Tripp, Carolin; Walles, Heike; Lauster, Roland; Marx, Uwe: Development of 3D human intestinal equivalents for substance testing in microliter-scale on a multi-organ-chip. - In: BMC Proceedings. - ISSN 1753-6561 (online). - 7 (2013), suppl. 6, P65. - doi:10.1186/1753-6561-7-S6-P65.

  17. A wafer-scale packaging structure with monolithic microwave integrated circuits and passives embedded in a silicon substrate for multichip modules for radio frequency applications

    Science.gov (United States)

    Geng, Fei; Ding, Xiao-yun; Xu, Gao-wei; Luo, Le

    2009-10-01

    A wafer-level packaging structure with chips and passive components embedded in a silicon substrate for multichip modules (MCM) is proposed for radio frequency (RF) applications. The packaging structure consists of two layers of benzocyclobutene (BCB) films and three layers of metalized films, in which the monolithic microwave ICs (MMICs), thin film resistors, striplines and microstrip lines are integrated. The low resistivity silicon wafer with etched cavities is used as a substrate. The BCB films serve as interlayer dielectrics (ILDs). Wirebonding gold bumps are used as electric interconnections between different layers, which eliminate the need of preparing vias by costly procedures including dry etching, metal sputtering and electroplating. The chemical mechanical planarization (CMP) is used to uncover the gold bumps, and the BCB curing profile is optimized to obtain the appropriate BCB film for CMP process. In this work, the thermal, mechanical, electrical as well as RF properties of the packaging structure are investigated. The packaging thermal resistance can be controlled below 2 °C W-1. The average shear strength of the gold bumps on the BCB surface is about 70 MPa. In addition, a Kelvin test structure is fabricated for resistance testing of the vertical vias. The performances of MMIC and interconnection structure at high frequency are simulated and tested. The testing results reveal that the slight shifting of S-parameter curves of the packaged MMIC indicates perfect transmission characteristics at high frequency. For the transition structure of transmission line, the experimental results are compatible with the simulation results. The insertion loss (S21) is below 0.4 dB from 0 to 40 GHz and the return loss (S11) is less than -20 dB from 0 to 40 GHz. For a low noise amplifier (LNA) chip, the S21 shifting caused by the packaging structure is below 0.5 dB, and S11 is less than -10 dB from 8 GHz to 14 GHz.

  18. A wafer-scale packaging structure with monolithic microwave integrated circuits and passives embedded in a silicon substrate for multichip modules for radio frequency applications

    International Nuclear Information System (INIS)

    A wafer-level packaging structure with chips and passive components embedded in a silicon substrate for multichip modules (MCM) is proposed for radio frequency (RF) applications. The packaging structure consists of two layers of benzocyclobutene (BCB) films and three layers of metalized films, in which the monolithic microwave ICs (MMICs), thin film resistors, striplines and microstrip lines are integrated. The low resistivity silicon wafer with etched cavities is used as a substrate. The BCB films serve as interlayer dielectrics (ILDs). Wirebonding gold bumps are used as electric interconnections between different layers, which eliminate the need of preparing vias by costly procedures including dry etching, metal sputtering and electroplating. The chemical mechanical planarization (CMP) is used to uncover the gold bumps, and the BCB curing profile is optimized to obtain the appropriate BCB film for CMP process. In this work, the thermal, mechanical, electrical as well as RF properties of the packaging structure are investigated. The packaging thermal resistance can be controlled below 2 °C W−1. The average shear strength of the gold bumps on the BCB surface is about 70 MPa. In addition, a Kelvin test structure is fabricated for resistance testing of the vertical vias. The performances of MMIC and interconnection structure at high frequency are simulated and tested. The testing results reveal that the slight shifting of S-parameter curves of the packaged MMIC indicates perfect transmission characteristics at high frequency. For the transition structure of transmission line, the experimental results are compatible with the simulation results. The insertion loss (S21) is below 0.4 dB from 0 to 40 GHz and the return loss (S11) is less than −20 dB from 0 to 40 GHz. For a low noise amplifier (LNA) chip, the S21 shifting caused by the packaging structure is below 0.5 dB, and S11 is less than −10 dB from 8 GHz to 14 GHz

  19. Developing technology for large-scale production of forest chips. Wood Energy Technology Programme 1999-2003. Final report

    Energy Technology Data Exchange (ETDEWEB)

    NONE

    2004-07-01

    The national Wood Energy Technology Programme was carried out by Tekes during the period 1999- 2003 to develop efficient technology for large- scale production of forest chips from small- sized trees and logging residues. This is the final report of the programme, and it outlines the general development of forest chip procurement and use during the programme period. In 2002, a sub-programme was established to address small-scale production and use of wood fuels. This sub-programme will continue to the end of 2004, and it is not reported here. The programme was coordinated by VTT Processes. As of January 2004, the programme consisted of 44 public research projects, 46 industrial or product development projects, and 29 demonstration projects. Altogether, 27 research organizations and 53 enterprises participated. The total cost of the programme was 42 M euro of which 13 M euro was provided by Tekes. The Ministry of Trade and Industry provided investment aid for the new technology employed in the demonstration projects. When the programme was launched at the end of the 1990s, the major barriers to the use of forest chips were high cost of production, shortage of reliable chip procurement organizations, and the unsatisfactory quality of fuel. Accordingly, the programme focused largely on these problems. In addition, upgrading of the fuel properties of bark was also studied. The production of forest chips must be adapted to the existing operating environment and infrastructure. In Finland, these are charaterized by rich bio-mass potential, a sophisticated and efficient organization for the procurement of industrial timber, a large capacity of heating and CHP plants to use wood fuels, the possibility to co-fire wood and peat, and the unreserved acceptance of society at large. A goal of Finnish energy and climate strategies is to use 5 million m3 (0.9 Mtoe) chips annually by 2010. The Wood Energy Technology Programme was an important link in the long chain of activities

  20. Comprehensive Investigation on Current Imbalance among Parallel Chips inside MW-Scale IGBT Power Modules

    DEFF Research Database (Denmark)

    Wu, Rui; Smirnova, Liudmila; Wang, Huai;

    2015-01-01

    With the demands for increasing the power rating and improving reliability level of the high power IGBT modules, there are further needs of understanding how to achieve stable paralleling and identical current sharing between the chips. This paper investigates the stray parameters imbalance among...... parallel chips inside the 1.7 kV/1 kA high power IGBT modules at different frequencies by Ansys Q3D parastics extractor. The resulted current imbalance is further confirmed by experimental measurement....

  1. Comprehensive Investigation on Current Imbalance among Parallel Chips inside MW-Scale IGBT Power Modules

    OpenAIRE

    Wu, Rui; Smirnova, Liudmila; Wang, Huai; Iannuzzo, Francesco; Blaabjerg, Frede

    2015-01-01

    With the demands for increasing the power rating and improving reliability level of the high power IGBT modules, there are further needs of understanding how to achieve stable paralleling and identical current sharing between the chips. This paper investigates the stray parameters imbalance among parallel chips inside the 1.7 kV/1 kA high power IGBT modules at different frequencies by Ansys Q3D parastics extractor. The resulted current imbalance is further confirmed by experimental measurement.

  2. Experimental and theoretical analyses of package-on-package structure under three-point bending loading

    Institute of Scientific and Technical Information of China (English)

    Jia Su; Wang Xi-Shu; Ren Huai-Hui

    2012-01-01

    High density packaging is developing toward miniaturization and integration,which causes many difficulties in designing,manufacturing,and reliability testing.Package-on-Package (PoP) is a promising three-dimensional high-density packaging method that integrates a chip scale package (CSP) in the top package and a fine-pitch ball grid array (FBGA) in the bottom package.In this paper,in-situ scanning electron microscopy (SEM) observation is carried out to detect the deformation and damage of the PoP structure under three-point bending loading.The results iudicate that the cracks occur in the die of the top package,then cause the crack deflection and bridging in the die attaching layer.Furthermore,the mechanical principles are used to analyse the cracking process of the PoP structure based on the multi-layer laminating hypothesis and the theoretical analysis results are found to be in good agreement with the experimental results.

  3. Chip-Scale Bioassays Based on Surface-Enhanced Raman Scattering: Fundamentals and Applications

    Energy Technology Data Exchange (ETDEWEB)

    Hye-Young Park

    2005-12-17

    This work explores the development and application of chip-scale bioassays based on surface-enhanced Raman scattering (SERS) for high throughput and high sensitivity analysis of biomolecules. The size effect of gold nanoparticles on the intensity of SERS is first presented. A sandwich immunoassay was performed using Raman-labeled immunogold nanoparticles with various sizes. The SERS responses were correlated to particle densities, which were obtained by atomic force microscopy (AFM). The response of individual particles was also investigated using Raman-microscope and an array of gold islands on a silicon substrate. The location and the size of individual particles were mapped using AFM. The next study describes a low-level detection of Escherichia coli 0157:H7 and simulants of biological warfare agents in a sandwich immunoassay format using SERS labels, which have been termed Extrinsic Raman labels (ERLs). A new ERL scheme based on a mixed monolayer is also introduced. The mixed monolayer ERLs were created by covering the gold nanoparticles with a mixture of two thiolates, one thiolate for covalently binding antibody to the particle and the other thiolate for producing a strong Raman signal. An assay platform based on mixed self-assembled monolayers (SAMs) on gold is then presented. The mixed SAMs were prepared from dithiobis(succinimidyl undecanoate) (DSU) to covalently bind antibodies on gold substrate and oligo(ethylene glycol)-terminated thiol to prevent nonspecific adsorption of antibodies. After the mixed SAMs surfaces, formed from various mole fraction of DSU were incubated with antibodies, AFM was used to image individual antibodies on the surface. The final study presents a collaborative work on the single molecule adsorption of YOYO-I labeled {lambda}-DNA at compositionally patterned SAMs using total internal reflection fluorescence microscopy. The role of solution pH, {lambda}-DNA concentration, and domain size was investigated. This work also revealed

  4. Chip-Scale Bioassays Based on Surface-Enhanced Raman Scattering: Fundamentals and Applications

    Energy Technology Data Exchange (ETDEWEB)

    Park, Hye-Young [Iowa State Univ., Ames, IA (United States)

    2005-01-01

    This work explores the development and application of chip-scale bioassays based on surface-enhanced Raman scattering (SERS) for high throughput and high sensitivity analysis of biomolecules. The size effect of gold nanoparticles on the intensity of SERS is first presented. A sandwich immunoassay was performed using Raman-labeled immunogold nanoparticles with various sizes. The SERS responses were correlated to particle densities, which were obtained by atomic force microscopy (AFM). The response of individual particles was also investigated using Raman-microscope and an array of gold islands on a silicon substrate. The location and the size of individual particles were mapped using AFM. The next study describes a low-level detection of Escherichia coli 0157:H7 and simulants of biological warfare agents in a sandwich immunoassay format using SERS labels, which have been termed Extrinsic Raman labels (ERLs). A new ERL scheme based on a mixed monolayer is also introduced. The mixed monolayer ERLs were created by covering the gold nanoparticles with a mixture of two thiolates, one thiolate for covalently binding antibody to the particle and the other thiolate for producing a strong Raman signal. An assay platform based on mixed self-assembled monolayers (SAMs) on gold is then presented. The mixed SAMs were prepared from dithiobis(succinimidyl undecanoate) (DSU) to covalently bind antibodies on gold substrate and oligo(ethylene glycol)-terminated thiol to prevent nonspecific adsorption of antibodies. After the mixed SAMs surfaces, formed from various mole fraction of DSU were incubated with antibodies, AFM was used to image individual antibodies on the surface. The final study presents a collaborative work on the single molecule adsorption of YOYO-I labeled {lambda}-DNA at compositionally patterned SAMs using total internal reflection fluorescence microscopy. The role of solution pH, {lambda}-DNA concentration, and domain size was investigated. This work also revealed

  5. Exploring massive, genome scale datasets with the GenometriCorr package.

    Directory of Open Access Journals (Sweden)

    Alexander Favorov

    2012-05-01

    Full Text Available UNLABELLED: We have created a statistically grounded tool for determining the correlation of genomewide data with other datasets or known biological features, intended to guide biological exploration of high-dimensional datasets, rather than providing immediate answers. The software enables several biologically motivated approaches to these data and here we describe the rationale and implementation for each approach. Our models and statistics are implemented in an R package that efficiently calculates the spatial correlation between two sets of genomic intervals (data and/or annotated features, for use as a metric of functional interaction. The software handles any type of pointwise or interval data and instead of running analyses with predefined metrics, it computes the significance and direction of several types of spatial association; this is intended to suggest potentially relevant relationships between the datasets. AVAILABILITY AND IMPLEMENTATION: The package, GenometriCorr, can be freely downloaded at http://genometricorr.sourceforge.net/. Installation guidelines and examples are available from the sourceforge repository. The package is pending submission to Bioconductor.

  6. Developing technology for large-scale production of forest chips. Wood Energy Technology Programme 1999-2003. Interim report

    Energy Technology Data Exchange (ETDEWEB)

    Hakkila, P. [VTT Processes, Espoo (Finland)

    2003-07-01

    Finland is enhancing its use of renewable sources in energy production. From the 1995 level, the use of renewable energy is to be increased by 50 % by 2010, and 100 % by 2025. Wood-based fuels will play a leading role in this development. The main source of wood-based fuels is processing residues from the forest industries. However, as all processing residues are already in use, an increase is possible only as far as the capacity and wood consumption of the forest industries grow. Energy policy affects the production and availability of processing residues only indirectly. Another large source of wood-based energy is forest fuels, consisting of traditional firewood and chips comminuted from low-quality biomass. It is estimated that the reserve of technically harvest-able forest biomass is 10-16 Mm' annually, when no specific cost limit is applied. This corresponds to 2-3 Mtoe or 6-9 % of the present consumption of primary energy in Finland. How much of this re-serve it will actually be possible to harvest and utilize depends on the cost competitiveness of forest chips against alternative sources of energy. A goal of Finnish energy and climate strategies is to use 5 Mm' forest chips annually by 2010. The use of wood fuels is being promoted by means of taxation, investment aid and support for chip production from young forests. Furthermore, research and development is being supported in order to create techno-economic conditions for the competitive production of forest chips. In 1999, the National Technology Agency Tekes established the five-year Wood Energy Technology Programme to stimulate the development of efficient systems for the large-scale production of forest chips. Key tar-gets are competitive costs, reliable supply and good quality chips. The two guiding principles of the programme are: (1) close cooperation between researchers and practitioners and (2) to apply research and development to the practical applications and commercialization. As of

  7. Thermal hehavior of Surface Mounted Devices (SMD) packaging

    Science.gov (United States)

    Bloch, Werner; Moeller, Werner

    The thermal behavior of Surface Mounted Devices (SMD) packaging was investigated on an easily variable type. The effect of basic materials, chip carriers, and bonding, soldering, glueing and casting techniques was examined, considering the most important quantities, switching time and power. The test results show that cooling measures in the chip domain, such as chip bonding, chip casting, and chip carrier lining, are especially efficient for short switching times. The basic materials, even with heat sinks, become only important for longer switching times. The chip temperature of a conventional FR4/LCCC packaging was halved by the application of novel packaging materials, without changing the cooling mechanisms and the power.

  8. Chip, Chip, Hooray!

    Science.gov (United States)

    Kelly, Susan

    2001-01-01

    Presents a science laboratory using different brands of potato chips in which students test their oiliness, size, thickness, saltiness, quality, and cost, then analyze the results to determine the best chip. Gives a brief history of potato chips. (YDS)

  9. A broadband chip-scale optical frequency synthesizer at 2.7 × 10(-16) relative uncertainty.

    Science.gov (United States)

    Huang, Shu-Wei; Yang, Jinghui; Yu, Mingbin; McGuyer, Bart H; Kwong, Dim-Lee; Zelevinsky, Tanya; Wong, Chee Wei

    2016-04-01

    Optical frequency combs-coherent light sources that connect optical frequencies with microwave oscillations-have become the enabling tool for precision spectroscopy, optical clockwork, and attosecond physics over the past decades. Current benchmark systems are self-referenced femtosecond mode-locked lasers, but Kerr nonlinear dynamics in high-Q solid-state microresonators has recently demonstrated promising features as alternative platforms. The advance not only fosters studies of chip-scale frequency metrology but also extends the realm of optical frequency combs. We report the full stabilization of chip-scale optical frequency combs. The microcomb's two degrees of freedom, one of the comb lines and the native 18-GHz comb spacing, are simultaneously phase-locked to known optical and microwave references. Active comb spacing stabilization improves long-term stability by six orders of magnitude, reaching a record instrument-limited residual instability of [Formula: see text]. Comparing 46 nitride frequency comb lines with a fiber laser frequency comb, we demonstrate the unprecedented microcomb tooth-to-tooth relative frequency uncertainty down to 50 mHz and 2.7 × 10(-16), heralding novel solid-state applications in precision spectroscopy, coherent communications, and astronomical spectrography.

  10. A broadband chip-scale optical frequency synthesizer at 2.7 × 10(-16) relative uncertainty.

    Science.gov (United States)

    Huang, Shu-Wei; Yang, Jinghui; Yu, Mingbin; McGuyer, Bart H; Kwong, Dim-Lee; Zelevinsky, Tanya; Wong, Chee Wei

    2016-04-01

    Optical frequency combs-coherent light sources that connect optical frequencies with microwave oscillations-have become the enabling tool for precision spectroscopy, optical clockwork, and attosecond physics over the past decades. Current benchmark systems are self-referenced femtosecond mode-locked lasers, but Kerr nonlinear dynamics in high-Q solid-state microresonators has recently demonstrated promising features as alternative platforms. The advance not only fosters studies of chip-scale frequency metrology but also extends the realm of optical frequency combs. We report the full stabilization of chip-scale optical frequency combs. The microcomb's two degrees of freedom, one of the comb lines and the native 18-GHz comb spacing, are simultaneously phase-locked to known optical and microwave references. Active comb spacing stabilization improves long-term stability by six orders of magnitude, reaching a record instrument-limited residual instability of [Formula: see text]. Comparing 46 nitride frequency comb lines with a fiber laser frequency comb, we demonstrate the unprecedented microcomb tooth-to-tooth relative frequency uncertainty down to 50 mHz and 2.7 × 10(-16), heralding novel solid-state applications in precision spectroscopy, coherent communications, and astronomical spectrography. PMID:27152341

  11. A broadband chip-scale optical frequency synthesizer at 2.7 × 10−16 relative uncertainty

    Science.gov (United States)

    Huang, Shu-Wei; Yang, Jinghui; Yu, Mingbin; McGuyer, Bart H.; Kwong, Dim-Lee; Zelevinsky, Tanya; Wong, Chee Wei

    2016-01-01

    Optical frequency combs—coherent light sources that connect optical frequencies with microwave oscillations—have become the enabling tool for precision spectroscopy, optical clockwork, and attosecond physics over the past decades. Current benchmark systems are self-referenced femtosecond mode-locked lasers, but Kerr nonlinear dynamics in high-Q solid-state microresonators has recently demonstrated promising features as alternative platforms. The advance not only fosters studies of chip-scale frequency metrology but also extends the realm of optical frequency combs. We report the full stabilization of chip-scale optical frequency combs. The microcomb’s two degrees of freedom, one of the comb lines and the native 18-GHz comb spacing, are simultaneously phase-locked to known optical and microwave references. Active comb spacing stabilization improves long-term stability by six orders of magnitude, reaching a record instrument-limited residual instability of 3.6mHz/τ. Comparing 46 nitride frequency comb lines with a fiber laser frequency comb, we demonstrate the unprecedented microcomb tooth-to-tooth relative frequency uncertainty down to 50 mHz and 2.7 × 10−16, heralding novel solid-state applications in precision spectroscopy, coherent communications, and astronomical spectrography. PMID:27152341

  12. Very large scale heterogeneous integration (VLSHI) and wafer-level vacuum packaging for infrared bolometer focal plane arrays

    Science.gov (United States)

    Forsberg, Fredrik; Roxhed, Niclas; Fischer, Andreas C.; Samel, Björn; Ericsson, Per; Hoivik, Nils; Lapadatu, Adriana; Bring, Martin; Kittilsland, Gjermund; Stemme, Göran; Niklaus, Frank

    2013-09-01

    Imaging in the long wavelength infrared (LWIR) range from 8 to 14 μm is an extremely useful tool for non-contact measurement and imaging of temperature in many industrial, automotive and security applications. However, the cost of the infrared (IR) imaging components has to be significantly reduced to make IR imaging a viable technology for many cost-sensitive applications. This paper demonstrates new and improved fabrication and packaging technologies for next-generation IR imaging detectors based on uncooled IR bolometer focal plane arrays. The proposed technologies include very large scale heterogeneous integration for combining high-performance, SiGe quantum-well bolometers with electronic integrated read-out circuits and CMOS compatible wafer-level vacuum packing. The fabrication and characterization of bolometers with a pitch of 25 μm × 25 μm that are arranged on read-out-wafers in arrays with 320 × 240 pixels are presented. The bolometers contain a multi-layer quantum well SiGe thermistor with a temperature coefficient of resistance of -3.0%/K. The proposed CMOS compatible wafer-level vacuum packaging technology uses Cu-Sn solid-liquid interdiffusion (SLID) bonding. The presented technologies are suitable for implementation in cost-efficient fabless business models with the potential to bring about the cost reduction needed to enable low-cost IR imaging products for industrial, security and automotive applications.

  13. Advanced organics for electronic substrates and packages

    CERN Document Server

    Fletcher, Andrew E

    1992-01-01

    Advanced Organics for Electronic Substrates and Packages provides information on packaging, which is one of the most technologically intensive activities in the electronics industry. The electronics packaging community has realized that while semiconductor devices continue to be improved upon for performance, cost, and reliability, it is the interconnection or packaging of these devices that will limit the performance of the systems. Technology must develop packaging for transistor chips, with high levels of performance and integration providing cooling, power, and interconnection, and yet pre

  14. Large-scale analysis of antisense transcription in wheat using the Affymetrix GeneChip Wheat Genome Array

    Directory of Open Access Journals (Sweden)

    Settles Matthew L

    2009-05-01

    Full Text Available Abstract Background Natural antisense transcripts (NATs are transcripts of the opposite DNA strand to the sense-strand either at the same locus (cis-encoded or a different locus (trans-encoded. They can affect gene expression at multiple stages including transcription, RNA processing and transport, and translation. NATs give rise to sense-antisense transcript pairs and the number of these identified has escalated greatly with the availability of DNA sequencing resources and public databases. Traditionally, NATs were identified by the alignment of full-length cDNAs or expressed sequence tags to genome sequences, but an alternative method for large-scale detection of sense-antisense transcript pairs involves the use of microarrays. In this study we developed a novel protocol to assay sense- and antisense-strand transcription on the 55 K Affymetrix GeneChip Wheat Genome Array, which is a 3' in vitro transcription (3'IVT expression array. We selected five different tissue types for assay to enable maximum discovery, and used the 'Chinese Spring' wheat genotype because most of the wheat GeneChip probe sequences were based on its genomic sequence. This study is the first report of using a 3'IVT expression array to discover the expression of natural sense-antisense transcript pairs, and may be considered as proof-of-concept. Results By using alternative target preparation schemes, both the sense- and antisense-strand derived transcripts were labeled and hybridized to the Wheat GeneChip. Quality assurance verified that successful hybridization did occur in the antisense-strand assay. A stringent threshold for positive hybridization was applied, which resulted in the identification of 110 sense-antisense transcript pairs, as well as 80 potentially antisense-specific transcripts. Strand-specific RT-PCR validated the microarray observations, and showed that antisense transcription is likely to be tissue specific. For the annotated sense

  15. Wafer-level scale package of MEMS device by eutectic bonding method

    Science.gov (United States)

    Chen, Sihai; Ma, Hong; Chen, Mingxiang; Xiong, Tao; Liu, Sheng; Yi, Xinjian

    2004-01-01

    This paper reports the preliminary results for an on-going program in wafer-level MEMS package. In this particular paper, three closed-loop microheaters of 5μm, 7μm and 9μm width were designed. By reactive ion sputtering technique, two classes of samples were presented. The first one was first co-sputtered with nickel / chromium (Ni/Cr) alloy and then sputtered with gold(Au) metal as heating material; the second one was sputtered with Cr, tin (Sn) and Au respectively as heating material. The bonding of the former sample based on the Ni/Cr and Au heating material failed. The eutectic bonding experiment of the later sample based on the Cr, Sn and Au heating material by global heating method was completed in annealing oven at temperature of about 400 deg. C. for 20 minutes. The SEM testing result showed the eutectic bonding of Au-Sn by global heating was successful. More results will be reported in future.

  16. Wafer-level-scale package of MEMS device by eutectic bonding method

    Science.gov (United States)

    Chen, Sihai; Ma, Hong; Chen, Mingxiang; Xiong, Tao; Liu, Sheng; Yi, Xinjian

    2003-12-01

    This paper reports the preliminary results for an on-going program in wafer-level MEMS package. In this particular paper, three closed-loop microheaters of 5μm, 7μm and 9μm width were designed. By reactive ion sputtering technique, two classes of samples were presented. The first one was first co-sputtered with nickel / chromium (Ni/Cr) alloy and then sputtered with gold(Au) metal as heating material; the second one was sputtered with Cr, tin (Sn) and Au respectively as heating material. The bonding of the former sample based on the Ni/Cr and Au heating material failed. The eutectic bonding experiment of the later sample based on the Cr, Sn and Au heating material by global heating method was completed in annealing oven at temperature of about 400 for 20 minutes. The SEM testing result showed the eutectic bonding of Au-Sn by global heating was successful. More results will be reported in future.

  17. On-chip photonic interconnects a computer architect's perspective

    CERN Document Server

    Nitta, Christopher J; Akella, Venkatesh

    2013-01-01

    As the number of cores on a chip continues to climb, architects will need to address both bandwidth and power consumption issues related to the interconnection network. Electrical interconnects are not likely to scale well to a large number of processors for energy efficiency reasons, and the problem is compounded by the fact that there is a fixed total power budget for a die, dictated by the amount of heat that can be dissipated without special (and expensive) cooling and packaging techniques. Thus, there is a need to seek alternatives to electrical signaling for on-chip interconnection appli

  18. GRASP92: a package for large-scale relativistic atomic structure calculations

    Science.gov (United States)

    Parpia, F. A.; Froese Fischer, C.; Grant, I. P.

    2006-12-01

    Program summaryTitle of program: GRASP92 Catalogue identifier: ADCU_v1_1 Program summary URL:http://cpc.cs.qub.ac.uk/summaries/ADCU_v1_1 Program obtainable from: CPC Program Library, Queen's University of Belfast, N. Ireland Licensing provisions: no Programming language used: Fortran Computer: IBM POWERstation 320H Operating system: IBM AIX 3.2.5+ RAM: 64M words No. of lines in distributed program, including test data, etc.: 65 224 No of bytes in distributed program, including test data, etc.: 409 198 Distribution format: tar.gz Catalogue identifier of previous version: ADCU_v1_0 Journal reference of previous version: Comput. Phys. Comm. 94 (1996) 249 Does the new version supersede the previous version?: Yes Nature of problem: Prediction of atomic spectra—atomic energy levels, oscillator strengths, and radiative decay rates—using a 'fully relativistic' approach. Solution method: Atomic orbitals are assumed to be four-component spinor eigenstates of the angular momentum operator, j=l+s, and the parity operator Π=βπ. Configuration state functions (CSFs) are linear combinations of Slater determinants of atomic orbitals, and are simultaneous eigenfunctions of the atomic electronic angular momentum operator, J, and the atomic parity operator, P. Lists of CSFs are either explicitly prescribed by the user or generated from a set of reference CSFs, a set of subshells, and rules for deriving other CSFs from these. Approximate atomic state functions (ASFs) are linear combinations of CSFs. A variational functional may be constructed by combining expressions for the energies of one or more ASFs. Average level (AL) functionals are weighted sums of energies of all possible ASFs that may be constructed from a set of CSFs; the number of ASFs is then the same as the number, n, of CSFs. Optimal level (OL) functionals are weighted sums of energies of some subset of ASFs; the GRASP92 package is optimized for this latter class of functionals. The composition of an ASF in terms

  19. Atom Chips

    CERN Document Server

    Folman, R; Cassettari, D; Hessmo, B; Maier, T; Schmiedmayer, J; Folman, Ron; Krüger, Peter; Cassettari, Donatella; Hessmo, Björn; Maier, Thomas

    1999-01-01

    Atoms can be trapped and guided using nano-fabricated wires on surfaces, achieving the scales required by quantum information proposals. These Atom Chips form the basis for robust and widespread applications of cold atoms ranging from atom optics to fundamental questions in mesoscopic physics, and possibly quantum information systems.

  20. Infrared vertically-illuminated photodiode for chip alignment feedback

    Science.gov (United States)

    Alloatti, L.; Ram, R. J.

    2016-08-01

    We report on vertically-illuminated photodiodes fabricated in the GlobalFoundries 45nm 12SOI node and on a packaging concept for optically-interconnected chips. The photodiodes are responsive at 1180 nm -a wavelength currently used in chip-to-chip communications. They have further a wide field-of-view which enables chip-to-board positional feedback in chip-board assemblies. Monolithic integration enables on-chip processing of the positional data.

  1. Infrared vertically-illuminated photodiode for chip alignment feedback

    CERN Document Server

    Alloatti, Luca

    2016-01-01

    We report on vertically-illuminated photodiodes fabricated in the GlobalFoundries 45nm 12SOI node and on a packaging concept for optically-interconnected chips. The photodiodes are responsive at 1180 nm, a wavelength currently used in chip-to-chip communications. They have further a wide field-of-view which enables chip-to-board positional feedback in chip-board assemblies. Monolithic integration enables on-chip processing of the positional data.

  2. Health and economic benefits of scaling up a home-based neonatal care package in rural India: a modelling analysis.

    Science.gov (United States)

    Nandi, Arindam; Colson, Abigail R; Verma, Amit; Megiddo, Itamar; Ashok, Ashvin; Laxminarayan, Ramanan

    2016-06-01

    Approximately 900 000 newborn children die every year in India, accounting for 28% of neonatal deaths globally. In 2011, India introduced a home-based newborn care (HBNC) package to be delivered by community health workers across rural areas. We estimate the disease and economic burden that could be averted by scaling up the HBNC in rural India using IndiaSim, an agent-based simulation model, to examine two interventions. In the first intervention, the existing community health worker network begins providing HBNC for rural households without access to home- or facility-based newborn care, as introduced by India's recent programme. In the second intervention, we consider increased coverage of HBNC across India so that total coverage of neonatal care (HBNC or otherwise) in the rural areas of each state reaches at least 90%. We find that compared with a baseline of no coverage, providing the care package through the existing network of community health workers could avert 48 [95% uncertainty range (UR) 34-63] incident cases of severe neonatal morbidity and 5 (95% UR 4-7) related deaths, save $4411 (95% UR $3088-$5735) in out-of-pocket treatment costs, and provide $285 (95% UR $200-$371) in value of insurance per 1000 live births in rural India. Increasing the coverage of HBNC to 90% will avert an additional 9 (95% UR 7-12) incident cases, 1 death (95% UR 0.72-1.33), and $613 (95% UR $430-$797) in out-of-pocket expenditures, and provide $55 (95% UR $39-$72) in incremental value of insurance per 1000 live births. Intervention benefits are greater for lower socioeconomic groups and in the poorer states of Chhattisgarh, Uttarakhand, Bihar, Assam and Uttar Pradesh. PMID:26561440

  3. Modeling of shielding benchmark for Na-24 γ-rays using scale code package and QAD-CGGP code

    International Nuclear Information System (INIS)

    The benchmark data were recently published for 1.37 and 2.75 MeV photons emitted by an Na-24 uniform disc source penetrating shields of six two-layer combinations, namely, 12''Al+Fe, 12''+Pb, 6''Fe+Al, 6''Fe+Pb, 4''Pb+Al, and 4''Pb+Fe. These benchmark data fill a gap in the energy range of practical interest and provide useful reference values for computational method evaluation. In order to evaluate the computational methods incorporated into widely used shielding codes SCALE and QAD we compared the benchmark data with results of benchmark modeling with these codes. Using the functional module SAS4 of SCALE4 modular code package and the point kernel code system for gamma-ray shielding calculations QAD-CGGP scalar flux density spectra in benchmark energy group structure for three two-layer combinations were calculated. The comparison of the benchmark data and the results obtained showed that QAD-CGGP and SAS4 results are in good agreement, but the benchmark experimental data differ significantly from the both of them. (author)

  4. Three-Dimensional Architecture at Chip Level for Large-Scale-Integration of Superconducting Quantum Electronic Devices

    Science.gov (United States)

    Göppl, Martin; Kurpiers, Philipp; Wallraff, Andreas

    We propose a novel way to realize three-dimensional circuit QED systems at chip level. System components such as qubits, transmission lines, capacitors, inductors or cross-overs can be implemented as suspended, electromagnetically shielded and optionally, as hermetically sealed structures. Compared to known state-of-the-art devices, volumes of dielectrics penetrated by electromagnetic fields can be drastically reduced. Our intention is to harness process technologies for very-large-scale-integration, reliably applied and improved over decades in micro-sensor- and semiconductor industry, for the realization of highly integrated circuit QED systems. Process capabilities are demonstrated by fabricating first exploratory devices using the back-end-of-line part of a commercial 180 nm CMOS foundry process in conjunction with HF vapor phase release etching.

  5. Physics of Failure Analysis of Xilinx Flip Chip CCGA Packages: Effects of Mission Environments on Properties of LP2 Underfill and ATI Lid Adhesive Materials

    Science.gov (United States)

    Suh, Jong-ook

    2013-01-01

    The Xilinx Virtex 4QV and 5QV (V4 and V5) are next-generation field-programmable gate arrays (FPGAs) for space applications. However, there have been concerns within the space community regarding the non-hermeticity of V4/V5 packages; polymeric materials such as the underfill and lid adhesive will be directly exposed to the space environment. In this study, reliability concerns associated with the non-hermeticity of V4/V5 packages were investigated by studying properties and behavior of the underfill and the lid adhesvie materials used in V4/V5 packages.

  6. Fully Streched Single DNA Molecules in a Nanofluidic Chip Show Large-Scale Structural Variation

    DEFF Research Database (Denmark)

    Pedersen, Jonas Nyvold; Marie, Rodolphe; Bauer, D. L.;

    2013-01-01

    When stretching and imaging DNA molecules in nanofluidic devices, it is important to know the relation between the physical length as measured in the lab and the distance along the contour of the DNA. Here a single DNA molecule longer than 1 Mbp is loaded into a nanofluidic device consisting of two...... the contour length of the DNA, and (iii) without having the full DNA molecule inside the field-of-view. The analysis is based on the transverse motion of the DNA due its Brownian motion, i.e. the DNA's response to the thermal fluctuations of the liquid surrounding it. The parameter values obtained by fitting...... reflects the local AT/GC-content. Single molecules are loaded into the chip and imaged. Due to the almost complete stretching of the DNA, structural variations in the size range from kbp to Mbp can be detected and quantified from the melting pattern alone....

  7. Optimization and pilot-scale testing of modified atmosphere packaging of irradiated fresh 'Carabao' mango (Mangifera indica L.) fruits

    International Nuclear Information System (INIS)

    Modified atmosphere packaging (MAP) for fresh 'Carabao' mango was optimized with respect to the number of pinholes needed for a fixed respiration rate, fill weight, oxygen transmission rate (OTR), and bag surface area. Computer simulations showed that 38-mm polyethylene or 20-mm Zeolite film with 52 or 44 pinholes, respectively, could be used for packing 5 kg of fruit in a bag with a surface area of approximately 0.80 sq m if held at 12.5 deg C. Subsequent laboratory trials using fruits irradiated at 150-250 Gy showed that 50 pinholes made with a 26-gauge cold needle could be used for both films; O2 levels during storage were close to the recommended levels of 3-5%. Pilot-scale trials using fruits harvested during the on and off-season show that both irradiation at 150-250 Gy and MAP could retard ripening and reduce softening. After 4 wk of storage at 12.5 deg C, MAP fruits were at a half-ripe and slightly-firm stage of ripeness, with minimal development of disease. Sensory tests at the table-ripe stage showed that irradiated MAP-stored fruits were acceptable

  8. Continuous using of the scaling factors for radionuclide evaluation in the packaged solid wastes originated from the Japanese Nuclear Power Plants since 2003

    International Nuclear Information System (INIS)

    The amounts and concentration of the nuclides in the waste packages are estimated by measuring some key nuclides, mostly gamma emitters, from outside of the packages and by applying the scaling factor method (using the relationship between some easy to measure key nuclides and the other difficult to measure nuclides). The solid wastes are classified into two kinds of packages: homogeneous solid wastes made from concentrated liquid wastes and spent fuels solidified with cement asphalt, or plastics and heterogeneous solid wastes made of cutting metals, compacted or fused filters solidified with mortars. Japan Nuclear Energy Safety Organization (JNES) established in 2005 is in charge of the confirmation of the inside contents with radionuclide information and compliance with formalities for safety maintenance and control. (S. Ohno)

  9. Packaging the MAMA module

    Science.gov (United States)

    Seals, J. Dennis

    1994-10-01

    The MAMA (Mixed Arithmetic, Multiprocessing Array) module is being developed to evaluate new packaging technologies and processing paradigms for advanced military processing systems. The architecture supports a tight mix of signal, data,and I/O processing at GFLOP throughput rates. It is fabricated using only commercial-on-the-sehlf (COTS) chips and will provide a high level of durability. Its attributes are largely the result of two new interconnection and packaging technologies. Chip-in-board packaging is used to reduce local x-y communication delays and solder joints, while significantly improving board-level packaging density. A unique 3-D interconnection technology called a cross-over cell has been developed to reduce board-to-board communication delays, drive power, glue logic, and card-edge pin-outs. These technologies enable true 3-D structures that are form, fit and connector compatible with conventional line-replacable modules. The module's design rational, packaging technology, and basic architecture will be presented in this paper.

  10. Mechanically Flexible Active Silicon Chips and Systems Project

    Data.gov (United States)

    National Aeronautics and Space Administration — Using innovative chip thinning technology married with recently available packaging technology, this effort will produce Mechanically Flexible Multifunctional...

  11. Reducing weight precision of convolutional neural networks towards large-scale on-chip image recognition

    Science.gov (United States)

    Ji, Zhengping; Ovsiannikov, Ilia; Wang, Yibing; Shi, Lilong; Zhang, Qiang

    2015-05-01

    In this paper, we develop a server-client quantization scheme to reduce bit resolution of deep learning architecture, i.e., Convolutional Neural Networks, for image recognition tasks. Low bit resolution is an important factor in bringing the deep learning neural network into hardware implementation, which directly determines the cost and power consumption. We aim to reduce the bit resolution of the network without sacrificing its performance. To this end, we design a new quantization algorithm called supervised iterative quantization to reduce the bit resolution of learned network weights. In the training stage, the supervised iterative quantization is conducted via two steps on server - apply k-means based adaptive quantization on learned network weights and retrain the network based on quantized weights. These two steps are alternated until the convergence criterion is met. In this testing stage, the network configuration and low-bit weights are loaded to the client hardware device to recognize coming input in real time, where optimized but expensive quantization becomes infeasible. Considering this, we adopt a uniform quantization for the inputs and internal network responses (called feature maps) to maintain low on-chip expenses. The Convolutional Neural Network with reduced weight and input/response precision is demonstrated in recognizing two types of images: one is hand-written digit images and the other is real-life images in office scenarios. Both results show that the new network is able to achieve the performance of the neural network with full bit resolution, even though in the new network the bit resolution of both weight and input are significantly reduced, e.g., from 64 bits to 4-5 bits.

  12. Edible packaging materials.

    Science.gov (United States)

    Janjarasskul, Theeranun; Krochta, John M

    2010-01-01

    Research groups and the food and pharmaceutical industries recognize edible packaging as a useful alternative or addition to conventional packaging to reduce waste and to create novel applications for improving product stability, quality, safety, variety, and convenience for consumers. Recent studies have explored the ability of biopolymer-based food packaging materials to carry and control-release active compounds. As diverse edible packaging materials derived from various by-products or waste from food industry are being developed, the dry thermoplastic process is advancing rapidly as a feasible commercial edible packaging manufacturing process. The employment of nanocomposite concepts to edible packaging materials promises to improve barrier and mechanical properties and facilitate effective incorporation of bioactive ingredients and other designed functions. In addition to the need for a more fundamental understanding to enable design to desired specifications, edible packaging has to overcome challenges such as regulatory requirements, consumer acceptance, and scaling-up research concepts to commercial applications. PMID:22129343

  13. Edible packaging materials.

    Science.gov (United States)

    Janjarasskul, Theeranun; Krochta, John M

    2010-01-01

    Research groups and the food and pharmaceutical industries recognize edible packaging as a useful alternative or addition to conventional packaging to reduce waste and to create novel applications for improving product stability, quality, safety, variety, and convenience for consumers. Recent studies have explored the ability of biopolymer-based food packaging materials to carry and control-release active compounds. As diverse edible packaging materials derived from various by-products or waste from food industry are being developed, the dry thermoplastic process is advancing rapidly as a feasible commercial edible packaging manufacturing process. The employment of nanocomposite concepts to edible packaging materials promises to improve barrier and mechanical properties and facilitate effective incorporation of bioactive ingredients and other designed functions. In addition to the need for a more fundamental understanding to enable design to desired specifications, edible packaging has to overcome challenges such as regulatory requirements, consumer acceptance, and scaling-up research concepts to commercial applications.

  14. Efficient large volume electroporation of dendritic cells through micrometer scale manipulation of flow in a disposable polymer chip

    DEFF Research Database (Denmark)

    Selmeczi, David; Hansen, Thomas; Met, Özcan;

    2011-01-01

    We present a hybrid chip of polymer and stainless steel designed for high-throughput continuous electroporation of cells in suspension. The chip is constructed with two parallel stainless steel mesh electrodes oriented perpendicular to the liquid flow. The relatively high hydrodynamic resistance ...

  15. High-performance semiconductor optical amplifier array for self-aligned packaging using Si V-groove flip-chip technique

    Science.gov (United States)

    Leclerc, D.; Brosson, P.; Pommereau, F.; Ngo, R.; Doussiere, P.; Mallecot, F.; Gavignet, P.; Wamsler, I.; Laube, G.; Hunziker, W.

    1995-05-01

    A high performance four-tilted stripe semiconductor optical amplifier array, with low polarization sensitivity and very low-gain ripple, compatible with self-aligned flip-chip mounting on a Si motherboard is reported. Up to 32 dB of internal gain with 2-dB polarization sensitivity is obtained. A multifiber module has been realized, following an almost static optical alignment procedure, showing no degradation of the SOA array performances. Fiber-to-fiber gain, measured on the four stripes, is 14.4 +/- 1.3 dB with a gain ripple below +/- 0.1 dB.

  16. Real-Time Very Large-Scale Integration Recognition System with an On-Chip Adaptive K-Means Learning Algorithm

    Science.gov (United States)

    Hou, Zuoxun; Ma, Yitao; Zhu, Hongbo; Zheng, Nanning; Shibata, Tadashi

    2013-04-01

    A very large-scale integration (VLSI) recognition system equipped with an on-chip learning capability has been developed for real-time processing applications. This system can work in two functional modes of operation: adaptive K-means learning mode and recognition mode. In the adaptive K-means learning mode, the variance ratio criterion (VRC) has been employed to evaluate the quality of K-means classification results, and the evaluation algorithm has been implemented on the chip. As a result, it has become possible for the system to autonomously determine the optimum number of clusters (K). In the recognition mode, the nearest-neighbor search algorithm is very efficiently carried out by the fully parallel architecture employed in the chip. In both modes of operation, many hardware resources are shared and the functionality is flexibly altered by the system controller designed as a finite-state machine (FSM). The chip is implemented on Altera Cyclone II FPGA with 46K logic cells. Its operating clock is 25 MHz and the processing times for adaptive learning and recognition with 256 64-dimension feature vectors are about 0.42 ms and 4 µs, respectively. Both adaptive K-means learning and recognition functions have been verified by experiments using the image data from the COIL-100 (Columbia University Object Image Library) database.

  17. Packaging fluency

    DEFF Research Database (Denmark)

    Mocanu, Ana; Chrysochou, Polymeros; Bogomolova, Svetlana;

    2011-01-01

    Research on packaging stresses the need for packaging design to read easily, presuming fast and accurate processing of product-related information. In this paper we define this property of packaging as “packaging fluency”. Based on the existing marketing and cognitive psychology literature...... on packaging design and processing fluency, our aim is to define and conceptualise packaging fluency. We stress the important role of packaging fluency since it is anticipated that a fluent package would influence the evaluative judgments for a product. We conclude this paper by setting the research agenda...

  18. Novel on chip-interconnection structures for giga-scale integration VLSI ICS

    Science.gov (United States)

    Nelakuditi, Usha R.; Reddy, S. N.

    2013-01-01

    Based on the guidelines of International Technology Roadmap for Semiconductors (ITRS) Intel has already designed and manufactured the next generation product of the Itanium family containing 1.72 billion transistors. In each new technology due to scaling, individual transistors are becoming smaller and faster, and are dissipating low power. The main challenge with these systems is wiring of these billion transistors since wire length interconnect scaling increases the distributed resistance-capacitance product. In addition, high clock frequencies necessitate reverse scaling of global and semi-global interconnects so that they satisfy the timing constraints. Hence, the performances of future GSI systems will be severely restricted by interconnect performance. It is therefore essential to look at interconnect design techniques that will reduce the impact of interconnect networks on the power, performance and cost of the entire system. In this paper a new routing technique called Wave-Pipelined Multiplexed (WPM) Routing similar to Time Division Multiple Access (TDMA) is discussed. This technique is highly useful for the current high density CMOS VLSI ICs. The major advantages of WPM routing technique are flexible, robust, simple to implement, and realized with low area, low power and performance overhead requirements.

  19. Control Effect of Occupational Hazards in Construction Project of Chip Package%某芯片封装测试项目职业病危害控制效果评价

    Institute of Scientific and Technical Information of China (English)

    康晓熙; 张遵真

    2013-01-01

    目的 评价某芯片封装测试项目职业病危害因素控制效果,为项目竣工验收提供依据.方法 依据相关资料,进行现场职业卫生学调查和职业危害因素检测,采用工程分析、定性定量分析等方法进行评价.结果 噪声、化学毒物、工频电磁场是芯片封装测试生产的主要职业病危害因素.其中,4个噪声测定点超标,该4点均为巡视人员巡检岗位,其接触噪声8h等效声级为77.7dB(A);化学毒物、工频电磁场作业点检测结果均符合国家职业卫生标准.结论 该项目为职业病危害一般的建设项目,该项目采取了卫生工程防护措施与个人防护措施相结合的方法控制职业有害因素,对接触有毒有害作业人员进行职业健康监护,职业病防护措施效果良好.%Objective To evaluate the occupational hazards in construction project of chip package,so as to provide the basis for the inspection by health administrative departments.Methods According to the related data,occupational hygienic investigation was carried out,occupational hazards factors were detected and both qualitative and quantitative analysis methods were applied.Results The main occupational hazard factors in the chip package production were noise,poisonous chemicals and power frequency.Four noise sites for patrol inspection exceed the standard with the Lex8hintensities noise of 77.7dB (A).Poisonous chemicals,power frequency were in accord with the occupational exposure standards.Conclusion The project is a common construction project,the occupational hazard prevention facilities and control measures basically come up to the national occupational health requirements.

  20. SU-8 cantilever chip interconnection

    DEFF Research Database (Denmark)

    Johansson, Alicia Charlotte; Janting, Jakob; Schultz, Peter;

    2006-01-01

    the electrodes on the SU-8 chip to a printed circuit board. Here, we present two different methods of electrically connecting an SU-8 chip, which contains a microfluidic network and free-hanging mechanical parts. The tested electrical interconnection techniques are flip chip bonding using underfill or flip chip...... bonding using an anisotropic conductive film (ACF). These are both widely used in the Si industry and might also be used for the large scale interconnection of SU-8 chips. The SU-8 chip, to which the interconnections are made, has a microfluidic channel with integrated micrometer-sized cantilevers...... that can be used for label-free biochemical detection. All the bonding tests are compared with results obtained using similar Si chips. It is found that it is significantly more complicated to interconnect SU-8 than Si cantilever chips primarily due to the softness of SU-8....

  1. Kinetic model for torrefaction of wood chips in a pilot-scale continuous reactor

    DEFF Research Database (Denmark)

    Shang, Lei; Ahrenfeldt, Jesper; Holm, Jens Kai;

    2014-01-01

    the temperature along the reactor and the biomass feeding rate in combination with the kinetic parameters obtained from the tests in the TGA. Together with results from a laboratory scale, batch torrefaction reactor that was used to determine the higher heating value (HHV) and mass loss (y) of the same material......Torrefaction is a mild thermal treatment (200-300 °C) in an inert atmosphere, known to increase the energy density of biomass by evaporation of water and a proportion of the volatiles. In this work a "two-step reaction in series" model was used to describe the thermal degradation kinetics of pine...... wood. The kinetic parameters were determined using a thermogravimetric analyzer (TGA) and the mass loss during the initial heating period was taken into account when deriving the kinetic parameters. It was shown that the experimental results at different heating rates (10-50 °C min-1) are in good...

  2. Radioistopes to Solar to High Energy Accelerators – Chip-Scale Energy Sources

    International Nuclear Information System (INIS)

    This talk will present MEMS based power sources that utilize radioisotopes, solar energy, and potentially nuclear energy through advancements in integration of new structures and materials within MEMS. Micro power harvesters can harness power from vibration, radioisotopes, light, sound, and biology may provide pathways to minimize or even eliminate batteries in sensor nodes. In this talk work on radioisotope thin films for MEMS will be include the self-reciprocating cantilever, betavoltaic cells, and high DC voltages. The self-reciprocating cantilever energy harvester allows small commercially viable amounts of radioisotopes to generate mW to Watts of power so that very reliable power sources that last 100s of years are possible. The tradeoffs between reliability and potential stigma with radioisotopes allow one to span a useful design space with reliability as a key parameter. These power sources provide pulsed power at three different time scales using mechanical, RF, and static extraction of energy from collected charge. Multi-use capability, both harvesting radioisotope power and local vibration energy extends the reliability of micro-power sources further

  3. Chip-scale parametric amplifier with 11 dB gain at 1550 nm based on a slow-light GaInP photonic crystal waveguide.

    Science.gov (United States)

    Cestier, Isabelle; Combrié, Sylvain; Xavier, Stéphane; Lehoucq, Gaëlle; De Rossi, Alfredo; Eisenstein, Gadi

    2012-10-01

    We report on a chip scale parametric amplifier based on a GaInP photonic crystal waveguide. The amplifier operates with both pump and signal in the 1550 nm wavelength range and offers an on-chip gain of 11 dB (5 dB including the 6 dB coupling losses) when pumped at only 800 mW. It enables us, therefore, to incorporate the many advantages of parametric amplification within photonic chips for optical communication applications.

  4. Characterization and modeling of two-phase heat transfer in chip-scale non-uniformly heated microgap channels

    Science.gov (United States)

    Ali, Ihab A.

    A chip-scale, non-uniformly heated microgap channel, 100 micron to 500 micron in height with dielectric fluid HFE-7100 providing direct single- and two-phase liquid cooling for a thermal test chip with localized heat flux reaching 100 W/cm2, is experimentally characterized and numerically modeled. Single-phase heat transfer and hydraulic characterization is performed to establish the single-phase baseline performance of the microgap channel and to validate the mesh-intensive CFD numerical model developed for the test channel. Convective heat transfer coefficients for HFE-7100 flowing in a 100-micron microgap channel reached 9 kW/m2K at 6.5 m/s fluid velocity. Despite the highly non-uniform boundary conditions imposed on the microgap channel, CFD model simulation gave excellent agreement with the experimental data (to within 5%), while the discrepancy with the predictions of the classical, "ideal" channel correlations in the literature reached 20%. A detailed investigation of two-phase heat transfer in non-ideal micro gap channels, with developing flow and significant non-uniformities in heat generation, was performed. Significant temperature non-uniformities were observed with non-uniform heating, where the wall temperature gradient exceeded 30°C with a heat flux gradient of 3-30 W/cm2, for the quadrant-die heating pattern compared to a 20°C gradient and 7-14 W/cm2 heat flux gradient for the uniform heating pattern, at 25W heat and 1500 kg/m2s mass flux. Using an inverse computation technique for determining the heat flow into the wetted microgap channel, average wall heat transfer coefficients were found to vary in a complex fashion with channel height, flow rate, heat flux, and heating pattern and to typically display an inverse parabolic segment of a previously observed M-shaped variation with quality, for two-phase thermal transport. Examination of heat transfer coefficients sorted by flow regimes yielded an overall agreement of 31% between predictions of the

  5. Processing and Validation of Whey-Protein-Coated Films and Laminates at Semi-Industrial Scale as Novel Recyclable Food Packaging Materials with Excellent Barrier Properties

    Directory of Open Access Journals (Sweden)

    E. Bugnicourt

    2013-01-01

    Full Text Available A biopolymer coating for plastic films was formulated based on whey protein, and its potential to replace current synthetic oxygen barrier layers used in food packaging such as ethylene vinyl alcohol copolymers (EVOH was tested. The whey-coating application was performed at semi-industrial scale. High barrier to oxygen with transmission rate down to ranges of 1 cm3 (STP m−2 d−1 bar−1 at and 50% relative humidity (r.h. but interesting humidity barrier down to ranges of 3 g m−2 d−1 (both normalized to 100 μm thickness were reached, outperforming most existing biopolymers. Coated films were validated for storing various food products showing that the shelf life and sensory attributes were maintained similar to reference packaging films while complying with food safety regulations. The developed whey coating could be enzymatically removed within 2 hours and is therefore compatible with plastic recycling operations to allow multilayer films to become recyclable by separating the other combined layers. A life cycle assessment was performed showing a significant reduction in the environmental impact of the packaging thanks in particular to the possibility of recycling materials as opposed to incinerating those containing EVOH or polyamide (PA, but due to the use of biosourced raw materials.

  6. Efficient large volume electroporation of dendritic cells through micrometer scale manipulation of flow in a disposable polymer chip

    DEFF Research Database (Denmark)

    Selmeczi, Dávid; Hansen, Thomas Steen; Met, Özcan;

    2011-01-01

    We present a hybrid chip of polymer and stainless steel designed for high-throughput continuous electroporation of cells in suspension. The chip is constructed with two parallel stainless steel mesh electrodes oriented perpendicular to the liquid flow. The relatively high hydrodynamic resistance...... of the micrometer sized holes in the meshes compared to the main channel enforces an almost homogeneous flow velocity between the meshes. Thereby, very uniform electroporation of the cells can be accomplished. Successful electroporation of 20 million human dendritic cells with mRNA is demonstrated. The performance...... of the chip is similar to that of the traditional electroporation cuvette, but without an upper limit on the number of cells to be electroporated. The device is constructed with two female Luer parts and can easily be integrated with other microfluidic components. Furthermore it is fabricated from injection...

  7. MEMS packaging

    CERN Document Server

    Hsu , Tai-Ran

    2004-01-01

    MEMS Packaging discusses the prevalent practices and enabling techniques in assembly, packaging and testing of microelectromechanical systems (MEMS). The entire spectrum of assembly, packaging and testing of MEMS and microsystems, from essential enabling technologies to applications in key industries of life sciences, telecommunications and aerospace engineering is covered. Other topics included are bonding and sealing of microcomponents, process flow of MEMS and microsystems packaging, automated microassembly, and testing and design for testing.The Institution of Engineering and Technology is

  8. Design and fabrication of a compact chip-scale optical cross-connect enabled by photonic crystals for optical interconnects

    Science.gov (United States)

    Zablocki, Mathew Joseph

    As integrated circuits, such as microprocessors, are fabricated with higher yields and with increasing numbers of smaller and smaller transistors, the communication between discrete elements becomes as important as the elements themselves. The delays associated with signal distribution across the chip have become a limiting factor for processor speeds, and are primarily located within the global interconnect layers for intra-chip and inter-chip communication. Optical interconnects have the potential to relieve the restrictions set by the interconnect bottleneck by taking advantage of their reduced power demands for signal distribution and their lower propagation delays. The work within this dissertation discusses the design, fabrication and characterization of an ultra-compact photonic crystal optical switch for use within a transparent optical cross-connect (OXC). To reduce the size and power consumption of the switch, perturbations were made within the photonic crystal structure to achieve a degree of slow light, decreasing the group velocity of the propagating signals. Further, as a means to integrate the developed switch matrix to a microprocessor in order to serve as a chip's optical global interconnect, a process was developed to transfer the switch fabric to a new substrate as a silicon-nanomembrane (Si-NM). The developed transfer process allows the transfer and stacking of intricate photonic devices, such as the aforementioned switch matrix, to new material platforms and substrates that would be incompatible with typical complementary-metal-oxide-semiconductor CMOS processing. The developed Si-NM processing along with the developed switch matrix for a transparent OXC are significant steps toward implementing an optical interconnect network on a chip.

  9. Battery packaging - Technology review

    Energy Technology Data Exchange (ETDEWEB)

    Maiser, Eric [The German Engineering Federation (VDMA), Battery Production Industry Group, Lyoner Str. 18, 60528 Frankfurt am Main (Germany)

    2014-06-16

    This paper gives a brief overview of battery packaging concepts, their specific advantages and drawbacks, as well as the importance of packaging for performance and cost. Production processes, scaling and automation are discussed in detail to reveal opportunities for cost reduction. Module standardization as an additional path to drive down cost is introduced. A comparison to electronics and photovoltaics production shows 'lessons learned' in those related industries and how they can accelerate learning curves in battery production.

  10. Battery packaging - Technology review

    International Nuclear Information System (INIS)

    This paper gives a brief overview of battery packaging concepts, their specific advantages and drawbacks, as well as the importance of packaging for performance and cost. Production processes, scaling and automation are discussed in detail to reveal opportunities for cost reduction. Module standardization as an additional path to drive down cost is introduced. A comparison to electronics and photovoltaics production shows 'lessons learned' in those related industries and how they can accelerate learning curves in battery production

  11. Silver flip chip interconnect technology and solid state bonding

    Science.gov (United States)

    Sha, Chu-Hsuan

    -section, there is no void or gap observed. The new bonding technique presented should be valuable in packaging high power electronic devices for high temperature operations. It should also be useful to bond two 304SS parts together at low bonding temperature of 190ºC. Solid state bonding technique is then introduced to bond semiconductor chips, such as Si, to common substrates, such as Cu or alumina, using pure Ag and Au at a temperature matching the typical reflow temperature used in packaging industries, 260°C. In bonding, we realize the possibilities of solid state bonding of Au to Au, Au to Ag, and Ag to Cu. The idea comes from that Cu, Ag, and Au are located in the same column on periodic table, meaning that they have similar electronic configuration. They therefore have a better chance to share electrons. Also, the crystal lattice of Cu, Ag, and Au is the same, face-centered cubic. In the project, the detailed bonding mechanism is beyond the scope and here we determine the bonding by the experimental result. Ag is chosen as the joint material because of its superior physical properties. It has the highest electrical and thermal conductivities among all metals. It has low yield strength and is relatively ductile. Au is considered as well because its excellent ductility and fatigue resistance. Thus, the Ag or Au joints can deform to accommodate the shear strain caused by CTE mismatch between Si and Cu. Ag and Au have melting temperatures higher than 950°C, so the pure Ag or Au joints are expected to sustain in high operating temperature. The resulting joints do not contain any intermetallic compound. Thus, all reliability issues associated with intermetallic growth in commonly used solder joints do not exist anymore. We finally move to the applications of solid state Ag bonding in flip chip interconnects design. At present, nearly all large-scale integrated circuit (IC) chips are packaged with flip-chip technology. This means that the chip is flipped over and the active

  12. Gain chip design, power scaling and intra-cavity frequency doubling with LBO of optically pumped red-emitting AlGaInP-VECSELs

    Science.gov (United States)

    Kahle, Hermann; Mateo, Cherry M. N.; Brauch, Uwe; Bek, Roman; Schwarzbäck, Thomas; Jetter, Michael; Graf, Thomas; Michler, Peter

    2016-03-01

    The wide range of applications in biophotonics, television or projectors, spectroscopy and lithography made the optically-pumped semiconductor (OPS) vertical external cavity surface-emitting lasers (VECSELs) an important category of power scalable lasers. The possibility of bandgap engineering, inserting frequency selective and converting elements into the open laser cavity and laser emission in the fundamental Gaussian mode leads to ongoing growth of the area of applications for tuneable laser sources. We present an AlGaInP-VECSEL system with a multi quantum well structure consisting of compressively strained GaInP quantum wells in an AlxGa1-xInP separate confinement heterostructure with an emission wavelength around 665 nm. The VECSEL chip with its n-λ cavity is pumped by a 532nm Nd:YAG laser under an angle to the normal incidence of 50°. In comparison, a gain chip design for high absorption values at pump wavelengths around 640nm with the use of quantum dot layers as active material is also presented. Frequency doubling is now realized with an antireflection coated lithium borate crystal, while a birefringent filter, placed inside the laser cavity under Brewster's angle, is used for frequency tuning. Further, power-scaling methods like in-well pumping as well as embedding the active region of a VECSEL between two transparent ic heaspreaders are under investigation.

  13. Preservation of forest wood chips

    Energy Technology Data Exchange (ETDEWEB)

    Kofman, P.D.; Thomsen, I.M.; Ohlsson, C.; Leer, E.; Ravn Schmidt, E.; Soerensen, M.; Knudsen, P.

    1999-01-01

    As part of the Danish Energy Research Programme on biomass utilisation for energy production (EFP), this project concerns problems connected to the handling and storing of wood chips. In this project, the possibility of preserving wood chips of the Norway Spruce (Picea Abies) is addressed, and the potential improvements by anaerobic storage are tested. Preservation of wood chips aims at reducing dry matter losses from extensive heating during storage and to reduce production of fungal spores. Fungal spores pose a health hazards to workers handling the chips. Further the producers of wood chips are interested in such a method since it would enable them to give a guarantee for the delivery of homogeneous wood chips also during the winter period. Three different types of wood chips were stored airtight and further one of these was stored in accordance with normal practise and use as reference. The results showed that airtight storage had a beneficial impact on the quality of the chips: no redistribution of moisture, low dry matter losses, unfavourable conditions for microbial activity of most fungi, and the promotion of yeasts instead of fungi with airborne spores. Likewise the firing tests showed that no combustion problems, and no increased risk to the environment or to the health of staff is caused by anaerobic storage of wood chips. In all, the tests of the anaerobic storage method of forest wood chips were a success and a large-scale test of the method will be carried out in 1999. (au)

  14. Additive manufacturing approaches for stress relief in semiconductor die packaging

    NARCIS (Netherlands)

    Zon, C.M.B. van der; Wiel, A. van der; Maalderink, H.H.; Vaes, M.H.E.; Aulbers, A.P.; Vorst, L.T.G. van de; Cate, A.T. ten; Furrer, J.F.; Burssens, J.W.; Chen, J.

    2012-01-01

    Packaging of semiconductor chips, especially MEMS-based, always causes stress on the functional areas of the die causing unpredictable changes in chip performance. As a consequence such devices can only be calibrated individually after complete assembly. Melexis and TNO have developed an approach to

  15. Heat transfer and structure stress analysis of micro packaging component of high power light emitting diode

    Directory of Open Access Journals (Sweden)

    Hsu Chih-Neng

    2013-01-01

    Full Text Available This paper focuses on the heat transfer and structural stress analysis of the micro- scale packaging structure of a high-power light emitting diode. The thermal-effect and thermal-stress of light emitting diode are determined numerically. Light emitting diode is attached to the silicon substrate through the wire bonding process by using epoxy as die bond material. The silicon substrate is etched with holes at the bottom and filled with high conductivity copper material. The chip temperature and structure stress increase with input power consumption. The micro light emitting diode is mounted on the heat sink to increase the heat dissipation performance, to decrease chip temperature, to enhance the material structure reliability and safety, and to avoid structure failure as well. This paper has successfully used the finite element method to the micro-scale light emitting diode heat transfer and stress concentration at the edges through etched holes.

  16. Continuous use after 1998 of the scaling factors for radionuclide evaluation in the packaged solid wastes generated from the Fukushima Daiichi Nuclear Power Plants of Tokyo Electric Power Company

    International Nuclear Information System (INIS)

    The waste packages containing solidified radioactive wastes generated from nuclear power plants are evaluated by measuring radioactivity from outside the drums and applying the scaling factor method to estimate the inside radionuclide concentrations. Japan Nuclear Energy Safety Organization (JNES) is in charge of the confirmation of the applicability of this method and this report presents the results of the examining processes of the working committee for this purpose. The properties of the solidified waste packages, the guidelines of using the scaling factors, the concept of renewal of reactor composing materials, are explained with radionuclide information and compliance with formalities for safety maintenance and control. (S. Ohno)

  17. Numerical Simulation of Non-Newtonian Underfill in Flip-Chip Packaging%倒装芯片封装中非牛顿流体下填充的数值仿真

    Institute of Scientific and Technical Information of China (English)

    姚兴军; 张关华; 王正东; 章文俊; 周鑫延

    2013-01-01

    倒装芯片封装中的下填充工艺可以有效地提高封装连接的可靠性,因而得到了广泛应用.含有硅填料的环氧树脂是常用的下填充胶料,在下填充流动过程中表现出明显的非牛顿流体特性.利用Fluent软件对具有非牛顿流体特性胶料的下填充过程进行了三维数值模拟.采用流体体积比函数(VOF)对流动前沿界面进行追踪,再用连续表面张力(CSF)模型来计算下填充流动的毛细驱动力,并用幂函数本构方程来体现下填充胶料的非牛顿流体特性.通过数值模拟,获得了下填充流动前沿位置随时间变化的数据,这些数据与实验结果有较好的吻合度.该数值方法可较好地预测具有非牛顿流体性质胶料的下填充过程.%Underfill technology is often used in flip-chip packaging as it can improve the reliability of the interconnect systems effectively. Epoxy containing silica fillers is the most common encapsulant, and it exhibits obvious non-Newtonian behavior in the underfill flow. The 3D simulation of the filling process was operated using Fluent software. Volume of fluid (VOF) technique was applied to track the flow front, and the continuum surface force (CSF) model was used to describe the capillary force when the power-law type equation was employed to model the viscosity of the underfill encapsulant. The numerical results show the variation of flow front position with respect to time agrees well with the previous experimental data. This simulation provides a reasonable flow front prediction for underfill flow of encapsulant with non-Newtonian feature.

  18. Comparison of different LED Packages

    Science.gov (United States)

    Dieker, Henning; Miesner, Christian; Püttjer, Dirk; Bachl, Bernhard

    2007-09-01

    In this paper different technologies for LED packaging are compared, focusing on Chip on Board (COB) and SMD technology. The package technology which is used depends on the LED application. A critical fact in LED technology is the thermal management, especially for high brightness LED applications because the thermal management is important for reliability, lifetime and electrooptical performance of the LED module. To design certain and long life LED applications knowledge of the heat flow from LEDs to the complete application is required. High sophisticated FEM simulations are indispensable for modern development of high power LED applications. We compare simulations of various substrate materials and packaging technologies simulated using FLOTHERM software. Thereby different substrates such as standard FR4, ceramic and metal core printed circuit boards are considered. For the verification of the simulated results and the testing of manufactured modules, advanced measurement tools are required. We show different ways to experimentally characterize the thermal behavior of LED modules. The thermal path is determined by the transient thermal analysis using the MicReD T3Ster analyzer. Afterwards it will be compared to the conventional method using thermocouples. The heat distribution over the module is investigated by an IR-Camera. We demonstrate and compare simulation and measurement results of Chip-on-Board (COB) and Sub-Mounted Devices (SMD) technology. The results reveal that for different applications certain packages are ideal.

  19. Correlations between homologue concentrations of PCDD/Fs and toxic equivalency values in laboratory-, package boiler-, and field-scale incinerators.

    Science.gov (United States)

    Iino, Fukuya; Takasuga, Takumi; Touati, Abderrahmane; Gullett, Brian K

    2003-01-01

    The toxic equivalency (TEQ) values of polychlorinated dibenzo-p-dioxins and polychlorinated dibenzofurans (PCDD/Fs) are predicted with a model based on the homologue concentrations measured from a laboratory-scale reactor (124 data points), a package boiler (61 data points), and operating municipal waste incinerators (114 data points). Regardless of the three scales and types of equipment, the different temperature profiles, sampling emissions and/or solids (fly ash), and the various chemical and physical properties of the fuels, all the PCDF plots showed highly linear correlations (R(2)>0.99). The fitting lines of the reactor and the boiler data were almost linear with slope of unity, whereas the slope of the municipal waste incinerator data was 0.86, which is caused by higher predicted values for samples with high measured TEQ. The strong correlation also implies that each of the 10 toxic PCDF congeners has a constant concentration relative to its respective total homologue concentration despite a wide range of facility types and combustion conditions. The PCDD plots showed significant scatter and poor linearity, which implies that the relative concentration of PCDD TEQ congeners is more sensitive to variations in reaction conditions than that of the PCDF congeners. PMID:14522191

  20. Human-machine Scale and Comfort in Packaging Container Modeling Design%包装容器造型设计的人机尺度与舒适度

    Institute of Scientific and Technical Information of China (English)

    黎英; 王建民

    2012-01-01

    Starting from ergonomic principles, it analyzed the human-machine factors in packaging container and the law of comfortable design based on the human-machine scales, systematically investigated the types of comfort from health and medical point of view. It is found that in order to gain physical and mental comfort while using the container so as to create an ideal lifestyle for consumers, scales including human body size, physiological and psychological needs and behaviour must be considered in packing design.%参考健康医学的观点,对舒适度的类型展开了分析,以人机工程学原理为启示,分析了包装容器造型设计的人机因素,探讨了基于人机尺度下包装容器造型的舒适性设计规律。在此基础上,提出了在包装造型设计中把握人体尺寸、生理需求、心理需求、使用行为的尺度,才能使容器在使用过程中获得生理和心理的舒适,从而为消费者营造理想的生活方式。

  1. Curbing variations in packaging process through Six Sigma way in a large-scale food-processing industry

    Science.gov (United States)

    Desai, Darshak A.; Kotadiya, Parth; Makwana, Nikheel; Patel, Sonalinkumar

    2015-08-01

    Indian industries need overall operational excellence for sustainable profitability and growth in the present age of global competitiveness. Among different quality and productivity improvement techniques, Six Sigma has emerged as one of the most effective breakthrough improvement strategies. Though Indian industries are exploring this improvement methodology to their advantage and reaping the benefits, not much has been presented and published regarding experience of Six Sigma in the food-processing industries. This paper is an effort to exemplify the application of Six Sigma quality improvement drive to one of the large-scale food-processing sectors in India. The paper discusses the phase wiz implementation of define, measure, analyze, improve, and control (DMAIC) on one of the chronic problems, variations in the weight of milk powder pouch. The paper wraps up with the improvements achieved and projected bottom-line gain to the unit by application of Six Sigma methodology.

  2. Economy analysis on reclamation of DIP packaged IC chip from discarded printed circuit boards%废弃电路板双列直插式封装的集成电路芯片回收的经济性分析

    Institute of Scientific and Technical Information of China (English)

    刘志峰; 朱一; 宋守许; 王玉琳; 刘光复

    2011-01-01

    Dismantling and recycling the waste electronic chips from printed circuit boards (PCB) could return good profit. Most of DIP packaged electronic chips was able to perform normal function after proper disposal, so it could be reused after qualified correlative criteria. In this paper, the electronic chip recovery process was designed base on the reclaim strategy, and the cost-benefit model was established to quantificationally evaluate the reclaim profit. The economy model was illustrated with specific disassembly instance. Finally, some suggestions were proposed for improving the recovery benefit.%废弃电路板电子元件拆除后回收具有较大的利润空间.回收的双列直插式封装(DIP)电子元件多数都保留正常的使用功能,经过适当的处理,检测合格后可以继续使用.提出了基于回收策略的废弃电路板DIP的集成电路(IC)芯片回收工艺,建立了回收经济性评估模型,并对2种回收的IC芯片进行经济性定量评价.

  3. Green Packaging Management of Logistics Enterprises

    Science.gov (United States)

    Zhang, Guirong; Zhao, Zongjian

    From the connotation of green logistics management, we discuss the principles of green packaging, and from the two levels of government and enterprises, we put forward a specific management strategy. The management of green packaging can be directly and indirectly promoted by laws, regulations, taxation, institutional and other measures. The government can also promote new investment to the development of green packaging materials, and establish specialized institutions to identify new packaging materials, standardization of packaging must also be accomplished through the power of the government. Business units of large scale through the packaging and container-based to reduce the use of packaging materials, develop and use green packaging materials and easy recycling packaging materials for proper packaging.

  4. Realtime 3D stress measurement in curing epoxy packaging

    DEFF Research Database (Denmark)

    Richter, Jacob; Hyldgård, A.; Birkelund, Karen;

    2007-01-01

    This paper presents a novel method to characterize stress in microsystem packaging. A circular p-type piezoresistor is implemented on a (001) silicon chip. We use the circular stress sensor to determine the packaging induced stress in a polystyrene tube filled with epoxy. The epoxy curing process...

  5. Atom chips

    CERN Document Server

    Reichel, Jakob

    2010-01-01

    This book provides a stimulating and multifaceted picture of a rapidly developing field. The first part reviews fundamentals of atom chip research in tutorial style, while subsequent parts focus on the topics of atom-surface interaction, coherence on atom chips, and possible future directions of atom chip research. The articles are written by leading researchers in the field in their characteristic and individual styles.

  6. Mikrofluidik-Chips

    NARCIS (Netherlands)

    Verpoorte, E.; Lichtenberg, J.

    2000-01-01

    Microfluidic chips are becoming the new paradigm for chemical processing and analysis in the laboratory. Hair-fine channels made in planar substrates using silicon processing technologies replace beakers and tubing for automated liquid transport and handling on a sub-μ L scale. Reduced conduit diame

  7. GEM400: A front-end chip based on capacitor-switch array for pixel-based GEM detector

    International Nuclear Information System (INIS)

    The upgrade of Beijing Synchrotron Radiation Facility (BSRF) needs two-dimensional position-sensitive detection equipment to improve the experimental performance. Gas Electron Multiplier (GEM) detector, in particular, pixel-based GEM detector has good application prospects in the domain of synchrotron radiation. The read-out of larger scale pixel-based GEM detector is difficult for the high density of the pixels (PAD for collecting electrons). In order to reduce the number of cables, this paper presents a read-out scheme for pixel-based GEM detector, which is based on System-in-Package technology and ASIC technology. We proposed a circuit structure based on capacitor switch array circuit, and design a chip GEM400, which is a 400 channels ASIC. The proposed circuit can achieve good stability and low power dissipation. The chip is implemented in a 0.35μm CMOS process. The basic functional circuitry in ths chip includes analog switch, analog buffer, voltage amplifier, bandgap and control logic block, and the layout of this chip takes 5mm × 5mm area. The simulation results show that the chip can allow the maximum amount of input charge 70pC on the condition of 100pF external integrator capacitor. Besides, the chip has good channel uniformity (INL is better than 0.1%) and lower power dissipation.

  8. Benchmarking of the scale code package and multi-group cross section libraries for analysis of lead-cooled fast reactor

    International Nuclear Information System (INIS)

    The Generation IV [1] International forum identified six advanced reactor concepts and related fuel cycles along with the R and D programs necessary to achieve the four key goals: (1) sustainability, (2) safety and reliability, (3) economics, (4) proliferation resistance and physical protection. Among these six promising reactor concepts, the lead-cooled fast reactor (LFR) has been selected for development by EURATOM, which in 2006 decided to finance the European Lead Cooled System (ELSY) project. The aim of the project is to demonstrate the possibility to design a safe and competitive lead-cooled fast power reactor using simple engineering solutions. This paper demonstrates the use of the code package SCALE5.1 and its NEWT/TRITON modules [3] for preliminary neutronic core analysis of a LFR within Generation IV Nuclear Energy systems program. More specifically, the analysis of the reference design of the ELSY-600 open square fuel assembly is presented. In particular, the use of ENDF/B-V and ENDF/B-VI.7 and multigroup energy structure was investigated. The homogenized cross sections calculated for the ELSY fuel assembly 2D model have been evaluated and compared to the results obtained with calculations performed with the deterministic code ERANOS/ECCO using JEFF2.2 cross section library. A good agreement has been observed in the energy range of interests, and generally for energy above 1 eV. (authors)

  9. Power Cycle Testing of Press-Pack IGBT Chips

    OpenAIRE

    Frank, Øyvind Bjerke

    2014-01-01

    In this thesis the power cycling capability of individual press-pack IGBT chips is investigated. Press-pack is a packaging technology used for power semiconductors. For press-packs, both thermal and electrical contact to the semiconductor chip is obtained by the application of force on the package. Press-pack IGBTs is claimed by the manufacturers to be especially suitable for high-power applications with large variations in power output. Power cycle testing is an accelerated lifetime stress t...

  10. 5GHz LTCC-based aperture coupled wireless transmitter for system-on-package applications

    KAUST Repository

    Shamim, Atif

    2012-01-01

    A novel System-on-Package (SoP) implementation is presented for a transmitter (TX) module which makes use of electromagnetic coupling between the TX chip and the package antenna. The TX chip is realized in 0.13μm CMOS process and comprises an on-chip antenna, which serves as the oscillator\\'s inductor as well. The TX chip is housed in a Low Temperature Co-fired Ceramic (LTCC) package with a patch antenna. The on-chip antenna feeds the LTCC patch antenna through aperture coupling, thus negating the need for RF buffer amplifiers, matching elements, baluns, bond wires and package transmission lines. This is the first ever demonstration of wireless-interconnect between on-chip and package antennas which increases the gain and range of the TX module manyfold with respect to the on-chip antenna alone. Though the range of the TX SoP increases considerably, power consumption remains the same as that of the TX chip only. A simple analytical model for the new wireless-interconnect has been developed which helps determine the optimum position of the chip with respect to the aperture in the ground plane.

  11. Challenges in the Packaging of MEMS

    Energy Technology Data Exchange (ETDEWEB)

    Malshe, A.P.; Singh, S.B.; Eaton, W.P.; O' Neal, C.; Brown, W.D.; Miller, W.M.

    1999-03-26

    The packaging of Micro-Electro-Mechanical Systems (MEMS) is a field of great importance to anyone using or manufacturing sensors, consumer products, or military applications. Currently much work has been done in the design and fabrication of MEMS devices but insufficient research and few publications have been completed on the packaging of these devices. This is despite the fact that packaging is a very large percentage of the total cost of MEMS devices. The main difference between IC packaging and MEMS packaging is that MEMS packaging is almost always application specific and greatly affected by its environment and packaging techniques such as die handling, die attach processes, and lid sealing. Many of these aspects are directly related to the materials used in the packaging processes. MEMS devices that are functional in wafer form can be rendered inoperable after packaging. MEMS dies must be handled only from the chip sides so features on the top surface are not damaged. This eliminates most current die pick-and-place fixtures. Die attach materials are key to MEMS packaging. Using hard die attach solders can create high stresses in the MEMS devices, which can affect their operation greatly. Low-stress epoxies can be high-outgassing, which can also affect device performance. Also, a low modulus die attach can allow the die to move during ultrasonic wirebonding resulting to low wirebond strength. Another source of residual stress is the lid sealing process. Most MEMS based sensors and devices require a hermetically sealed package. This can be done by parallel seam welding the package lid, but at the cost of further induced stress on the die. Another issue of MEMS packaging is the media compatibility of the packaged device. MEMS unlike ICS often interface with their environment, which could be high pressure or corrosive. The main conclusion we can draw about MEMS packaging is that the package affects the performance and reliability of the MEMS devices. There is a

  12. Effectiveness of a controlled release chlorhexidine chip (PerioColTM‑CG as an adjunctive to scaling and root planing when compared to scaling and root planing alone in the treatment of chronic periodontitis: A comparative study

    Directory of Open Access Journals (Sweden)

    Kameswari Kondreddy

    2012-01-01

    Full Text Available Aims and objectives: The aim of this study is to evaluate the effectiveness of a controlled-release chlorhexidine chip as an adjunctive therapy to scaling and root planing when compared with scaling and root planing alone in the treatment of chronic periodontitis. Materials and Methods: 20 patients with a total number of 40 posterior sites were selected. These sites were divided into two groups in a split mouth design,: Group A (control site had 20 sites treated with scaling and root planing alone and Group B (test site had 20 sites treated with scaling and root planing and PerioCol TM -CG. The clinical parameters (Plaque index, bleeding on probing, probing pocket depth, clinical attachment level were recorded at baseline, 90 th and 180 th day for both the groups. Results: When both groups were compared the change in Plaque index was significantly higher in Group B when compared to Group A on the 90 th day and 180 th day. However, there was no statistically significant difference in the mean percentage of gingival bleeding sites between the two groups on the 90 th day, though Group B showed a statistically higher reduction in the mean percentage of gingival bleeding sites at the end of 180 th day. There was no statistically significant difference in probing pocket depth between the two groups on both 90 th and 180 th day. Gain in clinical attachment level was significantly higher in Group B when compared to Group A on the 90 th and 180 th day. Conclusion: From the results observed in this study, it can be concluded that the adjunctive use of PerioCol TM -CG was safe and provided significant improvement in both Plaque index and gingival bleeding index. It was also more favorable than scaling and root planing alone for gain in clinical attachment level.

  13. Packaging Technologies for High Temperature Electronics and Sensors

    Science.gov (United States)

    Chen, Liangyu; Hunter, Gary W.; Neudeck, Philip G.; Beheim, Glenn M.; Spry, David J.; Meredith, Roger D.

    2013-01-01

    This paper reviews ceramic substrates and thick-film metallization based packaging technologies in development for 500degC silicon carbide (SiC) electronics and sensors. Prototype high temperature ceramic chip-level packages and printed circuit boards (PCBs) based on ceramic substrates of aluminum oxide (Al2O3) and aluminum nitride (AlN) have been designed and fabricated. These ceramic substrate-based chiplevel packages with gold (Au) thick-film metallization have been electrically characterized at temperatures up to 550degC. A 96% alumina based edge connector for a PCB level subsystem interconnection has also been demonstrated recently. The 96% alumina packaging system composed of chip-level packages and PCBs has been tested with high temperature SiC devices at 500degC for over 10,000 hours. In addition to tests in a laboratory environment, a SiC JFET with a packaging system composed of a 96% alumina chip-level package and an alumina printed circuit board mounted on a data acquisition circuit board was launched as a part of the MISSE-7 suite to the International Space Station via a Shuttle mission. This packaged SiC transistor was successfully tested in orbit for eighteen months. A spark-plug type sensor package designed for high temperature SiC capacitive pressure sensors was developed. This sensor package combines the high temperature interconnection system with a commercial high temperature high pressure stainless steel seal gland (electrical feed-through). Test results of a packaged high temperature capacitive pressure sensor at 500degC are also discussed. In addition to the pressure sensor package, efforts for packaging high temperature SiC diode-based gas chemical sensors are in process.

  14. Mineralogical and elemental composition of fly ash from pilot scale fluidised bed combustion of lignite, bituminous coal, wood chips and their blends

    Energy Technology Data Exchange (ETDEWEB)

    Nikolaos Koukouzas; Jouni Hamalainen; Dimitra Papanikolaou; Antti Tourunen; Timo Jantti [Institute for Solid Fuels Technology and Applications, Ptolemais (Greece). Centre for Research and Technology Hellas

    2007-09-15

    The chemical and mineralogical composition of fly ash samples collected from different parts of a laboratory and a pilot scale CFB facility has been investigated. The fabric filter and the second cyclone of the two facilities were chosen as sampling points. The fuels used were Greek lignite (from the Florina basin), Polish coal and wood chips. Characterization of the fly ash samples was conducted by means of X-ray fluorescence (XRF), inductive coupled plasma-optical emission spectrometry (ICP-OES), thermogravimetric analysis (TGA), particle size distribution (PSD) and X-ray diffraction (XRD). According to the chemical analyses the produced fly ashes are rich in CaO. Moreover, SiO{sub 2} is the dominant oxide in fly ash with Al{sub 2}O{sub 3} and Fe{sub 2}O{sub 3} found in considerable quantities. Results obtained by XRD showed that the major mineral phase of fly ash is quartz, while other mineral phases that are occurred are maghemite, hematite, periclase, rutile, gehlenite and anhydrite. The ICP-OES analysis showed rather low levels of trace elements, especially for As and Cr, in many of the ashes included in this study compared to coal ash from fluidised bed combustion in general. 23 refs., 3 figs., 5 tabs.

  15. 新经济形式下的包装设计尺度%Discussion on Packaging Design Scale under New Economic Form

    Institute of Scientific and Technical Information of China (English)

    过山; 熊菀君

    2009-01-01

    从可持续发展观和创建和谐社会的思路出发,研究不同类型、不同材质、不同生产工艺和不同消费群体的现代包装设计所应该遵循的基本尺度,即观念尺度、行为尺度、人为尺度,使设计师有目的、有效率地进行包装设计.%An issue ignored by most packaging designers was put forward, which was the application of natural eco-friendly materials in packaging design. The feasibility of application of natural eco-friendly materials in packaging design under existing condition was discussed with examples of traditional paper materials, natural materials, and new materials. The purpose was to promote the application of natural eco-friendly materials in food packaging.

  16. Sampling Ocsilloscope On-Chip

    OpenAIRE

    Forsgren, Niklas

    2003-01-01

    Signal-integrity degradation from such factors as supply and substrate noise and cross talk between interconnects restricts the performance advances in Very Large Scale Integration (VLSI). To avoid this and to keep the signal-integrity, accurate measurements of the on-chip signal must be performed to get an insight in how the physical phenomenon affects the signals. High-speed digital signals can be taken off chip, through buffers that add delay. Propagating a signal through buffers restores...

  17. PACE3 - front-end chip for the CMS Preshower

    CERN Multimedia

    Aspel, Paul

    2003-01-01

    This is PACE3 which is the front-end chip for the CMS Preshower. In fact PACE3 is the combination of two ASICs called Delta3 and PACEAM3. Delta3 is on the left and PACEAM3 is on the right. The two ASICs are bonded together and then packaged within a single 196 pin fpBGA package.

  18. Identification and characterisation of factors affecting losses in the large-scale, non-ventilated bulk storage of wood chips and development of best storage practices

    Energy Technology Data Exchange (ETDEWEB)

    Garstang, J.; Weekes, A.; Poulter, R.; Bartlett, D.

    2002-07-01

    The report describes the findings of a study to determine the factors affecting the commercial storage of wood chips for biomass power generation in the UK. The UK's first such plant in North Yorkshire uses a mixture of forestry residues and short rotation coppice (SRC) willow, where problems with the stored fuel highlighted the need to determine best storage practices. Two wood chip piles were built (one with willow chip and the other with wood chips from board leaf forestry residues) and monitored (moisture, temperature, chemical composition, spore numbers and species, heat and air flows, bulk density, etc). Local weather data was also obtained. Recommendations for future storage practices are made.

  19. Packetizing OCP Transactions in the MANGO Network-on-Chip

    DEFF Research Database (Denmark)

    Bjerregaard, Tobias; Sparsø, Jens

    2006-01-01

    The scaling of CMOS technology causes a widening gap between the performance of on-chip communication and computation. This calls for a communication-centric design flow. The MANGO network-on-chip architecture enables globally asynchronous locally synchronous (GALS) system-on-chip design, while...

  20. ATLAS software packaging

    CERN Document Server

    Rybkin, G

    2012-01-01

    Software packaging is indispensable part of build and prerequisite for deployment processes. Full ATLAS software stack consists of TDAQ, HLT, and Offline software. These software groups depend on some 80 external software packages. We present tools, package PackDist, developed and used to package all this software except for TDAQ project. PackDist is based on and driven by CMT, ATLAS software configuration and build tool, and consists of shell and Python scripts. The packaging unit used is CMT project. Each CMT project is packaged as several packages - platform dependent (one per platform available), source code excluding header files, other platform independent files, documentation, and debug information packages (the last two being built optionally). Packaging can be done recursively to package all the dependencies. The whole set of packages for one software release, distribution kit, also includes configuration packages and contains some 120 packages for one platform. Also packaged are physics analysis pro...

  1. 27 CFR 19.343 - Addition of oak chips to spirits and addition of caramel to brandy and rum.

    Science.gov (United States)

    2010-04-01

    ... 27 Alcohol, Tobacco Products and Firearms 1 2010-04-01 2010-04-01 false Addition of oak chips to... PLANTS Storage § 19.343 Addition of oak chips to spirits and addition of caramel to brandy and rum. Oak chips which have not been treated with any chemical may be added to packages either prior to or...

  2. Chips 2020

    CERN Document Server

    2016-01-01

    The release of this second volume of CHIPS 2020 coincides with the 50th anniversary of Moore’s Law, a critical year marked by the end of the nanometer roadmap and by a significantly reduced annual rise in chip performance. At the same time, we are witnessing a data explosion in the Internet, which is consuming 40% more electrical power every year, leading to fears of a major blackout of the Internet by 2020. The messages of the first CHIPS 2020, published in 2012, concerned the realization of quantum steps for improving the energy efficiency of all chip functions. With this second volume, we review these messages and amplify upon the most promising directions: ultra-low-voltage electronics, nanoscale monolithic 3D integration, relevant-data, brain- and human-vision-inspired processing, and energy harvesting for chip autonomy. The team of authors, enlarged by more world leaders in low-power, monolithic 3D, video, and Silicon brains, presents new vistas in nanoelectronics, promising  Moore-like exponential g...

  3. Performance and Energy Efficient Network-on-Chip Architectures

    OpenAIRE

    Vangal, Sriram

    2007-01-01

    The scaling of MOS transistors into the nanometer regime opens the possibility for creating large Network-on-Chip (NoC) architectures containing hundreds of integrated processing elements with on-chip communication. NoC architectures, with structured on-chip networks are emerging as a scalable and modular solution to global communications within large systems-on-chip. NoCs mitigate the emerging wire-delay problem and addresses the need for substantial interconnect bandwidth by replacing today...

  4. Status and prospects for phosphor-based white LED packaging

    Institute of Scientific and Technical Information of China (English)

    Zongyuan LIU; Sheng LIU; Kai WANG; Xiaobing LUO

    2009-01-01

    The status and prospects for high-power, phosphor-based white light-emitting diode (LED) pack-aging have been presented. A system view for packaging design is proposed to address packaging issues. Four aspects of packaging are reviewed: optical control, thermal management, reliability and cost. Phosphor materials play the most important role in light extraction and color control. The conformal coating method improves the spatial color distribution (SCD) of LEDs. High refractive index (RI) encapsulants with high transmittance and modified surface morphology can enhance light extraction. Multi-phosphor-based packaging can realize the control of correlated color temperature (CCT) with high color rendering index (CRI). Effective thermal management can dissipate heat rapidly and reduce thermal stress caused by the mismatch of the coefficient of thermal expansion (CTE). Chip-on-board (COB) technology with a multi-layer ceramic substrate is the most promising method for high-power LED packaging. Low junction temperature will improve the reliability and provide longer life. Advanced processes, precise fabrication and careful operation are essential for high reliability LEDs. Cost is one of the biggest obstacles for the penetration of white LEDs into the market for general illumination products. Mass production in terms of CoB, system in packaging (SIP), 3D packaging and wafer level packaging (WLP) can reduce the cost significantly, especially when chip cost is lowered by using a large wafer size.

  5. White LED with High Package Extraction Efficiency

    Energy Technology Data Exchange (ETDEWEB)

    Yi Zheng; Matthew Stough

    2008-09-30

    The goal of this project is to develop a high efficiency phosphor converting (white) Light Emitting Diode (pcLED) 1-Watt package through an increase in package extraction efficiency. A transparent/translucent monolithic phosphor is proposed to replace the powdered phosphor to reduce the scattering caused by phosphor particles. Additionally, a multi-layer thin film selectively reflecting filter is proposed between blue LED die and phosphor layer to recover inward yellow emission. At the end of the project we expect to recycle approximately 50% of the unrecovered backward light in current package construction, and develop a pcLED device with 80 lm/W{sub e} using our technology improvements and commercially available chip/package source. The success of the project will benefit luminous efficacy of white LEDs by increasing package extraction efficiency. In most phosphor-converting white LEDs, the white color is obtained by combining a blue LED die (or chip) with a powdered phosphor layer. The phosphor partially absorbs the blue light from the LED die and converts it into a broad green-yellow emission. The mixture of the transmitted blue light and green-yellow light emerging gives white light. There are two major drawbacks for current pcLEDs in terms of package extraction efficiency. The first is light scattering caused by phosphor particles. When the blue photons from the chip strike the phosphor particles, some blue light will be scattered by phosphor particles. Converted yellow emission photons are also scattered. A portion of scattered light is in the backward direction toward the die. The amount of this backward light varies and depends in part on the particle size of phosphors. The other drawback is that yellow emission from phosphor powders is isotropic. Although some backward light can be recovered by the reflector in current LED packages, there is still a portion of backward light that will be absorbed inside the package and further converted to heat. Heat

  6. Packaging Your Training Materials

    Science.gov (United States)

    Espeland, Pamela

    1977-01-01

    The types of packaging and packaging materials to use for training materials should be determined during the planning of the training programs, according to the packaging market. Five steps to follow in shopping for packaging are presented, along with a list of packaging manufacturers. (MF)

  7. Study on localized induction heating for wafer level packaging

    Institute of Scientific and Technical Information of China (English)

    2010-01-01

    Micro-electro-mechanical systems(MEMS)are being developed as a new multi-disciplinary technology,which will undoubtedly have a revolutionary impact on the future of human life.However,with the development of MEMS technology,the packaging has become the main technical obstacle to the commercialization of MEMS.An approach to MEMS packaging by high-frequency electromagnetic induction heating at wafer level is presented in terms of numerical simulation and experimental study.The structure of inductor is firstly designed and optimized.Then the heating situation of PCB board is verified.The results indicate that the heat impact on the chip during the packaging process can be effectively reduced by local induction heating packaging,therefore the thermal stress on the chip is considerably lowered.This method can effectively improve the reliability of the MEMS devices.

  8. Colour Design for Carton-Packed Fruit Juice Packages

    OpenAIRE

    Wei, Shuo-Ting; Ou, Li-Chen; Luo, M. Ronnier

    2009-01-01

    The present research studies the relationships between observers’ expectations for 7 fruit juice packages and the colour design of the package. To do this, a two-stage experiment was conducted. At the first stage, we studied perceived colours for the fruit images shown on each package. At the second stage, fruit juice packages with 20 package colours were rated using 5 bipolar scales: colour harmony, preference, freshness, naturalness and product quality. The experimental results show that th...

  9. High curvature bending characterization of ultra-thin chips and chip-on-foil assemblies

    NARCIS (Netherlands)

    Ende, D. van den; Verhoeven, F.; Eijnden, P. van der; Kusters, R.; Sridhar, A.; Cauwe, M.; Brand, J. van den

    2013-01-01

    Ultra-thin chips of less than 20μm become flexible, allowing integration of silicon IC technology with highly flexible electronics. This combination allows for highly intelligent products of unprecedented thinness, flexibility and cost. Examples include sensor systems integrated into food packaging

  10. Preparation for full scale demonstration of an air staged gasifier plant. Technical project development; For combined heat and power production with wood chips; Forberedelse til fuldskala demonstration af trinopdelt forgasningsanlaeg. Teknisk projektudvikling. Delrapport

    Energy Technology Data Exchange (ETDEWEB)

    Houmann Jakobsen, H.

    2011-04-15

    The project has aimed to further develop the technology for staged biomass gasification and establish an organizational and financial model to ensure that the technology can be introduced on the market. This report describes the technique in an upcoming demonstration plant. A complete planning and design of a demonstration plant with a capacity of 300 kW electric power and 700 kW heat was prepared. That is four times more than the pilot plant at Graested District Heating (Castor plant) can produce. A full scale demonstration plant with bio-gasification technology for wood chips will be established and put into operation in 2012. (ln)

  11. Demountable, high density package for high-speed testing of superconducting circuits

    International Nuclear Information System (INIS)

    This paper reports on a package that permits both quick integrated circuit (IC) throughput and high signal speed testing of superconducting devices and circuits. THe package contains 21 high-speed transmission lines and 64 dc bias lines contacting a 1 cm2 i.e. A novel demountable flip-chip connector incorporating both spring loaded and cantilever beam contacts maintains adequate chip to carrier continuity to allow signals from dc to 2 GHz to pass with minimal distortion at 4.2 K. The modular design of the connector and chip carrier allows maximum versatility in fast turnaround time testing

  12. Tunable on chip optofluidic laser

    DEFF Research Database (Denmark)

    Bakal, Avraham; Vannahme, Christoph; Kristensen, Anders;

    2015-01-01

    A chip scale tunable laser in the visible spectral band is realized by generating a periodic droplet array inside a microfluidic channel. Combined with a gain medium within the droplets, the periodic structure provides the optical feedback of the laser. By controlling the pressure applied to two...

  13. nu-TRLan User Guide Version 1.0: A High-Performance Software Package for Large-Scale Harmitian Eigenvalue Problems

    Energy Technology Data Exchange (ETDEWEB)

    Yamazaki, Ichitaro; Wu, Kesheng; Simon, Horst

    2008-10-27

    The original software package TRLan, [TRLan User Guide], page 24, implements the thick restart Lanczos method, [Wu and Simon 2001], page 24, for computing eigenvalues {lambda} and their corresponding eigenvectors v of a symmetric matrix A: Av = {lambda}v. Its effectiveness in computing the exterior eigenvalues of a large matrix has been demonstrated, [LBNL-42982], page 24. However, its performance strongly depends on the user-specified dimension of a projection subspace. If the dimension is too small, TRLan suffers from slow convergence. If it is too large, the computational and memory costs become expensive. Therefore, to balance the solution convergence and costs, users must select an appropriate subspace dimension for each eigenvalue problem at hand. To free users from this difficult task, nu-TRLan, [LNBL-1059E], page 23, adjusts the subspace dimension at every restart such that optimal performance in solving the eigenvalue problem is automatically obtained. This document provides a user guide to the nu-TRLan software package. The original TRLan software package was implemented in Fortran 90 to solve symmetric eigenvalue problems using static projection subspace dimensions. nu-TRLan was developed in C and extended to solve Hermitian eigenvalue problems. It can be invoked using either a static or an adaptive subspace dimension. In order to simplify its use for TRLan users, nu-TRLan has interfaces and features similar to those of TRLan: (1) Solver parameters are stored in a single data structure called trl-info, Chapter 4 [trl-info structure], page 7. (2) Most of the numerical computations are performed by BLAS, [BLAS], page 23, and LAPACK, [LAPACK], page 23, subroutines, which allow nu-TRLan to achieve optimized performance across a wide range of platforms. (3) To solve eigenvalue problems on distributed memory systems, the message passing interface (MPI), [MPI forum], page 23, is used. The rest of this document is organized as follows. In Chapter 2 [Installation

  14. Packaging Aspects of Photodetector Modules for 100 Gbit/s Ethernet Applications

    DEFF Research Database (Denmark)

    Jiang, Chenhui; Mekonnen, G.G.; Krozer, Viktor;

    2008-01-01

    Packaging is a major problem at millimetre-wave frequencies approaching 100 GHz. In this paper we present that insertion losses in a multi-chip module (MCM) can be less IL <0.6 dB at 100 GHz. The paper also analyzes in detail resonance modes in the packages. The characteristic of conductor-backed...

  15. Packaging of silicon sensors for microfluidic bio-analytical applications

    International Nuclear Information System (INIS)

    A new industrial concept is presented for packaging biosensor chips in disposable microfluidic cartridges to enable medical diagnostic applications. The inorganic electronic substrates, such as silicon or glass, are integrated in a polymer package which provides the electrical and fluidic interconnections to the world and provides mechanical strength and protection for out-of-lab use. The demonstrated prototype consists of a molded interconnection device (MID), a silicon-based giant magneto-resistive (GMR) biosensor chip, a flex and a polymer fluidic part with integrated tubing. The various processes are compatible with mass manufacturing and run at a high yield. The devices show a reliable electrical interconnection between the sensor chip and readout electronics during extended wet operation. Sandwich immunoassays were carried out in the cartridges with surface functionalized sensor chips. Biological response curves were determined for different concentrations of parathyroid hormone (PTH) on the packaged biosensor, which demonstrates the functionality and biocompatibility of the devices. The new packaging concept provides a platform for easy further integration of electrical and fluidic functions, as for instance required for integrated molecular diagnostic devices in cost-effective mass manufacturing

  16. Materials for optoelectronic device packaging/manufacturing

    Science.gov (United States)

    Lin, Yuan-Chang

    The first part of this work is to review the materials challenges and solutions for the packaging of high power LEDs, i.e., the light extraction efficiency, thermal and UV stability, and stress/delamination, which are all related to the reliability and lifetime of high power LEDs. The second part of this work is related to the development of transparent epoxy and silicone materials for the packaging of LEDs and the studies of light transmission stability under various treatments, including thermal, UV and combined treatments. It is found out that packaged high power blue LEDs encapsulated by epoxy materials have a very short lifetime due to the severe discoloration of epoxy at die-encapsulant interface caused by high flux radiation and junction temperature from LED chip. However, the reliability of formulated silicone outperforms epoxy materials, which can be explain by highly transparent in the UV-visible wavelength region and better thermal and UV resistance of silicone materials. The third part of this work is related to the study of optical properties of white LEDs, i.e., optical power, luminous efficiency, CCT, chromaticity coordinate and CRI as a function of phosphor wt% in silicone for the flat-top (FT) and flat-top-with lens (FTWL) packages. Due to the total internal reflection (TIR) at the encapsulant-air interface, the FT package shows a 10˜11% power (in mW) reduction compared with the FTWL package at the same phosphor concentration. However, it is demonstrated that the FT package provides a more efficient way of utilizing phosphor than the FTWL package based on the same targeted chromaticity coordinates due to the TIR effect inside, resulting in a reduced phosphor usage with a lumen output only about 3% lower than that of the FTWL package. Furthermore, the effects of fumed silica on optical properties are studied for these packages. In comparison to the package without fumed silica, the package with fumed silica has the advantages in anti-settling of

  17. Packaging for logistical support

    Science.gov (United States)

    Twede, Diana; Hughes, Harold

    Logistical packaging is conducted to furnish protection, utility, and communication for elements of a logistical system. Once the functional requirements of space logistical support packaging have been identified, decision-makers have a reasonable basis on which to compare package alternatives. Flexible packages may be found, for example, to provide adequate protection and superior utility to that of rigid packages requiring greater storage and postuse waste volumes.

  18. Challenges in the Packaging of MEMS

    Energy Technology Data Exchange (ETDEWEB)

    BROWN, WILLIAM D.; EATON, WILLIAM P.; MALSHE, AJAY P.; MILLER, WILLIAM M.; O' NEAL, CHAD; SINGH, SUSHILA B.

    1999-09-24

    Microelectromechanical Systems (MEMS) packaging is much different from conventional integrated circuit (IC) packaging. Many MEMS devices must interface to the environment in order to perform their intended function, and the package must be able to facilitate access with the environment while protecting the device. The package must also not interfere with or impede the operation of the MEMS device. The die attachment material should be low stress, and low outgassing, while also minimizing stress relaxation overtime which can lead to scale factor shifts in sensor devices. The fabrication processes used in creating the devices must be compatible with each other, and not result in damage to the devices. Many devices are application specific requiring custom packages that are not commercially available. Devices may also need media compatible packages that can protect the devices from harsh environments in which the MEMS device may operate. Techniques are being developed to handle, process, and package the devices such that high yields of functional packaged parts will result. Currently, many of the processing steps are potentially harmful to MEMS devices and negatively affect yield. It is the objective of this paper to review and discuss packaging challenges that exist for MEMS systems and to expose these issues to new audiences from the integrated circuit packaging community.

  19. Efficacy of 10% whole Azadirachta indica (neem) chip as an adjunct to scaling and root planning in chronic periodontitis: A clinical and microbiological study

    OpenAIRE

    K Vennila; Elanchezhiyan, S.; Sugumari Ilavarasu

    2016-01-01

    Introduction: Anti-microbial therapy is essential along with conventional therapy in the management of periodontal disease. Instead of systemic chemical agents, herbal products could be used as antimicrobial agents. Herbal local drug delivery systems are effective alternative for systemic therapy in managing the chronic periodontal disease. In this study, 10% neem oil chip was used as a local drug delivery system to evaluate the efficacy in the periodontal disease management. Materials an...

  20. Comparison of the copper and gold wire bonding processes for LED packaging*

    Institute of Scientific and Technical Information of China (English)

    Chen Zhaohui; Liu Yong; Liu Sheng

    2011-01-01

    Wire bonding is one of the main processes of the LED packaging which provides electrical interconnection between the LED chip and lead frame The gold wire bonding process has been widely used in LED packaging industry currently. However, due to the high cost of gold wire, copper wire bonding is a good substitute for the gold wire bonding which can lead to significant cost saving. In this paper, the copper and gold wire bonding processes on the high power LED chip are compared and analyzed with finite element simulation. This modeling work may provide guidelines for the parameter optimization of coppor wire bonding process on the high power LED packaging.

  1. Mechanical and electrical properties of ultra-thin chips and flexible electronics assemblies during bending

    NARCIS (Netherlands)

    Van Den Ende, D.A.; Van De Wiel, H.J.; Kusters, R.H.L.; Sridhar, A.; Schram, J.F.M.; Cauwe, M.; Van Den Brand, J.

    2014-01-01

    Ultra-thin chips of less than 20 μm become flexible, allowing integration of silicon IC technology with highly flexible electronics such as food packaging sensor systems or healthcare and sport monitoring tags as wearable patches or even directly in clothing textile. The ultra-thin chips in these pr

  2. Micro packaged MEMS pressure sensor for intracranial pressure measurement

    Science.gov (United States)

    Xiong, Liu; Yan, Yao; Jiahao, Ma; Yanhang, Zhang; Qian, Wang; Zhaohua, Zhang; Tianling, Ren

    2015-06-01

    This paper presents a micro packaged MEMS pressure sensor for intracranial pressure measurement which belongs to BioMEMS. It can be used in lumbar puncture surgery to measure intracranial pressure. Miniaturization is key for lumbar puncture surgery because the sensor must be small enough to allow it be placed in the reagent chamber of the lumbar puncture needle. The size of the sensor is decided by the size of the sensor chip and package. Our sensor chip is based on silicon piezoresistive effect and the size is 400 × 400 μm2. It is much smaller than the reported polymer intracranial pressure sensors such as liquid crystal polymer sensors. In terms of package, the traditional dual in-line package obviously could not match the size need, the minimal size of recently reported MEMS-based intracranial pressure sensors after packaging is 10 × 10 mm2. In this work, we are the first to introduce a quad flat no-lead package as the package form of piezoresistive intracranial pressure sensors, the whole size of the sensor is minimized to only 3 × 3 mm2. Considering the liquid measurement environment, the sensor is gummed and waterproof performance is tested; the sensitivity of the sensor is 0.9 × 10-2 mV/kPa. Project supported by the National Natural Science Foundation of China (Nos. 61025021, 61434001), and the ‘Thousands Talents’ Program for Pioneer Researchers and Its Innovation Team, China.

  3. Heterogeneously integrated microsystem-on-a-chip

    Science.gov (United States)

    Chanchani, Rajen

    2008-02-26

    A microsystem-on-a-chip comprises a bottom wafer of normal thickness and a series of thinned wafers can be stacked on the bottom wafer, glued and electrically interconnected. The interconnection layer comprises a compliant dielectric material, an interconnect structure, and can include embedded passives. The stacked wafer technology provides a heterogeneously integrated, ultra-miniaturized, higher performing, robust and cost-effective microsystem package. The highly integrated microsystem package, comprising electronics, sensors, optics, and MEMS, can be miniaturized both in volume and footprint to the size of a bottle-cap or less.

  4. Design and Simulation of High-power LED Array Packaging

    Institute of Scientific and Technical Information of China (English)

    TIAN Da-lei; GUAN Rong-feng; WANG Xing

    2008-01-01

    Thermal management is one of the key technologies for high-power Light emitting diode(LED) entering into the general illuminating field. Successful thermal management depends on optimal packaging structure and selected packaging materials. In this paper, the aluminum is employed as a substrate of LED, 3×3 array chips are placed on the substrate, heat dissipation performance is simulated using finite element analysis(FEA) software, analyzed are the influences on the temperature of the chip with different convection coefficient, and optical properties are simulated using optical analysis software. The results show that the packaging structure can not only effectually improve the thermal performance of high-power LED array but also increase the light extraction efficiency.

  5. Cool down computer chips with liquid metal device driven by the heat of chips

    Institute of Scientific and Technical Information of China (English)

    2008-01-01

    @@ With the soaring advances in computational speed, thermal management becomes a major concern in computer systems. To remove heat generated by computer chips or very large scale integrated circuits, a research team headed by Prof.

  6. The reduction of packaging waste

    Energy Technology Data Exchange (ETDEWEB)

    Raney, E.A.; Hogan, J.J.; McCollom, M.L.; Meyer, R.J.

    1994-04-01

    Nationwide, packaging waste comprises approximately one-third of the waste disposed in sanitary landfills. the US Department of Energy (DOE) generated close to 90,000 metric tons of sanitary waste. With roughly one-third of that being packaging waste, approximately 30,000 metric tons are generated per year. The purpose of the Reduction of Packaging Waste project was to investigate opportunities to reduce this packaging waste through source reduction and recycling. The project was divided into three areas: procurement, onsite packaging and distribution, and recycling. Waste minimization opportunities were identified and investigated within each area, several of which were chosen for further study and small-scale testing at the Hanford Site. Test results, were compiled into five ``how-to`` recipes for implementation at other sites. The subject of the recipes are as follows: (1) Vendor Participation Program; (2) Reusable Containers System; (3) Shrink-wrap System -- Plastic and Corrugated Cardboard Waste Reduction; (4) Cardboard Recycling ; and (5) Wood Recycling.

  7. Packaging for Food Service

    Science.gov (United States)

    Stilwell, E. J.

    1985-01-01

    Most of the key areas of concern in packaging the three principle food forms for the space station were covered. It can be generally concluded that there are no significant voids in packaging materials availability or in current packaging technology. However, it must also be concluded that the process by which packaging decisions are made for the space station feeding program will be very synergistic. Packaging selection will depend heavily on the preparation mechanics, the preferred presentation and the achievable disposal systems. It will be important that packaging be considered as an integral part of each decision as these systems are developed.

  8. On-chip cooling by superlattice-based thin-film thermoelectrics

    Science.gov (United States)

    Chowdhury, Ihtesham; Prasher, Ravi; Lofgreen, Kelly; Chrysler, Gregory; Narasimhan, Sridhar; Mahajan, Ravi; Koester, David; Alley, Randall; Venkatasubramanian, Rama

    2009-04-01

    There is a significant need for site-specific and on-demand cooling in electronic, optoelectronic and bioanalytical devices, where cooling is currently achieved by the use of bulky and/or over-designed system-level solutions. Thermoelectric devices can address these limitations while also enabling energy-efficient solutions, and significant progress has been made in the development of nanostructured thermoelectric materials with enhanced figures-of-merit. However, fully functional practical thermoelectric coolers have not been made from these nanomaterials due to the enormous difficulties in integrating nanoscale materials into microscale devices and packaged macroscale systems. Here, we show the integration of thermoelectric coolers fabricated from nanostructured Bi2Te3-based thin-film superlattices into state-of-the-art electronic packages. We report cooling of as much as 15 °C at the targeted region on a silicon chip with a high (~1,300 W cm-2) heat flux. This is the first demonstration of viable chip-scale refrigeration technology and has the potential to enable a wide range of currently thermally limited applications.

  9. Coupling structure in LED System-in-Package design: a physical responses-based critical parameter sheet like approach

    NARCIS (Netherlands)

    Borst, E.C.M. de; Gielen, A.W.J.; Etman, L.F.P.

    2012-01-01

    This paper introduces an approach to study the coupling structure between the design parameters and design objectives of a LED system-in-package (SiP) design concept [1]. The LED SiP is an integrated device that combines the LED chip with driver chips and potential other components in a single packa

  10. Use of pilot plant scale continuous fryer to simulate industrial production of potato chips: thermal properties of palm olein blends under continuous frying conditions

    OpenAIRE

    Tarmizi, Azmil Haizam Ahmad; Ismail, Razali

    2013-01-01

    Binary blends of palm olein (PO) with sunflower oil (SFO), canola oil (CNO), and cottonseed oil (CSO) were formulated to assess their stability under continuous frying conditions. The results were then compared with those obtained in PO. The oil blends studied were: (1) 60:40 for PO + SFO; (2) 70:30 for PO + CNO; and (3) 50:50 for PO + CSO. The PO and its blends were used to fry potato chips at 180°C for a total of 56 h of operation. The evolution of analytical parameters such as tocols, indu...

  11. Effect of Joint Scale and Processing on the Fracture of Sn-3Ag-0.5Cu Solder Joints: Application to Micro-bumps in 3D Packages

    Science.gov (United States)

    Talebanpour, B.; Huang, Z.; Chen, Z.; Dutta, I.

    2016-01-01

    In 3-dimensional (3D) packages, a stack of dies is vertically connected to each other using through-silicon vias and very thin solder micro-bumps. The thinness of the micro-bumps results in joints with a very high volumetric proportion of intermetallic compounds (IMCs), rendering them much more brittle compared to conventional joints. Because of this, the reliability of micro-bumps, and the dependence thereof on the proportion of IMC in the joint, is of substantial concern. In this paper, the growth kinetics of IMCs in thin Sn-3Ag-0.5Cu joints attached to Cu substrates were analyzed, and empirical kinetic laws for the growth of Cu6Sn5 and Cu3Sn in thin joints were obtained. Modified compact mixed mode fracture mechanics samples, with adhesive solder joints between massive Cu substrates, having similar thickness and IMC content as actual micro-bumps, were produced. The effects of IMC proportion and strain rate on fracture toughness and mechanisms were investigated. It was found that the fracture toughness G C decreased with decreasing joint thickness ( h Joint). In addition, the fracture toughness decreased with increasing strain rate. Aging also promoted alternation of the crack path between the two joint-substrate interfaces, possibly proffering a mechanism to enhance fracture toughness.

  12. Comparative Packaging Study

    Science.gov (United States)

    Perchonok, Michele; Antonini, David

    2008-01-01

    This viewgraph presentation describes a comparative packaging study for use on long duration space missions. The topics include: 1) Purpose; 2) Deliverables; 3) Food Sample Selection; 4) Experimental Design Matrix; 5) Permeation Rate Comparison; and 6) Packaging Material Information.

  13. Dual Use Packaging Project

    Data.gov (United States)

    National Aeronautics and Space Administration — NASA seeks down-weighted packaging compatible with microwave preparation and perhaps high hydrostatic pressure processing. New packaging must satisfy NASA's 3-year...

  14. Merganser Download Package

    Data.gov (United States)

    U.S. Environmental Protection Agency — This data download package contains an Esri 10.0 MXD, file geodatabase and copy of this FGDC metadata record. The data in this package are used in support of the...

  15. Recycling glass packaging

    OpenAIRE

    Monica Delia DOMNICA; Leila BARDAªUC

    2015-01-01

    From the specialized literature it follows that glass packaging is not as used as other packages, but in some industries are highly needed. Following, two features of glass packaging will become important until 2017: the shape of the glass packaging and glass recycling prospects in Romania. The recycling of glass is referred to the fact that it saves energy, but also to be in compliance with the provisions indicating the allowable limit values for the quantities of lead and cadmium.

  16. Materials for advanced packaging

    CERN Document Server

    Wong, CP

    2008-01-01

    Significant progress has been made in advanced packaging in recent years. Several new packaging techniques have been developed and new packaging materials have been introduced. This book provides a comprehensive overview of the recent developments in this industry, particularly in the areas of microelectronics, optoelectronics, digital health, and bio-medical applications. The book discusses established techniques, as well as emerging technologies, in order to provide readers with the most up-to-date developments in advanced packaging.

  17. ATLAS software packaging

    Science.gov (United States)

    Rybkin, Grigory

    2012-12-01

    Software packaging is indispensable part of build and prerequisite for deployment processes. Full ATLAS software stack consists of TDAQ, HLT, and Offline software. These software groups depend on some 80 external software packages. We present tools, package PackDist, developed and used to package all this software except for TDAQ project. PackDist is based on and driven by CMT, ATLAS software configuration and build tool, and consists of shell and Python scripts. The packaging unit used is CMT project. Each CMT project is packaged as several packages—platform dependent (one per platform available), source code excluding header files, other platform independent files, documentation, and debug information packages (the last two being built optionally). Packaging can be done recursively to package all the dependencies. The whole set of packages for one software release, distribution kit, also includes configuration packages and contains some 120 packages for one platform. Also packaged are physics analysis projects (currently 6) used by particular physics groups on top of the full release. The tools provide an installation test for the full distribution kit. Packaging is done in two formats for use with the Pacman and RPM package managers. The tools are functional on the platforms supported by ATLAS—GNU/Linux and Mac OS X. The packaged software is used for software deployment on all ATLAS computing resources from the detector and trigger computing farms, collaboration laboratories computing centres, grid sites, to physicist laptops, and CERN VMFS and covers the use cases of running all applications as well as of software development.

  18. Genome packaging in viruses

    OpenAIRE

    Sun, Siyang; Rao, Venigalla B.; Rossmann, Michael G.

    2010-01-01

    Genome packaging is a fundamental process in a viral life cycle. Many viruses assemble preformed capsids into which the genomic material is subsequently packaged. These viruses use a packaging motor protein that is driven by the hydrolysis of ATP to condense the nucleic acids into a confined space. How these motor proteins package viral genomes had been poorly understood until recently, when a few X-ray crystal structures and cryo-electron microscopy structures became available. Here we discu...

  19. Materials for advanced packaging

    CERN Document Server

    Lu, Daniel

    2010-01-01

    Significant progress has been made in advanced packaging in recent years. Several new packaging techniques have been developed and new packaging materials have been introduced. This book provides a comprehensive overview of the recent developments in this industry, particularly in the areas of microelectronics, optoelectronics, digital health, and bio-medical applications. The book discusses established techniques, as well as emerging technologies, in order to provide readers with the most up-to-date developments in advanced packaging.

  20. Central heating: package boilers

    Energy Technology Data Exchange (ETDEWEB)

    Farahan, E.

    1977-05-01

    Performance and cost data for electrical and fossil-fired package boilers currently available from manufacturers are provided. Performance characteristics investigated include: unit efficiency, rated capacity, and average expected lifetime of units. Costs are tabulated for equipment and installation of various package boilers. The information supplied in this report will simplify the process of selecting package boilers required for industrial, commercial, and residential applications.

  1. Trends in Food Packaging.

    Science.gov (United States)

    Ott, Dana B.

    1988-01-01

    This article discusses developments in food packaging, processing, and preservation techniques in terms of packaging materials, technologies, consumer benefits, and current and potential food product applications. Covers implications due to consumer life-style changes, cost-effectiveness of packaging materials, and the ecological impact of…

  2. Biobased packaging catalogue

    NARCIS (Netherlands)

    Molenveld, K.; Oever, van den M.J.A.; Bos, H.L.

    2015-01-01

    The purpose of the catalogue is to showcase biobased packaging products and provide an overview of commercially available biobased packaging in 2014. This catalogue is a translation of the Dutch version of the biobased packaging catalogue that was launched September 2014. The raw materials, products

  3. Can packaging elements elicit consumers’ emotional responses?

    DEFF Research Database (Denmark)

    Liao, Lewis; Corsi, Armando; Lockshin, Larry;

    Emotion has been an important concept in many areas of consumer research such as judgment, decision-making and advertising. Little research has been done on emotion in packaging adopting the physiological measures used in other areas. This paper draws on past studies in advertising that measure...... emotional responses toward image, colour and font, and apply them to packaging research. The study tests the extent at which packaging can elicit consumers’ spontaneous emotional response for each of those three elements, by using skin conductance, facial electromyography (EMG) and selfassessment scales....... The results show that packaging can elicit an emotional response via different elements. The paper also raises concerns about the accuracy of using selfreport measures of emotional responses to packaging research....

  4. Service Packages – Attractiveness Has Many Faces

    Directory of Open Access Journals (Sweden)

    Ilona Bondos

    2016-01-01

    Full Text Available This article is an attempt to identify the impact of the customer age (especially the Baby boomers generation and the X and the Y generation on the assessment of incentives to buy service package. Belonging to different age generations seems to be important for the effectiveness of service packages sales – the entrance by the consumers in subsequent phases of the life cycle is related to their perception of the market offer. The starting point for the empirical part of the article was to analyze the different average scores attractiveness of the ten packages service features (incentives to purchase. Then, using multidimensional scaling authors determined the similarity or dissimilarity data on a set of applied incentives to use service packages. Visible differences indicate a different perception of the attractiveness of packages representatives of the Baby boomer generation and Y generation. Managerial implications and directions for future research are discussed.

  5. Redsharc: A Programming Model and On-Chip Network for Multi-Core Systems on a Programmable Chip

    OpenAIRE

    Kritikos, William V.; Andrew G. Schmidt; Ron Sass; Anderson, Erik K.; Matthew French

    2012-01-01

    The reconfigurable data-stream hardware software architecture (Redsharc) is a programming model and network-on-a-chip solution designed to scale to meet the performance needs of multi-core Systems on a programmable chip (MCSoPC). Redsharc uses an abstract API that allows programmers to develop systems of simultaneously executing kernels, in software and/or hardware, that communicate over a seamless interface. Redsharc incorporates two on-chip networks that directly implement the API to suppor...

  6. Cleanup Verification Package for the 118-F-1 Burial Ground

    International Nuclear Information System (INIS)

    This cleanup verification package documents completion of remedial action for the 118-F-1 Burial Ground on the Hanford Site. This burial ground is a combination of two locations formerly called Minor Construction Burial Ground No. 2 and Solid Waste Burial Ground No. 2. This waste site received radioactive equipment and other miscellaneous waste from 105-F Reactor operations, including dummy elements and irradiated process tubing; gun barrel tips, steel sleeves, and metal chips removed from the reactor; filter boxes containing reactor graphite chips; and miscellaneous construction solid waste

  7. Cleanup Verification Package for the 118-F-1 Burial Ground

    Energy Technology Data Exchange (ETDEWEB)

    E. J. Farris and H. M. Sulloway

    2008-01-10

    This cleanup verification package documents completion of remedial action for the 118-F-1 Burial Ground on the Hanford Site. This burial ground is a combination of two locations formerly called Minor Construction Burial Ground No. 2 and Solid Waste Burial Ground No. 2. This waste site received radioactive equipment and other miscellaneous waste from 105-F Reactor operations, including dummy elements and irradiated process tubing; gun barrel tips, steel sleeves, and metal chips removed from the reactor; filter boxes containing reactor graphite chips; and miscellaneous construction solid waste.

  8. Chip-on-flex with 5-micron features

    Science.gov (United States)

    Salmon, Peter C.

    2003-01-01

    A new module packaging method is proposed for electronic systems comprising a motherboard and integrated circuit (IC) chips. Pitches of 10 microns for conductive traces, and 100 microns for bonding pads are achievable. The enabling technology is glass panel manufacture, using equipment and techniques similar to those employed for fabricating liquid crystal display (LCD) panels. Flexible circuits are produced on a glass carrier using a release layer, and the carrier is removed after most of the processing is complete. IC chips are stud bumped and flip chip bonded to wells filled with solder, provided on the flexible circuit. The fabrication density achievable with wafer level packaging (WLP) using silicon wafers is substantially more than is needed for module packaging, as described herein. It is possible to provide WLP performance on glass at a much lower cost. The conductor features on glass are fine enough for the most demanding packaging and assembly techniques. The lowered cost of glass applies to the interconnection circuit plus assembly, test and rework. A test method called Tester-On-Board (TOB) is proposed, employing special-purpose test chips that are directly mounted in the system and mimic the capabilities of external testers. Methods for hermetic sealing, electromagnetic screening, and high-density off-board connections are also proposed.

  9. APPLICATION OF NANOTECHNOLOGY IN FOOD PACKAGING

    Directory of Open Access Journals (Sweden)

    Renata Dobrucka

    2014-04-01

    Full Text Available Nanotechnology involves the design, production and use of structures through control of the size and shape of the materials at the nanometre scale. Also, nanomaterials have been already applied in many fields of human life. Nanocomposites have already led to several innovations with potential applications in the food packaging sector. The use of nanocomposite formulations is expected to considerably enhance the shelf-life of many types of food. This improvement can lead to lower weight packages because less material is needed to obtain the same or even better barrier properties. This, in turn, can lead to reduced package cost with less packaging waste. Antimicrobial packaging is another area with high potential for applying nanocomposite technology. Nanostructured antimicrobials have a higher surface area-to-volume ratio when compared with their higher scale counterparts. Therefore, antimicrobial nanocomposite packaging systems are supposed to be particularly efficient in their activities against microbial cells. In this review, definition of nanomaterials is presented. Besides, the paper shows examples of nanocomposities and antimicrobial nanopackaging mainly with the use of nanosilver. Moreover, nanoparticles such ZnO, TiO2, MgO and nanosensors in packaging were presented.

  10. Advanced Flip Chips in Extreme Temperature Environments

    Science.gov (United States)

    Ramesham, Rajeshuni

    2010-01-01

    material and the silicon die or chip, and also the underfill materials. Advanced packaging interconnects technology such as flip-chip interconnect test boards have been subjected to various extreme temperature ranges that cover military specifications and extreme Mars and asteroid environments. The eventual goal of each process step and the entire process is to produce components with 100 percent interconnect and satisfy the reliability requirements. Underfill materials, in general, may possibly meet demanding end use requirements such as low warpage, low stress, fine pitch, high reliability, and high adhesion.

  11. An all-solid-state, WDM silicon photonic digital link for chip-to-chip communications.

    Science.gov (United States)

    Thacker, Hiren D; Zheng, Xuezhe; Lexau, Jon; Shafiiha, Roshanak; Shubin, Ivan; Lin, Shiyun; Djordjevic, Stevan; Amberg, Philip; Chang, Eric; Liu, Frankie; Simons, John; Lee, Jin-Hyoung; Abed, Arin; Liang, Hong; Luo, Ying; Yao, Jin; Feng, Dazeng; Asghari, Mehdi; Ho, Ron; Raj, Kannan; Cunningham, John E; Krishnamoorthy, Ashok V

    2015-05-18

    We describe a multiwavelength hybrid-integrated solid-state link on a 3 µm silicon-on-insulator (SOI) nanophotonic platform. The link spans three chips and employs germanium-silicon electroabsorption waveguide modulators, silicon transport waveguides, echelle gratings for multiplexing and demultiplexing, and pure germanium waveguide photo-detectors. The 8λ WDM Tx and Rx components are interconnected via a routing "bridge" chip using edge-coupled optical proximity communication. The packaged, retimed digital WDM link is demonstrated at 10 Gb/s and 10(-12) BER, with three wavelength channels consuming an on-chip power below 1.5 pJ/bit, excluding the external laser power.

  12. Chlorhexidine Chip in the Treatment of Chronic Periodontitis – A Clinical Study

    OpenAIRE

    Medaiah, Sangeetha; Srinivas, M; Melath, Anil; Girish, Suragimath; Polepalle, Tejaswin; Dasari, Ankineedu Babu

    2014-01-01

    Aim: The aim of this study was to clinically evaluate the use of biodegradable chlorhexidine chip when used as an adjunct to scaling and root planing (SRP) in the treatment of moderate to severe periodontitis patients. The study also intended to compare the combined therapy (SRP and Chlorhexidine chip) with chlorhexidine chip alone in individuals with periodontitis.

  13. Pixel detector readout chip

    CERN Multimedia

    1991-01-01

    Close-up of a pixel detector readout chip. The photograph shows an aera of 1 mm x 2 mm containing 12 separate readout channels. The entire chip contains 1000 readout channels (around 80 000 transistors) covering a sensitive area of 8 mm x 5 mm. The chip has been mounted on a silicon detector to detect high energy particles.

  14. Adapting MCM-D technology to a piezoresistive accelerometer packaging

    Science.gov (United States)

    Collado, A.; Plaza, J. A.; Cabruja, E.; Esteve, J.

    2003-07-01

    A silicon-on-silicon multichip module for a piezoresistive accelerometer is presented in this paper. This packaging technology, a type of wafer level packaging, offers fully complementary metal-oxide semiconductor compatible silicon substrates, so a pre-amplification stage can be included at substrate level. The electrical contacts and a partial sealing of the sensor mobile structures are performed at the same step using flip-chip technology, so the cost is reduced. As accelerometers are stress-sensitive devices, great care must be taken in the fabrication process and materials. Thus, test structures have been included to study the packaging effects. In this paper we report on the compatibility of accelerometer and wafer level packaging technologies.

  15. Optimal and Robust Design Method for Two-Chip Out-of-Plane Microaccelerometers

    Directory of Open Access Journals (Sweden)

    Hyoungho Ko

    2010-11-01

    Full Text Available In this paper, an optimal and robust design method to implement a two-chip out-of-plane microaccelerometer system is presented. The two-chip microsystem consists of a MEMS chip for sensing the external acceleration and a CMOS chip for signal processing. An optimized design method to determine the device thickness, the sacrificial gap, and the vertical gap length of the M EMS sensing element is applied to minimize the fundamental noise level and also to achieve the robustness to the fabrication variations. In order to cancel out the offset and gain variations due to parasitic capacitances and process variations, a digitally trimmable architecture consisting of an 11 bit capacitor array is adopted in the analog front-end of the CMOS capacitive readout circuit. The out-of-plane microaccelerometer has the scale factor of 372 mV/g~389 mV/g, the output nonlinearity of 0.43% FSO~0.60% FSO, the input range of ±2 g and a bias instability of 122 μg~229 μg. The signal-to-noise ratio and the noise equivalent resolution are measured to be74.00 dB~75.23 dB and 180 μg/rtHz~190 μg/rtHz, respectively. The in-plane cross-axis sensitivities are measured to be 1.1%~1.9% and 0.3%~0.7% of the out-of-plane sensitivity, respectively. The results show that the optimal and robust design method for the MEMS sensing element and the highly trimmable capacity of the CMOS capacitive readout circuit are suitable to enhance the die-to-die uniformity of the packaged microsystem, without compromising the performance characteristics.

  16. Hardware support for CSP on a Java chip multiprocessor

    DEFF Research Database (Denmark)

    Gruian, Flavius; Schoeberl, Martin

    2013-01-01

    Due to memory bandwidth limitations, chip multiprocessors (CMPs) adopting the convenient shared memory model for their main memory architecture scale poorly. On-chip core-to-core communication is a solution to this problem, that can lead to further performance increase for a number of multithread...

  17. Quality requirements for forest chips; Kaeyttaejien laatuvaatimukset metsaehakkeelle

    Energy Technology Data Exchange (ETDEWEB)

    Impola, R. [VTT Energy, Jyvaeskylae (Finland)

    1999-07-01

    utilization of forest chips. Increasing utilization volumes may require industrial-scale production of forest chips. By using proper storage arrangements, it is possible to guarantee the better quality of forest chips and the deliveries all year round even when the road conditions are poor. Significant factors effecting on the utilization of forest chips in the future are also the price of the chips and the price-competitiveness on site compared to other fuels.

  18. Alignment of microcircuit chips using optically smeared images.

    Science.gov (United States)

    Lewis, R W

    1979-02-01

    An optical method for determining the position of microcircuit chips for wirebonding or electrical testing stations was evaluated. Optically smearing the chip image in one direction with a cylindrical lens produces a convenient means for determining both chip angular orientation and position. Digitized images from a linear photodiode array camera were analyzed. The results show that a class of microcircuit chips with medium scale integration can be aligned in angle and position to a higher accuracy than required for wirebonding and electrical testing stations. PMID:20208714

  19. ANALYTICAL CHIP FORMATION MODEL OF MICRO-END-MILLING

    Institute of Scientific and Technical Information of China (English)

    LI Chengfeng; LAI Xinmin; LI Hongtao; PENG Linfa; NI Jun

    2008-01-01

    A new analytical chip formation model is proposed for micro-end-milling operations. The model calculates an instantaneous uncut chip thickness by considering the combination of exact trochoidal trajectory of the tool tip and tool run-out, while the simplified circular trajectory and the neglected run-out create negligible change in conventional-scale chip formation models. Newton-Raphson iterative method is employed during the calculation to obtain quadratic convergence. The proposed approach allows the calculation of instantaneous uncut chip thickness to be done accurately and rapidly, and the prediction accuracy of this model is also verified by comparing the simulation results to experimental cutting forces.

  20. Ideal luminous efficacy and color spatial uniformity of package-free LED based on a packaging phosphor-coated geometry.

    Science.gov (United States)

    Lee, Tsung-Xian; Chou, Chien-Feng

    2016-09-20

    This paper presents the optical simulation of the luminous efficacy of radiation (LER) and color spatial uniformity (CSU) of a package-free white LED conducted to boost the LER and simultaneously improve the CSU. According to the simulation results, the main effect on the LER and CSU was the change in the geometrical ratio of phosphor coating. Regardless of the packaging size, when the ratio of the top coating to the sidewall coverage of the phosphor layer thickness was in the range from 0.9 to 1.1, the maximum LER and optimal CSU can be simultaneously obtained. Besides, effectively increasing the volume of the overall packaging dimension to be 30 times the size of the chip can enable a package-free LED to achieve 90% saturated maximum LER without affecting the CSU. PMID:27661598

  1. Smart packaging for photonics

    Energy Technology Data Exchange (ETDEWEB)

    Smith, J.H.; Carson, R.F.; Sullivan, C.T.; McClellan, G.; Palmer, D.W. [ed.

    1997-09-01

    Unlike silicon microelectronics, photonics packaging has proven to be low yield and expensive. One approach to make photonics packaging practical for low cost applications is the use of {open_quotes}smart{close_quotes} packages. {open_quotes}Smart{close_quotes} in this context means the ability of the package to actuate a mechanical change based on either a measurement taken by the package itself or by an input signal based on an external measurement. One avenue of smart photonics packaging, the use of polysilicon micromechanical devices integrated with photonic waveguides, was investigated in this research (LDRD 3505.340). The integration of optical components with polysilicon surface micromechanical actuation mechanisms shows significant promise for signal switching, fiber alignment, and optical sensing applications. The optical and stress properties of the oxides and nitrides considered for optical waveguides and how they are integrated with micromechanical devices were investigated.

  2. Packaging for Sustainability

    CERN Document Server

    Lewis, Helen; Fitzpatrick, Leanne

    2012-01-01

    The packaging industry is under pressure from regulators, customers and other stakeholders to improve packaging’s sustainability by reducing its environmental and societal impacts. This is a considerable challenge because of the complex interactions between products and their packaging, and the many roles that packaging plays in the supply chain. Packaging for Sustainability is a concise and readable handbook for practitioners who are trying to implement sustainability strategies for packaging. Industry case studies are used throughout the book to illustrate possible applications and scenarios. Packaging for Sustainability draws on the expertise of researchers and industry practitioners to provide information on business benefits, environmental issues and priorities, environmental evaluation tools, design for environment, marketing strategies, and challenges for the future.

  3. Packaged die heater

    Science.gov (United States)

    Spielberger, Richard; Ohme, Bruce Walker; Jensen, Ronald J.

    2011-06-21

    A heater for heating packaged die for burn-in and heat testing is described. The heater may be a ceramic-type heater with a metal filament. The heater may be incorporated into the integrated circuit package as an additional ceramic layer of the package, or may be an external heater placed in contact with the package to heat the die. Many different types of integrated circuit packages may be accommodated. The method provides increased energy efficiency for heating the die while reducing temperature stresses on testing equipment. The method allows the use of multiple heaters to heat die to different temperatures. Faulty die may be heated to weaken die attach material to facilitate removal of the die. The heater filament or a separate temperature thermistor located in the package may be used to accurately measure die temperature.

  4. Development of gold based solder candidates for flip chip assembly

    DEFF Research Database (Denmark)

    Chidambaram, Vivek; Hald, John; Hattel, Jesper Henri

    2009-01-01

    Flip chip technology is now rapidly replacing the traditional wire bonding interconnection technology in the first level packaging applications due to the miniaturization drive in the microelectronics industry. Flip chip assembly currently involves the use of high lead containing solders...... for interconnecting the chip to a carrier in certain applications due to the unique properties of lead. Despite of all the beneficial attributes of lead, its potential environmental impact when the products are discarded to land fills has resulted in various legislatives to eliminate lead from the electronic products...... based on its notorious legacy as a major health hazard across the spectrum of human generations and cultures. Flip chip assembly is also now increasingly being used for the high-performance (H-P) systems. These H-P systems perform mission-critical operations and are expected to experience virtually...

  5. Packaging for meat products

    OpenAIRE

    Vojtíšková, Zuzana

    2014-01-01

    Packaging for meat products Summary Packaging is usually integral to production process in meat industry. The packing has mainly influence on shelf life and quality of meat and meat products. It protects the product from adverse effects such as oxidation, especially fats. In addition it affects transport, storage and serves as a means of communication with customers (logo, marketing benefits, legislation). Significant is also the impact of packaging to keep attractive look of the prod...

  6. LED packaging for lighting applications design, manufacturing, and testing

    CERN Document Server

    Liu, Sheng

    2011-01-01

    Since the first light-emitting diode (LED) was invented by Holonyak and Bevacqua in 1962, LEDs have made remarkable progress in the past few decades with the rapid development of epitaxy growth, chip design and manufacture, packaging structure, processes, and packaging materials. LEDs have superior characteristics such as high efficiency, small size, long life, low power consumption, and high reliability. The market for white LED is growing rapidly in various applications. It has been widely accepted that white LEDs will be the fourth illumination source to substitute the incandescent, fluores

  7. Plasma physics plotting package

    International Nuclear Information System (INIS)

    We describe a package of plotting routines that do up to six two- or three-dimensional plots on a frame with minimal loss of resolution. The package now runs on a PDP-10 with PLOT-10 TCS primitives and on a Control Data Corporation-7600 and a Cray-1 with TV80LIB primitives on the National Magnetic Fusion Energy Computer Center network. The package is portable to other graphics systems because only the primitive plot calls are used from the underlying system's graphics package

  8. HIRENASD analysis Information Package

    Data.gov (United States)

    National Aeronautics and Space Administration — Updated November 2, 2011 Contains summary information and analysis condition details for the Aeroelastic Prediction Workshop Information plotted in this package is...

  9. Packaging Technologies for 500 C SiC Electronics and Sensors: Challenges in Material Science and Technology

    Science.gov (United States)

    Chen, Liang-Yu; Neudeck, Philip G.; Behelm, Glenn M.; Spry, David J.; Meredith, Roger D.; Hunter, Gary W.

    2015-01-01

    This paper presents ceramic substrates and thick-film metallization based packaging technologies in development for 500C silicon carbide (SiC) electronics and sensors. Prototype high temperature ceramic chip-level packages and printed circuit boards (PCBs) based on ceramic substrates of aluminum oxide (Al2O3) and aluminum nitride (AlN) have been designed and fabricated. These ceramic substrate-based chip-level packages with gold (Au) thick-film metallization have been electrically characterized at temperatures up to 550C. The 96 alumina packaging system composed of chip-level packages and PCBs has been successfully tested with high temperature SiC discrete transistor devices at 500C for over 10,000 hours. In addition to tests in a laboratory environment, a SiC junction field-effect-transistor (JFET) with a packaging system composed of a 96 alumina chip-level package and an alumina printed circuit board was tested on low earth orbit for eighteen months via a NASA International Space Station experiment. In addition to packaging systems for electronics, a spark-plug type sensor package based on this high temperature interconnection system for high temperature SiC capacitive pressure sensors was also developed and tested. In order to further significantly improve the performance of packaging system for higher packaging density, higher operation frequency, power rating, and even higher temperatures, some fundamental material challenges must be addressed. This presentation will discuss previous development and some of the challenges in material science (technology) to improve high temperature dielectrics for packaging applications.

  10. Use of pilot plant scale continuous fryer to simulate industrial production of potato chips: thermal properties of palm olein blends under continuous frying conditions.

    Science.gov (United States)

    Tarmizi, Azmil Haizam Ahmad; Ismail, Razali

    2014-01-01

    Binary blends of palm olein (PO) with sunflower oil (SFO), canola oil (CNO), and cottonseed oil (CSO) were formulated to assess their stability under continuous frying conditions. The results were then compared with those obtained in PO. The oil blends studied were: (1) 60:40 for PO + SFO; (2) 70:30 for PO + CNO; and (3) 50:50 for PO + CSO. The PO and its blends were used to fry potato chips at 180°C for a total of 56 h of operation. The evolution of analytical parameters such as tocols, induction period, color, p-anisidine value, free fatty acid, smoke point, polar compounds, and polymer compounds were evaluated over the frying time. Blending PO with unsaturated oils was generally proved to keep most qualitative parameters comparable to those demonstrated in PO. Indeed, none of the oils surpassed the legislative limits for used frying. Overall, it was noted that oil containing PO and SFO showed higher resistance toward oxidative and hydrolytic behaviors as compared to the other oil blends. PMID:24804062

  11. Packaging Technologies for 500C SiC Electronics and Sensors

    Science.gov (United States)

    Chen, Liang-Yu

    2013-01-01

    Various SiC electronics and sensors are currently under development for applications in 500C high temperature environments such as hot sections of aerospace engines and the surface of Venus. In order to conduct long-term test and eventually commercialize these SiC devices, compatible packaging technologies for the SiC electronics and sensors are required. This presentation reviews packaging technologies developed for 500C SiC electronics and sensors to address both component and subsystem level packaging needs for high temperature environments. The packaging system for high temperature SiC electronics includes ceramic chip-level packages, ceramic printed circuit boards (PCBs), and edge-connectors. High temperature durable die-attach and precious metal wire-bonding are used in the chip-level packaging process. A high temperature sensor package is specifically designed to address high temperature micro-fabricated capacitive pressure sensors for high differential pressure environments. This presentation describes development of these electronics and sensor packaging technologies, including some testing results of SiC electronics and capacitive pressure sensors using these packaging technologies.

  12. 电子封装、QFP和MCM热变形的实验及数值分析%Experimental and Numerical Analysis of Thermal Deformation of Electronic Packages,QFP and MCM

    Institute of Scientific and Technical Information of China (English)

    2006-01-01

    Moiré inteferometry and FEA (finite element analysis) were used to evaluate the thermal deformation of two electronic packages, QFP (quad flat package) and MCM (multi chip module).Thermal loading was applied by cooling the packages from 100℃ to room temperature (25℃). Moiré fringes were obtained on the cross sections of the packages to clarify the effect of the CTE (coefficient of thermal expansion) mismatch of the micro components, such as silicon, metal and resin. In QFP, the effects of packaging resin and PCB (printed circuit board) on the thermal deformation were investigated. The effect of location of three silicon chips in MCM was also examined.

  13. 3-D readout-electronics packaging for high-bandwidth massively paralleled imager

    Science.gov (United States)

    Kwiatkowski, Kris; Lyke, James

    2007-12-18

    Dense, massively parallel signal processing electronics are co-packaged behind associated sensor pixels. Microchips containing a linear or bilinear arrangement of photo-sensors, together with associated complex electronics, are integrated into a simple 3-D structure (a "mirror cube"). An array of photo-sensitive cells are disposed on a stacked CMOS chip's surface at a 45.degree. angle from light reflecting mirror surfaces formed on a neighboring CMOS chip surface. Image processing electronics are held within the stacked CMOS chip layers. Electrical connections couple each of said stacked CMOS chip layers and a distribution grid, the connections for distributing power and signals to components associated with each stacked CSMO chip layer.

  14. WASTE PACKAGE TRANSPORTER DESIGN

    Energy Technology Data Exchange (ETDEWEB)

    D.C. Weddle; R. Novotny; J. Cron

    1998-09-23

    The purpose of this Design Analysis is to develop preliminary design of the waste package transporter used for waste package (WP) transport and related functions in the subsurface repository. This analysis refines the conceptual design that was started in Phase I of the Viability Assessment. This analysis supports the development of a reliable emplacement concept and a retrieval concept for license application design. The scope of this analysis includes the following activities: (1) Assess features of the transporter design and evaluate alternative design solutions for mechanical components. (2) Develop mechanical equipment details for the transporter. (3) Prepare a preliminary structural evaluation for the transporter. (4) Identify and recommend the equipment design for waste package transport and related functions. (5) Investigate transport equipment interface tolerances. This analysis supports the development of the waste package transporter for the transport, emplacement, and retrieval of packaged radioactive waste forms in the subsurface repository. Once the waste containers are closed and accepted, the packaged radioactive waste forms are termed waste packages (WP). This terminology was finalized as this analysis neared completion; therefore, the term disposal container is used in several references (i.e., the System Description Document (SDD)) (Ref. 5.6). In this analysis and the applicable reference documents, the term ''disposal container'' is synonymous with ''waste package''.

  15. User friendly packaging

    DEFF Research Database (Denmark)

    Geert Jensen, Birgitte

    2010-01-01

    Most consumers have experienced occasional problems with opening packaging. Tomato sauce from the tinned mackerel splattered all over the kitchen counter, the unrelenting pickle jar lid, and the package of sliced ham that cannot be opened without a knife or a pair of scissors. The research project...

  16. Grooming. Learning Activity Package.

    Science.gov (United States)

    Stark, Pamela

    This learning activity package on grooming for health workers is one of a series of 12 titles developed for use in health occupations education programs. Materials in the package include objectives, a list of materials needed, information sheets, reviews (self evaluations) of portions of the content, and answers to reviews. These topics are…

  17. Hybrid photonic chip interferometer for embedded metrology

    Science.gov (United States)

    Kumar, P.; Martin, H.; Maxwell, G.; Jiang, X.

    2014-03-01

    Embedded metrology is the provision of metrology on the manufacturing platform, enabling measurement without the removal of the work piece. Providing closer integration of metrology upon the manufacturing platform can lead to the better control and increased throughput. In this work we present the development of a high precision hybrid optical chip interferometer metrology device. The complete metrology sensor system is structured into two parts; optical chip and optical probe. The hybrid optical chip interferometer is based on a silica-on-silicon etched integrated-optic motherboard containing waveguide structures and evanescent couplers. Upon the motherboard, electro-optic components such as photodiodes and a semiconductor gain block are mounted and bonded to provide the required functionality. The key structure in the device is a tunable laser module based upon an external-cavity diode laser (ECDL). Within the cavity is a multi-layer thin film filter which is rotated to select the longitudinal mode at which the laser operates. An optical probe, which uses a blazed diffracting grating and collimating objective lens, focuses light of different wavelengths laterally over the measurand. Incident laser light is then tuned in wavelength time to effectively sweep an `optical stylus' over the surface. Wavelength scanning and rapid phase shifting can then retrieve the path length change and thus the surface height. We give an overview of the overall design of the final hybrid photonic chip interferometer, constituent components, device integration and packaging as well as experimental test results from the current version now under evaluation.

  18. Waste package performance analysis

    International Nuclear Information System (INIS)

    A performance assessment model for multiple barrier packages containing unreprocessed spent fuel has been applied to several package designs. The resulting preliminary assessments were intended for use in making decisions about package development programs. A computer model called BARIER estimates the package life and subsequent rate of release of selected nuclides. The model accounts for temperature, pressure (and resulting stresses), bulk and localized corrosion, and nuclide retardation by the backfill after water intrusion into the waste form. The assessment model assumes a post-closure, flooded, geologic repository. Calculations indicated that, within the bounds of model assumptions, packages could last for several hundred years. Intact backfills of appropriate design may be capable of nuclide release delay times on the order of 107 yr for uranium, plutonium, and americium. 8 references, 6 figures, 9 tables

  19. Determination of packaging induced 3D stress utilizing a piezocoefficient mapping device

    DEFF Research Database (Denmark)

    Richter, Jacob; Hyldgård, A.; Birkelund, Karen;

    2007-01-01

    This paper presents a novel method to determine 3D stress in microsystem packaging. The stress components sigmaxx, sigmayy, sigmazz, and sigmaxy are found in an epoxy package using a piezocoefficient mapping device as stress sensor. We spin the current 360deg in a circular n-type (001) Si...... same concept as in [1] used for chip packaging for fisheries research. We investigate the EpoTek 305 epoxy and find stress values of sigmaxx ap -23 MPa, sigmayy ap -1 MPa, sigmaxy = 0.3 MPa, and sigmazz = 40 MPa. The presented method can be used for 3D stress measurements of various packaging concepts....... piezoresistor by contacts located near the perimeter of the resistor and do high impedance voltage measurements on contacts located near the centre of the resistor. By measuring the potential drops in these contacts we can determine the stress in the chip. The epoxy is potted in a polystyrene tube using the...

  20. The use of oxygen indicators - elements of intelligent packaging for monitoring of food quality

    OpenAIRE

    Renata Dobrucka

    2014-01-01

    Background: Producers and researchers are looking at not only the methods of protection against ingress of oxygen into the package, but also want to provide consumers with guarantees of quality food they buy. Therefore, large-scale studies are conducted and implementation of intelligent packaging. The operation of these packages is the use of interactive, the most colorful indicators to assess the quality of the packaged product. Methods: This article describes intelligent packaging tech...

  1. Evaluation of thermal resistance constitution for packaged AlGaN/GaN high electron mobility transistors by structure function method

    Institute of Scientific and Technical Information of China (English)

    Zhang Guang-Chen; Feng Shi-Wei; Zhou Zhou; Li Jing-Wan; Guo Chun-Sheng

    2011-01-01

    The evaluation of thermal resistance constitution for packaged AlGaN/GaN high electron mobility transistor (HEMT) by structure function method is proposed in this paper. The evaluation is based on the transient heating measurement of the AlGaN/GaN HEMT by pulsed electrical temperature sensitive parameter method. The extracted chip-level and package-level thermal resistances of the packaged multi-finger AlGaN/GaN HEMT with 400-μn SiC substrate are 22.5 K/W and 7.2 K/W respectively, which provides a non-invasive method to evaluate the chip-level thermal resistance of packaged AlGaN/GaN HEMTs. It is also experimentally proved that the extraction of the chip-level thermal resistance by this proposed method is not influenced by package form of the tested device and temperature boundary condition of measurement stage.

  2. Development of Microreactor Array Chip-Based Measurement System for Massively Parallel Analysis of Enzymatic Activity

    Science.gov (United States)

    Hosoi, Yosuke; Akagi, Takanori; Ichiki, Takanori

    Microarray chip technology such as DNA chips, peptide chips and protein chips is one of the promising approaches for achieving high-throughput screening (HTS) of biomolecule function since it has great advantages in feasibility of automated information processing due to one-to-one indexing between array position and molecular function as well as massively parallel sample analysis as a benefit of down-sizing and large-scale integration. Mostly, however, the function that can be evaluated by such microarray chips is limited to affinity of target molecules. In this paper, we propose a new HTS system of enzymatic activity based on microreactor array chip technology. A prototype of the automated and massively parallel measurement system for fluorometric assay of enzymatic reactions was developed by the combination of microreactor array chips and a highly-sensitive fluorescence microscope. Design strategy of microreactor array chips and an optical measurement platform for the high-throughput enzyme assay are discussed.

  3. A Study on the Conductivity Variation of Au Coated Conductive Particles in ACF Packaging Process

    OpenAIRE

    Jao-Hwa Kuang; Chao-Ming Hsu; Ah-Der Lin

    2015-01-01

    In the ACF packaging process, a bonding force will be applied to the ACF structure. The finite element analysis is used to simulate the ACF packaging process. Material behavior is assumed to be superelastic for resin, viscoelastic for polymer matrix, and elastic-plastic for metal, such as bump, pad, chip, and Au-film. The axis-symmetric model is employed in FEA simulation with time-varying bonding force and operating temperature. In this study, the parameters, including conductive particle d...

  4. Chip Multithreaded Consistency Model

    Institute of Scientific and Technical Information of China (English)

    Zu-Song Li; Dan-Dan Huan; Wei-Wu Hu; Zhi-Min Tang

    2008-01-01

    Multithreaded technique is the developing trend of high performance processor. Memory consistency model is essential to the correctness, performance and complexity of multithreaded processor. The chip multithreaded consistency model adapting to multithreaded processor is proposed in this paper. The restriction imposed on memory event ordering by chip multithreaded consistency is presented and formalized. With the idea of critical cycle built by Wei-Wu Hu, we prove that the proposed chip multithreaded consistency model satisfies the criterion of correct execution of sequential consistency model. Chip multithreaded consistency model provides a way of achieving high performance compared with sequential consistency model and ensures the compatibility of software that the execution result in multithreaded processor is the same as the execution result in uniprocessor. The implementation strategy of chip multithreaded consistency model in Godson-2 SMT processor is also proposed. Godson-2 SMT processor supports chip multithreaded consistency model correctly by exception scheme based on the sequential memory access queue of each thread.

  5. Analysis of trade packages in Chinese stock market

    OpenAIRE

    Fei Ren; Wei-Xing Zhou

    2011-01-01

    This paper conducts an empirically study on the trade package composed of a sequence of consecutive purchases or sales of 23 stocks in Chinese stock market. We investigate the probability distributions of the execution time, the number of trades and the total trading volume of trade packages, and analyze the possible scaling relations between them. Quantitative differences are observed between the institutional and individual investors. The trading profile of trade packages is investigated to...

  6. Wood chips procurement and research project at the Mikkeli region

    International Nuclear Information System (INIS)

    In 1993-94, a large-scale energywood production chain started as a co-operation project by the Mikkeli city forest office and local forestry societies. In 1995 over 115 000 m3 (about 85 000 MWh of energy) of wood chips were delivered to Pursiala heat and power plant in Mikkeli. About 75 % of these chips was forest processed chips. About 70 % of the forest processed chips was whole tree chips from improvement cuttings of young forest stands and the rest was logging waste chips from regeneration cutting areas. The average total delivery costs of forest processed chips after reduction of energywood and other subsidies were approximately 45 FIM/m3 (60 FIM/MWh) for the whole tree chips and 38 FIM/m3 (50 FIM/MWh) for logging waste chips. The delivery costs of forest processed chips could meet the target of Bioenergy Research Programme (45 FIM/MWh) only in the most favourable cases. In an average the delivery costs were about 9 FIM/MWh more than the price obtained when sold to the heat and power plant. However the wood chip production created 27 new jobs and the increase of income to the local economy was about 2.2 milj. FIM /year. The local communities got new tax revenue about 3 FIM/MWh. The gain for the forestry was approximated to be 5 - 6 FIM/MWh. The resources of forest processed chips were studied on the basis of stand measurements. According to the study the most remarkable energywood resources were in young thinning stands on Oxalis-Myrtillus and Myrtillus forest site types. On Oxalis-Myrtillus type almost every and on Myrtillus type every second stand included energywood more than 40 m3/ha

  7. Safety Analysis Report - Packages, 9965, 9968, 9972-9975 Packages

    International Nuclear Information System (INIS)

    This Safety Analysis Report for Packaging (SARP) documents the analysis and testing performed on four type B Packages: the 9972, 9973, 9974, and 9975 packages. Because all four packages have similar designs with very similar performance characteristics, all of them are presented in a single SARP. The performance evaluation presented in this SARP documents the compliance of the 9975 package with the regulatory safety requirements. Evaluations of the 9972, 9973, and 9974 packages support that of the 9975. To avoid confusion arising from the inclusion of four packages in a single document, the text segregates the data for each package in such a way that the reader interested in only one package can progress from Chapter 1 through Chapter 9. The directory at the beginning of each chapter identifies each section that should be read for a given package. Sections marked ''all'' are generic to all packages

  8. Lunar Dust Analysis Package - LDAP

    Science.gov (United States)

    Chalkley, S. A.; Richter, L.; Goepel, M.; Sovago, M.; Pike, W. T.; Yang, S.; Rodenburg, J.; Claus, D.

    2012-09-01

    The Lunar Dust Analysis package (L-DAP) is a suite of payloads which have been designed to operate in synergy with each other at the Lunar Surface. The benefits of combining these payloads in a single package allow very precise measurements of a particular regolith sample. At the same time the integration allows mass savings since common resources are shared and this also means that interfaces with the Lander are simplified significantly leading to benefits of integration and development of the overall mission. Lunar Dust represents a real hazard for lunar exploration due to its invasive, fine microscopic structure and toxic properties. However it is also valuable resource which could be exploited for future exploration if the characteristics and chemical composition is well known. Scientifically, the regolith provides an insight into the moon formation process and there are areas on the Moon which have never been ex-plored before. For example the Lunar South Pole Aitken Basin is the oldest and largest on the moon, providing excavated deep crust which has not been found on the previous lunar landing missions. The SEA-led team has been designing a compact package, known as LDAP, which will provide key data on the lunar dust properties. The intention is for this package to be part of the payload suite deployed on the ESA Lunar Lander Mission in 2018. The LDAP has a centralised power and data electronics, including front end electronics for the detectors as well as sample handling subsystem for the following set of internal instruments : • Optical Microscope - with a 1μm resolution to provide context of the regolith samples • Raman and LIBS spectrographic instrumentation providing quantification of mineral and elemental composition information of the soil at close to grain scale. This includes the capability to detect (and measure abundance of) crystalline and adsorbed volatile phases, from their Raman signature. The LIBS equipment will also allow chemical

  9. Hermeticity of electronic packages

    CERN Document Server

    Greenhouse, Hal; Romenesco, Bruce

    2011-01-01

    This is a book about the integrity of sealed packages to resist foreign gases and liquids penetrating the seal or an opening (crack) in the packageùespecially critical to the reliability and longevity of electronics. The author explains how to predict the reliability and the longevity of the packages based on leak rate measurements and the assumptions of impurities. Non-specialists in particular will benefit from the author's long involvement in the technology. Hermeticity is a subject that demands practical experience, and solving one problem does not necessarily give one the background to so

  10. Hermeticity of electronic packages

    CERN Document Server

    Greenhouse, Hal

    2000-01-01

    This is a book about the integrity of sealed packages to resist foreign gases and liquids penetrating the seal or an opening (crack) in the package-especially critical to the reliability and longevity of electronics. The author explains how to predict the reliability and the longevity of the packages based on leak rate measurements and the assumptions of impurities. Non-specialists in particular will benefit from the author's long involvement in the technology. Hermeticity is a subject that demands practical experience, and solving one problem does not necessarily give one the background to so

  11. Chip-size-packaged silicon microphones [for hearing instruments

    DEFF Research Database (Denmark)

    Müllenborn, Matthias; Rombach, Pirmin; Klein, Udo;

    2001-01-01

    bonding. The devices are fully encapsulated and provided with a well-determined interface to the environment. The integrated microphones operate at a bias of 1.5 V and are expected to reach a sensitivity of 5 mV/Pa, an A-weighted equivalent input noise of 24 dB sound pressure level, and a power...

  12. In-situ volumetric topography of IC chips for defect detection using infrared confocal measurement with active structured light

    Science.gov (United States)

    Chen, Liang-Chia; Le, Manh-Trung; Cong Phuc, Dao; Lin, Shyh-Tsong

    2014-09-01

    The article presents the development of in-situ integrated circuit (IC) chip defect detection techniques for automated clipping detection by proposing infrared imaging and full-field volumetric topography. IC chip inspection, especially held during or post IC packaging, has become an extremely critical procedure in IC fabrication to assure manufacturing quality and reduce production costs. To address this, in the article, microscopic infrared imaging using an electromagnetic light spectrum that ranges from 0.9 to 1.7 µm is developed to perform volumetric inspection of IC chips, in order to identify important defects such as silicon clipping, cracking or peeling. The main difficulty of infrared (IR) volumetric imaging lies in its poor image contrast, which makes it incapable of achieving reliable inspection, as infrared imaging is sensitive to temperature difference but insensitive to geometric variance of materials, resulting in difficulty detecting and quantifying defects precisely. To overcome this, 3D volumetric topography based on 3D infrared confocal measurement with active structured light, as well as light refractive matching principles, is developed to detect defects the size, shape and position of defects in ICs. The experimental results show that the algorithm is effective and suitable for in-situ defect detection of IC semiconductor packaging. The quality of defect detection, such as measurement repeatability and accuracy, is addressed. Confirmed by the experimental results, the depth measurement resolution can reach up to 0.3 µm, and the depth measurement uncertainty with one standard deviation was verified to be less than 1.0% of the full-scale depth-measuring range.

  13. Design and characterization of an image acquisition system and its optomechanical module for chip defects inspection on chip sorters

    Science.gov (United States)

    Chen, Ming-Fu; Huang, Po-Hsuan; Chen, Yung-Hsiang; Cheng, Yu-Cheng

    2011-08-01

    Chip sorter is one of packaging facilities in chip manufactory. Defects will occur for a few of chips during manufacturing processes. If the size of chip defects is larger than a criterion of impacting chip quality, these flawed chips have to be detected and removed. Defects inspection system is usually developed with frame CCD imagers. There're some drawbacks for this system, such as mechanism of pause type for image acquisition, complicated acquisition control, easy damage for moving components, etc. And acquired images per chip have to be processed in radiometry and geometry and then pieced together before inspection. These processes impact the accuracy and efficiency of defects inspection. So approaches of image acquisition system and its opto-mechanical module will be critical for inspection system. In this article, design and characterization of a new image acquisition system and its opto-mechanical module are presented. Defects with size of greater than 15μm have to be inspected. Inspection performance shall be greater than 0.6 m/sec. Thus image acquisition system shall have the characteristics of having (1) the resolution of 5μm and 10μm for optical lens and linear CCD imager respectively; (2) the lens magnification of 2; (3) the line rate of greater than 120 kHz for imager output. The design of structure and outlines for new system and module are also described in this work. Proposed system has advantages of such as transporting chips in constant speed to acquire images, using one image only per chip for inspection, no image-mosaic process, simplifying the control of image acquisition. And the inspection efficiency and accuracy will be substantially improved.

  14. London 2012 packaging guidelines

    OpenAIRE

    2013-01-01

    These guidelines are intended to provide supplemental advice to suppliers and licensees regarding the provisions of the LOCOG Sustainable Sourcing Code that relate to packaging design and materials selection.

  15. Dual Use Packaging Project

    Data.gov (United States)

    National Aeronautics and Space Administration — NASA calculation that over a kg of packaging waste are generated per day for a 6 member crew. This represents over 1.5 metric tons of waste during a Mars mission....

  16. FLEXIBLE FOOD PACKAGING LABORATORY

    Data.gov (United States)

    Federal Laboratory Consortium — This laboratory contains equipment to fabricate and test prototype packages of many types and sizes (e.g., bags, pouches, trays, cartons, etc.). This equipment can...

  17. Smart-pixel-based free-space interconnects: solving the high-speed multichip packaging bottleneck

    Science.gov (United States)

    Haney, Michael W.; Christensen, Marc P.; Milojkovic, Predrag; McFadden, Michael J.

    2001-11-01

    As IC densities grow to 100's of millions of devices per chip and beyond, the inter-chip link bandwidth becomes a critical performance-limiting bottleneck in many applications. Electronic packaging technology has not kept pace with the growth of IC I/O requirements. Recent advances in smart pixel technology, however, offer the potential to use 3-D optical interconnects to overcome the inter-chip I/O bottleneck by linking dense arrays of Vertical Cavity Surface Emitting Lasers (VCSELs) and photodetectors, which are directly integrated onto electronic IC circuits. Many switching and parallel computing applications demand multi-chip interconnection fabrics that achieve high-density global I/O across an array of chips. Such global interconnections require a high degree of space-variance in the interconnection fabric, in addition to high inter-chip throughput capacity. This paper reviews the architectural and optical design issues associated with global interconnections among arrays of chips. The emphasis is on progress made in the design and implementation of the second generation Free-space Accelerator for Switching Terabit Networks (FAST-Net) prototype. The FAST-Net prototype uses a macro-optical lens array and mirror to effect a global (fully connected) fabric across a 4 X 4 array of smart pixel chips. Clusters of VCSELs and photodetectors are imaged onto corresponding clusters on other chips, creating a high- density bi-directional data path between every pair of smart pixel chips on a multi-chip module. The combination of programmable intra-chip electronic routing and the fixed global inter-chip optical interconnection pattern of the FAST- Net architecture has been shown to provide a low latency, minimum complexity fabric, that can effect an arbitrary interconnection pattern across the chip array. Recent experimental results show that the narrow beam characteristics of VCSELs can be exploited in an efficient optical design for the FAST-Net optical interconnection

  18. CH Packaging Program Guidance

    International Nuclear Information System (INIS)

    The purpose of this document is to provide the technical requirements for preparation for use, operation, inspection, and maintenance of a Transuranic Package Transporter Model II (TRUPACT-II), a HalfPACT Shipping Package, and directly related components. This document complies with the minimum requirements as specified in TRUPACT-II Safety Analysis Report for Packaging (SARP), HalfPACT SARP, and Nuclear Regulatory Commission (NRC) Certificates of Compliance (C of C) 9218 and 9279, respectively. In the event there is a conflict between this document and the SARP or C of C, the SARP and/or C of C shall govern. C of Cs state: ''each package must be prepared for shipment and operated in accordance with the procedures described in Chapter 7.0, Operating Procedures, of the application.'' They further state: ''each package must be tested and maintained in accordance with the procedures described in Chapter 8.0, Acceptance Tests and Maintenance Program of the Application.'' Chapter 9.0 of the SAR P charges the WIPP Management and Operation (M and O) contractor with assuring packaging is used in accordance with the requirements of the C of C. Because the packaging is NRC-approved, users need to be familiar with 10 CFR 71.11. Any time a user suspects or has indications that the conditions of approval in the C of C were not met, the Carlsbad Field Office (CBFO) shall be notified immediately. CBFO will evaluate the issue and notify the NRC if required. This document details the instructions to be followed to operate, maintain, and test the TRUPACT-II and HalfPACT packaging. The intent of these instructions is to standardize these operations. All users will follow these instructions or equivalent instructions that assure operations are safe and meet the requirements of the SARPs

  19. CH Packaging Program Guidance

    International Nuclear Information System (INIS)

    The purpose of this document is to provide the technical requirements for preparation for use, operation, inspection, and maintenance of a Transuranic Package Transporter Model II (TRUPACT-II), a HalfPACT shipping package, and directly related components. This document complies with the minimum requirements as specified in the TRUPACT-II Safety Analysis Report for Packaging (SARP), HalfPACT SARP, and Nuclear Regulatory Commission (NRC) Certificates of Compliance (C of C) 9218 and 9279, respectively. In the event of a conflict between this document and the SARP or C of C, the C of C shall govern. The C of Cs state: ''each package must be prepared for shipment and operated in accordance with the procedures described in Chapter 7.0, Operating Procedures, of the application.'' They further state: ''each package must be tested and maintained in accordance with the procedures described in Chapter 8.0, Acceptance Tests and Maintenance Program of the Application.'' Chapter 9.0 of the SARP charges the WIPP management and operating (M and O) contractor with assuring packaging is used in accordance with the requirements of the C of C. Because the packaging is NRC-approved, users need to be familiar with 10 CFR 71.11. Any time a user suspects or has indications that the conditions of approval in the C of C were not met, the Carlsbad Field Office (CBFO) shall be notified immediately. CBFO will evaluate the issue and notify the NRC if required. This document provides the instructions to be followed to operate, maintain, and test the TRUPACT-II and HalfPACT packaging. The intent of these instructions is to standardize operations. All users will follow these instructions or equivalent instructions that assure operations are safe and meet the requirements of the SARPs

  20. Lush Cosmetics packaging

    OpenAIRE

    Hudson, Frazer

    2014-01-01

    Frazer Hudson – Lush Cosmetics Packaging Commissioned by Suzie Hackney for Lush Cosmetics via illustration Agency - Debut Art - February 2014 I was approached in February 2014 via my London based Illustration agency Debut Art to create packaging illustration designs for the high street retailer and International cosmetics brand ‘Lush’. The illustrations would be used on an octagonal gift box set and be positioned amongst other bespoke gift box set designs within Lush Cosme...

  1. Packaging sustainability assessment

    OpenAIRE

    Rubio Peregrina, Silvia

    2015-01-01

    Packaging is an essential part of the majority of products in the actual market. Therefore, packaging design must draw attention to improve its sustainable character in order to satisfy consumers, enhance its environmental performance and keep economic costs to a minimum. Measuring packaging’s sustainability would provide consumers information so as to raise awareness and, moreover, a tool that would help companies to find product weaknesses to be improved. For that purpose, this projec...

  2. The ENSDF Java Package

    International Nuclear Information System (INIS)

    A package of computer codes has been developed to process and display nuclear structure and decay data stored in the ENSDF (Evaluated Nuclear Structure Data File) library. The codes were written in an object-oriented fashion using the java language. This allows for an easy implementation across multiple platforms as well as deployment on web pages. The structure of the different java classes that make up the package is discussed as well as several different implementations

  3. Wafer-level vacuum/hermetic packaging technologies for MEMS

    Science.gov (United States)

    Lee, Sang-Hyun; Mitchell, Jay; Welch, Warren; Lee, Sangwoo; Najafi, Khalil

    2010-02-01

    An overview of wafer-level packaging technologies developed at the University of Michigan is presented. Two sets of packaging technologies are discussed: (i) a low temperature wafer-level packaging processes for vacuum/hermeticity sealing, and (ii) an environmentally resistant packaging (ERP) technology for thermal and mechanical control as well as vacuum packaging. The low temperature wafer-level encapsulation processes are implemented using solder bond rings which are first patterned on a cap wafer and then mated with a device wafer in order to encircle and encapsulate the device at temperatures ranging from 200 to 390 °C. Vacuum levels below 10 mTorr were achieved with yields in an optimized process of better than 90%. Pressures were monitored for more than 4 years yielding important information on reliability and process control. The ERP adopts an environment isolation platform in the packaging substrate. The isolation platform is designed to provide low power oven-control, vibration isolation and shock protection. It involves batch flip-chip assembly of a MEMS device onto the isolation platform wafer. The MEMS device and isolation structure are encapsulated at the wafer-level by another substrate with vertical feedthroughs for vacuum/hermetic sealing and electrical signal connections. This technology was developed for high performance gyroscopes, but can be applied to any type of MEMS device.

  4. Causes of stem end chip defect in chipping potatoes

    Science.gov (United States)

    Stem-end chip defect (SECD) is a serious tuber quality concern that affects chipping potatoes. This defect is characterized by dark-colored vascular tissues and adjacent cortical tissues at the tuber stem-end of potato chips after frying. Chips with SECD are unappealing to consumers and raw product ...

  5. A contact-lens-shaped IC chip technology

    International Nuclear Information System (INIS)

    We report on novel contact-lens-shaped silicon integrated circuit chip technology for applications such as forming a conforming retinal prosthesis. This is achieved by means of patterning thin films of high residual stress on top of a shaped thin silicon substrate. Several strategies are employed to achieve curvatures of various amounts. Firstly, high residual stress on a thin film makes a thin chip deform into a designed three-dimensional shape. Also, a series of patterned stress films and ‘petal-shaped’ chips were fabricated and analyzed. Large curvatures can also be formed and maintained by the packaging process of bonding the chips to constraining elements such as thin-film polymer ring structures. As a demonstration, a complementary metal oxide semiconductor transistor (CMOS) image-sensing retina chip is made into a contact-lens shape conforming to a human eyeball 12.5 mm in radius. This non-planar and flexible chip technology provides a desirable device surface interface to soft tissues or non-planar bio surfaces and opens up many other possibilities for biomedical applications. (paper)

  6. Single-serve ice cream packaging: packaging structures enhancing brand

    OpenAIRE

    Salo, August

    2014-01-01

    The thesis focuses on packaging structures and branding; discussing the role packaging plays in brand identity. In today’s crowded marketplaces brands must fight to differentiate themselves from the competition by offering unique product experiences. As most products are packaged in one way or another, packaging has become a valuable element in brand communication and marketing. Packaging is seen as a part of the product experience, adding value and personality to otherwise similar products. ...

  7. ALICE chip processor

    CERN Multimedia

    Maximilien Brice

    2003-01-01

    This tiny chip provides data processing for the time projection chamber on ALICE. Known as the ALICE TPC Read Out (ALTRO), this device was designed to minimize the size and power consumption of the TPC front end electronics. This single chip contains 16 low-power analogue-to-digital converters with six million transistors of digital processing and 8 kbits of data storage.

  8. Progress in Atom Chips and the Integration of Optical Microcavities

    Science.gov (United States)

    Hinds, E. A.; Trupke, M.; Darquie, B.; Goldwin, J.; Dutier, G.

    2008-04-01

    We review recent progress at the Centre for Cold Matter in developing atom chips. An important advantage of miniaturizing atom traps on a chip is the possibility of obtaining very tight trapping structures with the capability of manipulating atoms on the micron length scale. We recall some of the pros and cons of bringing atoms close to the chip surface, as is required in order to make small static structures, and we discuss the relative merits of metallic, dielectric and superconducting chip surfaces. We point out that the addition of integrated optical devices on the chip can enhance its capability through single atom detection and controlled photon production. Finally, we review the status of integrated microcavities that have recently been demonstrated at our Centre and discuss their prospects for future development.

  9. CH Packaging Program Guidance

    International Nuclear Information System (INIS)

    The purpose of this document is to provide the technical requirements for preparation for use, operation, inspection, and maintenance of a Transuranic Package Transporter Model II (TRUPACT-II), a HalfPACT shipping package, and directly related components. This document complies with the minimum requirements as specified in the TRUPACT-II Safety Analysis Report for Packaging (SARP), HalfPACT SARP, and U.S. Nuclear Regulatory Commission (NRC) Certificates of Compliance (C of C) 9218 and 9279, respectively. In the event of a conflict between this document and the SARP or C of C, the C of C shall govern. The C of Cs state: 'each package must be prepared for shipment and operated in accordance with the procedures described in Chapter 7.0, Operating Procedures, of the application.' They further state: 'each package must be tested and maintained in accordance with the procedures described in Chapter 8.0, Acceptance Tests and Maintenance Program of the Application.' Chapter 9.0 of the SARP charges the U.S. Department of Energy (DOE) or the Waste Isolation Pilot Plant (WIPP) management and operating (M and O) contractor with assuring packaging is used in accordance with the requirements of the C of C. Because the packaging is NRC-approved, users need to be familiar with Title 10 Code of Federal Regulations (CFR) 71.8. Any time a user suspects or has indications that the conditions of approval in the C of C were not met, the Carlsbad Field Office (CBFO) shall be notified immediately. The CBFO will evaluate the issue and notify the NRC if required. In accordance with 10 CFR Part 71, certificate holders, packaging users, and contractors or subcontractors who use, design, fabricate, test, maintain, or modify the packaging shall post copies of (1) 10 CFR Part 21 regulations, (2) Section 206 of the Energy Reorganization Act of 1974, and (3) NRC Form 3, Notice to Employees. These documents must be posted in a conspicuous location where the activities subject to these regulations

  10. RH Packaging Program Guidance

    Energy Technology Data Exchange (ETDEWEB)

    Washington TRU Solutions LLC

    2006-11-07

    The purpose of this program guidance document is to provide the technical requirements for use, operation, inspection, and maintenance of the RH-TRU 72-B Waste Shipping Package and directly related components. This document complies with the requirements as specified in the RH-TRU 72-B Safety Analysis Report for Packaging (SARP), and Nuclear Regulatory Commission (NRC) Certificate of Compliance (C of C) 9212. If there is a conflict between this document and the SARP and/or C of C, the C of C shall govern. The C of C states: "...each package must be prepared for shipment and operated in accordance with the procedures described in Chapter 7.0, Operating Procedures, of the application." It further states: "...each package must be tested and maintained in accordance with the procedures described in Chapter 8.0, Acceptance Tests and Maintenance Program of the Application." Chapter 9.0 of the SARP tasks the Waste Isolation Pilot Plant (WIPP) Management and Operating (M&O) Contractor with assuring the packaging is used in accordance with the requirements of the C of C. Because the packaging is NRC-approved, users need to be familiar with 10 Code of Federal Regulations (CFR) §71.8, "Deliberate Misconduct." Any time a user suspects or has indications that the conditions of approval in the C of C were not met, the U.S. Department of Energy (DOE) Carlsbad Field Office (CBFO) shall be notified immediately. CBFO will evaluate the issue and notify the NRC if required. In accordance with 10 CFR Part 71, "Packaging and Transportation of Radioactive Material," certificate holders, packaging users, and contractors or subcontractors who use, design, fabricate, test, maintain, or modify the packaging shall post copies of (1) 10 CFR Part 21, "Reporting of Defects and Noncompliance," regulations, (2) Section 206 of the Energy Reorganization Act of 1974, and (3) NRC Form 3, Notice to Employees. These documents must be posted in a conspicuous location where the activities subject to

  11. RH Packaging Program Guidance

    Energy Technology Data Exchange (ETDEWEB)

    Washington TRU Solutions LLC

    2008-01-12

    The purpose of this program guidance document is to provide the technical requirements for use, operation, inspection, and maintenance of the RH-TRU 72-B Waste Shipping Package (also known as the "RH-TRU 72-B cask") and directly related components. This document complies with the requirements as specified in the RH-TRU 72-B Safety Analysis Report for Packaging (SARP), and Nuclear Regulatory Commission (NRC) Certificate of Compliance (C of C) 9212. If there is a conflict between this document and the SARP and/or C of C, the C of C shall govern. The C of C states: "...each package must be prepared for shipment and operated in accordance with the procedures described in Chapter 7.0, Operating Procedures, of the application." It further states: "...each package must be tested and maintained in accordance with the procedures described in Chapter 8.0, Acceptance Tests and Maintenance Program of the Application." Chapter 9.0 of the SARP tasks the Waste Isolation Pilot Plant (WIPP) Management and Operating (M&O) Contractor with assuring the packaging is used in accordance with the requirements of the C of C. Because the packaging is NRC-approved, users need to be familiar with Title 10 Code of Federal Regulations (CFR) §71.8, "Deliberate Misconduct." Any time a user suspects or has indications that the conditions of approval in the C of C were not met, the U.S. Department of Energy (DOE) Carlsbad Field Office (CBFO) shall be notified immediately. The CBFO will evaluate the issue and notify the NRC if required.In accordance with 10 CFR Part 71, "Packaging and Transportation of Radioactive Material," certificate holders, packaging users, and contractors or subcontractors who use, design, fabricate, test, maintain, or modify the packaging shall post copies of (1) 10 CFR Part 21, "Reporting of Defects and Noncompliance," regulations, (2) Section 206 of the Energy Reorganization Act of 1974, and (3) NRC Form 3, Notice to Employees. These documents must be posted in a

  12. CH Packaging Program Guidance

    Energy Technology Data Exchange (ETDEWEB)

    None, None

    2008-09-11

    The purpose of this document is to provide the technical requirements for preparation for use, operation, inspection, and maintenance of a Transuranic Package Transporter Model II (TRUPACT-II), a HalfPACT shipping package, and directly related components. This document complies with the minimum requirements as specified in the TRUPACT-II Safety Analysis Report for Packaging (SARP), HalfPACT SARP, and U.S. Nuclear Regulatory Commission (NRC) Certificates of Compliance (C of C) 9218 and 9279, respectively. In the event of a conflict between this document and the SARP or C of C, the C of C shall govern. The C of Cs state: "each package must be prepared for shipment and operated in accordance with the procedures described in Chapter 7.0, Operating Procedures, of the pplication." They further state: "each package must be tested and maintained in accordance with the procedures described in Chapter 8.0, Acceptance Tests and Maintenance Program of the Application." Chapter 9.0 of the SARP charges the U.S. Department of Energy (DOE) or the Waste Isolation Pilot Plant (WIPP) management and operating (M&O) contractor with assuring packaging is used in accordance with the requirements of the C of C. Because the packaging is NRC-approved, users need to be familiar with Title 10 Code of Federal Regulations (CFR) §71.8. Any time a user suspects or has indications that the conditions of approval in the C of C were not met, the Carlsbad Field Office (CBFO) shall be notified immediately. The CBFO will evaluate the issue and notify the NRC if required. In accordance with 10 CFR Part 71, certificate holders, packaging users, and contractors or subcontractors who use, design, fabricate, test, maintain, or modify the packaging shall post copies of (1) 10 CFR Part 21 regulations, (2) Section 206 of the Energy Reorganization Act of 1974, and (3) NRC Form 3, Notice to Employees. These documents must be posted in a conspicuous location where the activities subject to these regulations are

  13. CH Packaging Program Guidance

    Energy Technology Data Exchange (ETDEWEB)

    None, None

    2009-06-01

    The purpose of this document is to provide the technical requirements for preparation for use, operation, inspection, and maintenance of a Transuranic Package Transporter Model II (TRUPACT-II), a HalfPACT shipping package, and directly related components. This document complies with the minimum requirements as specified in the TRUPACT-II Safety Analysis Report for Packaging (SARP), HalfPACT SARP, and U.S. Nuclear Regulatory Commission (NRC) Certificates of Compliance (C of C) 9218 and 9279, respectively. In the event of a conflict between this document and the SARP or C of C, the C of C shall govern. The C of Cs state: "each package must be prepared for shipment and operated in accordance with the procedures described in Chapter 7.0, Operating Procedures, of the application." They further state: "each package must be tested and maintained in accordance with the procedures described in Chapter 8.0, Acceptance Tests and Maintenance Program of the Application." Chapter 9.0 of the SARP charges the U.S. Department of Energy (DOE) or the Waste Isolation Pilot Plant (WIPP) management and operating (M&O) contractor with assuring packaging is used in accordance with the requirements of the C of C. Because the packaging is NRC-approved, users need to be familiar with Title 10 Code of Federal Regulations (CFR) §71.8. Any time a user suspects or has indications that the conditions of approval in the C of C were not met, the Carlsbad Field Office (CBFO) shall be notified immediately. The CBFO will evaluate the issue and notify the NRC if required. In accordance with 10 CFR Part 71, certificate holders, packaging users, and contractors or subcontractors who use, design, fabricate, test, maintain, or modify the packaging shall post copies of (1) 10 CFR Part 21 regulations, (2) Section 206 of the Energy Reorganization Act of 1974, and (3) NRC Form 3, Notice to Employees. These documents must be posted in a conspicuous location where the activities subject to these regulations are

  14. CHIP, CHIP, ARRAY! THREE CHIPS FOR POST-GENOMIC RESEARCH

    Science.gov (United States)

    Cambridge Healthtech Institute recently held the 4th installment of their popular "Lab-on-a-Chip" series in Zurich, Switzerland. As usual, it was enthusiastically received and over 225 people attended the 2-1/2 day meeting to see and hear about some of the latest developments an...

  15. A survey of research and practices of network-on-chip

    DEFF Research Database (Denmark)

    Bjerregaard, Tobias; Mahadevan, Shankar

    2006-01-01

    The scaling of microchip technologies has enabled large scale systems-on-chip (SoC). Network-on-chip (NoC) research addresses global communication in SoC, involving (i) a move from computation-centric to communication-centric design and (ii) the implementation of scalable communication structures...

  16. CHIPS Neutrino Detector Research and Development

    Science.gov (United States)

    Salazar, Ramon; Vahle, Patricia; Chips Collaboration

    2015-04-01

    The CHIPS R&D project is an effort to develop affordable megaton-scale neutrino detectors. The CHIPS strategy calls for submerging water Cherenkov detectors deep under water. The surrounding water acts as structural support, minimizing large initial investments in costly infrastructure, and serves as an overburden, shielding the detector from cosmic rays and eliminating the need for expensive underground construction. Additional cost savings will be achieved through photodetector development and optimization of readout geometry. In summer 2014 a small prototype of the CHIPS detector was deployed in the flooded Wentworth Mine Pit in Northern Minnesota. The detector has been recording data underwater throughout the fall and winter. In this talk, we will discuss lessons learned from the prototyping experience and the plans for submerging much larger detectors in future years.

  17. Food packages for Space Shuttle

    Science.gov (United States)

    Fohey, M. F.; Sauer, R. L.; Westover, J. B.; Rockafeller, E. F.

    1978-01-01

    The paper reviews food packaging techniques used in space flight missions and describes the system developed for the Space Shuttle. Attention is directed to bite-size food cubes used in Gemini, Gemini rehydratable food packages, Apollo spoon-bowl rehydratable packages, thermostabilized flex pouch for Apollo, tear-top commercial food cans used in Skylab, polyethylene beverage containers, Skylab rehydratable food package, Space Shuttle food package configuration, duck-bill septum rehydration device, and a drinking/dispensing nozzle for Space Shuttle liquids. Constraints and testing of packaging is considered, a comparison of food package materials is presented, and typical Shuttle foods and beverages are listed.

  18. Food Packaging Materials

    Science.gov (United States)

    1978-01-01

    The photos show a few of the food products packaged in Alure, a metallized plastic material developed and manufactured by St. Regis Paper Company's Flexible Packaging Division, Dallas, Texas. The material incorporates a metallized film originally developed for space applications. Among the suppliers of the film to St. Regis is King-Seeley Thermos Company, Winchester, Ma'ssachusetts. Initially used by NASA as a signal-bouncing reflective coating for the Echo 1 communications satellite, the film was developed by a company later absorbed by King-Seeley. The metallized film was also used as insulating material for components of a number of other spacecraft. St. Regis developed Alure to meet a multiple packaging material need: good eye appeal, product protection for long periods and the ability to be used successfully on a wide variety of food packaging equipment. When the cost of aluminum foil skyrocketed, packagers sought substitute metallized materials but experiments with a number of them uncovered problems; some were too expensive, some did not adequately protect the product, some were difficult for the machinery to handle. Alure offers a solution. St. Regis created Alure by sandwiching the metallized film between layers of plastics. The resulting laminated metallized material has the superior eye appeal of foil but is less expensive and more easily machined. Alure effectively blocks out light, moisture and oxygen and therefore gives the packaged food long shelf life. A major packaging firm conducted its own tests of the material and confirmed the advantages of machinability and shelf life, adding that it runs faster on machines than materials used in the past and it decreases product waste; the net effect is increased productivity.

  19. CH Packaging Program Guidance

    International Nuclear Information System (INIS)

    The purpose of this document is to provide the technical requirements for preparation for use, operation, inspection, and maintenance of a Transuranic Package Transporter Model II (TRUPACT-II), a HalfPACT shipping package, and directly related components. This document complies with the minimum requirements as specified in the TRUPACT-II Safety Analysis Report for Packaging (SARP), HalfPACT SARP, and U.S. Nuclear Regulatory Commission (NRC) Certificates of Compliance (C of C) 9218 and 9279, respectively. In the event of a conflict between this document and the SARP or C of C, the C of C shall govern. The C of Cs state: ''each package must be prepared for shipment and operated in accordance with the procedures described in Chapter 7.0, Operating Procedures, of the application.'' They further state: ''each package must be tested and maintained in accordance with the procedures described in Chapter 8.0, Acceptance Tests and Maintenance Program of the Application.'' Chapter 9.0 of the SARP charges the Waste Isolation Pilot Plant (WIPP) management and operating (M and O) contractor with assuring packaging is used in accordance with the requirements of the C of C. Because the packaging is NRC-approved, users need to be familiar with Title 10 Code of Federal Regulations (CFR) 71.8. Any time a user suspects or has indications that the conditions of approval in the C of C were not met, the Carlsbad Field Office (CBFO) shall be notified immediately. The CBFO will evaluate the issue and notify the NRC if required.

  20. 78 FR 13083 - Products Having Laminated Packaging, Laminated Packaging, and Components Thereof; Notice of...

    Science.gov (United States)

    2013-02-26

    ... COMMISSION Products Having Laminated Packaging, Laminated Packaging, and Components Thereof; Notice of... Commission has received a complaint entitled Products Having Laminated ] Packaging, Laminated Packaging, and... having laminated packaging, laminated packaging, and components thereof. The complaint names...

  1. CH Packaging Program Guidance

    International Nuclear Information System (INIS)

    The purpose of this document is to provide the technical requirements for preparation for use, operation, inspection, and maintenance of a Transuranic Package Transporter Model II (TRUPACT-II), a HalfPACT shipping package, and directly related components. This document complies with the minimum requirements as specified in the TRUPACT-II Safety Analysis Report for Packaging (SARP), HalfPACT SARP, and U.S. Nuclear Regulatory Commission (NRC) Certificates of Compliance (C of C) 9218 and 9279, respectively. In the event of a conflict between this document and the SARP or C of C, the C of C shall govern. The C of Cs state: 'each package must be prepared for shipment and operated in accordance with the procedures described in Chapter 7.0, Operating Procedures, of the application.' They further state: 'each package must be tested and maintained in accordance with the procedures described in Chapter 8.0, Acceptance Tests and Maintenance Program of the Application.' Chapter 9.0 of the SARP charges the U.S. Department of Energy (DOE) or the Waste Isolation Pilot Plant| (WIPP) management and operating (M and O) contractor with assuring packaging is used in accordance with the requirements of the C of C. Because the packaging is NRC-approved, users need to be familiar with Title 10 Code of Federal Regulations(CFR) 71.8. Any time a user suspects or has indications that the conditions of approval in the C of C were not met, the Carlsbad Field Office (CBFO) shall be notified immediately. The CBFO will evaluate the issue and notify the NRC if required.In accordance with 10 CFR Part 71, certificate holders, packaging users, and contractors or subcontractors who use, design, fabricate, test, maintain, or modify the packaging shall post copies of (1) 10 CFR Part 21 regulations, (2) Section 206 of the Energy Reorganization Act of 1974, and (3) NRC Form 3, Notice to Employees. These documents must be posted in a conspicuous location where the activities subject to these regulations

  2. CH Packaging Program Guidance

    International Nuclear Information System (INIS)

    The purpose of this document is to provide the technical requirements for preparation for use, operation, inspection, and maintenance of a Transuranic Package Transporter Model II (TRUPACT-II), a HalfPACT shipping package, and directly related components. This document complies with the minimum requirements as specified in the TRUPACT-II Safety Analysis Report for Packaging (SARP), HalfPACT SARP, and U.S. Nuclear Regulatory Commission (NRC) Certificates of Compliance (C of C) 9218 and 9279, respectively. In the event of a conflict between this document and the SARP or C of C, the C of C shall govern. The C of Cs state: 'each package must be prepared for shipment and operated in accordance with the procedures described in Chapter 7.0, Operating Procedures, of the application.' They further state: 'each package must be tested and maintained in accordance with the procedures described in Chapter 8.0, Acceptance Tests and Maintenance Program of the Application.' Chapter 9.0 of the SARP charges the U.S. Department of Energy (DOE) or the Waste Isolation Pilot Plant (WIPP) management and operating (M and O) contractor with assuring packaging is used in accordance with the requirements of the C of C. Because the packaging is NRC-approved, users need to be familiar with Title 10 Code of Federal Regulations (CFR) 71.8. Any time a user suspects or has indications that the conditions of approval in the C of C were not met, the Carlsbad Field Office (CBFO) shall be notified immediately. The CBFO will evaluate the issue and notify the NRC if required.In accordance with 10 CFR Part 71, certificate holders, packaging users, and contractors or subcontractors who use, design, fabricate, test, maintain, or modify the packaging shall post copies of (1) 10 CFR Part 21 regulations, (2) Section 206 of the Energy Reorganization Act of 1974, and (3) NRC Form 3, Notice to Employees. These documents must be posted in a conspicuous location where the activities subject to these regulations

  3. CH Packaging Program Guidance

    Energy Technology Data Exchange (ETDEWEB)

    None, None

    2006-04-25

    The purpose of this document is to provide the technical requirements for preparation for use, operation, inspection, and maintenance of a Transuranic Package TransporterModel II (TRUPACT-II), a HalfPACT shipping package, and directly related components. This document complies with the minimum requirements as specified in the TRUPACT-II Safety Analysis Report for Packaging (SARP), HalfPACT SARP, and U.S. Nuclear Regulatory Commission (NRC) Certificates of Compliance (C of C) 9218 and 9279, respectively. In the event of a conflict between this document and the SARP or C of C, the C of C shall govern. The C of Cs state: "each package must be prepared for shipment and operated in accordance with the procedures described in Chapter 7.0, Operating Procedures, of the application." They further state: "each package must be tested and maintained in accordance with the procedures described in Chapter 8.0, Acceptance Tests and Maintenance Program of the Application." Chapter 9.0 of the SARP charges the U.S. Department of Energy (DOE) or the Waste Isolation Pilot Plant| (WIPP) management and operating (M&O) contractor with assuring packaging is used in accordance with the requirements of the C of C. Because the packaging is NRC-approved, users need to be familiar with Title 10 Code of Federal Regulations(CFR) §71.8. Any time a user suspects or has indications that the conditions ofapproval in the C of C were not met, the Carlsbad Field Office (CBFO) shall be notified immediately. The CBFO will evaluate the issue and notify the NRC if required.In accordance with 10 CFR Part 71, certificate holders, packaging users, and contractors or subcontractors who use, design, fabricate, test, maintain, or modify the packaging shall post copies of (1) 10 CFR Part 21 regulations, (2) Section 206 of the Energy Reorganization Act of 1974, and (3) NRC Form 3, Notice to Employees. These documents must be posted in a conspicuous location where the activities subject to these regulations are

  4. CH Packaging Program Guidance

    Energy Technology Data Exchange (ETDEWEB)

    None, None

    2007-12-13

    The purpose of this document is to provide the technical requirements for preparation for use, operation, inspection, and maintenance of a Transuranic Package Transporter Model II (TRUPACT-II), a HalfPACT shipping package, and directly related components. This document complies with the minimum requirements as specified in the TRUPACT-II Safety Analysis Report for Packaging (SARP), HalfPACT SARP, and U.S. Nuclear Regulatory Commission (NRC) Certificates of Compliance (C of C) 9218 and 9279, respectively. In the event of a conflict between this document and the SARP or C of C, the C of C shall govern. The C of Cs state: "each package must be prepared for shipment and operated in accordance with the procedures described in Chapter 7.0, Operating Procedures, of the application." They further state: "each package must be tested and maintained in accordance with the procedures described in Chapter 8.0, Acceptance Tests and Maintenance Program of the Application." Chapter 9.0 of the SARP charges the U.S. Department of Energy (DOE) or the Waste Isolation Pilot Plant (WIPP) management and operating (M&O) contractor with assuring packaging is used in accordance with the requirements of the C of C. Because the packaging is NRC-approved, users need to be familiar with Title 10 Code of Federal Regulations (CFR) §71.8. Any time a user suspects or has indications that the conditions of approval in the C of C were not met, the Carlsbad Field Office (CBFO) shall be notified immediately. The CBFO will evaluate the issue and notify the NRC if required.In accordance with 10 CFR Part 71, certificate holders, packaging users, and contractors or subcontractors who use, design, fabricate, test, maintain, or modify the packaging shall post copies of (1) 10 CFR Part 21 regulations, (2) Section 206 of the Energy Reorganization Act of 1974, and (3) NRC Form 3, Notice to Employees. These documents must be posted in a conspicuous location where the activities subject to these regulations are

  5. Single-chip microprocessor that communicates directly using light

    Science.gov (United States)

    Sun, Chen; Wade, Mark T.; Lee, Yunsup; Orcutt, Jason S.; Alloatti, Luca; Georgas, Michael S.; Waterman, Andrew S.; Shainline, Jeffrey M.; Avizienis, Rimas R.; Lin, Sen; Moss, Benjamin R.; Kumar, Rajesh; Pavanello, Fabio; Atabaki, Amir H.; Cook, Henry M.; Ou, Albert J.; Leu, Jonathan C.; Chen, Yu-Hsin; Asanović, Krste; Ram, Rajeev J.; Popović, Miloš A.; Stojanović, Vladimir M.

    2015-12-01

    Data transport across short electrical wires is limited by both bandwidth and power density, which creates a performance bottleneck for semiconductor microchips in modern computer systems—from mobile phones to large-scale data centres. These limitations can be overcome by using optical communications based on chip-scale electronic-photonic systems enabled by silicon-based nanophotonic devices8. However, combining electronics and photonics on the same chip has proved challenging, owing to microchip manufacturing conflicts between electronics and photonics. Consequently, current electronic-photonic chips are limited to niche manufacturing processes and include only a few optical devices alongside simple circuits. Here we report an electronic-photonic system on a single chip integrating over 70 million transistors and 850 photonic components that work together to provide logic, memory, and interconnect functions. This system is a realization of a microprocessor that uses on-chip photonic devices to directly communicate with other chips using light. To integrate electronics and photonics at the scale of a microprocessor chip, we adopt a ‘zero-change’ approach to the integration of photonics. Instead of developing a custom process to enable the fabrication of photonics, which would complicate or eliminate the possibility of integration with state-of-the-art transistors at large scale and at high yield, we design optical devices using a standard microelectronics foundry process that is used for modern microprocessors. This demonstration could represent the beginning of an era of chip-scale electronic-photonic systems with the potential to transform computing system architectures, enabling more powerful computers, from network infrastructure to data centres and supercomputers.

  6. Single-chip microprocessor that communicates directly using light.

    Science.gov (United States)

    Sun, Chen; Wade, Mark T; Lee, Yunsup; Orcutt, Jason S; Alloatti, Luca; Georgas, Michael S; Waterman, Andrew S; Shainline, Jeffrey M; Avizienis, Rimas R; Lin, Sen; Moss, Benjamin R; Kumar, Rajesh; Pavanello, Fabio; Atabaki, Amir H; Cook, Henry M; Ou, Albert J; Leu, Jonathan C; Chen, Yu-Hsin; Asanović, Krste; Ram, Rajeev J; Popović, Miloš A; Stojanović, Vladimir M

    2015-12-24

    Data transport across short electrical wires is limited by both bandwidth and power density, which creates a performance bottleneck for semiconductor microchips in modern computer systems--from mobile phones to large-scale data centres. These limitations can be overcome by using optical communications based on chip-scale electronic-photonic systems enabled by silicon-based nanophotonic devices. However, combining electronics and photonics on the same chip has proved challenging, owing to microchip manufacturing conflicts between electronics and photonics. Consequently, current electronic-photonic chips are limited to niche manufacturing processes and include only a few optical devices alongside simple circuits. Here we report an electronic-photonic system on a single chip integrating over 70 million transistors and 850 photonic components that work together to provide logic, memory, and interconnect functions. This system is a realization of a microprocessor that uses on-chip photonic devices to directly communicate with other chips using light. To integrate electronics and photonics at the scale of a microprocessor chip, we adopt a 'zero-change' approach to the integration of photonics. Instead of developing a custom process to enable the fabrication of photonics, which would complicate or eliminate the possibility of integration with state-of-the-art transistors at large scale and at high yield, we design optical devices using a standard microelectronics foundry process that is used for modern microprocessors. This demonstration could represent the beginning of an era of chip-scale electronic-photonic systems with the potential to transform computing system architectures, enabling more powerful computers, from network infrastructure to data centres and supercomputers. PMID:26701054

  7. Single-chip microprocessor that communicates directly using light.

    Science.gov (United States)

    Sun, Chen; Wade, Mark T; Lee, Yunsup; Orcutt, Jason S; Alloatti, Luca; Georgas, Michael S; Waterman, Andrew S; Shainline, Jeffrey M; Avizienis, Rimas R; Lin, Sen; Moss, Benjamin R; Kumar, Rajesh; Pavanello, Fabio; Atabaki, Amir H; Cook, Henry M; Ou, Albert J; Leu, Jonathan C; Chen, Yu-Hsin; Asanović, Krste; Ram, Rajeev J; Popović, Miloš A; Stojanović, Vladimir M

    2015-12-24

    Data transport across short electrical wires is limited by both bandwidth and power density, which creates a performance bottleneck for semiconductor microchips in modern computer systems--from mobile phones to large-scale data centres. These limitations can be overcome by using optical communications based on chip-scale electronic-photonic systems enabled by silicon-based nanophotonic devices. However, combining electronics and photonics on the same chip has proved challenging, owing to microchip manufacturing conflicts between electronics and photonics. Consequently, current electronic-photonic chips are limited to niche manufacturing processes and include only a few optical devices alongside simple circuits. Here we report an electronic-photonic system on a single chip integrating over 70 million transistors and 850 photonic components that work together to provide logic, memory, and interconnect functions. This system is a realization of a microprocessor that uses on-chip photonic devices to directly communicate with other chips using light. To integrate electronics and photonics at the scale of a microprocessor chip, we adopt a 'zero-change' approach to the integration of photonics. Instead of developing a custom process to enable the fabrication of photonics, which would complicate or eliminate the possibility of integration with state-of-the-art transistors at large scale and at high yield, we design optical devices using a standard microelectronics foundry process that is used for modern microprocessors. This demonstration could represent the beginning of an era of chip-scale electronic-photonic systems with the potential to transform computing system architectures, enabling more powerful computers, from network infrastructure to data centres and supercomputers.

  8. Analysis of the fly ash from the processing of wood chips in a pilot-scale downdraft gasifier: Comparison of inorganic constituents determined by PIXE and ICP-AES

    International Nuclear Information System (INIS)

    Gasification of biomass ultimately generates at least one solid byproduct in which the inorganic constituents of the biomass are concentrated. Given the potential for utilization, or issues with disposal, facile methods are needed for determining the compositions of the fly ashes from recently-available gasifier-based bioenergy systems. Proton induced x-ray emission spectroscopy (PIXE) and inductively coupled plasma atomic emission spectroscopy (ICP-AES) were used to characterize the fly ash recovered from a pilot-scale (25 kW) modular bioenergy system operated with wood chips as the feedstock. The composition of the fly ash from the downdraft gasifier showed some similarities to compositions reported for boiler wood ashes, apart from one half of the material being unburned carbon. Although ICP-AES showed greater sensitivity for the analysis of the fly ash, especially for small amounts of heavy metal contaminants, PIXE proved to be a powerful analytical tool for screening of elements from sodium to uranium. Such broad spectrum screenings could prevent the inadvertent land application of unsuspected pollutant elements. Fly ashes from biomass gasification appear to be suitable for use as ash-based fertilizers for forest lands; however, combustion to remove unburned carbon may be advisable. -- Highlights: ► Fly ash composition data for commercial modular bioenergy systems are now reported. ► PIXE analysis better suited for analysis of fly ashes rich in silicates. Fly ashes generated by biomass gasification may be suitable for land application. ► Combustion of biomass-derived fly ashes is recommended before use as soil amendments

  9. Large-scale horizontally aligned ZnO microrod arrays with controlled orientation, periodic distribution as building blocks for chip-in piezo-phototronic LEDs.

    Science.gov (United States)

    Guo, Zhen; Li, Haiwen; Zhou, Lianqun; Zhao, Dongxu; Wu, Yihui; Zhang, Zhiqiang; Zhang, Wei; Li, Chuanyu; Yao, Jia

    2015-01-27

    A novel method of fabricating large-scale horizontally aligned ZnO microrod arrays with controlled orientation and periodic distribution via combing technology is introduced. Horizontally aligned ZnO microrod arrays with uniform orientation and periodic distribution can be realized based on the conventional bottom-up method prepared vertically aligned ZnO microrod matrix via the combing method. When the combing parameters are changed, the orientation of horizontally aligned ZnO microrod arrays can be adjusted (θ = 90° or 45°) in a plane and a misalignment angle of the microrods (0.3° to 2.3°) with low-growth density can be obtained. To explore the potential applications based on the vertically and horizontally aligned ZnO microrods on p-GaN layer, piezo-phototronic devices such as heterojunction LEDs are built. Electroluminescence (EL) emission patterns can be adjusted for the vertically and horizontally aligned ZnO microrods/p-GaN heterojunction LEDs by applying forward bias. Moreover, the emission color from UV-blue to yellow-green can be tuned by investigating the piezoelectric properties of the materials. The EL emission mechanisms of the LEDs are discussed in terms of band diagrams of the heterojunctions and carrier recombination processes.

  10. Packaging Solutions : Delivering customer value through Logistical Packaging: A Case Study at Stora Enso Packaging

    OpenAIRE

    Shan, Kun; Julius, Joezer

    2015-01-01

    AbstractBackground;Despite of the significant role of packaging within logistics and supply chain management, packaging is infrequently studied as focal point in supply chain. Most of the previous logistics research studies tend to explain the integration between packaging and logistics through logistical packaging. In very rare cases, the studies mentioned about customer value. Therefore the major disadvantage of these studies is that, they didn’t consider logistical packaging and customer v...

  11. Ion trap in a semiconductor chip

    Science.gov (United States)

    Stick, D.; Hensinger, W. K.; Olmschenk, S.; Madsen, M. J.; Schwab, K.; Monroe, C.

    2006-01-01

    The electromagnetic manipulation of isolated atoms has led to many advances in physics, from laser cooling and Bose-Einstein condensation of cold gases to the precise quantum control of individual atomic ions. Work on miniaturizing electromagnetic traps to the micrometre scale promises even higher levels of control and reliability. Compared with `chip traps' for confining neutral atoms, ion traps with similar dimensions and power dissipation offer much higher confinement forces and allow unparalleled control at the single-atom level. Moreover, ion microtraps are of great interest in the development of miniature mass-spectrometer arrays, compact atomic clocks and, most notably, large-scale quantum information processors. Here we report the operation of a micrometre-scale ion trap, fabricated on a monolithic chip using semiconductor micro-electromechanical systems (MEMS) technology. We confine, laser cool and measure heating of a single 111Cd+ ion in an integrated radiofrequency trap etched from a doped gallium-arsenide heterostructure.

  12. Ion Trap in a Semiconductor Chip

    CERN Document Server

    Stick, D; Olmschenk, S; Madsen, M J; Schwab, K; Monroe, C

    2006-01-01

    The electromagnetic manipulation of isolated atoms has led to many advances in physics, from laser cooling and Bose-Einstein condensation of cold gases to the precise quantum control of individual atomic ion. Work on miniaturizing electromagnetic traps to the micrometer scale promises even higher levels of control and reliability. Compared with 'chip traps' for confining neutral atoms, ion traps with similar dimensions and power dissipation offer much higher confinement forces and allow unparalleled control at the single-atom level. Moreover, ion microtraps are of great interest in the development of miniature mass spectrometer arrays, compact atomic clocks, and most notably, large scale quantum information processors. Here we report the operation of a micrometer-scale ion trap, fabricated on a monolithic chip using semiconductor micro-electromechanical systems (MEMS) technology. We confine, laser cool, and measure heating of a single 111Cd+ ion in an integrated radiofrequency trap etched from a doped gallium...

  13. Photonic Wire Bonds for Terabit/s Chip-to-Chip Interconnects

    CERN Document Server

    Lindenmann, Nicole; Hillerkuss, David; Schmogrow, Rene; Jordan, Meinert; Leuthold, Juerg; Freude, Wolfgang; Koos, Christian

    2011-01-01

    Photonic integration has witnessed tremendous progress over the last years, and chip-scale transceiver systems with Terabit/s data rates have come into reach. However, as on-chip integration density increases, efficient off-chip interfaces are becoming more and more crucial. A technological breakthrough is considered indispensable to cope with the challenges arising from large-scale photonic integration, and this particularly applies to short-distance optical interconnects. In this letter we introduce the concept of photonic wire bonding, where transparent waveguide wire bonds are used to bridge the gap between nanophotonic circuits located on different chips. We demonstrate for the first time the fabrication of three-dimensional freeform photonic wire bonds (PWB), and we confirm their viability in a multi-Terabit/s data transmission experiment. First-generation prototypes allow for efficient broadband coupling with overall losses of only 1.6 dB. Photonic wire bonding will enable flexible optical multi-chip a...

  14. SPHINX experimenters information package

    Energy Technology Data Exchange (ETDEWEB)

    Zarick, T.A. [Sandia National Lab., Albuquerque, NM (United States). Radiation Effects Experimentation Dept.

    1996-08-01

    This information package was prepared for both new and experienced users of the SPHINX (Short Pulse High Intensity Nanosecond X-radiator) flash X-Ray facility. It was compiled to help facilitate experiment design and preparation for both the experimenter(s) and the SPHINX operational staff. The major areas covered include: Recording Systems Capabilities,Recording System Cable Plant, Physical Dimensions of SPHINX and the SPHINX Test cell, SPHINX Operating Parameters and Modes, Dose Rate Map, Experiment Safety Approval Form, and a Feedback Questionnaire. This package will be updated as the SPHINX facilities and capabilities are enhanced.

  15. SPHINX experimenters information package

    International Nuclear Information System (INIS)

    This information package was prepared for both new and experienced users of the SPHINX (Short Pulse High Intensity Nanosecond X-radiator) flash X-Ray facility. It was compiled to help facilitate experiment design and preparation for both the experimenter(s) and the SPHINX operational staff. The major areas covered include: Recording Systems Capabilities,Recording System Cable Plant, Physical Dimensions of SPHINX and the SPHINX Test cell, SPHINX Operating Parameters and Modes, Dose Rate Map, Experiment Safety Approval Form, and a Feedback Questionnaire. This package will be updated as the SPHINX facilities and capabilities are enhanced

  16. Autonomous packaging robot

    OpenAIRE

    Vo, Van Thanh

    2010-01-01

    The objective of the autonomous packaging robot application is to replace manual product packaging in food industry with a fully automatic robot. The objective is achieved by using the combination of machine vision, central computer, sensors, microcontroller and a typical ABB robot. The method is to equip the robot with different sensors: camera as “eyes” of robot, distance sensor and microcontroller as “sense of touch” of the robot, central computer as “brain” of the robot. Because the ro...

  17. Polymer dispensing and embossing technology for the lens type LED packaging

    International Nuclear Information System (INIS)

    This study presents a ring-type micro-structure design on the substrate and its corresponding micro fabrication processes for a lens-type light-emitting diode (LED) package. The dome-type or crater-type silicone lenses are achieved by a dispensing and embossing process rather than a molding process. Silicone with a high viscosity and thixotropy index is used as the encapsulant material. The ring-type micro structure is adopted to confine the dispensed silicone encapsulant so as to form the packaged lens. With the architecture and process described, this LED package technology herein has three merits: (1) the flexibility of lens-type LED package designs is enhanced; (2) a dome-type package design is used to enhance the intensity; (3) a crater-type package design is used to enhance the view angle. Measurement results show the ratio between the lens height and lens radius can vary from 0.4 to 1 by changing the volume of dispensed silicone. The view angles of dome-type and crater-type packages can reach 155° ± 5° and 175° ± 5°, respectively. As compared with the commercial plastic leaded chip carrier-type package, the luminous flux of a monochromatic blue light LED is improved by 15% by the dome-type package (improved by 7% by the crater-type package) and the luminous flux of a white light LED is improved by 25% by the dome-type package (improved by 13% by the crater-type package). The luminous flux of monochromatic blue light LED and white light LED are respectively improved by 8% and 12% by the dome-type package as compare with the crater-type package. (paper)

  18. "Chips with Everything": A Laboratory Exercise for Comparing Subjective and Objective Measurements of Potato Chips

    Science.gov (United States)

    Davies, Cathy

    2005-01-01

    The following laboratory exercise was designed to aid student understanding of the differences between subjective and objective measurements. Students assess the color and texture of different varieties of potato chip (crisps) by means of an intensity rating scale and a rank test and objectively with a colorimeter and texture analyzer. For data…

  19. An Evaluation of an Integrated On-Chip/Off-Chip Network for High-Performance Reconfigurable Computing

    OpenAIRE

    Kritikos, William V.; Shanyuan Gao; Andrew G. Schmidt; Ron Sass

    2012-01-01

    As the number of cores per discrete integrated circuit (IC) device grows, the importance of the network on chip (NoC) increases. However, the body of research in this area has focused on discrete IC devices alone which may or may not serve the high-performance computing community which needs to assemble many of these devices into very large scale, parallel computing machines. This paper describes an integrated on-chip/off-chip network that has been implemented on an all-FPGA computing cluster...

  20. Heat transfer in high density electronics packaging

    Institute of Scientific and Technical Information of China (English)

    2001-01-01

    In order to get an insight into the thermal characteristic and to evaluate the thermal reliability of the "System in Packaging"(SIP), a new solution of electronics packaging, a heat transfer model of SIP was developed to predict the heat dissipation capacity and to investigate the effect of different factors on the temperature distribution in the electronics. The affecting parameters under consideration include the thermophysical properties of the substrates, the coefficient of convection heat transfer, the thickness of the chip, and the density of power dissipation. ALGOR, a kind of finite element analysis software,was used to do the model simulation. Based on the sinulation and analysis of the heat conduction and convection resistance, criteria for the thermal design were established and possible measurement for enhancing power dissipation was provided, The results show that the heat transfer model provides a new and effective way to the thermal design and thermal analysis of SIP and to the mechanical analysis for the further investigation of SIP.

  1. Standard semiconductor packaging for high-reliability low-cost MEMS applications

    Science.gov (United States)

    Harney, Kieran P.

    2005-01-01

    Microelectronic packaging technology has evolved over the years in response to the needs of IC technology. The fundamental purpose of the package is to provide protection for the silicon chip and to provide electrical connection to the circuit board. Major change has been witnessed in packaging and today wafer level packaging technology has further revolutionized the industry. MEMS (Micro Electro Mechanical Systems) technology has created new challenges for packaging that do not exist in standard ICs. However, the fundamental objective of MEMS packaging is the same as traditional ICs, the low cost and reliable presentation of the MEMS chip to the next level interconnect. Inertial MEMS is one of the best examples of the successful commercialization of MEMS technology. The adoption of MEMS accelerometers for automotive airbag applications has created a high volume market that demands the highest reliability at low cost. The suppliers to these markets have responded by exploiting standard semiconductor packaging infrastructures. However, there are special packaging needs for MEMS that cannot be ignored. New applications for inertial MEMS devices are emerging in the consumer space that adds the imperative of small size to the need for reliability and low cost. These trends are not unique to MEMS accelerometers. For any MEMS technology to be successful the packaging must provide the basic reliability and interconnection functions, adding the least possible cost to the product. This paper will discuss the evolution of MEMS packaging in the accelerometer industry and identify the main issues that needed to be addressed to enable the successful commercialization of the technology in the automotive and consumer markets.

  2. Polymers in Waveguide Packaging

    Institute of Scientific and Technical Information of China (English)

    G; Z.; Xiao; C.; P.; Grover

    2003-01-01

    Polymers were successfully used in the packaging of waveguide-based photonic components in the area of fiber-to-waveguide coupling, waveguide die attachment, strain relief, and waveguide encapsulation. The application results of these polymers were described in this paper.

  3. The Swarm Magnetometry Package

    DEFF Research Database (Denmark)

    Merayo, José M.G.; Jørgensen, John Leif; Friis-Christensen, Eigil;

    2008-01-01

    The Swarm mission under the ESA's Living Planet Programme is planned for launch in 2010 and consists of a constellation of three satellites at LEO. The prime objective of Swarm is to measure the geomagnetic field with unprecedented accuracy in space and time. The magnetometry package consists...

  4. Metric Education Evaluation Package.

    Science.gov (United States)

    Kansky, Bob; And Others

    This document was developed out of a need for a complete, carefully designed set of evaluation instruments and procedures that might be applied in metric inservice programs across the nation. Components of this package were prepared in such a way as to permit local adaptation to the evaluation of a broad spectrum of metric education activities.…

  5. Openability of tamperproof packaging

    NARCIS (Netherlands)

    Del Castillo C., A.; Wever, R.; Buijs, P.J.; Stevels, A.

    2007-01-01

    Communication, product protection and presentation are three key aspects in the world of packaging nowadays. Due to a retail landscape consisting of large stores, displaying packed products on the shelves in self-service environments, these aspects become increasingly important, not only for Fast Mo

  6. Electro-Microfluidic Packaging

    Science.gov (United States)

    Benavides, G. L.; Galambos, P. C.

    2002-06-01

    There are many examples of electro-microfluidic products that require cost effective packaging solutions. Industry has responded to a demand for products such as drop ejectors, chemical sensors, and biological sensors. Drop ejectors have consumer applications such as ink jet printing and scientific applications such as patterning self-assembled monolayers or ejecting picoliters of expensive analytes/reagents for chemical analysis. Drop ejectors can be used to perform chemical analysis, combinatorial chemistry, drug manufacture, drug discovery, drug delivery, and DNA sequencing. Chemical and biological micro-sensors can sniff the ambient environment for traces of dangerous materials such as explosives, toxins, or pathogens. Other biological sensors can be used to improve world health by providing timely diagnostics and applying corrective measures to the human body. Electro-microfluidic packaging can easily represent over fifty percent of the product cost and, as with Integrated Circuits (IC), the industry should evolve to standard packaging solutions. Standard packaging schemes will minimize cost and bring products to market sooner.

  7. Aquaculture Information Package

    Energy Technology Data Exchange (ETDEWEB)

    Boyd, T.; Rafferty, K. [editors

    1998-01-01

    This package of information is intended to provide background to developers of geothermal aquaculture projects. The material is divided into eight sections and includes information on market and price information for typical species, aquaculture water quality issues, typical species culture information, pond heat loss calculations, an aquaculture glossary, regional and university aquaculture offices and state aquaculture permit requirements.

  8. Geothermal Greenhouse Information Package

    Energy Technology Data Exchange (ETDEWEB)

    Rafferty, K. [P.E.; Boyd, T. [ed.

    1997-01-01

    This package of information is intended to provide a foundation of background information for developers of geothermal greenhouses. The material is divided into seven sections covering such issues as crop culture and prices, operating costs for greenhouses, heating system design, vendors and a list of other sources of information.

  9. Waste disposal package

    Science.gov (United States)

    Smith, M.J.

    1985-06-19

    This is a claim for a waste disposal package including an inner or primary canister for containing hazardous and/or radioactive wastes. The primary canister is encapsulated by an outer or secondary barrier formed of a porous ceramic material to control ingress of water to the canister and the release rate of wastes upon breach on the canister. 4 figs.

  10. Radiographic film package

    Energy Technology Data Exchange (ETDEWEB)

    Muylle, W. E.

    1985-08-27

    A radiographic film package for non-destructive testing, comprising a radiographic film sheet, an intensifying screen with a layer of lead bonded to a paper foil, and a vacuum heat-sealed wrapper with a layer of aluminum and a heat-sealed easy-peelable thermoplastic layer.

  11. A Quality-of-Service Mechanism for Interconnection Networks in System-on-Chips

    CERN Document Server

    Weber, Wolf-Dietrich; Swarbrick, Ian; Wingard, Drew

    2011-01-01

    As Moore's Law continues to fuel the ability to build ever increasingly complex system-on-chips (SoCs), achieving performance goals is rising as a critical challenge to completing designs. In particular, the system interconnect must efficiently service a diverse set of data flows with widely ranging quality-of-service (QoS) requirements. However, the known solutions for off-chip interconnects such as large-scale networks are not necessarily applicable to the on-chip environment. Latency and memory constraints for on-chip interconnects are quite different from larger-scale interconnects. This paper introduces a novel on-chip interconnect arbitration scheme. We show how this scheme can be distributed across a chip for high-speed implementation. We compare the performance of the arbitration scheme with other known interconnect arbitration schemes. Existing schemes typically focus heavily on either low latency of service for some initiators, or alternatively on guaranteed bandwidth delivery for other initiators. ...

  12. China's first WLAN chips

    Institute of Scientific and Technical Information of China (English)

    2007-01-01

    @@ The wireless local area network (WLAN) chips independently developed by CAS researchers were in the limelight of the recent Electronic Manufacture Exposition held in Suzhou, east China's Jiangsu Province.

  13. CHIP Enrollment Reports

    Data.gov (United States)

    U.S. Department of Health & Human Services — CHIP quarterly and annual statistical enrollment reports. The quarterly reports contain point-in-time and ever enrolled data and the annual reports contain ever...

  14. Medicaid CHIP ESPC Database

    Data.gov (United States)

    U.S. Department of Health & Human Services — The Environmental Scanning and Program Characteristic (ESPC) Database is in a Microsoft (MS) Access format and contains Medicaid and CHIP data, for the 50 states...

  15. Package performance evaluation: our latest 20-year experience

    International Nuclear Information System (INIS)

    Packages for the transport of radioactive material have to comply with national and / or international regulations. These regulations are widely based on the requirements set forth by the International Atomic Energy Agency (IAEA) in the ''Regulations for the Safe Transport of Radioactive Material''. During the last 20 years, on several of its package designs, COGEMA LOGISTICS has performed tests and analyses to simulate extremely severe accidents. These tests and analysis include: 1. long duration fire test and deep immersion test on a package designed to transport plutonium oxide powder, 2. deep immersion tests on scale model of packages designed to transport spent fuel, high level vitrified waste and fresh MOX (uranium and plutonium mixed oxide) fuel, 3. burial in a soft ground of packages designed to transport spent fuel, and 4. numerical study of the thermal behaviour of packages designed to transport spent fuel and high level vitrified waste. 5. aircraft crash test on scale models of dual-purpose packages for the transport and storage of spent fuel. The paper will: review the tests and analysis which were performed, show that our designs are able to withstand extremely severe conditions, demonstrate that there is no cliff effect: should a failure occurs, it appears gradually and there is no sudden collapse of the package, and explain how compliance with all the regulatory requirements lead to high performances regarding each of them (for instance, in many cases, the need to meet radiation exposure criteria induces a mechanical resistance higher than that required to pass the regulatory requirements)

  16. DVFS using clock scheduling for Multicore Systems-on-Chip and Networks-on-Chip

    OpenAIRE

    Yadav, Manoj Kumar

    2014-01-01

    A modern System-on-Chip (SoC) contains processor cores, application-specific process- ing elements, memory, peripherals, all connected with a high-bandwidth and low-latency Network-on-Chip (NoC). The downside of such very high level of integration and con- nectivity is the high power consumption. In CMOS technology this is made of a dynamic and a static component. To reduce the dynamic component, Dynamic voltage and Fre- quency Scaling (DVFS) has been adopted. Although DVFS is very effective ...

  17. Lakes Ecosystem Services Download Package

    Data.gov (United States)

    U.S. Environmental Protection Agency — This data download package contains Esri 10.0 MXDs, file geodatabases and copy of this FGDC metadata record. The data in this package are used in support of the...

  18. Sustainable Library Development Training Package

    Science.gov (United States)

    Peace Corps, 2012

    2012-01-01

    This Sustainable Library Development Training Package supports Peace Corps' Focus In/Train Up strategy, which was implemented following the 2010 Comprehensive Agency Assessment. Sustainable Library Development is a technical training package in Peace Corps programming within the Education sector. The training package addresses the Volunteer…

  19. Heat management in integrated circuits on-chip and system-level monitoring and cooling

    CERN Document Server

    Ogrenci-Memik, Seda

    2016-01-01

    This essential overview covers the subject of thermal monitoring and management in integrated circuits. Specifically, it focuses on devices and materials that are intimately integrated on-chip (as opposed to in-package or on-board) for the purposes of thermal monitoring and thermal management.

  20. The Ettention software package.

    Science.gov (United States)

    Dahmen, Tim; Marsalek, Lukas; Marniok, Nico; Turoňová, Beata; Bogachev, Sviatoslav; Trampert, Patrick; Nickels, Stefan; Slusallek, Philipp

    2016-02-01

    We present a novel software package for the problem "reconstruction from projections" in electron microscopy. The Ettention framework consists of a set of modular building-blocks for tomographic reconstruction algorithms. The well-known block iterative reconstruction method based on Kaczmarz algorithm is implemented using these building-blocks, including adaptations specific to electron tomography. Ettention simultaneously features (1) a modular, object-oriented software design, (2) optimized access to high-performance computing (HPC) platforms such as graphic processing units (GPU) or many-core architectures like Xeon Phi, and (3) accessibility to microscopy end-users via integration in the IMOD package and eTomo user interface. We also provide developers with a clean and well-structured application programming interface (API) that allows for extending the software easily and thus makes it an ideal platform for algorithmic research while hiding most of the technical details of high-performance computing. PMID:26686659

  1. Anticounterfeit packaging technologies

    Directory of Open Access Journals (Sweden)

    Ruchir Y Shah

    2010-01-01

    Full Text Available Packaging is the coordinated system that encloses and protects the dosage form. Counterfeit drugs are the major cause of morbidity, mortality, and failure of public interest in the healthcare system. High price and well-known brands make the pharma market most vulnerable, which accounts for top priority cardiovascular, obesity, and antihyperlipidemic drugs and drugs like sildenafil. Packaging includes overt and covert technologies like barcodes, holograms, sealing tapes, and radio frequency identification devices to preserve the integrity of the pharmaceutical product. But till date all the available techniques are synthetic and although provide considerable protection against counterfeiting, have certain limitations which can be overcome by the application of natural approaches and utilization of the principles of nanotechnology.

  2. Aquaculture information package

    Energy Technology Data Exchange (ETDEWEB)

    Boyd, T.; Rafferty, K.

    1998-08-01

    This package of information is intended to provide background information to developers of geothermal aquaculture projects. The material is divided into eight sections and includes information on market and price information for typical species, aquaculture water quality issues, typical species culture information, pond heat loss calculations, an aquaculture glossary, regional and university aquaculture offices and state aquaculture permit requirements. A bibliography containing 68 references is also included.

  3. Standard integrated head package

    International Nuclear Information System (INIS)

    An integrated head package for a standard-type nuclear reactor is described which consolidates many components and subassemblies of the upper reactor structure into a single unit which may be removed from the reactor vessel in a single lift. Included among the consolidated elements are a pressure vessel head, a cooling shroud, control rod drive mechanisms, a missile shield, a lifting rig, a hoist assembly, and a cable tray assembly. (author)

  4. Radiant heat test of Perforated Metal Air Transportable Package (PMATP).

    Energy Technology Data Exchange (ETDEWEB)

    Gronewald, Patrick James; Oneto, Robert (Weidlinger Associates, Inc., Los Altos, CA); Mould, John (Weidlinger Associates, Inc., Los Altos, CA); Pierce, Jim Dwight

    2003-08-01

    A conceptual design for a plutonium air transport package capable of surviving a 'worst case' airplane crash has been developed by Sandia National Laboratories (SNL) for the Japan Nuclear Cycle Development Institute (JNC). A full-scale prototype, designated as the Perforated Metal Air Transport Package (PMATP) was thermally tested in the SNL Radiant Heat Test Facility. This testing, conducted on an undamaged package, simulated a regulation one-hour aviation fuel pool fire test. Finite element thermal predictions compared well with the test results. The package performed as designed, with peak containment package temperatures less than 80 C after exposure to a one-hour test in a 1000 C environment.

  5. Plutonium stabilization and packaging system

    International Nuclear Information System (INIS)

    This document describes the functional design of the Plutonium Stabilization and Packaging System (Pu SPS). The objective of this system is to stabilize and package plutonium metals and oxides of greater than 50% wt, as well as other selected isotopes, in accordance with the requirements of the DOE standard for safe storage of these materials for 50 years. This system will support completion of stabilization and packaging campaigns of the inventory at a number of affected sites before the year 2002. The package will be standard for all sites and will provide a minimum of two uncontaminated, organics free confinement barriers for the packaged material

  6. Sensing systems using chip-based spectrometers

    Science.gov (United States)

    Nitkowski, Arthur; Preston, Kyle J.; Sherwood-Droz, Nicolás.; Behr, Bradford B.; Bismilla, Yusuf; Cenko, Andrew T.; DesRoches, Brandon; Meade, Jeffrey T.; Munro, Elizabeth A.; Slaa, Jared; Schmidt, Bradley S.; Hajian, Arsen R.

    2014-06-01

    Tornado Spectral Systems has developed a new chip-based spectrometer called OCTANE, the Optical Coherence Tomography Advanced Nanophotonic Engine, built using a planar lightwave circuit with integrated waveguides fabricated on a silicon wafer. While designed for spectral domain optical coherence tomography (SD-OCT) systems, the same miniaturized technology can be applied to many other spectroscopic applications. The field of integrated optics enables the design of complex optical systems which are monolithically integrated on silicon chips. The form factors of these systems can be significantly smaller, more robust and less expensive than their equivalent free-space counterparts. Fabrication techniques and material systems developed for microelectronics have previously been adapted for integrated optics in the telecom industry, where millions of chip-based components are used to power the optical backbone of the internet. We have further adapted the photonic technology platform for spectroscopy applications, allowing unheard-of economies of scale for these types of optical devices. Instead of changing lenses and aligning systems, these devices are accurately designed programmatically and are easily customized for specific applications. Spectrometers using integrated optics have large advantages in systems where size, robustness and cost matter: field-deployable devices, UAVs, UUVs, satellites, handheld scanning and more. We will discuss the performance characteristics of our chip-based spectrometers and the type of spectral sensing applications enabled by this technology.

  7. Reliability of Semiconductor Laser Packaging in Space Applications

    Science.gov (United States)

    Gontijo, Ivair; Qiu, Yueming; Shapiro, Andrew A.

    2008-01-01

    A typical set up used to perform lifetime tests of packaged, fiber pigtailed semiconductor lasers is described, as well as tests performed on a set of four pump lasers. It was found that two lasers failed after 3200, and 6100 hours under device specified bias conditions at elevated temperatures. Failure analysis of the lasers indicates imperfections and carbon contamination of the laser metallization, possibly from improperly cleaned photo resist. SEM imaging of the front facet of one of the lasers, although of poor quality due to the optical fiber charging effects, shows evidence of catastrophic damage at the facet. More stringent manufacturing controls with 100% visual inspection of laser chips are needed to prevent imperfect lasers from proceeding to packaging and ending up in space applications, where failure can result in the loss of a space flight mission.

  8. Fuzzy Logic Control ASIC Chip

    Institute of Scientific and Technical Information of China (English)

    沈理

    1997-01-01

    A fuzzy logic control VLSI chip,F100,for industry process real-time control has been designed and fabricated with 0.8μm CMOS technology.The chip has the features of simplicity,felexibility and generality.This paper presents the Fuzzy control inrerence method of the chip,its VLSI implementation,and testing esign consideration.

  9. Advanced Packaging Technology Used in Fabricating a High-Temperature Silicon Carbide Pressure Sensor

    Science.gov (United States)

    Beheim, Glenn M.

    2003-01-01

    The development of new aircraft engines requires the measurement of pressures in hot areas such as the combustor and the final stages of the compressor. The needs of the aircraft engine industry are not fully met by commercially available high-temperature pressure sensors, which are fabricated using silicon. Kulite Semiconductor Products and the NASA Glenn Research Center have been working together to develop silicon carbide (SiC) pressure sensors for use at high temperatures. At temperatures above 850 F, silicon begins to lose its nearly ideal elastic properties, so the output of a silicon pressure sensor will drift. SiC, however, maintains its nearly ideal mechanical properties to extremely high temperatures. Given a suitable sensor material, a key to the development of a practical high-temperature pressure sensor is the package. A SiC pressure sensor capable of operating at 930 F was fabricated using a newly developed package. The durability of this sensor was demonstrated in an on-engine test. The SiC pressure sensor uses a SiC diaphragm, which is fabricated using deep reactive ion etching. SiC strain gauges on the surface of the diaphragm sense the pressure difference across the diaphragm. Conventionally, the SiC chip is mounted to the package with the strain gauges outward, which exposes the sensitive metal contacts on the chip to the hostile measurement environment. In the new Kulite leadless package, the SiC chip is flipped over so that the metal contacts are protected from oxidation by a hermetic seal around the perimeter of the chip. In the leadless package, a conductive glass provides the electrical connection between the pins of the package and the chip, which eliminates the fragile gold wires used previously. The durability of the leadless SiC pressure sensor was demonstrated when two 930 F sensors were tested in the combustor of a Pratt & Whitney PW4000 series engine. Since the gas temperatures in these locations reach 1200 to 1300 F, the sensors were

  10. On-chip pretreatment of whole blood by using MEMS technology

    CERN Document Server

    Chen, Xing

    2012-01-01

    Microfabrication technology has stimulated a plurality of lab-on-a-chip research and development efforts aimed at enabling biomedical researchers and health care practitioners to manipulate and analyze complex biological fluids at the nano and microliter scale. On-chip pretreatment of whole blood is one of the hottest topics in lab-on-a-chip research since whole blood has been regarded as the most important clinical sample. Various microfluidic chips for blood sample pretreatment, such as plasma isolation, cells separation, cells lysis, gene or protein purification, etc., are described in this

  11. World with Chips

    Science.gov (United States)

    Hoefflinger, Bernd

    Although we are well advised to look at the future 1 day at a time, we have seen in the chapters of this book, and they necessarily could cover only a selection on the features and applications of those tiny chips, that their potential continues to grow at the exceptional rates of the past. However, the new commitment has to be towards Sustainable Nanoelectronics, guided by creating sensing, computing, memory, and communication functions, which move just a few electrons per operation, each operation consuming energy less than one or a few femtojoule, less than any of the 1014 synapses in our brains. At these energy levels, chips can serve everywhere, making them ubiquitous, pervasive, certainly wireless, and often energy-autonomous. The expected six Billion users of these chips in 2020, through their mobile, intelligent companions, will benefit from global and largely equal access to information, education, knowledge, skills, and care.

  12. Hermetic glass frit packaging in air and vacuum with localized laser joining

    Science.gov (United States)

    Lorenz, N.; Millar, S.; Desmulliez, M.; Hand, D. P.

    2011-04-01

    Glass frit packaging is a simple and robust method used for hermetic sealing of micro-devices. Conventional glass frit packaging processes rely on furnace heating where the entire package is heated to elevated temperatures, hence restricting the use of temperature-sensitive materials inside the package and generating problems in multi-stage packaging processes. The use of a laser as an alternative heat source offers the possibility of highly localized heating where the heat-input can be restricted to the joining area only. In this paper the clear benefits of combining glass frit packaging and localized laser heating are demonstrated. Two novel laser-based glass frit packaging processes for sealing of leadless chip carrier (LCC) packages in both air and vacuum have been developed. Full hermetic seals according to MIL-STD-883G are achieved in high yield processes where the temperature in the centre of the device is kept at least 230 °C below the temperature in the joining region.

  13. Increasing the portion size of a packaged snack increases energy intake in men and women.

    Science.gov (United States)

    Rolls, Barbara J; Roe, Liane S; Kral, Tanja V E; Meengs, Jennifer S; Wall, Denise E

    2004-02-01

    The objective of this study was to determine how the portion size of a packaged snack affects energy intake of the snack and of the subsequent meal. On five separate days, 60 subjects (34 women and 26 men) ate an afternoon snack and dinner in individual cubicles. For each snack, subjects were served one of five packages of potato chips (28, 42, 85, 128, or 170 g), which they consumed ad libitum directly from the unlabelled, opaque package. Subjects returned to the lab three hours later for a standard dinner, which was also consumed ad libitum. Results showed that snack intake increased significantly as the package size increased for both males and females (p snack and dinner also increased as the package size increased. On average, when served the largest snack package compared to the smallest, subjects consumed an additional 596 kJ (143 kcal) at snack and dinner combined. Results from this study demonstrate that short-term energy intake increases with increasing package size of a snack. These data suggest that the availability of large packages of energy-dense snacks may be one of the environmental influences associated with excess energy intake. PMID:15036784

  14. Packaging's Contribution for the Effectiveness of the Space Station's Food Service Operation

    Science.gov (United States)

    Rausch, B. A.

    1985-01-01

    Storage limitations will have a major effect on space station food service. For example: foods with low bulk density such as ice cream, bread, cake, standard type potato chips and other low density snacks, flaked cereals, etc., will exacerbate the problem of space limitations; package containers are inherently volume consuming and refuse creating; and the useful observation that the optimum package is no package at all leads to the tentative conclusion that the least amount of packaging per unit of food, consistent with storage, aesthetics, preservation, cleanliness, cost and disposal criteria, is the most practical food package for the space station. A series of trade offs may have to be made to arrive at the most appropriate package design for a particular type of food taking all the criteria into account. Some of these trade offs are: single serve vs. bulk; conventional oven vs. microwave oven; nonmetallic aseptically vs. non-aseptically packaged foods; and comparison of aseptic vs. nonaseptic food packages. The advantages and disadvantages are discussed.

  15. Ten-channel InP-based large-scale photonic integrated transmitter fabricated by SAG technology

    Science.gov (United States)

    Zhang, Can; Zhu, Hongliang; Liang, Song; Cui, Xiao; Wang, Huitao; Zhao, Lingjuan; Wang, Wei

    2014-12-01

    A 10-channel InP-based large-scale photonic integrated transmitter was fabricated by selective area growth (SAG) technology combined with butt-joint regrowth (BJR) technology. The SAG technology was utilized to fabricate the electroabsorption modulated distributed feedback (DFB) laser (EML) arrays at the same time. The design of coplanar electrodes for electroabsorption modulator (EAM) was used for the flip-chip bonding package. The lasing wavelength of DFB laser could be tuned by the integrated micro-heater to match the ITU grids, which only needs one electrode pad. The average output power of each channel is 250 μW with an injection current of 200 mA. The static extinction ratios of the EAMs for 10 channels tested are ranged from 15 to 27 dB with a reverse bias of 6 V. The frequencies of 3 dB bandwidth of the chip for each channel are around 14 GHz. The novel design and simple fabrication process show its enormous potential in reducing the cost of large-scale photonic integrated circuit (LS-PIC) transmitter with high chip yields.

  16. Packaging - Materials review

    Science.gov (United States)

    Herrmann, Matthias

    2014-06-01

    Nowadays, a large number of different electrochemical energy storage systems are known. In the last two decades the development was strongly driven by a continuously growing market of portable electronic devices (e.g. cellular phones, lap top computers, camcorders, cameras, tools). Current intensive efforts are under way to develop systems for automotive industry within the framework of electrically propelled mobility (e.g. hybrid electric vehicles, plug-in hybrid electric vehicles, full electric vehicles) and also for the energy storage market (e.g. electrical grid stability, renewable energies). Besides the different systems (cell chemistries), electrochemical cells and batteries were developed and are offered in many shapes, sizes and designs, in order to meet performance and design requirements of the widespread applications. Proper packaging is thereby one important technological step for designing optimum, reliable and safe batteries for operation. In this contribution, current packaging approaches of cells and batteries together with the corresponding materials are discussed. The focus is laid on rechargeable systems for industrial applications (i.e. alkaline systems, lithium-ion, lead-acid). In principle, four different cell types (shapes) can be identified - button, cylindrical, prismatic and pouch. Cell size can be either in accordance with international (e.g. International Electrotechnical Commission, IEC) or other standards or can meet application-specific dimensions. Since cell housing or container, terminals and, if necessary, safety installations as inactive (non-reactive) materials reduce energy density of the battery, the development of low-weight packages is a challenging task. In addition to that, other requirements have to be fulfilled: mechanical stability and durability, sealing (e.g. high permeation barrier against humidity for lithium-ion technology), high packing efficiency, possible installation of safety devices (current interrupt device

  17. Packaging - Materials review

    International Nuclear Information System (INIS)

    Nowadays, a large number of different electrochemical energy storage systems are known. In the last two decades the development was strongly driven by a continuously growing market of portable electronic devices (e.g. cellular phones, lap top computers, camcorders, cameras, tools). Current intensive efforts are under way to develop systems for automotive industry within the framework of electrically propelled mobility (e.g. hybrid electric vehicles, plug-in hybrid electric vehicles, full electric vehicles) and also for the energy storage market (e.g. electrical grid stability, renewable energies). Besides the different systems (cell chemistries), electrochemical cells and batteries were developed and are offered in many shapes, sizes and designs, in order to meet performance and design requirements of the widespread applications. Proper packaging is thereby one important technological step for designing optimum, reliable and safe batteries for operation. In this contribution, current packaging approaches of cells and batteries together with the corresponding materials are discussed. The focus is laid on rechargeable systems for industrial applications (i.e. alkaline systems, lithium-ion, lead-acid). In principle, four different cell types (shapes) can be identified - button, cylindrical, prismatic and pouch. Cell size can be either in accordance with international (e.g. International Electrotechnical Commission, IEC) or other standards or can meet application-specific dimensions. Since cell housing or container, terminals and, if necessary, safety installations as inactive (non-reactive) materials reduce energy density of the battery, the development of low-weight packages is a challenging task. In addition to that, other requirements have to be fulfilled: mechanical stability and durability, sealing (e.g. high permeation barrier against humidity for lithium-ion technology), high packing efficiency, possible installation of safety devices (current interrupt device

  18. Packaging - Materials review

    Energy Technology Data Exchange (ETDEWEB)

    Herrmann, Matthias [Hoppecke Advanced Battery Technology GmbH, 08056 Zwickau (Germany)

    2014-06-16

    Nowadays, a large number of different electrochemical energy storage systems are known. In the last two decades the development was strongly driven by a continuously growing market of portable electronic devices (e.g. cellular phones, lap top computers, camcorders, cameras, tools). Current intensive efforts are under way to develop systems for automotive industry within the framework of electrically propelled mobility (e.g. hybrid electric vehicles, plug-in hybrid electric vehicles, full electric vehicles) and also for the energy storage market (e.g. electrical grid stability, renewable energies). Besides the different systems (cell chemistries), electrochemical cells and batteries were developed and are offered in many shapes, sizes and designs, in order to meet performance and design requirements of the widespread applications. Proper packaging is thereby one important technological step for designing optimum, reliable and safe batteries for operation. In this contribution, current packaging approaches of cells and batteries together with the corresponding materials are discussed. The focus is laid on rechargeable systems for industrial applications (i.e. alkaline systems, lithium-ion, lead-acid). In principle, four different cell types (shapes) can be identified - button, cylindrical, prismatic and pouch. Cell size can be either in accordance with international (e.g. International Electrotechnical Commission, IEC) or other standards or can meet application-specific dimensions. Since cell housing or container, terminals and, if necessary, safety installations as inactive (non-reactive) materials reduce energy density of the battery, the development of low-weight packages is a challenging task. In addition to that, other requirements have to be fulfilled: mechanical stability and durability, sealing (e.g. high permeation barrier against humidity for lithium-ion technology), high packing efficiency, possible installation of safety devices (current interrupt device

  19. Components of Adenovirus Genome Packaging

    Science.gov (United States)

    Ahi, Yadvinder S.; Mittal, Suresh K.

    2016-01-01

    Adenoviruses (AdVs) are icosahedral viruses with double-stranded DNA (dsDNA) genomes. Genome packaging in AdV is thought to be similar to that seen in dsDNA containing icosahedral bacteriophages and herpesviruses. Specific recognition of the AdV genome is mediated by a packaging domain located close to the left end of the viral genome and is mediated by the viral packaging machinery. Our understanding of the role of various components of the viral packaging machinery in AdV genome packaging has greatly advanced in recent years. Characterization of empty capsids assembled in the absence of one or more components involved in packaging, identification of the unique vertex, and demonstration of the role of IVa2, the putative packaging ATPase, in genome packaging have provided compelling evidence that AdVs follow a sequential assembly pathway. This review provides a detailed discussion on the functions of the various viral and cellular factors involved in AdV genome packaging. We conclude by briefly discussing the roles of the empty capsids, assembly intermediates, scaffolding proteins, portal vertex and DNA encapsidating enzymes in AdV assembly and packaging. PMID:27721809

  20. Packaging-radiation disinfestation relationships

    International Nuclear Information System (INIS)

    Foods that are susceptible to insect infestation can be irradiated to destroy the infestation; however, the food must be kept essentially insect-free until consumed, or it must be disinfested again, perhaps repeatedly. Insect-resistant packages can be used to prevent reinfestation, but there are certain requirements that must be fulfilled before a package can be made insect resistant. These include the use of insect-light construction and packaging materials that resist boring insects. The relative insect resistance of various packages and packaging materials is discussed, as are behavior traits such as egressive boring that enables insects to escape from packages and the ability of insects to climb on various packaging materials. Some successful and unsuccessful attempts to make various types of packages insect resistant are discussed, as are factors that must be considered in the selection or development of insect-resistant packages for radiation disinfested foods. The latter factors include biological and physical environments, length of storage periods, stresses on packages during shipment, types of storage facilities, governmental regulations, health requirements, and others

  1. New package for CMOS sensors

    Science.gov (United States)

    Diot, Jean-Luc; Loo, Kum Weng; Moscicki, Jean-Pierre; Ng, Hun Shen; Tee, Tong Yan; Teysseyre, Jerome; Yap, Daniel

    2004-02-01

    Cost is the main drawback of existing packages for C-MOS sensors (mainly CLCC family). Alternative packages are thus developed world-wide. And in particular, S.T.Microelectronics has studied a low cost alternative packages based on QFN structure, still with a cavity. Intensive work was done to optimize the over-molding operation forming the cavity onto a metallic lead-frame (metallic lead-frame is a low cost substrate allowing very good mechanical definition of the final package). Material selection (thermo-set resin and glue for glass sealing) was done through standard reliability tests for cavity packages (Moisture Sensitivity Level 3 followed by temperature cycling, humidity storage and high temperature storage). As this package concept is new (without leads protruding the molded cavity), the effect of variation of package dimensions, as well as board lay-out design, are simulated on package life time (during temperature cycling, thermal mismatch between board and package leads to thermal fatigue of solder joints). These simulations are correlated with an experimental temperature cycling test with daisy-chain packages.

  2. The PIDCalib package

    CERN Document Server

    Anderlini, Lucio; Jones, Christopher Rob; Malde, Sneha Sirirshkumar; Muller, Dominik; Ogilvy, Stephen; Otalora Goicochea, Juan Martin; Pearce, Alex; Polyakov, Ivan; Qian, Wenbin; Sciascia, Barbara; Vazquez Gomez, Ricardo; Zhang, Yanxi

    2016-01-01

    The PIDCalib package is a tool, widely used within the LHCb Collaboration, providing access to the calibration samples of electrons, muons, pions, kaons and protons. This note covers both theoretical aspects related to the measurement of the efficiency of particle identification requirements, and more technical issues such as the selection of the calibration samples, the background subtraction procedure, and the storage of the data sets in the new data-processing scheme adopted by the LHCb experiment during the second run of the LHC.

  3. Rock mechanics data package

    International Nuclear Information System (INIS)

    This data package provides a summary of available laboratory and in situ stress field test results from site characterization investigations by the Basalt Waste Isolation Project Modeling and Analysis Group. The objective is to furnish rock mechanics information for use by Rockwell Hanford Operations and their subcontractors in performance assessment and engineering studies. This release includes Reference Repository Location (RRL) site specific laboratory and field test data from boreholes RRL-2, RRL-6, and RRL-14 as well as previous Hanford wide data available as of April, 1985. 25 refs., 9 figs., 16 tabs

  4. The PIDCalib package

    CERN Document Server

    Anderlini, Lucio; Jones, Christopher Rob; Malde, Sneha Sirirshkumar; Muller, Dominik; Ogilvy, Stephen; Otalora Goicochea, Juan Martin; Pearce, Alex; Polyakov, Ivan; Qian, Wenbin; Sciascia, Barbara; Vazquez Gomez, Ricardo; Zhang, Yanxi

    2016-01-01

    The PIDCalib package is a tool, widely used within the LHCb Collaboration, which provides access to the calibration samples of electrons, muons, pions, kaons and protons. This note covers both theoretical aspects related to the measurement of the efficiency of particle identification requirements, and more technical issues such as the selection of the calibration samples, the background subtraction procedure, and the storage of the data sets in the new data-processing scheme adopted by the LHCb experiment during the second run of the LHC.

  5. Package-on-Package (PoP) for Advanced PCB Manufacturing Process%用于先进PCB制造工艺的叠层封装

    Institute of Scientific and Technical Information of China (English)

    Joseph Y. Lee; Jinyong Ahn; JeGwang Yoo; Joonsung Kim; Hwa-Sun Park; Shuichi Okabe

    2007-01-01

    In the 1990's, both BGA (Ball Grid Array) and CSP (Chip Size Package) are entering their end in the front-end packaging materials and process technology. Both BGA and CSP like SMD (Surface Mount Device) from the 1980's and THD (Through-Hole mount Device) from the 1970's are reaching its own impasse in terms of maximizing its electrical, mechanical, and thermal performances, size,weight, and reliability. Now, 3D packages are the next phase for its future use in advanced PCB manufacturing process. They can be classified into wafer level, chip level, and package level stacking. So,package-on-package (PoP), a type of 3D package level stacking, is to be discussed in this paper [15].%在20世纪90年代,球栅阵列封装(BGA)和芯片尺寸封装(CSP)在封装材料和加工工艺方面达到了极限.这2种技术如同20世纪80年代的表面安装器件(SMD)和70年代通孔安装器件(THD)一样,在电学、机械、热性能、尺寸、质量和可靠性方面达到最大值.目前,三维封装正在成为用于未来采用的先进印制板(PCB)制造工艺的下一个阶段.它们可以分为圆片级封装、芯片级封装、和封装面.叠层封装(PoP)是一种封装面叠层封装类型的三维封装技术[15].

  6. Trapping molecules on chips

    CERN Document Server

    Santambrogio, Gabriele

    2015-01-01

    In the last years, it was demonstrated that neutral molecules can be loaded on a microchip directly from a supersonic beam. The molecules are confined in microscopic traps that can be moved smoothly over the surface of the chip. Once the molecules are trapped, they can be decelerated to a standstill, for instance, or pumped into selected quantum states by laser light or microwaves. Molecules are detected on the chip by time-resolved spatial imaging, which allows for the study of the distribution in the phase space of the molecular ensemble.

  7. Safety Analysis Report for packaging (onsite) steel waste package

    International Nuclear Information System (INIS)

    The steel waste package is used primarily for the shipment of remote-handled radioactive waste from the 324 Building to the 200 Area for interim storage. The steel waste package is authorized for shipment of transuranic isotopes. The maximum allowable radioactive material that is authorized is 500,000 Ci. This exceeds the highway route controlled quantity (3,000 A2s) and is a type B packaging

  8. Inherent polarization entanglement generated from a monolithic semiconductor chip

    DEFF Research Database (Denmark)

    Horn, Rolf T.; Kolenderski, Piotr; Kang, Dongpeng;

    2013-01-01

    Creating miniature chip scale implementations of optical quantum information protocols is a dream for many in the quantum optics community. This is largely because of the promise of stability and scalability. Here we present a monolithically integratable chip architecture upon which is built...... a photonic device primitive called a Bragg reflection waveguide (BRW). Implemented in gallium arsenide, we show that, via the process of spontaneous parametric down conversion, the BRW is capable of directly producing polarization entangled photons without additional path difference compensation, spectral...... as a serious contender on which to build large scale implementations of optical quantum processing devices....

  9. Evaluating laser-driven Bremsstrahlung radiation sources for imaging and analysis of nuclear waste packages.

    Science.gov (United States)

    Jones, Christopher P; Brenner, Ceri M; Stitt, Camilla A; Armstrong, Chris; Rusby, Dean R; Mirfayzi, Seyed R; Wilson, Lucy A; Alejo, Aarón; Ahmed, Hamad; Allott, Ric; Butler, Nicholas M H; Clarke, Robert J; Haddock, David; Hernandez-Gomez, Cristina; Higginson, Adam; Murphy, Christopher; Notley, Margaret; Paraskevoulakos, Charilaos; Jowsey, John; McKenna, Paul; Neely, David; Kar, Satya; Scott, Thomas B

    2016-11-15

    A small scale sample nuclear waste package, consisting of a 28mm diameter uranium penny encased in grout, was imaged by absorption contrast radiography using a single pulse exposure from an X-ray source driven by a high-power laser. The Vulcan laser was used to deliver a focused pulse of photons to a tantalum foil, in order to generate a bright burst of highly penetrating X-rays (with energy >500keV), with a source size of chips. The uranium penny was clearly resolved to sub-mm accuracy over a 30cm(2) scan area from a single shot acquisition. In addition, neutron generation was demonstrated in situ with the X-ray beam, with a single shot, thus demonstrating the potential for multi-modal criticality testing of waste materials. This feasibility study successfully demonstrated non-destructive radiography of encapsulated, high density, nuclear material. With recent developments of high-power laser systems, to 10Hz operation, a laser-driven multi-modal beamline for waste monitoring applications is envisioned. PMID:27484945

  10. Evaluating laser-driven Bremsstrahlung radiation sources for imaging and analysis of nuclear waste packages.

    Science.gov (United States)

    Jones, Christopher P; Brenner, Ceri M; Stitt, Camilla A; Armstrong, Chris; Rusby, Dean R; Mirfayzi, Seyed R; Wilson, Lucy A; Alejo, Aarón; Ahmed, Hamad; Allott, Ric; Butler, Nicholas M H; Clarke, Robert J; Haddock, David; Hernandez-Gomez, Cristina; Higginson, Adam; Murphy, Christopher; Notley, Margaret; Paraskevoulakos, Charilaos; Jowsey, John; McKenna, Paul; Neely, David; Kar, Satya; Scott, Thomas B

    2016-11-15

    A small scale sample nuclear waste package, consisting of a 28mm diameter uranium penny encased in grout, was imaged by absorption contrast radiography using a single pulse exposure from an X-ray source driven by a high-power laser. The Vulcan laser was used to deliver a focused pulse of photons to a tantalum foil, in order to generate a bright burst of highly penetrating X-rays (with energy >500keV), with a source size of <0.5mm. BAS-TR and BAS-SR image plates were used for image capture, alongside a newly developed Thalium doped Caesium Iodide scintillator-based detector coupled to CCD chips. The uranium penny was clearly resolved to sub-mm accuracy over a 30cm(2) scan area from a single shot acquisition. In addition, neutron generation was demonstrated in situ with the X-ray beam, with a single shot, thus demonstrating the potential for multi-modal criticality testing of waste materials. This feasibility study successfully demonstrated non-destructive radiography of encapsulated, high density, nuclear material. With recent developments of high-power laser systems, to 10Hz operation, a laser-driven multi-modal beamline for waste monitoring applications is envisioned.

  11. CH Packaging Operations Manual

    International Nuclear Information System (INIS)

    This document provides the user with instructions for assembling a payload. All the steps in Subsections 1.2, Preparing 55-Gallon Drum Payload Assembly; 1.3, Preparing 'Short' 85-Gallon Drum Payload Assembly (TRUPACT-II and HalfPACT); 1.4, Preparing 'Tall' 85-gallon Drum Payload Assembly (HalfPACT only); 1.5, Preparing 100-Gallon Drum Payload Assembly; 1.6, Preparing SWB Payload Assembly; and 1.7, Preparing TDOP Payload Assembly, must be completed, but may be performed in any order as long as radiological control steps are not bypassed. Transport trailer operations, package loading and unloading from transport trailers, hoisting and rigging activities such as ACGLF operations, equipment checkout and shutdown, and component inspection activities must be performed, but may be performed in any order and in parallel with other activities as long as radiological control steps are not bypassed. Steps involving OCA/ICV lid removal/installation and payload removal/loading may be performed in parallel if there are multiple operators working on the same packaging. Steps involving removal/installation of OCV/ICV upper and lower main O-rings must be performed in sequence.

  12. CH Packaging Operations Manual

    International Nuclear Information System (INIS)

    This document provides the user with instructions for assembling a payload. All the steps in Subsections 1.2, Preparing 55-Gallon Drum Payload Assembly; 1.3, Preparing 'Short' 85-Gallon Drum Payload Assembly (TRUPACT-II and HalfPACT); 1.4, Preparing 'Tall' 85-Gallon Drum Payload Assembly (HalfPACT only); 1.5, Preparing 100-Gallon Drum Payload Assembly; 1.6, Preparing Shielded Container Payload Assembly; 1.7, Preparing SWB Payload Assembly; and 1.8, Preparing TDOP Payload Assembly, must be completed, but may be performed in any order as long as radiological control steps are not bypassed. Transport trailer operations, package loading and unloading from transport trailers, hoisting and rigging activities such as ACGLF operations, equipment checkout and shutdown, and component inspection activities must be performed, but may be performed in any order and in parallel with other activities as long as radiological control steps are not bypassed. Steps involving OCA/ICV lid removal/installation and payload removal/loading may be performed in parallel if there are multiple operators working on the same packaging. Steps involving removal/installation of OCV/ICV upper and lower main O-rings must be performed in sequence, except as noted.

  13. Japan's electronic packaging technologies

    Science.gov (United States)

    Tummala, Rao R.; Pecht, Michael

    1995-01-01

    The JTEC panel found Japan to have significant leadership over the United States in the strategic area of electronic packaging. Many technologies and products once considered the 'heart and soul' of U.S. industry have been lost over the past decades to Japan and other Asian countries. The loss of consumer electronics technologies and products is the most notable of these losses, because electronics is the United States' largest employment sector and is critical for growth businesses in consumer products, computers, automobiles, aerospace, and telecommunications. In the past there was a distinction between consumer and industrial product technologies. While Japan concentrated on the consumer market, the United States dominated the industrial sector. No such distinction is anticipated in the future; the consumer-oriented technologies Japan has dominated are expected to characterize both domains. The future of U.S. competitiveness will, therefore, depend on the ability of the United States to rebuild its technological capabilities in the area of portable electronic packaging.

  14. Tamper indicating packaging

    International Nuclear Information System (INIS)

    Protecting sensitive items from undetected tampering in an unattended environment is crucial to the success of non-proliferation efforts relying on the verification of critical activities. Tamper Indicating Packaging (TIP) technologies are applied to containers, packages, and equipment that require an indication of a tamper attempt. Examples include: the transportation and storage of nuclear material, the operation and shipment of surveillance equipment and monitoring sensors, and the retail storage of medicine and food products. The spectrum of adversarial tampering ranges from attempted concealment of a pin-hole sized penetration to the complete container replacement, which would involve counterfeiting efforts of various degrees. Sandia National Laboratories (SNL) has developed a technology base for advanced TIP materials, sensors, designs, and processes which can be adapted to various future monitoring systems. The purpose of this technology base is to investigate potential new technologies, and to perform basic research of advanced technologies. This paper will describe the theory of TIP technologies and recent investigations of TIP technologies at SNL

  15. Polylactide nanocomposites for packaging materials: A review

    Science.gov (United States)

    Widiastuti, Indah

    2016-02-01

    This review aims at highlighting on an attempt for improving the properties of polylactide (PLA) as packaging material by application of nanocomposite technology. PLA is attracting considerable interest because of more eco-friendliness from its origin as contrast to the petrochemical-based polymers and its biodegradability. Despite possessing good mechanical and optical properties, deterioration of the material properties in PLA materials during their service time could occur after prolonged exposure to humidity and high temperature condition. Limited gas barrier is another drawback of PLA material that should be overcome to satisfy the requirement for packaging application. To further extend the range of mechanical and thermal properties achievable, several attempts have been made in modifying the material such as blending with other polymers, use of plasticizing material and development of PLA nanocomposites. Nanocomposite is a fairly new type of composite that has emerged in which the reinforcing filler has nanometer scale dimensions (at least one dimension of the filler is less than 100 nm). In this review, the critical properties of PLA as packaging materials and its degradation mechanism are presented. This paper discusses the current effort and key research challenges in the development of nanocomposites based on biodegradable polymer matrices and nano-fillers. The PLA layered silicate nanocomposites where the filler platelets can be dispersed in the polymer at the nanometer scale owing to the specific filler surface modification, frequently exhibits remarkable improvements of mechanical strength, gas barrier and thermal stability.

  16. The design, construction and testing of packaging

    International Nuclear Information System (INIS)

    Essentially uniform regulations, based on the IAEA Regulations for the Safe Transport of Radioactive Materials, have been adopted on a world-wide basis with the aim of ensuring safety in the transport of radioactive and fissile substances by road, rail, sea and air. The application of these regulations over a period of almost 20 years has resulted in practically complete safety in the sense that there has been no evidence of death or injury that could be attributed to the special properties of the material even when consignments were involved in serious accidents. In the regulations, reliance is placed, to the greatest extent possible, on the packaging to provide adequate shielding and containment of the contents under both normal transport and accident conditions. The Agency organized an international seminar in 1971 to consider the performance tests that have to be applied to packaging to demonstrate compliance with the regulatory requirements. The general conclusion was that the testing programme specified in the regulations was adequate for the near future, but that further consideration should be given to assessing the risks presented by the increasing volume of transport. The second international seminar, which is the subject of this report, dealt with all aspects of the design, construction and testing of packaging for the transport both of relatively small quantities of radioactive substances, which are being used to an ever increasing extent for medical and research purposes, and of the much larger quantities arising in various stages of the nuclear fuel cycle. The programme covered the general requirements for packaging; risk assessment for the transport of various radioactive and fissile substances, including plutonium; specific features of the design and construction of packaging; quality assurance; damage simulation tests, including calculational methods and scale-model testing; tests for the retention of shielding and containment after damage; and the

  17. Creating R Packages: A Tutorial

    OpenAIRE

    Leisch, Friedrich

    2008-01-01

    This tutorial gives a practical introduction to creating R packages. We discuss how object oriented programming and S formulas can be used to give R code the usual look and feel, how to start a package from a collection of R functions, and how to test the code once the package has been created. As running example we use functions for standard linear regression analysis which are developed from scratch.

  18. IN-PACKAGE CHEMISTRY ABSTRACTION

    International Nuclear Information System (INIS)

    This report was developed in accordance with the requirements in ''Technical Work Plan for Postclosure Waste Form Modeling'' (BSC 2005 [DIRS 173246]). The purpose of the in-package chemistry model is to predict the bulk chemistry inside of a breached waste package and to provide simplified expressions of that chemistry as a function of time after breach to Total Systems Performance Assessment for the License Application (TSPA-LA). The scope of this report is to describe the development and validation of the in-package chemistry model. The in-package model is a combination of two models, a batch reactor model, which uses the EQ3/6 geochemistry-modeling tool, and a surface complexation model, which is applied to the results of the batch reactor model. The batch reactor model considers chemical interactions of water with the waste package materials, and the waste form for commercial spent nuclear fuel (CSNF) waste packages and codisposed (CDSP) waste packages containing high-level waste glass (HLWG) and DOE spent fuel. The surface complexation model includes the impact of fluid-surface interactions (i.e., surface complexation) on the resulting fluid composition. The model examines two types of water influx: (1) the condensation of water vapor diffusing into the waste package, and (2) seepage water entering the waste package as a liquid from the drift. (1) Vapor-Influx Case: The condensation of vapor onto the waste package internals is simulated as pure H2O and enters at a rate determined by the water vapor pressure for representative temperature and relative humidity conditions. (2) Liquid-Influx Case: The water entering a waste package from the drift is simulated as typical groundwater and enters at a rate determined by the amount of seepage available to flow through openings in a breached waste package

  19. IN-PACKAGE CHEMISTRY ABSTRACTION

    Energy Technology Data Exchange (ETDEWEB)

    E. Thomas

    2005-07-14

    This report was developed in accordance with the requirements in ''Technical Work Plan for Postclosure Waste Form Modeling'' (BSC 2005 [DIRS 173246]). The purpose of the in-package chemistry model is to predict the bulk chemistry inside of a breached waste package and to provide simplified expressions of that chemistry as a function of time after breach to Total Systems Performance Assessment for the License Application (TSPA-LA). The scope of this report is to describe the development and validation of the in-package chemistry model. The in-package model is a combination of two models, a batch reactor model, which uses the EQ3/6 geochemistry-modeling tool, and a surface complexation model, which is applied to the results of the batch reactor model. The batch reactor model considers chemical interactions of water with the waste package materials, and the waste form for commercial spent nuclear fuel (CSNF) waste packages and codisposed (CDSP) waste packages containing high-level waste glass (HLWG) and DOE spent fuel. The surface complexation model includes the impact of fluid-surface interactions (i.e., surface complexation) on the resulting fluid composition. The model examines two types of water influx: (1) the condensation of water vapor diffusing into the waste package, and (2) seepage water entering the waste package as a liquid from the drift. (1) Vapor-Influx Case: The condensation of vapor onto the waste package internals is simulated as pure H{sub 2}O and enters at a rate determined by the water vapor pressure for representative temperature and relative humidity conditions. (2) Liquid-Influx Case: The water entering a waste package from the drift is simulated as typical groundwater and enters at a rate determined by the amount of seepage available to flow through openings in a breached waste package.

  20. K east encapsulation packager modifications

    International Nuclear Information System (INIS)

    This Supporting Document analyzes a proposal for reducing the under-packager volume to decrease the amount of fissile material that could accumulate there. The analysis shows that restricting the under packager volume to no more than 4080 in3 will assure that if accumulated fissile material beneath the packager is added to the worst-case mass of fissile material in the discharge chute, a keff of 0.98 will not be exceeded

  1. Laser Sealed Packaging for Microsystems

    OpenAIRE

    Seigneur, Frank; JACOT, Jacques

    2006-01-01

    Packaging is the last process of microsystem manufacturing. There are mainly two kinds of packages: plastic or metallic. The two main components of the package (base and cover) may either be glued or soldered. Each of these techniques has its advantages and drawbacks, and the choice should be driven by the functionality of the microsystem. The advantage of gluing is that it is quite an easy production process. The drawback is that glue, like all polymers, is not hermetic on the long te...

  2. Design and fabrication of a foldable 3D silicon based package for solid state lighting applications

    International Nuclear Information System (INIS)

    Miniaturization of solid state lighting (SSL) luminaires as well as reduction of packaging and assembly costs are of prime interest for the SSL lighting industry. A novel silicon based LED package for lighting applications is presented in this paper. The proposed design consists of 5 rigid Si tiles connected by flexible polyimide hinges with embedded interconnects (ICs). Electrical, optical and thermal characteristics were taken into consideration during design. The fabrication process involved polyimide (PI) application and patterning, aluminium interconnect integration in the flexible hinge, LED reflector cavity formation and metalization followed by through wafer DRIE etching for chip formation and release. A method to connect chip front to backside without TSVs was also integrated into the process. Post-fabrication wafer level assembly included LED mounting and wirebond, phosphor-based colour conversion and silicone encapsulation. The package formation was finalized by vacuum assisted wrapping around an assembly structure to form a 3D geometry, which is beneficial for omnidirectional lighting. Bending tests were performed on the flexible ICs and optical performance at different temperatures was evaluated. It is suggested that 3D packages can be expanded to platforms for miniaturized luminaire applications by combining monolithic silicon integration and system-in-package (SiP) technologies. (paper)

  3. Heat Transfer Characteristics in High Power LED Packaging

    Directory of Open Access Journals (Sweden)

    Chi-Hung Chung

    2014-03-01

    Full Text Available This study uses the T3Ster transient thermal resistance measuring device to investigate the effects to heat transfer performances from different LED crystal grains, packaging methods and heat-sink substrates through the experimental method. The experimental parameters are six different types of LED modules that are made alternatively with the crystal grain structure, the die attach method and the carrying substrate. The crystal grain structure includes the lateral type, flip chip type and vertical type. The die attach method includes silver paste and the eutectic structure. The carrying substrates are aluminum oxide (Alumina and aluminum nitride (AIN ceramic substrates and metal core PCB (MCPCB. The experimental results show that, under the conditions of the same crystal grain and die attach method, the thermal resistance values for the AIN substrate and the Alumina substrate are 2.1K/W and 5.1K/W, respectively and the total thermal resistance values are 7.3K/W and 10.8K/W. Compared to the Alumina substrate, the AIN substrate can effectively lower the total thermal resistance value by 32.4%. This is because the heat transfer coefficient of the AIN substrate is higher than that of the Alumina substrate, thus effectively increasing its thermal conductivity. In addition, under the conditions of the same crystal grain and the same substrate, the packaging methods are using silver paste and the eutectic structure for die attach. Their thermal resistance values are 5.7K/W and 2.7K/W, respectively, with a variance of 3K/W. Comparisons of the crystal grain structure show that the thermal resistance for the flip chip type is lower than that of the traditional lateral type by 0.9K/W. This is because the light emitting layer of the flip chip crystal grain is closer to the heat-sink substrate, shortening the heat dissipation route, and thus lowering the thermal resistance value. For the total thermal resistance, the crystal grain structure has a lesser

  4. Flock on a chip

    Science.gov (United States)

    Bartolo, Denis; Desreumaux, Nicolas

    2015-11-01

    We will show how to motorize colloidal particles capable of sensing the orientation of their neighbors and how to handle them in microfluidic chips. These populations of colloidal rollers display non-equilibrium transitions toward swarming or swirling motion depending on the system geometry . After characterizing these emergent patterns we will quantitatively describe them by means of an hydrodynamic theory of polar active liquids.

  5. Praktijkonderzoek naar chip's

    NARCIS (Netherlands)

    Huiskes, J.H.

    1989-01-01

    Momenteel wordt door onderzoek en bedrijfsleven hard gewerkt aan de ontwikkeling van een injecteerbaar electronische transponder voor varkens. Deze transponder, in de wandeling chip genoemd bevat het levensnummer van het varken. Het levensnummer gaat het hele leven van het varken mee.

  6. Fish and chips

    OpenAIRE

    Delvenne, Philippe; Deprez, Manuel; Bisig, Bettina; JAMAR, Mauricette; Boniver, Jacques; Bours, Vincent; Herens, Christian

    2010-01-01

    Academic hospital laboratories should offer patients the possibility to have the most accurate diagnosis by the development of new analyses, such as molecular biology tests including FISH (Fluorescent In Situ Hybridization) and chips (microarrays,...). The purpose of this article is to describe the principles and the potential applications of these techniques.

  7. Invisibility Cloak Printed on a Photonic Chip.

    Science.gov (United States)

    Feng, Zhen; Wu, Bing-Hong; Zhao, Yu-Xi; Gao, Jun; Qiao, Lu-Feng; Yang, Ai-Lin; Lin, Xiao-Feng; Jin, Xian-Min

    2016-01-01

    Invisibility cloak capable of hiding an object can be achieved by properly manipulating electromagnetic field. Such a remarkable ability has been shown in transformation and ray optics. Alternatively, it may be realistic to create a spatial cloak by means of confining electromagnetic field in three-dimensional arrayed waveguides and introducing appropriate collective curvature surrounding an object. We realize the artificial structure in borosilicate by femtosecond laser direct writing, where we prototype up to 5,000 waveguides to conceal millimeter-scale volume. We characterize the performance of the cloak by normalized cross correlation, tomography analysis and continuous three-dimensional viewing angle scan. Our results show invisibility cloak can be achieved in waveguide optics. Furthermore, directly printed invisibility cloak on a photonic chip may enable controllable study and novel applications in classical and quantum integrated photonics, such as invisualising a coupling or swapping operation with on-chip circuits of their own. PMID:27329510

  8. Invisibility Cloak Printed on a Photonic Chip

    Science.gov (United States)

    Feng, Zhen; Wu, Bing-Hong; Zhao, Yu-Xi; Gao, Jun; Qiao, Lu-Feng; Yang, Ai-Lin; Lin, Xiao-Feng; Jin, Xian-Min

    2016-01-01

    Invisibility cloak capable of hiding an object can be achieved by properly manipulating electromagnetic field. Such a remarkable ability has been shown in transformation and ray optics. Alternatively, it may be realistic to create a spatial cloak by means of confining electromagnetic field in three-dimensional arrayed waveguides and introducing appropriate collective curvature surrounding an object. We realize the artificial structure in borosilicate by femtosecond laser direct writing, where we prototype up to 5,000 waveguides to conceal millimeter-scale volume. We characterize the performance of the cloak by normalized cross correlation, tomography analysis and continuous three-dimensional viewing angle scan. Our results show invisibility cloak can be achieved in waveguide optics. Furthermore, directly printed invisibility cloak on a photonic chip may enable controllable study and novel applications in classical and quantum integrated photonics, such as invisualising a coupling or swapping operation with on-chip circuits of their own. PMID:27329510

  9. Wafer level vacuum packaging of scanning micro-mirrors using glass-frit and anodic bonding methods

    Science.gov (United States)

    Langa, S.; Drabe, C.; Kunath, C.; Dreyhaupt, A.; Schenk, H.

    2013-03-01

    In this paper the authors report about the six inch wafer level vacuum packaging of electro-statically driven two dimensional micro-mirrors. The packaging was done by means of two types of wafer bonding methods: anodic and glass frit. The resulting chips after dicing are 4 mm wide, 6 mm long and 1.6 mm high and the residual pressure inside the package after dicing was estimated to be between 2 and 20 mbar. This allowed us to reduce the driving voltage of the micro-mirrors by more than 40% compared to the driving voltage without vacuum packaging. The vacuum stability after 5 months was verified by measurement using the so called "membrane method". Persistence of the vacuum was proven. No getter materials were used for packaging.

  10. Integration of optoelectronic technologies for chip-to- chip interconnections and parallel pipeline processing

    Science.gov (United States)

    Wu, Jenming

    Digital information services such as multimedia systems and data communications require the processing and transfer of tremendous amount of data. These data need to be stored, accessed and delivered efficiently and reliably at high speed for various user applications. This represents a great challenge for current electronic systems. Electronics is effective in providing high performance processing and computation, but its input/outputs (I/Os) bandwidth is unable to scale with its processing power. The signal I/Os or interconnections are needed between processors and input devices, between processors for multiprocessor systems, and between processors and storage devices. Novel chip-to-chip interconnect technologies are needed to meet this challenge. This work integrates optoelectronic technologies for chip-to-chip interconnects and parallel pipeline processing. Photonic and electronic technologies are complementary to each other in the sense that electronics is more suitable for high-speed, low cost computation, and photonics is more suitable for high-bandwidth information transmission. Smart pixel technology uses electronics for logic switching and optics for chip-to- chip interconnects, thus combining the abilities of photonics and electronics nicely. This work describes both vertical and horizontal integration of smart pixel technologies for chip-to-chip optical interconnects and its applications. We present smart pixel VLSI designs in both hybrid CMOS/MQW smart pixel and monolithic GaAs smart pixel technologies. We use the CMOS/MQW technology for smart pixel array cellular logic (SPARCL) processors for SIMD parallel pipeline processing. We have tested the chip and constructed a prototype system for device characterization and system demonstration. We have verified the functionality of the system and characterized the electrical functions of the chip and the optoelectronic properties of the MQW devices. We have developed algorithms that utilize SPARCL for various

  11. Electronic equipment packaging technology

    CERN Document Server

    Ginsberg, Gerald L

    1992-01-01

    The last twenty years have seen major advances in the electronics industry. Perhaps the most significant aspect of these advances has been the significant role that electronic equipment plays in almost all product markets. Even though electronic equipment is used in a broad base of applications, many future applications have yet to be conceived. This versatility of electron­ ics has been brought about primarily by the significant advances that have been made in integrated circuit technology. The electronic product user is rarely aware of the integrated circuits within the equipment. However, the user is often very aware of the size, weight, mod­ ularity, maintainability, aesthetics, and human interface features of the product. In fact, these are aspects of the products that often are instrumental in deter­ mining its success or failure in the marketplace. Optimizing these and other product features is the primary role of Electronic Equipment Packaging Technology. As the electronics industry continues to pr...

  12. Geometry methods and packages

    International Nuclear Information System (INIS)

    The authors address the problem of following the trajectory of a particle in simulations. It is necessary to follow the motion of the particle, and to determine its intersection with different geometric surfaces in the problem, in order to relate the stepping of the particle trajectory into real motion through the physical problem at hand. The distance a particle moves before encountering a surface is needed to compare with the actual transport distance that is about to be used in the simulation. Basic mathematical expressions are developed for the intersections of particle trajectories with plane and conic surfaces. The authors show how these are used in the EGS4 code system, which should be typical of the general problem. They also review geometry packages currently being used in electron-photon Monte Carlo programs

  13. Design, fabrication, and packaging of an integrated, wirelessly-powered optrode array for optogenetics application

    OpenAIRE

    Kwon, Ki Yong; Lee, Hyung-Min; Ghovanloo, Maysam; Weber, Arthur; Li, Wen

    2015-01-01

    The recent development of optogenetics has created an increased demand for advancing engineering tools for optical modulation of neural circuitry. This paper details the design, fabrication, integration, and packaging procedures of a wirelessly-powered, light emitting diode (LED) coupled optrode neural interface for optogenetic studies. The LED-coupled optrode array employs microscale LED (μLED) chips and polymer-based microwaveguides to deliver light into multi-level cortical networks, coupl...

  14. Modeling Light-Extraction Characteristics of Packaged Light-Emitting Diodes

    OpenAIRE

    D. Z.-Y. Ting; McGill, T. C.

    1998-01-01

    We employ a Monte Carlo ray-tracing technique to model light-extraction characteristics of light-emitting diodes. By relaxing restrictive assumptions on photon traversal history, our method improves upon available analytical models for estimating light-extraction efficiencies from bare LED chips, and enhances modeling capabilities by realistically treating the various processes which photons can encounter in a packaged LED. Our method is not only capable of calculating extraction efficiencies...

  15. Dental Care for Medicaid and CHIP Enrollees

    Science.gov (United States)

    ... Amendments Dental Care Dental Care for Medicaid and CHIP Enrollees Dental health is an important part of ... for dental services. Dental Benefits for Children in CHIP States that provide CHIP coverage to children through ...

  16. Chemical Energy: A Learning Package.

    Science.gov (United States)

    Cohen, Ita; Ben-Zvi, Ruth

    1982-01-01

    A comprehensive teaching/learning chemical energy package was developed to overcome conceptual/experimental difficulties and time required for calculation of enthalpy changes. The package consists of five types of activities occuring in repeated cycles: group activities, laboratory experiments, inquiry questionnaires, teacher-led class…

  17. Oral Hygiene. Learning Activity Package.

    Science.gov (United States)

    Hime, Kirsten

    This learning activity package on oral hygiene is one of a series of 12 titles developed for use in health occupations education programs. Materials in the package include objectives, a list of materials needed, a list of definitions, information sheets, reviews (self evaluations) of portions of the content, and answers to reviews. These topics…

  18. Packaging Software Assets for Reuse

    Science.gov (United States)

    Mattmann, C. A.; Marshall, J. J.; Downs, R. R.

    2010-12-01

    The reuse of existing software assets such as code, architecture, libraries, and modules in current software and systems development projects can provide many benefits, including reduced costs, in time and effort, and increased reliability. Many reusable assets are currently available in various online catalogs and repositories, usually broken down by disciplines such as programming language (Ibiblio for Maven/Java developers, PyPI for Python developers, CPAN for Perl developers, etc.). The way these assets are packaged for distribution can play a role in their reuse - an asset that is packaged simply and logically is typically easier to understand, install, and use, thereby increasing its reusability. A well-packaged asset has advantages in being more reusable and thus more likely to provide benefits through its reuse. This presentation will discuss various aspects of software asset packaging and how they can affect the reusability of the assets. The characteristics of well-packaged software will be described. A software packaging domain model will be introduced, and some existing packaging approaches examined. An example case study of a Reuse Enablement System (RES), currently being created by near-term Earth science decadal survey missions, will provide information about the use of the domain model. Awareness of these factors will help software developers package their reusable assets so that they can provide the most benefits for software reuse.

  19. Gentoo package dependencies over time

    NARCIS (Netherlands)

    Bloemen, Remco; Amrit, Chintan; Kuhlmann, Stefan; Ordonez-Matamoros, Gonzalo

    2014-01-01

    Open source distributions such as Gentoo need to accurately track dependency relations between software packages in order to install working systems. To do this, Gentoo has a carefully authored database containing those relations. In this paper, we extract the Gentoo package dependency graph and its

  20. 19 CFR 191.13 - Packaging materials.

    Science.gov (United States)

    2010-04-01

    ... 19 Customs Duties 2 2010-04-01 2010-04-01 false Packaging materials. 191.13 Section 191.13 Customs... (CONTINUED) DRAWBACK General Provisions § 191.13 Packaging materials. (a) Imported packaging material... packaging material when used to package or repackage merchandise or articles exported or destroyed...

  1. 49 CFR 173.411 - Industrial packagings.

    Science.gov (United States)

    2010-10-01

    ... 49 Transportation 2 2010-10-01 2010-10-01 false Industrial packagings. 173.411 Section 173.411... SHIPMENTS AND PACKAGINGS Class 7 (Radioactive) Materials § 173.411 Industrial packagings. (a) General. Each industrial packaging must comply with the requirements of this section which specifies packaging tests,...

  2. System-in-package LTCC platform for 3D RF to millimeter wave

    Science.gov (United States)

    Vähä-Heikkilä, T.; Lahti, M.

    2011-04-01

    This presentation shows recent trends and results in 3D Low Temperature Co-Fired Ceramics (LTCC) modules in applications from RF to millimeter waves. The system-in-package LTCC platform is a true three dimensional module technology. LTCC is a lightweight multi-layer technology having typically 6-20 ceramic layers and metallizations between. The metallization levels i.e different metal layers can be patterned and connected together with metal vias. Passive devices can also be fabricated on LTCC while active devices and other chips are connected with flip-chip, wire bonding or soldering. In addition to passives directly fabricated to LTCC, several different technologies/ chips can be hybrid integrated to the same module. LTCC platform is also well suited for the realization of antenna arrays for microwave and millimeter wave applications. Potential applications are ranging from short range communications to space and radars. VTT has designed, fabricated and characterized microwave and millimeter wave packages for Radio Frequency (RF) Micro Electro Mechanical Systems (MEMS) as well as active devices. Also, several types of system-in-package modules have been realized containing hybrid integrated CMOS and GaAs MMICs and antenna arrays.

  3. Designing a WISHBONE Protocol Network Adapter for an Asynchronous Network-on-Chip

    OpenAIRE

    Soliman, Ahmed H. M.; E. M.Saad; M El Bably; Keshk, Hesham M. A. M.

    2012-01-01

    The Scaling of microchip technologies, from micron to submicron and now to deep sub-micron (DSM) range, has enabled large scale systems-on-chip (SoC). In future deep submicron (DSM) designs, the interconnect effect will definitely dominate performance. Network-on-Chip (NoC) has become a promising solution to bus-based communication infrastructure limitations. NoC designs usually targets Application Specific Integrated Circuits (ASICs), however, the fabrication process costs a lot. Implementin...

  4. 78 FR 19007 - Certain Products Having Laminated Packaging, Laminated Packaging, and Components Thereof...

    Science.gov (United States)

    2013-03-28

    ... COMMISSION Certain Products Having Laminated Packaging, Laminated Packaging, and Components Thereof... importation of certain products having laminated packaging, laminated packaging, and components thereof by... Investigation: Having considered the complaint, the U.S. International Trade Commission, on March 22,...

  5. Silicon integrated nanophotonics for on-chip interconnects

    Science.gov (United States)

    Vlasov, Yurii

    2008-03-01

    Current trend in microelectronics industry is to increase the parallelism in computation by multi-threading, by building large scale multi-chip systems and, more recently, by increasing the number of cores on a single chip. With such increase of parallelization the interconnect bandwidth between the racks, chips or different cores is becoming a limiting factor for the design of high performance computer systems. The on-chip ultrahigh-bandwidth silicon-based photonic network might provide an attractive solution to this bandwidth bottleneck. We will review recent results on silicon nanophotonic circuits based on photonic wires and photonic crystals. Strong light confinement at the diffraction limit enables dramatic scaling of the device area and allows unprecedented control over optical signals. Silicon nanophotonic devices have immense capacity for low-loss, high-bandwidth data processing that might enable the design of ultra-compact on-chip optical networks. In particular we will show recent results on design and characterization of various ultra-compact (circuits as optical delay lines, electro-optic modulators, broadband optical switches, wavelength filters, etc.

  6. Wood chips procurement and research project at the Mikkeli region; Puuhakkeen hankinta- ja tutkimusprojekti Mikkelin seudulla

    Energy Technology Data Exchange (ETDEWEB)

    Saksa, T. [Finnish Forest Research Inst., Suonenjoki (Finland). Suonenjoki Research Station; Auvinen, P. [Mikkeli city (Finland). Dept. of Agriculture and Forestry

    1996-12-31

    In 1993-94, a large-scale energywood production chain started as a co-operation project by the Mikkeli city forest office and local forestry societies. In 1995 over 115 000 m{sup 3} (about 85 000 MWh of energy) of wood chips were delivered to Pursiala heat and power plant in Mikkeli. About 75 % of these chips was forest processed chips. About 70 % of the forest processed chips was whole tree chips from improvement cuttings of young forest stands and the rest was logging waste chips from regeneration cutting areas. The average total delivery costs of forest processed chips after reduction of energywood and other subsidies were approximately 45 FIM/m{sup 3} (60 FIM/MWh) for the whole tree chips and 38 FIM/m{sup 3} (50 FIM/MWh) for logging waste chips. The delivery costs of forest processed chips could meet the target of Bioenergy Research Programme (45 FIM/MWh) only in the most favourable cases. In an average the delivery costs were about 9 FIM/MWh more than the price obtained when sold to the heat and power plant. However the wood chip production created 27 new jobs and the increase of income to the local economy was about 2.2 milj. FIM /year. The local communities got new tax revenue about 3 FIM/MWh. The gain for the forestry was approximated to be 5 - 6 FIM/MWh. The resources of forest processed chips were studied on the basis of stand measurements. According to the study the most remarkable energywood resources were in young thinning stands on Oxalis-Myrtillus and Myrtillus forest site types. On Oxalis-Myrtillus type almost every and on Myrtillus type every second stand included energywood more than 40 m{sup 3}/ha

  7. CDIAC catalog of numeric data packages and computer model packages

    International Nuclear Information System (INIS)

    The Carbon Dioxide Information Analysis Center acquires, quality-assures, and distributes to the scientific community numeric data packages (NDPs) and computer model packages (CMPs) dealing with topics related to atmospheric trace-gas concentrations and global climate change. These packages include data on historic and present atmospheric CO2 and CH4 concentrations, historic and present oceanic CO2 concentrations, historic weather and climate around the world, sea-level rise, storm occurrences, volcanic dust in the atmosphere, sources of atmospheric CO2, plants' response to elevated CO2 levels, sunspot occurrences, and many other indicators of, contributors to, or components of climate change. This catalog describes the packages presently offered by CDIAC, reviews the processes used by CDIAC to assure the quality of the data contained in these packages, notes the media on which each package is available, describes the documentation that accompanies each package, and provides ordering information. Numeric data are available in the printed NDPs and CMPs, in CD-ROM format, and from an anonymous FTP area via Internet. All CDIAC information products are available at no cost

  8. CMOS capacitive sensors for lab-on-chip applications a multidisciplinary approach

    CERN Document Server

    Ghafar-Zadeh, Ebrahim

    2010-01-01

    The main components of CMOS capacitive biosensors including sensing electrodes, bio-functionalized sensing layer, interface circuitries and microfluidic packaging are verbosely explained in chapters 2-6 after a brief introduction on CMOS based LoCs in Chapter 1. CMOS Capacitive Sensors for Lab-on-Chip Applications is written in a simple pedagogical way. It emphasises practical aspects of fully integrated CMOS biosensors rather than mathematical calculations and theoretical details. By using CMOS Capacitive Sensors for Lab-on-Chip Applications, the reader will have circuit design methodologies,

  9. Test Planning and Test Access Mechanism Design for Stacked Chips using ILP

    OpenAIRE

    Sengupta, Breeta; Larsson, Erik

    2014-01-01

    In this paper we propose a scheme for test planning and test access mechanism (TAM) design for stacked integrated circuits (SICs) that are designed in a core-based manner. Our scheme minimizes the test cost, which is given as the weighted sum of the test time and the TAM width. The test cost is evaluated for a test flow that consists of a wafer sort test of each individual chip and a package test of the complete stack of chips. We use an Integer Linear Programming (ILP) model to find the opti...

  10. Ultra-thin silicon (UTSi) on insulator CMOS transceiver and time-division multiplexed switch chips for smart pixel integration

    Science.gov (United States)

    Zhang, Liping; Sawchuk, Alexander A.

    2001-12-01

    We describe the design, fabrication and functionality of two different 0.5 micron CMOS optoelectronic integrated circuit (OEIC) chips based on the Peregrine Semiconductor Ultra-Thin Silicon on insulator technology. The Peregrine UTSi silicon- on-sapphire (SOS) technology is a member of the silicon-on- insulator (SOI) family. The low-loss synthetic sapphire substrate is optically transparent and has good thermal conductivity and coefficient of thermal expansion properties, which meet the requirements for flip-chip bonding of VCSELs and other optoelectronic input-output components. One chip contains transceiver and network components, including four channel high-speed CMOS transceiver modules, pseudo-random bit stream (PRBS) generators, a voltage controlled oscillator (VCO) and other test circuits. The transceiver chips can operate in both self-testing mode and networking mode. An on- chip clock and true-single-phase-clock (TSPC) D-flip-flop have been designed to generate a PRBS at over 2.5 Gb/s for the high-speed transceiver arrays to operate in self-testing mode. In the networking mode, an even number of transceiver chips forms a ring network through free-space or fiber ribbon interconnections. The second chip contains four channel optical time-division multiplex (TDM) switches, optical transceiver arrays, an active pixel detector and additional test devices. The eventual applications of these chips will require monolithic OEICs with integrated optical input and output. After fabrication and testing, the CMOS transceiver array dies will be packaged with 850 nm vertical cavity surface emitting lasers (VCSELs), and metal-semiconductor- metal (MSM) or GaAs p-i-n detector die arrays to achieve high- speed optical interconnections. The hybrid technique could be either wire bonding or flip-chip bonding of the CMOS SOS smart-pixel arrays with arrays of VCSELs and photodetectors onto an optoelectronic chip carrier as a multi-chip module (MCM).

  11. In-Package Chemistry Abstraction

    International Nuclear Information System (INIS)

    This report was developed in accordance with the requirements in ''Technical Work Plan for: Regulatory Integration Modeling and Analysis of the Waste Form and Waste Package'' (BSC 2004 [DIRS 171583]). The purpose of the in-package chemistry model is to predict the bulk chemistry inside of a breached waste package and to provide simplified expressions of that chemistry as function of time after breach to Total Systems Performance Assessment for the License Application (TSPA-LA). The scope of this report is to describe the development and validation of the in-package chemistry model. The in-package model is a combination of two models, a batch reactor model that uses the EQ3/6 geochemistry-modeling tool, and a surface complexation model that is applied to the results of the batch reactor model. The batch reactor model considers chemical interactions of water with the waste package materials and the waste form for commercial spent nuclear fuel (CSNF) waste packages and codisposed waste packages that contain both high-level waste glass (HLWG) and DOE spent fuel. The surface complexation model includes the impact of fluid-surface interactions (i.e., surface complexation) on the resulting fluid composition. The model examines two types of water influx: (1) the condensation of water vapor that diffuses into the waste package, and (2) seepage water that enters the waste package from the drift as a liquid. (1) Vapor Influx Case: The condensation of vapor onto the waste package internals is simulated as pure H2O and enters at a rate determined by the water vapor pressure for representative temperature and relative humidity conditions. (2) Water Influx Case: The water entering a waste package from the drift is simulated as typical groundwater and enters at a rate determined by the amount of seepage available to flow through openings in a breached waste package. TSPA-LA uses the vapor influx case for the nominal scenario for simulations where the waste package has been

  12. In-Package Chemistry Abstraction

    Energy Technology Data Exchange (ETDEWEB)

    E. Thomas

    2004-11-09

    This report was developed in accordance with the requirements in ''Technical Work Plan for: Regulatory Integration Modeling and Analysis of the Waste Form and Waste Package'' (BSC 2004 [DIRS 171583]). The purpose of the in-package chemistry model is to predict the bulk chemistry inside of a breached waste package and to provide simplified expressions of that chemistry as function of time after breach to Total Systems Performance Assessment for the License Application (TSPA-LA). The scope of this report is to describe the development and validation of the in-package chemistry model. The in-package model is a combination of two models, a batch reactor model that uses the EQ3/6 geochemistry-modeling tool, and a surface complexation model that is applied to the results of the batch reactor model. The batch reactor model considers chemical interactions of water with the waste package materials and the waste form for commercial spent nuclear fuel (CSNF) waste packages and codisposed waste packages that contain both high-level waste glass (HLWG) and DOE spent fuel. The surface complexation model includes the impact of fluid-surface interactions (i.e., surface complexation) on the resulting fluid composition. The model examines two types of water influx: (1) the condensation of water vapor that diffuses into the waste package, and (2) seepage water that enters the waste package from the drift as a liquid. (1) Vapor Influx Case: The condensation of vapor onto the waste package internals is simulated as pure H2O and enters at a rate determined by the water vapor pressure for representative temperature and relative humidity conditions. (2) Water Influx Case: The water entering a waste package from the drift is simulated as typical groundwater and enters at a rate determined by the amount of seepage available to flow through openings in a breached waste package. TSPA-LA uses the vapor influx case for the nominal scenario for simulations where the waste

  13. Perfume Packaging, Seduction and Gender

    Directory of Open Access Journals (Sweden)

    Magdalena Petersson McIntyre

    2013-06-01

    Full Text Available This article examines gender and cultural sense-making in relation to perfumes and their packaging. Gendered meanings of seduction, choice, consumption and taste are brought to the fore with the use of go-along interviews with consumers in per-fume stores. Meeting luxury packages in this feminized environment made the interviewed women speak of bottles as objects to fall in love with and they de-scribed packages as the active part in an act of seduction where they were expect-ing packages to persuade them into consumption. The interviewed men on the other hand portrayed themselves as active choice-makers and stressed that they were always in control and not seduced by packaging. However, while their ways of explaining their relationship with packaging on the surface seems to confirm cultural generalizations in relation to gender and seduction, the article argues that letting oneself be seduced is no less active than seducing. Based on a combination of actor network theories and theories of gender performativity the article points to the agency of packaging for constructions of gender and understands the inter-viewees as equally animated by the flows of passion which guide their actions.

  14. Laser Welding in Electronic Packaging

    Science.gov (United States)

    2000-01-01

    The laser has proven its worth in numerous high reliability electronic packaging applications ranging from medical to missile electronics. In particular, the pulsed YAG laser is an extremely flexible and versatile too] capable of hermetically sealing microelectronics packages containing sensitive components without damaging them. This paper presents an overview of details that must be considered for successful use of laser welding when addressing electronic package sealing. These include; metallurgical considerations such as alloy and plating selection, weld joint configuration, design of optics, use of protective gases and control of thermal distortions. The primary limitations on use of laser welding electronic for packaging applications are economic ones. The laser itself is a relatively costly device when compared to competing welding equipment. Further, the cost of consumables and repairs can be significant. These facts have relegated laser welding to use only where it presents a distinct quality or reliability advantages over other techniques of electronic package sealing. Because of the unique noncontact and low heat inputs characteristics of laser welding, it is an ideal candidate for sealing electronic packages containing MEMS devices (microelectromechanical systems). This paper addresses how the unique advantages of the pulsed YAG laser can be used to simplify MEMS packaging and deliver a product of improved quality.

  15. The impact of packaging on product competition

    OpenAIRE

    Maryam Masoumi; Naser Azad

    2012-01-01

    The primary objective of this paper is to detect important factors, which are influencing competitive advantage. The proposed model of this paper uses sampling technique to measure characteristics of society. There are eight independent variables for the proposed study of this paper including packaging endurance, easy distribution, customer promotion through packaging, packaging structure, packaging as silent advertiser, diversity of packaging, clean and healthy packaging and innovation in pa...

  16. Radioactive waste package acceptance criteria

    International Nuclear Information System (INIS)

    Preliminary acceptance criteria have been developed for packages containing nuclear waste which must be stored or disposed of by the US Department of Energy. Acceptance criteria are necessary to ensure that the waste packages are compatible with all elements of the Waste Management System. The acceptance criteria are subject to revision since many of the constraints that will be imposed on the waste packages by the Waste Management System have either not been defined or are being revised. Delineation of the acceptance criteria will provide bases for handling, transporting and disposing of the commercial waste

  17. Bioderadable Polymers in Food Packaging

    Directory of Open Access Journals (Sweden)

    P.A.Pawar

    2013-01-01

    Full Text Available In recent years, there has been a marked increase in the interest in use of biodegradable materials in packaging. The principal function of packaging is protection and preservation of food from external contamination. This function involves retardation of deterioration, extension of shelf life, and maintenance of quality and safety of packaged food. Biodegradable polymers are the one which fulfill all these functions without causing any threat to the environment. The belief is that biodegradable polymer materials will reduce the need for synthetic polymer production (thus reducing pollution at a low cost, thereby producing a positive effect both environmentally and economically.

  18. Parallel distributed free-space optoelectronic computer engine using flat plug-on-top optics package

    Science.gov (United States)

    Berger, Christoph; Ekman, Jeremy T.; Wang, Xiaoqing; Marchand, Philippe J.; Spaanenburg, Henk; Kiamilev, Fouad E.; Esener, Sadik C.

    2000-05-01

    We report about ongoing work on a free-space optical interconnect system, which will demonstrate a Fast Fourier Transformation calculation, distributed among six processor chips. Logically, the processors are arranged in two linear chains, where each element communicates optically with its nearest neighbors. Physically, the setup consists of a large motherboard, several multi-chip carrier modules, which hold the processor/driver chips and the optoelectronic chips (arrays of lasers and detectors), and several plug-on-top optics modules, which provide the optical links between the chip carrier modules. The system design tries to satisfy numerous constraints, such as compact size, potential for mass-production, suitability for large arrays (up to 1024 parallel channels), compatibility with standard electronics fabrication and packaging technology, potential for active misalignment compensation by integration MEMS technology, and suitability for testing different imaging topologies. We present the system architecture together with details of key components and modules, and report on first experiences with prototype modules of the setup.

  19. Lab-on-a-Chip Pathogen Sensors for Food Safety

    Directory of Open Access Journals (Sweden)

    Bumsang Kim

    2012-08-01

    Full Text Available There have been a number of cases of foodborne illness among humans that are caused by pathogens such as Escherichia coli O157:H7, Salmonella typhimurium, etc. The current practices to detect such pathogenic agents are cell culturing, immunoassays, or polymerase chain reactions (PCRs. These methods are essentially laboratory-based methods that are not at all real-time and thus unavailable for early-monitoring of such pathogens. They are also very difficult to implement in the field. Lab-on-a-chip biosensors, however, have a strong potential to be used in the field since they can be miniaturized and automated; they are also potentially fast and very sensitive. These lab-on-a-chip biosensors can detect pathogens in farms, packaging/processing facilities, delivery/distribution systems, and at the consumer level. There are still several issues to be resolved before applying these lab-on-a-chip sensors to field applications, including the pre-treatment of a sample, proper storage of reagents, full integration into a battery-powered system, and demonstration of very high sensitivity, which are addressed in this review article. Several different types of lab-on-a-chip biosensors, including immunoassay- and PCR-based, have been developed and tested for detecting foodborne pathogens. Their assay performance, including detection limit and assay time, are also summarized. Finally, the use of optical fibers or optical waveguide is discussed as a means to improve the portability and sensitivity of lab-on-a-chip pathogen sensors.

  20. Packaging systems for animal origin food

    Directory of Open Access Journals (Sweden)

    2011-03-01

    Full Text Available The main task of food packaging is to protect the product during storage and transport against the action of biological, chemical and mechanical factors. The paper presents packaging systems for food of animal origin. Vacuum and modified atmosphere packagings were characterised together with novel types of packagings, referred to as intelligent packaging and active packaging. The aim of this paper was to present all advantages and disadvantages of packaging used for meat products. Such list enables to choose the optimal type of packaging for given assortment of food and specific conditions of the transport and storing.

  1. VLSI design of 3D display processing chip for binocular stereo displays

    Institute of Scientific and Technical Information of China (English)

    Ge Chenyang; Zheng Nanning

    2010-01-01

    In order to develop the core chip supporting binocular stereo displays for head mounted display(HMD)and glasses-TV,a very large scale integrated(VLSI)design scheme is proposed by using a pipeline architecture for 3D display processing chip(HMD100).Some key techniques including stereo display processing and high precision video scaling based bicubic interpolation,and their hardware implementations which improve the image quality are presented.The proposed HMD100 chip is verified by the field-programmable gate array(FPGA).As one of innovative and high integration SoC chips,HMD100 is designed by a digital and analog mixed circuit.It can support binocular stereo display,has better scaling effect and integration.Hence it is applicable in virtual reality(VR),3D games and other microdisplay domains.

  2. The behaviour of radioactive waste packages under fire accident conditions

    International Nuclear Information System (INIS)

    An experimental study has been made of the behaviour of packaged Intermediate Level Wastes (ILW) subjected to heat. The conditions used represented fire accidents in the transport of the ILW to the repository in shielded transport containers and in the handling of the packages at the repository. The behaviour of four waste materials immobilised in cement and organic resin were studied. Each waste used had features which allowed the results to be applied to a wide range of other waste streams. Samples of these materials have been heated under controlled and well instrumented conditions in furnaces and pool fires. Inactive simulant wastes were used in small and full scale experiments. Fully active waste materials were used in small scale experiments only. Data are presented on the temperature profiles through the packaged ILW and on the release of volatile and particulate materials as a function of time and temperature. (orig.)

  3. 我国大型美术展览艺术品的包装运输与方法研究%Study on Packaging and Transportation of Works of Art for Large-scale Art Exhibitions in China

    Institute of Scientific and Technical Information of China (English)

    孙伟华

    2014-01-01

    In this paper, we pointed out the uniqueness and value of the works of art and that the heavy stress on security in the logistics of the works of art could be substantiated in the links of packaging, transportation and insurance. At the end, we gave advice to the specialized logistics companies in this field.%指出由于艺术品的唯一性和高价值性,艺术品物流必须高度重视安全性,应从包装、运输、保险三个环节来落实。专业的艺术品物流公司,科学的包装运输方法能保障艺术品在展览过程中的装卸、运输、清点、拆包工作的顺利进行,做到万无一失。

  4. New circuit switching techniques in on-chip networks

    OpenAIRE

    Shaoteng, Liu

    2015-01-01

    Network on Chip (NoC) is proposed as a promising technology to address the communication challenges in deep sub-micron era. NoC brings network-based communication into the on-chip environment and tackles the problems like long wire complexities, bandwidth scaling and so on. After more than a decade's evolution and development, there are many NoC architectures and solutions available. Nevertheless, NoCs can be classi_ed into two categories: packet switched NoC and circuit switched NoC. In this...

  5. Antenna-in-package system integrated with meander line antenna based on LTCC technology

    Institute of Scientific and Technical Information of China (English)

    Gang DONG; Wei XIONG; Zhao-yao WU; Yin-tang YANG

    2016-01-01

    We present an antenna-in-package system integrated with a meander line antenna based on low temperature co-fired ceramic (LTCC) technology. The proposed system employs a meander line patch antenna, a packaging layer, and a laminated multi-chip module (MCM) for integration of integrated circuit (IC) bare chips. A microstrip feed line is used to reduce the interaction between patch and package. To decrease electromagnetic coupling, a via hole structure is designed and analyzed. The meander line antenna achieved a bandwidth of 220 MHz with the center frequency at 2.4 GHz, a maximum gain of 2.2 dB, and a radiation efficiency about 90% over its operational frequency. The whole system, with a small size of 20.2 minx6.1 mmx2.6 mm, can be easily realized by a standard LTCC process. This antenna-in-package system integrated with a meander line antenna was fabricated and the experimental results agreed with simulations well.

  6. Antenna-in-package system integrated with meander line antenna based on LTCC technology

    Institute of Scientific and Technical Information of China (English)

    Gang DONG; Wei XIONG; Zhao-yao WU; Yin-tang YANG

    2016-01-01

    We present an antenna-in-package system integrated with a meander line antenna based on low temperature co-fi red ceramic (LTCC) technology. The proposed system employs a meander line patch antenna, a packaging layer, and a laminated multi-chip module (MCM) for integration of integrated circuit (IC) bare chips. A microstrip feed line is used to reduce the interaction between patch and package. To decrease electromagnetic coupling, a via hole structure is designed and analyzed. The meander line antenna achieved a bandwidth of 220 MHz with the center frequency at 2.4 GHz, a maximum gain of 2.2 dB, and a radiation efficiency about 90% over its operational frequency. The whole system, with a small size of 20.2 mm×6.1 mm×2.6 mm, can be easily realized by a standard LTCC process. This antenna-in-package system integrated with a meander line antenna was fabricated and the experimental results agreed with simulations well.

  7. Conceptual waste packaging options for deep borehole disposal

    Energy Technology Data Exchange (ETDEWEB)

    Su, Jiann -Cherng [Sandia National Laboratories (SNL-NM), Albuquerque, NM (United States); Hardin, Ernest L. [Sandia National Laboratories (SNL-NM), Albuquerque, NM (United States)

    2015-07-01

    This report presents four concepts for packaging of radioactive waste for disposal in deep boreholes. Two of these are reference-size packages (11 inch outer diameter) and two are smaller (5 inch) for disposal of Cs/Sr capsules. All four have an assumed length of approximately 18.5 feet, which allows the internal length of the waste volume to be 16.4 feet. However, package length and volume can be scaled by changing the length of the middle, tubular section. The materials proposed for use are low-alloy steels, commonly used in the oil-and-gas industry. Threaded connections between packages, and internal threads used to seal the waste cavity, are common oilfield types. Two types of fill ports are proposed: flask-type and internal-flush. All four package design concepts would withstand hydrostatic pressure of 9,600 psi, with factor safety 2.0. The combined loading condition includes axial tension and compression from the weight of a string or stack of packages in the disposal borehole, either during lower and emplacement of a string, or after stacking of multiple packages emplaced singly. Combined loading also includes bending that may occur during emplacement, particularly for a string of packages threaded together. Flask-type packages would be fabricated and heat-treated, if necessary, before loading waste. The fill port would be narrower than the waste cavity inner diameter, so the flask type is suitable for directly loading bulk granular waste, or loading slim waste canisters (e.g., containing Cs/Sr capsules) that fit through the port. The fill port would be sealed with a tapered, threaded plug, with a welded cover plate (welded after loading). Threaded connections between packages and between packages and a drill string, would be standard drill pipe threads. The internal flush packaging concepts would use semi-flush oilfield tubing, which is internally flush but has a slight external upset at the joints. This type of tubing can be obtained with premium, low

  8. Packaging Challenges and Solutions for Multi-Stack Die Applications%多层芯片应用中的封装挑战和解决方案

    Institute of Scientific and Technical Information of China (English)

    BobChylak; IvyWeiQin

    2003-01-01

    The continuous growth of stacked die packages is resulting from the technology's ability to effectively increase the functionality and capacity of electronic devices within the same footprint as a single chip. The increased utilization of stacked die packages in cell phone and other consumer products drives technologies that enable multiple die stacks within a given package dimension.This paper reviews the technology requirements and challenges for stacked die packages. Foremost among these is meeting package height requirements. For example, a standard package height is 1.2 mm for a single die package. For stacked die packages, two or more die need to fit in the same area. That means every dimension in the package has to decrease, including the die thickness, the mold cap thickness,the bond line thickness and the wire bond loop profile. The technology enablers for stacked die packages include wafer thinning, thin die attachment, low profile wire bonding, bonding to unsupported edges and low sweep molding.This article focuses on stacked die interconnect requirements. Technologies including forward ball bonding, reverse ball bonding and stud bumping for flip chip applications are reviewed, and the advantages and trade-offs are discussed. Developments in ball bonder capabilities to meet the challenges of stacked die packages are presented, such as ultra-low loop shapes, long wire spans and overhang bonding. Packaging design guidelines to maximize productivity and assembly yield are proposed to address the critical design and assembly issues such as maximum die over hang length at different die thickness, wire bond parameter optimization to minimize yield loss due to wire shorts, die crack and other wire bonding defects.

  9. Packaging the product

    International Nuclear Information System (INIS)

    Full text: Traditionally, when the nuclear industry produces a brochure or video programme, the platform of our arguments is reasoned, factual, abstract, far-sighted and convoluted. It is all about things and processes: energy plants, machinery, numbers and percentages. Yet we know that people are interested only in people, in emotions, in reality, and in basic values about next week or next month. And this is probably the biggest incongruity. Our painstaking, in-depth research backed by technical evidence and statistics is no match for the other side's anecdotal speech making. Our perfectly designed graphics cannot compete against those visual cliches that can give instant life to an abstract idea. In the UK, pioneering work for the British Nuclear Forum's, the Nuclear Industry Education Programme (NIEP) breaks through the traditional approach, allowing passion and feeling to stimulate debate. Material about nuclear power produced for young people often promotes knowledge acquisition about particular aspects of the nuclear fuel cycle without conceptual or value change. NIEP materials build on the experience of developing packages that fully meet curriculum objectives, follow educational best practice, and place nuclear power in a real energy context. But they also make a positive contribution to the meaning a young person attaches to a concept such as radiation. Essentially, the materials are in tune with the way young people make sense of their experience of the real world and the issues in it. For further information about AEA Technology's public acceptance programmes, contact: Roy Newson or Meriel Lewis on +44 235 433650, fax +44 235 432123. (author)

  10. Emotional response towards food packaging

    DEFF Research Database (Denmark)

    Liao, Lewis Xinwei; Corsi, Armando M.; Chrysochou, Polymeros;

    2015-01-01

    In this paper we investigate consumers’ emotional responses to food packaging. More specifically, we use self-report and physiological measures to jointly assess emotional responses to three typical food packaging elements: colours (lowwavelength vs. high-wavelength), images (positive vs. negative......) and typefaces (simple vs. ornate). A sample of 120 participants was exposed to mock package design concepts of chocolate blocks. The results suggest that images generate an emotional response that can be measured by both self-report and physiological measures, whereas colours and typefaces generate emotional...... response that can only be measured by self-report measures. We propose that a joint application of selfreport and physiological measures can lead to richer information and wider interpretation of consumer emotional responses to food packaging elements than using either measure alone....

  11. Packaging trends seen by ITRS

    Energy Technology Data Exchange (ETDEWEB)

    Juergen Wolf, M.; Reichl, H.; Aschenbrenner, R. [Fraunhofer IZM (Germany); Adams, J. [Skyworks Solutions, Corp. (United States)

    2004-07-01

    Faced with the rapid development of IC technology the traditional packaging is merging into a complex system integration technique to satisfy the growing demand in terms of increased functionality, performance and miniaturization of electronic products. This requires the development of new packaging and system integration technologies using complex design tools along with new materials to realize complex systems in a package carrying multiple components such as silicon ICs, MEMS, sensors or optical devices. System integration technologies have increasingly become a vital factor in the economic success of suppliers and users in the areas of consumer electronics, telecommunications, mechanical engineering and automotive industry. The paper discusses major aspects, challenges and requirements of system integration technologies which will be of special interest in the next years. The aspects discussed in the paper are primarily based on the work of the ITRS (International Technology Roadmap of Semiconductors) technical working group Packaging. (orig.)

  12. New Packaging for Amplifier Slabs

    Energy Technology Data Exchange (ETDEWEB)

    Riley, M. [Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States); Thorsness, C. [Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States); Suratwala, T. [Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States); Steele, R. [Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States); Rogowski, G. [Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States)

    2015-03-18

    The following memo provides a discussion and detailed procedure for a new finished amplifier slab shipping and storage container. The new package is designed to maintain an environment of <5% RH to minimize weathering.

  13. High Frequency Electronic Packaging Technology

    Science.gov (United States)

    Herman, M.; Lowry, L.; Lee, K.; Kolawa, E.; Tulintseff, A.; Shalkhauser, K.; Whitaker, J.; Piket-May, M.

    1994-01-01

    Commercial and government communication, radar, and information systems face the challenge of cost and mass reduction via the application of advanced packaging technology. A majority of both government and industry support has been focused on low frequency digital electronics.

  14. Packaging Review Guide for Reviewing Safety Analysis Reports for Packagings

    Energy Technology Data Exchange (ETDEWEB)

    DiSabatino, A; Biswas, D; DeMicco, M; Fisher, L E; Hafner, R; Haslam, J; Mok, G; Patel, C; Russell, E

    2007-04-12

    This Packaging Review Guide (PRG) provides guidance for Department of Energy (DOE) review and approval of packagings to transport fissile and Type B quantities of radioactive material. It fulfills, in part, the requirements of DOE Order 460.1B for the Headquarters Certifying Official to establish standards and to provide guidance for the preparation of Safety Analysis Reports for Packagings (SARPs). This PRG is intended for use by the Headquarters Certifying Official and his or her review staff, DOE Secretarial offices, operations/field offices, and applicants for DOE packaging approval. This PRG is generally organized at the section level in a format similar to that recommended in Regulatory Guide 7.9 (RG 7.9). One notable exception is the addition of Section 9 (Quality Assurance), which is not included as a separate chapter in RG 7.9. Within each section, this PRG addresses the technical and regulatory bases for the review, the manner in which the review is accomplished, and findings that are generally applicable for a package that meets the approval standards. This Packaging Review Guide (PRG) provides guidance for DOE review and approval of packagings to transport fissile and Type B quantities of radioactive material. It fulfills, in part, the requirements of DOE O 460.1B for the Headquarters Certifying Official to establish standards and to provide guidance for the preparation of Safety Analysis Reports for Packagings (SARPs). This PRG is intended for use by the Headquarters Certifying Official and his review staff, DOE Secretarial offices, operations/field offices, and applicants for DOE packaging approval. The primary objectives of this PRG are to: (1) Summarize the regulatory requirements for package approval; (2) Describe the technical review procedures by which DOE determines that these requirements have been satisfied; (3) Establish and maintain the quality and uniformity of reviews; (4) Define the base from which to evaluate proposed changes in scope

  15. Thermal diffusivity of light-emitting diode packaging material determined by photoacoustic piezoelectric technique

    Institute of Scientific and Technical Information of China (English)

    Sun Qi-Ming; Gao Chun-Ming; Zhao Bin-Xing; Rao Hai-Bo

    2010-01-01

    Thermal property is one of the most important properties of light-emitting diode (LED). Thermal property of LED packaging material determines the heat dissipations of the phosphor and the chip surface, accordingly having an influence on the light-emitting efficiency and the life-span of the device. In this paper, photoacoustic piezoelectric (PAPE) technique has been employed to investigate the thermal properties of polyvinyl alcohol (PVA) and silicon dioxide, which are the new and the traditional packaging materials in white LED, respectively. Firstly, the theory of PAPE technique has been developed for two-layer model in order to investigate soft materials; secondly, the experimental system has been set up and adjusted by measuring the reference sample; thirdly, the thermal diffusivities of PVA and silicon dioxide are measured and analysed. The experimental results show that PVA has a higher thermal diffusivity than silicon dioxide and is a better packaging material in the sense of thermal diffusivity for white LED.

  16. Food Packaging for Sustainable Development

    OpenAIRE

    Williams, Helén

    2011-01-01

    Packaging has been on the environmental agenda for decades. It has been discussed and debated within the society mainly as an environmental problem. Production, distribution and consumption of food and drinks contribute significant to the environmental impact. However, consumers in the EU waste about 20% of the food they buy. The function of packaging in reducing the amount of food losses is an important but often neglected environmental issue. This thesis focuses on the functions of packagin...

  17. Watermarking spot colors in packaging

    Science.gov (United States)

    Reed, Alastair; Filler, TomáÅ.¡; Falkenstern, Kristyn; Bai, Yang

    2015-03-01

    In January 2014, Digimarc announced Digimarc® Barcode for the packaging industry to improve the check-out efficiency and customer experience for retailers. Digimarc Barcode is a machine readable code that carries the same information as a traditional Universal Product Code (UPC) and is introduced by adding a robust digital watermark to the package design. It is imperceptible to the human eye but can be read by a modern barcode scanner at the Point of Sale (POS) station. Compared to a traditional linear barcode, Digimarc Barcode covers the whole package with minimal impact on the graphic design. This significantly improves the Items per Minute (IPM) metric, which retailers use to track the checkout efficiency since it closely relates to their profitability. Increasing IPM by a few percent could lead to potential savings of millions of dollars for retailers, giving them a strong incentive to add the Digimarc Barcode to their packages. Testing performed by Digimarc showed increases in IPM of at least 33% using the Digimarc Barcode, compared to using a traditional barcode. A method of watermarking print ready image data used in the commercial packaging industry is described. A significant proportion of packages are printed using spot colors, therefore spot colors needs to be supported by an embedder for Digimarc Barcode. Digimarc Barcode supports the PANTONE spot color system, which is commonly used in the packaging industry. The Digimarc Barcode embedder allows a user to insert the UPC code in an image while minimizing perceptibility to the Human Visual System (HVS). The Digimarc Barcode is inserted in the printing ink domain, using an Adobe Photoshop plug-in as the last step before printing. Since Photoshop is an industry standard widely used by pre-press shops in the packaging industry, a Digimarc Barcode can be easily inserted and proofed.

  18. AliPDU Package Upgrade

    CERN Document Server

    "Martin, Michael

    2015-01-01

    "AliPDU Package" is a set of script, panels, and datapoints designed in WinCC to manage and monitor PDU's. PDU is an essential component in the data center, in order to make data center working properly through the monitoring of power distribution and environmental condition of the data center. In this project "AliPDU Package" is upgraded so it can be used to monitor environmental condition of data center using PDU's and external environmental sensor connected to PDU.

  19. AliPDU Package Upgrade

    CERN Document Server

    Martin, Michael

    2015-01-01

    AliPDU Package is a set of script, panels, and datapoints designed in WinCC to manage and monitor PDU's. PDU is an essential component in the data center, in order to make data center working properly through the monitoring of power distribution and environmental condition of the data center. In this project "AliPDU Package" is upgraded so it can be used to monitor environmental condition of data center using PDU's and external environmental sensor connected to PDU.

  20. Avaliação da aceitação de "chips" de mandioca Acceptance evaluation of cassava chips

    Directory of Open Access Journals (Sweden)

    Regina Kitagawa Grizotto

    2003-12-01

    Full Text Available Pré-tratamentos como o cozimento, a fermentação natural e a secagem parcial foram aplicados em raízes de mandioca, visando a obtenção de "chips" comestíveis. A avaliação sensorial foi feita com base na aceitação e aparência dos "chips" das variedades IAC Mantiqueira e IAC 576.70. Trinta consumidores potenciais do produto foram selecionados em função da disponibilidade e interesse em participar dos testes. Foi utilizada escala hedônica de 7 pontos, onde os provadores avaliaram as amostras delineadas em blocos casualizados. Os resultados obtidos mostraram que os "chips" controle e pré-cozidos foram aceitos sensorialmente, apresentado médias de 5,1 (gostei ligeiramente para IAC Mantiqueira e 6,0 (gostei moderadamente para IAC 576.70. Os "chips" pré-fermentados de ambas variedades foram rejeitados. Os termos de agrado mais comentados pelos provadores foram "sabor de mandioca", "crocância" e "textura". Os termos de desagrado mais citados incluem "textura dura", "falta sabor de mandioca" e "gosto de óleo". Os provadores consideraram adequada a aparência dos "chips" de ambas variedades, sendo ligeiramente preferida a aparência dos "chips" da IAC 576.70, com exceção dos "chips" cozidos por 8 minutos e os fermentados, rejeitados pelos consumidores. A cor amarela da polpa pode ter influenciado a aceitação da variedade IAC 576.70. A composição centesimal e o teor de fibras na mandioca in natura e, o teor de lipídeos em "chips" de mandioca, também foram apresentados.Pre-treatments such as cooking, natural fermentation and partial drying were applied to cassava roots, aimed at obtaining edible cassava chips. The sensory evaluation was based on the acceptance and appearance of the chips, using the varieties IAC Mantiqueira and IAC 576.70. Thirty potential consumers of the product were selected based on their availability and interest. A 7-point hedonic scale was used, all the judges evaluating all the samples using a randomised

  1. Mechanical robustness of cryogenic temperature sensors packaged in a flat, hermetically-sealed package

    Science.gov (United States)

    Courts, S. S.

    2015-12-01

    Much of the work to develop internationally recognized temperature scales over the past 50 years was performed with thermometers whose sensing elements were constructed from platinum wire, rhodium-iron wire, or doped germanium elements. For high stability, the best results were obtained when the sensing element was strain-free mounted which reduced the effects of temperature-induced mechanical stress and deformation. Unfortunately, the devices were still highly susceptible to mechanical damage, and, barring a catastrophic mechanical shock, damage to the temperature sensors could go unnoticed as it could continue to operate with degraded accuracy. While not at the same level of stability as standards grade thermometers, many of the most commonly used cryogenic thermometers today are far more resistant to mechanical handling. This work examines the calibration offsets on three models of cryogenic temperature sensors resulting from mechanical shock and vibration. The models tested in this work were all obtained from Lake Shore Cryotronics, Inc., and included Cemox™ resistance thermometer models CX-1050-SD and CX-1050-AA, and a diode temperature sensor model DT-670-SD. Mechanical treatments were performed via a simple drop test (heights 20 cm, 50 cm, 1 m, and 4 m), random vibration per MIL-STD-202, Method 214, Table 2, Condition H, and mechanical shock per MIL-STD-883, Method 2002, Condition B. Each sensor was calibrated pre- and post-mechanical treatment and the effect of the treatment on each test sensor was quantified in terms of the equivalent temperature calibration shift. This work details the calibration shift of each sensor type following each treatment type over the 1.4 K to 325 K temperature range. No effects from the testing were discemable for Cemox and diode sensors packaged in the -SD package, a flat, hermetically sealed package, while small calibration offsets of less than 0.15% of temperature at higher temperatures were observed for Cemox sensors

  2. On-chip noninterference angular momentum multiplexing of broadband light.

    Science.gov (United States)

    Ren, Haoran; Li, Xiangping; Zhang, Qiming; Gu, Min

    2016-05-13

    Angular momentum division has emerged as a physically orthogonal multiplexing method in high-capacity optical information technologies. However, the typical bulky elements used for information retrieval from the overall diffracted field, based on the interference method, impose a fundamental limit toward realizing on-chip multiplexing. We demonstrate noninterference angular momentum multiplexing by using a mode-sorting nanoring aperture with a chip-scale footprint as small as 4.2 micrometers by 4.2 micrometers, where nanoring slits exhibit a distinctive outcoupling efficiency on tightly confined plasmonic modes. The nonresonant mode-sorting sensitivity and scalability of our approach enable on-chip parallel multiplexing over a bandwidth of 150 nanometers in the visible wavelength range. The results offer the possibility of ultrahigh-capacity and miniaturized nanophotonic devices harnessing angular momentum division.

  3. Ultra-thin chip technology and applications

    CERN Document Server

    2010-01-01

    Ultra-thin chips are the "smart skin" of a conventional silicon chip. This book shows how very thin and flexible chips can be fabricated and used in many new applications in microelectronics, microsystems, biomedical and other fields. It provides a comprehensive reference to the fabrication technology, post processing, characterization and the applications of ultra-thin chips.

  4. Upgrade of FUMACS code package

    International Nuclear Information System (INIS)

    The FUMACS code package (an acronym of FUel MAnagement Code System) was developed at Rudjer Boskovic Institute in year 1991 with the aim to enable in-core fuel management analysis of the NPP Krsko core for nominal (full power) conditions. The modernization and uprating of the NPP Krsko core from 1876 to 1994 MW (th) performed in year 2000 resulted in the change of operating conditions. The old version of the FUMACS code package would not model properly the NPP Krsko core for the new operating conditions. The upgrade of the FUMACS code package to enable the modeling of the NPP Krsko core for uprated conditions and longer cycles required modifications of master files, libraries and codes. In order to make the code package more user friendly, Windows (95/98/NT) compatible version of the code package, with incorporated graphical user interface has been developed. The new version of the code package has been verified and validated for new operating conditions through modeling and comparison of results with referent design of a number of 12-month and 18-month operating cycles.(author)

  5. Development of an AOI system for chips with a hole on backside based on a frame imager

    Science.gov (United States)

    Chen, Ming-Fu; Chou, Chih-Chung; Lien, Chun-Chien; Weng, Rui-Cian

    2016-01-01

    Defects exist for a few of IC chips during fabrication and packaging. The cost for follow-up processes can be reduced if chips with defect size of impacting chip quality can be inspected and removed during the earlier sorting process. Products will be more cost-effective and competitive. According to the inspecting requirements for microphone chips, developed AOI system has to detect the boundary flaws and hole-inside defects with size of greater than criteria from chips backside. Both the length and width of chip size are less than 5 mm and there's depth difference between the surface of chip backside and the hole-inside membrance. Thus image acquisition device is designed and implemented by an area scan imager and a telecentric lenses with a coaxial LED lighting module. Therefore we can ignore the image radiometric and geometric calibration, and keep off the shadow inside the rim of hole. An algorithm to detect defects and derive their size based on the edge pixels statistic distribution and binary chip edge image is selected. Developed AOI system then can meet the requirements of real-time defect inspection with high accuracy and performance. Frame opto-mechanical device has the spatial resolution of 5μm and FOV of 6.4 x 5.1 mm. And defect inspection can be completed within 150 ms for the chip size of 2.5 x 3.0 mm. The processes of image acquisition and defect inspection can be accomplished during the chip sorting process to satisfy the real-time online inspection. Inspected chips are placed in GO/NG trays in real-time according to their quality. From the verification results compared with the ones by microscope, the inspection accuracy is better than system requirements. The over kill rate is less than 0.3% and 3% for chip boundary flaws and hole-inside defects respectively. But it still can't be inspected correctly for the hole-inside defects of only one membrance breakage. In the future, we will improve the illumination and detecting algorithm to solve this

  6. Terahertz MMICs and Antenna-in-Package Technology at 300 GHz for KIOSK Download System

    Science.gov (United States)

    Tajima, Takuro; Kosugi, Toshihiko; Song, Ho-Jin; Hamada, Hiroshi; El Moutaouakil, Amine; Sugiyama, Hiroki; Matsuzaki, Hideaki; Yaita, Makoto; Kagami, Osamu

    2016-09-01

    Toward the realization of ultra-fast wireless communications systems, the inherent broad bandwidth of the terahertz (THz) band is attracting attention, especially for short-range instant download applications. In this paper, we present our recent progress on InP-based THz MMICs and packaging techniques based on low-temperature co-fibered ceramic (LTCC) technology. The transmitter MMICs are based on 80-nm InP-based high electron mobility transistors (HEMTs). Using the transmitter packaged in an E-plane split-block waveguide and compact lens receiver packaged in LTCC multilayered substrates, we tested wireless data transmission up to 27 Gbps with the simple amplitude key shifting (ASK) modulation scheme. We also present several THz antenna-in-packaging solutions based on substrate integrated waveguide (SIW) technology. A vertical hollow (VH) SIW was applied to a compact medium-gain SIW antenna and low-loss interconnection integrated in LTCC multi-layer substrates. The size of the LTCC antennas with 15-dBi gain is less than 0.1 cm3. For feeding the antenna, we investigated an LTCC-integrated transition and polyimide transition to LTCC VH SIWs. These transitions exhibit around 1-dB estimated loss at 300 GHz and more than 35 GHz bandwidth with 10-dB return loss. The proposed package solutions make antennas and interconnections easy to integrate in a compact LTCC package with an MMIC chip for practical applications.

  7. Development in Electronic Packaging – Moving to 3D System Configuration

    Directory of Open Access Journals (Sweden)

    I. Szendiuch

    2011-04-01

    Full Text Available The electronic industry is reducing package dimensions of components as well as complete electronics systems. Surface mount device passives and semiconductor chips have to be mounted together bringing a functional system that must realize the required function with necessary reliability and acceptable price. To make up a reliable and cost effective system, the size and weight is being reduced by employing lower voltages and higher speeds. For example, the typical size of SMD passives 30 years ago was 1206 when they were first introduced. Generally, all components including electrical joints are becoming miniaturized and smaller. The industry is moving toward a reduced size of 0201 and 01005 for passives, new fine pitch packages for actives, but the PCB now feature limits for further integration. System on Package (SOP is one way to reach the three-dimensional package concept where components will be placed in three-dimensional configuration. A similar concepts are “Package on Package” (PoP or ”Package in Package” (PiP.

  8. Repairable chip bonding/interconnect process

    Science.gov (United States)

    Bernhardt, Anthony F.; Contolini, Robert J.; Malba, Vincent; Riddle, Robert A.

    1997-01-01

    A repairable, chip-to-board interconnect process which addresses cost and testability issues in the multi-chip modules. This process can be carried out using a chip-on-sacrificial-substrate technique, involving laser processing. This process avoids the curing/solvent evolution problems encountered in prior approaches, as well is resolving prior plating problems and the requirements for fillets. For repairable high speed chip-to-board connection, transmission lines can be formed on the sides of the chip from chip bond pads, ending in a gull wing at the bottom of the chip for subsequent solder.

  9. The traditional packaged consumer goodstradein Colombia: consumer mobility

    OpenAIRE

    Emperatriz Londoño-Aldana; María E. Navas-Ríos

    2011-01-01

    The rapid growth of large-scale domestic and foreign sales coverage in many parts of Colombia since the mid-1990s, in line with theories explaining retail trade evolution, presumed that the small-scale consumer packaged goods traders would become extinct within a short time.The dynamism of trade adapting to society's evolution, as stated by Rebollo (1993), has quickly made obsolete those classifications grouping features or functions which are no longer use ful. However, the social phenomeno...

  10. CMOS On-Chip Optoelectronic Neural Interface Device with Integrated Light Source for Optogenetics

    Science.gov (United States)

    Sawadsaringkarn, Y.; Kimura, H.; Maezawa, Y.; Nakajima, A.; Kobayashi, T.; Sasagawa, K.; Noda, T.; Tokuda, T.; Ohta, J.

    2012-03-01

    A novel optoelectronic neural interface device is proposed for target applications in optogenetics for neural science. The device consists of a light emitting diode (LED) array implemented on a CMOS image sensor for on-chip local light stimulation. In this study, we designed a suitable CMOS image sensor equipped with on-chip electrodes to drive the LEDs, and developed a device structure and packaging process for LED integration. The prototype device produced an illumination intensity of approximately 1 mW with a driving current of 2.0 mA, which is expected to be sufficient to activate channelrhodopsin (ChR2). We also demonstrated the functions of light stimulation and on-chip imaging using a brain slice from a mouse as a target sample.

  11. Prevention policies addressing packaging and packaging waste: Some emerging trends.

    Science.gov (United States)

    Tencati, Antonio; Pogutz, Stefano; Moda, Beatrice; Brambilla, Matteo; Cacia, Claudia

    2016-10-01

    Packaging waste is a major issue in several countries. Representing in industrialized countries around 30-35% of municipal solid waste yearly generated, this waste stream has steadily grown over the years even if, especially in Europe, specific recycling and recovery targets have been fixed. Therefore, an increasing attention starts to be devoted to prevention measures and interventions. Filling a gap in the current literature, this explorative paper is a first attempt to map the increasingly important phenomenon of prevention policies in the packaging sector. Through a theoretical sampling, 11 countries/states (7 in and 4 outside Europe) have been selected and analyzed by gathering and studying primary and secondary data. Results show evidence of three specific trends in packaging waste prevention policies: fostering the adoption of measures directed at improving packaging design and production through an extensive use of the life cycle assessment; raising the awareness of final consumers by increasing the accountability of firms; promoting collaborative efforts along the packaging supply chains. PMID:27372152

  12. Prevention policies addressing packaging and packaging waste: Some emerging trends.

    Science.gov (United States)

    Tencati, Antonio; Pogutz, Stefano; Moda, Beatrice; Brambilla, Matteo; Cacia, Claudia

    2016-10-01

    Packaging waste is a major issue in several countries. Representing in industrialized countries around 30-35% of municipal solid waste yearly generated, this waste stream has steadily grown over the years even if, especially in Europe, specific recycling and recovery targets have been fixed. Therefore, an increasing attention starts to be devoted to prevention measures and interventions. Filling a gap in the current literature, this explorative paper is a first attempt to map the increasingly important phenomenon of prevention policies in the packaging sector. Through a theoretical sampling, 11 countries/states (7 in and 4 outside Europe) have been selected and analyzed by gathering and studying primary and secondary data. Results show evidence of three specific trends in packaging waste prevention policies: fostering the adoption of measures directed at improving packaging design and production through an extensive use of the life cycle assessment; raising the awareness of final consumers by increasing the accountability of firms; promoting collaborative efforts along the packaging supply chains.

  13. 7 CFR 58.626 - Packaging equipment.

    Science.gov (United States)

    2010-01-01

    ... 7 Agriculture 3 2010-01-01 2010-01-01 false Packaging equipment. 58.626 Section 58.626 Agriculture....626 Packaging equipment. Packaging equipment designed to mechanically fill and close single service... Standards for Equipment for Packaging Frozen Desserts and Cottage Cheese. Quality Specifications for...

  14. 21 CFR 820.130 - Device packaging.

    Science.gov (United States)

    2010-04-01

    ... 21 Food and Drugs 8 2010-04-01 2010-04-01 false Device packaging. 820.130 Section 820.130 Food and... QUALITY SYSTEM REGULATION Labeling and Packaging Control § 820.130 Device packaging. Each manufacturer shall ensure that device packaging and shipping containers are designed and constructed to protect...

  15. 40 CFR 157.27 - Unit packaging.

    Science.gov (United States)

    2010-07-01

    ... 40 Protection of Environment 23 2010-07-01 2010-07-01 false Unit packaging. 157.27 Section 157.27 Protection of Environment ENVIRONMENTAL PROTECTION AGENCY (CONTINUED) PESTICIDE PROGRAMS PACKAGING REQUIREMENTS FOR PESTICIDES AND DEVICES Child-Resistant Packaging § 157.27 Unit packaging. Pesticide...

  16. 10 CFR 71.35 - Package evaluation.

    Science.gov (United States)

    2010-01-01

    ... 10 Energy 2 2010-01-01 2010-01-01 false Package evaluation. 71.35 Section 71.35 Energy NUCLEAR REGULATORY COMMISSION (CONTINUED) PACKAGING AND TRANSPORTATION OF RADIOACTIVE MATERIAL Application for Package Approval § 71.35 Package evaluation. The application must include the following: (a)...

  17. 10 CFR 71.33 - Package description.

    Science.gov (United States)

    2010-01-01

    ... 10 Energy 2 2010-01-01 2010-01-01 false Package description. 71.33 Section 71.33 Energy NUCLEAR REGULATORY COMMISSION (CONTINUED) PACKAGING AND TRANSPORTATION OF RADIOACTIVE MATERIAL Application for Package Approval § 71.33 Package description. The application must include a description of the...

  18. Documentation of the seawater intrusion (SWI2) package for MODFLOW

    Science.gov (United States)

    Bakker, Mark; Schaars, Frans; Hughes, Joseph D.; Langevin, Christian D.; Dausman, Alyssa M.

    2013-01-01

    . This reduction in number of required model cells and the elimination of the need to solve the advective-dispersive transport equation results in substantial model run-time savings, which can be large for regional aquifers. The accuracy and use of the SWI2 Package is demonstrated through comparison with existing exact solutions and numerical solutions with SEAWAT. Results for an unconfined aquifer are also presented to demonstrate application of the SWI2 Package to a large-scale regional problem.

  19. 3D stacked chips from emerging processes to heterogeneous systems

    CERN Document Server

    Fettweis, Gerhard

    2016-01-01

    This book explains for readers how 3D chip stacks promise to increase the level of on-chip integration, and to design new heterogeneous semiconductor devices that combine chips of different integration technologies (incl. sensors) in a single package of the smallest possible size.  The authors focus on heterogeneous 3D integration, addressing some of the most important challenges in this emerging technology, including contactless, optics-based, and carbon-nanotube-based 3D integration, as well as signal-integrity and thermal management issues in copper-based 3D integration. Coverage also includes the 3D heterogeneous integration of power sources, photonic devices, and non-volatile memories based on new materials systems.   •Provides single-source reference to the latest research in 3D optoelectronic integration: process, devices, and systems; •Explains the use of wireless 3D integration to improve 3D IC reliability and yield; •Describes techniques for monitoring and mitigating thermal behavior in 3D I...

  20. Safety Analysis Report - Packages, 9965, 9968, 9972-9975 Packages

    International Nuclear Information System (INIS)

    This Safety Analysis Report for Packaging (SARP) documents the performance of the 9965 B, 9968 B, 9972 B(U), 9973 B(U), 9974 B(U), and 9975 B(U) packages in satisfying the regulatory safety requirements of the Code of Federal Regulations (CFR) 711 and the International Atomic Energy Agency (IAEA) Safety Series No. 6, Regulations for the Safe Transport of Radioactive Material, 1985 edition2. Results of the analysis and testing performed on the 9965 B, 9968 B, 9972 B(U), 9973 B(U), 9974 B(U), and 9975 B(U) packages are presented in this SARP, which was prepared in accordance with U.S. Department of energy (DOE) Order 5480.33 and in the format specified in the Nuclear Regulatory Commission (NRC) Regulatory Guides 7.94 and 7.10.5

  1. Safety analysis report - packages 9965, 9968, 9972-9975 packages

    International Nuclear Information System (INIS)

    This Safety Analysis Report for Packaging (SARP) documents the performance of the 9965 B( ), 9968 B( ), 9972 B(U), 9973 B(U), 9974 B(U), and 9975 B(U) packages in satisfying the regulatory safety requirements of the Code of Federal Regulations (CFR) 10 CFR 71 and the International Atomic Energy Agency (IAEA) Safety Series No. 6, Regulations for the Safe Transport of Radioactive Material, 1985 edition. Results of the analysis and testing performed on the 9965 B(), 9968 B(), 9972 B(U), 9973 B(U), and 9975 B(U) packages are presented in this SARP, which was prepared in accordance with U.S. Department of Energy (DOE) Order 5480.3 and in the format specified in the Nuclear Regulatory Commission (NRC) Regulatory Guides 7.9 and 7.10

  2. Chips in black boxes? Convenience life span, parafood, brandwidth, families, and co-creation.

    Science.gov (United States)

    Jacobs, Marc

    2015-11-01

    Any consumer who opens a bag of potato or corn chips (or crisps in the UK) knows there is no time to waste to enjoy or share them. The convenience life span of chips is limited: it is the shelf or storage life and a very limited time once outside the bag. Many technologies converge to generate the desired effect as a black box, not only of the packaging but also of the chips themselves. The concept of paratext can be applied to printed messages on the package, including the brand name and other texts like advertising (epitexts), which can be expanded into the concept of parafood. These concepts help to discuss technological developments and interpret why this has recently become a negotiation zone for co-creation (see the Do us a flavor campaigns). They are symptoms of changing relations between production, research and development, marketing, and consumption. This paper pays special attention to back stories, underdog brand biographies and narratives about origin. The concept of brandwidth is introduced to sensitize about the limits of combining different stories about chips. A recent brand biography, a family history and a cookery book are used to discuss the phenomenon of cooking with Fritos. Together with the concepts of parafood, brandwidth and black boxes, more reflection and dialogue about the role of history and heritage in marketing put new challenging perspectives on the agenda. PMID:25791963

  3. Chips in black boxes? Convenience life span, parafood, brandwidth, families, and co-creation.

    Science.gov (United States)

    Jacobs, Marc

    2015-11-01

    Any consumer who opens a bag of potato or corn chips (or crisps in the UK) knows there is no time to waste to enjoy or share them. The convenience life span of chips is limited: it is the shelf or storage life and a very limited time once outside the bag. Many technologies converge to generate the desired effect as a black box, not only of the packaging but also of the chips themselves. The concept of paratext can be applied to printed messages on the package, including the brand name and other texts like advertising (epitexts), which can be expanded into the concept of parafood. These concepts help to discuss technological developments and interpret why this has recently become a negotiation zone for co-creation (see the Do us a flavor campaigns). They are symptoms of changing relations between production, research and development, marketing, and consumption. This paper pays special attention to back stories, underdog brand biographies and narratives about origin. The concept of brandwidth is introduced to sensitize about the limits of combining different stories about chips. A recent brand biography, a family history and a cookery book are used to discuss the phenomenon of cooking with Fritos. Together with the concepts of parafood, brandwidth and black boxes, more reflection and dialogue about the role of history and heritage in marketing put new challenging perspectives on the agenda.

  4. The use of oxygen indicators - elements of intelligent packaging for monitoring of food quality

    Directory of Open Access Journals (Sweden)

    Renata Dobrucka

    2014-06-01

    Full Text Available Background: Producers and researchers are looking at not only the methods of protection against ingress of oxygen into the package, but also want to provide consumers with guarantees of quality food they buy. Therefore, large-scale studies are conducted and implementation of intelligent packaging. The operation of these packages is the use of interactive, the most colorful indicators to assess the quality of the packaged product. Methods: This article describes intelligent packaging technologies and presents research for different types of oxygen indicators. Results and conclusion: Indicators for the detection of oxygen allows the consumer to provide some information on the suitability of the product for consumption. Apart from that, they are a simple tool that allows you to reduce the costs associated with loss replacement, repair damaged products or their disposal. Construction of indicator contained in the package is related to the specific product and factor to be controlled.

  5. Chips with everything

    CERN Document Server

    CERN. Geneva

    2007-01-01

    In March 1972, Sir Robin Saxby gave a talk to the Royal Television Society called 'TV and Chips' about a 'state of the art' integrated circuit, containing 50 resistors and 50 transistors. Today's 'state of the art' chips contain up to a billion transistors. This enormous leap forward illustrates how dramatically the semiconductor industry has evolved in the past 34 years. The next 10 years are predicted to bring times of turbulent change for the industry, as more and more digital devices are used around the world. In this talk, Sir Robin will discuss the history of the Microchip Industry in parallel with ARM's history, demonstrating how a small European start-up can become a world player in the IT sector. He will also present his vision of important applications and developments in the next 20 years that are likely to become even more pervasive than the mobile phone is today, and will provide anecdotes and learning points from his own experience at ARM. About ARM: Sir Robin and a group of designers from Acorn...

  6. Semiconductor packaging materials interaction and reliability

    CERN Document Server

    Chen, Andrea

    2012-01-01

    In semiconductor manufacturing, understanding how various materials behave and interact is critical to making a reliable and robust semiconductor package. Semiconductor Packaging: Materials Interaction and Reliability provides a fundamental understanding of the underlying physical properties of the materials used in a semiconductor package. The book focuses on an important step in semiconductor manufacturing--package assembly and testing. It covers the basics of material properties and explains how to determine which behaviors are important to package performance. The authors also discuss how

  7. PACKAGING QUALITY ASSURANCE IN SUPPLY CHAIN

    OpenAIRE

    Agnieszka Cholewa-Wójcik; Agnieszka Kawecka

    2014-01-01

    Packaging is a very important element in products quality maintenance that is why quality of packaging has great influence and its quality assurance is necessary. Physical flow in supply chain may deteriorate some of packaging features, so their monitoring and proper conditions of storage, transport and suitable protection are important.The main goal of the paper was to present model of packaging supply chain with elements that are most influencing packaging quality. In the model are consider...

  8. Standardised Packaging of Tobacco Products Evidence Review

    OpenAIRE

    Department of Health

    2014-01-01

    The current report reviews the scientific evidence on standardised or “plain” packaging, and the extent to which plain packaging regulations would help Ireland to achieve its tobacco control objectives.   Plain packaging is a form of marketing restriction that prohibits the use of logos, colours, brand images and promotional information on tobacco packaging. Under plain packaging regulations, the colour of the pack is uniform across different brands and varieties. Regulations ma...

  9. Cigarette package design: opportunities for disease prevention

    OpenAIRE

    Pollay RW; DiFranza JR; Clark DM

    2002-01-01

    Abstract Objective To learn how cigarette packages are designed and to determine to what extent cigarette packages are designed to target children. Methods A computer search was made of all Internet websites that post tobacco industry documents using the search terms: packaging, package design, package study, box design, logo, trademark and design study. All documents were retrieved electronically and analyzed by the first author for recurrent themes. Data Synthesis Cigarette manufacturers de...

  10. SCAMPI: A code package for cross-section processing

    Energy Technology Data Exchange (ETDEWEB)

    Parks, C.V.; Petrie, L.M.; Bowman, S.M.; Broadhead, B.L.; Greene, N.M.; White, J.E.

    1996-04-01

    The SCAMPI code package consists of a set of SCALE and AMPX modules that have been assembled to facilitate user needs for preparation of problem-specific, multigroup cross-section libraries. The function of each module contained in the SCANTI code package is discussed, along with illustrations of their use in practical analyses. Ideas are presented for future work that can enable one-step processing from a fine-group, problem-independent library to a broad-group, problem-specific library ready for a shielding analysis.

  11. The paradox of packaging optimization – a characterization of packaging source reduction in the Netherlands

    NARCIS (Netherlands)

    van Sluisveld, M.A.E.; Worrell, E.

    2013-01-01

    The European Council Directive 94/62/EC for Packaging and Packaging Waste requires that Member States implement packaging waste prevention measures. However, consumption and subsequently packaging waste figures are still growing annually. It suggests that policies to accomplish packaging waste preve

  12. Development of a Packaged and Integrated Microturbine/ Chiller Combined Heat and Power (CHP) System

    Energy Technology Data Exchange (ETDEWEB)

    None

    2009-03-01

    This factsheet describes a research project whose goal is to define, develop, integrate, and validate at full scale the technology for a 1 MWe, microturbine-driven CHP packaged system for industrial or large commercial applications.

  13. Applying Partial Power-Gating to Direction-Sliced Network-on-Chip

    OpenAIRE

    Feng Wang; Xiantuo Tang; Zuocheng Xing

    2015-01-01

    Network-on-Chip (NoC) is one of critical communication architectures for future many-core systems. As technology is continually scaling down, on-chip network meets the increasing leakage power crisis. As a leakage power mitigation technique, power-gating can be utilized in on-chip network to solve the crisis. However, the network performance is severely affected by the disconnection in the conventional power-gated NoC. In this paper, we propose a novel partial power-gating approach to improve...

  14. On-chip spectroscopy with thermally-tuned high-Q photonic crystal cavities

    CERN Document Server

    Liapis, Andreas C; Siddiqui, Mahmudur R; Shi, Zhimin; Boyd, Robert W

    2015-01-01

    Spectroscopic methods are a sensitive way to determine the chemical composition of potentially hazardous materials. Here, we demonstrate that thermally-tuned high-Q photonic crystal cavities can be used as a compact high-resolution on-chip spectrometer. We have used such a chip-scale spectrometer to measure the absorption spectra of both acetylene and hydrogen cyanide in the 1550 nm spectral band, and show that we can discriminate between the two chemical species even though the two materials have spectral features in the same spectral region. Our results pave the way for the development of chip-size chemical sensors that can detect toxic substances.

  15. On-chip spectroscopy with thermally tuned high-Q photonic crystal cavities

    Energy Technology Data Exchange (ETDEWEB)

    Liapis, Andreas C., E-mail: andreas.liapis@gmail.com; Gao, Boshen; Siddiqui, Mahmudur R. [The Institute of Optics, University of Rochester, Rochester, New York 14627 (United States); Shi, Zhimin [Department of Physics, University of South Florida, Tampa, Florida 33620 (United States); Boyd, Robert W. [The Institute of Optics, University of Rochester, Rochester, New York 14627 (United States); Department of Physics and School of Electrical Engineering and Computer Science, University of Ottawa, Ottawa, Ontario K1N 6N5 (Canada)

    2016-01-11

    Spectroscopic methods are a sensitive way to determine the chemical composition of potentially hazardous materials. Here, we demonstrate that thermally tuned high-Q photonic crystal cavities can be used as a compact high-resolution on-chip spectrometer. We have used such a chip-scale spectrometer to measure the absorption spectra of both acetylene and hydrogen cyanide in the 1550 nm spectral band and show that we can discriminate between the two chemical species even though the two materials have spectral features in the same spectral region. Our results pave the way for the development of chip-size chemical sensors that can detect toxic substances.

  16. Measuring the Attenuation Length of Water in the CHIPS-M Water Cherenkov Detector

    CERN Document Server

    Amat, F; Bryant, J; Carroll, T J; Germani, S; Joyce, T; Kreisten, B; Marshak, M; Meier, J; Nelson, J; Perch, A; Pfuzner, M; De Rijck, S; Salazar, R; Thomas, J; Trokan-Tenorio, J; Vahle, P; Wade, R; Whitehead, L; Whitney, M

    2016-01-01

    The water at the proposed site of the CHIPS water Cherenkov detector has been studied to measure its attenuation length for Cherenkov light as a function of filtering time. A scaled model of the CHIPS detector filled with water from the Wentworth 2W pit, proposed site of the CHIPS deployment, in conjunction with a 3.2\\unit{m} vertical column filled with this water, was used to study the transmission of 405nm laser light. Results consistent with attenuation lengths of up to 100m were observed for this wavelength with filtration and UV sterilization alone.

  17. Materials for microfluidic chip fabrication.

    Science.gov (United States)

    Ren, Kangning; Zhou, Jianhua; Wu, Hongkai

    2013-11-19

    Through manipulating fluids using microfabricated channel and chamber structures, microfluidics is a powerful tool to realize high sensitive, high speed, high throughput, and low cost analysis. In addition, the method can establish a well-controlled microenivroment for manipulating fluids and particles. It also has rapid growing implementations in both sophisticated chemical/biological analysis and low-cost point-of-care assays. Some unique phenomena emerge at the micrometer scale. For example, reactions are completed in a shorter amount of time as the travel distances of mass and heat are relatively small; the flows are usually laminar; and the capillary effect becomes dominant owing to large surface-to-volume ratios. In the meantime, the surface properties of the device material are greatly amplified, which can lead to either unique functions or problems that we would not encounter at the macroscale. Also, each material inherently corresponds with specific microfabrication strategies and certain native properties of the device. Therefore, the material for making the device plays a dominating role in microfluidic technologies. In this Account, we address the evolution of materials used for fabricating microfluidic chips, and discuss the application-oriented pros and cons of different materials. This Account generally follows the order of the materials introduced to microfluidics. Glass and silicon, the first generation microfluidic device materials, are perfect for capillary electrophoresis and solvent-involved applications but expensive for microfabriaction. Elastomers enable low-cost rapid prototyping and high density integration of valves on chip, allowing complicated and parallel fluid manipulation and in-channel cell culture. Plastics, as competitive alternatives to elastomers, are also rapid and inexpensive to microfabricate. Their broad variety provides flexible choices for different needs. For example, some thermosets support in-situ fabrication of

  18. Reference waste package environment report

    International Nuclear Information System (INIS)

    One of three candidate repository sites for high-level radioactive waste packages is located at Yucca Mountain, Nevada, in rhyolitic tuff 700 to 1400 ft above the static water table. Calculations indicate that the package environment will experience a maximum temperature of ∼2300C at 9 years after emplacement. For the next 300 years the rock within 1 m of the waste packages will remain dehydrated. Preliminary results suggest that the waste package radiation field will have very little effect on the mechanical properties of the rock. Radiolysis products will have a negligible effect on the rock even after rehydration. Unfractured specimens of repository rock show no change in hydrologic characteristics during repeated dehydration-rehydration cycles. Fractured samples with initially high permeabilities show a striking permeability decrease during dehydration-rehydration cycling, which may be due to fracture healing via deposition of silica. Rock-water interaction studies demonstrate low and benign levels of anions and most cations. The development of sorptive secondary phases such as zeolites and clays suggests that anticipated rock-water interaction may produce beneficial changes in the package environment

  19. Package power stations for export

    Energy Technology Data Exchange (ETDEWEB)

    1985-01-01

    The cheap and efficient generation of power is an essential requirement for the success and prosperity of any community and is especially important to third world countries. It is therefore logical that the more technologically advanced nations should seek to produce power stations for the developing countries. Power plant can now be designed into a packaged form that may be readily exported and commissioned. This valuable and interesting collection of papers were originally presented at a seminar organised by the Power Industries Division of the Institution of Mechanical Engineers. Topics considered include the developing world market for packaged power stations using indigenous fuels; multi-fuel systems for power generation; packaging, modularisation, and containerisation of equipment for power boilers for export; compact coal-fired industrial plant; rural woodburning power stations; biomass gasification based power generation technology and potential; gas fed reciprocating engine development; packaged heavy duty gas turbines for power generation; and criteria for assessing the appropriateness of package power technologies in developing countries.

  20. Industrial packaging and assembly infrastructure for MOEMS

    Science.gov (United States)

    van Heeren, Henne

    2004-01-01

    , packaging and assembly is from nature application specific and solutions found are not always transferable from one product to another. But designers can often benefit from experience from other and general available technologies. A number of companies offer packaging and assembly services for MEMS/MST and this report give typical examples of those commercial services. The companies range from small start-ups, offering very specialized services, to large semiconductor packaging companies, having production lines for microsystem based products. Selecting the proper packaging method may tip the scales towards a product success or towards a product failure, while it nearly always present s a substantial part of the cost of the product. This is therefore is not a marginal concern, but a crucial part of the product design. The presentation will also address mayor trends and technologies. Finally, the article provides sufficient levels of classification and categorisation for various aspects for the technologies, in specific, and the industry, in general, to provide particularly useful insights into the activities and the developments in this market. With over 50 companies studied and assessed, it provides an up to date account of the state of this business and its future potential.

  1. HALT to qualify electronic packages: a proof of concept

    Science.gov (United States)

    Ramesham, Rajeshuni

    2014-03-01

    A proof of concept of the Highly Accelerated Life Testing (HALT) technique was explored to assess and optimize electronic packaging designs for long duration deep space missions in a wide temperature range (-150°C to +125°C). HALT is a custom hybrid package suite of testing techniques using environments such as extreme temperatures and dynamic shock step processing from 0g up to 50g of acceleration. HALT testing used in this study implemented repetitive shock on the test vehicle components at various temperatures to precipitate workmanship and/or manufacturing defects to show the weak links of the designs. The purpose is to reduce the product development cycle time for improvements to the packaging design qualification. A test article was built using advanced electronic package designs and surface mount technology processes, which are considered useful for a variety of JPL and NASA projects, i.e. (surface mount packages such as ball grid arrays (BGA), plastic ball grid arrays (PBGA), very thin chip array ball grid array (CVBGA), quad flat-pack (QFP), micro-lead-frame (MLF) packages, several passive components, etc.). These packages were daisy-chained and independently monitored during the HALT test. The HALT technique was then implemented to predict reliability and assess survivability of these advanced packaging techniques for long duration deep space missions in much shorter test durations. Test articles were built using advanced electronic package designs that are considered useful in various NASA projects. All the advanced electronic packages were daisychained independently to monitor the continuity of the individual electronic packages. Continuity of the daisy chain packages was monitored during the HALT testing using a data logging system. We were able to test the boards up to 40g to 50g shock levels at temperatures ranging from +125°C to -150°C. The HALT system can deliver 50g shock levels at room temperature. Several tests were performed by subjecting

  2. Evaluation of thermal resistance constitution for packaged AlGaN/GaN high electron mobility transistors by structure function method

    International Nuclear Information System (INIS)

    The evaluation of thermal resistance constitution for packaged AlGaN/GaN high electron mobility transistor (HEMT) by structure function method is proposed in this paper. The evaluation is based on the transient heating measurement of the AlGaN/GaN HEMT by pulsed electrical temperature sensitive parameter method. The extracted chip-level and package-level thermal resistances of the packaged multi-finger AlGaN/GaN HEMT with 400-μm SiC substrate are 22.5 K/W and 7.2 K/W respectively, which provides a non-invasive method to evaluate the chip-level thermal resistance of packaged AlGaN/GaN HEMTs. It is also experimentally proved that the extraction of the chip-level thermal resistance by this proposed method is not influenced by package form of the tested device and temperature boundary condition of measurement stage. (condensed matter: electronic structure, electrical, magnetic, and optical properties)

  3. Review: nanocomposites in food packaging.

    Science.gov (United States)

    Arora, Amit; Padua, G W

    2010-01-01

    The development of nanocomposites is a new strategy to improve physical properties of polymers, including mechanical strength, thermal stability, and gas barrier properties. The most promising nanoscale size fillers are montmorillonite and kaolinite clays. Graphite nanoplates are currently under study. In food packaging, a major emphasis is on the development of high barrier properties against the migration of oxygen, carbon dioxide, flavor compounds, and water vapor. Decreasing water vapor permeability is a critical issue in the development of biopolymers as sustainable packaging materials. The nanoscale plate morphology of clays and other fillers promotes the development of gas barrier properties. Several examples are cited. Challenges remain in increasing the compatibility between clays and polymers and reaching complete dispersion of nanoplates. Nanocomposites may advance the utilization of biopolymers in food packaging. PMID:20492194

  4. Waste package materials selection process

    International Nuclear Information System (INIS)

    The office of Civilian Radioactive Waste Management (OCRWM) of the United States Department of Energy (USDOE) is evaluating a site at Yucca Mountain in Southern Nevada to determine its suitability as a mined geologic disposal system (MGDS) for the disposal of high-level nuclear waste (HLW). The B ampersand W Fuel Company (BWFC), as a part of the Management and Operating (M ampersand O) team in support of the Yucca Mountain Site Characterization Project (YMP), is responsible for designing and developing the waste package for this potential repository. As part of this effort, Lawrence Livermore National Laboratory (LLNL) is responsible for testing materials and developing models for the materials to be used in the waste package. This paper is aimed at presenting the selection process for materials needed in fabricating the different components of the waste package

  5. Radiation sterilization and food packaging

    International Nuclear Information System (INIS)

    Food irradiation by gamma radiation or electron beams offers a number of benefits to be consumer and to the food industry. Low doses can delay fruit ripening while higher doses can reduce or eliminate pathrogenic microorganisms and control insect infestation. However, ionizing radiations are known to have an effect on the plastics used for food packaging, especially PVC and polyethylene. This chapter looks at food irradiation generally, including legislation on the irradiation of food packaging materials. The effect on specific polymers (PVC, polyethylenes, polypropylene, polystyrene, polyamides and flexible laminates) is then considered. It is concluded that few of the plastics used for food packaging are significantly affected by an overall average dose of 10KGy, the maximum likely for the irradiation of prepackaged food in the United Kingdom. (UK)

  6. On-Chip Manipulation of Protein-Coated Magnetic Beads via Domain-Wall Conduits

    DEFF Research Database (Denmark)

    Donolato, Marco; Vavassori, Paolo; Gobbi, Marco;

    2010-01-01

    Geometrically constrained magnetic domain walls (DWs) in magnetic nanowires can be manipulated at the nanometer scale. The inhomogeneous magnetic stray field generated by a DW can capture a magnetic nanoparticle in solution. On-chip nanomanipulation of individual magnetic beads coated with proteins...... is demonstrated through the motion of geometrically constrained DWs in specially designed magnetic nanoconduits fully integrated in a lab-on-a-chip platform....

  7. Measurements of millimeter wave test structures for high speed chip testing

    OpenAIRE

    De Keulenaer, Timothy; Ban, Yu; Torfs, Guy; Sercu, Stefaan; Geest, Jan van de; Bauwelinck, Johan

    2014-01-01

    This paper presents the frequency domain characterization of very high bandwidth connectorized traces and a millimeter wave rat race coupler. These connectorized differential grounded coplanar waveguide traces, essential for the testability of high speed integrated circuits, have a measured flat frequency response up to 67GHz which indicates correct connector footprint and transmission line design. The differential traces narrow down to a chip scale pitch of 150 μm allowing direct flip chip c...

  8. Lab-on-a-chip devices and micro-total analysis systems a practical guide

    CERN Document Server

    Svendsen, Winnie

    2015-01-01

    This book covers all the steps in order to fabricate a lab-on-a-chip device starting from the idea, the design, simulation, fabrication and final evaluation. Additionally, it includes basic theory on microfluidics essential to understand how fluids behave at such reduced scale. Examples of successful histories of lab-on-a-chip systems that made an impact in fields like biomedicine and life sciences are also provided.

  9. S-Chip Technical Assistance

    Data.gov (United States)

    U.S. Department of Health & Human Services — The page will provide access to reports and other published products designed to assist states with complicated S-Chip technical issues. The reports and products...

  10. Intelligent food packaging - research and development

    Directory of Open Access Journals (Sweden)

    Renata Dobrucka

    2015-03-01

    Full Text Available Packaging also fosters effective marketing of the food through distribution and sale channels. It is of the utmost importance to optimize the protection of the food, a great quality and appearance - better than typical packaged foods. In recent years, intelligent packaging became very popular. Intelligent packaging is becoming more and more widely used for food products. Application of this type of solution contributes to improvement of the quality consumer life undoubtedly. Intelligent packaging refers to a package that can sense environmental changes, and in turn, informs the users about the changes. These packaging systems contain devices that are capable of sensing and providing information about the functions and properties of the packaged foods. Also, this paper will review intelligent packaging technologies and describe different types of indicators (time-temperature indicators, freshness indicators.

  11. Development of a sensory test method for odor measurement in a package headspace

    DEFF Research Database (Denmark)

    Reinbach, Helene Christine; Allesen-Holm, Bodil Helene; Kristoffersson, Lars;

    2011-01-01

    The aim of the present study was to develop a sensory method to evaluate off-odors in a package headspace relative to a reference scale. Selection of panelists was performed with a questionnaire and with the Sniffin' stick test. A 1-butanol reference scale and three types of scales (a 15-cm line,...

  12. Whole-Teflon microfluidic chips

    OpenAIRE

    Ren, Kangning; Dai, Wen; Zhou, Jianhua; Su, Jing; Wu, Hongkai

    2011-01-01

    Although microfluidics has shown exciting potential, its broad applications are significantly limited by drawbacks of the materials used to make them. In this work, we present a convenient strategy for fabricating whole-Teflon microfluidic chips with integrated valves that show outstanding inertness to various chemicals and extreme resistance against all solvents. Compared with other microfluidic materials [e.g., poly(dimethylsiloxane) (PDMS)] the whole-Teflon chip has a few more advantages, ...

  13. Large-scale planar lightwave circuits

    Science.gov (United States)

    Bidnyk, Serge; Zhang, Hua; Pearson, Matt; Balakrishnan, Ashok

    2011-01-01

    By leveraging advanced wafer processing and flip-chip bonding techniques, we have succeeded in hybrid integrating a myriad of active optical components, including photodetectors and laser diodes, with our planar lightwave circuit (PLC) platform. We have combined hybrid integration of active components with monolithic integration of other critical functions, such as diffraction gratings, on-chip mirrors, mode-converters, and thermo-optic elements. Further process development has led to the integration of polarization controlling functionality. Most recently, all these technological advancements have been combined to create large-scale planar lightwave circuits that comprise hundreds of optical elements integrated on chips less than a square inch in size.

  14. Green Packaging Development. : A way to efficient, effective and more environmental friendly packaging solutions.

    OpenAIRE

    Mian Muhammad, Masoud

    2011-01-01

    Growing pressure on the packaging design to enhance the environmental and logistics performance of a packaging system stresses the packaging designers to search new design strategies that not only fulfill logistics requirements in the supply chain, but also reduce the CO 2emissions during the packaging life cycle. This thesis focuses on the packaging design process and suggests some improvements by considering its logistics performance and CO 2emissions. A Green packaging development model wa...

  15. Color in packaging design : Case: ZheJiang JinSheng packaging Co,Ltd

    OpenAIRE

    Hu, Cuicui

    2010-01-01

    Color occupies an important position in packaging design, with the improvement of living standard, the higher requirement of color design in packaging. The aim of this thesis was to discuss key issues concerning aesthetics of packaging design. Topics will include an overview of the packaging design, the influence factor of packaging design, and introduce the aesthetics from packaging aspect. This thesis will also identify common problems of the production process, and list the phases of ho...

  16. Quality assessment of packaged foods by optical oxygen sensing

    Science.gov (United States)

    Papkovsky, Dmitri B.; O'Mahony, Fiach C.; Kerry, Joe P.; Ogurtsov, Vladimir I.

    2005-11-01

    A phase-fluorometric oxygen sensor system has been developed, which allows non-destructive measurement of residual oxygen levels in sealed containers such as packaged foods. It operates with disposable solid-state sensors incorporated in each pack, and a portable detector which interrogates with the sensors through a (semi)transparent packaging material. The system has been optimized for packaging applications and validated in small and medium scale trials with different types of food, including MAP hams, cheese, convenience foods, smoked fish, bakery. It has demonstrated high efficiency in monitoring package integrity, oxygen profiles in packs, performance of packaging process and many other research and quality control tasks, allowing control of 100% of packs. The low-cost batch-calibrated sensors have demonstrated reliability, safety, stability including direct contact with food, high efficiency in the low oxygen range. Another system, which also employs the fluorescence-based oxygen sensing approach, provides rapid assessment of microbial contamination (total viable counts) in complex samples such as food homogenates, industrial waste, environmental samples, etc. It uses soluble oxygen-sensitive probes, standard microtitter plates and fluorescence measurements on conventional plate reader to monitor growth of aerobic bacteria in small test samples (e.g. food homogenates) via their oxygen respiration. The assay provides high sample through put, miniaturization, speed, and can serve as alternative to the established methods such as agar plate colony counts and turbidimetry.

  17. The Affordance Template ROS Package for Robot Task Programming

    Science.gov (United States)

    Hart, Stephen; Dinh, Paul; Hambuchen, Kimberly

    2015-01-01

    This paper introduces the Affordance Template ROS package for quickly programming, adjusting, and executing robot applications in the ROS RViz environment. This package extends the capabilities of RViz interactive markers by allowing an operator to specify multiple end-effector waypoint locations and grasp poses in object-centric coordinate frames and to adjust these waypoints in order to meet the run-time demands of the task (specifically, object scale and location). The Affordance Template package stores task specifications in a robot-agnostic XML description format such that it is trivial to apply a template to a new robot. As such, the Affordance Template package provides a robot-generic ROS tool appropriate for building semi-autonomous, manipulation-based applications. Affordance Templates were developed by the NASA-JSC DARPA Robotics Challenge (DRC) team and have since successfully been deployed on multiple platforms including the NASA Valkyrie and Robonaut 2 humanoids, the University of Texas Dreamer robot and the Willow Garage PR2. In this paper, the specification and implementation of the affordance template package is introduced and demonstrated through examples for wheel (valve) turning, pick-and-place, and drill grasping, evincing its utility and flexibility for a wide variety of robot applications.

  18. Design, realization and test of a digital chip for ALICE ITS experiment

    CERN Document Server

    Antinori, S; Gabrielli, A; Gandolfi, E

    2004-01-01

    CARLOS v3 (Compression And Run Length encOding subSystem) is the name of the third version of a digital radiation hardened chip that plays a significant role in the data acquisition chain of the ALICE experiment (A Large Ion Collider Experiment) for what concerns the Inner Tracking System (ITS). In particular CARLOS has the purpose of performing an on-line compression on data coming from two half detectors SDDs (Silicon Drift Detectors). In fact data volume of SDD events and trigger rate require the use of an on-line compression device with high performances for what concerns compression coefficient and total throughput. The chip has been tested using a specific PCB (Printed Circuit Board) containing the connectors for probing the ASIC with a pattern generator and a logic state analyzer. The chips have been inserted on the PCB using a ZIF socket, that allowed us to test the 35 packaged samples out of the total amount of bare chips received from the foundry. The test phase has shown that 32 out of 35 chips und...

  19. Hanford Site radioactive hazardous materials packaging directory

    Energy Technology Data Exchange (ETDEWEB)

    McCarthy, T.L.

    1995-12-01

    The Hanford Site Radioactive Hazardous Materials Packaging Directory (RHMPD) provides information concerning packagings owned or routinely leased by Westinghouse Hanford Company (WHC) for offsite shipments or onsite transfers of hazardous materials. Specific information is provided for selected packagings including the following: general description; approval documents/specifications (Certificates of Compliance and Safety Analysis Reports for Packaging); technical information (drawing numbers and dimensions); approved contents; areas of operation; and general information. Packaging Operations & Development (PO&D) maintains the RHMPD and may be contacted for additional information or assistance in obtaining referenced documentation or assistance concerning packaging selection, availability, and usage.

  20. A 4 × 2 switch matrix in QFN24 package for 0.5–3 GHz application

    International Nuclear Information System (INIS)

    This paper presents a 4 × 2 switching matrix implemented in the Win 0.5 μm GaAs pseudomorphic high electron mobility transistor process, it covers the 0.5–3 GHz frequency range. The switch matrix is composed of 4 SPDT switch whose two output ports can simultaneously select the input port and a 4 to 8 bit digital decoder, both the radio frequency (RF) part and the digital part are integrated into one single chip. The chip is packaged in a low cost QFN24 plastic package. On chip shunt, capacitors at the input ports are taken to compensate for the bonding wire inductance effect. The designed switch matrix shows a good measured performance: the insertion loss is less than 5.5 dB, the isolation is no worse than 30 dB, the return loss of input ports and output ports is better than −10 dB, the input 1 dB compression point is better than 25.6 dBm, and the OIP3 is better than 37 dBm. The chip size of the switch matrix is only 1.45 × 1.45 mm2. (semiconductor integrated circuits)