WorldWideScience

Sample records for chip scale package

  1. Integrated physics package of a chip-scale atomic clock

    International Nuclear Information System (INIS)

    The physics package of a chip-scale atomic clock (CSAC) has been successfully realized by integrating vertical cavity surface emitting laser (VCSEL), neutral density (ND) filter, λ/4 wave plate, 87Rb vapor cell, photodiode (PD), and magnetic coil into a cuboid metal package with a volume of about 2.8 cm3. In this physics package, the critical component, 87Rb vapor cell, is batch-fabricated based on MEMS technology and in-situ chemical reaction method. Pt heater and thermistors are integrated in the physics package. A PTFE pillar is used to support the optical elements in the physics package, in order to reduce the power dissipation. The optical absorption spectrum of 87Rb D1 line and the microwave frequency correction signal are successfully observed while connecting the package with the servo circuit system. Using the above mentioned packaging solution, a CSAC with short-term frequency stability of about 7 × 10−10 τ−1/2 has been successfully achieved, which demonstrates that this physics package would become one promising solution for the CSAC. (electromagnetism, optics, acoustics, heat transfer, classical mechanics, and fluid dynamics)

  2. Thermal characterization of overmolded underfill materials for stacked chip scale packages

    International Nuclear Information System (INIS)

    Stacked chip scale package (SCSP) is a new electronic packaging technology for non-CPU products, such as hand-held computing and communication devices. In this technology, one or more wire-bonded silicon chips are stacked on top of another flipped silicon chip, and an overmolded underfill encapsulant is used to both encapsulate and underfill the wire-bonded chip and the flip chip in a single process. In this paper, the cure behavior, thermal stability, filler content, and thermomechanical properties of five overmolded underfill materials have been studied using DSC, TGA, TMA, and DMA. Results showed that there is a strong correlation between thermomechanical properties and the filler content of the material. Based on measured thermomechanical properties, a 'figure-of-merit' approach was used to estimate the thermal stress induced in the package upon cooling. Results showed that an OMUF material with a low T g, low coefficient of thermal expansion (CTE), and low modulus can effectively reduce the package thermal stress. The reliability results are in good agreement with the predictions based on thermal stress estimation

  3. Advanced flip chip packaging

    CERN Document Server

    Lai, Yi-Shao; Wong, CP

    2013-01-01

    Advanced Flip Chip Packaging presents past, present and future advances and trends in areas such as substrate technology, material development, and assembly processes. Flip chip packaging is now in widespread use in computing, communications, consumer and automotive electronics, and the demand for flip chip technology is continuing to grow in order to meet the need for products that offer better performance, are smaller, and are environmentally sustainable. This book also: Offers broad-ranging chapters with a focus on IC-package-system integration Provides viewpoints from leading industry executives and experts Details state-of-the-art achievements in process technologies and scientific research Presents a clear development history and touches on trends in the industry while also discussing up-to-date technology information Advanced Flip Chip Packaging is an ideal book for engineers, researchers, and graduate students interested in the field of flip chip packaging.

  4. Validation and reliability assessment of board level drop test of chip-scale-packaging

    Science.gov (United States)

    Hung, Tuan-Yu; Chou, Chan-Yen; Yew, Ming-Chih; Chiang, Kuo-Ning

    2008-11-01

    The main objective of this study is to develop a stress-buffer-improved package that is subjected to a board level drop test under a specific-G impact level. In this regard, both the drop test experiment and the ANSYS/LS-DYNA simulations are carried out. Several studies have shown that the solder joints having the brittle intermetallic compound (IMC) layers within the wafer level chip scale packaging (WLCSP) are the weakest part. For the most part, this is due to the large relative motion occurring between the board and the chip. In addition, the stress buffer layer exhibiting a relatively large elongation which reduces the impact on the solder balls. Meanwhile, the novel stress-buffer-improve package's failure mode is different from the convention WLCSP structure which shifts to the trace damage of the chip side. The leading concern between the solder ball and trace damage is the critical region where failure occurred owing to the stress concentration effect. During the drop test experiment, the proposed stress-buffer-improved package is able to survive over 100 drops (most packages survived at above 200 drops). Hence, this drop performance very much surpasses the Joint Electron Device Engineering Council (JEDEC) criterion (drop number is 30 times). Nevertheless, the metal traces which are embedded in the stress buffer layer suffered relatively larger deformation. Generally, the stress concentration occurs at a single position, much like the trace/pad connecting junction in the analysis of detailed stress-buffer-improved package. Finally, the predict result in finite element (FE) analysis is similar to the broken metal trace's failure analysis in the drop test experiment.

  5. Characterizations of ball impact responses of wafer-level chip-scale packages

    International Nuclear Information System (INIS)

    We present in this paper ball impact test results conducted on package-level 95.5Sn-4Ag-0.5Cu solder joints of a wafer-level chip-scale package, under an impact velocity of 1.4 m/s. Scanning electron microscopy was employed to investigate intermetallic morphologies and fractographs around the under bump metallurgy before and after the ball impact test, respectively. An explicit three-dimensional finite element analysis was also conducted and the comparison between computed and measured impact force profiles are presented. The comparison indicates that when material properties and strengths are apppropriately and reasonably selected, the finite element analysis is capable of capturing relevant ball impact test (BIT)-induced transient structural responses of the solder joint prior to the initiation of fracturing

  6. Characterizations of ball impact responses of wafer-level chip-scale packages

    Energy Technology Data Exchange (ETDEWEB)

    Lai, Y.-S. [Stress-Reliability Laboratory, Advanced Semiconductor Engineering Inc., 26 Chin 3rd Road, Nantze Export Processing Zone, 811 Nantze, Kaohsiung, Taiwan (China)], E-mail: yishao_lai@aseglobal.com; Yeh, C.-L.; Chang, H.-C.; Kao, C.-L. [Stress-Reliability Laboratory, Advanced Semiconductor Engineering Inc., 26 Chin 3rd Road, Nantze Export Processing Zone, 811 Nantze, Kaohsiung, Taiwan (China)

    2008-02-14

    We present in this paper ball impact test results conducted on package-level 95.5Sn-4Ag-0.5Cu solder joints of a wafer-level chip-scale package, under an impact velocity of 1.4 m/s. Scanning electron microscopy was employed to investigate intermetallic morphologies and fractographs around the under bump metallurgy before and after the ball impact test, respectively. An explicit three-dimensional finite element analysis was also conducted and the comparison between computed and measured impact force profiles are presented. The comparison indicates that when material properties and strengths are apppropriately and reasonably selected, the finite element analysis is capable of capturing relevant ball impact test (BIT)-induced transient structural responses of the solder joint prior to the initiation of fracturing.

  7. Reliability and Characteristics of Wafer-Level Chip-Scale Packages under Current Stress

    Science.gov (United States)

    Chen, Po-Ying; Kung, Heng-Yu; Lai, Yi-Shao; Hsiung Tsai, Ming; Yeh, Wen-Kuan

    2008-02-01

    In this work, we present a novel approach and method for elucidating the characteristics of wafer-level chip-scale packages (WLCSPs) for electromigration (EM) tests. The die in WLCSP was directly attached to the substrate via a soldered interconnect. The shrinking of the area of the die that is available for power, and the solder bump also shrinks the volume and increases the density of electrons for interconnect efficiency. The bump current density now approaches to 106 A/cm2, at which point the EM becomes a significant reliability issue. As known, the EM failure depends on numerous factors, including the working temperature and the under bump metallization (UBM) thickness. A new interconnection geometry is adopted extensively with moderate success in overcoming larger mismatches between the displacements of components during current and temperature changes. Both environments and testing parameters for WLCSP are increasingly demanded. Although failure mechanisms are considered to have been eliminated or at least made manageable, new package technologies are again challenging its process, integrity and reliability. WLCSP technology was developed to eliminate the need for encapsulation to ensure compatibility with smart-mount technology (SMT). The package has good handing properties but is now facing serious reliability problems. In this work, we investigated the reliability of a WLCSP subjected to different accelerated current stressing conditions at a fixed ambient temperature of 125 °C. A very strong correlation exists between the mean time to failure (MTTF) of the WLCSP test vehicle and the mean current density that is carried by a solder joint. A series of current densities were applied to the WLCSP architecture; Black's power law was employed in a failure mode simulation. Additionally, scanning electron microscopy (SEM) was adopted to determine the differences existing between high- and low-current-density failure modes.

  8. Slip, Crystal Orientation, and Damage Evolution During Thermal Cycling in High-Strain Wafer-Level Chip-Scale Packages

    Science.gov (United States)

    Zhou, Bite; Zhou, Quan; Bieler, Thomas R.; Lee, Tae-kyu

    2015-03-01

    Wafer-level chip-scale package samples with pre-cross-sectioned edge rows were thermally cycled to study microstructure evolution and damage development. Electron backscattered diffraction (EBSD) and high-energy x-ray diffraction were used to obtain Sn grain orientations and the average coefficient of thermal expansion normal to the board in every joint of the package for samples in the as-fabricated and thermally cycled conditions. The results indicated a near-random distribution of joint orientation. Optical, scanning electron microscopy, and EBSD methods were used to characterize microstructure changes in pre-cross-sectioned samples due to thermal cycling. Slip trace analysis and Orientation Imaging Microscopy™ (OIM) show that slip systems with high Schmid factors (estimated global shear stress based on the package neutral point) are responsible for the observed microstructure evolution during thermal cycling, which provides information about slip systems that are more easily activated. Two joints were analyzed in detail to evaluate slip activity at different stages of their thermal history. The first case showed that a solidification twin grain boundary misorientation deviated from the twin relationship due to slip activity during thermal cycling, which can influence damage development and the path of crack propagation. The second case showed a new grain orientation developing due to gradual lattice rotation about the Sn [110] axis by a continuous recrystallization mechanism. This rotation was correlated with the operation of slip system . Small tin whiskers emerged from the initially polished chip interface and grew with increasing thermal cycles until a crack developed in the solder that relieved the stress. As the local stresses are not known experimentally, this analysis provides observations that can be compared with a crystal plasticity model simulation.

  9. Wafer-level chip-scale packaging analog and power semiconductor applications

    CERN Document Server

    Qu, Shichun

    2015-01-01

    This book presents a state-of-art and in-depth overview in analog and power WLCSP design, material characterization, reliability, and modeling. Recent advances in analog and power electronic WLCSP packaging are presented based on the development of analog technology and power device integration. The book covers in detail how advances in semiconductor content, analog and power advanced WLCSP design, assembly, materials, and reliability have co-enabled significant advances in fan-in and fan-out with redistributed layer (RDL) of analog and power device capability during recent years. Along with new analog and power WLCSP development, the role of modeling is a key to assure successful package design. An overview of the analog and power WLCSP modeling and typical thermal, electrical, and stress modeling methodologies is also provided. This book also: ·         Covers the development of wafer-level power discrete packaging with regular wafer-level design concepts and directly bumping technology ·    �...

  10. Self-adaptive phosphor coating technology for wafer-level scale chip packaging

    Institute of Scientific and Technical Information of China (English)

    Zhou Linsong; Rao Haibo; Wang Wei; Wan Xianlong; Liao Junyuan; Wang Xuemei; Zhou Da

    2013-01-01

    A new self-adaptive phosphor coating technology has been successfully developed,which adopted a slurry method combined with a self-exposure process.A phosphor suspension in the water-soluble photoresist was applied and exposed to LED blue light itself and developed to form a conformal phosphor coating with selfadaptability to the angular distribution of intensity of blue light and better-performing spatial color uniformity.The self-adaptive phosphor coating technology had been successfully adopted in the wafer surface to realize a waferlevel scale phosphor conformal coating.The first-stage experiments show satisfying results and give an adequate demonstration of the flexibility of self-adaptive coating technology on application of WLSCP.

  11. Estimate the thermomechanical fatigue life of two flip chip packages

    International Nuclear Information System (INIS)

    The continuing demand towards high density and low profile integrated circuit packaging has accelerated the development of flip chip structures as used in direct chip attach (DCA) technology, ball grid array (BOA) and chip scale package (CSP). In such structures the most widely used flip chip interconnects are solder joints. The reliability of flip chip structures largely depends on the reliability of solder joints. In this work solder joint fatigue life prediction for two chip scale packages is carried out. Elasto-plastic deformation behavior of the solder was simulated using ANSYS. Two dimensional plain strain finite element models were developed for each package to numerically compute the stress and total strain of the solder joints under temperature cycling. These stress and strain values are then used to predict the solder joint lifetime through modified Coffin Manson equation. The effect of solder joint's distance from edge of silicon die on life of the package is explored. The solder joint fatigue response is modeled for a typical temperature cycling of -60 to 140 degree C. (author)

  12. The extended Beer-Lambert theory for ray tracing modeling of LED chip-scaled packaging application with multiple luminescence materials

    Science.gov (United States)

    Yuan, Cadmus C. A.

    2015-12-01

    Optical ray tracing modeling applied Beer-Lambert method in the single luminescence material system to model the white light pattern from blue LED light source. This paper extends such algorithm to a mixed multiple luminescence material system by introducing the equivalent excitation and emission spectrum of individual luminescence materials. The quantum efficiency numbers of individual material and self-absorption of the multiple luminescence material system are considered as well. By this combination, researchers are able to model the luminescence characteristics of LED chip-scaled packaging (CSP), which provides simple process steps and the freedom of the luminescence material geometrical dimension. The method will be first validated by the experimental results. Afterward, a further parametric investigation has been then conducted.

  13. Flip-chip packaging for smart MEMS

    Science.gov (United States)

    Mayer, Felix; Ofner, Gerald; Koll, Andreas; Paul, Oliver; Baltes, Henry

    1998-07-01

    The cointegration of IC microsensors, actuators and readout circuit leads to smart Micro Electro Mechanical Systems (MEMS) which are superior in many aspects to their conventional discrete counterparts. However, the packaging of such device is still a challenge and a major factor of the overall production cost. On one hand MEMS need protection against mechanical contact and media. On the other hand, the encapsulation of the transducer must be partially permeable to the environment. We developed a packaging method which successfully addresses these challenges. Thereby the number of steps needed to electrically contact and partially seal the MEMS are reduced by combining them using flip-chip technology. An opening in the substrate is aligned with the transducer, and enables the interaction with external media. Concurrently with the electrical connections, a frame plated onto the microsystem is soldered to a corresponding structure on the substrate. This frame seals the rest of the chip from the medium interacting with the transducer. Using passive test chips we evaluate the performance of the new packaging method. Various underbump metal and solder deposition techniques were investigated. Both ceramic and flexible organic substrate materials were used. The combination Ni/Au bumps/InPb40 solder/ceramic substrate showed the following mechanical and electrical parameters: For 98% of the tested chips, the helium leakage rate of the sealing frame surrounding the sensor is below the threshold of the used mass spectrometer (5 X 10-7 Pa l s-1). For flip-chip pads ranging from 200 to 300 mm square, the bump resistances are smaller than 2 m(Omega) . The approach, is illustrated with three successfully packaged MEMS for the measurement of humidity, gas flow, and volatile organic compounds, respectively. They all contain integrated readout circuitry providing digital output.

  14. Microstructural Evolution of SAC305 Solder Joints in Wafer Level Chip-Scale Packaging (WLCSP) with Continuous and Interrupted Accelerated Thermal Cycling

    Science.gov (United States)

    Zhou, Quan; Zhou, Bite; Lee, Tae-Kyu; Bieler, Thomas

    2016-06-01

    Four high-strain design wafer level chip scale packages were given accelerated thermal cycling with a 10°C/min ramp rate and 10 min hold times between 0°C and 100°C to examine the effects of continuous and interrupted thermal cycling on the number of cycles to failure. The interruptions given two of the samples were the result of periodic examinations using electron backscattered pattern mapping, leading to room temperature aging of 30 days-2.5 years after increments of about 100 cycles at several stages of the cycling history. The continuous thermal cycling resulted in solder joints with a much larger degree of recrystallization, whereas the interrupted thermal cycling tests led to much less recrystallization, which was more localized near the package side, and the crack was more localized near the interface and had less branching. The failure mode for both conditions was still the same, with cracks nucleating along the high angle grain boundaries formed during recrystallization. In conditions where there were few recrystallized grains, recovery led to formation of subgrains that strengthened the solder, and the higher strength led to a larger driving force for crack growth through the solder, leading to failure after less than half of the cycles in the continuous accelerated thermal cycling condition. This work shows that there is a critical point where sufficient strain energy accumulation will trigger recrystallization, but this point depends on the rate of strain accumulation in each cycle and various recovery processes, which further depends on local crystal orientations, stress state evolution, and specific activated slip and twinning systems.

  15. Chip-size-packaged silicon microphones [for hearing instruments

    DEFF Research Database (Denmark)

    Müllenborn, Matthias; Rombach, Pirmin; Klein, Udo;

    2001-01-01

    The first results of silicon microphones that are completely batch-packaged and integrated with signal conditioning circuitry in a chip stack are discussed. The chip stack is designed to be directly mounted into a system, such as a hearing instrument, without further single-chip handling or wire...

  16. Fully additive chip packaging: science or fiction?

    NARCIS (Netherlands)

    Oosterhuis, G.; Zon, C.M.B. van der; Maalderink, H.H.

    2011-01-01

    The current trend in IC packaging towards an ever increasing degree of integration, combined with a high level of production flexibility calls for novel approaches in manufacturing. To address these challenges in a flexible manufacturing setting, TNO investigated to what extend mask-less additive ma

  17. Identifying Professional Competencies of the Flip-Chip Packaging Engineer in Taiwan

    Science.gov (United States)

    Guu, Y. H.; Lin, Kuen-Yi; Lee, Lung-Sheng

    2014-01-01

    This study employed a literature review, expert interviews, and a questionnaire survey to construct a set of two-tier competencies for a flip-chip packaging engineer. The fuzzy Delphi questionnaire was sent to 12 flip-chip engineering experts to identify professional competencies that a flip-chip packaging engineer must have. Four competencies,…

  18. The Numerical Analysis of Strain Behavior at Solder Joint and Interface of Flip Chip Package

    Institute of Scientific and Technical Information of China (English)

    S; C; Chen; Y; C; Lin

    2002-01-01

    The flip chip package is a kind of advanced electri ca l packages. Due to the requirement of miniaturization, lower weight, higher dens ity and higher performance in the advanced electric package, it is expected that flip chip package will soon be a mainstream technology. The silicon chip is dir ectly connected to printing circuit substrate by SnPb solder joints. Also, the u nderfill, a composite of polymer and silica particles, is filled in the gap betw een the chip and substrate around the solder joint...

  19. 75 FR 447 - In the Matter of Certain Semiconductor Chips With Minimized Chip Package Size and Products...

    Science.gov (United States)

    2010-01-05

    ..., 2007. 73 FR 2276 (Jan. 14, 2008). The complaint alleged violations of section 337 of the Tariff Act of... it determined to review, and on remedy, the public interest and bonding. 74 FR 57192 (Nov. 4, 2009... COMMISSION In the Matter of Certain Semiconductor Chips With Minimized Chip Package Size and...

  20. Concurrent chip and package design for radio and mixed-signal systems

    OpenAIRE

    Shen, Meigen

    2005-01-01

    The advances in VLSI and packaging technologies enable us to integrate a whole system on a single chip (SoC) or on a package module. In these systems, analog/RF electronics, digital circuitries, and memories coexist. This new technology brings us new freedom for system integration as well as new challenges in system design and implementation. To fully utilize the benefits of these new hardware technologies, concurrent design of system, chip, and package is necessary. This research aims to exp...

  1. Plasmonics: the next chip-scale technology

    Directory of Open Access Journals (Sweden)

    Rashid Zia

    2006-07-01

    Full Text Available The development of chip-scale electronics and photonics has led to remarkable data processing and transport capabilities that permeate almost every facet of our lives. Plasmonics is an exciting new device technology that has recently emerged. It exploits the unique optical properties of metallic nanostructures to enable routing and manipulation of light at the nanoscale. A tremendous synergy can be attained by integrating plasmonic, electronic, and conventional dielectric photonic devices on the same chip and taking advantage of the strengths of each technology.

  2. Ceramic thermal wind sensor based on advanced direct chip attaching package

    International Nuclear Information System (INIS)

    An advanced direct chip attaching packaged two-dimensional ceramic thermal wind sensor is studied. The thermal wind sensor chip is fabricated by metal lift-off processes on the ceramic substrate. An advanced direct chip attaching (DCA) packaging is adopted and this new packaged method simplifies the processes of packaging further. Simulations of the advanced DCA packaged sensor based on computational fluid dynamics (CFD) model show the sensor can detect wind speed and direction effectively. The wind tunnel testing results show the advanced DCA packaged sensor can detect the wind direction from 0° to 360° and wind speed from 0 to 20 m/s with the error less than 0.5 m/s. The nonlinear fitting based least square method in Matlab is used to analyze the performance of the sensor. (semiconductor devices)

  3. Flexible packaging of solid-state integrated circuit chips with elastomeric microfluidics

    OpenAIRE

    Bowei Zhang; Quan Dong; Korman, Can E.; Zhenyu Li; Zaghloul, Mona E.

    2013-01-01

    A flexible technology is proposed to integrate smart electronics and microfluidics all embedded in an elastomer package. The microfluidic channels are used to deliver both liquid samples and liquid metals to the integrated circuits (ICs). The liquid metals are used to realize electrical interconnects to the IC chip. This avoids the traditional IC packaging challenges, such as wire-bonding and flip-chip bonding, which are not compatible with current microfluidic technologies. As a demonstratio...

  4. Package-friendly piezoresistive pressure sensors with on-chip integrated packaging-stress-suppressed suspension (PS3) technology

    International Nuclear Information System (INIS)

    An on-chip integrated packaging-stress-suppressed suspension (PS3) technology for a packaging-stress-free pressure sensor is proposed and developed. With a MIS (microholes interetch and sealing) micromachining process implemented only from the front-side of a single-side polished (1 1 1) silicon wafer, a compact cantilever-shaped PS3 is on-chip integrated surrounding a piezoresistive pressure-sensing structure to provide a packaging-process/substrate-friendly method for low-cost but high-performance sensor applications. With the MIS process, the chip size of the PS3-enclosed pressure sensor is as small as 0.8 mm × 0.8 mm. Compared with a normal pressure sensor without PS3 (but with an identical pressure-sensing structure), the proposed pressure sensor has the same sensitivity of 0.046 mV kPa−1 (3.3 V) −1. However, without using the thermal compensation technique, a temperature coefficient of offset of only 0.016% °C−1 FS is noted for the sensor with PS3, which is about 15 times better than that for the sensor without PS3. Featuring effective isolation and elimination of the influence from packaging stress, the PS3 technique is promising to be widely used for packaging-friendly mechanical sensors. (paper)

  5. Apparatus and methods for packaging integrated circuit chips with antenna modules providing closed electromagnetic environment for integrated antennas

    Science.gov (United States)

    Gaucher, Brian P. (Inventor); Grzyb, Janusz (Inventor); Liu, Duixian (Inventor); Pfeiffer, Ullrich R. (Inventor)

    2008-01-01

    Apparatus and methods are provided for packaging IC chips together with integrated antenna modules designed to provide a closed EM (electromagnetic) environment for antenna radiators, thereby allowing antennas to be designed independent from the packaging technology.

  6. Storage stability of banana chips in polypropylene based nanocomposite packaging films

    OpenAIRE

    Manikantan, M. R.; Sharma, Rajiv; Kasturi, R.; Varadharaju, N.

    2012-01-01

    In this study, polypropylene (PP) based nanocomposite films of 15 different compositions of nanoclay, compatibilizer and thickness were developed and used for packaging and storage of banana chips. The effect of nanocomposite films on the quality characteristics viz. moisture content (MC), water activity (WA), total color difference(TCD), breaking force (BF), free fatty acid (FFA), peroxide value(PV), total plate count (TPC) and overall acceptability score of banana chips under ambient condit...

  7. New IC package, assembly technique by means of a "blind" alignment "flip-chip" method and assembling facilities

    Institute of Scientific and Technical Information of China (English)

    Vladimir V. Novikov

    2004-01-01

    @@ In spite of a long period of the development ofmicroelectronic components base, the problem of the creation of IC package design, providing minimal area losses in contrast with area of a chip, remains unsolved [1]Area losses can be described by the parameter P,which is equal to the ratio between the package area in plan and the chip area:

  8. Evaluation of solder joint reliability in flip-chip packages during accelerated testing

    Science.gov (United States)

    Kim, Jong-Woong; Kim, Dae-Gon; Hong, Won Sik; Jung, Seung-Boo

    2005-12-01

    The microstructural investigation and thermomechanical reliability evaluation of the Sn-3.0Ag-0.5Cu solder bumped flip-chip package were carried out during the thermal shock test of the package. In the initial reaction, the reaction product between the solder and Cu mini bump of chip side was Cu6Sn5 intermetallic compound (IMC) layer, while the two phases which were (Cu,Ni)6Sn5 and (Ni,Cu)3Sn4 were formed between the solder and electroless Ni-P layer of the package side. The cracks occurred at the corner solder joints after the thermal shocks of 400 cycles. The primary failure mechanism of the solder joints in this type of package was confirmed to be thermally-activated solder fatigue failure. The premature brittle interfacial failure sometimes occurred in the package side, but nearly all of the failed packages showed the occurrence of the typical fatigue cracks. The finite-element analyses were conducted to interpret the failure mechanisms of the packages, and revealed that the cracks were induced by the accumulation of the plastic work and viscoplastic shear strains.

  9. A packaging solution utilizing adhesive-filled TSVs and flip–chip methods

    International Nuclear Information System (INIS)

    A compact packaging solution for microelectromechanical systems (MEMS) devices is presented. The 3D-integrated packaging solution was designed for the instrumentation of a spinal screw with a wireless sensor array, but may be adapted for a variety of applications. To achieve the compact package size, an unobtrusive through-silicon via (TSV) design was added to the microfabrication process flow for the MEMS sensor. These TSVs allowed vertical integration of the MEMS devices onto flexible printed circuit boards (FPCBs) using a flip–chip system. Ohmic connections with resistance values below 1 Ω have been achieved for 100 µm TSVs in 300 and 500 µm substrates. This paper describes the design and microfabrication process flow for the TSVs, and provides details on the flip–chip techniques used to electrically and structurally connect the MEMS devices to the FPCBs. (paper)

  10. The IronChip evaluation package: a package of perl modules for robust analysis of custom microarrays

    Directory of Open Access Journals (Sweden)

    Brazma Alvis

    2010-03-01

    Full Text Available Abstract Background Gene expression studies greatly contribute to our understanding of complex relationships in gene regulatory networks. However, the complexity of array design, production and manipulations are limiting factors, affecting data quality. The use of customized DNA microarrays improves overall data quality in many situations, however, only if for these specifically designed microarrays analysis tools are available. Results The IronChip Evaluation Package (ICEP is a collection of Perl utilities and an easy to use data evaluation pipeline for the analysis of microarray data with a focus on data quality of custom-designed microarrays. The package has been developed for the statistical and bioinformatical analysis of the custom cDNA microarray IronChip but can be easily adapted for other cDNA or oligonucleotide-based designed microarray platforms. ICEP uses decision tree-based algorithms to assign quality flags and performs robust analysis based on chip design properties regarding multiple repetitions, ratio cut-off, background and negative controls. Conclusions ICEP is a stand-alone Windows application to obtain optimal data quality from custom-designed microarrays and is freely available here (see "Additional Files" section and at: http://www.alice-dsl.net/evgeniy.vainshtein/ICEP/

  11. Sub-Kelvin single flux quantum control circuits and multi-chip packaging for supporting superconducting qubit

    International Nuclear Information System (INIS)

    Superconducting single flux quantum (SFQ) circuit can operate at very low temperature. This is suitable for controlling a quantum computing system with Josephson junctions. However, it is difficult to integrate both SFQ circuits and qubits into a single-chip, because of the dissipative characteristics of SFQ circuits. Therefore, we have developed a multi-chip packaging technology for a qubit control module. The module consists of SFQ circuit chips, qubit chips, and a substrate all of which are fabricated with Nb and Al technology. The chips are flip-chip bonded with superconducting solder bumps. We also investigated SFQ control circuits for superconducting qubits and circuit parameter optimization for sub-Kelvin temperature operation. Using both multi-chip packaging and optimized SFQ control circuit makes the design of qubit control module more flexible

  12. Compact Shorted Stacked-Patch Antenna Integrated with Chip-Package Based on LTCC Technology

    Directory of Open Access Journals (Sweden)

    Yongjiu Li

    2014-01-01

    Full Text Available A low profile chip-package stacked-patch antenna is proposed by using low temperature cofired ceramic (LTCC technology. The proposed antenna employs a stacked-patch to achieve two operating frequency bands and enhance the bandwidth. The height of the antenna is decreased to 4.09 mm (about λ/25 at 2.45 GHz due to the shorted pin. The package is mounted on a 44 × 44 mm2 ground plane to miniaturize the volume of the system. The design parameters of the antenna and the effect of the antenna on chip-package cavity are carefully analyzed. The designed antenna operates at a center frequency of 2.45 GHz and its impedance bandwidth (S11< -10 dB is 200 MHz, resulting from two neighboring resonant frequencies at 2.41 and 2.51 GHz, respectively. The average gain across the frequency band is about 5.28 dBi.

  13. Optimal Structural Parameters For flip chip Assembly Based on Minimum Residual Stress Induced in Major Package Process

    International Nuclear Information System (INIS)

    Residual stress induced in packaging process is one of the major failure factors in flip chip components. In order to bring down the peak value and improve distribution form of the residual stress, a combined methodology of numerical simulation and optimization algorithm is introduced. A plane strain FEM model is established to simulate the thermal-mechanical characters of flip chip package. Anand mode and Maxwell mode are adopted to describe the time and temperature dependent material properties for eutectic solder joints and epoxy underfill respectively. On the foundation of numerical simulation result, sub-problem approximation method is employed to find optimal structural parameters for flip chip package assembly. Calculation result shows that residual stress can be effectively brought down by choosing optimal structural parameters

  14. SPIDER: Next Generation Chip Scale Imaging Sensor

    Science.gov (United States)

    Duncan, Alan; Kendrick, Rick; Thurman, Sam; Wuchenich, Danielle; Scott, Ryan P.; Yoo, S. J. B.; Su, Tiehui; Yu, Runxiang; Ogden, Chad; Proiett, Roberto

    The LM Advanced Technology Center and UC Davis are developing an Electro-Optical (EO) imaging sensor called SPIDER (Segmented Planar Imaging Detector for Electro-optical Reconnaissance) that provides a 10x to 100x size, weight, and power (SWaP) reduction alternative to the traditional bulky optical telescope and focal plane detector array. The substantial reductions in SWaP would reduce cost and/or provide higher resolution by enabling a larger aperture imager in a constrained volume. The SPIDER concept consists of thousands of direct detection white-light interferometers densely packed onto Photonic Integrated Circuits (PICs) to measure the amplitude and phase of the visibility function at spatial frequencies that span the full synthetic aperture. In other words, SPIDER would sample the object being imaged in the Fourier domain (i.e., spatial frequency domain), and then digitally reconstruct an image. The conventional approach for imaging interferometers requires complex mechanical delay lines to form the interference fringes. This results in designs that are not traceable to more than a few simultaneous spatial frequency measurements. SPIDER seeks to achieve this traceability by employing micron-=scale optical waveguides and nanophotonic structures fabricated on a PIC with micron-scale packing density to form the necessary interferometers. Prior LM IRAD and DARPA/NASA CRAD-funded SPIDER risk reduction experiments, design trades, and simulations have matured the SPIDER imager concept to a TRL 3 level. Current funding under the DARPA SPIDER Zoom program is maturing the underlying PIC technology for SPIDER to the TRL 4 level. This is done by developing and fabricating a second-generation PIC that is fully traceable to the multiple layers and low-power phase modulators required for higher-dimension waveguide arrays that are needed for higher field-of-view sensors. Our project also seeks to extend the SPIDER concept to add a zoom capability that would provide

  15. Active Solar Sail Designs for Chip-Scale Spacecraft

    OpenAIRE

    Weis, Lorraine; Peck, Mason

    2014-01-01

    Centimeter-scale spacecraft, known as ”Chipsats,” have very high surface-area-to-mass ratios, which accentuates solar radiation pressure (SRP) effects. In contrast to traditional. large solar sails, chip-scale solar sails have the potential to be highly agile in terms of attitude because of their structural rigidity and low moments of inertia. This ability to easily reorient a solar sail greatly expands the orbits that a solar-sail spacecraft can achieve. Solar sail actuation through electroc...

  16. Large scale production of wood chips for fuel

    International Nuclear Information System (INIS)

    The paper is based on the results of the national Wood Energy Technology Programme in 1999 - 2004 and the practical experiences of forest fuel production organizations in Finland. Traditionally, the major barriers to the large-scale use of forest residues for fuel are high cost of production, unsatisfactory fuel quality and unreliable supply. To overcome the barriers, the supply system must be integrated with the existing timber procurement organizations of the forest industries, procurement logistics must be refined, productivity of work must be improved through machine and system development and through learning, and the receiving and handling of chips at a plant must be adapted to wood fuels of variable quality. When the special requirements are met, wood chips are a viable and environmentally friendly fuel for large heating and CHP plants. (author)

  17. External efficiency and thermal reliability enhanced multi-chip package design for light emitting diodes

    Science.gov (United States)

    Tang, Meng-Han; Wu, Tsung-Han; Su, Guo-Dung J.

    2008-08-01

    With the power of light emitting diodes (LEDs) getting higher and higher, the issue of thermal management is getting much more important. In this paper, we discussed a new idea to get white light without using traditional phosphor and to enhance its extraction efficiency. Microlens is used for increasing external efficiency and shaping light pattern. The location of micro-lens is designed carefully by considering cup reflection. We also revealed that it is important to consider the angle of exit light from LEDs. The result shows our design is suitable for high color rendering index (CRI) application. At the same time, the uniform white light is approached as the light has been strongly diffused. Furthermore, we try to decrease the junction temperature as low as possible so as to increase stability and lifetime of LEDs. In order to maintain color mixing and dissipate heat, multi-chip or four pairs of electrodes which are electroplated with copper after bulk micromachining process within a silicon-based package are used. This novel packaging technique needs just a few processing steps and could be mass produced for nowadays high brightness light emitting diodes (HBLEDs).

  18. Crossmodal correspondences in product packaging. Assessing color-flavor correspondences for potato chips (crisps).

    Science.gov (United States)

    Piqueras-Fiszman, Betina; Spence, Charles

    2011-12-01

    We report a study designed to investigate consumers' crossmodal associations between the color of packaging and flavor varieties in crisps (potato chips). This product category was chosen because of the long-established but conflicting color-flavor conventions that exist for the salt and vinegar and cheese and onion flavor varieties in the UK. The use of both implicit and explicit measures of this crossmodal association revealed that consumers responded more slowly, and made more errors, when they had to pair the color and flavor that they implicitly thought of as being "incongruent" with the same response key. Furthermore, clustering consumers by the brand that they normally purchased revealed that the main reason why this pattern of results was observed could be their differing acquaintance with one brand versus another. In addition, when participants tried the two types of crisps from "congruently" and "incongruently" colored packets, some were unable to guess the flavor correctly in the latter case. These strong crossmodal associations did not have a significant effect on participants' hedonic appraisal of the crisps, but did arouse confusion. These results are relevant in terms of R&D, since ascertaining the appropriate color of the packaging across flavor varieties ought normally to help achieve immediate product recognition and consumer satisfaction. PMID:21824502

  19. Microelectronic packaging

    CERN Document Server

    Datta, M; Schultze, J Walter

    2004-01-01

    Microelectronic Packaging analyzes the massive impact of electrochemical technologies on various levels of microelectronic packaging. Traditionally, interconnections within a chip were considered outside the realm of packaging technologies, but this book emphasizes the importance of chip wiring as a key aspect of microelectronic packaging, and focuses on electrochemical processing as an enabler of advanced chip metallization.Divided into five parts, the book begins by outlining the basics of electrochemical processing, defining the microelectronic packaging hierarchy, and emphasizing the impac

  20. Chip-scale cavity optomechanics in lithium niobate

    OpenAIRE

    Jiang, Wei C.; LIN, QIANG

    2016-01-01

    We develop a chip-scale cavity optomechanical system in single-crystal lithium niobate that exhibits high optical quality factors and a large frequency-quality product as high as $3.6\\times 10^{12}$ Hz at room temperature and atmosphere. The excellent optical and mechanical properties together with the strong optomechanical coupling allow us to efficiently excite the coherent regenerative optomechanical oscillation operating at 375.8 MHz with a threshold power of 174 ${\\rm \\mu W}$ in the air....

  1. Chip-scale cavity optomechanics in lithium niobate

    CERN Document Server

    Jiang, Wei C

    2016-01-01

    We develop a chip-scale cavity optomechanical system in single-crystal lithium niobate that exhibits high optical quality factors and a large frequency-quality product as high as $3.6\\times 10^{12}$ Hz at room temperature and atmosphere. The excellent optical and mechanical properties together with the strong optomechanical coupling allow us to efficiently excite the coherent regenerative optomechanical oscillation operating at 375.8 MHz with a threshold power of 174 ${\\rm \\mu W}$ in the air. The demonstrated lithium niobate optomechanical device enables great potential for achieving electro-optic-mechanical hybrid systems for broad applications in sensing, metrology, and quantum physics.

  2. Lab and Bench-Scale Pelletization of Torrefied Wood Chips

    DEFF Research Database (Denmark)

    Shang, Lei; Nielsen, Niels Peter K.; Stelte, Wolfgang;

    2013-01-01

    Combined torrefaction and pelletization is used to increase the fuel value of biomass by increasing its energy density and improving its handling and combustion properties. In the present study, a single-pellet press tool was used to screen for the effects of pellet die temperature, moisture...... content, additive addition, and the degree of torrefaction on the pelletizing properties and pellet quality, i.e., density, static friction, and pellet strength. Results were compared with pellet production using a bench-scale pelletizer. The results indicate that friction is the key factor when scaling...... up from single-pellet press to bench-scale pelletizer. Tuning moisture content or increasing the die temperature did not ease the pellet production of torrefied wood chips significantly. The addition of rapeseed oil as a lubricant reduced the static friction by half and stabilized pellet production...

  3. Semiconductor Yield Analysis and Multi-Chip Package (MCP) Die Pairing Optimization using Machine Learning

    Institute of Scientific and Technical Information of China (English)

    Randall Goodwin; Russell Miller; Eugene Tuv; Alexander Borisov

    2006-01-01

    Machine Learning, Artificial Intelligence (AI) and Statistical Learning are related mathematical fields which utilize computer algorithms to create models for the purposes of data description and/or prediction. Some well known examples include biometric identification and authorization systems, speech recognition and user targeted internet advertising. Statistical Learning, which we will use in this paper, also has many applications in semiconductor manufacturing.Some of the challenging characteristics of semiconductor data include high dimensionality, mixtures of categorical and numeric data, non-randomly missing data, non-Gaussian and multimodal distributions, nonlinear complex relationships, noise, outliers and temporal dependencies. These challenges are becoming particularly acute as the quantity of available data increases and the ability to trace lots, wafers, die, and packages throughout the full fab, wafer test, assembly and final test manufacturing flow improves. Statistical-learning techniques are applied to address these challenges. In this paper we discuss the advancement and applications of Tree based classification and regression methods to semiconductor data. We begin the paper with a description of the problem, followed by and overview of the statistical-learning techniques we use in our case studies. We then describe how the challenges presented by semiconductor data were addressed with original extensions to tree-based and kernel-based methods. Next, we review four case studies: home sales price prediction, signal identification/separation, final speed bin classification and die pairing optimization for Multi-Chip Packages (MCP). Results from the case studies demonstrate how statistical-learning addresses the challenges presented by semiconductor manufacturing data and enables improved data discovery and prediction when compared to traditional statistical approaches.

  4. An RDL UBM Structural Design for Solving Ultralow- K Delamination Problem of Cu Pillar Bump Flip Chip BGA Packaging

    Science.gov (United States)

    Chen, K. M.; Wu, C. Y.; Wang, C. H.; Cheng, H. C.; Huang, N. C.

    2014-11-01

    Copper (Cu) pillar bumps tend to induce high thermal-mechanical stress during environmental tests and fabrication processes due to the high hardness of Cu, especially when applied with an ultralow- K (ULK) chip. A previous experiment showed that interfacial delamination was often observed in the ULK layers of conventional Cu pillar bump-type flip chip ball grid array (FCBGA) packages under thermal cycling, where under bump metallurgy (UBM) layers directly sit on the metal pads of silicon chips (herein termed ``direct UBM structure''). In this study, a UBM pad relocation scheme through redistribution layer (RDL) technology (herein termed ``RDL UBM structure'') is proposed to relieve the stress or ULK delamination issue. The proposed technique is tested on Cu pillar bump-type FCBGA packages subjected to thermal loading, the effectiveness of which is demonstrated through finite element stress simulation and experimental reliability tests. Simulation results reveal that the RDL UBM structure can greatly reduce the maximum stress in the ULK layers by as much as about 10% to 44%. Besides, it turns out that the Cu pillar bump-type FCBGA packages with the RDL UBM structure show good interconnect reliability performance in terms of thermal cycling, highly accelerated stress, and high-temperature storage.

  5. Photonic wire bonding: a novel concept for chip-scale interconnects

    OpenAIRE

    Lindenmann, N.; Balthasar, G.; Hillerkuss, D.; Schmogrow, R; Jordan, M.; Leuthold, J.; Freude, W; Koos, C.

    2012-01-01

    Photonic integration has witnessed tremendous progress over the last years, and chip-scale transceiver systems with Terabit/s data rates have come into reach. However, as on-chip integration density increases, efficient off-chip interfaces are becoming more and more crucial. A technological breakthrough is considered indispensable to cope with the challenges arising from large-scale photonic integration, and this particularly applies to short-distance optical interconnects. In this letter we ...

  6. An Investigation into the Package and Printed Circuit Board Assembly Solutions of an Ultrathin Coreless Flip-Chip Substrate

    Science.gov (United States)

    Chang, Jing-Yao; Chaung, Tung-Han; Chang, Tao-Chih

    2015-10-01

    Flip-chip technology has been widely accepted as a solution for electronic packaging of high-pin-count devices. Due to the demand for smaller and thinner package dimensions, coreless build-up substrates will be used in industry to carry the die by solder bumps due to the advantages of shorter transmission route and lower inductance and thermal resistance. However, coefficient of thermal expansion (CTE) mismatch between the Cu trace and the laminate often causes the coreless substrate to warp, which leads to failures such as nonwetted solder bumps and interfacial cracking during assembly and reliability tests. In a previous study, assembly of a six-layer polyimide-based coreless flip-chip package was achieved by a 17 mm × 17 mm die with 4355 Sn-37Pb solder bumps, an amide-based underfill, and 1521 Sn-3.0Ag-0.5Cu solder balls. For determination of its board-level reliability characteristics, the component was mounted on a printed circuit board (PCB) using a conventional surface mount technology, and 10 test vehicles were assembled for assessment of their reliability under a temperature cycling environment. The experimental results show that the characteristic life of the PCB assembly exceeded 1500 cycles and that failure resulted from fracture of the outermost solder balls on the substrate side. This was different from the failure mode of die cracking when the package experienced hundreds of temperature cycles at the component level because the rigid PCB, through solder balls, moderated the deformation of the coreless flip-chip package. Hence, the concentrated bending stress at the die edge region was lowered. Finally, the local CTE mismatch between the stiffener and the PCB dominated the fatigue fracture of the outermost solder balls to become the main failure mode.

  7. Fully front-side bulk-micromachined single-chip micro flow sensors for bare-chip SMT (surface mounting technology) packaging

    International Nuclear Information System (INIS)

    This paper reports novel single-wafer-based piezoresistive micro flow sensors, which are bulk micromachined only from the front side of the silicon wafer to facilitate the sensor-bare chips directly packaged into micro-fluidic systems with low-cost surface mounting technology (SMT). With neither double-sided micromachining nor multiwafer bonding needed, two structural types of the piezoresistive flow sensors are designed and fabricated in (1 1 1) wafers, where ‘type A’ sensor has a smaller channel cross section area compared to ‘type B’ sensor. After the bare sensor chip directly attached on a printed circuit board (PCB), wire bonded between the pads and the PCB for electric interconnection and the inlet/outlet front side connected, deionized water is flowed into the both types of flow sensors to characterize piezoresistive output of the differential pressure sensing elements in terms of the flow rate. For ‘type A’ and ‘type B’ sensors that are both power supplied with DC 5 V, the sensitivities are sequentially measured as 766.80 mV (µL s−1)−1 and 19.12 mV (µL s−1)−1, with the nonlinearities as 0.4% FS and 0.9% FS, respectively. Compared with traditionally fabricated micro flow sensors, the single-chip fabricated differential-pressure flow sensors can be low-cost volume manufactured. Moreover, the bare sensor chips can be simply SMT packaged for low-cost micro-system applications. (paper)

  8. 75 FR 51843 - In the Matter of Certain Large Scale Integrated Circuit Semiconductor Chips and Products...

    Science.gov (United States)

    2010-08-23

    ..., based on a complaint filed by Panasonic Corporation (``Panasonic'') of Japan. 75 FR 24742-43. The... COMMISSION In the Matter of Certain Large Scale Integrated Circuit Semiconductor Chips and Products... importation of certain large scale integrated circuit semiconductor chips and products containing same...

  9. New Polymer Materials for Microelectronics Packaging

    Institute of Scientific and Technical Information of China (English)

    2005-01-01

    @@ Researchers at the CAS Institute of Chemistry (ICCAS) have made breakthrough progress in developing the manufacturing technology of advanced polymer materials for microelectronics packaging applications. The advanced integrated circuit (IC) packaging polymer materials, including photoimageable polyimide resins and liquid epoxy underfills, are a key issue for FC-BGA/CSP(flip chip-ball grill array/chip scale packaging) which is the main stream for the next generation of microelectronics devices. With the down-sizing, thinning and high I/O (input/output) of IC chips, microelectronics packaging is now facing a big technology challenge.

  10. FlexiChip package: an universal microarray with a dedicated analysis software for high-thoughput SNPs detection linked to anti-malarial drug resistance

    Directory of Open Access Journals (Sweden)

    Dondorp Arjen M

    2009-10-01

    Full Text Available Abstract Background A number of molecular tools have been developed to monitor the emergence and spread of anti-malarial drug resistance to Plasmodium falciparum. One of the major obstacles to the wider implementation of these tools is the absence of practical methods enabling high throughput analysis. Here a new Zip-code array is described, called FlexiChip, linked to a dedicated software program, which largely overcomes this problem. Methods Previously published microarray probes detecting single-nucleotide polymorphisms (SNP associated with parasite resistance to anti-malarial drugs (ResMalChip were adapted for a universal microarray FlexiChip format. To evaluate the overall sensitivity of the FlexiChip package (microarray + software, the results of FlexiChip were compared to ResMalChip microarray, using the same extension probes and with the same PCR products. In both cases, sequence results were used as gold standard to calculate sensitivity and specificity. FlexiChip results obtained with a set of field isolates were then compared to those assessed in an independent reference laboratory. Results The FlexiChip package gave results identical to the ResMalChip results in 92.7% of samples (kappa coefficient 0.8491, with a standard error 0.021 and had a sensitivity of 95.88% and a specificity of 97.68% compared to the sequencing as the reference method. Moreover the method performed well compared to the results obtained in the reference laboratories, with 99.7% of identical results (kappa coefficient 0.9923, S.E. 0.0523. Conclusion Microarrays could be employed to monitor P. falciparum drug resistance markers with greater cost effectiveness and the possibility for high throughput analysis. The FlexiChip package is a promising tool for use in poor resource settings of malaria endemic countries.

  11. Reliability of an ultra-fine-pitch COF flip-chip package using non-conductive paste

    Science.gov (United States)

    Kim, Hae-Yeon; Min, Kyung-Eun; Lee, Jun-Sik; Lee, So-Jeong; Lee, Sung-Soo; Kim, Jun-Ki

    2016-01-01

    Ultra-fine-pitch chip-on-film (COF) packages such as display-drive-integrated circuit (DDI) modules are manufactured through an underfill process following Au-to-Sn thermo-compression bonding. As the interconnection pitch becomes finer and is reduced to less than 25 um, however, an alternative flip-chip technology, such as non-conductive paste (NCP) bonding, is needed in place of the capillary underfill process. In this study, new NCP formulations are investigated to achieve rapid curing at a temperature high enough to form a metallic bond between the bump and the pad. An appropriate curing agent was determined through a dielectric analysis (DEA). COF samples were prepared with a DDI chip 11,772 × 924 um in size and with a 38 um-thick polyimide flexible printed circuit by both NCP bonding and thermo-compressionunderfill processes. Pressure cooker tests lasting as long as 192 h revealed that the reliability of the NCP sample against high temperatures and high humidity levels exceeded somewhat that of the underfill sample. In thermal cycling test up to 500 cycles, however, the reliability of the NCP sample was inferior to that of the underfill sample. It was considered that unbonded faults and NCP trapping at the bump-to-pad joint were responsible for the premature failure of the NCP sample under a thermal cycling condition. [Figure not available: see fulltext.

  12. Co-Design Method and Wafer-Level Packaging Technique of Thin-Film Flexible Antenna and Silicon CMOS Rectifier Chips for Wireless-Powered Neural Interface Systems.

    Science.gov (United States)

    Okabe, Kenji; Jeewan, Horagodage Prabhath; Yamagiwa, Shota; Kawano, Takeshi; Ishida, Makoto; Akita, Ippei

    2015-01-01

    In this paper, a co-design method and a wafer-level packaging technique of a flexible antenna and a CMOS rectifier chip for use in a small-sized implantable system on the brain surface are proposed. The proposed co-design method optimizes the system architecture, and can help avoid the use of external matching components, resulting in the realization of a small-size system. In addition, the technique employed to assemble a silicon large-scale integration (LSI) chip on the very thin parylene film (5 μm) enables the integration of the rectifier circuits and the flexible antenna (rectenna). In the demonstration of wireless power transmission (WPT), the fabricated flexible rectenna achieved a maximum efficiency of 0.497% with a distance of 3 cm between antennas. In addition, WPT with radio waves allows a misalignment of 185% against antenna size, implying that the misalignment has a less effect on the WPT characteristics compared with electromagnetic induction. PMID:26694407

  13. Co-Design Method and Wafer-Level Packaging Technique of Thin-Film Flexible Antenna and Silicon CMOS Rectifier Chips for Wireless-Powered Neural Interface Systems

    Directory of Open Access Journals (Sweden)

    Kenji Okabe

    2015-12-01

    Full Text Available In this paper, a co-design method and a wafer-level packaging technique of a flexible antenna and a CMOS rectifier chip for use in a small-sized implantable system on the brain surface are proposed. The proposed co-design method optimizes the system architecture, and can help avoid the use of external matching components, resulting in the realization of a small-size system. In addition, the technique employed to assemble a silicon large-scale integration (LSI chip on the very thin parylene film (5 μm enables the integration of the rectifier circuits and the flexible antenna (rectenna. In the demonstration of wireless power transmission (WPT, the fabricated flexible rectenna achieved a maximum efficiency of 0.497% with a distance of 3 cm between antennas. In addition, WPT with radio waves allows a misalignment of 185% against antenna size, implying that the misalignment has a less effect on the WPT characteristics compared with electromagnetic induction.

  14. The Investigation of Die Back Edge Cracking in Flip Chip Ceramic Ball Grid Array Package (FC-CBGA

    Directory of Open Access Journals (Sweden)

    Zainudin Kornain

    2011-09-01

    Full Text Available The cracking between die back edge and top fillet for Flip Chip Ceramic Ball Grid Array (FC-CBGA package due to thermal cycling have been investigated in this study. Finite Element Analysis (FEA model was used to analyze the effect of fillet geometry and material properties of underfill upon stresses along the die back edge. The thermo-mechanical properties of commercial underfill were obtained by using Thermal Mechanical Analyzer (TMA and Dynamic Mechanical Analyzer (DMA as the input for the simulation. Die stress distribution for different fillet height and width were generated to depict variation of stress due thermal loading and the variations of tensile stress were discussed for parameter optimization. The effect of different underfill material properties were discussed as well for thermal stress reliability improvement.

  15. Insight into economies of scale for waste packaging sorting plants

    DEFF Research Database (Denmark)

    Cimpan, Ciprian; Wenzel, Henrik; Maul, Anja;

    2015-01-01

    This contribution presents the results of a techno-economic analysis performed for German Materials Recovery Facilities (MRFs) which sort commingled lightweight packaging waste (consisting of plastics, metals, beverage cartons and other composite packaging). The study addressed the importance......-70 € for large plants employing advanced process flows. Typical operational practice, often riddled with inadequate process parameters was compared with planned or designed operation. The former was found to significantly influence plant efficiency and therefore possible revenue streams from the sale of output...

  16. Simulation and analysis of effects of Young's modulus of isolation material on natural frequencies of the sensor package and displacement of the chip

    Institute of Scientific and Technical Information of China (English)

    YIN Jing-hua; LV Guang-jun; LIU Xiao-wei; LEI Qing-quan

    2005-01-01

    For the first time an anti-shock packaging model of an acoustic-vibration sensor system has been designed by using the shocking isolation principle. The finite element analysis has been applied for design and simulation of the model. The effects of Young's modulus of anti-shock rubber on naturally occurring frequencies of the combination of rubber and an acoustic sensor chip were analyzed. The displacement of the acoustic sensor chip is loaded with force. The results of static analysis and harmonic analysis show that while increasing Young's modulus of anti-chock rubber, the first five natural frequencies of the package body also increases. Yet the displacement of the acoustic sensor chip around the resonant frequency decreases. The results of static and transient analysis show that the displacement of the acoustic sensor chip decreases with the increase of Young's modulus of anti-chock rubber being loaded with either transient force or static force at the bottom of the combination of rubber and acoustic sensor chip.

  17. MEMS Direct Chip Attach Packaging Methodologies and Apparatuses for Harsh Environments

    Science.gov (United States)

    Okojie, Robert S. (Inventor)

    2009-01-01

    Methods of bulk manufacturing high temperature sensor subassembly packages are disclosed and claimed. Sensors are sandwiched between a top cover and a bottom cover so as to enable the peripheries of the top covers, sensors and bottom covers to be sealed and bound securely together are disclosed and claimed. Sensors are placed on the bottom covers leaving the periphery of the bottom cover exposed. Likewise, top covers are placed on the sensors leaving the periphery of the sensor exposed. Individual sensor sub-assemblies are inserted into final packaging elements which are also disclosed and claimed. Methods of directly attaching wires or pins to contact pads on the sensors are disclosed and claimed. Sensors, such as pressure sensors and accelerometers, and headers made out of silicon carbide and aluminum nitride are disclosed and claimed. Reference cavities are formed in some embodiments disclosed and claimed herein where top covers are not employed.

  18. 罐装薯片包装的生命周期评价%LCA of Canned Potato Chip Packaging

    Institute of Scientific and Technical Information of China (English)

    谢勇; 王凯丽; 谭海湖

    2015-01-01

    The life cycle assessment(LCA) of canned potato chip packaging was conducted covering the phases of acquisition and processing of raw materials, transportation from manufactures to consumers, use of packaging containers, recycling and waste disposal etc., with the energy consumption and environmental impact also being evaluated. The conclu-sion showed: environmental impact of the composite packaging is mainly in the material acquisition phase, i.e. the fuel consumption. The environmental impact of paper processing is much greater than those of plastic and aluminum. The impact of three disposal methods of landfill, incineration and recycling were focused on fossil fuel consumption, land occupation and inorganic substances damage to human body. Therefore, material reduction and container lightweight are the most direct and effective ways to improving packaging environmental adaptability while maintaining the existing structure.%对罐装薯片包装进行了生命周期评价,包括从原材料的获取、生产加工,工厂、消费者的运输,到包装容器的使用、二次回收使用,废弃物处理等包装的生命周期环节,对其能量消耗、环境影响等进行了评价.分析结果表明:纸铝塑复合包装的环境负荷主要体现在原材料的获取阶段,集中在燃料能源的消耗,其中纸材料加工的环境负荷要大于塑料与铝;填埋、焚烧、再利用这3种处置方式对环境的影响主要集中在化石燃料的消耗、土地占用和无机物对人体的损害上.因此,在维持现有结构的情况下,实行材料减量化和容器轻量化是提高包装环保适性最直接、有效的途径.

  19. Photonic-crystal lasers on silicon for chip-scale optical interconnects

    Science.gov (United States)

    Takeda, Koji; Fujii, Takuro; Shinya, Akihiko; Kuramochi, Eiichi; Notomi, Masaya; Hasebe, Koichi; Kakitsuka, Takaaki; Matsuo, Shinji

    2016-03-01

    Optical interconnects are expected to reduce the power consumption of ICT instruments. To realize chip-to-chip or chip-scale optical interconnects, it is essential to fabricate semiconductor lasers with a smaller energy cost. In this context, we are developing lambda-scale embedded active-region photonic-crystal (LEAP) lasers as light sources for chip-scale optical interconnects. We demonstrated the first continuous-wave (CW) operation of LEAP lasers in 2012 and reported a record low threshold current and energy cost of 4.8 μA and 4.4 fJ/bit at 10 Gbit/s in 2013. We have also integrated photonic crystal photodetectors on the same InP chip and demonstrated waveform transfer along 500-μm-long waveguides. Although LEAP lasers exhibit excellent performance, they have to be integrated on Si wafers for use as light sources for chip-scale optical interconnects. In this paper, we give a brief overview of our LEAP lasers on InP and report our recent progress in fabricating them on Si. We bonded the InP wafers with quantum-well gain layers directly on thermally oxidized Si wafers and performed all process steps on the Si wafer, including high-temperature regrowth. After this process modification, we again achieved CW operation and obtained a threshold current of 57 μA with a maximum output power of more than 3.5 μW at the output waveguides. An output light was successfully guided through 500 × 250-nm InP waveguides.

  20. Exploring massive, genome scale datasets with the genometricorr package

    KAUST Repository

    Favorov, Alexander

    2012-05-31

    We have created a statistically grounded tool for determining the correlation of genomewide data with other datasets or known biological features, intended to guide biological exploration of high-dimensional datasets, rather than providing immediate answers. The software enables several biologically motivated approaches to these data and here we describe the rationale and implementation for each approach. Our models and statistics are implemented in an R package that efficiently calculates the spatial correlation between two sets of genomic intervals (data and/or annotated features), for use as a metric of functional interaction. The software handles any type of pointwise or interval data and instead of running analyses with predefined metrics, it computes the significance and direction of several types of spatial association; this is intended to suggest potentially relevant relationships between the datasets. Availability and implementation: The package, GenometriCorr, can be freely downloaded at http://genometricorr.sourceforge.net/. Installation guidelines and examples are available from the sourceforge repository. The package is pending submission to Bioconductor. © 2012 Favorov et al.

  1. Towards Chip Scale Liquid Chromatography and High Throughput Immunosensing

    Energy Technology Data Exchange (ETDEWEB)

    Ni, J.

    2000-09-21

    This work describes several research projects aimed towards developing new instruments and novel methods for high throughput chemical and biological analysis. Approaches are taken in two directions. The first direction takes advantage of well-established semiconductor fabrication techniques and applies them to miniaturize instruments that are workhorses in analytical laboratories. Specifically, the first part of this work focused on the development of micropumps and microvalves for controlled fluid delivery. The mechanism of these micropumps and microvalves relies on the electrochemically-induced surface tension change at a mercury/electrolyte interface. A miniaturized flow injection analysis device was integrated and flow injection analyses were demonstrated. In the second part of this work, microfluidic chips were also designed, fabricated, and tested. Separations of two fluorescent dyes were demonstrated in microfabricated channels, based on an open-tubular liquid chromatography (OT LC) or an electrochemically-modulated liquid chromatography (EMLC) format. A reduction in instrument size can potentially increase analysis speed, and allow exceedingly small amounts of sample to be analyzed under diverse separation conditions. The second direction explores the surface enhanced Raman spectroscopy (SERS) as a signal transduction method for immunoassay analysis. It takes advantage of the improved detection sensitivity as a result of surface enhancement on colloidal gold, the narrow width of Raman band, and the stability of Raman scattering signals to distinguish several different species simultaneously without exploiting spatially-separated addresses on a biochip. By labeling gold nanoparticles with different Raman reporters in conjunction with different detection antibodies, a simultaneous detection of a dual-analyte immunoassay was demonstrated. Using this scheme for quantitative analysis was also studied and preliminary dose-response curves from an immunoassay of a

  2. Chip scale low dimensional materials: optoelectronics & nonlinear optics

    Science.gov (United States)

    Gu, Tingyi

    The CMOS foundry infrastructure enables integration of high density, high performance optical transceivers. We developed integrated devices that assemble resonators, waveguide, tapered couplers, pn junction and electrodes. Not only the volume standard manufacture in silicon foundry is promising to low-lost optical components operating at IR and mid-IR range, it also provides a robust platform for revealing new physical phenomenon. The thesis starts from comparison between photonic crystal and micro-ring resonators based on chip routers, showing photonic crystal switches have small footprint, consume low operation power, but its higher linear loss may require extra energy for signal amplification. Different designs are employed in their implementation in optical signal routing on chip. The second part of chapter 2 reviews the graphene based optoelectronic devices, such as modulators, lasers, switches and detectors, potential for group IV optoelectronic integrated circuits (OEIC). In chapter 3, the highly efficient thermal optic control could act as on-chip switches and (transmittance) tunable filters. Local temperature tuning compensates the wavelength differences between two resonances, and separate electrode is used for fine tuning of optical pathways between two resonators. In frequency domain, the two cavity system also serves as an optical analogue of Autler-Towns splitting, where the cavity-cavity resonance detuning is controlled by the length of pathway (phase) between them. The high thermal sensitivity of cavity resonance also effectively reflects the heat distribution around the nanoheaters, and thus derives the thermal conductivity in the planar porous suspended silicon membrane. Chapter 4 & 5 analyze graphene-silicon photonic crystal cavities with high Q and small mode volume. With negligible nonlinear response to the milliwatt laser excitation, the monolithic silicon PhC turns into highly nonlinear after transferring the single layer graphene with

  3. Ultrasonic power features of wire bonding and thermosonic flip chip bonding in microelectronics packaging

    Institute of Scientific and Technical Information of China (English)

    LI Jun-hui; HAN Lei; ZHONG Jue

    2008-01-01

    The driving voltage and current signals of piezoeeramie transducer (PZT) were measured directly by designing circuits from ultrasonic generator and using a data acquisition software system. The input impedance and power of PZT were investigated by using root mean square (RMS) calculation. The vibration driven by high frequency was tested by laser Doppler vibrometer (PSV-400-M2). And the thermosonic bonding features were observed by scanning electron microscope (JSM-6360LV). The results show that the input power of bonding is lower than that of no load. The input impedance of bonding is greater than that of no load.Nonlinear phase, plastic flow and expansion period, and strengthening bonding process are shown in the impedance and power curves. The ultrasonic power is in direct proportion to the vibration displacement driven by the power, and greater displacements driven by high power (5W) result in welding failure phenomena, such as crack, break, and peeling off in wedge bonding. For thermosonic flip chip bonding, the high power decreases position precision of bonding or results in slippage and rotation phenomena of bumps. To improve reliability and precision of thermosonic bonding, the low ultrasonic power (about 1-5W) should be chosen.

  4. Photonic packaging sourcebook fiber-chip coupling for optical components, basic calculations, modules

    CERN Document Server

    Fischer-Hirchert, Ulrich H P

    2015-01-01

    This book serves as a guide on photonic assembly techniques. It provides an overview of today's state-of-the-art technologies for photonic packaging experts and professionals in the field. The text guides the readers to the practical use of optical connectors. It also assists engineers to find a way to an effective and inexpensive set-up for their own needs. In addition, many types of current industrial modules and state-of-the-art applications from single fiber to multi fiber are described in detail. Simulation techniques such as FEM, BPM and ray tracing are explained in depth. Finally, all recent reliability test procedures for datacom and telecom modules are illustrated in combination with related standardization aspects.

  5. GaN-on-Si blue/white LEDs: epitaxy, chip, and package

    Science.gov (United States)

    Qian, Sun; Wei, Yan; Meixin, Feng; Zengcheng, Li; Bo, Feng; Hanmin, Zhao; Hui, Yang

    2016-04-01

    The dream of epitaxially integrating III-nitride semiconductors on large diameter silicon is being fulfilled through the joint R&D efforts of academia and industry, which is driven by the great potential of GaN-on-silicon technology in improving the efficiency yet at a much reduced manufacturing cost for solid state lighting and power electronics. It is very challenging to grow high quality GaN on Si substrates because of the huge mismatch in the coefficient of thermal expansion (CTE) and the large mismatch in lattice constant between GaN and silicon, often causing a micro-crack network and a high density of threading dislocations (TDs) in the GaN film. Al-composition graded AlGaN/AlN buffer layers have been utilized to not only build up a compressive strain during the high temperature growth for compensating the tensile stress generated during the cool down, but also filter out the TDs to achieve crack-free high-quality n-GaN film on Si substrates, with an X-ray rocking curve linewidth below 300 arcsec for both (0002) and (101¯2) diffractions. Upon the GaN-on-Si templates, prior to the deposition of p-AlGaN and p-GaN layers, high quality InGaN/GaN multiple quantum wells (MQWs) are overgrown with well-engineered V-defects intentionally incorporated to shield the TDs as non-radiative recombination centers and to enhance the hole injection into the MQWs through the via-like structures. The as-grown GaN-on-Si LED wafers are processed into vertical structure thin film LED chips with a reflective p-electrode and the N-face surface roughened after the removal of the epitaxial Si(111) substrates, to enhance the light extraction efficiency. We have commercialized GaN-on-Si LEDs with an average efficacy of 150–160 lm/W for 1mm2 LED chips at an injection current of 350 mA, which have passed the 10000-h LM80 reliability test. The as-produced GaN-on-Si LEDs featured with a single-side uniform emission and a nearly Lambertian distribution can adopt the wafer-level phosphor

  6. Scale-up considerations relevant to experimental studies of nuclear waste-package behavior

    International Nuclear Information System (INIS)

    Results from a study that investigated whether testing large-scale nuclear waste-package assemblages was technically warranted are reported. It was recognized that the majority of the investigations for predicting waste-package performance to date have relied primarily on laboratory-scale experimentation. However, methods for the successful extrapolation of the results from such experiments, both geometrically and over time, to actual repository conditions have not been well defined. Because a well-developed scaling technology exists in the chemical-engineering discipline, it was presupposed that much of this technology could be applicable to the prediction of waste-package performance. A review of existing literature documented numerous examples where a consideration of scaling technology was important. It was concluded that much of the existing scale-up technology is applicable to the prediction of waste-package performance for both size and time extrapolations and that conducting scale-up studies may be technically merited. However, the applicability for investigating the complex chemical interactions needs further development. It was recognized that the complexity of the system, and the long time periods involved, renders a completely theoretical approach to performance prediction almost hopeless. However, a theoretical and experimental study was defined for investigating heat and fluid flow. It was concluded that conducting scale-up modeling and experimentation for waste-package performance predictions is possible using existing technology. A sequential series of scaling studies, both theoretical and experimental, will be required to formulate size and time extrapolations of waste-package performance

  7. Leadless chip carrier packaging and cad/cam-supported wire wrap interconnect technology for subnanosecond ecl. Interim report 1 jul 80-30 jun 81

    Energy Technology Data Exchange (ETDEWEB)

    Gilbert, B.K.

    1981-11-01

    This report describes the results of work conducted to develop rapid methods for designing and prototyping high-speed digital processor systems using subnanosecond emitter coupled logic (ECL). In Task I, we have begun a conversion of the design rules, interconnection protocols, special components, and standard logic panels developed during the first year for high-speed ECL-based digital processors from a technology based upon dual-in-line packages (DIP) to a technology based upon specially designed leadless ceramic chip carriers. This conversion was undertaken since it was learned during the first year that the DIP packages themselves are compromising the maximum performance levels of which the ECL dice are capable. We have also undertaken an extensive investigation of several possible approaches to increasing these operational maxima to an even greater extent than with our present design for new Leadless Ceramic Chip Carriers. Task 2 was to continue development of a comprehensive computer-aided design/computer-aided manufacturing (CAD/CAM) software package which would be specifically tailored to support the peculiar design requirements of processors operating in a high clock rate, transmission line environment. The CAD/CAM software package has been structured to be sufficiently flexible to assimilate advances in device and component technology, and to accept new sets of design rules resulting from advances in engineering design practice.

  8. User-Loaded SlipChip for Equipment-Free Multiplexed Nanoliter-Scale Experiments

    Energy Technology Data Exchange (ETDEWEB)

    Li, Liang; Du, Wenbin; Ismagilov, Rustem (UC)

    2010-08-04

    This paper describes a microfluidic approach to perform multiplexed nanoliter-scale experiments by combining a sample with multiple different reagents, each at multiple mixing ratios. This approach employs a user-loaded, equipment-free SlipChip. The mixing ratios, characterized by diluting a fluorescent dye, could be controlled by the volume of each of the combined wells. The SlipChip design was validated on an {approx}12 nL scale by screening the conditions for crystallization of glutaryl-CoA dehydrogenase from Burkholderia pseudomallei against 48 different reagents; each reagent was tested at 11 different mixing ratios, for a total of 528 crystallization trials. The total consumption of the protein sample was {approx}10 {micro}L. Conditions for crystallization were successfully identified. The crystallization experiments were successfully scaled up in well plates using the conditions identified in the SlipChip. Crystals were characterized by X-ray diffraction and provided a protein structure in a different space group and at a higher resolution than the structure obtained by conventional methods. In this work, this user-loaded SlipChip has been shown to reliably handle fluids of diverse physicochemical properties, such as viscosities and surface tensions. Quantitative measurements of fluorescent intensities and high-resolution imaging were straighforward to perform in these glass SlipChips. Surface chemistry was controlled using fluorinated lubricating fluid, analogous to the fluorinated carrier fluid used in plug-based crystallization. Thus, we expect this approach to be valuable in a number of areas beyond protein crystallization, especially those areas where droplet-based microfluidic systems have demonstrated successes, including measurements of enzyme kinetics and blood coagulation, cell-based assays, and chemical reactions.

  9. Kinetic model for torrefaction of wood chips in a pilot-scale continuous reactor

    DEFF Research Database (Denmark)

    Shang, Lei; Ahrenfeldt, Jesper; Holm, Jens Kai;

    2014-01-01

    at different torrefaction temperatures, it was possible to predict the HHV of torrefied wood chips from the pilot reactor. The results from this study and the presented modeling approach can be used to predict the product quality from pilot scale torrefaction reactors based on small scale experiments...... temperature along the reactor and the biomass feeding rate in combination with the kinetic parameters obtained from the tests in the TGA. Together with results from a laboratory scale, batch torrefaction reactor that was used to determine the higher heating value (HHV) and mass loss (y) of the same material...

  10. Analytical investigation of the feasibility of sacrificial microchannel sealing for Chip-Scale Atomic Magnetometers

    OpenAIRE

    Tsujimoto, Kazuya; Hirai, Yoshikazu; Sugano, Koji; Tsuchiya, Toshiyuki; TABATA, Osamu

    2014-01-01

    An alkali metal vapor cell is a crucial component of the highly sensitive Chip Scale Atomic Magnetometers (CSAMs) that are increasingly deployed in a variety of electronic devices. Herein, we propose a novel microfabrication technique utilizing an array of microchannels at a bonded interface, to enable gas feedthrough for evacuation of unwanted gases from a vapor cell and subsequent introduction of an inert gas, followed by permanent sealing of the microchannels by reflow of a glass frit. The...

  11. Chip-Scale Continuously Tunable Optical Orbital Angular Momentum Generator

    CERN Document Server

    Sun, Jie; Moresco, Michele; Coolbaugh, Douglas; Watts, Michael R

    2014-01-01

    Light carrying orbital angular momentum (OAM) has potential to impact a wide variety of applications ranging from optical communications to quantum information and optical forces for the excitation and manipulation of atoms, molecules, and micro-particles. The unique advantage of utilizing OAM in these applications relies, to a large extent, on the use of multiple different OAM states. Therefore, it is desirable to have a device that is able to gen- erate light with freely adjustable OAM states in an integrated form for large- scale integration. We propose and demonstrate a compact silicon photonic integrated circuit to generate a free-space optical beam with OAM state con- tinuously tuned from a single electrical input signal, realizing both integer and non-integer OAM states. The compactness and flexibility of the device and its compatibility with complementary metal-oxide-semiconductor (CMOS) pro- cessing hold promise for integration with other silicon photonic components for wide-ranging applications.

  12. Validation of SCALE code package on high performance neutron shields

    International Nuclear Information System (INIS)

    The shielding ability and other properties of new high performance neutron shielding materials from the KRAFTON series have been recently published. A comparison of the published experimental and MCNP results for the two materials of the KRAFTON series, with our own calculations has been done. Two control modules of the SCALE-4.4 code system have been used, one of them based on one dimensional radiation transport analysis (SAS1) and other based on the three dimensional Monte Carlo method (SAS3). The comparison of the calculated neutron dose equivalent rates shows a good agreement between experimental and calculated results for the KRAFTON-N2 material.. Our results indicate that the N2-M-N2 sandwich type is approximately 10% inferior as neutron shield to the KRAFTON-N2 material. All values of neutron dose equivalent obtained by SAS1 are approximately 25% lower in comparison with the SAS3 results, which indicates proportions of discrepancies introduced by one-dimensional geometry approximation.(author)

  13. Stabilized chip-scale Kerr frequency comb via a high-Q reference photonic microresonator

    Science.gov (United States)

    Lim, Jinkang; Huang, Shu-Wei; Vinod, Abhinav K.; Mortazavian, Parastou; Yu, Mingbin; Kwong, Dim-Lee; Savchenkov, Anatoliy A.; Matsko, Andrey B.; Maleki, Lute; Wong, Chee Wei

    2016-08-01

    We stabilize a chip-scale Si3N4 phase-locked Kerr frequency comb via locking the pump laser to an independent stable high-Q reference microresonator and locking the comb spacing to an external microwave oscillator. In this comb, the pump laser shift induces negligible impact on the comb spacing change. This scheme is a step towards miniaturization of the stabilized Kerr comb system as the microresonator reference can potentially be integrated on-chip. Fractional instability of the optical harmonics of the stabilized comb is limited by the microwave oscillator used for comb spacing lock below 1 s averaging time and coincides with the pump laser drift in the long term.

  14. A stabilized chip-scale Kerr frequency comb via a high-Q reference photonic microresonator

    CERN Document Server

    Lim, Jinkang; Vinod, Abhinav K; Mortazavian, Parastou; Yu, Mingbin; Kwong, Dim-Lee; Savchenkov, Anatoliy A; Matsko, Andrey B; Maleki, Lute; Wong, Chee Wei

    2016-01-01

    We stabilize a chip-scale Si3N4 phase-locked Kerr frequency comb via locking the pump laser to an independent stable high-Q reference microresonator and locking the comb spacing to an external microwave oscillator. In this comb, the pump laser shift induces negligible impact on the comb spacing change. This scheme is a step towards miniaturization of the stabilized Kerr comb system as the microresonator reference can potentially be integrated on-chip. Fractional instability of the optical harmonics of the stabilized comb is limited by the microwave oscillator used for comb spacing lock below 1 s averaging time and coincides with the pump laser drift in the long term.

  15. Nature-Inspired Interconnects for Self-Assembled Large-Scale Network-on-Chip Designs

    CERN Document Server

    Teuscher, Christof

    2007-01-01

    Future nano-scale electronics built up from an Avogadro number of components needs efficient, highly scalable, and robust means of communication in order to be competitive with traditional silicon approaches. In recent years, the Networks-on-Chip (NoC) paradigm emerged as a promising solution to interconnect challenges in silicon-based electronics. Current NoC architectures are either highly regular or fully customized, both of which represent implausible assumptions for emerging bottom-up self-assembled molecular electronics that are generally assumed to have a high degree of irregularity and imperfection. Here, we pragmatically and experimentally investigate important design trade-offs and properties of an irregular, abstract, yet physically plausible 3D small-world interconnect fabric that is inspired by modern network-on-chip paradigms. We vary the framework's key parameters, such as the connectivity, the number of switch nodes, the distribution of long- versus short-range connections, and measure the net...

  16. Surface Tension Directed Fluidic Self-Assembly of Semiconductor Chips across Length Scales and Material Boundaries

    Directory of Open Access Journals (Sweden)

    Shantonu Biswas

    2016-03-01

    Full Text Available This publication provides an overview and discusses some challenges of surface tension directed fluidic self-assembly of semiconductor chips which are transported in a liquid medium. The discussion is limited to surface tension directed self-assembly where the capture, alignment, and electrical connection process is driven by the surface free energy of molten solder bumps where the authors have made a contribution. The general context is to develop a massively parallel and scalable assembly process to overcome some of the limitations of current robotic pick and place and serial wire bonding concepts. The following parts will be discussed: (2 Single-step assembly of LED arrays containing a repetition of a single component type; (3 Multi-step assembly of more than one component type adding a sequence and geometrical shape confinement to the basic concept to build more complex structures; demonstrators contain (3.1 self-packaging surface mount devices, and (3.2 multi-chip assemblies with unique angular orientation. Subsequently, measures are discussed (4 to enable the assembly of microscopic chips (10 μm–1 mm; a different transport method is introduced; demonstrators include the assembly of photovoltaic modules containing microscopic silicon tiles. Finally, (5 the extension to enable large area assembly is presented; a first reel-to-reel assembly machine is realized; the machine is applied to the field of solid state lighting and the emerging field of stretchable electronics which requires the assembly and electrical connection of semiconductor devices over exceedingly large area substrates.

  17. Preliminary evaluation of waste package releases using drift-scale thermo-hydrologic analyses

    International Nuclear Information System (INIS)

    In a 1993 performance assessment, the uncertainty associated with using panel-scale thermo-hydrologic analyses to define the near-field environment in the vicinity of the waste packages was identified as one of the major factors impacting the predicted performance. This was because of the impact of the thermo-hydrologic regime on the initiation of aqueous corrosion as well as the rate of corrosion, rate of waste form dissolution (due to the uncertainty in the percent of the waste form surface covered by water film), solubility limits, and the effective diffusion through the waste package and engineered barrier. This document presents an initial attempt to incorporate, in a more representative fashion, the anticipated thermo-hydrologic response in the vicinity of in-drift emplaced waste packages into the post-closure performance assessment. It illustrates some of the issues which must be resolved prior to justifying the inclusion of these representations into the assessment

  18. Development of the Large-Scale Oligonucleotide Chip for the Diagnosis of Plant Viruses and its Practical Use

    OpenAIRE

    Nam, Moon; Kim, Jeong-Seon; Lim, Seungmo; Park, Chung Youl; Kim, Jeong-Gyu; Choi, Hong-Soo; Lim, Hyoun-Sub; Moon, Jae Sun; Lee, Su-Heon

    2014-01-01

    A large-scale oligonucleotide (LSON) chip was developed for the detection of the plant viruses with known genetic information. The LSON chip contains two sets of 3,978 probes for 538 species of targets including plant viruses, satellite RNAs and viroids. A hundred forty thousand probes, consisting of isolate-, species- and genus-specific probes respectively, are designed from 20,000 of independent nucleotide sequence of plant viruses. Based on the economic importance, the amount of genome inf...

  19. Chip-Scale Nanofabrication of Single Spins and Spin Arrays in Diamond

    Energy Technology Data Exchange (ETDEWEB)

    Toyli, David M.; Weis, Christoph D.; Fuchs, D.; Schenkel, Thomas; Awschalom, David D.

    2010-07-02

    We demonstrate a technique to nanofabricate nitrogen vacancy (NV) centers in diamond based on broad-beam nitrogen implantation through apertures in electron beam lithography resist. This method enables high-throughput nanofabrication of single NV centers on sub-100-nm length scales. Secondary ion mass spectroscopy measurements facilitate depth profiling of the implanted nitrogen to provide three-dimensional characterization of the NV center spatial distribution. Measurements of NV center coherence with on-chip coplanar waveguides suggest a pathway for incorporating this scalable nanofabrication technique in future quantum applications.

  20. New Latency Model for Dynamic Frequency Scaling on Network-on-Chip

    Institute of Scientific and Technical Information of China (English)

    Sheng-Nan Li; Wen-Ming Pan

    2014-01-01

    Modulating both the clock frequency and supply voltage of the network-on-chip (NoC) during runtime can reduce the power consumption and heat flux, but will lead to the increase of the latency of NoC. It is necessary to find a tradeoff between power consumption and communication latency. So we propose an analytical latency model which can show us the relationship of them. The proposed model to analyze latency is based on the M/G/1 queuing model, which is suitable for dynamic frequency scaling. The experiment results show that the accuracy of this model is more than 90%.

  1. Characterization of integrated circuit packaging materials

    CERN Document Server

    Moore, Thomas

    1993-01-01

    Chapters in this volume address important characteristics of IC packages. Analytical techniques appropriate for IC package characterization are demonstrated through examples of the measurement of critical performance parameters and the analysis of key technological problems of IC packages. Issues are discussed which affect a variety of package types, including plastic surface-mount packages, hermetic packages, and advanced designs such as flip-chip, chip-on-board and multi-chip models.

  2. Network Partitioning Domain Knowledge Multiobjective Application Mapping for Large-Scale Network-on-Chip

    Directory of Open Access Journals (Sweden)

    Yin Zhen Tei

    2014-01-01

    Full Text Available This paper proposes a multiobjective application mapping technique targeted for large-scale network-on-chip (NoC. As the number of intellectual property (IP cores in multiprocessor system-on-chip (MPSoC increases, NoC application mapping to find optimum core-to-topology mapping becomes more challenging. Besides, the conflicting cost and performance trade-off makes multiobjective application mapping techniques even more complex. This paper proposes an application mapping technique that incorporates domain knowledge into genetic algorithm (GA. The initial population of GA is initialized with network partitioning (NP while the crossover operator is guided with knowledge on communication demands. NP reduces the large-scale application mapping complexity and provides GA with a potential mapping search space. The proposed genetic operator is compared with state-of-the-art genetic operators in terms of solution quality. In this work, multiobjective optimization of energy and thermal-balance is considered. Through simulation, knowledge-based initial mapping shows significant improvement in Pareto front compared to random initial mapping that is widely used. The proposed knowledge-based crossover also shows better Pareto front compared to state-of-the-art knowledge-based crossover.

  3. A chip tuneable laser developed for on-line micro–nano scale surface measurements

    International Nuclear Information System (INIS)

    The demand for accuracy and precision at the micro–nano level is constantly increasing in the manufacture of high added value products. This requires control and measurement of the surface structure since surface properties at such tiny scales are the dominant functional determinant. Many commercial instruments have been used for surface measurements. However, these devices are almost always operated in an off-line environment, and are not suitable for on-line application. This paper presents a new interferometry system consisting of a chip tuneable laser for future on-line micro–nano scale surface measurements. It is simple, compact and robust as most environmental noise and disturbance can be eliminated without any servo control system due to the near common path configuration and the compact construction. The experimental results show that this system has good performance, and there is scope to improve this if the performance of the laser is enhanced

  4. Large-field-of-view Chip-scale Talbot-grid-based Fluorescence Microscopy

    CERN Document Server

    Pang, Shuo; Kato, Mihoko; Sternberg, Paul W; Yang, Changhuei

    2012-01-01

    The fluorescence microscope is one of the most important tools in modern clinical diagnosis and biological science. However, its expense, size and limited field-of-view (FOV) are becoming bottlenecks in key applications such as large-scale phenotyping and low-resource-setting diagnostics. Here we report a low-cost, compact chip-scale fluorescence-imaging platform, termed the Fluorescence Talbot Microscopy (FTM), which utilizes the Talbot self-imaging effect to enable efficient fluorescence imaging over a large and directly-scalable FOV. The FTM prototype has a resolution of 1.2 microns and an FOV of 3.9 mm x 3.5 mm. We demonstrate the imaging capability of FTM on fluorescently labeled breast cancer cells (SK-BR-3) and HEK cells expressing green fluorescent protein.

  5. Using Synchrotron Radiation Microtomography to Investigate Multi-scale Three-dimensional Microelectronic Packages.

    Science.gov (United States)

    Carlton, Holly D; Elmer, John W; Li, Yan; Pacheco, Mario; Goyal, Deepak; Parkinson, Dilworth Y; MacDowell, Alastair A

    2016-01-01

    Synchrotron radiation micro-tomography (SRµT) is a non-destructive three-dimensional (3D) imaging technique that offers high flux for fast data acquisition times with high spatial resolution. In the electronics industry there is serious interest in performing failure analysis on 3D microelectronic packages, many which contain multiple levels of high-density interconnections. Often in tomography there is a trade-off between image resolution and the volume of a sample that can be imaged. This inverse relationship limits the usefulness of conventional computed tomography (CT) systems since a microelectronic package is often large in cross sectional area 100-3,600 mm(2), but has important features on the micron scale. The micro-tomography beamline at the Advanced Light Source (ALS), in Berkeley, CA USA, has a setup which is adaptable and can be tailored to a sample's properties, i.e., density, thickness, etc., with a maximum allowable cross-section of 36 x 36 mm. This setup also has the option of being either monochromatic in the energy range ~7-43 keV or operating with maximum flux in white light mode using a polychromatic beam. Presented here are details of the experimental steps taken to image an entire 16 x 16 mm system within a package, in order to obtain 3D images of the system with a spatial resolution of 8.7 µm all within a scan time of less than 3 min. Also shown are results from packages scanned in different orientations and a sectioned package for higher resolution imaging. In contrast a conventional CT system would take hours to record data with potentially poorer resolution. Indeed, the ratio of field-of-view to throughput time is much higher when using the synchrotron radiation tomography setup. The description below of the experimental setup can be implemented and adapted for use with many other multi-materials. PMID:27167469

  6. Development of the large-scale oligonucleotide chip for the diagnosis of plant viruses and its practical use.

    Science.gov (United States)

    Nam, Moon; Kim, Jeong-Seon; Lim, Seungmo; Park, Chung Youl; Kim, Jeong-Gyu; Choi, Hong-Soo; Lim, Hyoun-Sub; Moon, Jae Sun; Lee, Su-Heon

    2014-03-01

    A large-scale oligonucleotide (LSON) chip was developed for the detection of the plant viruses with known genetic information. The LSON chip contains two sets of 3,978 probes for 538 species of targets including plant viruses, satellite RNAs and viroids. A hundred forty thousand probes, consisting of isolate-, species- and genus-specific probes respectively, are designed from 20,000 of independent nucleotide sequence of plant viruses. Based on the economic importance, the amount of genome information, and the number of strains and/or isolates, one to fifty-one probes for each target virus are selected and spotted on the chip. The standard and field samples for the analysis of the LSON chip have been prepared and tested by RT-PCR. The probe's specific and/or nonspecific reaction patterns by LSON chip allow us to diagnose the unidentified viruses. Thus, the LSON chip in this study could be highly useful for the detection of unexpected plant viruses, the monitoring of emerging viruses and the fluctuation of the population of major viruses in each plant. PMID:25288985

  7. Sacrificial Microchannel Sealing by Glass-Frit Reflow for Chip Scale Atomic Magnetometer

    Science.gov (United States)

    Tsujimoto, Kazuya; Hirai, Yoshikazu; Sugano, Koji; Tsuchiya, Toshiyuki; Tabata, Osamu

    A novel sealing technique using sacrificial microchannels was proposed for atmosphere control in a micromachined alkali gas-filled cell for a chip scale atomic magnetometer. The microchannels act as feedthrough connecting the cell to outside atmosphere during evacuation and gas-filling steps, and eventually they are sealed by glass-frit reflow. Si microchannel dedicated as a sacrificial microchannel was proposed and its feasibility was successfully demonstrated by experiments. The simulation results clarified the glass-frit reflow characteristics and its dependence on cross-sectional shape of the microchannel. Hermeticity of the proposed sealing technique of less than 10-12Pa·m3/s leak rate was verified by a high resolution helium leak test.

  8. Review of chip-scale atomic clocks based on coherent population trapping

    International Nuclear Information System (INIS)

    Research on chip-scale atomic clocks (CSACs) based on coherent population trapping (CPT) is reviewed. The background and the inspiration for the research are described, including the important schemes proposed to improve the CPT signal quality, the selection of atoms and buffer gases, and the development of micro-cell fabrication. With regard to the reliability, stability, and service life of the CSACs, the research regarding the sensitivity of the CPT resonance to temperature and laser power changes is also reviewed, as well as the CPT resonance's collision and light of frequency shifts. The first generation CSACs have already been developed but its characters are still far from our expectations. Our conclusion is that miniaturization and power reduction are the most important aspects calling for further research. (review)

  9. Chip-scale fully reconfigurable optical add/drop multiplexing subsystem in polymer microphotonic circuits

    Science.gov (United States)

    Izuhara, Tomoyuki; Fujita, Junichiro; Radojevic, Antonije; Gerhardt, Reinald; Eldada, Louay A.

    2004-10-01

    We report on a highly integrated photonic circuit using a polymer-based planar waveguide system. The properties of the materials used in this work such as ultra-low optical loss, widely tunable refractive index, and large thermo-optic coefficient, enable a multi-functional chip-scale microphotonic circuit. We discuss the application of this technology to the fabrication of a fully reconfigurable optical add/drop multiplexer. This subsystem includes channel switching, power monitoring, load balancing, and wavelength shuffling functionalities that are required for agile wavelength-division multiplexing optical networks. Optical properties of our material systems and performance characteristics of the implemented optical passive/active elements are presented, and the integration schemes of the devices to achieve a fully integrated reconfigurable optical add/drop multiplexer are discussed.

  10. A magnetic bead-integrated chip for the large scale manufacture of normalized esiRNAs.

    Directory of Open Access Journals (Sweden)

    Zhao Wang

    Full Text Available The chemically-synthesized siRNA duplex has become a powerful and widely used tool for RNAi loss-of-function studies, but suffers from a high off-target effect problem. Recently, endoribonulease-prepared siRNA (esiRNA has been shown to be an attractive alternative due to its lower off-target effect and cost effectiveness. However, the current manufacturing method for esiRNA is complicated, mainly in regards to purification and normalization on a large-scale level. In this study, we present a magnetic bead-integrated chip that can immobilize amplification or transcription products on beads and accomplish transcription, digestion, normalization and purification in a robust and convenient manner. This chip is equipped to manufacture ready-to-use esiRNAs on a large-scale level. Silencing specificity and efficiency of these esiRNAs were validated at the transcriptional, translational and functional levels. Manufacture of several normalized esiRNAs in a single well, including those silencing PARP1 and BRCA1, was successfully achieved, and the esiRNAs were subsequently utilized to effectively investigate their synergistic effect on cell viability. A small esiRNA library targeting 68 tyrosine kinase genes was constructed for a loss-of-function study, and four genes were identified in regulating the migration capability of Hela cells. We believe that this approach provides a more robust and cost-effective choice for manufacturing esiRNAs than current approaches, and therefore these heterogeneous RNA strands may have utility in most intensive and extensive applications.

  11. Wafer-level packaging and laser bonding as an approach for silicon-into-lab-on-chip integration

    International Nuclear Information System (INIS)

    A novel approach for the integration of silicon biosensors into microfluidics is presented. Our approach is based on wafer-level packaging of the silicon die and a laser-bonding process of the resulting mold package into a polymer-multilayer stack. The introduction of a flexible and 40 μm thin hot melt foil as an intermediate layer enables laser bonding between materials with different melting temperatures, where standard laser welding processes cannot be employed. All process steps are suitable for mass production, e.g. the approach does not involve any dispensing steps for glue or underfiller. The integration approach was demonstrated and evaluated regarding process technology by wafer-level redistribution of daisy chain silicon dies representing a generic biosensor. Electrical connection was successfully established and laser-bonding tensile strength of 5.7 N mm−2 and burst pressure of 587 kPa at a temperature of 100 °C were achieved for the new material combination. The feasibility of the complete packaging approach was shown by the fabrication of a microfluidic flow cell with embedded mold package. (paper)

  12. Electrical performance analysis of IC package for the high-end memory device

    Science.gov (United States)

    Lee, Dong H.; Han, Chan M.

    1997-08-01

    The developments of processing technology and design make it possible to increase the clock speed and the number of input outputs (I/Os) in memory devices. The interconnections of IC package are considered as an important factor to decide the performance of the memory devices. In order to overcome the limitations of the conventional package, new types of package such as Ball Grid Array (BGA), chip scale package or flip chip bonding are adopted by many IC manufacturers. The present work has compared the electrical performances of 3 different packages to provide deign guide for IC packages of the high performance memory devices in the future. Those packages are designed for the same memory devices to confront to the diversity of memory market demand. The conventional package using lead frame, wire bonded BGA using printed circuit board substrate and flip chip bonded BGA are analyzed. Their electrical performances are compared in the area of signal delay and coupling effect between signal interconnections. The electrical package modeling is built by extracting parasitic of interconnections in IC package through electro-magnetic simulations. The electrical package modeling is built by extracting parasitic of interconnections in IC package through electro-magnetic simulations. The analysis of electrical behavior is performed using SPICE model which is made to represent the real situation. The methodology presented is also capable of determining the most suitable memory package for a particular device based on the electrical performance.

  13. Integrated chip-scale Si3N4 wavemeter with narrow free spectral range and high stability.

    Science.gov (United States)

    Xiang, Chao; Tran, Minh A; Komljenovic, Tin; Hulme, Jared; Davenport, Michael; Baney, Doug; Szafraniec, Bogdan; Bowers, John E

    2016-07-15

    We designed, fabricated, and characterized an integrated chip-scale wavemeter based on an unbalanced Mach-Zehnder interferometer with 300 MHz free spectral range. The wavemeter is realized in the Si3N4 platform, allowing for low loss with ∼62  cm of on-chip delay. We also integrated an optical hybrid to provide phase information. The main benefit of a fully integrated wavemeter, beside its small dimensions, is increased robustness to vibrations and temperature variations and much improved stability over fiber-based solutions. PMID:27420522

  14. Thermal chip fabrication with arrays of sensors and heaters for micro-scale impingement cooling heat transfer analysis and measurements.

    Science.gov (United States)

    Shen, C H; Gau, C

    2004-07-30

    The design and fabrication for a thermal chip with an array of temperature sensors and heaters for study of micro-jet impingement cooling heat transfer process are presented. This thermal chip can minimize the heat loss from the system to the ambient and provide a uniform heat flux along the wall, thus local heat transfer processes along the wall can be measured and obtained. The fabrication procedure presented can reach a chip yield of 100%, and every one of the sensors and heaters on the chip is in good condition. In addition, micro-jet impingement cooling experiments are performed to obtain the micro-scale local heat transfer Nusselt number along the wall. Flow visualization for the micro-impinging jet is also made. The experimental results indicate that both the micro-scale impinging jet flow structure and the heat transfer process along the wall is significantly different from the case of large-scale jet impingement cooling process. PMID:15142582

  15. Development of a small-scale protope of the GOSSIPO-2 chip in 0.13 um CMOS technology

    CERN Document Server

    Kluit, R; Gromov, V

    2007-01-01

    The GOSSIP (Gas On Slimmed Silicon Pixel) detector is a proposed alternative for silicon based pixel detectors. The Gossip Prototype (GOSSIPO) chip is being developed to serve as a prototype read-out chip for such a gas-filled detector. Thanks to the very low capacitance at the preamplifier input, the front-end of the chip demonstrates low-noise performance in combination with a fast peaking time and low analog power dissipation. Measurement of the drift time of every primary electron in the gas volume enables 3D reconstruction of the particle tracks. For this purpose a Time-to- Digital converter must be placed in each pixel. A small-scale prototype of the GOSSIP chip has been developed in the 0.13 μm CMOS technology. The prototype includes a 16 by 16 pixel array where each pixel is equipped with a front-end circuit, threshold DAC, and a 4-bit TDC. The chip is available for testing in May 2007 and after initial tests it will be postprocessed to build a prototype detector. This paper describes the detector de...

  16. Chip integration using inkjet-printed silver conductive tracks reinforced by electroless plating for flexible board packages

    OpenAIRE

    Cauchois, Romain; Saadaoui, Mohamed; Legeleux, Jacques; Malia, Thierry; Dubois-Bonvalot, Béatrice; Inal, Karim; Fidalgo, Jean-Christophe

    2012-01-01

    International audience Inkjet-printing of interconnects is a maskless technology that has attracted great interest for printed electronics and packaging applications. Gemalto is expecting by motivated and developing skills and knowledge in this area to be at the forefront of European Security innovation and to answer to a continuous market pressure for higher security, lower cost and more secure complex systems. With an increasing need for flexible and mass deliveries of advanced secure pe...

  17. Wire-bonding on inkjet-printed silver pads reinforced by electroless plating for chip on flexible board packages

    OpenAIRE

    Cauchois, Romain; Saadaoui, Mohamed; Legeleux, Jacques; Malia, Thierry; Dubois-Bonvalot, Béatrice; Inal, Karim; Fidalgo, Jean-Christophe

    2010-01-01

    The nanoporous nature of the inkjet printed silver nanoparticles entail low hardness and surface effective contact area for being compatible with pads that are suitable for wire-bonding in electronic packaging. Electroless nickel plating is a selective metal deposition technique which can brings the required thickness and hardness for further pads processing. Here, a 1.7 μm thick nickel layer is deposited on top of 600 nm thick printed and sintered silver nanoparticles using Kapton polyimide ...

  18. Global review of open access risk assessment software packages valid for global or continental scale analysis

    Science.gov (United States)

    Daniell, James; Simpson, Alanna; Gunasekara, Rashmin; Baca, Abigail; Schaefer, Andreas; Ishizawa, Oscar; Murnane, Rick; Tijssen, Annegien; Deparday, Vivien; Forni, Marc; Himmelfarb, Anne; Leder, Jan

    2015-04-01

    -defined exposure and vulnerability. Without this function, many tools can only be used regionally and not at global or continental scale. It is becoming increasingly easy to use multiple packages for a single region and/or hazard to characterize the uncertainty in the risk, or use as checks for the sensitivities in the analysis. There is a potential for valuable synergy between existing software. A number of open source software packages could be combined to generate a multi-risk model with multiple views of a hazard. This extensive review has simply attempted to provide a platform for dialogue between all open source and open access software packages and to hopefully inspire collaboration between developers, given the great work done by all open access and open source developers.

  19. ''ALCESTE'', a hot cell for the full-scale low and intermediate level waste packages characterization and expert investigation

    International Nuclear Information System (INIS)

    In order to characterize radioactive waste packages, equipments have been developed in the CHICADE facility (Basic nuclear facility) which belong to the department of Radioactive Waste Storage and Disposal of the CEA Fuel Directory. One of the most recent equipment is the ALCESTE hot cell. This cell allows sampling extraction from large scale radioactive waste drums. Sampling may be carried out in homogeneous or heterogeneous wastes packages by dry coring or drilling techniques in hydraulic binder, concrete, bitumen or polymer materials. (authors)

  20. Pilot-scale studies of dried fish irradiation: Bulk packaging of irradiated dried fish

    International Nuclear Information System (INIS)

    Two methods of salting fresh chub mackerel (R. neglectus) were examined: dry salting and brine salting. With dry salting (and sun drying) moulding occurs after 1 month. Sorbate prevents moulding. Irradiation reduces the bacterial population. Best results are obtained with sorbate and radiation used in combination. The brine salting investigation was not completed at the time of writing. Packaging materials for study were selected on the basis of the physical protection that could be obtained and also cost. Based on drop tests, irradiation of polyethylene film with doses up to 10 kGy does not significantly affect tensile strength or tear resistance. Similar results were obtained with polypropylene woven cloth. Carton boxes were unchanged with doses up to 5 kGy. Carton boxes are more suitable than woven bags for large scale irradiation. (author). 2 figs, 12 tabs

  1. Small-Scale High Temperature Melter-1 (SSHTM-1) Data Package. Appendix A

    International Nuclear Information System (INIS)

    This appendix provides the data for Alternate HTM Flowsheet 1 (No Reductant Addition, Nitric Acid) melter feed preparation activities in both the laboratory and small-scale testing. The first section provides an outline of this appendix. The melter feed preparation data are presented in the next two main sections, laboratory welter feed preparation data and small-scale melter feed preparation data. Section 3.0 provides the laboratory data which is discussed in the main body of the Small-Scale High Temperature-1 (SSHTM-1) Data Package, milestone C95-02.02Y. Section 3.1 gives the flowsheet in outline form as used in the laboratory-scale tests. This section also includes the ''Laboratory Melter Feed Preparation Activity Log'' which gives a chronological account of the test in terms of time, temperature, slurry pH, and specific observations about slurry appearance, acid addition rates, and samples taken. The ''Laboratory Melter Feed Preparation Activity Log'' provides a road map to the reader by which all the activity and data from the laboratory can be easily accessed. A summary of analytical data is presented next, section 3.2, which covers starting materials and progresses to the analysis of the melter feed. The next section, 3.3, characterizes the off-gas generation that occurs during the slurry processing. The following section, 3.4, provides the rheology data gathered including gram waste oxide loading information for the various slurries tested. The final section, 3.5. includes data from standard crucible redox testing. Section 4.0 provides the small-scale data tn parallel form to section 3.0. Section 5.0 concludes with the references for this appendix

  2. Small-Scale High Temperature Melter-1 (SSHTM-1) Data Package. Appendix B

    International Nuclear Information System (INIS)

    This appendix provides the data for Alternate HTM Flowsheet 2 (Glycolic Acid) melter feed preparation activities in both the laboratory- and small-scale testing. The first section provides an outline of this appendix. The melter feed preparation data are presented in the next two main sections, laboratory melter feed preparation data and small-scale melter feed preparation data. Section 3.0 provides the laboratory data which is discussed in the main body of the Small-Scale High Temperature-1 (SSHTM-1) Data Package, milestone C95-02.02Y. Section 3.1 gives the flowsheet in outline form as used in the laboratory-scale tests. This section also includes the ''Laboratory Melter Feed Preparation Activity Log'' which gives A chronological account of the test in terms of time, temperature, slurry pH, and specific observations about slurry appearance, acid addition rates, and samples taken. The ''Laboratory Melter Feed Preparation Activity Log'' provides a road map to the reader by which all the activity and data from the laboratory can be easily accessed. A summary of analytical data is presented next, section 3.2, which covers starting materials and progresses to the analysis of the melter feed. The next section, 3.3, characterizes the off-gas generation that occurs during the slurry processing. The following section, 3.4, provides the rheology data gathered including gram waste oxide loading information for the various slurries tested. The final section, 3.5, includes data from standard crucible redox testing. Section 4.0 provides the small-scale data in parallel form to section 3.0. Section 5.0 concludes with the references for this appendix

  3. Small-Scale High Temperature Melter-1 (SSHTM-1) Data Package. Appendix B

    Energy Technology Data Exchange (ETDEWEB)

    NONE

    1996-03-01

    This appendix provides the data for Alternate HTM Flowsheet 2 (Glycolic Acid) melter feed preparation activities in both the laboratory- and small-scale testing. The first section provides an outline of this appendix. The melter feed preparation data are presented in the next two main sections, laboratory melter feed preparation data and small-scale melter feed preparation data. Section 3.0 provides the laboratory data which is discussed in the main body of the Small-Scale High Temperature-1 (SSHTM-1) Data Package, milestone C95-02.02Y. Section 3.1 gives the flowsheet in outline form as used in the laboratory-scale tests. This section also includes the ``Laboratory Melter Feed Preparation Activity Log`` which gives A chronological account of the test in terms of time, temperature, slurry pH, and specific observations about slurry appearance, acid addition rates, and samples taken. The ``Laboratory Melter Feed Preparation Activity Log`` provides a road map to the reader by which all the activity and data from the laboratory can be easily accessed. A summary of analytical data is presented next, section 3.2, which covers starting materials and progresses to the analysis of the melter feed. The next section, 3.3, characterizes the off-gas generation that occurs during the slurry processing. The following section, 3.4, provides the rheology data gathered including gram waste oxide loading information for the various slurries tested. The final section, 3.5, includes data from standard crucible redox testing. Section 4.0 provides the small-scale data in parallel form to section 3.0. Section 5.0 concludes with the references for this appendix.

  4. A broadband chip-scale optical frequency synthesizer at 2.7 × 10−16 relative uncertainty

    OpenAIRE

    Huang, Shu-Wei; Yang, Jinghui; Yu, Mingbin; McGuyer, Bart H.; Kwong, Dim-Lee; Zelevinsky, Tanya; Wong, Chee Wei

    2016-01-01

    Optical frequency combs—coherent light sources that connect optical frequencies with microwave oscillations—have become the enabling tool for precision spectroscopy, optical clockwork, and attosecond physics over the past decades. Current benchmark systems are self-referenced femtosecond mode-locked lasers, but Kerr nonlinear dynamics in high-Q solid-state microresonators has recently demonstrated promising features as alternative platforms. The advance not only fosters studies of chip-scale ...

  5. Development of 3D human intestinal equivalents for substance testing in microliter-scale on a multi-organ-chip

    OpenAIRE

    Jaenicke, Annika; Tordy, Dominique; Groeber, Florian; Hansmann, Jan; Nietzer, Sarah; Tripp, Carolin; Walles, Heike; Lauster, Roland; Marx, Uwe

    2013-01-01

    First published by BioMed Central: Jaenicke, Annika; Tordy, Dominique; Groeber, Florian; Hansmann, Jan; Nietzer, Sarah; Tripp, Carolin; Walles, Heike; Lauster, Roland; Marx, Uwe: Development of 3D human intestinal equivalents for substance testing in microliter-scale on a multi-organ-chip. - In: BMC Proceedings. - ISSN 1753-6561 (online). - 7 (2013), suppl. 6, P65. - doi:10.1186/1753-6561-7-S6-P65.

  6. High density packaging technology ultra thin package & new tab package

    Science.gov (United States)

    Nakagawa, Osamu; Shimamoto, Haruo; Ueda, Tetsuya; Shimomura, Kou; Hata, Tsutomu; Tachikawa, Toru; Fukushima, Jiro; Banjo, Toshinobu; Yamamoto, Isamu

    1989-09-01

    As electronic devices become more highly integrated, the demand for small, high pin count packages has been increasing. We have developed two new types of IC packages in response to this demand. One is an ultra thin small outline package (TSOP) which has been reduced in size from the standard SOP and the other, which uses Tape Automated Bonding (TAB) technology, is a super thin, high pin count TAB in cap (T.I.C.) package. In this paper, we present these packages and their features along with the technologies used to improve package reliability and TAB. Thin packages are vulnerable to high humidity exposure, especially after heat shock.1 The following items were therefore investigated in order to improve humidity resistance: (1) The molding compound thermal stress, (2) Water absorption into the molding compound and its effect on package cracking during solder dipping, (3) Chip attach pad area and its affect on package cracking, (4) Adhesion between molding resin and chip attach pad and its affect on humidity resistance. With the improvements made as a result of these investigations, the reliability of the new thin packages is similar to that of the standard thicker plastic packages.

  7. Thermal simulation for the chip model based on RCP package%基于RCP封装的芯片模型电热模拟

    Institute of Scientific and Technical Information of China (English)

    张路

    2015-01-01

    基于集成电路重分布封装技术(redistributed chip packaging,RCP)的发展,通过提取芯片封装体的具体参数,建立并优化了RCP芯片的热学模型.采用有限元的方法计算了该模型在一定热耗散功率下,施加不同风速条件时的温度分布情况,结果表明:强制对流条件的施加显著增强了RCP芯片封装体的散热能力,4m/s的风速可使其系统热阻降低58%,但是随着风速的增大,其影响不断减弱.所得出的具体风速与芯片结温的关系,可为RCP封装技术的散热设计提供有价值的参考.

  8. Development of Generalized Perturbation Theory Capability within the SCALE Code Package

    International Nuclear Information System (INIS)

    Computational capability has been developed to calculate sensitivity coefficients of generalized responses with respect to cross-section data in the SCALE code system. The focus of this paper is the implementation of generalized perturbation theory (GPT) for one-dimensional and two-dimensional deterministic neutron transport calculations. GPT is briefly summarized for computing sensitivity coefficients for reaction rate ratio responses within the existing framework of the TSUNAMI sensitivity and uncertainty (S/U) analysis code package in SCALE. GPT provides the capability to analyze generalized responses related to reactor analysis, such as homogenized cross-sections, relative powers, and conversion ratios, as well as measured experimental parameters such as 28 (epithermal/thermal 238U capture rates) in thermal benchmarks and fission ratios such as 239Pu(n,f)/235U(n,f) in fast benchmarks. The S/U analysis of these experimental integral responses can be used to augment the existing TSUNAMI S/U analysis capabilities for system similarity assessment and data adjustment. S/U analysis is provided for boiling water reactor pin cell as part of the Organization for Economic Cooperation and Development Uncertainty Analysis in Modeling benchmark.

  9. Development of generalized perturbation theory capability within the scale code package

    International Nuclear Information System (INIS)

    Computational capability has been developed to calculate sensitivity coefficients of generalized responses with respect to cross-section data in the SCALE code system. The focus of this paper is the implementation of generalized perturbation theory (GPT) for one-dimensional and two-dimensional deterministic neutron transport calculations. GPT is briefly summarized for computing sensitivity coefficients for reaction rate ratio responses within the existing framework of the TSUNAMI sensitivity and uncertainty (S/U) analysis code package in SCALE. GPT provides the capability to analyze generalized responses related to reactor analysis, such as homogenized cross-sections, relative powers, and conversion ratios, as well as measured experimental parameters such as 28ρ(epithermal/thermal 238U capture rates) in thermal benchmarks and fission ratios such as 239U(n,f)/235U(n,f) in fast benchmarks. The S/U analysis of these experimental integral responses can be used to augment the existing TSUNAMI S/U analysis capabilities for system similarity assessment and data adjustment. S/U analysis is provided for boiling water reactor pin cell as part of the Organization for Economic Cooperation and Development Uncertainty Analysis in Modeling benchmark. (authors)

  10. Comprehensive Investigation on Current Imbalance among Parallel Chips inside MW-Scale IGBT Power Modules

    DEFF Research Database (Denmark)

    Wu, Rui; Smirnova, Liudmila; Wang, Huai;

    2015-01-01

    With the demands for increasing the power rating and improving reliability level of the high power IGBT modules, there are further needs of understanding how to achieve stable paralleling and identical current sharing between the chips. This paper investigates the stray parameters imbalance among...... parallel chips inside the 1.7 kV/1 kA high power IGBT modules at different frequencies by Ansys Q3D parastics extractor. The resulted current imbalance is further confirmed by experimental measurement....

  11. Comprehensive Investigation on Current Imbalance among Parallel Chips inside MW-Scale IGBT Power Modules

    OpenAIRE

    Wu, Rui; Smirnova, Liudmila; Wang, Huai; Iannuzzo, Francesco; Blaabjerg, Frede

    2015-01-01

    With the demands for increasing the power rating and improving reliability level of the high power IGBT modules, there are further needs of understanding how to achieve stable paralleling and identical current sharing between the chips. This paper investigates the stray parameters imbalance among parallel chips inside the 1.7 kV/1 kA high power IGBT modules at different frequencies by Ansys Q3D parastics extractor. The resulted current imbalance is further confirmed by experimental measurement.

  12. ESTABLISHMENT OF DESIGN CRITERIA FOR OPTIMUM BURNERS FOR APPLICATION TO HEAVY FUEL FIRED PACKAGE BOILERS. VOLUME 2. PILOT SCALE TESTS

    Science.gov (United States)

    The report gives results of a research program to develop low-NOx heavy oil burners for application to industrial package boilers. Volume I documents Phase 1 of the program, bench scale studies which defined optimum conditions for two-stage combustion. The information led to a co...

  13. ESTABLISHMENT OF DESIGN CRITERIA FOR OPTIMUM BURNERS FOR APPLICATION TO HEAVY FUEL FIRED PACKAGE BOILERS. VOLUME 1. LABORATORY SCALE TESTS

    Science.gov (United States)

    The report gives results of a research program to develop low-NOx heavy oil burners for application to industrial package boilers. Volume I documents Phase 1 of the program, bench scale studies which defined optimum conditions for two-stage combustion. The information led to a co...

  14. Chip-Scale Bioassays Based on Surface-Enhanced Raman Scattering: Fundamentals and Applications

    Energy Technology Data Exchange (ETDEWEB)

    Hye-Young Park

    2005-12-17

    This work explores the development and application of chip-scale bioassays based on surface-enhanced Raman scattering (SERS) for high throughput and high sensitivity analysis of biomolecules. The size effect of gold nanoparticles on the intensity of SERS is first presented. A sandwich immunoassay was performed using Raman-labeled immunogold nanoparticles with various sizes. The SERS responses were correlated to particle densities, which were obtained by atomic force microscopy (AFM). The response of individual particles was also investigated using Raman-microscope and an array of gold islands on a silicon substrate. The location and the size of individual particles were mapped using AFM. The next study describes a low-level detection of Escherichia coli 0157:H7 and simulants of biological warfare agents in a sandwich immunoassay format using SERS labels, which have been termed Extrinsic Raman labels (ERLs). A new ERL scheme based on a mixed monolayer is also introduced. The mixed monolayer ERLs were created by covering the gold nanoparticles with a mixture of two thiolates, one thiolate for covalently binding antibody to the particle and the other thiolate for producing a strong Raman signal. An assay platform based on mixed self-assembled monolayers (SAMs) on gold is then presented. The mixed SAMs were prepared from dithiobis(succinimidyl undecanoate) (DSU) to covalently bind antibodies on gold substrate and oligo(ethylene glycol)-terminated thiol to prevent nonspecific adsorption of antibodies. After the mixed SAMs surfaces, formed from various mole fraction of DSU were incubated with antibodies, AFM was used to image individual antibodies on the surface. The final study presents a collaborative work on the single molecule adsorption of YOYO-I labeled {lambda}-DNA at compositionally patterned SAMs using total internal reflection fluorescence microscopy. The role of solution pH, {lambda}-DNA concentration, and domain size was investigated. This work also revealed

  15. Factor Analysis for Multiple Testing (FAMT: An R Package for Large-Scale Signi

    Directory of Open Access Journals (Sweden)

    David Causeur

    2011-05-01

    Full Text Available The R package FAMT (factor analysis for multiple testing provides a powerful method for large-scale significance testing under dependence. It is especially designed to select differentially expressed genes in microarray data when the correlation structure among gene expressions is strong. Indeed, this method reduces the negative impact of dependence on the multiple testing procedures by modeling the common information shared by all the variables using a factor analysis structure. New test statistics for general linear contrasts are deduced, taking advantage of the common factor structure to reduce correlation and consequently the variance of error rates. Thus, the FAMT method shows improvements with respect to most of the usual methods regarding the non discovery rate and the control of the false discovery rate (FDR. The steps of this procedure, each of them corresponding to R functions, are illustrated in this paper by two microarray data analyses. We first present how to import the gene ex- pression data, the covariates and gene annotations. The second step includes the choice of the optimal number of factors, the factor model fitting, and provides a list of selected genes according to a preset FDR control level. Finally, diagnostic plots are provided to help the user interpret the factors using available external information on either genes or arrays.

  16. Demonstration of structural performance of IP-2 packages by advanced analytical simulation and full-scale drop test

    International Nuclear Information System (INIS)

    Two new types of IP-2 (Industrial Package Type 2) to transport low and intermediate level radioactive waste (LILW) steel drums from nuclear power plants to a disposal facility have been developed in accordance with the IAEA and Korean regulations for radioactive materials. According to the regulations, both packages must preserve their structural performance after they are subjected to 0.9 m free drop tests, which are prescribed as normal conditions. In this study, an advanced analytical simulation and an evaluation process using the finite element (FE) method have been developed for the design assessment of the newly developed IP-2s. Then, analytical simulations for the various drop orientations were performed to evaluate the structural performance of the packages and demonstrate their compliance with the regulatory requirements. Also, full-scale drop tests were carried out to verify the numerical tools and modeling methodology used in the analyses and to confirm the performance of the IP-2s. In addition, parametric studies are carried out to investigate the sensitivity of the analytical variables, such as the material model and modeling methodology. In addition, this paper intends to provide basic guidance on the analytical simulation and evaluation process specifically for Korean types of transport packages, because numerous transport packages must now be developed for the various kinds of LILW that have accumulated in temporary storage facilities in Korea.

  17. Chip-scale fluorescence microscope based on a silo-filter complementary metal-oxide semiconductor image sensor.

    Science.gov (United States)

    Ah Lee, Seung; Ou, Xiaoze; Lee, J Eugene; Yang, Changhuei

    2013-06-01

    We demonstrate a silo-filter (SF) complementary metal-oxide semiconductor (CMOS) image sensor for a chip-scale fluorescence microscope. The extruded pixel design with metal walls between neighboring pixels guides fluorescence emission through the thick absorptive filter to the photodiode of a pixel. Our prototype device achieves 13 μm resolution over a wide field of view (4.8 mm × 4.4 mm). We demonstrate bright-field and fluorescence longitudinal imaging of living cells in a compact, low-cost configuration. PMID:23722754

  18. Atom Chips

    CERN Document Server

    Folman, R; Cassettari, D; Hessmo, B; Maier, T; Schmiedmayer, J; Folman, Ron; Krüger, Peter; Cassettari, Donatella; Hessmo, Björn; Maier, Thomas

    1999-01-01

    Atoms can be trapped and guided using nano-fabricated wires on surfaces, achieving the scales required by quantum information proposals. These Atom Chips form the basis for robust and widespread applications of cold atoms ranging from atom optics to fundamental questions in mesoscopic physics, and possibly quantum information systems.

  19. Factor Analysis for Multiple Testing (FAMT): An R Package for Large-Scale Significance Testing under Dependence

    OpenAIRE

    Causeur, David; Friguet, Chloé; Houee-Bigot, Magali; Kloareg, Maela

    2011-01-01

    The R package FAMT (factor analysis for multiple testing) provides a powerful method for large-scale significance testing under dependence. It is especially designed to select differentially expressed genes in microarray data when the correlation structure among gene expressions is strong. Indeed, this method reduces the negative impact of dependence on the multiple testing procedures by modeling the common information shared by all the variables using a factor analysis structure. New test st...

  20. Inducible packaging cells for large-scale production of lentiviral vectors in serum-free suspension culture.

    Science.gov (United States)

    Broussau, Sophie; Jabbour, Nadine; Lachapelle, Guillaume; Durocher, Yves; Tom, Rosanne; Transfiguracion, Julia; Gilbert, Rénald; Massie, Bernard

    2008-03-01

    We have developed new packaging cell lines (293SF-PacLV) that can produce lentiviral vectors (LVs) in serum-free suspension cultures. A cell line derived from 293SF cells, expressing the repressor (CymR) of the cumate switch and the reverse transactivator (rtTA2(S)-M2) of the tetracycline (Tet) switch, was established first. We next generated clones stably expressing the Gag/Pol and Rev genes of human immunodeficiency virus-1, and the glycoprotein of vesicular stomatitis virus (VSV-G). Expression of Rev and VSV-G was tightly regulated by the cumate and Tet switches. Our best packaging cells produced up to 2.6 x 10(7) transducing units (TU)/ml after transfection with the transfer vector. Up to 3.4 x 10(7) TU/ml were obtained using stable producers generated by transducing the packaging cells with conditional-SIN-LV. The 293SF-PacLV was stable, as shown by the fact that some producers maintained high-level LV production for 18 weeks without selective pressure. The utility of the 293SF-PacLV for scaling up production in serum-free medium was demonstrated in suspension cultures and in a 3.5-L bioreactor. In shake flasks, the best packaging cells produced between 3.0 and 8.0 x 10(6) TU/ml/day for 3 days, and the best producer cells, between 1.0 and 3.4 x 10(7) TU/ml/day for 5 days. In the bioreactor, 2.8 liters containing 2.0 x 10(6) TU/ml was obtained after 3 days of batch culture following the transfection of packaging cells. In summary, the 293SF-PacLV possesses all the attributes necessary to become a valuable tool for scaling up LV production for preclinical and clinical applications. PMID:18180776

  1. A broadband chip-scale optical frequency synthesizer at 2.7 × 10−16 relative uncertainty

    Science.gov (United States)

    Huang, Shu-Wei; Yang, Jinghui; Yu, Mingbin; McGuyer, Bart H.; Kwong, Dim-Lee; Zelevinsky, Tanya; Wong, Chee Wei

    2016-01-01

    Optical frequency combs—coherent light sources that connect optical frequencies with microwave oscillations—have become the enabling tool for precision spectroscopy, optical clockwork, and attosecond physics over the past decades. Current benchmark systems are self-referenced femtosecond mode-locked lasers, but Kerr nonlinear dynamics in high-Q solid-state microresonators has recently demonstrated promising features as alternative platforms. The advance not only fosters studies of chip-scale frequency metrology but also extends the realm of optical frequency combs. We report the full stabilization of chip-scale optical frequency combs. The microcomb’s two degrees of freedom, one of the comb lines and the native 18-GHz comb spacing, are simultaneously phase-locked to known optical and microwave references. Active comb spacing stabilization improves long-term stability by six orders of magnitude, reaching a record instrument-limited residual instability of 3.6mHz/τ. Comparing 46 nitride frequency comb lines with a fiber laser frequency comb, we demonstrate the unprecedented microcomb tooth-to-tooth relative frequency uncertainty down to 50 mHz and 2.7 × 10−16, heralding novel solid-state applications in precision spectroscopy, coherent communications, and astronomical spectrography. PMID:27152341

  2. A broadband chip-scale optical frequency synthesizer at 2.7 × 10(-16) relative uncertainty.

    Science.gov (United States)

    Huang, Shu-Wei; Yang, Jinghui; Yu, Mingbin; McGuyer, Bart H; Kwong, Dim-Lee; Zelevinsky, Tanya; Wong, Chee Wei

    2016-04-01

    Optical frequency combs-coherent light sources that connect optical frequencies with microwave oscillations-have become the enabling tool for precision spectroscopy, optical clockwork, and attosecond physics over the past decades. Current benchmark systems are self-referenced femtosecond mode-locked lasers, but Kerr nonlinear dynamics in high-Q solid-state microresonators has recently demonstrated promising features as alternative platforms. The advance not only fosters studies of chip-scale frequency metrology but also extends the realm of optical frequency combs. We report the full stabilization of chip-scale optical frequency combs. The microcomb's two degrees of freedom, one of the comb lines and the native 18-GHz comb spacing, are simultaneously phase-locked to known optical and microwave references. Active comb spacing stabilization improves long-term stability by six orders of magnitude, reaching a record instrument-limited residual instability of [Formula: see text]. Comparing 46 nitride frequency comb lines with a fiber laser frequency comb, we demonstrate the unprecedented microcomb tooth-to-tooth relative frequency uncertainty down to 50 mHz and 2.7 × 10(-16), heralding novel solid-state applications in precision spectroscopy, coherent communications, and astronomical spectrography. PMID:27152341

  3. Submission of the First Full Scale Prototype Chip for Upgraded ATLAS Pixel Detector at LHC, FE-I4A

    CERN Document Server

    Barbero, M; The ATLAS collaboration; Beccherle, R; Darbo, G; Dube, S; Elledge, D; Fleury, J; Fougeron, D; Garcia-Sciveres, M; Gensolen, F; Gnani, D; Gromov, V; Jensen, F; Hemperek, T; Karagounis, M; Kluit, R; Kruth, A; Mekkaoui, A; Menouni, M; Schipper, JD; Wermes, N; Zivkovic, V

    2010-01-01

    A new ATLAS pixel chip FE-I4 is being developed for use in upgraded LHC luminosity environments, including the near-term Insertable B-Layer (IBL) upgrade. FE-I4 is designed in a 130nm CMOS technology, presenting advantages in terms of radiation tolerance and digital logic density compared to the 250nm CMOS technology used for the current ATLAS pixel IC, FE-I3. The FE-I4 architecture is based on an array of 80x336 pixels, each 50x250um^2, consisting of analog and digital sections. In the summer 2010, a first full scale prototype FE-I4A was submitted for an engineering run. This IC features the full scale pixel array as well as the complex periphery of the future full-size FE-I4. The FE-I4A contains also various extra test features which should prove very useful for the chip characterization, but deviate from the needs for standard operation of the final FE-I4 for IBL. In this paper, focus will be brought to the various features implemented in the FE-I4A submission, while also underlining the main differences b...

  4. Large-scale analysis of antisense transcription in wheat using the Affymetrix GeneChip Wheat Genome Array

    Directory of Open Access Journals (Sweden)

    Settles Matthew L

    2009-05-01

    Full Text Available Abstract Background Natural antisense transcripts (NATs are transcripts of the opposite DNA strand to the sense-strand either at the same locus (cis-encoded or a different locus (trans-encoded. They can affect gene expression at multiple stages including transcription, RNA processing and transport, and translation. NATs give rise to sense-antisense transcript pairs and the number of these identified has escalated greatly with the availability of DNA sequencing resources and public databases. Traditionally, NATs were identified by the alignment of full-length cDNAs or expressed sequence tags to genome sequences, but an alternative method for large-scale detection of sense-antisense transcript pairs involves the use of microarrays. In this study we developed a novel protocol to assay sense- and antisense-strand transcription on the 55 K Affymetrix GeneChip Wheat Genome Array, which is a 3' in vitro transcription (3'IVT expression array. We selected five different tissue types for assay to enable maximum discovery, and used the 'Chinese Spring' wheat genotype because most of the wheat GeneChip probe sequences were based on its genomic sequence. This study is the first report of using a 3'IVT expression array to discover the expression of natural sense-antisense transcript pairs, and may be considered as proof-of-concept. Results By using alternative target preparation schemes, both the sense- and antisense-strand derived transcripts were labeled and hybridized to the Wheat GeneChip. Quality assurance verified that successful hybridization did occur in the antisense-strand assay. A stringent threshold for positive hybridization was applied, which resulted in the identification of 110 sense-antisense transcript pairs, as well as 80 potentially antisense-specific transcripts. Strand-specific RT-PCR validated the microarray observations, and showed that antisense transcription is likely to be tissue specific. For the annotated sense

  5. A wafer-scale packaging structure with monolithic microwave integrated circuits and passives embedded in a silicon substrate for multichip modules for radio frequency applications

    International Nuclear Information System (INIS)

    A wafer-level packaging structure with chips and passive components embedded in a silicon substrate for multichip modules (MCM) is proposed for radio frequency (RF) applications. The packaging structure consists of two layers of benzocyclobutene (BCB) films and three layers of metalized films, in which the monolithic microwave ICs (MMICs), thin film resistors, striplines and microstrip lines are integrated. The low resistivity silicon wafer with etched cavities is used as a substrate. The BCB films serve as interlayer dielectrics (ILDs). Wirebonding gold bumps are used as electric interconnections between different layers, which eliminate the need of preparing vias by costly procedures including dry etching, metal sputtering and electroplating. The chemical mechanical planarization (CMP) is used to uncover the gold bumps, and the BCB curing profile is optimized to obtain the appropriate BCB film for CMP process. In this work, the thermal, mechanical, electrical as well as RF properties of the packaging structure are investigated. The packaging thermal resistance can be controlled below 2 °C W−1. The average shear strength of the gold bumps on the BCB surface is about 70 MPa. In addition, a Kelvin test structure is fabricated for resistance testing of the vertical vias. The performances of MMIC and interconnection structure at high frequency are simulated and tested. The testing results reveal that the slight shifting of S-parameter curves of the packaged MMIC indicates perfect transmission characteristics at high frequency. For the transition structure of transmission line, the experimental results are compatible with the simulation results. The insertion loss (S21) is below 0.4 dB from 0 to 40 GHz and the return loss (S11) is less than −20 dB from 0 to 40 GHz. For a low noise amplifier (LNA) chip, the S21 shifting caused by the packaging structure is below 0.5 dB, and S11 is less than −10 dB from 8 GHz to 14 GHz

  6. On-chip photonic interconnects a computer architect's perspective

    CERN Document Server

    Nitta, Christopher J; Akella, Venkatesh

    2013-01-01

    As the number of cores on a chip continues to climb, architects will need to address both bandwidth and power consumption issues related to the interconnection network. Electrical interconnects are not likely to scale well to a large number of processors for energy efficiency reasons, and the problem is compounded by the fact that there is a fixed total power budget for a die, dictated by the amount of heat that can be dissipated without special (and expensive) cooling and packaging techniques. Thus, there is a need to seek alternatives to electrical signaling for on-chip interconnection appli

  7. Three-Dimensional Architecture at Chip Level for Large-Scale-Integration of Superconducting Quantum Electronic Devices

    Science.gov (United States)

    Göppl, Martin; Kurpiers, Philipp; Wallraff, Andreas

    We propose a novel way to realize three-dimensional circuit QED systems at chip level. System components such as qubits, transmission lines, capacitors, inductors or cross-overs can be implemented as suspended, electromagnetically shielded and optionally, as hermetically sealed structures. Compared to known state-of-the-art devices, volumes of dielectrics penetrated by electromagnetic fields can be drastically reduced. Our intention is to harness process technologies for very-large-scale-integration, reliably applied and improved over decades in micro-sensor- and semiconductor industry, for the realization of highly integrated circuit QED systems. Process capabilities are demonstrated by fabricating first exploratory devices using the back-end-of-line part of a commercial 180 nm CMOS foundry process in conjunction with HF vapor phase release etching.

  8. Fully Streched Single DNA Molecules in a Nanofluidic Chip Show Large-Scale Structural Variation

    DEFF Research Database (Denmark)

    Pedersen, Jonas Nyvold; Marie, Rodolphe; Bauer, D. L.;

    2013-01-01

    When stretching and imaging DNA molecules in nanofluidic devices, it is important to know the relation between the physical length as measured in the lab and the distance along the contour of the DNA. Here a single DNA molecule longer than 1 Mbp is loaded into a nanofluidic device consisting of two...... the contour length of the DNA, and (iii) without having the full DNA molecule inside the field-of-view. The analysis is based on the transverse motion of the DNA due its Brownian motion, i.e. the DNA's response to the thermal fluctuations of the liquid surrounding it. The parameter values obtained by fitting...... reflects the local AT/GC-content. Single molecules are loaded into the chip and imaged. Due to the almost complete stretching of the DNA, structural variations in the size range from kbp to Mbp can be detected and quantified from the melting pattern alone....

  9. Infrared vertically-illuminated photodiode for chip alignment feedback

    CERN Document Server

    Alloatti, Luca

    2016-01-01

    We report on vertically-illuminated photodiodes fabricated in the GlobalFoundries 45nm 12SOI node and on a packaging concept for optically-interconnected chips. The photodiodes are responsive at 1180 nm, a wavelength currently used in chip-to-chip communications. They have further a wide field-of-view which enables chip-to-board positional feedback in chip-board assemblies. Monolithic integration enables on-chip processing of the positional data.

  10. Physics of Failure Analysis of Xilinx Flip Chip CCGA Packages: Effects of Mission Environments on Properties of LP2 Underfill and ATI Lid Adhesive Materials

    Science.gov (United States)

    Suh, Jong-ook

    2013-01-01

    The Xilinx Virtex 4QV and 5QV (V4 and V5) are next-generation field-programmable gate arrays (FPGAs) for space applications. However, there have been concerns within the space community regarding the non-hermeticity of V4/V5 packages; polymeric materials such as the underfill and lid adhesive will be directly exposed to the space environment. In this study, reliability concerns associated with the non-hermeticity of V4/V5 packages were investigated by studying properties and behavior of the underfill and the lid adhesvie materials used in V4/V5 packages.

  11. Very large scale heterogeneous integration (VLSHI) and wafer-level vacuum packaging for infrared bolometer focal plane arrays

    Science.gov (United States)

    Forsberg, Fredrik; Roxhed, Niclas; Fischer, Andreas C.; Samel, Björn; Ericsson, Per; Hoivik, Nils; Lapadatu, Adriana; Bring, Martin; Kittilsland, Gjermund; Stemme, Göran; Niklaus, Frank

    2013-09-01

    Imaging in the long wavelength infrared (LWIR) range from 8 to 14 μm is an extremely useful tool for non-contact measurement and imaging of temperature in many industrial, automotive and security applications. However, the cost of the infrared (IR) imaging components has to be significantly reduced to make IR imaging a viable technology for many cost-sensitive applications. This paper demonstrates new and improved fabrication and packaging technologies for next-generation IR imaging detectors based on uncooled IR bolometer focal plane arrays. The proposed technologies include very large scale heterogeneous integration for combining high-performance, SiGe quantum-well bolometers with electronic integrated read-out circuits and CMOS compatible wafer-level vacuum packing. The fabrication and characterization of bolometers with a pitch of 25 μm × 25 μm that are arranged on read-out-wafers in arrays with 320 × 240 pixels are presented. The bolometers contain a multi-layer quantum well SiGe thermistor with a temperature coefficient of resistance of -3.0%/K. The proposed CMOS compatible wafer-level vacuum packaging technology uses Cu-Sn solid-liquid interdiffusion (SLID) bonding. The presented technologies are suitable for implementation in cost-efficient fabless business models with the potential to bring about the cost reduction needed to enable low-cost IR imaging products for industrial, security and automotive applications.

  12. Advanced organics for electronic substrates and packages

    CERN Document Server

    Fletcher, Andrew E

    1992-01-01

    Advanced Organics for Electronic Substrates and Packages provides information on packaging, which is one of the most technologically intensive activities in the electronics industry. The electronics packaging community has realized that while semiconductor devices continue to be improved upon for performance, cost, and reliability, it is the interconnection or packaging of these devices that will limit the performance of the systems. Technology must develop packaging for transistor chips, with high levels of performance and integration providing cooling, power, and interconnection, and yet pre

  13. Wafer-level scale package of MEMS device by eutectic bonding method

    Science.gov (United States)

    Chen, Sihai; Ma, Hong; Chen, Mingxiang; Xiong, Tao; Liu, Sheng; Yi, Xinjian

    2004-01-01

    This paper reports the preliminary results for an on-going program in wafer-level MEMS package. In this particular paper, three closed-loop microheaters of 5μm, 7μm and 9μm width were designed. By reactive ion sputtering technique, two classes of samples were presented. The first one was first co-sputtered with nickel / chromium (Ni/Cr) alloy and then sputtered with gold(Au) metal as heating material; the second one was sputtered with Cr, tin (Sn) and Au respectively as heating material. The bonding of the former sample based on the Ni/Cr and Au heating material failed. The eutectic bonding experiment of the later sample based on the Cr, Sn and Au heating material by global heating method was completed in annealing oven at temperature of about 400 deg. C. for 20 minutes. The SEM testing result showed the eutectic bonding of Au-Sn by global heating was successful. More results will be reported in future.

  14. Wafer-level-scale package of MEMS device by eutectic bonding method

    Science.gov (United States)

    Chen, Sihai; Ma, Hong; Chen, Mingxiang; Xiong, Tao; Liu, Sheng; Yi, Xinjian

    2003-12-01

    This paper reports the preliminary results for an on-going program in wafer-level MEMS package. In this particular paper, three closed-loop microheaters of 5μm, 7μm and 9μm width were designed. By reactive ion sputtering technique, two classes of samples were presented. The first one was first co-sputtered with nickel / chromium (Ni/Cr) alloy and then sputtered with gold(Au) metal as heating material; the second one was sputtered with Cr, tin (Sn) and Au respectively as heating material. The bonding of the former sample based on the Ni/Cr and Au heating material failed. The eutectic bonding experiment of the later sample based on the Cr, Sn and Au heating material by global heating method was completed in annealing oven at temperature of about 400 for 20 minutes. The SEM testing result showed the eutectic bonding of Au-Sn by global heating was successful. More results will be reported in future.

  15. Novel on chip-interconnection structures for giga-scale integration VLSI ICS

    Science.gov (United States)

    Nelakuditi, Usha R.; Reddy, S. N.

    2013-01-01

    Based on the guidelines of International Technology Roadmap for Semiconductors (ITRS) Intel has already designed and manufactured the next generation product of the Itanium family containing 1.72 billion transistors. In each new technology due to scaling, individual transistors are becoming smaller and faster, and are dissipating low power. The main challenge with these systems is wiring of these billion transistors since wire length interconnect scaling increases the distributed resistance-capacitance product. In addition, high clock frequencies necessitate reverse scaling of global and semi-global interconnects so that they satisfy the timing constraints. Hence, the performances of future GSI systems will be severely restricted by interconnect performance. It is therefore essential to look at interconnect design techniques that will reduce the impact of interconnect networks on the power, performance and cost of the entire system. In this paper a new routing technique called Wave-Pipelined Multiplexed (WPM) Routing similar to Time Division Multiple Access (TDMA) is discussed. This technique is highly useful for the current high density CMOS VLSI ICs. The major advantages of WPM routing technique are flexible, robust, simple to implement, and realized with low area, low power and performance overhead requirements.

  16. GRASP92: a package for large-scale relativistic atomic structure calculations

    Science.gov (United States)

    Parpia, F. A.; Froese Fischer, C.; Grant, I. P.

    2006-12-01

    Program summaryTitle of program: GRASP92 Catalogue identifier: ADCU_v1_1 Program summary URL:http://cpc.cs.qub.ac.uk/summaries/ADCU_v1_1 Program obtainable from: CPC Program Library, Queen's University of Belfast, N. Ireland Licensing provisions: no Programming language used: Fortran Computer: IBM POWERstation 320H Operating system: IBM AIX 3.2.5+ RAM: 64M words No. of lines in distributed program, including test data, etc.: 65 224 No of bytes in distributed program, including test data, etc.: 409 198 Distribution format: tar.gz Catalogue identifier of previous version: ADCU_v1_0 Journal reference of previous version: Comput. Phys. Comm. 94 (1996) 249 Does the new version supersede the previous version?: Yes Nature of problem: Prediction of atomic spectra—atomic energy levels, oscillator strengths, and radiative decay rates—using a 'fully relativistic' approach. Solution method: Atomic orbitals are assumed to be four-component spinor eigenstates of the angular momentum operator, j=l+s, and the parity operator Π=βπ. Configuration state functions (CSFs) are linear combinations of Slater determinants of atomic orbitals, and are simultaneous eigenfunctions of the atomic electronic angular momentum operator, J, and the atomic parity operator, P. Lists of CSFs are either explicitly prescribed by the user or generated from a set of reference CSFs, a set of subshells, and rules for deriving other CSFs from these. Approximate atomic state functions (ASFs) are linear combinations of CSFs. A variational functional may be constructed by combining expressions for the energies of one or more ASFs. Average level (AL) functionals are weighted sums of energies of all possible ASFs that may be constructed from a set of CSFs; the number of ASFs is then the same as the number, n, of CSFs. Optimal level (OL) functionals are weighted sums of energies of some subset of ASFs; the GRASP92 package is optimized for this latter class of functionals. The composition of an ASF in terms

  17. Mechanically Flexible Active Silicon Chips and Systems Project

    Data.gov (United States)

    National Aeronautics and Space Administration — Using innovative chip thinning technology married with recently available packaging technology, this effort will produce Mechanically Flexible Multifunctional...

  18. High-performance semiconductor optical amplifier array for self-aligned packaging using Si V-groove flip-chip technique

    Science.gov (United States)

    Leclerc, D.; Brosson, P.; Pommereau, F.; Ngo, R.; Doussiere, P.; Mallecot, F.; Gavignet, P.; Wamsler, I.; Laube, G.; Hunziker, W.

    1995-05-01

    A high performance four-tilted stripe semiconductor optical amplifier array, with low polarization sensitivity and very low-gain ripple, compatible with self-aligned flip-chip mounting on a Si motherboard is reported. Up to 32 dB of internal gain with 2-dB polarization sensitivity is obtained. A multifiber module has been realized, following an almost static optical alignment procedure, showing no degradation of the SOA array performances. Fiber-to-fiber gain, measured on the four stripes, is 14.4 +/- 1.3 dB with a gain ripple below +/- 0.1 dB.

  19. Efficient large volume electroporation of dendritic cells through micrometer scale manipulation of flow in a disposable polymer chip

    DEFF Research Database (Denmark)

    Selmeczi, Dávid; Hansen, Thomas Steen; Met, Özcan; Svane, Inge Marie; Larsen, Niels Bent

    2011-01-01

    We present a hybrid chip of polymer and stainless steel designed for high-throughput continuous electroporation of cells in suspension. The chip is constructed with two parallel stainless steel mesh electrodes oriented perpendicular to the liquid flow. The relatively high hydrodynamic resistance of...... performance of the chip is similar to that of the traditional electroporation cuvette, but without an upper limit on the number of cells to be electroporated. The device is constructed with two female Luer parts and can easily be integrated with other microfluidic components. Furthermore it is fabricated from...... injection molded polymer parts and commercially available stainless steel mesh, making it suitable for inexpensive mass production....

  20. Real-Time Very Large-Scale Integration Recognition System with an On-Chip Adaptive K-Means Learning Algorithm

    Science.gov (United States)

    Hou, Zuoxun; Ma, Yitao; Zhu, Hongbo; Zheng, Nanning; Shibata, Tadashi

    2013-04-01

    A very large-scale integration (VLSI) recognition system equipped with an on-chip learning capability has been developed for real-time processing applications. This system can work in two functional modes of operation: adaptive K-means learning mode and recognition mode. In the adaptive K-means learning mode, the variance ratio criterion (VRC) has been employed to evaluate the quality of K-means classification results, and the evaluation algorithm has been implemented on the chip. As a result, it has become possible for the system to autonomously determine the optimum number of clusters (K). In the recognition mode, the nearest-neighbor search algorithm is very efficiently carried out by the fully parallel architecture employed in the chip. In both modes of operation, many hardware resources are shared and the functionality is flexibly altered by the system controller designed as a finite-state machine (FSM). The chip is implemented on Altera Cyclone II FPGA with 46K logic cells. Its operating clock is 25 MHz and the processing times for adaptive learning and recognition with 256 64-dimension feature vectors are about 0.42 ms and 4 µs, respectively. Both adaptive K-means learning and recognition functions have been verified by experiments using the image data from the COIL-100 (Columbia University Object Image Library) database.

  1. Key of Packaged Grain Quantity Recognition - - Research on Processing and Describing of "fish and Describing of "fish Scale Body"

    Science.gov (United States)

    Lin, Ying; Fang, Xinglin; Sun, Yueheng; Sun, Yanhong

    The key to identifying the packaged grain is the shape of package, and the key to identifying shape is processing and describing the boundary of package. Based on a lot of analysis and experiment, this article select the canny operator and chain code to process and describe the boundary of package. Aiming at the boundary is not absolute connectivity, the closure operation of Mathematical Morphology is introduced to do pretreatment on binary image of packaged grain. Finally the boundary is absolute connectivity. Experiments show that the proposed method enhances the anti-jamming and robustness of edge detection.

  2. Packaging a liquid metal ESD with micro-scale Mercury droplet.

    Energy Technology Data Exchange (ETDEWEB)

    Barnard, Casey Anderson

    2011-08-01

    A liquid metal ESD is being developed to provide electrical switching at different acceleration levels. The metal will act as both proof mass and electric contact. Mercury is chosen to comply with operation parameters. There are many challenges surrounding the deposition and containment of micro scale mercury droplets. Novel methods of micro liquid transfer are developed to deliver controllable amounts of mercury to the appropriate channels in volumes under 1 uL. Issues of hermetic sealing and avoidance of mercury contamination are also addressed.

  3. Modeling of shielding benchmark for Na-24 γ-rays using scale code package and QAD-CGGP code

    International Nuclear Information System (INIS)

    The benchmark data were recently published for 1.37 and 2.75 MeV photons emitted by an Na-24 uniform disc source penetrating shields of six two-layer combinations, namely, 12''Al+Fe, 12''+Pb, 6''Fe+Al, 6''Fe+Pb, 4''Pb+Al, and 4''Pb+Fe. These benchmark data fill a gap in the energy range of practical interest and provide useful reference values for computational method evaluation. In order to evaluate the computational methods incorporated into widely used shielding codes SCALE and QAD we compared the benchmark data with results of benchmark modeling with these codes. Using the functional module SAS4 of SCALE4 modular code package and the point kernel code system for gamma-ray shielding calculations QAD-CGGP scalar flux density spectra in benchmark energy group structure for three two-layer combinations were calculated. The comparison of the benchmark data and the results obtained showed that QAD-CGGP and SAS4 results are in good agreement, but the benchmark experimental data differ significantly from the both of them. (author)

  4. Health and economic benefits of scaling up a home-based neonatal care package in rural India: a modelling analysis.

    Science.gov (United States)

    Nandi, Arindam; Colson, Abigail R; Verma, Amit; Megiddo, Itamar; Ashok, Ashvin; Laxminarayan, Ramanan

    2016-06-01

    Approximately 900 000 newborn children die every year in India, accounting for 28% of neonatal deaths globally. In 2011, India introduced a home-based newborn care (HBNC) package to be delivered by community health workers across rural areas. We estimate the disease and economic burden that could be averted by scaling up the HBNC in rural India using IndiaSim, an agent-based simulation model, to examine two interventions. In the first intervention, the existing community health worker network begins providing HBNC for rural households without access to home- or facility-based newborn care, as introduced by India's recent programme. In the second intervention, we consider increased coverage of HBNC across India so that total coverage of neonatal care (HBNC or otherwise) in the rural areas of each state reaches at least 90%. We find that compared with a baseline of no coverage, providing the care package through the existing network of community health workers could avert 48 [95% uncertainty range (UR) 34-63] incident cases of severe neonatal morbidity and 5 (95% UR 4-7) related deaths, save $4411 (95% UR $3088-$5735) in out-of-pocket treatment costs, and provide $285 (95% UR $200-$371) in value of insurance per 1000 live births in rural India. Increasing the coverage of HBNC to 90% will avert an additional 9 (95% UR 7-12) incident cases, 1 death (95% UR 0.72-1.33), and $613 (95% UR $430-$797) in out-of-pocket expenditures, and provide $55 (95% UR $39-$72) in incremental value of insurance per 1000 live births. Intervention benefits are greater for lower socioeconomic groups and in the poorer states of Chhattisgarh, Uttarakhand, Bihar, Assam and Uttar Pradesh. PMID:26561440

  5. SU-8 cantilever chip interconnection

    DEFF Research Database (Denmark)

    Johansson, Alicia Charlotte; Janting, Jakob; Schultz, Peter;

    2006-01-01

    the electrodes on the SU-8 chip to a printed circuit board. Here, we present two different methods of electrically connecting an SU-8 chip, which contains a microfluidic network and free-hanging mechanical parts. The tested electrical interconnection techniques are flip chip bonding using underfill or flip chip...... bonding using an anisotropic conductive film (ACF). These are both widely used in the Si industry and might also be used for the large scale interconnection of SU-8 chips. The SU-8 chip, to which the interconnections are made, has a microfluidic channel with integrated micrometer-sized cantilevers...... that can be used for label-free biochemical detection. All the bonding tests are compared with results obtained using similar Si chips. It is found that it is significantly more complicated to interconnect SU-8 than Si cantilever chips primarily due to the softness of SU-8....

  6. Radioistopes to Solar to High Energy Accelerators – Chip-Scale Energy Sources

    International Nuclear Information System (INIS)

    This talk will present MEMS based power sources that utilize radioisotopes, solar energy, and potentially nuclear energy through advancements in integration of new structures and materials within MEMS. Micro power harvesters can harness power from vibration, radioisotopes, light, sound, and biology may provide pathways to minimize or even eliminate batteries in sensor nodes. In this talk work on radioisotope thin films for MEMS will be include the self-reciprocating cantilever, betavoltaic cells, and high DC voltages. The self-reciprocating cantilever energy harvester allows small commercially viable amounts of radioisotopes to generate mW to Watts of power so that very reliable power sources that last 100s of years are possible. The tradeoffs between reliability and potential stigma with radioisotopes allow one to span a useful design space with reliability as a key parameter. These power sources provide pulsed power at three different time scales using mechanical, RF, and static extraction of energy from collected charge. Multi-use capability, both harvesting radioisotope power and local vibration energy extends the reliability of micro-power sources further

  7. Characterization and modeling of two-phase heat transfer in chip-scale non-uniformly heated microgap channels

    Science.gov (United States)

    Ali, Ihab A.

    A chip-scale, non-uniformly heated microgap channel, 100 micron to 500 micron in height with dielectric fluid HFE-7100 providing direct single- and two-phase liquid cooling for a thermal test chip with localized heat flux reaching 100 W/cm2, is experimentally characterized and numerically modeled. Single-phase heat transfer and hydraulic characterization is performed to establish the single-phase baseline performance of the microgap channel and to validate the mesh-intensive CFD numerical model developed for the test channel. Convective heat transfer coefficients for HFE-7100 flowing in a 100-micron microgap channel reached 9 kW/m2K at 6.5 m/s fluid velocity. Despite the highly non-uniform boundary conditions imposed on the microgap channel, CFD model simulation gave excellent agreement with the experimental data (to within 5%), while the discrepancy with the predictions of the classical, "ideal" channel correlations in the literature reached 20%. A detailed investigation of two-phase heat transfer in non-ideal micro gap channels, with developing flow and significant non-uniformities in heat generation, was performed. Significant temperature non-uniformities were observed with non-uniform heating, where the wall temperature gradient exceeded 30°C with a heat flux gradient of 3-30 W/cm2, for the quadrant-die heating pattern compared to a 20°C gradient and 7-14 W/cm2 heat flux gradient for the uniform heating pattern, at 25W heat and 1500 kg/m2s mass flux. Using an inverse computation technique for determining the heat flow into the wetted microgap channel, average wall heat transfer coefficients were found to vary in a complex fashion with channel height, flow rate, heat flux, and heating pattern and to typically display an inverse parabolic segment of a previously observed M-shaped variation with quality, for two-phase thermal transport. Examination of heat transfer coefficients sorted by flow regimes yielded an overall agreement of 31% between predictions of the

  8. Optimization and pilot-scale testing of modified atmosphere packaging of irradiated fresh 'Carabao' mango (Mangifera indica L.) fruits

    International Nuclear Information System (INIS)

    Modified atmosphere packaging (MAP) for fresh 'Carabao' mango was optimized with respect to the number of pinholes needed for a fixed respiration rate, fill weight, oxygen transmission rate (OTR), and bag surface area. Computer simulations showed that 38-mm polyethylene or 20-mm Zeolite film with 52 or 44 pinholes, respectively, could be used for packing 5 kg of fruit in a bag with a surface area of approximately 0.80 sq m if held at 12.5 deg C. Subsequent laboratory trials using fruits irradiated at 150-250 Gy showed that 50 pinholes made with a 26-gauge cold needle could be used for both films; O2 levels during storage were close to the recommended levels of 3-5%. Pilot-scale trials using fruits harvested during the on and off-season show that both irradiation at 150-250 Gy and MAP could retard ripening and reduce softening. After 4 wk of storage at 12.5 deg C, MAP fruits were at a half-ripe and slightly-firm stage of ripeness, with minimal development of disease. Sensory tests at the table-ripe stage showed that irradiated MAP-stored fruits were acceptable

  9. Continuous using of the scaling factors for radionuclide evaluation in the packaged solid wastes originated from the Japanese Nuclear Power Plants since 2003

    International Nuclear Information System (INIS)

    The amounts and concentration of the nuclides in the waste packages are estimated by measuring some key nuclides, mostly gamma emitters, from outside of the packages and by applying the scaling factor method (using the relationship between some easy to measure key nuclides and the other difficult to measure nuclides). The solid wastes are classified into two kinds of packages: homogeneous solid wastes made from concentrated liquid wastes and spent fuels solidified with cement asphalt, or plastics and heterogeneous solid wastes made of cutting metals, compacted or fused filters solidified with mortars. Japan Nuclear Energy Safety Organization (JNES) established in 2005 is in charge of the confirmation of the inside contents with radionuclide information and compliance with formalities for safety maintenance and control. (S. Ohno)

  10. Design and fabrication of a compact chip-scale optical cross-connect enabled by photonic crystals for optical interconnects

    Science.gov (United States)

    Zablocki, Mathew Joseph

    As integrated circuits, such as microprocessors, are fabricated with higher yields and with increasing numbers of smaller and smaller transistors, the communication between discrete elements becomes as important as the elements themselves. The delays associated with signal distribution across the chip have become a limiting factor for processor speeds, and are primarily located within the global interconnect layers for intra-chip and inter-chip communication. Optical interconnects have the potential to relieve the restrictions set by the interconnect bottleneck by taking advantage of their reduced power demands for signal distribution and their lower propagation delays. The work within this dissertation discusses the design, fabrication and characterization of an ultra-compact photonic crystal optical switch for use within a transparent optical cross-connect (OXC). To reduce the size and power consumption of the switch, perturbations were made within the photonic crystal structure to achieve a degree of slow light, decreasing the group velocity of the propagating signals. Further, as a means to integrate the developed switch matrix to a microprocessor in order to serve as a chip's optical global interconnect, a process was developed to transfer the switch fabric to a new substrate as a silicon-nanomembrane (Si-NM). The developed transfer process allows the transfer and stacking of intricate photonic devices, such as the aforementioned switch matrix, to new material platforms and substrates that would be incompatible with typical complementary-metal-oxide-semiconductor CMOS processing. The developed Si-NM processing along with the developed switch matrix for a transparent OXC are significant steps toward implementing an optical interconnect network on a chip.

  11. Package Holds Five Monolithic Microwave Integrated Circuits

    Science.gov (United States)

    Mysoor, Narayan R.; Decker, D. Richard; Olson, Hilding M.

    1996-01-01

    Packages protect and hold monolithic microwave integrated circuit (MMIC) chips while providing dc and radio-frequency (RF) electrical connections for chips undergoing development. Required to be compact, lightweight, and rugged. Designed to minimize undesired resonances, reflections, losses, and impedance mismatches.

  12. A novel conceptual design of parallel nitrogen expansion liquefaction process for small-scale LNG (liquefied natural gas) plant in skid-mount packages

    International Nuclear Information System (INIS)

    The utilization of unconventional natural gas is still a great challenge for China due to its distribution locations and small reserves. Thus, liquefying the unconventional natural gas by using small-scale LNG plant in skid-mount packages is a good choice with great economic benefits. A novel conceptual design of parallel nitrogen expansion liquefaction process for small-scale plant in skid-mount packages has been proposed. It first designs a process configuration. Then, thermodynamic analysis of the process is conducted. Next, an optimization model with genetic algorithm method is developed to optimize the process. Finally, the flexibilities of the process are tested by two different feed gases. In conclusion, the proposed parallel nitrogen expansion liquefaction process can be used in small-scale LNG plant in skid-mount packages with high exergy efficiency and great economic benefits. - Highlights: • A novel design of parallel nitrogen expansion liquefaction process is proposed. • Genetic algorithm is applied to optimize the novel process. • The unit energy consumption of optimized process is 0.5163 kWh/Nm3. • The exergy efficiency of the optimized case is 0.3683. • The novel process has a good flexibility for different feed gas conditions

  13. Packaging fluency

    DEFF Research Database (Denmark)

    Mocanu, Ana; Chrysochou, Polymeros; Bogomolova, Svetlana;

    2011-01-01

    Research on packaging stresses the need for packaging design to read easily, presuming fast and accurate processing of product-related information. In this paper we define this property of packaging as “packaging fluency”. Based on the existing marketing and cognitive psychology literature...... on packaging design and processing fluency, our aim is to define and conceptualise packaging fluency. We stress the important role of packaging fluency since it is anticipated that a fluent package would influence the evaluative judgments for a product. We conclude this paper by setting the research agenda...

  14. Preservation of forest wood chips

    Energy Technology Data Exchange (ETDEWEB)

    Kofman, P.D.; Thomsen, I.M.; Ohlsson, C.; Leer, E.; Ravn Schmidt, E.; Soerensen, M.; Knudsen, P.

    1999-01-01

    As part of the Danish Energy Research Programme on biomass utilisation for energy production (EFP), this project concerns problems connected to the handling and storing of wood chips. In this project, the possibility of preserving wood chips of the Norway Spruce (Picea Abies) is addressed, and the potential improvements by anaerobic storage are tested. Preservation of wood chips aims at reducing dry matter losses from extensive heating during storage and to reduce production of fungal spores. Fungal spores pose a health hazards to workers handling the chips. Further the producers of wood chips are interested in such a method since it would enable them to give a guarantee for the delivery of homogeneous wood chips also during the winter period. Three different types of wood chips were stored airtight and further one of these was stored in accordance with normal practise and use as reference. The results showed that airtight storage had a beneficial impact on the quality of the chips: no redistribution of moisture, low dry matter losses, unfavourable conditions for microbial activity of most fungi, and the promotion of yeasts instead of fungi with airborne spores. Likewise the firing tests showed that no combustion problems, and no increased risk to the environment or to the health of staff is caused by anaerobic storage of wood chips. In all, the tests of the anaerobic storage method of forest wood chips were a success and a large-scale test of the method will be carried out in 1999. (au)

  15. Atom chips

    CERN Document Server

    Reichel, Jakob

    2010-01-01

    This book provides a stimulating and multifaceted picture of a rapidly developing field. The first part reviews fundamentals of atom chip research in tutorial style, while subsequent parts focus on the topics of atom-surface interaction, coherence on atom chips, and possible future directions of atom chip research. The articles are written by leading researchers in the field in their characteristic and individual styles.

  16. Gain chip design, power scaling and intra-cavity frequency doubling with LBO of optically pumped red-emitting AlGaInP-VECSELs

    Science.gov (United States)

    Kahle, Hermann; Mateo, Cherry M. N.; Brauch, Uwe; Bek, Roman; Schwarzbäck, Thomas; Jetter, Michael; Graf, Thomas; Michler, Peter

    2016-03-01

    The wide range of applications in biophotonics, television or projectors, spectroscopy and lithography made the optically-pumped semiconductor (OPS) vertical external cavity surface-emitting lasers (VECSELs) an important category of power scalable lasers. The possibility of bandgap engineering, inserting frequency selective and converting elements into the open laser cavity and laser emission in the fundamental Gaussian mode leads to ongoing growth of the area of applications for tuneable laser sources. We present an AlGaInP-VECSEL system with a multi quantum well structure consisting of compressively strained GaInP quantum wells in an AlxGa1-xInP separate confinement heterostructure with an emission wavelength around 665 nm. The VECSEL chip with its n-λ cavity is pumped by a 532nm Nd:YAG laser under an angle to the normal incidence of 50°. In comparison, a gain chip design for high absorption values at pump wavelengths around 640nm with the use of quantum dot layers as active material is also presented. Frequency doubling is now realized with an antireflection coated lithium borate crystal, while a birefringent filter, placed inside the laser cavity under Brewster's angle, is used for frequency tuning. Further, power-scaling methods like in-well pumping as well as embedding the active region of a VECSEL between two transparent ic heaspreaders are under investigation.

  17. Processing and Validation of Whey-Protein-Coated Films and Laminates at Semi-Industrial Scale as Novel Recyclable Food Packaging Materials with Excellent Barrier Properties

    Directory of Open Access Journals (Sweden)

    E. Bugnicourt

    2013-01-01

    Full Text Available A biopolymer coating for plastic films was formulated based on whey protein, and its potential to replace current synthetic oxygen barrier layers used in food packaging such as ethylene vinyl alcohol copolymers (EVOH was tested. The whey-coating application was performed at semi-industrial scale. High barrier to oxygen with transmission rate down to ranges of 1 cm3 (STP m−2 d−1 bar−1 at and 50% relative humidity (r.h. but interesting humidity barrier down to ranges of 3 g m−2 d−1 (both normalized to 100 μm thickness were reached, outperforming most existing biopolymers. Coated films were validated for storing various food products showing that the shelf life and sensory attributes were maintained similar to reference packaging films while complying with food safety regulations. The developed whey coating could be enzymatically removed within 2 hours and is therefore compatible with plastic recycling operations to allow multilayer films to become recyclable by separating the other combined layers. A life cycle assessment was performed showing a significant reduction in the environmental impact of the packaging thanks in particular to the possibility of recycling materials as opposed to incinerating those containing EVOH or polyamide (PA, but due to the use of biosourced raw materials.

  18. Setting of scaling factors and average radioactivity concentration on container-filled and solidified waste packages generated from Kashiwazaki Kariwa Nuclear Power Plants Unit 1-5

    International Nuclear Information System (INIS)

    The report evaluates the appropriateness of the point of view addressed from Japan Nuclear Fuel Co., an enterprise in charge of radioactive waste disposal. The low-level radioactive wastes produced from Kashiwazaki Kariwa Power Plants Unit 1 - 5 as in container-filled and solidified packages in 200L drums were investigated for adequateness of using the same scaling factors and confirming the average radioactivity concentration of H-3, C-14, Co-60, Ni-59, Ni-63, Sr-90, Nb-94, Tc-99, I-129, Cs-137, and total alpha-emitting nuclei before sending to Rokkasho radioactive waste storing center. (S. Ohno)

  19. Waste package scenario modelling

    International Nuclear Information System (INIS)

    UK Nirex has supported a programme of work to develop models describing the post-closure evolution of intermediate-level waste packages with the objectives of: - providing support and justification for the parameters and representations used in performance assessment models; - informing future model development and packaging advice. Scenarios for the potential evolution of a waste package were developed and modelled taking explicit account of waste package heterogeneity and the time-dependence of the physical and chemical characteristics of the system. The modelling work highlighted the treatment of organic complexants and the representation of physical containment as two areas in which the impacts of time dependence and package scale heterogeneity might be particularly significant. A subsequent study of the impact of organic complexants emphasised the importance of heterogeneity in package inventory in determining the radionuclide release from the near field. The degree of containment afforded by the wasteform and the waste container has been investigated as part of a study to develop a preliminary understanding of the mixing scales within the repository. The study suggests that the most important control on the release of radionuclides from the waste packages is the integrity of the waste encapsulation grout. Interactions between neighbouring packages are to be expected, but the degree to which homogeneous (well mixed) conditions develop may be limited in both time and space. (author)

  20. Laser applications in integrated circuits and photonics packaging

    Science.gov (United States)

    Lu, Yong Feng; Li, L. P.; Mendu, K.; Shi, J.

    2004-07-01

    Laser processing has large potential in the packaging of integrated circuits (IC). It can be used in many applications such as laser cleaning of IC mold tools, laser deflash to remove mold flash from heat sinks and lead wires of IC packages, laser singulation of BGA (ball grid array) and CSP (chip scale packages), laser reflow of solder ball on GBA, laser peeling for CSP, laser marking on packages and on Si wafers. Laser nanoimprinting of self-assembled nanoparticles has been recently developed to fabricate hemispherical cavity arrays on semiconductor surfaces. This process has the potential applications in fabrication and packaging of photonic devices such as waveguides and optical interconnections. During the implementation of all these applications, laser parameters, material issues, throughput, yield, reliability and monitoring techniques have to be taken into account. Monitoring of laser-induced plasma and laser induced acoustic wave has been used to understand and to control the processes involved in these applications. Numerical simulations can provide useful information on process analysis and optimization.

  1. MEMS packaging

    CERN Document Server

    Hsu , Tai-Ran

    2004-01-01

    MEMS Packaging discusses the prevalent practices and enabling techniques in assembly, packaging and testing of microelectromechanical systems (MEMS). The entire spectrum of assembly, packaging and testing of MEMS and microsystems, from essential enabling technologies to applications in key industries of life sciences, telecommunications and aerospace engineering is covered. Other topics included are bonding and sealing of microcomponents, process flow of MEMS and microsystems packaging, automated microassembly, and testing and design for testing.The Institution of Engineering and Technology is

  2. Numerical Simulation of Non-Newtonian Underfill in Flip-Chip Packaging%倒装芯片封装中非牛顿流体下填充的数值仿真

    Institute of Scientific and Technical Information of China (English)

    姚兴军; 张关华; 王正东; 章文俊; 周鑫延

    2013-01-01

    倒装芯片封装中的下填充工艺可以有效地提高封装连接的可靠性,因而得到了广泛应用.含有硅填料的环氧树脂是常用的下填充胶料,在下填充流动过程中表现出明显的非牛顿流体特性.利用Fluent软件对具有非牛顿流体特性胶料的下填充过程进行了三维数值模拟.采用流体体积比函数(VOF)对流动前沿界面进行追踪,再用连续表面张力(CSF)模型来计算下填充流动的毛细驱动力,并用幂函数本构方程来体现下填充胶料的非牛顿流体特性.通过数值模拟,获得了下填充流动前沿位置随时间变化的数据,这些数据与实验结果有较好的吻合度.该数值方法可较好地预测具有非牛顿流体性质胶料的下填充过程.%Underfill technology is often used in flip-chip packaging as it can improve the reliability of the interconnect systems effectively. Epoxy containing silica fillers is the most common encapsulant, and it exhibits obvious non-Newtonian behavior in the underfill flow. The 3D simulation of the filling process was operated using Fluent software. Volume of fluid (VOF) technique was applied to track the flow front, and the continuum surface force (CSF) model was used to describe the capillary force when the power-law type equation was employed to model the viscosity of the underfill encapsulant. The numerical results show the variation of flow front position with respect to time agrees well with the previous experimental data. This simulation provides a reasonable flow front prediction for underfill flow of encapsulant with non-Newtonian feature.

  3. Nanoslits in silicon chips

    International Nuclear Information System (INIS)

    Potassium hydroxide (KOH) etching of a patterned oriented silicon wafer produces V-shaped etch pits. We demonstrate that the remaining thickness of silicon at the tip of the etch pit can be reduced to ∼5 μm using an appropriately sized etch mask and optical feedback. Starting from such an etched chip, we have developed two different routes for fabricating 100 nm scale slits that penetrate through the macroscopic silicon chip (the slits are ∼850 μm wide at one face of the chip and gradually narrow to ∼100-200 nm wide at the opposite face of the chip). In the first process, the etched chips are sonicated to break the thin silicon at the tip of the etch pit and then further KOH etched to form a narrow slit. In the second process, focused ion beam milling is used to etch through the thin silicon at the tip of the etch pit. The first method has the advantage that it uses only low-resolution technology while the second method offers more control over the length and width of the slit. Our slits can be used for preparing mechanically stable, transmission electron microscopy samples compatible with electrical transport measurements or as nanostencils for depositing nanowires seamlessly connected to their contact pads.

  4. Battery packaging - Technology review

    International Nuclear Information System (INIS)

    This paper gives a brief overview of battery packaging concepts, their specific advantages and drawbacks, as well as the importance of packaging for performance and cost. Production processes, scaling and automation are discussed in detail to reveal opportunities for cost reduction. Module standardization as an additional path to drive down cost is introduced. A comparison to electronics and photovoltaics production shows 'lessons learned' in those related industries and how they can accelerate learning curves in battery production

  5. Chips 2020

    CERN Document Server

    2016-01-01

    The release of this second volume of CHIPS 2020 coincides with the 50th anniversary of Moore’s Law, a critical year marked by the end of the nanometer roadmap and by a significantly reduced annual rise in chip performance. At the same time, we are witnessing a data explosion in the Internet, which is consuming 40% more electrical power every year, leading to fears of a major blackout of the Internet by 2020. The messages of the first CHIPS 2020, published in 2012, concerned the realization of quantum steps for improving the energy efficiency of all chip functions. With this second volume, we review these messages and amplify upon the most promising directions: ultra-low-voltage electronics, nanoscale monolithic 3D integration, relevant-data, brain- and human-vision-inspired processing, and energy harvesting for chip autonomy. The team of authors, enlarged by more world leaders in low-power, monolithic 3D, video, and Silicon brains, presents new vistas in nanoelectronics, promising  Moore-like exponential g...

  6. Wear out Reliability and Intermetallic Compound Diffusion Kinetics of Au and PdCu Wires Used in Nano scale Device Packaging

    International Nuclear Information System (INIS)

    Wear out reliability and diffusion kinetics of Au and Pd-coated Cu (PdCu) ball bonds are useful technical information for Cu wire deployment in nano scale semiconductor device packaging. This paper discusses the HAST (with bias) and UHAST (unbiased HAST) wear out reliability performance of Au and PdCu wires used in fine pitch BGA packages. In-depth failure analysis has been carried out to identify the failure mechanism under various wear out conditions. Intermetallic compound (IMC) diffusion constants and apparent activation energies (Eaa) of both wire types were investigated after high temperature storage life test (HTSL). Au bonds were identified to have faster IMC formation, compared to slower IMC growth of PdCu. PdCu wire was found to exhibit equivalent or better wear out reliability margin compared to conventional Au wire bonds. Failure mechanisms of Au, Cu ball bonds post-HAST and UHAST tests are been proposed, and both Au and PdCu IMC diffusion kinetics and their characteristics are discussed in this paper.

  7. Accurate macromolecular crystallographic refinement: incorporation of the linear scaling, semiempirical quantum-mechanics program DivCon into the PHENIX refinement package

    International Nuclear Information System (INIS)

    Semiempirical quantum-chemical X-ray macromolecular refinement using the program DivCon integrated with PHENIX is described. Macromolecular crystallographic refinement relies on sometimes dubious stereochemical restraints and rudimentary energy functionals to ensure the correct geometry of the model of the macromolecule and any covalently bound ligand(s). The ligand stereochemical restraint file (CIF) requires a priori understanding of the ligand geometry within the active site, and creation of the CIF is often an error-prone process owing to the great variety of potential ligand chemistry and structure. Stereochemical restraints have been replaced with more robust functionals through the integration of the linear-scaling, semiempirical quantum-mechanics (SE-QM) program DivCon with the PHENIX X-ray refinement engine. The PHENIX/DivCon package has been thoroughly validated on a population of 50 protein–ligand Protein Data Bank (PDB) structures with a range of resolutions and chemistry. The PDB structures used for the validation were originally refined utilizing various refinement packages and were published within the past five years. PHENIX/DivCon does not utilize CIF(s), link restraints and other parameters for refinement and hence it does not make as many a priori assumptions about the model. Across the entire population, the method results in reasonable ligand geometries and low ligand strains, even when the original refinement exhibited difficulties, indicating that PHENIX/DivCon is applicable to both single-structure and high-throughput crystallography

  8. Power Cycle Testing of Press-Pack IGBT Chips

    OpenAIRE

    Frank, Øyvind Bjerke

    2014-01-01

    In this thesis the power cycling capability of individual press-pack IGBT chips is investigated. Press-pack is a packaging technology used for power semiconductors. For press-packs, both thermal and electrical contact to the semiconductor chip is obtained by the application of force on the package. Press-pack IGBTs is claimed by the manufacturers to be especially suitable for high-power applications with large variations in power output. Power cycle testing is an accelerated lifetime stress t...

  9. GEM400: A front-end chip based on capacitor-switch array for pixel-based GEM detector

    International Nuclear Information System (INIS)

    The upgrade of Beijing Synchrotron Radiation Facility (BSRF) needs two-dimensional position-sensitive detection equipment to improve the experimental performance. Gas Electron Multiplier (GEM) detector, in particular, pixel-based GEM detector has good application prospects in the domain of synchrotron radiation. The read-out of larger scale pixel-based GEM detector is difficult for the high density of the pixels (PAD for collecting electrons). In order to reduce the number of cables, this paper presents a read-out scheme for pixel-based GEM detector, which is based on System-in-Package technology and ASIC technology. We proposed a circuit structure based on capacitor switch array circuit, and design a chip GEM400, which is a 400 channels ASIC. The proposed circuit can achieve good stability and low power dissipation. The chip is implemented in a 0.35μm CMOS process. The basic functional circuitry in ths chip includes analog switch, analog buffer, voltage amplifier, bandgap and control logic block, and the layout of this chip takes 5mm × 5mm area. The simulation results show that the chip can allow the maximum amount of input charge 70pC on the condition of 100pF external integrator capacitor. Besides, the chip has good channel uniformity (INL is better than 0.1%) and lower power dissipation.

  10. Heat transfer and structure stress analysis of micro packaging component of high power light emitting diode

    Directory of Open Access Journals (Sweden)

    Hsu Chih-Neng

    2013-01-01

    Full Text Available This paper focuses on the heat transfer and structural stress analysis of the micro- scale packaging structure of a high-power light emitting diode. The thermal-effect and thermal-stress of light emitting diode are determined numerically. Light emitting diode is attached to the silicon substrate through the wire bonding process by using epoxy as die bond material. The silicon substrate is etched with holes at the bottom and filled with high conductivity copper material. The chip temperature and structure stress increase with input power consumption. The micro light emitting diode is mounted on the heat sink to increase the heat dissipation performance, to decrease chip temperature, to enhance the material structure reliability and safety, and to avoid structure failure as well. This paper has successfully used the finite element method to the micro-scale light emitting diode heat transfer and stress concentration at the edges through etched holes.

  11. Additive manufacturing approaches for stress relief in semiconductor die packaging

    NARCIS (Netherlands)

    Zon, C.M.B. van der; Wiel, A. van der; Maalderink, H.H.; Vaes, M.H.E.; Aulbers, A.P.; Vorst, L.T.G. van de; Cate, A.T. ten; Furrer, J.F.; Burssens, J.W.; Chen, J.

    2012-01-01

    Packaging of semiconductor chips, especially MEMS-based, always causes stress on the functional areas of the die causing unpredictable changes in chip performance. As a consequence such devices can only be calibrated individually after complete assembly. Melexis and TNO have developed an approach to

  12. Mineralogical and elemental composition of fly ash from pilot scale fluidised bed combustion of lignite, bituminous coal, wood chips and their blends

    Energy Technology Data Exchange (ETDEWEB)

    Nikolaos Koukouzas; Jouni Hamalainen; Dimitra Papanikolaou; Antti Tourunen; Timo Jantti [Institute for Solid Fuels Technology and Applications, Ptolemais (Greece). Centre for Research and Technology Hellas

    2007-09-15

    The chemical and mineralogical composition of fly ash samples collected from different parts of a laboratory and a pilot scale CFB facility has been investigated. The fabric filter and the second cyclone of the two facilities were chosen as sampling points. The fuels used were Greek lignite (from the Florina basin), Polish coal and wood chips. Characterization of the fly ash samples was conducted by means of X-ray fluorescence (XRF), inductive coupled plasma-optical emission spectrometry (ICP-OES), thermogravimetric analysis (TGA), particle size distribution (PSD) and X-ray diffraction (XRD). According to the chemical analyses the produced fly ashes are rich in CaO. Moreover, SiO{sub 2} is the dominant oxide in fly ash with Al{sub 2}O{sub 3} and Fe{sub 2}O{sub 3} found in considerable quantities. Results obtained by XRD showed that the major mineral phase of fly ash is quartz, while other mineral phases that are occurred are maghemite, hematite, periclase, rutile, gehlenite and anhydrite. The ICP-OES analysis showed rather low levels of trace elements, especially for As and Cr, in many of the ashes included in this study compared to coal ash from fluidised bed combustion in general. 23 refs., 3 figs., 5 tabs.

  13. Copper chip technology

    Science.gov (United States)

    Edelstein, Daniel C.

    1998-09-01

    Recently, IBM announced the first silicon integrated circuit technology that incorporates copper on-chip wiring. This technology, which combines industry-leading CMOS ULSI devices with 6 levels of hierarchically-scaled Cu metallization, has reached the point of manufacturing, after passing the qualification tests required to prove feasibility, yield, reliability, and manufacturability. The discussion of the change from Al To Cu interconnects for ULSI encompasses a wide variety of issues. This paper attempts to address these by way of example, from the broad range of detailed studies that have been performed in the course of developing these so-called 'copper chips.' Motivational issues are covered by comparative modeling of performance aspects and cost. The technology parameters and features are shown, as well as data relating to the process integration, electrical yield and parametric behavior, early manufacturing data, high-frequency modeling and measurements, noise and clock skew. The viability of this technology is indicated by results from reliability stressing, as well as the first successful demonstrations of fully functional SRAM, DRAM, and microprocessor chips with Cu wiring. The advantages of integrated Cu wiring may be applied even more broadly in the future. An example shown here is the achievement of very high-quality integrated inductors; these may help prospects for complete integration of RF and wireless communications chips onto silicon.

  14. Continuous use after 1998 of the scaling factors for radionuclide evaluation in the packaged solid wastes generated from the Fukushima Daiichi Nuclear Power Plants of Tokyo Electric Power Company

    International Nuclear Information System (INIS)

    The waste packages containing solidified radioactive wastes generated from nuclear power plants are evaluated by measuring radioactivity from outside the drums and applying the scaling factor method to estimate the inside radionuclide concentrations. Japan Nuclear Energy Safety Organization (JNES) is in charge of the confirmation of the applicability of this method and this report presents the results of the examining processes of the working committee for this purpose. The properties of the solidified waste packages, the guidelines of using the scaling factors, the concept of renewal of reactor composing materials, are explained with radionuclide information and compliance with formalities for safety maintenance and control. (S. Ohno)

  15. Wafer Level Package for Image Sensor Module

    OpenAIRE

    Jeung, Won-Kyu; Lim, Chang-Hyun; Yuan, Jingli; Park, Seung-Wook

    2008-01-01

    A new ISM (image sensor module) WLP (wafer level package) for reflow process is designed, fabricated and tested. The ISM WLP is composed of polymer bonding layer, glass cap wafer for particle free process and CIS (CMOS Image Sensor) chip wafer which has micro via hole interconnection. During the last decades, WLP is highlighted as the next generation ISM Package method for many advantages like high yield (particle free process), small form factor (3D interconnection), low assembly cost and so...

  16. Effectiveness of a controlled release chlorhexidine chip (PerioColTM‑CG as an adjunctive to scaling and root planing when compared to scaling and root planing alone in the treatment of chronic periodontitis: A comparative study

    Directory of Open Access Journals (Sweden)

    Kameswari Kondreddy

    2012-01-01

    Full Text Available Aims and objectives: The aim of this study is to evaluate the effectiveness of a controlled-release chlorhexidine chip as an adjunctive therapy to scaling and root planing when compared with scaling and root planing alone in the treatment of chronic periodontitis. Materials and Methods: 20 patients with a total number of 40 posterior sites were selected. These sites were divided into two groups in a split mouth design,: Group A (control site had 20 sites treated with scaling and root planing alone and Group B (test site had 20 sites treated with scaling and root planing and PerioCol TM -CG. The clinical parameters (Plaque index, bleeding on probing, probing pocket depth, clinical attachment level were recorded at baseline, 90 th and 180 th day for both the groups. Results: When both groups were compared the change in Plaque index was significantly higher in Group B when compared to Group A on the 90 th day and 180 th day. However, there was no statistically significant difference in the mean percentage of gingival bleeding sites between the two groups on the 90 th day, though Group B showed a statistically higher reduction in the mean percentage of gingival bleeding sites at the end of 180 th day. There was no statistically significant difference in probing pocket depth between the two groups on both 90 th and 180 th day. Gain in clinical attachment level was significantly higher in Group B when compared to Group A on the 90 th and 180 th day. Conclusion: From the results observed in this study, it can be concluded that the adjunctive use of PerioCol TM -CG was safe and provided significant improvement in both Plaque index and gingival bleeding index. It was also more favorable than scaling and root planing alone for gain in clinical attachment level.

  17. Automating dChip: toward reproducible sharing of microarray data analysis

    OpenAIRE

    Li Cheng

    2008-01-01

    Abstract Background During the past decade, many software packages have been developed for analysis and visualization of various types of microarrays. We have developed and maintained the widely used dChip as a microarray analysis software package accessible to both biologist and data analysts. However, challenges arise when dChip users want to analyze large number of arrays automatically and share data analysis procedures and parameters. Improvement is also needed when the dChip user support...

  18. Future trends in secure chip data managemen

    OpenAIRE

    Anciaux, Nicolas; Bouganim, Luc; Pucheral, Philippe

    2007-01-01

    Secure chips, e.g. present in smart cards, TPM, USB dongles are now ubiquitous in applications with strong security requirements. Secure chips host personal data that must be carefully managed and protected, thus requiring embedded data management techniques. However, secure chips have severe hardware constraints which make traditional database techniques irrelevant. We previously addressed the problem of scaling down database techniques for the smart card and proposed the design of a DBMS ke...

  19. Future Trends in Secure Chip Data Management

    OpenAIRE

    Anciaux, Nicolas; Bouganim, Luc; Pucheral, Philippe

    2007-01-01

    Secure chips, e.g. present in smart cards, TPM, USB dongles are now ubiquitous in applications with strong security requirements. Secure chips host personal data that must be carefully managed and protected, thus requiring embedded data management techniques. However, secure chips have severe hardware constraints which make traditional database techniques irrelevant. We previously addressed the problem of scaling down database techniques for the smart card and proposed the design of a DBMS ke...

  20. Key of Packaged Grain Quantity RECOGNITION——RESEARCH on Processing and Describing of ``FISH and Describing of ``FISH Scale Body''

    Science.gov (United States)

    Lin, Ying; Fang, Xinglin; Sun, Yueheng; Sun, Yanhong

    The key to identifying the packaged grain is the shape of package, and the key to identifying shape is processing and describing the boundary of package. Based on a lot of analysis and experiment, this article select the canny operator and chain code to process and describe the boundary of package. Aiming at the boundary is not absolute connectivity, the closure operation of Mathematical Morphology is introduced to do pretreatment on binary image of packaged grain. Finally the boundary is absolute connectivity. Experiments show that the proposed method enhances the anti-jamming and robustness of edge detection.

  1. Comparison of different LED Packages

    Science.gov (United States)

    Dieker, Henning; Miesner, Christian; Püttjer, Dirk; Bachl, Bernhard

    2007-09-01

    In this paper different technologies for LED packaging are compared, focusing on Chip on Board (COB) and SMD technology. The package technology which is used depends on the LED application. A critical fact in LED technology is the thermal management, especially for high brightness LED applications because the thermal management is important for reliability, lifetime and electrooptical performance of the LED module. To design certain and long life LED applications knowledge of the heat flow from LEDs to the complete application is required. High sophisticated FEM simulations are indispensable for modern development of high power LED applications. We compare simulations of various substrate materials and packaging technologies simulated using FLOTHERM software. Thereby different substrates such as standard FR4, ceramic and metal core printed circuit boards are considered. For the verification of the simulated results and the testing of manufactured modules, advanced measurement tools are required. We show different ways to experimentally characterize the thermal behavior of LED modules. The thermal path is determined by the transient thermal analysis using the MicReD T3Ster analyzer. Afterwards it will be compared to the conventional method using thermocouples. The heat distribution over the module is investigated by an IR-Camera. We demonstrate and compare simulation and measurement results of Chip-on-Board (COB) and Sub-Mounted Devices (SMD) technology. The results reveal that for different applications certain packages are ideal.

  2. Correlations between homologue concentrations of PCDD/Fs and toxic equivalency values in laboratory-, package boiler-, and field-scale incinerators.

    Science.gov (United States)

    Iino, Fukuya; Takasuga, Takumi; Touati, Abderrahmane; Gullett, Brian K

    2003-01-01

    The toxic equivalency (TEQ) values of polychlorinated dibenzo-p-dioxins and polychlorinated dibenzofurans (PCDD/Fs) are predicted with a model based on the homologue concentrations measured from a laboratory-scale reactor (124 data points), a package boiler (61 data points), and operating municipal waste incinerators (114 data points). Regardless of the three scales and types of equipment, the different temperature profiles, sampling emissions and/or solids (fly ash), and the various chemical and physical properties of the fuels, all the PCDF plots showed highly linear correlations (R(2)>0.99). The fitting lines of the reactor and the boiler data were almost linear with slope of unity, whereas the slope of the municipal waste incinerator data was 0.86, which is caused by higher predicted values for samples with high measured TEQ. The strong correlation also implies that each of the 10 toxic PCDF congeners has a constant concentration relative to its respective total homologue concentration despite a wide range of facility types and combustion conditions. The PCDD plots showed significant scatter and poor linearity, which implies that the relative concentration of PCDD TEQ congeners is more sensitive to variations in reaction conditions than that of the PCDF congeners. PMID:14522191

  3. Human-machine Scale and Comfort in Packaging Container Modeling Design%包装容器造型设计的人机尺度与舒适度

    Institute of Scientific and Technical Information of China (English)

    黎英; 王建民

    2012-01-01

    Starting from ergonomic principles, it analyzed the human-machine factors in packaging container and the law of comfortable design based on the human-machine scales, systematically investigated the types of comfort from health and medical point of view. It is found that in order to gain physical and mental comfort while using the container so as to create an ideal lifestyle for consumers, scales including human body size, physiological and psychological needs and behaviour must be considered in packing design.%参考健康医学的观点,对舒适度的类型展开了分析,以人机工程学原理为启示,分析了包装容器造型设计的人机因素,探讨了基于人机尺度下包装容器造型的舒适性设计规律。在此基础上,提出了在包装造型设计中把握人体尺寸、生理需求、心理需求、使用行为的尺度,才能使容器在使用过程中获得生理和心理的舒适,从而为消费者营造理想的生活方式。

  4. Identification and characterisation of factors affecting losses in the large-scale, non-ventilated bulk storage of wood chips and development of best storage practices

    Energy Technology Data Exchange (ETDEWEB)

    Garstang, J.; Weekes, A.; Poulter, R.; Bartlett, D.

    2002-07-01

    The report describes the findings of a study to determine the factors affecting the commercial storage of wood chips for biomass power generation in the UK. The UK's first such plant in North Yorkshire uses a mixture of forestry residues and short rotation coppice (SRC) willow, where problems with the stored fuel highlighted the need to determine best storage practices. Two wood chip piles were built (one with willow chip and the other with wood chips from board leaf forestry residues) and monitored (moisture, temperature, chemical composition, spore numbers and species, heat and air flows, bulk density, etc). Local weather data was also obtained. Recommendations for future storage practices are made.

  5. Curbing variations in packaging process through Six Sigma way in a large-scale food-processing industry

    Science.gov (United States)

    Desai, Darshak A.; Kotadiya, Parth; Makwana, Nikheel; Patel, Sonalinkumar

    2015-08-01

    Indian industries need overall operational excellence for sustainable profitability and growth in the present age of global competitiveness. Among different quality and productivity improvement techniques, Six Sigma has emerged as one of the most effective breakthrough improvement strategies. Though Indian industries are exploring this improvement methodology to their advantage and reaping the benefits, not much has been presented and published regarding experience of Six Sigma in the food-processing industries. This paper is an effort to exemplify the application of Six Sigma quality improvement drive to one of the large-scale food-processing sectors in India. The paper discusses the phase wiz implementation of define, measure, analyze, improve, and control (DMAIC) on one of the chronic problems, variations in the weight of milk powder pouch. The paper wraps up with the improvements achieved and projected bottom-line gain to the unit by application of Six Sigma methodology.

  6. PACE3 - front-end chip for the CMS Preshower

    CERN Multimedia

    Aspel, Paul

    2003-01-01

    This is PACE3 which is the front-end chip for the CMS Preshower. In fact PACE3 is the combination of two ASICs called Delta3 and PACEAM3. Delta3 is on the left and PACEAM3 is on the right. The two ASICs are bonded together and then packaged within a single 196 pin fpBGA package.

  7. Ceramic packages for liquid-nitrogen operation

    International Nuclear Information System (INIS)

    To evaluate their compatibility for use in a liquid-nitrogen computer, metallized ceramic packages with test chips joined using IBM controlled-collapse solder (Pb-Sn) technology have been cycled between 300C and liquid-nitrogen temperature. Room-temperature electrical resistance measurements were made at regular intervals of cycles to determine whether solder failure accompanied by a significant resistance increase had occurred. For the failed solder joints characterized by the highest thermal shear strain amplitude of 3.3 percent, the authors were able to estimate the number of liquid-nitrogen cycles needed to produce the corresponding failure rate using a room-temperature solder lifetime model. Cross-sectional examination of the failed solder joints using scanning electron microscopy and energy dispersive X-ray analysis indicated solder cracking occurring at the solder-ceramic interface. Chip pull tests on cycled packages yielded strengths far exceeding the minimal requirement. Mechanisms involving the formation of intermetallics were proposed to account for the observed solder fracture modes after liquid-nitrogen cycling and after chip pull. Furthermore, scanning electron microscopic examination of pulled chips in cycled packages showed no apparent sign of cracking in quartz and polyimide for chip insulation

  8. Thermal characterization and modeling of ultra-thin silicon chips

    Science.gov (United States)

    Alshahed, Muhammad; Yu, Zili; Rempp, Horst; Richter, Harald; Harendt, Christine; Burghartz, Joachim N.

    2015-11-01

    Manufacturing ultra-thin chip is an emerging field in semiconductor technology that is driven by 3-D integrated circuits and flexible electronics. Unlike bulk silicon (Si) chips with thickness greater than 400 μm, the thermal management of ultra-thin Si chips with thickness smaller than 20 μm is challenging due to the increased lateral thermal resistance implying stringent cooling requirements. Therefore, a reasonable prediction of temperature gradients in such chips is necessary. In this work, a thermal chip is implemented in an ultra-thin 0.5 μm CMOS technology to be employed in surface steady-state and transient temperature measurement. Test chips are either packaged in a Pin Grid Array (PGA) ceramic package or attached to a flexible polyimide substrate. The experimental results show an on-chip temperature gradient of ∼15 °C for a dissipated power of 0.4 W in the case of the PGA package and ∼30 °C for the polyimide substrate. The time constants are ∼50 s and ∼1 s for the PGA and the polyimide packages respectively. The measurements are complemented by FEM simulations using ANSYS 14.5 workbench and spice simulations using an equivalent lumped-component thermal circuit model. The lumped-element thermal circuit model is then used for the surface temperature prediction, which is compared to measurement results.

  9. Production of structured thin wooden chips by milling with small cutting angles

    OpenAIRE

    Heisel, Uwe; Tröger, Johannes

    1994-01-01

    Thin wooden chips can be used in a wide range, primarily to produce ecological positive materials to substitute plastics and mineral wool for the use of thermal isolation and packaging materials. There are wide resources of wood and it can be wasted ecologically. Additionally, the production of wooden chips for the above mentioned purposes has clear advantages regarding the expenditure of energy. With existing machining methods for the production of wooden cutting chips, only a chip thickness...

  10. Green Packaging Management of Logistics Enterprises

    Science.gov (United States)

    Zhang, Guirong; Zhao, Zongjian

    From the connotation of green logistics management, we discuss the principles of green packaging, and from the two levels of government and enterprises, we put forward a specific management strategy. The management of green packaging can be directly and indirectly promoted by laws, regulations, taxation, institutional and other measures. The government can also promote new investment to the development of green packaging materials, and establish specialized institutions to identify new packaging materials, standardization of packaging must also be accomplished through the power of the government. Business units of large scale through the packaging and container-based to reduce the use of packaging materials, develop and use green packaging materials and easy recycling packaging materials for proper packaging.

  11. Bioclim deliverable D8a: development of the rule-based down-scaling methodology for BIOCLIM Work-package 3

    International Nuclear Information System (INIS)

    The BIOCLIM project on modelling sequential Biosphere systems under Climate change for radioactive waste disposal is part of the EURATOM fifth European framework programme. The project was launched in October 2000 for a three-year period. The project aims at providing a scientific basis and practical methodology for assessing the possible long term impacts on the safety of radioactive waste repositories in deep formations due to climate and environmental change. Five work packages (WP) have been identified to fulfill the project objectives. One of the tasks of BIOCLIM WP3 was to develop a rule-based approach for down-scaling from the MoBidiC model of intermediate complexity in order to provide consistent estimates of monthly temperature and precipitation for the specific regions of interest to BIOCLIM (Central Spain, Central England and Northeast France, together with Germany and the Czech Republic). A statistical down-scaling methodology has been developed by Philippe Marbaix of CEA/LSCE for use with the second climate model of intermediate complexity used in BIOCLIM - CLIMBER-GREMLINS. The rule-based methodology assigns climate states or classes to a point on the time continuum of a region according to a combination of simple threshold values which can be determined from the coarse scale climate model. Once climate states or classes have been defined, monthly temperature and precipitation climatologies are constructed using analogue stations identified from a data base of present-day climate observations. The most appropriate climate classification for BIOCLIM purposes is the Koeppen/Trewartha scheme. This scheme has the advantage of being empirical, but only requires monthly averages of temperature and precipitation as input variables. Section 2 of this deliverable (D8a) outline how each of the eight methodological steps have been undertaken for each of the three main BIOCLIM study regions (Central England, Northeast France and Central Spain) using Mo

  12. Performance and Energy Efficient Network-on-Chip Architectures

    OpenAIRE

    Vangal, Sriram

    2007-01-01

    The scaling of MOS transistors into the nanometer regime opens the possibility for creating large Network-on-Chip (NoC) architectures containing hundreds of integrated processing elements with on-chip communication. NoC architectures, with structured on-chip networks are emerging as a scalable and modular solution to global communications within large systems-on-chip. NoCs mitigate the emerging wire-delay problem and addresses the need for substantial interconnect bandwidth by replacing today...

  13. Benchmarking of the scale code package and multi-group cross section libraries for analysis of lead-cooled fast reactor

    International Nuclear Information System (INIS)

    The Generation IV [1] International forum identified six advanced reactor concepts and related fuel cycles along with the R and D programs necessary to achieve the four key goals: (1) sustainability, (2) safety and reliability, (3) economics, (4) proliferation resistance and physical protection. Among these six promising reactor concepts, the lead-cooled fast reactor (LFR) has been selected for development by EURATOM, which in 2006 decided to finance the European Lead Cooled System (ELSY) project. The aim of the project is to demonstrate the possibility to design a safe and competitive lead-cooled fast power reactor using simple engineering solutions. This paper demonstrates the use of the code package SCALE5.1 and its NEWT/TRITON modules [3] for preliminary neutronic core analysis of a LFR within Generation IV Nuclear Energy systems program. More specifically, the analysis of the reference design of the ELSY-600 open square fuel assembly is presented. In particular, the use of ENDF/B-V and ENDF/B-VI.7 and multigroup energy structure was investigated. The homogenized cross sections calculated for the ELSY fuel assembly 2D model have been evaluated and compared to the results obtained with calculations performed with the deterministic code ERANOS/ECCO using JEFF2.2 cross section library. A good agreement has been observed in the energy range of interests, and generally for energy above 1 eV. (authors)

  14. Silicon chips light up

    International Nuclear Information System (INIS)

    Researchers have demonstrated a continuous laser in silicon, which paves the way for computing at the speed of light Silicon is the racehorse of microelectronics. For the last 40 years, the number of transistors that can be crammed onto a single silicon wafer has doubled every 18 months or so, with the latest 'Itanium' chip packing in almost half a billion of them. But Moore's law, as this exponential trend is popularly known, is coming to an end due to fundamental physical limitations. These include the difficulty of keeping the chips cool and the fact that length scales are quickly approaching those of a single atom. A silicon laser could help chip makers beat these limitations by harnessing light, thus reducing the size and cost of microelectronic circuits even further,while at the same time increasing their speed. The problem is that silicon is a very inefficient light emitter, which means that silicon-based optoelectronics has remained out of reach. Since 2000 all this has changed and the race to build a silicon laser has begun in earnest. Now, Mario Paniccia and colleagues at Intel in the US and Israel have demonstrated the first continuous all-silicon laser by harnessing a phenomenon called Raman scattering (Nature 433 292 and 725). (U.K.)

  15. 5GHz LTCC-based aperture coupled wireless transmitter for system-on-package applications

    KAUST Repository

    Shamim, Atif

    2012-01-01

    A novel System-on-Package (SoP) implementation is presented for a transmitter (TX) module which makes use of electromagnetic coupling between the TX chip and the package antenna. The TX chip is realized in 0.13μm CMOS process and comprises an on-chip antenna, which serves as the oscillator\\'s inductor as well. The TX chip is housed in a Low Temperature Co-fired Ceramic (LTCC) package with a patch antenna. The on-chip antenna feeds the LTCC patch antenna through aperture coupling, thus negating the need for RF buffer amplifiers, matching elements, baluns, bond wires and package transmission lines. This is the first ever demonstration of wireless-interconnect between on-chip and package antennas which increases the gain and range of the TX module manyfold with respect to the on-chip antenna alone. Though the range of the TX SoP increases considerably, power consumption remains the same as that of the TX chip only. A simple analytical model for the new wireless-interconnect has been developed which helps determine the optimum position of the chip with respect to the aperture in the ground plane.

  16. 27 CFR 19.343 - Addition of oak chips to spirits and addition of caramel to brandy and rum.

    Science.gov (United States)

    2010-04-01

    ... 27 Alcohol, Tobacco Products and Firearms 1 2010-04-01 2010-04-01 false Addition of oak chips to... PLANTS Storage § 19.343 Addition of oak chips to spirits and addition of caramel to brandy and rum. Oak chips which have not been treated with any chemical may be added to packages either prior to or...

  17. Tunable on chip optofluidic laser

    DEFF Research Database (Denmark)

    Bakal, Avraham; Vannahme, Christoph; Kristensen, Anders;

    2015-01-01

    A chip scale tunable laser in the visible spectral band is realized by generating a periodic droplet array inside a microfluidic channel. Combined with a gain medium within the droplets, the periodic structure provides the optical feedback of the laser. By controlling the pressure applied to two...

  18. Preparation for full scale demonstration of an air staged gasifier plant. Technical project development; For combined heat and power production with wood chips; Forberedelse til fuldskala demonstration af trinopdelt forgasningsanlaeg. Teknisk projektudvikling. Delrapport

    Energy Technology Data Exchange (ETDEWEB)

    Houmann Jakobsen, H.

    2011-04-15

    The project has aimed to further develop the technology for staged biomass gasification and establish an organizational and financial model to ensure that the technology can be introduced on the market. This report describes the technique in an upcoming demonstration plant. A complete planning and design of a demonstration plant with a capacity of 300 kW electric power and 700 kW heat was prepared. That is four times more than the pilot plant at Graested District Heating (Castor plant) can produce. A full scale demonstration plant with bio-gasification technology for wood chips will be established and put into operation in 2012. (ln)

  19. Packaging Technologies for High Temperature Electronics and Sensors

    Science.gov (United States)

    Chen, Liangyu; Hunter, Gary W.; Neudeck, Philip G.; Beheim, Glenn M.; Spry, David J.; Meredith, Roger D.

    2013-01-01

    This paper reviews ceramic substrates and thick-film metallization based packaging technologies in development for 500degC silicon carbide (SiC) electronics and sensors. Prototype high temperature ceramic chip-level packages and printed circuit boards (PCBs) based on ceramic substrates of aluminum oxide (Al2O3) and aluminum nitride (AlN) have been designed and fabricated. These ceramic substrate-based chiplevel packages with gold (Au) thick-film metallization have been electrically characterized at temperatures up to 550degC. A 96% alumina based edge connector for a PCB level subsystem interconnection has also been demonstrated recently. The 96% alumina packaging system composed of chip-level packages and PCBs has been tested with high temperature SiC devices at 500degC for over 10,000 hours. In addition to tests in a laboratory environment, a SiC JFET with a packaging system composed of a 96% alumina chip-level package and an alumina printed circuit board mounted on a data acquisition circuit board was launched as a part of the MISSE-7 suite to the International Space Station via a Shuttle mission. This packaged SiC transistor was successfully tested in orbit for eighteen months. A spark-plug type sensor package designed for high temperature SiC capacitive pressure sensors was developed. This sensor package combines the high temperature interconnection system with a commercial high temperature high pressure stainless steel seal gland (electrical feed-through). Test results of a packaged high temperature capacitive pressure sensor at 500degC are also discussed. In addition to the pressure sensor package, efforts for packaging high temperature SiC diode-based gas chemical sensors are in process.

  20. Wood chip delivery and research project at Mikkeli region

    International Nuclear Information System (INIS)

    In 1994, a large-scale energywood production chain was started as a co-operation project by the Mikkeli city forest office and local forestry societies. Over 60 000 m3 (about 46 000 MWh of energy) of forest processed chips were delivered to Pursiala heat and power plant in Mikkeli. About 60 % of these chips was whole tree chips from improvement cuttings of young forest stands and the rest was logging waste chips from regeneration cutting areas. The average total delivery costs of forest processed chips after reduction of energywood and other subsidies were approximately 51 FIM/m3 (68 FIM/MWh) for the whole tree chips and 40 FIM/m3 (53 FIM/MWh) for logging waste chips. The delivery costs of wood chips could compete with those of fuel peat only in the most favourable cases. The resources of forest processed chips were studied on the basis of forestry plans. According to the study, there is enough raw material for permanent, large-scale delivery of forest processed chips (up to 250 000 m3/a) in the forests located at a distance of under 40 road kilometers from the Pursiala heat and power plant. The following project stages will involve further development of the wood chip delivery chain logistics, as well as improvement of logging and chipping equipment and methods in energywood and logging waste production. Also the effects of wood energy production on the economy and environment of the whole Mikkeli region will be studied. (author)

  1. 新经济形式下的包装设计尺度%Discussion on Packaging Design Scale under New Economic Form

    Institute of Scientific and Technical Information of China (English)

    过山; 熊菀君

    2009-01-01

    从可持续发展观和创建和谐社会的思路出发,研究不同类型、不同材质、不同生产工艺和不同消费群体的现代包装设计所应该遵循的基本尺度,即观念尺度、行为尺度、人为尺度,使设计师有目的、有效率地进行包装设计.%An issue ignored by most packaging designers was put forward, which was the application of natural eco-friendly materials in packaging design. The feasibility of application of natural eco-friendly materials in packaging design under existing condition was discussed with examples of traditional paper materials, natural materials, and new materials. The purpose was to promote the application of natural eco-friendly materials in food packaging.

  2. Efficacy of 10% whole Azadirachta indica (neem) chip as an adjunct to scaling and root planning in chronic periodontitis: A clinical and microbiological study

    OpenAIRE

    K Vennila; Elanchezhiyan, S.; Sugumari Ilavarasu

    2016-01-01

    Introduction: Anti-microbial therapy is essential along with conventional therapy in the management of periodontal disease. Instead of systemic chemical agents, herbal products could be used as antimicrobial agents. Herbal local drug delivery systems are effective alternative for systemic therapy in managing the chronic periodontal disease. In this study, 10% neem oil chip was used as a local drug delivery system to evaluate the efficacy in the periodontal disease management. Materials an...

  3. High-step-coverage Cu-lateral interconnections over 100 µm thick chips on a polymer substrate—an alternative method to wire bonding

    International Nuclear Information System (INIS)

    We propose a novel chip in the polymer board interconnect method for packaging different kinds of chips on a wafer level, where conventional wire bonding may not be possible due to either space or mechanical constraints. High-step-coverage copper (Cu)-lateral interconnects formed over 100 µm thick Si chips by the electroplating method have been investigated for their microstructure and electrical characteristics, using the field emission scanning electron microscope and semiconductor parameter analyzer (Agilent, 4156C). The obtained coverage ratios (i.e. the layer thickness on the chip surface to the sidewall of the chip) for each formed layer, i.e. the tantalum barrier layer, Cu seed layer, SiO2 dielectric layer and electroplated Cu layer, were 3:1, 3:1, 1.5:1 and 1:1, respectively. The measured mean electrical resistances for 36 µm × 2000 µm and 58 µm × 2000 µm interconnect lines were respectively 31.1 and 24 mΩ, and the difference between measured and calculated resistance values was less than 5%. The good quality of as-fabricated Cu-lateral interconnects was evidenced from the observed low resistance values for isolated interconnects and the linear change in daisy chain resistance with the number of interconnects. More importantly, even at a high operating temperature of 150 °C, the resistance value of the Cu-lateral interconnect over the integrated chip was very close to that of the resistance value of interconnect on the plain wafer. The suitability of this technique in integrating various chips heterogeneously was validated from the no observed change in transistor behavior due to this technique. Since this is a CMOS compatible interconnection method between the polymer substrate and chip, it can readily be scaled up to the wafer level. (paper)

  4. Heterogeneously integrated microsystem-on-a-chip

    Science.gov (United States)

    Chanchani, Rajen

    2008-02-26

    A microsystem-on-a-chip comprises a bottom wafer of normal thickness and a series of thinned wafers can be stacked on the bottom wafer, glued and electrically interconnected. The interconnection layer comprises a compliant dielectric material, an interconnect structure, and can include embedded passives. The stacked wafer technology provides a heterogeneously integrated, ultra-miniaturized, higher performing, robust and cost-effective microsystem package. The highly integrated microsystem package, comprising electronics, sensors, optics, and MEMS, can be miniaturized both in volume and footprint to the size of a bottle-cap or less.

  5. High Temperature Pt/Alumina Co-Fired System for 500 C Electronic Packaging Applications

    Science.gov (United States)

    Chen, Liang-Yu; Neudeck, Philip G.; Spry, David J.; Beheim, Glenn M.; Hunter, Gary W.

    2015-01-01

    Gold thick-film metallization and 96 alumina substrate based prototype packaging system developed for 500C SiC electronics and sensors is briefly reviewed, the needs of improvement are discussed. A high temperature co-fired alumina material system based packaging system composed of 32-pin chip-level package and printed circuit board is discussed for packaging 500C SiC electronics and sensors.

  6. Cool down computer chips with liquid metal device driven by the heat of chips

    Institute of Scientific and Technical Information of China (English)

    2008-01-01

    @@ With the soaring advances in computational speed, thermal management becomes a major concern in computer systems. To remove heat generated by computer chips or very large scale integrated circuits, a research team headed by Prof.

  7. ATLAS software packaging

    CERN Document Server

    Rybkin, G

    2012-01-01

    Software packaging is indispensable part of build and prerequisite for deployment processes. Full ATLAS software stack consists of TDAQ, HLT, and Offline software. These software groups depend on some 80 external software packages. We present tools, package PackDist, developed and used to package all this software except for TDAQ project. PackDist is based on and driven by CMT, ATLAS software configuration and build tool, and consists of shell and Python scripts. The packaging unit used is CMT project. Each CMT project is packaged as several packages - platform dependent (one per platform available), source code excluding header files, other platform independent files, documentation, and debug information packages (the last two being built optionally). Packaging can be done recursively to package all the dependencies. The whole set of packages for one software release, distribution kit, also includes configuration packages and contains some 120 packages for one platform. Also packaged are physics analysis pro...

  8. Use of pilot plant scale continuous fryer to simulate industrial production of potato chips: thermal properties of palm olein blends under continuous frying conditions

    OpenAIRE

    Tarmizi, Azmil Haizam Ahmad; Ismail, Razali

    2013-01-01

    Binary blends of palm olein (PO) with sunflower oil (SFO), canola oil (CNO), and cottonseed oil (CSO) were formulated to assess their stability under continuous frying conditions. The results were then compared with those obtained in PO. The oil blends studied were: (1) 60:40 for PO + SFO; (2) 70:30 for PO + CNO; and (3) 50:50 for PO + CSO. The PO and its blends were used to fry potato chips at 180°C for a total of 56 h of operation. The evolution of analytical parameters such as tocols, indu...

  9. Status and prospects for phosphor-based white LED packaging

    Institute of Scientific and Technical Information of China (English)

    Zongyuan LIU; Sheng LIU; Kai WANG; Xiaobing LUO

    2009-01-01

    The status and prospects for high-power, phosphor-based white light-emitting diode (LED) pack-aging have been presented. A system view for packaging design is proposed to address packaging issues. Four aspects of packaging are reviewed: optical control, thermal management, reliability and cost. Phosphor materials play the most important role in light extraction and color control. The conformal coating method improves the spatial color distribution (SCD) of LEDs. High refractive index (RI) encapsulants with high transmittance and modified surface morphology can enhance light extraction. Multi-phosphor-based packaging can realize the control of correlated color temperature (CCT) with high color rendering index (CRI). Effective thermal management can dissipate heat rapidly and reduce thermal stress caused by the mismatch of the coefficient of thermal expansion (CTE). Chip-on-board (COB) technology with a multi-layer ceramic substrate is the most promising method for high-power LED packaging. Low junction temperature will improve the reliability and provide longer life. Advanced processes, precise fabrication and careful operation are essential for high reliability LEDs. Cost is one of the biggest obstacles for the penetration of white LEDs into the market for general illumination products. Mass production in terms of CoB, system in packaging (SIP), 3D packaging and wafer level packaging (WLP) can reduce the cost significantly, especially when chip cost is lowered by using a large wafer size.

  10. Automating dChip: toward reproducible sharing of microarray data analysis

    Directory of Open Access Journals (Sweden)

    Li Cheng

    2008-05-01

    Full Text Available Abstract Background During the past decade, many software packages have been developed for analysis and visualization of various types of microarrays. We have developed and maintained the widely used dChip as a microarray analysis software package accessible to both biologist and data analysts. However, challenges arise when dChip users want to analyze large number of arrays automatically and share data analysis procedures and parameters. Improvement is also needed when the dChip user support team tries to identify the causes of reported analysis errors or bugs from users. Results We report here implementation and application of the dChip automation module. Through this module, dChip automation files can be created to include menu steps, parameters, and data viewpoints to run automatically. A data-packaging function allows convenient transfer from one user to another of the dChip software, microarray data, and analysis procedures, so that the second user can reproduce the entire analysis session of the first user. An analysis report file can also be generated during an automated run, including analysis logs, user comments, and viewpoint screenshots. Conclusion The dChip automation module is a step toward reproducible research, and it can prompt a more convenient and reproducible mechanism for sharing microarray software, data, and analysis procedures and results. Automation data packages can also be used as publication supplements. Similar automation mechanisms could be valuable to the research community if implemented in other genomics and bioinformatics software packages.

  11. Pixel detector readout chip

    CERN Multimedia

    1991-01-01

    Close-up of a pixel detector readout chip. The photograph shows an aera of 1 mm x 2 mm containing 12 separate readout channels. The entire chip contains 1000 readout channels (around 80 000 transistors) covering a sensitive area of 8 mm x 5 mm. The chip has been mounted on a silicon detector to detect high energy particles.

  12. White LED with High Package Extraction Efficiency

    International Nuclear Information System (INIS)

    The goal of this project is to develop a high efficiency phosphor converting (white) Light Emitting Diode (pcLED) 1-Watt package through an increase in package extraction efficiency. A transparent/translucent monolithic phosphor is proposed to replace the powdered phosphor to reduce the scattering caused by phosphor particles. Additionally, a multi-layer thin film selectively reflecting filter is proposed between blue LED die and phosphor layer to recover inward yellow emission. At the end of the project we expect to recycle approximately 50% of the unrecovered backward light in current package construction, and develop a pcLED device with 80 lm/We using our technology improvements and commercially available chip/package source. The success of the project will benefit luminous efficacy of white LEDs by increasing package extraction efficiency. In most phosphor-converting white LEDs, the white color is obtained by combining a blue LED die (or chip) with a powdered phosphor layer. The phosphor partially absorbs the blue light from the LED die and converts it into a broad green-yellow emission. The mixture of the transmitted blue light and green-yellow light emerging gives white light. There are two major drawbacks for current pcLEDs in terms of package extraction efficiency. The first is light scattering caused by phosphor particles. When the blue photons from the chip strike the phosphor particles, some blue light will be scattered by phosphor particles. Converted yellow emission photons are also scattered. A portion of scattered light is in the backward direction toward the die. The amount of this backward light varies and depends in part on the particle size of phosphors. The other drawback is that yellow emission from phosphor powders is isotropic. Although some backward light can be recovered by the reflector in current LED packages, there is still a portion of backward light that will be absorbed inside the package and further converted to heat. Heat generated

  13. White LED with High Package Extraction Efficiency

    Energy Technology Data Exchange (ETDEWEB)

    Yi Zheng; Matthew Stough

    2008-09-30

    The goal of this project is to develop a high efficiency phosphor converting (white) Light Emitting Diode (pcLED) 1-Watt package through an increase in package extraction efficiency. A transparent/translucent monolithic phosphor is proposed to replace the powdered phosphor to reduce the scattering caused by phosphor particles. Additionally, a multi-layer thin film selectively reflecting filter is proposed between blue LED die and phosphor layer to recover inward yellow emission. At the end of the project we expect to recycle approximately 50% of the unrecovered backward light in current package construction, and develop a pcLED device with 80 lm/W{sub e} using our technology improvements and commercially available chip/package source. The success of the project will benefit luminous efficacy of white LEDs by increasing package extraction efficiency. In most phosphor-converting white LEDs, the white color is obtained by combining a blue LED die (or chip) with a powdered phosphor layer. The phosphor partially absorbs the blue light from the LED die and converts it into a broad green-yellow emission. The mixture of the transmitted blue light and green-yellow light emerging gives white light. There are two major drawbacks for current pcLEDs in terms of package extraction efficiency. The first is light scattering caused by phosphor particles. When the blue photons from the chip strike the phosphor particles, some blue light will be scattered by phosphor particles. Converted yellow emission photons are also scattered. A portion of scattered light is in the backward direction toward the die. The amount of this backward light varies and depends in part on the particle size of phosphors. The other drawback is that yellow emission from phosphor powders is isotropic. Although some backward light can be recovered by the reflector in current LED packages, there is still a portion of backward light that will be absorbed inside the package and further converted to heat. Heat

  14. High-performance packaging for monolithic microwave and millimeter-wave integrated circuits

    Science.gov (United States)

    Shalkhauser, K. A.; Li, K.; Shih, Y. C.

    1992-01-01

    Packaging schemes are developed that provide low-loss, hermetic enclosure for enhanced monolithic microwave and millimeter-wave integrated circuits. These package schemes are based on a fused quartz substrate material offering improved RF performance through 44 GHz. The small size and weight of the packages make them useful for a number of applications, including phased array antenna systems. As part of the packaging effort, a test fixture was developed to interface the single chip packages to conventional laboratory instrumentation for characterization of the packaged devices.

  15. Study on localized induction heating for wafer level packaging

    Institute of Scientific and Technical Information of China (English)

    2010-01-01

    Micro-electro-mechanical systems(MEMS)are being developed as a new multi-disciplinary technology,which will undoubtedly have a revolutionary impact on the future of human life.However,with the development of MEMS technology,the packaging has become the main technical obstacle to the commercialization of MEMS.An approach to MEMS packaging by high-frequency electromagnetic induction heating at wafer level is presented in terms of numerical simulation and experimental study.The structure of inductor is firstly designed and optimized.Then the heating situation of PCB board is verified.The results indicate that the heat impact on the chip during the packaging process can be effectively reduced by local induction heating packaging,therefore the thermal stress on the chip is considerably lowered.This method can effectively improve the reliability of the MEMS devices.

  16. Colour Design for Carton-Packed Fruit Juice Packages

    OpenAIRE

    Wei, Shuo-Ting; Ou, Li-Chen; Luo, M. Ronnier

    2009-01-01

    The present research studies the relationships between observers’ expectations for 7 fruit juice packages and the colour design of the package. To do this, a two-stage experiment was conducted. At the first stage, we studied perceived colours for the fruit images shown on each package. At the second stage, fruit juice packages with 20 package colours were rated using 5 bipolar scales: colour harmony, preference, freshness, naturalness and product quality. The experimental results show that th...

  17. Advanced Flip Chips in Extreme Temperature Environments

    Science.gov (United States)

    Ramesham, Rajeshuni

    2010-01-01

    material and the silicon die or chip, and also the underfill materials. Advanced packaging interconnects technology such as flip-chip interconnect test boards have been subjected to various extreme temperature ranges that cover military specifications and extreme Mars and asteroid environments. The eventual goal of each process step and the entire process is to produce components with 100 percent interconnect and satisfy the reliability requirements. Underfill materials, in general, may possibly meet demanding end use requirements such as low warpage, low stress, fine pitch, high reliability, and high adhesion.

  18. Redsharc: A Programming Model and On-Chip Network for Multi-Core Systems on a Programmable Chip

    OpenAIRE

    Kritikos, William V.; Andrew G. Schmidt; Ron Sass; Anderson, Erik K.; Matthew French

    2012-01-01

    The reconfigurable data-stream hardware software architecture (Redsharc) is a programming model and network-on-a-chip solution designed to scale to meet the performance needs of multi-core Systems on a programmable chip (MCSoPC). Redsharc uses an abstract API that allows programmers to develop systems of simultaneously executing kernels, in software and/or hardware, that communicate over a seamless interface. Redsharc incorporates two on-chip networks that directly implement the API to suppor...

  19. Demountable, high density package for high-speed testing of superconducting circuits

    International Nuclear Information System (INIS)

    This paper reports on a package that permits both quick integrated circuit (IC) throughput and high signal speed testing of superconducting devices and circuits. THe package contains 21 high-speed transmission lines and 64 dc bias lines contacting a 1 cm2 i.e. A novel demountable flip-chip connector incorporating both spring loaded and cantilever beam contacts maintains adequate chip to carrier continuity to allow signals from dc to 2 GHz to pass with minimal distortion at 4.2 K. The modular design of the connector and chip carrier allows maximum versatility in fast turnaround time testing

  20. Chip-on-flex with 5-micron features

    Science.gov (United States)

    Salmon, Peter C.

    2003-01-01

    A new module packaging method is proposed for electronic systems comprising a motherboard and integrated circuit (IC) chips. Pitches of 10 microns for conductive traces, and 100 microns for bonding pads are achievable. The enabling technology is glass panel manufacture, using equipment and techniques similar to those employed for fabricating liquid crystal display (LCD) panels. Flexible circuits are produced on a glass carrier using a release layer, and the carrier is removed after most of the processing is complete. IC chips are stud bumped and flip chip bonded to wells filled with solder, provided on the flexible circuit. The fabrication density achievable with wafer level packaging (WLP) using silicon wafers is substantially more than is needed for module packaging, as described herein. It is possible to provide WLP performance on glass at a much lower cost. The conductor features on glass are fine enough for the most demanding packaging and assembly techniques. The lowered cost of glass applies to the interconnection circuit plus assembly, test and rework. A test method called Tester-On-Board (TOB) is proposed, employing special-purpose test chips that are directly mounted in the system and mimic the capabilities of external testers. Methods for hermetic sealing, electromagnetic screening, and high-density off-board connections are also proposed.

  1. Packaging of silicon sensors for microfluidic bio-analytical applications

    International Nuclear Information System (INIS)

    A new industrial concept is presented for packaging biosensor chips in disposable microfluidic cartridges to enable medical diagnostic applications. The inorganic electronic substrates, such as silicon or glass, are integrated in a polymer package which provides the electrical and fluidic interconnections to the world and provides mechanical strength and protection for out-of-lab use. The demonstrated prototype consists of a molded interconnection device (MID), a silicon-based giant magneto-resistive (GMR) biosensor chip, a flex and a polymer fluidic part with integrated tubing. The various processes are compatible with mass manufacturing and run at a high yield. The devices show a reliable electrical interconnection between the sensor chip and readout electronics during extended wet operation. Sandwich immunoassays were carried out in the cartridges with surface functionalized sensor chips. Biological response curves were determined for different concentrations of parathyroid hormone (PTH) on the packaged biosensor, which demonstrates the functionality and biocompatibility of the devices. The new packaging concept provides a platform for easy further integration of electrical and fluidic functions, as for instance required for integrated molecular diagnostic devices in cost-effective mass manufacturing

  2. Quality requirements for forest chips; Kaeyttaejien laatuvaatimukset metsaehakkeelle

    Energy Technology Data Exchange (ETDEWEB)

    Impola, R. [VTT Energy, Jyvaeskylae (Finland)

    1999-07-01

    utilization of forest chips. Increasing utilization volumes may require industrial-scale production of forest chips. By using proper storage arrangements, it is possible to guarantee the better quality of forest chips and the deliveries all year round even when the road conditions are poor. Significant factors effecting on the utilization of forest chips in the future are also the price of the chips and the price-competitiveness on site compared to other fuels.

  3. ANALYTICAL CHIP FORMATION MODEL OF MICRO-END-MILLING

    Institute of Scientific and Technical Information of China (English)

    LI Chengfeng; LAI Xinmin; LI Hongtao; PENG Linfa; NI Jun

    2008-01-01

    A new analytical chip formation model is proposed for micro-end-milling operations. The model calculates an instantaneous uncut chip thickness by considering the combination of exact trochoidal trajectory of the tool tip and tool run-out, while the simplified circular trajectory and the neglected run-out create negligible change in conventional-scale chip formation models. Newton-Raphson iterative method is employed during the calculation to obtain quadratic convergence. The proposed approach allows the calculation of instantaneous uncut chip thickness to be done accurately and rapidly, and the prediction accuracy of this model is also verified by comparing the simulation results to experimental cutting forces.

  4. Chip Multithreaded Consistency Model

    Institute of Scientific and Technical Information of China (English)

    Zu-Song Li; Dan-Dan Huan; Wei-Wu Hu; Zhi-Min Tang

    2008-01-01

    Multithreaded technique is the developing trend of high performance processor. Memory consistency model is essential to the correctness, performance and complexity of multithreaded processor. The chip multithreaded consistency model adapting to multithreaded processor is proposed in this paper. The restriction imposed on memory event ordering by chip multithreaded consistency is presented and formalized. With the idea of critical cycle built by Wei-Wu Hu, we prove that the proposed chip multithreaded consistency model satisfies the criterion of correct execution of sequential consistency model. Chip multithreaded consistency model provides a way of achieving high performance compared with sequential consistency model and ensures the compatibility of software that the execution result in multithreaded processor is the same as the execution result in uniprocessor. The implementation strategy of chip multithreaded consistency model in Godson-2 SMT processor is also proposed. Godson-2 SMT processor supports chip multithreaded consistency model correctly by exception scheme based on the sequential memory access queue of each thread.

  5. Materials for optoelectronic device packaging/manufacturing

    Science.gov (United States)

    Lin, Yuan-Chang

    The first part of this work is to review the materials challenges and solutions for the packaging of high power LEDs, i.e., the light extraction efficiency, thermal and UV stability, and stress/delamination, which are all related to the reliability and lifetime of high power LEDs. The second part of this work is related to the development of transparent epoxy and silicone materials for the packaging of LEDs and the studies of light transmission stability under various treatments, including thermal, UV and combined treatments. It is found out that packaged high power blue LEDs encapsulated by epoxy materials have a very short lifetime due to the severe discoloration of epoxy at die-encapsulant interface caused by high flux radiation and junction temperature from LED chip. However, the reliability of formulated silicone outperforms epoxy materials, which can be explain by highly transparent in the UV-visible wavelength region and better thermal and UV resistance of silicone materials. The third part of this work is related to the study of optical properties of white LEDs, i.e., optical power, luminous efficiency, CCT, chromaticity coordinate and CRI as a function of phosphor wt% in silicone for the flat-top (FT) and flat-top-with lens (FTWL) packages. Due to the total internal reflection (TIR) at the encapsulant-air interface, the FT package shows a 10˜11% power (in mW) reduction compared with the FTWL package at the same phosphor concentration. However, it is demonstrated that the FT package provides a more efficient way of utilizing phosphor than the FTWL package based on the same targeted chromaticity coordinates due to the TIR effect inside, resulting in a reduced phosphor usage with a lumen output only about 3% lower than that of the FTWL package. Furthermore, the effects of fumed silica on optical properties are studied for these packages. In comparison to the package without fumed silica, the package with fumed silica has the advantages in anti-settling of

  6. Use of forest chips in Finland. Position paper for 1999

    International Nuclear Information System (INIS)

    Finland has decided to raise the energy use of forest chips to 5 million m3 solid by 2010. This corresponds to 0.9 million tonnes of oil equivalent. In order to monitor the ongoing development and the effectiveness of energy policy matters, the Wood Energy Technology Program of Tekes executed a survey of the use of forest chips in 1999. Forest chips were used in 135 heating plants (minimum size 0,5 MW), 21 power plants, and several thousands of small buildings and farm houses. The commercial use was 567 000 m3 solid and small-scale non- commercial use 180 000 m3 solid. The use of forest chips is increasing rapidly especially in combined production of heat and electricity. The report gives information on the use in plants of different size, seasonal variation of use, raw material sources of chips, moisture content of chips, and the development of prices. During the 1990s, the average price of forest chips was reduced by 35 %. In 1999, the average price at the plant was 61 FIM/MWh for whole-tree chips, 44 FIM/MWh for chips reduced from logging residues from forest regeneration areas, and 53 FIM/MWh for the entire flow of forest chips, VAT excluded. (orig.)

  7. Use of pilot plant scale continuous fryer to simulate industrial production of potato chips: thermal properties of palm olein blends under continuous frying conditions.

    Science.gov (United States)

    Tarmizi, Azmil Haizam Ahmad; Ismail, Razali

    2014-01-01

    Binary blends of palm olein (PO) with sunflower oil (SFO), canola oil (CNO), and cottonseed oil (CSO) were formulated to assess their stability under continuous frying conditions. The results were then compared with those obtained in PO. The oil blends studied were: (1) 60:40 for PO + SFO; (2) 70:30 for PO + CNO; and (3) 50:50 for PO + CSO. The PO and its blends were used to fry potato chips at 180°C for a total of 56 h of operation. The evolution of analytical parameters such as tocols, induction period, color, p-anisidine value, free fatty acid, smoke point, polar compounds, and polymer compounds were evaluated over the frying time. Blending PO with unsaturated oils was generally proved to keep most qualitative parameters comparable to those demonstrated in PO. Indeed, none of the oils surpassed the legislative limits for used frying. Overall, it was noted that oil containing PO and SFO showed higher resistance toward oxidative and hydrolytic behaviors as compared to the other oil blends. PMID:24804062

  8. Chlorhexidine Chip in the Treatment of Chronic Periodontitis – A Clinical Study

    OpenAIRE

    Medaiah, Sangeetha; Srinivas, M; Melath, Anil; Girish, Suragimath; Polepalle, Tejaswin; Dasari, Ankineedu Babu

    2014-01-01

    Aim: The aim of this study was to clinically evaluate the use of biodegradable chlorhexidine chip when used as an adjunct to scaling and root planing (SRP) in the treatment of moderate to severe periodontitis patients. The study also intended to compare the combined therapy (SRP and Chlorhexidine chip) with chlorhexidine chip alone in individuals with periodontitis.

  9. Implementation of Guaranteed Services in the MANGO Clockless Network-on-Chip

    DEFF Research Database (Denmark)

    Bjerregaard, Tobias; Sparsø, Jens

    2006-01-01

    Shared, segmented, on-chip interconnection networks, known as networks-on-chip (NoC), may become the preferred way of interconnecting intellectual property (IP) cores in future giga-scale system-on-chip (SoC) designs. A NoC can provide the required communication bandwidth while accommodating the...

  10. Packaging for logistical support

    Science.gov (United States)

    Twede, Diana; Hughes, Harold

    Logistical packaging is conducted to furnish protection, utility, and communication for elements of a logistical system. Once the functional requirements of space logistical support packaging have been identified, decision-makers have a reasonable basis on which to compare package alternatives. Flexible packages may be found, for example, to provide adequate protection and superior utility to that of rigid packages requiring greater storage and postuse waste volumes.

  11. Development of gold based solder candidates for flip chip assembly

    DEFF Research Database (Denmark)

    Chidambaram, Vivek; Hald, John; Hattel, Jesper Henri

    2009-01-01

    Flip chip technology is now rapidly replacing the traditional wire bonding interconnection technology in the first level packaging applications due to the miniaturization drive in the microelectronics industry. Flip chip assembly currently involves the use of high lead containing solders...... for interconnecting the chip to a carrier in certain applications due to the unique properties of lead. Despite of all the beneficial attributes of lead, its potential environmental impact when the products are discarded to land fills has resulted in various legislatives to eliminate lead from the electronic products...... based on its notorious legacy as a major health hazard across the spectrum of human generations and cultures. Flip chip assembly is also now increasingly being used for the high-performance (H-P) systems. These H-P systems perform mission-critical operations and are expected to experience virtually...

  12. Challenges in the Packaging of MEMS

    Energy Technology Data Exchange (ETDEWEB)

    BROWN, WILLIAM D.; EATON, WILLIAM P.; MALSHE, AJAY P.; MILLER, WILLIAM M.; O' NEAL, CHAD; SINGH, SUSHILA B.

    1999-09-24

    Microelectromechanical Systems (MEMS) packaging is much different from conventional integrated circuit (IC) packaging. Many MEMS devices must interface to the environment in order to perform their intended function, and the package must be able to facilitate access with the environment while protecting the device. The package must also not interfere with or impede the operation of the MEMS device. The die attachment material should be low stress, and low outgassing, while also minimizing stress relaxation overtime which can lead to scale factor shifts in sensor devices. The fabrication processes used in creating the devices must be compatible with each other, and not result in damage to the devices. Many devices are application specific requiring custom packages that are not commercially available. Devices may also need media compatible packages that can protect the devices from harsh environments in which the MEMS device may operate. Techniques are being developed to handle, process, and package the devices such that high yields of functional packaged parts will result. Currently, many of the processing steps are potentially harmful to MEMS devices and negatively affect yield. It is the objective of this paper to review and discuss packaging challenges that exist for MEMS systems and to expose these issues to new audiences from the integrated circuit packaging community.

  13. Alumina Based 500 C Electronic Packaging Systems and Future Development

    Science.gov (United States)

    Chen, Liang-Yu

    2012-01-01

    NASA space and aeronautical missions for probing the inner solar planets as well as for in situ monitoring and control of next-generation aeronautical engines require high-temperature environment operable sensors and electronics. A 96% aluminum oxide and Au thick-film metallization based packaging system including chip-level packages, printed circuit board, and edge-connector is in development for high temperature SiC electronics. An electronic packaging system based on this material system was successfully tested and demonstrated with SiC electronics at 500 C for over 10,000 hours in laboratory conditions previously. In addition to the tests in laboratory environments, this packaging system has more recently been tested with a SiC junction field effect transistor (JFET) on low earth orbit through the NASA Materials on the International Space Station Experiment 7 (MISSE7). A SiC JFET with a packaging system composed of a 96% alumina chip-level package and an alumina printed circuit board mounted on a data acquisition circuit board was launched as a part of the MISSE7 suite to International Space Station via a Shuttle mission and tested on the orbit for eighteen months. A summary of results of tests in both laboratory and space environments will be presented. The future development of alumina based high temperature packaging using co-fired material systems for improved performance at high temperature and more feasible mass production will also be discussed.

  14. Packaging of photodetector modules for 100 Gbit/s applications using electromagnetic simulations

    DEFF Research Database (Denmark)

    Jiang, Chenhui; Krozer, Viktor; Bach, H.-G.;

    2009-01-01

    conversion loss due to mode mismatch is identified as the dominant effect of limiting bandwidth of packaged modules. Finally, PD chips are successfully packaged by using wire-bonding technology and conventional coplanar waveguide (CPW) for avoiding mode mismatch. The new packaged PD module demonstrates......In this paper we demonstrate ultra-broadband packaging and interconnection designs for photodetector (PD) modules for 100 Gbit/s data transmission applications. The design of packaging and interconnection structures is based on accurate and reliable 3D electromagnetic (EM) simulations. Mode...

  15. Optimal and Robust Design Method for Two-Chip Out-of-Plane Microaccelerometers

    Directory of Open Access Journals (Sweden)

    Hyoungho Ko

    2010-11-01

    Full Text Available In this paper, an optimal and robust design method to implement a two-chip out-of-plane microaccelerometer system is presented. The two-chip microsystem consists of a MEMS chip for sensing the external acceleration and a CMOS chip for signal processing. An optimized design method to determine the device thickness, the sacrificial gap, and the vertical gap length of the M EMS sensing element is applied to minimize the fundamental noise level and also to achieve the robustness to the fabrication variations. In order to cancel out the offset and gain variations due to parasitic capacitances and process variations, a digitally trimmable architecture consisting of an 11 bit capacitor array is adopted in the analog front-end of the CMOS capacitive readout circuit. The out-of-plane microaccelerometer has the scale factor of 372 mV/g~389 mV/g, the output nonlinearity of 0.43% FSO~0.60% FSO, the input range of ±2 g and a bias instability of 122 μg~229 μg. The signal-to-noise ratio and the noise equivalent resolution are measured to be74.00 dB~75.23 dB and 180 μg/rtHz~190 μg/rtHz, respectively. The in-plane cross-axis sensitivities are measured to be 1.1%~1.9% and 0.3%~0.7% of the out-of-plane sensitivity, respectively. The results show that the optimal and robust design method for the MEMS sensing element and the highly trimmable capacity of the CMOS capacitive readout circuit are suitable to enhance the die-to-die uniformity of the packaged microsystem, without compromising the performance characteristics.

  16. Hybrid photonic chip interferometer for embedded metrology

    Science.gov (United States)

    Kumar, P.; Martin, H.; Maxwell, G.; Jiang, X.

    2014-03-01

    Embedded metrology is the provision of metrology on the manufacturing platform, enabling measurement without the removal of the work piece. Providing closer integration of metrology upon the manufacturing platform can lead to the better control and increased throughput. In this work we present the development of a high precision hybrid optical chip interferometer metrology device. The complete metrology sensor system is structured into two parts; optical chip and optical probe. The hybrid optical chip interferometer is based on a silica-on-silicon etched integrated-optic motherboard containing waveguide structures and evanescent couplers. Upon the motherboard, electro-optic components such as photodiodes and a semiconductor gain block are mounted and bonded to provide the required functionality. The key structure in the device is a tunable laser module based upon an external-cavity diode laser (ECDL). Within the cavity is a multi-layer thin film filter which is rotated to select the longitudinal mode at which the laser operates. An optical probe, which uses a blazed diffracting grating and collimating objective lens, focuses light of different wavelengths laterally over the measurand. Incident laser light is then tuned in wavelength time to effectively sweep an `optical stylus' over the surface. Wavelength scanning and rapid phase shifting can then retrieve the path length change and thus the surface height. We give an overview of the overall design of the final hybrid photonic chip interferometer, constituent components, device integration and packaging as well as experimental test results from the current version now under evaluation.

  17. BAE systems' SMART chip camera FPA development

    Science.gov (United States)

    Sengupta, Louise; Auroux, Pierre-Alain; McManus, Don; Harris, D. Ahmasi; Blackwell, Richard J.; Bryant, Jeffrey; Boal, Mihir; Binkerd, Evan

    2015-06-01

    BAE Systems' SMART (Stacked Modular Architecture High-Resolution Thermal) Chip Camera provides very compact long-wave infrared (LWIR) solutions by combining a 12 μm wafer-level packaged focal plane array (FPA) with multichip-stack, application-specific integrated circuit (ASIC) and wafer-level optics. The key innovations that enabled this include a single-layer 12 μm pixel bolometer design and robust fabrication process, as well as wafer-level lid packaging. We used advanced packaging techniques to achieve an extremely small-form-factor camera, with a complete volume of 2.9 cm3 and a thermal core weight of 5.1g. The SMART Chip Camera supports up to 60 Hz frame rates, and requires less than 500 mW of power. This work has been supported by the Defense Advanced Research Projects Agency's (DARPA) Low Cost Thermal Imager - Manufacturing (LCTI-M) program, and BAE Systems' internal research and development investment.

  18. CHIP, CHIP, ARRAY! THREE CHIPS FOR POST-GENOMIC RESEARCH

    Science.gov (United States)

    Cambridge Healthtech Institute recently held the 4th installment of their popular "Lab-on-a-Chip" series in Zurich, Switzerland. As usual, it was enthusiastically received and over 225 people attended the 2-1/2 day meeting to see and hear about some of the latest developments an...

  19. Mathematical Simulation for Integrated Linear Fresnel Spectrometer Chip

    Science.gov (United States)

    Park, Yeonjoon; Yoon, Hargoon; Lee, Uhn; King, Glen C.; Choi, Sang H.

    2012-01-01

    A miniaturized solid-state optical spectrometer chip was designed with a linear gradient-gap Fresnel grating which was mounted perpendicularly to a sensor array surface and simulated for its performance and functionality. Unlike common spectrometers which are based on Fraunhoffer diffraction with a regular periodic line grating, the new linear gradient grating Fresnel spectrometer chip can be miniaturized to a much smaller form-factor into the Fresnel regime exceeding the limit of conventional spectrometers. This mathematical calculation shows that building a tiny motionless multi-pixel microspectrometer chip which is smaller than 1 cubic millimter of optical path volume is possible. The new Fresnel spectrometer chip is proportional to the energy scale (hc/lambda), while the conventional spectrometers are proportional to the wavelength scale (lambda). We report the theoretical optical working principle and new data collection algorithm of the new Fresnel spectrometer to build a compact integrated optical chip.

  20. Mathematical simulation for integrated linear Fresnel spectrometer chip

    Science.gov (United States)

    Park, Yeonjoon; Yoon, Hargsoon; Lee, Uhn; King, Glen C.; Choi, Sang

    2012-04-01

    A miniaturized solid-state optical spectrometer chip was designed with a linear gradient-gap Fresnel grating which was mounted perpendicularly to a sensor array surface and simulated for its performance and functionality. Unlike common spectrometers which are based on Fraunhoffer diffraction with a regular periodic line grating, the new linear gradient grating Fresnel spectrometer chip can be miniaturized to a much smaller form-factor into the Fresnel regime exceeding the limit of conventional spectrometers. This mathematical calculation shows that building a tiny motionless multi-pixel microspectrometer chip which is smaller than 1mm3 of optical path volume is possible. The new Fresnel spectrometer chip is proportional to the energy scale (hc/λ), while the conventional spectrometers are proportional to the wavelength scale (λ). We report the theoretical optical working principle and new data collection algorithm of the new Fresnel spectrometer to build a compact integrated optical chip.

  1. ALICE chip processor

    CERN Multimedia

    Maximilien Brice

    2003-01-01

    This tiny chip provides data processing for the time projection chamber on ALICE. Known as the ALICE TPC Read Out (ALTRO), this device was designed to minimize the size and power consumption of the TPC front end electronics. This single chip contains 16 low-power analogue-to-digital converters with six million transistors of digital processing and 8 kbits of data storage.

  2. The reduction of packaging waste

    Energy Technology Data Exchange (ETDEWEB)

    Raney, E.A.; Hogan, J.J.; McCollom, M.L.; Meyer, R.J.

    1994-04-01

    Nationwide, packaging waste comprises approximately one-third of the waste disposed in sanitary landfills. the US Department of Energy (DOE) generated close to 90,000 metric tons of sanitary waste. With roughly one-third of that being packaging waste, approximately 30,000 metric tons are generated per year. The purpose of the Reduction of Packaging Waste project was to investigate opportunities to reduce this packaging waste through source reduction and recycling. The project was divided into three areas: procurement, onsite packaging and distribution, and recycling. Waste minimization opportunities were identified and investigated within each area, several of which were chosen for further study and small-scale testing at the Hanford Site. Test results, were compiled into five ``how-to`` recipes for implementation at other sites. The subject of the recipes are as follows: (1) Vendor Participation Program; (2) Reusable Containers System; (3) Shrink-wrap System -- Plastic and Corrugated Cardboard Waste Reduction; (4) Cardboard Recycling ; and (5) Wood Recycling.

  3. Waste Package Lifting Calculation

    International Nuclear Information System (INIS)

    The objective of this calculation is to evaluate the structural response of the waste package during the horizontal and vertical lifting operations in order to support the waste package lifting feature design. The scope of this calculation includes the evaluation of the 21 PWR UCF (pressurized water reactor uncanistered fuel) waste package, naval waste package, 5 DHLW/DOE SNF (defense high-level waste/Department of Energy spent nuclear fuel)--short waste package, and 44 BWR (boiling water reactor) UCF waste package. Procedure AP-3.12Q, Revision 0, ICN 0, calculations, is used to develop and document this calculation

  4. Causes of stem end chip defect in chipping potatoes

    Science.gov (United States)

    Stem-end chip defect (SECD) is a serious tuber quality concern that affects chipping potatoes. This defect is characterized by dark-colored vascular tissues and adjacent cortical tissues at the tuber stem-end of potato chips after frying. Chips with SECD are unappealing to consumers and raw product ...

  5. Effect of Joint Scale and Processing on the Fracture of Sn-3Ag-0.5Cu Solder Joints: Application to Micro-bumps in 3D Packages

    Science.gov (United States)

    Talebanpour, B.; Huang, Z.; Chen, Z.; Dutta, I.

    2016-01-01

    In 3-dimensional (3D) packages, a stack of dies is vertically connected to each other using through-silicon vias and very thin solder micro-bumps. The thinness of the micro-bumps results in joints with a very high volumetric proportion of intermetallic compounds (IMCs), rendering them much more brittle compared to conventional joints. Because of this, the reliability of micro-bumps, and the dependence thereof on the proportion of IMC in the joint, is of substantial concern. In this paper, the growth kinetics of IMCs in thin Sn-3Ag-0.5Cu joints attached to Cu substrates were analyzed, and empirical kinetic laws for the growth of Cu6Sn5 and Cu3Sn in thin joints were obtained. Modified compact mixed mode fracture mechanics samples, with adhesive solder joints between massive Cu substrates, having similar thickness and IMC content as actual micro-bumps, were produced. The effects of IMC proportion and strain rate on fracture toughness and mechanisms were investigated. It was found that the fracture toughness G C decreased with decreasing joint thickness ( h Joint). In addition, the fracture toughness decreased with increasing strain rate. Aging also promoted alternation of the crack path between the two joint-substrate interfaces, possibly proffering a mechanism to enhance fracture toughness.

  6. Comparative Packaging Study

    Science.gov (United States)

    Perchonok, Michele; Antonini, David

    2008-01-01

    This viewgraph presentation describes a comparative packaging study for use on long duration space missions. The topics include: 1) Purpose; 2) Deliverables; 3) Food Sample Selection; 4) Experimental Design Matrix; 5) Permeation Rate Comparison; and 6) Packaging Material Information.

  7. Dual Use Packaging Project

    Data.gov (United States)

    National Aeronautics and Space Administration — NASA seeks down-weighted packaging compatible with microwave preparation and perhaps high hydrostatic pressure processing. New packaging must satisfy NASA's 3-year...

  8. Merganser Download Package

    Data.gov (United States)

    U.S. Environmental Protection Agency — This data download package contains an Esri 10.0 MXD, file geodatabase and copy of this FGDC metadata record. The data in this package are used in support of the...

  9. Wood chips procurement and research project at the Mikkeli region

    International Nuclear Information System (INIS)

    In 1993-94, a large-scale energywood production chain started as a co-operation project by the Mikkeli city forest office and local forestry societies. In 1995 over 115 000 m3 (about 85 000 MWh of energy) of wood chips were delivered to Pursiala heat and power plant in Mikkeli. About 75 % of these chips was forest processed chips. About 70 % of the forest processed chips was whole tree chips from improvement cuttings of young forest stands and the rest was logging waste chips from regeneration cutting areas. The average total delivery costs of forest processed chips after reduction of energywood and other subsidies were approximately 45 FIM/m3 (60 FIM/MWh) for the whole tree chips and 38 FIM/m3 (50 FIM/MWh) for logging waste chips. The delivery costs of forest processed chips could meet the target of Bioenergy Research Programme (45 FIM/MWh) only in the most favourable cases. In an average the delivery costs were about 9 FIM/MWh more than the price obtained when sold to the heat and power plant. However the wood chip production created 27 new jobs and the increase of income to the local economy was about 2.2 milj. FIM /year. The local communities got new tax revenue about 3 FIM/MWh. The gain for the forestry was approximated to be 5 - 6 FIM/MWh. The resources of forest processed chips were studied on the basis of stand measurements. According to the study the most remarkable energywood resources were in young thinning stands on Oxalis-Myrtillus and Myrtillus forest site types. On Oxalis-Myrtillus type almost every and on Myrtillus type every second stand included energywood more than 40 m3/ha

  10. Recycling glass packaging

    OpenAIRE

    Monica Delia DOMNICA; Leila BARDAªUC

    2015-01-01

    From the specialized literature it follows that glass packaging is not as used as other packages, but in some industries are highly needed. Following, two features of glass packaging will become important until 2017: the shape of the glass packaging and glass recycling prospects in Romania. The recycling of glass is referred to the fact that it saves energy, but also to be in compliance with the provisions indicating the allowable limit values for the quantities of lead and cadmium.

  11. Materials for advanced packaging

    CERN Document Server

    Lu, Daniel

    2010-01-01

    Significant progress has been made in advanced packaging in recent years. Several new packaging techniques have been developed and new packaging materials have been introduced. This book provides a comprehensive overview of the recent developments in this industry, particularly in the areas of microelectronics, optoelectronics, digital health, and bio-medical applications. The book discusses established techniques, as well as emerging technologies, in order to provide readers with the most up-to-date developments in advanced packaging.

  12. ATLAS software packaging

    Science.gov (United States)

    Rybkin, Grigory

    2012-12-01

    Software packaging is indispensable part of build and prerequisite for deployment processes. Full ATLAS software stack consists of TDAQ, HLT, and Offline software. These software groups depend on some 80 external software packages. We present tools, package PackDist, developed and used to package all this software except for TDAQ project. PackDist is based on and driven by CMT, ATLAS software configuration and build tool, and consists of shell and Python scripts. The packaging unit used is CMT project. Each CMT project is packaged as several packages—platform dependent (one per platform available), source code excluding header files, other platform independent files, documentation, and debug information packages (the last two being built optionally). Packaging can be done recursively to package all the dependencies. The whole set of packages for one software release, distribution kit, also includes configuration packages and contains some 120 packages for one platform. Also packaged are physics analysis projects (currently 6) used by particular physics groups on top of the full release. The tools provide an installation test for the full distribution kit. Packaging is done in two formats for use with the Pacman and RPM package managers. The tools are functional on the platforms supported by ATLAS—GNU/Linux and Mac OS X. The packaged software is used for software deployment on all ATLAS computing resources from the detector and trigger computing farms, collaboration laboratories computing centres, grid sites, to physicist laptops, and CERN VMFS and covers the use cases of running all applications as well as of software development.

  13. Materials for advanced packaging

    CERN Document Server

    Wong, CP

    2008-01-01

    Significant progress has been made in advanced packaging in recent years. Several new packaging techniques have been developed and new packaging materials have been introduced. This book provides a comprehensive overview of the recent developments in this industry, particularly in the areas of microelectronics, optoelectronics, digital health, and bio-medical applications. The book discusses established techniques, as well as emerging technologies, in order to provide readers with the most up-to-date developments in advanced packaging.

  14. ATLAS software packaging

    International Nuclear Information System (INIS)

    Software packaging is indispensable part of build and prerequisite for deployment processes. Full ATLAS software stack consists of TDAQ, HLT, and Offline software. These software groups depend on some 80 external software packages. We present tools, package PackDist, developed and used to package all this software except for TDAQ project. PackDist is based on and driven by CMT, ATLAS software configuration and build tool, and consists of shell and Python scripts. The packaging unit used is CMT project. Each CMT project is packaged as several packages—platform dependent (one per platform available), source code excluding header files, other platform independent files, documentation, and debug information packages (the last two being built optionally). Packaging can be done recursively to package all the dependencies. The whole set of packages for one software release, distribution kit, also includes configuration packages and contains some 120 packages for one platform. Also packaged are physics analysis projects (currently 6) used by particular physics groups on top of the full release. The tools provide an installation test for the full distribution kit. Packaging is done in two formats for use with the Pacman and RPM package managers. The tools are functional on the platforms supported by ATLAS—GNU/Linux and Mac OS X. The packaged software is used for software deployment on all ATLAS computing resources from the detector and trigger computing farms, collaboration laboratories computing centres, grid sites, to physicist laptops, and CERN VMFS and covers the use cases of running all applications as well as of software development.

  15. Scale-4 and related modular systems for the evaluation of nuclear facilities and package design featuring criticality, shielding and transfer capabilities

    International Nuclear Information System (INIS)

    Nuclear industry, licensing and regulatory authorities need to be able to rely on good performance of computer codes and nuclear data used in calculations for design and operation of nuclear energy facilities. Given the international impact of a major nuclear accident, and the current crisis in public confidence, it is equally important that the methods, programs and data issued should be internationally accepted. The SCALE modular system has been developed and its capabilities extended during the last 15 years. The driving idea behind its development is that it should contain well established computer codes and data libraries, have an user friendly input format, combine and automate analyses requiring multiple computer codes or calculations into standard analytic sequences and to be well documented and publicly available. The fifth version called SCALE-4 has now been released through the Radiation Shielding Information Center (RSIC) to the OECD/NEA Data Bank. SCALE is now used worldwide. The NEA Data Bank alone has distributed more than one hundred copies of the different versions. The OECD/NEA Data Bank has been asked by its international management committee to hold a seminar with the purpose of exchanging information on the latest developments and experiences among code authors and users, to ensure that users have a correct understanding as to how SCALE should be used to model different problems, and to issue recommendations for further development and benchmarking

  16. Central heating: package boilers

    Energy Technology Data Exchange (ETDEWEB)

    Farahan, E.

    1977-05-01

    Performance and cost data for electrical and fossil-fired package boilers currently available from manufacturers are provided. Performance characteristics investigated include: unit efficiency, rated capacity, and average expected lifetime of units. Costs are tabulated for equipment and installation of various package boilers. The information supplied in this report will simplify the process of selecting package boilers required for industrial, commercial, and residential applications.

  17. Biobased packaging catalogue

    NARCIS (Netherlands)

    Molenveld, K.; Oever, van den M.J.A.; Bos, H.L.

    2015-01-01

    The purpose of the catalogue is to showcase biobased packaging products and provide an overview of commercially available biobased packaging in 2014. This catalogue is a translation of the Dutch version of the biobased packaging catalogue that was launched September 2014. The raw materials, products

  18. Bioclim Deliverable D8b: development of the physical/statistical down-scaling methodology and application to climate model Climber for BIOCLIM Work-package 3

    International Nuclear Information System (INIS)

    The overall aim of BIOCLIM is to assess the possible long term impacts due to climate change on the safety of radioactive waste repositories in deep formations. The main aim of this deliverable is to provide time series of climatic variables at the high resolution as needed by performance assessment (PA) of radioactive waste repositories, on the basis of coarse output from the CLIMBER-GREMLINS climate model. The climatological variables studied here are long-term (monthly) mean temperature and precipitation, as these are the main variables of interest for performance assessment. CLIMBER-GREMLINS is an earth-system model of intermediate complexity (EMIC), designed for long climate simulations (glacial cycles). Thus, this model has a coarse resolution (about 50 degrees in longitude) and other limitations which are sketched in this report. For the purpose of performance assessment, the climatological variables are required at scales pertinent for the knowledge of the conditions at the depository site. In this work, the final resolution is that of the best available global gridded present-day climatology, which is 1/6 degree in both longitude and latitude. To obtain climate-change information at this high resolution on the basis of the climate model outputs, a 2-step down-scaling method is designed. First, physical considerations are used to define variables which are expected to have links which climatological values; secondly a statistical model is used to find the links between these variables and the high-resolution climatology of temperature and precipitation. Thus the method is termed as 'physical/statistical': it involves physically based assumptions to compute predictors from model variables and then relies on statistics to find empirical links between these predictors and the climatology. The simple connection of coarse model results to regional values can not be done on a purely empirical way because the model does not provide enough information - it is both

  19. Can packaging elements elicit consumers’ emotional responses?

    DEFF Research Database (Denmark)

    Liao, Lewis; Corsi, Armando; Lockshin, Larry;

    Emotion has been an important concept in many areas of consumer research such as judgment, decision-making and advertising. Little research has been done on emotion in packaging adopting the physiological measures used in other areas. This paper draws on past studies in advertising that measure...... emotional responses toward image, colour and font, and apply them to packaging research. The study tests the extent at which packaging can elicit consumers’ spontaneous emotional response for each of those three elements, by using skin conductance, facial electromyography (EMG) and selfassessment scales....... The results show that packaging can elicit an emotional response via different elements. The paper also raises concerns about the accuracy of using selfreport measures of emotional responses to packaging research....

  20. Cleanup Verification Package for the 118-F-1 Burial Ground

    International Nuclear Information System (INIS)

    This cleanup verification package documents completion of remedial action for the 118-F-1 Burial Ground on the Hanford Site. This burial ground is a combination of two locations formerly called Minor Construction Burial Ground No. 2 and Solid Waste Burial Ground No. 2. This waste site received radioactive equipment and other miscellaneous waste from 105-F Reactor operations, including dummy elements and irradiated process tubing; gun barrel tips, steel sleeves, and metal chips removed from the reactor; filter boxes containing reactor graphite chips; and miscellaneous construction solid waste

  1. Medicaid CHIP ESPC Database

    Data.gov (United States)

    U.S. Department of Health & Human Services — The Environmental Scanning and Program Characteristic (ESPC) Database is in a Microsoft (MS) Access format and contains Medicaid and CHIP data, for the 50 states...

  2. Utilization of titanium chips

    International Nuclear Information System (INIS)

    Complex of equipment is created for realization of developed technology in experimental-inductrial production of secondary titanium alloys with annual efficiency of 50-100 t. The complex includes a section for chips preparation, facility for electride vacuum hot pressins, vacuum arc furnace for melting ingots of <200 kg. The ingots obtained will be reprocessed into bars, forgins, powers and also be used for production of shaped castings. Approbation of the developed technology was carried out by production of three types of secondary titanium lloys. The technical titanium chips were used as blend for production of TV1 alloy, chips of VT5 and PT3V alloys for TV2 and chips of VT6 and VT23 alloys for TV3 alloys. Study of chemical composition, mechanical properties and structure of secondary titanium alloys were performed on forged bars 20 mm in diameter

  3. China's first WLAN chips

    Institute of Scientific and Technical Information of China (English)

    2007-01-01

    @@ The wireless local area network (WLAN) chips independently developed by CAS researchers were in the limelight of the recent Electronic Manufacture Exposition held in Suzhou, east China's Jiangsu Province.

  4. A contact-lens-shaped IC chip technology

    International Nuclear Information System (INIS)

    We report on novel contact-lens-shaped silicon integrated circuit chip technology for applications such as forming a conforming retinal prosthesis. This is achieved by means of patterning thin films of high residual stress on top of a shaped thin silicon substrate. Several strategies are employed to achieve curvatures of various amounts. Firstly, high residual stress on a thin film makes a thin chip deform into a designed three-dimensional shape. Also, a series of patterned stress films and ‘petal-shaped’ chips were fabricated and analyzed. Large curvatures can also be formed and maintained by the packaging process of bonding the chips to constraining elements such as thin-film polymer ring structures. As a demonstration, a complementary metal oxide semiconductor transistor (CMOS) image-sensing retina chip is made into a contact-lens shape conforming to a human eyeball 12.5 mm in radius. This non-planar and flexible chip technology provides a desirable device surface interface to soft tissues or non-planar bio surfaces and opens up many other possibilities for biomedical applications. (paper)

  5. Progress in Atom Chips and the Integration of Optical Microcavities

    Science.gov (United States)

    Hinds, E. A.; Trupke, M.; Darquie, B.; Goldwin, J.; Dutier, G.

    2008-04-01

    We review recent progress at the Centre for Cold Matter in developing atom chips. An important advantage of miniaturizing atom traps on a chip is the possibility of obtaining very tight trapping structures with the capability of manipulating atoms on the micron length scale. We recall some of the pros and cons of bringing atoms close to the chip surface, as is required in order to make small static structures, and we discuss the relative merits of metallic, dielectric and superconducting chip surfaces. We point out that the addition of integrated optical devices on the chip can enhance its capability through single atom detection and controlled photon production. Finally, we review the status of integrated microcavities that have recently been demonstrated at our Centre and discuss their prospects for future development.

  6. Continuous use after 1998 of the scaling factors for radionuclide evaluation in the packaged solid wastes generated from the Shimane plant 2 of Chugoku Electric Power Company

    International Nuclear Information System (INIS)

    Low-level radioactive wastes such as concentrated-exhaust liquid and spent resins from nuclear power plants are mixed with cement, asphalt or plastics to form solidified materials and filled in the 200 litter drums. Radionuclide concentrations in the drums are confirmed by JNES (Japan Nuclear Energy Safety Organization) before sending to provisional disposal facilities. The present report describes examination processes of JNES using the same scaling factor for the wastes generated during 1999 - 2005 as used until 1998 and evaluation of its validity with specific evidence given. (S. Ohno)

  7. APPLICATION OF NANOTECHNOLOGY IN FOOD PACKAGING

    Directory of Open Access Journals (Sweden)

    Renata Dobrucka

    2014-04-01

    Full Text Available Nanotechnology involves the design, production and use of structures through control of the size and shape of the materials at the nanometre scale. Also, nanomaterials have been already applied in many fields of human life. Nanocomposites have already led to several innovations with potential applications in the food packaging sector. The use of nanocomposite formulations is expected to considerably enhance the shelf-life of many types of food. This improvement can lead to lower weight packages because less material is needed to obtain the same or even better barrier properties. This, in turn, can lead to reduced package cost with less packaging waste. Antimicrobial packaging is another area with high potential for applying nanocomposite technology. Nanostructured antimicrobials have a higher surface area-to-volume ratio when compared with their higher scale counterparts. Therefore, antimicrobial nanocomposite packaging systems are supposed to be particularly efficient in their activities against microbial cells. In this review, definition of nanomaterials is presented. Besides, the paper shows examples of nanocomposities and antimicrobial nanopackaging mainly with the use of nanosilver. Moreover, nanoparticles such ZnO, TiO2, MgO and nanosensors in packaging were presented.

  8. In-situ volumetric topography of IC chips for defect detection using infrared confocal measurement with active structured light

    International Nuclear Information System (INIS)

    The article presents the development of in-situ integrated circuit (IC) chip defect detection techniques for automated clipping detection by proposing infrared imaging and full-field volumetric topography. IC chip inspection, especially held during or post IC packaging, has become an extremely critical procedure in IC fabrication to assure manufacturing quality and reduce production costs. To address this, in the article, microscopic infrared imaging using an electromagnetic light spectrum that ranges from 0.9 to 1.7 µm is developed to perform volumetric inspection of IC chips, in order to identify important defects such as silicon clipping, cracking or peeling. The main difficulty of infrared (IR) volumetric imaging lies in its poor image contrast, which makes it incapable of achieving reliable inspection, as infrared imaging is sensitive to temperature difference but insensitive to geometric variance of materials, resulting in difficulty detecting and quantifying defects precisely. To overcome this, 3D volumetric topography based on 3D infrared confocal measurement with active structured light, as well as light refractive matching principles, is developed to detect defects the size, shape and position of defects in ICs. The experimental results show that the algorithm is effective and suitable for in-situ defect detection of IC semiconductor packaging. The quality of defect detection, such as measurement repeatability and accuracy, is addressed. Confirmed by the experimental results, the depth measurement resolution can reach up to 0.3 µm, and the depth measurement uncertainty with one standard deviation was verified to be less than 1.0% of the full-scale depth-measuring range. (paper)

  9. In-situ volumetric topography of IC chips for defect detection using infrared confocal measurement with active structured light

    Science.gov (United States)

    Chen, Liang-Chia; Le, Manh-Trung; Cong Phuc, Dao; Lin, Shyh-Tsong

    2014-09-01

    The article presents the development of in-situ integrated circuit (IC) chip defect detection techniques for automated clipping detection by proposing infrared imaging and full-field volumetric topography. IC chip inspection, especially held during or post IC packaging, has become an extremely critical procedure in IC fabrication to assure manufacturing quality and reduce production costs. To address this, in the article, microscopic infrared imaging using an electromagnetic light spectrum that ranges from 0.9 to 1.7 µm is developed to perform volumetric inspection of IC chips, in order to identify important defects such as silicon clipping, cracking or peeling. The main difficulty of infrared (IR) volumetric imaging lies in its poor image contrast, which makes it incapable of achieving reliable inspection, as infrared imaging is sensitive to temperature difference but insensitive to geometric variance of materials, resulting in difficulty detecting and quantifying defects precisely. To overcome this, 3D volumetric topography based on 3D infrared confocal measurement with active structured light, as well as light refractive matching principles, is developed to detect defects the size, shape and position of defects in ICs. The experimental results show that the algorithm is effective and suitable for in-situ defect detection of IC semiconductor packaging. The quality of defect detection, such as measurement repeatability and accuracy, is addressed. Confirmed by the experimental results, the depth measurement resolution can reach up to 0.3 µm, and the depth measurement uncertainty with one standard deviation was verified to be less than 1.0% of the full-scale depth-measuring range.

  10. Ion trap in a semiconductor chip

    Science.gov (United States)

    Stick, D.; Hensinger, W. K.; Olmschenk, S.; Madsen, M. J.; Schwab, K.; Monroe, C.

    2006-01-01

    The electromagnetic manipulation of isolated atoms has led to many advances in physics, from laser cooling and Bose-Einstein condensation of cold gases to the precise quantum control of individual atomic ions. Work on miniaturizing electromagnetic traps to the micrometre scale promises even higher levels of control and reliability. Compared with `chip traps' for confining neutral atoms, ion traps with similar dimensions and power dissipation offer much higher confinement forces and allow unparalleled control at the single-atom level. Moreover, ion microtraps are of great interest in the development of miniature mass-spectrometer arrays, compact atomic clocks and, most notably, large-scale quantum information processors. Here we report the operation of a micrometre-scale ion trap, fabricated on a monolithic chip using semiconductor micro-electromechanical systems (MEMS) technology. We confine, laser cool and measure heating of a single 111Cd+ ion in an integrated radiofrequency trap etched from a doped gallium-arsenide heterostructure.

  11. Ion Trap in a Semiconductor Chip

    CERN Document Server

    Stick, D; Olmschenk, S; Madsen, M J; Schwab, K; Monroe, C

    2006-01-01

    The electromagnetic manipulation of isolated atoms has led to many advances in physics, from laser cooling and Bose-Einstein condensation of cold gases to the precise quantum control of individual atomic ion. Work on miniaturizing electromagnetic traps to the micrometer scale promises even higher levels of control and reliability. Compared with 'chip traps' for confining neutral atoms, ion traps with similar dimensions and power dissipation offer much higher confinement forces and allow unparalleled control at the single-atom level. Moreover, ion microtraps are of great interest in the development of miniature mass spectrometer arrays, compact atomic clocks, and most notably, large scale quantum information processors. Here we report the operation of a micrometer-scale ion trap, fabricated on a monolithic chip using semiconductor micro-electromechanical systems (MEMS) technology. We confine, laser cool, and measure heating of a single 111Cd+ ion in an integrated radiofrequency trap etched from a doped gallium...

  12. Polydimethylsiloxane-based conducting composites and their applications in microfluidic chip fabrication

    OpenAIRE

    Gong, Xiuqing; Wen, Weijia

    2009-01-01

    This paper reviews the design and fabrication of polydimethylsiloxane (PDMS)-based conducting composites and their applications in microfluidic chip fabrication. Owing to their good electrical conductivity and rubberlike elastic characteristics, these composites can be used variously in soft-touch electronic packaging, planar and three-dimensional electronic circuits, and in-chip electrodes. Several microfluidic components fabricated with PDMS-based composites have been introduced, including ...

  13. NASA Electronic Parts and Packaging (NEPP) Program - Update

    Science.gov (United States)

    LaBel, Kenneth A.; Sampson, Michael J.

    2010-01-01

    This slide presentation reviews the goals and mission of the NASA Electronic Parts and Packaging (NEPP) Program. The NEPP mission is to provide guidance to NASA for the selection and application of microelectronics technologies, to improve understanding of the risks related to the use of these technologies in the space environment and to ensure that appropriate research is performed to meet NASA mission assurance needs. The program has been supporting NASA for over 20 years. The focus is on the reliability aspects of electronic devices. In this work the program also supports the electronics industry. There are several areas that the program is involved in: Memories, systems on a chip (SOCs), data conversion devices, power MOSFETS, power converters, scaled CMOS, capacitors, linear devices, fiber optics, and other electronics such as sensors, cryogenic and SiGe that are used in space systems. Each of these area are reviewed with the work that is being done in reliability and effects of radiation on these technologies.

  14. Photonic Wire Bonds for Terabit/s Chip-to-Chip Interconnects

    CERN Document Server

    Lindenmann, Nicole; Hillerkuss, David; Schmogrow, Rene; Jordan, Meinert; Leuthold, Juerg; Freude, Wolfgang; Koos, Christian

    2011-01-01

    Photonic integration has witnessed tremendous progress over the last years, and chip-scale transceiver systems with Terabit/s data rates have come into reach. However, as on-chip integration density increases, efficient off-chip interfaces are becoming more and more crucial. A technological breakthrough is considered indispensable to cope with the challenges arising from large-scale photonic integration, and this particularly applies to short-distance optical interconnects. In this letter we introduce the concept of photonic wire bonding, where transparent waveguide wire bonds are used to bridge the gap between nanophotonic circuits located on different chips. We demonstrate for the first time the fabrication of three-dimensional freeform photonic wire bonds (PWB), and we confirm their viability in a multi-Terabit/s data transmission experiment. First-generation prototypes allow for efficient broadband coupling with overall losses of only 1.6 dB. Photonic wire bonding will enable flexible optical multi-chip a...

  15. Single-chip microprocessor that communicates directly using light.

    Science.gov (United States)

    Sun, Chen; Wade, Mark T; Lee, Yunsup; Orcutt, Jason S; Alloatti, Luca; Georgas, Michael S; Waterman, Andrew S; Shainline, Jeffrey M; Avizienis, Rimas R; Lin, Sen; Moss, Benjamin R; Kumar, Rajesh; Pavanello, Fabio; Atabaki, Amir H; Cook, Henry M; Ou, Albert J; Leu, Jonathan C; Chen, Yu-Hsin; Asanović, Krste; Ram, Rajeev J; Popović, Miloš A; Stojanović, Vladimir M

    2015-12-24

    Data transport across short electrical wires is limited by both bandwidth and power density, which creates a performance bottleneck for semiconductor microchips in modern computer systems--from mobile phones to large-scale data centres. These limitations can be overcome by using optical communications based on chip-scale electronic-photonic systems enabled by silicon-based nanophotonic devices. However, combining electronics and photonics on the same chip has proved challenging, owing to microchip manufacturing conflicts between electronics and photonics. Consequently, current electronic-photonic chips are limited to niche manufacturing processes and include only a few optical devices alongside simple circuits. Here we report an electronic-photonic system on a single chip integrating over 70 million transistors and 850 photonic components that work together to provide logic, memory, and interconnect functions. This system is a realization of a microprocessor that uses on-chip photonic devices to directly communicate with other chips using light. To integrate electronics and photonics at the scale of a microprocessor chip, we adopt a 'zero-change' approach to the integration of photonics. Instead of developing a custom process to enable the fabrication of photonics, which would complicate or eliminate the possibility of integration with state-of-the-art transistors at large scale and at high yield, we design optical devices using a standard microelectronics foundry process that is used for modern microprocessors. This demonstration could represent the beginning of an era of chip-scale electronic-photonic systems with the potential to transform computing system architectures, enabling more powerful computers, from network infrastructure to data centres and supercomputers. PMID:26701054

  16. Single-chip microprocessor that communicates directly using light

    Science.gov (United States)

    Sun, Chen; Wade, Mark T.; Lee, Yunsup; Orcutt, Jason S.; Alloatti, Luca; Georgas, Michael S.; Waterman, Andrew S.; Shainline, Jeffrey M.; Avizienis, Rimas R.; Lin, Sen; Moss, Benjamin R.; Kumar, Rajesh; Pavanello, Fabio; Atabaki, Amir H.; Cook, Henry M.; Ou, Albert J.; Leu, Jonathan C.; Chen, Yu-Hsin; Asanović, Krste; Ram, Rajeev J.; Popović, Miloš A.; Stojanović, Vladimir M.

    2015-12-01

    Data transport across short electrical wires is limited by both bandwidth and power density, which creates a performance bottleneck for semiconductor microchips in modern computer systems—from mobile phones to large-scale data centres. These limitations can be overcome by using optical communications based on chip-scale electronic-photonic systems enabled by silicon-based nanophotonic devices8. However, combining electronics and photonics on the same chip has proved challenging, owing to microchip manufacturing conflicts between electronics and photonics. Consequently, current electronic-photonic chips are limited to niche manufacturing processes and include only a few optical devices alongside simple circuits. Here we report an electronic-photonic system on a single chip integrating over 70 million transistors and 850 photonic components that work together to provide logic, memory, and interconnect functions. This system is a realization of a microprocessor that uses on-chip photonic devices to directly communicate with other chips using light. To integrate electronics and photonics at the scale of a microprocessor chip, we adopt a ‘zero-change’ approach to the integration of photonics. Instead of developing a custom process to enable the fabrication of photonics, which would complicate or eliminate the possibility of integration with state-of-the-art transistors at large scale and at high yield, we design optical devices using a standard microelectronics foundry process that is used for modern microprocessors. This demonstration could represent the beginning of an era of chip-scale electronic-photonic systems with the potential to transform computing system architectures, enabling more powerful computers, from network infrastructure to data centres and supercomputers.

  17. Packaging for Sustainability

    CERN Document Server

    Lewis, Helen; Fitzpatrick, Leanne

    2012-01-01

    The packaging industry is under pressure from regulators, customers and other stakeholders to improve packaging’s sustainability by reducing its environmental and societal impacts. This is a considerable challenge because of the complex interactions between products and their packaging, and the many roles that packaging plays in the supply chain. Packaging for Sustainability is a concise and readable handbook for practitioners who are trying to implement sustainability strategies for packaging. Industry case studies are used throughout the book to illustrate possible applications and scenarios. Packaging for Sustainability draws on the expertise of researchers and industry practitioners to provide information on business benefits, environmental issues and priorities, environmental evaluation tools, design for environment, marketing strategies, and challenges for the future.

  18. Smart packaging for photonics

    Energy Technology Data Exchange (ETDEWEB)

    Smith, J.H.; Carson, R.F.; Sullivan, C.T.; McClellan, G.; Palmer, D.W. [ed.

    1997-09-01

    Unlike silicon microelectronics, photonics packaging has proven to be low yield and expensive. One approach to make photonics packaging practical for low cost applications is the use of {open_quotes}smart{close_quotes} packages. {open_quotes}Smart{close_quotes} in this context means the ability of the package to actuate a mechanical change based on either a measurement taken by the package itself or by an input signal based on an external measurement. One avenue of smart photonics packaging, the use of polysilicon micromechanical devices integrated with photonic waveguides, was investigated in this research (LDRD 3505.340). The integration of optical components with polysilicon surface micromechanical actuation mechanisms shows significant promise for signal switching, fiber alignment, and optical sensing applications. The optical and stress properties of the oxides and nitrides considered for optical waveguides and how they are integrated with micromechanical devices were investigated.

  19. Realtime 3D stress measurement in curing epoxy packaging

    DEFF Research Database (Denmark)

    Richter, Jacob; Hyldgård, A.; Birkelund, Karen;

    2007-01-01

    This paper presents a novel method to characterize stress in microsystem packaging. A circular p-type piezoresistor is implemented on a (001) silicon chip. We use the circular stress sensor to determine the packaging induced stress in a polystyrene tube filled with epoxy. The epoxy curing process...... is monitored by stress measurements. From the stress measurements we conclude that the epoxy cures in 8 hours at room temperature. We find the difference in in-plane normal stresses to be sigmaxx-sigmayy=6.7 MPa and (sigmaxx+sigmayy-0.4sigmazz)=232 MPa....

  20. LED packaging for lighting applications design, manufacturing, and testing

    CERN Document Server

    Liu, Sheng

    2011-01-01

    Since the first light-emitting diode (LED) was invented by Holonyak and Bevacqua in 1962, LEDs have made remarkable progress in the past few decades with the rapid development of epitaxy growth, chip design and manufacture, packaging structure, processes, and packaging materials. LEDs have superior characteristics such as high efficiency, small size, long life, low power consumption, and high reliability. The market for white LED is growing rapidly in various applications. It has been widely accepted that white LEDs will be the fourth illumination source to substitute the incandescent, fluores

  1. Packaging for meat products

    OpenAIRE

    Vojtíšková, Zuzana

    2014-01-01

    Packaging for meat products Summary Packaging is usually integral to production process in meat industry. The packing has mainly influence on shelf life and quality of meat and meat products. It protects the product from adverse effects such as oxidation, especially fats. In addition it affects transport, storage and serves as a means of communication with customers (logo, marketing benefits, legislation). Significant is also the impact of packaging to keep attractive look of the prod...

  2. "Chips with Everything": A Laboratory Exercise for Comparing Subjective and Objective Measurements of Potato Chips

    Science.gov (United States)

    Davies, Cathy

    2005-01-01

    The following laboratory exercise was designed to aid student understanding of the differences between subjective and objective measurements. Students assess the color and texture of different varieties of potato chip (crisps) by means of an intensity rating scale and a rank test and objectively with a colorimeter and texture analyzer. For data…

  3. Analysis of the fly ash from the processing of wood chips in a pilot-scale downdraft gasifier: Comparison of inorganic constituents determined by PIXE and ICP-AES

    International Nuclear Information System (INIS)

    Gasification of biomass ultimately generates at least one solid byproduct in which the inorganic constituents of the biomass are concentrated. Given the potential for utilization, or issues with disposal, facile methods are needed for determining the compositions of the fly ashes from recently-available gasifier-based bioenergy systems. Proton induced x-ray emission spectroscopy (PIXE) and inductively coupled plasma atomic emission spectroscopy (ICP-AES) were used to characterize the fly ash recovered from a pilot-scale (25 kW) modular bioenergy system operated with wood chips as the feedstock. The composition of the fly ash from the downdraft gasifier showed some similarities to compositions reported for boiler wood ashes, apart from one half of the material being unburned carbon. Although ICP-AES showed greater sensitivity for the analysis of the fly ash, especially for small amounts of heavy metal contaminants, PIXE proved to be a powerful analytical tool for screening of elements from sodium to uranium. Such broad spectrum screenings could prevent the inadvertent land application of unsuspected pollutant elements. Fly ashes from biomass gasification appear to be suitable for use as ash-based fertilizers for forest lands; however, combustion to remove unburned carbon may be advisable. -- Highlights: ► Fly ash composition data for commercial modular bioenergy systems are now reported. ► PIXE analysis better suited for analysis of fly ashes rich in silicates. Fly ashes generated by biomass gasification may be suitable for land application. ► Combustion of biomass-derived fly ashes is recommended before use as soil amendments

  4. User friendly packaging

    DEFF Research Database (Denmark)

    Geert Jensen, Birgitte

    2010-01-01

    “User-friendly Packaging” aims to create a platform for developing more user-friendly packaging. One intended outcome of the project is a guideline that industry can use in development efforts. The project also points the way for more extended collaboration between companies and design researchers. How...... can design research help industry in packaging innovation?......Most consumers have experienced occasional problems with opening packaging. Tomato sauce from the tinned mackerel splattered all over the kitchen counter, the unrelenting pickle jar lid, and the package of sliced ham that cannot be opened without a knife or a pair of scissors. The research project...

  5. HIRENASD analysis Information Package

    Data.gov (United States)

    National Aeronautics and Space Administration — Updated November 2, 2011 Contains summary information and analysis condition details for the Aeroelastic Prediction Workshop Information plotted in this package is...

  6. Plasma physics plotting package

    International Nuclear Information System (INIS)

    We describe a package of plotting routines that do up to six two- or three-dimensional plots on a frame with minimal loss of resolution. The package now runs on a PDP-10 with PLOT-10 TCS primitives and on a Control Data Corporation-7600 and a Cray-1 with TV80LIB primitives on the National Magnetic Fusion Energy Computer Center network. The package is portable to other graphics systems because only the primitive plot calls are used from the underlying system's graphics package

  7. Packaging Technologies for 500 C SiC Electronics and Sensors: Challenges in Material Science and Technology

    Science.gov (United States)

    Chen, Liang-Yu; Neudeck, Philip G.; Behelm, Glenn M.; Spry, David J.; Meredith, Roger D.; Hunter, Gary W.

    2015-01-01

    This paper presents ceramic substrates and thick-film metallization based packaging technologies in development for 500C silicon carbide (SiC) electronics and sensors. Prototype high temperature ceramic chip-level packages and printed circuit boards (PCBs) based on ceramic substrates of aluminum oxide (Al2O3) and aluminum nitride (AlN) have been designed and fabricated. These ceramic substrate-based chip-level packages with gold (Au) thick-film metallization have been electrically characterized at temperatures up to 550C. The 96 alumina packaging system composed of chip-level packages and PCBs has been successfully tested with high temperature SiC discrete transistor devices at 500C for over 10,000 hours. In addition to tests in a laboratory environment, a SiC junction field-effect-transistor (JFET) with a packaging system composed of a 96 alumina chip-level package and an alumina printed circuit board was tested on low earth orbit for eighteen months via a NASA International Space Station experiment. In addition to packaging systems for electronics, a spark-plug type sensor package based on this high temperature interconnection system for high temperature SiC capacitive pressure sensors was also developed and tested. In order to further significantly improve the performance of packaging system for higher packaging density, higher operation frequency, power rating, and even higher temperatures, some fundamental material challenges must be addressed. This presentation will discuss previous development and some of the challenges in material science (technology) to improve high temperature dielectrics for packaging applications.

  8. Inherent polarization entanglement generated from a monolithic semiconductor chip

    DEFF Research Database (Denmark)

    Horn, Rolf T.; Kolenderski, Piotr; Kang, Dongpeng;

    2013-01-01

    Creating miniature chip scale implementations of optical quantum information protocols is a dream for many in the quantum optics community. This is largely because of the promise of stability and scalability. Here we present a monolithically integratable chip architecture upon which is built...... filtering or post-selection. After splitting the twin-photons immediately after they emerge from the chip, we perform a variety of correlation tests on the photon pairs and show non-classical behaviour in their polarization. Combined with the BRW's versatile architecture our results signify the BRW design...

  9. Packetizing OCP Transactions in the MANGO Network-on-Chip

    DEFF Research Database (Denmark)

    Bjerregaard, Tobias; Sparsø, Jens

    2006-01-01

    The scaling of CMOS technology causes a widening gap between the performance of on-chip communication and computation. This calls for a communication-centric design flow. The MANGO network-on-chip architecture enables globally asynchronous locally synchronous (GALS) system-on-chip design, while...... transactions are packetized and transmitted across the shared network, and illustrate how this affects the end-to-end performance. A high predictability of the latency of communication on shared links is shown in a MANGO-based demonstrator system...

  10. Price of forest chips decreasing

    International Nuclear Information System (INIS)

    Use of forest chips was studied in 1999 in the national Puuenergia (Wood Energy) research program. Wood combusting heating plants were questioned about are the main reasons restricting the increment of the use of forest chips. Heating plants, which did not use forest chips at all or which used less than 250 m3 (625 bulk- m3) in 1999 were excluded. The main restrictions for additional use of forest chips were: too high price of forest chips; lack of suppliers and/or uncertainty of deliveries; technical problems of reception and processing of forest chips; insufficiency of boiler output especially in winter; and unsatisfactory quality of chips. The price of forest chips becomes relatively high because wood biomass used for production of forest chips has to be collected from wide area. Heavy equipment has to be used even though small fragments of wood are processed, which increases the price of chips. It is essential for forest chips that the costs can be pressed down because competition with fossil fuels, peat and industrial wood residues is hard. Low market price leads to the situation in which forest owner gets no price of the raw material, the entrepreneurs operate at the limit of profitability and renovation of machinery is difficult, and forest chips suppliers have to sell the chips at prime costs. Price of forest chips has decreased significantly during the past decade. Nominal price of forest chips is now lower than two decades ago. The real price of chips has decreased even more than the nominal price, 35% during the past decade and 20% during the last five years. Chips, made of small diameter wood, are expensive because the price includes the felling costs and harvesting is carried out at thinning lots. Price is especially high if chips are made of delimbed small diameter wood due to increased the work and reduced amount of chips. The price of logging residue chips is most profitable because cutting does not cause additional costs. Recovery of chips is

  11. Packaging Technologies for 500C SiC Electronics and Sensors

    Science.gov (United States)

    Chen, Liang-Yu

    2013-01-01

    Various SiC electronics and sensors are currently under development for applications in 500C high temperature environments such as hot sections of aerospace engines and the surface of Venus. In order to conduct long-term test and eventually commercialize these SiC devices, compatible packaging technologies for the SiC electronics and sensors are required. This presentation reviews packaging technologies developed for 500C SiC electronics and sensors to address both component and subsystem level packaging needs for high temperature environments. The packaging system for high temperature SiC electronics includes ceramic chip-level packages, ceramic printed circuit boards (PCBs), and edge-connectors. High temperature durable die-attach and precious metal wire-bonding are used in the chip-level packaging process. A high temperature sensor package is specifically designed to address high temperature micro-fabricated capacitive pressure sensors for high differential pressure environments. This presentation describes development of these electronics and sensor packaging technologies, including some testing results of SiC electronics and capacitive pressure sensors using these packaging technologies.

  12. 电子封装、QFP和MCM热变形的实验及数值分析%Experimental and Numerical Analysis of Thermal Deformation of Electronic Packages,QFP and MCM

    Institute of Scientific and Technical Information of China (English)

    2006-01-01

    Moiré inteferometry and FEA (finite element analysis) were used to evaluate the thermal deformation of two electronic packages, QFP (quad flat package) and MCM (multi chip module).Thermal loading was applied by cooling the packages from 100℃ to room temperature (25℃). Moiré fringes were obtained on the cross sections of the packages to clarify the effect of the CTE (coefficient of thermal expansion) mismatch of the micro components, such as silicon, metal and resin. In QFP, the effects of packaging resin and PCB (printed circuit board) on the thermal deformation were investigated. The effect of location of three silicon chips in MCM was also examined.

  13. An Evaluation of an Integrated On-Chip/Off-Chip Network for High-Performance Reconfigurable Computing

    OpenAIRE

    Kritikos, William V.; Shanyuan Gao; Andrew G. Schmidt; Ron Sass

    2012-01-01

    As the number of cores per discrete integrated circuit (IC) device grows, the importance of the network on chip (NoC) increases. However, the body of research in this area has focused on discrete IC devices alone which may or may not serve the high-performance computing community which needs to assemble many of these devices into very large scale, parallel computing machines. This paper describes an integrated on-chip/off-chip network that has been implemented on an all-FPGA computing cluster...

  14. 3-D readout-electronics packaging for high-bandwidth massively paralleled imager

    Science.gov (United States)

    Kwiatkowski, Kris; Lyke, James

    2007-12-18

    Dense, massively parallel signal processing electronics are co-packaged behind associated sensor pixels. Microchips containing a linear or bilinear arrangement of photo-sensors, together with associated complex electronics, are integrated into a simple 3-D structure (a "mirror cube"). An array of photo-sensitive cells are disposed on a stacked CMOS chip's surface at a 45.degree. angle from light reflecting mirror surfaces formed on a neighboring CMOS chip surface. Image processing electronics are held within the stacked CMOS chip layers. Electrical connections couple each of said stacked CMOS chip layers and a distribution grid, the connections for distributing power and signals to components associated with each stacked CSMO chip layer.

  15. DVFS using clock scheduling for Multicore Systems-on-Chip and Networks-on-Chip

    OpenAIRE

    Yadav, Manoj Kumar

    2014-01-01

    A modern System-on-Chip (SoC) contains processor cores, application-specific process- ing elements, memory, peripherals, all connected with a high-bandwidth and low-latency Network-on-Chip (NoC). The downside of such very high level of integration and con- nectivity is the high power consumption. In CMOS technology this is made of a dynamic and a static component. To reduce the dynamic component, Dynamic voltage and Fre- quency Scaling (DVFS) has been adopted. Although DVFS is very effective ...

  16. Design aspects of plutonium air-transportable packages

    International Nuclear Information System (INIS)

    Recent worldwide interest in transporting plutonium powders by air has created a need for expanding the packaging technology base as well as improving their understanding of how plutonium air transport (PAT) packagings perform during severe accident tests. Historically it has not been possible to establish design rules for individual package components because of the complex way parts interacted in forming a successful whole unit. Also, computer analyses were only considered valid for very limited portions of the design effort because of large deformations, localized tearing occurring in the package during accident testing, and extensive use of orthotropic materials. Consequently, iterative design and experimentation has historically been used to develop plutonium air-transportable packages. Full-scale prototypes have been tested since scaling of packages utilizing wood as an energy absorber and thermal insulator has not proven to be very successful. This is because the wood grain and dynamic performance of the wood during crush do not always scale. The high cost of full-scale testing of large packages has certainly hindered obtaining additional data and development new designs. The testing criteria for PAT packages, as described in the US Nuclear Regulatory Commission's Qualification Criteria to Certify a Package for Air Transport of Plutonium, NUREG-0360, 1978, are summarized. Computer modeling techniques have greatly improved over the last ten years, and there are some areas of opportunity for future applications to plutonium air-transportable package design problems. Having developed a better understanding of the performance of current packages, they have the opportunity to make major improvements in new packaging concepts. Each of these areas is explored in further depth to establish their impact on design practices for air-transportable packages

  17. WASTE PACKAGE TRANSPORTER DESIGN

    International Nuclear Information System (INIS)

    The purpose of this Design Analysis is to develop preliminary design of the waste package transporter used for waste package (WP) transport and related functions in the subsurface repository. This analysis refines the conceptual design that was started in Phase I of the Viability Assessment. This analysis supports the development of a reliable emplacement concept and a retrieval concept for license application design. The scope of this analysis includes the following activities: (1) Assess features of the transporter design and evaluate alternative design solutions for mechanical components. (2) Develop mechanical equipment details for the transporter. (3) Prepare a preliminary structural evaluation for the transporter. (4) Identify and recommend the equipment design for waste package transport and related functions. (5) Investigate transport equipment interface tolerances. This analysis supports the development of the waste package transporter for the transport, emplacement, and retrieval of packaged radioactive waste forms in the subsurface repository. Once the waste containers are closed and accepted, the packaged radioactive waste forms are termed waste packages (WP). This terminology was finalized as this analysis neared completion; therefore, the term disposal container is used in several references (i.e., the System Description Document (SDD)) (Ref. 5.6). In this analysis and the applicable reference documents, the term ''disposal container'' is synonymous with ''waste package''

  18. WASTE PACKAGE TRANSPORTER DESIGN

    Energy Technology Data Exchange (ETDEWEB)

    D.C. Weddle; R. Novotny; J. Cron

    1998-09-23

    The purpose of this Design Analysis is to develop preliminary design of the waste package transporter used for waste package (WP) transport and related functions in the subsurface repository. This analysis refines the conceptual design that was started in Phase I of the Viability Assessment. This analysis supports the development of a reliable emplacement concept and a retrieval concept for license application design. The scope of this analysis includes the following activities: (1) Assess features of the transporter design and evaluate alternative design solutions for mechanical components. (2) Develop mechanical equipment details for the transporter. (3) Prepare a preliminary structural evaluation for the transporter. (4) Identify and recommend the equipment design for waste package transport and related functions. (5) Investigate transport equipment interface tolerances. This analysis supports the development of the waste package transporter for the transport, emplacement, and retrieval of packaged radioactive waste forms in the subsurface repository. Once the waste containers are closed and accepted, the packaged radioactive waste forms are termed waste packages (WP). This terminology was finalized as this analysis neared completion; therefore, the term disposal container is used in several references (i.e., the System Description Document (SDD)) (Ref. 5.6). In this analysis and the applicable reference documents, the term ''disposal container'' is synonymous with ''waste package''.

  19. The DYNAMIC program package

    International Nuclear Information System (INIS)

    The most important constituents and capacities of the practice-oriented program package DYNAMIC are explained. The versatility of the package in dealing with problems of structural dynamics is shown by examples (seismic qualification of SF6 switchgear equipment, turbine building of a BWR). The examples explain applications in the fields of construction engineering and electromechanics. (orig./HP)

  20. Networks on chip

    CERN Document Server

    Jantsch, Axel

    2007-01-01

    From the reviews:""This edited book is concerned with the fundamentals of Networks-on-Chip design. … Overall, the various authors have done an excellent job in covering their material, and the book is well edited. The authors' objectives were that of providing an in-depth, up-to-date, unified and comprehensive treatment ... . These are difficult objectives … and they have done a creditable job of attaining them. In summary, this book is a welcome addition to the literature on networks on chip design … ."" (Mile Stojcev, Microelectronics Reliability, Vol. 44, 2004)

  1. Trapping molecules on chips

    CERN Document Server

    Santambrogio, Gabriele

    2015-01-01

    In the last years, it was demonstrated that neutral molecules can be loaded on a microchip directly from a supersonic beam. The molecules are confined in microscopic traps that can be moved smoothly over the surface of the chip. Once the molecules are trapped, they can be decelerated to a standstill, for instance, or pumped into selected quantum states by laser light or microwaves. Molecules are detected on the chip by time-resolved spatial imaging, which allows for the study of the distribution in the phase space of the molecular ensemble.

  2. Issues associated with scaling up production of a lab demonstrated MEMS mass sensor

    International Nuclear Information System (INIS)

    This work reports on the development of a lab demonstrated resonant mass sensor towards mid-size production. The issues associated with scaling-up production of the microfabricated chip are discussed with particular focus on yield and device reproducibility, as well as the constraints imposed on the design and manufacturing of the device when packaging and integration must be taken into account. Issues of modal alignment and ambient operational pressure are discussed. Fabricated devices show a 4.81 Hz pg−1 mass sensitivity with a temperature sensitivity of typically 10 Hz °C−1. (paper)

  3. Determination of packaging induced 3D stress utilizing a piezocoefficient mapping device

    DEFF Research Database (Denmark)

    Richter, Jacob; Hyldgård, A.; Birkelund, Karen;

    2007-01-01

    This paper presents a novel method to determine 3D stress in microsystem packaging. The stress components sigmaxx, sigmayy, sigmazz, and sigmaxy are found in an epoxy package using a piezocoefficient mapping device as stress sensor. We spin the current 360deg in a circular n-type (001) Si...... same concept as in [1] used for chip packaging for fisheries research. We investigate the EpoTek 305 epoxy and find stress values of sigmaxx ap -23 MPa, sigmayy ap -1 MPa, sigmaxy = 0.3 MPa, and sigmazz = 40 MPa. The presented method can be used for 3D stress measurements of various packaging concepts....... piezoresistor by contacts located near the perimeter of the resistor and do high impedance voltage measurements on contacts located near the centre of the resistor. By measuring the potential drops in these contacts we can determine the stress in the chip. The epoxy is potted in a polystyrene tube using the...

  4. Waste package performance analysis

    International Nuclear Information System (INIS)

    A performance assessment model for multiple barrier packages containing unreprocessed spent fuel has been applied to several package designs. The resulting preliminary assessments were intended for use in making decisions about package development programs. A computer model called BARIER estimates the package life and subsequent rate of release of selected nuclides. The model accounts for temperature, pressure (and resulting stresses), bulk and localized corrosion, and nuclide retardation by the backfill after water intrusion into the waste form. The assessment model assumes a post-closure, flooded, geologic repository. Calculations indicated that, within the bounds of model assumptions, packages could last for several hundred years. Intact backfills of appropriate design may be capable of nuclide release delay times on the order of 107 yr for uranium, plutonium, and americium. 8 references, 6 figures, 9 tables

  5. The use of oxygen indicators - elements of intelligent packaging for monitoring of food quality

    OpenAIRE

    Renata Dobrucka

    2014-01-01

    Background: Producers and researchers are looking at not only the methods of protection against ingress of oxygen into the package, but also want to provide consumers with guarantees of quality food they buy. Therefore, large-scale studies are conducted and implementation of intelligent packaging. The operation of these packages is the use of interactive, the most colorful indicators to assess the quality of the packaged product. Methods: This article describes intelligent packaging tech...

  6. A Quality-of-Service Mechanism for Interconnection Networks in System-on-Chips

    CERN Document Server

    Weber, Wolf-Dietrich; Swarbrick, Ian; Wingard, Drew

    2011-01-01

    As Moore's Law continues to fuel the ability to build ever increasingly complex system-on-chips (SoCs), achieving performance goals is rising as a critical challenge to completing designs. In particular, the system interconnect must efficiently service a diverse set of data flows with widely ranging quality-of-service (QoS) requirements. However, the known solutions for off-chip interconnects such as large-scale networks are not necessarily applicable to the on-chip environment. Latency and memory constraints for on-chip interconnects are quite different from larger-scale interconnects. This paper introduces a novel on-chip interconnect arbitration scheme. We show how this scheme can be distributed across a chip for high-speed implementation. We compare the performance of the arbitration scheme with other known interconnect arbitration schemes. Existing schemes typically focus heavily on either low latency of service for some initiators, or alternatively on guaranteed bandwidth delivery for other initiators. ...

  7. Sensing systems using chip-based spectrometers

    Science.gov (United States)

    Nitkowski, Arthur; Preston, Kyle J.; Sherwood-Droz, Nicolás.; Behr, Bradford B.; Bismilla, Yusuf; Cenko, Andrew T.; DesRoches, Brandon; Meade, Jeffrey T.; Munro, Elizabeth A.; Slaa, Jared; Schmidt, Bradley S.; Hajian, Arsen R.

    2014-06-01

    Tornado Spectral Systems has developed a new chip-based spectrometer called OCTANE, the Optical Coherence Tomography Advanced Nanophotonic Engine, built using a planar lightwave circuit with integrated waveguides fabricated on a silicon wafer. While designed for spectral domain optical coherence tomography (SD-OCT) systems, the same miniaturized technology can be applied to many other spectroscopic applications. The field of integrated optics enables the design of complex optical systems which are monolithically integrated on silicon chips. The form factors of these systems can be significantly smaller, more robust and less expensive than their equivalent free-space counterparts. Fabrication techniques and material systems developed for microelectronics have previously been adapted for integrated optics in the telecom industry, where millions of chip-based components are used to power the optical backbone of the internet. We have further adapted the photonic technology platform for spectroscopy applications, allowing unheard-of economies of scale for these types of optical devices. Instead of changing lenses and aligning systems, these devices are accurately designed programmatically and are easily customized for specific applications. Spectrometers using integrated optics have large advantages in systems where size, robustness and cost matter: field-deployable devices, UAVs, UUVs, satellites, handheld scanning and more. We will discuss the performance characteristics of our chip-based spectrometers and the type of spectral sensing applications enabled by this technology.

  8. A Study on the Conductivity Variation of Au Coated Conductive Particles in ACF Packaging Process

    OpenAIRE

    Jao-Hwa Kuang; Chao-Ming Hsu; Ah-Der Lin

    2015-01-01

    In the ACF packaging process, a bonding force will be applied to the ACF structure. The finite element analysis is used to simulate the ACF packaging process. Material behavior is assumed to be superelastic for resin, viscoelastic for polymer matrix, and elastic-plastic for metal, such as bump, pad, chip, and Au-film. The axis-symmetric model is employed in FEA simulation with time-varying bonding force and operating temperature. In this study, the parameters, including conductive particle d...

  9. Flock on a chip

    Science.gov (United States)

    Bartolo, Denis; Desreumaux, Nicolas

    2015-11-01

    We will show how to motorize colloidal particles capable of sensing the orientation of their neighbors and how to handle them in microfluidic chips. These populations of colloidal rollers display non-equilibrium transitions toward swarming or swirling motion depending on the system geometry . After characterizing these emergent patterns we will quantitatively describe them by means of an hydrodynamic theory of polar active liquids.

  10. Fish and chips

    OpenAIRE

    Delvenne, Philippe; Deprez, Manuel; Bisig, Bettina; JAMAR, Mauricette; Boniver, Jacques; Bours, Vincent; Herens, Christian

    2010-01-01

    Academic hospital laboratories should offer patients the possibility to have the most accurate diagnosis by the development of new analyses, such as molecular biology tests including FISH (Fluorescent In Situ Hybridization) and chips (microarrays,...). The purpose of this article is to describe the principles and the potential applications of these techniques.

  11. Analysis of trade packages in Chinese stock market

    OpenAIRE

    Fei Ren; Wei-Xing Zhou

    2011-01-01

    This paper conducts an empirically study on the trade package composed of a sequence of consecutive purchases or sales of 23 stocks in Chinese stock market. We investigate the probability distributions of the execution time, the number of trades and the total trading volume of trade packages, and analyze the possible scaling relations between them. Quantitative differences are observed between the institutional and individual investors. The trading profile of trade packages is investigated to...

  12. An empirical survey on factors influencing on packaging dairy products

    OpenAIRE

    Naser Azad; Mina Mohammadi

    2013-01-01

    Packaging plays an essential role on supplying different materials such as dairy products. The first thing people may look into when they purchase dairy products such as milk, cheese, etc. is associated with the packaging characteristics. This paper attempts to find important factors influencing on packaging dairy products. The study uses factor analysis to detect important factors based on a questionnaire consists of 28 questions in Likert scale, which is distributed among 200 regular employ...

  13. Lunar Dust Analysis Package - LDAP

    Science.gov (United States)

    Chalkley, S. A.; Richter, L.; Goepel, M.; Sovago, M.; Pike, W. T.; Yang, S.; Rodenburg, J.; Claus, D.

    2012-09-01

    The Lunar Dust Analysis package (L-DAP) is a suite of payloads which have been designed to operate in synergy with each other at the Lunar Surface. The benefits of combining these payloads in a single package allow very precise measurements of a particular regolith sample. At the same time the integration allows mass savings since common resources are shared and this also means that interfaces with the Lander are simplified significantly leading to benefits of integration and development of the overall mission. Lunar Dust represents a real hazard for lunar exploration due to its invasive, fine microscopic structure and toxic properties. However it is also valuable resource which could be exploited for future exploration if the characteristics and chemical composition is well known. Scientifically, the regolith provides an insight into the moon formation process and there are areas on the Moon which have never been ex-plored before. For example the Lunar South Pole Aitken Basin is the oldest and largest on the moon, providing excavated deep crust which has not been found on the previous lunar landing missions. The SEA-led team has been designing a compact package, known as LDAP, which will provide key data on the lunar dust properties. The intention is for this package to be part of the payload suite deployed on the ESA Lunar Lander Mission in 2018. The LDAP has a centralised power and data electronics, including front end electronics for the detectors as well as sample handling subsystem for the following set of internal instruments : • Optical Microscope - with a 1μm resolution to provide context of the regolith samples • Raman and LIBS spectrographic instrumentation providing quantification of mineral and elemental composition information of the soil at close to grain scale. This includes the capability to detect (and measure abundance of) crystalline and adsorbed volatile phases, from their Raman signature. The LIBS equipment will also allow chemical

  14. Safety Analysis Report - Packages, 9965, 9968, 9972-9975 Packages

    International Nuclear Information System (INIS)

    This Safety Analysis Report for Packaging (SARP) documents the analysis and testing performed on four type B Packages: the 9972, 9973, 9974, and 9975 packages. Because all four packages have similar designs with very similar performance characteristics, all of them are presented in a single SARP. The performance evaluation presented in this SARP documents the compliance of the 9975 package with the regulatory safety requirements. Evaluations of the 9972, 9973, and 9974 packages support that of the 9975. To avoid confusion arising from the inclusion of four packages in a single document, the text segregates the data for each package in such a way that the reader interested in only one package can progress from Chapter 1 through Chapter 9. The directory at the beginning of each chapter identifies each section that should be read for a given package. Sections marked ''all'' are generic to all packages

  15. Hermeticity of electronic packages

    CERN Document Server

    Greenhouse, Hal; Romenesco, Bruce

    2011-01-01

    This is a book about the integrity of sealed packages to resist foreign gases and liquids penetrating the seal or an opening (crack) in the packageùespecially critical to the reliability and longevity of electronics. The author explains how to predict the reliability and the longevity of the packages based on leak rate measurements and the assumptions of impurities. Non-specialists in particular will benefit from the author's long involvement in the technology. Hermeticity is a subject that demands practical experience, and solving one problem does not necessarily give one the background to so

  16. Hermeticity of electronic packages

    CERN Document Server

    Greenhouse, Hal

    2000-01-01

    This is a book about the integrity of sealed packages to resist foreign gases and liquids penetrating the seal or an opening (crack) in the package-especially critical to the reliability and longevity of electronics. The author explains how to predict the reliability and the longevity of the packages based on leak rate measurements and the assumptions of impurities. Non-specialists in particular will benefit from the author's long involvement in the technology. Hermeticity is a subject that demands practical experience, and solving one problem does not necessarily give one the background to so

  17. Smart-pixel-based free-space interconnects: solving the high-speed multichip packaging bottleneck

    Science.gov (United States)

    Haney, Michael W.; Christensen, Marc P.; Milojkovic, Predrag; McFadden, Michael J.

    2001-11-01

    As IC densities grow to 100's of millions of devices per chip and beyond, the inter-chip link bandwidth becomes a critical performance-limiting bottleneck in many applications. Electronic packaging technology has not kept pace with the growth of IC I/O requirements. Recent advances in smart pixel technology, however, offer the potential to use 3-D optical interconnects to overcome the inter-chip I/O bottleneck by linking dense arrays of Vertical Cavity Surface Emitting Lasers (VCSELs) and photodetectors, which are directly integrated onto electronic IC circuits. Many switching and parallel computing applications demand multi-chip interconnection fabrics that achieve high-density global I/O across an array of chips. Such global interconnections require a high degree of space-variance in the interconnection fabric, in addition to high inter-chip throughput capacity. This paper reviews the architectural and optical design issues associated with global interconnections among arrays of chips. The emphasis is on progress made in the design and implementation of the second generation Free-space Accelerator for Switching Terabit Networks (FAST-Net) prototype. The FAST-Net prototype uses a macro-optical lens array and mirror to effect a global (fully connected) fabric across a 4 X 4 array of smart pixel chips. Clusters of VCSELs and photodetectors are imaged onto corresponding clusters on other chips, creating a high- density bi-directional data path between every pair of smart pixel chips on a multi-chip module. The combination of programmable intra-chip electronic routing and the fixed global inter-chip optical interconnection pattern of the FAST- Net architecture has been shown to provide a low latency, minimum complexity fabric, that can effect an arbitrary interconnection pattern across the chip array. Recent experimental results show that the narrow beam characteristics of VCSELs can be exploited in an efficient optical design for the FAST-Net optical interconnection

  18. Hardware support for CSP on a Java chip multiprocessor

    DEFF Research Database (Denmark)

    Gruian, Flavius; Schoeberl, Martin

    2013-01-01

    Due to memory bandwidth limitations, chip multiprocessors (CMPs) adopting the convenient shared memory model for their main memory architecture scale poorly. On-chip core-to-core communication is a solution to this problem, that can lead to further performance increase for a number of multithreaded...... applications. Programmatically, the Communicating Sequential Processes (CSPs) paradigm provides a sound computational model for such an architecture with message based communication. In this paper we explore hardware support for CSP in the context of an embedded Java CMP. The hardware support for CSP are on-chip...... communication channels, implemented by a ring-based network-on-chip (NoC), to reduce the memory bandwidth pressure on the shared memory.The presented solution is scalable and also specific for our limited resources and real-time predictability requirements. CMP architectures of three to eight processors were...

  19. London 2012 packaging guidelines

    OpenAIRE

    2013-01-01

    These guidelines are intended to provide supplemental advice to suppliers and licensees regarding the provisions of the LOCOG Sustainable Sourcing Code that relate to packaging design and materials selection.

  20. Dual Use Packaging Project

    Data.gov (United States)

    National Aeronautics and Space Administration — NASA calculation that over a kg of packaging waste are generated per day for a 6 member crew. This represents over 1.5 metric tons of waste during a Mars mission....

  1. FLEXIBLE FOOD PACKAGING LABORATORY

    Data.gov (United States)

    Federal Laboratory Consortium — This laboratory contains equipment to fabricate and test prototype packages of many types and sizes (e.g., bags, pouches, trays, cartons, etc.). This equipment can...

  2. CH Packaging Program Guidance

    International Nuclear Information System (INIS)

    The purpose of this document is to provide the technical requirements for preparation for use, operation, inspection, and maintenance of a Transuranic Package Transporter Model II (TRUPACT-II), a HalfPACT Shipping Package, and directly related components. This document complies with the minimum requirements as specified in TRUPACT-II Safety Analysis Report for Packaging (SARP), HalfPACT SARP, and Nuclear Regulatory Commission (NRC) Certificates of Compliance (C of C) 9218 and 9279, respectively. In the event there is a conflict between this document and the SARP or C of C, the SARP and/or C of C shall govern. C of Cs state: ''each package must be prepared for shipment and operated in accordance with the procedures described in Chapter 7.0, Operating Procedures, of the application.'' They further state: ''each package must be tested and maintained in accordance with the procedures described in Chapter 8.0, Acceptance Tests and Maintenance Program of the Application.'' Chapter 9.0 of the SAR P charges the WIPP Management and Operation (M and O) contractor with assuring packaging is used in accordance with the requirements of the C of C. Because the packaging is NRC-approved, users need to be familiar with 10 CFR 71.11. Any time a user suspects or has indications that the conditions of approval in the C of C were not met, the Carlsbad Field Office (CBFO) shall be notified immediately. CBFO will evaluate the issue and notify the NRC if required. This document details the instructions to be followed to operate, maintain, and test the TRUPACT-II and HalfPACT packaging. The intent of these instructions is to standardize these operations. All users will follow these instructions or equivalent instructions that assure operations are safe and meet the requirements of the SARPs

  3. CH Packaging Program Guidance

    International Nuclear Information System (INIS)

    The purpose of this document is to provide the technical requirements for preparation for use, operation, inspection, and maintenance of a Transuranic Package Transporter Model II (TRUPACT-II), a HalfPACT shipping package, and directly related components. This document complies with the minimum requirements as specified in the TRUPACT-II Safety Analysis Report for Packaging (SARP), HalfPACT SARP, and Nuclear Regulatory Commission (NRC) Certificates of Compliance (C of C) 9218 and 9279, respectively. In the event of a conflict between this document and the SARP or C of C, the C of C shall govern. The C of Cs state: ''each package must be prepared for shipment and operated in accordance with the procedures described in Chapter 7.0, Operating Procedures, of the application.'' They further state: ''each package must be tested and maintained in accordance with the procedures described in Chapter 8.0, Acceptance Tests and Maintenance Program of the Application.'' Chapter 9.0 of the SARP charges the WIPP management and operating (M and O) contractor with assuring packaging is used in accordance with the requirements of the C of C. Because the packaging is NRC-approved, users need to be familiar with 10 CFR 71.11. Any time a user suspects or has indications that the conditions of approval in the C of C were not met, the Carlsbad Field Office (CBFO) shall be notified immediately. CBFO will evaluate the issue and notify the NRC if required. This document provides the instructions to be followed to operate, maintain, and test the TRUPACT-II and HalfPACT packaging. The intent of these instructions is to standardize operations. All users will follow these instructions or equivalent instructions that assure operations are safe and meet the requirements of the SARPs

  4. The ENSDF Java Package

    International Nuclear Information System (INIS)

    A package of computer codes has been developed to process and display nuclear structure and decay data stored in the ENSDF (Evaluated Nuclear Structure Data File) library. The codes were written in an object-oriented fashion using the java language. This allows for an easy implementation across multiple platforms as well as deployment on web pages. The structure of the different java classes that make up the package is discussed as well as several different implementations

  5. Packaging sustainability assessment

    OpenAIRE

    Rubio Peregrina, Silvia

    2015-01-01

    Packaging is an essential part of the majority of products in the actual market. Therefore, packaging design must draw attention to improve its sustainable character in order to satisfy consumers, enhance its environmental performance and keep economic costs to a minimum. Measuring packaging’s sustainability would provide consumers information so as to raise awareness and, moreover, a tool that would help companies to find product weaknesses to be improved. For that purpose, this projec...

  6. Lush Cosmetics packaging

    OpenAIRE

    Hudson, Frazer

    2014-01-01

    Frazer Hudson – Lush Cosmetics Packaging Commissioned by Suzie Hackney for Lush Cosmetics via illustration Agency - Debut Art - February 2014 I was approached in February 2014 via my London based Illustration agency Debut Art to create packaging illustration designs for the high street retailer and International cosmetics brand ‘Lush’. The illustrations would be used on an octagonal gift box set and be positioned amongst other bespoke gift box set designs within Lush Cosme...

  7. Heat management in integrated circuits on-chip and system-level monitoring and cooling

    CERN Document Server

    Ogrenci-Memik, Seda

    2016-01-01

    This essential overview covers the subject of thermal monitoring and management in integrated circuits. Specifically, it focuses on devices and materials that are intimately integrated on-chip (as opposed to in-package or on-board) for the purposes of thermal monitoring and thermal management.

  8. Wafer-level vacuum/hermetic packaging technologies for MEMS

    Science.gov (United States)

    Lee, Sang-Hyun; Mitchell, Jay; Welch, Warren; Lee, Sangwoo; Najafi, Khalil

    2010-02-01

    An overview of wafer-level packaging technologies developed at the University of Michigan is presented. Two sets of packaging technologies are discussed: (i) a low temperature wafer-level packaging processes for vacuum/hermeticity sealing, and (ii) an environmentally resistant packaging (ERP) technology for thermal and mechanical control as well as vacuum packaging. The low temperature wafer-level encapsulation processes are implemented using solder bond rings which are first patterned on a cap wafer and then mated with a device wafer in order to encircle and encapsulate the device at temperatures ranging from 200 to 390 °C. Vacuum levels below 10 mTorr were achieved with yields in an optimized process of better than 90%. Pressures were monitored for more than 4 years yielding important information on reliability and process control. The ERP adopts an environment isolation platform in the packaging substrate. The isolation platform is designed to provide low power oven-control, vibration isolation and shock protection. It involves batch flip-chip assembly of a MEMS device onto the isolation platform wafer. The MEMS device and isolation structure are encapsulated at the wafer-level by another substrate with vertical feedthroughs for vacuum/hermetic sealing and electrical signal connections. This technology was developed for high performance gyroscopes, but can be applied to any type of MEMS device.

  9. Backside preparation and failure analysis for packaged microelectromechanical systems (MEMS)

    Science.gov (United States)

    Walraven, Jeremy A.; Cole, Edward I., Jr.; Barr, David L.; Anderson, Richard E.; Kilgo, Alice; Maciel, John J.; Morrison, Richard; Karabudak, Nafiz N.

    2005-01-01

    Failure analysis tools and techniques that identify root cause failure mechanisms are key components to improving MEMS technology. Failure analysis and characterization are relatively simple at the wafer and die level where chip access is straightforward. However, analysis and characterization of packaged parts or components encapsulated with covers, caps, etc may be more cumbersome and lead to problems assessing the root cause of failure. This paper will discuss two methods used to prepare the backside of the package/device to allow for failure analysis and inspection of different MEMS components without removing the cap, cover, or lid on the device and/or the package. One method for backside preparation was grinding and polishing the package for IR inspection. This method involved backfilling the package cavity with epoxy to hold the die in place. The other method involved opening a window through the backside of the package, exposing the die for IR inspection. Failure analysis results showed both methods of backside preparation were successful in revealing the failure mechanisms on two different MEMS technologies.

  10. Automation Using Robotic Arm in Rotor Packaging

    OpenAIRE

    G. Gopu; ARJUN SHIBY M; NAGA ARJUN M; SHASHANK R; SINAN V

    2013-01-01

    Till date automation in small and medium scale industries has not enjoyed the same rate of growth as in other information technology sectors, lagging significantly behind automation in large batch production .The use of LabVIEW interfaced with micro-controller in controlling a robotic arm is a latest technique which is being implemented in this project. In medium scale industries packaging of rotors is done manually. This Process is time consuming and also requires manpower. Through this proj...

  11. CH Packaging Program Guidance

    International Nuclear Information System (INIS)

    The purpose of this document is to provide the technical requirements for preparation for use, operation, inspection, and maintenance of a Transuranic Package Transporter Model II (TRUPACT-II), a HalfPACT shipping package, and directly related components. This document complies with the minimum requirements as specified in the TRUPACT-II Safety Analysis Report for Packaging (SARP), HalfPACT SARP, and U.S. Nuclear Regulatory Commission (NRC) Certificates of Compliance (C of C) 9218 and 9279, respectively. In the event of a conflict between this document and the SARP or C of C, the C of C shall govern. The C of Cs state: 'each package must be prepared for shipment and operated in accordance with the procedures described in Chapter 7.0, Operating Procedures, of the application.' They further state: 'each package must be tested and maintained in accordance with the procedures described in Chapter 8.0, Acceptance Tests and Maintenance Program of the Application.' Chapter 9.0 of the SARP charges the U.S. Department of Energy (DOE) or the Waste Isolation Pilot Plant (WIPP) management and operating (M and O) contractor with assuring packaging is used in accordance with the requirements of the C of C. Because the packaging is NRC-approved, users need to be familiar with Title 10 Code of Federal Regulations (CFR) 71.8. Any time a user suspects or has indications that the conditions of approval in the C of C were not met, the Carlsbad Field Office (CBFO) shall be notified immediately. The CBFO will evaluate the issue and notify the NRC if required. In accordance with 10 CFR Part 71, certificate holders, packaging users, and contractors or subcontractors who use, design, fabricate, test, maintain, or modify the packaging shall post copies of (1) 10 CFR Part 21 regulations, (2) Section 206 of the Energy Reorganization Act of 1974, and (3) NRC Form 3, Notice to Employees. These documents must be posted in a conspicuous location where the activities subject to these regulations

  12. RH Packaging Program Guidance

    Energy Technology Data Exchange (ETDEWEB)

    Washington TRU Solutions LLC

    2006-11-07

    The purpose of this program guidance document is to provide the technical requirements for use, operation, inspection, and maintenance of the RH-TRU 72-B Waste Shipping Package and directly related components. This document complies with the requirements as specified in the RH-TRU 72-B Safety Analysis Report for Packaging (SARP), and Nuclear Regulatory Commission (NRC) Certificate of Compliance (C of C) 9212. If there is a conflict between this document and the SARP and/or C of C, the C of C shall govern. The C of C states: "...each package must be prepared for shipment and operated in accordance with the procedures described in Chapter 7.0, Operating Procedures, of the application." It further states: "...each package must be tested and maintained in accordance with the procedures described in Chapter 8.0, Acceptance Tests and Maintenance Program of the Application." Chapter 9.0 of the SARP tasks the Waste Isolation Pilot Plant (WIPP) Management and Operating (M&O) Contractor with assuring the packaging is used in accordance with the requirements of the C of C. Because the packaging is NRC-approved, users need to be familiar with 10 Code of Federal Regulations (CFR) §71.8, "Deliberate Misconduct." Any time a user suspects or has indications that the conditions of approval in the C of C were not met, the U.S. Department of Energy (DOE) Carlsbad Field Office (CBFO) shall be notified immediately. CBFO will evaluate the issue and notify the NRC if required. In accordance with 10 CFR Part 71, "Packaging and Transportation of Radioactive Material," certificate holders, packaging users, and contractors or subcontractors who use, design, fabricate, test, maintain, or modify the packaging shall post copies of (1) 10 CFR Part 21, "Reporting of Defects and Noncompliance," regulations, (2) Section 206 of the Energy Reorganization Act of 1974, and (3) NRC Form 3, Notice to Employees. These documents must be posted in a conspicuous location where the activities subject to

  13. CH Packaging Program Guidance

    Energy Technology Data Exchange (ETDEWEB)

    None, None

    2009-06-01

    The purpose of this document is to provide the technical requirements for preparation for use, operation, inspection, and maintenance of a Transuranic Package Transporter Model II (TRUPACT-II), a HalfPACT shipping package, and directly related components. This document complies with the minimum requirements as specified in the TRUPACT-II Safety Analysis Report for Packaging (SARP), HalfPACT SARP, and U.S. Nuclear Regulatory Commission (NRC) Certificates of Compliance (C of C) 9218 and 9279, respectively. In the event of a conflict between this document and the SARP or C of C, the C of C shall govern. The C of Cs state: "each package must be prepared for shipment and operated in accordance with the procedures described in Chapter 7.0, Operating Procedures, of the application." They further state: "each package must be tested and maintained in accordance with the procedures described in Chapter 8.0, Acceptance Tests and Maintenance Program of the Application." Chapter 9.0 of the SARP charges the U.S. Department of Energy (DOE) or the Waste Isolation Pilot Plant (WIPP) management and operating (M&O) contractor with assuring packaging is used in accordance with the requirements of the C of C. Because the packaging is NRC-approved, users need to be familiar with Title 10 Code of Federal Regulations (CFR) §71.8. Any time a user suspects or has indications that the conditions of approval in the C of C were not met, the Carlsbad Field Office (CBFO) shall be notified immediately. The CBFO will evaluate the issue and notify the NRC if required. In accordance with 10 CFR Part 71, certificate holders, packaging users, and contractors or subcontractors who use, design, fabricate, test, maintain, or modify the packaging shall post copies of (1) 10 CFR Part 21 regulations, (2) Section 206 of the Energy Reorganization Act of 1974, and (3) NRC Form 3, Notice to Employees. These documents must be posted in a conspicuous location where the activities subject to these regulations are

  14. CH Packaging Program Guidance

    Energy Technology Data Exchange (ETDEWEB)

    None, None

    2008-09-11

    The purpose of this document is to provide the technical requirements for preparation for use, operation, inspection, and maintenance of a Transuranic Package Transporter Model II (TRUPACT-II), a HalfPACT shipping package, and directly related components. This document complies with the minimum requirements as specified in the TRUPACT-II Safety Analysis Report for Packaging (SARP), HalfPACT SARP, and U.S. Nuclear Regulatory Commission (NRC) Certificates of Compliance (C of C) 9218 and 9279, respectively. In the event of a conflict between this document and the SARP or C of C, the C of C shall govern. The C of Cs state: "each package must be prepared for shipment and operated in accordance with the procedures described in Chapter 7.0, Operating Procedures, of the pplication." They further state: "each package must be tested and maintained in accordance with the procedures described in Chapter 8.0, Acceptance Tests and Maintenance Program of the Application." Chapter 9.0 of the SARP charges the U.S. Department of Energy (DOE) or the Waste Isolation Pilot Plant (WIPP) management and operating (M&O) contractor with assuring packaging is used in accordance with the requirements of the C of C. Because the packaging is NRC-approved, users need to be familiar with Title 10 Code of Federal Regulations (CFR) §71.8. Any time a user suspects or has indications that the conditions of approval in the C of C were not met, the Carlsbad Field Office (CBFO) shall be notified immediately. The CBFO will evaluate the issue and notify the NRC if required. In accordance with 10 CFR Part 71, certificate holders, packaging users, and contractors or subcontractors who use, design, fabricate, test, maintain, or modify the packaging shall post copies of (1) 10 CFR Part 21 regulations, (2) Section 206 of the Energy Reorganization Act of 1974, and (3) NRC Form 3, Notice to Employees. These documents must be posted in a conspicuous location where the activities subject to these regulations are

  15. RH Packaging Program Guidance

    Energy Technology Data Exchange (ETDEWEB)

    Washington TRU Solutions LLC

    2008-01-12

    The purpose of this program guidance document is to provide the technical requirements for use, operation, inspection, and maintenance of the RH-TRU 72-B Waste Shipping Package (also known as the "RH-TRU 72-B cask") and directly related components. This document complies with the requirements as specified in the RH-TRU 72-B Safety Analysis Report for Packaging (SARP), and Nuclear Regulatory Commission (NRC) Certificate of Compliance (C of C) 9212. If there is a conflict between this document and the SARP and/or C of C, the C of C shall govern. The C of C states: "...each package must be prepared for shipment and operated in accordance with the procedures described in Chapter 7.0, Operating Procedures, of the application." It further states: "...each package must be tested and maintained in accordance with the procedures described in Chapter 8.0, Acceptance Tests and Maintenance Program of the Application." Chapter 9.0 of the SARP tasks the Waste Isolation Pilot Plant (WIPP) Management and Operating (M&O) Contractor with assuring the packaging is used in accordance with the requirements of the C of C. Because the packaging is NRC-approved, users need to be familiar with Title 10 Code of Federal Regulations (CFR) §71.8, "Deliberate Misconduct." Any time a user suspects or has indications that the conditions of approval in the C of C were not met, the U.S. Department of Energy (DOE) Carlsbad Field Office (CBFO) shall be notified immediately. The CBFO will evaluate the issue and notify the NRC if required.In accordance with 10 CFR Part 71, "Packaging and Transportation of Radioactive Material," certificate holders, packaging users, and contractors or subcontractors who use, design, fabricate, test, maintain, or modify the packaging shall post copies of (1) 10 CFR Part 21, "Reporting of Defects and Noncompliance," regulations, (2) Section 206 of the Energy Reorganization Act of 1974, and (3) NRC Form 3, Notice to Employees. These documents must be posted in a

  16. Single-serve ice cream packaging: packaging structures enhancing brand

    OpenAIRE

    Salo, August

    2014-01-01

    The thesis focuses on packaging structures and branding; discussing the role packaging plays in brand identity. In today’s crowded marketplaces brands must fight to differentiate themselves from the competition by offering unique product experiences. As most products are packaged in one way or another, packaging has become a valuable element in brand communication and marketing. Packaging is seen as a part of the product experience, adding value and personality to otherwise similar products. ...

  17. Invisibility Cloak Printed on a Photonic Chip

    Science.gov (United States)

    Feng, Zhen; Wu, Bing-Hong; Zhao, Yu-Xi; Gao, Jun; Qiao, Lu-Feng; Yang, Ai-Lin; Lin, Xiao-Feng; Jin, Xian-Min

    2016-01-01

    Invisibility cloak capable of hiding an object can be achieved by properly manipulating electromagnetic field. Such a remarkable ability has been shown in transformation and ray optics. Alternatively, it may be realistic to create a spatial cloak by means of confining electromagnetic field in three-dimensional arrayed waveguides and introducing appropriate collective curvature surrounding an object. We realize the artificial structure in borosilicate by femtosecond laser direct writing, where we prototype up to 5,000 waveguides to conceal millimeter-scale volume. We characterize the performance of the cloak by normalized cross correlation, tomography analysis and continuous three-dimensional viewing angle scan. Our results show invisibility cloak can be achieved in waveguide optics. Furthermore, directly printed invisibility cloak on a photonic chip may enable controllable study and novel applications in classical and quantum integrated photonics, such as invisualising a coupling or swapping operation with on-chip circuits of their own. PMID:27329510

  18. Invisibility Cloak Printed on a Photonic Chip.

    Science.gov (United States)

    Feng, Zhen; Wu, Bing-Hong; Zhao, Yu-Xi; Gao, Jun; Qiao, Lu-Feng; Yang, Ai-Lin; Lin, Xiao-Feng; Jin, Xian-Min

    2016-01-01

    Invisibility cloak capable of hiding an object can be achieved by properly manipulating electromagnetic field. Such a remarkable ability has been shown in transformation and ray optics. Alternatively, it may be realistic to create a spatial cloak by means of confining electromagnetic field in three-dimensional arrayed waveguides and introducing appropriate collective curvature surrounding an object. We realize the artificial structure in borosilicate by femtosecond laser direct writing, where we prototype up to 5,000 waveguides to conceal millimeter-scale volume. We characterize the performance of the cloak by normalized cross correlation, tomography analysis and continuous three-dimensional viewing angle scan. Our results show invisibility cloak can be achieved in waveguide optics. Furthermore, directly printed invisibility cloak on a photonic chip may enable controllable study and novel applications in classical and quantum integrated photonics, such as invisualising a coupling or swapping operation with on-chip circuits of their own. PMID:27329510

  19. Practical Packaging Technology for Microfluidic Systems

    International Nuclear Information System (INIS)

    This paper presents the technology for the design, fabrication, and characterization of a microfluidic system interface (MSI): the purpose of this technology is to enable the integration of complex microfluidic systems. The MSI technology can be applied in a simple manner for realizing complex arrangements of microfluidic interconnects, integrated microvalves for fluid control, and optical windows for on-chip optical processes. A microfluidic system for the preparation of genetic samples was used as the test vehicle to prove the effectiveness of the MSI technology for packaging complex microfluidic systems with multiple functionalities. The miniaturized genetic sample preparation system comprised several functional compartments, including compartments for cell purification, cell separation, cell lysis, solid-phase DNA extraction, polymerase chain reaction, and capillary electrophoresis. Additionally, the functional operation of the solid-phase extraction and PCR thermocycling compartments was demonstrated by using the MSI

  20. On-chip pretreatment of whole blood by using MEMS technology

    CERN Document Server

    Chen, Xing

    2012-01-01

    Microfabrication technology has stimulated a plurality of lab-on-a-chip research and development efforts aimed at enabling biomedical researchers and health care practitioners to manipulate and analyze complex biological fluids at the nano and microliter scale. On-chip pretreatment of whole blood is one of the hottest topics in lab-on-a-chip research since whole blood has been regarded as the most important clinical sample. Various microfluidic chips for blood sample pretreatment, such as plasma isolation, cells separation, cells lysis, gene or protein purification, etc., are described in this

  1. CH Packaging Program Guidance

    International Nuclear Information System (INIS)

    The purpose of this document is to provide the technical requirements for preparation for use, operation, inspection, and maintenance of a Transuranic Package Transporter Model II (TRUPACT-II), a HalfPACT shipping package, and directly related components. This document complies with the minimum requirements as specified in the TRUPACT-II Safety Analysis Report for Packaging (SARP), HalfPACT SARP, and U.S. Nuclear Regulatory Commission (NRC) Certificates of Compliance (C of C) 9218 and 9279, respectively. In the event of a conflict between this document and the SARP or C of C, the C of C shall govern. The C of Cs state: ''each package must be prepared for shipment and operated in accordance with the procedures described in Chapter 7.0, Operating Procedures, of the application.'' They further state: ''each package must be tested and maintained in accordance with the procedures described in Chapter 8.0, Acceptance Tests and Maintenance Program of the Application.'' Chapter 9.0 of the SARP charges the Waste Isolation Pilot Plant (WIPP) management and operating (M and O) contractor with assuring packaging is used in accordance with the requirements of the C of C. Because the packaging is NRC-approved, users need to be familiar with Title 10 Code of Federal Regulations (CFR) 71.8. Any time a user suspects or has indications that the conditions of approval in the C of C were not met, the Carlsbad Field Office (CBFO) shall be notified immediately. The CBFO will evaluate the issue and notify the NRC if required.

  2. Food Packaging Materials

    Science.gov (United States)

    1978-01-01

    The photos show a few of the food products packaged in Alure, a metallized plastic material developed and manufactured by St. Regis Paper Company's Flexible Packaging Division, Dallas, Texas. The material incorporates a metallized film originally developed for space applications. Among the suppliers of the film to St. Regis is King-Seeley Thermos Company, Winchester, Ma'ssachusetts. Initially used by NASA as a signal-bouncing reflective coating for the Echo 1 communications satellite, the film was developed by a company later absorbed by King-Seeley. The metallized film was also used as insulating material for components of a number of other spacecraft. St. Regis developed Alure to meet a multiple packaging material need: good eye appeal, product protection for long periods and the ability to be used successfully on a wide variety of food packaging equipment. When the cost of aluminum foil skyrocketed, packagers sought substitute metallized materials but experiments with a number of them uncovered problems; some were too expensive, some did not adequately protect the product, some were difficult for the machinery to handle. Alure offers a solution. St. Regis created Alure by sandwiching the metallized film between layers of plastics. The resulting laminated metallized material has the superior eye appeal of foil but is less expensive and more easily machined. Alure effectively blocks out light, moisture and oxygen and therefore gives the packaged food long shelf life. A major packaging firm conducted its own tests of the material and confirmed the advantages of machinability and shelf life, adding that it runs faster on machines than materials used in the past and it decreases product waste; the net effect is increased productivity.

  3. CH Packaging Program Guidance

    International Nuclear Information System (INIS)

    The purpose of this document is to provide the technical requirements for preparation for use, operation, inspection, and maintenance of a Transuranic Package Transporter Model II (TRUPACT-II), a HalfPACT shipping package, and directly related components. This document complies with the minimum requirements as specified in the TRUPACT-II Safety Analysis Report for Packaging (SARP), HalfPACT SARP, and U.S. Nuclear Regulatory Commission (NRC) Certificates of Compliance (C of C) 9218 and 9279, respectively. In the event of a conflict between this document and the SARP or C of C, the C of C shall govern. The C of Cs state: 'each package must be prepared for shipment and operated in accordance with the procedures described in Chapter 7.0, Operating Procedures, of the application.' They further state: 'each package must be tested and maintained in accordance with the procedures described in Chapter 8.0, Acceptance Tests and Maintenance Program of the Application.' Chapter 9.0 of the SARP charges the U.S. Department of Energy (DOE) or the Waste Isolation Pilot Plant| (WIPP) management and operating (M and O) contractor with assuring packaging is used in accordance with the requirements of the C of C. Because the packaging is NRC-approved, users need to be familiar with Title 10 Code of Federal Regulations(CFR) 71.8. Any time a user suspects or has indications that the conditions of approval in the C of C were not met, the Carlsbad Field Office (CBFO) shall be notified immediately. The CBFO will evaluate the issue and notify the NRC if required.In accordance with 10 CFR Part 71, certificate holders, packaging users, and contractors or subcontractors who use, design, fabricate, test, maintain, or modify the packaging shall post copies of (1) 10 CFR Part 21 regulations, (2) Section 206 of the Energy Reorganization Act of 1974, and (3) NRC Form 3, Notice to Employees. These documents must be posted in a conspicuous location where the activities subject to these regulations

  4. CH Packaging Program Guidance

    International Nuclear Information System (INIS)

    The purpose of this document is to provide the technical requirements for preparation for use, operation, inspection, and maintenance of a Transuranic Package Transporter Model II (TRUPACT-II), a HalfPACT shipping package, and directly related components. This document complies with the minimum requirements as specified in the TRUPACT-II Safety Analysis Report for Packaging (SARP), HalfPACT SARP, and U.S. Nuclear Regulatory Commission (NRC) Certificates of Compliance (C of C) 9218 and 9279, respectively. In the event of a conflict between this document and the SARP or C of C, the C of C shall govern. The C of Cs state: 'each package must be prepared for shipment and operated in accordance with the procedures described in Chapter 7.0, Operating Procedures, of the application.' They further state: 'each package must be tested and maintained in accordance with the procedures described in Chapter 8.0, Acceptance Tests and Maintenance Program of the Application.' Chapter 9.0 of the SARP charges the U.S. Department of Energy (DOE) or the Waste Isolation Pilot Plant (WIPP) management and operating (M and O) contractor with assuring packaging is used in accordance with the requirements of the C of C. Because the packaging is NRC-approved, users need to be familiar with Title 10 Code of Federal Regulations (CFR) 71.8. Any time a user suspects or has indications that the conditions of approval in the C of C were not met, the Carlsbad Field Office (CBFO) shall be notified immediately. The CBFO will evaluate the issue and notify the NRC if required.In accordance with 10 CFR Part 71, certificate holders, packaging users, and contractors or subcontractors who use, design, fabricate, test, maintain, or modify the packaging shall post copies of (1) 10 CFR Part 21 regulations, (2) Section 206 of the Energy Reorganization Act of 1974, and (3) NRC Form 3, Notice to Employees. These documents must be posted in a conspicuous location where the activities subject to these regulations

  5. CH Packaging Program Guidance

    Energy Technology Data Exchange (ETDEWEB)

    None, None

    2006-04-25

    The purpose of this document is to provide the technical requirements for preparation for use, operation, inspection, and maintenance of a Transuranic Package TransporterModel II (TRUPACT-II), a HalfPACT shipping package, and directly related components. This document complies with the minimum requirements as specified in the TRUPACT-II Safety Analysis Report for Packaging (SARP), HalfPACT SARP, and U.S. Nuclear Regulatory Commission (NRC) Certificates of Compliance (C of C) 9218 and 9279, respectively. In the event of a conflict between this document and the SARP or C of C, the C of C shall govern. The C of Cs state: "each package must be prepared for shipment and operated in accordance with the procedures described in Chapter 7.0, Operating Procedures, of the application." They further state: "each package must be tested and maintained in accordance with the procedures described in Chapter 8.0, Acceptance Tests and Maintenance Program of the Application." Chapter 9.0 of the SARP charges the U.S. Department of Energy (DOE) or the Waste Isolation Pilot Plant| (WIPP) management and operating (M&O) contractor with assuring packaging is used in accordance with the requirements of the C of C. Because the packaging is NRC-approved, users need to be familiar with Title 10 Code of Federal Regulations(CFR) §71.8. Any time a user suspects or has indications that the conditions ofapproval in the C of C were not met, the Carlsbad Field Office (CBFO) shall be notified immediately. The CBFO will evaluate the issue and notify the NRC if required.In accordance with 10 CFR Part 71, certificate holders, packaging users, and contractors or subcontractors who use, design, fabricate, test, maintain, or modify the packaging shall post copies of (1) 10 CFR Part 21 regulations, (2) Section 206 of the Energy Reorganization Act of 1974, and (3) NRC Form 3, Notice to Employees. These documents must be posted in a conspicuous location where the activities subject to these regulations are

  6. CH Packaging Program Guidance

    Energy Technology Data Exchange (ETDEWEB)

    None, None

    2007-12-13

    The purpose of this document is to provide the technical requirements for preparation for use, operation, inspection, and maintenance of a Transuranic Package Transporter Model II (TRUPACT-II), a HalfPACT shipping package, and directly related components. This document complies with the minimum requirements as specified in the TRUPACT-II Safety Analysis Report for Packaging (SARP), HalfPACT SARP, and U.S. Nuclear Regulatory Commission (NRC) Certificates of Compliance (C of C) 9218 and 9279, respectively. In the event of a conflict between this document and the SARP or C of C, the C of C shall govern. The C of Cs state: "each package must be prepared for shipment and operated in accordance with the procedures described in Chapter 7.0, Operating Procedures, of the application." They further state: "each package must be tested and maintained in accordance with the procedures described in Chapter 8.0, Acceptance Tests and Maintenance Program of the Application." Chapter 9.0 of the SARP charges the U.S. Department of Energy (DOE) or the Waste Isolation Pilot Plant (WIPP) management and operating (M&O) contractor with assuring packaging is used in accordance with the requirements of the C of C. Because the packaging is NRC-approved, users need to be familiar with Title 10 Code of Federal Regulations (CFR) §71.8. Any time a user suspects or has indications that the conditions of approval in the C of C were not met, the Carlsbad Field Office (CBFO) shall be notified immediately. The CBFO will evaluate the issue and notify the NRC if required.In accordance with 10 CFR Part 71, certificate holders, packaging users, and contractors or subcontractors who use, design, fabricate, test, maintain, or modify the packaging shall post copies of (1) 10 CFR Part 21 regulations, (2) Section 206 of the Energy Reorganization Act of 1974, and (3) NRC Form 3, Notice to Employees. These documents must be posted in a conspicuous location where the activities subject to these regulations are

  7. Studies on bulk packaging of irradiated dried fish

    International Nuclear Information System (INIS)

    An experiment has been conducted to evaluate suitable packaging method to be used in large scale dried fish irradiation. The study consisted of the selection of packaging materials used, determination of irradiation effects on physical characteristics of the packaging material, and determination of dose uniformity in the dried fish packages. From the point of view of physical strength, woven polypropylene bag lined with low density polyethylene film of 0.1 mm thickness, and carton box were found to be suitable for packaging of irradiated dried fish. However, from technological point of view, carton boxes were found to be more practicable to be used in irradiation process and gave better dose uniformity in the package. Irradiation doses of up to 5 and 10 kGy seem to have no significant effect on physical characteristics of the carton boxes and woven plastic bags, respectively. (author)

  8. Dental Care for Medicaid and CHIP Enrollees

    Science.gov (United States)

    ... Amendments Dental Care Dental Care for Medicaid and CHIP Enrollees Dental health is an important part of ... for dental services. Dental Benefits for Children in CHIP States that provide CHIP coverage to children through ...

  9. Waste package characterisation

    International Nuclear Information System (INIS)

    Radioactive wastes originating from the hot labs of the Belgian Nuclear Research Centre SCK-CEN contain a wide variety of radiotoxic substances. The accurate characterisation of the short- and long-term radiotoxic components is extremely difficult but required in view of geological disposal. This paper describes the methodology which was developed and adopted to characterise the high- and medium-level waste packages at the SCK-CEN hot laboratories. The proposed method is based on the estimation of the fuel inventory evacuated in a particular waste package; a calculation of the relative fission product contribution on the fuel fabrication and irradiation footing; a comparison of the calculated, as expected, dose rate and the real measured dose rate of the waste package. To cope with the daily practice an appropriate fuel inventory estimation route, a user friendly computer programme for fission product and corresponding dose rate calculation, and a simple dose rate measurement method have been developed and implemented

  10. Novel optimized design of a piezoelectric energy harvester in a package for low amplitude vibrations

    International Nuclear Information System (INIS)

    This paper presents a novel piezoelectric energy harvesting device created with the flip-chip bonding of two different parts, one is a MEMS die which plays the role of inertial mass and the other is an associate CMOS chip anchored to the vibrating environment. The flip-chip bonding is performed between the MEMS die, which consists of four piezoelectric beams connected to four PADs or anchor points, and a test PCB, which is used to validate the feasibility of the whole assembled system. The resulting system in package is a proof of concept of a novel design concept that increases the extracted power from an ambient vibration. FEM simulations have been carried out to study the mechanical behaviour of the who le system. Moreover, the fabrication of the piezoelectric die and the test PCB has been successfully performed, as well as their flip-chip integration

  11. Packaging Solutions : Delivering customer value through Logistical Packaging: A Case Study at Stora Enso Packaging

    OpenAIRE

    Shan, Kun; Julius, Joezer

    2015-01-01

    AbstractBackground;Despite of the significant role of packaging within logistics and supply chain management, packaging is infrequently studied as focal point in supply chain. Most of the previous logistics research studies tend to explain the integration between packaging and logistics through logistical packaging. In very rare cases, the studies mentioned about customer value. Therefore the major disadvantage of these studies is that, they didn’t consider logistical packaging and customer v...

  12. An ECG-on-Chip with 535-nW/Channel Integrated Lossless Data Compressor for Wireless Sensors

    OpenAIRE

    Deepu, C. J.; Zhang, X.; Liew, W. -S.; Wong, D. L. T.; Lian, Y.

    2014-01-01

    This paper presents a low-power ECG recording system-on-chip (SoC) with on-chip low-complexity lossless ECG compression for data reduction in wireless/ambulatory ECG sensor devices. The chip uses a linear slope predictor for data compression, and incorporates a novel low-complexity dynamic coding-packaging scheme to frame the prediction error into fixed-length 16-bit format. The proposed technique achieves an average compression ratio of 2.25x on MIT/BIH ECG database. Implemented in a standar...

  13. SPHINX experimenters information package

    Energy Technology Data Exchange (ETDEWEB)

    Zarick, T.A. [Sandia National Lab., Albuquerque, NM (United States). Radiation Effects Experimentation Dept.

    1996-08-01

    This information package was prepared for both new and experienced users of the SPHINX (Short Pulse High Intensity Nanosecond X-radiator) flash X-Ray facility. It was compiled to help facilitate experiment design and preparation for both the experimenter(s) and the SPHINX operational staff. The major areas covered include: Recording Systems Capabilities,Recording System Cable Plant, Physical Dimensions of SPHINX and the SPHINX Test cell, SPHINX Operating Parameters and Modes, Dose Rate Map, Experiment Safety Approval Form, and a Feedback Questionnaire. This package will be updated as the SPHINX facilities and capabilities are enhanced.

  14. SPHINX experimenters information package

    International Nuclear Information System (INIS)

    This information package was prepared for both new and experienced users of the SPHINX (Short Pulse High Intensity Nanosecond X-radiator) flash X-Ray facility. It was compiled to help facilitate experiment design and preparation for both the experimenter(s) and the SPHINX operational staff. The major areas covered include: Recording Systems Capabilities,Recording System Cable Plant, Physical Dimensions of SPHINX and the SPHINX Test cell, SPHINX Operating Parameters and Modes, Dose Rate Map, Experiment Safety Approval Form, and a Feedback Questionnaire. This package will be updated as the SPHINX facilities and capabilities are enhanced

  15. Autonomous packaging robot

    OpenAIRE

    Vo, Van Thanh

    2010-01-01

    The objective of the autonomous packaging robot application is to replace manual product packaging in food industry with a fully automatic robot. The objective is achieved by using the combination of machine vision, central computer, sensors, microcontroller and a typical ABB robot. The method is to equip the robot with different sensors: camera as “eyes” of robot, distance sensor and microcontroller as “sense of touch” of the robot, central computer as “brain” of the robot. Because the ro...

  16. Optimization of Cardboard Packaging

    OpenAIRE

    Dominika Crnjac Milic

    2010-01-01

    The paper will show that the area of a cube is less than the area of a parallelepiped of the same volume, and that the volume of the cube is greater than the volume of the parallelepiped of the same area, what is of major importance for the transportation of goods in cardboard packaging with the possibility of application to other packaging materials. Motivation for finding an exact mathematical proof for this problem originates from the Nestle company, since inadequate forms of product packa...

  17. Polymer dispensing and embossing technology for the lens type LED packaging

    International Nuclear Information System (INIS)

    This study presents a ring-type micro-structure design on the substrate and its corresponding micro fabrication processes for a lens-type light-emitting diode (LED) package. The dome-type or crater-type silicone lenses are achieved by a dispensing and embossing process rather than a molding process. Silicone with a high viscosity and thixotropy index is used as the encapsulant material. The ring-type micro structure is adopted to confine the dispensed silicone encapsulant so as to form the packaged lens. With the architecture and process described, this LED package technology herein has three merits: (1) the flexibility of lens-type LED package designs is enhanced; (2) a dome-type package design is used to enhance the intensity; (3) a crater-type package design is used to enhance the view angle. Measurement results show the ratio between the lens height and lens radius can vary from 0.4 to 1 by changing the volume of dispensed silicone. The view angles of dome-type and crater-type packages can reach 155° ± 5° and 175° ± 5°, respectively. As compared with the commercial plastic leaded chip carrier-type package, the luminous flux of a monochromatic blue light LED is improved by 15% by the dome-type package (improved by 7% by the crater-type package) and the luminous flux of a white light LED is improved by 25% by the dome-type package (improved by 13% by the crater-type package). The luminous flux of monochromatic blue light LED and white light LED are respectively improved by 8% and 12% by the dome-type package as compare with the crater-type package. (paper)

  18. A wafer-level multi-chip module process with thick photosensitive benzocyclobutene as the dielectric for microwave application

    International Nuclear Information System (INIS)

    A wafer-level microwave multi-chip module (MMCM) packaging process is presented. Thick photosensitive-benzocyclobutene (photo-BCB) polymer (about 25 µm/layer) is used as the dielectric for its simplified process and the capability of obtaining desirable electrical, chemical and mechanical properties at high frequencies. The MMCM packaging structure contains a monolithic microwave integrated circuit (MMIC) chip embedded in a lossy-silicon wafer, a microwave band-pass filter (BPF) and two layers of BCB/Au interconnection. Key processes of fabrication are described in detail. The non-uniformity of BCB film and the sidewall angle of the via-holes for inter-layer connection are tested. Via-chains prepared by metal/BCB multilayer structures are tested through the Kelvin test structure to investigate the resistances of inter-layer connection. The average value is measured to be 73.5 mΩ. The electrical characteristic of this structure is obtained by a microwave transmission performance test from 15 to 30 GHz. The measurement results show good consistency between the bare MMIC die and the packaged die in the test frequency band. The gain of the MMIC chip after packaging is better than 18 dB within the designed operating frequency range (from 23 to 25 GHz). When the packaged MMIC chip is connected to a BPF, the maximum gain is still measured to reach 11.95 dB at 23.8 GHz

  19. Broadband Packaging of Photodetectors for 100 Gb/s Ethernet Applications

    DEFF Research Database (Denmark)

    Jiang, Chenhui; Krozer, Viktor; Bach, Heinz-Gunter;

    2013-01-01

    of limiting the bandwidth of PD modules. After eliminating the mode mismatch effect by improving the chip-conductor-backed coplanar waveguide transition, a final optimal packaging structure is implemented for the PD module with reduced attenuation up to 100 GHz and a broader 3-dB bandwidth of more than 90 GHz......The packing structure of functional modules is a major limitaion in achieving a desired performance for 100 Gb/s ethernet applications. This paper presents a methodology of developing advanced packaging of photodetectors (PDs) for high-speed data transmission applications by using 3-D...... electromagnetic (EM) simulations. A simplified model of the PD module is first used to analyze and optimize packaging structures and propose an optimal packaging design based on the simplified model. Although a PD module with improved performance proved the success of the optimal packaging design, the simplified...

  20. Integration of microelectronic chips in microfluidic systems on printed circuit board

    International Nuclear Information System (INIS)

    A new scheme for the integration of small semiconductor transducer chips with microfluidic structures on printed circuit board (PCB) is presented. The proposed approach is based on a packaging technique that yields a large and flat area with small and shallow (∼44 µm deep) openings over the chips. The photocurable encapsulant material used, based on a diacrylate bisphenol A polymer, enables irreversible bonding of polydimethylsiloxane microfluidic structures at moderate temperatures (80 °C). This integration scheme enables the insertion of transducer chips in microfluidic systems with a lower added volume than previous schemes. Leakage tests have shown that the bonded structures withstand more than 360 kPa of pressure. A prototype microfluidic system with two detection chips, including one inter-digitated electrode (IDE) chip for conductivity and one ion selective field effect transistor (ISFET) chip for pH, has been implemented and characterized. Good electrical insulation of the chip contacts and silicon edge surfaces from the solution in the microchannels has been achieved. This integration procedure opens the door to the low-cost fabrication of complex analytical microsystems that combine the extraordinary potential of both the microfluidics and silicon microtechnology fields. (paper)

  1. Heat transfer in high density electronics packaging

    Institute of Scientific and Technical Information of China (English)

    2001-01-01

    In order to get an insight into the thermal characteristic and to evaluate the thermal reliability of the "System in Packaging"(SIP), a new solution of electronics packaging, a heat transfer model of SIP was developed to predict the heat dissipation capacity and to investigate the effect of different factors on the temperature distribution in the electronics. The affecting parameters under consideration include the thermophysical properties of the substrates, the coefficient of convection heat transfer, the thickness of the chip, and the density of power dissipation. ALGOR, a kind of finite element analysis software,was used to do the model simulation. Based on the sinulation and analysis of the heat conduction and convection resistance, criteria for the thermal design were established and possible measurement for enhancing power dissipation was provided, The results show that the heat transfer model provides a new and effective way to the thermal design and thermal analysis of SIP and to the mechanical analysis for the further investigation of SIP.

  2. Packaged and connectorized optical interconnect circuits for optoelectronic cross-connect switching

    Science.gov (United States)

    Popelek, Jan; Ai, Jun; Li, Yao

    1999-10-01

    Cross-connect switching is a common switching architecture for telecom and datacom applications. Large bandwidth O-E interface devices have recently been made commercially available. Small scale fast electronic switches and large scale optical interconnect circuits can be effectively used for handling large bandwidth O-E cross-connect switching. In this paper, we show two packaged and connectorized optical interconnect circuits. The first one is a 100 X 100 channel guided-wave circuit fully compatible, through MT array connectors, to O-E interface devices, such as Motorola OPTOBUSTM or Simens PAROLITM chips. The second one is a more scalable architecture which is a hybrid of free- space and fiber circuits. For demonstration purpose, a 256 X 256 channel hybrid circuit is shown. Key parameters, such as insertion loss, cross-talk, and bit-error-rate of these interconnect circuits are presented. Transmission and routing of video data are performed to demonstrate interconnect quality of various data links. Scalability of these demonstrated circuits to larger sizes are speculated.

  3. Aquaculture Information Package

    Energy Technology Data Exchange (ETDEWEB)

    Boyd, T.; Rafferty, K. [editors

    1998-01-01

    This package of information is intended to provide background to developers of geothermal aquaculture projects. The material is divided into eight sections and includes information on market and price information for typical species, aquaculture water quality issues, typical species culture information, pond heat loss calculations, an aquaculture glossary, regional and university aquaculture offices and state aquaculture permit requirements.

  4. Openability of tamperproof packaging

    NARCIS (Netherlands)

    Del Castillo C., A.; Wever, R.; Buijs, P.J.; Stevels, A.

    2007-01-01

    Communication, product protection and presentation are three key aspects in the world of packaging nowadays. Due to a retail landscape consisting of large stores, displaying packed products on the shelves in self-service environments, these aspects become increasingly important, not only for Fast Mo

  5. Printer Graphics Package

    Science.gov (United States)

    Blanchard, D. C.

    1986-01-01

    Printer Graphics Package (PGP) is tool for making two-dimensional symbolic plots on line printer. PGP created to support development of Heads-Up Display (HUD) simulation. Standard symbols defined with HUD in mind. Available symbols include circle, triangle, quadrangle, window, line, numbers, and text. Additional symbols easily added or built up from available symbols.

  6. Polymers in Waveguide Packaging

    Institute of Scientific and Technical Information of China (English)

    Zhiyi Zhang; G. Z.Xiao; Jiaren Liu; C. P. Grover

    2003-01-01

    Polymers were successfully used in the packaging of waveguide-based photonic components in the area of fiber-to-waveguide coupling, waveguide die attachment, strain relief, and waveguide encapsulation. The application results of these polymers were described in this paper.

  7. Waste disposal package

    Science.gov (United States)

    Smith, M.J.

    1985-06-19

    This is a claim for a waste disposal package including an inner or primary canister for containing hazardous and/or radioactive wastes. The primary canister is encapsulated by an outer or secondary barrier formed of a porous ceramic material to control ingress of water to the canister and the release rate of wastes upon breach on the canister. 4 figs.

  8. Geothermal Greenhouse Information Package

    Energy Technology Data Exchange (ETDEWEB)

    Rafferty, K. [P.E.; Boyd, T. [ed.

    1997-01-01

    This package of information is intended to provide a foundation of background information for developers of geothermal greenhouses. The material is divided into seven sections covering such issues as crop culture and prices, operating costs for greenhouses, heating system design, vendors and a list of other sources of information.

  9. The Swarm Magnetometry Package

    DEFF Research Database (Denmark)

    Merayo, José M.G.; Jørgensen, John Leif; Friis-Christensen, Eigil;

    2008-01-01

    The Swarm mission under the ESA's Living Planet Programme is planned for launch in 2010 and consists of a constellation of three satellites at LEO. The prime objective of Swarm is to measure the geomagnetic field with unprecedented accuracy in space and time. The magnetometry package consists of an...

  10. The Swarm Magnetometry Package

    DEFF Research Database (Denmark)

    Merayo, José M.G.; Jørgensen, John Leif; Friis-Christensen, Eigil; Brauer, Peter; Primdahl, Fritz; Jørgensen, Peter Siegbjørn; Allin, Thomas Højgaard; Denver, Troelz

    The Swarm mission under the ESA's Living Planet Programme is planned for launch in 2010 and consists of a constellation of three satellites at LEO. The prime objective of Swarm is to measure the geomagnetic field with unprecedented accuracy in space and time. The magnetometry package consists of an...

  11. Silicon integrated nanophotonics for on-chip interconnects

    Science.gov (United States)

    Vlasov, Yurii

    2008-03-01

    Current trend in microelectronics industry is to increase the parallelism in computation by multi-threading, by building large scale multi-chip systems and, more recently, by increasing the number of cores on a single chip. With such increase of parallelization the interconnect bandwidth between the racks, chips or different cores is becoming a limiting factor for the design of high performance computer systems. The on-chip ultrahigh-bandwidth silicon-based photonic network might provide an attractive solution to this bandwidth bottleneck. We will review recent results on silicon nanophotonic circuits based on photonic wires and photonic crystals. Strong light confinement at the diffraction limit enables dramatic scaling of the device area and allows unprecedented control over optical signals. Silicon nanophotonic devices have immense capacity for low-loss, high-bandwidth data processing that might enable the design of ultra-compact on-chip optical networks. In particular we will show recent results on design and characterization of various ultra-compact (circuits as optical delay lines, electro-optic modulators, broadband optical switches, wavelength filters, etc.

  12. Multichip packaging technology with laser-patterned interconnects

    Science.gov (United States)

    Barfknecht, Andrew T.; Tuckerman, David B.; Kaschmitter, James L.; McWilliams, Bruce M.

    1989-04-01

    A multichip silicon-on-silicon packaging technology was developed which incorporates laser-patterned thin-film interconnects. This technology is particularly suited for application in high speed, high power, and high I/O systems where its unique characteristics provide many advantages over more traditional methods. The laser-patterned thin-film interconnects allow higher I/O densities and better electrical performance than wire bonds or TAB. The face-up, thin-film eutectic die attach technique used provides much lower thermal resistance between the substrate and the chips than solder bump die attach can achieve. In addition, laser-patterned interconnects demonstrate superior ruggedness and fatigue resistance under thermomechanical cycling and shock. This technology was used to produce a 10-chip memory module, samples of which were tested to relevant methods of MIL-STD 883C.

  13. Package performance evaluation: our latest 20-year experience

    International Nuclear Information System (INIS)

    Packages for the transport of radioactive material have to comply with national and / or international regulations. These regulations are widely based on the requirements set forth by the International Atomic Energy Agency (IAEA) in the ''Regulations for the Safe Transport of Radioactive Material''. During the last 20 years, on several of its package designs, COGEMA LOGISTICS has performed tests and analyses to simulate extremely severe accidents. These tests and analysis include: 1. long duration fire test and deep immersion test on a package designed to transport plutonium oxide powder, 2. deep immersion tests on scale model of packages designed to transport spent fuel, high level vitrified waste and fresh MOX (uranium and plutonium mixed oxide) fuel, 3. burial in a soft ground of packages designed to transport spent fuel, and 4. numerical study of the thermal behaviour of packages designed to transport spent fuel and high level vitrified waste. 5. aircraft crash test on scale models of dual-purpose packages for the transport and storage of spent fuel. The paper will: review the tests and analysis which were performed, show that our designs are able to withstand extremely severe conditions, demonstrate that there is no cliff effect: should a failure occurs, it appears gradually and there is no sudden collapse of the package, and explain how compliance with all the regulatory requirements lead to high performances regarding each of them (for instance, in many cases, the need to meet radiation exposure criteria induces a mechanical resistance higher than that required to pass the regulatory requirements)

  14. Chips with everything

    CERN Document Server

    CERN. Geneva

    2007-01-01

    In March 1972, Sir Robin Saxby gave a talk to the Royal Television Society called 'TV and Chips' about a 'state of the art' integrated circuit, containing 50 resistors and 50 transistors. Today's 'state of the art' chips contain up to a billion transistors. This enormous leap forward illustrates how dramatically the semiconductor industry has evolved in the past 34 years. The next 10 years are predicted to bring times of turbulent change for the industry, as more and more digital devices are used around the world. In this talk, Sir Robin will discuss the history of the Microchip Industry in parallel with ARM's history, demonstrating how a small European start-up can become a world player in the IT sector. He will also present his vision of important applications and developments in the next 20 years that are likely to become even more pervasive than the mobile phone is today, and will provide anecdotes and learning points from his own experience at ARM. About ARM: Sir Robin and a group of designers from Acorn...

  15. Lakes Ecosystem Services Download Package

    Data.gov (United States)

    U.S. Environmental Protection Agency — This data download package contains Esri 10.0 MXDs, file geodatabases and copy of this FGDC metadata record. The data in this package are used in support of the...

  16. Designing a WISHBONE Protocol Network Adapter for an Asynchronous Network-on-Chip

    OpenAIRE

    Soliman, Ahmed H. M.; E. M.Saad; M El Bably; Keshk, Hesham M. A. M.

    2012-01-01

    The Scaling of microchip technologies, from micron to submicron and now to deep sub-micron (DSM) range, has enabled large scale systems-on-chip (SoC). In future deep submicron (DSM) designs, the interconnect effect will definitely dominate performance. Network-on-Chip (NoC) has become a promising solution to bus-based communication infrastructure limitations. NoC designs usually targets Application Specific Integrated Circuits (ASICs), however, the fabrication process costs a lot. Implementin...

  17. Characterization of quartz-based package for RF MEMS

    Science.gov (United States)

    Sordo, G.; Faes, A.; Resta, G.; Iannacci, J.

    2013-05-01

    In the last decade Micro-Electro-Mechanical Systems (MEMS) technology experienced a significant development in various fields of Information and Communication Technology (ICT). In particular MEMS for Radio Frequency (RF) applications have emerged as a remarkable solution in order to fabricate components with outstanding performances. The encapsulation of such devices is a relevant aspect to be addressed in order to enable wide exploitation of RF-MEMS technology in commercial applications. A MEMS package must not only protect fragile mechanical parts but also provide the interface to the next level of the packaging hierarchy in a cost effective technology. Additionally, in RF applications the electromagnetic impact of the package has to be carefully considered. Given such a scenario, the focus of this work is the characterization of a chip capping solution for RF-MEMS devices. Such solution uses a quartz cap having an epoxy-based dry film sealing ring. Relevant issues affecting RF-MEMS devices once packaged, e.g. the mechanical strain induced by the cap and the hermeticity of the sealing ring, are worth investigating. This work focuses on the study of induced strain, as a function of different bonding parameters. Dimensional features of the sealing ring (i.e. the width), and process parameters, like temperature and pressure, have been considered. The package characterization is performed by using basic test vehicles, such as strain gauges, designed to be integrated inside the internal cavity of the package itself. Polysilicon piezoresistors are used as strain gauges, whereas aluminum resistors are used as thermometers to assess the impact of temperature changes on strain measurements. Experimental data are reported including calibration of the sensors as well as environmental measurements with and without cap. In addition measurements of the shear stress of the proposed packaging solution are also reported.

  18. Wood chips procurement and research project at the Mikkeli region; Puuhakkeen hankinta- ja tutkimusprojekti Mikkelin seudulla

    Energy Technology Data Exchange (ETDEWEB)

    Saksa, T. [Finnish Forest Research Inst., Suonenjoki (Finland). Suonenjoki Research Station; Auvinen, P. [Mikkeli city (Finland). Dept. of Agriculture and Forestry

    1996-12-31

    In 1993-94, a large-scale energywood production chain started as a co-operation project by the Mikkeli city forest office and local forestry societies. In 1995 over 115 000 m{sup 3} (about 85 000 MWh of energy) of wood chips were delivered to Pursiala heat and power plant in Mikkeli. About 75 % of these chips was forest processed chips. About 70 % of the forest processed chips was whole tree chips from improvement cuttings of young forest stands and the rest was logging waste chips from regeneration cutting areas. The average total delivery costs of forest processed chips after reduction of energywood and other subsidies were approximately 45 FIM/m{sup 3} (60 FIM/MWh) for the whole tree chips and 38 FIM/m{sup 3} (50 FIM/MWh) for logging waste chips. The delivery costs of forest processed chips could meet the target of Bioenergy Research Programme (45 FIM/MWh) only in the most favourable cases. In an average the delivery costs were about 9 FIM/MWh more than the price obtained when sold to the heat and power plant. However the wood chip production created 27 new jobs and the increase of income to the local economy was about 2.2 milj. FIM /year. The local communities got new tax revenue about 3 FIM/MWh. The gain for the forestry was approximated to be 5 - 6 FIM/MWh. The resources of forest processed chips were studied on the basis of stand measurements. According to the study the most remarkable energywood resources were in young thinning stands on Oxalis-Myrtillus and Myrtillus forest site types. On Oxalis-Myrtillus type almost every and on Myrtillus type every second stand included energywood more than 40 m{sup 3}/ha

  19. Packaging based on polymeric materials

    OpenAIRE

    Jovanović Slobodan M.; Živković Predrag M.; Stoiljković Dragoslav M.

    2005-01-01

    In the past two years the consumption of common in the developed countries world wide (high tonnage) polymers for packaging has approached a value of 50 wt.%. In the same period more than 50% of the packaging units on the world market were made of polymeric materials despite the fact that polymeric materials present 17 wt.% of all packaging materials. The basic properties of polymeric materials and their environmental and economical advantages, providing them such a position among packaging m...

  20. Ultra-thin chip technology and applications

    CERN Document Server

    2010-01-01

    Ultra-thin chips are the "smart skin" of a conventional silicon chip. This book shows how very thin and flexible chips can be fabricated and used in many new applications in microelectronics, microsystems, biomedical and other fields. It provides a comprehensive reference to the fabrication technology, post processing, characterization and the applications of ultra-thin chips.

  1. Sustainable Library Development Training Package

    Science.gov (United States)

    Peace Corps, 2012

    2012-01-01

    This Sustainable Library Development Training Package supports Peace Corps' Focus In/Train Up strategy, which was implemented following the 2010 Comprehensive Agency Assessment. Sustainable Library Development is a technical training package in Peace Corps programming within the Education sector. The training package addresses the Volunteer…

  2. Nonequilibrium dynamics, Optimal Control and Nanofibers on an Atom Chip

    International Nuclear Information System (INIS)

    Full text: We present experiments on dynamical scaling of many-particle states, performed on degenerate 87Rb Bose gases in a time dependent trapping potential. A stochastic optimal control scheme has been implemented to manipulate the motional dynamics of such clouds, with prospects to engineer specific nonequilibrium states. Further, we present a novel atom - photon interface based on integrating optical nanofibers and nanofiber - cavities on an atom chip. Applications encompass light storage and nonlinear interactions between photons within the device, facilitated by the high optical densities and low temperatures of ultracold atom clouds in a chip trap, as well as the high transmission of an optical nanofiber. (author)

  3. New circuit switching techniques in on-chip networks

    OpenAIRE

    Shaoteng, Liu

    2015-01-01

    Network on Chip (NoC) is proposed as a promising technology to address the communication challenges in deep sub-micron era. NoC brings network-based communication into the on-chip environment and tackles the problems like long wire complexities, bandwidth scaling and so on. After more than a decade's evolution and development, there are many NoC architectures and solutions available. Nevertheless, NoCs can be classi_ed into two categories: packet switched NoC and circuit switched NoC. In this...

  4. Lab-on-a-Chip Pathogen Sensors for Food Safety

    Directory of Open Access Journals (Sweden)

    Bumsang Kim

    2012-08-01

    Full Text Available There have been a number of cases of foodborne illness among humans that are caused by pathogens such as Escherichia coli O157:H7, Salmonella typhimurium, etc. The current practices to detect such pathogenic agents are cell culturing, immunoassays, or polymerase chain reactions (PCRs. These methods are essentially laboratory-based methods that are not at all real-time and thus unavailable for early-monitoring of such pathogens. They are also very difficult to implement in the field. Lab-on-a-chip biosensors, however, have a strong potential to be used in the field since they can be miniaturized and automated; they are also potentially fast and very sensitive. These lab-on-a-chip biosensors can detect pathogens in farms, packaging/processing facilities, delivery/distribution systems, and at the consumer level. There are still several issues to be resolved before applying these lab-on-a-chip sensors to field applications, including the pre-treatment of a sample, proper storage of reagents, full integration into a battery-powered system, and demonstration of very high sensitivity, which are addressed in this review article. Several different types of lab-on-a-chip biosensors, including immunoassay- and PCR-based, have been developed and tested for detecting foodborne pathogens. Their assay performance, including detection limit and assay time, are also summarized. Finally, the use of optical fibers or optical waveguide is discussed as a means to improve the portability and sensitivity of lab-on-a-chip pathogen sensors.

  5. Anticounterfeit packaging technologies

    Directory of Open Access Journals (Sweden)

    Ruchir Y Shah

    2010-01-01

    Full Text Available Packaging is the coordinated system that encloses and protects the dosage form. Counterfeit drugs are the major cause of morbidity, mortality, and failure of public interest in the healthcare system. High price and well-known brands make the pharma market most vulnerable, which accounts for top priority cardiovascular, obesity, and antihyperlipidemic drugs and drugs like sildenafil. Packaging includes overt and covert technologies like barcodes, holograms, sealing tapes, and radio frequency identification devices to preserve the integrity of the pharmaceutical product. But till date all the available techniques are synthetic and although provide considerable protection against counterfeiting, have certain limitations which can be overcome by the application of natural approaches and utilization of the principles of nanotechnology.

  6. KAPPA -- Kernel Application Package

    Science.gov (United States)

    Currie, Malcolm J.; Berry, David. S.

    KAPPA is an applications package comprising about 180 general-purpose commands for image processing, data visualisation, and manipulation of the standard Starlink data format---the NDF. It is intended to work in conjunction with Starlink's various specialised packages. In addition to the NDF, KAPPA can also process data in other formats by using the `on-the-fly' conversion scheme. Many commands can process data arrays of arbitrary dimension, and others work on both spectra and images. KAPPA operates from both the UNIX C-shell and the ICL command language. This document describes how to use KAPPA and its features. There is some description of techniques too, including a section on writing scripts. This document includes several tutorials and is illustrated with numerous examples. The bulk of this document comprises detailed descriptions of each command as well as classified and alphabetical summaries.

  7. The Ettention software package.

    Science.gov (United States)

    Dahmen, Tim; Marsalek, Lukas; Marniok, Nico; Turoňová, Beata; Bogachev, Sviatoslav; Trampert, Patrick; Nickels, Stefan; Slusallek, Philipp

    2016-02-01

    We present a novel software package for the problem "reconstruction from projections" in electron microscopy. The Ettention framework consists of a set of modular building-blocks for tomographic reconstruction algorithms. The well-known block iterative reconstruction method based on Kaczmarz algorithm is implemented using these building-blocks, including adaptations specific to electron tomography. Ettention simultaneously features (1) a modular, object-oriented software design, (2) optimized access to high-performance computing (HPC) platforms such as graphic processing units (GPU) or many-core architectures like Xeon Phi, and (3) accessibility to microscopy end-users via integration in the IMOD package and eTomo user interface. We also provide developers with a clean and well-structured application programming interface (API) that allows for extending the software easily and thus makes it an ideal platform for algorithmic research while hiding most of the technical details of high-performance computing. PMID:26686659

  8. CMOS capacitive sensors for lab-on-chip applications a multidisciplinary approach

    CERN Document Server

    Ghafar-Zadeh, Ebrahim

    2010-01-01

    The main components of CMOS capacitive biosensors including sensing electrodes, bio-functionalized sensing layer, interface circuitries and microfluidic packaging are verbosely explained in chapters 2-6 after a brief introduction on CMOS based LoCs in Chapter 1. CMOS Capacitive Sensors for Lab-on-Chip Applications is written in a simple pedagogical way. It emphasises practical aspects of fully integrated CMOS biosensors rather than mathematical calculations and theoretical details. By using CMOS Capacitive Sensors for Lab-on-Chip Applications, the reader will have circuit design methodologies,

  9. Test Planning and Test Access Mechanism Design for Stacked Chips using ILP

    OpenAIRE

    Sengupta, Breeta; Larsson, Erik

    2014-01-01

    In this paper we propose a scheme for test planning and test access mechanism (TAM) design for stacked integrated circuits (SICs) that are designed in a core-based manner. Our scheme minimizes the test cost, which is given as the weighted sum of the test time and the TAM width. The test cost is evaluated for a test flow that consists of a wafer sort test of each individual chip and a package test of the complete stack of chips. We use an Integer Linear Programming (ILP) model to find the opti...

  10. Software packager user's guide

    Science.gov (United States)

    Callahan, John R.

    1995-01-01

    Software integration is a growing area of concern for many programmers and software managers because the need to build new programs quickly from existing components is greater than ever. This includes building versions of software products for multiple hardware platforms and operating systems, building programs from components written in different languages, and building systems from components that must execute on different machines in a distributed network. The goal of software integration is to make building new programs from existing components more seamless -- programmers should pay minimal attention to the underlying configuration issues involved. Libraries of reusable components and classes are important tools but only partial solutions to software development problems. Even though software components may have compatible interfaces, there may be other reasons, such as differences between execution environments, why they cannot be integrated. Often, components must be adapted or reimplemented to fit into another application because of implementation differences -- they are implemented in different programming languages, dependent on different operating system resources, or must execute on different physical machines. The software packager is a tool that allows programmers to deal with interfaces between software components and ignore complex integration details. The packager takes modular descriptions of the structure of a software system written in the package specification language and produces an integration program in the form of a makefile. If complex integration tools are needed to integrate a set of components, such as remote procedure call stubs, their use is implied by the packager automatically and stub generation tools are invoked in the corresponding makefile. The programmer deals only with the components themselves and not the details of how to build the system on any given platform.

  11. Aquaculture information package

    Energy Technology Data Exchange (ETDEWEB)

    Boyd, T.; Rafferty, K.

    1998-08-01

    This package of information is intended to provide background information to developers of geothermal aquaculture projects. The material is divided into eight sections and includes information on market and price information for typical species, aquaculture water quality issues, typical species culture information, pond heat loss calculations, an aquaculture glossary, regional and university aquaculture offices and state aquaculture permit requirements. A bibliography containing 68 references is also included.

  12. Standard integrated head package

    International Nuclear Information System (INIS)

    An integrated head package for a standard-type nuclear reactor is described which consolidates many components and subassemblies of the upper reactor structure into a single unit which may be removed from the reactor vessel in a single lift. Included among the consolidated elements are a pressure vessel head, a cooling shroud, control rod drive mechanisms, a missile shield, a lifting rig, a hoist assembly, and a cable tray assembly. (author)

  13. Materials for microfluidic chip fabrication.

    Science.gov (United States)

    Ren, Kangning; Zhou, Jianhua; Wu, Hongkai

    2013-11-19

    Through manipulating fluids using microfabricated channel and chamber structures, microfluidics is a powerful tool to realize high sensitive, high speed, high throughput, and low cost analysis. In addition, the method can establish a well-controlled microenivroment for manipulating fluids and particles. It also has rapid growing implementations in both sophisticated chemical/biological analysis and low-cost point-of-care assays. Some unique phenomena emerge at the micrometer scale. For example, reactions are completed in a shorter amount of time as the travel distances of mass and heat are relatively small; the flows are usually laminar; and the capillary effect becomes dominant owing to large surface-to-volume ratios. In the meantime, the surface properties of the device material are greatly amplified, which can lead to either unique functions or problems that we would not encounter at the macroscale. Also, each material inherently corresponds with specific microfabrication strategies and certain native properties of the device. Therefore, the material for making the device plays a dominating role in microfluidic technologies. In this Account, we address the evolution of materials used for fabricating microfluidic chips, and discuss the application-oriented pros and cons of different materials. This Account generally follows the order of the materials introduced to microfluidics. Glass and silicon, the first generation microfluidic device materials, are perfect for capillary electrophoresis and solvent-involved applications but expensive for microfabriaction. Elastomers enable low-cost rapid prototyping and high density integration of valves on chip, allowing complicated and parallel fluid manipulation and in-channel cell culture. Plastics, as competitive alternatives to elastomers, are also rapid and inexpensive to microfabricate. Their broad variety provides flexible choices for different needs. For example, some thermosets support in-situ fabrication of

  14. CRRES microelectronic test chip

    International Nuclear Information System (INIS)

    This paper reports on the JPL CRRES chip which was designed and fabricated in 1985 and included in the CRRES MEP. MOSFET Matrix results show the effect of shielding on radiation-induced MOSFET threshold voltage shifts and channel mobility degradation. Shielded (middle board) MOSFETs have a threshold-voltage damage factor that is approximately three-orders of magnitude smaller than would be estimated from Co-60 ground tests. Temperature swings as large as 23 degrees C with a 22.5 orbit periodicity affected the MOSFET data and was removed from the data in order to reveal the radiation effects. This experiment demonstrated the feasibility of characterizing MOSFETs in a matrix thus reducing the complexity and mass of the experiment

  15. Structural evaluation on the impact of a radioisotope package

    International Nuclear Information System (INIS)

    A package to transport high-level radioactive materials is required to withstand normal transport and hypothetical accident conditions pursuant to the IAEA and domestic regulations. The package should maintain the structural safety not to release radioactive material in any condition. The structural safety of the package has been evaluated by test using proto-type or scaled-down models, however, the method by analysis is gradually utilized due to recent advancement of computers and computer codes. In this paper, to evaluate the structural safety of a radioisotope package of the KAERI, the three dimensional impact analyses under 9 m free drop and 1 m puncture were performed with an explicit finite-element code, the LS-DYNA3D code. The maximum stress intensity on each part was calculated and the structural safety of the package was evaluated in accordance with the regulations. (author)

  16. Radiant heat test of Perforated Metal Air Transportable Package (PMATP).

    Energy Technology Data Exchange (ETDEWEB)

    Gronewald, Patrick James; Oneto, Robert (Weidlinger Associates, Inc., Los Altos, CA); Mould, John (Weidlinger Associates, Inc., Los Altos, CA); Pierce, Jim Dwight

    2003-08-01

    A conceptual design for a plutonium air transport package capable of surviving a 'worst case' airplane crash has been developed by Sandia National Laboratories (SNL) for the Japan Nuclear Cycle Development Institute (JNC). A full-scale prototype, designated as the Perforated Metal Air Transport Package (PMATP) was thermally tested in the SNL Radiant Heat Test Facility. This testing, conducted on an undamaged package, simulated a regulation one-hour aviation fuel pool fire test. Finite element thermal predictions compared well with the test results. The package performed as designed, with peak containment package temperatures less than 80 C after exposure to a one-hour test in a 1000 C environment.

  17. Reliability of Semiconductor Laser Packaging in Space Applications

    Science.gov (United States)

    Gontijo, Ivair; Qiu, Yueming; Shapiro, Andrew A.

    2008-01-01

    A typical set up used to perform lifetime tests of packaged, fiber pigtailed semiconductor lasers is described, as well as tests performed on a set of four pump lasers. It was found that two lasers failed after 3200, and 6100 hours under device specified bias conditions at elevated temperatures. Failure analysis of the lasers indicates imperfections and carbon contamination of the laser metallization, possibly from improperly cleaned photo resist. SEM imaging of the front facet of one of the lasers, although of poor quality due to the optical fiber charging effects, shows evidence of catastrophic damage at the facet. More stringent manufacturing controls with 100% visual inspection of laser chips are needed to prevent imperfect lasers from proceeding to packaging and ending up in space applications, where failure can result in the loss of a space flight mission.

  18. 78 FR 19007 - Certain Products Having Laminated Packaging, Laminated Packaging, and Components Thereof...

    Science.gov (United States)

    2013-03-28

    ... COMMISSION Certain Products Having Laminated Packaging, Laminated Packaging, and Components Thereof.... 1337, on behalf of Lamina Packaging Innovations LLC of Longview, Texas. An amended complaint was filed... importation of certain products having laminated packaging, laminated packaging, and components thereof...

  19. 78 FR 13083 - Products Having Laminated Packaging, Laminated Packaging, and Components Thereof; Notice of...

    Science.gov (United States)

    2013-02-26

    ... COMMISSION Products Having Laminated Packaging, Laminated Packaging, and Components Thereof; Notice of... Commission has received a complaint entitled Products Having Laminated ] Packaging, Laminated Packaging, and... filed on behalf of Lamina Packaging Innovations LLC on February 20, 2013. The complaint...

  20. Plutonium stabilization and packaging system

    Energy Technology Data Exchange (ETDEWEB)

    NONE

    1996-05-01

    This document describes the functional design of the Plutonium Stabilization and Packaging System (Pu SPS). The objective of this system is to stabilize and package plutonium metals and oxides of greater than 50% wt, as well as other selected isotopes, in accordance with the requirements of the DOE standard for safe storage of these materials for 50 years. This system will support completion of stabilization and packaging campaigns of the inventory at a number of affected sites before the year 2002. The package will be standard for all sites and will provide a minimum of two uncontaminated, organics free confinement barriers for the packaged material.

  1. Ensuring socially responsible packaging design

    DEFF Research Database (Denmark)

    Jensen, Birgitte Geert; Widding, Sofie Hartvig

    "User‐friendly Packaging" aims to create a platform for developing more user‐friendly packaging. One intended outcome of the project is a guideline that industry can use in development efforts. The project also points the way for more extended collaboration between companies and design researchers. How...... can design research help industry in packaging innovation?......Most consumers have experienced occasional problems with opening packaging. Tomato sauce from the tinned mackerel splattered all over the kitchen counter, the unrelenting pickle jar lid, and the package of sliced ham that cannot be opened without a knife or a pair of scissors. The research project...

  2. Plutonium stabilization and packaging system

    International Nuclear Information System (INIS)

    This document describes the functional design of the Plutonium Stabilization and Packaging System (Pu SPS). The objective of this system is to stabilize and package plutonium metals and oxides of greater than 50% wt, as well as other selected isotopes, in accordance with the requirements of the DOE standard for safe storage of these materials for 50 years. This system will support completion of stabilization and packaging campaigns of the inventory at a number of affected sites before the year 2002. The package will be standard for all sites and will provide a minimum of two uncontaminated, organics free confinement barriers for the packaged material

  3. Fermions and bosons on an atom chip

    Science.gov (United States)

    Extravour, Marcius H. T.

    Ultra-cold dilute gases of neutral atoms are attractive candidates for creating controlled mesoscopic quantum systems. In particular, quantum degenerate gases of bosonic and fermionic atoms can be used to model the correlated many-body behaviour of Bose and Fermi condensed matter systems, and to study matter wave interference and coherence. This thesis describes the experimental realization and manipulation of Bose-Einstein condensates (BECs) of 87Rb and degenerate Fermi gases (DFGs) of 40K using static and dynamic magnetic atom chip traps. Atom chips are versatile modern tools used to manipulate atomic gases. The chips consist of micrometre-scale conductors supported by a planar insulating substrate, and can be used to create confining potentials for neutral atoms tens or hundreds of micrometres from the chip surface. We demonstrate for the first time that a DFG can be produced via sympathetic cooling with a BEC using a simple single-vacuum-chamber apparatus. The large 40 K-87Rb collision rate afforded by the strongly confining atom chip potential permits rapid cooling of 40K to quantum degeneracy via sympathetic cooling with 87Rb. By studying 40K-87Rb cross-thermalization as a function of temperature, we observe the Ramsauer-Townsend reduction in the 40K-87Rb elastic scattering cross-section. We achieve DFG temperatures as low as T ≈ 0:1TF, and observe Fermi pressure in the time-of-flight expansion of the gas. This thesis also describes the radio-frequency (RF) manipulation of trapped atoms to create dressed state double-well potentials for BEC and DFG. We demonstrate for the first time that RF-dressed potentials are species-selective, permitting the formation of simultaneous 87Rb double-well and 40K single-well potentials using a 40K-87Rb mixture. We also develop tools to measure fluctuations of the relative atom number and relative phase of a dynamically split 87Rb BEC. In particular, we observe atom number fluctuations at the shot-noise level using time

  4. 21 CFR 355.20 - Packaging conditions.

    Science.gov (United States)

    2010-04-01

    ... (toothpastes and tooth powders) packages shall not contain more than 276 milligrams (mg) total fluorine per... packages shall not contain more than 120 mg total fluorine per package. (3) Exception. Package...

  5. Avaliação da aceitação de "chips" de mandioca Acceptance evaluation of cassava chips

    Directory of Open Access Journals (Sweden)

    Regina Kitagawa Grizotto

    2003-12-01

    Full Text Available Pré-tratamentos como o cozimento, a fermentação natural e a secagem parcial foram aplicados em raízes de mandioca, visando a obtenção de "chips" comestíveis. A avaliação sensorial foi feita com base na aceitação e aparência dos "chips" das variedades IAC Mantiqueira e IAC 576.70. Trinta consumidores potenciais do produto foram selecionados em função da disponibilidade e interesse em participar dos testes. Foi utilizada escala hedônica de 7 pontos, onde os provadores avaliaram as amostras delineadas em blocos casualizados. Os resultados obtidos mostraram que os "chips" controle e pré-cozidos foram aceitos sensorialmente, apresentado médias de 5,1 (gostei ligeiramente para IAC Mantiqueira e 6,0 (gostei moderadamente para IAC 576.70. Os "chips" pré-fermentados de ambas variedades foram rejeitados. Os termos de agrado mais comentados pelos provadores foram "sabor de mandioca", "crocância" e "textura". Os termos de desagrado mais citados incluem "textura dura", "falta sabor de mandioca" e "gosto de óleo". Os provadores consideraram adequada a aparência dos "chips" de ambas variedades, sendo ligeiramente preferida a aparência dos "chips" da IAC 576.70, com exceção dos "chips" cozidos por 8 minutos e os fermentados, rejeitados pelos consumidores. A cor amarela da polpa pode ter influenciado a aceitação da variedade IAC 576.70. A composição centesimal e o teor de fibras na mandioca in natura e, o teor de lipídeos em "chips" de mandioca, também foram apresentados.Pre-treatments such as cooking, natural fermentation and partial drying were applied to cassava roots, aimed at obtaining edible cassava chips. The sensory evaluation was based on the acceptance and appearance of the chips, using the varieties IAC Mantiqueira and IAC 576.70. Thirty potential consumers of the product were selected based on their availability and interest. A 7-point hedonic scale was used, all the judges evaluating all the samples using a randomised

  6. Effect of on-chip filter on Coulomb blockade thermometer

    International Nuclear Information System (INIS)

    Coulomb Blockade Thermometer (CBT) is a primary thermometer based on electric conductance of normal tunnel junction arrays. One limitation for CBT use at the lowest temperatures has been due to environmental noise heating. To improve on this limitation, we have done measurements on CBT sensors fabricated with different on-chip filtering structures in a dilution refrigerator with a base temperature of 10 mK. The CBT sensors were produced with a wafer scale tunnel junction process. We present how the different on-chip filtering schemes affect the limiting saturation temperatures and show that CBT sensors with proper on-chip filtering work at temperatures below 20 mK and are tolerant to noisy environment.

  7. Advanced Packaging Technology Used in Fabricating a High-Temperature Silicon Carbide Pressure Sensor

    Science.gov (United States)

    Beheim, Glenn M.

    2003-01-01

    The development of new aircraft engines requires the measurement of pressures in hot areas such as the combustor and the final stages of the compressor. The needs of the aircraft engine industry are not fully met by commercially available high-temperature pressure sensors, which are fabricated using silicon. Kulite Semiconductor Products and the NASA Glenn Research Center have been working together to develop silicon carbide (SiC) pressure sensors for use at high temperatures. At temperatures above 850 F, silicon begins to lose its nearly ideal elastic properties, so the output of a silicon pressure sensor will drift. SiC, however, maintains its nearly ideal mechanical properties to extremely high temperatures. Given a suitable sensor material, a key to the development of a practical high-temperature pressure sensor is the package. A SiC pressure sensor capable of operating at 930 F was fabricated using a newly developed package. The durability of this sensor was demonstrated in an on-engine test. The SiC pressure sensor uses a SiC diaphragm, which is fabricated using deep reactive ion etching. SiC strain gauges on the surface of the diaphragm sense the pressure difference across the diaphragm. Conventionally, the SiC chip is mounted to the package with the strain gauges outward, which exposes the sensitive metal contacts on the chip to the hostile measurement environment. In the new Kulite leadless package, the SiC chip is flipped over so that the metal contacts are protected from oxidation by a hermetic seal around the perimeter of the chip. In the leadless package, a conductive glass provides the electrical connection between the pins of the package and the chip, which eliminates the fragile gold wires used previously. The durability of the leadless SiC pressure sensor was demonstrated when two 930 F sensors were tested in the combustor of a Pratt & Whitney PW4000 series engine. Since the gas temperatures in these locations reach 1200 to 1300 F, the sensors were

  8. VLSI design of 3D display processing chip for binocular stereo displays

    Institute of Scientific and Technical Information of China (English)

    Ge Chenyang; Zheng Nanning

    2010-01-01

    In order to develop the core chip supporting binocular stereo displays for head mounted display(HMD)and glasses-TV,a very large scale integrated(VLSI)design scheme is proposed by using a pipeline architecture for 3D display processing chip(HMD100).Some key techniques including stereo display processing and high precision video scaling based bicubic interpolation,and their hardware implementations which improve the image quality are presented.The proposed HMD100 chip is verified by the field-programmable gate array(FPGA).As one of innovative and high integration SoC chips,HMD100 is designed by a digital and analog mixed circuit.It can support binocular stereo display,has better scaling effect and integration.Hence it is applicable in virtual reality(VR),3D games and other microdisplay domains.

  9. Ultra-thin silicon (UTSi) on insulator CMOS transceiver and time-division multiplexed switch chips for smart pixel integration

    Science.gov (United States)

    Zhang, Liping; Sawchuk, Alexander A.

    2001-12-01

    We describe the design, fabrication and functionality of two different 0.5 micron CMOS optoelectronic integrated circuit (OEIC) chips based on the Peregrine Semiconductor Ultra-Thin Silicon on insulator technology. The Peregrine UTSi silicon- on-sapphire (SOS) technology is a member of the silicon-on- insulator (SOI) family. The low-loss synthetic sapphire substrate is optically transparent and has good thermal conductivity and coefficient of thermal expansion properties, which meet the requirements for flip-chip bonding of VCSELs and other optoelectronic input-output components. One chip contains transceiver and network components, including four channel high-speed CMOS transceiver modules, pseudo-random bit stream (PRBS) generators, a voltage controlled oscillator (VCO) and other test circuits. The transceiver chips can operate in both self-testing mode and networking mode. An on- chip clock and true-single-phase-clock (TSPC) D-flip-flop have been designed to generate a PRBS at over 2.5 Gb/s for the high-speed transceiver arrays to operate in self-testing mode. In the networking mode, an even number of transceiver chips forms a ring network through free-space or fiber ribbon interconnections. The second chip contains four channel optical time-division multiplex (TDM) switches, optical transceiver arrays, an active pixel detector and additional test devices. The eventual applications of these chips will require monolithic OEICs with integrated optical input and output. After fabrication and testing, the CMOS transceiver array dies will be packaged with 850 nm vertical cavity surface emitting lasers (VCSELs), and metal-semiconductor- metal (MSM) or GaAs p-i-n detector die arrays to achieve high- speed optical interconnections. The hybrid technique could be either wire bonding or flip-chip bonding of the CMOS SOS smart-pixel arrays with arrays of VCSELs and photodetectors onto an optoelectronic chip carrier as a multi-chip module (MCM).

  10. S-Chip Technical Assistance

    Data.gov (United States)

    U.S. Department of Health & Human Services — The page will provide access to reports and other published products designed to assist states with complicated S-Chip technical issues. The reports and products...

  11. On-Chip Optical Squeezing

    CERN Document Server

    Dutt, Avik; Manipatruni, Sasikanth; Gaeta, Alexander L; Nussenzveig, Paulo; Lipson, Michal

    2013-01-01

    A squeezed light source, i.e. a source with ultra low noise level, below the standard quantum limit (SQL), can enable quantum enhanced sensing, spectroscopy[1, 2], metrology[3] and quantum information processing[4,5]. To date, such a non classical light source on-chip, scalable, compact and robust has not been demonstrated. Such a source could not only enable ultrasensitive measurements on chip, but also provide squeezing over high bandwidths in contrast to most sources which usually rely on large optical cavities with narrow bandwidths. Here, we report the observation of squeezed light in an on-chip monolithically integrated platform, generated in a micron-size silicon nitride oscillator[6] with GHz cavity linewidth. We show 1.7dB noise squeezing, i.e. reduction of the noise level below the standard quantum limit, of the intensity difference between two beams generated by an on-chip optical parametric oscillator.

  12. A 1,000 Frames/s Programmable Vision Chip with Variable Resolution and Row-Pixel-Mixed Parallel Image Processors

    OpenAIRE

    2009-01-01

    A programmable vision chip with variable resolution and row-pixel-mixed parallel image processors is presented. The chip consists of a CMOS sensor array, with row-parallel 6-bit Algorithmic ADCs, row-parallel gray-scale image processors, pixel-parallel SIMD Processing Element (PE) array, and instruction controller. The resolution of the image in the chip is variable: high resolution for a focused area and low resolution for general view. It implements gray-scale and binary mathematical morpho...

  13. Ten-channel InP-based large-scale photonic integrated transmitter fabricated by SAG technology

    Science.gov (United States)

    Zhang, Can; Zhu, Hongliang; Liang, Song; Cui, Xiao; Wang, Huitao; Zhao, Lingjuan; Wang, Wei

    2014-12-01

    A 10-channel InP-based large-scale photonic integrated transmitter was fabricated by selective area growth (SAG) technology combined with butt-joint regrowth (BJR) technology. The SAG technology was utilized to fabricate the electroabsorption modulated distributed feedback (DFB) laser (EML) arrays at the same time. The design of coplanar electrodes for electroabsorption modulator (EAM) was used for the flip-chip bonding package. The lasing wavelength of DFB laser could be tuned by the integrated micro-heater to match the ITU grids, which only needs one electrode pad. The average output power of each channel is 250 μW with an injection current of 200 mA. The static extinction ratios of the EAMs for 10 channels tested are ranged from 15 to 27 dB with a reverse bias of 6 V. The frequencies of 3 dB bandwidth of the chip for each channel are around 14 GHz. The novel design and simple fabrication process show its enormous potential in reducing the cost of large-scale photonic integrated circuit (LS-PIC) transmitter with high chip yields.

  14. Whole-Teflon microfluidic chips

    OpenAIRE

    Ren, Kangning; Dai, Wen; Zhou, Jianhua; Su, Jing; Wu, Hongkai

    2011-01-01

    Although microfluidics has shown exciting potential, its broad applications are significantly limited by drawbacks of the materials used to make them. In this work, we present a convenient strategy for fabricating whole-Teflon microfluidic chips with integrated valves that show outstanding inertness to various chemicals and extreme resistance against all solvents. Compared with other microfluidic materials [e.g., poly(dimethylsiloxane) (PDMS)] the whole-Teflon chip has a few more advantages, ...

  15. Hermetic glass frit packaging in air and vacuum with localized laser joining

    Science.gov (United States)

    Lorenz, N.; Millar, S.; Desmulliez, M.; Hand, D. P.

    2011-04-01

    Glass frit packaging is a simple and robust method used for hermetic sealing of micro-devices. Conventional glass frit packaging processes rely on furnace heating where the entire package is heated to elevated temperatures, hence restricting the use of temperature-sensitive materials inside the package and generating problems in multi-stage packaging processes. The use of a laser as an alternative heat source offers the possibility of highly localized heating where the heat-input can be restricted to the joining area only. In this paper the clear benefits of combining glass frit packaging and localized laser heating are demonstrated. Two novel laser-based glass frit packaging processes for sealing of leadless chip carrier (LCC) packages in both air and vacuum have been developed. Full hermetic seals according to MIL-STD-883G are achieved in high yield processes where the temperature in the centre of the device is kept at least 230 °C below the temperature in the joining region.

  16. Hermetic glass frit packaging in air and vacuum with localized laser joining

    International Nuclear Information System (INIS)

    Glass frit packaging is a simple and robust method used for hermetic sealing of micro-devices. Conventional glass frit packaging processes rely on furnace heating where the entire package is heated to elevated temperatures, hence restricting the use of temperature-sensitive materials inside the package and generating problems in multi-stage packaging processes. The use of a laser as an alternative heat source offers the possibility of highly localized heating where the heat-input can be restricted to the joining area only. In this paper the clear benefits of combining glass frit packaging and localized laser heating are demonstrated. Two novel laser-based glass frit packaging processes for sealing of leadless chip carrier (LCC) packages in both air and vacuum have been developed. Full hermetic seals according to MIL-STD-883G are achieved in high yield processes where the temperature in the centre of the device is kept at least 230 °C below the temperature in the joining region.

  17. Packaging - Materials review

    Energy Technology Data Exchange (ETDEWEB)

    Herrmann, Matthias [Hoppecke Advanced Battery Technology GmbH, 08056 Zwickau (Germany)

    2014-06-16

    Nowadays, a large number of different electrochemical energy storage systems are known. In the last two decades the development was strongly driven by a continuously growing market of portable electronic devices (e.g. cellular phones, lap top computers, camcorders, cameras, tools). Current intensive efforts are under way to develop systems for automotive industry within the framework of electrically propelled mobility (e.g. hybrid electric vehicles, plug-in hybrid electric vehicles, full electric vehicles) and also for the energy storage market (e.g. electrical grid stability, renewable energies). Besides the different systems (cell chemistries), electrochemical cells and batteries were developed and are offered in many shapes, sizes and designs, in order to meet performance and design requirements of the widespread applications. Proper packaging is thereby one important technological step for designing optimum, reliable and safe batteries for operation. In this contribution, current packaging approaches of cells and batteries together with the corresponding materials are discussed. The focus is laid on rechargeable systems for industrial applications (i.e. alkaline systems, lithium-ion, lead-acid). In principle, four different cell types (shapes) can be identified - button, cylindrical, prismatic and pouch. Cell size can be either in accordance with international (e.g. International Electrotechnical Commission, IEC) or other standards or can meet application-specific dimensions. Since cell housing or container, terminals and, if necessary, safety installations as inactive (non-reactive) materials reduce energy density of the battery, the development of low-weight packages is a challenging task. In addition to that, other requirements have to be fulfilled: mechanical stability and durability, sealing (e.g. high permeation barrier against humidity for lithium-ion technology), high packing efficiency, possible installation of safety devices (current interrupt device

  18. Packaging - Materials review

    International Nuclear Information System (INIS)

    Nowadays, a large number of different electrochemical energy storage systems are known. In the last two decades the development was strongly driven by a continuously growing market of portable electronic devices (e.g. cellular phones, lap top computers, camcorders, cameras, tools). Current intensive efforts are under way to develop systems for automotive industry within the framework of electrically propelled mobility (e.g. hybrid electric vehicles, plug-in hybrid electric vehicles, full electric vehicles) and also for the energy storage market (e.g. electrical grid stability, renewable energies). Besides the different systems (cell chemistries), electrochemical cells and batteries were developed and are offered in many shapes, sizes and designs, in order to meet performance and design requirements of the widespread applications. Proper packaging is thereby one important technological step for designing optimum, reliable and safe batteries for operation. In this contribution, current packaging approaches of cells and batteries together with the corresponding materials are discussed. The focus is laid on rechargeable systems for industrial applications (i.e. alkaline systems, lithium-ion, lead-acid). In principle, four different cell types (shapes) can be identified - button, cylindrical, prismatic and pouch. Cell size can be either in accordance with international (e.g. International Electrotechnical Commission, IEC) or other standards or can meet application-specific dimensions. Since cell housing or container, terminals and, if necessary, safety installations as inactive (non-reactive) materials reduce energy density of the battery, the development of low-weight packages is a challenging task. In addition to that, other requirements have to be fulfilled: mechanical stability and durability, sealing (e.g. high permeation barrier against humidity for lithium-ion technology), high packing efficiency, possible installation of safety devices (current interrupt device

  19. Packaging - Materials review

    Science.gov (United States)

    Herrmann, Matthias

    2014-06-01

    Nowadays, a large number of different electrochemical energy storage systems are known. In the last two decades the development was strongly driven by a continuously growing market of portable electronic devices (e.g. cellular phones, lap top computers, camcorders, cameras, tools). Current intensive efforts are under way to develop systems for automotive industry within the framework of electrically propelled mobility (e.g. hybrid electric vehicles, plug-in hybrid electric vehicles, full electric vehicles) and also for the energy storage market (e.g. electrical grid stability, renewable energies). Besides the different systems (cell chemistries), electrochemical cells and batteries were developed and are offered in many shapes, sizes and designs, in order to meet performance and design requirements of the widespread applications. Proper packaging is thereby one important technological step for designing optimum, reliable and safe batteries for operation. In this contribution, current packaging approaches of cells and batteries together with the corresponding materials are discussed. The focus is laid on rechargeable systems for industrial applications (i.e. alkaline systems, lithium-ion, lead-acid). In principle, four different cell types (shapes) can be identified - button, cylindrical, prismatic and pouch. Cell size can be either in accordance with international (e.g. International Electrotechnical Commission, IEC) or other standards or can meet application-specific dimensions. Since cell housing or container, terminals and, if necessary, safety installations as inactive (non-reactive) materials reduce energy density of the battery, the development of low-weight packages is a challenging task. In addition to that, other requirements have to be fulfilled: mechanical stability and durability, sealing (e.g. high permeation barrier against humidity for lithium-ion technology), high packing efficiency, possible installation of safety devices (current interrupt device

  20. The PIDCalib package

    CERN Document Server

    Anderlini, Lucio; Jones, Christopher Rob; Malde, Sneha Sirirshkumar; Muller, Dominik; Ogilvy, Stephen; Otalora Goicochea, Juan Martin; Pearce, Alex; Polyakov, Ivan; Qian, Wenbin; Sciascia, Barbara; Vazquez Gomez, Ricardo; Zhang, Yanxi

    2016-01-01

    The PIDCalib package is a tool, widely used within the LHCb Collaboration, providing access to the calibration samples of electrons, muons, pions, kaons and protons. This note covers both theoretical aspects related to the measurement of the efficiency of particle identification requirements, and more technical issues such as the selection of the calibration samples, the background subtraction procedure, and the storage of the data sets in the new data-processing scheme adopted by the LHCb experiment during the second run of the LHC.

  1. The Kull IMC package

    International Nuclear Information System (INIS)

    We describe the Kull IMC package, and Implicit Monte Carlo Program written for use in A and X division radiation hydro codes. The Kull IMC has been extensively tested. Written in C++ and using genericity via the template feature to allow easy integration into different codes, the Kull IMC currently runs coupled radiation hydrodynamic problems in 2 different 3D codes. A stand-alone version also exists, which has been parallelized with mesh replication. This version has been run on up to 384 processors on ASCI Blue Pacific

  2. Rock mechanics data package

    International Nuclear Information System (INIS)

    This data package provides a summary of available laboratory and in situ stress field test results from site characterization investigations by the Basalt Waste Isolation Project Modeling and Analysis Group. The objective is to furnish rock mechanics information for use by Rockwell Hanford Operations and their subcontractors in performance assessment and engineering studies. This release includes Reference Repository Location (RRL) site specific laboratory and field test data from boreholes RRL-2, RRL-6, and RRL-14 as well as previous Hanford wide data available as of April, 1985. 25 refs., 9 figs., 16 tabs

  3. Nuclear application software package

    International Nuclear Information System (INIS)

    The Nuclear Application Software Package generates a full-core distribution and power peaking analysis every six minutes during reactor operation. Information for these calculations is provided by a set of fixed incore, self-powered rhodium detectors whose signals are monitored and averaged to obtain input for the software. Following the calculation of a power distribution and its normalization to a core heat balance, the maximum power peaks in the core and minimum DNBR are calculated. Additional routines are provided to calculate the core reactivity, future xenon concentrations, critical rod positions, and assembly isotopic concentrations

  4. The PIDCalib package

    CERN Document Server

    Anderlini, Lucio; Jones, Christopher Rob; Malde, Sneha Sirirshkumar; Muller, Dominik; Ogilvy, Stephen; Otalora Goicochea, Juan Martin; Pearce, Alex; Polyakov, Ivan; Qian, Wenbin; Sciascia, Barbara; Vazquez Gomez, Ricardo; Zhang, Yanxi

    2016-01-01

    The PIDCalib package is a tool, widely used within the LHCb Collaboration, which provides access to the calibration samples of electrons, muons, pions, kaons and protons. This note covers both theoretical aspects related to the measurement of the efficiency of particle identification requirements, and more technical issues such as the selection of the calibration samples, the background subtraction procedure, and the storage of the data sets in the new data-processing scheme adopted by the LHCb experiment during the second run of the LHC.

  5. Packaging-radiation disinfestation relationships

    International Nuclear Information System (INIS)

    Foods that are susceptible to insect infestation can be irradiated to destroy the infestation; however, the food must be kept essentially insect-free until consumed, or it must be disinfested again, perhaps repeatedly. Insect-resistant packages can be used to prevent reinfestation, but there are certain requirements that must be fulfilled before a package can be made insect resistant. These include the use of insect-light construction and packaging materials that resist boring insects. The relative insect resistance of various packages and packaging materials is discussed, as are behavior traits such as egressive boring that enables insects to escape from packages and the ability of insects to climb on various packaging materials. Some successful and unsuccessful attempts to make various types of packages insect resistant are discussed, as are factors that must be considered in the selection or development of insect-resistant packages for radiation disinfested foods. The latter factors include biological and physical environments, length of storage periods, stresses on packages during shipment, types of storage facilities, governmental regulations, health requirements, and others

  6. Package-on-Package (PoP) for Advanced PCB Manufacturing Process%用于先进PCB制造工艺的叠层封装

    Institute of Scientific and Technical Information of China (English)

    Joseph Y. Lee; Jinyong Ahn; JeGwang Yoo; Joonsung Kim; Hwa-Sun Park; Shuichi Okabe

    2007-01-01

    In the 1990's, both BGA (Ball Grid Array) and CSP (Chip Size Package) are entering their end in the front-end packaging materials and process technology. Both BGA and CSP like SMD (Surface Mount Device) from the 1980's and THD (Through-Hole mount Device) from the 1970's are reaching its own impasse in terms of maximizing its electrical, mechanical, and thermal performances, size,weight, and reliability. Now, 3D packages are the next phase for its future use in advanced PCB manufacturing process. They can be classified into wafer level, chip level, and package level stacking. So,package-on-package (PoP), a type of 3D package level stacking, is to be discussed in this paper [15].%在20世纪90年代,球栅阵列封装(BGA)和芯片尺寸封装(CSP)在封装材料和加工工艺方面达到了极限.这2种技术如同20世纪80年代的表面安装器件(SMD)和70年代通孔安装器件(THD)一样,在电学、机械、热性能、尺寸、质量和可靠性方面达到最大值.目前,三维封装正在成为用于未来采用的先进印制板(PCB)制造工艺的下一个阶段.它们可以分为圆片级封装、芯片级封装、和封装面.叠层封装(PoP)是一种封装面叠层封装类型的三维封装技术[15].

  7. Safety Analysis Report for packaging (onsite) steel waste package

    Energy Technology Data Exchange (ETDEWEB)

    BOEHNKE, W.M.

    2000-07-13

    The steel waste package is used primarily for the shipment of remote-handled radioactive waste from the 324 Building to the 200 Area for interim storage. The steel waste package is authorized for shipment of transuranic isotopes. The maximum allowable radioactive material that is authorized is 500,000 Ci. This exceeds the highway route controlled quantity (3,000 A{sub 2}s) and is a type B packaging.

  8. Safety Analysis Report for packaging (onsite) steel waste package

    International Nuclear Information System (INIS)

    The steel waste package is used primarily for the shipment of remote-handled radioactive waste from the 324 Building to the 200 Area for interim storage. The steel waste package is authorized for shipment of transuranic isotopes. The maximum allowable radioactive material that is authorized is 500,000 Ci. This exceeds the highway route controlled quantity (3,000 A2s) and is a type B packaging

  9. The Package Blueprint: visually analyzing and quantifying package dependencies

    OpenAIRE

    Abdeen, Hani; Ducasse, Stéphane; Pollet, Damien; Alloui, Ilham; Falleri, Jean-Rémy

    2014-01-01

    Large object-oriented applications are structured over many packages. Packages are important but complex structural entities that are difficult to understand since they act as containers of classes, which can have many dependencies with other classes spread over multiple packages. However to be able to take decisions (e.g., refactoring and/or assessment decisions), maintainers face the challenges of managing (sorting, grouping) the massive amount of dependencies between classes spread over mu...

  10. Evaluating laser-driven Bremsstrahlung radiation sources for imaging and analysis of nuclear waste packages.

    Science.gov (United States)

    Jones, Christopher P; Brenner, Ceri M; Stitt, Camilla A; Armstrong, Chris; Rusby, Dean R; Mirfayzi, Seyed R; Wilson, Lucy A; Alejo, Aarón; Ahmed, Hamad; Allott, Ric; Butler, Nicholas M H; Clarke, Robert J; Haddock, David; Hernandez-Gomez, Cristina; Higginson, Adam; Murphy, Christopher; Notley, Margaret; Paraskevoulakos, Charilaos; Jowsey, John; McKenna, Paul; Neely, David; Kar, Satya; Scott, Thomas B

    2016-11-15

    A small scale sample nuclear waste package, consisting of a 28mm diameter uranium penny encased in grout, was imaged by absorption contrast radiography using a single pulse exposure from an X-ray source driven by a high-power laser. The Vulcan laser was used to deliver a focused pulse of photons to a tantalum foil, in order to generate a bright burst of highly penetrating X-rays (with energy >500keV), with a source size of chips. The uranium penny was clearly resolved to sub-mm accuracy over a 30cm(2) scan area from a single shot acquisition. In addition, neutron generation was demonstrated in situ with the X-ray beam, with a single shot, thus demonstrating the potential for multi-modal criticality testing of waste materials. This feasibility study successfully demonstrated non-destructive radiography of encapsulated, high density, nuclear material. With recent developments of high-power laser systems, to 10Hz operation, a laser-driven multi-modal beamline for waste monitoring applications is envisioned. PMID:27484945

  11. 3D stacked chips from emerging processes to heterogeneous systems

    CERN Document Server

    Fettweis, Gerhard

    2016-01-01

    This book explains for readers how 3D chip stacks promise to increase the level of on-chip integration, and to design new heterogeneous semiconductor devices that combine chips of different integration technologies (incl. sensors) in a single package of the smallest possible size.  The authors focus on heterogeneous 3D integration, addressing some of the most important challenges in this emerging technology, including contactless, optics-based, and carbon-nanotube-based 3D integration, as well as signal-integrity and thermal management issues in copper-based 3D integration. Coverage also includes the 3D heterogeneous integration of power sources, photonic devices, and non-volatile memories based on new materials systems.   •Provides single-source reference to the latest research in 3D optoelectronic integration: process, devices, and systems; •Explains the use of wireless 3D integration to improve 3D IC reliability and yield; •Describes techniques for monitoring and mitigating thermal behavior in 3D I...

  12. HPLOT: the graphics interface package for the HBOOK histogramming package

    International Nuclear Information System (INIS)

    The subroutine package HPLOT described in this report, enables the CERN histogramming package HBOOK to produce high-quality pictures by means of high-resolution devices such as plotters. HPLOT can be implemented on any scientific computing system with a Fortran IV compiler and can be interfaced with any graphics package; spectral routines in addition to the basic ones enable users to embellish their histograms. Examples are also given of the use of HPLOT as a graphics package for plotting simple pictures without histograms. (Auth.)

  13. A regulator's perspective on physical testing for type B packages

    International Nuclear Information System (INIS)

    The U.S. Nuclear Regulatory Commission has a great deal of experience certifying Type B transport packages as complying with the regulations in 10 CFR Part 71. With this experience base, supporting risk studies, and with an exceptional historical safety record for transport, we are very confident in both the current regulations and the methods we use to review and certify transportation packages. Nevertheless, we have a responsibility to remain vigilant and review our regulations and implementing practices with a view towards continuous improvement. NRC regulations permit certification through testing, analyses, comparison to similar approved designs, or combinations of these methods. Testing can be further broken into scale models, components, simple models, or full-scale models. NRC does not require full-scale testing for certification of any package; however, many applicants for package certification have conducted a physical testing program to demonstrate that the package design meets the hypothetical accident conditions. The plans for a repository at Yucca Mountain have raised significant interest in the United States of America in transportation of spent fuel, and created a broad stakeholder and public interest in transportation package testing. As an expected large increase in the number of spent fuel transports nears, this interest will likely grow. The technical and regulatory reasons for, or for not, performing tests need to be well understood and communicated to all stakeholders

  14. CH Packaging Operations Manual

    International Nuclear Information System (INIS)

    This document provides the user with instructions for assembling a payload. All the steps in Subsections 1.2, Preparing 55-Gallon Drum Payload Assembly; 1.3, Preparing 'Short' 85-Gallon Drum Payload Assembly (TRUPACT-II and HalfPACT); 1.4, Preparing 'Tall' 85-gallon Drum Payload Assembly (HalfPACT only); 1.5, Preparing 100-Gallon Drum Payload Assembly; 1.6, Preparing SWB Payload Assembly; and 1.7, Preparing TDOP Payload Assembly, must be completed, but may be performed in any order as long as radiological control steps are not bypassed. Transport trailer operations, package loading and unloading from transport trailers, hoisting and rigging activities such as ACGLF operations, equipment checkout and shutdown, and component inspection activities must be performed, but may be performed in any order and in parallel with other activities as long as radiological control steps are not bypassed. Steps involving OCA/ICV lid removal/installation and payload removal/loading may be performed in parallel if there are multiple operators working on the same packaging. Steps involving removal/installation of OCV/ICV upper and lower main O-rings must be performed in sequence.

  15. CH Packaging Operations Manual

    International Nuclear Information System (INIS)

    This document provides the user with instructions for assembling a payload. All the steps in Subsections 1.2, Preparing 55-Gallon Drum Payload Assembly; 1.3, Preparing 'Short' 85-Gallon Drum Payload Assembly (TRUPACT-II and HalfPACT); 1.4, Preparing 'Tall' 85-Gallon Drum Payload Assembly (HalfPACT only); 1.5, Preparing 100-Gallon Drum Payload Assembly; 1.6, Preparing Shielded Container Payload Assembly; 1.7, Preparing SWB Payload Assembly; and 1.8, Preparing TDOP Payload Assembly, must be completed, but may be performed in any order as long as radiological control steps are not bypassed. Transport trailer operations, package loading and unloading from transport trailers, hoisting and rigging activities such as ACGLF operations, equipment checkout and shutdown, and component inspection activities must be performed, but may be performed in any order and in parallel with other activities as long as radiological control steps are not bypassed. Steps involving OCA/ICV lid removal/installation and payload removal/loading may be performed in parallel if there are multiple operators working on the same packaging. Steps involving removal/installation of OCV/ICV upper and lower main O-rings must be performed in sequence, except as noted.

  16. Japan's electronic packaging technologies

    Science.gov (United States)

    Tummala, Rao R.; Pecht, Michael

    1995-01-01

    The JTEC panel found Japan to have significant leadership over the United States in the strategic area of electronic packaging. Many technologies and products once considered the 'heart and soul' of U.S. industry have been lost over the past decades to Japan and other Asian countries. The loss of consumer electronics technologies and products is the most notable of these losses, because electronics is the United States' largest employment sector and is critical for growth businesses in consumer products, computers, automobiles, aerospace, and telecommunications. In the past there was a distinction between consumer and industrial product technologies. While Japan concentrated on the consumer market, the United States dominated the industrial sector. No such distinction is anticipated in the future; the consumer-oriented technologies Japan has dominated are expected to characterize both domains. The future of U.S. competitiveness will, therefore, depend on the ability of the United States to rebuild its technological capabilities in the area of portable electronic packaging.

  17. Tamper indicating packaging

    International Nuclear Information System (INIS)

    Protecting sensitive items from undetected tampering in an unattended environment is crucial to the success of non-proliferation efforts relying on the verification of critical activities. Tamper Indicating Packaging (TIP) technologies are applied to containers, packages, and equipment that require an indication of a tamper attempt. Examples include: the transportation and storage of nuclear material, the operation and shipment of surveillance equipment and monitoring sensors, and the retail storage of medicine and food products. The spectrum of adversarial tampering ranges from attempted concealment of a pin-hole sized penetration to the complete container replacement, which would involve counterfeiting efforts of various degrees. Sandia National Laboratories (SNL) has developed a technology base for advanced TIP materials, sensors, designs, and processes which can be adapted to various future monitoring systems. The purpose of this technology base is to investigate potential new technologies, and to perform basic research of advanced technologies. This paper will describe the theory of TIP technologies and recent investigations of TIP technologies at SNL

  18. Automation Using Robotic Arm in Rotor Packaging

    Directory of Open Access Journals (Sweden)

    GOPU G.

    2013-03-01

    Full Text Available Till date automation in small and medium scale industries has not enjoyed the same rate of growth as in other information technology sectors, lagging significantly behind automation in large batch production .The use of LabVIEW interfaced with micro-controller in controlling a robotic arm is a latest technique which is being implemented in this project. In medium scale industries packaging of rotors is done manually. This Process is time consuming and also requires manpower. Through this project our efforts are to increase the efficiency by building an automated system which would employ and also reduces manpower. It involves the use of a robotic arm which would identify the rotors positioning, pick it and then place it in the desired location. With the use of this system the process of packaging can be done effectively without any manpower and also does not require constant monitoring and guidance. The DC gear motors are used in actuating the robotic arm. Electromagnetic gripper is employed at the end of the arm which picks and places the helical rotor of weight 1.5 kg in the desired position for packaging and this mechanism is automated and controlled using LabVIEW. The complete set up is compact and versatile.

  19. Development of an AOI system for chips with a hole on backside based on a frame imager

    Science.gov (United States)

    Chen, Ming-Fu; Chou, Chih-Chung; Lien, Chun-Chien; Weng, Rui-Cian

    2016-01-01

    Defects exist for a few of IC chips during fabrication and packaging. The cost for follow-up processes can be reduced if chips with defect size of impacting chip quality can be inspected and removed during the earlier sorting process. Products will be more cost-effective and competitive. According to the inspecting requirements for microphone chips, developed AOI system has to detect the boundary flaws and hole-inside defects with size of greater than criteria from chips backside. Both the length and width of chip size are less than 5 mm and there's depth difference between the surface of chip backside and the hole-inside membrance. Thus image acquisition device is designed and implemented by an area scan imager and a telecentric lenses with a coaxial LED lighting module. Therefore we can ignore the image radiometric and geometric calibration, and keep off the shadow inside the rim of hole. An algorithm to detect defects and derive their size based on the edge pixels statistic distribution and binary chip edge image is selected. Developed AOI system then can meet the requirements of real-time defect inspection with high accuracy and performance. Frame opto-mechanical device has the spatial resolution of 5μm and FOV of 6.4 x 5.1 mm. And defect inspection can be completed within 150 ms for the chip size of 2.5 x 3.0 mm. The processes of image acquisition and defect inspection can be accomplished during the chip sorting process to satisfy the real-time online inspection. Inspected chips are placed in GO/NG trays in real-time according to their quality. From the verification results compared with the ones by microscope, the inspection accuracy is better than system requirements. The over kill rate is less than 0.3% and 3% for chip boundary flaws and hole-inside defects respectively. But it still can't be inspected correctly for the hole-inside defects of only one membrance breakage. In the future, we will improve the illumination and detecting algorithm to solve this

  20. Heat Transfer Characteristics in High Power LED Packaging

    Directory of Open Access Journals (Sweden)

    Chi-Hung Chung

    2014-03-01

    Full Text Available This study uses the T3Ster transient thermal resistance measuring device to investigate the effects to heat transfer performances from different LED crystal grains, packaging methods and heat-sink substrates through the experimental method. The experimental parameters are six different types of LED modules that are made alternatively with the crystal grain structure, the die attach method and the carrying substrate. The crystal grain structure includes the lateral type, flip chip type and vertical type. The die attach method includes silver paste and the eutectic structure. The carrying substrates are aluminum oxide (Alumina and aluminum nitride (AIN ceramic substrates and metal core PCB (MCPCB. The experimental results show that, under the conditions of the same crystal grain and die attach method, the thermal resistance values for the AIN substrate and the Alumina substrate are 2.1K/W and 5.1K/W, respectively and the total thermal resistance values are 7.3K/W and 10.8K/W. Compared to the Alumina substrate, the AIN substrate can effectively lower the total thermal resistance value by 32.4%. This is because the heat transfer coefficient of the AIN substrate is higher than that of the Alumina substrate, thus effectively increasing its thermal conductivity. In addition, under the conditions of the same crystal grain and the same substrate, the packaging methods are using silver paste and the eutectic structure for die attach. Their thermal resistance values are 5.7K/W and 2.7K/W, respectively, with a variance of 3K/W. Comparisons of the crystal grain structure show that the thermal resistance for the flip chip type is lower than that of the traditional lateral type by 0.9K/W. This is because the light emitting layer of the flip chip crystal grain is closer to the heat-sink substrate, shortening the heat dissipation route, and thus lowering the thermal resistance value. For the total thermal resistance, the crystal grain structure has a lesser

  1. Design and fabrication of a foldable 3D silicon based package for solid state lighting applications

    International Nuclear Information System (INIS)

    Miniaturization of solid state lighting (SSL) luminaires as well as reduction of packaging and assembly costs are of prime interest for the SSL lighting industry. A novel silicon based LED package for lighting applications is presented in this paper. The proposed design consists of 5 rigid Si tiles connected by flexible polyimide hinges with embedded interconnects (ICs). Electrical, optical and thermal characteristics were taken into consideration during design. The fabrication process involved polyimide (PI) application and patterning, aluminium interconnect integration in the flexible hinge, LED reflector cavity formation and metalization followed by through wafer DRIE etching for chip formation and release. A method to connect chip front to backside without TSVs was also integrated into the process. Post-fabrication wafer level assembly included LED mounting and wirebond, phosphor-based colour conversion and silicone encapsulation. The package formation was finalized by vacuum assisted wrapping around an assembly structure to form a 3D geometry, which is beneficial for omnidirectional lighting. Bending tests were performed on the flexible ICs and optical performance at different temperatures was evaluated. It is suggested that 3D packages can be expanded to platforms for miniaturized luminaire applications by combining monolithic silicon integration and system-in-package (SiP) technologies. (paper)

  2. CMOS On-Chip Optoelectronic Neural Interface Device with Integrated Light Source for Optogenetics

    International Nuclear Information System (INIS)

    A novel optoelectronic neural interface device is proposed for target applications in optogenetics for neural science. The device consists of a light emitting diode (LED) array implemented on a CMOS image sensor for on-chip local light stimulation. In this study, we designed a suitable CMOS image sensor equipped with on-chip electrodes to drive the LEDs, and developed a device structure and packaging process for LED integration. The prototype device produced an illumination intensity of approximately 1 mW with a driving current of 2.0 mA, which is expected to be sufficient to activate channelrhodopsin (ChR2). We also demonstrated the functions of light stimulation and on-chip imaging using a brain slice from a mouse as a target sample.

  3. Performance of High-Speed PWM Control Chips at Cryogenic Temperatures

    Science.gov (United States)

    Elbuluk, Malik E.; Gerber, Scott; Hammoud, Ahmad; Patterson, Richard; Overton, Eric

    2001-01-01

    The operation of power electronic systems at cryogenic temperatures is anticipated in many NASA space missions such as planetary exploration and deep space probes. In addition to surviving the space hostile environment, electronics capable of low temperature operation would contribute to improving circuit performance, increasing system efficiency, and reducing development and launch costs. As part of the NASA Glenn Low Temperature Electronics Program, several commercial high-speed Pulse Width Modulation (PWM) chips have been characterized in terms of their performance as a function of temperature in the range of 25 to -196 C (liquid nitrogen). These chips ranged in their electrical characteristics, modes of control, packaging options, and applications. The experimental procedures along with the experimental data obtained on the investigated chips are presented and discussed.

  4. Development and application of compact models of packages based on DELPHI methodology

    CERN Document Server

    Parry, J; Shidore, S

    1997-01-01

    The accurate prediction of the temperatures of critical electronic parts at the package- board- and system-level is seriously hampered by the lack of reliable, standardised input data for the characterisation of the thermal $9 behaviour of these parts. The recently completed collaborative European project, DELPHI has been concerned with the creation and experimental validation of thermal models (both detailed and compact) of a range of electronic parts, $9 including mono-chip packages. This paper demonstrates the reliable performance of thermal compact models in a range of applications, by comparison with the detailed models from which they were derived. (31 refs).

  5. IN-PACKAGE CHEMISTRY ABSTRACTION

    Energy Technology Data Exchange (ETDEWEB)

    E. Thomas

    2005-07-14

    This report was developed in accordance with the requirements in ''Technical Work Plan for Postclosure Waste Form Modeling'' (BSC 2005 [DIRS 173246]). The purpose of the in-package chemistry model is to predict the bulk chemistry inside of a breached waste package and to provide simplified expressions of that chemistry as a function of time after breach to Total Systems Performance Assessment for the License Application (TSPA-LA). The scope of this report is to describe the development and validation of the in-package chemistry model. The in-package model is a combination of two models, a batch reactor model, which uses the EQ3/6 geochemistry-modeling tool, and a surface complexation model, which is applied to the results of the batch reactor model. The batch reactor model considers chemical interactions of water with the waste package materials, and the waste form for commercial spent nuclear fuel (CSNF) waste packages and codisposed (CDSP) waste packages containing high-level waste glass (HLWG) and DOE spent fuel. The surface complexation model includes the impact of fluid-surface interactions (i.e., surface complexation) on the resulting fluid composition. The model examines two types of water influx: (1) the condensation of water vapor diffusing into the waste package, and (2) seepage water entering the waste package as a liquid from the drift. (1) Vapor-Influx Case: The condensation of vapor onto the waste package internals is simulated as pure H{sub 2}O and enters at a rate determined by the water vapor pressure for representative temperature and relative humidity conditions. (2) Liquid-Influx Case: The water entering a waste package from the drift is simulated as typical groundwater and enters at a rate determined by the amount of seepage available to flow through openings in a breached waste package.

  6. Packaging investigation of optoelectronic devices

    Science.gov (United States)

    Zhike, Zhang; Yu, Liu; Jianguo, Liu; Ninghua, Zhu

    2015-10-01

    Compared with microelectronic packaging, optoelectronic packaging as a new packaging type has been developed rapidly and it will play an essential role in optical communication. In this paper, we try to summarize the development history, research status, technology issues and future prospects, and hope to provide a meaningful reference. Project supported by the National High Technology Research and Development Program of China (Nos. 2013AA014201, 2013AA014203) and the National Natural Science Foundation of China (Nos. 61177080, 61335004, 61275031).

  7. Creating R Packages: A Tutorial

    OpenAIRE

    Leisch, Friedrich

    2008-01-01

    This tutorial gives a practical introduction to creating R packages. We discuss how object oriented programming and S formulas can be used to give R code the usual look and feel, how to start a package from a collection of R functions, and how to test the code once the package has been created. As running example we use functions for standard linear regression analysis which are developed from scratch.

  8. K east encapsulation packager modifications

    International Nuclear Information System (INIS)

    This Supporting Document analyzes a proposal for reducing the under-packager volume to decrease the amount of fissile material that could accumulate there. The analysis shows that restricting the under packager volume to no more than 4080 in3 will assure that if accumulated fissile material beneath the packager is added to the worst-case mass of fissile material in the discharge chute, a keff of 0.98 will not be exceeded

  9. Laser Sealed Packaging for Microsystems

    OpenAIRE

    Seigneur, Frank; JACOT, Jacques

    2006-01-01

    Packaging is the last process of microsystem manufacturing. There are mainly two kinds of packages: plastic or metallic. The two main components of the package (base and cover) may either be glued or soldered. Each of these techniques has its advantages and drawbacks, and the choice should be driven by the functionality of the microsystem. The advantage of gluing is that it is quite an easy production process. The drawback is that glue, like all polymers, is not hermetic on the long te...

  10. IN-PACKAGE CHEMISTRY ABSTRACTION

    International Nuclear Information System (INIS)

    This report was developed in accordance with the requirements in ''Technical Work Plan for Postclosure Waste Form Modeling'' (BSC 2005 [DIRS 173246]). The purpose of the in-package chemistry model is to predict the bulk chemistry inside of a breached waste package and to provide simplified expressions of that chemistry as a function of time after breach to Total Systems Performance Assessment for the License Application (TSPA-LA). The scope of this report is to describe the development and validation of the in-package chemistry model. The in-package model is a combination of two models, a batch reactor model, which uses the EQ3/6 geochemistry-modeling tool, and a surface complexation model, which is applied to the results of the batch reactor model. The batch reactor model considers chemical interactions of water with the waste package materials, and the waste form for commercial spent nuclear fuel (CSNF) waste packages and codisposed (CDSP) waste packages containing high-level waste glass (HLWG) and DOE spent fuel. The surface complexation model includes the impact of fluid-surface interactions (i.e., surface complexation) on the resulting fluid composition. The model examines two types of water influx: (1) the condensation of water vapor diffusing into the waste package, and (2) seepage water entering the waste package as a liquid from the drift. (1) Vapor-Influx Case: The condensation of vapor onto the waste package internals is simulated as pure H2O and enters at a rate determined by the water vapor pressure for representative temperature and relative humidity conditions. (2) Liquid-Influx Case: The water entering a waste package from the drift is simulated as typical groundwater and enters at a rate determined by the amount of seepage available to flow through openings in a breached waste package

  11. The design, construction and testing of packaging

    International Nuclear Information System (INIS)

    Essentially uniform regulations, based on the IAEA Regulations for the Safe Transport of Radioactive Materials, have been adopted on a world-wide basis with the aim of ensuring safety in the transport of radioactive and fissile substances by road, rail, sea and air. The application of these regulations over a period of almost 20 years has resulted in practically complete safety in the sense that there has been no evidence of death or injury that could be attributed to the special properties of the material even when consignments were involved in serious accidents. In the regulations, reliance is placed, to the greatest extent possible, on the packaging to provide adequate shielding and containment of the contents under both normal transport and accident conditions. The Agency organized an international seminar in 1971 to consider the performance tests that have to be applied to packaging to demonstrate compliance with the regulatory requirements. The general conclusion was that the testing programme specified in the regulations was adequate for the near future, but that further consideration should be given to assessing the risks presented by the increasing volume of transport. The second international seminar, which is the subject of this report, dealt with all aspects of the design, construction and testing of packaging for the transport both of relatively small quantities of radioactive substances, which are being used to an ever increasing extent for medical and research purposes, and of the much larger quantities arising in various stages of the nuclear fuel cycle. The programme covered the general requirements for packaging; risk assessment for the transport of various radioactive and fissile substances, including plutonium; specific features of the design and construction of packaging; quality assurance; damage simulation tests, including calculational methods and scale-model testing; tests for the retention of shielding and containment after damage; and the

  12. Advanced copper/low-k IC devices: Packaging process development and materials integrtion

    Science.gov (United States)

    Chungpaiboonpatana, Surasit

    Cu/low-k technology provides a number of key advantages including higher interconnect density, improved electrical performance, enhanced thermal performance, and reduced cost. Nevertheless, Cu/low-k IC technology poses many challenges to the packaging industry today. Specifically, low-k dielectric is much more fragile mechanically and copper surfaces are readily oxidized thereby weakening their adhesion to the ILD/metallization layers. The purpose of the study is to provide integrated and reliable materials and process solutions for the packaging of advanced Cu/low-k devices through fundamental materials science understanding. Novel solutions for advanced wirebond and flip-chip technologies are developed, along with resolutions for local and global material interaction issues. The zero-th packaging level study examines a novel direct gold wirebonding onto the Cu/low-k terminal pad structure. The first packaging level study attempts to eliminate the Cu/low-k wiresweeping issue through assembly material interactions with both bonding and transfer molding processes. The second packaging level study exams at the impact of Cu/low-k and processing material implementations on the copper trace cracking failures at the substrate level of a package. An integrated first and second level study on high performance flip chip technology using 8M Cu/low-k silicon chip is performed by the optimization of the underfill and substrate materials selections. Lastly, electromigration phenomena and corrosion mechanisms of copper metallization are developed for biased stressing assembly environment through the fundamental of electrochemistry. Throughout the experiment, the 90/130nm technology node of copper wafer fabrication using Black Diamond low-k dielectric is implemented in several large form-factor package assemblies. Functional test vehicles are assembled, reliability-stressed, and failure-analyzed according to the JEDEC standards for the validity of the integrated materials

  13. Investigation of the mechanical and thermal reliability of quilt packaging

    Science.gov (United States)

    Zheng, Quanling

    An interchip interconnection approach based on a new 2-D system-in-package (SiP) method---Quilt Packaging (QP), invented at the University of Notre Dame, is discussed. The principal idea of QP is to assemble a planar mosaic, or "quilt," of dies interconnected by conductive nodules that protrude from vertical faces of ICs. QP offers reduced delay, ultrawide bandwidth, low electrical noise, decreased system size and weight, and the opportunity for heterogeneous integration. In this dissertation, modifications to previous QP fabrication processes are introduced. A new joining method for QP interconnection is presented, using solder paste applied with the pin transfer method, which greatly improves mechanical and thermal reliability, and manufacturability. Chip-to-chip alignment offsets smaller than 1 mum are demonstrated. Simulations and measurements indicate that the microwave performance of QP interconnects provides ultrawide bandwidth. Moreover, the use of solder paste does not significantly degrade the microwave performance of QP. In particular, the return loss associated with the chip-to-chip QP nodules is better than 12.5 dB, and the insertion loss is better than 0.8 dB, at frequencies up to 110 GHz. Mechanical and thermal reliability testing were performed on QP, including pull and thermal shock tests. A novel mechanical testing system that combines a force gauge and a micropull tester was designed and constructed. Pull tests were used to investigate the mechanical strength of QP, and it is found that individual nodules are about as strong as individual wirebonds, but acting together require several pounds of force to separate the chips. Investigations were conducted to learn the effects of thermal shock on all components of the nodule system, including the inter-nodule solder, the copper nodule itself, and the nodule-to-substrate interface layers. Pull tests were performed after thermal shock testing, and it was found that during the first 200 thermal shock

  14. About the ZOOM minimization package

    Energy Technology Data Exchange (ETDEWEB)

    Fischler, M.; Sachs, D.; /Fermilab

    2004-11-01

    A new object-oriented Minimization package is available for distribution in the same manner as CLHEP. This package, designed for use in HEP applications, has all the capabilities of Minuit, but is a re-write from scratch, adhering to modern C++ design principles. A primary goal of this package is extensibility in several directions, so that its capabilities can be kept fresh with as little maintenance effort as possible. This package is distinguished by the priority that was assigned to C++ design issues, and the focus on producing an extensible system that will resist becoming obsolete.

  15. On-chip spectroscopy with thermally tuned high-Q photonic crystal cavities

    Energy Technology Data Exchange (ETDEWEB)

    Liapis, Andreas C., E-mail: andreas.liapis@gmail.com; Gao, Boshen; Siddiqui, Mahmudur R. [The Institute of Optics, University of Rochester, Rochester, New York 14627 (United States); Shi, Zhimin [Department of Physics, University of South Florida, Tampa, Florida 33620 (United States); Boyd, Robert W. [The Institute of Optics, University of Rochester, Rochester, New York 14627 (United States); Department of Physics and School of Electrical Engineering and Computer Science, University of Ottawa, Ottawa, Ontario K1N 6N5 (Canada)

    2016-01-11

    Spectroscopic methods are a sensitive way to determine the chemical composition of potentially hazardous materials. Here, we demonstrate that thermally tuned high-Q photonic crystal cavities can be used as a compact high-resolution on-chip spectrometer. We have used such a chip-scale spectrometer to measure the absorption spectra of both acetylene and hydrogen cyanide in the 1550 nm spectral band and show that we can discriminate between the two chemical species even though the two materials have spectral features in the same spectral region. Our results pave the way for the development of chip-size chemical sensors that can detect toxic substances.

  16. On-chip spectroscopy with thermally-tuned high-Q photonic crystal cavities

    CERN Document Server

    Liapis, Andreas C; Siddiqui, Mahmudur R; Shi, Zhimin; Boyd, Robert W

    2015-01-01

    Spectroscopic methods are a sensitive way to determine the chemical composition of potentially hazardous materials. Here, we demonstrate that thermally-tuned high-Q photonic crystal cavities can be used as a compact high-resolution on-chip spectrometer. We have used such a chip-scale spectrometer to measure the absorption spectra of both acetylene and hydrogen cyanide in the 1550 nm spectral band, and show that we can discriminate between the two chemical species even though the two materials have spectral features in the same spectral region. Our results pave the way for the development of chip-size chemical sensors that can detect toxic substances.

  17. Applying Partial Power-Gating to Direction-Sliced Network-on-Chip

    OpenAIRE

    Feng Wang; Xiantuo Tang; Zuocheng Xing

    2015-01-01

    Network-on-Chip (NoC) is one of critical communication architectures for future many-core systems. As technology is continually scaling down, on-chip network meets the increasing leakage power crisis. As a leakage power mitigation technique, power-gating can be utilized in on-chip network to solve the crisis. However, the network performance is severely affected by the disconnection in the conventional power-gated NoC. In this paper, we propose a novel partial power-gating approach to improve...

  18. On-chip spectroscopy with thermally tuned high-Q photonic crystal cavities

    International Nuclear Information System (INIS)

    Spectroscopic methods are a sensitive way to determine the chemical composition of potentially hazardous materials. Here, we demonstrate that thermally tuned high-Q photonic crystal cavities can be used as a compact high-resolution on-chip spectrometer. We have used such a chip-scale spectrometer to measure the absorption spectra of both acetylene and hydrogen cyanide in the 1550 nm spectral band and show that we can discriminate between the two chemical species even though the two materials have spectral features in the same spectral region. Our results pave the way for the development of chip-size chemical sensors that can detect toxic substances

  19. Evaluation of Package Stress during Temperature Cycling using Metal Deformation Measurement and FEM Simulation

    International Nuclear Information System (INIS)

    Plastic encapsulated devices that are exposed to Temperature Cycling (TC) tests undergo an excessive mechanical stress due to different Coefficients of Thermal Expansion (CTE) of the various materials used in the system. Especially in the corners of the die, passivation cracks and shifted metal lines can be observed, which demonstrates an increasing mechanical stress from chip center to the corners of the die. This effect has been known for a long time. This paper presents a simple measurement technique to quantify the mechanical shear stress at the chip-Mold Compound (MC) interface by measuring the deformation of a periodical metal structure. Based on this deformation measurement, we evaluated the stress distribution within the package, and the influence of different parameters such as number of cycles and chip size. Furthermore, these experimental results were compared with FEM simulation, and showed good agreement but could not account in all cases for the total amount of observed shift

  20. Chips in black boxes? Convenience life span, parafood, brandwidth, families, and co-creation.

    Science.gov (United States)

    Jacobs, Marc

    2015-11-01

    Any consumer who opens a bag of potato or corn chips (or crisps in the UK) knows there is no time to waste to enjoy or share them. The convenience life span of chips is limited: it is the shelf or storage life and a very limited time once outside the bag. Many technologies converge to generate the desired effect as a black box, not only of the packaging but also of the chips themselves. The concept of paratext can be applied to printed messages on the package, including the brand name and other texts like advertising (epitexts), which can be expanded into the concept of parafood. These concepts help to discuss technological developments and interpret why this has recently become a negotiation zone for co-creation (see the Do us a flavor campaigns). They are symptoms of changing relations between production, research and development, marketing, and consumption. This paper pays special attention to back stories, underdog brand biographies and narratives about origin. The concept of brandwidth is introduced to sensitize about the limits of combining different stories about chips. A recent brand biography, a family history and a cookery book are used to discuss the phenomenon of cooking with Fritos. Together with the concepts of parafood, brandwidth and black boxes, more reflection and dialogue about the role of history and heritage in marketing put new challenging perspectives on the agenda. PMID:25791963

  1. Materials, design and processing of air encapsulated MEMS packaging

    Science.gov (United States)

    Fritz, Nathan T.

    This work uses a three-dimensional air cavity technology to improve the fabrication, and functionality of microelectronics devices, performance of on-board transmission lines, and packaging of micro-electromechanical systems (MEMS). The air cavity process makes use of the decomposition of a patterned sacrificial polymer followed by the diffusion of its by-products through a curing polymer overcoat to obtain the embedded air structure. Applications and research of air cavities have focused on simple designs that concentrate on the size and functionality of the particular device. However, a lack of guidelines for fabrication, materials used, and structural design has led to mechanical stability issues and processing refinements. This work investigates improved air gap cavities for use in MEMS packaging processes, resulting in fewer fabrication flaws and lower cost. The identification of new materials, such as novel photo-definable organic/inorganic hybrid polymers, was studied for increased strength and rigidity due to their glass-like structure. A novel epoxy polyhedral oligomeric silsesquioxane (POSS) material was investigated and characterized for use as a photodefineable, permanent dielectrics with improved mechanical properties. The POSS material improved the air gap fabrication because it served as a high-selectivity etch mask for patterning sacrificial materials as well as a cavity overcoat material with improved rigidity. An investigation of overcoat thickness and decomposition kinetics provided a fundamental understanding of the properties that impart mechanical stability to cavities of different shape and volume. Metallization of the cavities was investigated so as to provide hermetic sealing and improved cavity strength. The improved air cavity, wafer-level packages were tested using resonator-type devices and chip-level lead frame packaging. The air cavity package was molded under traditional lead frame molding pressures and tested for mechanical

  2. Design, fabrication, and packaging of an integrated, wirelessly-powered optrode array for optogenetics application

    OpenAIRE

    Kwon, Ki Yong; Lee, Hyung-Min; Ghovanloo, Maysam; Weber, Arthur; Li, Wen

    2015-01-01

    The recent development of optogenetics has created an increased demand for advancing engineering tools for optical modulation of neural circuitry. This paper details the design, fabrication, integration, and packaging procedures of a wirelessly-powered, light emitting diode (LED) coupled optrode neural interface for optogenetic studies. The LED-coupled optrode array employs microscale LED (μLED) chips and polymer-based microwaveguides to deliver light into multi-level cortical networks, coupl...

  3. Modeling Light-Extraction Characteristics of Packaged Light-Emitting Diodes

    OpenAIRE

    D. Z.-Y. Ting; McGill, T. C.

    1998-01-01

    We employ a Monte Carlo ray-tracing technique to model light-extraction characteristics of light-emitting diodes. By relaxing restrictive assumptions on photon traversal history, our method improves upon available analytical models for estimating light-extraction efficiencies from bare LED chips, and enhances modeling capabilities by realistically treating the various processes which photons can encounter in a packaged LED. Our method is not only capable of calculating extraction efficiencies...

  4. Wafer level vacuum packaging of scanning micro-mirrors using glass-frit and anodic bonding methods

    Science.gov (United States)

    Langa, S.; Drabe, C.; Kunath, C.; Dreyhaupt, A.; Schenk, H.

    2013-03-01

    In this paper the authors report about the six inch wafer level vacuum packaging of electro-statically driven two dimensional micro-mirrors. The packaging was done by means of two types of wafer bonding methods: anodic and glass frit. The resulting chips after dicing are 4 mm wide, 6 mm long and 1.6 mm high and the residual pressure inside the package after dicing was estimated to be between 2 and 20 mbar. This allowed us to reduce the driving voltage of the micro-mirrors by more than 40% compared to the driving voltage without vacuum packaging. The vacuum stability after 5 months was verified by measurement using the so called "membrane method". Persistence of the vacuum was proven. No getter materials were used for packaging.

  5. Atom chip gravimeter

    Science.gov (United States)

    Schubert, Christian; Abend, Sven; Gebbe, Martina; Gersemann, Matthias; Ahlers, Holger; Müntinga, Hauke; Matthias, Jonas; Sahelgozin, Maral; Herr, Waldemar; Lämmerzahl, Claus; Ertmer, Wolfgang; Rasel, Ernst

    2016-04-01

    Atom interferometry has developed into a tool for measuring rotations [1], accelerations [2], and testing fundamental physics [3]. Gravimeters based on laser cooled atoms demonstrated residual uncertainties of few microgal [2,4] and were simplified for field applications [5]. Atomic gravimeters rely on the interference of matter waves which are coherently manipulated by laser light fields. The latter can be interpreted as rulers to which the position of the atoms is compared. At three points in time separated by a free evolution, the light fields are pulsed onto the atoms. First, a coherent superposition of two momentum states is produced, then the momentum is inverted, and finally the two trajectories are recombined. Depending on the acceleration the atoms experienced, the number of atoms detected in the output ports will change. Consequently, the acceleration can be determined from the output signal. The laser cooled atoms with microkelvin temperatures used in state-of-the-art gravimeters impose limits on the accuracy [4]. Therefore, ultra-cold atoms generated by Bose-Einstein condensation and delta-kick collimation [6,7] are expected to be the key for further improvements. These sources suffered from a low flux implying an incompatible noise floor, but a competitive performance was demonstrated recently with atom chips [8]. In the compact and robust setup constructed for operation in the drop tower [6] we demonstrated all steps necessary for an atom chip gravimeter with Bose-Einstein condensates in a ground based operation. We will discuss the principle of operation, the current performance, and the perspectives to supersede the state of the art. The authors thank the QUANTUS cooperation for contributions to the drop tower project in the earlier stages. This work is supported by the German Space Agency (DLR) with funds provided by the Federal Ministry for Economic Affairs and Energy (BMWi) due to an enactment of the German Bundestag under grant numbers DLR 50WM

  6. Geometry methods and packages

    International Nuclear Information System (INIS)

    The authors address the problem of following the trajectory of a particle in simulations. It is necessary to follow the motion of the particle, and to determine its intersection with different geometric surfaces in the problem, in order to relate the stepping of the particle trajectory into real motion through the physical problem at hand. The distance a particle moves before encountering a surface is needed to compare with the actual transport distance that is about to be used in the simulation. Basic mathematical expressions are developed for the intersections of particle trajectories with plane and conic surfaces. The authors show how these are used in the EGS4 code system, which should be typical of the general problem. They also review geometry packages currently being used in electron-photon Monte Carlo programs

  7. Tritium waste package

    Science.gov (United States)

    Rossmassler, Rich; Ciebiera, Lloyd; Tulipano, Francis J.; Vinson, Sylvester; Walters, R. Thomas

    1995-01-01

    A containment and waste package system for processing and shipping tritium xide waste received from a process gas includes an outer drum and an inner drum containing a disposable molecular sieve bed (DMSB) seated within outer drum. The DMSB includes an inlet diffuser assembly, an outlet diffuser assembly, and a hydrogen catalytic recombiner. The DMSB absorbs tritium oxide from the process gas and converts it to a solid form so that the tritium is contained during shipment to a disposal site. The DMSB is filled with type 4A molecular sieve pellets capable of adsorbing up to 1000 curies of tritium. The recombiner contains a sufficient amount of catalyst to cause any hydrogen add oxygen present in the process gas to recombine to form water vapor, which is then adsorbed onto the DMSB.

  8. Electronic equipment packaging technology

    CERN Document Server

    Ginsberg, Gerald L

    1992-01-01

    The last twenty years have seen major advances in the electronics industry. Perhaps the most significant aspect of these advances has been the significant role that electronic equipment plays in almost all product markets. Even though electronic equipment is used in a broad base of applications, many future applications have yet to be conceived. This versatility of electron­ ics has been brought about primarily by the significant advances that have been made in integrated circuit technology. The electronic product user is rarely aware of the integrated circuits within the equipment. However, the user is often very aware of the size, weight, mod­ ularity, maintainability, aesthetics, and human interface features of the product. In fact, these are aspects of the products that often are instrumental in deter­ mining its success or failure in the marketplace. Optimizing these and other product features is the primary role of Electronic Equipment Packaging Technology. As the electronics industry continues to pr...

  9. Stem end chip defect in tubers used for potato chip production

    Science.gov (United States)

    Stem-end chip defect (SECD) is a serious tuber quality concern that affects chipping potatoes (Solanum tuberosum). SECD defect is characterized by dark-colored vascular tissues and adjacent cortical tissues at the tuber stem-end portion of potato chips after frying. Chips with SECD are unattractive ...

  10. Measurements of millimeter wave test structures for high speed chip testing

    OpenAIRE

    De Keulenaer, Timothy; Ban, Yu; Torfs, Guy; Sercu, Stefaan; Geest, Jan van de; Bauwelinck, Johan

    2014-01-01

    This paper presents the frequency domain characterization of very high bandwidth connectorized traces and a millimeter wave rat race coupler. These connectorized differential grounded coplanar waveguide traces, essential for the testability of high speed integrated circuits, have a measured flat frequency response up to 67GHz which indicates correct connector footprint and transmission line design. The differential traces narrow down to a chip scale pitch of 150 μm allowing direct flip chip c...

  11. Lab-on-a-chip devices and micro-total analysis systems a practical guide

    CERN Document Server

    Svendsen, Winnie

    2015-01-01

    This book covers all the steps in order to fabricate a lab-on-a-chip device starting from the idea, the design, simulation, fabrication and final evaluation. Additionally, it includes basic theory on microfluidics essential to understand how fluids behave at such reduced scale. Examples of successful histories of lab-on-a-chip systems that made an impact in fields like biomedicine and life sciences are also provided.

  12. Development, Fabrication and Characterisation of Atom Chips

    OpenAIRE

    Groth, Sönke

    2006-01-01

    Atom chips are robust and extremely powerful toolboxes for quantum optical experiments, since they make it possible to create exceedingly precise magnetic traps for neutral atoms with minimal field modulations. Accurate manipulation of trapped atoms is feasible with magnetic and electric fields created on the atom chip. Therefore atom chips with high quality surfaces and extremely well defined wires were build (roughness < 20nm). Furthermore new generations of atom chips were developed, like ...

  13. System-in-package LTCC platform for 3D RF to millimeter wave

    Science.gov (United States)

    Vähä-Heikkilä, T.; Lahti, M.

    2011-04-01

    This presentation shows recent trends and results in 3D Low Temperature Co-Fired Ceramics (LTCC) modules in applications from RF to millimeter waves. The system-in-package LTCC platform is a true three dimensional module technology. LTCC is a lightweight multi-layer technology having typically 6-20 ceramic layers and metallizations between. The metallization levels i.e different metal layers can be patterned and connected together with metal vias. Passive devices can also be fabricated on LTCC while active devices and other chips are connected with flip-chip, wire bonding or soldering. In addition to passives directly fabricated to LTCC, several different technologies/ chips can be hybrid integrated to the same module. LTCC platform is also well suited for the realization of antenna arrays for microwave and millimeter wave applications. Potential applications are ranging from short range communications to space and radars. VTT has designed, fabricated and characterized microwave and millimeter wave packages for Radio Frequency (RF) Micro Electro Mechanical Systems (MEMS) as well as active devices. Also, several types of system-in-package modules have been realized containing hybrid integrated CMOS and GaAs MMICs and antenna arrays.

  14. Oral Hygiene. Learning Activity Package.

    Science.gov (United States)

    Hime, Kirsten

    This learning activity package on oral hygiene is one of a series of 12 titles developed for use in health occupations education programs. Materials in the package include objectives, a list of materials needed, a list of definitions, information sheets, reviews (self evaluations) of portions of the content, and answers to reviews. These topics…

  15. Packaging Software Assets for Reuse

    Science.gov (United States)

    Mattmann, C. A.; Marshall, J. J.; Downs, R. R.

    2010-12-01

    The reuse of existing software assets such as code, architecture, libraries, and modules in current software and systems development projects can provide many benefits, including reduced costs, in time and effort, and increased reliability. Many reusable assets are currently available in various online catalogs and repositories, usually broken down by disciplines such as programming language (Ibiblio for Maven/Java developers, PyPI for Python developers, CPAN for Perl developers, etc.). The way these assets are packaged for distribution can play a role in their reuse - an asset that is packaged simply and logically is typically easier to understand, install, and use, thereby increasing its reusability. A well-packaged asset has advantages in being more reusable and thus more likely to provide benefits through its reuse. This presentation will discuss various aspects of software asset packaging and how they can affect the reusability of the assets. The characteristics of well-packaged software will be described. A software packaging domain model will be introduced, and some existing packaging approaches examined. An example case study of a Reuse Enablement System (RES), currently being created by near-term Earth science decadal survey missions, will provide information about the use of the domain model. Awareness of these factors will help software developers package their reusable assets so that they can provide the most benefits for software reuse.

  16. Gentoo package dependencies over time

    NARCIS (Netherlands)

    Bloemen, Remco; Amrit, Chintan; Kuhlmann, Stefan; Ordonez-Matamoros, Gonzalo

    2014-01-01

    Open source distributions such as Gentoo need to accurately track dependency relations between software packages in order to install working systems. To do this, Gentoo has a carefully authored database containing those relations. In this paper, we extract the Gentoo package dependency graph and its

  17. 49 CFR 173.411 - Industrial packagings.

    Science.gov (United States)

    2010-10-01

    ... comparative data showing that the construction methods, packaging design, and materials of construction comply... industrial packaging must comply with the requirements of this section which specifies packaging tests, and record retention applicable to Industrial Packaging Type 1 (IP-1), Industrial Packaging Type 2...

  18. 49 CFR 173.63 - Packaging exceptions.

    Science.gov (United States)

    2010-10-01

    ... 49 Transportation 2 2010-10-01 2010-10-01 false Packaging exceptions. 173.63 Section 173.63... SHIPMENTS AND PACKAGINGS Definitions, Classification and Packaging for Class 1 § 173.63 Packaging exceptions... which are used to project fastening devices. (2) Packaging for cartridges, small arms, and...

  19. 19 CFR 191.13 - Packaging materials.

    Science.gov (United States)

    2010-04-01

    ... 19 Customs Duties 2 2010-04-01 2010-04-01 false Packaging materials. 191.13 Section 191.13 Customs... (CONTINUED) DRAWBACK General Provisions § 191.13 Packaging materials. (a) Imported packaging material... packaging material when used to package or repackage merchandise or articles exported or destroyed...

  20. Near Field On Chip RFID Antenna Design

    OpenAIRE

    Vargas, Alberto; Vojtech, Lukas

    2010-01-01

    The process of fabricating the antenna on the top of the RFID chip eliminates the need for a separated and costly expensive process for antenna printing and assemblage, compulsory for a separated "off-chip" antenna which is much more times larger than the chip itself. This

  1. On-Chip Optical Squeezing

    Science.gov (United States)

    Dutt, Avik; Luke, Kevin; Manipatruni, Sasikanth; Gaeta, Alexander L.; Nussenzveig, Paulo; Lipson, Michal

    2015-04-01

    We report the observation of all-optical squeezing in an on-chip monolithically integrated CMOS-compatible platform. Our device consists of a low-loss silicon nitride microring optical parametric oscillator (OPO) with a gigahertz cavity linewidth. We measure 1.7 dB (5 dB corrected for losses) of sub-shot-noise quantum correlations between bright twin beams generated in the microring four-wave-mixing OPO pumped above threshold. This experiment demonstrates a compact, robust, and scalable platform for quantum-optics and quantum-information experiments on chip.

  2. Planar ion chip design for scalable quantum information processing

    Institute of Scientific and Technical Information of China (English)

    Wan Jin-Yin; Wang Yu-Zhu; Liu Liang

    2008-01-01

    We investigate a planar ion chip design with a two-dimensional array of linear ion traps for scalable quantum information processing.Qubits are formed from the internal electronic states of trapped 40Ca+ ions.The segmented electrodes reside in a single plane on a substrate and a grounded metal plate separately,a combination of appropriaterf and DC potentials is applied to them for stable ion confinement.Every two adjacent electrodes can generate a linear ion trap in and between the electrodes above the chip at a distance dependent on the geometrical scale and other considerations.The potential distributions are calculated by using a static electric field qualitatively.This architecture provides a conceptually simple avenue to achieving the microfabrication and large-scale quantum computation based on the axrays of trapped ions.

  3. CDIAC catalog of numeric data packages and computer model packages

    International Nuclear Information System (INIS)

    The Carbon Dioxide Information Analysis Center acquires, quality-assures, and distributes to the scientific community numeric data packages (NDPs) and computer model packages (CMPs) dealing with topics related to atmospheric trace-gas concentrations and global climate change. These packages include data on historic and present atmospheric CO2 and CH4 concentrations, historic and present oceanic CO2 concentrations, historic weather and climate around the world, sea-level rise, storm occurrences, volcanic dust in the atmosphere, sources of atmospheric CO2, plants' response to elevated CO2 levels, sunspot occurrences, and many other indicators of, contributors to, or components of climate change. This catalog describes the packages presently offered by CDIAC, reviews the processes used by CDIAC to assure the quality of the data contained in these packages, notes the media on which each package is available, describes the documentation that accompanies each package, and provides ordering information. Numeric data are available in the printed NDPs and CMPs, in CD-ROM format, and from an anonymous FTP area via Internet. All CDIAC information products are available at no cost

  4. The Applications of Synchrotron Radiation X-rays 3D Imaging Techniques to The Study of Electromigration Failure in Flip-Chip Solder Joints

    OpenAIRE

    TIAN, TIAN

    2012-01-01

    The advanced packaging technology is a business of billions of dollars. The reliability issues of the packaging products are of keen interest. In the microelectronic industry, a major paradigm change from two-dimensional integrated circuit (2D-IC) to three-dimensional integrated circuit (3D-IC) is occurring. Electromigration (EM), referring to the atomic diffusion induced by a high electron current density, is one of the most serious reliability concerns of flip chip solder joints used in pac...

  5. Microtraps and Atom Chips: Toolboxes for Cold Atom Physics

    OpenAIRE

    Feenstra, L.; Andersson, L. M.; Schmiedmayer, J.

    2003-01-01

    Magnetic microtraps and Atom Chips are safe, small-scale, reliable and flexible tools to prepare ultra-cold and degenerate atom clouds as sources for various atom-optical experiments. We present an overview of the possibilities of the devices and indicate how a microtrap can be used to prepare and launch a Bose-Einstein condensate for use in an atom clock or an interferometer.

  6. A new golden bump making method for high power LED flip chip

    Science.gov (United States)

    Liu, Hongwei; Niu, Pingjuan; Hu, Haiyang; Chen, Hongda; Xia, Zhiwei

    2007-11-01

    Nowadays, high power LED is often packaged with flip chip method. The gold bump is usually made by electroplating or gold evaporation, which cause the environment pollution and material waste. A gold wire bump manufacture technology for high power LED flip chip is described in this paper. The wire bond device is used and different bump making parameters, such as weld temperature, pressure and ultrasonic power, are optimized through experiments. At the same time, a new bump wire tail height managing process is introduced. The gold wire bump with this method height difference keep in 3 micrometers and which is convenient for flip chip. Then, rapid annealing is taken to make sure the gold wire bump has a well adherence to the wafer. At last, the bump weld result is tested and the bump invalidation is analyzed with the SEM. The bonding force between bump and wafer more than 10 grams. The flip chip high power LED with gold wire bump has low forth voltage and heat resistance. All of above proved that the gold wire bump is convenient and reliable for high power flip chip LED.

  7. Bi-axial fracture strength characteristic of an ultra-thin flash memory chip

    International Nuclear Information System (INIS)

    Recently, ultra-thin chips with thicknesses of under 35 µm have emerged as an option for thinner, high performance electronic devices. For reliable electronic devices and high throughput packaging processes, the mechanical properties of ultra-thin chips need to be accurately understood. In this study, the fracture strength of an ultra-thin flash memory chip was measured using a ball-on-ring (BOR) test. To evaluate and validate the bi-axial strength in the BOR test, a finite element analysis was performed. It was compared with the analytical solution based on Hertzian contact theory. Flash memory chip specimens with different thicknesses were prepared and their bi-axial strengths were tested with respect to various wafer thinning process parameters such as grinding speed and polishing time. Raman spectroscopy was used to characterize the residual stress generated during the wafer thinning process. The surface roughness of the silicon wafer was measured using an atomic force microscope under various wafer thinning conditions. From the study, the fracture strength characteristics of the ultra-thin chip could be established as a function of the wafer thinning parameters. (paper)

  8. Invisibility Cloak Printed on a Photonic Chip

    CERN Document Server

    Feng, Zhen; Zhao, Yu-Xi; Gao, Jun; Qiao, Lu-Feng; Yang, Ai-Lin; Lin, Xiao-Feng; Jin, Xian-Min

    2016-01-01

    Invisibility cloak capable of hiding an object can be achieved by properly manipulating electromagnetic field. Such a remarkable ability has been shown in transformation and ray optics. Alternatively, it may be realistic to create a spatial cloak by means of confining electromagnetic field in three-dimensional arrayed waveguides and introducing appropriate collective curvature surrounding an object. We realize the artificial structure in borosilicate by femtosecond laser direct writing, where we prototype up to 5000 waveguides to conceal millimeter-scale volume. We characterize the performance of the cloak by normalized cross correlation, tomography analysis and continuous three-dimensional viewing angle scan. Our results show invisibility cloak can be achieved in waveguide optics. Furthermore, directly printed invisibility cloak on a photonic chip may enable controllable study and novel applications in classical and quantum integrated photonics, such as invisualising a coupling or swapping operation with on-...

  9. Soil chip convey of lunar subsurface auger drill

    Science.gov (United States)

    Zhao, Deming; Tang, Dewei; Hou, Xuyan; Jiang, Shengyuan; Deng, Zongquan

    2016-05-01

    Celestial body subsurface drilling and sampling is a key aspect of near-earth exploration projects. In these sample return missions, the auger drill system is universally used due to the environment and detector load limits. The common failure that the auger faces is chip chocking, which can raise the torque and cause the drill to stick. This paper builds auger drill models describing chip flow in the auger groove to balance geometric parameters, functional capability, and reliability. The features of chip flow are summarized and verified by a series of discrete element method simulations. In contrast to previous auger design, a convey capability factor is defined to indicate the auger's chip removal capacity, and the role of pitch angle and other parameters is assessed through motion analysis of the lunar soil flow process. The theory is verified by testing the drill penetrating speed limit, which combines drill geometry and motion parameters. This work provides a new method for design and optimization of low speed auger drill systems and research on particle flow with small scale mechanical constraints.

  10. Development of a sensory test method for odor measurement in a package headspace

    DEFF Research Database (Denmark)

    Reinbach, Helene Christine; Allesen-Holm, Bodil Helene; Kristoffersson, Lars;

    2011-01-01

    The aim of the present study was to develop a sensory method to evaluate off-odors in a package headspace relative to a reference scale. Selection of panelists was performed with a questionnaire and with the Sniffin' stick test. A 1-butanol reference scale and three types of scales (a 15-cm line, a...... color-graded brightness line scale and a color-graded brightness category scale) were compared. 1-butanol proved to be a reliable reference scale for the off-odor intensity in the package headspace. The type of scales did not affect the odor intensity ratings; however, the color-graded brightness line...... scale tended to give a greater accuracy of scored odor intensity. The color-graded brightness scale may strengthen the repeatability of the intensity measures due to the cross-modal support in the judgment processes. The method allows the conversion of intensity judgment of a package headspace to a...

  11. Nuclear waste packaging facility

    International Nuclear Information System (INIS)

    A nuclear waste packaging facility comprising: (a) a first section substantially surrounded by radiation shielding, including means for remotely handling waste delivered to the first section and for placing the waste into a disposal module; (b) a second section substantially surrounded by radiation shielding, including means for handling a deformable container bearing waste delivered to the second section, the handling means including a compactor and means for placing the waste bearing deformable container into the compactor, the compactor capable of applying a compacting force to the waste bearing containers sufficient to inelastically deform the waste and container, and means for delivering the deformed waste bearing containers to a disposal module; (c) a module transportation and loading section disposed between the first and second sections including a means for handling empty modules delivered to the facility and for loading the empty modules on the transport means; the transport means moving empty disposal modules to the first section and empty disposal modules to the second section for locating empty modules in a position for loading with nuclear waste, and (d) a grouting station comprising means for pouring grout into the waste bearing disposal module, and a capping station comprising means for placing a lid onto the waste bearing grout-filled disposal module to completely encapsulate the waste

  12. RankAggreg, an R package for weighted rank aggregation

    Directory of Open Access Journals (Sweden)

    Datta Susmita

    2009-02-01

    Full Text Available Abstract Background Researchers in the field of bioinformatics often face a challenge of combining several ordered lists in a proper and efficient manner. Rank aggregation techniques offer a general and flexible framework that allows one to objectively perform the necessary aggregation. With the rapid growth of high-throughput genomic and proteomic studies, the potential utility of rank aggregation in the context of meta-analysis becomes even more apparent. One of the major strengths of rank-based aggregation is the ability to combine lists coming from different sources and platforms, for example different microarray chips, which may or may not be directly comparable otherwise. Results The RankAggreg package provides two methods for combining the ordered lists: the Cross-Entropy method and the Genetic Algorithm. Two examples of rank aggregation using the package are given in the manuscript: one in the context of clustering based on gene expression, and the other one in the context of meta-analysis of prostate cancer microarray experiments. Conclusion The two examples described in the manuscript clearly show the utility of the RankAggreg package in the current bioinformatics context where ordered lists are routinely produced as a result of modern high-throughput technologies.

  13. In-Package Chemistry Abstraction

    International Nuclear Information System (INIS)

    This report was developed in accordance with the requirements in ''Technical Work Plan for: Regulatory Integration Modeling and Analysis of the Waste Form and Waste Package'' (BSC 2004 [DIRS 171583]). The purpose of the in-package chemistry model is to predict the bulk chemistry inside of a breached waste package and to provide simplified expressions of that chemistry as function of time after breach to Total Systems Performance Assessment for the License Application (TSPA-LA). The scope of this report is to describe the development and validation of the in-package chemistry model. The in-package model is a combination of two models, a batch reactor model that uses the EQ3/6 geochemistry-modeling tool, and a surface complexation model that is applied to the results of the batch reactor model. The batch reactor model considers chemical interactions of water with the waste package materials and the waste form for commercial spent nuclear fuel (CSNF) waste packages and codisposed waste packages that contain both high-level waste glass (HLWG) and DOE spent fuel. The surface complexation model includes the impact of fluid-surface interactions (i.e., surface complexation) on the resulting fluid composition. The model examines two types of water influx: (1) the condensation of water vapor that diffuses into the waste package, and (2) seepage water that enters the waste package from the drift as a liquid. (1) Vapor Influx Case: The condensation of vapor onto the waste package internals is simulated as pure H2O and enters at a rate determined by the water vapor pressure for representative temperature and relative humidity conditions. (2) Water Influx Case: The water entering a waste package from the drift is simulated as typical groundwater and enters at a rate determined by the amount of seepage available to flow through openings in a breached waste package. TSPA-LA uses the vapor influx case for the nominal scenario for simulations where the waste package has been

  14. In-Package Chemistry Abstraction

    Energy Technology Data Exchange (ETDEWEB)

    E. Thomas

    2004-11-09

    This report was developed in accordance with the requirements in ''Technical Work Plan for: Regulatory Integration Modeling and Analysis of the Waste Form and Waste Package'' (BSC 2004 [DIRS 171583]). The purpose of the in-package chemistry model is to predict the bulk chemistry inside of a breached waste package and to provide simplified expressions of that chemistry as function of time after breach to Total Systems Performance Assessment for the License Application (TSPA-LA). The scope of this report is to describe the development and validation of the in-package chemistry model. The in-package model is a combination of two models, a batch reactor model that uses the EQ3/6 geochemistry-modeling tool, and a surface complexation model that is applied to the results of the batch reactor model. The batch reactor model considers chemical interactions of water with the waste package materials and the waste form for commercial spent nuclear fuel (CSNF) waste packages and codisposed waste packages that contain both high-level waste glass (HLWG) and DOE spent fuel. The surface complexation model includes the impact of fluid-surface interactions (i.e., surface complexation) on the resulting fluid composition. The model examines two types of water influx: (1) the condensation of water vapor that diffuses into the waste package, and (2) seepage water that enters the waste package from the drift as a liquid. (1) Vapor Influx Case: The condensation of vapor onto the waste package internals is simulated as pure H2O and enters at a rate determined by the water vapor pressure for representative temperature and relative humidity conditions. (2) Water Influx Case: The water entering a waste package from the drift is simulated as typical groundwater and enters at a rate determined by the amount of seepage available to flow through openings in a breached waste package. TSPA-LA uses the vapor influx case for the nominal scenario for simulations where the waste

  15. Parallel distributed free-space optoelectronic computer engine using flat plug-on-top optics package

    Science.gov (United States)

    Berger, Christoph; Ekman, Jeremy T.; Wang, Xiaoqing; Marchand, Philippe J.; Spaanenburg, Henk; Kiamilev, Fouad E.; Esener, Sadik C.

    2000-05-01

    We report about ongoing work on a free-space optical interconnect system, which will demonstrate a Fast Fourier Transformation calculation, distributed among six processor chips. Logically, the processors are arranged in two linear chains, where each element communicates optically with its nearest neighbors. Physically, the setup consists of a large motherboard, several multi-chip carrier modules, which hold the processor/driver chips and the optoelectronic chips (arrays of lasers and detectors), and several plug-on-top optics modules, which provide the optical links between the chip carrier modules. The system design tries to satisfy numerous constraints, such as compact size, potential for mass-production, suitability for large arrays (up to 1024 parallel channels), compatibility with standard electronics fabrication and packaging technology, potential for active misalignment compensation by integration MEMS technology, and suitability for testing different imaging topologies. We present the system architecture together with details of key components and modules, and report on first experiences with prototype modules of the setup.

  16. Laser Welding in Electronic Packaging

    Science.gov (United States)

    2000-01-01

    The laser has proven its worth in numerous high reliability electronic packaging applications ranging from medical to missile electronics. In particular, the pulsed YAG laser is an extremely flexible and versatile too] capable of hermetically sealing microelectronics packages containing sensitive components without damaging them. This paper presents an overview of details that must be considered for successful use of laser welding when addressing electronic package sealing. These include; metallurgical considerations such as alloy and plating selection, weld joint configuration, design of optics, use of protective gases and control of thermal distortions. The primary limitations on use of laser welding electronic for packaging applications are economic ones. The laser itself is a relatively costly device when compared to competing welding equipment. Further, the cost of consumables and repairs can be significant. These facts have relegated laser welding to use only where it presents a distinct quality or reliability advantages over other techniques of electronic package sealing. Because of the unique noncontact and low heat inputs characteristics of laser welding, it is an ideal candidate for sealing electronic packages containing MEMS devices (microelectromechanical systems). This paper addresses how the unique advantages of the pulsed YAG laser can be used to simplify MEMS packaging and deliver a product of improved quality.

  17. FERMI multi-chip module

    CERN Multimedia

    This FERMI multi-chip module contains five million transistors. 25 000 of these modules will handle the flood of information through parts of the ATLAS and CMS detectors at the LHC. To select interesting events for recording, crucial decisions are taken before the data leaves the detector. FERMI modules are being developed at CERN in partnership with European industry.

  18. Fiber cavities for atom chips

    OpenAIRE

    Klappauf, B.G.; Horak, P.; Kazansky, P. G.

    2003-01-01

    We present experimental realizations of several micro-cavities, constructed from standard fiber optic components, which meet the theoretical criteria for single atom detection from laser-cooled samples. We discuss integration of these cavities into state-of-the-art 'atom chips'.

  19. Kinerja Pengeringan Chip Ubi Kayu

    Directory of Open Access Journals (Sweden)

    Sandi Asmara

    2010-10-01

    Full Text Available Lampung Province is the largest producer of cassava in Indonesia. Cassava has a weakness that is easily damaged and could not be stored longer. To overcome this, there is a need of an effective drying process so that cassava can be processed into other materials of lower power use as well as its economic value. A hybrid drying system is one solution to resolve the issue. The purpose of this research is to study the performance of drying cassava chips by using a hybrid type of dryer rack. The process of drying cassava chips made using a three-stage treatments with three replicates with the input load of 30 kg of cassava chips. The results showed that the pattern of decline in water levels in each treatment is uneven. The time needed to dry cassava chips to reach the water content of 10% - 12% in the drying of materials using sunlight for 18 hours, using electrical energy for 16 hours and use the energy of sunlight and electricity for 12 hours. The higher temperatures produced the shorter the time required in the drying process. Electrical energy required for the drying process using electric energy was 91 440 kJ and drying using electrical energy and sunlight was 68600 kJ.

  20. Reconfigurable Networks-on-Chip

    CERN Document Server

    Chen, Sao-Jie; Tsai, Wen-Chung; Hu, Yu-Hen

    2012-01-01

    This book provides a comprehensive survey of recent progress in the design and implementation of Networks-on-Chip. It addresses a wide spectrum of on-chip communication problems, ranging from physical, network, to application layers. Specific topics that are explored in detail include packet routing, resource arbitration, error control/correction, application mapping, and communication scheduling. Additionally, a novel bi-directional communication channel NoC (BiNoC) architecture is described, with detailed explanation.   Written for practicing engineers in need of practical knowledge about the design and implementation of networks-on-chip; Includes tutorial-like details to introduce readers to a diverse range of NoC designs, as well as in-depth analysis for designers with NoC experience to explore advanced issues; Describes a variety of on-chip communication architectures, including a novel bi-directional communication channel NoC.     From the Foreword: Overall this book shows important advances over the...