Chip-package nano-structured copper and nickel interconnections with metallic and polymeric bonding interfaces

Science.gov (United States)

Aggarwal, Ankur

With the semiconductor industry racing toward a historic transition, nano chips with less than 45 nm features demand I/Os in excess of 20,000 that support computing speed in terabits per second, with multi-core processors aggregately providing highest bandwidth at lowest power. On the other hand, emerging mixed signal systems are driving the need for 3D packaging with embedded active components and ultra-short interconnections. Decreasing I/O pitch together with low cost, high electrical performance and high reliability are the key technological challenges identified by the 2005 International Technology Roadmap for Semiconductors (ITRS). Being able to provide several fold increase in the chip-to-package vertical interconnect density is essential for garnering the true benefits of nanotechnology that will utilize nano-scale devices. Electrical interconnections are multi-functional materials that must also be able to withstand complex, sustained and cyclic thermo-mechanical loads. In addition, the materials must be environmentally-friendly, corrosion resistant, thermally stable over a long time, and resistant to electro-migration. A major challenge is also to develop economic processes that can be integrated into back end of the wafer foundry, i.e. with wafer level packaging. Device-to-system board interconnections are typically accomplished today with either wire bonding or solders. Both of these are incremental and run into either electrical or mechanical barriers as they are extended to higher density of interconnections. Downscaling traditional solder bump interconnect will not satisfy the thermo-mechanical reliability requirements at very fine pitches of the order of 30 microns and less. Alternate interconnection approaches such as compliant interconnects typically require lengthy connections and are therefore limited in terms of electrical properties, although expected to meet the mechanical requirements. A novel chip-package interconnection technology is

A proposed holistic approach to on-chip, off-chip, test, and package interconnections

Science.gov (United States)

Bartelink, Dirk J.

1998-11-01

The term interconnection has traditionally implied a `robust' connection from a transistor or a group of transistors in an IC to the outside world, usually a PC board. Optimum system utilization is done from outside the IC. As an alternative, this paper addresses `unimpeded' transistor-to-transistor interconnection aimed at reaching the high circuit densities and computational capabilities of neighboring IC's. In this view, interconnections are not made to some human-centric place outside the IC world requiring robustness—except for system input and output connections. This unimpeded interconnect style is currently available only through intra-chip signal traces in `system-on-a-chip' implementations, as exemplified by embedded DRAMs. Because the traditional off-chip penalty in performance and wiring density is so large, a merging of complex process technologies is the only option today. It is suggested that, for system integration to move forward, the traditional robustness requirement inherited from conventional packaging interconnect and IC manufacturing test must be discarded. Traditional system assembly from vendor parts requires robustness under shipping, inspection and assembly. The trend toward systems on a chip signifies willingness by semiconductor companies to design and fabricate whole systems in house, so that `in-house' chip-to-chip assembly is not beyond reach. In this scenario, bare chips never leave the controlled environment of the IC fabricator while the two major contributors to off-chip signal penalty, ESD protection and the need to source a 50-ohm test head, are avoided. With in-house assembly, ESD protection can be eliminated with the precautions already familiar in plasma etching. Test interconnection impacts the fundamentals of IC manufacturing, particularly with clock speeds approaching 1GHz, and cannot be an afterthought. It should be an integral part of the chip-to-chip interconnection bandwidth optimization, because—as we must

Interface thermal characteristics of flip chip packages - A numerical study

International Nuclear Information System (INIS)

Kandasamy, Ravi; Mujumdar, A.S.

2009-01-01

Flip chip ball grid array (FC-BGA) packages are commonly used for high inputs/outputs (I/O) ICs; they have been proven to provide good solutions for a variety of applications to maximize thermal and electrical performance. A fundamental limitation to such devices is the thermal resistance at the top of the package, which is characterized θ JC parameter. The die-to-lid interface thermal resistance is identified as a critical issue for the thermal management of electronic packages. This paper focuses on the effect of the interface material property changes on the interface thermal resistance. The effect of package's junction to case (Theta-JC or θ JC ) thermal performance is investigated for bare die, flat lid and cup lid packages using a validated thermal model. Thermal performance of a cup or flat lid attached and bare die packages were investigated for different interface materials. Improved Theta-JC performance was observed for the large die as compared to the smaller die. Several parametric studies were carried out to understand the effects of interface bond line thickness (BLT), different die sizes, the average void size during assembly and thermal conductivity of interface materials on package thermal resistance

Microelectronic packaging

CERN Document Server

Datta, M; Schultze, J Walter

2004-01-01

Microelectronic Packaging analyzes the massive impact of electrochemical technologies on various levels of microelectronic packaging. Traditionally, interconnections within a chip were considered outside the realm of packaging technologies, but this book emphasizes the importance of chip wiring as a key aspect of microelectronic packaging, and focuses on electrochemical processing as an enabler of advanced chip metallization.Divided into five parts, the book begins by outlining the basics of electrochemical processing, defining the microelectronic packaging hierarchy, and emphasizing the impac

Materials for advanced packaging

CERN Document Server

Wong, CP

2017-01-01

This second edition continues to be the most comprehensive review on the developments in advanced electronic packaging technologies, with a focus on materials and processing. Recognized experts in the field contribute to 22 updated and new chapters that provide comprehensive coverage on various 3D package architectures, novel bonding and joining techniques, wire bonding, wafer thinning techniques, organic substrates, and novel approaches to make electrical interconnects between integrated circuit and substrates. Various chapters also address advances in several key packaging materials, including: Lead-free solders Flip chip underfills Epoxy molding compounds Conductive adhesives Die attach adhesives/films Thermal interface materials (TIMS) Materials for fabricating embedded passives including capacitors, inductors, and resistors Materials and processing aspects on wafer-level chip scale package (CSP) and MicroElectroMechanical system (MEMS) Contributors also review new and emerging technologies such as Light ...

The Chip-Scale Atomic Clock - Recent Development Progress

Science.gov (United States)

2004-09-01

35th Annual Precise Time and Time Interval (PTTI) Meeting 467 THE CHIP-SCALE ATOMIC CLOCK – RECENT DEVELOPMENT PROGRESS R. Lutwak ...1] R. Lutwak , et al., 2003, “The Chip-Scale Atomic Clock – Coherent Population Trapping vs. Conventional Interrogation,” in

The Chip-Scale Atomic Clock - Prototype Evaluation

Science.gov (United States)

2007-11-01

39th Annual Precise Time and Time Interval (PTTI) Meeting THE CHIP-SCALE ATOMIC CLOCK – PROTOTYPE EVALUATION R. Lutwak *, A. Rashed...been supported by the Defense Advanced Research Projects Agency, Contract # NBCHC020050. REFERENCES [1] R. Lutwak , D. Emmons, W. Riley, and...D.C.), pp. 539-550. [2] R. Lutwak , D. Emmons, T. English, W. Riley, A. Duwel, M. Varghese, D. K. Serkland, and G. M. Peake, 2004, “The Chip-Scale

Wafer-level chip-scale packaging analog and power semiconductor applications

CERN Document Server

Qu, Shichun

2015-01-01

This book presents a state-of-art and in-depth overview in analog and power WLCSP design, material characterization, reliability, and modeling. Recent advances in analog and power electronic WLCSP packaging are presented based on the development of analog technology and power device integration. The book covers in detail how advances in semiconductor content, analog and power advanced WLCSP design, assembly, materials, and reliability have co-enabled significant advances in fan-in and fan-out with redistributed layer (RDL) of analog and power device capability during recent years. Along with new analog and power WLCSP development, the role of modeling is a key to assure successful package design. An overview of the analog and power WLCSP modeling and typical thermal, electrical, and stress modeling methodologies is also provided. This book also: ·         Covers the development of wafer-level power discrete packaging with regular wafer-level design concepts and directly bumping technology ·    �...

Numerical Analysis of Warpage Induced by Thermo-Compression Bonding Process of Cu Pillar Bump Flip Chip Package

Energy Technology Data Exchange (ETDEWEB)

Kwon, Oh Young; Jung, Hoon Sun; Lee, Jung Hoon; Choa, Sung-Hoon [Seoul Nat’l Univ. of Science and Technology, Seoul (Korea, Republic of)

2017-06-15

In flip chip technology, the conventional solder bump has been replaced with a copper (Cu) pillar bump owing to its higher input/output (I/O) density, finer pitch, and higher reliability. However, Cu pillar bump technology faces several issues, such as interconnect shorting and higher low-k stress due to stiffer Cu pillar structure when the conventional reflow process is used. Therefore, the thermal compression bonding (TCB) process has been adopted in the flip chip attachment process in order to reduce the package warpage and stress. In this study, we investigated the package warpage induced during the TCB process using a numerical analysis. The warpage of the TCB process was compared with that of the reflow process.

Characterization of integrated circuit packaging materials

CERN Document Server

Moore, Thomas

1993-01-01

Chapters in this volume address important characteristics of IC packages. Analytical techniques appropriate for IC package characterization are demonstrated through examples of the measurement of critical performance parameters and the analysis of key technological problems of IC packages. Issues are discussed which affect a variety of package types, including plastic surface-mount packages, hermetic packages, and advanced designs such as flip-chip, chip-on-board and multi-chip models.

Integrated microsystems packaging approach with LCP

Science.gov (United States)

Jaynes, Paul; Shacklette, Lawrence W.

2006-05-01

Within the government communication market there is an increasing push to further miniaturize systems with the use of chip-scale packages, flip-chip bonding, and other advances over traditional packaging techniques. Harris' approach to miniaturization includes these traditional packaging advances, but goes beyond this level of miniaturization by combining the functional and structural elements of a system, thus creating a Multi-Functional Structural Circuit (MFSC). An emerging high-frequency, near hermetic, thermoplastic electronic substrate material, Liquid Crystal Polymer (LCP), is the material that will enable the combination of the electronic circuit and the physical structure of the system. The first embodiment of this vision for Harris is the development of a battlefield acoustic sensor module. This paper will introduce LCP and its advantages for MFSC, present an example of the work that Harris has performed, and speak to LCP MFSCs' potential benefits to miniature communications modules and sensor platforms.

The silicon chip: A versatile micro-scale platform for micro- and nano-scale systems

Science.gov (United States)

Choi, Edward

Cutting-edge advances in micro- and nano-scale technology require instrumentation to interface with the external world. While technology feature sizes are continually being reduced, the size of experimentalists and their instrumentation do not mirror this trend. Hence there is a need for effective application-specific instrumentation to bridge the gap from the micro and nano-scale phenomena being studied to the comparative macro-scale of the human interfaces. This dissertation puts forward the idea that the silicon CMOS integrated circuit, or microchip in short, serves as an excellent platform to perform this functionality. The electronic interfaces designed for the semiconductor industry are particularly attractive as development platforms, and the reduction in feature sizes that has been a hallmark of the industry suggests that chip-scale instrumentation may be more closely coupled to the phenomena of interest, allowing finer control or improved measurement capabilities. Compatibility with commercial processes will further enable economies of scale through mass production, another welcome feature of this approach. Thus chip-scale instrumentation may replace the bulky, expensive, cumbersome-to-operate macro-scale prototypes currently in use for many of these applications. The dissertation examines four specific applications in which the chip may serve as the ideal instrumentation platform. These are nanorod manipulation, polypyrrole bilayer hinge microactuator control, organic transistor hybrid circuits, and contact fluorescence imaging. The thesis is structured around chapters devoted to each of these projects, in addition to a chapter on preliminary work on an RFID system that serves as a wireless interface model. Each of these chapters contains tools and techniques developed for chip-scale instrumentation, from custom scripts for automated layout and data collection to microfabrication processes. Implementation of these tools to develop systems for the

Experimental and theoretical analyses of package-on-package structure under three-point bending loading

International Nuclear Information System (INIS)

Jia Su; Wang Xi-Shu; Ren Huai-Hui

2012-01-01

High density packaging is developing toward miniaturization and integration, which causes many difficulties in designing, manufacturing, and reliability testing. Package-on-Package (PoP) is a promising three-dimensional high-density packaging method that integrates a chip scale package (CSP) in the top package and a fine-pitch ball grid array (FBGA) in the bottom package. In this paper, in-situ scanning electron microscopy (SEM) observation is carried out to detect the deformation and damage of the PoP structure under three-point bending loading. The results indicate that the cracks occur in the die of the top package, then cause the crack deflection and bridging in the die attaching layer. Furthermore, the mechanical principles are used to analyse the cracking process of the PoP structure based on the multi-layer laminating hypothesis and the theoretical analysis results are found to be in good agreement with the experimental results. (condensed matter: structural, mechanical, and thermal properties)

SCALE criticality safety verification and validation package

International Nuclear Information System (INIS)

Bowman, S.M.; Emmett, M.B.; Jordan, W.C.

1998-01-01

Verification and validation (V and V) are essential elements of software quality assurance (QA) for computer codes that are used for performing scientific calculations. V and V provides a means to ensure the reliability and accuracy of such software. As part of the SCALE QA and V and V plans, a general V and V package for the SCALE criticality safety codes has been assembled, tested and documented. The SCALE criticality safety V and V package is being made available to SCALE users through the Radiation Safety Information Computational Center (RSICC) to assist them in performing adequate V and V for their SCALE applications

Co-Design Method and Wafer-Level Packaging Technique of Thin-Film Flexible Antenna and Silicon CMOS Rectifier Chips for Wireless-Powered Neural Interface Systems

Directory of Open Access Journals (Sweden)

Kenji Okabe

2015-12-01

Full Text Available In this paper, a co-design method and a wafer-level packaging technique of a flexible antenna and a CMOS rectifier chip for use in a small-sized implantable system on the brain surface are proposed. The proposed co-design method optimizes the system architecture, and can help avoid the use of external matching components, resulting in the realization of a small-size system. In addition, the technique employed to assemble a silicon large-scale integration (LSI chip on the very thin parylene film (5 μm enables the integration of the rectifier circuits and the flexible antenna (rectenna. In the demonstration of wireless power transmission (WPT, the fabricated flexible rectenna achieved a maximum efficiency of 0.497% with a distance of 3 cm between antennas. In addition, WPT with radio waves allows a misalignment of 185% against antenna size, implying that the misalignment has a less effect on the WPT characteristics compared with electromagnetic induction.

Co-Design Method and Wafer-Level Packaging Technique of Thin-Film Flexible Antenna and Silicon CMOS Rectifier Chips for Wireless-Powered Neural Interface Systems.

Science.gov (United States)

Okabe, Kenji; Jeewan, Horagodage Prabhath; Yamagiwa, Shota; Kawano, Takeshi; Ishida, Makoto; Akita, Ippei

2015-12-16

In this paper, a co-design method and a wafer-level packaging technique of a flexible antenna and a CMOS rectifier chip for use in a small-sized implantable system on the brain surface are proposed. The proposed co-design method optimizes the system architecture, and can help avoid the use of external matching components, resulting in the realization of a small-size system. In addition, the technique employed to assemble a silicon large-scale integration (LSI) chip on the very thin parylene film (5 μm) enables the integration of the rectifier circuits and the flexible antenna (rectenna). In the demonstration of wireless power transmission (WPT), the fabricated flexible rectenna achieved a maximum efficiency of 0.497% with a distance of 3 cm between antennas. In addition, WPT with radio waves allows a misalignment of 185% against antenna size, implying that the misalignment has a less effect on the WPT characteristics compared with electromagnetic induction.

On-chip photonic interconnects a computer architect's perspective

CERN Document Server

Nitta, Christopher J; Akella, Venkatesh

2013-01-01

As the number of cores on a chip continues to climb, architects will need to address both bandwidth and power consumption issues related to the interconnection network. Electrical interconnects are not likely to scale well to a large number of processors for energy efficiency reasons, and the problem is compounded by the fact that there is a fixed total power budget for a die, dictated by the amount of heat that can be dissipated without special (and expensive) cooling and packaging techniques. Thus, there is a need to seek alternatives to electrical signaling for on-chip interconnection appli

Long-Term Stability of NIST Chip-Scale Atomic Clock Physics Packages

Science.gov (United States)

2007-01-01

vacuum packaging), as has been demonstrated by Lutwak et al. [3]. Nevertheless, we tried to investigate the causes for the frequency shifts of...stability,” Optics Express, 13, 1249-1253. [3] R. Lutwak , J. Deng, W. Riley, M. Varghese, J. Leblanc, G. Tepolt, M. Mescher, D. K. Serkland, K. M. Geib...the 1st Annual Multiconference on Electronics and Photonics, 7-11 November 2006, Guanajuato, Mexico, in press. [6] R. Lutwak , P. Vlitas, M

5GHz LTCC-based aperture coupled wireless transmitter for system-on-package applications

KAUST Repository

Shamim, Atif

2012-01-01

A novel System-on-Package (SoP) implementation is presented for a transmitter (TX) module which makes use of electromagnetic coupling between the TX chip and the package antenna. The TX chip is realized in 0.13μm CMOS process and comprises an on-chip antenna, which serves as the oscillator\\'s inductor as well. The TX chip is housed in a Low Temperature Co-fired Ceramic (LTCC) package with a patch antenna. The on-chip antenna feeds the LTCC patch antenna through aperture coupling, thus negating the need for RF buffer amplifiers, matching elements, baluns, bond wires and package transmission lines. This is the first ever demonstration of wireless-interconnect between on-chip and package antennas which increases the gain and range of the TX module manyfold with respect to the on-chip antenna alone. Though the range of the TX SoP increases considerably, power consumption remains the same as that of the TX chip only. A simple analytical model for the new wireless-interconnect has been developed which helps determine the optimum position of the chip with respect to the aperture in the ground plane.

5GHz LTCC-based aperture coupled wireless transmitter for system-on-package applications

KAUST Repository

Shamim, Atif; Arsalan, Muhammad; Hojjat, Nasrin; Roy, Langis

2012-01-01

A novel System-on-Package (SoP) implementation is presented for a transmitter (TX) module which makes use of electromagnetic coupling between the TX chip and the package antenna. The TX chip is realized in 0.13μm CMOS process and comprises an on-chip antenna, which serves as the oscillator's inductor as well. The TX chip is housed in a Low Temperature Co-fired Ceramic (LTCC) package with a patch antenna. The on-chip antenna feeds the LTCC patch antenna through aperture coupling, thus negating the need for RF buffer amplifiers, matching elements, baluns, bond wires and package transmission lines. This is the first ever demonstration of wireless-interconnect between on-chip and package antennas which increases the gain and range of the TX module manyfold with respect to the on-chip antenna alone. Though the range of the TX SoP increases considerably, power consumption remains the same as that of the TX chip only. A simple analytical model for the new wireless-interconnect has been developed which helps determine the optimum position of the chip with respect to the aperture in the ground plane.

Automating dChip: toward reproducible sharing of microarray data analysis

Directory of Open Access Journals (Sweden)

Li Cheng

2008-05-01

Full Text Available Abstract Background During the past decade, many software packages have been developed for analysis and visualization of various types of microarrays. We have developed and maintained the widely used dChip as a microarray analysis software package accessible to both biologist and data analysts. However, challenges arise when dChip users want to analyze large number of arrays automatically and share data analysis procedures and parameters. Improvement is also needed when the dChip user support team tries to identify the causes of reported analysis errors or bugs from users. Results We report here implementation and application of the dChip automation module. Through this module, dChip automation files can be created to include menu steps, parameters, and data viewpoints to run automatically. A data-packaging function allows convenient transfer from one user to another of the dChip software, microarray data, and analysis procedures, so that the second user can reproduce the entire analysis session of the first user. An analysis report file can also be generated during an automated run, including analysis logs, user comments, and viewpoint screenshots. Conclusion The dChip automation module is a step toward reproducible research, and it can prompt a more convenient and reproducible mechanism for sharing microarray software, data, and analysis procedures and results. Automation data packages can also be used as publication supplements. Similar automation mechanisms could be valuable to the research community if implemented in other genomics and bioinformatics software packages.

Transportable GPU (General Processor Units) chip set technology for standard computer architectures

Science.gov (United States)

Fosdick, R. E.; Denison, H. C.

1982-11-01

The USAFR-developed GPU Chip Set has been utilized by Tracor to implement both USAF and Navy Standard 16-Bit Airborne Computer Architectures. Both configurations are currently being delivered into DOD full-scale development programs. Leadless Hermetic Chip Carrier packaging has facilitated implementation of both architectures on single 41/2 x 5 substrates. The CMOS and CMOS/SOS implementations of the GPU Chip Set have allowed both CPU implementations to use less than 3 watts of power each. Recent efforts by Tracor for USAF have included the definition of a next-generation GPU Chip Set that will retain the application-proven architecture of the current chip set while offering the added cost advantages of transportability across ISO-CMOS and CMOS/SOS processes and across numerous semiconductor manufacturers using a newly-defined set of common design rules. The Enhanced GPU Chip Set will increase speed by an approximate factor of 3 while significantly reducing chip counts and costs of standard CPU implementations.

Miniature stick-packaging--an industrial technology for pre-storage and release of reagents in lab-on-a-chip systems.

Science.gov (United States)

van Oordt, Thomas; Barb, Yannick; Smetana, Jan; Zengerle, Roland; von Stetten, Felix

2013-08-07

Stick-packaging of goods in tubular-shaped composite-foil pouches has become a popular technology for food and drug packaging. We miniaturized stick-packaging for use in lab-on-a-chip (LOAC) systems to pre-store and on-demand release the liquid and dry reagents in a volume range of 80-500 μl. An integrated frangible seal enables the pressure-controlled release of reagents and simplifies the layout of LOAC systems, thereby making the package a functional microfluidic release unit. The frangible seal is adjusted to defined burst pressures ranging from 20 to 140 kPa. The applied ultrasonic welding process allows the packaging of temperature sensitive reagents. Stick-packs have been successfully tested applying recovery tests (where 99% (STDV = 1%) of 250 μl pre-stored liquid is released), long-term storage tests (where there is loss of only <0.5% for simulated 2 years) and air transport simulation tests. The developed technology enables the storage of a combination of liquid and dry reagents. It is a scalable technology suitable for rapid prototyping and low-cost mass production.

Photometric and Colorimetric Assessment of LED Chip Scale Packages by Using a Step-Stress Accelerated Degradation Test (SSADT) Method.

Science.gov (United States)

Qian, Cheng; Fan, Jiajie; Fang, Jiayi; Yu, Chaohua; Ren, Yi; Fan, Xuejun; Zhang, Guoqi

2017-10-16

By solving the problem of very long test time on reliability qualification for Light-emitting Diode (LED) products, the accelerated degradation test with a thermal overstress at a proper range is regarded as a promising and effective approach. For a comprehensive survey of the application of step-stress accelerated degradation test (SSADT) in LEDs, the thermal, photometric, and colorimetric properties of two types of LED chip scale packages (CSPs), i.e., 4000 °K and 5000 °K samples each of which was driven by two different levels of currents (i.e., 120 mA and 350 mA, respectively), were investigated under an increasing temperature from 55 °C to 150 °C and a systemic study of driving current effect on the SSADT results were also reported in this paper. During SSADT, junction temperatures of the test samples have a positive relationship with their driving currents. However, the temperature-voltage curve, which represents the thermal resistance property of the test samples, does not show significant variance as long as the driving current is no more than the sample's rated current. But when the test sample is tested under an overdrive current, its temperature-voltage curve is observed as obviously shifted to the left when compared to that before SSADT. Similar overdrive current affected the degradation scenario is also found in the attenuation of Spectral Power Distributions (SPDs) of the test samples. As used in the reliability qualification, SSADT provides explicit scenes on color shift and correlated color temperature (CCT) depreciation of the test samples, but not on lumen maintenance depreciation. It is also proved that the varying rates of the color shift and CCT depreciation failures can be effectively accelerated with an increase of the driving current, for instance, from 120 mA to 350 mA. For these reasons, SSADT is considered as a suitable accelerated test method for qualifying these two failure modes of LED CSPs.

Photometric and Colorimetric Assessment of LED Chip Scale Packages by Using a Step-Stress Accelerated Degradation Test (SSADT) Method

Science.gov (United States)

Yu, Chaohua; Fan, Xuejun; Zhang, Guoqi

2017-01-01

By solving the problem of very long test time on reliability qualification for Light-emitting Diode (LED) products, the accelerated degradation test with a thermal overstress at a proper range is regarded as a promising and effective approach. For a comprehensive survey of the application of step-stress accelerated degradation test (SSADT) in LEDs, the thermal, photometric, and colorimetric properties of two types of LED chip scale packages (CSPs), i.e., 4000 °K and 5000 °K samples each of which was driven by two different levels of currents (i.e., 120 mA and 350 mA, respectively), were investigated under an increasing temperature from 55 °C to 150 °C and a systemic study of driving current effect on the SSADT results were also reported in this paper. During SSADT, junction temperatures of the test samples have a positive relationship with their driving currents. However, the temperature-voltage curve, which represents the thermal resistance property of the test samples, does not show significant variance as long as the driving current is no more than the sample’s rated current. But when the test sample is tested under an overdrive current, its temperature-voltage curve is observed as obviously shifted to the left when compared to that before SSADT. Similar overdrive current affected the degradation scenario is also found in the attenuation of Spectral Power Distributions (SPDs) of the test samples. As used in the reliability qualification, SSADT provides explicit scenes on color shift and correlated color temperature (CCT) depreciation of the test samples, but not on lumen maintenance depreciation. It is also proved that the varying rates of the color shift and CCT depreciation failures can be effectively accelerated with an increase of the driving current, for instance, from 120 mA to 350 mA. For these reasons, SSADT is considered as a suitable accelerated test method for qualifying these two failure modes of LED CSPs. PMID:29035300

Ceramic packages for liquid-nitrogen operation

International Nuclear Information System (INIS)

Tong, H.M.; Yeh, H.L.; Goldblatt, R.D.

1989-01-01

To evaluate their compatibility for use in a liquid-nitrogen computer, metallized ceramic packages with test chips joined using IBM controlled-collapse solder (Pb-Sn) technology have been cycled between 30 0 C and liquid-nitrogen temperature. Room-temperature electrical resistance measurements were made at regular intervals of cycles to determine whether solder failure accompanied by a significant resistance increase had occurred. For the failed solder joints characterized by the highest thermal shear strain amplitude of 3.3 percent, the authors were able to estimate the number of liquid-nitrogen cycles needed to produce the corresponding failure rate using a room-temperature solder lifetime model. Cross-sectional examination of the failed solder joints using scanning electron microscopy and energy dispersive X-ray analysis indicated solder cracking occurring at the solder-ceramic interface. Chip pull tests on cycled packages yielded strengths far exceeding the minimal requirement. Mechanisms involving the formation of intermetallics were proposed to account for the observed solder fracture modes after liquid-nitrogen cycling and after chip pull. Furthermore, scanning electron microscopic examination of pulled chips in cycled packages showed no apparent sign of cracking in quartz and polyimide for chip insulation

RF-Interrogated End-State Chip-Scale Atomic Clock

Science.gov (United States)

2007-11-01

coherent population trapping,” Electronics Letters 37, (24), 1449-1451. [2] R. Lutwak , P. Vlitas, M. Varghese, M. Mescher, D. K. Serkland, and G. M...367. [9] R. Lutwak , D. Emmons, T. English, W. Riley, A. Duwel, M. Varghese, D. K. Serland, and G. M. Peake, 2003, “Chip-Scale Atomic Clock, Recent

Packaged integrated opto-fluidic solution for harmful fluid analysis

Science.gov (United States)

Allenet, T.; Bucci, D.; Geoffray, F.; Canto, F.; Couston, L.; Jardinier, E.; Broquin, J.-E.

2016-02-01

Advances in nuclear fuel reprocessing have led to a surging need for novel chemical analysis tools. In this paper, we present a packaged lab-on-chip approach with co-integration of optical and micro-fluidic functions on a glass substrate as a solution. A chip was built and packaged to obtain light/fluid interaction in order for the entire device to make spectral measurements using the photo spectroscopy absorption principle. The interaction between the analyte solution and light takes place at the boundary between a waveguide and a fluid micro-channel thanks to the evanescent part of the waveguide's guided mode that propagates into the fluid. The waveguide was obtained via ion exchange on a glass wafer. The input and the output of the waveguides were pigtailed with standard single mode optical fibers. The micro-scale fluid channel was elaborated with a lithography procedure and hydrofluoric acid wet etching resulting in a 150+/-8 μm deep channel. The channel was designed with fluidic accesses, in order for the chip to be compatible with commercial fluidic interfaces/chip mounts. This allows for analyte fluid in external capillaries to be pumped into the device through micro-pipes, hence resulting in a fully packaged chip. In order to produce this co-integrated structure, two substrates were bonded. A study of direct glass wafer-to-wafer molecular bonding was carried-out to improve detector sturdiness and durability and put forward a bonding protocol with a bonding surface energy of γ>2.0 J.m-2. Detector viability was shown by obtaining optical mode measurements and detecting traces of 1.2 M neodymium (Nd) solute in 12+/-1 μL of 0.01 M and pH 2 nitric acid (HNO3) solvent by obtaining an absorption peak specific to neodymium at 795 nm.

Scale-up considerations relevant to experimental studies of nuclear waste-package behavior

International Nuclear Information System (INIS)

Coles, D.G.; Peters, R.D.

1986-04-01

Results from a study that investigated whether testing large-scale nuclear waste-package assemblages was technically warranted are reported. It was recognized that the majority of the investigations for predicting waste-package performance to date have relied primarily on laboratory-scale experimentation. However, methods for the successful extrapolation of the results from such experiments, both geometrically and over time, to actual repository conditions have not been well defined. Because a well-developed scaling technology exists in the chemical-engineering discipline, it was presupposed that much of this technology could be applicable to the prediction of waste-package performance. A review of existing literature documented numerous examples where a consideration of scaling technology was important. It was concluded that much of the existing scale-up technology is applicable to the prediction of waste-package performance for both size and time extrapolations and that conducting scale-up studies may be technically merited. However, the applicability for investigating the complex chemical interactions needs further development. It was recognized that the complexity of the system, and the long time periods involved, renders a completely theoretical approach to performance prediction almost hopeless. However, a theoretical and experimental study was defined for investigating heat and fluid flow. It was concluded that conducting scale-up modeling and experimentation for waste-package performance predictions is possible using existing technology. A sequential series of scaling studies, both theoretical and experimental, will be required to formulate size and time extrapolations of waste-package performance

Nutrition labelling, marketing techniques, nutrition claims and health claims on chip and biscuit packages from sixteen countries.

Science.gov (United States)

Mayhew, Alexandra J; Lock, Karen; Kelishadi, Roya; Swaminathan, Sumathi; Marcilio, Claudia S; Iqbal, Romaina; Dehghan, Mahshid; Yusuf, Salim; Chow, Clara K

2016-04-01

Food packages were objectively assessed to explore differences in nutrition labelling, selected promotional marketing techniques and health and nutrition claims between countries, in comparison to national regulations. Cross-sectional. Chip and sweet biscuit packages were collected from sixteen countries at different levels of economic development in the EPOCH (Environmental Profile of a Community's Health) study between 2008 and 2010. Seven hundred and thirty-seven food packages were systematically evaluated for nutrition labelling, selected promotional marketing techniques relevant to nutrition and health, and health and nutrition claims. We compared pack labelling in countries with labelling regulations, with voluntary regulations and no regulations. Overall 86 % of the packages had nutrition labels, 30 % had health or nutrition claims and 87 % displayed selected marketing techniques. On average, each package displayed two marketing techniques and one health or nutrition claim. In countries with mandatory nutrition labelling a greater proportion of packages displayed nutrition labels, had more of the seven required nutrients present, more total nutrients listed and higher readability compared with those with voluntary or no regulations. Countries with no health or nutrition claim regulations had fewer claims per package compared with countries with regulations. Nutrition label regulations were associated with increased prevalence and quality of nutrition labels. Health and nutrition claim regulations were unexpectedly associated with increased use of claims, suggesting that current regulations may not have the desired effect of protecting consumers. Of concern, lack of regulation was associated with increased promotional marketing techniques directed at children and misleadingly promoting broad concepts of health.

Kinetic model for torrefaction of wood chips in a pilot-scale continuous reactor

DEFF Research Database (Denmark)

Shang, Lei; Ahrenfeldt, Jesper; Holm, Jens Kai

2014-01-01

accordance with the model data. In an additional step a continuous, pilot scale reactor was built to produce torrefied wood chips in large quantities. The "two-step reaction in series" model was applied to predict the mass yield of the torrefaction reaction. Parameters used for the calculation were...... at different torrefaction temperatures, it was possible to predict the HHV of torrefied wood chips from the pilot reactor. The results from this study and the presented modeling approach can be used to predict the product quality from pilot scale torrefaction reactors based on small scale experiments and could...

Development of Equivalent Material Properties of Microbump for Simulating Chip Stacking Packaging

Directory of Open Access Journals (Sweden)

Chang-Chun Lee

2015-08-01

Full Text Available three-dimensional integrated circuit (3D-IC structure with a significant scale mismatch causes difficulty in analytic model construction. This paper proposes a simulation technique to introduce an equivalent material composed of microbumps and their surrounding wafer level underfill (WLUF. The mechanical properties of this equivalent material, including Young’s modulus (E, Poisson’s ratio, shear modulus, and coefficient of thermal expansion (CTE, are directly obtained by applying either a tensile load or a constant displacement, and by increasing the temperature during simulations, respectively. Analytic results indicate that at least eight microbumps at the outermost region of the chip stacking structure need to be considered as an accurate stress/strain contour in the concerned region. In addition, a factorial experimental design with analysis of variance is proposed to optimize chip stacking structure reliability with four factors: chip thickness, substrate thickness, CTE, and E-value. Analytic results show that the most significant factor is CTE of WLUF. This factor affects microbump reliability and structural warpage under a temperature cycling load and high-temperature bonding process. WLUF with low CTE and high E-value are recommended to enhance the assembly reliability of the 3D-IC architecture.

Mechanism of Void Prediction in Flip Chip Packages with Molded Underfill

Science.gov (United States)

Wu, Kuo-Tsai; Hwang, Sheng-Jye; Lee, Huei-Huang

2017-08-01

Voids have always been present using the molded underfill (MUF) package process, which is a problem that needs further investigation. In this study, the process was studied using the Moldex3D numerical analysis software. The effects of gas (air vent effect) on the overall melt front were also considered. In this isothermal process containing two fluids, the gas and melt colloid interact in the mold cavity. Simulation enabled an appropriate understanding of the actual situation to be gained, and, through analysis, the void region and exact location of voids were predicted. First, the global flow end area was observed to predict the void movement trend, and then the local flow ends were observed to predict the location and size of voids. In the MUF 518 case study, simulations predicted the void region as well as the location and size of the voids. The void phenomenon in a flip chip ball grid array underfill is discussed as part of the study.

3D packaging of a microfluidic system with sensory applications

Science.gov (United States)

Morrissey, Anthony; Kelly, Gerard; Alderman, John C.

1997-09-01

Among the main benefits of microsystem technology are its contributions to cost reductio, reliability and improved performance. however, the packaging of microsystems, and particularly microsensor, has proven to be one of the biggest limitations to their commercialization and the packaging of silicon sensor devices can be the most costly part of their fabrication. This paper describes the integration of 3D packaging of a microsystem. Central to the operation of the 3D demonstrator is a micromachined silicon membrane pump to supply fluids to a sensing chamber constructed about the active area of a sensor chip. This chip carries ISFET based chemical sensors, pressure sensors and thermal sensors. The electronics required for controlling and regulating the activity of the various sensors ar also available on this chip and as other chips in the 3D assembly. The demonstrator also contains a power supply module with optical fiber interconnections. All of these modules are integrated into a single plastic- encapsulated 3D vertical multichip module. The reliability of such a structure, initially proposed by Val was demonstrated by Barrett et al. An additional module available for inclusion in some of our assemblies is a test chip capable of measuring the packaging-induced stress experienced during and after assembly. The packaging process described produces a module with very high density and utilizes standard off-the-shelf components to minimize costs. As the sensor chip and micropump include micromachined silicon membranes and microvalves, the packaging of such structures has to allow consideration for the minimization of the packaging-induced stresses. With this in mind, low stress techniques, including the use of soft glob-top materials, were employed.

MEMS packaging: state of the art and future trends

Science.gov (United States)

Bossche, Andre; Cotofana, Carmen V. B.; Mollinger, Jeff R.

1998-07-01

Now that the technology for Integrated sensor and MEMS devices has become sufficiently mature to allow mass production, it is expected that the prices of bare chips will drop dramatically. This means that the package prices will become a limiting factor in market penetration, unless low cost packaging solutions become available. This paper will discuss the developments in packaging technology. Both single-chip and multi-chip packaging solutions will be addressed. It first starts with a discussion on the different requirements that have to be met; both from a device point of view (open access paths to the environment, vacuum cavities, etc.) and from the application point of view (e.g. environmental hostility). Subsequently current technologies are judged on their applicability for MEMS and sensor packaging and a forecast is given for future trends. It is expected that the large majority of sensing devices will be applied in relative friendly environments for which plastic packages would suffice. Therefore, on the short term an important role is foreseen for recently developed plastic packaging techniques such as precision molding and precision dispensing. Just like in standard electronic packaging, complete wafer level packaging methods for sensing devices still have a long way to go before they can compete with the highly optimized and automated plastic packaging processes.

A novel bonding method for large scale poly(methyl methacrylate) micro- and nanofluidic chip fabrication

Science.gov (United States)

Qu, Xingtian; Li, Jinlai; Yin, Zhifu

2018-04-01

Micro- and nanofluidic chips are becoming increasing significance for biological and medical applications. Future advances in micro- and nanofluidics and its utilization in commercial applications depend on the development and fabrication of low cost and high fidelity large scale plastic micro- and nanofluidic chips. However, the majority of the present fabrication methods suffer from a low bonding rate of the chip during thermal bonding process due to air trapping between the substrate and the cover plate. In the present work, a novel bonding technique based on Ar plasma and water treatment was proposed to fully bond the large scale micro- and nanofluidic chips. The influence of Ar plasma parameters on the water contact angle and the effect of bonding conditions on the bonding rate and the bonding strength of the chip were studied. The fluorescence tests demonstrate that the 5 × 5 cm2 poly(methyl methacrylate) chip with 180 nm wide and 180 nm deep nanochannels can be fabricated without any block and leakage by our newly developed method.

Chip-to-Chip Half Duplex Spiking Data Communication over Power Supply Rails

Science.gov (United States)

Hashida, Takushi; Nagata, Makoto

Chip-to-chip serial data communication is superposed on power supply over common Vdd/Vss connections through chip, package, and board traces. A power line transceiver demonstrates half duplex spiking communication at more than 100Mbps. A pair of transceivers consumes 1.35mA from 3.3V, at 130Mbps. On-chip power line LC low pass filter attenuates pseudo-differential communication spikes by 30dB, purifying power supply current for internal circuits. Bi-directional spiking communication was successfully examined in a 90-nm CMOS prototype setup of on-chip waveform capturing. A micro controller forwards clock pulses to and receives data streams from a comparator based waveform capturer formed on a different chip, through a single pair of power and ground traces. The bit error rate is small enough not to degrade waveform acquisition capability, maintaining the spurious free dynamic range of higher than 50dB.

Packaging Technologies for High Temperature Electronics and Sensors

Science.gov (United States)

Chen, Liangyu; Hunter, Gary W.; Neudeck, Philip G.; Beheim, Glenn M.; Spry, David J.; Meredith, Roger D.

2013-01-01

This paper reviews ceramic substrates and thick-film metallization based packaging technologies in development for 500degC silicon carbide (SiC) electronics and sensors. Prototype high temperature ceramic chip-level packages and printed circuit boards (PCBs) based on ceramic substrates of aluminum oxide (Al2O3) and aluminum nitride (AlN) have been designed and fabricated. These ceramic substrate-based chiplevel packages with gold (Au) thick-film metallization have been electrically characterized at temperatures up to 550degC. A 96% alumina based edge connector for a PCB level subsystem interconnection has also been demonstrated recently. The 96% alumina packaging system composed of chip-level packages and PCBs has been tested with high temperature SiC devices at 500degC for over 10,000 hours. In addition to tests in a laboratory environment, a SiC JFET with a packaging system composed of a 96% alumina chip-level package and an alumina printed circuit board mounted on a data acquisition circuit board was launched as a part of the MISSE-7 suite to the International Space Station via a Shuttle mission. This packaged SiC transistor was successfully tested in orbit for eighteen months. A spark-plug type sensor package designed for high temperature SiC capacitive pressure sensors was developed. This sensor package combines the high temperature interconnection system with a commercial high temperature high pressure stainless steel seal gland (electrical feed-through). Test results of a packaged high temperature capacitive pressure sensor at 500degC are also discussed. In addition to the pressure sensor package, efforts for packaging high temperature SiC diode-based gas chemical sensors are in process.

Packaging of silicon sensors for microfluidic bio-analytical applications

International Nuclear Information System (INIS)

Wimberger-Friedl, Reinhold; Prins, Menno; Megens, Mischa; Dittmer, Wendy; Witz, Christiane de; Nellissen, Ton; Weekamp, Wim; Delft, Jan van; Ansems, Will; Iersel, Ben van

2009-01-01

A new industrial concept is presented for packaging biosensor chips in disposable microfluidic cartridges to enable medical diagnostic applications. The inorganic electronic substrates, such as silicon or glass, are integrated in a polymer package which provides the electrical and fluidic interconnections to the world and provides mechanical strength and protection for out-of-lab use. The demonstrated prototype consists of a molded interconnection device (MID), a silicon-based giant magneto-resistive (GMR) biosensor chip, a flex and a polymer fluidic part with integrated tubing. The various processes are compatible with mass manufacturing and run at a high yield. The devices show a reliable electrical interconnection between the sensor chip and readout electronics during extended wet operation. Sandwich immunoassays were carried out in the cartridges with surface functionalized sensor chips. Biological response curves were determined for different concentrations of parathyroid hormone (PTH) on the packaged biosensor, which demonstrates the functionality and biocompatibility of the devices. The new packaging concept provides a platform for easy further integration of electrical and fluidic functions, as for instance required for integrated molecular diagnostic devices in cost-effective mass manufacturing

Small-scale, self-propagating combustion realized with on-chip porous silicon.

Science.gov (United States)

Piekiel, Nicholas W; Morris, Christopher J

2015-05-13

For small-scale energy applications, energetic materials represent a high energy density source that, in certain cases, can be accessed with a very small amount of energy input. Recent advances in microprocessing techniques allow for the implementation of a porous silicon energetic material onto a crystalline silicon wafer at the microscale; however, combustion at a small length scale remains to be fully investigated, particularly with regards to the limitations of increased relative heat loss during combustion. The present study explores the critical dimensions of an on-chip porous silicon energetic material (porous silicon + sodium perchlorate (NaClO4)) required to propagate combustion. We etched ∼97 μm wide and ∼45 μm deep porous silicon channels that burned at a steady rate of 4.6 m/s, remaining steady across 90° changes in direction. In an effort to minimize the potential on-chip footprint for energetic porous silicon, we also explored the minimum spacing between porous silicon channels. We demonstrated independent burning of porous silicon channels at a spacing of 0.5 m on a chip surface area of 1.65 cm(2). Smaller porous silicon channels of ∼28 μm wide and ∼14 μm deep were also utilized. These samples propagated combustion, but at times, did so unsteadily. This result may suggest that we are approaching a critical length scale for self-propagating combustion in a porous silicon energetic material.

Crossmodal correspondences in product packaging. Assessing color-flavor correspondences for potato chips (crisps).

Science.gov (United States)

Piqueras-Fiszman, Betina; Spence, Charles

2011-12-01

We report a study designed to investigate consumers' crossmodal associations between the color of packaging and flavor varieties in crisps (potato chips). This product category was chosen because of the long-established but conflicting color-flavor conventions that exist for the salt and vinegar and cheese and onion flavor varieties in the UK. The use of both implicit and explicit measures of this crossmodal association revealed that consumers responded more slowly, and made more errors, when they had to pair the color and flavor that they implicitly thought of as being "incongruent" with the same response key. Furthermore, clustering consumers by the brand that they normally purchased revealed that the main reason why this pattern of results was observed could be their differing acquaintance with one brand versus another. In addition, when participants tried the two types of crisps from "congruently" and "incongruently" colored packets, some were unable to guess the flavor correctly in the latter case. These strong crossmodal associations did not have a significant effect on participants' hedonic appraisal of the crisps, but did arouse confusion. These results are relevant in terms of R&D, since ascertaining the appropriate color of the packaging across flavor varieties ought normally to help achieve immediate product recognition and consumer satisfaction. Copyright © 2011 Elsevier Ltd. All rights reserved.

Package Holds Five Monolithic Microwave Integrated Circuits

Science.gov (United States)

Mysoor, Narayan R.; Decker, D. Richard; Olson, Hilding M.

1996-01-01

Packages protect and hold monolithic microwave integrated circuit (MMIC) chips while providing dc and radio-frequency (RF) electrical connections for chips undergoing development. Required to be compact, lightweight, and rugged. Designed to minimize undesired resonances, reflections, losses, and impedance mismatches.

Study on the Thermal Resistance of Multi-chip Module High Power LED Packaging Heat Dissipation System

Directory of Open Access Journals (Sweden)

Kailin Pan

2014-10-01

Full Text Available Thermal resistance is a key technical index which indicates the thermal management of multi-chip module high power LED (MCM-LED packaging heat dissipation system. In this paper, the prototype structure of MCM-LED packaging heat dissipation system is proposed to study the reliable thermal resistance calculation method. In order to analyze the total thermal resistance of the MCM-LED packaging heat dissipation system, three kinds of thermal resistance calculation method including theoretical calculation, experimental testing and finite element simulation are developed respectively. Firstly, based on the thermal resistance network model and the principle of steady state heat transfer, the theoretical value of total thermal resistance is 6.111 K/W through sum of the thermal resistance of every material layer in the major direction of heat flow. Secondly, the thermal resistance experiment is carried out by T3Ster to obtain the experimental result of total thermal resistance, and the value is 6.729 K/W. Thirdly, a three-dimensional finite element model of MCM-LED packaging heat dissipation system is established, and the junction temperature experiment is also performed to calculated the finite element simulated result of total thermal resistance, the value is 6.99 K/W. Finally, by comparing the error of all the three kinds of result, the error of total thermal resistance between the theoretical value and experimental result is 9.2 %, and the error of total thermal resistance between the experimental result and finite element simulation is only about -3.9 %, meanwhile, the main reason of each error is discussed respectively.

Welding robot package; Arc yosetsu robot package

Energy Technology Data Exchange (ETDEWEB)

Nishikawa, S. [Yaskawa Electric Corp., Kitakyushu (Japan)

1998-09-01

For the conventional high-speed welding robot, the welding current was controlled mainly for reducing the spatters during short circuits and for stabilizing the beads by the periodic short circuits. However, an increase of deposition amount in response to the speed is required for the high-speed welding. Large-current low-spatter welding current region control was added. Units were integrated into a package by which the arc length is kept in short without dispersion of arc length for welding without defects such as undercut and unequal beads. In automobile industry, use of aluminum parts is extended for the light weight. The welding is very difficult, and automation is not so progressing in spite of the poor environment. Buckling of welding wire is easy to occur, and supply of wire is obstructed by the deposition of chipped powders on the torch cable, which stay within the contact chip resulting in the deposition. Dislocation of locus is easy to occur at the corner of rectangular pipe during the welding. By improving these troubles, an aluminum MIG welding robot package has been developed. 13 figs.

Interface analysis of embedded chip resistor device package and its effect on drop shock reliability.

Science.gov (United States)

Park, Se-Hoon; Kim, Sun Kyoung; Kim, Young-Ho

2012-04-01

In this study, the drop reliability of an embedded passive package is investigated under JESD22-B111 condition. Chip resistors were buried in a PCB board, and it was electrically interconnected by electroless and electrolytic copper plating on a tin pad of a chip resistor without intermetallic phase. However tin, nickel, and copper formed a complex intermetallic phase, such as (Cu, Ni)6Sn5, (Cu, Ni)3Sn, and (Ni, Cu)3Sn2, at the via interface and via wall after reflow and aging. Since the amount of the tin layer was small compared with the solder joint, excessive intermetallic layer growth was not observed during thermal aging. Drop failures are always initiated at the IMC interface, and as aging time increases Cu-Sn-Ni IMC phases are transformed continuously due to Cu diffusion. We studied the intermetallic formation of the Cu via interface and simulated the stress distribution of drop shock by using material properties and board structure of embedded passive boards. The drop simulation was conducted according to the JEDEC standard. It was revealed that the crack starting point related to failure fracture changed due to intermetallic phase transformation along the via interface, and the position where failure occurs experimentally agrees well with our simulation results.

Enhanced thermaly managed packaging for III-nitride light emitters

Science.gov (United States)

Kudsieh, Nicolas

In this Dissertation our work on `enhanced thermally managed packaging of high power semiconductor light sources for solid state lighting (SSL)' is presented. The motivation of this research and development is to design thermally high stable cost-efficient packaging of single and multi-chip arrays of III-nitrides wide bandgap semiconductor light sources through mathematical modeling and simulations. Major issues linked with this technology are device overheating which causes serious degradation in their illumination intensity and decrease in the lifetime. In the introduction the basics of III-nitrides WBG semiconductor light emitters are presented along with necessary thermal management of high power cingulated and multi-chip LEDs and laser diodes. This work starts at chip level followed by its extension to fully packaged lighting modules and devices. Different III-nitride structures of multi-quantum well InGaN/GaN and AlGaN/GaN based LEDs and LDs were analyzed using advanced modeling and simulation for different packaging designs and high thermal conductivity materials. Study started with basic surface mounted devices using conventional packaging strategies and was concluded with the latest thermal management of chip-on-plate (COP) method. Newly discovered high thermal conductivity materials have also been incorporated for this work. Our study also presents the new approach of 2D heat spreaders using such materials for SSL and micro LED array packaging. Most of the work has been presented in international conferences proceedings and peer review journals. Some of the latest work has also been submitted to well reputed international journals which are currently been reviewed for publication. .

System issues for multichip packaging

Science.gov (United States)

Sage, Maurice G.; Hartley, Neil

1991-04-01

It is now generally recognised that the performance of an electronic system is governed by the choice of packaging technology. Never before have the technical and financial implications of a packaging technology choice been more critical and never before has technology interdependence or industry globalisation made the choice more difficult. This paper is aimed at examining the choices available and the system issues resulting from the move from single chip to multichip packaging.

Towards co-packaging of photonics and microelectronics in existing manufacturing facilities

Science.gov (United States)

Janta-Polczynski, Alexander; Cyr, Elaine; Bougie, Jerome; Drouin, Alain; Langlois, Richard; Childers, Darrell; Takenobu, Shotaro; Taira, Yoichi; Lichoulas, Ted W.; Kamlapurkar, Swetha; Engelmann, Sebastian; Fortier, Paul; Boyer, Nicolas; Barwicz, Tymon

2018-02-01

The impact of integrated photonics on optical interconnects is currently muted by challenges in photonic packaging and in the dense integration of photonic modules with microelectronic components on printed circuit boards. Single mode optics requires tight alignment tolerance for optical coupling and maintaining this alignment in a cost-efficient package can be challenging during thermal excursions arising from downstream microelectronic assembly processes. In addition, the form factor of typical fiber connectors is incompatible with the dense module integration expected on printed circuit boards. We have implemented novel approaches to interfacing photonic chips to standard optical fibers. These leverage standard high throughput microelectronic assembly tooling and self-alignment techniques resulting in photonic packaging that is scalable in manufacturing volume and in the number of optical IOs per chip. In addition, using dense optical fiber connectors with space-efficient latching of fiber patch cables results in compact module size and efficient board integration, bringing the optics closer to the logic chip to alleviate bandwidth bottlenecks. This packaging direction is also well suited for embedding optics in multi-chip modules, including both photonic and microelectronic chips. We discuss the challenges and rewards in this type of configuration such as thermal management and signal integrity.

Fundamental study of microelectronic chip response under laser ultrasonic-interferometric inspection using C-scan method

Science.gov (United States)

Yang, Lei; Gong, Jie; Ume, I. Charles

2014-02-01

In modern surface mount packaging technologies, such as flip chips, chip scale packages, and ball grid arrays(BGA), chips are attached to the substrates/printed wiring board (PWB) using solder bump interconnections. The quality of solder bumps between the chips and the substrate/board is difficult to inspect. Laser ultrasonic-interferometric technique was proved to be a promising approach for solder bump inspection because of its noncontact and nondestructive characteristics. Different indicators extracted from received signals have been used to predict the potential defects, such as correlation coefficient, error ratio, frequency shifting, etc. However, the fundamental understanding of the chip behavior under laser ultrasonic inspection is still missing. Specifically, it is not sure whether the laser interferometer detected out-of-plane displacements were due to wave propagation or structural vibration when the chip was excited by pulsed laser. Plus, it is found that the received signals are chip dependent. Both challenges impede the interpretation of acquired signals. In this paper, a C-scan method was proposed to study the underlying phenomenon during laser ultrasonic inspection. The full chip was inspected. The response of the chip under laser excitation was visualized in a movie resulted from acquired signals. Specifically, a BGA chip was investigated to demonstrate the effectiveness of this method. By characterizing signals using discrete wavelet transform(DWT), both ultrasonic wave propagation and vibration were observed. Separation of them was successfully achieved using ideal band-pass filter and visualized in resultant movies, too. The observed ultrasonic waves were characterized and their respective speeds were measured by applying 2-D FFT. The C-scan method, combined with different digital signal processing techniques, was proved to be an very effective methodology to learn the behavior of chips under laser excitation. This general procedure can be

Characterization of AGIPD1.0: The full scale chip

Energy Technology Data Exchange (ETDEWEB)

Mezza, D., E-mail: davide.mezza@psi.ch [Paul-Scherrer-Institute (PSI), Villigen (Switzerland); Allahgholi, A.; Arino-Estrada, G.; Bianco, L.; Delfs, A. [Deutsches Elektronensynchrotron DESY, Hamburg (Germany); Dinapoli, R. [Paul-Scherrer-Institute (PSI), Villigen (Switzerland); Goettlicher, P. [Deutsches Elektronensynchrotron DESY, Hamburg (Germany); Graafsma, H. [Deutsches Elektronensynchrotron DESY, Hamburg (Germany); Mid Sweden University, Sundsvall (Sweden); Greiffenberg, D. [Paul-Scherrer-Institute (PSI), Villigen (Switzerland); Hirsemann, H.; Jack, S. [Deutsches Elektronensynchrotron DESY, Hamburg (Germany); Klanner, R. [University of Hamburg, Hamburg (Germany); Klyuev, A. [Deutsches Elektronensynchrotron DESY, Hamburg (Germany); Krueger, H. [University of Bonn, Bonn (Germany); Marras, A. [Deutsches Elektronensynchrotron DESY, Hamburg (Germany); Mozzanica, A. [Paul-Scherrer-Institute (PSI), Villigen (Switzerland); Poehlsen, J. [Deutsches Elektronensynchrotron DESY, Hamburg (Germany); Schmitt, B. [Paul-Scherrer-Institute (PSI), Villigen (Switzerland); Schwandt, J. [University of Hamburg, Hamburg (Germany); Sheviakov, I. [Deutsches Elektronensynchrotron DESY, Hamburg (Germany); and others

2016-12-01

The AGIPD (adaptive gain integrating pixel detector) detector is a high frame rate (4.5 MHz) and high dynamic range (up to 10{sup 4} ·12.4 keV photons) detector with single photon resolution (down to 4 keV taking 5σ as limit and lowest noise settings) developed for the European XFEL (XFEL.EU). This work is focused on the characterization of AGIPD1.0, which is the first full scale version of the chip. The chip is 64×64 pixels and each pixel has a size of 200×200 μm{sup 2}. Each pixel can store up to 352 images at a rate of 4.5 MHz (corresponding to 220 ns). A detailed characterization of the AGIPD1.0 chip has been performed in order to assess the main performance of the ASIC in terms of gain, noise, speed and dynamic range. From the measurements presented in this paper a good uniformity of the gain, a noise around 320 e{sup −} (rms) in standard mode and around 240 e{sup −} (rms) in high gain mode has been measured. Furthermore a detailed discussion about the non-linear behavior after the gain switching is presented with both experimental results and simulations.

Development and psychometric properties of the Carer - Head Injury Neurobehavioral Assessment Scale (C-HINAS) and the Carer - Head Injury Participation Scale (C-HIPS): patient and family determined outcome scales.

Science.gov (United States)

Deb, Shoumitro; Bryant, Eleanor; Morris, Paul G; Prior, Lindsay; Lewis, Glyn; Haque, Sayeed

2007-06-01

Develop and assess the psychometric properties of the Carer - Head Injury Participation Scale (C-HIPS) and its biggest factor the Carer - Head Injury Neurobehavioral Assessment Scale (C-HINAS). Furthermore, the aim was to examine the inter-informant reliability by comparing the self reports of individuals with traumatic brain injury (TBI) with the carer reports on the C-HIPS and the C-HINAS. Thirty-two TBI individuals and 27 carers took part in in-depth qualitative interviews exploring the consequences of the TBI. Interview transcripts were analysed and key themes and concepts were used to construct a 49-item and 58-item patient (Patient - Head Injury Participation Scale [P-HIPS]) and carer outcome measure (C-HIPS) respectively, of which 49 were parallel items and nine additional items were used to assess carer burden. Postal versions of the P-HIPS, C-HIPS, Mayo Portland Adaptability Inventory-3 (MPAI-3), and the Glasgow Outcome Scale-Extended (GOSE) were completed by a cohort of 113 TBI individuals and 80 carers. Data from a sub-group of 66 patient/carer pairs were used to compare inter-informant reliability between the P-HIPS and the C-HIPS, and the P-HINAS and the C-HINAS respectively. All individual 49 items of the C-HIPS and their total score showed good test-retest reliability (0.95) and internal consistency (0.95). Comparisons with the MPAI-3 and GOSE found a good correlation with the MPAI-3 (0.7) and a moderate negative correlation with the GOSE (-0.6). Factor analysis of these items extracted a 4-factor structure which represented the domains 'Emotion/Behavior' (C-HINAS), 'Independence/Community Living', 'Cognition', and 'Physical'. The C-HINAS showed good internal consistency (0.92), test-retest reliability (0.93), and concurrent validity with one MPAI subscale (0.7). Assessment of inter-informant reliability revealed good correspondence between the reports of the patients and the carers for both the C-HIPS (0.83) and the C-HINAS (0.82). Both the C

Advanced organics for electronic substrates and packages

CERN Document Server

Fletcher, Andrew E

1992-01-01

Advanced Organics for Electronic Substrates and Packages provides information on packaging, which is one of the most technologically intensive activities in the electronics industry. The electronics packaging community has realized that while semiconductor devices continue to be improved upon for performance, cost, and reliability, it is the interconnection or packaging of these devices that will limit the performance of the systems. Technology must develop packaging for transistor chips, with high levels of performance and integration providing cooling, power, and interconnection, and yet pre

Neural Implants, Packaging for Biocompatible Implants, and Improving Fabricated Capacitors

Science.gov (United States)

Agger, Elizabeth Rose

We have completed the circuit design and packaging procedure for an NIH-funded neural implant, called a MOTE (Microscale Optoelectronically Transduced Electrode). Neural recording implants for mice have greatly advanced neuroscience, but they are often damaging and limited in their recording location. This project will result in free-floating implants that cause less damage, provide rapid electronic recording, and increase range of recording across the cortex. A low-power silicon IC containing amplification and digitization sub-circuits is powered by a dual-function gallium arsenide photovoltaic and LED. Through thin film deposition, photolithography, and chemical and physical etching, the Molnar Group and the McEuen Group (Applied and Engineering Physics department) will package the IC and LED into a biocompatible implant approximately 100microm3. The IC and LED are complete and we have begun refining this packaging procedure in the Cornell NanoScale Science & Technology Facility. ICs with 3D time-resolved imaging capabilities can image microorganisms and other biological samples given proper packaging. A portable, flat, easily manufactured package would enable scientists to place biological samples on slides directly above the Molnar group's imaging chip. We have developed a packaging procedure using laser cutting, photolithography, epoxies, and metal deposition. Using a flip-chip method, we verified the process by aligning and adhering a sample chip to a holder wafer. In the CNF, we have worked on a long-term metal-insulator-metal (MIM) capacitor characterization project. Former Fellow and continuing CNF user Kwame Amponsah developed the original procedure for the capacitor fabrication, and another former fellow, Jonilyn Longenecker, revised the procedure and began the arduous process of characterization. MIM caps are useful to clean room users as testing devices to verify electronic characteristics of their active circuitry. This project's objective is to

Ceramic ball grid array package stress analysis

Science.gov (United States)

Badri, S. H. B. S.; Aziz, M. H. A.; Ong, N. R.; Sauli, Z.; Alcain, J. B.; Retnasamy, V.

2017-09-01

The ball grid array (BGA), a form of chip scale package (CSP), was developed as one of the most advanced surface mount devices, which may be assembled by an ordinary surface ball bumps are used instead of plated nickel and gold (Ni/Au) bumps. Assembly and reliability of the BGA's printed circuit board (PCB), which is soldered by conventional surface mount technology is considered in this study. The Ceramic Ball Grid Array (CBGA) is a rectangular ceramic package or square-shaped that will use the solder ball for external electrical connections instead of leads or wire for connections. The solder balls will be arranged in an array or grid at the bottom of the ceramic package body. In this study, ANSYS software is used to investigate the stress on the package for 2 balls and 4 balls of the CBGA package with the various force range of 1-3 Newton applied to the top of the die, top of the substrate and side of the substrate. The highest maximum stress was analyzed and the maximum equivalent stress was observed on the solder ball and the die. From the simulation result, the CBGA package with less solder balls experience higher stress compared to the package with many solder balls. Therefore, less number of solder ball on the CBGA package results higher stress and critically affect the reliability of the solder balls itself, substrate and die which can lead to the solder crack and also die crack.

Packaging Technologies for 500C SiC Electronics and Sensors

Science.gov (United States)

Chen, Liang-Yu

2013-01-01

Various SiC electronics and sensors are currently under development for applications in 500C high temperature environments such as hot sections of aerospace engines and the surface of Venus. In order to conduct long-term test and eventually commercialize these SiC devices, compatible packaging technologies for the SiC electronics and sensors are required. This presentation reviews packaging technologies developed for 500C SiC electronics and sensors to address both component and subsystem level packaging needs for high temperature environments. The packaging system for high temperature SiC electronics includes ceramic chip-level packages, ceramic printed circuit boards (PCBs), and edge-connectors. High temperature durable die-attach and precious metal wire-bonding are used in the chip-level packaging process. A high temperature sensor package is specifically designed to address high temperature micro-fabricated capacitive pressure sensors for high differential pressure environments. This presentation describes development of these electronics and sensor packaging technologies, including some testing results of SiC electronics and capacitive pressure sensors using these packaging technologies.

Physics-based process modeling, reliability prediction, and design guidelines for flip-chip devices

Science.gov (United States)

Michaelides, Stylianos

Flip Chip on Board (FCOB) and Chip-Scale Packages (CSPs) are relatively new technologies that are being increasingly used in the electronic packaging industry. Compared to the more widely used face-up wirebonding and TAB technologies, flip-chips and most CSPs provide the shortest possible leads, lower inductance, higher frequency, better noise control, higher density, greater input/output (I/O), smaller device footprint and lower profile. However, due to the short history and due to the introduction of several new electronic materials, designs, and processing conditions, very limited work has been done to understand the role of material, geometry, and processing parameters on the reliability of flip-chip devices. Also, with the ever-increasing complexity of semiconductor packages and with the continued reduction in time to market, it is too costly to wait until the later stages of design and testing to discover that the reliability is not satisfactory. The objective of the research is to develop integrated process-reliability models that will take into consideration the mechanics of assembly processes to be able to determine the reliability of face-down devices under thermal cycling and long-term temperature dwelling. The models incorporate the time and temperature-dependent constitutive behavior of various materials in the assembly to be able to predict failure modes such as die cracking and solder cracking. In addition, the models account for process-induced defects and macro-micro features of the assembly. Creep-fatigue and continuum-damage mechanics models for the solder interconnects and fracture-mechanics models for the die have been used to determine the reliability of the devices. The results predicted by the models have been successfully validated against experimental data. The validated models have been used to develop qualification and test procedures for implantable medical devices. In addition, the research has helped develop innovative face

Development of gold based solder candidates for flip chip assembly

DEFF Research Database (Denmark)

Chidambaram, Vivek; Hald, John; Hattel, Jesper Henri

2009-01-01

Flip chip technology is now rapidly replacing the traditional wire bonding interconnection technology in the first level packaging applications due to the miniaturization drive in the microelectronics industry. Flip chip assembly currently involves the use of high lead containing solders...

Full-scale testing of waste package inspection system

International Nuclear Information System (INIS)

Yagi, T.; Kuribayashi, H.; Moriya, Y.; Fujisawa, H.; Takebayashi, N.

1989-01-01

In land disposal of low-level radioactive waste (LLW) in Japan, it is legally required that the waste packages to be disposed of be inspected for conformance to applicable technical regulations prior to shipment from each existing power station. JGC has constructed a fully automatic waste package inspection system for the purpose of obtaining the required design data and proving the performance of the system. This system consists of three inspection units (for visual inspection, surface contamination/dose rate measurement and radioactivity/weight measurement), a labelling unit, a centralized control unit and a drum handling unit. The outstanding features of the system are as follows: The equipment and components are modularized and designed to be of the most compact size and the quality control functions are performed by an advanced centralized control system. The authors discuss how, as a result of the full-scale testing, it has been confirmed that this system satisfies all the performance requirements for the inspection of disposal packages

Packaging Technologies for 500 C SiC Electronics and Sensors: Challenges in Material Science and Technology

Science.gov (United States)

Chen, Liang-Yu; Neudeck, Philip G.; Behelm, Glenn M.; Spry, David J.; Meredith, Roger D.; Hunter, Gary W.

2015-01-01

This paper presents ceramic substrates and thick-film metallization based packaging technologies in development for 500C silicon carbide (SiC) electronics and sensors. Prototype high temperature ceramic chip-level packages and printed circuit boards (PCBs) based on ceramic substrates of aluminum oxide (Al2O3) and aluminum nitride (AlN) have been designed and fabricated. These ceramic substrate-based chip-level packages with gold (Au) thick-film metallization have been electrically characterized at temperatures up to 550C. The 96 alumina packaging system composed of chip-level packages and PCBs has been successfully tested with high temperature SiC discrete transistor devices at 500C for over 10,000 hours. In addition to tests in a laboratory environment, a SiC junction field-effect-transistor (JFET) with a packaging system composed of a 96 alumina chip-level package and an alumina printed circuit board was tested on low earth orbit for eighteen months via a NASA International Space Station experiment. In addition to packaging systems for electronics, a spark-plug type sensor package based on this high temperature interconnection system for high temperature SiC capacitive pressure sensors was also developed and tested. In order to further significantly improve the performance of packaging system for higher packaging density, higher operation frequency, power rating, and even higher temperatures, some fundamental material challenges must be addressed. This presentation will discuss previous development and some of the challenges in material science (technology) to improve high temperature dielectrics for packaging applications.

From Global to Cloud Resolving Scale: Experiments with a Scale- and Aerosol-Aware Physics Package and Impact on Tracer Transport

Science.gov (United States)

Grell, G. A.; Freitas, S. R.; Olson, J.; Bela, M.

2017-12-01

We will start by providing a summary of the latest cumulus parameterization modeling efforts at NOAA's Earth System Research Laboratory (ESRL) will be presented on both regional and global scales. The physics package includes a scale-aware parameterization of subgrid cloudiness feedback to radiation (coupled PBL, microphysics, radiation, shallow and congestus type convection), the stochastic Grell-Freitas (GF) scale- and aerosol-aware convective parameterization, and an aerosol aware microphysics package. GF is based on a stochastic approach originally implemented by Grell and Devenyi (2002) and described in more detail in Grell and Freitas (2014, ACP). It was expanded to include PDF's for vertical mass flux, as well as modifications to improve the diurnal cycle. This physics package will be used on different scales, spanning global to cloud resolving, to look at the impact on scalar transport and numerical weather prediction.

Numerical investigation of heat transfer in Plastic Leaded Chip ...

African Journals Online (AJOL)

Plastic Leaded Chip Carrier (PLCC) package has been emerged a promising option to tackle the thermal management issue of micro-electronic devices. In the present study, three dimensional numerical analysis of heat and fluid flow through PLCC packages oriented in-line and mounted horizontally on a printed circuit ...

Development and psychometric properties of the Carer – Head Injury Neurobehavioral Assessment Scale (C-HINAS) and the Carer – Head Injury Participation Scale (C-HIPS): patient and family determined outcome scales

Science.gov (United States)

Deb, Shoumitro; Bryant, Eleanor; Morris, Paul G; Prior, Lindsay; Lewis, Glyn; Haque, Sayeed

2007-01-01

Objective Develop and assess the psychometric properties of the Carer – Head Injury Participation Scale (C-HIPS) and its biggest factor the Carer – Head Injury Neurobehavioral Assessment Scale (C-HINAS). Furthermore, the aim was to examine the inter-informant reliability by comparing the self reports of individuals with traumatic brain injury (TBI) with the carer reports on the C-HIPS and the C-HINAS. Method Thirty-two TBI individuals and 27 carers took part in in-depth qualitative interviews exploring the consequences of the TBI. Interview transcripts were analysed and key themes and concepts were used to construct a 49-item and 58-item patient (Patient – Head Injury Participation Scale [P-HIPS]) and carer outcome measure (C-HIPS) respectively, of which 49 were parallel items and nine additional items were used to assess carer burden. Postal versions of the P-HIPS, C-HIPS, Mayo Portland Adaptability Inventory-3 (MPAI-3), and the Glasgow Outcome Scale-Extended (GOSE) were completed by a cohort of 113 TBI individuals and 80 carers. Data from a sub-group of 66 patient/carer pairs were used to compare inter-informant reliability between the P-HIPS and the C-HIPS, and the P-HINAS and the C-HINAS respectively. Results All individual 49 items of the C-HIPS and their total score showed good test-retest reliability (0.95) and internal consistency (0.95). Comparisons with the MPAI-3 and GOSE found a good correlation with the MPAI-3 (0.7) and a moderate negative correlation with the GOSE (−0.6). Factor analysis of these items extracted a 4-factor structure which represented the domains ‘Emotion/Behavior’ (C-HINAS), ‘Independence/Community Living’, ‘Cognition’, and ‘Physical’. The C-HINAS showed good internal consistency (0.92), test-retest reliability (0.93), and concurrent validity with one MPAI subscale (0.7). Assessment of inter-informant reliability revealed good correspondence between the reports of the patients and the carers for both the C-HIPS

Wafer level packaging of MEMS

International Nuclear Information System (INIS)

Esashi, Masayoshi

2008-01-01

Wafer level packaging plays many important roles for MEMS (micro electro mechanical systems), including cost, yield and reliability. MEMS structures on silicon chips are encapsulated between bonded wafers or by surface micromachining, and electrical interconnections are made from the cavity. Bonding at the interface, such as glass–Si anodic bonding and metal-to-metal bonding, requires electrical interconnection through the lid vias in many cases. On the other hand, lateral electrical interconnections on the surface of the chip are used for bonding with intermediate melting materials, such as low melting point glass and solder. The cavity formed by surface micromachining is made using sacrificial etching, and the openings needed for the sacrificial etching are plugged using deposition sealing methods. Vacuum packaging methods and the structures for electrical feedthrough for the interconnection are discussed in this review. (topical review)

Electroless Ni-B plating on SiO2 with 3-aminopropyl-triethoxysilane as a barrier layer against Cu diffusion for through-Si via interconnections in a 3-dimensional multi-chip package

International Nuclear Information System (INIS)

Ikeda, Akihiro; Sakamoto, Atsushi; Hattori, Reiji; Kuroki, Yukinori

2009-01-01

Electroless Ni-B was plated on SiO 2 as a barrier layer against Cu diffusion for through-Si via (TSV) interconnections in a 3-dimensional multi-chip package. The electroless Ni-B was deposited on the entire area of the SiO 2 side wall of a deep via with vapor phase pre-deposition of 3-aminopropyl-triethoxysilane on the SiO 2 . The carrier lifetimes in the Si substrates plated with Ni-B/Cu did not decrease with an increase in annealing temperature up to 400 deg. C . The absence of degradation of carrier lifetimes indicates that Cu atoms did not diffuse into the Si through the Ni-B. The advantages of electroless Ni-B (good conformal deposition and forming an effective diffusion barrier against Cu) make it useful as a barrier layer for TSV interconnections in a 3-dimensional multi-chip package

Realtime 3D stress measurement in curing epoxy packaging

DEFF Research Database (Denmark)

Richter, Jacob; Hyldgård, A.; Birkelund, Karen

2007-01-01

This paper presents a novel method to characterize stress in microsystem packaging. A circular p-type piezoresistor is implemented on a (001) silicon chip. We use the circular stress sensor to determine the packaging induced stress in a polystyrene tube filled with epoxy. The epoxy curing process...

White LED with High Package Extraction Efficiency

International Nuclear Information System (INIS)

Yi Zheng; Stough, Matthew

2008-01-01

The goal of this project is to develop a high efficiency phosphor converting (white) Light Emitting Diode (pcLED) 1-Watt package through an increase in package extraction efficiency. A transparent/translucent monolithic phosphor is proposed to replace the powdered phosphor to reduce the scattering caused by phosphor particles. Additionally, a multi-layer thin film selectively reflecting filter is proposed between blue LED die and phosphor layer to recover inward yellow emission. At the end of the project we expect to recycle approximately 50% of the unrecovered backward light in current package construction, and develop a pcLED device with 80 lm/W e using our technology improvements and commercially available chip/package source. The success of the project will benefit luminous efficacy of white LEDs by increasing package extraction efficiency. In most phosphor-converting white LEDs, the white color is obtained by combining a blue LED die (or chip) with a powdered phosphor layer. The phosphor partially absorbs the blue light from the LED die and converts it into a broad green-yellow emission. The mixture of the transmitted blue light and green-yellow light emerging gives white light. There are two major drawbacks for current pcLEDs in terms of package extraction efficiency. The first is light scattering caused by phosphor particles. When the blue photons from the chip strike the phosphor particles, some blue light will be scattered by phosphor particles. Converted yellow emission photons are also scattered. A portion of scattered light is in the backward direction toward the die. The amount of this backward light varies and depends in part on the particle size of phosphors. The other drawback is that yellow emission from phosphor powders is isotropic. Although some backward light can be recovered by the reflector in current LED packages, there is still a portion of backward light that will be absorbed inside the package and further converted to heat. Heat generated

The Advances, Challenges and Future Possibilities of Millimeter-Wave Chip-to-Chip Interconnections for Multi-Chip Systems

Directory of Open Access Journals (Sweden)

Amlan Ganguly

2018-02-01

Full Text Available With aggressive scaling of device geometries, density of manufacturing faults is expected to increase. Therefore, yield of complex Multi-Processor Systems-on-Chips (MP-SoCs will decrease due to higher probability of manufacturing defects especially, in dies with large area. Therefore, disintegration of large SoCs into smaller chips called chiplets will improve yield and cost of complex platform-based systems. This will also provide functional flexibility, modular scalability as well as the capability to integrate heterogeneous architectures and technologies in a single unit. However, with scaling of the number of chiplets in such a system, the shared resources in the system such as the interconnection fabric and memory modules will become performance bottlenecks. Additionally, the integration of heterogeneous chiplets operating at different frequencies and voltages can be challenging. State-of-the-art inter-chip communication requires power-hungry high-speed I/O circuits and data transfer over long wired traces on substrates. This increases energy consumption and latency while decreasing data bandwidth for chip-to-chip communication. In this paper, we explore the advances and the challenges of interconnecting a multi-chip system with millimeter-wave (mm-wave wireless interconnects from a variety of perspectives spanning multiple aspects of the wireless interconnection design. Our discussion on the recent advances include aspects such as interconnection topology, physical layer, Medium Access Control (MAC and routing protocols. We also present some potential paradigm-shifting applications as well as complementary technologies of wireless inter-chip communications.

Packaging Effects on RadFET Sensors for High Energy Physics Experiments

CERN Document Server

Mekki, J; Glaser, M; Guatelli, S; Moll, M; Pia, M G; Ravotti, F

2009-01-01

RadFETs in customized chip carrier packages are installed in the LHC Experiments as radiation monitors. The package influence on the dose measurement in the complex LHC radiation environment is evaluated using Geant4 simulations and experimental data.

Recovery of leaded-frame metals from integrated circuit package; Shuseki kairo package kara no lead frame kinzoku no kaishu

Energy Technology Data Exchange (ETDEWEB)

Rokukawa, N.; Sakamoto, H. [National Institute for Resources and Environment, Tsukuba (Japan)

1997-12-25

Discussions were given on separation and recovery of leaded-frame metals from an integrated circuit (IC) package. A printed wiring board in an electronic device is mounted with an IC package molded with an IC as a major component, and composed of IC chips, leaded-frame metals (the pin section retains the IC chips safely in a mold, and plays a role of terminal with an external circuit), and mold material (thermally hardened and reinforced resin). Quantity of IC packages discarded as a result of the deterioration due to aging is increasing year after year. IC package test pieces were crushed in a mortar, selected of metals manually, and classified by using a magnet and a sieve. The leaded-frame metals were easily separated from the mold material by crushing, and capable of being recovered by using a magnet. However, since the recovered leaded-frame metals are alloys having different compositions, how each metal component could be separated and refined is an important problem to be solved. For the time being, the metals may be utilized as structural materials for building materials by melting and alloying the leaded-frame metals. 10 refs., 7 tabs.

Packaging and testing of multi-wavelength DFB laser array using REC technology

Science.gov (United States)

Ni, Yi; Kong, Xuan; Gu, Xiaofeng; Chen, Xiangfei; Zheng, Guanghui; Luan, Jia

2014-02-01

Packaging of distributed feedback (DFB) laser array based on reconstruction-equivalent-chirp (REC) technology is a bridge from chip to system, and influences the practical process of REC chip. In this paper, DFB laser arrays of 4-channel @1310 nm and 8-channel @1550 nm are packaged. Our experimental results show that both these laser arrays have uniform wavelength spacing and larger than 35 dB average Side Mode Suppression Ratio (SMSR). When I=35 mA, we obtain the total output power of 1 mW for 4-channel @1310 nm, and 227 μw for 8-channel @1550 nm respectively. The high frequency characteristics of the packaged chips are also obtained, and the requirements for 4×10 G or even 8×10 G systems can be reached. Our results demonstrate the practical and low cost performance of REC technology and indicate its potential in the future fiber-to-the-home (FTTH) application.

RF and microwave microelectronics packaging II

CERN Document Server

Sturdivant, Rick

2017-01-01

Reviews RF, microwave, and microelectronics assembly process, quality control, and failure analysis Bridges the gap between low cost commercial and hi-res RF/Microwave packaging technologies Engages in an in-depth discussion of challenges in packaging and assembly of advanced high-power amplifiers This book presents the latest developments in packaging for high-frequency electronics. It is a companion volume to “RF and Microwave Microelectronics Packaging” (2010) and covers the latest developments in thermal management, electrical/RF/thermal-mechanical designs and simulations, packaging and processing methods, and other RF and microwave packaging topics. Chapters provide detailed coverage of phased arrays, T/R modules, 3D transitions, high thermal conductivity materials, carbon nanotubes and graphene advanced materials, and chip size packaging for RF MEMS. It appeals to practicing engineers in the electronic packaging and high-frequency electronics domain, and to academic researchers interested in underst...

Experience from large scale use of the EuroGenomics custom SNP chip in cattle

DEFF Research Database (Denmark)

Boichard, Didier A; Boussaha, Mekki; Capitan, Aurélien

2018-01-01

This article presents the strategy to evaluate candidate mutations underlying QTL or responsible for genetic defects, based upon the design and large-scale use of the Eurogenomics custom SNP chip set up for bovine genomic selection. Some variants under study originated from mapping genetic defect...

A contact-lens-shaped IC chip technology

International Nuclear Information System (INIS)

Liu, Ching-Yu; Yang, Frank; Teng, Chih-Chiao; Fan, Long-Sheng

2014-01-01

We report on novel contact-lens-shaped silicon integrated circuit chip technology for applications such as forming a conforming retinal prosthesis. This is achieved by means of patterning thin films of high residual stress on top of a shaped thin silicon substrate. Several strategies are employed to achieve curvatures of various amounts. Firstly, high residual stress on a thin film makes a thin chip deform into a designed three-dimensional shape. Also, a series of patterned stress films and ‘petal-shaped’ chips were fabricated and analyzed. Large curvatures can also be formed and maintained by the packaging process of bonding the chips to constraining elements such as thin-film polymer ring structures. As a demonstration, a complementary metal oxide semiconductor transistor (CMOS) image-sensing retina chip is made into a contact-lens shape conforming to a human eyeball 12.5 mm in radius. This non-planar and flexible chip technology provides a desirable device surface interface to soft tissues or non-planar bio surfaces and opens up many other possibilities for biomedical applications. (paper)

High-performance packaging for monolithic microwave and millimeter-wave integrated circuits

Science.gov (United States)

Shalkhauser, K. A.; Li, K.; Shih, Y. C.

1992-01-01

Packaging schemes are developed that provide low-loss, hermetic enclosure for enhanced monolithic microwave and millimeter-wave integrated circuits. These package schemes are based on a fused quartz substrate material offering improved RF performance through 44 GHz. The small size and weight of the packages make them useful for a number of applications, including phased array antenna systems. As part of the packaging effort, a test fixture was developed to interface the single chip packages to conventional laboratory instrumentation for characterization of the packaged devices.

Micro packaged MEMS pressure sensor for intracranial pressure measurement

International Nuclear Information System (INIS)

Liu Xiong; Yao Yan; Ma Jiahao; Zhang Zhaohua; Zhang Yanhang; Wang Qian; Ren Tianling

2015-01-01

This paper presents a micro packaged MEMS pressure sensor for intracranial pressure measurement which belongs to BioMEMS. It can be used in lumbar puncture surgery to measure intracranial pressure. Miniaturization is key for lumbar puncture surgery because the sensor must be small enough to allow it be placed in the reagent chamber of the lumbar puncture needle. The size of the sensor is decided by the size of the sensor chip and package. Our sensor chip is based on silicon piezoresistive effect and the size is 400 × 400 μm 2 . It is much smaller than the reported polymer intracranial pressure sensors such as liquid crystal polymer sensors. In terms of package, the traditional dual in-line package obviously could not match the size need, the minimal size of recently reported MEMS-based intracranial pressure sensors after packaging is 10 × 10 mm 2 . In this work, we are the first to introduce a quad flat no-lead package as the package form of piezoresistive intracranial pressure sensors, the whole size of the sensor is minimized to only 3 × 3 mm 2 . Considering the liquid measurement environment, the sensor is gummed and waterproof performance is tested; the sensitivity of the sensor is 0.9 × 10 −2 mV/kPa. (paper)

New generation of single-chip microcomputers focused on cost performance

Energy Technology Data Exchange (ETDEWEB)

Akao, Y.; Iwashita, H. (Hitachi, Ltd., Tokyo (Japan))

1993-06-01

A single-chip microcomputer which incorporates a CPU (central processing unit), memory, and peripheral functions in one chip has been increasingly applied to various fields as the heart of electronic equipment in terms of its economy, compactness, lightness, and suitability for mass production. In response to a wide variety of needs, a lineup must have substantial breadth with regard to performance, on-chip memory capacity, on-chip peripheral functions, operating voltage, and packaging. In particular, low-voltage high-speed operation, high integration, expanded address space, and improved software productivity, which are required for mobile communication terminals, are the common needs for single-chip microcomputers. In accordance with these needs, Hitachi has been actively developing new products. The present paper introduces Hitachi's lineup of single-chip microcomputers. 10 figs., 1 tab.

PACE3 - front-end chip for the CMS Preshower

CERN Multimedia

Aspel, Paul

2003-01-01

This is PACE3 which is the front-end chip for the CMS Preshower. In fact PACE3 is the combination of two ASICs called Delta3 and PACEAM3. Delta3 is on the left and PACEAM3 is on the right. The two ASICs are bonded together and then packaged within a single 196 pin fpBGA package.

A wafer-level multi-chip module process with thick photosensitive benzocyclobutene as the dielectric for microwave application

International Nuclear Information System (INIS)

Tang, Jiajie; Sun, Xiaowei; Luo, Le

2011-01-01

A wafer-level microwave multi-chip module (MMCM) packaging process is presented. Thick photosensitive-benzocyclobutene (photo-BCB) polymer (about 25 µm/layer) is used as the dielectric for its simplified process and the capability of obtaining desirable electrical, chemical and mechanical properties at high frequencies. The MMCM packaging structure contains a monolithic microwave integrated circuit (MMIC) chip embedded in a lossy-silicon wafer, a microwave band-pass filter (BPF) and two layers of BCB/Au interconnection. Key processes of fabrication are described in detail. The non-uniformity of BCB film and the sidewall angle of the via-holes for inter-layer connection are tested. Via-chains prepared by metal/BCB multilayer structures are tested through the Kelvin test structure to investigate the resistances of inter-layer connection. The average value is measured to be 73.5 mΩ. The electrical characteristic of this structure is obtained by a microwave transmission performance test from 15 to 30 GHz. The measurement results show good consistency between the bare MMIC die and the packaged die in the test frequency band. The gain of the MMIC chip after packaging is better than 18 dB within the designed operating frequency range (from 23 to 25 GHz). When the packaged MMIC chip is connected to a BPF, the maximum gain is still measured to reach 11.95 dB at 23.8 GHz

Development of a small-scale protope of the GOSSIPO-2 chip in 0.13 um CMOS technology

CERN Document Server

Kluit, R; Gromov, V

2007-01-01

The GOSSIP (Gas On Slimmed Silicon Pixel) detector is a proposed alternative for silicon based pixel detectors. The Gossip Prototype (GOSSIPO) chip is being developed to serve as a prototype read-out chip for such a gas-filled detector. Thanks to the very low capacitance at the preamplifier input, the front-end of the chip demonstrates low-noise performance in combination with a fast peaking time and low analog power dissipation. Measurement of the drift time of every primary electron in the gas volume enables 3D reconstruction of the particle tracks. For this purpose a Time-to- Digital converter must be placed in each pixel. A small-scale prototype of the GOSSIP chip has been developed in the 0.13 μm CMOS technology. The prototype includes a 16 by 16 pixel array where each pixel is equipped with a front-end circuit, threshold DAC, and a 4-bit TDC. The chip is available for testing in May 2007 and after initial tests it will be postprocessed to build a prototype detector. This paper describes the detector de...

Wafer-level packaged RF-MEMS switches fabricated in a CMOS fab

NARCIS (Netherlands)

Tilmans, H.A.C.; Ziad, H.; Jansen, Henricus V.; Di Monaco, O.; Jourdain, A.; De Raedt, W.; Rottenberg, X.; De Backer, E.; Decoussernaeker, A.; Baert, K.

2001-01-01

Reports on wafer-level packaged RF-MEMS switches fabricated in a commercial CMOS fab. Switch fabrication is based on a metal surface micromachining process. A novel wafer-level packaging scheme is developed, whereby the switches are housed in on-chip sealed cavities using benzocyclobutene (BCB) as

Analysis of Design of Mixed-Signal Electronic Packaging

National Research Council Canada - National Science Library

Pileggi, Lawrence

1999-01-01

The objective of this project is to develop innovative algorithms and prototype tools that will help facilitate the design of mixed signal multi-chip modules and packaging in a manner that is similar...

Surface Tension Directed Fluidic Self-Assembly of Semiconductor Chips across Length Scales and Material Boundaries

Directory of Open Access Journals (Sweden)

Shantonu Biswas

2016-03-01

Full Text Available This publication provides an overview and discusses some challenges of surface tension directed fluidic self-assembly of semiconductor chips which are transported in a liquid medium. The discussion is limited to surface tension directed self-assembly where the capture, alignment, and electrical connection process is driven by the surface free energy of molten solder bumps where the authors have made a contribution. The general context is to develop a massively parallel and scalable assembly process to overcome some of the limitations of current robotic pick and place and serial wire bonding concepts. The following parts will be discussed: (2 Single-step assembly of LED arrays containing a repetition of a single component type; (3 Multi-step assembly of more than one component type adding a sequence and geometrical shape confinement to the basic concept to build more complex structures; demonstrators contain (3.1 self-packaging surface mount devices, and (3.2 multi-chip assemblies with unique angular orientation. Subsequently, measures are discussed (4 to enable the assembly of microscopic chips (10 μm–1 mm; a different transport method is introduced; demonstrators include the assembly of photovoltaic modules containing microscopic silicon tiles. Finally, (5 the extension to enable large area assembly is presented; a first reel-to-reel assembly machine is realized; the machine is applied to the field of solid state lighting and the emerging field of stretchable electronics which requires the assembly and electrical connection of semiconductor devices over exceedingly large area substrates.

Advanced Packaging Technology Used in Fabricating a High-Temperature Silicon Carbide Pressure Sensor

Science.gov (United States)

Beheim, Glenn M.

2003-01-01

The development of new aircraft engines requires the measurement of pressures in hot areas such as the combustor and the final stages of the compressor. The needs of the aircraft engine industry are not fully met by commercially available high-temperature pressure sensors, which are fabricated using silicon. Kulite Semiconductor Products and the NASA Glenn Research Center have been working together to develop silicon carbide (SiC) pressure sensors for use at high temperatures. At temperatures above 850 F, silicon begins to lose its nearly ideal elastic properties, so the output of a silicon pressure sensor will drift. SiC, however, maintains its nearly ideal mechanical properties to extremely high temperatures. Given a suitable sensor material, a key to the development of a practical high-temperature pressure sensor is the package. A SiC pressure sensor capable of operating at 930 F was fabricated using a newly developed package. The durability of this sensor was demonstrated in an on-engine test. The SiC pressure sensor uses a SiC diaphragm, which is fabricated using deep reactive ion etching. SiC strain gauges on the surface of the diaphragm sense the pressure difference across the diaphragm. Conventionally, the SiC chip is mounted to the package with the strain gauges outward, which exposes the sensitive metal contacts on the chip to the hostile measurement environment. In the new Kulite leadless package, the SiC chip is flipped over so that the metal contacts are protected from oxidation by a hermetic seal around the perimeter of the chip. In the leadless package, a conductive glass provides the electrical connection between the pins of the package and the chip, which eliminates the fragile gold wires used previously. The durability of the leadless SiC pressure sensor was demonstrated when two 930 F sensors were tested in the combustor of a Pratt & Whitney PW4000 series engine. Since the gas temperatures in these locations reach 1200 to 1300 F, the sensors were

Hybrid macro-micro fluidics system for a chip-based biosensor

Science.gov (United States)

Tamanaha, C. R.; Whitman, L. J.; Colton, R. J.

2002-03-01

We describe the engineering of a hybrid fluidics platform for a chip-based biosensor system that combines high-performance microfluidics components with powerful, yet compact, millimeter-scale pump and valve actuators. The microfluidics system includes channels, valveless diffuser-based pumps, and pinch-valves that are cast into a poly(dimethylsiloxane) (PDMS) membrane and packaged along with the sensor chip into a palm-sized plastic cartridge. The microfluidics are driven by pump and valve actuators contained in an external unit (with a volume ~30 cm3) that interfaces kinematically with the PDMS microelements on the cartridge. The pump actuator is a simple-lever, flexure-hinge displacement amplifier that increases the motion of a piezoelectric stack. The valve actuators are an array of cantilevers operated by shape memory alloy wires. All components can be fabricated without the need for complex lithography or micromachining, and can be used with fluids containing micron-sized particulates. Prototypes have been modeled and tested to ensure the delivery of microliter volumes of fluid and the even dispersion of reagents over the chip sensing elements. With this hybrid approach to the fluidics system, the biochemical assay benefits from the many advantages of microfluidics yet we avoid the complexity and unknown reliability of immature microactuator technologies.

The fastclime Package for Linear Programming and Large-Scale Precision Matrix Estimation in R.

Science.gov (United States)

Pang, Haotian; Liu, Han; Vanderbei, Robert

2014-02-01

We develop an R package fastclime for solving a family of regularized linear programming (LP) problems. Our package efficiently implements the parametric simplex algorithm, which provides a scalable and sophisticated tool for solving large-scale linear programs. As an illustrative example, one use of our LP solver is to implement an important sparse precision matrix estimation method called CLIME (Constrained L 1 Minimization Estimator). Compared with existing packages for this problem such as clime and flare, our package has three advantages: (1) it efficiently calculates the full piecewise-linear regularization path; (2) it provides an accurate dual certificate as stopping criterion; (3) it is completely coded in C and is highly portable. This package is designed to be useful to statisticians and machine learning researchers for solving a wide range of problems.

RELIC: a novel dye-bias correction method for Illumina Methylation BeadChip.

Science.gov (United States)

Xu, Zongli; Langie, Sabine A S; De Boever, Patrick; Taylor, Jack A; Niu, Liang

2017-01-03

The Illumina Infinium HumanMethylation450 BeadChip and its successor, Infinium MethylationEPIC BeadChip, have been extensively utilized in epigenome-wide association studies. Both arrays use two fluorescent dyes (Cy3-green/Cy5-red) to measure methylation level at CpG sites. However, performance difference between dyes can result in biased estimates of methylation levels. Here we describe a novel method, called REgression on Logarithm of Internal Control probes (RELIC) to correct for dye bias on whole array by utilizing the intensity values of paired internal control probes that monitor the two color channels. We evaluate the method in several datasets against other widely used dye-bias correction methods. Results on data quality improvement showed that RELIC correction statistically significantly outperforms alternative dye-bias correction methods. We incorporated the method into the R package ENmix, which is freely available from the Bioconductor website ( https://www.bioconductor.org/packages/release/bioc/html/ENmix.html ). RELIC is an efficient and robust method to correct for dye-bias in Illumina Methylation BeadChip data. It outperforms other alternative methods and conveniently implemented in R package ENmix to facilitate DNA methylation studies.

Network Partitioning Domain Knowledge Multiobjective Application Mapping for Large-Scale Network-on-Chip

Directory of Open Access Journals (Sweden)

Yin Zhen Tei

2014-01-01

Full Text Available This paper proposes a multiobjective application mapping technique targeted for large-scale network-on-chip (NoC. As the number of intellectual property (IP cores in multiprocessor system-on-chip (MPSoC increases, NoC application mapping to find optimum core-to-topology mapping becomes more challenging. Besides, the conflicting cost and performance trade-off makes multiobjective application mapping techniques even more complex. This paper proposes an application mapping technique that incorporates domain knowledge into genetic algorithm (GA. The initial population of GA is initialized with network partitioning (NP while the crossover operator is guided with knowledge on communication demands. NP reduces the large-scale application mapping complexity and provides GA with a potential mapping search space. The proposed genetic operator is compared with state-of-the-art genetic operators in terms of solution quality. In this work, multiobjective optimization of energy and thermal-balance is considered. Through simulation, knowledge-based initial mapping shows significant improvement in Pareto front compared to random initial mapping that is widely used. The proposed knowledge-based crossover also shows better Pareto front compared to state-of-the-art knowledge-based crossover.

Heat transfer and structure stress analysis of micro packaging component of high power light emitting diode

Directory of Open Access Journals (Sweden)

Hsu Chih-Neng

2013-01-01

Full Text Available This paper focuses on the heat transfer and structural stress analysis of the micro- scale packaging structure of a high-power light emitting diode. The thermal-effect and thermal-stress of light emitting diode are determined numerically. Light emitting diode is attached to the silicon substrate through the wire bonding process by using epoxy as die bond material. The silicon substrate is etched with holes at the bottom and filled with high conductivity copper material. The chip temperature and structure stress increase with input power consumption. The micro light emitting diode is mounted on the heat sink to increase the heat dissipation performance, to decrease chip temperature, to enhance the material structure reliability and safety, and to avoid structure failure as well. This paper has successfully used the finite element method to the micro-scale light emitting diode heat transfer and stress concentration at the edges through etched holes.

Insight into economies of scale for waste packaging sorting plants

DEFF Research Database (Denmark)

Cimpan, Ciprian; Wenzel, Henrik; Maul, Anja

2015-01-01

of economies of scale and discussed complementary relations occurring between capacity size, technology level and operational practice. Processing costs (capital and operational expenditure) per unit waste input were found to decrease from above 100 € for small plants with a basic technology level to 60......This contribution presents the results of a techno-economic analysis performed for German Materials Recovery Facilities (MRFs) which sort commingled lightweight packaging waste (consisting of plastics, metals, beverage cartons and other composite packaging). The study addressed the importance......-70 € for large plants employing advanced process flows. Typical operational practice, often riddled with inadequate process parameters was compared with planned or designed operation. The former was found to significantly influence plant efficiency and therefore possible revenue streams from the sale of output...

Evaluation of thermal resistance constitution for packaged AlGaN/GaN high electron mobility transistors by structure function method

International Nuclear Information System (INIS)

Zhang Guang-Chen; Feng Shi-Wei; Zhou Zhou; Li Jing-Wan; Guo Chun-Sheng

2011-01-01

The evaluation of thermal resistance constitution for packaged AlGaN/GaN high electron mobility transistor (HEMT) by structure function method is proposed in this paper. The evaluation is based on the transient heating measurement of the AlGaN/GaN HEMT by pulsed electrical temperature sensitive parameter method. The extracted chip-level and package-level thermal resistances of the packaged multi-finger AlGaN/GaN HEMT with 400-μm SiC substrate are 22.5 K/W and 7.2 K/W respectively, which provides a non-invasive method to evaluate the chip-level thermal resistance of packaged AlGaN/GaN HEMTs. It is also experimentally proved that the extraction of the chip-level thermal resistance by this proposed method is not influenced by package form of the tested device and temperature boundary condition of measurement stage. (condensed matter: electronic structure, electrical, magnetic, and optical properties)

A novel conductive-polymer-based integration process for high-performance flip-chip packages

Science.gov (United States)

Lohokare, Saurabh

Conductive polymers have recently attracted considerable attention for low-temperature fabrication of lead-free, reworkable, and flexible flip-chip interconnects. Using these materials, I demonstrate in this thesis a process that enables low-cost and high-resolution flip-chip interconnects using conventional micro-fabrication techniques. This fabrication process offers improved performance as compared to conventional flip-chip techniques, such as screen-printing, and allows for definition of interconnects with excellent surface uniformity and control over the bump profile. In order to demonstrate the utility and wide applicability of this process, several test implementations that serve as case studies were investigated. Specifically, novel InGaAsSb avalanche photodiodes (APDs), operating around lambda = 2m and targeted for free-space communication and biomedical spectroscopy applications, were fabricated and flip-chip-integrated to test the static electrical characteristics of the polymer bumps. Additionally, the dynamic electrical performance characteristics of the polymer bumps were studied by using AlGaAsSb/AlGaSb p-i-n photodetectors as a case study. The fabrication of these photodetectors, operating around lambda = 1.55mum and targeted for optical communication applications, was accomplished using a customized inductively coupled plasma (ICP) etch process that resulted in a low dark current and excellent speed (3dB bandwidth of 10GHz) and, responsivity (60% external quantum efficiency) characteristics. Furthermore, flip-chip integration was used to demonstrate a three-dimensional, point-to-point micro-optical interconnect, which was 2.33mm-long in a system 15.27mm3 in volume. Lastly, high-speed parallel optical interconnects were demonstrated using polymer-flip-chip-integrated 10GHz vertical-cavity surface-emitting laser (VCSEL) and DOEs. Such interconnects offer the ability to alleviate the communication bottleneck that is projected to occur in future, high

High coherence plane breaking packaging for superconducting qubits

Science.gov (United States)

Bronn, Nicholas T.; Adiga, Vivekananda P.; Olivadese, Salvatore B.; Wu, Xian; Chow, Jerry M.; Pappas, David P.

2018-04-01

We demonstrate a pogo pin package for a superconducting quantum processor specifically designed with a nontrivial layout topology (e.g., a center qubit that cannot be accessed from the sides of the chip). Two experiments on two nominally identical superconducting quantum processors in pogo packages, which use commercially available parts and require modest machining tolerances, are performed at low temperature (10 mK) in a dilution refrigerator and both found to behave comparably to processors in standard planar packages with wirebonds where control and readout signals come in from the edges. Single- and two-qubit gate errors are also characterized via randomized benchmarking, exhibiting similar error rates as in standard packages, opening the possibility of integrating pogo pin packaging with extensible qubit architectures.

Packaging of photodetector modules for 100 Gbit/s applications using electromagnetic simulations

DEFF Research Database (Denmark)

Jiang, Chenhui; Krozer, Viktor; Bach, H.-G.

2009-01-01

In this paper we demonstrate ultra-broadband packaging and interconnection designs for photodetector (PD) modules for 100 Gbit/s data transmission applications. The design of packaging and interconnection structures is based on accurate and reliable 3D electromagnetic (EM) simulations. Mode...... conversion loss due to mode mismatch is identified as the dominant effect of limiting bandwidth of packaged modules. Finally, PD chips are successfully packaged by using wire-bonding technology and conventional coplanar waveguide (CPW) for avoiding mode mismatch. The new packaged PD module demonstrates...

Mechanical and electrical properties of ultra-thin chips and flexible electronics assemblies during bending

NARCIS (Netherlands)

Van Den Ende, D.A.; Van De Wiel, H.J.; Kusters, R.H.L.; Sridhar, A.; Schram, J.F.M.; Cauwe, M.; Van Den Brand, J.

2014-01-01

Ultra-thin chips of less than 20 μm become flexible, allowing integration of silicon IC technology with highly flexible electronics such as food packaging sensor systems or healthcare and sport monitoring tags as wearable patches or even directly in clothing textile. The ultra-thin chips in these

Standard semiconductor packaging for high-reliability low-cost MEMS applications

Science.gov (United States)

Harney, Kieran P.

2005-01-01

Microelectronic packaging technology has evolved over the years in response to the needs of IC technology. The fundamental purpose of the package is to provide protection for the silicon chip and to provide electrical connection to the circuit board. Major change has been witnessed in packaging and today wafer level packaging technology has further revolutionized the industry. MEMS (Micro Electro Mechanical Systems) technology has created new challenges for packaging that do not exist in standard ICs. However, the fundamental objective of MEMS packaging is the same as traditional ICs, the low cost and reliable presentation of the MEMS chip to the next level interconnect. Inertial MEMS is one of the best examples of the successful commercialization of MEMS technology. The adoption of MEMS accelerometers for automotive airbag applications has created a high volume market that demands the highest reliability at low cost. The suppliers to these markets have responded by exploiting standard semiconductor packaging infrastructures. However, there are special packaging needs for MEMS that cannot be ignored. New applications for inertial MEMS devices are emerging in the consumer space that adds the imperative of small size to the need for reliability and low cost. These trends are not unique to MEMS accelerometers. For any MEMS technology to be successful the packaging must provide the basic reliability and interconnection functions, adding the least possible cost to the product. This paper will discuss the evolution of MEMS packaging in the accelerometer industry and identify the main issues that needed to be addressed to enable the successful commercialization of the technology in the automotive and consumer markets.

Self-adaptive phosphor coating technology for wafer-level scale chip packaging

International Nuclear Information System (INIS)

Zhou Linsong; Rao Haibo; Wang Wei; Wan Xianlong; Liao Junyuan; Wang Xuemei; Zhou Da; Lei Qiaolin

2013-01-01

A new self-adaptive phosphor coating technology has been successfully developed, which adopted a slurry method combined with a self-exposure process. A phosphor suspension in the water-soluble photoresist was applied and exposed to LED blue light itself and developed to form a conformal phosphor coating with self-adaptability to the angular distribution of intensity of blue light and better-performing spatial color uniformity. The self-adaptive phosphor coating technology had been successfully adopted in the wafer surface to realize a wafer-level scale phosphor conformal coating. The first-stage experiments show satisfying results and give an adequate demonstration of the flexibility of self-adaptive coating technology on application of WLSCP. (semiconductor devices)

Effect of Various Packaging Methods on Small-Scale Hanwoo (Korean Native Cattle) during Refrigerated Storage

Science.gov (United States)

Yu, Hwan Hee; Song, Myung Wook; Kim, Tae-Kyung; Choi, Yun-Sang; Cho, Gyu Yong; Lee, Na-Kyoung; Paik, Hyun-Dong

2018-01-01

Abstract The objective of this study was to investigate comparison of physicochemical, microbiological, and sensory characteristics of Hanwoo eye of round by various packaging methods [wrapped packaging (WP), modified atmosphere packaging (MAP), vacuum packaging (VP) with three different vacuum films, and vacuum skin packaging (VSP)] at a small scale. Packaged Hanwoo beef samples were stored in refrigerated conditions (4±1°C) for 28 days. Packaged beef was sampled on days 0, 7, 14, 21, and 28. Physicochemical [pH, surface color, thiobarbituric acid reactive substances (TBARS), and volatile basic nitrogen (VBN) values], microbiological, and sensory analysis of packaged beef samples were performed. VP and VSP samples showed low TBARS and VBN values, and pH and surface color did not change substantially during the 28-day period. For VSP, total viable bacteria, psychrotrophic bacteria, lactic acid bacteria, and coliform counts were lower than those for other packaging systems. Salmonella spp. and Escherichia coli O157:H7 were not detected in any packaged beef samples. A sensory analysis showed that the scores for appearance, flavor, color, and overall acceptability did not change significantly until day 7. In total, VSP was effective with respect to significantly higher a* values, physicochemical stability, and microbial safety in Hanwoo packaging (p<0.05). PMID:29805283

Assembly reliability of CSPs with various chiip sizes by accelerated thermal and mechanical cycling test

Science.gov (United States)

Ghaffarian, R.

2000-01-01

A JPL-led chip scale package (CSP) Consortium, composed of team members representing government agencies and private companies, recently joined together to pool in-kind resources for developing the quality and reliability of chip scale packages (CSPs) for a variety of projects.

Improving the scaling normalization for high-density oligonucleotide GeneChip expression microarrays

Directory of Open Access Journals (Sweden)

Lu Chao

2004-07-01

Full Text Available Abstract Background Normalization is an important step for microarray data analysis to minimize biological and technical variations. Choosing a suitable approach can be critical. The default method in GeneChip expression microarray uses a constant factor, the scaling factor (SF, for every gene on an array. The SF is obtained from a trimmed average signal of the array after excluding the 2% of the probe sets with the highest and the lowest values. Results Among the 76 U34A GeneChip experiments, the total signals on each array showed 25.8% variations in terms of the coefficient of variation, although all microarrays were hybridized with the same amount of biotin-labeled cRNA. The 2% of the probe sets with the highest signals that were normally excluded from SF calculation accounted for 34% to 54% of the total signals (40.7% ± 4.4%, mean ± sd. In comparison with normalization factors obtained from the median signal or from the mean of the log transformed signal, SF showed the greatest variation. The normalization factors obtained from log transformed signals showed least variation. Conclusions Eliminating 40% of the signal data during SF calculation failed to show any benefit. Normalization factors obtained with log transformed signals performed the best. Thus, it is suggested to use the mean of the logarithm transformed data for normalization, rather than the arithmetic mean of signals in GeneChip gene expression microarrays.

A chip-scale, telecommunications-band frequency conversion interface for quantum emitters.

Science.gov (United States)

Agha, Imad; Ates, Serkan; Davanço, Marcelo; Srinivasan, Kartik

2013-09-09

We describe a chip-scale, telecommunications-band frequency conversion interface designed for low-noise operation at wavelengths desirable for common single photon emitters. Four-wave-mixing Bragg scattering in silicon nitride waveguides is used to demonstrate frequency upconversion and downconversion between the 980 nm and 1550 nm wavelength regions, with signal-to-background levels > 10 and conversion efficiency of ≈ -60 dB at low continuous wave input pump powers ( 25 % in existing geometries. Finally, we present waveguide designs that can be used to connect shorter wavelength (637 nm to 852 nm) quantum emitters with 1550 nm.

Internalization of subcellular-scale microfabricated chips by healthy and cancer cells

Science.gov (United States)

Wong, H.-S. Philip

2018-01-01

Continuous monitoring of physiological parameters inside a living cell will lead to major advances in our understanding of biology and complex diseases, such as cancer. It also enables the development of new medical diagnostics and therapeutics. Progress in nanofabrication and wireless communication has opened up the potential of making a wireless chip small enough that it can be wholly inserted into a living cell. To investigate how such chips could be internalized into various types of living single cells and how this process might affect cells’ physiology, we designed and fabricated a series of multilayered micron-scale tag structures with different sizes as potential RFID (Radio Frequency IDentification) cell trackers. While the present structures are test structures that do not resonate, the tags that do resonate have similar structure from device fabrication, material properties, and device size point of view. The structures are in four different sizes, the largest with the lateral dimension of 9 μm × 21 μm. The thickness for these structures is kept constant at 1.5 μm. We demonstrate successful delivery of our fabricated chips into various types of living cells, such as melanoma skin cancer, breast cancer, colon cancer and healthy/normal fibroblast skin cells. To our surprise, we observed a remarkable internalization rate difference between each cell type; the uptake rate was faster for more aggressive cancer cells than the normal/healthy cells. Cell viability before and after tag cellular internalization and persistence of the internalized tags have also been recorded over the course of five days of incubation. These results establish the foundations of the possibility of long term, wireless, intracellular physiological signal monitoring. PMID:29601607

Chip compacting press; Jido kirikuzu asshukuki

Energy Technology Data Exchange (ETDEWEB)

Oura, K. [Yuken Kogyo Co. Ltd., Kanagawa (Japan)

1998-08-15

The chips exhausted from various machine tools are massy, occupy much space and make working environment worse by staying added cutting oil to lower part. The chips are exhausted as a result of machining and have not constant quality. Even if used material is same the chips have various shapes and properties by kinds and machining methods of used machine tools, and are troublesome materials from a standpoint of their treatment. Pressing and solidification of the chips have frequently been tried. A chip compacting press introduced in this paper, a relatively cheap chip compacting press aimed for relatively small scale chip treatment, and has such characteristics and effects as follows. Chips are pressed and solidified by each raw material, so fractional management can be easily conducted. As casting metal chips and curled chips of iron and aluminum can be pressed to about 1/3 to 1/5 and about 1/40, respectively, space saving can be conducted. Chip compacting pressing upgrades its transporting efficiency to make possible to reduce its transporting cost. As chip solidification controls its oxidation and most cutting oil are removed, chips are easy to recycle. 2 figs., 1 tab.

Fabrication and Characterization of Bi2Te3-Based Chip-Scale Thermoelectric Energy Harvesting Devices

Science.gov (United States)

Cornett, Jane; Chen, Baoxing; Haidar, Samer; Berney, Helen; McGuinness, Pat; Lane, Bill; Gao, Yuan; He, Yifan; Sun, Nian; Dunham, Marc; Asheghi, Mehdi; Goodson, Ken; Yuan, Yi; Najafi, Khalil

2017-05-01

Thermoelectric energy harvesters convert otherwise wasted heat into electrical energy. As a result, they have the potential to play a critical role in the autonomous wireless sensor network signal chain. In this paper, we present work carried out on the development of Bi2Te3-based thermoelectric chip-scale energy harvesting devices. Process flow, device demonstration and characterization are highlighted.

Full scale tests on remote handled FFTF fuel assembly waste handling and packaging

International Nuclear Information System (INIS)

Allen, C.R.; Cash, R.J.; Dawson, S.A.; Strode, J.N.

1986-01-01

Handling and packaging of remote handled, high activity solid waste fuel assembly hardware components from spent FFTF reactor fuel assemblies have been evaluated using full scale components. The demonstration was performed using FFTF fuel assembly components and simulated components which were handled remotely using electromechanical manipulators, shielding walls, master slave manipulators, specially designed grapples, and remote TV viewing. The testing and evaluation included handling, packaging for current and conceptual shipping containers, and the effects of volume reduction on packing efficiency and shielding requirements. Effects of waste segregation into transuranic (TRU) and non-transuranic fractions also are discussed

Opto-electronic DNA chip-based integrated card for clinical diagnostics.

Science.gov (United States)

Marchand, Gilles; Broyer, Patrick; Lanet, Véronique; Delattre, Cyril; Foucault, Frédéric; Menou, Lionel; Calvas, Bernard; Roller, Denis; Ginot, Frédéric; Campagnolo, Raymond; Mallard, Frédéric

2008-02-01

Clinical diagnostics is one of the most promising applications for microfluidic lab-on-a-chip or lab-on-card systems. DNA chips, which provide multiparametric data, are privileged tools for genomic analysis. However, automation of molecular biology protocol and use of these DNA chips in fully integrated systems remains a great challenge. Simplicity of chip and/or card/instrument interfaces is amongst the most critical issues to be addressed. Indeed, current detection systems for DNA chip reading are often complex, expensive, bulky and even limited in terms of sensitivity or accuracy. Furthermore, for liquid handling in the lab-on-cards, many devices use complex and bulky systems, either to directly manipulate fluids, or to ensure pneumatic or mechanical control of integrated valves. All these drawbacks prevent or limit the use of DNA-chip-based integrated systems, for point-of-care testing or as a routine diagnostics tool. We present here a DNA-chip-based protocol integration on a plastic card for clinical diagnostics applications including: (1) an opto-electronic DNA-chip, (2) fluid handling using electrically activated embedded pyrotechnic microvalves with closing/opening functions. We demonstrate both fluidic and electric packaging of the optoelectronic DNA chip without major alteration of its electronical and biological functionalities, and fluid control using novel electrically activable pyrotechnic microvalves. Finally, we suggest a complete design of a card dedicated to automation of a complex biological protocol with a fully electrical fluid handling and DNA chip reading.

Integration of microelectronic chips in microfluidic systems on printed circuit board

International Nuclear Information System (INIS)

Burdallo, I; Jimenez-Jorquera, C; Fernández-Sánchez, C; Baldi, A

2012-01-01

A new scheme for the integration of small semiconductor transducer chips with microfluidic structures on printed circuit board (PCB) is presented. The proposed approach is based on a packaging technique that yields a large and flat area with small and shallow (∼44 µm deep) openings over the chips. The photocurable encapsulant material used, based on a diacrylate bisphenol A polymer, enables irreversible bonding of polydimethylsiloxane microfluidic structures at moderate temperatures (80 °C). This integration scheme enables the insertion of transducer chips in microfluidic systems with a lower added volume than previous schemes. Leakage tests have shown that the bonded structures withstand more than 360 kPa of pressure. A prototype microfluidic system with two detection chips, including one inter-digitated electrode (IDE) chip for conductivity and one ion selective field effect transistor (ISFET) chip for pH, has been implemented and characterized. Good electrical insulation of the chip contacts and silicon edge surfaces from the solution in the microchannels has been achieved. This integration procedure opens the door to the low-cost fabrication of complex analytical microsystems that combine the extraordinary potential of both the microfluidics and silicon microtechnology fields. (paper)

Systematic study of packaging designs on the performance of CMOS thermoresistive micro calorimetric flow sensors

International Nuclear Information System (INIS)

Xu, Wei; Gao, Bo; Xu, Kun; Lee, Yi-Kuen; Pan, Liang; Chiu, Yi

2017-01-01

We systematically study the effect of two packaging configurations for the CMOS thermoresistive micro calorimetric flow (TMCF) sensors: S-type with the sensor chip protrusion-mounted on the flow channel wall and E-type with the sensor chip flush-mounted on the flow channel wall. Although the experimental results indicated that the sensitivity of the S-type was increased by more than 30%; the corresponding flow range as compared to the E-type was dramatically reduced by 60% from 0–11 m s −1 to 0–4.5 m s −1 . Comprehensive 2D CFD simulation and in-house developed 3D numerical simulations based on the gas-kinetic scheme were applied to study the flow separation of these two packaging designs with the major parameters. Indeed, the S-type design with the large protrusion would change the local convective heat transfer of the TMCF sensor and dramatically decrease the sensors’ performance. In addition, parametric CFD simulations of the packaging designs provide inspiration to propose a novel general flow regime map (FRM), i.e. normalized protrusion d * versus reduced chip Reynolds number Re * , where the critical boundary curve for the flow separation of TMCF sensors was determined at different channel aspect ratios. The proposed FRM can be a useful guideline for the packaging design and manufacturing of different micro thermal flow sensors. (paper)

Warpage behavior analysis in package processes of embedded copper substrates

Directory of Open Access Journals (Sweden)

Hwang Yeong-Maw

2017-01-01

Full Text Available With the advance of the semiconductor industry and in response to the demands of ultra-thin products, packaging technology has been continuously developed. Thermal bonding process of copper pillar flip chip packages is a new bonding process in packaging technology, especially for substrates with embedded copper trace. During the packaging process, the substrate usually warps because of the heating process. In this paper, a finite element software ANSYS is used to model the embedded copper trace substrate and simulate the thermal and deformation behaviors of the substrate during the heating package process. A fixed geometric configuration equivalent to the real structure is duplicated to make the simulation of the warpage behavior of the substrate feasible. An empirical formula for predicting the warpage displacements is also established.

CMOS capacitive sensors for lab-on-chip applications a multidisciplinary approach

CERN Document Server

Ghafar-Zadeh, Ebrahim

2010-01-01

The main components of CMOS capacitive biosensors including sensing electrodes, bio-functionalized sensing layer, interface circuitries and microfluidic packaging are verbosely explained in chapters 2-6 after a brief introduction on CMOS based LoCs in Chapter 1. CMOS Capacitive Sensors for Lab-on-Chip Applications is written in a simple pedagogical way. It emphasises practical aspects of fully integrated CMOS biosensors rather than mathematical calculations and theoretical details. By using CMOS Capacitive Sensors for Lab-on-Chip Applications, the reader will have circuit design methodologies,

A fully packaged micromachined single crystalline resonant force sensor

Energy Technology Data Exchange (ETDEWEB)

Cavalloni, C.; Gnielka, M.; Berg, J. von [Kistler Instrumente AG, Winterthur (Switzerland); Haueis, M.; Dual, J. [ETH Zuerich, Inst. of Mechanical Systems, Zuerich (Switzerland); Buser, R. [Interstate Univ. of Applied Science Buchs, Buchs (Switzerland)

2001-07-01

In this work a fully packaged resonant force sensor for static load measurements is presented. The working principle is based on the shift of the resonance frequency in response to the applied load. The heart of the sensor, the resonant structure, is fabricated by micromachining using single crystalline silicon. To avoid creep and hysteresis and to minimize temperature induced stress the resonant structure is encapsulated using an all-in-silicon solution. This means that the load coupling, the excitation of the microresonator and the detection of the oscillation signal are integrated in only one single crystalline silicon chip. The chip is packaged into a specially designed housing made of steel which has been designed with respect to application in harsh environments. The unloaded sensor has an initial frequency of about 22,5 kHz. The sensitivity amounts to 26 Hz/N with a linearity error significantly less than 0,5%FSO. (orig.)

In-situ volumetric topography of IC chips for defect detection using infrared confocal measurement with active structured light

International Nuclear Information System (INIS)

Chen, Liang-Chia; Le, Manh-Trung; Phuc, Dao Cong; Lin, Shyh-Tsong

2014-01-01

The article presents the development of in-situ integrated circuit (IC) chip defect detection techniques for automated clipping detection by proposing infrared imaging and full-field volumetric topography. IC chip inspection, especially held during or post IC packaging, has become an extremely critical procedure in IC fabrication to assure manufacturing quality and reduce production costs. To address this, in the article, microscopic infrared imaging using an electromagnetic light spectrum that ranges from 0.9 to 1.7 µm is developed to perform volumetric inspection of IC chips, in order to identify important defects such as silicon clipping, cracking or peeling. The main difficulty of infrared (IR) volumetric imaging lies in its poor image contrast, which makes it incapable of achieving reliable inspection, as infrared imaging is sensitive to temperature difference but insensitive to geometric variance of materials, resulting in difficulty detecting and quantifying defects precisely. To overcome this, 3D volumetric topography based on 3D infrared confocal measurement with active structured light, as well as light refractive matching principles, is developed to detect defects the size, shape and position of defects in ICs. The experimental results show that the algorithm is effective and suitable for in-situ defect detection of IC semiconductor packaging. The quality of defect detection, such as measurement repeatability and accuracy, is addressed. Confirmed by the experimental results, the depth measurement resolution can reach up to 0.3 µm, and the depth measurement uncertainty with one standard deviation was verified to be less than 1.0% of the full-scale depth-measuring range. (paper)

Development of the simulation package 'ELSES' for extra-large-scale electronic structure calculation

International Nuclear Information System (INIS)

Hoshi, T; Fujiwara, T

2009-01-01

An early-stage version of the simulation package 'ELSES' (extra-large-scale electronic structure calculation) is developed for simulating the electronic structure and dynamics of large systems, particularly nanometer-scale and ten-nanometer-scale systems (see www.elses.jp). Input and output files are written in the extensible markup language (XML) style for general users. Related pre-/post-simulation tools are also available. A practical workflow and an example are described. A test calculation for the GaAs bulk system is shown, to demonstrate that the present code can handle systems with more than one atom species. Several future aspects are also discussed.

The composing technique of fast and large scale nuclear data acquisition and control system with single chip microcomputers and PC computers

International Nuclear Information System (INIS)

Xu Zurun; Wu Shiying; Liu Haitao; Yao Yangsen; Wang Yingguan; Yang Chaowen

1998-01-01

The technique of employing single-chip microcomputers and PC computers to compose a fast and large scale nuclear data acquisition and control system was discussed in detail. The optimum composition mode of this kind of system, the acquisition and control circuit unit based on single-chip microcomputers, the real-time communication methods and the software composition under the Windows 3.2 were also described. One, two and three dimensional spectra measured by this system were demonstrated

The composing technique of fast and large scale nuclear data acquisition and control system with single chip microcomputers and PC computers

International Nuclear Information System (INIS)

Xu Zurun; Wu Shiying; Liu Haitao; Yao Yangsen; Wang Yingguan; Yang Chaowen

1997-01-01

The technique of employing single-chip microcomputers and PC computers to compose a fast and large scale nuclear data acquisition and control system was discussed in detail. The optimum composition mode of this kind of system, the acquisition and control circuit unit based on single-chip microcomputers, the real-time communication methods and the software composition under the Windows 3.2 were also described. One, two and three dimensional spectra measured by this system were demonstrated

Design of a small scale boiler package for testing high moisture content biofuels

Energy Technology Data Exchange (ETDEWEB)

Proctor, Andrew

2005-07-01

This report presents the results of a project to design a prototype, small-scale boiler (0.88 MWth output) to enable clean and efficient combustion of high moisture content (>30%) biomass fuels. The boiler was based on an open bottom smoke tube design, modified to incorporate water tubes in the combustion chamber running from front to back. These were added to support refractory bricks to create an extra pass in the boiler combustion chamber such that the reflected heat from the refractory increased the rate of evaporation of moisture from the fuel. A chain grate stoker was employed. The combustion tests involved three biofuels: wood pellets with a low moisture content (8-10%) (to provide combustion rates for a commercially proven biofuel); wood chips from forestry waste with a 30-40% moisture content; and spent mushroom compost with 70-75% moisture. The tests on the wood chips required a number of modifications to the fuel feeding system and to the boiler in order to achieve limited success and the tests with the mushroom compost were unsuccessful due to the combination of the high moisture content and the fuel's low calorific value. Experience gained with the wood chips suggested a number of improvements for a future boiler design. As well as describing the experimental work and test results, the report offers an economic analysis (capital costs, fuel costs, running costs) of the scheme.

Coupling structure in LED System-In-Package design: a physical responses-based critical parameter sheet like approach

NARCIS (Netherlands)

Borst, de E.C.M.; Gielen, A.W.J.; Etman, L.F.P.

2012-01-01

Abstract This paper introduces an approach to study the coupling structure between the design parameters and design objectives of a LED system-in-package (SiP) design concept [1]. The LED SiP is an integrated device that combines the LED chip with driver chips and potential other components in a

Coupling structure in LED System-in-Package design: a physical responses-based critical parameter sheet like approach

NARCIS (Netherlands)

Borst, E.C.M. de; Gielen, A.W.J.; Etman, L.F.P.

2012-01-01

This paper introduces an approach to study the coupling structure between the design parameters and design objectives of a LED system-in-package (SiP) design concept [1]. The LED SiP is an integrated device that combines the LED chip with driver chips and potential other components in a single

Advanced chip designs and novel cooling techniques for brightness scaling of industrial, high power diode laser bars

Science.gov (United States)

Heinemann, S.; McDougall, S. D.; Ryu, G.; Zhao, L.; Liu, X.; Holy, C.; Jiang, C.-L.; Modak, P.; Xiong, Y.; Vethake, T.; Strohmaier, S. G.; Schmidt, B.; Zimer, H.

2018-02-01

The advance of high power semiconductor diode laser technology is driven by the rapidly growing industrial laser market, with such high power solid state laser systems requiring ever more reliable diode sources with higher brightness and efficiency at lower cost. In this paper we report simulation and experimental data demonstrating most recent progress in high brightness semiconductor laser bars for industrial applications. The advancements are in three principle areas: vertical laser chip epitaxy design, lateral laser chip current injection control, and chip cooling technology. With such improvements, we demonstrate disk laser pump laser bars with output power over 250W with 60% efficiency at the operating current. Ion implantation was investigated for improved current confinement. Initial lifetime tests show excellent reliability. For direct diode applications 96% polarization are additional requirements. Double sided cooling deploying hard solder and optimized laser design enable single emitter performance also for high fill factor bars and allow further power scaling to more than 350W with 65% peak efficiency with less than 8 degrees slow axis divergence and high polarization.

Cleanup Verification Package for the 118-F-1 Burial Ground

Energy Technology Data Exchange (ETDEWEB)

E. J. Farris and H. M. Sulloway

2008-01-10

This cleanup verification package documents completion of remedial action for the 118-F-1 Burial Ground on the Hanford Site. This burial ground is a combination of two locations formerly called Minor Construction Burial Ground No. 2 and Solid Waste Burial Ground No. 2. This waste site received radioactive equipment and other miscellaneous waste from 105-F Reactor operations, including dummy elements and irradiated process tubing; gun barrel tips, steel sleeves, and metal chips removed from the reactor; filter boxes containing reactor graphite chips; and miscellaneous construction solid waste.

Packaging technology of LEDs for LCD backlights

International Nuclear Information System (INIS)

Fan Manning; Liang Meng; Wang Guohong

2009-01-01

We design a package patterned with red and green emitting phosphors excited by a blue LED to emit tri-basic mixing color. For high backlight display quality, we compare several phosphors. According to our measurements, green phosphors 0752G, 0753G and red phosphor 0763R are preferred for producing a good backlight source. Compared to RGB-LED backlight units, this frame typically benefits the lighting uniformity, and can simplify the structures. It also provides higher color render and better CCT than the traditional package method of a yellow phosphor with a blue chip. However, its light efficiency needs to be further improved for the use of backlights for LCDs.

Wafer Scale Integration of CMOS Chips for Biomedical Applications via Self-Aligned Masking.

Science.gov (United States)

Uddin, Ashfaque; Milaninia, Kaveh; Chen, Chin-Hsuan; Theogarajan, Luke

2011-12-01

This paper presents a novel technique for the integration of small CMOS chips into a large area substrate. A key component of the technique is the CMOS chip based self-aligned masking. This allows for the fabrication of sockets in wafers that are at most 5 µm larger than the chip on each side. The chip and the large area substrate are bonded onto a carrier such that the top surfaces of the two components are flush. The unique features of this technique enable the integration of macroscale components, such as leads and microfluidics. Furthermore, the integration process allows for MEMS micromachining after CMOS die-wafer integration. To demonstrate the capabilities of the proposed technology, a low-power integrated potentiostat chip for biosensing implemented in the AMI 0.5 µm CMOS technology is integrated in a silicon substrate. The horizontal gap and the vertical displacement between the chip and the large area substrate measured after the integration were 4 µm and 0.5 µm, respectively. A number of 104 interconnects are patterned with high-precision alignment. Electrical measurements have shown that the functionality of the chip is not affected by the integration process.

A survey of research and practices of network-on-chip

DEFF Research Database (Denmark)

Bjerregaard, Tobias; Mahadevan, Shankar

2006-01-01

The scaling of microchip technologies has enabled large scale systems-on-chip (SoC). Network-on-chip (NoC) research addresses global communication in SoC, involving (i) a move from computation-centric to communication-centric design and (ii) the implementation of scalable communication structures...

Wood chip delivery and research project at Mikkeli region

International Nuclear Information System (INIS)

Saksa, T.; Auvinen, P.

1995-01-01

In 1994, a large-scale energywood production chain was started as a co-operation project by the Mikkeli city forest office and local forestry societies. Over 60 000 m 3 (about 46 000 MWh of energy) of forest processed chips were delivered to Pursiala heat and power plant in Mikkeli. About 60 % of these chips was whole tree chips from improvement cuttings of young forest stands and the rest was logging waste chips from regeneration cutting areas. The average total delivery costs of forest processed chips after reduction of energywood and other subsidies were approximately 51 FIM/m 3 (68 FIM/MWh) for the whole tree chips and 40 FIM/m 3 (53 FIM/MWh) for logging waste chips. The delivery costs of wood chips could compete with those of fuel peat only in the most favourable cases. The resources of forest processed chips were studied on the basis of forestry plans. According to the study, there is enough raw material for permanent, large-scale delivery of forest processed chips (up to 250 000 m 3 /a) in the forests located at a distance of under 40 road kilometers from the Pursiala heat and power plant. The following project stages will involve further development of the wood chip delivery chain logistics, as well as improvement of logging and chipping equipment and methods in energywood and logging waste production. Also the effects of wood energy production on the economy and environment of the whole Mikkeli region will be studied. (author)

Examination of shipping package 9975-04985

Energy Technology Data Exchange (ETDEWEB)

Daugherty, W. L. [Savannah River Site (SRS), Aiken, SC (United States). Savannah River National Lab. (SRNL)

2017-08-01

Package 9975-04985 was examined following the identification of several unexpected conditions during surveillance activities. A heavy layer of corrosion product on the shield and the shield outer diameter being larger that allowed by drawing tolerances contributed to a very tight fit between the upper fiberboard assembly and shield. The average corrosion rate for the shield is estimated to be 0.0018 inch/year or less, which falls within the bounding rate of 0.002 inch/year that has been previously recommended for these packages. Several apparent foreign objects were noted within the package. One object observed on the air shield was identified as tape. The other objects were comprised of mostly fine fibers from the cane fiberboard. It is postulated that the upper and lower fiberboard assemblies were able to rub against each other due to the upper fiberboard assembly being held tight to the shield, and a few stray cane chips became frayed under vibratory motions.

Enhanced lateral heat dissipation packaging structure for GaN HEMTs on Si substrate

International Nuclear Information System (INIS)

Cheng, Stone; Chou, Po-Chien; Chieng, Wei-Hua; Chang, E.Y.

2013-01-01

This work presents a technology for packaging AlGaN/GaN high electron mobility transistors (HEMTs) on a Si substrate. The GaN HEMTs are attached to a V-groove copper base and mounted on a TO-3P leadframe. The various thermal paths from the GaN gate junction to the case are carried out for heat dissipation by spreading to protective coating; transferring through the bond wires; spreading in the lateral device structure through the adhesive layer, and vertical heat spreading of silicon chip bottom. Thermal characterization showed a thermal resistance of 13.72 °C/W from the device to the TO-3P package. Experimental tests of a 30 mm gate-periphery single chip packaged in a 5 × 3 mm V-groove Cu base with a 100 V drain bias showed power dissipation of 22 W. -- Highlights: ► An enhanced packaging structure designed for AlGaN/GaN HEMTs on an Si substrate. ► The V-groove copper base is designed on the device periphery surface heat conduction for enhancing Si substrate thermal dissipation. ► The proposed device shows a lower thermal resistance and upgrade in thermal conductivity capability. ► This work provides useful thermal IR imagery information to aid in designing high efficiency package for GaN HEMTs on Si

Preservation of forest wood chips

Energy Technology Data Exchange (ETDEWEB)

Kofman, P.D.; Thomsen, I.M.; Ohlsson, C.; Leer, E.; Ravn Schmidt, E.; Soerensen, M.; Knudsen, P.

1999-01-01

As part of the Danish Energy Research Programme on biomass utilisation for energy production (EFP), this project concerns problems connected to the handling and storing of wood chips. In this project, the possibility of preserving wood chips of the Norway Spruce (Picea Abies) is addressed, and the potential improvements by anaerobic storage are tested. Preservation of wood chips aims at reducing dry matter losses from extensive heating during storage and to reduce production of fungal spores. Fungal spores pose a health hazards to workers handling the chips. Further the producers of wood chips are interested in such a method since it would enable them to give a guarantee for the delivery of homogeneous wood chips also during the winter period. Three different types of wood chips were stored airtight and further one of these was stored in accordance with normal practise and use as reference. The results showed that airtight storage had a beneficial impact on the quality of the chips: no redistribution of moisture, low dry matter losses, unfavourable conditions for microbial activity of most fungi, and the promotion of yeasts instead of fungi with airborne spores. Likewise the firing tests showed that no combustion problems, and no increased risk to the environment or to the health of staff is caused by anaerobic storage of wood chips. In all, the tests of the anaerobic storage method of forest wood chips were a success and a large-scale test of the method will be carried out in 1999. (au)

Packaging's Contribution for the Effectiveness of the Space Station's Food Service Operation

Science.gov (United States)

Rausch, B. A.

1985-01-01

Storage limitations will have a major effect on space station food service. For example: foods with low bulk density such as ice cream, bread, cake, standard type potato chips and other low density snacks, flaked cereals, etc., will exacerbate the problem of space limitations; package containers are inherently volume consuming and refuse creating; and the useful observation that the optimum package is no package at all leads to the tentative conclusion that the least amount of packaging per unit of food, consistent with storage, aesthetics, preservation, cleanliness, cost and disposal criteria, is the most practical food package for the space station. A series of trade offs may have to be made to arrive at the most appropriate package design for a particular type of food taking all the criteria into account. Some of these trade offs are: single serve vs. bulk; conventional oven vs. microwave oven; nonmetallic aseptically vs. non-aseptically packaged foods; and comparison of aseptic vs. nonaseptic food packages. The advantages and disadvantages are discussed.

Review of chip-scale atomic clocks based on coherent population trapping

International Nuclear Information System (INIS)

Wang Zhong

2014-01-01

Research on chip-scale atomic clocks (CSACs) based on coherent population trapping (CPT) is reviewed. The background and the inspiration for the research are described, including the important schemes proposed to improve the CPT signal quality, the selection of atoms and buffer gases, and the development of micro-cell fabrication. With regard to the reliability, stability, and service life of the CSACs, the research regarding the sensitivity of the CPT resonance to temperature and laser power changes is also reviewed, as well as the CPT resonance's collision and light of frequency shifts. The first generation CSACs have already been developed but its characters are still far from our expectations. Our conclusion is that miniaturization and power reduction are the most important aspects calling for further research. (review)

Chip-scale fluorescence microscope based on a silo-filter complementary metal-oxide semiconductor image sensor.

Science.gov (United States)

Ah Lee, Seung; Ou, Xiaoze; Lee, J Eugene; Yang, Changhuei

2013-06-01

We demonstrate a silo-filter (SF) complementary metal-oxide semiconductor (CMOS) image sensor for a chip-scale fluorescence microscope. The extruded pixel design with metal walls between neighboring pixels guides fluorescence emission through the thick absorptive filter to the photodiode of a pixel. Our prototype device achieves 13 μm resolution over a wide field of view (4.8 mm × 4.4 mm). We demonstrate bright-field and fluorescence longitudinal imaging of living cells in a compact, low-cost configuration.

Development in Electronic Packaging – Moving to 3D System Configuration

Directory of Open Access Journals (Sweden)

I. Szendiuch

2011-04-01

Full Text Available The electronic industry is reducing package dimensions of components as well as complete electronics systems. Surface mount device passives and semiconductor chips have to be mounted together bringing a functional system that must realize the required function with necessary reliability and acceptable price. To make up a reliable and cost effective system, the size and weight is being reduced by employing lower voltages and higher speeds. For example, the typical size of SMD passives 30 years ago was 1206 when they were first introduced. Generally, all components including electrical joints are becoming miniaturized and smaller. The industry is moving toward a reduced size of 0201 and 01005 for passives, new fine pitch packages for actives, but the PCB now feature limits for further integration. System on Package (SOP is one way to reach the three-dimensional package concept where components will be placed in three-dimensional configuration. A similar concepts are “Package on Package” (PoP or ”Package in Package” (PiP.

Chips in black boxes? Convenience life span, parafood, brandwidth, families, and co-creation.

Science.gov (United States)

Jacobs, Marc

2015-11-01

Any consumer who opens a bag of potato or corn chips (or crisps in the UK) knows there is no time to waste to enjoy or share them. The convenience life span of chips is limited: it is the shelf or storage life and a very limited time once outside the bag. Many technologies converge to generate the desired effect as a black box, not only of the packaging but also of the chips themselves. The concept of paratext can be applied to printed messages on the package, including the brand name and other texts like advertising (epitexts), which can be expanded into the concept of parafood. These concepts help to discuss technological developments and interpret why this has recently become a negotiation zone for co-creation (see the Do us a flavor campaigns). They are symptoms of changing relations between production, research and development, marketing, and consumption. This paper pays special attention to back stories, underdog brand biographies and narratives about origin. The concept of brandwidth is introduced to sensitize about the limits of combining different stories about chips. A recent brand biography, a family history and a cookery book are used to discuss the phenomenon of cooking with Fritos. Together with the concepts of parafood, brandwidth and black boxes, more reflection and dialogue about the role of history and heritage in marketing put new challenging perspectives on the agenda. Copyright © 2015 Elsevier Ltd. All rights reserved.

A review of digital microfluidics as portable platforms for lab-on a-chip applications.

Science.gov (United States)

Samiei, Ehsan; Tabrizian, Maryam; Hoorfar, Mina

2016-07-07

Following the development of microfluidic systems, there has been a high tendency towards developing lab-on-a-chip devices for biochemical applications. A great deal of effort has been devoted to improve and advance these devices with the goal of performing complete sets of biochemical assays on the device and possibly developing portable platforms for point of care applications. Among the different microfluidic systems used for such a purpose, digital microfluidics (DMF) shows high flexibility and capability of performing multiplex and parallel biochemical operations, and hence, has been considered as a suitable candidate for lab-on-a-chip applications. In this review, we discuss the most recent advances in the DMF platforms, and evaluate the feasibility of developing multifunctional packages for performing complete sets of processes of biochemical assays, particularly for point-of-care applications. The progress in the development of DMF systems is reviewed from eight different aspects, including device fabrication, basic fluidic operations, automation, manipulation of biological samples, advanced operations, detection, biological applications, and finally, packaging and portability of the DMF devices. Success in developing the lab-on-a-chip DMF devices will be concluded based on the advances achieved in each of these aspects.

An economic evaluation of a chlorhexidine chip for treating chronic periodontitis: the CHIP (chlorhexidine in periodontitis) study.

Science.gov (United States)

Henke, C J; Villa, K F; Aichelmann-Reidy, M E; Armitage, G C; Eber, R M; Genco, R J; Killoy, W J; Miller, D P; Page, R C; Polson, A M; Ryder, M I; Silva, S J; Somerman, M J; Van Dyke, T E; Wolff, L F; Evans, C J; Finkelman, R D

2001-11-01

The authors previously suggested that an adjunctive, controlled-release chlorhexidine, or CHX, chip may reduce periodontal surgical needs at little additional cost. This article presents an economic analysis of the CHX chip in general dental practice. In a one-year prospective clinical trial, 484 chronic periodontitis patients in 52 general practices across the United States were treated with either scaling and root planing, or SRP, plus any therapy prescribed by treating, unblinded dentists; or SRP plus other therapy as above but including the CHX chip. Economic data were collected from bills, case report forms and 12-month treatment recommendations from blinded periodontist evaluators. Total dental charges were higher for SRP + CHX chip patients vs. SRP patients when CHX chip costs were included (P = .027) but lower when CHX chip costs were excluded (P = .012). About one-half of the CHX chip acquisition cost was offset by savings in other charges. SRP + CHX chip patients were about 50 percent less likely to undergo surgical procedures than were SRP patients (P = .021). At the end of the trial, periodontist evaluators recommended similar additional procedures for both groups: SRP, about 46 percent; maintenance, about 37 percent; surgery, 56 percent for SRP alone and 63 percent for SRP + CHX chip. Adjunctive CHX chip use for general-practice patients with periodontitis increased costs but reduced surgeries over one year. At study's end, periodontists recommended similar additional surgical treatment for both groups. In general practice, routine use of the CHX chip suggests that costs will be partially offset by reduced surgery over at least one year.

ChAMP: updated methylation analysis pipeline for Illumina BeadChips.

Science.gov (United States)

Tian, Yuan; Morris, Tiffany J; Webster, Amy P; Yang, Zhen; Beck, Stephan; Feber, Andrew; Teschendorff, Andrew E

2017-12-15

The Illumina Infinium HumanMethylationEPIC BeadChip is the new platform for high-throughput DNA methylation analysis, effectively doubling the coverage compared to the older 450 K array. Here we present a significantly updated and improved version of the Bioconductor package ChAMP, which can be used to analyze EPIC and 450k data. Many enhanced functionalities have been added, including correction for cell-type heterogeneity, network analysis and a series of interactive graphical user interfaces. ChAMP is a BioC package available from https://bioconductor.org/packages/release/bioc/html/ChAMP.html. a.teschendorff@ucl.ac.uk or s.beck@ucl.ac.uk or a.feber@ucl.ac.uk. Supplementary data are available at Bioinformatics online. © The Author(s) 2017. Published by Oxford University Press.

Heat management in integrated circuits on-chip and system-level monitoring and cooling

CERN Document Server

Ogrenci-Memik, Seda

2016-01-01

This essential overview covers the subject of thermal monitoring and management in integrated circuits. Specifically, it focuses on devices and materials that are intimately integrated on-chip (as opposed to in-package or on-board) for the purposes of thermal monitoring and thermal management.

Design and fabrication of a foldable 3D silicon based package for solid state lighting applications

International Nuclear Information System (INIS)

Sokolovskij, R; Liu, P; Van Zeijl, H W; Mimoun, B; Zhang, G Q

2015-01-01

Miniaturization of solid state lighting (SSL) luminaires as well as reduction of packaging and assembly costs are of prime interest for the SSL lighting industry. A novel silicon based LED package for lighting applications is presented in this paper. The proposed design consists of 5 rigid Si tiles connected by flexible polyimide hinges with embedded interconnects (ICs). Electrical, optical and thermal characteristics were taken into consideration during design. The fabrication process involved polyimide (PI) application and patterning, aluminium interconnect integration in the flexible hinge, LED reflector cavity formation and metalization followed by through wafer DRIE etching for chip formation and release. A method to connect chip front to backside without TSVs was also integrated into the process. Post-fabrication wafer level assembly included LED mounting and wirebond, phosphor-based colour conversion and silicone encapsulation. The package formation was finalized by vacuum assisted wrapping around an assembly structure to form a 3D geometry, which is beneficial for omnidirectional lighting. Bending tests were performed on the flexible ICs and optical performance at different temperatures was evaluated. It is suggested that 3D packages can be expanded to platforms for miniaturized luminaire applications by combining monolithic silicon integration and system-in-package (SiP) technologies. (paper)

Design aspects of plutonium air-transportable packages

International Nuclear Information System (INIS)

Allen, G.C.; Moya, J.L.; Pierce, J.D.; Attaway, S.W.

1989-01-01

Recent worldwide interest in transporting plutonium powders by air has created a need for expanding the packaging technology base as well as improving their understanding of how plutonium air transport (PAT) packagings perform during severe accident tests. Historically it has not been possible to establish design rules for individual package components because of the complex way parts interacted in forming a successful whole unit. Also, computer analyses were only considered valid for very limited portions of the design effort because of large deformations, localized tearing occurring in the package during accident testing, and extensive use of orthotropic materials. Consequently, iterative design and experimentation has historically been used to develop plutonium air-transportable packages. Full-scale prototypes have been tested since scaling of packages utilizing wood as an energy absorber and thermal insulator has not proven to be very successful. This is because the wood grain and dynamic performance of the wood during crush do not always scale. The high cost of full-scale testing of large packages has certainly hindered obtaining additional data and development new designs. The testing criteria for PAT packages, as described in the US Nuclear Regulatory Commission's Qualification Criteria to Certify a Package for Air Transport of Plutonium, NUREG-0360, 1978, are summarized. Computer modeling techniques have greatly improved over the last ten years, and there are some areas of opportunity for future applications to plutonium air-transportable package design problems. Having developed a better understanding of the performance of current packages, they have the opportunity to make major improvements in new packaging concepts. Each of these areas is explored in further depth to establish their impact on design practices for air-transportable packages

A 4 × 2 switch matrix in QFN24 package for 0.5–3 GHz application

International Nuclear Information System (INIS)

Liu Yuzhe; Mu Pengfei; Gong Renjie; Wan Jing; Zhang Yulin; Yan Yuepeng

2014-01-01

This paper presents a 4 × 2 switching matrix implemented in the Win 0.5 μm GaAs pseudomorphic high electron mobility transistor process, it covers the 0.5–3 GHz frequency range. The switch matrix is composed of 4 SPDT switch whose two output ports can simultaneously select the input port and a 4 to 8 bit digital decoder, both the radio frequency (RF) part and the digital part are integrated into one single chip. The chip is packaged in a low cost QFN24 plastic package. On chip shunt, capacitors at the input ports are taken to compensate for the bonding wire inductance effect. The designed switch matrix shows a good measured performance: the insertion loss is less than 5.5 dB, the isolation is no worse than 30 dB, the return loss of input ports and output ports is better than −10 dB, the input 1 dB compression point is better than 25.6 dBm, and the OIP3 is better than 37 dBm. The chip size of the switch matrix is only 1.45 × 1.45 mm 2 . (semiconductor integrated circuits)

Monolithically Integrated Light Feedback Control Circuit for Blue/UV LED Smart Package

NARCIS (Netherlands)

Koladouz Esfahani, Z.; Tohidian, M.; van Zeijl, H.W.; Kolahdouz, Mohammadreza; Zhang, G.Q.

2017-01-01

Given the performance decay of high-power light-emitting diode (LED) chips over time and package condition changes, having a reliable output light for sensitive applications is a point of concern. In this study, a light feedback control circuit, including blue-selective photodiodes, for

NASA Electronic Parts and Packaging (NEPP) Program - Update

Science.gov (United States)

LaBel, Kenneth A.; Sampson, Michael J.

2010-01-01

This slide presentation reviews the goals and mission of the NASA Electronic Parts and Packaging (NEPP) Program. The NEPP mission is to provide guidance to NASA for the selection and application of microelectronics technologies, to improve understanding of the risks related to the use of these technologies in the space environment and to ensure that appropriate research is performed to meet NASA mission assurance needs. The program has been supporting NASA for over 20 years. The focus is on the reliability aspects of electronic devices. In this work the program also supports the electronics industry. There are several areas that the program is involved in: Memories, systems on a chip (SOCs), data conversion devices, power MOSFETS, power converters, scaled CMOS, capacitors, linear devices, fiber optics, and other electronics such as sensors, cryogenic and SiGe that are used in space systems. Each of these area are reviewed with the work that is being done in reliability and effects of radiation on these technologies.

Low Loss Nanostructured Polymers for Chip-scale Waveguide Amplifiers.

Science.gov (United States)

Chen, George F R; Zhao, Xinyu; Sun, Yang; He, Chaobin; Tan, Mei Chee; Tan, Dawn T H

2017-06-13

On-chip waveguide amplifiers offer higher gain in small device sizes and better integration with photonic devices than the commonly available fiber amplifiers. However, on-chip amplifiers have yet to make its way into the mainstream due to the limited availability of materials with ideal light guiding and amplification properties. A low-loss nanostructured on-chip channel polymeric waveguide amplifier was designed, characterized, fabricated and its gain experimentally measured at telecommunication wavelength. The active polymeric waveguide core comprises of NaYF 4 :Yb,Er,Ce core-shell nanocrystals dispersed within a SU8 polymer, where the nanoparticle interfacial characteristics were tailored using hydrolyzed polyhedral oligomeric silsesquioxane-graft-poly(methyl methacrylate) to improve particle dispersion. Both the enhanced IR emission intensity from our nanocrystals using a tri-dopant scheme and the reduced scattering losses from our excellent particle dispersion at a high solid loading of 6.0 vol% contributed to the outstanding optical performance of our polymeric waveguide. We achieved one of the highest reported gain of 6.6 dB/cm using a relatively low coupled pump power of 80 mW. These polymeric waveguide amplifiers offer greater promise for integrated optical circuits due to their processability and integration advantages which will play a key role in the emerging areas of flexible communication and optoelectronic devices.

A flip chip process based on electroplated solder bumps

Science.gov (United States)

Salonen, J.; Salmi, J.

1994-01-01

Compared to wire bonding and TAB, flip chip technology using solder joints offers the highest pin count and packaging density and superior electrical performance. The chips are mounted upside down on the substrate, which can be made of silicon, ceramic, glass or - in some cases - even PCB. The extra processing steps required for chips are the deposition of a suitable thin film metal layer(s) on the standard Al pad and the formation of bumps. Also, the development of new fine line substrate technologies is required to utilize the full potential of the technology. In our bumping process, bump deposition is done by electroplating, which was chosen for its simplicity and economy. Sputter deposited molybdenum and copper are used as thin film layers between the aluminum pads and the solder bumps. A reason for this choice is that the metals can be selectively etched after bumping using the bumps as a mask, thus circumventing the need for a separate mask for etching the thin film metals. The bumps are electroplated from a binary Pb-Sn bath using a thick liquid photoresist. An extensively modified commercial flip chip bonder is used for alignment and bonding. Heat assisted tack bonding is used to attach the chips to the substrate, and final reflow joining is done without flux in a vacuum furnace.

CMOS On-Chip Optoelectronic Neural Interface Device with Integrated Light Source for Optogenetics

International Nuclear Information System (INIS)

Sawadsaringkarn, Y; Kimura, H; Maezawa, Y; Nakajima, A; Kobayashi, T; Sasagawa, K; Noda, T; Tokuda, T; Ohta, J

2012-01-01

A novel optoelectronic neural interface device is proposed for target applications in optogenetics for neural science. The device consists of a light emitting diode (LED) array implemented on a CMOS image sensor for on-chip local light stimulation. In this study, we designed a suitable CMOS image sensor equipped with on-chip electrodes to drive the LEDs, and developed a device structure and packaging process for LED integration. The prototype device produced an illumination intensity of approximately 1 mW with a driving current of 2.0 mA, which is expected to be sufficient to activate channelrhodopsin (ChR2). We also demonstrated the functions of light stimulation and on-chip imaging using a brain slice from a mouse as a target sample.

Heat Transfer Characteristics in High Power LED Packaging

Directory of Open Access Journals (Sweden)

Chi-Hung Chung

2014-03-01

Full Text Available This study uses the T3Ster transient thermal resistance measuring device to investigate the effects to heat transfer performances from different LED crystal grains, packaging methods and heat-sink substrates through the experimental method. The experimental parameters are six different types of LED modules that are made alternatively with the crystal grain structure, the die attach method and the carrying substrate. The crystal grain structure includes the lateral type, flip chip type and vertical type. The die attach method includes silver paste and the eutectic structure. The carrying substrates are aluminum oxide (Alumina and aluminum nitride (AIN ceramic substrates and metal core PCB (MCPCB. The experimental results show that, under the conditions of the same crystal grain and die attach method, the thermal resistance values for the AIN substrate and the Alumina substrate are 2.1K/W and 5.1K/W, respectively and the total thermal resistance values are 7.3K/W and 10.8K/W. Compared to the Alumina substrate, the AIN substrate can effectively lower the total thermal resistance value by 32.4%. This is because the heat transfer coefficient of the AIN substrate is higher than that of the Alumina substrate, thus effectively increasing its thermal conductivity. In addition, under the conditions of the same crystal grain and the same substrate, the packaging methods are using silver paste and the eutectic structure for die attach. Their thermal resistance values are 5.7K/W and 2.7K/W, respectively, with a variance of 3K/W. Comparisons of the crystal grain structure show that the thermal resistance for the flip chip type is lower than that of the traditional lateral type by 0.9K/W. This is because the light emitting layer of the flip chip crystal grain is closer to the heat-sink substrate, shortening the heat dissipation route, and thus lowering the thermal resistance value. For the total thermal resistance, the crystal grain structure has a lesser

A New Test Device for Characterization of Mechanical Stress Caused by Packaging Processes

International Nuclear Information System (INIS)

Hirsch, Soeren; Doerner, Steffen; Hauptmann, Peter; Schmidt, Bertram

2006-01-01

This paper reports on a new method for estimation and minimization of mechanical stress on MEMS sensor and actuator structures due to packaging processes based on flip chip technology. For studying mechanical stress a test chip with silicon membranes was fabricated. A network of piezo-resistive solid state resistors created by diffusion was used to measure the surface tension pattern between adjacent membranes. Finite element method simulation was used to calculate the stress profile and to determine the optimum positions for placing the resistive network

Low-cost and versatile thermal test chip for power assemblies assessment and thermometric calibration purposes

International Nuclear Information System (INIS)

Jorda, X.; Perpina, X.; Vellvehi, M.; Madrid, F.; Flores, D.; Hidalgo, S.; Millan, J.

2011-01-01

Chips specifically designed for thermal tests such as the assessment of packages, are of main interest in Microelectronics. Nevertheless, these test dies are required in relatively low quantities and their price is a limiting factor. This work describes a low-cost thermal test chip, specifically developed for the needs of power electronics. It is based on a poly-silicon heating resistor and a decoupled Pt temperature sensing resistor on the top, allowing to dissipate more than 60 W (170 W/cm 2 ) and reaching temperatures up to 200 o C. Its simple structure allows an easy simulation and modeling. These features have been taken in profit for packaging materials assessment, calibration of temperature measurement apparatus and methods, and validation of thermal models and simulations. - Highlights: → We describe a low-cost thermal test chip developed for power electronics applications. → It integrates a poly-silicon heating resistor and a Pt temperature sensing resistor on the top. → It can dissipate up to 200 W/cm 2 and work up to 200 o C. → It has been used for thermal resistance and conductivity measurement of substrates. → It allowed also the calibration of advanced thermometric equipments.

3D stacked chips from emerging processes to heterogeneous systems

CERN Document Server

Fettweis, Gerhard

2016-01-01

This book explains for readers how 3D chip stacks promise to increase the level of on-chip integration, and to design new heterogeneous semiconductor devices that combine chips of different integration technologies (incl. sensors) in a single package of the smallest possible size.  The authors focus on heterogeneous 3D integration, addressing some of the most important challenges in this emerging technology, including contactless, optics-based, and carbon-nanotube-based 3D integration, as well as signal-integrity and thermal management issues in copper-based 3D integration. Coverage also includes the 3D heterogeneous integration of power sources, photonic devices, and non-volatile memories based on new materials systems.   •Provides single-source reference to the latest research in 3D optoelectronic integration: process, devices, and systems; •Explains the use of wireless 3D integration to improve 3D IC reliability and yield; •Describes techniques for monitoring and mitigating thermal behavior in 3D I...

Edible packaging materials.

Science.gov (United States)

Janjarasskul, Theeranun; Krochta, John M

2010-01-01

Research groups and the food and pharmaceutical industries recognize edible packaging as a useful alternative or addition to conventional packaging to reduce waste and to create novel applications for improving product stability, quality, safety, variety, and convenience for consumers. Recent studies have explored the ability of biopolymer-based food packaging materials to carry and control-release active compounds. As diverse edible packaging materials derived from various by-products or waste from food industry are being developed, the dry thermoplastic process is advancing rapidly as a feasible commercial edible packaging manufacturing process. The employment of nanocomposite concepts to edible packaging materials promises to improve barrier and mechanical properties and facilitate effective incorporation of bioactive ingredients and other designed functions. In addition to the need for a more fundamental understanding to enable design to desired specifications, edible packaging has to overcome challenges such as regulatory requirements, consumer acceptance, and scaling-up research concepts to commercial applications.

Broadband Packaging of Photodetectors for 100 Gb/s Ethernet Applications

DEFF Research Database (Denmark)

Jiang, Chenhui; Krozer, Viktor; Bach, Heinz-Gunter

2013-01-01

The packing structure of functional modules is a major limitaion in achieving a desired performance for 100 Gb/s ethernet applications. This paper presents a methodology of developing advanced packaging of photodetectors (PDs) for high-speed data transmission applications by using 3-D electromagn......The packing structure of functional modules is a major limitaion in achieving a desired performance for 100 Gb/s ethernet applications. This paper presents a methodology of developing advanced packaging of photodetectors (PDs) for high-speed data transmission applications by using 3-D...... electromagnetic (EM) simulations. A simplified model of the PD module is first used to analyze and optimize packaging structures and propose an optimal packaging design based on the simplified model. Although a PD module with improved performance proved the success of the optimal packaging design, the simplified...... of limiting the bandwidth of PD modules. After eliminating the mode mismatch effect by improving the chip-conductor-backed coplanar waveguide transition, a final optimal packaging structure is implemented for the PD module with reduced attenuation up to 100 GHz and a broader 3-dB bandwidth of more than 90 GHz...

Development of the simulation package 'ELSES' for extra-large-scale electronic structure calculation

Energy Technology Data Exchange (ETDEWEB)

Hoshi, T [Department of Applied Mathematics and Physics, Tottori University, Tottori 680-8550 (Japan); Fujiwara, T [Core Research for Evolutional Science and Technology, Japan Science and Technology Agency (CREST-JST) (Japan)

2009-02-11

An early-stage version of the simulation package 'ELSES' (extra-large-scale electronic structure calculation) is developed for simulating the electronic structure and dynamics of large systems, particularly nanometer-scale and ten-nanometer-scale systems (see www.elses.jp). Input and output files are written in the extensible markup language (XML) style for general users. Related pre-/post-simulation tools are also available. A practical workflow and an example are described. A test calculation for the GaAs bulk system is shown, to demonstrate that the present code can handle systems with more than one atom species. Several future aspects are also discussed.

Nanotechnology for Food Packaging and Food Quality Assessment.

Science.gov (United States)

Rossi, Marco; Passeri, Daniele; Sinibaldi, Alberto; Angjellari, Mariglen; Tamburri, Emanuela; Sorbo, Angela; Carata, Elisabetta; Dini, Luciana

Nanotechnology has paved the way to innovative food packaging materials and analytical methods to provide the consumers with healthier food and to reduce the ecological footprint of the whole food chain. Combining antimicrobial and antifouling properties, thermal and mechanical protection, oxygen and moisture barrier, as well as to verify the actual quality of food, e.g., sensors to detect spoilage, bacterial growth, and to monitor incorrect storage conditions, or anticounterfeiting devices in food packages may extend the products shelf life and ensure higher quality of foods. Also the ecological footprint of food chain can be reduced by developing new completely recyclable and/or biodegradable packages from natural and eco-friendly resources. The contribution of nanotechnologies to these goals is reviewed in this chapter, together with a description of portable devices ("lab-on-chip," sensors, nanobalances, etc.) which can be used to assess the quality of food and an overview of regulations in force on food contact materials. © 2017 Elsevier Inc. All rights reserved.

Adiabatic shear banding and scaling laws in chip formation with application to cutting of Ti-6Al-4V

Science.gov (United States)

Molinari, A.; Soldani, X.; Miguélez, M. H.

2013-11-01

The phenomenon of adiabatic shear banding is analyzed theoretically in the context of metal cutting. The mechanisms of material weakening that are accounted for are (i) thermal softening and (ii) material failure related to a critical value of the accumulated plastic strain. Orthogonal cutting is viewed as a unique configuration where adiabatic shear bands can be experimentally produced under well controlled loading conditions by individually tuning the cutting speed, the feed (uncut chip thickness) and the tool geometry. The role of cutting conditions on adiabatic shear banding and chip serration is investigated by combining finite element calculations and analytical modeling. This leads to the characterization and classification of different regimes of shear banding and the determination of scaling laws which involve dimensionless parameters representative of thermal and inertia effects. The analysis gives new insights into the physical aspects of plastic flow instability in chip formation. The originality with respect to classical works on adiabatic shear banding stems from the various facets of cutting conditions that influence shear banding and from the specific role exercised by convective flow on the evolution of shear bands. Shear bands are generated at the tool tip and propagate towards the chip free surface. They grow within the chip formation region while being convected away by chip flow. It is shown that important changes in the mechanism of shear banding take place when the characteristic time of shear band propagation becomes equal to a characteristic convection time. Application to Ti-6Al-4V titanium are considered and theoretical predictions are compared to available experimental data in a wide range of cutting speeds and feeds. The fundamental knowledge developed in this work is thought to be useful not only for the understanding of metal cutting processes but also, by analogy, to similar problems where convective flow is also interfering with

Developing technology for large-scale production of forest chips. Wood Energy Technology Programme 1999-2003. Interim report

International Nuclear Information System (INIS)

Hakkila, P.

2003-01-01

Finland is enhancing its use of renewable sources in energy production. From the 1995 level, the use of renewable energy is to be increased by 50 % by 2010, and 100 % by 2025. Wood-based fuels will play a leading role in this development. The main source of wood-based fuels is processing residues from the forest industries. However, as all processing residues are already in use, an increase is possible only as far as the capacity and wood consumption of the forest industries grow. Energy policy affects the production and availability of processing residues only indirectly. Another large source of wood-based energy is forest fuels, consisting of traditional firewood and chips comminuted from low-quality biomass. It is estimated that the reserve of technically harvest-able forest biomass is 10-16 Mm' annually, when no specific cost limit is applied. This corresponds to 2-3 Mtoe or 6-9 % of the present consumption of primary energy in Finland. How much of this re-serve it will actually be possible to harvest and utilize depends on the cost competitiveness of forest chips against alternative sources of energy. A goal of Finnish energy and climate strategies is to use 5 Mm' forest chips annually by 2010. The use of wood fuels is being promoted by means of taxation, investment aid and support for chip production from young forests. Furthermore, research and development is being supported in order to create techno-economic conditions for the competitive production of forest chips. In 1999, the National Technology Agency Tekes established the five-year Wood Energy Technology Programme to stimulate the development of efficient systems for the large-scale production of forest chips. Key tar-gets are competitive costs, reliable supply and good quality chips. The two guiding principles of the programme are: (1) close cooperation between researchers and practitioners and (2) to apply research and development to the practical applications and commercialization. As of November

Wafer-level vacuum/hermetic packaging technologies for MEMS

Science.gov (United States)

Lee, Sang-Hyun; Mitchell, Jay; Welch, Warren; Lee, Sangwoo; Najafi, Khalil

2010-02-01

An overview of wafer-level packaging technologies developed at the University of Michigan is presented. Two sets of packaging technologies are discussed: (i) a low temperature wafer-level packaging processes for vacuum/hermeticity sealing, and (ii) an environmentally resistant packaging (ERP) technology for thermal and mechanical control as well as vacuum packaging. The low temperature wafer-level encapsulation processes are implemented using solder bond rings which are first patterned on a cap wafer and then mated with a device wafer in order to encircle and encapsulate the device at temperatures ranging from 200 to 390 °C. Vacuum levels below 10 mTorr were achieved with yields in an optimized process of better than 90%. Pressures were monitored for more than 4 years yielding important information on reliability and process control. The ERP adopts an environment isolation platform in the packaging substrate. The isolation platform is designed to provide low power oven-control, vibration isolation and shock protection. It involves batch flip-chip assembly of a MEMS device onto the isolation platform wafer. The MEMS device and isolation structure are encapsulated at the wafer-level by another substrate with vertical feedthroughs for vacuum/hermetic sealing and electrical signal connections. This technology was developed for high performance gyroscopes, but can be applied to any type of MEMS device.

On-chip dual-comb source for spectroscopy.

Science.gov (United States)

Dutt, Avik; Joshi, Chaitanya; Ji, Xingchen; Cardenas, Jaime; Okawachi, Yoshitomo; Luke, Kevin; Gaeta, Alexander L; Lipson, Michal

2018-03-01

Dual-comb spectroscopy is a powerful technique for real-time, broadband optical sampling of molecular spectra, which requires no moving components. Recent developments with microresonator-based platforms have enabled frequency combs at the chip scale. However, the need to precisely match the resonance wavelengths of distinct high quality-factor microcavities has hindered the development of on-chip dual combs. We report the simultaneous generation of two microresonator combs on the same chip from a single laser, drastically reducing experimental complexity. We demonstrate broadband optical spectra spanning 51 THz and low-noise operation of both combs by deterministically tuning into soliton mode-locked states using integrated microheaters, resulting in narrow (lasers or microwave oscillators. We demonstrate high signal-to-noise ratio absorption spectroscopy spanning 170 nm using the dual-comb source over a 20-μs acquisition time. Our device paves the way for compact and robust spectrometers at nanosecond time scales enabled by large beat-note spacings (>1 GHz).

Challenges in the Packaging of MEMS

Energy Technology Data Exchange (ETDEWEB)

Malshe, A.P.; Singh, S.B.; Eaton, W.P.; O' Neal, C.; Brown, W.D.; Miller, W.M.

1999-03-26

The packaging of Micro-Electro-Mechanical Systems (MEMS) is a field of great importance to anyone using or manufacturing sensors, consumer products, or military applications. Currently much work has been done in the design and fabrication of MEMS devices but insufficient research and few publications have been completed on the packaging of these devices. This is despite the fact that packaging is a very large percentage of the total cost of MEMS devices. The main difference between IC packaging and MEMS packaging is that MEMS packaging is almost always application specific and greatly affected by its environment and packaging techniques such as die handling, die attach processes, and lid sealing. Many of these aspects are directly related to the materials used in the packaging processes. MEMS devices that are functional in wafer form can be rendered inoperable after packaging. MEMS dies must be handled only from the chip sides so features on the top surface are not damaged. This eliminates most current die pick-and-place fixtures. Die attach materials are key to MEMS packaging. Using hard die attach solders can create high stresses in the MEMS devices, which can affect their operation greatly. Low-stress epoxies can be high-outgassing, which can also affect device performance. Also, a low modulus die attach can allow the die to move during ultrasonic wirebonding resulting to low wirebond strength. Another source of residual stress is the lid sealing process. Most MEMS based sensors and devices require a hermetically sealed package. This can be done by parallel seam welding the package lid, but at the cost of further induced stress on the die. Another issue of MEMS packaging is the media compatibility of the packaged device. MEMS unlike ICS often interface with their environment, which could be high pressure or corrosive. The main conclusion we can draw about MEMS packaging is that the package affects the performance and reliability of the MEMS devices. There is a

Design and Optimisation of Home Scale Greywater Recycling Package

Directory of Open Access Journals (Sweden)

a/l Arugam Kalaichelvan

2018-01-01

Full Text Available Water crisis is becoming one of the biggest challenges in some countries due to over population and drought. Therefore, government and non-government organisations in well-developed countries are encouraging industries to install water recycling package to reduce water usage and consume greywater instead. However the home scale is not yet available in the market. This research focuses on design a home scale greywater treatment system for toilet flushing within 3,000 to 5,000 USD as a collaboration with DD Techniche Sdn Bhd. Greywater is the waste water produced from laundry, kitchen and bathroom except the toilet waste and contains suspended solids, microorganisms, oil, nitrates and phosphorus which needs to be treated using suitable types of treatment for safe reuse. The treatments include physical, chemical and biological water treatment in which in this study the proposed system is a combination of all three. The design is evaluated using experimental methods to meet the standard of toilet flushing quality. The greywater system consists of the mechanical parts to control the flow of greywater and store the treated water including pumps, sand filtration tank, wire mesh chassis and collection tank. The final design has dimension of 6 m3 and optimised price within the budget.

Implementation of Guaranteed Services in the MANGO Clockless Network-on-Chip

DEFF Research Database (Denmark)

Bjerregaard, Tobias; Sparsø, Jens

2006-01-01

(clockless implementation, standard socket access points, and guaranteed communication services) make MANGO suitable for a modular SoC design flow is explained. Among the advantages of using clockless circuit techniques are inherent global timing closure, low forward latency in pipelines, and zero dynamic......Shared, segmented, on-chip interconnection networks, known as networks-on-chip (NoC), may become the preferred way of interconnecting intellectual property (IP) cores in future giga-scale system-on-chip (SoC) designs. A NoC can provide the required communication bandwidth while accommodating...... the effects of scaling microchip technologies. Equally important, a NoC facilitates a truly modular and scalable design flow. The MANGO (message-passing asynchronous network-on-chip providing guaranteed services over open core protocol (OCP) interfaces) NoC is presented, and how its key characteristics...

Epoxy Chip-in-Carrier Integration and Screen-Printed Metalization for Multichannel Microfluidic Lab-on-CMOS Microsystems.

Science.gov (United States)

Li, Lin; Yin, Heyu; Mason, Andrew J

2018-04-01

The integration of biosensors, microfluidics, and CMOS instrumentation provides a compact lab-on-CMOS microsystem well suited for high throughput measurement. This paper describes a new epoxy chip-in-carrier integration process and two planar metalization techniques for lab-on-CMOS that enable on-CMOS electrochemical measurement with multichannel microfluidics. Several design approaches with different fabrication steps and materials were experimentally analyzed to identify an ideal process that can achieve desired capability with high yield and low material and tool cost. On-chip electrochemical measurements of the integrated assembly were performed to verify the functionality of the chip-in-carrier packaging and its capability for microfluidic integration. The newly developed CMOS-compatible epoxy chip-in-carrier process paves the way for full implementation of many lab-on-CMOS applications with CMOS ICs as core electronic instruments.

Submission of the First Full Scale Prototype Chip for Upgraded ATLAS Pixel Detector at LHC, FE-I4A

CERN Document Server

Barbero, M; The ATLAS collaboration; Beccherle, R; Darbo, G; Dube, S; Elledge, D; Fleury, J; Fougeron, D; Garcia-Sciveres, M; Gensolen, F; Gnani, D; Gromov, V; Jensen, F; Hemperek, T; Karagounis, M; Kluit, R; Kruth, A; Mekkaoui, A; Menouni, M; Schipper, JD; Wermes, N; Zivkovic, V

2010-01-01

A new ATLAS pixel chip FE-I4 is being developed for use in upgraded LHC luminosity environments, including the near-term Insertable B-Layer (IBL) upgrade. FE-I4 is designed in a 130nm CMOS technology, presenting advantages in terms of radiation tolerance and digital logic density compared to the 250nm CMOS technology used for the current ATLAS pixel IC, FE-I3. The FE-I4 architecture is based on an array of 80x336 pixels, each 50x250um^2, consisting of analog and digital sections. In the summer 2010, a first full scale prototype FE-I4A was submitted for an engineering run. This IC features the full scale pixel array as well as the complex periphery of the future full-size FE-I4. The FE-I4A contains also various extra test features which should prove very useful for the chip characterization, but deviate from the needs for standard operation of the final FE-I4 for IBL. In this paper, focus will be brought to the various features implemented in the FE-I4A submission, while also underlining the main differences b...

Large-scale analysis of antisense transcription in wheat using the Affymetrix GeneChip Wheat Genome Array

Directory of Open Access Journals (Sweden)

Settles Matthew L

2009-05-01

Full Text Available Abstract Background Natural antisense transcripts (NATs are transcripts of the opposite DNA strand to the sense-strand either at the same locus (cis-encoded or a different locus (trans-encoded. They can affect gene expression at multiple stages including transcription, RNA processing and transport, and translation. NATs give rise to sense-antisense transcript pairs and the number of these identified has escalated greatly with the availability of DNA sequencing resources and public databases. Traditionally, NATs were identified by the alignment of full-length cDNAs or expressed sequence tags to genome sequences, but an alternative method for large-scale detection of sense-antisense transcript pairs involves the use of microarrays. In this study we developed a novel protocol to assay sense- and antisense-strand transcription on the 55 K Affymetrix GeneChip Wheat Genome Array, which is a 3' in vitro transcription (3'IVT expression array. We selected five different tissue types for assay to enable maximum discovery, and used the 'Chinese Spring' wheat genotype because most of the wheat GeneChip probe sequences were based on its genomic sequence. This study is the first report of using a 3'IVT expression array to discover the expression of natural sense-antisense transcript pairs, and may be considered as proof-of-concept. Results By using alternative target preparation schemes, both the sense- and antisense-strand derived transcripts were labeled and hybridized to the Wheat GeneChip. Quality assurance verified that successful hybridization did occur in the antisense-strand assay. A stringent threshold for positive hybridization was applied, which resulted in the identification of 110 sense-antisense transcript pairs, as well as 80 potentially antisense-specific transcripts. Strand-specific RT-PCR validated the microarray observations, and showed that antisense transcription is likely to be tissue specific. For the annotated sense

A low-frequency chip-scale optomechanical oscillator with 58 kHz mechanical stiffening and more than 100th-order stable harmonics.

Science.gov (United States)

Huang, Yongjun; Flores, Jaime Gonzalo Flor; Cai, Ziqiang; Yu, Mingbin; Kwong, Dim-Lee; Wen, Guangjun; Churchill, Layne; Wong, Chee Wei

2017-06-29

For the sensitive high-resolution force- and field-sensing applications, the large-mass microelectromechanical system (MEMS) and optomechanical cavity have been proposed to realize the sub-aN/Hz 1/2 resolution levels. In view of the optomechanical cavity-based force- and field-sensors, the optomechanical coupling is the key parameter for achieving high sensitivity and resolution. Here we demonstrate a chip-scale optomechanical cavity with large mass which operates at ≈77.7 kHz fundamental mode and intrinsically exhibiting large optomechanical coupling of 44 GHz/nm or more, for both optical resonance modes. The mechanical stiffening range of ≈58 kHz and a more than 100 th -order harmonics are obtained, with which the free-running frequency instability is lower than 10 -6 at 100 ms integration time. Such results can be applied to further improve the sensing performance of the optomechanical inspired chip-scale sensors.

On-chip dual comb source for spectroscopy

OpenAIRE

Dutt, Avik; Joshi, Chaitanya; Ji, Xingchen; Cardenas, Jaime; Okawachi, Yoshitomo; Luke, Kevin; Gaeta, Alexander L.; Lipson, Michal

2016-01-01

Dual-comb spectroscopy is a powerful technique for real-time, broadband optical sampling of molecular spectra which requires no moving components. Recent developments with microresonator-based platforms have enabled frequency combs at the chip scale. However, the need to precisely match the resonance wavelengths of distinct high-quality-factor microcavities has hindered the development of an on-chip dual comb source. Here, we report the first simultaneous generation of two microresonator comb...

Study on boiling heat transfer from diode elements in an integrated circuit chip

Energy Technology Data Exchange (ETDEWEB)

Hijikata, Kunio; Nagasaki, Takao; Kurata, Naoki (Tokyo Institute of Technology Faculty of Engineering (Japan))

1989-02-25

By temperature measurement of elements in boiling experiments with diodes in an integrated circuit (IC) chip, characteristics of boiling heat transfer from tiny heat generating elements in an IC chip and thermal transfer characteristics of multiple heating elements adjoining positioned were studied. The Package of an IC was removed by acid to expose the IC chip. Electricity is applied to the diode in the IC to study the heat transfer properties. The heat transfer rate from a tiny heating element on an IC is greater than that from the conventional continual heated surface. In the case of heat generation by two adjoining elements, the relationship between the total amount of heat and the temperature of elements shows the same characteristics as in the case with a single element. The boiling heat transfer properties of an element in an IC chip are influenced by such microstructure surrounding the element as the pattern of wiring. Heat transfer increases with the decreasing size of the heating element by the heat transfer to the substrate beneath the element. 10 refs., 15 figs.

Analytical thermal modelling of multilayered active embedded chips into high density electronic board

Directory of Open Access Journals (Sweden)

Monier-Vinard Eric

2013-01-01

Full Text Available The recent Printed Wiring Board embedding technology is an attractive packaging alternative that allows a very high degree of miniaturization by stacking multiple layers of embedded chips. This disruptive technology will further increase the thermal management challenges by concentrating heat dissipation at the heart of the organic substrate structure. In order to allow the electronic designer to early analyze the limits of the power dissipation, depending on the embedded chip location inside the board, as well as the thermal interactions with other buried chips or surface mounted electronic components, an analytical thermal modelling approach was established. The presented work describes the comparison of the analytical model results with the numerical models of various embedded chips configurations. The thermal behaviour predictions of the analytical model, found to be within ±10% of relative error, demonstrate its relevance for modelling high density electronic board. Besides the approach promotes a practical solution to study the potential gain to conduct a part of heat flow from the components towards a set of localized cooled board pads.

Lab-on-a-Chip Pathogen Sensors for Food Safety

Directory of Open Access Journals (Sweden)

Bumsang Kim

2012-08-01

Full Text Available There have been a number of cases of foodborne illness among humans that are caused by pathogens such as Escherichia coli O157:H7, Salmonella typhimurium, etc. The current practices to detect such pathogenic agents are cell culturing, immunoassays, or polymerase chain reactions (PCRs. These methods are essentially laboratory-based methods that are not at all real-time and thus unavailable for early-monitoring of such pathogens. They are also very difficult to implement in the field. Lab-on-a-chip biosensors, however, have a strong potential to be used in the field since they can be miniaturized and automated; they are also potentially fast and very sensitive. These lab-on-a-chip biosensors can detect pathogens in farms, packaging/processing facilities, delivery/distribution systems, and at the consumer level. There are still several issues to be resolved before applying these lab-on-a-chip sensors to field applications, including the pre-treatment of a sample, proper storage of reagents, full integration into a battery-powered system, and demonstration of very high sensitivity, which are addressed in this review article. Several different types of lab-on-a-chip biosensors, including immunoassay- and PCR-based, have been developed and tested for detecting foodborne pathogens. Their assay performance, including detection limit and assay time, are also summarized. Finally, the use of optical fibers or optical waveguide is discussed as a means to improve the portability and sensitivity of lab-on-a-chip pathogen sensors.

Light emitting diode package element with internal meniscus for bubble free lens placement

Science.gov (United States)

Tarsa, Eric; Yuan, Thomas C.; Becerra, Maryanne; Yadev, Praveen

2010-09-28

A method for fabricating a light emitting diode (LED) package comprising providing an LED chip and covering at least part of the LED chip with a liquid encapsulant having a radius of curvature. An optical element is provided having a bottom surface with at least a portion having a radius of curvature larger than the liquid encapsulant. The larger radius of curvature portion of the optical element is brought into contact with the liquid encapsulant. The optical element is then moved closer to the LED chip, growing the contact area between said optical element and said liquid encapsulant. The liquid encapsulant is then cured. A light emitting diode comprising a substrate with an LED chip mounted to it. A meniscus ring is on the substrate around the LED chip with the meniscus ring having a meniscus holding feature. An inner encapsulant is provided over the LED chip with the inner encapsulant having a contacting surface on the substrate, with the meniscus holding feature which defines the edge of the contacting surface. An optical element is included having a bottom surface with at least a portion that is concave. The optical element is arranged on the substrate with the concave portion over the LED chip. A contacting encapsulant is included between the inner encapsulant and optical element.

Multiple plasmonically induced transparency for chip-scale bandpass filters in metallic nanowaveguides

Science.gov (United States)

Lu, Hua; Yue, Zengqi; Zhao, Jianlin

2018-05-01

We propose and investigate a new kind of bandpass filters based on the plasmonically induced transparency (PIT) effect in a special metal-insulator-metal (MIM) waveguide system. The finite element method (FEM) simulations illustrate that the obvious PIT response can be generated in the metallic nanostructure with the stub and coupled cavities. The lineshape and position of the PIT peak are particularly dependent on the lengths of the stub and coupled cavities, the waveguide width, as well as the coupling distance between the stub and coupled cavities. The numerical simulations are in accordance with the results obtained by the temporal coupled-mode theory. The multi-peak PIT effect can be achieved by integrating multiple coupled cavities into the plasmonic waveguide. This PIT response contributes to the flexible realization of chip-scale multi-channel bandpass filters, which could find crucial applications in highly integrated optical circuits for signal processing.

Laser-assisted ultrathin bare die packaging: a route to a new class of microelectronic devices

Science.gov (United States)

Marinov, Val R.; Swenson, Orven; Atanasov, Yuriy; Schneck, Nathan

2013-03-01

Ultrathin flip-chip semiconductor die packaging on paper substrates is an enabling technology for a variety of extremely low-cost electronic devices with huge market potential such as RFID smart forms, smart labels, smart tickets, banknotes, security documents, etc. Highly flexible and imperceptible dice are possible only at a thickness of less than 50 μm, preferably down to 10-20 μm or less. Several cents per die cost is achievable only if the die size is size and thickness. LEAP-packaged RFID-enabled paper for financial and security applications is also demonstrated. The cost of packaging using LEAP is lower compared to the conventional pick-and-place methods while the rate of packaging is much higher and independent of the die size.

On-chip photonic particle sensor

Science.gov (United States)

Singh, Robin; Ma, Danhao; Agarwal, Anu; Anthony, Brian

2018-02-01

We propose an on-chip photonic particle sensor design that can perform particle sizing and counting for various environmental applications. The sensor is based on micro photonic ring resonators that are able to detect the presence of the free space particles through the interaction with their evanescent electric field tail. The sensor can characterize a wide range of the particle size ranging from a few nano meters to micron ( 1 micron). The photonic platform offers high sensitivity, compactness, fast response of the device. Further, FDTD simulations are performed to analyze different particle-light interactions. Such a compact and portable platform, packaged with integrated photonic circuit provides a useful sensing modality in space shuttle and environmental applications.

Effecting aging time of epoxy molding compound to molding process for integrated circuit packaging

Science.gov (United States)

Tachapitunsuk, Jirayu; Ugsornrat, Kessararat; Srisuwitthanon, Warayoot; Thonglor, Panakamon

2017-09-01

This research studied about effecting aging time of epoxy molding compound (EMC) that effect to reliability performance of integrated circuit (IC) package in molding process. Molding process is so important of IC packaging process for protecting IC chip (or die) from temperature and humidity environment using encapsulated EMC. For general molding process, EMC are stored in the frozen at 5°C and left at room temperature at 25 °C for aging time on self before molding of die onto lead frame is 24 hours. The aging time effect to reliability performance of IC package due to different temperature and humidity inside the package. In experiment, aging time of EMC were varied from 0 to 24 hours for molding process of SOIC-8L packages. For analysis, these packages were tested by x-ray and scanning acoustic microscope to analyze properties of EMC with an aging time and also analyzed delamination, internal void, and wire sweep inside the packages with different aging time. The results revealed that different aging time of EMC effect to properties and reliability performance of molding process.

An SOI CMOS-Based Multi-Sensor MEMS Chip for Fluidic Applications.

Science.gov (United States)

Mansoor, Mohtashim; Haneef, Ibraheem; Akhtar, Suhail; Rafiq, Muhammad Aftab; De Luca, Andrea; Ali, Syed Zeeshan; Udrea, Florin

2016-11-04

An SOI CMOS multi-sensor MEMS chip, which can simultaneously measure temperature, pressure and flow rate, has been reported. The multi-sensor chip has been designed keeping in view the requirements of researchers interested in experimental fluid dynamics. The chip contains ten thermodiodes (temperature sensors), a piezoresistive-type pressure sensor and nine hot film-based flow rate sensors fabricated within the oxide layer of the SOI wafers. The silicon dioxide layers with embedded sensors are relieved from the substrate as membranes with the help of a single DRIE step after chip fabrication from a commercial CMOS foundry. Very dense sensor packing per unit area of the chip has been enabled by using technologies/processes like SOI, CMOS and DRIE. Independent apparatuses were used for the characterization of each sensor. With a drive current of 10 µA-0.1 µA, the thermodiodes exhibited sensitivities of 1.41 mV/°C-1.79 mV/°C in the range 20-300 °C. The sensitivity of the pressure sensor was 0.0686 mV/(V excit kPa) with a non-linearity of 0.25% between 0 and 69 kPa above ambient pressure. Packaged in a micro-channel, the flow rate sensor has a linearized sensitivity of 17.3 mV/(L/min) -0.1 in the tested range of 0-4.7 L/min. The multi-sensor chip can be used for simultaneous measurement of fluid pressure, temperature and flow rate in fluidic experiments and aerospace/automotive/biomedical/process industries.

APPLICATION OF NANOTECHNOLOGY IN FOOD PACKAGING

Directory of Open Access Journals (Sweden)

Renata Dobrucka

2014-04-01

Full Text Available Nanotechnology involves the design, production and use of structures through control of the size and shape of the materials at the nanometre scale. Also, nanomaterials have been already applied in many fields of human life. Nanocomposites have already led to several innovations with potential applications in the food packaging sector. The use of nanocomposite formulations is expected to considerably enhance the shelf-life of many types of food. This improvement can lead to lower weight packages because less material is needed to obtain the same or even better barrier properties. This, in turn, can lead to reduced package cost with less packaging waste. Antimicrobial packaging is another area with high potential for applying nanocomposite technology. Nanostructured antimicrobials have a higher surface area-to-volume ratio when compared with their higher scale counterparts. Therefore, antimicrobial nanocomposite packaging systems are supposed to be particularly efficient in their activities against microbial cells. In this review, definition of nanomaterials is presented. Besides, the paper shows examples of nanocomposities and antimicrobial nanopackaging mainly with the use of nanosilver. Moreover, nanoparticles such ZnO, TiO2, MgO and nanosensors in packaging were presented.

Polymer dispensing and embossing technology for the lens type LED packaging

Science.gov (United States)

Chien, Chien-Lin Chang; Huang, Yu-Che; Hu, Syue-Fong; Chang, Chung-Min; Yip, Ming-Chuen; Fang, Weileun

2013-06-01

This study presents a ring-type micro-structure design on the substrate and its corresponding micro fabrication processes for a lens-type light-emitting diode (LED) package. The dome-type or crater-type silicone lenses are achieved by a dispensing and embossing process rather than a molding process. Silicone with a high viscosity and thixotropy index is used as the encapsulant material. The ring-type micro structure is adopted to confine the dispensed silicone encapsulant so as to form the packaged lens. With the architecture and process described, this LED package technology herein has three merits: (1) the flexibility of lens-type LED package designs is enhanced; (2) a dome-type package design is used to enhance the intensity; (3) a crater-type package design is used to enhance the view angle. Measurement results show the ratio between the lens height and lens radius can vary from 0.4 to 1 by changing the volume of dispensed silicone. The view angles of dome-type and crater-type packages can reach 155° ± 5° and 175° ± 5°, respectively. As compared with the commercial plastic leaded chip carrier-type package, the luminous flux of a monochromatic blue light LED is improved by 15% by the dome-type package (improved by 7% by the crater-type package) and the luminous flux of a white light LED is improved by 25% by the dome-type package (improved by 13% by the crater-type package). The luminous flux of monochromatic blue light LED and white light LED are respectively improved by 8% and 12% by the dome-type package as compare with the crater-type package.

Tunable on chip optofluidic laser

DEFF Research Database (Denmark)

Bakal, Avraham; Vannahme, Christoph; Kristensen, Anders

2015-01-01

A chip scale tunable laser in the visible spectral band is realized by generating a periodic droplet array inside a microfluidic channel. Combined with a gain medium within the droplets, the periodic structure provides the optical feedback of the laser. By controlling the pressure applied to two...

Silicon Chip-to-Chip Mode-Division Multiplexing

DEFF Research Database (Denmark)

Baumann, Jan Markus; Porto da Silva, Edson; Ding, Yunhong

2018-01-01

A chip-to-chip mode-division multiplexing connection is demonstrated using a pair of multiplexers/demultiplexers fabricated on the silicon-on-insulator platform. Successful mode multiplexing and demultiplexing is experimentally demonstrated, using the LP01, LP11a and LP11b modes.......A chip-to-chip mode-division multiplexing connection is demonstrated using a pair of multiplexers/demultiplexers fabricated on the silicon-on-insulator platform. Successful mode multiplexing and demultiplexing is experimentally demonstrated, using the LP01, LP11a and LP11b modes....

Inherent polarization entanglement generated from a monolithic semiconductor chip

DEFF Research Database (Denmark)

Horn, Rolf T.; Kolenderski, Piotr; Kang, Dongpeng

2013-01-01

Creating miniature chip scale implementations of optical quantum information protocols is a dream for many in the quantum optics community. This is largely because of the promise of stability and scalability. Here we present a monolithically integratable chip architecture upon which is built...... a photonic device primitive called a Bragg reflection waveguide (BRW). Implemented in gallium arsenide, we show that, via the process of spontaneous parametric down conversion, the BRW is capable of directly producing polarization entangled photons without additional path difference compensation, spectral...... as a serious contender on which to build large scale implementations of optical quantum processing devices....

Error Control for Network-on-Chip Links

CERN Document Server

Fu, Bo

2012-01-01

As technology scales into nanoscale regime, it is impossible to guarantee the perfect hardware design. Moreover, if the requirement of 100% correctness in hardware can be relaxed, the cost of manufacturing, verification, and testing will be significantly reduced. Many approaches have been proposed to address the reliability problem of on-chip communications. This book focuses on the use of error control codes (ECCs) to improve on-chip interconnect reliability. Coverage includes detailed description of key issues in NOC error control faced by circuit and system designers, as well as practical error control techniques to minimize the impact of these errors on system performance. Provides a detailed background on the state of error control methods for on-chip interconnects; Describes the use of more complex concatenated codes such as Hamming Product Codes with Type-II HARQ, while emphasizing integration techniques for on-chip interconnect links; Examines energy-efficient techniques for integrating multiple error...

Packaging of structural health monitoring components

Science.gov (United States)

Kessler, Seth S.; Spearing, S. Mark; Shi, Yong; Dunn, Christopher T.

2004-07-01

Structural Health Monitoring (SHM) technologies have the potential to realize economic benefits in a broad range of commercial and defense markets. Previous research conducted by Metis Design and MIT has demonstrated the ability of Lamb waves methods to provide reliable information regarding the presence, location and type of damage in composite specimens. The present NSF funded program was aimed to study manufacturing, packaging and interface concepts for critical SHM components. The intention is to be able to cheaply manufacture robust actuating/sensing devices, and isolate them from harsh operating environments including natural, mechanical, or electrical extremes. Currently the issues related to SHM system durability have remained undressed. During the course of this research several sets of test devices were fabricated and packaged to protect the piezoelectric component assemblies for robust operation. These assemblies were then tested in hot and wet conditions, as well as in electrically noisy environments. Future work will aim to package the other supporting components such as the battery and wireless chip, as well as integrating all of these components together for operation. SHM technology will enable the reduction or complete elimination of scheduled inspections, and will allow condition-based maintenance for increased reliability and reduced overall life-cycle costs.

Ultrahigh-speed hybrid laser for silicon photonic integrated chips

DEFF Research Database (Denmark)

Chung, Il-Sug; Park, Gyeong Cheol; Ran, Qijiang

2013-01-01

Increasing power consumption for electrical interconnects between and inside chips is posing a real challenge to continue the performance scaling of processors/computers as predicted by D. Moore. In recent processors, energy consumption for electrical interconnects is half of power supplied...... and will be 80% in near future. This challenge strongly has motivated replacing electrical interconnects with optical ones even in chip level communications [1]. This chip-level optical interconnects need quite different performance of optoelectronic devices than required for conventional optical communications....... For a light source, the energy consumption per sending a bit is required to be

Demonstration of a Packaged Capacitive Pressure Sensor System Suitable for Jet Turbofan Engine Health Monitoring

Science.gov (United States)

Scardelletti, Maximilian C.; Jordan, Jennifer L.; Meredith, Roger D.; Harsh, Kevin; Pilant, Evan; Usrey, Michael W.; Beheim, Glenn M.; Hunter, Gary W.; Zorman, Christian A.

2016-01-01

In this paper, the development and characterization of a packaged pressure sensor system suitable for jet engine health monitoring is demonstrated. The sensing system operates from 97 to 117 MHz over a pressure range from 0 to 350 psi and a temperature range from 25 to 500 deg. The sensing system consists of a Clapp-type oscillator that is fabricated on an alumina substrate and is comprised of a Cree SiC MESFET, MIM capacitors, a wire-wound inductor, chip resistors and a SiCN capacitive pressure sensor. The pressure sensor is located in the LC tank circuit of the oscillator so that a change in pressure causes a change in capacitance, thus changing the resonant frequency of the sensing system. The chip resistors, wire-wound inductors and MIM capacitors have all been characterized at temperature and operational frequency, and perform with less than 5% variance in electrical performance. The measured capacitive pressure sensing system agrees very well with simulated results. The packaged pressure sensing system is specifically designed to measure the pressure on a jet turbofan engine. The packaged system can be installed by way of borescope plug adaptor fitted to a borescope port exposed to the gas path of a turbofan engine.

Design, realization and test of a rad-hard 2D-compressor and packing chip for high energy physics experiments

International Nuclear Information System (INIS)

Antinori, Samuele; Falchieri, Davide; Gabrielli, Alessandro; Gandolfi, Enzo

2004-01-01

CARLOSv3 is a third version of a chip that plays a significant role in the data acquisition chain of the A Large Ion Collider Experiment Inner Tracking System experiment. It has been designed and realized with a 0.25 μm CMOS 3-metal rad-hard digital library. The chip elaborates and compresses, by means of a bi-dimensional compressor, data belonging to a so-called event. The compressor looks for cross-shaped clusters within the whole data set coming from the silicon detector. To test the chip a specific PCB has been designed; it contains the connectors for probing the ASIC with a pattern generator and a logic state analyzer. The chip is inserted on the PCB using a ZIF socket. This allows to test the 35 packaged samples out of the total amount of bare chips we have from the foundry. The test phase has shown that 32 out of 35 chips under test work well. It is planned to redesign a new version of the chip by adding extra features and to submit the final version of CARLOS upon the final DAQ chain will be totally tested both in Bologna and at CERN

An SOI CMOS-Based Multi-Sensor MEMS Chip for Fluidic Applications †

Science.gov (United States)

Mansoor, Mohtashim; Haneef, Ibraheem; Akhtar, Suhail; Rafiq, Muhammad Aftab; De Luca, Andrea; Ali, Syed Zeeshan; Udrea, Florin

2016-01-01

An SOI CMOS multi-sensor MEMS chip, which can simultaneously measure temperature, pressure and flow rate, has been reported. The multi-sensor chip has been designed keeping in view the requirements of researchers interested in experimental fluid dynamics. The chip contains ten thermodiodes (temperature sensors), a piezoresistive-type pressure sensor and nine hot film-based flow rate sensors fabricated within the oxide layer of the SOI wafers. The silicon dioxide layers with embedded sensors are relieved from the substrate as membranes with the help of a single DRIE step after chip fabrication from a commercial CMOS foundry. Very dense sensor packing per unit area of the chip has been enabled by using technologies/processes like SOI, CMOS and DRIE. Independent apparatuses were used for the characterization of each sensor. With a drive current of 10 µA–0.1 µA, the thermodiodes exhibited sensitivities of 1.41 mV/°C–1.79 mV/°C in the range 20–300 °C. The sensitivity of the pressure sensor was 0.0686 mV/(Vexcit kPa) with a non-linearity of 0.25% between 0 and 69 kPa above ambient pressure. Packaged in a micro-channel, the flow rate sensor has a linearized sensitivity of 17.3 mV/(L/min)−0.1 in the tested range of 0–4.7 L/min. The multi-sensor chip can be used for simultaneous measurement of fluid pressure, temperature and flow rate in fluidic experiments and aerospace/automotive/biomedical/process industries. PMID:27827904

A novel conceptual design of parallel nitrogen expansion liquefaction process for small-scale LNG (liquefied natural gas) plant in skid-mount packages

International Nuclear Information System (INIS)

He, Tianbiao; Ju, Yonglin

2014-01-01

The utilization of unconventional natural gas is still a great challenge for China due to its distribution locations and small reserves. Thus, liquefying the unconventional natural gas by using small-scale LNG plant in skid-mount packages is a good choice with great economic benefits. A novel conceptual design of parallel nitrogen expansion liquefaction process for small-scale plant in skid-mount packages has been proposed. It first designs a process configuration. Then, thermodynamic analysis of the process is conducted. Next, an optimization model with genetic algorithm method is developed to optimize the process. Finally, the flexibilities of the process are tested by two different feed gases. In conclusion, the proposed parallel nitrogen expansion liquefaction process can be used in small-scale LNG plant in skid-mount packages with high exergy efficiency and great economic benefits. - Highlights: • A novel design of parallel nitrogen expansion liquefaction process is proposed. • Genetic algorithm is applied to optimize the novel process. • The unit energy consumption of optimized process is 0.5163 kWh/Nm 3 . • The exergy efficiency of the optimized case is 0.3683. • The novel process has a good flexibility for different feed gas conditions

Radiation-Resistant Photon-Counting Detector Package Providing Sub-ps Stability for Laser Time Transfer in Space

Science.gov (United States)

Prochzaka, Ivan; Kodat, Jan; Blazej, Josef; Sun, Xiaoli (Editor)

2015-01-01

We are reporting on a design, construction and performance of photon-counting detector packages based on silicon avalanche photodiodes. These photon-counting devices have been optimized for extremely high stability of their detection delay. The detectors have been designed for future applications in fundamental metrology and optical time transfer in space. The detectors have been qualified for operation in space missions. The exceptional radiation tolerance of the detection chip itself and of all critical components of a detector package has been verified in a series of experiments.

CORRELATIONS BETWEEN HOMOLOGUE CONCENTRATIONS OF PCDD/FS AND TOXIC EQUIVALENCY VALUES IN LABORATORY-, PACKAGE BOILER-, AND FIELD-SCALE INCINERATORS

Science.gov (United States)

The toxic equivalency (TEQ) values of polychlorinated dibenzo-p-dioxins and polychlorinated dibenzofurans (PCDD/Fs) are predicted with a model based on the homologue concentrations measured from a laboratory-scale reactor (124 data points), a package boiler (61 data points), and ...

Flip chip assembly of thinned chips for hybrid pixel detector applications

International Nuclear Information System (INIS)

Fritzsch, T; Zoschke, K; Rothermund, M; Oppermann, H; Woehrmann, M; Ehrmann, O; Lang, K D; Huegging, F

2014-01-01

There is a steady trend to ultra-thin microelectronic devices. Especially for future particle detector systems a reduced readout chip thickness is required to limit the loss of tracking precision due to scattering. The reduction of silicon thickness is performed at wafer level in a two-step thinning process. To minimize the risk of wafer breakage the thinned wafer needs to be handled by a carrier during the whole process chain of wafer bumping. Another key process is the flip chip assembly of thinned readout chips onto thin sensor tiles. Besides the prevention of silicon breakage the minimization of chip warpage is one additional task for a high yield and reliable flip chip process. A new technology using glass carrier wafer will be described in detail. The main advantage of this technology is the combination of a carrier support during wafer processing and the chip support during flip chip assembly. For that a glass wafer is glue-bonded onto the backside of the thinned readout chip wafer. After the bump deposition process the glass-readout chip stack is diced in one step. Finally the glass carrier chip is released by laser illumination after flip chip assembly of the readout chip onto sensor tile. The results of the flip chip assembly process development for the ATLAS IBL upgrade are described more in detail. The new ATLAS FEI4B chip with a size of 20 × 19 mm 2 is flip chip bonded with a thickness of only 150 μm, but the capability of this technology has been demonstrated on hybrid modules with a reduced readout chip thickness of down to 50 μm which is a major step for ultra-thin electronic systems

Washing scaling of GeneChip microarray expression

Directory of Open Access Journals (Sweden)

Krohn Knut

2010-05-01

Full Text Available Abstract Background Post-hybridization washing is an essential part of microarray experiments. Both the quality of the experimental washing protocol and adequate consideration of washing in intensity calibration ultimately affect the quality of the expression estimates extracted from the microarray intensities. Results We conducted experiments on GeneChip microarrays with altered protocols for washing, scanning and staining to study the probe-level intensity changes as a function of the number of washing cycles. For calibration and analysis of the intensity data we make use of the 'hook' method which allows intensity contributions due to non-specific and specific hybridization of perfect match (PM and mismatch (MM probes to be disentangled in a sequence specific manner. On average, washing according to the standard protocol removes about 90% of the non-specific background and about 30-50% and less than 10% of the specific targets from the MM and PM, respectively. Analysis of the washing kinetics shows that the signal-to-noise ratio doubles roughly every ten stringent washing cycles. Washing can be characterized by time-dependent rate constants which reflect the heterogeneous character of target binding to microarray probes. We propose an empirical washing function which estimates the survival of probe bound targets. It depends on the intensity contribution due to specific and non-specific hybridization per probe which can be estimated for each probe using existing methods. The washing function allows probe intensities to be calibrated for the effect of washing. On a relative scale, proper calibration for washing markedly increases expression measures, especially in the limit of small and large values. Conclusions Washing is among the factors which potentially distort expression measures. The proposed first-order correction method allows direct implementation in existing calibration algorithms for microarray data. We provide an experimental

Research Progress of Microfluidic Chips Preparation and its Optical Element

Directory of Open Access Journals (Sweden)

Feng WANG

2014-03-01

Full Text Available Microfluidic technology is the emerging technologies in researching fluid channel and related applications in the micro and nano-scale space. Microfluidic chip is a new miniaturized rapid analysis platform by microfluidic technology, it has many characteristics such as liquid flow control, minimal reagent consumption, rapid analysis, which is widely used in physics, chemistry, biology, and engineering science and other fields, it has strong interdisciplinary. This paper mainly discusses research progress of materials used for microfluidic chips and the devices based on microfluidic technology, including microfluidic chip, microfluidic optical devices, microfluidic laser preparation, microfluidic chip applications, focusing on the quasi-molecular laser processing technology and femtosecond laser processing technology in the microfluidic devices preparation, and make development prospects for it.

Hardware support for CSP on a Java chip multiprocessor

DEFF Research Database (Denmark)

Gruian, Flavius; Schoeberl, Martin

2013-01-01

Due to memory bandwidth limitations, chip multiprocessors (CMPs) adopting the convenient shared memory model for their main memory architecture scale poorly. On-chip core-to-core communication is a solution to this problem, that can lead to further performance increase for a number of multithreaded...... applications. Programmatically, the Communicating Sequential Processes (CSPs) paradigm provides a sound computational model for such an architecture with message based communication. In this paper we explore hardware support for CSP in the context of an embedded Java CMP. The hardware support for CSP are on......-chip communication channels, implemented by a ring-based network-on-chip (NoC), to reduce the memory bandwidth pressure on the shared memory.The presented solution is scalable and also specific for our limited resources and real-time predictability requirements. CMP architectures of three to eight processors were...

Exploring massive, genome scale datasets with the genometricorr package

KAUST Repository

Favorov, Alexander; Mularoni, Loris; Cope, Leslie M.; Medvedeva, Yulia; Mironov, Andrey A.; Makeev, Vsevolod J.; Wheelan, Sarah J.

2012-01-01

We have created a statistically grounded tool for determining the correlation of genomewide data with other datasets or known biological features, intended to guide biological exploration of high-dimensional datasets, rather than providing immediate answers. The software enables several biologically motivated approaches to these data and here we describe the rationale and implementation for each approach. Our models and statistics are implemented in an R package that efficiently calculates the spatial correlation between two sets of genomic intervals (data and/or annotated features), for use as a metric of functional interaction. The software handles any type of pointwise or interval data and instead of running analyses with predefined metrics, it computes the significance and direction of several types of spatial association; this is intended to suggest potentially relevant relationships between the datasets. Availability and implementation: The package, GenometriCorr, can be freely downloaded at http://genometricorr.sourceforge.net/. Installation guidelines and examples are available from the sourceforge repository. The package is pending submission to Bioconductor. © 2012 Favorov et al.

Exploring massive, genome scale datasets with the genometricorr package

KAUST Repository

Favorov, Alexander

2012-05-31

We have created a statistically grounded tool for determining the correlation of genomewide data with other datasets or known biological features, intended to guide biological exploration of high-dimensional datasets, rather than providing immediate answers. The software enables several biologically motivated approaches to these data and here we describe the rationale and implementation for each approach. Our models and statistics are implemented in an R package that efficiently calculates the spatial correlation between two sets of genomic intervals (data and/or annotated features), for use as a metric of functional interaction. The software handles any type of pointwise or interval data and instead of running analyses with predefined metrics, it computes the significance and direction of several types of spatial association; this is intended to suggest potentially relevant relationships between the datasets. Availability and implementation: The package, GenometriCorr, can be freely downloaded at http://genometricorr.sourceforge.net/. Installation guidelines and examples are available from the sourceforge repository. The package is pending submission to Bioconductor. © 2012 Favorov et al.

Broadband and scalable optical coupling for silicon photonics using polymer waveguides

Science.gov (United States)

La Porta, Antonio; Weiss, Jonas; Dangel, Roger; Jubin, Daniel; Meier, Norbert; Horst, Folkert; Offrein, Bert Jan

2018-04-01

We present optical coupling schemes for silicon integrated photonics circuits that account for the challenges in large-scale data processing systems such as those used for emerging big data workloads. Our waveguide based approach allows to optimally exploit the on-chip optical feature size, and chip- and package real-estate. It further scales well to high numbers of channels and is compatible with state-of-the-art flip-chip die packaging. We demonstrate silicon waveguide to polymer waveguide coupling losses below 1.5 dB for both the O- and C-bands with a polarisation dependent loss of <1 dB. Over 100 optical silicon waveguide to polymer waveguide interfaces were assembled within a single alignment step, resulting in a physical I/O channel density of up to 13 waveguides per millimetre along the chip-edge, with an average coupling loss of below 3.4 dB measured at 1310 nm.

Effect of on-chip filter on Coulomb blockade thermometer

International Nuclear Information System (INIS)

Roschier, L; Penttilä, J S; Gunnarsson, D; Prunnila, M; Meschke, M; Savin, A

2012-01-01

Coulomb Blockade Thermometer (CBT) is a primary thermometer based on electric conductance of normal tunnel junction arrays. One limitation for CBT use at the lowest temperatures has been due to environmental noise heating. To improve on this limitation, we have done measurements on CBT sensors fabricated with different on-chip filtering structures in a dilution refrigerator with a base temperature of 10 mK. The CBT sensors were produced with a wafer scale tunnel junction process. We present how the different on-chip filtering schemes affect the limiting saturation temperatures and show that CBT sensors with proper on-chip filtering work at temperatures below 20 mK and are tolerant to noisy environment.

Comprehensive Investigation on Current Imbalance among Parallel Chips inside MW-Scale IGBT Power Modules

DEFF Research Database (Denmark)

Wu, Rui; Smirnova, Liudmila; Wang, Huai

2015-01-01

With the demands for increasing the power rating and improving reliability level of the high power IGBT modules, there are further needs of understanding how to achieve stable paralleling and identical current sharing between the chips. This paper investigates the stray parameters imbalance among...... parallel chips inside the 1.7 kV/1 kA high power IGBT modules at different frequencies by Ansys Q3D parastics extractor. The resulted current imbalance is further confirmed by experimental measurement....

Packaging Aspects of Photodetector Modules for 100 Gbit/s Ethernet Applications

DEFF Research Database (Denmark)

Jiang, Chenhui; Mekonnen, G.G.; Krozer, Viktor

2008-01-01

Packaging is a major problem at millimetre-wave frequencies approaching 100 GHz. In this paper we present that insertion losses in a multi-chip module (MCM) can be less IL ...-backed coplanar waveguides (CBCPWs) with vias is accurately analyzed using 3D electromagnetic (EM) simulation over a wide frequency range. Patch antenna mode resonances are identified as a major origin of resonances in simulated and measured transmission characteristics of the CBCPW with vias. Based on EM...

Avaliação da aceitação de "chips" de mandioca Acceptance evaluation of cassava chips

Directory of Open Access Journals (Sweden)

Regina Kitagawa Grizotto

2003-12-01

Full Text Available Pré-tratamentos como o cozimento, a fermentação natural e a secagem parcial foram aplicados em raízes de mandioca, visando a obtenção de "chips" comestíveis. A avaliação sensorial foi feita com base na aceitação e aparência dos "chips" das variedades IAC Mantiqueira e IAC 576.70. Trinta consumidores potenciais do produto foram selecionados em função da disponibilidade e interesse em participar dos testes. Foi utilizada escala hedônica de 7 pontos, onde os provadores avaliaram as amostras delineadas em blocos casualizados. Os resultados obtidos mostraram que os "chips" controle e pré-cozidos foram aceitos sensorialmente, apresentado médias de 5,1 (gostei ligeiramente para IAC Mantiqueira e 6,0 (gostei moderadamente para IAC 576.70. Os "chips" pré-fermentados de ambas variedades foram rejeitados. Os termos de agrado mais comentados pelos provadores foram "sabor de mandioca", "crocância" e "textura". Os termos de desagrado mais citados incluem "textura dura", "falta sabor de mandioca" e "gosto de óleo". Os provadores consideraram adequada a aparência dos "chips" de ambas variedades, sendo ligeiramente preferida a aparência dos "chips" da IAC 576.70, com exceção dos "chips" cozidos por 8 minutos e os fermentados, rejeitados pelos consumidores. A cor amarela da polpa pode ter influenciado a aceitação da variedade IAC 576.70. A composição centesimal e o teor de fibras na mandioca in natura e, o teor de lipídeos em "chips" de mandioca, também foram apresentados.Pre-treatments such as cooking, natural fermentation and partial drying were applied to cassava roots, aimed at obtaining edible cassava chips. The sensory evaluation was based on the acceptance and appearance of the chips, using the varieties IAC Mantiqueira and IAC 576.70. Thirty potential consumers of the product were selected based on their availability and interest. A 7-point hedonic scale was used, all the judges evaluating all the samples using a randomised

Evaluation of Package Stress during Temperature Cycling using Metal Deformation Measurement and FEM Simulation

International Nuclear Information System (INIS)

Hoeglauer, J.; Bohm, C.; Otremba, R.; Maerz, J.; Nelle, P.; Stecher, M.; Alpern, P.

2006-01-01

Plastic encapsulated devices that are exposed to Temperature Cycling (TC) tests undergo an excessive mechanical stress due to different Coefficients of Thermal Expansion (CTE) of the various materials used in the system. Especially in the corners of the die, passivation cracks and shifted metal lines can be observed, which demonstrates an increasing mechanical stress from chip center to the corners of the die. This effect has been known for a long time. This paper presents a simple measurement technique to quantify the mechanical shear stress at the chip-Mold Compound (MC) interface by measuring the deformation of a periodical metal structure. Based on this deformation measurement, we evaluated the stress distribution within the package, and the influence of different parameters such as number of cycles and chip size. Furthermore, these experimental results were compared with FEM simulation, and showed good agreement but could not account in all cases for the total amount of observed shift

GMATA: An Integrated Software Package for Genome-Scale SSR Mining, Marker Development and Viewing.

Science.gov (United States)

Wang, Xuewen; Wang, Le

2016-01-01

Simple sequence repeats (SSRs), also referred to as microsatellites, are highly variable tandem DNAs that are widely used as genetic markers. The increasing availability of whole-genome and transcript sequences provides information resources for SSR marker development. However, efficient software is required to efficiently identify and display SSR information along with other gene features at a genome scale. We developed novel software package Genome-wide Microsatellite Analyzing Tool Package (GMATA) integrating SSR mining, statistical analysis and plotting, marker design, polymorphism screening and marker transferability, and enabled simultaneously display SSR markers with other genome features. GMATA applies novel strategies for SSR analysis and primer design in large genomes, which allows GMATA to perform faster calculation and provides more accurate results than existing tools. Our package is also capable of processing DNA sequences of any size on a standard computer. GMATA is user friendly, only requires mouse clicks or types inputs on the command line, and is executable in multiple computing platforms. We demonstrated the application of GMATA in plants genomes and reveal a novel distribution pattern of SSRs in 15 grass genomes. The most abundant motifs are dimer GA/TC, the A/T monomer and the GCG/CGC trimer, rather than the rich G/C content in DNA sequence. We also revealed that SSR count is a linear to the chromosome length in fully assembled grass genomes. GMATA represents a powerful application tool that facilitates genomic sequence analyses. GAMTA is freely available at http://sourceforge.net/projects/gmata/?source=navbar.

Small-Scale High Temperature Melter-1 (SSHTM-1) Data Package. Appendix B

Energy Technology Data Exchange (ETDEWEB)

NONE

1996-03-01

This appendix provides the data for Alternate HTM Flowsheet 2 (Glycolic Acid) melter feed preparation activities in both the laboratory- and small-scale testing. The first section provides an outline of this appendix. The melter feed preparation data are presented in the next two main sections, laboratory melter feed preparation data and small-scale melter feed preparation data. Section 3.0 provides the laboratory data which is discussed in the main body of the Small-Scale High Temperature-1 (SSHTM-1) Data Package, milestone C95-02.02Y. Section 3.1 gives the flowsheet in outline form as used in the laboratory-scale tests. This section also includes the ``Laboratory Melter Feed Preparation Activity Log`` which gives A chronological account of the test in terms of time, temperature, slurry pH, and specific observations about slurry appearance, acid addition rates, and samples taken. The ``Laboratory Melter Feed Preparation Activity Log`` provides a road map to the reader by which all the activity and data from the laboratory can be easily accessed. A summary of analytical data is presented next, section 3.2, which covers starting materials and progresses to the analysis of the melter feed. The next section, 3.3, characterizes the off-gas generation that occurs during the slurry processing. The following section, 3.4, provides the rheology data gathered including gram waste oxide loading information for the various slurries tested. The final section, 3.5, includes data from standard crucible redox testing. Section 4.0 provides the small-scale data in parallel form to section 3.0. Section 5.0 concludes with the references for this appendix.

Wood chips procurement and research project at the Mikkeli region

International Nuclear Information System (INIS)

Saksa, T.; Auvinen, P.

1996-01-01

In 1993-94, a large-scale energywood production chain started as a co-operation project by the Mikkeli city forest office and local forestry societies. In 1995 over 115 000 m 3 (about 85 000 MWh of energy) of wood chips were delivered to Pursiala heat and power plant in Mikkeli. About 75 % of these chips was forest processed chips. About 70 % of the forest processed chips was whole tree chips from improvement cuttings of young forest stands and the rest was logging waste chips from regeneration cutting areas. The average total delivery costs of forest processed chips after reduction of energywood and other subsidies were approximately 45 FIM/m 3 (60 FIM/MWh) for the whole tree chips and 38 FIM/m 3 (50 FIM/MWh) for logging waste chips. The delivery costs of forest processed chips could meet the target of Bioenergy Research Programme (45 FIM/MWh) only in the most favourable cases. In an average the delivery costs were about 9 FIM/MWh more than the price obtained when sold to the heat and power plant. However the wood chip production created 27 new jobs and the increase of income to the local economy was about 2.2 milj. FIM /year. The local communities got new tax revenue about 3 FIM/MWh. The gain for the forestry was approximated to be 5 - 6 FIM/MWh. The resources of forest processed chips were studied on the basis of stand measurements. According to the study the most remarkable energywood resources were in young thinning stands on Oxalis-Myrtillus and Myrtillus forest site types. On Oxalis-Myrtillus type almost every and on Myrtillus type every second stand included energywood more than 40 m 3 /ha

Nanoliter Centrifugal Liquid Dispenser Coupled with Superhydrophobic Microwell Array Chips for High-Throughput Cell Assays

Directory of Open Access Journals (Sweden)

Yuyi Wang

2018-06-01

Full Text Available Microfluidic systems have been regarded as a potential platform for high-throughput screening technology in drug discovery due to their low sample consumption, high integration, and easy operation. The handling of small-volume liquid is an essential operation in microfluidic systems, especially in investigating large-scale combination conditions. Here, we develop a nanoliter centrifugal liquid dispenser (NanoCLD coupled with superhydrophobic microwell array chips for high-throughput cell-based assays in the nanoliter scale. The NanoCLD consists of a plastic stock block with an array of drilled through holes, a reagent microwell array chip (reagent chip, and an alignment bottom assembled together in a fixture. A simple centrifugation at 800 rpm can dispense ~160 nL reagents into microwells in 5 min. The dispensed reagents are then delivered to cells by sandwiching the reagent chip upside down with another microwell array chip (cell chip on which cells are cultured. A gradient of doxorubicin is then dispensed to the cell chip using the NanoCLD for validating the feasibility of performing drug tests on our microchip platform. This novel nanoliter-volume liquid dispensing method is simple, easy to operate, and especially suitable for repeatedly dispensing many different reagents simultaneously to microwells.

Low-Power, Chip-Scale, Carbon Dioxide Gas Sensors for Spacesuit Monitoring

Science.gov (United States)

Rani, Asha; Shi, Chen; Thomson, Brian; Debnath, Ratan; Wen, Boamei; Motayed, Abhishek; Chullen, Cinda

2018-01-01

N5 Sensors, Inc. through a Small Business Technology Transfer (STTR) contract award has been developing ultra-small, low-power carbon dioxide (CO2) gas sensors, suited for monitoring CO2 levels inside NASA spacesuits. Due to the unique environmental conditions within the spacesuits, such as high humidity, large temperature swings, and operating pressure swings, measurement of key gases relevant to astronaut's safety and health such as(CO2), is quite challenging. Conventional non-dispersive infrared absorption based CO2 sensors present challenges inside the spacesuits due to size, weight, and power constraints, along with the ability to sense CO2 in a high humidity environment. Unique chip-scale, nanoengineered chemiresistive gas-sensing architecture has been developed for this application, which can be operated in a typical space-suite environmental conditions. Unique design combining the selective adsorption properties of the nanophotocatalytic clusters of metal-oxides and metals, provides selective detection of CO2 in high relative humidity conditions. All electronic design provides a compact and low-power solution, which can be implemented for multipoint detection of CO2 inside the spacesuits. This paper will describe the sensor architecture, development of new photocatalytic material for better sensor response, and advanced structure for better sensitivity and shorter response times.

Flip chip assembly of thinned chips for hybrid pixel detector applications

CERN Document Server

Fritzsch, T; Woehrmann, M; Rothermund, M; Huegging, F; Ehrmann, O; Oppermann, H; Lang, K.D

2014-01-01

There is a steady trend to ultra-thin microelectronic devices. Especially for future particle detector systems a reduced readout chip thickness is required to limit the loss of tracking precision due to scattering. The reduction of silicon thickness is performed at wafer level in a two-step thinning process. To minimize the risk of wafer breakage the thinned wafer needs to be handled by a carrier during the whole process chain of wafer bumping. Another key process is the flip chip assembly of thinned readout chips onto thin sensor tiles. Besides the prevention of silicon breakage the minimization of chip warpage is one additional task for a high yield and reliable flip chip process. A new technology using glass carrier wafer will be described in detail. The main advantage of this technology is the combination of a carrier support during wafer processing and the chip support during flip chip assembly. For that a glass wafer is glue-bonded onto the backside of the thinned readout chip wafer. After the bump depo...

Wirebond crosstalk and cavity modes in large chip mounts for superconducting qubits

Energy Technology Data Exchange (ETDEWEB)

Wenner, J; Neeley, M; Bialczak, Radoslaw C; Lenander, M; Lucero, Erik; O' Connell, A D; Sank, D; Wang, H; Weides, M; Cleland, A N; Martinis, John M, E-mail: martinis@physics.ucsb.edu [Department of Physics, University of California, Santa Barbara, CA 93106 (United States)

2011-06-15

We analyze the performance of a microwave chip mount that uses wirebonds to connect the chip and mount grounds. A simple impedance ladder model predicts that transmission crosstalk between two feedlines falls off exponentially with distance at low frequencies, but rises to near unity above a resonance frequency set by the chip to ground capacitance. Using SPICE simulations and experimental measurements of a scale model, the basic predictions of the ladder model were verified. In particular, by decreasing the capacitance between the chip and box grounds, the resonance frequency increased and transmission decreased. This model then influenced the design of a new mount that improved the isolation to - 65 dB at 6 GHz, even though the chip dimensions were increased to 1 cm x 1 cm, three times as large as our previous devices. We measured a coplanar resonator in this mount as preparation for larger qubit chips, and were able to identify cavity, slotline, and resonator modes.

Wirebond crosstalk and cavity modes in large chip mounts for superconducting qubits

International Nuclear Information System (INIS)

Wenner, J; Neeley, M; Bialczak, Radoslaw C; Lenander, M; Lucero, Erik; O'Connell, A D; Sank, D; Wang, H; Weides, M; Cleland, A N; Martinis, John M

2011-01-01

We analyze the performance of a microwave chip mount that uses wirebonds to connect the chip and mount grounds. A simple impedance ladder model predicts that transmission crosstalk between two feedlines falls off exponentially with distance at low frequencies, but rises to near unity above a resonance frequency set by the chip to ground capacitance. Using SPICE simulations and experimental measurements of a scale model, the basic predictions of the ladder model were verified. In particular, by decreasing the capacitance between the chip and box grounds, the resonance frequency increased and transmission decreased. This model then influenced the design of a new mount that improved the isolation to - 65 dB at 6 GHz, even though the chip dimensions were increased to 1 cm x 1 cm, three times as large as our previous devices. We measured a coplanar resonator in this mount as preparation for larger qubit chips, and were able to identify cavity, slotline, and resonator modes.

Exploring massive, genome scale datasets with the GenometriCorr package.

Directory of Open Access Journals (Sweden)

Alexander Favorov

2012-05-01

Full Text Available We have created a statistically grounded tool for determining the correlation of genomewide data with other datasets or known biological features, intended to guide biological exploration of high-dimensional datasets, rather than providing immediate answers. The software enables several biologically motivated approaches to these data and here we describe the rationale and implementation for each approach. Our models and statistics are implemented in an R package that efficiently calculates the spatial correlation between two sets of genomic intervals (data and/or annotated features, for use as a metric of functional interaction. The software handles any type of pointwise or interval data and instead of running analyses with predefined metrics, it computes the significance and direction of several types of spatial association; this is intended to suggest potentially relevant relationships between the datasets.The package, GenometriCorr, can be freely downloaded at http://genometricorr.sourceforge.net/. Installation guidelines and examples are available from the sourceforge repository. The package is pending submission to Bioconductor.

On-chip concentration of bacteria using a 3D dielectrophoretic chip and subsequent laser-based DNA extraction in the same chip

International Nuclear Information System (INIS)

Cho, Yoon-Kyoung; Kim, Tae-hyeong; Lee, Jeong-Gun

2010-01-01

We report the on-chip concentration of bacteria using a dielectrophoretic (DEP) chip with 3D electrodes and subsequent laser-based DNA extraction in the same chip. The DEP chip has a set of interdigitated Au post electrodes with 50 µm height to generate a network of non-uniform electric fields for the efficient trapping by DEP. The metal post array was fabricated by photolithography and subsequent Ni and Au electroplating. Three model bacteria samples (Escherichia coli, Staphylococcus epidermidis, Streptococcus mutans) were tested and over 80-fold concentrations were achieved within 2 min. Subsequently, on-chip DNA extraction from the concentrated bacteria in the 3D DEP chip was performed by laser irradiation using the laser-irradiated magnetic bead system (LIMBS) in the same chip. The extracted DNA was analyzed with silicon chip-based real-time polymerase chain reaction (PCR). The total process of on-chip bacteria concentration and the subsequent DNA extraction can be completed within 10 min including the manual operation time.

Liquid-Phase Packaging of a Glucose Oxidase Solution with Parylene Direct Encapsulation and an Ultraviolet Curing Adhesive Cover for Glucose Sensors

OpenAIRE

Seiichi Takamatsu; Hisanori Takano; Nguyen Binh-Khiem; Tomoyuki Takahata; Eiji Iwase; Kiyoshi Matsumoto; Isao Shimoyama

2010-01-01

We have developed a package for disposable glucose sensor chips using Parylene encapsulation of a glucose oxidase solution in the liquid phase and a cover structure made of an ultraviolet (UV) curable adhesive. Parylene was directly deposited onto a small volume (1 μL) of glucose oxidase solution through chemical vapor deposition. The cover and reaction chamber were constructed on Parylene film using a UV-curable adhesive and photolithography. The package was processed at room temperature to ...

Project monitoring package (PMP) : A package for project activity monitoring

International Nuclear Information System (INIS)

Vyas, K.N.; Kannan, A.; Susandhi, R.; Basu, S.

1987-01-01

A package for preparing PERT/CPM network diagrams has been written for PDP-11/34. The program uses PLOT-10 library calls for device interfacing. The package is essentially non-interactive in nature, and reads input data in the form of activity description and duration. It calculates the critical path time and performs time scaling of the events. The report gives a brief outline of the logic used, a sample plot and tabular output for reference. An additional facility for performing project activity monitoring has also been implemented. Activity monitoring generally requires various reports such as feed back reports from various group co-ordinators, information report for project co-ordinator and brief periodical reports for management. A package 'DATATRIEVE' (DTR) on PDP-11/34 system is utilized for generating the above mentioned reports. As DTR can also use normal sequential files, an interfacing program has been written which reformats the files accepted by PERT program acceptable to DTR. Various types of reports as generated by DTR are included. However this part of the package is not transportable and can be implemented only on systems having DTR. 6 figures. (author)

Ultra-thin silicon (UTSi) on insulator CMOS transceiver and time-division multiplexed switch chips for smart pixel integration

Science.gov (United States)

Zhang, Liping; Sawchuk, Alexander A.

2001-12-01

We describe the design, fabrication and functionality of two different 0.5 micron CMOS optoelectronic integrated circuit (OEIC) chips based on the Peregrine Semiconductor Ultra-Thin Silicon on insulator technology. The Peregrine UTSi silicon- on-sapphire (SOS) technology is a member of the silicon-on- insulator (SOI) family. The low-loss synthetic sapphire substrate is optically transparent and has good thermal conductivity and coefficient of thermal expansion properties, which meet the requirements for flip-chip bonding of VCSELs and other optoelectronic input-output components. One chip contains transceiver and network components, including four channel high-speed CMOS transceiver modules, pseudo-random bit stream (PRBS) generators, a voltage controlled oscillator (VCO) and other test circuits. The transceiver chips can operate in both self-testing mode and networking mode. An on- chip clock and true-single-phase-clock (TSPC) D-flip-flop have been designed to generate a PRBS at over 2.5 Gb/s for the high-speed transceiver arrays to operate in self-testing mode. In the networking mode, an even number of transceiver chips forms a ring network through free-space or fiber ribbon interconnections. The second chip contains four channel optical time-division multiplex (TDM) switches, optical transceiver arrays, an active pixel detector and additional test devices. The eventual applications of these chips will require monolithic OEICs with integrated optical input and output. After fabrication and testing, the CMOS transceiver array dies will be packaged with 850 nm vertical cavity surface emitting lasers (VCSELs), and metal-semiconductor- metal (MSM) or GaAs p-i-n detector die arrays to achieve high- speed optical interconnections. The hybrid technique could be either wire bonding or flip-chip bonding of the CMOS SOS smart-pixel arrays with arrays of VCSELs and photodetectors onto an optoelectronic chip carrier as a multi-chip module (MCM).

27 CFR 19.343 - Addition of oak chips to spirits and addition of caramel to brandy and rum.

Science.gov (United States)

2010-04-01

... spirits and addition of caramel to brandy and rum. 19.343 Section 19.343 Alcohol, Tobacco Products and... PLANTS Storage § 19.343 Addition of oak chips to spirits and addition of caramel to brandy and rum. Oak... records. Caramel possessing no material sweetening properties may be added to rum or brandy in packages or...

HyDe: a Python Package for Genome-Scale Hybridization Detection.

Science.gov (United States)

Blischak, Paul D; Chifman, Julia; Wolfe, Andrea D; Kubatko, Laura S

2018-03-19

The analysis of hybridization and gene flow among closely related taxa is a common goal for researchers studying speciation and phylogeography. Many methods for hybridization detection use simple site pattern frequencies from observed genomic data and compare them to null models that predict an absence of gene flow. The theory underlying the detection of hybridization using these site pattern probabilities exploits the relationship between the coalescent process for gene trees within population trees and the process of mutation along the branches of the gene trees. For certain models, site patterns are predicted to occur in equal frequency (i.e., their difference is 0), producing a set of functions called phylogenetic invariants. In this paper we introduce HyDe, a software package for detecting hybridization using phylogenetic invariants arising under the coalescent model with hybridization. HyDe is written in Python, and can be used interactively or through the command line using pre-packaged scripts. We demonstrate the use of HyDe on simulated data, as well as on two empirical data sets from the literature. We focus in particular on identifying individual hybrids within population samples and on distinguishing between hybrid speciation and gene flow. HyDe is freely available as an open source Python package under the GNU GPL v3 on both GitHub (https://github.com/pblischak/HyDe) and the Python Package Index (PyPI: https://pypi.python.org/pypi/phyde).

Chip-scale pattern modification method for equalizing residual layer thickness in nanoimprint lithography

Science.gov (United States)

Youn, Sung-Won; Suzuki, Kenta; Hiroshima, Hiroshi

2018-06-01

A software program for modifying a mold design to obtain a uniform residual layer thickness (RLT) distribution has been developed and its validity was verified by UV-nanoimprint lithography (UV-NIL) simulation. First, the effects of granularity (G) on both residual layer uniformity and filling characteristics were characterized. For a constant complementary pattern depth and a granularity that was sufficiently larger than the minimum pattern width, filling time decreased with the decrease in granularity. For a pattern design with a wide density range and an irregular distribution, the choice of a small granularity was not always a good strategy since the etching depth required for a complementary pattern occasionally exceptionally increased with the decrease in granularity. On basis of the results obtained, the automated method was applied to a chip-scale pattern modification. Simulation results showed a marked improvement in residual layer thickness uniformity for a capacity-equalized (CE) mold. For the given conditions, the standard deviation of RLT decreased in the range from 1/3 to 1/5 in accordance with pattern designs.

Chips 2020

CERN Document Server

2016-01-01

The release of this second volume of CHIPS 2020 coincides with the 50th anniversary of Moore’s Law, a critical year marked by the end of the nanometer roadmap and by a significantly reduced annual rise in chip performance. At the same time, we are witnessing a data explosion in the Internet, which is consuming 40% more electrical power every year, leading to fears of a major blackout of the Internet by 2020. The messages of the first CHIPS 2020, published in 2012, concerned the realization of quantum steps for improving the energy efficiency of all chip functions. With this second volume, we review these messages and amplify upon the most promising directions: ultra-low-voltage electronics, nanoscale monolithic 3D integration, relevant-data, brain- and human-vision-inspired processing, and energy harvesting for chip autonomy. The team of authors, enlarged by more world leaders in low-power, monolithic 3D, video, and Silicon brains, presents new vistas in nanoelectronics, promising  Moore-like exponential g...

Quantum interference in heterogeneous superconducting-photonic circuits on a silicon chip.

Science.gov (United States)

Schuck, C; Guo, X; Fan, L; Ma, X; Poot, M; Tang, H X

2016-01-21

Quantum information processing holds great promise for communicating and computing data efficiently. However, scaling current photonic implementation approaches to larger system size remains an outstanding challenge for realizing disruptive quantum technology. Two main ingredients of quantum information processors are quantum interference and single-photon detectors. Here we develop a hybrid superconducting-photonic circuit system to show how these elements can be combined in a scalable fashion on a silicon chip. We demonstrate the suitability of this approach for integrated quantum optics by interfering and detecting photon pairs directly on the chip with waveguide-coupled single-photon detectors. Using a directional coupler implemented with silicon nitride nanophotonic waveguides, we observe 97% interference visibility when measuring photon statistics with two monolithically integrated superconducting single-photon detectors. The photonic circuit and detector fabrication processes are compatible with standard semiconductor thin-film technology, making it possible to implement more complex and larger scale quantum photonic circuits on silicon chips.

A 1,000 Frames/s Programmable Vision Chip with Variable Resolution and Row-Pixel-Mixed Parallel Image Processors

Directory of Open Access Journals (Sweden)

Nanjian Wu

2009-07-01

Full Text Available A programmable vision chip with variable resolution and row-pixel-mixed parallel image processors is presented. The chip consists of a CMOS sensor array, with row-parallel 6-bit Algorithmic ADCs, row-parallel gray-scale image processors, pixel-parallel SIMD Processing Element (PE array, and instruction controller. The resolution of the image in the chip is variable: high resolution for a focused area and low resolution for general view. It implements gray-scale and binary mathematical morphology algorithms in series to carry out low-level and mid-level image processing and sends out features of the image for various applications. It can perform image processing at over 1,000 frames/s (fps. A prototype chip with 64 × 64 pixels resolution and 6-bit gray-scale image is fabricated in 0.18 mm Standard CMOS process. The area size of chip is 1.5 mm × 3.5 mm. Each pixel size is 9.5 μm × 9.5 μm and each processing element size is 23 μm × 29 μm. The experiment results demonstrate that the chip can perform low-level and mid-level image processing and it can be applied in the real-time vision applications, such as high speed target tracking.

On-chip spectroscopy with thermally tuned high-Q photonic crystal cavities

Energy Technology Data Exchange (ETDEWEB)

Liapis, Andreas C., E-mail: andreas.liapis@gmail.com; Gao, Boshen; Siddiqui, Mahmudur R. [The Institute of Optics, University of Rochester, Rochester, New York 14627 (United States); Shi, Zhimin [Department of Physics, University of South Florida, Tampa, Florida 33620 (United States); Boyd, Robert W. [The Institute of Optics, University of Rochester, Rochester, New York 14627 (United States); Department of Physics and School of Electrical Engineering and Computer Science, University of Ottawa, Ottawa, Ontario K1N 6N5 (Canada)

2016-01-11

Spectroscopic methods are a sensitive way to determine the chemical composition of potentially hazardous materials. Here, we demonstrate that thermally tuned high-Q photonic crystal cavities can be used as a compact high-resolution on-chip spectrometer. We have used such a chip-scale spectrometer to measure the absorption spectra of both acetylene and hydrogen cyanide in the 1550 nm spectral band and show that we can discriminate between the two chemical species even though the two materials have spectral features in the same spectral region. Our results pave the way for the development of chip-size chemical sensors that can detect toxic substances.

Lab-on-a-Chip Based Protein Crystallization

Science.gov (United States)

vanderWoerd, Mark J.; Brasseur, Michael M.; Spearing, Scott F.; Whitaker, Ann F. (Technical Monitor)

2001-01-01

We are developing a novel technique with which we will grow protein crystals in very small volumes, utilizing chip-based, microfluidic ("LabChip") technology. This development, which is a collaborative effort between NASA's Marshall Space Flight Center and Caliper Technologies Corporation, promises a breakthrough in the field of protein crystal growth. Our initial results obtained from two model proteins, Lysozyme and Thaumatin, show that it is feasible to dispense and adequately mix protein and precipitant solutions on a nano-liter scale. The mixtures have shown crystal growth in volumes in the range of 10 nanoliters to 5 microliters. In addition, large diffraction quality crystals were obtained by this method. X-ray data from these crystals were shown to be of excellent quality. Our future efforts will include the further development of protein crystal growth with LabChip(trademark) technology for more complex systems. We will initially address the batch growth method, followed by the vapor diffusion method and the liquid-liquid diffusion method. The culmination of these chip developments is to lead to an on orbit protein crystallization facility on the International Space Station. Structural biologists will be invited to utilize the on orbit Iterative Biological Crystallization facility to grow high quality macromolecular crystals in microgravity.

Price of forest chips decreasing

International Nuclear Information System (INIS)

Hakkila, P.

2001-01-01

Use of forest chips was studied in 1999 in the national Puuenergia (Wood Energy) research program. Wood combusting heating plants were questioned about are the main reasons restricting the increment of the use of forest chips. Heating plants, which did not use forest chips at all or which used less than 250 m 3 (625 bulk- m 3 ) in 1999 were excluded. The main restrictions for additional use of forest chips were: too high price of forest chips; lack of suppliers and/or uncertainty of deliveries; technical problems of reception and processing of forest chips; insufficiency of boiler output especially in winter; and unsatisfactory quality of chips. The price of forest chips becomes relatively high because wood biomass used for production of forest chips has to be collected from wide area. Heavy equipment has to be used even though small fragments of wood are processed, which increases the price of chips. It is essential for forest chips that the costs can be pressed down because competition with fossil fuels, peat and industrial wood residues is hard. Low market price leads to the situation in which forest owner gets no price of the raw material, the entrepreneurs operate at the limit of profitability and renovation of machinery is difficult, and forest chips suppliers have to sell the chips at prime costs. Price of forest chips has decreased significantly during the past decade. Nominal price of forest chips is now lower than two decades ago. The real price of chips has decreased even more than the nominal price, 35% during the past decade and 20% during the last five years. Chips, made of small diameter wood, are expensive because the price includes the felling costs and harvesting is carried out at thinning lots. Price is especially high if chips are made of delimbed small diameter wood due to increased the work and reduced amount of chips. The price of logging residue chips is most profitable because cutting does not cause additional costs. Recovery of chips is

An innovative container supply chain for forest chips

Energy Technology Data Exchange (ETDEWEB)

Karttunen, Kalle; Korpinen, Olli-Jussi; Laettilae, Lauri; Foehr, Jarno; Ranta, Tapio [Lappeenranta Univ. of Technology, Mikkeli (Finland)], e-mail: kalle.karttunen@lut.fi

2012-11-01

Most forest chips are transported by trucks with a solid frame. Forest-chip volumes will at least double before 2020, which means longer transport distances from the supply areas to the largest demand sites in Finland. The study concentrates on an innovative container solution based on a channel composite structure, creating a lighter, temperature-isolated, and more durable structure. In addition to the structural benefits, the container includes an innovative supply chain with a beneficial handling operation, interchangeability and maximising of the payload capacity, resulting in an energy- and cost-efficient solution. This innovative-container-based supply chain for forest chips has been studied via cost analysis, GIS analysis, and discrete-event simulation methods. The purpose of the study was to compare a truck of interchangeable containers with solid-frame trucks. The option of interchangeable containers allows combining truck logistics with other modes of transport, such as trains and waterways. The study showed the cost-efficiency potential of container truck logistics, stemming from the cost and payload savings and the supply-chain productivity advantages over solid-frame trucks. The innovative solution for interchangeable-container logistics is an option for large-scale supply of forest chips.

Development of semiconductor ΔE-E detector chip using standard bipolar IC technology

International Nuclear Information System (INIS)

Mishra, Vijay; Kataria, S.K.

2005-01-01

A proposal has been made for developing silicon based AE-E detector chip which can be used as particle identifiers in nuclear physics experiments and also in several applications in nuclear industry scenario. The proposed development work employs standard bipolar IC fabrication technology of Bharat Electronics Ltd. and the deliverable products that emerge out will be very cost effective. The present paper discusses the concept, feasibility studies and systematic plan for fabrication, characterization and packaging of the proposed detectors. (author)

Hybrid Macro-Micro Fluidics System for a Chip-Based Biosensor

National Research Council Canada - National Science Library

Tamanaha, C. R; Whitman, L. J; Colton, R.J

2002-01-01

We describe the engineering of a hybrid fluidics platform for a chip-based biosensor system that combines high-performance microfluidics components with powerful, yet compact, millimeter-scale pump and valve actuators...

Thermal analysis and improvement of cascode GaN device package for totem-pole bridgeless PFC rectifier

International Nuclear Information System (INIS)

She, Shuojie; Zhang, Wenli; Liu, Zhengyang; Lee, Fred C.; Huang, Xiucheng; Du, Weijing; Li, Qiang

2015-01-01

The totem-pole bridgeless power factor correction (PFC) rectifier has a simpler topology and higher efficiency than other boost-type bridgeless PFC rectifiers. Its promising performance is enabled by using high-voltage gallium nitride (GaN) high-electron-mobility transistors, which have considerably better figures of merit (e.g., lower reverse recovery charges and less switching losses) than the state-of-the-art silicon metal-oxide-semiconductor field-effect transistors. Cascode GaN devices in traditional packages, i.e., the TO-220 and power quad flat no-lead, are used in the totem-pole PFC boost rectifier. But the parasitic inductances induced by the traditional packages not only significantly deteriorate the switching characteristics of the discrete GaN device but also adversely affect the performance of the built PFC rectifier. A new stack-die packaging structure with an embedded capacitor has been introduced and proven to be efficient in reducing parasitic ringing at the turn-off transition and achieving true zero-voltage-switching turn-on. However, the thermal dissipation capability of the device packaged in this configuration becomes a limitation on further pushing the operating frequency and the output current level for high-efficiency power conversion. This paper focuses on the thermal analysis of the cascode GaN devices in different packages and the GaN-based multichip module used in a two-phase totem-pole bridgeless PFC boost rectifier. A series of thermal models are built based on the actual structures and materials of the packaged devices to evaluate their thermal performance. Finite element analysis (FEA) simulation results of the cascode GaN device in a flip-chip format demonstrate the possibility of increasing the device switching speed while maintaining the peak temperature of the device below 125 °C. Thermal analysis of the GaN-based power module in a very similar structure is also conducted using the FEA method. Experimental data measured using

Continuous using of the scaling factors for radionuclide evaluation in the packaged solid wastes originated from the Japanese Nuclear Power Plants since 2003

International Nuclear Information System (INIS)

2005-03-01

The amounts and concentration of the nuclides in the waste packages are estimated by measuring some key nuclides, mostly gamma emitters, from outside of the packages and by applying the scaling factor method (using the relationship between some easy to measure key nuclides and the other difficult to measure nuclides). The solid wastes are classified into two kinds of packages: homogeneous solid wastes made from concentrated liquid wastes and spent fuels solidified with cement asphalt, or plastics and heterogeneous solid wastes made of cutting metals, compacted or fused filters solidified with mortars. Japan Nuclear Energy Safety Organization (JNES) established in 2005 is in charge of the confirmation of the inside contents with radionuclide information and compliance with formalities for safety maintenance and control. (S. Ohno)

STUDY OF CHIP IGNITION AND CHIP MORPHOLOGY AFTER MILLING OF MAGNESIUM ALLOYS

Directory of Open Access Journals (Sweden)

Ireneusz Zagórski

2016-12-01

Full Text Available The paper analyses the impact of specified technological parameters of milling (vc, fz, ap on time to ignition. Stages leading to chip ignition were analysed. Metallographic images of magnesium chip were presented. No significant difference was observed in time to ignition in different chip fractions. Moreover, the surface of chips was free of products of ignition and signs of strong oxidation.

Management of Chronic Periodontitis Using Chlorhexidine Chip and Diode Laser-A Clinical Study.

Science.gov (United States)

Jose, Kachapilly Arun; Ambooken, Majo; Mathew, Jayan Jacob; Issac, Annie Valayil; Kunju, Ajithkumar Parachalil; Parameshwaran, Renjith Athirkandathil

2016-04-01

The use of adjuncts like chlorhexidine local delivery and diode laser decontamination have been found to improve the clinical outcomes of scaling and root planing in non-surgical periodontal therapy in patients with chronic periodontitis. To evaluate the effects of diode laser and chlorhexidine chip as adjuncts to scaling and root planing in the management of chronic periodontitis. The objective is to evaluate the outcome of chlorhexidine chip and diode laser as adjuncts to scaling and root planing on clinical parameters like Plaque Index, Gingival Index, probing pocket depth and clinical attachment level. Department of Periodontics. Randomized clinical trial with split mouth design. Fifteen chronic periodontitis patients having a probing pocket depth of 5mm-7mm on at least one interproximal site in each quadrant of the mouth were included in the study. After initial treatment, four sites in each patient were randomly subjected to scaling and root planing (control), chlorhexidine chip application (CHX chip group), diode laser (810 nm) decontamination (Diode laser group) or combination of both (Diode laser and chip group). Plaque Index (PI), Gingival Index (GI), probing pocket depth (PPD) and clinical attachment level (CAL) were assessed at baseline, one month and three months. Results were statistically analysed using paired T test, one-way ANOVA, Tukey's HSD test and repeated measure ANOVA. Post-treatment, the test and control sites showed a statistically significant reduction in PI, GI, PPD, and CAL. After three months, a mean PPD reduction of 1.47±0.52 mm in control group, 1.40±0.83 mm in diode laser group, 2.67±0.62 mm in CHX group, and 2.80± 0.77 mm in combination group was seen. The mean gain in CAL were 1.47±0.52 mm in the control group, 1.40±0.83 mm in diode laser group, 2.67± 0.49 mm in CHX group and 2.67± 0.82 mm in combination group respectively. The differences in PPD reduction and CAL gain between control group and CHX chip and combination

Management of Chronic Periodontitis Using Chlorhexidine Chip and Diode Laser-A Clinical Study

Science.gov (United States)

Ambooken, Majo; Mathew, Jayan Jacob; Issac, Annie Valayil; Kunju, Ajithkumar Parachalil; Parameshwaran, Renjith Athirkandathil

2016-01-01

Introduction The use of adjuncts like chlorhexidine local delivery and diode laser decontamination have been found to improve the clinical outcomes of scaling and root planing in non-surgical periodontal therapy in patients with chronic periodontitis. Aim To evaluate the effects of diode laser and chlorhexidine chip as adjuncts to scaling and root planing in the management of chronic periodontitis. The objective is to evaluate the outcome of chlorhexidine chip and diode laser as adjuncts to scaling and root planing on clinical parameters like Plaque Index, Gingival Index, probing pocket depth and clinical attachment level. Study and Design Department of Periodontics. Randomized clinical trial with split mouth design. Materials and Methods Fifteen chronic periodontitis patients having a probing pocket depth of 5mm-7mm on at least one interproximal site in each quadrant of the mouth were included in the study. After initial treatment, four sites in each patient were randomly subjected to scaling and root planing (control), chlorhexidine chip application (CHX chip group), diode laser (810 nm) decontamination (Diode laser group) or combination of both (Diode laser and chip group). Plaque Index (PI), Gingival Index (GI), probing pocket depth (PPD) and clinical attachment level (CAL) were assessed at baseline, one month and three months. Statistical analysis Results were statistically analysed using paired T test, one-way ANOVA, Tukey’s HSD test and repeated measure ANOVA. Results Post-treatment, the test and control sites showed a statistically significant reduction in PI, GI, PPD, and CAL. After three months, a mean PPD reduction of 1.47±0.52 mm in control group, 1.40±0.83 mm in diode laser group, 2.67±0.62 mm in CHX group, and 2.80± 0.77 mm in combination group was seen. The mean gain in CAL were 1.47±0.52 mm in the control group, 1.40±0.83 mm in diode laser group, 2.67± 0.49 mm in CHX group and 2.67± 0.82 mm in combination group respectively. The

The impact of packaging transparency on product attractiveness

Directory of Open Access Journals (Sweden)

Barbara Sabo

2017-12-01

Full Text Available The aim of the study was to investigate the impact of different levels of packaging transparency on the evaluation of attractiveness of a product within the packaging, in relation to whether it is a healthy or unhealthy product. Consumer preferences during buying decision process were also investigated. The study was conducted by two methods. The first one was related to consumer preferences and was based on a choice task, while the other one was related to packaging attractiveness and was based on subjective evaluation expressed through the Likert scale. Eight samples of packaging were used. They differed according to product type (healthy and unhealthy, and the level of transparency (fully transparent packaging, packaging with two windows, packaging with one window and non-transparent packaging. According to the results, consumers tend to ignore non-transparent packaging, regardless the product healthiness. The findings indicate the importance of thoughtful selection of packaging structure and its material in design process and launching the food products on the retail market.

Development of a Metal Cutting Tool Fase in Order to Create the Conditions of Ringed Chips Wrapping

OpenAIRE

Korchuganova, Mariya Anatolievna; Syrbakov, Andrey Pavlovich; Chernysheva, Tatiana Yurievna; Ivanov, G.; Korchuganov, Maksim Anatolievich

2016-01-01

When processing ductile metals with high cutting speed, there is a need to take additional measures for a comfortable and safe formation and removal of chips. In the conditions of large-scale manufacture, it is recommended to produce flow chips in the form of short fragments, while in the conditions of small-lot and single-piece manufacture, it is reasonable to wrap the chips spirally with a rather small turn radius. Such way of chips formation reduces the time of its removal from the working...

Low temperature fluidized wood chip drying with monoterpene analysis

Science.gov (United States)

Bridget N. Bero; Alarick Reiboldt; Ward Davis; Natalie Bedard; Evan Russell

2011-01-01

This paper describes the drying of ponderosa pine wood chips at low (20°C and 50°C) temperatures using a bench-scale batch pulsed fluidizer to evaluate both volatile pine oils (monoterpenes) and moisture losses during drying.

Self-Assembly of Chip-Size Components with Cavity Structures: High-Precision Alignment and Direct Bonding without Thermal Compression for Hetero Integration

Directory of Open Access Journals (Sweden)

Mitsumasa Koyanagi

2011-02-01

Full Text Available New surface mounting and packaging technologies, using self-assembly with chips having cavity structures, were investigated for three-dimensional (3D and hetero integration of complementary metal-oxide semiconductors (CMOS and microelectromechanical systems (MEMS. By the surface tension of small droplets of 0.5 wt% hydrogen fluoride (HF aqueous solution, the cavity chips, with a side length of 3 mm, were precisely aligned to hydrophilic bonding regions on the surface of plateaus formed on Si substrates. The plateaus have micro-channels to readily evaporate and fully remove the liquid from the cavities. The average alignment accuracy of the chips with a 1 mm square cavity was found to be 0.4 mm. The alignment accuracy depends, not only on the area of the bonding regions on the substrates and the length of chip periphery without the widths of channels in the plateaus, but also the area wetted by the liquid on the bonding regions. The precisely aligned chips were then directly bonded to the substrates at room temperature without thermal compression, resulting in a high shear bonding strength of more than 10 MPa.

Global review of open access risk assessment software packages valid for global or continental scale analysis

Science.gov (United States)

Daniell, James; Simpson, Alanna; Gunasekara, Rashmin; Baca, Abigail; Schaefer, Andreas; Ishizawa, Oscar; Murnane, Rick; Tijssen, Annegien; Deparday, Vivien; Forni, Marc; Himmelfarb, Anne; Leder, Jan

2015-04-01

-defined exposure and vulnerability. Without this function, many tools can only be used regionally and not at global or continental scale. It is becoming increasingly easy to use multiple packages for a single region and/or hazard to characterize the uncertainty in the risk, or use as checks for the sensitivities in the analysis. There is a potential for valuable synergy between existing software. A number of open source software packages could be combined to generate a multi-risk model with multiple views of a hazard. This extensive review has simply attempted to provide a platform for dialogue between all open source and open access software packages and to hopefully inspire collaboration between developers, given the great work done by all open access and open source developers.

Measuring the attenuation length of water in the CHIPS-M water Cherenkov detector

Energy Technology Data Exchange (ETDEWEB)

Amat, F.; Bizouard, P. [Aix Marseille University Saint-Jerome, 13013 Marseille (France); Bryant, J. [Department of Physics and Astronomy, UCL, Gower St, London WC1E 6BT (United Kingdom); Carroll, T.J.; Rijck, S. De [Department of Physics, University of Texas at Austin, Austin, TX 78712 (United States); Germani, S. [Department of Physics and Astronomy, UCL, Gower St, London WC1E 6BT (United Kingdom); Joyce, T. [School of Physics and Astronomy, University of Minnesota, Minneapolis, MN 55455 (United States); Kriesten, B. [Department of Physics, College of William & Mary, Williamsburg, VA 23187 (United States); Marshak, M.; Meier, J. [School of Physics and Astronomy, University of Minnesota, Minneapolis, MN 55455 (United States); Nelson, J.K. [Department of Physics, College of William & Mary, Williamsburg, VA 23187 (United States); Perch, A.J.; Pfützner, M.M. [Department of Physics and Astronomy, UCL, Gower St, London WC1E 6BT (United Kingdom); Salazar, R. [Department of Physics, University of Texas at Austin, Austin, TX 78712 (United States); Thomas, J., E-mail: jennifer.thomas@ucl.ac.uk [Department of Physics and Astronomy, UCL, Gower St, London WC1E 6BT (United Kingdom); Department of Physics, University of Wisconsin, Madison, WI 53706 (United States); Trokan-Tenorio, J. [Department of Physics, University of Wisconsin, Madison, WI 53706 (United States); Vahle, P. [Department of Physics, College of William & Mary, Williamsburg, VA 23187 (United States); Wade, R. [Avenir Consulting, Abingdon, Oxfordshire (United Kingdom); Wendt, C. [Department of Physics, University of Wisconsin, Madison, WI 53706 (United States); Whitehead, L.H. [Department of Physics and Astronomy, UCL, Gower St, London WC1E 6BT (United Kingdom); and others

2017-02-01

The water at the proposed site of the CHIPS water Cherenkov detector has been studied to measure its attenuation length for Cherenkov light as a function of filtering time. A scaled model of the CHIPS detector filled with water from the Wentworth 2W pit, proposed site of the CHIPS deployment, in conjunction with a 3.2 m vertical column filled with this water, was used to study the transmission of 405 nm laser light. Results consistent with attenuation lengths of up to 100 m were observed for this wavelength with filtration and UV sterilization alone.

Antimicrobial nanomaterials for food packaging applications

Directory of Open Access Journals (Sweden)

Radusin Tanja I.

2016-01-01

Full Text Available Food packaging industry presents one of the fastest growing industries nowadays. New trends in this industry, which include reducing food as well as packaging waste, improved preservation of food and prolonged shelf-life together with substitution of petrochemical sources with renewable ones are leading to development of this industrial area in diverse directions. This multidisciplinary challenge is set up both in front of food and material scientists. Nanotechnology is recently answering to these challenges, with different solutions-from improvements in materials properties to active packaging solutions, or both at the same time. Incorporation of nanoparticles into polymer matrix and preparation of hybrid materials is one of the methods of modification of polymer properties. Nano scaled materials with antimicrobial properties can act as active components when added into polymer, thereby leading to prolonged protective function of pristine food packaging material. This paper presents a review in the field of antimicrobial nanomaterials for food packaging in turn of technology, application and regulatory issues.

Efficient large volume electroporation of dendritic cells through micrometer scale manipulation of flow in a disposable polymer chip

DEFF Research Database (Denmark)

Selmeczi, David; Hansen, Thomas; Met, Özcan

2011-01-01

We present a hybrid chip of polymer and stainless steel designed for high-throughput continuous electroporation of cells in suspension. The chip is constructed with two parallel stainless steel mesh electrodes oriented perpendicular to the liquid flow. The relatively high hydrodynamic resistance ...

A regulator's perspective on physical testing for type B packages

International Nuclear Information System (INIS)

Brach, William E.

2004-01-01

The U.S. Nuclear Regulatory Commission has a great deal of experience certifying Type B transport packages as complying with the regulations in 10 CFR Part 71. With this experience base, supporting risk studies, and with an exceptional historical safety record for transport, we are very confident in both the current regulations and the methods we use to review and certify transportation packages. Nevertheless, we have a responsibility to remain vigilant and review our regulations and implementing practices with a view towards continuous improvement. NRC regulations permit certification through testing, analyses, comparison to similar approved designs, or combinations of these methods. Testing can be further broken into scale models, components, simple models, or full-scale models. NRC does not require full-scale testing for certification of any package; however, many applicants for package certification have conducted a physical testing program to demonstrate that the package design meets the hypothetical accident conditions. The plans for a repository at Yucca Mountain have raised significant interest in the United States of America in transportation of spent fuel, and created a broad stakeholder and public interest in transportation package testing. As an expected large increase in the number of spent fuel transports nears, this interest will likely grow. The technical and regulatory reasons for, or for not, performing tests need to be well understood and communicated to all stakeholders

Towards Chip Scale Liquid Chromatography and High Throughput Immunosensing

Energy Technology Data Exchange (ETDEWEB)

Ni, Jing [Iowa State Univ., Ames, IA (United States)

2000-09-21

This work describes several research projects aimed towards developing new instruments and novel methods for high throughput chemical and biological analysis. Approaches are taken in two directions. The first direction takes advantage of well-established semiconductor fabrication techniques and applies them to miniaturize instruments that are workhorses in analytical laboratories. Specifically, the first part of this work focused on the development of micropumps and microvalves for controlled fluid delivery. The mechanism of these micropumps and microvalves relies on the electrochemically-induced surface tension change at a mercury/electrolyte interface. A miniaturized flow injection analysis device was integrated and flow injection analyses were demonstrated. In the second part of this work, microfluidic chips were also designed, fabricated, and tested. Separations of two fluorescent dyes were demonstrated in microfabricated channels, based on an open-tubular liquid chromatography (OT LC) or an electrochemically-modulated liquid chromatography (EMLC) format. A reduction in instrument size can potentially increase analysis speed, and allow exceedingly small amounts of sample to be analyzed under diverse separation conditions. The second direction explores the surface enhanced Raman spectroscopy (SERS) as a signal transduction method for immunoassay analysis. It takes advantage of the improved detection sensitivity as a result of surface enhancement on colloidal gold, the narrow width of Raman band, and the stability of Raman scattering signals to distinguish several different species simultaneously without exploiting spatially-separated addresses on a biochip. By labeling gold nanoparticles with different Raman reporters in conjunction with different detection antibodies, a simultaneous detection of a dual-analyte immunoassay was demonstrated. Using this scheme for quantitative analysis was also studied and preliminary dose-response curves from an immunoassay of a

Research Article Special Issue

African Journals Online (AJOL)

pc

2017-11-24

Nov 24, 2017 ... as encapsulants to chip-scale and wafer-level packaging in ultra-large-scale- ... acetone, ethanol and 1M HCl standard cleaning process was carried out in order to remove .... [12] Fan ZH, Gu P and Nishida T (2014).

Sandwich-Architectured Poly(lactic acid)-Graphene Composite Food Packaging Films.

Science.gov (United States)

Goh, Kunli; Heising, Jenneke K; Yuan, Yang; Karahan, Huseyin E; Wei, Li; Zhai, Shengli; Koh, Jia-Xuan; Htin, Nanda M; Zhang, Feimo; Wang, Rong; Fane, Anthony G; Dekker, Matthijs; Dehghani, Fariba; Chen, Yuan

2016-04-20

Biodegradable food packaging promises a more sustainable future. Among the many different biopolymers used, poly(lactic acid) (PLA) possesses the good mechanical property and cost-effectiveness necessary of a biodegradable food packaging. However, PLA food packaging suffers from poor water vapor and oxygen barrier properties compared to many petroleum-derived ones. A key challenge is, therefore, to simultaneously enhance both the water vapor and oxygen barrier properties of the PLA food packaging. To address this issue, we design a sandwich-architectured PLA-graphene composite film, which utilizes an impermeable reduced graphene oxide (rGO) as the core barrier and commercial PLA films as the outer protective encapsulation. The synergy between the barrier and the protective encapsulation results in a significant 87.6% reduction in the water vapor permeability. At the same time, the oxygen permeability is reduced by two orders of magnitude when evaluated under both dry and humid conditions. The excellent barrier properties can be attributed to the compact lamellar microstructure and the hydrophobicity of the rGO core barrier. Mechanistic analysis shows that the large rGO lateral dimension and the small interlayer spacing between the rGO sheets have created an extensive and tortuous diffusion pathway, which is up to 1450-times the thickness of the rGO barrier. In addition, the sandwiched architecture has imbued the PLA-rGO composite film with good processability, which increases the manageability of the film and its competency to be tailored. Simulations using the PLA-rGO composite food packaging film for edible oil and potato chips also exhibit at least eight-fold extension in the shelf life of these oxygen and moisture sensitive food products. Overall, these qualities have demonstrated the high potential of a sandwich-architectured PLA-graphene composite film for food packaging applications.

A scalable single-chip multi-processor architecture with on-chip RTOS kernel

NARCIS (Netherlands)

Theelen, B.D.; Verschueren, A.C.; Reyes Suarez, V.V.; Stevens, M.P.J.; Nunez, A.

2003-01-01

Now that system-on-chip technology is emerging, single-chip multi-processors are becoming feasible. A key problem of designing such systems is the complexity of their on-chip interconnects and memory architecture. It is furthermore unclear at what level software should be integrated. An example of a

Integrated on-chip solid state capacitor based on vertically aligned carbon nanofibers, grown using a CMOS temperature compatible process

Science.gov (United States)

Saleem, Amin M.; Andersson, Rickard; Desmaris, Vincent; Enoksson, Peter

2018-01-01

Complete miniaturized on-chip integrated solid-state capacitors have been fabricated based on conformal coating of vertically aligned carbon nanofibers (VACNFs), using a CMOS temperature compatible microfabrication processes. The 5 μm long VACNFs, operating as electrode, are grown on a silicon substrate and conformally coated by aluminum oxide dielectric using atomic layer deposition (ALD) technique. The areal (footprint) capacitance density value of 11-15 nF/mm2 is realized with high reproducibility. The CMOS temperature compatible microfabrication, ultra-low profile (less than 7 μm thickness) and high capacitance density would enables direct integration of micro energy storage devices on the active CMOS chip, multi-chip package and passives on silicon or glass interposer. A model is developed to calculate the surface area of VACNFs and the effective capacitance from the devices. It is thereby shown that 71% of surface area of the VACNFs has contributed to the measured capacitance, and by using the entire area the capacitance can potentially be increased.

Lab-on-a-chip devices and micro-total analysis systems a practical guide

CERN Document Server

Svendsen, Winnie

2015-01-01

This book covers all the steps in order to fabricate a lab-on-a-chip device starting from the idea, the design, simulation, fabrication and final evaluation. Additionally, it includes basic theory on microfluidics essential to understand how fluids behave at such reduced scale. Examples of successful histories of lab-on-a-chip systems that made an impact in fields like biomedicine and life sciences are also provided.

GaN-on-Si blue/white LEDs: epitaxy, chip, and package

Science.gov (United States)

Qian, Sun; Wei, Yan; Meixin, Feng; Zengcheng, Li; Bo, Feng; Hanmin, Zhao; Hui, Yang

2016-04-01

The dream of epitaxially integrating III-nitride semiconductors on large diameter silicon is being fulfilled through the joint R&D efforts of academia and industry, which is driven by the great potential of GaN-on-silicon technology in improving the efficiency yet at a much reduced manufacturing cost for solid state lighting and power electronics. It is very challenging to grow high quality GaN on Si substrates because of the huge mismatch in the coefficient of thermal expansion (CTE) and the large mismatch in lattice constant between GaN and silicon, often causing a micro-crack network and a high density of threading dislocations (TDs) in the GaN film. Al-composition graded AlGaN/AlN buffer layers have been utilized to not only build up a compressive strain during the high temperature growth for compensating the tensile stress generated during the cool down, but also filter out the TDs to achieve crack-free high-quality n-GaN film on Si substrates, with an X-ray rocking curve linewidth below 300 arcsec for both (0002) and (101¯2) diffractions. Upon the GaN-on-Si templates, prior to the deposition of p-AlGaN and p-GaN layers, high quality InGaN/GaN multiple quantum wells (MQWs) are overgrown with well-engineered V-defects intentionally incorporated to shield the TDs as non-radiative recombination centers and to enhance the hole injection into the MQWs through the via-like structures. The as-grown GaN-on-Si LED wafers are processed into vertical structure thin film LED chips with a reflective p-electrode and the N-face surface roughened after the removal of the epitaxial Si(111) substrates, to enhance the light extraction efficiency. We have commercialized GaN-on-Si LEDs with an average efficacy of 150-160 lm/W for 1mm2 LED chips at an injection current of 350 mA, which have passed the 10000-h LM80 reliability test. The as-produced GaN-on-Si LEDs featured with a single-side uniform emission and a nearly Lambertian distribution can adopt the wafer-level phosphor

Practical Packaging Technology for Microfluidic Systems

International Nuclear Information System (INIS)

Lee, Hwan Yong; Han, Song I; Han, Ki Ho

2010-01-01

This paper presents the technology for the design, fabrication, and characterization of a microfluidic system interface (MSI): the purpose of this technology is to enable the integration of complex microfluidic systems. The MSI technology can be applied in a simple manner for realizing complex arrangements of microfluidic interconnects, integrated microvalves for fluid control, and optical windows for on-chip optical processes. A microfluidic system for the preparation of genetic samples was used as the test vehicle to prove the effectiveness of the MSI technology for packaging complex microfluidic systems with multiple functionalities. The miniaturized genetic sample preparation system comprised several functional compartments, including compartments for cell purification, cell separation, cell lysis, solid-phase DNA extraction, polymerase chain reaction, and capillary electrophoresis. Additionally, the functional operation of the solid-phase extraction and PCR thermocycling compartments was demonstrated by using the MSI

Packaging and interconnection for superconductive circuitry

International Nuclear Information System (INIS)

Anacker, W.

1976-01-01

A three dimensional microelectronic module packaged for reduced signal propagation delay times including a plurality of circuit carrying means, which may comprise unbacked chips, with integrated superconductive circuitry thereon is described. The circuit carrying means are supported on their edges and have contact lands in the vicinity of, or at, the edges to provide for interconnecting circuitry. The circuit carrying means are supported by supporting means which include slots to provide a path for interconnection wiring to contact the lands of the circuit carrying means. Further interconnecting wiring may take the form of integrated circuit wiring on the reverse side of the supporting means. The low heat dissipation of the superconductive circuitry allows the circuit carrying means to be spaced approximately no less than 30 mils apart. The three dimensional arrangement provides lower random propagation delays than would a planar array of circuits

Neural Cell Chip Based Electrochemical Detection of Nanotoxicity.

Science.gov (United States)

Kafi, Md Abdul; Cho, Hyeon-Yeol; Choi, Jeong Woo

2015-07-02

Development of a rapid, sensitive and cost-effective method for toxicity assessment of commonly used nanoparticles is urgently needed for the sustainable development of nanotechnology. A neural cell with high sensitivity and conductivity has become a potential candidate for a cell chip to investigate toxicity of environmental influences. A neural cell immobilized on a conductive surface has become a potential tool for the assessment of nanotoxicity based on electrochemical methods. The effective electrochemical monitoring largely depends on the adequate attachment of a neural cell on the chip surfaces. Recently, establishment of integrin receptor specific ligand molecules arginine-glycine-aspartic acid (RGD) or its several modifications RGD-Multi Armed Peptide terminated with cysteine (RGD-MAP-C), C(RGD)₄ ensure farm attachment of neural cell on the electrode surfaces either in their two dimensional (dot) or three dimensional (rod or pillar) like nano-scale arrangement. A three dimensional RGD modified electrode surface has been proven to be more suitable for cell adhesion, proliferation, differentiation as well as electrochemical measurement. This review discusses fabrication as well as electrochemical measurements of neural cell chip with particular emphasis on their use for nanotoxicity assessments sequentially since inception to date. Successful monitoring of quantum dot (QD), graphene oxide (GO) and cosmetic compound toxicity using the newly developed neural cell chip were discussed here as a case study. This review recommended that a neural cell chip established on a nanostructured ligand modified conductive surface can be a potential tool for the toxicity assessments of newly developed nanomaterials prior to their use on biology or biomedical technologies.

Neural Cell Chip Based Electrochemical Detection of Nanotoxicity

Directory of Open Access Journals (Sweden)

Md. Abdul Kafi

2015-07-01

Full Text Available Development of a rapid, sensitive and cost-effective method for toxicity assessment of commonly used nanoparticles is urgently needed for the sustainable development of nanotechnology. A neural cell with high sensitivity and conductivity has become a potential candidate for a cell chip to investigate toxicity of environmental influences. A neural cell immobilized on a conductive surface has become a potential tool for the assessment of nanotoxicity based on electrochemical methods. The effective electrochemical monitoring largely depends on the adequate attachment of a neural cell on the chip surfaces. Recently, establishment of integrin receptor specific ligand molecules arginine-glycine-aspartic acid (RGD or its several modifications RGD-Multi Armed Peptide terminated with cysteine (RGD-MAP-C, C(RGD4 ensure farm attachment of neural cell on the electrode surfaces either in their two dimensional (dot or three dimensional (rod or pillar like nano-scale arrangement. A three dimensional RGD modified electrode surface has been proven to be more suitable for cell adhesion, proliferation, differentiation as well as electrochemical measurement. This review discusses fabrication as well as electrochemical measurements of neural cell chip with particular emphasis on their use for nanotoxicity assessments sequentially since inception to date. Successful monitoring of quantum dot (QD, graphene oxide (GO and cosmetic compound toxicity using the newly developed neural cell chip were discussed here as a case study. This review recommended that a neural cell chip established on a nanostructured ligand modified conductive surface can be a potential tool for the toxicity assessments of newly developed nanomaterials prior to their use on biology or biomedical technologies.

On-chip electrochromic micro display for a disposable bio-sensor chip

Science.gov (United States)

Zhu, Yanjun; Tsukamoto, Takashiro; Tanaka, Shuji

2017-12-01

This paper reports an on-chip electrochromic micro display made of polyaniline (PANi) which can be easily made on a CMOS chip. Micro-patterned PANi thin films were selectively deposited on pre-patterned microelectrodes by using electrodeposition. The optimum conditions for deposition and electrochromism were investigated. An 8-pixel on-chip micro display was made on a Si chip. The color of each PANi film could be independently but simultaneously controlled, which means any 1-byte digital data could be displayed on the display. The PANi display had a response time as fast as about 100 ms, which means the transfer data rate was as fast as 80 bits per second.

On-Chip Microwave Quantum Hall Circulator

Directory of Open Access Journals (Sweden)

A. C. Mahoney

2017-01-01

Full Text Available Circulators are nonreciprocal circuit elements that are integral to technologies including radar systems, microwave communication transceivers, and the readout of quantum information devices. Their nonreciprocity arises from the interference of microwaves over the centimeter scale of the signal wavelength, in the presence of bulky magnetic media that breaks time-reversal symmetry. Here, we realize a completely passive on-chip microwave circulator with size 1/1000th the wavelength by exploiting the chiral, “slow-light” response of a two-dimensional electron gas in the quantum Hall regime. For an integrated GaAs device with 330  μm diameter and about 1-GHz center frequency, a nonreciprocity of 25 dB is observed over a 50-MHz bandwidth. Furthermore, the nonreciprocity can be dynamically tuned by varying the voltage at the port, an aspect that may enable reconfigurable passive routing of microwave signals on chip.

A Transcriptome—Targeting EcoChip for Assessing Functional Mycodiversity

Directory of Open Access Journals (Sweden)

Derek Peršoh

2011-10-01

Full Text Available A functional biodiversity microarray (EcoChip prototype has been developed to facilitate the analysis of fungal communities in environmental samples with broad functional and phylogenetic coverage and to enable the incorporation of nucleic acid sequence data as they become available from large-scale (next generation sequencing projects. A dual probe set (DPS was designed to detect a functional enzyme transcripts at conserved protein sites and b phylogenetic barcoding transcripts at ITS regions present in precursor rRNA. Deviating from the concept of GeoChip-type microarrays, the presented EcoChip microarray phylogenetic information was obtained using a dedicated set of barcoding microarray probes, whereas functional gene expression was analyzed by conserved domain-specific probes. By unlinking these two target groups, the shortage of broad sequence information of functional enzyme-coding genes in environmental communities became less important. The novel EcoChip microarray could be successfully applied to identify specific degradation activities in environmental samples at considerably high phylogenetic resolution. Reproducible and unbiased microarray signals could be obtained with chemically labeled total RNA preparations, thus avoiding the use of enzymatic labeling steps. ITS precursor rRNA was detected for the first time in a microarray experiment, which confirms the applicability of the EcoChip concept to selectively quantify the transcriptionally active part of fungal communities at high phylogenetic resolution. In addition, the chosen microarray platform facilitates the conducting of experiments with high sample throughput in almost any molecular biology laboratory.

Cost calculation model concerning small-scale production of chips and split firewood

International Nuclear Information System (INIS)

Ryynaenen, S.; Naett, H.; Valkonen, J.

1995-01-01

The TTS-Institute's Forestry Department has developed a computer-based cost calculation model for the production of wood chips and split firewood. This development work was carried out in conjunction with the nation-wide BIOENERGY -research programme. The said calculation model eases and speeds up the calculation of unit costs and resource needs in harvesting systems for wood chips and split firewood. The model also enables the user to find out how changes in the productivity and costs bases of different harvesting chains influences the unit costs of the system as a whole. The undertaking was composed of the following parts: clarification and modification of productivity bases for application in the model as mathematical models, clarification of machine and device costs bases, designing of the structure and functions of the calculation model, construction and testing of the model's 0-version, model calculations concerning typical chains, review of calculation bases, and charting of development needs focusing on the model. The calculation model was developed to serve research needs, but with further development it could be useful as a tool in forestry and agricultural extension work, related schools and colleges, and in the hands of firewood producers. (author)

Optimization of a PCRAM Chip for high-speed read and highly reliable reset operations

Science.gov (United States)

Li, Xiaoyun; Chen, Houpeng; Li, Xi; Wang, Qian; Fan, Xi; Hu, Jiajun; Lei, Yu; Zhang, Qi; Tian, Zhen; Song, Zhitang

2016-10-01

The widely used traditional Flash memory suffers from its performance limits such as its serious crosstalk problems, and increasing complexity of floating gate scaling. Phase change random access memory (PCRAM) becomes one of the most potential nonvolatile memories among the new memory techniques. In this paper, a 1M-bit PCRAM chip is designed based on the SMIC 40nm CMOS technology. Focusing on the read and write performance, two new circuits with high-speed read operation and highly reliable reset operation are proposed. The high-speed read circuit effectively reduces the reading time from 74ns to 40ns. The double-mode reset circuit improves the chip yield. This 1M-bit PCRAM chip has been simulated on cadence. After layout design is completed, the chip will be taped out for post-test.

X-CHIP: an integrated platform for high-throughput protein crystallization and on-the-chip X-ray diffraction data collection

International Nuclear Information System (INIS)

Kisselman, Gera; Qiu, Wei; Romanov, Vladimir; Thompson, Christine M.; Lam, Robert; Battaile, Kevin P.; Pai, Emil F.; Chirgadze, Nickolay Y.

2011-01-01

The X-CHIP (X-ray Crystallography High-throughput Integrated Platform) is a novel microchip that has been developed to combine multiple steps of the crystallographic pipeline from crystallization to diffraction data collection on a single device to streamline the entire process. The X-CHIP (X-ray Crystallization High-throughput Integrated Platform) is a novel microchip that has been developed to combine multiple steps of the crystallographic pipeline from crystallization to diffraction data collection on a single device to streamline the entire process. The system has been designed for crystallization condition screening, visual crystal inspection, initial X-ray screening and data collection in a high-throughput fashion. X-ray diffraction data acquisition can be performed directly on-the-chip at room temperature using an in situ approach. The capabilities of the chip eliminate the necessity for manual crystal handling and cryoprotection of crystal samples, while allowing data collection from multiple crystals in the same drop. This technology would be especially beneficial for projects with large volumes of data, such as protein-complex studies and fragment-based screening. The platform employs hydrophilic and hydrophobic concentric ring surfaces on a miniature plate transparent to visible light and X-rays to create a well defined and stable microbatch crystallization environment. The results of crystallization and data-collection experiments demonstrate that high-quality well diffracting crystals can be grown and high-resolution diffraction data sets can be collected using this technology. Furthermore, the quality of a single-wavelength anomalous dispersion data set collected with the X-CHIP at room temperature was sufficient to generate interpretable electron-density maps. This technology is highly resource-efficient owing to the use of nanolitre-scale drop volumes. It does not require any modification for most in-house and synchrotron beamline systems and offers

X-CHIP: an integrated platform for high-throughput protein crystallization and on-the-chip X-ray diffraction data collection

Energy Technology Data Exchange (ETDEWEB)

Kisselman, Gera; Qiu, Wei; Romanov, Vladimir; Thompson, Christine M.; Lam, Robert [Ontario Cancer Institute, Princess Margaret Hospital, University Health Network, Toronto, Ontario M5G 2C4 (Canada); Battaile, Kevin P. [Argonne National Laboratory, Argonne, Illinois 60439 (United States); Pai, Emil F.; Chirgadze, Nickolay Y., E-mail: nchirgad@uhnresearch.ca [Ontario Cancer Institute, Princess Margaret Hospital, University Health Network, Toronto, Ontario M5G 2C4 (Canada); University of Toronto, Toronto, Ontario M5S 1A8 (Canada)

2011-06-01

The X-CHIP (X-ray Crystallography High-throughput Integrated Platform) is a novel microchip that has been developed to combine multiple steps of the crystallographic pipeline from crystallization to diffraction data collection on a single device to streamline the entire process. The X-CHIP (X-ray Crystallization High-throughput Integrated Platform) is a novel microchip that has been developed to combine multiple steps of the crystallographic pipeline from crystallization to diffraction data collection on a single device to streamline the entire process. The system has been designed for crystallization condition screening, visual crystal inspection, initial X-ray screening and data collection in a high-throughput fashion. X-ray diffraction data acquisition can be performed directly on-the-chip at room temperature using an in situ approach. The capabilities of the chip eliminate the necessity for manual crystal handling and cryoprotection of crystal samples, while allowing data collection from multiple crystals in the same drop. This technology would be especially beneficial for projects with large volumes of data, such as protein-complex studies and fragment-based screening. The platform employs hydrophilic and hydrophobic concentric ring surfaces on a miniature plate transparent to visible light and X-rays to create a well defined and stable microbatch crystallization environment. The results of crystallization and data-collection experiments demonstrate that high-quality well diffracting crystals can be grown and high-resolution diffraction data sets can be collected using this technology. Furthermore, the quality of a single-wavelength anomalous dispersion data set collected with the X-CHIP at room temperature was sufficient to generate interpretable electron-density maps. This technology is highly resource-efficient owing to the use of nanolitre-scale drop volumes. It does not require any modification for most in-house and synchrotron beamline systems and offers

Qubit entanglement between ring-resonator photon-pair sources on a silicon chip

Science.gov (United States)

Silverstone, J. W.; Santagati, R.; Bonneau, D.; Strain, M. J.; Sorel, M.; O'Brien, J. L.; Thompson, M. G.

2015-01-01

Entanglement—one of the most delicate phenomena in nature—is an essential resource for quantum information applications. Scalable photonic quantum devices must generate and control qubit entanglement on-chip, where quantum information is naturally encoded in photon path. Here we report a silicon photonic chip that uses resonant-enhanced photon-pair sources, spectral demultiplexers and reconfigurable optics to generate a path-entangled two-qubit state and analyse its entanglement. We show that ring-resonator-based spontaneous four-wave mixing photon-pair sources can be made highly indistinguishable and that their spectral correlations are small. We use on-chip frequency demultiplexers and reconfigurable optics to perform both quantum state tomography and the strict Bell-CHSH test, both of which confirm a high level of on-chip entanglement. This work demonstrates the integration of high-performance components that will be essential for building quantum devices and systems to harness photonic entanglement on the large scale. PMID:26245267

GeoChip 3.0 as a high-thoughput tool for analyzing microbial community composition, structure, and functional activity

Energy Technology Data Exchange (ETDEWEB)

He, Z.; Deng, Y.; Van Nostrand, J.D.; Tu, Q.; Xu, M.; Hemme, C.L.; Li, X.; Wu, L.; Gentry, T.J.; Yin, Y.; Liebich, J.; Hazen, T.C.; Zhou, J.

2010-04-01

A new generation of functional gene arrays (FGAs; GeoChip 3.0) has been developed, with {approx}28,000 probes covering approximately 57,000 gene variants from 292 functional gene families involved in carbon, nitrogen, phosphorus and sulfur cycles, energy metabolism, antibiotic resistance, metal resistance and organic contaminant degradation. GeoChip 3.0 also has several other distinct features, such as a common oligo reference standard (CORS) for data normalization and comparison, a software package for data management and future updating and the gyrB gene for phylogenetic analysis. Computational evaluation of probe specificity indicated that all designed probes would have a high specificity to their corresponding targets. Experimental analysis with synthesized oligonucleotides and genomic DNAs showed that only 0.0036-0.025% false-positive rates were observed, suggesting that the designed probes are highly specific under the experimental conditions examined. In addition, GeoChip 3.0 was applied to analyze soil microbial communities in a multifactor grassland ecosystem in Minnesota, USA, which showed that the structure, composition and potential activity of soil microbial communities significantly changed with the plant species diversity. As expected, GeoChip 3.0 is a high-throughput powerful tool for studying microbial community functional structure, and linking microbial communities to ecosystem processes and functioning.

Study on the mechanism of color coordinate shift of LED package

Science.gov (United States)

Zhuang, Yunyi; Wang, Yong; Yang, Bobo; Li, Zhanguo; Yang, Lei; Zou, Jun

2017-07-01

In the paper, the influences of the chip, silicone and phosphors on the color coordinate shift of LED were studied. In the process of LED baking, it was found that the effect of the chip and silicone on the color coordinate drift is less than 3% through the analysis of each influencing factor. But the influence of the phosphors is large and accounted for 11.11% of the overall impact factors. Therefore, it is important to select the better green phosphors in thermal stability for the LED package and it has a guiding significance to the color coordinate of LED distribution. Project supported by the National Natural Science Foundation of China (No. 11474036), the Natural Science Foundation of Shanghai (No. 12ZR1430900), the Shanghai Institute of Technology Talents Scheme (No. YJ2014-04), the Shanghai Municipal Alliance Program (Nos. Lm201514, Lm201505, Lm201455), the Science and Technology Commission of Shanghai Municipality (CN) (No. 14500503300), the Shanghai Cooperative Project (No. ShanghaiCXY-2013-61), and the Jiashan County Technology Program (No. 20141316).

Interconnect mechanisms in microelectronic packaging

Science.gov (United States)

Roma, Maria Penafrancia C.

alloy showed differences in adhesion strength and IMC formation. Bond strength by wire pull testing showed the 95Ag alloy with higher values while shear bond testing showed the 88Ag higher bond strength. Use of Cu pillars in flip chips and eutectic bonding in wafer level chip scale packages are direct consequences of diminishing interconnect dimension as a result of the drive for miniaturization. The combination of Cu-Sn interdiffusion, Kirkendall mechanism and heterogeneous vacancy precipitation are the main causes of IMC and void formation in Cu pillar - Sn solder - Cu lead frame sandwich structure. However, adding a Ni barrier agent showed less porous IMC layer as well as void formation as a result of the modified Cu and Sn movement well as the void formation. Direct die to die bonding using Al-Ge eutectic bonds is necessary when 3D integration is needed to reduce the footprint of a package. Hermeticity and adhesion strength are a function of the Al/Ge thickness ratio, bonding pressure, temperature and time. Scanning Electron Microscope (SEM) and Focused Ion Beam (FIB) allowed imaging of interfacial microstructures, porosity, grain morphology while Scanning Transmission Electron microscope (STEM) provided diffusion profile and confirmed interdiffusion. Ion polishing technique provided information on porosity and when imaged using backscattered mode, grain structure confirmed mechanical deformation of the bonds. Measurements of the interfacial bond strength are made by wire pull tests and ball shear tests based on existing industry standard tests. However, for the Al-Ge eutectic bonds, no standard strength is available so a test is developed using the stud pull test method using the Dage 4000 Plus to yield consistent results. Adhesion strengths of 30-40 MPa are found for eutectic bonded packages however, as low as 20MPa was measured in low temperature bonded areas.

Service Packages – Attractiveness Has Many Faces

Directory of Open Access Journals (Sweden)

Ilona Bondos

2016-01-01

Full Text Available This article is an attempt to identify the impact of the customer age (especially the Baby boomers generation and the X and the Y generation on the assessment of incentives to buy service package. Belonging to different age generations seems to be important for the effectiveness of service packages sales – the entrance by the consumers in subsequent phases of the life cycle is related to their perception of the market offer. The starting point for the empirical part of the article was to analyze the different average scores attractiveness of the ten packages service features (incentives to purchase. Then, using multidimensional scaling authors determined the similarity or dissimilarity data on a set of applied incentives to use service packages. Visible differences indicate a different perception of the attractiveness of packages representatives of the Baby boomer generation and Y generation. Managerial implications and directions for future research are discussed.

Long-term durability experiments with concrete-based waste packages in simulated repository conditions

International Nuclear Information System (INIS)

Ipatti, A.

1993-03-01

Two extensive experiments on long-term durability of waste packages in simulated repository conditions are described. The first one is a 'half-scale experiment' comprising radioactive waste product and half-scale concrete containers in site specific groundwater conditions. The second one is 'full-scale experiment' including simulated inactive waste product and full-scale concrete container stored in slowly flowing fresh water. The scope of the experiments is to demonstrate long-term behaviour of the designed waste packages in contact with moderately concrete aggressive groundwater, and to evaluate the possible interactions between the waste product, concrete container and ground water. As the waste packages are made of high-quality concrete, provisions have been made to continue the experiments for several years

Advanced Liquid-Free, Piezoresistive, SOI-Based Pressure Sensors for Measurements in Harsh Environments

Directory of Open Access Journals (Sweden)

Ha-Duong Ngo

2015-08-01

Full Text Available In this paper we present and discuss two innovative liquid-free SOI sensors for pressure measurements in harsh environments. The sensors are capable of measuring pressures at high temperatures. In both concepts media separation is realized using a steel membrane. The two concepts represent two different strategies for packaging of devices for use in harsh environments and at high temperatures. The first one is a “one-sensor-one-packaging_technology” concept. The second one uses a standard flip-chip bonding technique. The first sensor is a “floating-concept”, capable of measuring pressures at temperatures up to 400 °C (constant load with an accuracy of 0.25% Full Scale Output (FSO. A push rod (mounted onto the steel membrane transfers the applied pressure directly to the center-boss membrane of the SOI-chip, which is placed on a ceramic carrier. The chip membrane is realized by Deep Reactive Ion Etching (DRIE or Bosch Process. A novel propertied chip housing employing a sliding sensor chip that is fixed during packaging by mechanical preloading via the push rod is used, thereby avoiding chip movement, and ensuring optimal push rod load transmission. The second sensor can be used up to 350 °C. The SOI chips consists of a beam with an integrated centre-boss with was realized using KOH structuring and DRIE. The SOI chip is not “floating” but bonded by using flip-chip technology. The fabricated SOI sensor chip has a bridge resistance of 3250 Ω. The realized sensor chip has a sensitivity of 18 mV/µm measured using a bridge current of 1 mA.

Advanced Liquid-Free, Piezoresistive, SOI-Based Pressure Sensors for Measurements in Harsh Environments.

Science.gov (United States)

Ngo, Ha-Duong; Mukhopadhyay, Biswaijit; Ehrmann, Oswin; Lang, Klaus-Dieter

2015-08-18

In this paper we present and discuss two innovative liquid-free SOI sensors for pressure measurements in harsh environments. The sensors are capable of measuring pressures at high temperatures. In both concepts media separation is realized using a steel membrane. The two concepts represent two different strategies for packaging of devices for use in harsh environments and at high temperatures. The first one is a "one-sensor-one-packaging_technology" concept. The second one uses a standard flip-chip bonding technique. The first sensor is a "floating-concept", capable of measuring pressures at temperatures up to 400 °C (constant load) with an accuracy of 0.25% Full Scale Output (FSO). A push rod (mounted onto the steel membrane) transfers the applied pressure directly to the center-boss membrane of the SOI-chip, which is placed on a ceramic carrier. The chip membrane is realized by Deep Reactive Ion Etching (DRIE or Bosch Process). A novel propertied chip housing employing a sliding sensor chip that is fixed during packaging by mechanical preloading via the push rod is used, thereby avoiding chip movement, and ensuring optimal push rod load transmission. The second sensor can be used up to 350 °C. The SOI chips consists of a beam with an integrated centre-boss with was realized using KOH structuring and DRIE. The SOI chip is not "floating" but bonded by using flip-chip technology. The fabricated SOI sensor chip has a bridge resistance of 3250 Ω. The realized sensor chip has a sensitivity of 18 mV/µm measured using a bridge current of 1 mA.

Harshlight: a "corrective make-up" program for microarray chips

Directory of Open Access Journals (Sweden)

Wittkowski Knut M

2005-12-01

Full Text Available Abstract Background Microscopists are familiar with many blemishes that fluorescence images can have due to dust and debris, glass flaws, uneven distribution of fluids or surface coatings, etc. Microarray scans do show similar artifacts, which might affect subsequent analysis. Although all but the starkest blemishes are hard to find by the unaided eye, particularly in high-density oligonucleotide arrays (HDONAs, few tools are available to help with the detection of those defects. Results We develop a novel tool, Harshlight, for the automatic detection and masking of blemishes in HDONA microarray chips. Harshlight uses a combination of statistic and image processing methods to identify three different types of defects: localized blemishes affecting a few probes, diffuse defects affecting larger areas, and extended defects which may invalidate an entire chip. Conclusion We demonstrate the use of Harshlight can materially improve analysis of HDONA chips, especially for experiments with subtle changes between samples. For the widely used MAS5 algorithm, we show that compact blemishes cause an average of 8 gene expression values per chip to change by more than 50%, two of them by more than twofold; our masking algorithm restores about two thirds of this damage. Large-scale artifacts are successfully detected and eliminated.

"Hook"-calibration of GeneChip-microarrays: Chip characteristics and expression measures

Directory of Open Access Journals (Sweden)

Krohn Knut

2008-08-01

Full Text Available Abstract Background Microarray experiments rely on several critical steps that may introduce biases and uncertainty in downstream analyses. These steps include mRNA sample extraction, amplification and labelling, hybridization, and scanning causing chip-specific systematic variations on the raw intensity level. Also the chosen array-type and the up-to-dateness of the genomic information probed on the chip affect the quality of the expression measures. In the accompanying publication we presented theory and algorithm of the so-called hook method which aims at correcting expression data for systematic biases using a series of new chip characteristics. Results In this publication we summarize the essential chip characteristics provided by this method, analyze special benchmark experiments to estimate transcript related expression measures and illustrate the potency of the method to detect and to quantify the quality of a particular hybridization. It is shown that our single-chip approach provides expression measures responding linearly on changes of the transcript concentration over three orders of magnitude. In addition, the method calculates a detection call judging the relation between the signal and the detection limit of the particular measurement. The performance of the method in the context of different chip generations and probe set assignments is illustrated. The hook method characterizes the RNA-quality in terms of the 3'/5'-amplification bias and the sample-specific calling rate. We show that the proper judgement of these effects requires the disentanglement of non-specific and specific hybridization which, otherwise, can lead to misinterpretations of expression changes. The consequences of modifying probe/target interactions by either changing the labelling protocol or by substituting RNA by DNA targets are demonstrated. Conclusion The single-chip based hook-method provides accurate expression estimates and chip-summary characteristics

Pixel detector readout chip

CERN Multimedia

1991-01-01

Close-up of a pixel detector readout chip. The photograph shows an aera of 1 mm x 2 mm containing 12 separate readout channels. The entire chip contains 1000 readout channels (around 80 000 transistors) covering a sensitive area of 8 mm x 5 mm. The chip has been mounted on a silicon detector to detect high energy particles.

Package performance evaluation: our latest 30-year experience

International Nuclear Information System (INIS)

Malesys, Pierre; Gagner, Laurent

2006-01-01

Packages for the transport of radioactive material have to comply with national and / or international regulations. These regulations are widely based on the requirements set forth by the International Atomic Energy Agency (IAEA) in the 'Regulations for the Safe Transport of Radioactive Material'. The packages designed to transport the most demanding contents are submitted to tests for demonstrating their ability to withstand accident conditions of transport. These tests are typically: - a nine-meter drop onto a flat and unyielding surface, - a one-meter drop onto a punch, - a 800 deg. C / 30 minutes fire, and an immersion under a head of water of either 0.9 m, or 15 m or 200 m (depending of the criteria to be considered). During the last 20 years, on several of its package designs, COGEMA LOGISTICS has performed tests and analyses to simulate extremely severe accidents. These tests and analysis include: 1. long duration fire test and deep immersion test on a package designed to transport plutonium oxide powder; - 2. deep immersion tests on scale model of packages designed to transport spent fuel, high level vitrified waste and fresh MOX (uranium and plutonium mixed oxide) fuel; - 3. burial in a soft ground of packages designed to transport spent fuel; - 4. numerical study of the thermal behaviour of packages designed to transport spent fuel and high level vitrified waste; - 5. aircraft crash test on scale models of dual-purpose packages for the transport and storage of spent fuel. The paper will: - review the tests and analysis which were performed; - show that our designs are able to withstand extremely severe conditions; - demonstrate that there is no cliff effect: should a failure occurs, it appears gradually and there is no sudden collapse of the package; - explain how compliance with all the regulatory requirements lead to high performances regarding each of them (for instance, in many cases, the need to meet radiation exposure criteria induces a mechanical

Packagings in the silicon era

International Nuclear Information System (INIS)

Beone, G.; Mione, A.; Orsini, A.; Forasassi, G.

1993-01-01

ENEA is studying, with the collaboration of the DCMN of the Pisa University, a new packaging to collect wastes in various facilities while proceeding to find a final disposal. Following a survey on the wastes that could be transported in the future, it was agreed to design a packaging able to contain an industrial drum, with a maximum capacity of 220 litres and a total weight less than 4000 N, previously filled with solid wastes in bulk or in a solid binding material. The packaging, to be approved as a Type B in agreement with the IAEA Regulations, will be useful to transport not only radioactive wastes but any kind of dangerous goods and also those not in agreement with the UNO Regulations. The 1/2 scale model of the packaging is formed by two concentric vessels of mild steel obtained by welding commercial shells to cylindrical walls and joined through a flange. The new packaging under development presents features that seem to be proper for its envisaged waste collection main use such as construction simplicity, relatively low cost, time and use endurance, low maintenance requirements. The design analysis and testing program ongoing at present allowed for the preliminary definition of the packaging geometry and confirmed the necessity of further investigations in some key areas as the determination of actual behaviour of the silicon foam, used as energy absorbing/thermal insulating material, in the specific conditions of interest. (J.P.N.)

Addressing On-Chip Power Converstion and Dissipation Issues in Many-Core System-on-a-Chip Based on Conventional Silicon and Emerging Nanotechnologies

Science.gov (United States)

Ashenafi, Emeshaw

Integrated circuits (ICs) are moving towards system-on-a-chip (SOC) designs. SOC allows various small and large electronic systems to be implemented in a single chip. This approach enables the miniaturization of design blocks that leads to high density transistor integration, faster response time, and lower fabrication costs. To reap the benefits of SOC and uphold the miniaturization of transistors, innovative power delivery and power dissipation management schemes are paramount. This dissertation focuses on on-chip integration of power delivery systems and managing power dissipation to increase the lifetime of energy storage elements. We explore this problem from two different angels: On-chip voltage regulators and power gating techniques. On-chip voltage regulators reduce parasitic effects, and allow faster and efficient power delivery for microprocessors. Power gating techniques, on the other hand, reduce the power loss incurred by circuit blocks during standby mode. Power dissipation (Ptotal = Pstatic and Pdynamic) in a complementary metal-oxide semiconductor (CMOS) circuit comes from two sources: static and dynamic. A quadratic dependency on the dynamic switching power and a more than linear dependency on static power as a form of gate leakage (subthreshold current) exist. To reduce dynamic power loss, the supply power should be reduced. A significant reduction in power dissipation occurs when portions of a microprocessor operate at a lower voltage level. This reduction in supply voltage is achieved via voltage regulators or converters. Voltage regulators are used to provide a stable power supply to the microprocessor. The conventional off-chip switching voltage regulator contains a passive floating inductor, which is difficult to be implemented inside the chip due to excessive power dissipation and parasitic effects. Additionally, the inductor takes a very large chip area while hampering the scaling process. These limitations make passive inductor based on-chip

fast minimization on the xiao map using row group structure rules

African Journals Online (AJOL)

user

1989-09-01

Sep 1, 1989 ... insignificant thereby changing the focus of digital design from gate minimization to package or chip minmisation [1]. Gate level minimization still remains relevant despite the advent of large scale integrated circuit (LSI) and very large scale integrated circuit. (VLSI). For example, map entered variable.

Production of dry wood chips in connection with a district heating plant

Directory of Open Access Journals (Sweden)

Yrjölä Jukka

2004-01-01

Full Text Available Moisture and its variation in wood chips make the control of burning in small scale heating appliances difficult resulting in emissions and loss of efficiency. If the quality of wood chips would be better, i. e. dried and sieved fuel with more uniform size distribution would be avail able, the burning could be much cleaner and efficiency higher. In addition higher power out put could be obtained and the investment costs of the burning appliances would be lower. The production of sieved and dried wood chip with good quality could be accomplished in connection with a district heating plant. Then the plant would make profit, in addition to the district heat, from the dried wood chips sold to the neighboring buildings and enterprises sep a rated from the district heating net using wood chips in energy production. The peak power of a district heating plant is required only a short time during the coldest days of the winter. Then the excess capacity during the milder days can be used as heat source for drying of wood chips to be marketed. Then wood chips are sieved and the fuel with best quality is sold and the reject is used as fuel in the plant it self. In a larger district heating plant, quality of the fuel does not need to be so high In this paper the effect of moisture on the fuel chain and on the boiler is discussed. Energy and mass balance calculations as a tool of system design is described and the characteristics of proposed dry chips production method is discussed.

The impact of CHIP premium increases on insurance outcomes among CHIP eligible children.

Science.gov (United States)

Nikolova, Silviya; Stearns, Sally

2014-03-03

Within the United States, public insurance premiums are used both to discourage private health policy holders from dropping coverage and to reduce state budget costs. Prior research suggests that the odds of having private coverage and being uninsured increase with increases in public insurance premiums. The aim of this paper is to test effects of Children's Health Insurance Program (CHIP) premium increases on public insurance, private insurance, and uninsurance rates. The fact that families just below and above a state-specific income cut-off are likely very similar in terms of observable and unobservable characteristics except the premium contribution provides a natural experiment for estimating the effect of premium increases. Using 2003 Medical Expenditure Panel Survey (MEPS) merged with CHIP premiums, we compare health insurance outcomes for CHIP eligible children as of January 2003 in states with a two-tier premium structure using a cross-sectional regression discontinuity methodology. We use difference-in-differences analysis to compare longitudinal insurance outcomes by December 2003. Higher CHIP premiums are associated with higher likelihood of private insurance. Disenrollment from CHIP in response to premium increases over time does not increase the uninsurance rate. When faced with higher CHIP premiums, private health insurance may be a preferable alternative for CHIP eligible families with higher incomes. Therefore, competition in the insurance exchanges being formed under the Affordable Care Act could enhance choice.

UW VLSI chip tester

Science.gov (United States)

McKenzie, Neil

1989-12-01

We present a design for a low-cost, functional VLSI chip tester. It is based on the Apple MacIntosh II personal computer. It tests chips that have up to 128 pins. All pin drivers of the tester are bidirectional; each pin is programmed independently as an input or an output. The tester can test both static and dynamic chips. Rudimentary speed testing is provided. Chips are tested by executing C programs written by the user. A software library is provided for program development. Tests run under both the Mac Operating System and A/UX. The design is implemented using Xilinx Logic Cell Arrays. Price/performance tradeoffs are discussed.

Nanotechnology: An Untapped Resource for Food Packaging.

Science.gov (United States)

Sharma, Chetan; Dhiman, Romika; Rokana, Namita; Panwar, Harsh

2017-01-01

Food commodities are packaged and hygienically transported to protect and preserve them from any un-acceptable alteration in quality, before reaching the end-consumer. Food packaging continues to evolve along-with the innovations in material science and technology, as well as in light of consumer's demand. Presently, the modern consumers of competitive economies demands for food with natural quality, assured safety, minimal processing, extended shelf-life and ready-to-eat concept. Innovative packaging systems, not only ascertains transit preservation and effective distribution, but also facilitates communication at the consumer levels. The technological advances in the domain of food packaging in twenty-first century are mainly chaired by nanotechnology, the science of nano-materials. Nanotechnology manipulates and creates nanometer scale materials, of commercial and scientific relevance. Introduction of nanotechnology in food packaging sector has significantly addressed the food quality, safety and stability concerns. Besides, nanotechnology based packaging intimate's consumers about the real time quality of food product. Additionally, nanotechnology has been explored for controlled release of preservatives/antimicrobials, extending the product shelf life within the package. The promising reports for nanotechnology interventions in food packaging have established this as an independent priority research area. Nanoparticles based food packages offer improved barrier and mechanical properties, along with food preservation and have gained welcoming response from market and end users. In contrary, recent advances and up-liftment in this area have raised various ethical, environmental and safety concerns. Policies and regulation regarding nanoparticles incorporation in food packaging are being reviewed. This review presents the existing knowledge, recent advances, concerns and future applications of nanotechnology in food packaging sector.

Cache-aware network-on-chip for chip multiprocessors

Science.gov (United States)

Tatas, Konstantinos; Kyriacou, Costas; Dekoulis, George; Demetriou, Demetris; Avraam, Costas; Christou, Anastasia

2009-05-01

This paper presents the hardware prototype of a Network-on-Chip (NoC) for a chip multiprocessor that provides support for cache coherence, cache prefetching and cache-aware thread scheduling. A NoC with support to these cache related mechanisms can assist in improving systems performance by reducing the cache miss ratio. The presented multi-core system employs the Data-Driven Multithreading (DDM) model of execution. In DDM thread scheduling is done according to data availability, thus the system is aware of the threads to be executed in the near future. This characteristic of the DDM model allows for cache aware thread scheduling and cache prefetching. The NoC prototype is a crossbar switch with output buffering that can support a cache-aware 4-node chip multiprocessor. The prototype is built on the Xilinx ML506 board equipped with a Xilinx Virtex-5 FPGA.

Experiment list: SRX122496 [Chip-atlas[Archive

Lifescience Database Archive (English)

Full Text Available || chip antibody=Rel || treatment=LPS || time=120 min || chip antibody manufacturer 1=Santa Cruz || chip ant...ibody catalog number 1=sc-71 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc

Smart vision chips: An overview

Science.gov (United States)

Koch, Christof

1994-01-01

This viewgraph presentation presents four working analog VLSI vision chips: (1) time-derivative retina, (2) zero-crossing chip, (3) resistive fuse, and (4) figure-ground chip; work in progress on computing motion and neuromorphic systems; and conceptual and practical lessons learned.

Experiment list: SRX122465 [Chip-atlas[Archive

Lifescience Database Archive (English)

Full Text Available 6 || chip antibody=Relb || treatment=LPS || time=120 min || chip antibody manufacturer 1=Bethyl || chip anti...body catalog number 1=A302-183A || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2

Experiment list: SRX122555 [Chip-atlas[Archive

Lifescience Database Archive (English)

Full Text Available chip antibody=Stat1 || treatment=LPS || time=120 min || chip antibody manufacturer 1=Santa Cruz || chip anti...body catalog number 1=sc-346 || chip antibody manufacturer 2=Bethyl || chip antibody catalog number 2=A302-7

Calculating with light using a chip-scale all-optical abacus.

Science.gov (United States)

Feldmann, J; Stegmaier, M; Gruhler, N; Ríos, C; Bhaskaran, H; Wright, C D; Pernice, W H P

2017-11-02

Machines that simultaneously process and store multistate data at one and the same location can provide a new class of fast, powerful and efficient general-purpose computers. We demonstrate the central element of an all-optical calculator, a photonic abacus, which provides multistate compute-and-store operation by integrating functional phase-change materials with nanophotonic chips. With picosecond optical pulses we perform the fundamental arithmetic operations of addition, subtraction, multiplication, and division, including a carryover into multiple cells. This basic processing unit is embedded into a scalable phase-change photonic network and addressed optically through a two-pulse random access scheme. Our framework provides first steps towards light-based non-von Neumann arithmetic.

On-chip digital power supply control for system-on-chip applications

NARCIS (Netherlands)

Meijer, M.; Pineda de Gyvez, J.; Otten, R.H.J.M.

2005-01-01

The authors presented an on-chip, fully-digital, power-supply control system. The scheme consists of two independent control loops that regulate power supply variations due to semiconductor process spread, temperature, and chip's workload. Smart power-switches working as linear voltage regulators

Collective Memory Transfers for Multi-Core Chips

Energy Technology Data Exchange (ETDEWEB)

Michelogiannakis, George; Williams, Alexander; Shalf, John

2013-11-13

Future performance improvements for microprocessors have shifted from clock frequency scaling towards increases in on-chip parallelism. Performance improvements for a wide variety of parallel applications require domain-decomposition of data arrays from a contiguous arrangement in memory to a tiled layout for on-chip L1 data caches and scratchpads. How- ever, DRAM performance suffers under the non-streaming access patterns generated by many independent cores. We propose collective memory scheduling (CMS) that actively takes control of collective memory transfers such that requests arrive in a sequential and predictable fashion to the memory controller. CMS uses the hierarchically tiled arrays formal- ism to compactly express collective operations, which greatly improves programmability over conventional prefetch or list- DMA approaches. CMS reduces application execution time by up to 32% and DRAM read power by 2.2×, compared to a baseline DMA architecture such as STI Cell.

Radiation-induced effects on the XAA1.2 ASIC chip for space application

Energy Technology Data Exchange (ETDEWEB)

Del Monte, Ettore [Istituto di Astrofisica Spaziale e Fisica Cosmica, CNR, Roma, Via Fosso del Cavaliere 100, I-00133 Rome (Italy) and Dipartimento di Fisica, Universita di Roma ' Tor Vergata' , Via della Ricerca Scientifica 1, I-00133 Rome (Italy)]. E-mail: delmonte@rm.iasf.cnr.it; Pacciani, Luigi [Istituto di Astrofisica Spaziale e Fisica Cosmica, CNR, Roma, Via Fosso del Cavaliere 100, I-00133 Rome (Italy); Porrovecchio, Geiland [Istituto di Astrofisica Spaziale e Fisica Cosmica, CNR, Roma, Via Fosso del Cavaliere 100, I-00133 Rome (Italy); Soffitta, Paolo [Istituto di Astrofisica Spaziale e Fisica Cosmica, CNR, Roma, Via Fosso del Cavaliere 100, I-00133 Rome (Italy); Costa, Enrico [Istituto di Astrofisica Spaziale e Fisica Cosmica, CNR, Roma, Via Fosso del Cavaliere 100, I-00133 Rome (Italy); Di Persio, Giuseppe [Istituto di Astrofisica Spaziale e Fisica Cosmica, CNR, Roma, Via Fosso del Cavaliere 100, I-00133 Rome (Italy); Feroci, Marco [Istituto di Astrofisica Spaziale e Fisica Cosmica, CNR, Roma, Via Fosso del Cavaliere 100, I-00133 Rome (Italy); Mastropietro, Marcello [Istituto di Metodologie Inorganiche e dei Plasmi, CNR, Roma, Via Salaria km 29.300, I-00016 Monterotondo Scalo (RM) c.p. 10 (Italy); Morelli, Ennio [Istituto di Astrofisica Spaziale e Fisica Cosmica, CNR, Bologna, Via P. Gobetti 101, I-40129 Bologna (Italy); Rapisarda, Massimo [ENEA C.R. Frascati, Via Enrico Fermi 45, I-00044 Frascati, RM (Italy); Rubini, Alda [Istituto di Astrofisica Spaziale e Fisica Cosmica, CNR, Roma, Via Fosso del Cavaliere 100, I-00133 Rome (Italy); Bisello, Dario; Candelori, Andrea [Dipartimento di Fisica, Universita di Padova, INFN Sezione di Padova, Via Marzolo 8, I-35100 Padova (Italy); Kaminski, Alexandre [Dipartimento di Fisica, Universita di Padova, INFN Sezione di Padova, Via Marzolo 8, I-35100 Padova (Italy); Wyss, Jeffery [DIMSAT, Universita di Cassino, Via Di Biasio 43, I-03043 Cassino, FR (Italy)

2005-02-11

The XAA1.2 is a custom ASIC chip for space applications built using a 0.8{mu}m complementary metal oxide semiconductor technology on epitaxial layer. It has been selected as the front-end electronics chip of the SuperAGILE experiment on board the AGILE space mission, although it is not specifically designed as a radiation hard device. To study the XAA1.2 sensitivity to Single Event Effects and Total Dose Effects we irradiate this chip at the SIRAD facility of the Laboratori Nazionali INFN of Legnaro. In this paper we describe the experimental set-up and the measurements. We then discuss how the results can be scaled to the cosmic rays environment in a low-Earth orbit.

Multifrequency Excitation Method for Rapid and Accurate Dynamic Test of Micromachined Gyroscope Chips

Directory of Open Access Journals (Sweden)

Yan Deng

2014-10-01

Full Text Available A novel multifrequency excitation (MFE method is proposed to realize rapid and accurate dynamic testing of micromachined gyroscope chips. Compared with the traditional sweep-frequency excitation (SFE method, the computational time for testing one chip under four modes at a 1-Hz frequency resolution and 600-Hz bandwidth was dramatically reduced from 10 min to 6 s. A multifrequency signal with an equal amplitude and initial linear-phase-difference distribution was generated to ensure test repeatability and accuracy. The current test system based on LabVIEW using the SFE method was modified to use the MFE method without any hardware changes. The experimental results verified that the MFE method can be an ideal solution for large-scale dynamic testing of gyroscope chips and gyroscopes.

Radiation-induced effects on the XAA1.2 ASIC chip for space application

International Nuclear Information System (INIS)

Del Monte, Ettore; Pacciani, Luigi; Porrovecchio, Geiland; Soffitta, Paolo; Costa, Enrico; Di Persio, Giuseppe; Feroci, Marco; Mastropietro, Marcello; Morelli, Ennio; Rapisarda, Massimo; Rubini, Alda; Bisello, Dario; Candelori, Andrea; Kaminski, Alexandre; Wyss, Jeffery

2005-01-01

The XAA1.2 is a custom ASIC chip for space applications built using a 0.8μm complementary metal oxide semiconductor technology on epitaxial layer. It has been selected as the front-end electronics chip of the SuperAGILE experiment on board the AGILE space mission, although it is not specifically designed as a radiation hard device. To study the XAA1.2 sensitivity to Single Event Effects and Total Dose Effects we irradiate this chip at the SIRAD facility of the Laboratori Nazionali INFN of Legnaro. In this paper we describe the experimental set-up and the measurements. We then discuss how the results can be scaled to the cosmic rays environment in a low-Earth orbit

Photonic packaging sourcebook fiber-chip coupling for optical components, basic calculations, modules

CERN Document Server

Fischer-Hirchert, Ulrich H P

2015-01-01

This book serves as a guide on photonic assembly techniques. It provides an overview of today's state-of-the-art technologies for photonic packaging experts and professionals in the field. The text guides the readers to the practical use of optical connectors. It also assists engineers to find a way to an effective and inexpensive set-up for their own needs. In addition, many types of current industrial modules and state-of-the-art applications from single fiber to multi fiber are described in detail. Simulation techniques such as FEM, BPM and ray tracing are explained in depth. Finally, all recent reliability test procedures for datacom and telecom modules are illustrated in combination with related standardization aspects.

Review of criticality safety and shielding analysis issues for transportation packages

International Nuclear Information System (INIS)

Parks, C.V.; Broadhead, B.L.

1995-01-01

The staff of the Nuclear Engineering Applications Section (NEAS) at Oak Ridge National Laboratory (ORNL) have been involved for over 25 years with the development and application of computational tools for use in analyzing the criticality safety and shielding features of transportation packages carrying radioactive material (RAM). The majority of the computational tools developed by ORNL/NEAS have been included within the SCALE modular code system (SCALE 1995). This code system has been used throughout the world for the evaluation of nuclear facility and package designs. With this development and application experience as a basis, this paper highlights a number of criticality safety and shielding analysis issues that confront the designer and reviewer of a new RAM package. Changes in the types and quantities of material that need to be shipped will keep these issues before the technical community and provide challenges to future package design and certification

Supply chains of forest chip production in Finland

Energy Technology Data Exchange (ETDEWEB)

Kaerhae, Kalle (Metsaeteho Oy, Helsinki (Finland)), e-mail: kalle.karha@metsateho.fi

2010-07-15

The Metsaeteho study investigated how logging residue chips, stump wood chips, and chips from small sized thinning wood and large-sized (rotten) roundwood used by heating and power plants were produced in Finland in 2008. Almost all the major forest chip suppliers in Finland were involved in the study. The total volume of forest chips supplied in 2008 by these suppliers was 6.5 TWh. The study was implemented by conducting an e-mail questionnaire survey and telephone interviews. Research data was collected in March-May 2009. The majority of the logging residue chips and chips from small-sized thinning wood were produced using the roadside chipping supply chain in Finland in 2008. The chipping at plant supply chain was also significant in the production of logging residue chips. 70% of all stump wood chips consumed were comminuted at the plant and 29% at terminals. The role of the terminal chipping supply chain was also significant in the production of chips from logging residues and small-sized wood chips. When producing chips from large-sized (rotten) roundwood, nearly a half of chips were comminuted at plants and more than 40% at terminals

Supply systems of forest chip production in Finland

Energy Technology Data Exchange (ETDEWEB)

Kaerhae, K. (Metsaeteho Oy, Helsinki (Finland)), e-mail: kalle.karha@metsateho.fi

2010-07-01

The Metsaeteho study investigated how logging residue chips, stump wood chips, and chips from small-diameter thinning wood and large-sized (rotten) roundwood used by heating and power plants were produced in Finland in 2009. Almost all the major forest chip suppliers in Finland were involved in the study. The total volume of forest chips supplied in 2009 by these suppliers was 8,4 TWh. The study was implemented by conducting an e-mail questionnaire survey and telephone interviews. Research data was collected from March-May, 2010. The majority of the logging residue chips and chips from small-diameter thinning wood were produced using the roadside chipping supply system in Finland in 2009. The chipping at plant supply system was also significant in the production of logging residue chips. Nearly 70 % of all stump wood chips consumed were comminuted at the plant and 28 % at terminals. The role of the terminal chipping supply system was also significant in the production of chips from logging residues and small-diameter wood chips. When producing chips from large-sized (rotten) roundwood, similarly roughly 70 % of chips were comminuted at plants and 23 % at terminals. (orig.)

Supply chains of forest chip production in Finland

Energy Technology Data Exchange (ETDEWEB)

Kaerhae, K. (Metsaeteho Oy, Helsinki (Finland)), Email: kalle.karha@metsateho.fi

2009-07-01

The Metsaeteho study investigated how logging residue chips. stump wood chips, and chips from small-sized thinning wood and large-sized (rotten) roundwood used by heating and power plants were produced in Finland in 2008. Almost all the major forest chip suppliers in Finland were involved in the study. The total volume of forest chips supplied in 2008 by these suppliers was 6,5 TWh. The study was implemented by conducting an e-mail questionnaire survey and telephone interviews. Research data was collected in March-May 2009. The majority of the logging residue chips and chips from small-sized thinning wood were produced using the roadside chipping supply chain in Finland in 2008. The chipping at plant supply chain was also significant in the production of logging residue chips. 70% of all stump wood chips consumed were comminuted at the plant and 29% at terminals. The role of the terminal chipping supply chain was also significant in the production of chips from logging residues and small-sized wood chips. When producing chips from large-sized (rotten) roundwood, nearly a half of chips were comminuted at plants and more than 40 % at terminals. (orig.)

arXiv Characterization and Verification Environment for the RD53A Pixel Readout Chip in 65 nm CMOS

CERN Document Server

Vogt, M.; Hemperek, T.; Janssen, J.; Pohl, D.L.; Daas, M.

2018-02-02

The RD53 collaboration is currently designing a large scale prototype pixel readout chip in 65 nm CMOS technology for the phase 2 upgrades at the HL-LHC. The RD53A chip will be available by the end of the year 2017 and will be extensively tested to confirm if the circuit and the architecture make a solid foundation for the final pixel readout chips for the experiments at the HL-LHC. A test and data acquisition system for the RD53A chip is currently under development to perform single-chip and multi-chip module measurements. In addition, the verification of the RD53A design is performed in a dedicated simulation environment. The concept and the implementation of the test and data acquisition system and the simulation environment, which are based on a modular data acquisition and system testing framework, are presented in this work.

Destructive testing of transport packaging. Quality assurance applied to transport packaging in the USA

International Nuclear Information System (INIS)

Barker, R.F.

1976-01-01

This paper discusses several aspects of quality assurance as applied to packaging, including such requirements for an adequate quality assurance program as assignment of responsibilities, inspections, and audits. In certain cases, we have determined the margin of safety inherent in specific package designs. Testing of packaging to destruction, by subjecting it to conditions far beyond the present accident criteria, was carried out to establish the levels of impact, puncture, crush, and fire at which present designs would fail. A second area in which the Nuclear Regulatory Commission has applied quality assurance is qualification testing. The standards for testing prototypes require essentially no loss of contents under the specified accident test conditions. Qualifying a design with an acceptable degree of reliability by testing it at the specified stress levels with no measurable effect requires large numbers of samples to be tested. Testing the prototype under conditions well above the criteria is shown to offer one of the most effective means of demonstrating the adequacy of a design. Scenario tests, i.e., staged accidents or full-scale tests in which vehicles with samples of packages on board are crashed under specified conditions, in most cases present singular points on a curve. One-point tests in most cases will disprove a package design if it fails but may not confirm that a design will not fail. At the same time, much information and some public assurances can be obtained from such tests. (author)

Safety Analysis Report - Packages, 9965, 9968, 9972-9975 Packages

International Nuclear Information System (INIS)

Blanton, P.

2000-01-01

This Safety Analysis Report for Packaging (SARP) documents the analysis and testing performed on four type B Packages: the 9972, 9973, 9974, and 9975 packages. Because all four packages have similar designs with very similar performance characteristics, all of them are presented in a single SARP. The performance evaluation presented in this SARP documents the compliance of the 9975 package with the regulatory safety requirements. Evaluations of the 9972, 9973, and 9974 packages support that of the 9975. To avoid confusion arising from the inclusion of four packages in a single document, the text segregates the data for each package in such a way that the reader interested in only one package can progress from Chapter 1 through Chapter 9. The directory at the beginning of each chapter identifies each section that should be read for a given package. Sections marked ''all'' are generic to all packages

Production, Cost and Chip Characteristics of In-Woods Microchipping

Science.gov (United States)

J. Thompson; W. Sprinkle

2013-01-01

Emerging markets for biomass have increased the interest in producing microchips in the field. As a component of a large United States Department of Energy (DOE) funded project, microchipping has been trialed on a limited scale. The goal of the research was to evaluate the production, cost and chip characteristics of a mobile disc chipper configured to produce...

Single chip camera active pixel sensor

Science.gov (United States)

Shaw, Timothy (Inventor); Pain, Bedabrata (Inventor); Olson, Brita (Inventor); Nixon, Robert H. (Inventor); Fossum, Eric R. (Inventor); Panicacci, Roger A. (Inventor); Mansoorian, Barmak (Inventor)

2003-01-01

A totally digital single chip camera includes communications to operate most of its structure in serial communication mode. The digital single chip camera include a D/A converter for converting an input digital word into an analog reference signal. The chip includes all of the necessary circuitry for operating the chip using a single pin.

Nanophotonic lab-on-a-chip platforms including novel bimodal interferometers, microfluidics and grating couplers.

Science.gov (United States)

Duval, Daphné; González-Guerrero, Ana Belén; Dante, Stefania; Osmond, Johann; Monge, Rosa; Fernández, Luis J; Zinoviev, Kirill E; Domínguez, Carlos; Lechuga, Laura M

2012-05-08

One of the main limitations for achieving truly lab-on-a-chip (LOC) devices for point-of-care diagnosis is the incorporation of the "on-chip" detection. Indeed, most of the state-of-the-art LOC devices usually require complex read-out instrumentation, losing the main advantages of portability and simplicity. In this context, we present our last advances towards the achievement of a portable and label-free LOC platform with highly sensitive "on-chip" detection by using nanophotonic biosensors. Bimodal waveguide interferometers fabricated by standard silicon processes have been integrated with sub-micronic grating couplers for efficient light in-coupling, showing a phase resolution of 6.6 × 10(-4)× 2π rad and a limit of detection of 3.3 × 10(-7) refractive index unit (RIU) in bulk. A 3D network of SU-8 polymer microfluidics monolithically assembled at the wafer-level was included, ensuring perfect sealing and compact packaging. To overcome some of the drawbacks inherent to interferometric read-outs, a novel all-optical wavelength modulation system has been implemented, providing a linear response and a direct read-out of the phase variation. Sensitivity, specificity and reproducibility of the wavelength modulated BiMW sensor has been demonstrated through the label-free immunodetection of the human hormone hTSH at picomolar level using a reliable biofunctionalization process.

From lab-on-a-chip to lab-in-a-cell

NARCIS (Netherlands)

Andersson, Helene; van den Berg, Albert

2005-01-01

There are many efforts today trying to mimic the properties of single cells in order to design chips that are as efficient as cells. However, cells are nature"s nanotechnology engineering at the scale of atoms and molecules. Therefore, it might be better to vision a microchip that utilizes a single

Adjunctive Effects of A Piscean Collagen-Based Controlled-Release Chlorhexidine Chip in the Treatment of Chronic Periodontitis: A Clinical and Microbiological Study

Science.gov (United States)

John, Priya; Lazarus, Flemingson; Selvam, Arul; Prabhuji, Munivenkatappa Lakshmaiah Venkatesh

2015-01-01

Introduction PerioChip a bovine origin gelatine based CHX chip has shown beneficial effects in the management of Chronic Periodontitis. A new fish collagen based CHX chip similar to PerioChip is currently available; however this product has not been thoroughly researched. Aim The aim of the present study was to evaluate the effectiveness of a new Piscean collagen-based controlled-release chlorhexidine chip (CHX chip) as an adjunctive therapy to scaling and root planing (SRP). Settings and Design The study was conducted as a randomised, split-mouth, controlled clinical trial at Krishnadevaraya College of Dental Sciences, Bangalore, India. Materials and Methods In a split–mouth study involving 20 sites in 10 patients with chronic periodontitis, control sites received scaling and root planing and test sites received scaling and root planing (SRP) and the intrapocket CHX chip placement as an adjunct. Subgingival plaque samples were collected from both control and test sites at baseline, 11 days and 11 weeks and the anaerobic colony count were assessed. Clinical parameters that were recorded at baseline and 11 weeks were gingival index, Plaque index, Probing pocket depth (PPD), and Clinical attachment level (CAL). Plaque index was recorded additionally at 11 days. Results In the test group there was a statistically significant reduction in the total anaerobic colony count, gingival index and plaque scores from baseline as compared to control sites at all time intervals. An additional 0.8mm reduction in mean probing pocket depth was noted in the test group. Gain in Clinical attachment level was comparable in both groups. Conclusion The adjunctive use of the new collagen-based CHX chip yielded significant antimicrobial benefit accompanied by a reduction in probing depth and a clinical attachment level gain as compared to SRP alone. This suggests that it may be a useful treatment option of nonsurgical periodontal treatment of chronic periodontitis. PMID:26155567

Ultra-thin chip technology and applications

CERN Document Server

2010-01-01

Ultra-thin chips are the "smart skin" of a conventional silicon chip. This book shows how very thin and flexible chips can be fabricated and used in many new applications in microelectronics, microsystems, biomedical and other fields. It provides a comprehensive reference to the fabrication technology, post processing, characterization and the applications of ultra-thin chips.

Machinery and labour force requirements for forest chip production in Finland in 2020

Energy Technology Data Exchange (ETDEWEB)

Kaerhae, K.; Strandsroem, M. (Metsaeteho Oy, Helsinki (Finland)), Email: kalle.karha@metsateho.fi, Email: markus.strandstrom@metsateho.fi; Lahtinen, P.; Elo, J. (Poeyry Energy Oy, Espoo (Finland)), Email: perttu.lahtinen@poyry.com, Email: juha.elo@poyry.com

2009-07-01

The research carried out by Metsaeteho Oy and Poeyry Energy Oy estimated how much machinery and labour would be needed for large-scale forest chip production if the use of forest chips increases extensively in Finland during the coming decade. If the production and consumption of forest chips are 25 to 30 TWh in Finland 2020, then 1,900 to 2,200 machinery units, i.e. machines and trucks, would be needed. This would mean total investments in production machinery of 530 to 630 million euro (VAT 0 %). The labour demand would be 3,400 to 4,000 machine operators and drivers, and 4,200 to 5,100 labour years including indirect labour. Respectively, if the production and consumption of forest chips is 15 to 20 TWh in Finland in 2020, then the production machinery requirement would be 1,100 to 1,500 machines and trucks. The total machinery investment cost would be 320 to 420 million euro (VAT 0 %) and the calculated labour demand 2,000 to 2,700 machine operators and drivers (2,500 to 3,400 labour years). The results of the study indicated that forest chip production resources will be a major bottleneck in reaching the consumption target of 12 million m3, i.e. around 24 TWh of forest chips in Finland by 2020. (orig.)

Accelerated thermal and mechanical testing of CSP assemblies

Science.gov (United States)

Ghaffarian, R.

2000-01-01

Chip Scale Packages (CSP) are now widely used for many electronic applications including portable and telecommunication products. A test vehicle (TV-1) with eleven package types and pitches was built and tested by the JPL MicrotypeBGA Consortium during 1997 to 1999. Lessons learned by the team were published as a guidelines document for industry use. The finer pitch CSP packages which recently became available were indluded in the next test vehicle of the JPL CSP Consortium.

Photonic network-on-chip design

CERN Document Server

Bergman, Keren; Biberman, Aleksandr; Chan, Johnnie; Hendry, Gilbert

2013-01-01

This book provides a comprehensive synthesis of the theory and practice of photonic devices for networks-on-chip. It outlines the issues in designing photonic network-on-chip architectures for future many-core high performance chip multiprocessors. The discussion is built from the bottom up: starting with the design and implementation of key photonic devices and building blocks, reviewing networking and network-on-chip theory and existing research, and finishing with describing various architectures, their characteristics, and the impact they will have on a computing system. After acquainting

Solid state silicon based condenser microphone for hearing aid, has transducer chip and IC chip between intermediate chip and openings on both sides of intermediate chip, to allow sound towards diaphragm

DEFF Research Database (Denmark)

2000-01-01

towards diaphragm. Surface of the chip (2) has electrical conductors (14) to connect chip with IC chip (3). USE - For use in miniature electroacoustic devices such as hearing aid. ADVANTAGE - Since sound inlet is covered by filter, dust, moisture and other impurities do not obstruct interior and sound...... inlet of microphone. External electrical connection can be made economically reliable and the thermal stress is avoided with the small size solid state silicon based condenser microphone....

Experiment list: SRX214086 [Chip-atlas[Archive

Lifescience Database Archive (English)

Full Text Available entiated || cell line=KH2 || chip antibody 1=none || chip antibody manufacturer 1=none || chip antibody 2=none || chip antibody manuf...acturer 2=none http://dbarchive.biosciencedbc.jp/kyushu-

Optical lattice on an atom chip

DEFF Research Database (Denmark)

Gallego, D.; Hofferberth, S.; Schumm, Thorsten

2009-01-01

Optical dipole traps and atom chips are two very powerful tools for the quantum manipulation of neutral atoms. We demonstrate that both methods can be combined by creating an optical lattice potential on an atom chip. A red-detuned laser beam is retroreflected using the atom chip surface as a high......-quality mirror, generating a vertical array of purely optical oblate traps. We transfer thermal atoms from the chip into the lattice and observe cooling into the two-dimensional regime. Using a chip-generated Bose-Einstein condensate, we demonstrate coherent Bloch oscillations in the lattice....

A novel model for simulating the racing effect in capillary-driven underfill process in flip chip

Science.gov (United States)

Zhu, Wenhui; Wang, Kanglun; Wang, Yan

2018-04-01

Underfill is typically applied in flip chips to increase the reliability of the electronic packagings. In this paper, the evolution of the melt-front shape of the capillary-driven underfill flow is studied through 3D numerical analysis. Two different models, the prevailing surface force model and the capillary model based on the wetted wall boundary condition, are introduced to test their applicability, where level set method is used to track the interface of the two phase flow. The comparison between the simulation results and experimental data indicates that, the surface force model produces better prediction on the melt-front shape, especially in the central area of the flip chip. Nevertheless, the two above models cannot simulate properly the racing effect phenomenon that appears during underfill encapsulation. A novel ‘dynamic pressure boundary condition’ method is proposed based on the validated surface force model. Utilizing this approach, the racing effect phenomenon is simulated with high precision. In addition, a linear relationship is derived from this model between the flow front location at the edge of the flip chip and the filling time. Using the proposed approach, the impact of the underfill-dispensing length on the melt-front shape is also studied.

Experiment list: SRX214071 [Chip-atlas[Archive

Lifescience Database Archive (English)

Full Text Available Undifferentiated || treatment=Overexpress Sox2-V5 tagged || cell line=KH2 || chip antibody 1=none || chip antibody manufacture...r 1=none || chip antibody 2=V5 || chip antibody manufacturer 2=

Generation, transmission, and detection of terahertz photons on an electrically driven single chip

Energy Technology Data Exchange (ETDEWEB)

Ikushima, Kenji; Ito, Atsushi; Okano, Shun [Department of Applied Physics, Tokyo University of Agriculture and Technology, 2-24-16 Nakacho, Koganei, Tokyo 184-8588 (Japan)

2014-02-03

We demonstrate single photon counting of terahertz (THz) waves transmitted from a local THz point source through a coplanar two-wire waveguide on a GaAs/AlGaAs single heterostructure crystal. In the electrically driven all-in-one chip, quantum Hall edge transport is used to achieve a noiseless injection current for a monochromatic point source of THz fields. The local THz fields are coupled to a coplanar two-wire metal waveguide and transmitted over a macroscopic scale greater than the wavelength (38 μm in GaAs). THz waves propagating on the waveguide are counted as individual photons by a quantum-dot single-electron transistor on the same chip. Photon counting on integrated high-frequency circuits will open the possibilities for on-chip quantum optical experiments.

Experiment list: SRX214075 [Chip-atlas[Archive

Lifescience Database Archive (English)

Full Text Available age=Undifferentiated || treatment=Overexpress Sox17EK-V5 tagged || cell line=KH2 || chip antibody 1=none || chip antibody manufacture...r 1=none || chip antibody 2=V5 || chip antibody manufacture

Experiment list: SRX214074 [Chip-atlas[Archive

Lifescience Database Archive (English)

Full Text Available ge=Undifferentiated || treatment=Overexpress Sox17EK-V5 tagged || cell line=KH2 || chip antibody 1=none || chip antibody manufacture...r 1=none || chip antibody 2=V5 || chip antibody manufacture

Experiment list: SRX214072 [Chip-atlas[Archive

Lifescience Database Archive (English)

Full Text Available e=Undifferentiated || treatment=Overexpress Sox2KE-V5 tagged || cell line=KH2 || chip antibody 1=none || chip antibody manufacture...r 1=none || chip antibody 2=V5 || chip antibody manufacture

Experiment list: SRX214067 [Chip-atlas[Archive

Lifescience Database Archive (English)

Full Text Available fferentiated || cell line=F9 || chip antibody 1=Pou5f1/Oct4 || chip antibody manufacture...r 1=Santa Cruz || chip antibody 2=none || chip antibody manufacturer 2=none http://dbarchive.bioscien

Generation of segmental chips in metal cutting modeled with the PFEM

Science.gov (United States)

Rodriguez Prieto, J. M.; Carbonell, J. M.; Cante, J. C.; Oliver, J.; Jonsén, P.

2017-09-01

The Particle Finite Element Method, a lagrangian finite element method based on a continuous Delaunay re-triangulation of the domain, is used to study machining of Ti6Al4V. In this work the method is revised and applied to study the influence of the cutting speed on the cutting force and the chip formation process. A parametric methodology for the detection and treatment of the rigid tool contact is presented. The adaptive insertion and removal of particles are developed and employed in order to sidestep the difficulties associated with mesh distortion, shear localization as well as for resolving the fine-scale features of the solution. The performance of PFEM is studied with a set of different two-dimensional orthogonal cutting tests. It is shown that, despite its Lagrangian nature, the proposed combined finite element-particle method is well suited for large deformation metal cutting problems with continuous chip and serrated chip formation.

Flexible packaging for PV modules

Science.gov (United States)

Dhere, Neelkanth G.

2008-08-01

Economic, flexible packages that provide needed level of protection to organic and some other PV cells over >25-years have not yet been developed. However, flexible packaging is essential in niche large-scale applications. Typical configuration used in flexible photovoltaic (PV) module packaging is transparent frontsheet/encapsulant/PV cells/flexible substrate. Besides flexibility of various components, the solder bonds should also be flexible and resistant to fatigue due to cyclic loading. Flexible front sheets should provide optical transparency, mechanical protection, scratch resistance, dielectric isolation, water resistance, UV stability and adhesion to encapsulant. Examples are Tefzel, Tedlar and Silicone. Dirt can get embedded in soft layers such as silicone and obscure light. Water vapor transmittance rate (WVTR) of polymer films used in the food packaging industry as moisture barriers are ~0.05 g/(m2.day) under ambient conditions. In comparison, light emitting diodes employ packaging components that have WVTR of ~10-6 g/(m2.day). WVTR of polymer sheets can be improved by coating them with dense inorganic/organic multilayers. Ethylene vinyl acetate, an amorphous copolymer used predominantly by the PV industry has very high O2 and H2O diffusivity. Quaternary carbon chains (such as acetate) in a polymer lead to cleavage and loss of adhesional strength at relatively low exposures. Reactivity of PV module components increases in presence of O2 and H2O. Adhesional strength degrades due to the breakdown of structure of polymer by reactive, free radicals formed by high-energy radiation. Free radical formation in polymers is reduced when the aromatic rings are attached at regular intervals. This paper will review flexible packaging for PV modules.

Antimicrobial food packaging: potential and pitfalls

Science.gov (United States)

Malhotra, Bhanu; Keshwani, Anu; Kharkwal, Harsha

2015-01-01

Nowadays food preservation, quality maintenance, and safety are major growing concerns of the food industry. It is evident that over time consumers’ demand for natural and safe food products with stringent regulations to prevent food-borne infectious diseases. Antimicrobial packaging which is thought to be a subset of active packaging and controlled release packaging is one such promising technology which effectively impregnates the antimicrobial into the food packaging film material and subsequently delivers it over the stipulated period of time to kill the pathogenic microorganisms affecting food products thereby increasing the shelf life to severe folds. This paper presents a picture of the recent research on antimicrobial agents that are aimed at enhancing and improving food quality and safety by reduction of pathogen growth and extension of shelf life, in a form of a comprehensive review. Examination of the available antimicrobial packaging technologies is also presented along with their significant impact on food safety. This article entails various antimicrobial agents for commercial applications, as well as the difference between the use of antimicrobials under laboratory scale and real time applications. Development of resistance amongst microorganisms is considered as a future implication of antimicrobials with an aim to come up with actual efficacies in extension of shelf life as well as reduction in bacterial growth through the upcoming and promising use of antimicrobials in food packaging for the forthcoming research down the line. PMID:26136740

Wax-bonding 3D microfluidic chips

KAUST Repository

Gong, Xiuqing; Yi, Xin; Xiao, Kang; Li, Shunbo; Kodzius, Rimantas; Qin, Jianhua; Wen, Weijia

2013-01-01

We report a simple, low-cost and detachable microfluidic chip incorporating easily accessible paper, glass slides or other polymer films as the chip materials along with adhesive wax as the recycling bonding material. We use a laser to cut through the paper or film to form patterns and then sandwich the paper and film between glass sheets or polymer membranes . The hot-melt adhesive wax can realize bridge bonding between various materials, for example, paper, polymethylmethacrylate (PMMA) film, glass sheets, or metal plate. The bonding process is reversible and the wax is reusable through a melting and cooling process. With this process, a three-dimensional (3D) microfluidic chip is achievable by vacuating and venting the chip in a hot-water bath. To study the biocompatibility and applicability of the wax-based microfluidic chip, we tested the PCR compatibility with the chip materials first. Then we applied the wax-paper based microfluidic chip to HeLa cell electroporation (EP ). Subsequently, a prototype of a 5-layer 3D chip was fabricated by multilayer wax bonding. To check the sealing ability and the durability of the chip, green fluorescence protein (GFP) recombinant Escherichia coli (E. coli) bacteria were cultured, with which the chemotaxis of E. coli was studied in order to determine the influence of antibiotic ciprofloxacin concentration on the E. coli migration.

Wax-bonding 3D microfluidic chips

KAUST Repository

Gong, Xiuqing

2013-10-10

We report a simple, low-cost and detachable microfluidic chip incorporating easily accessible paper, glass slides or other polymer films as the chip materials along with adhesive wax as the recycling bonding material. We use a laser to cut through the paper or film to form patterns and then sandwich the paper and film between glass sheets or polymer membranes . The hot-melt adhesive wax can realize bridge bonding between various materials, for example, paper, polymethylmethacrylate (PMMA) film, glass sheets, or metal plate. The bonding process is reversible and the wax is reusable through a melting and cooling process. With this process, a three-dimensional (3D) microfluidic chip is achievable by vacuating and venting the chip in a hot-water bath. To study the biocompatibility and applicability of the wax-based microfluidic chip, we tested the PCR compatibility with the chip materials first. Then we applied the wax-paper based microfluidic chip to HeLa cell electroporation (EP ). Subsequently, a prototype of a 5-layer 3D chip was fabricated by multilayer wax bonding. To check the sealing ability and the durability of the chip, green fluorescence protein (GFP) recombinant Escherichia coli (E. coli) bacteria were cultured, with which the chemotaxis of E. coli was studied in order to determine the influence of antibiotic ciprofloxacin concentration on the E. coli migration.

Experiment list: SRX122523 [Chip-atlas[Archive

Lifescience Database Archive (English)

Full Text Available ntibody=Irf2 || treatment=LPS || time=60 min || chip antibody manufacturer 1=Abcam || chip antibody catalog ...number 1=ab65048 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-498 http://

Experiment list: SRX122414 [Chip-atlas[Archive

Lifescience Database Archive (English)

Full Text Available ntibody=Junb || treatment=LPS || time=30 min || chip antibody manufacturer 1=Abcam || chip antibody catalog ...number 1=ab28838 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-46 http://d

Experiment list: SRX214077 [Chip-atlas[Archive

Lifescience Database Archive (English)

Full Text Available erentiated || treatment=Overexpress Sox17_V5 tagged || cell line=KH2 || chip antibody 1=Sox17 || chip antibody manufacture...r 1=R&D || chip antibody 2=V5 || chip antibody manufacturer 2=Invit

Experiment list: SRX122485 [Chip-atlas[Archive

Lifescience Database Archive (English)

Full Text Available antibody=Atf3 || treatment=LPS || time=120 min || chip antibody manufacturer 1=Santa Cruz || chip antibody ...catalog number 1=sc-188 || chip antibody manufacturer 2=Abcam || chip antibody catalog number 2=ab70005-100

Experiment list: SRX122521 [Chip-atlas[Archive

Lifescience Database Archive (English)

Full Text Available ntibody=Irf2 || treatment=LPS || time=30 min || chip antibody manufacturer 1=Abcam || chip antibody catalog ...number 1=ab65048 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-498 http://

Experiment list: SRX122417 [Chip-atlas[Archive

Lifescience Database Archive (English)

Full Text Available ntibody=Junb || treatment=LPS || time=60 min || chip antibody manufacturer 1=Abcam || chip antibody catalog ...number 1=ab28838 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-46 http://d

Experiment list: SRX122520 [Chip-atlas[Archive

Lifescience Database Archive (English)

Full Text Available ntibody=Irf2 || treatment=LPS || time=30 min || chip antibody manufacturer 1=Abcam || chip antibody catalog ...number 1=ab65048 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-498 http://

Experiment list: SRX122413 [Chip-atlas[Archive

Lifescience Database Archive (English)

Full Text Available antibody=Junb || treatment=LPS || time=120 min || chip antibody manufacturer 1=Abcam || chip antibody catalo...g number 1=ab28838 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-46 http:/

Experiment list: SRX122412 [Chip-atlas[Archive

Lifescience Database Archive (English)

Full Text Available antibody=Junb || treatment=LPS || time=120 min || chip antibody manufacturer 1=Abcam || chip antibody catalo...g number 1=ab28838 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-46 http:/

Experiment list: SRX122406 [Chip-atlas[Archive

Lifescience Database Archive (English)

Full Text Available antibody=Irf1 || treatment=LPS || time=0 min || chip antibody manufacturer 1=Abcam || chip antibody catalog... number 1=ab52520 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-640 http:/

Experiment list: SRX122415 [Chip-atlas[Archive

Lifescience Database Archive (English)

Full Text Available ntibody=Junb || treatment=LPS || time=30 min || chip antibody manufacturer 1=Abcam || chip antibody catalog ...number 1=ab28838 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-46 http://d

Experiment list: SRX122416 [Chip-atlas[Archive

Lifescience Database Archive (English)

Full Text Available ntibody=Junb || treatment=LPS || time=60 min || chip antibody manufacturer 1=Abcam || chip antibody catalog ...number 1=ab28838 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-46 http://d

Experiment list: SRX122565 [Chip-atlas[Archive

Lifescience Database Archive (English)

Full Text Available antibody=Stat2 || treatment=LPS || time=0 min || chip antibody manufacturer 1=Abcam || chip antibody catalog... number 1=ab53149 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-839 http:/

Experiment list: SRX122510 [Chip-atlas[Archive

Lifescience Database Archive (English)

Full Text Available antibody=Egr1 || treatment=LPS || time=0 min || chip antibody manufacturer 1=Abcam || chip antibody catalog... number 1=ab54966-100 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-110 ht

Experiment list: SRX122519 [Chip-atlas[Archive

Lifescience Database Archive (English)

Full Text Available antibody=Irf2 || treatment=LPS || time=120 min || chip antibody manufacturer 1=Abcam || chip antibody catalo...g number 1=ab65048 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-498 http:

Experiment list: SRX122472 [Chip-atlas[Archive

Lifescience Database Archive (English)

Full Text Available antibody=Runx1 || treatment=LPS || time=0 min || chip antibody manufacturer 1=Abcam || chip antibody catalo...g number 1=ab61753 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-8564 http

Experiment list: SRX122473 [Chip-atlas[Archive

Lifescience Database Archive (English)

Full Text Available ip antibody=Runx1 || treatment=LPS || time=120 min || chip antibody manufacturer 1=Abcam || chip antibody ca...talog number 1=ab61753 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-8564

Experiment list: SRX122497 [Chip-atlas[Archive

Lifescience Database Archive (English)

Full Text Available antibody=Rel || treatment=LPS || time=30 min || chip antibody manufacturer 1=Santa Cruz || chip antibody cat...alog number 1=sc-71 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-70 http:

Experiment list: SRX122410 [Chip-atlas[Archive

Lifescience Database Archive (English)

Full Text Available ntibody=Junb || treatment=LPS || time=0 min || chip antibody manufacturer 1=Abcam || chip antibody catalog n...umber 1=ab28838 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-46 http://db

Experiment list: SRX186172 [Chip-atlas[Archive

Lifescience Database Archive (English)

Full Text Available 1=YY1 || chip antibody manufacturer 1=Abcam || chip antibody 2=YY1 || chip antibody manufacturer 2=Santa Cru...ip-Seq; Mus musculus; ChIP-Seq source_name=Rag1 -/- pro-B cells || chip antibody

Experiment list: SRX122493 [Chip-atlas[Archive

Lifescience Database Archive (English)

Full Text Available antibody=Atf4 || treatment=LPS || time=120 min || chip antibody manufacturer 1=Abcam || chip antibody catal...og number 1=ab28830-100 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-200

Experiment list: SRX122571 [Chip-atlas[Archive

Lifescience Database Archive (English)

Full Text Available antibody=Stat2 || treatment=LPS || time=30 min || chip antibody manufacturer 1=Abcam || chip antibody catal...og number 1=ab53149 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-839 http

Experiment list: SRX122411 [Chip-atlas[Archive

Lifescience Database Archive (English)

Full Text Available ntibody=Junb || treatment=LPS || time=0 min || chip antibody manufacturer 1=Abcam || chip antibody catalog n...umber 1=ab28838 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-46 http://db

Experiment list: SRX122498 [Chip-atlas[Archive

Lifescience Database Archive (English)

Full Text Available antibody=Rel || treatment=LPS || time=60 min || chip antibody manufacturer 1=Santa Cruz || chip antibody cat...alog number 1=sc-71 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-70 http:

Experiment list: SRX122516 [Chip-atlas[Archive

Lifescience Database Archive (English)

Full Text Available antibody=Irf2 || treatment=LPS || time=120 min || chip antibody manufacturer 1=Abcam || chip antibody catalo...g number 1=ab65048 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-498 http:

Experiment list: SRX122495 [Chip-atlas[Archive

Lifescience Database Archive (English)

Full Text Available ntibody=Rel || treatment=LPS || time=0 min || chip antibody manufacturer 1=Santa Cruz || chip antibody catal...og number 1=sc-71 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-70 http://

Wood chips procurement and research project at the Mikkeli region; Puuhakkeen hankinta- ja tutkimusprojekti Mikkelin seudulla

Energy Technology Data Exchange (ETDEWEB)

Saksa, T [Finnish Forest Research Inst., Suonenjoki (Finland). Suonenjoki Research Station; Auvinen, P [Mikkeli city (Finland). Dept. of Agriculture and Forestry

1997-12-31

In 1993-94, a large-scale energywood production chain started as a co-operation project by the Mikkeli city forest office and local forestry societies. In 1995 over 115 000 m{sup 3} (about 85 000 MWh of energy) of wood chips were delivered to Pursiala heat and power plant in Mikkeli. About 75 % of these chips was forest processed chips. About 70 % of the forest processed chips was whole tree chips from improvement cuttings of young forest stands and the rest was logging waste chips from regeneration cutting areas. The average total delivery costs of forest processed chips after reduction of energywood and other subsidies were approximately 45 FIM/m{sup 3} (60 FIM/MWh) for the whole tree chips and 38 FIM/m{sup 3} (50 FIM/MWh) for logging waste chips. The delivery costs of forest processed chips could meet the target of Bioenergy Research Programme (45 FIM/MWh) only in the most favourable cases. In an average the delivery costs were about 9 FIM/MWh more than the price obtained when sold to the heat and power plant. However the wood chip production created 27 new jobs and the increase of income to the local economy was about 2.2 milj. FIM /year. The local communities got new tax revenue about 3 FIM/MWh. The gain for the forestry was approximated to be 5 - 6 FIM/MWh. The resources of forest processed chips were studied on the basis of stand measurements. According to the study the most remarkable energywood resources were in young thinning stands on Oxalis-Myrtillus and Myrtillus forest site types. On Oxalis-Myrtillus type almost every and on Myrtillus type every second stand included energywood more than 40 m{sup 3}/ha

Wood chips procurement and research project at the Mikkeli region; Puuhakkeen hankinta- ja tutkimusprojekti Mikkelin seudulla

Energy Technology Data Exchange (ETDEWEB)

Saksa, T. [Finnish Forest Research Inst., Suonenjoki (Finland). Suonenjoki Research Station; Auvinen, P. [Mikkeli city (Finland). Dept. of Agriculture and Forestry

1996-12-31

In 1993-94, a large-scale energywood production chain started as a co-operation project by the Mikkeli city forest office and local forestry societies. In 1995 over 115 000 m{sup 3} (about 85 000 MWh of energy) of wood chips were delivered to Pursiala heat and power plant in Mikkeli. About 75 % of these chips was forest processed chips. About 70 % of the forest processed chips was whole tree chips from improvement cuttings of young forest stands and the rest was logging waste chips from regeneration cutting areas. The average total delivery costs of forest processed chips after reduction of energywood and other subsidies were approximately 45 FIM/m{sup 3} (60 FIM/MWh) for the whole tree chips and 38 FIM/m{sup 3} (50 FIM/MWh) for logging waste chips. The delivery costs of forest processed chips could meet the target of Bioenergy Research Programme (45 FIM/MWh) only in the most favourable cases. In an average the delivery costs were about 9 FIM/MWh more than the price obtained when sold to the heat and power plant. However the wood chip production created 27 new jobs and the increase of income to the local economy was about 2.2 milj. FIM /year. The local communities got new tax revenue about 3 FIM/MWh. The gain for the forestry was approximated to be 5 - 6 FIM/MWh. The resources of forest processed chips were studied on the basis of stand measurements. According to the study the most remarkable energywood resources were in young thinning stands on Oxalis-Myrtillus and Myrtillus forest site types. On Oxalis-Myrtillus type almost every and on Myrtillus type every second stand included energywood more than 40 m{sup 3}/ha

Experiment list: SRX122563 [Chip-atlas[Archive

Lifescience Database Archive (English)

Full Text Available antibody=Stat1 || treatment=LPS || time=60 min || chip antibody manufacturer 1=Santa Cruz || chip antibody ...catalog number 1=sc-346 || chip antibody manufacturer 2=Bethyl || chip antibody catalog number 2=A302-753A h

Experiment list: SRX122564 [Chip-atlas[Archive

Lifescience Database Archive (English)

Full Text Available antibody=Stat1 || treatment=LPS || time=60 min || chip antibody manufacturer 1=Santa Cruz || chip antibody ...catalog number 1=sc-346 || chip antibody manufacturer 2=Bethyl || chip antibody catalog number 2=A302-753A h

Experiment list: SRX122488 [Chip-atlas[Archive

Lifescience Database Archive (English)

Full Text Available antibody=Atf3 || treatment=LPS || time=120 min || chip antibody manufacturer 1=Santa Cruz || chip antibody c...atalog number 1=sc-188 || chip antibody manufacturer 2=Abcam || chip antibody catalog number 2=ab70005-100 h

Experiment list: SRX122491 [Chip-atlas[Archive

Lifescience Database Archive (English)

Full Text Available ntibody=Atf3 || treatment=LPS || time=60 min || chip antibody manufacturer 1=Santa Cruz || chip antibody cat...alog number 1=sc-188 || chip antibody manufacturer 2=Abcam || chip antibody catalog number 2=ab70005-100 htt

Experiment list: SRX122548 [Chip-atlas[Archive

Lifescience Database Archive (English)

Full Text Available ip antibody=Stat1 || treatment=LPS || time=0 min || chip antibody manufacturer 1=Santa Cruz || chip antibody... catalog number 1=sc-346 || chip antibody manufacturer 2=Bethyl || chip antibody catalog number 2=A302-753A

Experiment list: SRX122468 [Chip-atlas[Archive

Lifescience Database Archive (English)

Full Text Available antibody=Rela || treatment=LPS || time=0 min || chip antibody manufacturer 1=Bethyl || chip antibody catalo...g number 1=A301-824A || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-372 htt

Experiment list: SRX122561 [Chip-atlas[Archive

Lifescience Database Archive (English)

Full Text Available antibody=Stat1 || treatment=LPS || time=30 min || chip antibody manufacturer 1=Santa Cruz || chip antibody ...catalog number 1=sc-346 || chip antibody manufacturer 2=Bethyl || chip antibody catalog number 2=A302-753A h

Experiment list: SRX122409 [Chip-atlas[Archive

Lifescience Database Archive (English)

Full Text Available ip antibody=Irf1 || treatment=LPS || time=60 min || chip antibody manufacturer 1=Abcam || chip antibody cata...log number 1=ab52520 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-640 htt

Experiment list: SRX122487 [Chip-atlas[Archive

Lifescience Database Archive (English)

Full Text Available antibody=Atf3 || treatment=LPS || time=120 min || chip antibody manufacturer 1=Santa Cruz || chip antibody c...atalog number 1=sc-188 || chip antibody manufacturer 2=Abcam || chip antibody catalog number 2=ab70005-100 h

Experiment list: SRX122552 [Chip-atlas[Archive

Lifescience Database Archive (English)

Full Text Available ip antibody=Stat1 || treatment=LPS || time=120 min || chip antibody manufacturer 1=Santa Cruz || chip antibo...dy catalog number 1=sc-346 || chip antibody manufacturer 2=Bethyl || chip antibody catalog number 2=A302-753

Experiment list: SRX122408 [Chip-atlas[Archive

Lifescience Database Archive (English)

Full Text Available p antibody=Irf1 || treatment=LPS || time=30 min || chip antibody manufacturer 1=Abcam || chip antibody catal...og number 1=ab52520 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-640 http

Experiment list: SRX122513 [Chip-atlas[Archive

Lifescience Database Archive (English)

Full Text Available p antibody=Egr1 || treatment=LPS || time=60 min || chip antibody manufacturer 1=Abcam || chip antibody catal...og number 1=ab54966-100 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-110

Experiment list: SRX122567 [Chip-atlas[Archive

Lifescience Database Archive (English)

Full Text Available p antibody=Stat2 || treatment=LPS || time=120 min || chip antibody manufacturer 1=Abcam || chip antibody cat...alog number 1=ab53149 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-839 ht

Experiment list: SRX122490 [Chip-atlas[Archive

Lifescience Database Archive (English)

Full Text Available ntibody=Atf3 || treatment=LPS || time=30 min || chip antibody manufacturer 1=Santa Cruz || chip antibody cat...alog number 1=sc-188 || chip antibody manufacturer 2=Abcam || chip antibody catalog number 2=ab70005-100 htt

Experiment list: SRX122558 [Chip-atlas[Archive

Lifescience Database Archive (English)

Full Text Available hip antibody=Stat1 || treatment=LPS || time=120 min || chip antibody manufacturer 1=Santa Cruz || chip antib...ody catalog number 1=sc-346 || chip antibody manufacturer 2=Bethyl || chip antibody catalog number 2=A302-75

Experiment list: SRX122494 [Chip-atlas[Archive

Lifescience Database Archive (English)

Full Text Available hip antibody=Atf4 || treatment=LPS || time=120 min || chip antibody manufacturer 1=Abcam || chip antibody ca...talog number 1=ab28830-100 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-2

Experiment list: SRX122557 [Chip-atlas[Archive

Lifescience Database Archive (English)

Full Text Available hip antibody=Stat1 || treatment=LPS || time=120 min || chip antibody manufacturer 1=Santa Cruz || chip antib...ody catalog number 1=sc-346 || chip antibody manufacturer 2=Bethyl || chip antibody catalog number 2=A302-75

Experiment list: SRX122492 [Chip-atlas[Archive

Lifescience Database Archive (English)

Full Text Available ntibody=Atf3 || treatment=LPS || time=60 min || chip antibody manufacturer 1=Santa Cruz || chip antibody cat...alog number 1=sc-188 || chip antibody manufacturer 2=Abcam || chip antibody catalog number 2=ab70005-100 htt

Experiment list: SRX122549 [Chip-atlas[Archive

Lifescience Database Archive (English)

Full Text Available ip antibody=Stat1 || treatment=LPS || time=0 min || chip antibody manufacturer 1=Santa Cruz || chip antibody... catalog number 1=sc-346 || chip antibody manufacturer 2=Bethyl || chip antibody catalog number 2=A302-753A

Experiment list: SRX122484 [Chip-atlas[Archive

Lifescience Database Archive (English)

Full Text Available ntibody=Atf3 || treatment=LPS || time=0 min || chip antibody manufacturer 1=Santa Cruz || chip antibody cata...log number 1=sc-188 || chip antibody manufacturer 2=Abcam || chip antibody catalog number 2=ab70005-100 http

Experiment list: SRX122514 [Chip-atlas[Archive

Lifescience Database Archive (English)

Full Text Available tibody=Irf2 || treatment=LPS || time=0 min || chip antibody manufacturer 1=Abcam || chip antibody catalog nu...mber 1=ab65048 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-498 http://db

Experiment list: SRX122570 [Chip-atlas[Archive

Lifescience Database Archive (English)

Full Text Available p antibody=Stat2 || treatment=LPS || time=120 min || chip antibody manufacturer 1=Abcam || chip antibody cat...alog number 1=ab53149 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-839 ht

Experiment list: SRX122569 [Chip-atlas[Archive

Lifescience Database Archive (English)

Full Text Available ip antibody=Stat2 || treatment=LPS || time=120 min || chip antibody manufacturer 1=Abcam || chip antibody ca...talog number 1=ab53149 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-839 h

Experiment list: SRX122511 [Chip-atlas[Archive

Lifescience Database Archive (English)

Full Text Available ip antibody=Egr1 || treatment=LPS || time=120 min || chip antibody manufacturer 1=Abcam || chip antibody cat...alog number 1=ab54966-100 || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-11

Experiment list: SRX122471 [Chip-atlas[Archive

Lifescience Database Archive (English)

Full Text Available ip antibody=Rela || treatment=LPS || time=60 min || chip antibody manufacturer 1=Bethyl || chip antibody cat...alog number 1=A301-824A || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-372

Experiment list: SRX122554 [Chip-atlas[Archive

Lifescience Database Archive (English)

Full Text Available ip antibody=Stat1 || treatment=LPS || time=120 min || chip antibody manufacturer 1=Santa Cruz || chip antibo...dy catalog number 1=sc-346 || chip antibody manufacturer 2=Bethyl || chip antibody catalog number 2=A302-753

Development of a Metal Cutting Tool Fase in Order to Create the Conditions of Ringed Chips Wrapping

Science.gov (United States)

Korchuganova, M.; Syrbakov, A.; Chernysheva, T.; Ivanov, G.; Korchuganov, M.

2016-08-01

When processing ductile metals with high cutting speed, there is a need to take additional measures for a comfortable and safe formation and removal of chips. In the conditions of large-scale manufacture, it is recommended to produce flow chips in the form of short fragments, while in the conditions of small-lot and single-piece manufacture, it is reasonable to wrap the chips spirally with a rather small turn radius. Such way of chips formation reduces the time of its removal from the working area as well as facilitates its transportation and processing. In order to solve the problem of chip wrapping and breakage, almost all modern manufacturers of tools with replaceable many-sided plates (RMSP) followed the way of complication of tool faces and determination of the areas of effective chip breaking. On the one hand, the suggested solution turns out to be effective; however, as showed the analysis of recommended cutting modes for complex forms of RMSP made by leading manufacturers, they all correspond to the definite cross section of the cut-layer S/t=0.1.

Experiment list: SRX122551 [Chip-atlas[Archive

Lifescience Database Archive (English)

Full Text Available antibody=Stat1 || treatment=LPS || time=0 min || chip antibody manufacturer 1=Santa Cruz || chip antibody ca...talog number 1=sc-346 || chip antibody manufacturer 2=Bethyl || chip antibody catalog number 2=A302-753A htt

Experiment list: SRX122546 [Chip-atlas[Archive

Lifescience Database Archive (English)

Full Text Available p antibody=Stat1 || treatment=LPS || time=0 min || chip antibody manufacturer 1=Santa Cruz || chip antibody ...catalog number 1=sc-346 || chip antibody manufacturer 2=Bethyl || chip antibody catalog number 2=A302-753A h

Experiment list: SRX122547 [Chip-atlas[Archive

Lifescience Database Archive (English)

Full Text Available antibody=Stat1 || treatment=LPS || time=0 min || chip antibody manufacturer 1=Santa Cruz || chip antibody c...atalog number 1=sc-346 || chip antibody manufacturer 2=Bethyl || chip antibody catalog number 2=A302-753A ht

Experiment list: SRX214084 [Chip-atlas[Archive

Lifescience Database Archive (English)

Full Text Available turer 1=Santa Cruz || chip antibody 2=V5 || chip antibody manufacture...ge=Undifferentiated || treatment=Overexpress Sox17-V5 tagged || cell line=KH2 || chip antibody 1=Pou5f1/Oct4 || chip antibody manufac

Experiment list: SRX122544 [Chip-atlas[Archive

Lifescience Database Archive (English)

Full Text Available antibody=Stat1 || treatment=LPS || time=0 min || chip antibody manufacturer 1=Santa Cruz || chip antibody c...atalog number 1=sc-346 || chip antibody manufacturer 2=Bethyl || chip antibody catalog number 2=A302-753A ht

Experiment list: SRX214082 [Chip-atlas[Archive

Lifescience Database Archive (English)

Full Text Available facturer 1=Santa Cruz || chip antibody 2=V5 || chip antibody manufacture...age=Undifferentiated || treatment=Overexpress Sox17EK-V5 tagged || cell line=KH2 || chip antibody 1=Pou5f1/Oct4 || chip antibody manu

Experiment list: SRX122466 [Chip-atlas[Archive

Lifescience Database Archive (English)

Full Text Available p antibody=Relb || treatment=LPS || time=30 min || chip antibody manufacturer 1=Bethyl || chip antibody cata...log number 1=A302-183A || chip antibody manufacturer 2=Santa Cruz || chip antibody catalog number 2=sc-226 h

Experiment list: SRX122545 [Chip-atlas[Archive

Lifescience Database Archive (English)

Full Text Available antibody=Stat1 || treatment=LPS || time=0 min || chip antibody manufacturer 1=Santa Cruz || chip antibody c...atalog number 1=sc-346 || chip antibody manufacturer 2=Bethyl || chip antibody catalog number 2=A302-753A ht

Experiment list: SRX214080 [Chip-atlas[Archive

Lifescience Database Archive (English)

Full Text Available cturer 1=Santa Cruz || chip antibody 2=V5 || chip antibody manufacture...ge=Undifferentiated || treatment=Overexpress Sox2KE-V5 tagged || cell line=KH2 || chip antibody 1=Pou5f1/Oct4 || chip antibody manufa

Experiment list: SRX214081 [Chip-atlas[Archive

Lifescience Database Archive (English)

Full Text Available cturer 1=Santa Cruz || chip antibody 2=V5 || chip antibody manufacture...ge=Undifferentiated || treatment=Overexpress Sox2KE-V5 tagged || cell line=KH2 || chip antibody 1=Pou5f1/Oct4 || chip antibody manufa

Laser Light-field Fusion for Wide-field Lensfree On-chip Phase Contrast Microscopy of Nanoparticles

Science.gov (United States)

Kazemzadeh, Farnoud; Wong, Alexander

2016-12-01

Wide-field lensfree on-chip microscopy, which leverages holography principles to capture interferometric light-field encodings without lenses, is an emerging imaging modality with widespread interest given the large field-of-view compared to lens-based techniques. In this study, we introduce the idea of laser light-field fusion for lensfree on-chip phase contrast microscopy for detecting nanoparticles, where interferometric laser light-field encodings acquired using a lensfree, on-chip setup with laser pulsations at different wavelengths are fused to produce marker-free phase contrast images of particles at the nanometer scale. As a proof of concept, we demonstrate, for the first time, a wide-field lensfree on-chip instrument successfully detecting 300 nm particles across a large field-of-view of ~30 mm2 without any specialized or intricate sample preparation, or the use of synthetic aperture- or shift-based techniques.

Invited Article: Terahertz microfluidic chips sensitivity-enhanced with a few arrays of meta-atoms

Directory of Open Access Journals (Sweden)

Kazunori Serita

2018-05-01

Full Text Available We present a nonlinear optical crystal (NLOC-based terahertz (THz microfluidic chip with a few arrays of split ring resonators (SRRs for ultra-trace and quantitative measurements of liquid solutions. The proposed chip operates on the basis of near-field coupling between the SRRs and a local emission of point like THz source that is generated in the process of optical rectification in NLOCs on a sub-wavelength scale. The liquid solutions flowing inside the microchannel modify the resonance frequency and peak attenuation in the THz transmission spectra. In contrast to conventional bio-sensing with far/near-field THz waves, our technique can be expected to compactify the chip design as well as realize high sensitive near-field measurement of liquid solutions without any high-power optical/THz source, near-field probes, and prisms. Using this chip, we have succeeded in observing the 31.8 fmol of ion concentration in actual amount of 318 pl water solutions from the shift of the resonance frequency. The technique opens the door to microanalysis of biological samples with THz waves and accelerates development of THz lab-on-chip devices.

Invited Article: Terahertz microfluidic chips sensitivity-enhanced with a few arrays of meta-atoms

Science.gov (United States)

Serita, Kazunori; Matsuda, Eiki; Okada, Kosuke; Murakami, Hironaru; Kawayama, Iwao; Tonouchi, Masayoshi

2018-05-01

We present a nonlinear optical crystal (NLOC)-based terahertz (THz) microfluidic chip with a few arrays of split ring resonators (SRRs) for ultra-trace and quantitative measurements of liquid solutions. The proposed chip operates on the basis of near-field coupling between the SRRs and a local emission of point like THz source that is generated in the process of optical rectification in NLOCs on a sub-wavelength scale. The liquid solutions flowing inside the microchannel modify the resonance frequency and peak attenuation in the THz transmission spectra. In contrast to conventional bio-sensing with far/near-field THz waves, our technique can be expected to compactify the chip design as well as realize high sensitive near-field measurement of liquid solutions without any high-power optical/THz source, near-field probes, and prisms. Using this chip, we have succeeded in observing the 31.8 fmol of ion concentration in actual amount of 318 pl water solutions from the shift of the resonance frequency. The technique opens the door to microanalysis of biological samples with THz waves and accelerates development of THz lab-on-chip devices.

Adaptive WTA with an analog VLSI neuromorphic learning chip.

Science.gov (United States)

Häfliger, Philipp

2007-03-01

In this paper, we demonstrate how a particular spike-based learning rule (where exact temporal relations between input and output spikes of a spiking model neuron determine the changes of the synaptic weights) can be tuned to express rate-based classical Hebbian learning behavior (where the average input and output spike rates are sufficient to describe the synaptic changes). This shift in behavior is controlled by the input statistic and by a single time constant. The learning rule has been implemented in a neuromorphic very large scale integration (VLSI) chip as part of a neurally inspired spike signal image processing system. The latter is the result of the European Union research project Convolution AER Vision Architecture for Real-Time (CAVIAR). Since it is implemented as a spike-based learning rule (which is most convenient in the overall spike-based system), even if it is tuned to show rate behavior, no explicit long-term average signals are computed on the chip. We show the rule's rate-based Hebbian learning ability in a classification task in both simulation and chip experiment, first with artificial stimuli and then with sensor input from the CAVIAR system.

On-Chip Manipulation of Protein-Coated Magnetic Beads via Domain-Wall Conduits

DEFF Research Database (Denmark)

Donolato, Marco; Vavassori, Paolo; Gobbi, Marco

2010-01-01

Geometrically constrained magnetic domain walls (DWs) in magnetic nanowires can be manipulated at the nanometer scale. The inhomogeneous magnetic stray field generated by a DW can capture a magnetic nanoparticle in solution. On-chip nanomanipulation of individual magnetic beads coated with proteins...

Experiment list: SRX214068 [Chip-atlas[Archive

Lifescience Database Archive (English)

Full Text Available inoic acid || cell line=F9 || chip antibody 1=Pou5f1/Oct4 || chip antibody manufacturer 1=Santa Cruz || chip... antibody 2=none || chip antibody manufacturer 2=none http://dbarchive.biosciencedbc.jp/kyushu-u/mm9/eachDat

Packaging Solutions : Delivering customer value through Logistical Packaging: A Case Study at Stora Enso Packaging

OpenAIRE

Shan, Kun; Julius, Joezer

2015-01-01

AbstractBackground;Despite of the significant role of packaging within logistics and supply chain management, packaging is infrequently studied as focal point in supply chain. Most of the previous logistics research studies tend to explain the integration between packaging and logistics through logistical packaging. In very rare cases, the studies mentioned about customer value. Therefore the major disadvantage of these studies is that, they didn’t consider logistical packaging and customer v...

ALICE chip processor

CERN Multimedia

Maximilien Brice

2003-01-01

This tiny chip provides data processing for the time projection chamber on ALICE. Known as the ALICE TPC Read Out (ALTRO), this device was designed to minimize the size and power consumption of the TPC front end electronics. This single chip contains 16 low-power analogue-to-digital converters with six million transistors of digital processing and 8 kbits of data storage.

Materials of Criticality Safety Concern in Waste Packages

International Nuclear Information System (INIS)

Larson, S.L.; Day, B.A.

2006-01-01

10 CFR 71.55 requires in part that the fissile material package remain subcritical when considering 'the most reactive credible configuration consistent with the chemical and physical form of the material'. As waste drums and packages may contain unlimited types of materials, determination of the appropriately bounding moderator and reflector materials to ensure compliance with 71.55 requires a comprehensive analysis. Such an analysis was performed to determine the materials or elements that produce the most reactive configuration with regards to both moderation and reflection of a Pu-239 system. The study was originally performed for the TRUPACT-II shipping package and thus the historical fissile mass limit for the package, 325 g Pu-239, was used [1]. Reactivity calculations were performed with the SCALE package to numerically assess the moderation or reflection merits of the materials [2]. Additional details and results are given in SAIC-1322-001 [3]. The development of payload controls utilizing process knowledge to determine the classification of special moderator and/or reflector materials and the associated fissile mass limit is also addressed. (authors)

Packaging fluency

DEFF Research Database (Denmark)

Mocanu, Ana; Chrysochou, Polymeros; Bogomolova, Svetlana

2011-01-01

Research on packaging stresses the need for packaging design to read easily, presuming fast and accurate processing of product-related information. In this paper we define this property of packaging as “packaging fluency”. Based on the existing marketing and cognitive psychology literature on pac...

Wireless Interconnect in Multilayer Chip-Area-Networks for Future Multimaterial High-Speed Systems Design

Directory of Open Access Journals (Sweden)

Oluwole John Famoriji

2017-01-01

Full Text Available Wireless chip area network which enables wireless communication among chips fosters development in wireless communication and it is envisioned that future hardware system and developmental functionality will require multimaterial. However, the traditional system architecture is limited by channel bandwidth-limited interfaces, throughput, delay, and power consumption and as a result limits the efficiency and system performance. Wireless interconnect has been proposed to overcome scalability and performance limitations of multihop wired architectures. Characterization and modeling of channel become more important for specification of choice of modulation or demodulation techniques, channel bandwidths, and other mitigation techniques for channel distortion and interference such as equalization. This paper presents an analytical channel model for characterization, modeling, and analysis of wireless chip-to-chip or interchip interconnects in wireless chip area network with a particular focus on large-scale analysis. The proposed model accounts for both static and dynamic channel losses/attenuation in high-speed systems. Simulation and evaluation of the model with experimental data conducted in a computer desktop casing depict that proposed model matched measurement data very closely. The transmission of EM waves via a medium introduces molecular absorption due to various molecules within the material substance. This model is a representative of channel loss profile in wireless chip-area-network communication and good for future electronic circuits and high-speed systems design.

SCAMPI: A code package for cross-section processing

International Nuclear Information System (INIS)

Parks, C.V.; Petrie, L.M.; Bowman, S.M.; Broadhead, B.L.; Greene, N.M.; White, J.E.

1996-01-01

The SCAMPI code package consists of a set of SCALE and AMPX modules that have been assembled to facilitate user needs for preparation of problem-specific, multigroup cross-section libraries. The function of each module contained in the SCANTI code package is discussed, along with illustrations of their use in practical analyses. Ideas are presented for future work that can enable one-step processing from a fine-group, problem-independent library to a broad-group, problem-specific library ready for a shielding analysis

SCAMPI: A code package for cross-section processing

Energy Technology Data Exchange (ETDEWEB)

Parks, C.V.; Petrie, L.M.; Bowman, S.M.; Broadhead, B.L.; Greene, N.M.; White, J.E.

1996-04-01

The SCAMPI code package consists of a set of SCALE and AMPX modules that have been assembled to facilitate user needs for preparation of problem-specific, multigroup cross-section libraries. The function of each module contained in the SCANTI code package is discussed, along with illustrations of their use in practical analyses. Ideas are presented for future work that can enable one-step processing from a fine-group, problem-independent library to a broad-group, problem-specific library ready for a shielding analysis.

Eddylicious: A Python package for turbulent inflow generation

Science.gov (United States)

Mukha, Timofey; Liefvendahl, Mattias

2018-01-01

A Python package for generating inflow for scale-resolving computer simulations of turbulent flow is presented. The purpose of the package is to unite existing inflow generation methods in a single code-base and make them accessible to users of various Computational Fluid Dynamics (CFD) solvers. The currently existing functionality consists of an accurate inflow generation method suitable for flows with a turbulent boundary layer inflow and input/output routines for coupling with the open-source CFD solver OpenFOAM.

Large-scale matrix-handling subroutines 'ATLAS'

International Nuclear Information System (INIS)

Tsunematsu, Toshihide; Takeda, Tatsuoki; Fujita, Keiichi; Matsuura, Toshihiko; Tahara, Nobuo

1978-03-01

Subroutine package ''ATLAS'' has been developed for handling large-scale matrices. The package is composed of four kinds of subroutines, i.e., basic arithmetic routines, routines for solving linear simultaneous equations and for solving general eigenvalue problems and utility routines. The subroutines are useful in large scale plasma-fluid simulations. (auth.)

Pelly Crossing wood chip boiler

Energy Technology Data Exchange (ETDEWEB)

1985-03-11

The Pelly wood chip project has demonstrated that wood chips are a successful fuel for space and domestic water heating in a northern climate. Pelly Crossing was chosen as a demonstration site for the following reasons: its extreme temperatures, an abundant local supply of resource material, the high cost of fuel oil heating and a lack of local employment. The major obstacle to the smooth operation of the boiler system was the poor quality of the chip supply. The production of poor quality chips has been caused by inadequate operation and maintenance of the chipper. Dull knives and faulty anvil adjustments produced chips and splinters far in excess of the one centimetre size specified for the system's design. Unanticipated complications have caused costs of the system to be higher than expected by approximately $15,000. The actual cost of the project was approximately $165,000. The first year of the system's operation was expected to accrue $11,600 in heating cost savings. This estimate was impossible to confirm given the system's irregular operation and incremental costs. Consistent operation of the system for a period of at least one year plus the installation of monitoring devices will allow the cost effectiveness to be calculated. The wood chip system's impact on the environment was estimated to be minimal. Wood chip burning was considered cleaner and safer than cordwood burning. 9 refs., 6 figs., 6 tabs.

High-performance fluorescence-encoded magnetic microbeads as microfluidic protein chip supports for AFP detection

Energy Technology Data Exchange (ETDEWEB)

Gong, Xiaoqun [School of Life Sciences, Tianjin Engineering Center of Micro-Nano Biomaterials and Detection-Treatment Technology, Collaborative Innovation Center of Chemical Science and Engineering, Tianjin University, Tianjin 300072 (China); Yan, Huan; Yang, Jiumin [Department of Laboratory Medicine, Tianjin Medical University General Hospital, Tianjin, 300052 (China); Wu, Yudong; Zhang, Jian; Yao, Yingyi [School of Life Sciences, Tianjin Engineering Center of Micro-Nano Biomaterials and Detection-Treatment Technology, Collaborative Innovation Center of Chemical Science and Engineering, Tianjin University, Tianjin 300072 (China); Liu, Ping [Bioscience (Tianjin) Diagnostic Technology CO., LTD, Tianjin, 300300 (China); Wang, Huiquan [Department of Biomedical Engineering, School of Electronics and Information Engineering, Tianjin Polytechnic University, Tianjin, 300387 (China); Hu, Zhidong, E-mail: huzhidong27@163.com [Department of Laboratory Medicine, Tianjin Medical University General Hospital, Tianjin, 300052 (China); Chang, Jin, E-mail: jinchang@tju.edu.cn [School of Life Sciences, Tianjin Engineering Center of Micro-Nano Biomaterials and Detection-Treatment Technology, Collaborative Innovation Center of Chemical Science and Engineering, Tianjin University, Tianjin 300072 (China)

2016-10-05

Fluorescence-encoded magnetic microbeads (FEMMs), with the fluorescence encoding ability of quantum dots (QDs) and magnetic enrichment and separation functions of Fe{sub 3}O{sub 4} nanoparticles, have been widely used for multiple biomolecular detection as microfluidic protein chip supports. However, the preparation of FEMMs with long-term fluorescent encoding and immunodetection stability is still a challenge. In this work, we designed a novel high-temperature chemical swelling strategy. The QDs and Fe{sub 3}O{sub 4} nanoparticles were effectively packaged into microbeads via the thermal motion of the polymer chains and the hydrophobic interaction between the nanoparticles and microbeads. The FEMMs obtained a highly uniform fluorescent property and long-term encoding and immunodetection stability and could be quickly magnetically separated and enriched. Then, the QD-encoded magnetic microbeads were applied to alpha fetoprotein (AFP) detection via sandwich immunoreaction. The properties of the encoded microspheres were characterized using a self-designed detecting apparatus, and the target molecular concentration in the sample was also quantified. The results suggested that the high-performance FEMMs have great potential in the field of biomolecular detection. - Graphical abstract: We designed a novel strategy to prepare a kind of high-performance fluorescence-encoded magnetic microbeads as microfluidic protein chip support with long-time fluorescent encoding and immunodetection stability for AFP detection. - Highlights: • A novel strategy combined the high temperature with chemical swelling technology is designed. • Based on hydrophobic interaction and polymer thermal motion, QDs and Fe{sub 3}O{sub 4} were effectively packaged into microbeads. • The fluorescence-encoded magnetic microbeads show long-term fluorescent encoding and immunodetection stability.

Scalable on-chip quantum state tomography

Science.gov (United States)

Titchener, James G.; Gräfe, Markus; Heilmann, René; Solntsev, Alexander S.; Szameit, Alexander; Sukhorukov, Andrey A.

2018-03-01

Quantum information systems are on a path to vastly exceed the complexity of any classical device. The number of entangled qubits in quantum devices is rapidly increasing, and the information required to fully describe these systems scales exponentially with qubit number. This scaling is the key benefit of quantum systems, however it also presents a severe challenge. To characterize such systems typically requires an exponentially long sequence of different measurements, becoming highly resource demanding for large numbers of qubits. Here we propose and demonstrate a novel and scalable method for characterizing quantum systems based on expanding a multi-photon state to larger dimensionality. We establish that the complexity of this new measurement technique only scales linearly with the number of qubits, while providing a tomographically complete set of data without a need for reconfigurability. We experimentally demonstrate an integrated photonic chip capable of measuring two- and three-photon quantum states with statistical reconstruction fidelity of 99.71%.

Evaluation of a fast and flexible OPC package: OPTISSIMO

Science.gov (United States)

Maurer, Wilhelm; Waas, Thomas; Eisenmann, Hans

1996-12-01

It is out of question, that current state-of-the-art lithography--printing 350 nm structures with i-line tools or 250 nm structures with DUV tools--needs to correct for proximity effects (OPC). Otherwise, all the well-known effects like line-end shortening, linewidth variation as a function of adjacent patterns, linewidth non-linearity, etc. will produce a pattern, that is significantly different from the intended design. In this paper, we report first evaluation results of OPTISSIMO, a software package for automatic proximity correction. Besides the ability to handle full-chip designs by preserving as much as possible of the original data-hierarchy, there are significant options for the user. A large number of choices can be made to balance between the precision of the correction and the complexity of the corrected design. The main target of our evaluations was to check for full-chip OPC for the gate level of a state-of-the-art design. This corresponds to print either linewidths in the 350 nm to 400 nm range with i-line lithography or 250 nm/300 nm linewidth with DUV lithography. Taking 400 nm i-line lithography as an example, 3% precision OPC which has been demonstrated. By using hierarchical data handling, it was shown, that even the data complexity of a 256 M DRAM can be managed within reasonable time.

Recycling melting process of the zirconium alloy chips

Energy Technology Data Exchange (ETDEWEB)

Reis, Luis A.M. dos; Mucsi, Cristiano S.; Tavares, Luiz A.P.; Alencar, Maicon C.; Gomes, Maurilio P.; Barbosa, Luzinete P.; Rossi, Jesualdo L., E-mail: luisreis.09@gmail.com, E-mail: csmucsi@gmail.com [Instituto de Pesquisas Energéticas e Nucleares (IPEN/CNEN-SP), São Paulo, SP (Brazil)

2017-07-01

Pressurized water reactors (PWR) commonly use {sup 235}U enriched uranium dioxide pellets as a nuclear fuel, these are assembled and stacked in zirconium alloy tubes and end caps (M5, Zirlo, Zircaloy). During the machining of these components large amounts of chips are generated which are contaminated with cutting fluid. Its storage presents safety and environmental risks due to its pyrophoric and reactive nature. Recycling industry shown interest in its recycling due to its strategic importance. This paper presents a study on the recycling process and the results aiming the efficiency in the cleaning process; the quality control; the obtaining of the pressed electrodes and finally the melting in a Vacuum Arc Remelting furnace (VAR). The recycling process begins with magnetic separation of possible ferrous alloys chips contaminant, the washing of the cutting fluid that is soluble in water, washing with an industrial degreaser, followed by a rinse with continuous flow of water under high pressure and drying with hot air. The first evaluation of the process was done by an Energy Dispersive X-rays Fluorescence Spectrometry (EDXRFS) showed the presence of 10 wt. % to 17 wt. % of impurities due the mixing with stainless steel machining chips. The chips were then pressed in a custom-made matrix of square section (40 x 40 mm - 500 mm in length), resulting in electrodes with 20% of apparent density of the original alloy. The electrode was then melted in a laboratory scale VAR furnace at the CCTM-IPEN, producing a massive ingot with 0.8 kg. It was observed that the samples obtained from Indústrias Nucleares do Brasil (INB) are supposed to be secondary scrap and it is suggested careful separation in the generation of this material. The melting of the chips is possible and feasible in a VAR furnace which reduces the storage volume by up to 40 times of this material, however, it is necessary to correct the composition of the alloy for the melting of these ingots. (author)

Recycling melting process of the zirconium alloy chips

International Nuclear Information System (INIS)

Reis, Luis A.M. dos; Mucsi, Cristiano S.; Tavares, Luiz A.P.; Alencar, Maicon C.; Gomes, Maurilio P.; Barbosa, Luzinete P.; Rossi, Jesualdo L.

2017-01-01

Pressurized water reactors (PWR) commonly use 235 U enriched uranium dioxide pellets as a nuclear fuel, these are assembled and stacked in zirconium alloy tubes and end caps (M5, Zirlo, Zircaloy). During the machining of these components large amounts of chips are generated which are contaminated with cutting fluid. Its storage presents safety and environmental risks due to its pyrophoric and reactive nature. Recycling industry shown interest in its recycling due to its strategic importance. This paper presents a study on the recycling process and the results aiming the efficiency in the cleaning process; the quality control; the obtaining of the pressed electrodes and finally the melting in a Vacuum Arc Remelting furnace (VAR). The recycling process begins with magnetic separation of possible ferrous alloys chips contaminant, the washing of the cutting fluid that is soluble in water, washing with an industrial degreaser, followed by a rinse with continuous flow of water under high pressure and drying with hot air. The first evaluation of the process was done by an Energy Dispersive X-rays Fluorescence Spectrometry (EDXRFS) showed the presence of 10 wt. % to 17 wt. % of impurities due the mixing with stainless steel machining chips. The chips were then pressed in a custom-made matrix of square section (40 x 40 mm - 500 mm in length), resulting in electrodes with 20% of apparent density of the original alloy. The electrode was then melted in a laboratory scale VAR furnace at the CCTM-IPEN, producing a massive ingot with 0.8 kg. It was observed that the samples obtained from Indústrias Nucleares do Brasil (INB) are supposed to be secondary scrap and it is suggested careful separation in the generation of this material. The melting of the chips is possible and feasible in a VAR furnace which reduces the storage volume by up to 40 times of this material, however, it is necessary to correct the composition of the alloy for the melting of these ingots. (author)

The Packaging Handbook -- A guide to package design

International Nuclear Information System (INIS)

Shappert, L.B.

1995-01-01

The Packaging Handbook is a compilation of 14 technical chapters and five appendices that address the life cycle of a packaging which is intended to transport radioactive material by any transport mode in normal commerce. Although many topics are discussed in depth, this document focuses on the design aspects of a packaging. The Handbook, which is being prepared under the direction of the US Department of Energy, is intended to provide a wealth of technical guidance that will give designers a better understanding of the regulatory approval process, preferences of regulators in specific aspects of packaging design, and the types of analyses that should be seriously considered when developing the packaging design. Even though the Handbook is concerned with all packagings, most of the emphasis is placed on large packagings that are capable of transporting large radioactive sources that are also fissile (e.g., spent fuel). These are the types of packagings that must address the widest range of technical topics in order to meet domestic and international regulations. Most of the chapters in the Handbook have been drafted and submitted to the Oak Ridge National Laboratory for editing; the majority of these have been edited. This report summarizes the contents

A Single-Chip CMOS Pulse Oximeter with On-Chip Lock-In Detection

Directory of Open Access Journals (Sweden)

Diwei He

2015-07-01

Full Text Available Pulse oximetry is a noninvasive and continuous method for monitoring the blood oxygen saturation level. This paper presents the design and testing of a single-chip pulse oximeter fabricated in a 0.35 µm CMOS process. The chip includes photodiode, transimpedance amplifier, analogue band-pass filters, analogue-to-digital converters, digital signal processor and LED timing control. The experimentally measured AC and DC characteristics of individual circuits including the DC output voltage of the transimpedance amplifier, transimpedance gain of the transimpedance amplifier, and the central frequency and bandwidth of the analogue band-pass filters, show a good match (within 1% with the circuit simulations. With modulated light source and integrated lock-in detection the sensor effectively suppresses the interference from ambient light and 1/f noise. In a breath hold and release experiment the single chip sensor demonstrates consistent and comparable performance to commercial pulse oximetry devices with a mean of 1.2% difference. The single-chip sensor enables a compact and robust design solution that offers a route towards wearable devices for health monitoring.

A Single-Chip CMOS Pulse Oximeter with On-Chip Lock-In Detection.

Science.gov (United States)

He, Diwei; Morgan, Stephen P; Trachanis, Dimitrios; van Hese, Jan; Drogoudis, Dimitris; Fummi, Franco; Stefanni, Francesco; Guarnieri, Valerio; Hayes-Gill, Barrie R

2015-07-14

Pulse oximetry is a noninvasive and continuous method for monitoring the blood oxygen saturation level. This paper presents the design and testing of a single-chip pulse oximeter fabricated in a 0.35 µm CMOS process. The chip includes photodiode, transimpedance amplifier, analogue band-pass filters, analogue-to-digital converters, digital signal processor and LED timing control. The experimentally measured AC and DC characteristics of individual circuits including the DC output voltage of the transimpedance amplifier, transimpedance gain of the transimpedance amplifier, and the central frequency and bandwidth of the analogue band-pass filters, show a good match (within 1%) with the circuit simulations. With modulated light source and integrated lock-in detection the sensor effectively suppresses the interference from ambient light and 1/f noise. In a breath hold and release experiment the single chip sensor demonstrates consistent and comparable performance to commercial pulse oximetry devices with a mean of 1.2% difference. The single-chip sensor enables a compact and robust design solution that offers a route towards wearable devices for health monitoring.

Very large scale heterogeneous integration (VLSHI) and wafer-level vacuum packaging for infrared bolometer focal plane arrays

Science.gov (United States)

Forsberg, Fredrik; Roxhed, Niclas; Fischer, Andreas C.; Samel, Björn; Ericsson, Per; Hoivik, Nils; Lapadatu, Adriana; Bring, Martin; Kittilsland, Gjermund; Stemme, Göran; Niklaus, Frank

2013-09-01

Imaging in the long wavelength infrared (LWIR) range from 8 to 14 μm is an extremely useful tool for non-contact measurement and imaging of temperature in many industrial, automotive and security applications. However, the cost of the infrared (IR) imaging components has to be significantly reduced to make IR imaging a viable technology for many cost-sensitive applications. This paper demonstrates new and improved fabrication and packaging technologies for next-generation IR imaging detectors based on uncooled IR bolometer focal plane arrays. The proposed technologies include very large scale heterogeneous integration for combining high-performance, SiGe quantum-well bolometers with electronic integrated read-out circuits and CMOS compatible wafer-level vacuum packing. The fabrication and characterization of bolometers with a pitch of 25 μm × 25 μm that are arranged on read-out-wafers in arrays with 320 × 240 pixels are presented. The bolometers contain a multi-layer quantum well SiGe thermistor with a temperature coefficient of resistance of -3.0%/K. The proposed CMOS compatible wafer-level vacuum packaging technology uses Cu-Sn solid-liquid interdiffusion (SLID) bonding. The presented technologies are suitable for implementation in cost-efficient fabless business models with the potential to bring about the cost reduction needed to enable low-cost IR imaging products for industrial, security and automotive applications.

Hybridization of active and passive elements for planar photonic components and interconnects

Science.gov (United States)

Pearson, M.; Bidnyk, S.; Balakrishnan, A.

2007-02-01

The deployment of Passive Optical Networks (PON) for Fiber-to-the-Home (FTTH) applications currently represents the fastest growing sector of the telecommunication industry. Traditionally, FTTH transceivers have been manufactured using commodity bulk optics subcomponents, such as thin film filters (TFFs), micro-optic collimating lenses, TO-packaged lasers, and photodetectors. Assembling these subcomponents into a single housing requires active alignment and labor-intensive techniques. Today, the majority of cost reducing strategies using bulk subcomponents has been implemented making future reductions in the price of manufacturing FTTH transceivers unlikely. Future success of large scale deployments of FTTH depends on further cost reductions of transceivers. Realizing the necessity of a radically new packaging approach for assembly of photonic components and interconnects, we designed a novel way of hybridizing active and passive elements into a planar lightwave circuit (PLC) platform. In our approach, all the filtering components were monolithically integrated into the chip using advancements in planar reflective gratings. Subsequently, active components were passively hybridized with the chip using fully-automated high-capacity flip-chip bonders. In this approach, the assembly of the transceiver package required no active alignment and was readily suitable for large-scale production. This paper describes the monolithic integration of filters and hybridization of active components in both silica-on-silicon and silicon-on-insulator PLCs.

Model 9975 Life Extension Package 1 - Final Report

International Nuclear Information System (INIS)

Daugherty, W.

2011-01-01

Life extension package LE1 (9975-03382) was instrumented and subjected to a temperature/humidity environment that bounds KAMS package storage conditions for 92 weeks. During this time, the maximum fiberboard temperature was ∼180 F, and was established by a combination of internal heat (12 watts) and external heat (∼142 F). The relative humidity external to the package was maintained at 80 %RH. This package was removed from test in November 2010 after several degraded conditions were observed during a periodic examination. These conditions included degraded fiberboard (easily broken, bottom layer stuck to the drum), corrosion of the drum, and separation of the air shield from the upper fiberboard assembly. Several tests and parameters were used to characterize the package components. Results from these tests generally indicate agreement between this full-scale shipping package and small-scale laboratory tests on fiberboard and O-ring samples. These areas of agreement include the rate of fiberboard weight loss, change in fiberboard thermal conductivity, fiberboard compression strength, and O-ring compression set. In addition, this package provides an example of the extent to which moisture within the fiberboard can redistribute in the presence of a temperature gradient such as might be created by a 12 watt internal heat load. Much of the moisture near the fiberboard ID surface migrated towards the OD surface, but there was not a significant axial moisture gradient during most of the test duration. Only during the last inspection period (i.e. after 92 weeks exposure during the second phase) did enough moisture migrate to the bottom fiberboard layers to cause saturation. A side effect of moisture migration is the leaching of soluble compounds from the fiberboard. In particular, the corrosion observed on the drum appears related primarily to the leaching and concentration of chlorides. In most locations, this attack appears to be general corrosion, with shallow

Model 9975 Life Extension Test Package 3 - Interim Report - January 2017

Energy Technology Data Exchange (ETDEWEB)

Daugherty, W. [Savannah River Site (SRS), Aiken, SC (United States). Savannah River National Lab. (SRNL)

2017-01-31

Life extension package LE3 (9975-03203) has been instrumented and subjected to an elevated temperature environment for approximately 8 years. During this time, the cane fiberboard has been maintained at a maximum temperature of ~160 - 165 °F, which was established by a combination of internal (19 watts) and external heat sources. Several tests and parameters were used to characterize the package components. Results from these tests generally indicate agreement between this full-scale shipping package and small-scale laboratory tests on fiberboard samples, including the degradation models based on the laboratory tests. These areas of agreement include the rate of change of fiberboard weight, dimensions and density, and change in fiberboard thermal conductivity. Corrosion of the lead shield occurred at a high rate during the first several weeks of aging, but dropped significantly after most of the moisture in the fiberboard migrated away from the lead shield. Dimensional measurements of the lead shield indicate that no significant creep deformation has occurred. This is consistent with literature data that predict a very small creep deformation for the time at temperature experienced by this package. The SCV O-rings were verified to remain leak-tight after ~5 years aging at an average temperature of ~170 °F. This package provides an example of the extent to which moisture within a typical fiberboard assembly can redistribute in the presence of a temperature gradient such as might be created by a 19 watt internal heat load. The majority of water within the fiberboard migrated to the bottom layers of fiberboard, with approximately 2 kg of water (2 liters) eventually escaping from the package. Two conditions have developed that are not consistent with package certification requirements. The axial gap at the top of the package increased to a maximum value of 1.549 inches, exceeding the 1 inch criterion. In addition, staining and/or corrosion have formed in a few spots

Lab-on a-Chip

Science.gov (United States)

1999-01-01

Labs on chips are manufactured in many shapes and sizes and can be used for numerous applications, from medical tests to water quality monitoring to detecting the signatures of life on other planets. The eight holes on this chip are actually ports that can be filled with fluids or chemicals. Tiny valves control the chemical processes by mixing fluids that move in the tiny channels that look like lines, connecting the ports. Scientists at NASA's Marshall Space Flight Center (MSFC) in Huntsville, Alabama designed this chip to grow biological crystals on the International Space Station (ISS). Through this research, they discovered that this technology is ideally suited for solving the challenges of the Vision for Space Exploration. For example, thousands of chips the size of dimes could be loaded on a Martian rover looking for biosignatures of past or present life. Other types of chips could be placed in handheld devices used to monitor microbes in water or to quickly conduct medical tests on astronauts. The portable, handheld Lab-on-a Chip Application Development Portable Test System (LOCAD-PTS) made its debut flight aboard Discovery during the STS-116 mission launched December 9, 2006. The system allowed crew members to monitor their environment for problematic contaminants such as yeast, mold, and even E.coli, and salmonella. Once LOCAD-PTS reached the ISS, the Marshall team continued to manage the experiment, monitoring the study from a console in the Payload Operations Center at MSFC. The results of these studies will help NASA researchers refine the technology for future Moon and Mars missions. (NASA/MSFC/D.Stoffer)

All-polymer organic semiconductor laser chips: Parallel fabrication and encapsulation

DEFF Research Database (Denmark)

Vannahme, Christoph; Klinkhammer, Sönke; Christiansen, Mads Brøkner

2010-01-01

Organic semiconductor lasers are of particular interest as tunable visible laser light sources. For bringing those to market encapsulation is needed to ensure practicable lifetimes. Additionally, fabrication technologies suitable for mass production must be used. We introduce all-polymer chips...... comprising encapsulated distributed feedback organic semiconductor lasers. Several chips are fabricated in parallel by thermal nanoimprint of the feedback grating on 4? wafer scale out of poly(methyl methacrylate) (PMMA) and cyclic olefin copolymer (COC). The lasers consisting of the organic semiconductor...... tris(8- hydroxyquinoline) aluminum (Alq3) doped with the laser dye 4-dicyanomethylene-2- methyl-6-(p-dimethylaminostyril)-4H-pyrane (DCM) are hermetically sealed by thermally bonding a polymer lid. The organic thin film is placed in a basin within the substrate and is not in direct contact to the lid...

A coral-on-a-chip microfluidic platform enabling live-imaging microscopy of reef-building corals

Science.gov (United States)

Shapiro, Orr H.; Kramarsky-Winter, Esti; Gavish, Assaf R.; Stocker, Roman; Vardi, Assaf

2016-01-01

Coral reefs, and the unique ecosystems they support, are facing severe threats by human activities and climate change. Our understanding of these threats is hampered by the lack of robust approaches for studying the micro-scale interactions between corals and their environment. Here we present an experimental platform, coral-on-a-chip, combining micropropagation and microfluidics to allow direct microscopic study of live coral polyps. The small and transparent coral micropropagates are ideally suited for live-imaging microscopy, while the microfluidic platform facilitates long-term visualization under controlled environmental conditions. We demonstrate the usefulness of this approach by imaging coral micropropagates at previously unattainable spatio-temporal resolutions, providing new insights into several micro-scale processes including coral calcification, coral–pathogen interaction and the loss of algal symbionts (coral bleaching). Coral-on-a-chip thus provides a powerful method for studying coral physiology in vivo at the micro-scale, opening new vistas in coral biology. PMID:26940983

Design of analog front-ends for the RD53 demonstrator chip

CERN Document Server

Gaioni, L; Nodari, B; Manghisoni, M; Re, V; Traversi, G; Barbero, M B; Fougeron, D; Gensolen, F; Godiot, S; Menouni, M; Pangaud, P; Rozanov, A; Wang, A; Bomben, M; Calderini, G; Crescioli, F; Le Dortz, O; Marchiori, G; Dzahini, D; Rarbi, F E; Gaglione, R; Gonella, L; Hemperek, T; Huegging, F; Karagounis, M; Kishishita, T; Krueger, H; Rymaszewski, P; Wermes, N; Ciciriello, F; Corsi, F; Marzocca, C; De Robertis, G; Loddo, F; Licciulli, F; Andreazza, A; Liberali, V; Shojaii, S; Stabile, A; Bagatin, M; Bisello, D; Mattiazzo, S; Ding, L; Gerardin, S; Giubilato, P; Neviani, A; Paccagnella, A; Vogrig, D; Wyss, J; Bacchetta, N; Della Casa, G; Demaria, N; Mazza, G; Rivetti, A; Da Rocha Rolo, M D; Comotti, D; Ratti, L; Vacchi, C; Beccherle, R; Bellazzini, R; Magazzu, G; Minuti, M; Morsani, F; Palla, F; Poulios, S; Fanucci, L; Rizzi, A; Saponara, S; Androsov, K; Bilei, G M; Menichelli, M; Conti, E; Marconi, S; Passeri, D; Placidi, P; Monteil, E; Pacher, L; Paternò, A; Gajanana, D; Gromov, V; Hessey, N; Kluit, R; Zivkovic, V; Havranek, M; Janoska, Z; Marcisovsky, M; Neue, G; Tomasek, L; Kafka, V; Sicho, P; Vrba, V; Vila, I; Lopez-Morillo, E; Aguirre, M A; Palomo, F R; Muñoz, F; Abbaneo, D; Christiansen, J; Dannheim, D; Dobos, D; Linssen, L; Pernegger, H; Valerio, P; Alipour Tehrani, N; Bell, S; Prydderch, M L; Thomas, S; Christian, D C; Fahim, F; Hoff, J; Lipton, R; Liu, T; Zimmerman, T; Garcia-Sciveres, M; Gnani, D; Mekkaoui, A; Gorelov, I; Hoeferkamp, M; Seidel, S; Toms, K; De Witt, J N; Grillo, A

2017-01-01

The RD53 collaboration is developing a large scale pixel front-end chip, which will be a tool to evaluate the performance of 65 nm CMOS technology in view of its application to the readout of the innermost detector layers of ATLAS and CMS at the HL-LHC. Experimental results of the characterization of small prototypes will be discussed in the frame of the design work that is currently leading to the development of the large scale demonstrator chip RD53A to be submitted in early 2017. The paper is focused on the analog processors developed in the framework of the RD53 collaboration, including three time over threshold front-ends, designed by INFN Torino and Pavia, University of Bergamo and LBNL and a zero dead time front-end based on flash ADC designed by a joint collaboration between the Fermilab and INFN. The paper will also discuss the radiation tolerance features of the front-end channels, which were exposed to up to 800 Mrad of total ionizing dose to reproduce the system operation in the actual experiment.

Liquid-Phase Packaging of a Glucose Oxidase Solution with Parylene Direct Encapsulation and an Ultraviolet Curing Adhesive Cover for Glucose Sensors

Directory of Open Access Journals (Sweden)

Seiichi Takamatsu

2010-06-01

Full Text Available We have developed a package for disposable glucose sensor chips using Parylene encapsulation of a glucose oxidase solution in the liquid phase and a cover structure made of an ultraviolet (UV curable adhesive. Parylene was directly deposited onto a small volume (1 μL of glucose oxidase solution through chemical vapor deposition. The cover and reaction chamber were constructed on Parylene film using a UV-curable adhesive and photolithography. The package was processed at room temperature to avoid denaturation of the glucose oxidase. The glucose oxidase solution was encapsulated and unsealed. Glucose sensing was demonstrated using standard amperometric detection at glucose concentrations between 0.1 and 100 mM, which covers the glucose concentration range of diabetic patients. Our proposed Parylene encapsulation and UV-adhesive cover form a liquid phase glucose-oxidase package that has the advantages of room temperature processing and direct liquid encapsulation of a small volume solution without use of conventional solidifying chemicals.

High-power, format-flexible, 885-nm vertical-cavity surface-emitting laser arrays

Science.gov (United States)

Wang, Chad; Talantov, Fedor; Garrett, Henry; Berdin, Glen; Cardellino, Terri; Millenheft, David; Geske, Jonathan

2013-03-01

High-power, format flexible, 885 nm vertical-cavity surface-emitting laser (VCSEL) arrays have been developed for solid-state pumping and illumination applications. In this approach, a common VCSEL size format was designed to enable tiling into flexible formats and operating configurations. The fabrication of a common chip size on ceramic submount enables low-cost volume manufacturing of high-power VCSEL arrays. This base VCSEL chip was designed to be 5x3.33 mm2, and produced up to 50 Watts of peak continuous wave (CW) power. To scale to higher powers, multiple chips can be tiled into a combination of series or parallel configurations tailored to the application driver conditions. In actively cooled CW operation, the VCSEL array chips were packaged onto a single water channel cooler, and we have demonstrated 0.5x1, 1x1, and 1x3 cm2 formats, producing 150, 250, and 500 Watts of peak power, respectively, in under 130 A operating current. In QCW operation, the 1x3 cm2 VCSEL module, which contains 18 VCSEL array chips packaged on a single water cooler, produced over 1.3 kW of peak power. In passively cooled packages, multiple chip configurations have been developed for illumination applications, producing over 300 Watts of peak power in QCW operating conditions. These VCSEL chips use a substrate-removed structure to allow for efficient thermal heatsinking to enable high-power operation. This scalable, format flexible VCSEL architecture can be applied to wavelengths ranging from 800 to 1100 nm, and can be used to tailor emission spectral widths and build high-power hyperspectral sources.

Diode temperature sensor array for measuring and controlling micro scale surface temperature

International Nuclear Information System (INIS)

Han, Il Young; Kim, Sung Jin

2004-01-01

The needs of micro scale thermal detecting technique are increasing in biology and chemical industry. For example, thermal finger print, Micro PCR(Polymer Chain Reaction), TAS and so on. To satisfy these needs, we developed a DTSA(Diode Temperature Sensor Array) for detecting and controlling the temperature on small surface. The DTSA is fabricated by using VLSI technique. It consists of 32 array of diodes(1,024 diodes) for temperature detection and 8 heaters for temperature control on a 8mm surface area. The working principle of temperature detection is that the forward voltage drop across a silicon diode is approximately proportional to the inverse of the absolute temperature of diode. And eight heaters (1K) made of poly-silicon are added onto a silicon wafer and controlled individually to maintain a uniform temperature distribution across the DTSA. Flip chip packaging used for easy connection of the DTSA. The circuitry for scanning and controlling DTSA are also developed

Optimal selection of TLD chips

International Nuclear Information System (INIS)

Phung, P.; Nicoll, J.J.; Edmonds, P.; Paris, M.; Thompson, C.

1996-01-01

Large sets of TLD chips are often used to measure beam dose characteristics in radiotherapy. A sorting method is presented to allow optimal selection of chips from a chosen set. This method considers the variation

Evaluating laser-driven Bremsstrahlung radiation sources for imaging and analysis of nuclear waste packages.

Science.gov (United States)

Jones, Christopher P; Brenner, Ceri M; Stitt, Camilla A; Armstrong, Chris; Rusby, Dean R; Mirfayzi, Seyed R; Wilson, Lucy A; Alejo, Aarón; Ahmed, Hamad; Allott, Ric; Butler, Nicholas M H; Clarke, Robert J; Haddock, David; Hernandez-Gomez, Cristina; Higginson, Adam; Murphy, Christopher; Notley, Margaret; Paraskevoulakos, Charilaos; Jowsey, John; McKenna, Paul; Neely, David; Kar, Satya; Scott, Thomas B

2016-11-15

A small scale sample nuclear waste package, consisting of a 28mm diameter uranium penny encased in grout, was imaged by absorption contrast radiography using a single pulse exposure from an X-ray source driven by a high-power laser. The Vulcan laser was used to deliver a focused pulse of photons to a tantalum foil, in order to generate a bright burst of highly penetrating X-rays (with energy >500keV), with a source size of <0.5mm. BAS-TR and BAS-SR image plates were used for image capture, alongside a newly developed Thalium doped Caesium Iodide scintillator-based detector coupled to CCD chips. The uranium penny was clearly resolved to sub-mm accuracy over a 30cm(2) scan area from a single shot acquisition. In addition, neutron generation was demonstrated in situ with the X-ray beam, with a single shot, thus demonstrating the potential for multi-modal criticality testing of waste materials. This feasibility study successfully demonstrated non-destructive radiography of encapsulated, high density, nuclear material. With recent developments of high-power laser systems, to 10Hz operation, a laser-driven multi-modal beamline for waste monitoring applications is envisioned. Copyright © 2016. Published by Elsevier B.V.

Identification and characterisation of factors affecting losses in the large-scale, non-ventilated bulk storage of wood chips and development of best storage practices

Energy Technology Data Exchange (ETDEWEB)

Garstang, J.; Weekes, A.; Poulter, R.; Bartlett, D.

2002-07-01

The report describes the findings of a study to determine the factors affecting the commercial storage of wood chips for biomass power generation in the UK. The UK's first such plant in North Yorkshire uses a mixture of forestry residues and short rotation coppice (SRC) willow, where problems with the stored fuel highlighted the need to determine best storage practices. Two wood chip piles were built (one with willow chip and the other with wood chips from board leaf forestry residues) and monitored (moisture, temperature, chemical composition, spore numbers and species, heat and air flows, bulk density, etc). Local weather data was also obtained. Recommendations for future storage practices are made.

Chip-Scale Bioassays Based on Surface-Enhanced Raman Scattering: Fundamentals and Applications

Energy Technology Data Exchange (ETDEWEB)

Park, Hye-Young [Iowa State Univ., Ames, IA (United States)

2005-01-01

This work explores the development and application of chip-scale bioassays based on surface-enhanced Raman scattering (SERS) for high throughput and high sensitivity analysis of biomolecules. The size effect of gold nanoparticles on the intensity of SERS is first presented. A sandwich immunoassay was performed using Raman-labeled immunogold nanoparticles with various sizes. The SERS responses were correlated to particle densities, which were obtained by atomic force microscopy (AFM). The response of individual particles was also investigated using Raman-microscope and an array of gold islands on a silicon substrate. The location and the size of individual particles were mapped using AFM. The next study describes a low-level detection of Escherichia coli 0157:H7 and simulants of biological warfare agents in a sandwich immunoassay format using SERS labels, which have been termed Extrinsic Raman labels (ERLs). A new ERL scheme based on a mixed monolayer is also introduced. The mixed monolayer ERLs were created by covering the gold nanoparticles with a mixture of two thiolates, one thiolate for covalently binding antibody to the particle and the other thiolate for producing a strong Raman signal. An assay platform based on mixed self-assembled monolayers (SAMs) on gold is then presented. The mixed SAMs were prepared from dithiobis(succinimidyl undecanoate) (DSU) to covalently bind antibodies on gold substrate and oligo(ethylene glycol)-terminated thiol to prevent nonspecific adsorption of antibodies. After the mixed SAMs surfaces, formed from various mole fraction of DSU were incubated with antibodies, AFM was used to image individual antibodies on the surface. The final study presents a collaborative work on the single molecule adsorption of YOYO-I labeled {lambda}-DNA at compositionally patterned SAMs using total internal reflection fluorescence microscopy. The role of solution pH, {lambda}-DNA concentration, and domain size was investigated. This work also revealed

Experiment list: SRX110782 [Chip-atlas[Archive

Lifescience Database Archive (English)

Full Text Available e3 (ab6002, abcam), Pol II (CTD4H8, Millipore) || chip antibody 1 manufacturer=ab...cam || chip antibody 2=Pol II (CTD4H8, Millipore) || chip antibody 2 manufacturer=Millipore http://dbarchive

Fully Automated On-Chip Imaging Flow Cytometry System with Disposable Contamination-Free Plastic Re-Cultivation Chip

Directory of Open Access Journals (Sweden)

Tomoyuki Kaneko

2011-06-01

Full Text Available We have developed a novel imaging cytometry system using a poly(methyl methacrylate (PMMA based microfluidic chip. The system was contamination-free, because sample suspensions contacted only with a flammable PMMA chip and no other component of the system. The transparency and low-fluorescence of PMMA was suitable for microscopic imaging of cells flowing through microchannels on the chip. Sample particles flowing through microchannels on the chip were discriminated by an image-recognition unit with a high-speed camera in real time at the rate of 200 event/s, e.g., microparticles 2.5 μm and 3.0 μm in diameter were differentiated with an error rate of less than 2%. Desired cells were separated automatically from other cells by electrophoretic or dielectrophoretic force one by one with a separation efficiency of 90%. Cells in suspension with fluorescent dye were separated using the same kind of microfluidic chip. Sample of 5 μL with 1 × 106 particle/mL was processed within 40 min. Separated cells could be cultured on the microfluidic chip without contamination. The whole operation of sample handling was automated using 3D micropipetting system. These results showed that the novel imaging flow cytometry system is practically applicable for biological research and clinical diagnostics.

MEMS packaging

CERN Document Server

Hsu , Tai-Ran

2004-01-01

MEMS Packaging discusses the prevalent practices and enabling techniques in assembly, packaging and testing of microelectromechanical systems (MEMS). The entire spectrum of assembly, packaging and testing of MEMS and microsystems, from essential enabling technologies to applications in key industries of life sciences, telecommunications and aerospace engineering is covered. Other topics included are bonding and sealing of microcomponents, process flow of MEMS and microsystems packaging, automated microassembly, and testing and design for testing.The Institution of Engineering and Technology is

In situ TEM/SEM electronic/mechanical characterization of nano material with MEMS chip

International Nuclear Information System (INIS)

Wang Yuelin; Li Tie; Zhang Xiao; Zeng Hongjiang; Jin Qinhua

2014-01-01

Our investigation of in situ observations on electronic and mechanical properties of nano materials using a scanning electron microscope (SEM) and a transmission electron microscope (TEM) with the help of traditional micro-electro-mechanical system (MEMS) technology has been reviewed. Thanks to the stability, continuity and controllability of the loading force from the electrostatic actuator and the sensitivity of the sensor beam, a MEMS tensile testing chip for accurate tensile testing in the nano scale is obtained. Based on the MEMS chips, the scale effect of Young's modulus in silicon has been studied and confirmed directly in a tensile experiment using a transmission electron microscope. Employing the nanomanipulation technology and FIB technology, Cu and SiC nanowires have been integrated into the tensile testing device and their mechanical, electronic properties under different stress have been achieved, simultaneously. All these will aid in better understanding the nano effects and contribute to the designation and application in nano devices. (invited papers)

Packaging design criteria for the Hanford Ecorok Packaging

International Nuclear Information System (INIS)

Mercado, M.S.

1996-01-01

The Hanford Ecorok Packaging (HEP) will be used to ship contaminated water purification filters from K Basins to the Central Waste Complex. This packaging design criteria documents the design of the HEP, its intended use, and the transportation safety criteria it is required to meet. This information will serve as a basis for the safety analysis report for packaging

Wood chip production technology and costs for fuel in Namibia

Energy Technology Data Exchange (ETDEWEB)

Leinonen, A.

2007-12-15

steer and Nisula harvester head for felling, were tested at CCF. The most effective felling device in the tests appeared to be rotary saw in the skid steer. Based on these tests it was designed a new totally mechanized production chain. The working phases in this mechanized production chain are felling with a rotary saw in skid steer, compiling with a grapple fork in skid steer, drying in the heaps, chipping with a mobile chipper with a loader and road transport with a tractor trailer. This new production chain is not fully tested in Namibia. The calculated production and road transport costs of wood chips with the designed new mechanized production chain are about 15% lower than those of the semi-mechanized production chain. The production costs with the new mechanized production chain are 170.5 N dollar/wet ton (4.4 Euros/MWh) for 5 MWe power plant, 181.4 N dollar/wet ton (4.7 Euros/MWh) for 10 MWe power plant and 192.3 N dollar/wet ton (4.9 Euros/MWh) for 20 MWe power plant. The average road transport distance in the calculation is 30 km for a 5 MWe, 40 km for 10 MWe and 50 km for 20 MWe power plants. The production and road transport costs of wood chips from Okahandja to Van Eck power plant are 238.4 N dollar/wet ton (6.1 Euros/MWh) and from Otjiwarongo 350.3 N dollar/wet ton (9.0 Euros/MWh using the new mechanized wood chip production chain. The wet ton and MWh units are presented in 20 w-% moisture content. The designed mechanized production chain is very effective and suitable for large-scale wood chip production. With the new mechanized production chain the labour force demand of producing wood chips is 32 men for a 5 MWe, 65 men for 10 MWe and 136 men for 20 MWe power plant. The average yield in selective bush harvesting at CCF was 7.0 wet tons (20 w-%) per hectare. The annual total wood chip production area is 4 600 ha in the case of a 5 MWe power plant, 8 600 ha for a 10 MWe and 16 900 ha for 20 MWe power plant if the harvesting yield is 7.0 wet tons per ha

Normalization and experimental design for ChIP-chip data

Directory of Open Access Journals (Sweden)

Alekseyenko Artyom A

2007-06-01

Full Text Available Abstract Background Chromatin immunoprecipitation on tiling arrays (ChIP-chip has been widely used to investigate the DNA binding sites for a variety of proteins on a genome-wide scale. However, several issues in the processing and analysis of ChIP-chip data have not been resolved fully, including the effect of background (mock control subtraction and normalization within and across arrays. Results The binding profiles of Drosophila male-specific lethal (MSL complex on a tiling array provide a unique opportunity for investigating these topics, as it is known to bind on the X chromosome but not on the autosomes. These large bound and control regions on the same array allow clear evaluation of analytical methods. We introduce a novel normalization scheme specifically designed for ChIP-chip data from dual-channel arrays and demonstrate that this step is critical for correcting systematic dye-bias that may exist in the data. Subtraction of the mock (non-specific antibody or no antibody control data is generally needed to eliminate the bias, but appropriate normalization obviates the need for mock experiments and increases the correlation among replicates. The idea underlying the normalization can be used subsequently to estimate the background noise level in each array for normalization across arrays. We demonstrate the effectiveness of the methods with the MSL complex binding data and other publicly available data. Conclusion Proper normalization is essential for ChIP-chip experiments. The proposed normalization technique can correct systematic errors and compensate for the lack of mock control data, thus reducing the experimental cost and producing more accurate results.

A study on effects of packaging characteristics on consumer's purchasing confidence

Directory of Open Access Journals (Sweden)

Naser Azad

2012-01-01

Full Text Available Packaging plays an important role on marketing products and services in many competitive environments. A good packaging can increase sales of products, reduces the level of inventory, which yields to higher profitability. In this paper, we study the relationship between a good packaging program and customer's confidence as well as customer's attraction on purchasing goods and services. The paper uses a questionnaire based on Likert scale and distributes among the target population of this survey and the information of packaging are divided into two groups of visibility and informative. The results indicate that a good and label with detailed and precise information on product could significantly impact customer's confidence while other visible information do not have much impact on customer's confidence.