Property-driven functional verification technique for high-speed vision system-on-chip processor

Science.gov (United States)

Nshunguyimfura, Victor; Yang, Jie; Liu, Liyuan; Wu, Nanjian

2017-04-01

The implementation of functional verification in a fast, reliable, and effective manner is a challenging task in a vision chip verification process. The main reason for this challenge is the stepwise nature of existing functional verification techniques. This vision chip verification complexity is also related to the fact that in most vision chip design cycles, extensive efforts are focused on how to optimize chip metrics such as performance, power, and area. Design functional verification is not explicitly considered at an earlier stage at which the most sound decisions are made. In this paper, we propose a semi-automatic property-driven verification technique. The implementation of all verification components is based on design properties. We introduce a low-dimension property space between the specification space and the implementation space. The aim of this technique is to speed up the verification process for high-performance parallel processing vision chips. Our experimentation results show that the proposed technique can effectively improve the verification effort up to 20% for the complex vision chip design while reducing the simulation and debugging overheads.

A data acquisition and control system for high-speed gamma-ray tomography

Science.gov (United States)

Hjertaker, B. T.; Maad, R.; Schuster, E.; Almås, O. A.; Johansen, G. A.

2008-09-01

A data acquisition and control system (DACS) for high-speed gamma-ray tomography based on the USB (Universal Serial Bus) and Ethernet communication protocols has been designed and implemented. The high-speed gamma-ray tomograph comprises five 500 mCi 241Am gamma-ray sources, each at a principal energy of 59.5 keV, which corresponds to five detector modules, each consisting of 17 CdZnTe detectors. The DACS design is based on Microchip's PIC18F4550 and PIC18F4620 microcontrollers, which facilitates an USB 2.0 interface protocol and an Ethernet (IEEE 802.3) interface protocol, respectively. By implementing the USB- and Ethernet-based DACS, a sufficiently high data acquisition rate is obtained and no dedicated hardware installation is required for the data acquisition computer, assuming that it is already equipped with a standard USB and/or Ethernet port. The API (Application Programming Interface) for the DACS is founded on the National Instrument's LabVIEW® graphical development tool, which provides a simple and robust foundation for further application software developments for the tomograph. The data acquisition interval, i.e. the integration time, of the high-speed gamma-ray tomograph is user selectable and is a function of the statistical measurement accuracy required for the specific application. The bandwidth of the DACS is 85 kBytes s-1 for the USB communication protocol and 28 kBytes s-1 for the Ethernet protocol. When using the iterative least square technique reconstruction algorithm with a 1 ms integration time, the USB-based DACS provides an online image update rate of 38 Hz, i.e. 38 frames per second, whereas 31 Hz for the Ethernet-based DACS. The off-line image update rate (storage to disk) for the USB-based DACS is 278 Hz using a 1 ms integration time. Initial characterization of the high-speed gamma-ray tomograph using the DACS on polypropylene phantoms is presented in the paper.

A data acquisition and control system for high-speed gamma-ray tomography

International Nuclear Information System (INIS)

Hjertaker, B T; Maad, R; Schuster, E; Almås, O A; Johansen, G A

2008-01-01

A data acquisition and control system (DACS) for high-speed gamma-ray tomography based on the USB (Universal Serial Bus) and Ethernet communication protocols has been designed and implemented. The high-speed gamma-ray tomograph comprises five 500 mCi 241 Am gamma-ray sources, each at a principal energy of 59.5 keV, which corresponds to five detector modules, each consisting of 17 CdZnTe detectors. The DACS design is based on Microchip's PIC18F4550 and PIC18F4620 microcontrollers, which facilitates an USB 2.0 interface protocol and an Ethernet (IEEE 802.3) interface protocol, respectively. By implementing the USB- and Ethernet-based DACS, a sufficiently high data acquisition rate is obtained and no dedicated hardware installation is required for the data acquisition computer, assuming that it is already equipped with a standard USB and/or Ethernet port. The API (Application Programming Interface) for the DACS is founded on the National Instrument's LabVIEW® graphical development tool, which provides a simple and robust foundation for further application software developments for the tomograph. The data acquisition interval, i.e. the integration time, of the high-speed gamma-ray tomograph is user selectable and is a function of the statistical measurement accuracy required for the specific application. The bandwidth of the DACS is 85 kBytes s −1 for the USB communication protocol and 28 kBytes s −1 for the Ethernet protocol. When using the iterative least square technique reconstruction algorithm with a 1 ms integration time, the USB-based DACS provides an online image update rate of 38 Hz, i.e. 38 frames per second, whereas 31 Hz for the Ethernet-based DACS. The off-line image update rate (storage to disk) for the USB-based DACS is 278 Hz using a 1 ms integration time. Initial characterization of the high-speed gamma-ray tomograph using the DACS on polypropylene phantoms is presented in the paper

Method of mechanical holding of cantilever chip for tip-scan high-speed atomic force microscope

Energy Technology Data Exchange (ETDEWEB)

Fukuda, Shingo [Department of Physics, College of Science and Engineering, Kanazawa University, Kakuma-machi, Kanazawa 920-1192 (Japan); Uchihashi, Takayuki; Ando, Toshio [Department of Physics, College of Science and Engineering, Kanazawa University, Kakuma-machi, Kanazawa 920-1192 (Japan); Bio-AFM Frontier Research Center, College of Science and Engineering, Kanazawa University, Kakuma-machi, Kanazawa 920-1192 (Japan); Core Research for Evolutional Science and Technology of the Japan Science and Technology Agency, 7 Goban-cho, Chiyoda-ku, Tokyo 102-0076 (Japan)

2015-06-15

In tip-scan atomic force microscopy (AFM) that scans a cantilever chip in the three dimensions, the chip body is held on the Z-scanner with a holder. However, this holding is not easy for high-speed (HS) AFM because the holder that should have a small mass has to be able to clamp the cantilever chip firmly without deteriorating the Z-scanner’s fast performance, and because repeated exchange of cantilever chips should not damage the Z-scanner. This is one of the reasons that tip-scan HS-AFM has not been established, despite its advantages over sample stage-scan HS-AFM. Here, we present a novel method of cantilever chip holding which meets all conditions required for tip-scan HS-AFM. The superior performance of this novel chip holding mechanism is demonstrated by imaging of the α{sub 3}β{sub 3} subcomplex of F{sub 1}-ATPase in dynamic action at ∼7 frames/s.

FPGA communications based on Gigabit Ethernet

International Nuclear Information System (INIS)

Doolittle, L.R.; Serrano, C.

2012-01-01

The use of Field Programmable Gate Arrays (FPGAs) in accelerators is widespread due to their flexibility, performance, and reasonable costs. Whether they are used for fast feedback systems, data acquisition, fast communications using custom protocols, or any other application, there is a need for the end-user and the global control software to access FPGA features using a commodity computer. The choice of communication standards that can be used to interface to a FPGA board is wide, however there is one that stands out for its maturity, basis in standards, performance, and hardware support: Gigabit Ethernet. In the context of accelerators it is desirable to have highly reliable, portable, and flexible solutions. We have therefore developed a chip and board-independent FPGA design which implements the Gigabit Ethernet (GbE) standard. Our design has been configured for use with multiple projects, supports full line-rate traffic, and communicates with any other device implementing the same well-established protocol, easily supported by any modern workstation or controls computer. (authors)

A high-speed on-chip pseudo-random binary sequence generator for multi-tone phase calibration

Science.gov (United States)

Gommé, Liesbeth; Vandersteen, Gerd; Rolain, Yves

2011-07-01

An on-chip reference generator is conceived by adopting the technique of decimating a pseudo-random binary sequence (PRBS) signal in parallel sequences. This is of great benefit when high-speed generation of PRBS and PRBS-derived signals is the objective. The design implemented standard CMOS logic is available in commercial libraries to provide the logic functions for the generator. The design allows the user to select the periodicity of the PRBS and the PRBS-derived signals. The characterization of the on-chip generator marks its performance and reveals promising specifications.

A high-speed on-chip pseudo-random binary sequence generator for multi-tone phase calibration

International Nuclear Information System (INIS)

Gommé, Liesbeth; Vandersteen, Gerd; Rolain, Yves

2011-01-01

An on-chip reference generator is conceived by adopting the technique of decimating a pseudo-random binary sequence (PRBS) signal in parallel sequences. This is of great benefit when high-speed generation of PRBS and PRBS-derived signals is the objective. The design implemented standard CMOS logic is available in commercial libraries to provide the logic functions for the generator. The design allows the user to select the periodicity of the PRBS and the PRBS-derived signals. The characterization of the on-chip generator marks its performance and reveals promising specifications

CHEETAH: circuit-switched high-speed end-to-end transport architecture

Science.gov (United States)

Veeraraghavan, Malathi; Zheng, Xuan; Lee, Hyuk; Gardner, M.; Feng, Wuchun

2003-10-01

Leveraging the dominance of Ethernet in LANs and SONET/SDH in MANs and WANs, we propose a service called CHEETAH (Circuit-switched High-speed End-to-End Transport ArcHitecture). The service concept is to provide end hosts with high-speed, end-to-end circuit connectivity on a call-by-call shared basis, where a "circuit" consists of Ethernet segments at the ends that are mapped into Ethernet-over-SONET long-distance circuits. This paper focuses on the file-transfer application for such circuits. For this application, the CHEETAH service is proposed as an add-on to the primary Internet access service already in place for enterprise hosts. This allows an end host that is sending a file to first attempt setting up an end-to-end Ethernet/EoS circuit, and if rejected, fall back to the TCP/IP path. If the circuit setup is successful, the end host will enjoy a much shorter file-transfer delay than on the TCP/IP path. To determine the conditions under which an end host with access to the CHEETAH service should attempt circuit setup, we analyze mean file-transfer delays as a function of call blocking probability in the circuit-switched network, probability of packet loss in the IP network, round-trip times, link rates, and so on.

Performance evaluation of a high-speed switched network for PACS

Science.gov (United States)

Zhang, Randy H.; Tao, Wenchao; Huang, Lu J.; Valentino, Daniel J.

1998-07-01

We have replaced our shared-media Ethernet and FDDI network with a multi-tiered, switched network using OC-12 (622 Mbps) ATM for the network backbone, OC3 (155 Mbps) connections to high-end servers and display workstations, and switched 100/10 Mbps Ethernet for workstations and desktop computers. The purpose of this research was to help PACS designers and implementers understand key performance factors in a high- speed switched network by characterizing and evaluating its image delivery performance, specifically, the performance of socket-based TCP (Transmission Control Protocol) and DICOM 3.0 communications. A test network within the UCLA Clinical RIS/PACS was constructed using Sun UltraSPARC-II machines with ATM, Fast Ethernet, and Ethernet network interfaces. To identify performance bottlenecks, we evaluated network throughput for memory to memory, memory to disk, disk to memory, and disk to disk transfers. To evaluate the effect of file size, tests involving disks were further divided using sizes of small (514 KB), medium (8 MB), and large (16 MB) files. The observed maximum throughput for various network configurations using the TCP protocol was 117 Mbps for memory to memory and 88 MBPS for memory to disk. For disk to memory, the peak throughput was 98 Mbps using small files, 114 Mbps using medium files, and 116 Mbps using large files. The peak throughput for disk to disk became 64 Mbps using small files and 96 Mbps using medium and large files. The peak throughput using the DICOM 3.0 protocol was substantially lower in all categories. The measured throughput varied significantly among the tests when TCP socket buffer was raised above the default value. The optimal buffer size was approximately 16 KB or the TCP protocol and around 256 KB for the DICOM protocol. The application message size also displayed distinctive effects on network throughput when the TCP socket buffer size was varied. The throughput results for Fast Ethernet and Ethernet were expectedly

The research and application of Ethernet over RPR technology

Science.gov (United States)

Feng, Xiancheng; Yun, Xiang

2008-11-01

With service competitions of carriers aggravating and client's higher service experience requirement, it urges the MAN technology develops forward. When the Core Layer and Distribution Layer technology are mature, all kinds of reliability technologies of MAN access Layer are proposed. EoRPR is one of reliability technologies for MAN access network service protection. This paper elaborates Ethernet over RPR technology's many advantages through analyzing basic principle, address learning and key technologies of Ethernet over RPR. EpRPR has quicker replacing speed, plug and play, stronger QoS ability, convenient service deployment, band fairly sharing, and so on. At the same time the paper proposed solution of Ethernet over RPR in MAN, NGN network and enterprise Private network. So, among many technologies of MAN access network, EoRPR technology has higher reliability and manageable and highly effectiveness and lower costive of Ethernet. It is not only suitable for enterprise interconnection, BTV and NGN access services and so on, but also can meet the requirement of carriers' reducing CAPEX and OPEX's and increase the rate of investment.

Study of cutting speed on surface roughness and chip formation when machining nickel-based alloy

International Nuclear Information System (INIS)

Khidhir, Basim A.; Mohamed, Bashir

2010-01-01

Nickel- based alloy is difficult-to-machine because of its low thermal diffusive property and high strength at higher temperature. The machinability of nickel- based Hastelloy C-276 in turning operations has been carried out using different types of inserts under dry conditions on a computer numerical control (CNC) turning machine at different stages of cutting speed. The effects of cutting speed on surface roughness have been investigated. This study explores the types of wear caused by the effect of cutting speed on coated and uncoated carbide inserts. In addition, the effect of burr formation is investigated. The chip burr is found to have different shapes at lower speeds. Triangles and squares have been noticed for both coated and uncoated tips as well. The conclusion from this study is that the transition from thick continuous chip to wider discontinuous chip is caused by different types of inserts. The chip burr has a significant effect on tool damage starting in the line of depth-of-cut. For the coated insert tips, the burr disappears when the speed increases to above 150 m/min with the improvement of surface roughness; increasing the speed above the same limit for uncoated insert tips increases the chip burr size. The results of this study showed that the surface finish of nickel-based alloy is highly affected by the insert type with respect to cutting speed changes and its effect on chip burr formation and tool failure

Integrating Gigabit ethernet cameras into EPICS at Diamond light source

International Nuclear Information System (INIS)

Cobb, T.

2012-01-01

At Diamond Light Source a range of cameras are used to provide images for diagnostic purposes in both the accelerator and photo beamlines. The accelerator and existing beamlines use Point Grey Flea and Flea2 Firewire cameras. We have selected Gigabit Ethernet cameras supporting GigE Vision for our new photon beamlines. GigE Vision is an interface standard for high speed Ethernet cameras which encourages inter-operability between manufacturers. This paper describes the challenges encountered while integrating GigE Vision cameras from a range of vendors into EPICS. GigE Vision cameras appear to be more reliable than the Firewire cameras, and the simple cabling makes much easier to move the cameras to different positions. Upcoming power over Ethernet versions of the cameras will reduce the number of cables still further

Chip formation and surface integrity in high-speed machining of hardened steel

Science.gov (United States)

Kishawy, Hossam Eldeen A.

Increasing demands for high production rates as well as cost reduction have emphasized the potential for the industrial application of hard turning technology during the past few years. Machining instead of grinding hardened steel components reduces the machining sequence, the machining time, and the specific cutting energy. Hard turning Is characterized by the generation of high temperatures, the formation of saw toothed chips, and the high ratio of thrust to tangential cutting force components. Although a large volume of literature exists on hard turning, the change in machined surface physical properties represents a major challenge. Thus, a better understanding of the cutting mechanism in hard turning is still required. In particular, the chip formation process and the surface integrity of the machined surface are important issues which require further research. In this thesis, a mechanistic model for saw toothed chip formation is presented. This model is based on the concept of crack initiation on the free surface of the workpiece. The model presented explains the mechanism of chip formation. In addition, experimental investigation is conducted in order to study the chip morphology. The effect of process parameters, including edge preparation and tool wear on the chip morphology, is studied using Scanning Electron Microscopy (SEM). The dynamics of chip formation are also investigated. The surface integrity of the machined parts is also investigated. This investigation focusses on residual stresses as well as surface and sub-surface deformation. A three dimensional thermo-elasto-plastic finite element model is developed to predict the machining residual stresses. The effect of flank wear is introduced during the analysis. Although residual stresses have complicated origins and are introduced by many factors, in this model only the thermal and mechanical factors are considered. The finite element analysis demonstrates the significant effect of the heat generated

Design and FPGA implementation for MAC layer of Ethernet PON

Science.gov (United States)

Zhu, Zengxi; Lin, Rujian; Chen, Jian; Ye, Jiajun; Chen, Xinqiao

2004-04-01

Ethernet passive optical network (EPON), which represents the convergence of low-cost, high-bandwidth and supporting multiple services, appears to be one of the best candidates for the next-generation access network. The work of standardizing EPON as a solution for access network is still underway in the IEEE802.3ah Ethernet in the first mile (EFM) task force. The final release is expected in 2004. Up to now, there has been no standard application specific integrated circuit (ASIC) chip available which fulfills the functions of media access control (MAC) layer of EPON. The MAC layer in EPON system has many functions, such as point-to-point emulation (P2PE), Ethernet MAC functionality, multi-point control protocol (MPCP), network operation, administration and maintenance (OAM) and link security. To implement those functions mentioned above, an embedded real-time operating system (RTOS) and a flexible programmable logic device (PLD) with an embedded processor are used. The software and hardware functions in MAC layer are realized through programming embedded microprocessor and field programmable gate array(FPGA). Finally, some experimental results are given in this paper. The method stated here can provide a valuable reference for developing EPON MAC layer ASIC.

Design of analog-type high-speed SerDes using digital components for optical chip-to-chip link

Science.gov (United States)

Sangirov, Jamshid; Nguyen, Nga T. H.; Ngo, Trong-Hieu; Im, Dong-min; Ukaegbu, Augustine I.; Lee, Tae-Woo; Cho, Mu Hee; Park, Hyo-Hoon

2010-02-01

An analog-type high-speed serializer/deserializer (SerDes) has been designed for optical links especially between CPU and memory. The circuit uses a system clock and its phases to multiplex data to the serial link which avoids the need for a PLL-based high frequency clock generation used in serializing parallel data as in conventional SerDes design. The multiplexed link combined with the de-serializing clock is used as a reference signal for de-serialization. The SerDes is being designed in a 0.13 μm Si-CMOS technology. The fabricated serializer has a core chip size of 360 x750 μm2. Power dissipation for the SerDes is 71.4 mW operating up to 6.5 Gbps.

Feasibility Study of 8-Bit Microcontroller Applications for Ethernet

Directory of Open Access Journals (Sweden)

Lech Gulbinovič

2011-08-01

Full Text Available Feasibility study of 8-bit microcontroller applications for Ethernet is presented. Designed device is based on ATmega32 microcontroller and 10 Mbps Ethernet controller ENC28J60. Device is simulated as mass queuing theoretical model with ticket booking counter. Practical explorations are accomplished and characteristics are determined. Practical results are compared to theoretical ones. Program code and device packet processing speed optimization are discussed. Microcontroller packet processing speed and packet latency depend on packet size. For ICMP protocol packet processing speed varies 1.4–2.1 Mbps, latency – 0.8–8.4 ms. UDP protocol packet processing speed varies 1.3–1.8 Mbps, latency – 1.1–9.6 ms. Packet processing speed depends on compilation settings and program code compression level. Best results are reached on optimization le­vel ‑O3, then speed increased ~3% but program code size increased 68% comparing to –Os optimization level.Article in Lithuanian

High-speed VCSEL-based optical interconnects

Science.gov (United States)

Ishak, Waguih S.

2001-11-01

Vertical Cavity Surface Emitting Lasers (VCSEL) have made significant inroads into commercial realization especially in the area of data communications. Single VCSEL devices are key components in Gb Ethernet Transceivers. A multi-element VCSEL array is the key enabling technology for high-speed multi Gb/s parallel optical interconnect modules. In 1996, several companies introduced a new generation of fiber optic products based VCSEL technology such as multimode fiber transceivers for the ANSI Fiber Channel and Gigabit Ethernet IEEE 802.3 standards. VCSELs offer unique advantages over its edge-emitting counterparts in several areas. These include low-cost (LED-like) manufacturability, low current operation and array integrability. As data rates continue to increase, VCSELs offer the advantage of being able to provide the highest modulation bandwidth per milliamp of modulation current. Currently, most of the VCSEL-based products use short (780 - 980 nm) wavelength lasers. However, significant research efforts are taking place at universities and industrial research labs around the world to develop reliable, manufacturable and high-power long (1300 - 1550 nm) wavelength VCSELs. These lasers will allow longer (several km) transmission distances and will help alleviate some of the eye-safety issues. Perhaps, the most important advantage of VCSELs is the ability to form two-dimensional arrays much easier than in the case of edge-emitting lasers. These arrays (single and two-dimensional) will allow a whole new family of applications, specifically in very high-speed computer and switch interconnects.

Ethernet-based test stand for a CAN network

Science.gov (United States)

Ziebinski, Adam; Cupek, Rafal; Drewniak, Marek

2017-11-01

This paper presents a test stand for the CAN-based systems that are used in automotive systems. The authors propose applying an Ethernet-based test system that supports the virtualisation of a CAN network. The proposed solution has many advantages compared to classical test beds that are based on dedicated CAN-PC interfaces: it allows the physical constraints associated with the number of interfaces that can be simultaneously connected to a tested system to be avoided, which enables the test time for parallel tests to be shortened; the high speed of Ethernet transmission allows for more frequent sampling of the messages that are transmitted by a CAN network (as the authors show in the experiment results section) and the cost of the proposed solution is much lower than the traditional lab-based dedicated CAN interfaces for PCs.

Ethernet redundancy

Energy Technology Data Exchange (ETDEWEB)

Burak, K. [Invensys Process Systems, M/S C42-2B, 33 Commercial Street, Foxboro, MA 02035 (United States)

2006-07-01

We describe the Ethernet systems and their evolution: LAN Segmentation, DUAL networks, network loops, network redundancy and redundant network access. Ethernet (IEEE 802.3) is an open standard with no licensing fees and its specifications are freely available. As a result, it is the most popular data link protocol in use. It is important that the network be redundant and standard Ethernet protocols like RSTP (IEEE 802.1w) provide the fast network fault detection and recovery times that is required today. As Ethernet does continue to evolve, network redundancy is and will be a mixture of technology standards. So it is very important that both end-stations and networking devices be Ethernet (IEEE 802.3) compliant. Then when new technologies, such as the IEEE 802.1aq Shortest Path Bridging protocol, come to market they can be easily deployed in the network without worry.

Ethernet redundancy

International Nuclear Information System (INIS)

Burak, K.

2006-01-01

We describe the Ethernet systems and their evolution: LAN Segmentation, DUAL networks, network loops, network redundancy and redundant network access. Ethernet (IEEE 802.3) is an open standard with no licensing fees and its specifications are freely available. As a result, it is the most popular data link protocol in use. It is important that the network be redundant and standard Ethernet protocols like RSTP (IEEE 802.1w) provide the fast network fault detection and recovery times that is required today. As Ethernet does continue to evolve, network redundancy is and will be a mixture of technology standards. So it is very important that both end-stations and networking devices be Ethernet (IEEE 802.3) compliant. Then when new technologies, such as the IEEE 802.1aq Shortest Path Bridging protocol, come to market they can be easily deployed in the network without worry

A mixed signal multi-chip module with high speed serial output links for the ATLAS Level-1 trigger

CERN Document Server

Pfeiffer, U

2000-01-01

We have built and tested a mixed signal multi-chip module (MCM) to be used in the Level-1 Pre-Processor system for the Calorimeter Trigger of the ATLAS experiment at CERN. The MCM performs high speed digital signal processing on four analogue input signals. Results are transmitted serially at a serial data rate of 800 MBd. Nine chips of different technologies are mounted on a four layer Cu substrate. ADC converters and serialiser chips are the major consumers of electrical power on the MCM, which amounts to 9 W for all dies. Special cut-out areas are used to dissipate heat directly to the copper substrate. In this paper we report on design criteria, chosen MCM technology for substrate and die mounting, experiences with the MCM operation and measurement results. (4 refs).

Data transfer based on intelligent ethernet card

International Nuclear Information System (INIS)

Zhu Haitao; Chinese Academy of Sciences, Beijing; Chu Yuanping; Zhao Jingwei

2007-01-01

Intelligent Ethernet Cards are widely used in systems where the network throughout is very large, such as the DAQ systems for modern high energy physics experiments, web service. With the example of a commercial intelligent Ethernet card, this paper introduces the architecture, the principle and the process of intelligent Ethernet cards. In addition, the results of several experiments showing the differences between intelligent Ethernet cards and general ones are also presented. (authors)

Experience with PACS in an ATM/Ethernet switched network environment.

Science.gov (United States)

Pelikan, E; Ganser, A; Kotter, E; Schrader, U; Timmermann, U

1998-03-01

Legacy local area network (LAN) technologies based on shared media concepts are not adequate for the growth of a large-scale picture archiving and communication system (PACS) in a client-server architecture. First, an asymmetric network load, due to the requests of a large number of PACS clients for only a few main servers, should be compensated by communication links to the servers with a higher bandwidth compared to the clients. Secondly, as the number of PACS nodes increases, the network throughout should not measurably cut production. These requirements can easily be fulfilled using switching technologies. Here asynchronous transfer mode (ATM) is clearly one of the hottest topics in networking because the ATM architecture provides integrated support for a variety of communication services, and it supports virtual networking. On the other hand, most of the imaging modalities are not yet ready for integration into a native ATM network. For a lot of nodes already joining an Ethernet, a cost-effective and pragmatic way to benefit from the switching concept would be a combined ATM/Ethernet switching environment. This incorporates an incremental migration strategy with the immediate benefits of high-speed, high-capacity ATM (for servers and high-sophisticated display workstations), while preserving elements of the existing network technologies. In addition, Ethernet switching instead of shared media Ethernet improves the performance considerably. The LAN emulation (LANE) specification by the ATM forum defines mechanisms that allow ATM networks to coexist with legacy systems using any data networking protocol. This paper points out the suitability of this network architecture in accordance with an appropriate system design.

Optimization of PAM-4 transmitters based on lumped silicon photonic MZMs for high-speed short-reach optical links.

Science.gov (United States)

Zhou, Shiyu; Wu, Hsin-Ta; Sadeghipour, Khosrov; Scarcella, Carmelo; Eason, Cormac; Rensing, Marc; Power, Mark J; Antony, Cleitus; O'Brien, Peter; Townsend, Paul D; Ossieur, Peter

2017-02-20

We demonstrate how to optimize the performance of PAM-4 transmitters based on lumped Silicon Photonic Mach-Zehnder Modulators (MZMs) for short-reach optical links. Firstly, we analyze the trade-off that occurs between extinction ratio and modulation loss when driving an MZM with a voltage swing less than the MZM's Vπ. This is important when driver circuits are realized in deep submicron CMOS process nodes. Next, a driving scheme based upon a switched capacitor approach is proposed to maximize the achievable bandwidth of the combined lumped MZM and CMOS driver chip. This scheme allows the use of lumped MZM for high speed optical links with reduced RF driver power consumption compared to the conventional approach of driving MZMs (with transmission line based electrodes) with a power amplifier. This is critical for upcoming short-reach link standards such as 400Gb/s 802.3 Ethernet. The driver chip was fabricated using a 65nm CMOS technology and flip-chipped on top of the Silicon Photonic chip (fabricated using IMEC's ISIPP25G technology) that contains the MZM. Open eyes with 4dB extinction ratio for a 36Gb/s (18Gbaud) PAM-4 signal are experimentally demonstrated. The electronic driver chip has a core area of only 0.11mm2 and consumes 236mW from 1.2V and 2.4V supply voltages. This corresponds to an energy efficiency of 6.55pJ/bit including Gray encoder and retiming, or 5.37pJ/bit for the driver circuit only.

Highly Accurate Timestamping for Ethernet-Based Clock Synchronization

OpenAIRE

Loschmidt, Patrick; Exel, Reinhard; Gaderer, Georg

2012-01-01

It is not only for test and measurement of great importance to synchronize clocks of networked devices to timely coordinate data acquisition. In this context the seek for high accuracy in Ethernet-based clock synchronization has been significantly supported by enhancements to the Network Time Protocol (NTP) and the introduction of the Precision Time Protocol (PTP). The latter was even applied to instrumentation and measurement applications through the introduction of LXI....

High capacity carrier ethernet transport networks

DEFF Research Database (Denmark)

Rasmussen, Anders; Zhang, Jiang; Yu, Hao

2009-01-01

OAM functions, survivability and the increased bandwidth requirements of carrier class systems. This article provides an overview of PBB-TE and T-MPLS and demonstrates how IPTV services can be realized in the framework of Carrier Ethernet. In addition we provide a case study on performing bit error...

Enterasys Networks delivers 10-Gigabit ethernet for the enterprise with new matrix E1 switching family

CERN Multimedia

2001-01-01

Enterasys Networks Inc., today announced its new Matrix E1 family of 10-Gigabit and Gigabit Ethernet switches. The Matrix E1 Optical Access Switch (OAS) enables organizations to deliver applications at 10-Gb speeds across a single fibre optic pair. Jacques Altaber, deputy leader of IT at CERN said "High-bandwith solutions are essential to leveraging more computing power, so 10-Gb Ethernet is the next logical step for us...The Matrix E1 allows us to provide the networking support that our scientists need and gives us a certain future for bandwidth and computing expansion".

Low-power grating detection system chip for high-speed low-cost length and angle precision measurement

Science.gov (United States)

Hou, Ligang; Luo, Rengui; Wu, Wuchen

2006-11-01

This paper forwards a low power grating detection chip (EYAS) on length and angle precision measurement. Traditional grating detection method, such as resister chain divide or phase locked divide circuit are difficult to design and tune. The need of an additional CPU for control and display makes these methods' implementation more complex and costly. Traditional methods also suffer low sampling speed for the complex divide circuit scheme and CPU software compensation. EYAS is an application specific integrated circuit (ASIC). It integrates micro controller unit (MCU), power management unit (PMU), LCD controller, Keyboard interface, grating detection unit and other peripherals. Working at 10MHz, EYAS can afford 5MHz internal sampling rate and can handle 1.25MHz orthogonal signal from grating sensor. With a simple control interface by keyboard, sensor parameter, data processing and system working mode can be configured. Two LCD controllers can adapt to dot array LCD or segment bit LCD, which comprised output interface. PMU alters system between working and standby mode by clock gating technique to save power. EYAS in test mode (system action are more frequently than real world use) consumes 0.9mw, while 0.2mw in real world use. EYAS achieved the whole grating detection system function, high-speed orthogonal signal handling in a single chip with very low power consumption.

An automatic chip structure optical inspection system for electronic components

Science.gov (United States)

Song, Zhichao; Xue, Bindang; Liang, Jiyuan; Wang, Ke; Chen, Junzhang; Liu, Yunhe

2018-01-01

An automatic chip structure inspection system based on machine vision is presented to ensure the reliability of electronic components. It consists of four major modules, including a metallographic microscope, a Gigabit Ethernet high-resolution camera, a control system and a high performance computer. An auto-focusing technique is presented to solve the problem that the chip surface is not on the same focusing surface under the high magnification of the microscope. A panoramic high-resolution image stitching algorithm is adopted to deal with the contradiction between resolution and field of view, caused by different sizes of electronic components. In addition, we establish a database to storage and callback appropriate parameters to ensure the consistency of chip images of electronic components with the same model. We use image change detection technology to realize the detection of chip images of electronic components. The system can achieve high-resolution imaging for chips of electronic components with various sizes, and clearly imaging for the surface of chip with different horizontal and standardized imaging for ones with the same model, and can recognize chip defects.

Next generation network based carrier ethernet test bed for IPTV traffic

DEFF Research Database (Denmark)

Fu, Rong; Berger, Michael Stübert; Zheng, Yu

2009-01-01

This paper presents a Carrier Ethernet (CE) test bed based on the Next Generation Network (NGN) framework. After the concept of CE carried out by Metro Ethernet Forum (MEF), the carrier-grade Ethernet are obtaining more and more interests and being investigated as the low cost and high performanc...... services of transport network to carry the IPTV traffic. This test bed is approaching to support the research on providing a high performance carrier-grade Ethernet transport network for IPTV traffic....

Universal interface on Zynq"® SoC with CAN, RS-232, Ethernet and AXI GPIO for instrumentation & control

International Nuclear Information System (INIS)

Kumar, Abhijeet; Rajpal, Rachana; Pujara, Harshad; Mandaliya, Hitesh; Edappala, Praveenalal

2016-01-01

Highlights: • We have designed Universal Interface on Zynq"® SoC with CAN, RS-232, Ethernet and AXI GPIO for Instrumentation & Control. This project is based on Zynq"®-7000 family xc7z020clg484-1 chip. • We explored the full design flow starting from the hardware development in Vivado to software development in SDK using APIs in C language and then interfacing the host application developed in LabVIEW. • We also explored how to make custom IP with AXI bus interface in Vivado. • Useful for those who wants to make custom hardware on Zynq"® SoC. - Abstract: This paper describes an application developed on the latest Zynq"®-7000 All Programmable SoC (AP SoC) [1] devices which integrate the software programmability of an ARM"®-based processor with the hardware programmability of an FPGA, on a single device. In this paper we have implemented application which uses various interfaces like CAN, RS-232, Ethernet and AXI GPIO, so that our host application running on PC in LabVIEW can communicates with any hardware which has at least any one of the available interface. Zynq-7000 All Programmable SoCs (System On Chip) infuse customizable intelligence into today’s embedded systems to suit your unique application requirements. This family of FPGA is meant for high end application because it has huge resources on single chip. It offers you to make your own custom hardware IP, in fact we have made our custom IP called myIP in our design. The beauty of this chip is that it can write drivers for your custom IP which has AXI bus layer attached. After exporting the hardware information to the Software Development Kit (SDK), the tool is able to write drivers for your custom IP. This simplifies your development to a great extent. In a way this application provides the universal interfacing option to user. User can also write the digital data on the GPIO (General Purpose Input Output) through LabVIEW Test application GUI. This project can be used for remote control and

Evaluation of Giga-bit Ethernet instrumentation for SalSA electronics readout

International Nuclear Information System (INIS)

Varner, Gary S.; Murakami, Laine; Ridley, David; Zhu Chaopin; Gorham, Peter

2005-01-01

An instrumentation prototype for acquiring high-speed transient data from an array of high bandwidth antennas is presented. Multi-kilometer cable runs complicate acquisition of such large bandwidth radio signals from an extensive antenna array. Solutions using analog fiber optic links are being explored though are very expensive. We propose an inexpensive solution that allows for individual operation of each antenna element, operating at potentially high local self-trigger rates. Digitized data packets are transmitted to the surface via commercially available Giga-bit Ethernet hardware. Events are then reconstructed on a computer farm by sorting the received packets using standard networking gear, eliminating the need for custom, very high speed trigger hardware. Such a system is completely scalable and leverages the enormous capital investment made by the telecommunications industry. Test results from a demonstration prototype are presented

Testiranje Ethernet mehanizmov OAM

OpenAIRE

GERKŠIČ, KATJA

2015-01-01

V magistrskem delu preučimo in primerjamo standarde ter priporočila na področju Ethernet OAM (angl. OAM – Operation, administration and maintenance). Tehnologija Ethernet postaja vedno polj prisotna v mestnih in prostranih omrežjih, zato je pomembno, da imamo dobro definirane mehanizme za nadzor delovanja, administracijo in upravljanje Ethernet omrežij. V delu se osredotočimo predvsem na standarda IEEE 802.3ah in IEEE 802.1ag ter priporočilo ITU-T Y.1731. Posebno pozornost namenimo delovanju ...

Universal interface on Zynq{sup ®} SoC with CAN, RS-232, Ethernet and AXI GPIO for instrumentation & control

Energy Technology Data Exchange (ETDEWEB)

Kumar, Abhijeet, E-mail: akumar@ipr.res.in; Rajpal, Rachana; Pujara, Harshad; Mandaliya, Hitesh; Edappala, Praveenalal

2016-11-15

Highlights: • We have designed Universal Interface on Zynq{sup ®} SoC with CAN, RS-232, Ethernet and AXI GPIO for Instrumentation & Control. This project is based on Zynq{sup ®}-7000 family xc7z020clg484-1 chip. • We explored the full design flow starting from the hardware development in Vivado to software development in SDK using APIs in C language and then interfacing the host application developed in LabVIEW. • We also explored how to make custom IP with AXI bus interface in Vivado. • Useful for those who wants to make custom hardware on Zynq{sup ®} SoC. - Abstract: This paper describes an application developed on the latest Zynq{sup ®}-7000 All Programmable SoC (AP SoC) [1] devices which integrate the software programmability of an ARM{sup ®}-based processor with the hardware programmability of an FPGA, on a single device. In this paper we have implemented application which uses various interfaces like CAN, RS-232, Ethernet and AXI GPIO, so that our host application running on PC in LabVIEW can communicates with any hardware which has at least any one of the available interface. Zynq-7000 All Programmable SoCs (System On Chip) infuse customizable intelligence into today’s embedded systems to suit your unique application requirements. This family of FPGA is meant for high end application because it has huge resources on single chip. It offers you to make your own custom hardware IP, in fact we have made our custom IP called myIP in our design. The beauty of this chip is that it can write drivers for your custom IP which has AXI bus layer attached. After exporting the hardware information to the Software Development Kit (SDK), the tool is able to write drivers for your custom IP. This simplifies your development to a great extent. In a way this application provides the universal interfacing option to user. User can also write the digital data on the GPIO (General Purpose Input Output) through LabVIEW Test application GUI. This project can be used

HIPPI-6400 -- Designing for speed

Energy Technology Data Exchange (ETDEWEB)

Tolmie, D.E.

1998-03-01

The emerging High Performance Parallel Interface 6400 Mbit/s interface (HIPPI-6400), is targeted as a local area network (LAN), or system area network (SAN), supporting data rates of 6400 Mbit/s (800 Mbyte/s). This is eight times the speed of Gigabit Ethernet. The features used, and the design choices made, for the data link and physical layers of HIPPI-6400, to achieve this unprecedented speed are the subject of this paper. HIPPI-6400 borrowed freely from other successful technologies such as ATM, Ethernet and the original HIPPI -- taking the best features of each and melding them with some new features. HIPPI-6400 is a cost effective reliable interconnect for distances up to 1 km; it intermixes large and small messages efficiently.

Towards Terabit Carrier Ethernet and Energy Efficient Optical Transport Networks

DEFF Research Database (Denmark)

Rasmussen, Anders

This thesis focuses on the challenges of scaling current network node technology to support connection speeds of 100Gbps and beyond. Out of the many exiting aspects of reaching this goal, the main scope of this thesis is to investigate packet processing (address lookup and scheduling), forward....... The more advanced schemes also require more complex calculations to process each bit. This thesis will investigate how both the standard OTN FEC as well as more advanced FEC schemes can be implemented for 100G and above operation. As the networks are expanded to run at increasingly higher speeds...... error correction and energy efficiency. Scheduling and address lookup are key functions and potential bottle necks in high speed network nodes, as the minimum packet/frame sizes in both the popular Ethernet protocol, as well as the Internet Protocol (IP) still remains constant (84B and 40B, respectively...

Fast BPM data distribution for global orbit feedback using commercial gigabit ethernet technology

International Nuclear Information System (INIS)

Hulsart, R.; Cerniglia, P.; Michnoff, R.; Minty, M.

2011-01-01

In order to correct beam perturbations in RHIC around 10Hz, a new fast data distribution network was required to deliver BPM position data at rates several orders of magnitude above the capability of the existing system. The urgency of the project limited the amount of custom hardware that could be developed, which dictated the use of as much commercially available equipment as possible. The selected architecture uses a custom hardware interface to the existing RHIC BPM electronics together with commercially available Gigabit Ethernet switches to distribute position data to devices located around the collider ring. Using the minimum Ethernet packet size and a field programmable gate array (FPGA) based state machine logic instead of a software based driver, real-time and deterministic data delivery is possible using Ethernet. The method of adapting this protocol for low latency data delivery, bench testing of Ethernet hardware, and the logic to construct Ethernet packets using FPGA hardware will be discussed. A robust communications system using almost all commercial off-the-shelf equipment was developed in under a year which enabled retrofitting of the existing RHIC BPM system to provide 10 KHz data delivery for a global orbit feedback scheme using 72 BPMs. Total latencies from data acquisition at the BPMs to delivery at the controller modules, including very long transmission distances, were kept under 100 (micro)s, which provide very little phase error in correcting the 10 Hz oscillations. Leveraging off of the speed of Gigabit Ethernet and wide availability of Ethernet products enabled this solution to be fully implemented in a much shorter time and at lower cost than if a similar network was developed using a proprietary method.

A prototype switched Ethernet data acquisition system

International Nuclear Information System (INIS)

Ye Gaoying; Deng Huichen; Chen Liaoyuan; Liu Li; Wang Xinhui

1999-01-01

A prototype switched Ethernet data acquisition system has been built up and successfully operated in HL-1M tokamak experiments. The system is based on a switched high bandwidth Ethernet network with which the CAMAC crates are directly interfaced. It takes the advanced features of LAN switch and Ethernet CAMAC controller (ECC 1365 MK III, HYTEC product) to avoid the rewriting of CAMAC driver for an individual computer system and to ensure high data transmission rate between CAMAC system and host computers on the network. It is a new approach to DAS system architecture and provides a solution for a well-known bottleneck problem in traditional distributed DAS system for fusion research. An average throughput of the test system reaches over 100 Mbps. The system features also an easy and low cost migration from traditional distributed DAS system. In the paper, the hardware configuration, software structure, performance of the system and the method of migrating from current DAS system are discussed in detail. (orig.)

Ultrahigh-speed Si-integrated on-chip laser with tailored dynamic characteristics

DEFF Research Database (Denmark)

Park, Gyeong Cheol; Xue, Weiqi; Piels, Molly

2016-01-01

-pumped compact optical feedback structure can be realised, which together tailor the frequency response function for achieving a very high speed at low injection currents. Furthermore, light can be emitted laterally into a Si waveguide. From an 1.54-μm optically-pumped laser, a 3-dB frequency of 27 GHz...... was obtained at a pumping level corresponding to sub-mA. Using measured 3-dB frequen-cies and calculated equivalent currents, the modulation current efficiency factor (MCEF) is estimated to be 42.1 GHz/mA(1/2), which is superior among microcavity lasers. This shows a high potential for a very high speed at low......For on-chip interconnects, an ideal light source should have an ultralow energy consumption per bandwidth (operating en-ergy) as well as sufficient output power for error-free detection. Nanocavity lasers have been considered the most ideal for smaller operating energy. However, they have...

Performance Evaluation of 100 Gigabit Ethernet Switches under Bursty Traffic

DEFF Research Database (Denmark)

Ruepp, Sarah Renée; Rytlig, A.; Manolova, Anna Vasileva

2011-01-01

Switch fabrics for 100 Gigabit Ethernet systems pose high demands in terms of delay and scalability. In this paper we analyze the performance of a Clos-based switch fabric under uniform and bursty traffic, and compare its performance to a crossbar-based switch design for benchmarking. In particular......, we focus on a Clos-design using a Space-Memory-Memory (SMM) configuration, which has recently gained increased interest due to its reduced hardware complexity. The traffic between the input and the central modules is distributed in either a static, random or Desynchronized Static Round Robin (DSRR...... switch only reveals a minor performance penalty, which can be compensated by the high scalability, robustness and low complexity of the Clos-based design for high speed switching systems....

On-Chip Enucleation of Bovine Oocytes using Microrobot-Assisted Flow-Speed Control

Directory of Open Access Journals (Sweden)

Akihiko Ichikawa

2013-06-01

Full Text Available In this study, we developed a microfluidic chip with a magnetically driven microrobot for oocyte enucleation. A microfluidic system was specially designed for enucleation, and the microrobot actively controls the local flow-speed distribution in the microfluidic chip. The microrobot can adjust fluid resistances in a channel and can open or close the channel to control the flow distribution. Analytical modeling was conducted to control the fluid speed distribution using the microrobot, and the model was experimentally validated. The novelties of the developed microfluidic system are as follows: (1 the cutting speed improved significantly owing to the local fluid flow control; (2 the cutting volume of the oocyte can be adjusted so that the oocyte undergoes less damage; and (3 the nucleus can be removed properly using the combination of a microrobot and hydrodynamic forces. Using this device, we achieved a minimally invasive enucleation process. The average enucleation time was 2.5 s and the average removal volume ratio was 20%. The proposed new system has the advantages of better operation speed, greater cutting precision, and potential for repeatable enucleation.

A Systematic Scheme for Multiple Access in Ethernet Passive Optical Access Networks

Science.gov (United States)

Ma, Maode; Zhu, Yongqing; Hiang Cheng, Tee

2005-11-01

While backbone networks have experienced substantial changes in the last decade, access networks have not changed much. Recently, passive optical networks (PONs) seem to be ready for commercial deployment as access networks, due to the maturity of a number of enabling technologies. Among the PON technologies, Ethernet PON (EPON) standardized by the IEEE 802.3ah Ethernet in the First Mile (EFM) Task Force is the most attractive one because of its high speed, low cost, familiarity, interoperability, and low overhead. In this paper, we consider the issue of upstream channel sharing in the EPONs. We propose a novel multiple-access control scheme to provide bandwidth-guaranteed service for high-demand customers, while providing best effort service to low-demand customers according to the service level agreement (SLA). The analytical and simulation results prove that the proposed scheme performs best in what it is designed to do compared to another well-known scheme that has not considered providing differentiated services. With business customers preferring premium services with guaranteed bandwidth and residential users preferring low-cost best effort services, our scheme could benefit both groups of subscribers, as well as the operators.

Analysis of SCTP and TCP based communication in high-speed clusters

International Nuclear Information System (INIS)

Kozlovszky, M.; Berceli, T.; Kutor, L.

2006-01-01

Performance and financial constraints are pushing modern DAQs (Data Acquisition Systems) to use distributed cluster environments instead of monolith one-box systems. Inside clusters application communication layers should support outstanding high performance requirements. We are currently investigating different network protocols that could meet the requirements of high speed/low latency peer-to-peer communication within DAQ clusters. We have carried out various performance measurements with TCP and SCTP over Fast and Gigabit Ethernet. We are focusing on Ethernet Technologies, because this transport medium is broad deployed, cost efficient and it has much better cost/throughput ratio than other available communication alternatives (e.g.: Myrinet, Infiniband). During this study, a protocol performance measurement application with different peer transport components has been developed. In the first part of the paper, we give a short comparison of the two protocols (SCTP and TCP), and an introduction of the transport layer structure developed. Later on we discuss the performance results of single/multi-stream peer-to-peer communication, give overview about application code transition possibilities from application developer point of view between the two protocols, and draw conclusions about usability

Reliability in automotive ethernet networks

DEFF Research Database (Denmark)

Soares, Fabio L.; Campelo, Divanilson R.; Yan, Ying

2015-01-01

This paper provides an overview of in-vehicle communication networks and addresses the challenges of providing reliability in automotive Ethernet in particular.......This paper provides an overview of in-vehicle communication networks and addresses the challenges of providing reliability in automotive Ethernet in particular....

Towards 100 gigabit carrier ethernet transport networks

DEFF Research Database (Denmark)

Rasmussen, Anders; Zhang, Jiang; Yu, Hao

2010-01-01

technology, making the use of Ethernet as a convergence layer for Next Generation Networks a distinct possibility. Triple Play services, in particular IPTV, are expected to be a main drivers for carrier Ethernet, however, a number of challenges must be addressed including QoS enabled control plane, enhanced......Ethernet as a transport technology has, up to now, lacked the features such as network layer architecture, customer separation and manageability that carriers require for wide-scale deployment. However, with the advent of PBB-TE and TMPLS, it is now possible to use Ethernet as a transport...

10BASE5 Ethernet Cable & Vampire Tap

CERN Document Server

1983-01-01

10BASE5 Thick Ethernet Cable, 10Mbit/sec. In the 1980s and early 1990's, Ethernet became more popular and provided a much faster data transmission rate. This cable is one of the first ethernet cables from 1983, a thick, bulky affair. Computers were attached via "Vampire Taps" which were connectors screwed straight through the shielding of the cable.

A High-Speed Design of Montgomery Multiplier

Science.gov (United States)

Fan, Yibo; Ikenaga, Takeshi; Goto, Satoshi

With the increase of key length used in public cryptographic algorithms such as RSA and ECC, the speed of Montgomery multiplication becomes a bottleneck. This paper proposes a high speed design of Montgomery multiplier. Firstly, a modified scalable high-radix Montgomery algorithm is proposed to reduce critical path. Secondly, a high-radix clock-saving dataflow is proposed to support high-radix operation and one clock cycle delay in dataflow. Finally, a hardware-reused architecture is proposed to reduce the hardware cost and a parallel radix-16 design of data path is proposed to accelerate the speed. By using HHNEC 0.25μm standard cell library, the implementation results show that the total cost of Montgomery multiplier is 130 KGates, the clock frequency is 180MHz and the throughput of 1024-bit RSA encryption is 352kbps. This design is suitable to be used in high speed RSA or ECC encryption/decryption. As a scalable design, it supports any key-length encryption/decryption up to the size of on-chip memory.

High Performance Gigabit Ethernet Switches for DAQ Systems

CERN Document Server

Barczyk, Artur

2005-01-01

Commercially available high performance Gigabit Ethernet (GbE) switches are optimized mostly for Internet and standard LAN application traffic. DAQ systems on the other hand usually make use of very specific traffic patterns, with e.g. deterministic arrival times. Industry's accepted loss-less limit of 99.999% may be still unacceptably high for DAQ purposes, as e.g. in the case of the LHCb readout system. In addition, even switches passing this criteria under random traffic can show significantly higher loss rates if subject to our traffic pattern, mainly due to buffer memory limitations. We have evaluated the performance of several switches, ranging from "pizza-box" devices with 24 or 48 ports up to chassis based core switches in a test-bed capable to emulate realistic traffic patterns as expected in the readout system of our experiment. The results obtained in our tests have been used to refine and parametrize our packet level simulation of the complete LHCb readout network. In this paper we report on the...

Atmel's New Rad-Hard Sparc V8 Processor 200Mhz & Low Power System on Chip

Science.gov (United States)

Ganry, Nicolas; Mantelet, Guy; Parkes, Steve; McClements, Chris

2014-08-01

The AT6981 is a new generation of processor designed for critical spaceflight applications, which combines a high-performance SPARC® V8 radiation hard processor, with enough on-chip memory for many aerospace applications and state-of-the-art SpaceWire networking technology from STAR- Dundee. The AT6981 is implemented in Atmel 90nm rad-hard technology, enabling 200 MHz operating speed for the processor with power consumption levels around 1W. This advanced technology allows strong system integration in a SoC with embedded peripherals like CAN, 1553, Ethernet, DDR and embedded memory with 1Mbytes SRAM. The device is ITAR- free and is developed in France by Atmel Aerospace having more than of 30years space experience. This paper describes this new SoC architecture and technical options considered to insure the best performances, the minimum power consumption and high reliability. This device will be available on the market in H2 2014 for evaluation with first flight models targeted end 2015.

Ethernet direct display: a new dimension for in-vehicle video connectivity solutions

Science.gov (United States)

Rowley, Vincent

2009-05-01

To improve the local situational awareness (LSA) of personnel in light or heavily armored vehicles, most military organizations recognize the need to equip their fleets with high-resolution digital video systems. Several related upgrade programs are already in progress and, almost invariably, COTS IP/Ethernet is specified as the underlying transport mechanism. The high bandwidths, long reach, networking flexibility, scalability, and affordability of IP/Ethernet make it an attractive choice. There are significant technical challenges, however, in achieving high-performance, real-time video connectivity over the IP/Ethernet platform. As an early pioneer in performance-oriented video systems based on IP/Ethernet, Pleora Technologies has developed core expertise in meeting these challenges and applied a singular focus to innovating within the required framework. The company's field-proven iPORTTM Video Connectivity Solution is deployed successfully in thousands of real-world applications for medical, military, and manufacturing operations. Pleora's latest innovation is eDisplayTM, a smallfootprint, low-power, highly efficient IP engine that acquires video from an Ethernet connection and sends it directly to a standard HDMI/DVI monitor for real-time viewing. More costly PCs are not required. This paper describes Pleora's eDisplay IP Engine in more detail. It demonstrates how - in concert with other elements of the end-to-end iPORT Video Connectivity Solution - the engine can be used to build standards-based, in-vehicle video systems that increase the safety and effectiveness of military personnel while fully leveraging the advantages of the lowcost COTS IP/Ethernet platform.

Residential High-Speed Internet Among Those Likely to Benefit From an Online Health Insurance Marketplace

Directory of Open Access Journals (Sweden)

Michel H. Boudreaux PhD

2016-01-01

Full Text Available Using data from the 2013 American Community Survey, we found that 24.3 million people (about 1 in 4 who were either eligible for Medicaid/Children’s Health Inusrance Program (CHIP or appeared likely to shop for Qualified Health Plan (QHP lacked residential high-speed Internet. Specifically, 28.6% or 18.9 million people eligible for Medicaid/CHIP and 17.1% or 5.5 million people who appeared likely to shop for a QHP did not have high-speed Internet in the home. For both the Medicaid/CHIP eligible and those likely to shop for a QHP, the proportion of people living in households without Internet varied substantially by race, geography, and other socio-demographic characteristics.

CMOS analog integrated circuits high-speed and power-efficient design

CERN Document Server

Ndjountche, Tertulien

2011-01-01

High-speed, power-efficient analog integrated circuits can be used as standalone devices or to interface modern digital signal processors and micro-controllers in various applications, including multimedia, communication, instrumentation, and control systems. New architectures and low device geometry of complementary metaloxidesemiconductor (CMOS) technologies have accelerated the movement toward system on a chip design, which merges analog circuits with digital, and radio-frequency components. CMOS: Analog Integrated Circuits: High-Speed and Power-Efficient Design describes the important tren

Impact of high-pressure coolant supply on chip formation in milling

Science.gov (United States)

Klocke, F.; Döbbeler, B.; Lakner, T.

2017-10-01

Machining of titanium alloys is considered as difficult, because of their high temperature strength, low thermal conductivity and low E-modulus, which contributes to high mechanical loads and high temperatures in the contact zone between tool and workpiece. The generated heat in the cutting zone can be dissipated only in a low extent. When cutting steel materials, up to 75% of the process heat is transported away by the chips, contrary to only 25% when machining titanium alloys. As a result, the cutting tool heats up, which leads to high tool wear. Therefore, machining of titanium alloys is only possible with relatively low cutting speeds. This leads to low levels of productivity for milling processes with titanium alloys. One way to increase productivity is to use more cutting edges in tools with the same diameter. However, the limiting factor of adding more cutting edges to a milling tool is the minimum size of the chip spaces, which are sufficient for a stable chip evacuation. This paper presents experimental results on the chip formation and chip size influenced by high-pressure coolant supply, which can lead to smaller chips and to smaller sizes of the chip spaces, respectively. Both influences, the pressure of the supplied coolant and the volumetric flow rate were individually examined. Alpha-beta annealed titanium TiAl6V4 was examined in relation to the reference material quenched and tempered steel 42CrMo4+QT (AISI 4140+QT). The work shows that with proper chip control due to high-pressure coolant supply in milling, the number of cutting edges on the same diameter tool can be increased, which leads to improved productivity.

Ethernet over SDH (EoS): Summary

Indian Academy of Sciences (India)

Cost effective way to support data customers. Use of integrated Ethernet eliminates the need for costly WAN interfaces (E1/E3/STM-1) on routers connecting to SDH/SONET; WAN bandwidth can be provided directly from customers' Ethernet switches, potentially eliminating routers at customer sites ...

SynUTC - high precision time synchronization over ethernet networks

CERN Document Server

Höller, R; Horauer, M; Kerö, N; Schmid, U; Schossmaier, K

2002-01-01

This article describes our SynUTC (Synchronized Universal Time Coordinated) technology, which enables high-accuracy distribution of GPS time and time synchronization of network nodes connected via standard Ethernet LANs. By means of exchanging data packets in conjunction with moderate hardware support at nodes and switches, an overall worst-case accuracy in the range of some 100 ns can be achieved, with negligible communication overhead. Our technology thus improves the 1 ms-range accuracy achievable by conventional, software-based approaches like NTP by 4 orders of magnitude. Applications can use the high-accuracy global time provided by SynUTC for event timestamping and event generation both at hardware and software level. SynUTC is based upon inserting highly accurate time information into dedicated data packets at the media-independent interface (MII) between the physical layer transceiver and the network controller upon packet transmission and reception, respectively. As a consequence, every node has acc...

Residential High-Speed Internet Among Those Likely to Benefit From an Online Health Insurance Marketplace.

Science.gov (United States)

Boudreaux, Michel H; Gonzales, Gilbert; Blewett, Lynn; Fried, Brett; Karaca-Mandic, Pinar

2016-01-01

Using data from the 2013 American Community Survey, we found that 24.3 million people (about 1 in 4) who were either eligible for Medicaid/Children's Health Insurance Program (CHIP) or appeared likely to shop for Qualified Health Plan (QHP) lacked residential high-speed Internet. Specifically, 28.6% or 18.9 million people eligible for Medicaid/CHIP and 17.1% or 5.5 million people who appeared likely to shop for a QHP did not have high-speed Internet in the home. For both the Medicaid/CHIP eligible and those likely to shop for a QHP, the proportion of people living in households without Internet varied substantially by race, geography, and other socio-demographic characteristics. © The Author(s) 2016.

Optical frame synchronizer for 10 G Ethernet packets aiming at 1 Tb/s OTDM Ethernet

DEFF Research Database (Denmark)

Hu, Hao; Palushani, Evarist; Laguardia Areal, Janaina

2010-01-01

Synchronization of 10 G Ethernet packets to a local clock was demonstrated using a phase modulator and a SMF as retiming elements. Error free performances for the synchronized packets with different lengths were achieved.......Synchronization of 10 G Ethernet packets to a local clock was demonstrated using a phase modulator and a SMF as retiming elements. Error free performances for the synchronized packets with different lengths were achieved....

Systems-on-chip approach for real-time simulation of wheel-rail contact laws

Science.gov (United States)

Mei, T. X.; Zhou, Y. J.

2013-04-01

This paper presents the development of a systems-on-chip approach to speed up the simulation of wheel-rail contact laws, which can be used to reduce the requirement for high-performance computers and enable simulation in real time for the use of hardware-in-loop for experimental studies of the latest vehicle dynamic and control technologies. The wheel-rail contact laws are implemented using a field programmable gate array (FPGA) device with a design that substantially outperforms modern general-purpose PC platforms or fixed architecture digital signal processor devices in terms of processing time, configuration flexibility and cost. In order to utilise the FPGA's parallel-processing capability, the operations in the contact laws algorithms are arranged in a parallel manner and multi-contact patches are tackled simultaneously in the design. The interface between the FPGA device and the host PC is achieved by using a high-throughput and low-latency Ethernet link. The development is based on FASTSIM algorithms, although the design can be adapted and expanded for even more computationally demanding tasks.

An Analysis of an Ultra-High Speed Content-Addressable Database Retrieval System

National Research Council Canada - National Science Library

Costianes, Peter

2001-01-01

...) and its implementation as a high speed optical chip. The paradigm uses polarization states to represent binary very words and EO modulators to represent database words to perform what is essentially XOR operations...

Full-field parallel interferometry coherence probe microscope for high-speed optical metrology.

Science.gov (United States)

Safrani, A; Abdulhalim, I

2015-06-01

Parallel detection of several achromatic phase-shifted images is used to obtain a high-speed, high-resolution, full-field, optical coherence probe tomography system based on polarization interferometry. The high enface imaging speed, short coherence gate, and high lateral resolution provided by the system are exploited to determine microbump height uniformity in an integrated semiconductor chip at 50 frames per second. The technique is demonstrated using the Linnik microscope, although it can be implemented on any polarization-based interference microscopy system.

Plastic straw: future of high-speed signaling

Science.gov (United States)

Song, Ha Il; Jin, Huxian; Bae, Hyeon-Min

2015-11-01

The ever-increasing demand for bandwidth triggered by mobile and video Internet traffic requires advanced interconnect solutions satisfying functional and economic constraints. A new interconnect called E-TUBE is proposed as a cost-and-power-effective all-electrical-domain wideband waveguide solution for high-speed high-volume short-reach communication links. The E-TUBE achieves an unprecedented level of performance in terms of bandwidth-per-carrier frequency, power, and density without requiring a precision manufacturing process unlike conventional optical/waveguide solutions. The E-TUBE exhibits a frequency-independent loss-profile of 4 dB/m and has nearly 20-GHz bandwidth over the V band. A single-sideband signal transmission enabled by the inherent frequency response of the E-TUBE renders two-times data throughput without any physical overhead compared to conventional radio frequency communication technologies. This new interconnect scheme would be attractive to parties interested in high throughput links, including but not limited to, 100/400 Gbps chip-to-chip communications.

Data acquisition and control using ETHERNET

International Nuclear Information System (INIS)

Elkins, E.P.

1985-01-01

We have developed a distributed computer control system to monitor and control a linear accelerator. This system consists of two PDP-11s and eight LSI 11/23s linked together with ETHERNET. The higher level systems (control consoles, etc.) use the RSX11M operating system, whereas the data acquisition and control is performed using the RSX11S operating system downline loaded from a central host computer. Locally written ETHERNET drivers are used to reduce the CPU overhead and therefore improve system response. The ETHERNET system permits remote file access by means of operator or program interaction, as well as supporting downline system loading. Control-system functions supported are supervisory control, closed-loop control, data monitoring, and data recording. 4 refs., 2 figs., 1 tab

A novel conductive-polymer-based integration process for high-performance flip-chip packages

Science.gov (United States)

Lohokare, Saurabh

Conductive polymers have recently attracted considerable attention for low-temperature fabrication of lead-free, reworkable, and flexible flip-chip interconnects. Using these materials, I demonstrate in this thesis a process that enables low-cost and high-resolution flip-chip interconnects using conventional micro-fabrication techniques. This fabrication process offers improved performance as compared to conventional flip-chip techniques, such as screen-printing, and allows for definition of interconnects with excellent surface uniformity and control over the bump profile. In order to demonstrate the utility and wide applicability of this process, several test implementations that serve as case studies were investigated. Specifically, novel InGaAsSb avalanche photodiodes (APDs), operating around lambda = 2m and targeted for free-space communication and biomedical spectroscopy applications, were fabricated and flip-chip-integrated to test the static electrical characteristics of the polymer bumps. Additionally, the dynamic electrical performance characteristics of the polymer bumps were studied by using AlGaAsSb/AlGaSb p-i-n photodetectors as a case study. The fabrication of these photodetectors, operating around lambda = 1.55mum and targeted for optical communication applications, was accomplished using a customized inductively coupled plasma (ICP) etch process that resulted in a low dark current and excellent speed (3dB bandwidth of 10GHz) and, responsivity (60% external quantum efficiency) characteristics. Furthermore, flip-chip integration was used to demonstrate a three-dimensional, point-to-point micro-optical interconnect, which was 2.33mm-long in a system 15.27mm3 in volume. Lastly, high-speed parallel optical interconnects were demonstrated using polymer-flip-chip-integrated 10GHz vertical-cavity surface-emitting laser (VCSEL) and DOEs. Such interconnects offer the ability to alleviate the communication bottleneck that is projected to occur in future, high

Holistic design in high-speed optical interconnects

Science.gov (United States)

Saeedi, Saman

Integrated circuit scaling has enabled a huge growth in processing capability, which necessitates a corresponding increase in inter-chip communication bandwidth. As bandwidth requirements for chip-to-chip interconnection scale, deficiencies of electrical channels become more apparent. Optical links present a viable alternative due to their low frequency-dependent loss and higher bandwidth density in the form of wavelength division multiplexing. As integrated photonics and bonding technologies are maturing, commercialization of hybrid-integrated optical links are becoming a reality. Increasing silicon integration leads to better performance in optical links but necessitates a corresponding co-design strategy in both electronics and photonics. In this light, holistic design of high-speed optical links with an in-depth understanding of photonics and state-of-the-art electronics brings their performance to unprecedented levels. This thesis presents developments in high-speed optical links by co-designing and co-integrating the primary elements of an optical link: receiver, transmitter, and clocking. In the first part of this thesis a 3D-integrated CMOS/Silicon-photonic receiver will be presented. The electronic chip features a novel design that employs a low-bandwidth TIA front-end, double-sampling and equalization through dynamic offset modulation. Measured results show -14.9dBm of sensitivity and energy eciency of 170fJ/b at 25Gb/s. The same receiver front-end is also used to implement source-synchronous 4-channel WDM-based parallel optical receiver. Quadrature ILO-based clocking is employed for synchronization and a novel frequency-tracking method that exploits the dynamics of IL in a quadrature ring oscillator to increase the effective locking range. An adaptive body-biasing circuit is designed to maintain the per-bit-energy consumption constant across wide data-rates. The prototype measurements indicate a record-low power consumption of 153fJ/b at 32Gb/s. The

Providing resilience for carrier ethernet multicast traffic

DEFF Research Database (Denmark)

Ruepp, Sarah Renée; Wessing, Henrik; Zhang, Jiang

2009-01-01

This paper presents an overview of the Carrier Ethernet technology with specific focus on resilience. In particular, we detail how multicast traffic, which is essential for e.g. IPTV can be protected. We present Carrier Ethernet resilience methods for linear and ring networks and show by simulation...

Auto correct method of AD converters precision based on ethernet

Directory of Open Access Journals (Sweden)

NI Jifeng

2013-10-01

Full Text Available Ideal AD conversion should be a straight zero-crossing line in the Cartesian coordinate axis system. While in practical engineering, the signal processing circuit, chip performance and other factors have an impact on the accuracy of conversion. Therefore a linear fitting method is adopted to improve the conversion accuracy. An automatic modification of AD conversion based on Ethernet is presented by using software and hardware. Just by tapping the mouse, all the AD converter channel linearity correction can be automatically completed, and the error, SNR and ENOB (effective number of bits are calculated. Then the coefficients of linear modification are loaded into the onboard AD converter card's EEPROM. Compared with traditional methods, this method is more convenient, accurate and efficient，and has a broad application prospects.

Comparison of microrings and microdisks for high-speed optical modulation in silicon photonics

Science.gov (United States)

Ying, Zhoufeng; Wang, Zheng; Zhao, Zheng; Dhar, Shounak; Pan, David Z.; Soref, Richard; Chen, Ray T.

2018-03-01

The past several decades have witnessed the gradual transition from electrical to optical interconnects, ranging from long-haul telecommunication to chip-to-chip interconnects. As one type of key component in integrated optical interconnect and high-performance computing, optical modulators have been well developed these past few years, including ultrahigh-speed microring and microdisk modulators. In this paper, a comparison between microring and microdisk modulators is well analyzed in terms of dimensions, static and dynamic power consumption, and fabrication tolerance. The results show that microdisks have advantages over microrings in these aspects, which gives instructions to the chip design of high-density integrated systems for optical interconnects and optical computing.

All-IP-Ethernet architecture for real-time sensor-fusion processing

Science.gov (United States)

Hiraki, Kei; Inaba, Mary; Tezuka, Hiroshi; Tomari, Hisanobu; Koizumi, Kenichi; Kondo, Shuya

2016-03-01

Serendipter is a device that distinguishes and selects very rare particles and cells from huge amount of population. We are currently designing and constructing information processing system for a Serendipter. The information processing system for Serendipter is a kind of sensor-fusion system but with much more difficulties: To fulfill these requirements, we adopt All IP based architecture: All IP-Ethernet based data processing system consists of (1) sensor/detector directly output data as IP-Ethernet packet stream, (2) single Ethernet/TCP/IP streams by a L2 100Gbps Ethernet switch, (3) An FPGA board with 100Gbps Ethernet I/F connected to the switch and a Xeon based server. Circuits in the FPGA include 100Gbps Ethernet MAC, buffers and preprocessing, and real-time Deep learning circuits using multi-layer neural networks. Proposed All-IP architecture solves existing problem to construct large-scale sensor-fusion systems.

Ultra-high-speed Optical Signal Processing using Silicon Photonics

DEFF Research Database (Denmark)

Oxenløwe, Leif Katsuo; Ji, Hua; Jensen, Asger Sellerup

with a photonic layer on top to interconnect them. For such systems, silicon is an attractive candidate enabling both electronic and photonic control. For some network scenarios, it may be beneficial to use optical on-chip packet switching, and for high data-density environments one may take advantage...... of the ultra-fast nonlinear response of silicon photonic waveguides. These chips offer ultra-broadband wavelength operation, ultra-high timing resolution and ultra-fast response, and when used appropriately offer energy-efficient switching. In this presentation we review some all-optical functionalities based...... on silicon photonics. In particular we use nano-engineered silicon waveguides (nanowires) [1] enabling efficient phasematched four-wave mixing (FWM), cross-phase modulation (XPM) or self-phase modulation (SPM) for ultra-high-speed optical signal processing of ultra-high bit rate serial data signals. We show...

Evaluating multicast resilience in carrier ethernet

DEFF Research Database (Denmark)

Ruepp, Sarah Renée; Wessing, Henrik; Zhang, Jiang

2010-01-01

This paper gives an overview of the Carrier Ethernet technology with specific focus on resilience. In particular, we show how multicast traffic, which is essential for IPTV can be protected. We detail the ackground for resilience mechanisms and their control and e present Carrier Ethernet...... resilience methods for linear nd ring networks. By simulation we show that the vailability of a multicast connection can be significantly increased by applying protection methods....

IPTV traffic management using topology-based hierarchical scheduling in Carrier Ethernet transport networks

DEFF Research Database (Denmark)

Yu, Hao; Yan, Ying; Berger, Michael Stubert

2009-01-01

Carrier Ethernet is becoming a favorable access technology for Next Generation Network (NGN). The features of cost-efficiency, operation flexibility and high bandwidth have a great attraction to service providers. However, to achieve these characteristics, Carrier Ethernet needs to have Quality o....... This work has been carried out as a part of the research project HIPT (High quality IP network for IPTV and VoIP) founded by Danish Advanced Technology Foundation....

A high speed dual-gain preamplifier system with multiple channels

International Nuclear Information System (INIS)

Zhao Lei; Liu Shubin; Xian Ze; An Qi

2008-01-01

In this paper, a multiple-channel high speed preamplifier module with dual-gain is presented, together with its design principle, test methods and performance parameter. By proper choice of the chips and careful circuit design, the preamplifier accomplishes a fine performance in high speed analog signal processing. The 3 dB bandwidth is above 440 MHz for gain factor of 2 and 280 MHz for gain factor of 8, with the leading edge time of less than 2 ns. The preamplifier module has been used in the research project of β-delayed neutron emission of radionuclides in neutron-rich region. (authors)

Proposal for tutorial: Resilience in carrier Ethernet transport

DEFF Research Database (Denmark)

Berger, Michael Stübert; Wessing, Henrik; Ruepp, Sarah Renée

2009-01-01

This tutorial addresses how Carrier Ethernet technologies can be used in the transport network to provide resilience to the packet layer. Carrier Ethernet networks based on PBB-TE and T-MPLS/MPLS-TP are strong candidates for reliable transport of triple-play services. These technologies offer...... of enhancements are still required to make Carrier Ethernet ready for large scale deployments of reliable point-to-multipoint services. The tutorial highlights the necessary enhancements and shows possible solutions and directions towards reliable multicast. Explicit focus is on OAM for multicast, where...

Possibilities of implementation of synchronous Ethernet in popular Ethernet version using timing and interference constraints

Directory of Open Access Journals (Sweden)

Seetaiah KILARU

2015-12-01

Full Text Available Popular network architectures are following packet based architectures instead of conventional Time division multiplexing. The existed Ethernet is basically asynchronous in nature and was not designed based on timing transfer constraints. To achieve the challenge of next generation network with respect to efficient bandwidth and faster data rates, we have to deploy the network which has less latency. This can be achieved by Synchronous Ethernet (SyncE. In Sync-E, Phase Locked Loop (PLL was used to recover the incoming jitter from clock recovery circuit. Then feed the PLL block to transmission device. We have to design the network in an unaffected way that the functions of Ethernet should run in normal way even we introduced timing path at physical layer. This paper will give detailed outlook on how Sync-E is achieved from Asynchronous format. Reference model of 100 Base-TX/FX was analyzed with respect to timing and interference constraints. Finally, it was analyzed with the data rate improvement with the proposed method.

Synchronized High-Speed Vision Sensor Network for Expansion of Field of View

Directory of Open Access Journals (Sweden)

Akihito Noda

2018-04-01

Full Text Available We propose a 500-frames-per-second high-speed vision (HSV sensor network that acquires frames at a timing that is precisely synchronized across the network. Multiple vision sensor nodes, individually comprising a camera and a PC, are connected via Ethernet for data transmission and for clock synchronization. A network of synchronized HSV sensors provides a significantly expanded field-of-view compared with that of each individual HSV sensor. In the proposed system, the shutter of each camera is controlled based on the clock of the PC locally provided inside the node, and the shutters are globally synchronized using the Precision Time Protocol (PTP over the network. A theoretical analysis and experiment results indicate that the shutter trigger skew among the nodes is a few tens of microseconds at most, which is significantly smaller than the frame interval of 1000-fps-class high-speed cameras. Experimental results obtained with the proposed system comprising four nodes demonstrated the ability to capture the propagation of a small displacement along a large-scale structure.

Carrier ethernet network control plane based on the Next Generation Network

DEFF Research Database (Denmark)

Fu, Rong; Wang, Yanmeng; Berger, Michael Stubert

2008-01-01

This paper contributes on presenting a step towards the realization of Carrier Ethernet control plane based on the next generation network (NGN). Specifically, transport MPLS (T-MPLS) is taken as the transport technology in Carrier Ethernet. It begins with providing an overview of the evolving...... architecture of the next generation network (NGN). As an essential candidate among the NGN transport technologies, the definition of Carrier Ethernet (CE) is also introduced here. The second part of this paper depicts the contribution on the T-MPLS based Carrier Ethernet network with control plane based on NGN...... at illustrating the improvement of the Carrier Ethernet network with the NGN control plane....

Radiation Hardened Ethernet PHY and Switch Fabric, Phase I

Data.gov (United States)

National Aeronautics and Space Administration — Innoflight will develop a new family of radiation hardened (up to 3 Mrad(Si)), fault-tolerant, high data-rate (up to 8 Gbps), low power Gigabit Ethernet PHY and...

Design of high-speed data transmission system for Lanzhou heavy ion therapy accelerator

International Nuclear Information System (INIS)

Mao Wenyu; Qiao Weimin; Jing Lan; Li Guihua

2012-01-01

In order to satisfy the transmission requirements of partial synchronization data and process data for the heavy ion therapy accelerator, a high-speed, error-correction, long-distance, and real-time data transmission system was proposed and achieved. It can improve the efficiency and reliability of the accelerator control and synchronization. The system optimizes the hardware configuration and layout of the traditional system. FPGA, gigabit fiber module, PXI and SDRAM are the main parts of the system. It replaces the low-speed, short-distance, and poor anti-interference of the traditional data path and the data processing chips. Through the programming in the two FPGA chips, the PXI and DMA transmission mode was used to exchange data with the server of the accelerator. The front-end of the system achieves a real-time, long-distance, and high-speed serial frame transmission with 800 MHz carrier and 100 MHz base band signal. The real-time -data like synchronous event signal, power waveform data of the heavy ion therapy accelerator can be transmitted efficiently between the server and the remote controller through the system. (authors)

Fault Tolerant Ethernet Based Network for Time Sensitive Applications in Electrical Power Distribution Systems

Directory of Open Access Journals (Sweden)

Leos Bohac

2013-01-01

Full Text Available The paper analyses and experimentally verifies deployment of Ethernet based network technology to enable fault tolerant and timely exchange of data among a number of high voltage protective relays that use proprietary serial communication line to exchange data in real time on a state of its high voltage circuitry facilitating a fast protection switching in case of critical failures. The digital serial signal is first fetched into PCM multiplexer where it is mapped to the corresponding E1 (2 Mbit/s time division multiplexed signal. Subsequently, the resulting E1 frames are then packetized and sent through Ethernet control LAN to the opposite PCM demultiplexer where the same but reverse processing is done finally sending a signal into the opposite protective relay. The challenge of this setup is to assure very timely delivery of the control information between protective relays even in the cases of potential failures of Ethernet network itself. The tolerance of Ethernet network to faults is assured using widespread per VLAN Rapid Spanning Tree Protocol potentially extended by 1+1 PCM protection as a valuable option.

Ethernet ring protection with managed FDB using APS payload

Science.gov (United States)

Im, Jinsung; Ryoo, Jeong-dong; Joo, Bheom Soon; Rhee, J.-K. Kevin

2007-11-01

Ethernet ring protection (ERP) is a new technology based on OAM (operations, administration, and maintenance) being standardized by the ITU-T G.8032 working group. In this paper, we present the recent development of Ethernet ring protection which is called FDB (filtering database) flush scheme and propose a new Ethernet ring protection technique introducing a managed FDB using APS to deliver information how to fix FDB selectively. We discuss the current development of the ERP technology at ITU-T and performance comparisons between different proposals.

Converting serial networks to Ethernet communications

Energy Technology Data Exchange (ETDEWEB)

Rosado, Elroy [Freewave Technologies, Inc., Boulder, CO (United States). Latin America

2008-07-01

Many oil and gas producers and pipeline companies find themselves in an awkward position. They have invested millions of dollars in legacy serial communications systems and in most cases, millions more in older SCADA remote terminal units and electronic flow meters. There is a desire throughout most of the industry to convert these systems to Ethernet. This presentation will explore how Ethernet protocol offers advantages over the older serial communications in terms of peer to peer communication, faster polling cycles, and the ability to poll multiple devices at the same time. (author)

Ethernet Networks for Real-Time Use in the ATLAS Experiment

CERN Document Server

Meirosu, C; Martin, B

2005-01-01

Ethernet became today's de-facto standard technology for local area networks. Defined by the IEEE 802.3 and 802.1 working groups, the Ethernet standards cover technologies deployed at the first two layers of the OSI protocol stack. The architecture of modern Ethernet networks is based on switches. The switches are devices usually built using a store-and-forward concept. At the highest level, they can be seen as a collection of queues and mathematically modelled by means of queuing theory. However, the traffic profiles on modern Ethernet networks are rather different from those assumed in classical queuing theory. The standard recommendations for evaluating the performance of network devices define the values that should be measured but do not specify a way of reconciling these values with the internal architecture of the switches. The introduction of the 10 Gigabit Ethernet standard provided a direct gateway from the LAN to the WAN by the means of the WAN PHY. Certain aspects related to the actual use of WAN ...

Radiation Hardened 10BASE-T Ethernet Physical Layer (PHY)

Science.gov (United States)

Lin, Michael R. (Inventor); Petrick, David J. (Inventor); Ballou, Kevin M. (Inventor); Espinosa, Daniel C. (Inventor); James, Edward F. (Inventor); Kliesner, Matthew A. (Inventor)

2017-01-01

Embodiments may provide a radiation hardened 10BASE-T Ethernet interface circuit suitable for space flight and in compliance with the IEEE 802.3 standard for Ethernet. The various embodiments may provide a 10BASE-T Ethernet interface circuit, comprising a field programmable gate array (FPGA), a transmitter circuit connected to the FPGA, a receiver circuit connected to the FPGA, and a transformer connected to the transmitter circuit and the receiver circuit. In the various embodiments, the FPGA, transmitter circuit, receiver circuit, and transformer may be radiation hardened.

Research of high speed data readout and pre-processing system based on xTCA for silicon pixel detector

International Nuclear Information System (INIS)

Zhao Jingzhou; Lin Haichuan; Guo Fang; Liu Zhen'an; Xu Hao; Gong Wenxuan; Liu Zhao

2012-01-01

As the development of the detector, Silicon pixel detectors have been widely used in high energy physics experiments. It needs data processing system with high speed, high bandwidth and high availability to read data from silicon pixel detectors which generate more large data. The same question occurs on Belle II Pixel Detector which is a new style silicon pixel detector used in SuperKEKB accelerator with high luminance. The paper describes the research of High speed data readout and pre-processing system based on xTCA for silicon pixel detector. The system consists of High Performance Computer Node (HPCN) based on xTCA and ATCA frame. The HPCN consists of 4XFPs based on AMC, 1 AMC Carrier ATCA Board (ACAB) and 1 Rear Transmission Module. It characterized by 5 high performance FPGAs, 16 fiber links based on RocketIO, 5 Gbit Ethernet ports and DDR2 with capacity up to 18GB. In a ATCA frame, 14 HPCNs make up a system using the high speed backplane to achieve the function of data pre-processing and trigger. This system will be used on the trigger and data acquisition system of Belle II Pixel detector. (authors)

Efficient power supply using Power over Ethernet; Effiziente Stromversorgung mittels Power over Ethernet (PoE)

Energy Technology Data Exchange (ETDEWEB)

Huser, A.

2005-07-01

This final report for the Swiss Federal Office of Energy (SFOE) takes a look at methods of supplying small equipment such as Internet telephones, web cams, hubs, hard discs, audio equipment, point-of-sale terminals, game consoles etc. with power via their Ethernet connections. A short comparison is presented between Power over Ethernet (PoE) and other methods of supplying power along with data, including Universal Serial Bus (USB), FireWire and Powerline systems. The advantages of PoE over the use of separate power supply units are discussed and recommendations are made to the manufacturers and users of small peripheral equipment regarding the dimensioning and loading of such power supply systems.

Synchronization, retiming and OTDM of an asynchronous 10 Gigabit Ethernet NRZ packet using a time lens for Terabit Ethernet

DEFF Research Database (Denmark)

Hu, Hao; Laguardia Areal, Janaina; Mulvad, Hans Christian Hansen

2011-01-01

An asynchronous 10G Ethernet packet is synchronized and retimed to a master clock using a time lens. The NRZ packet is converted into an RZ packet and multiplexed with a serial 1.28 Tb/s signal.......An asynchronous 10G Ethernet packet is synchronized and retimed to a master clock using a time lens. The NRZ packet is converted into an RZ packet and multiplexed with a serial 1.28 Tb/s signal....

Performance evaluation of 100 Gigabit ethernet switching system

DEFF Research Database (Denmark)

Rytlig, Andreas; Ruepp, Sarah Renée; Manolova, Anna Vasileva

2010-01-01

100 Gigabit Ethernet is an emerging technology and to support it, existing switch fabrics need to be redesigned. High throughput and QoS are required. A scalable multi-stage fabric based on a Clos architecture is envisaged to meet these demands. Using OPNET modeler, a design based on a variation...

FASTBUS Readout Controller card for high speed data acquisition

International Nuclear Information System (INIS)

Zimmermann, S.

1991-10-01

This article describes a FASTBUS Readout Controller (FRC) for high speed data acquisition in FASTBUS based systems. The controller has two main interfaces: to FASTBUS and to a Readout Port. The FASTBUS interface performs FASTBUS master and slave operations at a maximum transfer rate exceeding 40 MBytes/s. The Readout Port can be adapted for a variety of protocols. Currently, it will be interfaced to a VME bus based processor with a VSB port. The on-board LR33000 embedded processor controls the readout, executing a list of operations download into its memory. It scans the FASTBUS modules and stores the data in a triple port DRAM (TPDRAM), through one of the Serial Access Memory (SAM) ports of the (TPDRAM). Later, it transfers this data to the readout port using the other SAM. The FRC also supports serial communication via RS232 and Ethernet interfaces. This device is intended for use in the data acquisition system at the Collider Detector at Fermilab. 5 refs., 3 figs

Hardware Realization of an Ethernet Packet Analyzer Search Engine

Science.gov (United States)

2000-06-30

specific for the home automation industry. This analyzer will be at the gateway of a network and analyze Ethernet packets as they go by. It will keep... home automation and not the computer network. This system is a stand-alone real-time network analyzer capable of decoding Ethernet protocols. The

Ethernet for Space Flight Applications

Science.gov (United States)

Webb, Evan; Day, John H. (Technical Monitor)

2002-01-01

NASA's Goddard Space Flight Center (GSFC) is adapting current data networking technologies to fly on future spaceflight missions. The benefits of using commercially based networking standards and protocols have been widely discussed and are expected to include reduction in overall mission cost, shortened integration and test (I&T) schedules, increased operations flexibility, and hardware and software upgradeability/scalability with developments ongoing in the commercial world. The networking effort is a comprehensive one encompassing missions ranging from small University Explorer (UNEX) class spacecraft to large observatories such as the Next Generation Space Telescope (NGST). Mission aspects such as flight hardware and software, ground station hardware and software, operations, RF communications, and security (physical and electronic) are all being addressed to ensure a complete end-to-end system solution. One of the current networking development efforts at GSFC is the SpaceLAN (Spacecraft Local Area Network) project, development of a space-qualifiable Ethernet network. To this end we have purchased an IEEE 802.3-compatible 10/100/1000 Media Access Control (MAC) layer Intellectual Property (IP) core and are designing a network node interface (NNI) and associated network components such as a switch. These systems will ultimately allow the replacement of the typical MIL-STD-1553/1773 and custom interfaces that inhabit most spacecraft. In this paper we will describe our current Ethernet NNI development along with a novel new space qualified physical layer that will be used in place of the standard interfaces. We will outline our plans for development of space qualified network components that will allow future spacecraft to operate in significant radiation environments while using a single onboard network for reliable commanding and data transfer. There will be a brief discussion of some issues surrounding system implications of a flight Ethernet. Finally, we will

Simulation and Evaluation of Ethernet Passive Optical Network

Directory of Open Access Journals (Sweden)

Salah A. Jaro Alabady

2013-05-01

Full Text Available      This paper studies simulation and evaluation of Ethernet Passive Optical Network (EPON system, IEEE802.3ah based OPTISM 3.6 simulation program. The simulation program is used in this paper to build a typical ethernet passive optical network, and to evaluate the network performance when using the (1580, 1625 nm wavelength instead of (1310, 1490 nm that used in Optical Line Terminal (OLT and Optical Network Units (ONU's in system architecture of Ethernet passive optical network at different bit rate and different fiber optic length. The results showed enhancement in network performance by increase the number of nodes (subscribers connected to the network, increase the transmission distance, reduces the received power and reduces the Bit Error Rate (BER.   

Microstructural characterization of WC-TiC-Co cutting tools during high-speed machining of P20 mold steel

International Nuclear Information System (INIS)

Farhat, Z.N.

2003-01-01

The wear behavior of tungsten carbide (WC)-TiC-Co cutting tools during cutting P20 tool steel was investigated. Orthogonal cutting tests were performed on a CNC lathe using five speeds, namely, 60, 120, 240, 380 and 600 m/min. Wear, as the width of the wear land, was monitored at five time intervals. Wear characterization of the rake and the flank surfaces as well as the collected chips was performed using scanning electron microscopy (SEM), backscattered electron imaging and energy-dispersive X-ray analysis (EDX). Microhardness of collected chips was also performed to monitor strain hardening effects during cutting. Two dominant wear mechanisms were identified: at high speed (380-600 m/min), wear was found to occur by a melt wear mechanism; at low speed (60-120 m/min), adhesion (built-up edge) followed by delamination was found to be the cause of wear damage. It was also found that deformation in the chips occurred by localized shear deformation

Impedance Discontinuity Reduction Between High-Speed Differential Connectors and PCB Interfaces

Science.gov (United States)

Navidi, Sal; Agdinaoay, Rodell; Walter, Keith

2013-01-01

High-speed serial communication (i.e., Gigabit Ethernet) requires differential transmission and controlled impedances. Impedance control is essential throughout cabling, connector, and circuit board construction. An impedance discontinuity arises at the interface of a high-speed quadrax and twinax connectors and the attached printed circuit board (PCB). This discontinuity usually is lower impedance since the relative dielectric constant of the board is higher (i.e., polyimide approx. = 4) than the connector (Teflon approx. = 2.25). The discontinuity can be observed in transmit or receive eye diagrams, and can reduce the effective link margin of serial data networks. High-speed serial data network transmission improvements can be made at the connector-to-board interfaces as well as improving differential via hole impedances. The impedance discontinuity was improved by 10 percent by drilling a 20-mil (approx. = 0.5-mm) hole in between the pin of a differential connector spaced 55 mils (approx. = 1.4 mm) apart as it is attached to the PCB. The effective dielectric constant of the board can be lowered by drilling holes into the board material between the differential lines in a quadrax or twinax connector attachment points. The differential impedance is inversely proportional to the square root of the relative dielectric constant. This increases the differential impedance and thus reduces the above described impedance discontinuity. The differential via hole impedance can also be increased in the same manner. This technique can be extended to multiple smaller drilled holes as well as tapered holes (i.e., big in the middle followed by smaller ones diagonally).

Optimization of high frequency flip-chip interconnects for digital superconducting circuits

International Nuclear Information System (INIS)

Rafique, M R; Engseth, H; Kidiyarova-Shevchenko, A

2006-01-01

This paper presents the results of theoretical optimization of the multi-chip-module (MCM) contact and driver circuitries for gigabit chip-to-chip communication. Optimization has been done using 3D electromagnetic (EM) simulations of MCM contacts and time domain simulations of drivers and receivers. A single optimized MCM contact has a signal reflection of less than -20 dB for more than 400 GHz bandwidth. The MCM data link with the optimized SFQ driver, receiver and two MCM contacts has operational margins on the global bias current of ± 30% at 30 Gbit s -1 speedand can operate above 100 Gbit s -1 speed. Wide bandwidth transmission requires the realization of an advanced flip-chip process with a small dimension of the MCM contact (less than 30 μm diameter of the contact pad) and small height of the flip-chip contact bumps of the order of 2 μm. Current processes with about 7 μm height of the bumps require the application of a double-flux-quantum (DFQ) driver. The data link with the DFQ driver was also simulated. It has operational margins on the global bias current of ± 30% at 30 Gbit s -1 ; however, the maximum speed of operation is 61 Gbit s -1 . Several test structures have been designed for measurements of signal reflection, bit error rate and operational margins of the data link

Using a Control System Ethernet Network as a Field Bus

CERN Document Server

De Van, William R; Lawson, Gregory S; Wagner, William H; Wantland, David M; Williams, Ernest

2005-01-01

A major component of a typical accelerator distributed control system (DCS) is a dedicated, large-scale local area communications network (LAN). The SNS EPICS-based control system uses a LAN based on the popular IEEE-802.3 set of standards (Ethernet). Since the control system network infrastructure is available throughout the facility, and since Ethernet-based controllers are readily available, it is tempting to use the control system LAN for "fieldbus" communications to low-level control devices (e.g. vacuum controllers; remote I/O). These devices may or may not be compatible with the high-level DCS protocols. This paper presents some of the benefits and risks of combining high-level DCS communications with low-level "field bus" communications on the same network, and describes measures taken at SNS to promote compatibility between devices connected to the control system network.

A wireless high-speed data acquisition system for geotechnical centrifuge model testing

Science.gov (United States)

Gaudin, C.; White, D. J.; Boylan, N.; Breen, J.; Brown, T.; DeCatania, S.; Hortin, P.

2009-09-01

This paper describes a novel high-speed wireless data acquisition system (WDAS) developed at the University of Western Australia for operation onboard a geotechnical centrifuge, in an enhanced gravitational field of up to 300 times Earth's gravity. The WDAS system consists of up to eight separate miniature units distributed around the circumference of a 0.8 m diameter drum centrifuge, communicating with the control room via wireless Ethernet. Each unit is capable of powering and monitoring eight instrument channels at a sampling rate of up to 1 MHz at 16-bit resolution. The data are stored within the logging unit in solid-state memory, but may also be streamed in real-time at low frequency (up to 10 Hz) to the centrifuge control room, via wireless transmission. The high-speed logging runs continuously within a circular memory (buffer), allowing for storage of a pre-trigger segment of data prior to an event. To suit typical geotechnical modelling applications, the system can record low-speed data continuously, until a burst of high-speed acquisition is triggered when an experimental event occurs, after which the system reverts back to low-speed acquisition to monitor the aftermath of the event. Unlike PC-based data acquisition solutions, this system performs the full sequence of amplification, conditioning, digitization and storage on a single circuit board via an independent micro-controller allocated to each pair of instrumented channels. This arrangement is efficient, compact and physically robust to suit the centrifuge environment. This paper details the design specification of the WDAS along with the software interface developed to control the units. Results from a centrifuge test of a submarine landslide are used to illustrate the performance of the new WDAS.

A wireless high-speed data acquisition system for geotechnical centrifuge model testing

International Nuclear Information System (INIS)

Gaudin, C; White, D J; Boylan, N; Breen, J; Brown, T; De Catania, S; Hortin, P

2009-01-01

This paper describes a novel high-speed wireless data acquisition system (WDAS) developed at the University of Western Australia for operation onboard a geotechnical centrifuge, in an enhanced gravitational field of up to 300 times Earth's gravity. The WDAS system consists of up to eight separate miniature units distributed around the circumference of a 0.8 m diameter drum centrifuge, communicating with the control room via wireless Ethernet. Each unit is capable of powering and monitoring eight instrument channels at a sampling rate of up to 1 MHz at 16-bit resolution. The data are stored within the logging unit in solid-state memory, but may also be streamed in real-time at low frequency (up to 10 Hz) to the centrifuge control room, via wireless transmission. The high-speed logging runs continuously within a circular memory (buffer), allowing for storage of a pre-trigger segment of data prior to an event. To suit typical geotechnical modelling applications, the system can record low-speed data continuously, until a burst of high-speed acquisition is triggered when an experimental event occurs, after which the system reverts back to low-speed acquisition to monitor the aftermath of the event. Unlike PC-based data acquisition solutions, this system performs the full sequence of amplification, conditioning, digitization and storage on a single circuit board via an independent micro-controller allocated to each pair of instrumented channels. This arrangement is efficient, compact and physically robust to suit the centrifuge environment. This paper details the design specification of the WDAS along with the software interface developed to control the units. Results from a centrifuge test of a submarine landslide are used to illustrate the performance of the new WDAS

Comparison of High Performance Network Options: EDR InfiniBand vs.100Gb RDMA Capable Ethernet

Energy Technology Data Exchange (ETDEWEB)

Kachelmeier, Luke Anthony [Los Alamos National Lab. (LANL), Los Alamos, NM (United States); Univ. of New Mexico, Albuquerque, NM (United States); Van Wig, Faith Virginia [Los Alamos National Lab. (LANL), Los Alamos, NM (United States); Missouri Univ. of Science and Technology, Rolla, MO (United States); Erickson, Kari Natania [Los Alamos National Lab. (LANL), Los Alamos, NM (United States); New Mexico Inst. of Mining and Technology, Socorro, NM (United States)

2016-08-08

These are the slides for a presentation at the HPC Mini Showcase. This is a comparison of two different high performance network options: EDR InfiniBand and 100Gb RDMA capable ethernet. The conclusion of this comparison is the following: there is good potential, as shown with the direct results; 100Gb technology is too new and not standardized, thus deployment effort is complex for both options; different companies are not necessarily compatible; if you want 100Gb/s, you must get it all from one place.

Application of Ethernet Powerlink for communication in a Linux RTAI open CNC control system

OpenAIRE

Erwiński, Krystian; Paprocki, Marcin; Grzesiak, Lech; Karwowski, Kazimierz; Wawrzak, Andrzej

2013-01-01

In computerized numerical control (CNC) systems, the communication bus between the controller and axis servo drives must offer high bandwidth, noise immunity, and time determinism. More and more CNC systems use real-time Ethernet protocols such as Ethernet Powerlink (EPL). Many modern controllers are closed costly hardware-based solutions. In this paper, the implementation of EPL communication bus in a PC-based CNC system is presented. The CNC system includes a PC, a s...

Protection switching for carrier ethernet multicast

DEFF Research Database (Denmark)

Ruepp, Sarah Renée; Wessing, Henrik; Berger, Michael Stübert

2010-01-01

This paper addresses network survivability for IPTV multicast transport in Carrier Ethernet networks. The impact of link failures is investigated and suggestions for intelligent multicast resilience schemes are proposed. In particular, functions of the multicast tree are integrated with the Carri...... recovery path length, recovery time, number of branch nodes and operational complexity. The integrated approach therefore shows significant potential to increase the QoE for IPTV users in case of network failures and recovery actions.......This paper addresses network survivability for IPTV multicast transport in Carrier Ethernet networks. The impact of link failures is investigated and suggestions for intelligent multicast resilience schemes are proposed. In particular, functions of the multicast tree are integrated with the Carrier...

Adiabatic shear bands as predictors of strain rate in high speed machining of ramax-2

International Nuclear Information System (INIS)

Zeb, M.A.; Irfan, M.A.; Velduis, A.C.

2008-01-01

Shear band formation was studied in the chips obtained by turning of stainless steel- Ramax-2 (AISI 420F). The machining was performed on a CNC lathe using a PVD (Physical Vapor Deposition) cutting tool insert. The cutting speeds ranged from 50 m/ min to 250 m/min. Dry cutting conditions were employed. At cutting speeds higher than 30 m/mill, the chip did not remain intact with the workpiece using quick stop device. It was difficult to get the chip root SEM (Scanning Electron Microscope) micrographs at further higher speeds. Therefore, the width of the shear bands was used as the predictor of the strain rates involved at various cutting speeds. The results showed that the strain rates are quite in agreement with the amount of strain rate found during machining of such types of stainless steels. It was also observed that shear band density increased with increasing cutting speed. (author)

New Observations on High-Speed Machining of Hardened AISI 4340 Steel Using Alumina-Based Ceramic Tools

Directory of Open Access Journals (Sweden)

Mohamed Shalaby

2018-05-01

Full Text Available High-speed machining (HSM is used in industry to improve the productivity and quality of the cutting operations. In this investigation, pure alumina ceramics with the addition of ZrO2, and mixed alumina (Al2O3 + TiC tools were used in the dry hard turning of AISI 4340 (52 HRC at different high cutting speeds of 150, 250, 700 and 1000 m/min. It was observed that at cutting speeds of 150 and 250 m/min, pure alumina ceramic tools had better wear resistance than mixed alumina ones. However, upon increasing the cutting speed from 700 to 1000 m/min, mixed alumina ceramic tools outperformed pure ceramic ones. Scanning electron microscopy (SEM and X-ray photoelectron spectroscopy (XPS were used to investigate the worn cutting edges and analyze the obtained results. It was found that the tribo-films formed at the cutting zone during machining affected the wear resistances of the tools and influenced the coefficient of friction at the tool-chip interface. These observations were confirmed by the chip compression ratio results at different cutting conditions. Raising cutting speed to 1000 m/min corresponded to a remarkable decrease in cutting force components in the dry hard turning of AISI 4340 steel.

High-Speed Computation using FPGA for Excellent Performance of Direct Torque Control of Induction Machines

Directory of Open Access Journals (Sweden)

Tole Sutikno

2016-03-01

Full Text Available The major problems in hysteresis-based DTC are high torque ripple and variable switching frequency. In order to minimize the torque ripple, high sampling time and fast digital realization should be applied. The high sampling and fast digital realization time can be achieved by utilizing high-speed processor where the operation of the discrete hysteresis regulator is becoming similar to the operation of analog-based comparator. This can be achieved by utilizing field programmable gate array (FPGA which can perform a sampling at a very high speed, compared to the fact that developing an ASIC chip is expensive and laborious.

FPGA Implementation of Real-Time Ethernet for Motion Control

Directory of Open Access Journals (Sweden)

Chen Youdong

2013-01-01

Full Text Available This paper provides an applicable implementation of real-time Ethernet named CASNET, which modifies the Ethernet medium access control (MAC to achieve the real-time requirement for motion control. CASNET is the communication protocol used for motion control system. Verilog hardware description language (VHDL has been used in the MAC logic design. The designed MAC serves as one of the intellectual properties (IPs and is applicable to various industrial controllers. The interface of the physical layer is RJ45. The other layers have been implemented by using C programs. The real-time Ethernet has been implemented by using field programmable gate array (FPGA technology and the proposed solution has been tested through the cycle time, synchronization accuracy, and Wireshark testing.

High-speed computation of the EM algorithm for PET image reconstruction

International Nuclear Information System (INIS)

Rajan, K.; Patnaik, L.M.; Ramakrishna, J.

1994-01-01

The PET image reconstruction based on the EM algorithm has several attractive advantages over the conventional convolution backprojection algorithms. However, two major drawbacks have impeded the routine use of the EM algorithm, namely, the long computational time due to slow convergence and the large memory required for the storage of the image, projection data and the probability matrix. In this study, the authors attempts to solve these two problems by parallelizing the EM algorithm on a multiprocessor system. The authors have implemented an extended hypercube (EH) architecture for the high-speed computation of the EM algorithm using the commercially available fast floating point digital signal processor (DSP) chips as the processing elements (PEs). The authors discuss and compare the performance of the EM algorithm on a 386/387 machine, CD 4360 mainframe, and on the EH system. The results show that the computational speed performance of an EH using DSP chips as PEs executing the EM image reconstruction algorithm is about 130 times better than that of the CD 4360 mainframe. The EH topology is expandable with more number of PEs

Ethernet Operation Administration and Maintenance ; Opportunities for the NREN community

NARCIS (Netherlands)

Prins, M.J.; Malhotra, R.

2011-01-01

Ethernet started its life as a Local Area Network technology and initially did not have Operations, Administration and Maintenance (OAM) features like IP Ping, IP Traceroute and SDH Loss of Frame. Monitoring and management was mainly done on the IP level. In the case of delivery of Ethernet

An ethernet/IP security review with intrusion detection applications

International Nuclear Information System (INIS)

Laughter, S. A.; Williams, R. D.

2006-01-01

Supervisory Control and Data Acquisition (SCADA) and automation networks, used throughout utility and manufacturing applications, have their own specific set of operational and security requirements when compared to corporate networks. The modern climate of heightened national security and awareness of terrorist threats has made the security of these systems of prime concern. There is a need to understand the vulnerabilities of these systems and how to monitor and protect them. Ethernet/IP is a member of a family of protocols based on the Control and Information Protocol (CIP). Ethernet/IP allows automation systems to be utilized on and integrated with traditional TCP/IP networks, facilitating integration of these networks with corporate systems and even the Internet. A review of the CIP protocol and the additions Ethernet/IP makes to it has been done to reveal the kind of attacks made possible through the protocol. A set of rules for the SNORT Intrusion Detection software is developed based on the results of the security review. These can be used to monitor, and possibly actively protect, a SCADA or automation network that utilizes Ethernet/IP in its infrastructure. (authors)

Architectural Design Study for a 10Gb/s Ethernet Switch

CERN Document Server

Oltean, Alexandra Dana

2004-01-01

The demand for 10Gb/s switches at this early stage in the market is primarily for modular solutions that can grow as do the bandwidth requirements. This indicates a requirement for chassis based solutions where individual line cards can be added to a chassis infrastructure and have to communicate across a 10Gb/s switching backplane. The present study is provides an architectural design solution for a passive copper backplane used for moving data between the line cards of a 10Gb/s Ethernet switch system. The ability to pass multi-gigabit data rates through a backplane system requires great attention to details previously thought to be irrelevant at lower frequencies. The trace dimensions, the via holes diameters, the backplane materials and choice of connectors, all play a crucial role in determining the success of the system. At high-speed even a subtle change in any of these elements can drastically affect the end-to-end system performance. In this context, the study presents the modeling and simulation work...

Převodník Ethernet na RS-232

OpenAIRE

Dreiseitel, Jiří

2012-01-01

Práce je věnována problematice konstrukce převodníku Ethernet na RS-232 za pomocí jednočipového mikrokontroléru. Cílem je seznámit čtenáře se síťovou technologií Ethernet a technologií pro sériový přenos založený na protokolu RS-232 a zároveň s technologií vestavěných systémů pro konstrukci zařízení. Součástí práce je kompletní návrh převodníku Ethernet na RS-232 včetně návrhu a implementace firmware v jazyce C za využití LwIP TCP/IP stacku. Převodník je postaven na základě vývojového kitu ST...

The Design of High Performance, Low Power Triple-Track Magnetic Sensor Chip

Directory of Open Access Journals (Sweden)

Junning Chen

2013-07-01

Full Text Available This paper presents a design of a high performance and low power consumption triple-track magnetic sensor chip which was fabricated in TSMC 0.35 μm CMOS process. This chip is able to simultaneously sense, decode and read out the information stored in triple-track magnetic cards. A reference voltage generating circuit, a low-cost filter circuit, a power-on reset circuit, an RC oscillator, and a pre-decoding circuit are utilized as the basic modules. The triple-track magnetic sensor chip has four states, i.e., reset, sleep, swiping card and data read-out. In sleep state, the internal RC oscillator is closed, which means that the digital part does not operate to optimize energy consumption. In order to improve decoding accuracy and expand the sensing range of the signal, two kinds of circuit are put forward, naming offset correction circuit, and tracking circuit. With these two circuits, the sensing function of this chip can be more efficiently and accurately. We simulated these circuit modules with TSMC technology library. The results showed that these modules worked well within wide range input signal. Based on these results, the layout and tape-out were carried out. The measurement results showed that the chip do function well within a wide swipe speed range, which achieved the design target.

The role of Ethernet in providing state-of-the-art and protected industrial networking

Energy Technology Data Exchange (ETDEWEB)

Hammond, J. [GarrettCom Inc., Fremont, CA (United States)

2006-07-01

Many networks in power substations are now using Ethernet-based solutions that use specialized protocols and customized controls. This paper discussed the advantages of using Ethernet in power utility network systems. Threats to computer networks supporting process control and supervisory control and data acquisition (SCADA) systems in power utilities also were discussed, and systems and components at risk were reviewed. Higher Ethernet bandwidths now permit more data and control information to be processed by networks. Ethernet bandwidths can be used for physical security functions as well as for the control of processes and systems. Components have now been designed to provide end-to-end Ethernet installations in order to save training costs. New security features include anti-hacking protocols, firewalls, and password protection, and card and badge readers for physical intrusion protection. Traffic restrictions have been implemented between designed ports in order to create secure traffic domains. It was concluded that Ethernet can provide the level of security needed to protect important energy infrastructure.

High-speed high-sensitivity infrared spectroscopy using mid-infrared swept lasers (Conference Presentation)

Science.gov (United States)

Childs, David T. D.; Groom, Kristian M.; Hogg, Richard A.; Revin, Dmitry G.; Cockburn, John W.; Rehman, Ihtesham U.; Matcher, Stephen J.

2016-03-01

Infrared spectroscopy is a highly attractive read-out technology for compositional analysis of biomedical specimens because of its unique combination of high molecular sensitivity without the need for exogenous labels. Traditional techniques such as FTIR and Raman have suffered from comparatively low speed and sensitivity however recent innovations are challenging this situation. Direct mid-IR spectroscopy is being speeded up by innovations such as MEMS-based FTIR instruments with very high mirror speeds and supercontinuum sources producing very high sample irradiation levels. Here we explore another possible method - external cavity quantum cascade lasers (EC-QCL's) with high cavity tuning speeds (mid-IR swept lasers). Swept lasers have been heavily developed in the near-infrared where they are used for non-destructive low-coherence imaging (OCT). We adapt these concepts in two ways. Firstly by combining mid-IR quantum cascade gain chips with external cavity designs adapted from OCT we achieve spectral acquisition rates approaching 1 kHz and demonstrate potential to reach 100 kHz. Secondly we show that mid-IR swept lasers share a fundamental sensitivity advantage with near-IR OCT swept lasers. This makes them potentially able to achieve the same spectral SNR as an FTIR instrument in a time x N shorter (N being the number of spectral points) under otherwise matched conditions. This effect is demonstrated using measurements of a PDMS sample. The combination of potentially very high spectral acquisition rates, fundamental SNR advantage and the use of low-cost detector systems could make mid-IR swept lasers a powerful technology for high-throughput biomedical spectroscopy.

Variation Tolerant On-Chip Interconnects

CERN Document Server

Nigussie, Ethiopia Enideg

2012-01-01

This book presents design techniques, analysis and implementation of high performance and power efficient, variation tolerant on-chip interconnects.  Given the design paradigm shift to multi-core, interconnect-centric designs and the increase in sources of variability and their impact in sub-100nm technologies, this book will be an invaluable reference for anyone concerned with the design of next generation, high-performance electronics systems. Provides comprehensive, circuit-level explanation of high-performance, energy-efficient, variation-tolerant on-chip interconnect; Describes design techniques to mitigate problems caused by variation; Includes techniques for design and implementation of self-timed on-chip interconnect, delay variation insensitive communication protocols, high speed signaling techniques and circuits, bit-width independent completion detection and process, voltage and temperature variation tolerance.                          

A rapid protection switching method in carrier ethernet ring networks

Science.gov (United States)

Yuan, Liang; Ji, Meng

2008-11-01

Abstract: Ethernet is the most important Local Area Network (LAN) technology since more than 90% data traffic in access layer is carried on Ethernet. From 10M to 10G, the improving Ethernet technology can be not only used in LAN, but also a good choice for MAN even WAN. MAN are always constructed in ring topology because the ring network could provide resilient path protection by using less resource (fibre or cable) than other network topologies. In layer 2 data networks, spanning tree protocol (STP) is always used to protect transmit link and preventing the formation of logic loop in networks. However, STP cannot guarantee the efficiency of service convergence when link fault happened. In fact, convergent time of networks with STP is about several minutes. Though Rapid Spanning Tree Protocol (RSTP) and Multi-Spanning Tree Protocol (MSTP) improve the STP technology, they still need a couple of seconds to achieve convergence, and can not provide sub-50ms protection switching. This paper presents a novel rapid ring protection method (RRPM) for carrier Ethernet. Unlike other link-fault detection method, it adopts distributed algorithm to detect link fault rapidly (sub-50ms). When networks restore from link fault, it can revert to the original working state. RRPM can provide single ring protection and interconnected ring protection without the formation of super loop. In normal operation, the master node blocks the secondary port for all non-RRPM Ethernet frames belonging to the given RRPM Ring, thereby avoiding a loop in the ring. When link fault happens, the node on which the failure happens moves from the "ring normal" state to the "ring fault" state. It also sends "link down" frame immediately to other nodes and blocks broken port and flushes its forwarding database. Those who receive "link down" frame will flush forwarding database and master node should unblock its secondary port. When the failure restores, the whole ring will revert to the normal state. That is

Modelling Of Residual Stresses Induced By High Speed Milling Process

International Nuclear Information System (INIS)

Desmaison, Olivier; Mocellin, Katia; Jardin, Nicolas

2011-01-01

Maintenance processes used in heavy industries often include high speed milling operations. The reliability of the post-process material state has to be studied. Numerical simulation appears to be a very interesting way to supply an efficient residual stresses (RS) distribution prediction.Because the adiabatic shear band and the serrated chip shaping are features of the austenitic stainless steel high speed machining, a 2D high speed orthogonal cutting model is briefly presented. This finite element model, developed on Forge registered software, is based on data taken from Outeiro and al.'s paper [1]. A new behaviour law fully coupling Johnson-Cook's constitutive law and Latham and Cockcroft's damage model is detailed in this paper. It ensures results that fit those found in literature.Then, the numerical tools used on the 2D model are integrated to a 3D high speed milling model. Residual stresses distribution is analysed, on the surface and into the depth of the material. Various revolutions and passes of the two teeth hemispheric mill on the workpiece are simulated. Thus the sensitivity of the residual stresses generation to the cutting conditions can be discussed. In order to validate the 3D model, a comparison of the cutting forces measured by EDF R and D to those given by numerical simulations is achieved.

Subsurface damage mechanism of high speed grinding process in single crystal silicon revealed by atomistic simulations

International Nuclear Information System (INIS)

Li, Jia; Fang, Qihong; Zhang, Liangchi; Liu, Youwen

2015-01-01

Highlights: • Molecular dynamic model of nanoscale high speed grinding of silicon workpiece has been established. • The effect of grinding speed on subsurface damage and grinding surface integrity by analyzing the chip, dislocation movement, and phase transformation during high speed grinding process are thoroughly investigated. • Subsurface damage is studied by the evolution of surface area at first time for more obvious observation on transition from ductile to brittle. • The hydrostatic stress and von Mises stress by the established analytical model are studied subsurface damage mechanism during nanoscale grinding. - Abstract: Three-dimensional molecular dynamics (MD) simulations are performed to investigate the nanoscale grinding process of single crystal silicon using diamond tool. The effect of grinding speed on subsurface damage and grinding surface integrity by analyzing the chip, dislocation movement, and phase transformation are studied. We also establish an analytical model to calculate several important stress fields including hydrostatic stress and von Mises stress for studying subsurface damage mechanism, and obtain the dislocation density on the grinding subsurface. The results show that a higher grinding velocity in machining brittle material silicon causes a larger chip and a higher temperature, and reduces subsurface damage. However, when grinding velocity is above 180 m s −1 , subsurface damage thickness slightly increases because a higher grinding speed leads to the increase in grinding force and temperature, which accelerate dislocation nucleation and motion. Subsurface damage is studied by the evolution of surface area at first time for more obvious observation on transition from ductile to brittle, that provides valuable reference for machining nanometer devices. The von Mises stress and the hydrostatic stress play an important role in the grinding process, and explain the subsurface damage though dislocation mechanism under high

IEEE 8023 ethernet, current status and future prospects at the LHC

CERN Document Server

Dobinson, Robert W; Haas, S; Martin, B; Le Vine, M J; Saka, F

2000-01-01

The status of the IEEE 802.3 standard is reviewed and prospects for the future, including the new 10 Gigabit version of Ethernet, are discussed. The relevance of Ethernet for experiments at the CERN Large Hadron Collider is considered, with emphasis on on-line applications and areas which are technically challenging. 8 Refs.

High-speed architecture for the decoding of trellis-coded modulation

Science.gov (United States)

Osborne, William P.

1992-01-01

Since 1971, when the Viterbi Algorithm was introduced as the optimal method of decoding convolutional codes, improvements in circuit technology, especially VLSI, have steadily increased its speed and practicality. Trellis-Coded Modulation (TCM) combines convolutional coding with higher level modulation (non-binary source alphabet) to provide forward error correction and spectral efficiency. For binary codes, the current stare-of-the-art is a 64-state Viterbi decoder on a single CMOS chip, operating at a data rate of 25 Mbps. Recently, there has been an interest in increasing the speed of the Viterbi Algorithm by improving the decoder architecture, or by reducing the algorithm itself. Designs employing new architectural techniques are now in existence, however these techniques are currently applied to simpler binary codes, not to TCM. The purpose of this report is to discuss TCM architectural considerations in general, and to present the design, at the logic gate level, or a specific TCM decoder which applies these considerations to achieve high-speed decoding.

High Precision Testbed to Evaluate Ethernet Performance for In-Car Networks

DEFF Research Database (Denmark)

Revsbech, Kasper; Madsen, Tatiana Kozlova; Schiøler, Henrik

2012-01-01

Validating safety-critical real-time systems such as in-car networks often involves a model-based performance analysis of the network. An important issue performing such analysis is to provide precise model parameters, matching the actual equipment. One way to obtain such parameters is to derive...... them by measurements of the equipment. In this work we describe the design of a testbed enabling active measurements on up to 1 [Gb=Sec] Copper based Ethernet Switches. By use of the testbed it self, we conduct a series of tests where the precision of the testbed is estimated. We find a maximum error...

High-Speed Soft-Decision Decoding of Two Reed-Muller Codes

Science.gov (United States)

Lin, Shu; Uehara, Gregory T.

1996-01-01

implement the system at high speed. Second, we will describe details of the 8-trellis diagram we found to best meet the trade-offs between chip and overall system complexity. The chosen approach implements the trellis for the (64, 40, 8) RM subcode with 32 independent sub-trellises. And third, we will describe results of our feasibility study on the implementation of such an IC chip in CMOS technology to implement one of these sub-trellises.

Cutting Temperature Investigation of AISI H13 in High Speed End Milling

Directory of Open Access Journals (Sweden)

Muhammad Riza

2016-10-01

Full Text Available Heat produced at the tool-chip interface during high speed milling operations have been known as a significant factor that affect to tool life and workpiece geometry or properties. This paper aims to investigate cutting temperature behaviours of AISI H13 (48 HRC under high speed machining circumstances during pocketing. The experiments were conducted on CNC vertical machining centre by using PVD coated carbide insert. Milling processes were done at cutting speeds 150, 200 and 250 m/min and feed rate were 0.05, 0.1 and 0.15 mm/tooth. Depths of cut applied were 0.1, 0.15 and 0.2 mm. Tool path method applied in this experiment was contour in. Results presented in this paper indicate that by increasing cutting speed the cutting temperature is lower than low cutting speed. However, by decreasing feed rate leads to cutting temperature low. Cutting temperature phenomena at the corner of pocket milling were also investigated. The phenomena showed that cutting temperature tends to decrease a moment when cutter comes to the corner of pocket and turning point of tool path and increase extremely a moment before leaving the corner and turning point.

Optimal multicasting in a multi-line-rate ethernet-over-WDM network

Science.gov (United States)

Harve, Shruthi; Batayneh, Marwan; Mukherjee, Biswanath

2009-11-01

Ethernet is the dominant transport technology for Local Area Networks. Efforts are now under way to use carrier-grade Ethernet in backbone networks of different service providers. With the advent of applications such as IPTV and Videoon- Demand, there is need for techniques to route multicast traffic over the Ethernet backbone networks. Here, we address the problem of Routing and Wavelength Assignment (RWA) of a set of multicast requests in a Multi-Line-Rate Ethernet backbone network with the objective of minimizing the cost of setting up the network, in terms of the Service Provider's Capital Expenditure (CAPEX). We present an Auxiliary Graph based heuristic algorithm that routes each multicast request on a light-tree structure, and assigns minimum cost wavelengths along the route. We compare the properties of the algorithm to the optimal solution given by a mathematical model formulated as an Integer Linear Program (ILP), and show that they compare very well. We also find that the algorithm is most cost-effective when the incoming requests are processed in descending order of their bandwidth requirements.

Development of Ethernet emulation driver for reflective memory

International Nuclear Information System (INIS)

Seo, Seong-Heon

2010-01-01

Reflective memory (RFM) is adopted as a real time network in the KSTAR plasma control system (PCS). Since the data uploaded from any computer are automatically shared among all the computers on the RFM network, the design of a distributed control system based on RFM is easily implemented through the management of memory mapping. The data providers and consumers are logically well seperated so that, if memory mapping information is given, a new control unit can be added without any modification to the existing system except connecting a new RFM module through an optical cable. The KSTAR PCS is also connected with the Ethernet in addition to the RFM because the RFM does not support the Transmission Control Protocol/Internet Protocol (TCP/IP) and many network services of the operating system such as the Network File System (NFS) and the Secure Shell (SSH) are based on the TCP/IP. Therefore we developed an Ethernet emulation driver for the RFM to eliminate the need for a separate Ethernet network. The driver was tested on the Linux kernel 2.6.31. The algorithm of the emulation driver is explained and the experimental setup is presented.

Performance analysis of Ethernet PON system accommodating 64 ONUs

Science.gov (United States)

Tanaka, Keiji; Ohara, Kazuho; Miyazaki, Noriyuki; Edagawa, Noboru

2007-05-01

We report the performance of an IEEE 802.3 standard compliant Ethernet passive optical network (EPON) system accommodating 64 optical network units (ONUs). After investigating the optical transmission performance, we successfully demonstrate that a high throughput of more than 900Mbits/s can be achieved in a 64-ONU EPON system using multiple logical link identifiers per ONU within a range of 10km. In addition, we confirm the feasibility of IP-based high-quality triple play services in the EPON system.

The difference of delay time in monitoring system of facial acupressure learning media using bluetooth, wireless and ethernet

Science.gov (United States)

Agustin, Eny Widhia; Hangga, Arimaz; Fahrian, Muhammad Iqbal; Azhari, Anis Fikri

2018-03-01

The implementation of monitoring system in the facial acupressure learning media could increase the students' proficiency. However the common learning media still has not implemented a monitoring system in their learning process. This research was conducted to implement monitoring system in the mannequin head prototype as a learning media of facial acupressure using Bluetooth, wireless and Ethernet. The results of the implementation of monitoring system in the prototype showed that there were differences in the delay time between Bluetooth and wireless or Ethernet. The results data showed no difference in the average delay time between the use of Bluetooth with wireless and the use of Bluetooth with Ethernet in monitoring system of facial acupressure learning media. From all the facial acupressure points, the forehead facial acupressure point has the longest delay time of 11.93 seconds. The average delay time in all 3 class rooms was 1.96 seconds therefore the use of Bluetooth, wireless and Ethernet is highly recommended in the monitoring system of facial acupressure.

On-chip power delivery and management

CERN Document Server

Vaisband, Inna P; Popovich, Mikhail; Mezhiba, Andrey V; Köse, Selçuk; Friedman, Eby G

2016-01-01

This book describes methods for distributing power in high speed, high complexity integrated circuits with power levels exceeding many tens of watts and power supplies below a volt. It provides a broad and cohesive treatment of power delivery and management systems and related design problems, including both circuit network models and design techniques for on-chip decoupling capacitors, providing insight and intuition into the behavior and design of on-chip power distribution systems. Organized into subareas to provide a more intuitive flow to the reader, this fourth edition adds more than a hundred pages of new content, including inductance models for interdigitated structures, design strategies for multi-layer power grids, advanced methods for efficient power grid design and analysis, and methodologies for simultaneously placing on-chip multiple power supplies and decoupling capacitors. The emphasis of this additional material is on managing the complexity of on-chip power distribution networks.

The Advances, Challenges and Future Possibilities of Millimeter-Wave Chip-to-Chip Interconnections for Multi-Chip Systems

Directory of Open Access Journals (Sweden)

Amlan Ganguly

2018-02-01

Full Text Available With aggressive scaling of device geometries, density of manufacturing faults is expected to increase. Therefore, yield of complex Multi-Processor Systems-on-Chips (MP-SoCs will decrease due to higher probability of manufacturing defects especially, in dies with large area. Therefore, disintegration of large SoCs into smaller chips called chiplets will improve yield and cost of complex platform-based systems. This will also provide functional flexibility, modular scalability as well as the capability to integrate heterogeneous architectures and technologies in a single unit. However, with scaling of the number of chiplets in such a system, the shared resources in the system such as the interconnection fabric and memory modules will become performance bottlenecks. Additionally, the integration of heterogeneous chiplets operating at different frequencies and voltages can be challenging. State-of-the-art inter-chip communication requires power-hungry high-speed I/O circuits and data transfer over long wired traces on substrates. This increases energy consumption and latency while decreasing data bandwidth for chip-to-chip communication. In this paper, we explore the advances and the challenges of interconnecting a multi-chip system with millimeter-wave (mm-wave wireless interconnects from a variety of perspectives spanning multiple aspects of the wireless interconnection design. Our discussion on the recent advances include aspects such as interconnection topology, physical layer, Medium Access Control (MAC and routing protocols. We also present some potential paradigm-shifting applications as well as complementary technologies of wireless inter-chip communications.

1-Gb/s zero-pole cancellation CMOS transimpedance amplifier for Gigabit Ethernet applications

International Nuclear Information System (INIS)

Huang Beiju; Zhang Xu; Chen Hongda

2009-01-01

A zero-pole cancellation transimpedance amplifier (TIA) has been realized in 0.35 μm RF CMOS technology for Gigabit Ethernet applications. The TIA exploits a zero-pole cancellation configuration to isolate the input parasitic capacitance including photodiode capacitance from bandwidth deterioration. Simulation results show that the proposed TIA has a bandwidth of 1.9 GHz and a transimpedance gain of 65 dB·Ω for 1.5 pF photodiode capacitance, with a gain-bandwidth product of 3.4 THz·Ω. Even with 2 pF photodiode capacitance, the bandwidth exhibits a decline of only 300 MHz, confirming the mechanism of the zero-pole cancellation configuration. The input resistance is 50 Ω, and the average input noise current spectral density is 9.7 pA/√Hz. Testing results shows that the eye diagram at 1 Gb/s is wide open. The chip dissipates 17 mW under a single 3.3 V supply.

1-Gb/s zero-pole cancellation CMOS transimpedance amplifier for Gigabit Ethernet applications

Energy Technology Data Exchange (ETDEWEB)

Huang Beiju; Zhang Xu; Chen Hongda, E-mail: bjhuang@semi.ac.c [State Key Laboratory of Integrated Optoelectronics, Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083 (China)

2009-10-15

A zero-pole cancellation transimpedance amplifier (TIA) has been realized in 0.35 {mu}m RF CMOS technology for Gigabit Ethernet applications. The TIA exploits a zero-pole cancellation configuration to isolate the input parasitic capacitance including photodiode capacitance from bandwidth deterioration. Simulation results show that the proposed TIA has a bandwidth of 1.9 GHz and a transimpedance gain of 65 dB{center_dot}{Omega} for 1.5 pF photodiode capacitance, with a gain-bandwidth product of 3.4 THz{center_dot}{Omega}. Even with 2 pF photodiode capacitance, the bandwidth exhibits a decline of only 300 MHz, confirming the mechanism of the zero-pole cancellation configuration. The input resistance is 50 {Omega}, and the average input noise current spectral density is 9.7 pA/{radical}Hz. Testing results shows that the eye diagram at 1 Gb/s is wide open. The chip dissipates 17 mW under a single 3.3 V supply.

Optical bio-sensors in microfluidic chips

NARCIS (Netherlands)

Pollnau, Markus; Dongre, C.; Pham Van So, P.V.S.; Bernhardi, Edward; Worhoff, Kerstin; de Ridder, R.M.; Hoekstra, Hugo

2012-01-01

Direct femtosecond laser writing is used to integrate optical waveguides that intersect the microfluidic channels in a commercial optofluidic chip. With laser excitation, fluorescently labeled DNA molecules of different sizes are separated by capillary electrophoresis with high operating speed and

Link layer topology discovery in an uncooperative ethernet environment

CSIR Research Space (South Africa)

Delport, JP

2007-05-01

Full Text Available single destination is called a unicast address. Ethernet addresses also exist for sending data to multiple stations at once and are called multicast addresses. A special address, with all the bits in the address set to one (FF:FF:FF:FF:FF:FF), is used... P (2007) 2.4. Relevant Ethernet Concepts 14 Destination and source addresses are MAC addresses as defined in Sec- tion 2.4.2. The destination address might contain a unicast, multicast or broadcast address. The length or type field allows two types...

SPIDR, a general-purpose readout system for pixel ASICs

International Nuclear Information System (INIS)

Heijden, B. van der; Visser, J.; Beuzekom, M. van; Boterenbrood, H.; Munneke, B.; Schreuder, F.; Kulis, S.

2017-01-01

The SPIDR (Speedy PIxel Detector Readout) system is a flexible general-purpose readout platform that can be easily adapted to test and characterize new and existing detector readout ASICs. It is originally designed for the readout of pixel ASICs from the Medipix/Timepix family, but other types of ASICs or front-end circuits can be read out as well. The SPIDR system consists of an FPGA board with memory and various communication interfaces, FPGA firmware, CPU subsystem and an API library on the PC . The FPGA firmware can be adapted to read out other ASICs by re-using IP blocks. The available IP blocks include a UDP packet builder, 1 and 10 Gigabit Ethernet MAC's and a 'soft core' CPU . Currently the firmware is targeted at the Xilinx VC707 development board and at a custom board called Compact-SPIDR . The firmware can easily be ported to other Xilinx 7 series and ultra scale FPGAs. The gap between an ASIC and the data acquisition back-end is bridged by the SPIDR system. Using the high pin count VITA 57 FPGA Mezzanine Card (FMC) connector only a simple chip carrier PCB is required. A 1 and a 10 Gigabit Ethernet interface handle the connection to the back-end. These can be used simultaneously for high-speed data and configuration over separate channels. In addition to the FMC connector, configurable inputs and outputs are available for synchronization with other detectors. A high resolution (≈ 27 ps bin size) Time to Digital converter is provided for time stamping events in the detector. The SPIDR system is frequently used as readout for the Medipix3 and Timepix3 ASICs. Using the 10 Gigabit Ethernet interface it is possible to read out a single chip at full bandwidth or up to 12 chips at a reduced rate. Another recent application is the test-bed for the VeloPix ASIC, which is developed for the Vertex Detector of the LHCb experiment. In this case the SPIDR system processes the 20 Gbps scrambled data stream from the VeloPix and distributes it over four

New generation of single-chip microcomputers focused on cost performance

Energy Technology Data Exchange (ETDEWEB)

Akao, Y.; Iwashita, H. (Hitachi, Ltd., Tokyo (Japan))

1993-06-01

A single-chip microcomputer which incorporates a CPU (central processing unit), memory, and peripheral functions in one chip has been increasingly applied to various fields as the heart of electronic equipment in terms of its economy, compactness, lightness, and suitability for mass production. In response to a wide variety of needs, a lineup must have substantial breadth with regard to performance, on-chip memory capacity, on-chip peripheral functions, operating voltage, and packaging. In particular, low-voltage high-speed operation, high integration, expanded address space, and improved software productivity, which are required for mobile communication terminals, are the common needs for single-chip microcomputers. In accordance with these needs, Hitachi has been actively developing new products. The present paper introduces Hitachi's lineup of single-chip microcomputers. 10 figs., 1 tab.

Physical Layer Ethernet Clock Synchronization

Science.gov (United States)

2010-11-01

42 nd Annual Precise Time and Time Interval (PTTI) Meeting 77 PHYSICAL LAYER ETHERNET CLOCK SYNCHRONIZATION Reinhard Exel, Georg...oeaw.ac.at Nikolaus Kerö Oregano Systems, Mohsgasse 1, 1030 Wien, Austria E-mail: nikolaus.keroe@oregano.at Abstract Clock synchronization ...is a service widely used in distributed networks to coordinate data acquisition and actions. As the requirement to achieve tighter synchronization

Wear mechanism of CBN cutting tool during high-speed machining of mold steel

International Nuclear Information System (INIS)

Farhat, Z.N.

2003-01-01

Wear behavior of cubic boron nitride (CBN) cutting tool when cutting P20 tool steel was investigated. Oblique cutting tests were performed on a CNC lathe using five speeds, namely, 240, 600 and 1000 m min -1 . The CBN cutting tools were found to be superior to tungsten carbide (WC) tools. Fourfold increase in productivity and significant reduction in chipping and cratering was achieved for CBN as compared to WC. Wear, as the width of the wear land (VB), was monitored at selected time intervals; furthermore, topography of worn surfaces was performed, using a profilometer. Wear characterization of the rake and the flank surfaces as well as of the collected chips was conducted using a scanning electron microscopy (SEM), backscattered electron imaging and energy depressive X-ray (EDX). It was found that deformation in the chips occurs by localized shear deformation and the dominant wear mechanism at all speeds used was identified to be diffusive wear. At a 1000 m min -1 cutting speed, a secondary wear mechanism was identified, which is melt wear, i.e., formation of low melting point Cr and Mn compounds with the tool material and the subsequent ejection from the cutting zone

Reconfigurable radio-frequency arbitrary waveforms synthesized in a silicon photonic chip.

Science.gov (United States)

Wang, Jian; Shen, Hao; Fan, Li; Wu, Rui; Niu, Ben; Varghese, Leo T; Xuan, Yi; Leaird, Daniel E; Wang, Xi; Gan, Fuwan; Weiner, Andrew M; Qi, Minghao

2015-01-12

Photonic methods of radio-frequency waveform generation and processing can provide performance advantages and flexibility over electronic methods due to the ultrawide bandwidth offered by the optical carriers. However, bulk optics implementations suffer from the lack of integration and slow reconfiguration speed. Here we propose an architecture of integrated photonic radio-frequency generation and processing and implement it on a silicon chip fabricated in a semiconductor manufacturing foundry. Our device can generate programmable radio-frequency bursts or continuous waveforms with only the light source, electrical drives/controls and detectors being off-chip. It modulates an individual pulse in a radio-frequency burst within 4 ns, achieving a reconfiguration speed three orders of magnitude faster than thermal tuning. The on-chip optical delay elements offer an integrated approach to accurately manipulating individual radio-frequency waveform features without constraints set by the speed and timing jitter of electronics, and should find applications ranging from high-speed wireless to defence electronics.

Design and Construction of a High-speed Network Connecting All the Protein Crystallography Beamlines at the Photon Factory

International Nuclear Information System (INIS)

Matsugaki, Naohiro; Yamada, Yusuke; Igarashi, Noriyuki; Wakatsuki, Soichi

2007-01-01

A private network, physically separated from the facility network, was designed and constructed which covered all the four protein crystallography beamlines at the Photon Factory (PF) and Structural Biology Research Center (SBRC). Connecting all the beamlines in the same network allows for simple authentication and a common working environment for a user who uses multiple beamlines. Giga-bit Ethernet wire-speed was achieved for the communication among the beamlines and SBRC buildings

IEEE 802.3 Ethernet, Current Status and Future Prospects at the LHC

CERN Document Server

Dobinson, Robert W; Haas, S W; Martin, B; Le Vine, M J; Saka, F

2000-01-01

The status of the IEEE 802.3 standard is reviewed and prospects for the future, including the new 10 Gigabit version of Ethernet, are discussed. The relevance of Ethernet for experiments at the CERN Large Hadron Collider is considered, with emphasis on on-line applications and areas which are technically challenging.

Flexible multimode polymer waveguides for high-speed short-reach communication links

Science.gov (United States)

Bamiedakis, N.; Shi, F.; Chu, D.; Penty, R. V.; White, I. H.

2018-02-01

Multimode polymer waveguides have attracted great interest for use in high-speed short-reach communication links as they can be cost-effectively integrated onto standard PCBs using conventional methods of the electronics industry and provide low loss (30 GHz×m) interconnection. The formation of such waveguides on flexible substrates can further provide flexible low-weight low-thickness interconnects and offer additional freedom in the implementation of high-speed short-reach optical links. These attributes make these flexible waveguides particularly attractive for use in low-cost detachable chip-to-chip links and in environments where weight and shape conformity become important, such as in cars and aircraft. However, the highly-multimoded nature of these waveguides raises important questions about their performance under severe flex due to mode loss and mode coupling. In this work therefore, we investigate the loss, crosstalk and bandwidth performance of such waveguides under out-of plane bending and in-plane twisting under different launch conditions and carry out data transmission tests at 40 Gb/s on a 1 m long spiral flexible waveguide under flexure. Excellent optical transmission characteristics are obtained while robust loss, crosstalk and bandwidth performance are demonstrated under flexure. Error-free (BER<10-12) 40 Gb/s data transmission is achieved over the 1 m long spiral waveguide for a 180° bend with a 4 mm radius. The obtained results demonstrate the excellent optical and mechanical properties of this technology and highlight its potential for use in real-world systems.

Division Multiplexing of 10 Gbit/s Ethernet Signals Synchronized by All-Optical Signal Processing Based on a Time-Lens

DEFF Research Database (Denmark)

Areal, Janaina Laguardia

This Thesis presents 3 years work of an optical circuit that performs both pulse compression and frame synchronization and retiming. Our design aims at directly multiplexing several 10G Ethernet data packets (frames) to a high-speed OTDM link. This scheme is optically trans-parent and does not re...... coupler, completing the OTDM signal generation. We demonstrate the effectiveness of the design by laboratory experi-ments and simulations with VPI and MatLab....... not require clock recovery, resulting in a potentially very efficient solution. The scheme uses a time-lens, implemented through a sinusoidally driven optical phase modulation, combined with a linear dispersion element. As time-lenses are also used for pulse compression, we de-sign the circuit also to perform...

Characterization of Tool Wear in High-Speed Milling of Hardened Powder Metallurgical Steels

Directory of Open Access Journals (Sweden)

Fritz Klocke

2011-01-01

Full Text Available In this experimental study, the cutting performance of ball-end mills in high-speed dry-hard milling of powder metallurgical steels was investigated. The cutting performance of the milling tools was mainly evaluated in terms of cutting length, tool wear, and cutting forces. Two different types of hardened steels were machined, the cold working steel HS 4-2-4 PM (K490 Microclean/66 HRC and the high speed steel HS 6-5-3 PM (S790 Microclean/64 HRC. The milling tests were performed at effective cutting speeds of 225, 300, and 400 m/min with a four fluted solid carbide ball-end mill (0 = 6, TiAlN coating. It was observed that by means of analytically optimised chipping parameters and increased cutting speed, the tool life can be drastically enhanced. Further, in machining the harder material HS 4-2-4 PM, the tool life is up to three times in regard to the less harder material HS 6-5-3 PM. Thus, it can be assumed that not only the hardness of the material to be machined plays a vital role for the high-speed dry-hard cutting performance, but also the microstructure and thermal characteristics of the investigated powder metallurgical steels in their hardened state.

Optical Time-Division Multiplexing of 10 Gbit/s Ethernet Signals Synchronized by All-Optical Signal Processing Based on a Time-Lens

DEFF Research Database (Denmark)

Areal, Janaina Laguardia

This Thesis presents 3 years work of an optical circuit that performs both pulse compression and frame synchronization and retiming. Our design aims at directly multiplexing several 10G Ethernet data packets (frames) to a high-speed OTDM link. This scheme is optically transparent and does not req...... coupler, completing the OTDM signal generation. We demonstrate the effectiveness of the design by laboratory experiments and simulations with VPI and MatLab....... not require clock recovery, resulting in a potentially very efficient solution. The scheme uses a time-lens, implemented through a sinusoidally driven optical phase modulation, combined with a linear dispersion element. As time-lenses are also used for pulse compression, we design the circuit also to perform...

Katherine: Ethernet Embedded Readout Interface for Timepix3

Science.gov (United States)

Burian, P.; Broulím, P.; Jára, M.; Georgiev, V.; Bergmann, B.

2017-11-01

The Timepix3—the latest generation of hybrid particle pixel detectors of Medipix family—yields a lot of new possibilities, i.e. a high hit-rate, a time resolution of 1.56 ns, event data-driven readout mode, and the capability of measuring the Time-over-Threshold (ToT - energy) and the Time-of-Arrival (ToA) simultaneously. This paper introduces a newly developed readout device for the Timepix3, called "Katherine", featuring a Gigabit Ethernet interface. The primary benefit of the Katherine is the operation of Timepix3 at long distance (up to 100 m) from computer or server, which is advantageous for the installation at beam lines, where the access is difficult or where radiation levels are too high for human interventions. The maximal hit-rate is limited by the bandwidth of the Ethernet connection (peer-to-peer connection; up to 16 Mhit/s). Since the Katherine interface is equipped with a processor of high computational power (ARM Cortex-A9 dual-core processor), it permits the use as a stand-alone (autonomous) radiation detector. The key features of the device are described in detail. These are the implemented high voltage power supply offering both polarities of bias voltage (up to ± 300 V), the automatic data sending to a sever via SSH, the automatic compensation of ToA values from columns with shifted matrix clock, etc. A dedicated control software was developed, which can be used for the detector preparation (sensor equalization, the DACs dependency scan, and the THL scan) and measurement control. Measured energy spectra from photon fields are shown.

Evaluation of restoration mechanisms for future services using Carrier Ethernet

DEFF Research Database (Denmark)

Wessing, Henrik; Berger, Michael Stübert; Gestsson, H.M.

2010-01-01

In this paper, we evaluate and classify future service according to their requirements for delay, loss and bandwidth. The most demanding services include IPTV in different forms, hence IPTV is used as a representative for future services. Carrier Ethernet technologies are introduced with special...... focus on its OAM functionalities, and it is evaluated how IPTV performs in case of link failures on a Carrier Ethernet implementation. It is concluded that OAM update times of 10 ms is required to provide acceptable restoration performance in case of errors....

High-speed uncooled MWIR hostile fire indication sensor

Science.gov (United States)

Zhang, L.; Pantuso, F. P.; Jin, G.; Mazurenko, A.; Erdtmann, M.; Radhakrishnan, S.; Salerno, J.

2011-06-01

Hostile fire indication (HFI) systems require high-resolution sensor operation at extremely high speeds to capture hostile fire events, including rocket-propelled grenades, anti-aircraft artillery, heavy machine guns, anti-tank guided missiles and small arms. HFI must also be conducted in a waveband with large available signal and low background clutter, in particular the mid-wavelength infrared (MWIR). The shortcoming of current HFI sensors in the MWIR is the bandwidth of the sensor is not sufficient to achieve the required frame rate at the high sensor resolution. Furthermore, current HFI sensors require cryogenic cooling that contributes to size, weight, and power (SWAP) in aircraft-mounted applications where these factors are at a premium. Based on its uncooled photomechanical infrared imaging technology, Agiltron has developed a low-SWAP, high-speed MWIR HFI sensor that breaks the bandwidth bottleneck typical of current infrared sensors. This accomplishment is made possible by using a commercial-off-the-shelf, high-performance visible imager as the readout integrated circuit and physically separating this visible imager from the MWIR-optimized photomechanical sensor chip. With this approach, we have achieved high-resolution operation of our MWIR HFI sensor at 1000 fps, which is unprecedented for an uncooled infrared sensor. We have field tested our MWIR HFI sensor for detecting all hostile fire events mentioned above at several test ranges under a wide range of environmental conditions. The field testing results will be presented.

Ultrahigh-speed, high-sensitivity color camera with 300,000-pixel single CCD

Science.gov (United States)

Kitamura, K.; Arai, T.; Yonai, J.; Hayashida, T.; Ohtake, H.; Kurita, T.; Tanioka, K.; Maruyama, H.; Namiki, J.; Yanagi, T.; Yoshida, T.; van Kuijk, H.; Bosiers, Jan T.; Etoh, T. G.

2007-01-01

We have developed an ultrahigh-speed, high-sensitivity portable color camera with a new 300,000-pixel single CCD. The 300,000-pixel CCD, which has four times the number of pixels of our initial model, was developed by seamlessly joining two 150,000-pixel CCDs. A green-red-green-blue (GRGB) Bayer filter is used to realize a color camera with the single-chip CCD. The camera is capable of ultrahigh-speed video recording at up to 1,000,000 frames/sec, and small enough to be handheld. We also developed a technology for dividing the CCD output signal to enable parallel, highspeed readout and recording in external memory; this makes possible long, continuous shots up to 1,000 frames/second. As a result of an experiment, video footage was imaged at an athletics meet. Because of high-speed shooting, even detailed movements of athletes' muscles were captured. This camera can capture clear slow-motion videos, so it enables previously impossible live footage to be imaged for various TV broadcasting programs.

Use of Ethernet and TCP/IP socket communications library routines for data acquisition and control in the LEP RF system

International Nuclear Information System (INIS)

Ciapala, E.; Collier, P.; Lienard, P.

1991-01-01

A general move is being made at CERN towards the direct connection of intelligent equipment and device controllers to the control room consoles by the use of local Ethernet segments bridged to the main Token Ring networks. Communications is based on standard TCP/IP protocols which allows immediate use of standard software packages. The Data Managers which control the LEP RF accelerating units and transverse feedback systems have recently been connected. The implementation of Ethernet and TCP/IP socket communications routines for RF data acquisition and control is described. The adaptation of almost all of the existing software for RF system control, data acquisition and diagnostics to make use of this means of communication has proved straightforward. Furthermore the transparent transfer of data in the form of 'C' structures from the Data Managers to the control center workstations and other computers has considerably simplified the software required for remote surveillance and data logging with a corresponding increase in speed and reliability

Enterasys Networks delivers standards-based 10-Gigabit ethernet modules for its Enterasys X-Pedition Routers and Enterasys Matrix Switches

CERN Multimedia

2002-01-01

Enterasys Networks Inc. has announced new 10-Gigabit Ethernet modules for the Enterasys X-Pedition ER16 routers and Enterasys Matrix E1 OAS (Optical Access Switch). The addition of 10-Gigabit Ethernet technology enables the Enterasys X-Pedition ER16 enables real-time delivery of high-bandwidth, advanced applications across local area network (LAN), wide area network (WAN) and metropolitan area network (MAN) environments (1/2 page).

Using a Commercial Ethernet PHY Device in a Radiation Environment

Science.gov (United States)

Parks, Jeremy; Arani, Michael; Arroyo, Roberto

2014-01-01

This work involved placing a commercial Ethernet PHY on its own power boundary, with limited current supply, and providing detection methods to determine when the device is not operating and when it needs either a reset or power-cycle. The device must be radiation-tested and free of destructive latchup errors. The commercial Ethernet PHY's own power boundary must be supplied by a current-limited power regulator that must have an enable (for power cycling), and its maximum power output must not exceed the PHY's input requirements, thus preventing damage to the device. A regulator with configurable output limits and short-circuit protection (such as the RHFL4913, rad hard positive voltage regulator family) is ideal. This will prevent a catastrophic failure due to radiation (such as a short between the commercial device's power and ground) from taking down the board's main power. Logic provided on the board will detect errors in the PHY. An FPGA (field-programmable gate array) with embedded Ethernet MAC (Media Access Control) will work well. The error detection includes monitoring the PHY's interrupt line, and the status of the Ethernet's switched power. When the PHY is determined to be non-functional, the logic device resets the PHY, which will often clear radiation induced errors. If this doesn't work, the logic device power-cycles the FPGA by toggling the regulator's enable input. This should clear almost all radiation induced errors provided the device is not latched up.

Ultrahigh-speed hybrid laser for silicon photonic integrated chips

DEFF Research Database (Denmark)

Chung, Il-Sug; Park, Gyeong Cheol; Ran, Qijiang

2013-01-01

Increasing power consumption for electrical interconnects between and inside chips is posing a real challenge to continue the performance scaling of processors/computers as predicted by D. Moore. In recent processors, energy consumption for electrical interconnects is half of power supplied...... and will be 80% in near future. This challenge strongly has motivated replacing electrical interconnects with optical ones even in chip level communications [1]. This chip-level optical interconnects need quite different performance of optoelectronic devices than required for conventional optical communications....... For a light source, the energy consumption per sending a bit is required to be

Towards Chip Scale Liquid Chromatography and High Throughput Immunosensing

Energy Technology Data Exchange (ETDEWEB)

Ni, Jing [Iowa State Univ., Ames, IA (United States)

2000-09-21

This work describes several research projects aimed towards developing new instruments and novel methods for high throughput chemical and biological analysis. Approaches are taken in two directions. The first direction takes advantage of well-established semiconductor fabrication techniques and applies them to miniaturize instruments that are workhorses in analytical laboratories. Specifically, the first part of this work focused on the development of micropumps and microvalves for controlled fluid delivery. The mechanism of these micropumps and microvalves relies on the electrochemically-induced surface tension change at a mercury/electrolyte interface. A miniaturized flow injection analysis device was integrated and flow injection analyses were demonstrated. In the second part of this work, microfluidic chips were also designed, fabricated, and tested. Separations of two fluorescent dyes were demonstrated in microfabricated channels, based on an open-tubular liquid chromatography (OT LC) or an electrochemically-modulated liquid chromatography (EMLC) format. A reduction in instrument size can potentially increase analysis speed, and allow exceedingly small amounts of sample to be analyzed under diverse separation conditions. The second direction explores the surface enhanced Raman spectroscopy (SERS) as a signal transduction method for immunoassay analysis. It takes advantage of the improved detection sensitivity as a result of surface enhancement on colloidal gold, the narrow width of Raman band, and the stability of Raman scattering signals to distinguish several different species simultaneously without exploiting spatially-separated addresses on a biochip. By labeling gold nanoparticles with different Raman reporters in conjunction with different detection antibodies, a simultaneous detection of a dual-analyte immunoassay was demonstrated. Using this scheme for quantitative analysis was also studied and preliminary dose-response curves from an immunoassay of a

High speed machinability of the aerospace alloy AA7075 T6 under different cooling conditions

Science.gov (United States)

Imbrogno, Stano; Rinaldi, Sergio; Suarez, Asier Gurruchaga; Arrazola, Pedro J.; Umbrello, Domenico

2018-05-01

This paper describes the results of an experimental investigation aimed to st udy the machinability of AA7075 T6 (160 HV) for aerospace industry at high cutting speeds. The paper investigates the effects of different lubri-cooling strategies (cryogenic, M QL and dry) during high speed turning process on cutting forces, tool wear, chip morphology and cutting temperatures. The cutting speeds selected were 1000m/min, 1250m/min and 1500 m/min, while the feed rate values used were 0.1mm/rev and 0.3 mm/rev. The results of cryogenic and M QL application is compared with dry application. It was found that the cryogenic and M QL lubri-cooling techniques could represent a functional alternative to the common dry cutting application in order to implement a more effect ive high speed turning process. Higher cuttingparameters would be able to increase the productivity and reduce the production costs. The effects of the cutting parameters and on the variables object of study were investigated and the role of the different lubri-cooling conditions was assessed.

The Design of Passive Optical Networking+Ethernet over Coaxial Cable Access Networking and Video-on-Demand Services Carrying

Science.gov (United States)

Ji, Wei

2013-07-01

Video on demand is a very attractive service used for entertainment, education, and other purposes. The design of passive optical networking+Ethernet over coaxial cable accessing and a home gateway system is proposed. The network integrates the passive optical networking and Ethernet over coaxial cable to provide high dedicated bandwidth for the metropolitan video-on-demand services. Using digital video broadcasting, IP television protocol, unicasting, and broadcasting mechanisms maximizes the system throughput. The home gateway finishes radio frequency signal receiving and provides three kinds of interfaces for high-definition video, voice, and data, which achieves triple-play and wire/wireless access synchronously.

A proposed holistic approach to on-chip, off-chip, test, and package interconnections

Science.gov (United States)

Bartelink, Dirk J.

1998-11-01

The term interconnection has traditionally implied a `robust' connection from a transistor or a group of transistors in an IC to the outside world, usually a PC board. Optimum system utilization is done from outside the IC. As an alternative, this paper addresses `unimpeded' transistor-to-transistor interconnection aimed at reaching the high circuit densities and computational capabilities of neighboring IC's. In this view, interconnections are not made to some human-centric place outside the IC world requiring robustness—except for system input and output connections. This unimpeded interconnect style is currently available only through intra-chip signal traces in `system-on-a-chip' implementations, as exemplified by embedded DRAMs. Because the traditional off-chip penalty in performance and wiring density is so large, a merging of complex process technologies is the only option today. It is suggested that, for system integration to move forward, the traditional robustness requirement inherited from conventional packaging interconnect and IC manufacturing test must be discarded. Traditional system assembly from vendor parts requires robustness under shipping, inspection and assembly. The trend toward systems on a chip signifies willingness by semiconductor companies to design and fabricate whole systems in house, so that `in-house' chip-to-chip assembly is not beyond reach. In this scenario, bare chips never leave the controlled environment of the IC fabricator while the two major contributors to off-chip signal penalty, ESD protection and the need to source a 50-ohm test head, are avoided. With in-house assembly, ESD protection can be eliminated with the precautions already familiar in plasma etching. Test interconnection impacts the fundamentals of IC manufacturing, particularly with clock speeds approaching 1GHz, and cannot be an afterthought. It should be an integral part of the chip-to-chip interconnection bandwidth optimization, because—as we must

High speed atom source

International Nuclear Information System (INIS)

Hoshino, Hitoshi.

1990-01-01

In a high speed atom source, since the speed is not identical between ions and electrons, no sufficient neutralizing effect for ionic rays due to the mixing of the ionic rays and the electron rays can be obtained failing to obtain high speed atomic rays at high density. In view of the above, a speed control means is disposed for equalizing the speed of ions forming ionic rays and the speed of electrons forming electron rays. Further, incident angle of the electron rays and/or ionic rays to a magnet or an electrode is made variable. As a result, the relative speed between the ions and the electrons to the processing direction is reduced to zero, in which the probability of association between the ions and the electrons due to the coulomb force is increased to improve the neutralizing efficiency to easily obtain fine and high density high speed electron rays. Further, by varying the incident angle, a track capable of obtaining an ideal mixing depending on the energy of the neutralized ionic rays is formed. Since the high speed electron rays has such high density, they can be irradiated easily to the minute region of the specimen. (N.H.)

Flow Monitoring Experiences at the Ethernet-Layer

NARCIS (Netherlands)

Hofstede, Rick; Hofstede, R.J.; Drago, Idilio; Sperotto, Anna; Pras, Aiko; Lehnert, Ralf

2011-01-01

Flow monitoring is a scalable technology for providing summaries of network activity. Being deployed at the IP-layer, it uses fixed flow definitions, based on fields of the IP-layer and higher layers. Since several backbone network operators are considering the deployment of (Carrier) Ethernet in

Ethernet image communication performance in a multimodal PACS network

International Nuclear Information System (INIS)

Lou, S.L.; Valentino, D.J.; Chan, K.K.; Huang, H.K.

1989-01-01

The authors have evaluated the performance of an Ethernet network in a multimodal picture archiving and communications system (PACS) environment. The study included measurements between Sun workstations and PC- AT computers running communication software at the TCP level. First they initiated image transfers between two workstations, a server and a client. Next, they successively added clients to transfer images to the server and they measured degradation in network performance. Finally, they initiated image transfers between pairs of workstations and again measured performance degradation. The results of the authors' experiments indicate that Ethernet is suitable for image communication only in limited network situations. They discuss how to maximize network performance given these constraints

Design and reliability analysis of high-speed and continuous data recording system based on disk array

Science.gov (United States)

Jiang, Changlong; Ma, Cheng; He, Ning; Zhang, Xugang; Wang, Chongyang; Jia, Huibo

2002-12-01

In many real-time fields the sustained high-speed data recording system is required. This paper proposes a high-speed and sustained data recording system based on the complex-RAID 3+0. The system consists of Array Controller Module (ACM), String Controller Module (SCM) and Main Controller Module (MCM). ACM implemented by an FPGA chip is used to split the high-speed incoming data stream into several lower-speed streams and generate one parity code stream synchronously. It also can inversely recover the original data stream while reading. SCMs record lower-speed streams from the ACM into the SCSI disk drivers. In the SCM, the dual-page buffer technology is adopted to implement speed-matching function and satisfy the need of sustainable recording. MCM monitors the whole system, controls ACM and SCMs to realize the data stripping, reconstruction, and recovery functions. The method of how to determine the system scale is presented. At the end, two new ways Floating Parity Group (FPG) and full 2D-Parity Group (full 2D-PG) are proposed to improve the system reliability and compared with the Traditional Parity Group (TPG). This recording system can be used conveniently in many areas of data recording, storing, playback and remote backup with its high-reliability.

A computer tool to support in design of industrial Ethernet.

Science.gov (United States)

Lugli, Alexandre Baratella; Santos, Max Mauro Dias; Franco, Lucia Regina Horta Rodrigues

2009-04-01

This paper presents a computer tool to support in the project and development of an industrial Ethernet network, verifying the physical layer (cables-resistance and capacitance, scan time, network power supply-POE's concept "Power Over Ethernet" and wireless), and occupation rate (amount of information transmitted to the network versus the controller network scan time). These functions are accomplished without a single physical element installed in the network, using only simulation. The computer tool has a software that presents a detailed vision of the network to the user, besides showing some possible problems in the network, and having an extremely friendly environment.

Sniffer para redes Ethernet de tempo-real baseado em FPGA

OpenAIRE

Faria, João Pedro Puga

2008-01-01

A crescente utilização de sistemas distribuídos em aplicações de tempo-real tem levado á criação de protocolos de comunicação cada vez mais com- plexos e sofisticados. Apesar da rede Ethernet não apresentar característi- cas de tempo-real, devido ás suas vantagens, têm sido desenvolvidos muitos protocolos de comunicação tempo-real baseados em Ethernet. Nesta disser- tação é analisada a importância das arquitecturas distribuídas em aplicações de tempo-real, sendo apresentados...

Analysis and solutions of security issues in Ethernet PON

Science.gov (United States)

Meng, Yu; Jiang, Tao; Xiao, Dingzhong

2005-02-01

Ethernet Passive Optical Network (EPON), which combines the low cost Ethernet equipment and economic fiber infrastructure, is being considered as a promising solution for Fiber-To-The-Home (FTTH). However, since EPON is an optical shared medium network, some unique features make it more vulnerable to security attacks. In this paper, the key security threats of EPON are firstly analyzed. And then, considering some specific properties which might be utilized for security, such as the safety of transmissions in upstream direction, some novel methods are presented to solve security problems. Firstly, based on some modification about registration, the mechanism of access control is achieved. Secondly, we implement an AES-128 symmetrical encryption and decryption in the EPON system. The AES-128 algorithm can process data blocks of 128 bits, but the length of Ethernet frame is variable. How to deal with the last block, which is not up to 128 bits, is discussed in detail. Finally, key update is accomplished through a vendor specific OAM frame in order to enhance the level of security. The proposed mechanism will remain in conformance with P2MP specification defined by 802.3ah TF, and can supply a complete security solution for EPON.

Ultra-thin silicon (UTSi) on insulator CMOS transceiver and time-division multiplexed switch chips for smart pixel integration

Science.gov (United States)

Zhang, Liping; Sawchuk, Alexander A.

2001-12-01

We describe the design, fabrication and functionality of two different 0.5 micron CMOS optoelectronic integrated circuit (OEIC) chips based on the Peregrine Semiconductor Ultra-Thin Silicon on insulator technology. The Peregrine UTSi silicon- on-sapphire (SOS) technology is a member of the silicon-on- insulator (SOI) family. The low-loss synthetic sapphire substrate is optically transparent and has good thermal conductivity and coefficient of thermal expansion properties, which meet the requirements for flip-chip bonding of VCSELs and other optoelectronic input-output components. One chip contains transceiver and network components, including four channel high-speed CMOS transceiver modules, pseudo-random bit stream (PRBS) generators, a voltage controlled oscillator (VCO) and other test circuits. The transceiver chips can operate in both self-testing mode and networking mode. An on- chip clock and true-single-phase-clock (TSPC) D-flip-flop have been designed to generate a PRBS at over 2.5 Gb/s for the high-speed transceiver arrays to operate in self-testing mode. In the networking mode, an even number of transceiver chips forms a ring network through free-space or fiber ribbon interconnections. The second chip contains four channel optical time-division multiplex (TDM) switches, optical transceiver arrays, an active pixel detector and additional test devices. The eventual applications of these chips will require monolithic OEICs with integrated optical input and output. After fabrication and testing, the CMOS transceiver array dies will be packaged with 850 nm vertical cavity surface emitting lasers (VCSELs), and metal-semiconductor- metal (MSM) or GaAs p-i-n detector die arrays to achieve high- speed optical interconnections. The hybrid technique could be either wire bonding or flip-chip bonding of the CMOS SOS smart-pixel arrays with arrays of VCSELs and photodetectors onto an optoelectronic chip carrier as a multi-chip module (MCM).

Approaching Incast Congestion with Multi-host Ethernet Controllers

CERN Document Server

Jereczek, Grzegorz Edmund; The ATLAS collaboration

2018-01-01

The bursty many-to-one communication pattern, typical for data acquisition systems, but also present in datacenter networks, is particularly demanding for commodity TCP/IP and Ethernet technologies. We expand our study of building incast-resistant networks based on software switches running on commercial-off-the-shelf servers. In this paper we provide the estimates for costs and physical area required to build such a network. Our estimates indicate that our proposed design offers significant cost advantage over traditional solutions, but higher space utilisation. Next, we show how the latter can be improved with multi-host Ethernet controllers, as an alternative to typical network interface cards. This can also make software switching easier to adapt in datacenter as a solution for incast congestion. We confirm the capabilities for incast-avoidance by evaluating the performance of a reference platform.

Approaching Incast Congestion with Multi-host Ethernet Controllers

CERN Document Server

AUTHOR|(SzGeCERN)698154; The ATLAS collaboration; Lehmann Miotto, Giovanna; Malone, David; Walukiewicz, Miroslaw

2017-01-01

The bursty many-to-one communication pattern, typical for data acquisition systems, but also present in datacenter networks, is particularly demanding for commodity TCP/IP and Ethernet technologies. We expand our study of building incast-resistant networks based on software switches running on commercial-off-the-shelf servers. In this paper we provide the estimates for costs and physical area required to build such a network. Our estimates indicate that our proposed design offers significant cost advantage over traditional solutions, but higher space utilisation. Next, we show how the latter can be improved with multi-host Ethernet controllers, as an alternative to typical network interface cards. This can also make software switching easier to adapt in datacenter as a solution for incast congestion. We confirm the capabilities for incast-avoidance by evaluating the performance of a reference platform.

An Integrated Power-Efficient Active Rectifier With Offset-Controlled High Speed Comparators for Inductively Powered Applications

Science.gov (United States)

Lee, Hyung-Min; Ghovanloo, Maysam

2011-01-01

We present an active full-wave rectifier with offset-controlled high speed comparators in standard CMOS that provides high power conversion efficiency (PCE) in high frequency (HF) range for inductively powered devices. This rectifier provides much lower dropout voltage and far better PCE compared to the passive on-chip or off-chip rectifiers. The built-in offset-control functions in the comparators compensate for both turn-on and turn-off delays in the main rectifying switches, thus maximizing the forward current delivered to the load and minimizing the back current to improve the PCE. We have fabricated this active rectifier in a 0.5-μm 3M2P standard CMOS process, occupying 0.18 mm2 of chip area. With 3.8 V peak ac input at 13.56 MHz, the rectifier provides 3.12 V dc output to a 500 Ω load, resulting in the PCE of 80.2%, which is the highest measured at this frequency. In addition, overvoltage protection (OVP) as safety measure and built-in back telemetry capabilities have been incorporated in our design using detuning and load shift keying (LSK) techniques, respectively, and tested. PMID:22174666

Cost-effective, compact and high-speed integrable multi-mode interference modulator

NARCIS (Netherlands)

Lenstra, Daan; Yao, Weiming; Cardarelli, Simone; Mink, Jan

2017-01-01

Theoretical analysis of the modulation performance of this wave-guide device shows great potential when combined with a single-mode laser on a monolithic optical chip. On the basis of the reversed-bias electro-optic effect, modulation speeds surmounting 25 Gbit/s with 10 dB extinction ratio are

Use of modeling to assess the scalability of Ethernet networks for the ATLAS second level trigger

CERN Document Server

Korcyl, K; Dobinson, Robert W; Saka, F

1999-01-01

The second level trigger of LHC's ATLAS experiment has to perform real-time analyses on detector data at 10 GBytes/s. A switching network is required to connect more than thousand read-out buffers to about thousand processors that execute the trigger algorithm. We are investigating the use of Ethernet technology to build this large switching network. Ethernet is attractive because of the huge installed base, competitive prices, and recent introduction of the high-performance Gigabit version. Due to the network's size it has to be constructed as a layered structure of smaller units. To assess the scalability of such a structure we evaluated a single switch unit. (0 refs).

UW VLSI chip tester

Science.gov (United States)

McKenzie, Neil

1989-12-01

We present a design for a low-cost, functional VLSI chip tester. It is based on the Apple MacIntosh II personal computer. It tests chips that have up to 128 pins. All pin drivers of the tester are bidirectional; each pin is programmed independently as an input or an output. The tester can test both static and dynamic chips. Rudimentary speed testing is provided. Chips are tested by executing C programs written by the user. A software library is provided for program development. Tests run under both the Mac Operating System and A/UX. The design is implemented using Xilinx Logic Cell Arrays. Price/performance tradeoffs are discussed.

A test method for analysing disturbed ethernet data streams

Science.gov (United States)

Kreitlow, M.; Sabath, F.; Garbe, H.

2015-11-01

Ethernet connections, which are widely used in many computer networks, can suffer from electromagnetic interference. Typically, a degradation of the data transmission rate can be perceived as electromagnetic disturbances lead to corruption of data frames on the network media. In this paper a software-based measuring method is presented, which allows a direct assessment of the effects on the link layer. The results can directly be linked to the physical interaction without the influence of software related effects on higher protocol layers. This gives a simple tool for a quantitative analysis of the disturbance of an Ethernet connection based on time domain data. An example is shown, how the data can be used for further investigation of mechanisms and detection of intentional electromagnetic attacks.

High-speed highly temperature stable 980 nm VCSELs operating at 25 Gb/s at up to 85 °C for short reach optical interconnects

Science.gov (United States)

Mutig, Alex; Lott, James A.; Blokhin, Sergey A.; Moser, Philip; Wolf, Philip; Hofmann, Werner; Nadtochiy, Alexey M.; Bimberg, Dieter

2011-03-01

The progressive penetration of optical communication links into traditional copper interconnect markets greatly expands the applications of vertical cavity surface emitting lasers (VCSELs) for the next-generation of board-to-board, moduleto- module, chip-to-chip, and on-chip optical interconnects. Stability of the VCSEL parameters at high temperatures is indispensable for such applications, since these lasers typically reside directly on or near integrated circuit chips. Here we present 980 nm oxide-confined VCSELs operating error-free at bit rates up to 25 Gbit/s at temperatures as high as 85 °C without adjustment of the drive current and peak-to-peak modulation voltage. The driver design is therefore simplified and the power consumption of the driver electronics is lowered, reducing the production and operational costs. Small and large signal modulation experiments at various temperatures from 20 up to 85 °C for lasers with different oxide aperture diameters are presented in order to analyze the physical processes controlling the performance of the VCSELs. Temperature insensitive maximum -3 dB bandwidths of around 13-15 GHz for VCSELs with aperture diameters of 10 μm and corresponding parasitic cut-off frequencies exceeding 22 GHz are observed. Presented results demonstrate the suitability of our VCSELs for practical high speed and high temperature stable short-reach optical links.

Source-synchronous networks-on-chip circuit and architectural interconnect modeling

CERN Document Server

Mandal, Ayan; Mahapatra, Rabi

2014-01-01

This book describes novel methods for network-on-chip (NoC) design, using source-synchronous high-speed resonant clocks.  The authors discuss NoCs from the bottom up, providing circuit level details, before providing architectural simulations. As a result, readers will get a complete picture of how a NoC can be designed and optimized.  Using the methods described in this book, readers are enabled to design NoCs that are 5X better than existing approaches in terms of latency and throughput and can also sustain a significantly greater amount of traffic.   • Describes novel methods for high-speed network-on-chip (NoC) design; • Enables readers to understand NoC design from both circuit and architectural levels; • Provides circuit-level details of the NoC (including clocking, router design), along with a high-speed, resonant clocking style which is used in the NoC; • Includes architectural simulations of the NoC, demonstrating significantly superior performance over the state-of-the-art.

The integration of multiple OS-9 stations with a VAX/VMS host via Ethernet

International Nuclear Information System (INIS)

Charity, T.

1989-01-01

In this paper a method for providing embedded microprocessors with virtual disk storage capacity and remote terminal access from a VAX/VMS host via Ethernet is described. The underlying Ethernet driver permits different network protocols to be co-resident in the microprocessors. The system described is in use in many experiments at CERN and elsewhere, and provides a cheap and effective method for sharing data and programs between microprocessors and VAX/VMS systems. Existing approaches to these problems required sole use of a dedicated intelligent network interface, and were biased towards VMEbus systems. One of the goals of the design was to provide a highly transparent and easy-to-use development environment such that users would appear to be working on dedicated microprocessor workstations, unaware of the underlying network connections

Performance Comparison of 112-Gb/s DMT, Nyquist PAM4, and Partial-Response PAM4 for Future 5G Ethernet-Based Fronthaul Architecture

Science.gov (United States)

Eiselt, Nicklas; Muench, Daniel; Dochhan, Annika; Griesser, Helmut; Eiselt, Michael; Olmos, Juan Jose Vegas; Monroy, Idelfonso Tafur; Elbers, Joerg-Peter

2018-05-01

For a future 5G Ethernet-based fronthaul architecture, 100G trunk lines of a transmission distance up to 10 km standard single mode fiber (SSMF) in combination with cheap grey optics to daisy chain cell site network interfaces are a promising cost- and power-efficient solution. For such a scenario, different intensity modulation and direct detect (IMDD) Formats at a data rate of 112 Gb/s, namely Nyquist four-level pulse amplitude modulation (PAM4), discrete multi-tone Transmission (DMT) and partial-response (PR) PAM4 are experimentally investigated, using a low-cost electro-absorption modulated laser (EML), a 25G driver and current state-of-the-art high Speed 84 GS/s CMOS digital-to-analog converter (DAC) and analog-to-digital converter (ADC) test chips. Each modulation Format is optimized independently for the desired scenario and their digital signal processing (DSP) requirements are investigated. The performance of Nyquist PAM4 and PR PAM4 depend very much on the efficiency of pre- and post-equalization. We show the necessity for at least 11 FFE-taps for pre-emphasis and up to 41 FFE coefficients at the receiver side. In addition, PR PAM4 requires an MLSE with four states to decode the signal back to a PAM4 signal. On the contrary, bit- and power-loading (BL, PL) is crucial for DMT and an FFT length of at least 512 is necessary. With optimized parameters, all Modulation formats result in a very similar performances, demonstrating a transmission distance of up to 10 km over SSMF with bit error rates (BERs) below a FEC threshold of 4.4E-3, allowing error free transmission.

Investigation of High-Speed Cryogenic Machining Based on Finite Element Approach

Directory of Open Access Journals (Sweden)

Pooyan Vahidi Pashaki

Full Text Available Abstract The simulation of cryogenic machining process because of using a three-dimensional model and high process duration time in the finite element method, have been studied rarely. In this study, to overcome this limitation, a 2.5D finite element model using the commercial finite element software ABAQUS has been developed for the cryogenic machining process and by considering more realistic assumptions, the chip formation procedure investigated. In the proposed method, the liquid nitrogen has been used as a coolant. At the modeling of friction during the interaction of tools - chip, the Coulomb law has been used. In order to simulate the behavior of plasticity and failure criterion, Johnson-Cook model was used, and unlike previous investigations, thermal and mechanical properties of materials as a function of temperature were applied to the software. After examining accuracy of the model with present experimental data, the effect of parameters such as rake angle and the cutting speed as well as dry machining of aluminum alloy by the use of coupled dynamic temperature solution has been studied. Results indicated that at the cutting velocity of 10 m/s, cryogenic cooling has caused into decreasing 60 percent of tools temperature in comparison with the dry cooling. Furthermore, a chip which has been made by cryogenic machining were connected and without fracture in contrast to dry machining.

A low power high speed radiation hard serializer for High Energy Physics experiments

CERN Document Server

AUTHOR|(CDS)2080243; Marchioro, Alessandro; Ottavi, Marco

This Ph.D. thesis focuses on the development and the characterization of novel solutions for electronic systems for high-speed data transmission in extremely high radio-active environment (e.g. high energy physics application). The text proposes two alternative full-custom solutions for a fundamental enabling block for a lowpower serial data transmission system, the serializer. This block will find place in a future transceiver conceived for the future upgraded phase of the Large Hadron Collider, or LHC, at CERN. The first solution proposed, called “triple module redundancy”, is based on hardware redundancy, a well-known solution, to obtain protection against the temporary malfunctioning induced by radiation. In the second case a new architecture, called “code protected”, is proposed. This architecture takes advantage of the error correction code present in the data word to obtain radiation robustness on data and some parts of the control logic and to further reduce the power consumption. A test chip ...

Fully Automated On-Chip Imaging Flow Cytometry System with Disposable Contamination-Free Plastic Re-Cultivation Chip

Directory of Open Access Journals (Sweden)

Tomoyuki Kaneko

2011-06-01

Full Text Available We have developed a novel imaging cytometry system using a poly(methyl methacrylate (PMMA based microfluidic chip. The system was contamination-free, because sample suspensions contacted only with a flammable PMMA chip and no other component of the system. The transparency and low-fluorescence of PMMA was suitable for microscopic imaging of cells flowing through microchannels on the chip. Sample particles flowing through microchannels on the chip were discriminated by an image-recognition unit with a high-speed camera in real time at the rate of 200 event/s, e.g., microparticles 2.5 μm and 3.0 μm in diameter were differentiated with an error rate of less than 2%. Desired cells were separated automatically from other cells by electrophoretic or dielectrophoretic force one by one with a separation efficiency of 90%. Cells in suspension with fluorescent dye were separated using the same kind of microfluidic chip. Sample of 5 μL with 1 × 106 particle/mL was processed within 40 min. Separated cells could be cultured on the microfluidic chip without contamination. The whole operation of sample handling was automated using 3D micropipetting system. These results showed that the novel imaging flow cytometry system is practically applicable for biological research and clinical diagnostics.

Systems and technologies for high-speed inter-office/datacenter interface

Science.gov (United States)

Sone, Y.; Nishizawa, H.; Yamamoto, S.; Fukutoku, M.; Yoshimatsu, T.

2017-01-01

Emerging requirements for inter-office/inter-datacenter short reach links for data center interconnects (DCI) and metro transport networks have led to various inter-office and inter-datacenter optical interface technologies. These technologies are bringing significant changes to systems and network architectures. In this paper, we present a system and ZR optical interface technologies for DCI and metro transport networks, then introduce the latest challenges facing the system framework. There are two trends in reach extension; one is to use Ethernet and the other is to use digital coherent technologies. The first approach achieves reach extension while using as many existing Ethernet components as possible. It offers low costs as reuses the cost-effective components created for the large Ethernet market. The second approach adopts low-cost and low power coherent DSPs that implement the minimal set long haul transmission functions. This paper introduces an architecture that integrates both trends. The architecture satisfies both datacom and telecom needs with a common control and management interface and automated configuration.

The use of Ethernet in the DataFlow of the ATLAS Trigger & DAQ

CERN Document Server

Stancu, Stefan; Dobinson, Bob; Korcyl, Krzysztof; Knezo, Emil; CHEP 2003 Computing in High Energy Physics

2003-01-01

The article analyzes a proposed network topology for the ATLAS DAQ DataFlow, and identifies the Ethernet features required for a proper operation of the network: MAC address table size, switch performance in terms of throughput and latency, the use of Flow Control, Virtual LANs and Quality of Service. We investigate these features on some Ethernet switches, and conclude on their usefulness for the ATLAS DataFlow network

Fronthaul evolution: From CPRI to Ethernet

Science.gov (United States)

Gomes, Nathan J.; Chanclou, Philippe; Turnbull, Peter; Magee, Anthony; Jungnickel, Volker

2015-12-01

It is proposed that using Ethernet in the fronthaul, between base station baseband unit (BBU) pools and remote radio heads (RRHs), can bring a number of advantages, from use of lower-cost equipment, shared use of infrastructure with fixed access networks, to obtaining statistical multiplexing and optimised performance through probe-based monitoring and software-defined networking. However, a number of challenges exist: ultra-high-bit-rate requirements from the transport of increased bandwidth radio streams for multiple antennas in future mobile networks, and low latency and jitter to meet delay requirements and the demands of joint processing. A new fronthaul functional division is proposed which can alleviate the most demanding bit-rate requirements by transport of baseband signals instead of sampled radio waveforms, and enable statistical multiplexing gains. Delay and synchronisation issues remain to be solved.

Analysis of Microstructure and Chip Formation When Machining Ti-6Al-4V

Directory of Open Access Journals (Sweden)

Islam Shyha

2018-03-01

Full Text Available Microstructure and chip formation were evaluated during the step shoulder down-milling of Ti-6Al-4V using a water-miscible vegetable oil-based cutting fluid. Experiments were conducted using the Cut-list fluid supply system previous developed by the authors and a conventional cutting fluid supply system. A thin plastically deformed layer below the machined surface was observed during the metallurgical investigation of the surfaces produced using both systems. Despite noticeable reductions in cutting fluid consumption achieved by Cut-list, no significant disparity was found in microstructural damage. The microstructure of the machined surfaces was strongly affected by cutting speed and fluid flow rate with a discontinuous serrated chip being the principal type. However, increases in cutting fluid flow rate associated with increased cutting speed significantly changed chip morphology where average distance between chip segments increased with cutting speed. Cut-list produced smaller saw-tooth height and larger segmented width, while the transition from aperiodic to periodic serrated chip formation was governed by cutting speed and feed rate. Chip segmentation frequency and shear angle were also sensitive to cutting speed.

Design optimization of high speed gamma-ray tomography

International Nuclear Information System (INIS)

Maad, Rachid

2009-01-01

This thesis concerns research and development of efficient gamma-ray systems for high speed tomographic imaging of hydrocarbon flow dynamics with a particular focus on gas liquid imaging. The Bergen HSGT (High Speed Gamma-ray Tomograph) based on instant imaging with a fixed source-detector geometry setup, has been thoroughly characterized with a variety of image reconstruction algorithms and flow conditions. Experiments in flow loops have been carried out for reliable characterization and error analysis, static flow phantoms have been applied for the majority of experiments to provide accurate imaging references. A semi-empirical model has been developed for estimation of the contribution of scattered radiation to each HSGT detector and further for correction of this contribution prior to data reconstruction. The Bergen FGGT (Flexible Geometry Gamma-ray Tomograph) has been further developed, particularly on the software side. The system emulates any fan beam tomography. Based on user input of geometry and other conditions, the new software perform scanning, data acquisition and storage, and also weight matrix calculation and image reconstruction with the desired method. The FGGT has been used for experiments supporting those carried out with the HSGT, and in addition for research on other fan beam geometries suitable for hydrocarbon flow imaging applications. An instant no-scanning tomograph like the HSGT has no flexibility with respect to change of geometry, which usually is necessary when applying the tomograph for a new application. A computer controlled FGGT has been designed and built at the UoB. The software developed for the FGGT controls the scanning procedure, the data acquisition, calculates the weight matrix necessary for the image reconstruction, reconstructs the image using standard reconstruction algorithms, and calculates the error of the reconstructed image. The performance of the geometry has been investigated using a 100 mCi 241 Am disk source, a

Upgrade of Spring-8 Beamline Network with Vlan Technology Over Gigabit Ethernet

OpenAIRE

Ishii, M.; Fukui, T.; Furukawa, Y.; Nakatani, T.; Ohata, T.; Tanaka, R.

2001-01-01

The beamline network system at SPring-8 consists of three LANs; a BL-LAN for beamline component control, a BL-USER-LAN for beamline experimental users and an OA-LAN for the information services. These LANs are interconnected by a firewall system. Since the network traffic and the number of beamlines have increased, we upgraded the backbone of BL-USER-LAN from Fast Ethernet to Gigabit Ethernet. And then, to establish the independency of a beamline and to raise flexibility of every beamline, we...

Using the ACR/NEMA standard with TCP/IP and Ethernet

Science.gov (United States)

Chimiak, William J.; Williams, Rodney C.

1991-07-01

There is a need for a consolidated picture archival and communications system (PACS) in hospitals. At the Bowman Gray School of Medicine of Wake Forest University (BGSM), the authors are enhancing the ACR/NEMA Version 2 protocol using UNIX sockets and TCP/IP to greatly improve connectivity. Initially, nuclear medicine studies using gamma cameras are to be sent to PACS. The ACR/NEMA Version 2 protocol provides the functionality of the upper three layers of the open system interconnection (OSI) model in this implementation. The images, imaging equipment information, and patient information are then sent in ACR/NEMA format to a software socket. From there it is handed to the TCP/IP protocol, which provides the transport and network service. TCP/IP, in turn, uses the services of IEEE 802.3 (Ethernet) to complete the connectivity. The advantage of this implementation is threefold: (1) Only one I/O port is consumed by numerous nuclear medicine cameras, instead of a physical port for each camera. (2) Standard protocols are used which maximize interoperability with ACR/NEMA compliant PACSs. (3) The use of sockets allows a migration path to the transport and networking services of OSIs TP4 and connectionless network service as well as the high-performance protocol being considered by the American National Standards Institute (ANSI) and the International Standards Organization (ISO) -- the Xpress Transfer Protocol (XTP). The use of sockets also gives access to ANSI's Fiber Distributed Data Interface (FDDI) as well as other high-speed network standards.

A CMOS 0.18 μm 600 MHz clock multiplier PLL and a pseudo-LVDS driver for the high speed data transmission for the ALICE Inner Tracking System front-end chip

International Nuclear Information System (INIS)

Lattuca, A.; Mazza, G.; Rinella, G. Aglieri; Cavicchioli, C.; Hillemanns, H.; Hristozkov, S.; Junique, A.; Keil, M.; Kofarago, M.; Kugathasan, T.; Chanlek, N.; Collu, A.; Degerli, Y.; Flouzat, C.; Guilloux, F.; Dorokhov, A.; Gajanana, D.; Gao, C.; Kim, D.; Kwon, Y.

2016-01-01

This work presents the 600 MHz clock multiplier PLL and the pseudo-LVDS driver which are two essential components of the Data Transmission Unit (DTU), a fast serial link for the 1.2 Gb/s data transmission of the ALICE inner detector front-end chip (ALPIDE). The PLL multiplies the 40 MHz input clock in order to obtain the 600 MHz and the 200 MHz clock for a fast serializer which works in Double Data Rate mode. The outputs of the serializer feed the pseudo-LVDS driver inputs which transmits the data from the pixel chip to the patch panel with a limited number of signal lines. The driver drives a 5.3 m-6.5 m long differential transmission line by steering a maximum of 5 mA of current at the target speed. To overcome bandwidth limitations coming from the long cables the pre-emphasis can be applied to the output. Currents for the main and pre-emphasis driver can individually be adjusted using on-chip digital-to-analog converters. The circuits will be integrated in the pixel chip and are designed in the same 0.18 μm CMOS technology and will operate from the same 1.8 V supply. Design and test results of both circuits are presented

A CMOS 0.18 μm 600 MHz clock multiplier PLL and a pseudo-LVDS driver for the high speed data transmission for the ALICE Inner Tracking System front-end chip

Science.gov (United States)

Lattuca, A.; Mazza, G.; Aglieri Rinella, G.; Cavicchioli, C.; Chanlek, N.; Collu, A.; Degerli, Y.; Dorokhov, A.; Flouzat, C.; Gajanana, D.; Gao, C.; Guilloux, F.; Hillemanns, H.; Hristozkov, S.; Junique, A.; Keil, M.; Kim, D.; Kofarago, M.; Kugathasan, T.; Kwon, Y.; Mager, M.; Sielewicz, K. Marek; Marin Tobon, C. Augusto; Marras, D.; Martinengo, P.; Mugnier, H.; Musa, L.; Pham, T. Hung; Puggioni, C.; Reidt, F.; Riedler, P.; Rousset, J.; Siddhanta, S.; Snoeys, W.; Song, M.; Usai, G.; Van Hoorne, J. Willem; Yang, P.

2016-01-01

This work presents the 600 MHz clock multiplier PLL and the pseudo-LVDS driver which are two essential components of the Data Transmission Unit (DTU), a fast serial link for the 1.2 Gb/s data transmission of the ALICE inner detector front-end chip (ALPIDE). The PLL multiplies the 40 MHz input clock in order to obtain the 600 MHz and the 200 MHz clock for a fast serializer which works in Double Data Rate mode. The outputs of the serializer feed the pseudo-LVDS driver inputs which transmits the data from the pixel chip to the patch panel with a limited number of signal lines. The driver drives a 5.3 m-6.5 m long differential transmission line by steering a maximum of 5 mA of current at the target speed. To overcome bandwidth limitations coming from the long cables the pre-emphasis can be applied to the output. Currents for the main and pre-emphasis driver can individually be adjusted using on-chip digital-to-analog converters. The circuits will be integrated in the pixel chip and are designed in the same 0.18 μm CMOS technology and will operate from the same 1.8 V supply. Design and test results of both circuits are presented.

Performance Comparison of 112 Gb/s DMT, Nyquist PAM4 and Partial-Response PAM4 for Future 5G Ethernet-based Fronthaul Architecture

DEFF Research Database (Denmark)

Eiselt, Nicklas; Muench, Daniel; Dochhan, Annika

2018-01-01

(EML), a 25G driver and current state-of-the-art high speed 84 GS/s CMOS digital-to-analog converter (DAC) and analog-to-digital converter (ADC) test chips. Each modulation format is optimized independently for the desired scenario and their digital signal processing (DSP) requirements are investigated...

High-performance, scalable optical network-on-chip architectures

Science.gov (United States)

Tan, Xianfang

The rapid advance of technology enables a large number of processing cores to be integrated into a single chip which is called a Chip Multiprocessor (CMP) or a Multiprocessor System-on-Chip (MPSoC) design. The on-chip interconnection network, which is the communication infrastructure for these processing cores, plays a central role in a many-core system. With the continuously increasing complexity of many-core systems, traditional metallic wired electronic networks-on-chip (NoC) became a bottleneck because of the unbearable latency in data transmission and extremely high energy consumption on chip. Optical networks-on-chip (ONoC) has been proposed as a promising alternative paradigm for electronic NoC with the benefits of optical signaling communication such as extremely high bandwidth, negligible latency, and low power consumption. This dissertation focus on the design of high-performance and scalable ONoC architectures and the contributions are highlighted as follow: 1. A micro-ring resonator (MRR)-based Generic Wavelength-routed Optical Router (GWOR) is proposed. A method for developing any sized GWOR is introduced. GWOR is a scalable non-blocking ONoC architecture with simple structure, low cost and high power efficiency compared to existing ONoC designs. 2. To expand the bandwidth and improve the fault tolerance of the GWOR, a redundant GWOR architecture is designed by cascading different type of GWORs into one network. 3. The redundant GWOR built with MRR-based comb switches is proposed. Comb switches can expand the bandwidth while keep the topology of GWOR unchanged by replacing the general MRRs with comb switches. 4. A butterfly fat tree (BFT)-based hybrid optoelectronic NoC (HONoC) architecture is developed in which GWORs are used for global communication and electronic routers are used for local communication. The proposed HONoC uses less numbers of electronic routers and links than its counterpart of electronic BFT-based NoC. It takes the advantages of

Analysis of the resistive network in a bio-inspired CMOS vision chip

Science.gov (United States)

Kong, Jae-Sung; Sung, Dong-Kyu; Hyun, Hyo-Young; Shin, Jang-Kyoo

2007-12-01

CMOS vision chips for edge detection based on a resistive circuit have recently been developed. These chips help develop neuromorphic systems with a compact size, high speed of operation, and low power dissipation. The output of the vision chip depends dominantly upon the electrical characteristics of the resistive network which consists of a resistive circuit. In this paper, the body effect of the MOSFET for current distribution in a resistive circuit is discussed with a simple model. In order to evaluate the model, two 160×120 CMOS vision chips have been fabricated by using a standard CMOS technology. The experimental results have been nicely matched with our prediction.

Design and implementation of digital television over ethernet PON transmission system

Science.gov (United States)

Lu, Xi; Liu, Deming; Mao, Minjing; Wang, Jinjuan

2005-11-01

There are two primary methods of transmitting signal of digital television to the home in China. The first one is HFC mode, which is widely used. The other is IPTV mode, which is emerging. In this paper, the scheme of digital television over Ethernet PON is proposed. There are several differences from this system to IPTV and Video over LAN: the real-time transmission of equal-bandwidth based on statistical multiplexing, channel switching based on multicast and IP CA system, etc.. And these are also the key techniques used in this system. The architecture of DTV over EPON system, the function of every component, the framing process and the multiplexing of Ethernet frame are described. The implementation procedure of the system is shown. The mechanism of channel switching using multicast technique is designed and realized. We also present the method of using static VLAN and IGMP snooping mechanism to implement statistical multiplexing on Ethernet layer, and put forward the concept of IP Conditional Access System and define it. An experimental system of DTV over EPON is set up and the experimental result is significant.

Local structure of metallic chips examined by X-ray microdiffraction

International Nuclear Information System (INIS)

Saksl, K.; Rokicki, P.; Siemers, C.; Ostroushko, D.; Bednarčík, J.; Rütt, U.

2013-01-01

Highlights: •We present a detailed microstructure and phase analysis of chips produced by cutting. •3D analysis proved mixed nature of shear bands propagation to the material. •We examine phase composition of the chips by focused X-ray beam. •Crystallites in segment and shear band change their orientation up to 10°. -- Abstract: Nickel-base alloys are used in high-temperature applications whenever steels or titanium alloys cannot be applied anymore. This class of alloys is furthermore used in low-temperature applications in the oil or gas industry in case the corrosion resistance of stainless steels in related liquid media is not sufficient and titanium alloys would be too expensive. Nickel-base alloys, however, due to their high strength and toughness can be machined only at low cutting speeds as otherwise poor surface quality and enhanced tool wear is observed. From all aspects influencing the machinability, the chip formation mechanism is the key factor and only a thorough understanding of this mechanism can lead to an optimisation of the cutting process. In the current study, a detailed microstructure and phase analysis of Alloy 625 chips produced in an orthogonal cutting process at conventional cutting speeds is presented. Utilising hard monochromatic X-rays focused down to micrometre size, microstructural differences between distinct structural units of the chips, namely, the segments and shear bands, are investigated. Scanning cross sections of the chips with this small beam allowed us to determine misorientation between the segments and shear bands crystal lattices which as we found are not changing abruptly but continuously, with an absolute difference up to 10°

Local structure of metallic chips examined by X-ray microdiffraction

Energy Technology Data Exchange (ETDEWEB)

Saksl, K., E-mail: ksaksl@imr.saske.sk [Institut of Materials Research, Slovak Academy of Sciences, Watsonova 47, 040 01 Košice (Slovakia); Rokicki, P. [The Faculty of Mechanical Engineering and Aeronautics, Rzeszow University of Technology, Al. Powstancow Warszawy 12, 35-959 Rzeszow (Poland); Siemers, C. [Institut fuer Werkstoffe, Technische Universitaet Braunschweig, Langer Kamp 8, 38106 Braunschweig (Germany); Ostroushko, D. [Faculty of Metallurgy and Materials Engineering, VŠB – Technical University of Ostrava, 17.listopadu 15, 708 33 Ostrava (Czech Republic); Bednarčík, J.; Rütt, U. [HASYLAB at DESY, Notkestr. 85, D-22607 Hamburg (Germany)

2013-12-25

Highlights: •We present a detailed microstructure and phase analysis of chips produced by cutting. •3D analysis proved mixed nature of shear bands propagation to the material. •We examine phase composition of the chips by focused X-ray beam. •Crystallites in segment and shear band change their orientation up to 10°. -- Abstract: Nickel-base alloys are used in high-temperature applications whenever steels or titanium alloys cannot be applied anymore. This class of alloys is furthermore used in low-temperature applications in the oil or gas industry in case the corrosion resistance of stainless steels in related liquid media is not sufficient and titanium alloys would be too expensive. Nickel-base alloys, however, due to their high strength and toughness can be machined only at low cutting speeds as otherwise poor surface quality and enhanced tool wear is observed. From all aspects influencing the machinability, the chip formation mechanism is the key factor and only a thorough understanding of this mechanism can lead to an optimisation of the cutting process. In the current study, a detailed microstructure and phase analysis of Alloy 625 chips produced in an orthogonal cutting process at conventional cutting speeds is presented. Utilising hard monochromatic X-rays focused down to micrometre size, microstructural differences between distinct structural units of the chips, namely, the segments and shear bands, are investigated. Scanning cross sections of the chips with this small beam allowed us to determine misorientation between the segments and shear bands crystal lattices which as we found are not changing abruptly but continuously, with an absolute difference up to 10°.

OFDM and PAM comparison using a high baudrate low resolution IM/DD interface for 400G Ethernet access.

Science.gov (United States)

André, Nuno Sequeira; Louchet, Hadrien; Filsinger, Volker; Hansen, Erik; Richter, André

2016-05-30

We compare OFDM and PAM for 400G Ethernet based on a 3-bit high baudrate IM/DD interface at 1550nm. We demonstrate 27Gb/s and 32Gb/s transmission over 10km SSMF using OFDM and PAM respectively. We show that capacity can be improved through adaptation/equalization to achieve 42Gb/s and 64Gb/s for OFDM and PAM respectively. Experimental results are used to create realistic simulations to extrapolate the performance of both modulation formats under varied conditions. For the considered interface we found that PAM has the best performance, OFDM is impaired by quantization noise. When the resolution limitation is relaxed, OFDM shows better performance.

Synchronous Ethernet- Considerations and Implementation of the Packet Network Management Scheme

Science.gov (United States)

Gundale, A. S.; Aradhye, Ashwini

2010-11-01

Packet technologies were designed to work in asynchronous mode, where the oscillators in the equipment are free running. Although this allows the underlying infrastructure to operate, many applications exist that require frequency synchronization. Also, the ability to distribute synchronization from center to edge of network declines as infrastructure evolves toward a packet-based architecture. Synchronous Ethernet (SyncE) is a key development of the evolution of Ethernet into a carrier grade technology suitable for the WAN environment where frequency synchronization is required. The time of the day distribution in synchronized network at the physical layer enables many useful propositions in packet handling policies and other network management aspects.

Oxide-confined 2D VCSEL arrays for high-density inter/intra-chip interconnects

Science.gov (United States)

King, Roger; Michalzik, Rainer; Jung, Christian; Grabherr, Martin; Eberhard, Franz; Jaeger, Roland; Schnitzer, Peter; Ebeling, Karl J.

1998-04-01

We have designed and fabricated 4 X 8 vertical-cavity surface-emitting laser (VCSEL) arrays intended to be used as transmitters in short-distance parallel optical interconnects. In order to meet the requirements of 2D, high-speed optical links, each of the 32 laser diodes is supplied with two individual top contacts. The metallization scheme allows flip-chip mounting of the array modules junction-side down on silicon complementary metal oxide semiconductor (CMOS) chips. The optical and electrical characteristics across the arrays with device pitch of 250 micrometers are quite homogeneous. Arrays with 3 micrometers , 6 micrometers and 10 micrometers active diameter lasers have been investigated. The small devices show threshold currents of 600 (mu) A, single-mode output powers as high as 3 mW and maximum wavelength deviations of only 3 nm. The driving characteristics of all arrays are fully compatible to advanced 3.3 V CMOS technology. Using these arrays, we have measured small-signal modulation bandwidths exceeding 10 GHz and transmitted pseudo random data at 8 Gbit/s channel over 500 m graded index multimode fiber. This corresponds to a data transmission rate of 256 Gbit/s per array of 1 X 2 mm2 footprint area.

Research on Dynamic Torque Measurement of High Speed Rotating Axis Based on Whole Optical Fiber Technique

Energy Technology Data Exchange (ETDEWEB)

Ma, H P; Jin, Y Q; Ha, Y W; Liu, L H [Department of Automatic Measurement and Control, Harbin Institute of Technology, PO Box 305, Harbin, 150001 (China)

2006-10-15

Non-contact torque measurement system of fiber grating is proposed in this paper. It is used for the dynamic torque measurement of the rotating axis in the spaceflight servo system. Optical fiber is used as sensing probe with high sensitivity, anti-electromagnetic interference, resistance to high temperature and corrosion. It is suitable to apply in a bad environment. Signals are processed by digital circuit and Single Chip Microcomputer. This project can realize super speed dynamic measurement and it is the first time to apply the project in the spaceflight system.

Research on Dynamic Torque Measurement of High Speed Rotating Axis Based on Whole Optical Fiber Technique

Science.gov (United States)

Ma, H. P.; Jin, Y. Q.; Ha, Y. W.; Liu, L. H.

2006-10-01

Non-contact torque measurement system of fiber grating is proposed in this paper. It is used for the dynamic torque measurement of the rotating axis in the spaceflight servo system. Optical fiber is used as sensing probe with high sensitivity, anti-electromagnetic interference, resistance to high temperature and corrosion. It is suitable to apply in a bad environment. Signals are processed by digital circuit and Single Chip Microcomputer. This project can realize super speed dynamic measurement and it is the first time to apply the project in the spaceflight system.

Research on Dynamic Torque Measurement of High Speed Rotating Axis Based on Whole Optical Fiber Technique

International Nuclear Information System (INIS)

Ma, H P; Jin, Y Q; Ha, Y W; Liu, L H

2006-01-01

Non-contact torque measurement system of fiber grating is proposed in this paper. It is used for the dynamic torque measurement of the rotating axis in the spaceflight servo system. Optical fiber is used as sensing probe with high sensitivity, anti-electromagnetic interference, resistance to high temperature and corrosion. It is suitable to apply in a bad environment. Signals are processed by digital circuit and Single Chip Microcomputer. This project can realize super speed dynamic measurement and it is the first time to apply the project in the spaceflight system

Contribución para QoS en Redes Metropolitanas Ethernet

Directory of Open Access Journals (Sweden)

Omar Álvarez

2007-11-01

Full Text Available Los sistemas de control de acceso (ACS permiten apoyar las soluciones actuales de Calidad de Servicio. Éstos consideran entre sus variables el retardo, variación de retardo, pérdida de paquetes o una combinación para asegurar los requerimientos de calidad de servicio para sesiones de voz y video. Proponemos un ACS basado en la pérdida de paquetes de prueba extremo a extremo para la decisión de aceptar nuevas sesiones. La red de transporte será la familia Ethernet, la cual ha incursionado de manera importante en los ámbitos metropolitanos (802.3ae. El presente trabajo muestra la interoperatividad y ventajas de ME-ACS con MPLS./ The access control systems (ACS are useful to improve the Quality of Service solutions. These systems are generally based on delay, jitter or packet loss, employing more of these criteria to maintain the required quality of service requiring for voice or video sessions. We propose an ACS that employs packet loss between probes that send an end-to-end test stream before accepting additional sessions. We used Ethernet as our transport network because the 803.3ae is widely used in metropolitan area networks. This paper presents how the ACS will interoperate with MPLS and describe the improvements related to its use in a metropolitan Ethernet network.

Application of high voltage electric field (HVEF) drying technology in potato chips

International Nuclear Information System (INIS)

Bai, Yaxiang; Shi, Hua; Yang, Yaxin

2013-01-01

In order to improve the drying efficiency and qualities of vegetable by high voltage electric field (HVEF), potato chips as a representative of vegetable was dried using a high voltage electric drying systems at 20°C. The shrinkage rate, water absorption and rehydration ratio of dried potato chips were measured. The results indicated that the drying rate of potato chips was significantly improved in the high voltage electric drying systems. The shrinkage rate of potato chips dried by high voltage electric field was 1.1% lower than that by oven drying method. And the rehydration rate of high voltage electric field was 24.6% higher than that by oven drying method. High voltage electric field drying is very advantageous and can be used as a substitute for traditional drying method.

High speed serial communications for control systems

International Nuclear Information System (INIS)

Mathieson, D.; Kalbfleisch, C.; Hunt, S.; Low, K.

1993-01-01

The Superconducting Super Collider Laboratory is a complex of accelerators being built in Ellis County, Texas. The SSCL control system consists of front-end processors and their associated control points remotely distributed from the Central and Regional control rooms. Control messages passing between these locations require timely (deterministic) distribution. A prototype network consisting of point-to-point links utilizing commercial T1 (1.544 Mb/s) communication boards has been implemented. These dedicated communication links will replace networking services traditionally provided for by shared medium networks like Ethernet(IEEE 802.3) and FDDI(IEEE 802.5). A seamless migration will be achieved by using packet encapsulation based on PPP(Point-to-Point Protocol, RFC 1171). All other networking functions including routing and reliable delivery are still being handled by the usual internet services. A distributed control system that currently uses Ethernet for communication is being re-implemented using these point-to-point links. The authors report on throughput measurements, timing constraints and ease of transition of a point-to-point network

Timing Analysis of Rate Constrained Traffic for the TTEthernet Communication Protocol

DEFF Research Database (Denmark)

Tamas-Selicean, Domitian; Pop, Paul; Steiner, Wilfried

2015-01-01

Ethernet is a low-cost communication solution offering high transmission speeds. Although its applications extend beyond computer networking, Ethernet is not suitable for real-time and safety-critical systems. To alleviate this, several real-time Ethernet-based communication protocols have been...

Fiber optic Ethernet transceiver for Joint STARS block I GSM

Science.gov (United States)

Gatens, Dennis R.; Usberghi, Michael J.

The authors discuss the use of FiberCom's DPT dual redundant counter-rotating ring Ethernet transceiver, and its use as an integral part of the Joint STARS (Surveillance Target Attack Radar System) surface-to-air battlefield information station called the ground station module (GSM). The Ethernet transceiver uses a dual counter-rotating fiber ring architecture. The operation of the unit enables the network to have fault-tolerant capability with no single point of failure. This results from the unit's ability to reconfigure around a network failure, creating a new working segment from the remaining portion. The medium attachment unit interface conforms to ANSI/IEEE Std. 802.3-1985, the IEEE Standard for Local Area Networks-Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer Specifications.

Ethernet access network based on free-space optic deployment technology

Science.gov (United States)

Gebhart, Michael; Leitgeb, Erich; Birnbacher, Ulla; Schrotter, Peter

2004-06-01

The satisfaction of all communication needs from single households and business companies over a single access infrastructure is probably the most challenging topic in communications technology today. But even though the so-called "Last Mile Access Bottleneck" is well known since more than ten years and many distribution technologies have been tried out, the optimal solution has not yet been found and paying commercial access networks offering all service classes are still rare today. Conventional services like telephone, radio and TV, as well as new and emerging services like email, web browsing, online-gaming, video conferences, business data transfer or external data storage can all be transmitted over the well known and cost effective Ethernet networking protocol standard. Key requirements for the deployment technology driven by the different services are high data rates to the single customer, security, moderate deployment costs and good scalability to number and density of users, quick and flexible deployment without legal impediments and high availability, referring to the properties of optical and wireless communication. We demonstrate all elements of an Ethernet Access Network based on Free Space Optic distribution technology. Main physical parts are Central Office, Distribution Network and Customer Equipment. Transmission of different services, as well as configuration, service upgrades and remote control of the network are handled by networking features over one FSO connection. All parts of the network are proven, the latest commercially available technology. The set up is flexible and can be adapted to any more specific need if required.

Development of a Metal Cutting Tool Fase in Order to Create the Conditions of Ringed Chips Wrapping

OpenAIRE

Korchuganova, Mariya Anatolievna; Syrbakov, Andrey Pavlovich; Chernysheva, Tatiana Yurievna; Ivanov, G.; Korchuganov, Maksim Anatolievich

2016-01-01

When processing ductile metals with high cutting speed, there is a need to take additional measures for a comfortable and safe formation and removal of chips. In the conditions of large-scale manufacture, it is recommended to produce flow chips in the form of short fragments, while in the conditions of small-lot and single-piece manufacture, it is reasonable to wrap the chips spirally with a rather small turn radius. Such way of chips formation reduces the time of its removal from the working...

Energy Harvesting Chip and the Chip Based Power Supply Development for a Wireless Sensor Network.

Science.gov (United States)

Lee, Dasheng

2008-12-02

In this study, an energy harvesting chip was developed to scavenge energy from artificial light to charge a wireless sensor node. The chip core is a miniature transformer with a nano-ferrofluid magnetic core. The chip embedded transformer can convert harvested energy from its solar cell to variable voltage output for driving multiple loads. This chip system yields a simple, small, and more importantly, a battery-less power supply solution. The sensor node is equipped with multiple sensors that can be enabled by the energy harvesting power supply to collect information about the human body comfort degree. Compared with lab instruments, the nodes with temperature, humidity and photosensors driven by harvested energy had variation coefficient measurement precision of less than 6% deviation under low environmental light of 240 lux. The thermal comfort was affected by the air speed. A flow sensor equipped on the sensor node was used to detect airflow speed. Due to its high power consumption, this sensor node provided 15% less accuracy than the instruments, but it still can meet the requirement of analysis for predicted mean votes (PMV) measurement. The energy harvesting wireless sensor network (WSN) was deployed in a 24-hour convenience store to detect thermal comfort degree from the air conditioning control. During one year operation, the sensor network powered by the energy harvesting chip retained normal functions to collect the PMV index of the store. According to the one month statistics of communication status, the packet loss rate (PLR) is 2.3%, which is as good as the presented results of those WSNs powered by battery. Referring to the electric power records, almost 54% energy can be saved by the feedback control of an energy harvesting sensor network. These results illustrate that, scavenging energy not only creates a reliable power source for electronic devices, such as wireless sensor nodes, but can also be an energy source by building an energy efficient

Energy Harvesting Chip and the Chip Based Power Supply Development for a Wireless Sensor Network

Science.gov (United States)

Lee, Dasheng

2008-01-01

In this study, an energy harvesting chip was developed to scavenge energy from artificial light to charge a wireless sensor node. The chip core is a miniature transformer with a nano-ferrofluid magnetic core. The chip embedded transformer can convert harvested energy from its solar cell to variable voltage output for driving multiple loads. This chip system yields a simple, small, and more importantly, a battery-less power supply solution. The sensor node is equipped with multiple sensors that can be enabled by the energy harvesting power supply to collect information about the human body comfort degree. Compared with lab instruments, the nodes with temperature, humidity and photosensors driven by harvested energy had variation coefficient measurement precision of less than 6% deviation under low environmental light of 240 lux. The thermal comfort was affected by the air speed. A flow sensor equipped on the sensor node was used to detect airflow speed. Due to its high power consumption, this sensor node provided 15% less accuracy than the instruments, but it still can meet the requirement of analysis for predicted mean votes (PMV) measurement. The energy harvesting wireless sensor network (WSN) was deployed in a 24-hour convenience store to detect thermal comfort degree from the air conditioning control. During one year operation, the sensor network powered by the energy harvesting chip retained normal functions to collect the PMV index of the store. According to the one month statistics of communication status, the packet loss rate (PLR) is 2.3%, which is as good as the presented results of those WSNs powered by battery. Referring to the electric power records, almost 54% energy can be saved by the feedback control of an energy harvesting sensor network. These results illustrate that, scavenging energy not only creates a reliable power source for electronic devices, such as wireless sensor nodes, but can also be an energy source by building an energy efficient

Energy Harvesting Chip and the Chip Based Power Supply Development for a Wireless Sensor Network

Directory of Open Access Journals (Sweden)

Dasheng Lee

2008-12-01

Full Text Available In this study, an energy harvesting chip was developed to scavenge energy from artificial light to charge a wireless sensor node. The chip core is a miniature transformer with a nano-ferrofluid magnetic core. The chip embedded transformer can convert harvested energy from its solar cell to variable voltage output for driving multiple loads. This chip system yields a simple, small, and more importantly, a battery-less power supply solution. The sensor node is equipped with multiple sensors that can be enabled by the energy harvesting power supply to collect information about the human body comfort degree. Compared with lab instruments, the nodes with temperature, humidity and photosensors driven by harvested energy had variation coefficient measurement precision of less than 6% deviation under low environmental light of 240 lux. The thermal comfort was affected by the air speed. A flow sensor equipped on the sensor node was used to detect airflow speed. Due to its high power consumption, this sensor node provided 15% less accuracy than the instruments, but it still can meet the requirement of analysis for predicted mean votes (PMV measurement. The energy harvesting wireless sensor network (WSN was deployed in a 24-hour convenience store to detect thermal comfort degree from the air conditioning control. During one year operation, the sensor network powered by the energy harvesting chip retained normal functions to collect the PMV index of the store. According to the one month statistics of communication status, the packet loss rate (PLR is 2.3%, which is as good as the presented results of those WSNs powered by battery. Referring to the electric power records, almost 54% energy can be saved by the feedback control of an energy harvesting sensor network. These results illustrate that, scavenging energy not only creates a reliable power source for electronic devices, such as wireless sensor nodes, but can also be an energy source by building an

Development of a high-speed single-photon pixellated detector for visible wavelengths

CERN Document Server

Mac Raighne, Aaron; Mathot, Serge; McPhate, Jason; Vallerga, John; Jarron, Pierre; Brownlee, Colin; O’Shea, Val

2009-01-01

We present the development of a high-speed, single-photon counting, Hybrid Photo Detector (HPD). The HPD consists of a vacuum tube, containing the detector assembly, sealed with a transparent optical input window. Photons incident on the photocathode eject a photoelectron into a large electric field, which accelerates the incident electron onto a silicon detector. The silicon detector is bump bonded to a Medipix readout chip. This set-up allows for the detection and readout of low incident photon intensities at rates that are otherwise unattainable with current camera technology. Reported is the fabrication of the camera that brings together a range of sophisticated design and fabrication techniques and the expected theoretical imaging performance. Applications to cellular and molecular microscopy are also described in which single-photon-counting abilities at high frame rates are crucial

Safety management of Ethernet broadband access based on VLAN aggregation

Science.gov (United States)

Wang, Li

2004-04-01

With broadband access network development, the Ethernet technology is more and more applied access network now. It is different from the private network -LAN. The differences lie in four points: customer management, safety management, service management and count-fee management. This paper mainly discusses the safety management related questions. Safety management means that the access network must secure the customer data safety, isolate the broad message which brings the customer private information, such as ARP, DHCP, and protect key equipment from attack. Virtue LAN (VLAN) technology can restrict network broadcast flow. We can config each customer port with a VLAN, so each customer is isolated with others. The IP address bound with VLAN ID can be routed rightly. But this technology brings another question: IP address shortage. VLAN aggregation technology can solve this problem well. Such a mechanism provides several advantages over traditional IPv4 addressing architectures employed in large switched LANs today. With VLAN aggregation technology, we introduce the notion of sub-VLANs and super-VLANs, a much more optimal approach to IP addressing can be realized. This paper will expatiate the VLAN aggregation model and its implementation in Ethernet access network. It is obvious that the customers in different sub-VLANs can not communication to each other because the ARP packet is isolated. Proxy ARP can enable the communication among them. This paper will also expatiate the proxy ARP model and its implementation in Ethernet access network.

Parallel Void Thread in Long-Reach Ethernet Passive Optical Networks

KAUST Repository

Elrasad, Amr; Shihada, Basem

2015-01-01

This work investigates void filling (idle periods) in long-reach Ethernet passive optical networks. We focus on reducing grant delays and hence reducing the average packet delay. We introduce a novel approach called parallel void thread (PVT), which

A new method for grain refinement in magnesium alloy: High speed extrusion machining

Energy Technology Data Exchange (ETDEWEB)

Liu, Yao, E-mail: liuyao@ustb.edu.cn [School of Mathematics and Physics, University of Science and Technology Beijing, Beijing 100083 (China); Cai, Songlin [China Electric Power Research Institute, State Grid Corporation of China, Beijing 100192 (China); Dai, Lanhong [State Key Laboratory of Nonlinear Mechanics, Institute of Mechanics, Chinese Academy of Science, Beijing 100190 (China)

2016-01-10

Magnesium alloys have received broad attentions in industry due to their competitive strength to density ratio, but the poor ductility and strength limit their wide range of applications as engineering materials. A novel severe plastic deformation (SPD) technique of high speed extrusion machining (HSEM) was used here. This method could improve the aforementioned disadvantages of magnesium alloys by one single processing step. In this work, systematic HSEM experiments with different chip thickness ratios were conducted for magnesium alloy AZ31B. The microstructure of the chips reveals that HSEM is an effective SPD method for attaining magnesium alloys with different grain sizes and textures. The magnesium alloy with bimodal grain size distribution has increased mechanical properties than initial sample. The electron backscatter diffraction (EBSD) analysis shows that the dynamic recrystallization (DRX) affects the grain refinement and resulting hardness in AZ31B. Based on the experimental observations, a new theoretical model is put forward to describe the effect of DRX on materials during HSEM. Compared with the experimental measurements, the theoretical model is effective to predict the mechanical property of materials after HSEM.

Wear evaluation of flank in burins of high speed steel modified with titanium ions

Science.gov (United States)

E Caballero, J.; V-Niño, E. D.

2017-12-01

This report shows the results obtained researching the flank wearing resistance performed by the high-speed steel (HSS) burins without any surface treatment (reference substrate) and others with surface treatment based on Titanium ions. The flank wearing was carried out by means of an industrial process by chip removal with repetitive tests of dry finished turning of AISI/SAE 1045 steel bars. The useful service life of the burins was evaluated according to ISO 3685:1993, and it was found that the burins treated with Titanium ions showed an increase in the flank wearing resistance with respect to the ones used as reference.

A compact PE memory for vision chips

Science.gov (United States)

Cong, Shi; Zhe, Chen; Jie, Yang; Nanjian, Wu; Zhihua, Wang

2014-09-01

This paper presents a novel compact memory in the processing element (PE) for single-instruction multiple-data (SIMD) vision chips. The PE memory is constructed with 8 × 8 register cells, where one latch in the slave stage is shared by eight latches in the master stage. The memory supports simultaneous read and write on the same address in one clock cycle. Its compact area of 14.33 μm2/bit promises a higher integration level of the processor. A prototype chip with a 64 × 64 PE array is fabricated in a UMC 0.18 μm CMOS technology. Five types of the PE memory cell structure are designed and compared. The testing results demonstrate that the proposed PE memory architecture well satisfies the requirement of the vision chip in high-speed real-time vision applications, such as 1000 fps edge extraction.

A compact PE memory for vision chips

International Nuclear Information System (INIS)

Shi Cong; Chen Zhe; Yang Jie; Wu Nanjian; Wang Zhihua

2014-01-01

This paper presents a novel compact memory in the processing element (PE) for single-instruction multiple-data (SIMD) vision chips. The PE memory is constructed with 8 × 8 register cells, where one latch in the slave stage is shared by eight latches in the master stage. The memory supports simultaneous read and write on the same address in one clock cycle. Its compact area of 14.33 μm 2 /bit promises a higher integration level of the processor. A prototype chip with a 64 × 64 PE array is fabricated in a UMC 0.18 μm CMOS technology. Five types of the PE memory cell structure are designed and compared. The testing results demonstrate that the proposed PE memory architecture well satisfies the requirement of the vision chip in high-speed real-time vision applications, such as 1000 fps edge extraction. (semiconductor integrated circuits)

Co-design for an SoC embedded network controller

Institute of Scientific and Technical Information of China (English)

无

2006-01-01

With the development of Ethernet systems and the growing capacity of modern silicon technology, embedded communication networks are playing an increasingly important role in embedded and safety critical systems. Hardware/software co-design is a methodology for solving design problems in processor based embedded systems. In this work, we implemented a new 1-cycle pipeline microprocessor and a fast Ethernet transceiver and established a low cost, high performance embedded network controller, and designed a TCP/IP stack to access the Internet. We discussed the hardware/software architecture in the forepart, and then the whole system-on-a-chip on Altera Stratix EP1S25F780C6 device. Using the FPGA environment and SmartBit tester, we tested the system's throughput. Our simulation results showed that the maximum throughput of Ethernet packets is up to 7 Mbps, that of UDP packets is up to 5.8 Mbps, and that of TCP packets is up to 3.4 Mbps, which showed that this embedded system can easily transmit basic voice and video signals through Ethernet, and that using only one chip can realize that many electronic devices access to the Internet directly and get high performance.

Chip formation in turning S45C medium carbon steel in cryogenic conditions

Directory of Open Access Journals (Sweden)

Jaharah A. Ghani

2017-09-01

Full Text Available This paper presents the tribology issue regarding the chip formation in machining medium carbon steel (S45C using a coated and uncoated carbide tools. The machining parameters under investigation were cutting speed, feed rate, and depth of cut under dry and cryogenic cutting condition using coated and uncoated carbide tools. The chip shape was largely depended on the combination of machining parameters, especially at high depth of cut and feed rate; the favorable chip was produced. Larger value of shear angle results in smaller shear plane area that provides benefits of lower cutting force needed to shear off the chips and lower cutting temperature being generated during the machining process.

A High-Throughput, High-Accuracy System-Level Simulation Framework for System on Chips

Directory of Open Access Journals (Sweden)

Guanyi Sun

2011-01-01

Full Text Available Today's System-on-Chips (SoCs design is extremely challenging because it involves complicated design tradeoffs and heterogeneous design expertise. To explore the large solution space, system architects have to rely on system-level simulators to identify an optimized SoC architecture. In this paper, we propose a system-level simulation framework, System Performance Simulation Implementation Mechanism, or SPSIM. Based on SystemC TLM2.0, the framework consists of an executable SoC model, a simulation tool chain, and a modeling methodology. Compared with the large body of existing research in this area, this work is aimed at delivering a high simulation throughput and, at the same time, guaranteeing a high accuracy on real industrial applications. Integrating the leading TLM techniques, our simulator can attain a simulation speed that is not slower than that of the hardware execution by a factor of 35 on a set of real-world applications. SPSIM incorporates effective timing models, which can achieve a high accuracy after hardware-based calibration. Experimental results on a set of mobile applications proved that the difference between the simulated and measured results of timing performance is within 10%, which in the past can only be attained by cycle-accurate models.

High-speed 1.3 -1.55 um InGaAs/InP PIN photodetector for microwave photonics

Science.gov (United States)

Kozyreva, O. A.; Solov'ev, Y. V.; Polukhin, I. S.; Mikhailov, A. K.; Mikhailovskiy, G. A.; Odnoblyudov, M. A.; Gareev, E. Z.; Kolodeznyi, E. S.; Novikov, I. I.; Karachinsky, L. Ya; Egorov, A. Yu; Bougrov, V. E.

2017-11-01

We have fabricated the 1.3-1.55 um PIN photodetector based on InGaAs/InP heterostructure. Measurement results of optical and electrical characteristics of PIN photodetector chip were the following: photoconductivity at 1550 nm was 0.65 A/W and internal capacitance was 0.025 pF. Microwave model of photodetector was developed and verified by measurements of scattering matrix. The implementation of broadband (up to 20 GHz) hybrid integrated matching and biasing circuit for high-speed photodetector is presented.

Chromatically encoded high-speed photography of cavitation bubble dynamics inside inhomogeneous ophthalmic tissue

Science.gov (United States)

Tinne, N.; Matthias, B.; Kranert, F.; Wetzel, C.; Krüger, A.; Ripken, T.

2016-03-01

The interaction effect of photodisruption, which is used for dissection of biological tissue with fs-laser pulses, has been intensively studied inside water as prevalent sample medium. In this case, the single effect is highly reproducible and, hence, the method of time-resolved photography is sufficiently applicable. In contrast, the reproducibility significantly decreases analyzing more solid and anisotropic media like biological tissue. Therefore, a high-speed photographic approach is necessary in this case. The presented study introduces a novel technique for high-speed photography based on the principle of chromatic encoding. For illumination of the region of interest within the sample medium, the light paths of up to 12 LEDs with various emission wavelengths are overlaid via optical filters. Here, MOSFET-electronics provide a LED flash with a duration diodes are externally triggered with a distinct delay for every LED. Furthermore, the different illumination wavelengths are chromatically separated again for detection via camera chip. Thus, the experimental setup enables the generation of a time-sequence of laser-tissue interaction inside anisotropic biological tissue and for the optimization of the surgical process with high-repetition rate fs-lasers. Additionally, this application is also suitable for the investigation of other microscopic, ultra-fast events in transparent inhomogeneous materials.

Optical signal processing for enabling high-speed, highly spectrally efficient and high capacity optical systems

Science.gov (United States)

Fazal, Muhammad Irfan

The unabated demand for more capacity due to the ever-increasing internet traffic dictates that the boundaries of the state of the art maybe pushed to send more data through the network. Traditionally, this need has been satisfied by multiple wavelengths (wavelength division multiplexing), higher order modulation formats and coherent communication (either individually or combined together). WDM has the ability to reduce cost by using multiple channels within the same physical fiber, and with EDFA amplifiers, the need for O-E-O regenerators is eliminated. Moreover the availability of multiple colors allows for wavelength-based routing and network planning. Higher order modulation formats increases the capacity of the link by their ability to encode data in both the phase and amplitude of light, thereby increasing the bits/sec/Hz as compared to simple on-off keyed format. Coherent communications has also emerged as a primary means of transmitting and receiving optical data due to its support of formats that utilize both phase and amplitude to further increase the spectral efficiency of the optical channel, including quadrature amplitude modulation (QAM) and quadrature phase shift keying (QPSK). Polarization multiplexing of channels can double capacity by allowing two channels to share the same wavelength by propagating on orthogonal polarization axis and is easily supported in coherent systems where the polarization tracking can be performed in the digital domain. Furthermore, the forthcoming IEEE 100 Gbit/s Ethernet Standard, 802.3ba, provides greater bandwidth, higher data rates, and supports a mixture of modulation formats. In particular, Pol-MUX QPSK is increasingly becoming the industry's format of choice as the high spectral efficiency allows for 100 Gbit/s transmission while still occupying the current 50 GHz/channel allocation of current 10 Gbit/s OOK fiber systems. In this manner, 100 Gbit/s transfer speeds using current fiber links, amplifiers, and filters

Establishing Relationship between Process Parameters and Temperature during High Speed End Milling of Soda Lime Glass

Science.gov (United States)

Nasima Bagum, Mst.; Konneh, Mohamed; Yeakub Ali, Mohammad

2018-01-01

In glass machining crack free surface is required in biomedical and optical industry. Ductile mode machining allows materials removal from brittle materials in a ductile manner rather than by brittle fracture. Although end milling is a versatile process, it has not been applied frequently for machining soda lime glass. Soda lime glass is a strain rate and temperature sensitive material; especially around glass transition temperature Tg, ductility increased and strength decreased. Hence, it is envisaged that the generated temperature by high-speed end milling (HSEM) could be brought close to the glass transition temperature, which promote ductile machining. In this research, the objective is to investigate the effect of high speed machining parameters on generated temperature. The cutting parameters were optimized to generate temperature around glass transition temperature of soda lime using response surface methodology (RSM). Result showed that the most influencing process parameter is feed rate followed by spindle speed and depth of cut to generate temperature. Confirmation test showed that combination of spindle speed 30,173 rpm, feed rate 13.2 mm/min and depth of cut 37.68 µm generate 635°C, hence ductile chip removal with machined surface Ra 0.358 µm was possible to achieve.

Study Application of RADIUS Protocol on Ethernet

Institute of Scientific and Technical Information of China (English)

GUO Fang; YANG Huan-yu; LI Hong

2004-01-01

This paper presents how to apply the RADIUS (Remote Authentication Dial In User Service)protocol ,which is generally applied to dial-up network, to the authentication & charge of Broad Band accessing control system on Ethernet. It is provided that the Broad Band accessing control system included a self-designed communication protocol is used in communicating between an terminal user and Network Access Server .The interface module on the servers side and the Radius system is also given in this article.

High-speed AC motors

Energy Technology Data Exchange (ETDEWEB)

Jokinen, T.; Arkkio, A. [Helsinki University of Technology Laboratory of Electromechanics, Otaniemi (Finland)

1997-12-31

The paper deals with various types of highspeed electric motors, and their limiting powers. Standard machines with laminated rotors can be utilised if the speed is moderate. The solid rotor construction makes it possible to reach higher power and speed levels than those of laminated rotors. The development work on high-speed motors done at Helsinki University of Technology is presented, too. (orig.) 12 refs.

Development and validation of a general-purpose ASIC chip for the control of switched reluctance machines

International Nuclear Information System (INIS)

Chen Haijin; Lu Shengli; Shi Longxing

2009-01-01

A general-purpose application specific integrated circuit (ASIC) chip for the control of switched reluctance machines (SRMs) was designed and validated to fill the gap between the microcontroller capability and the controller requirements of high performance switched reluctance drive (SRD) systems. It can be used for the control of SRM running either in low speed or in high-speed, i.e., either in chopped current control (CCC) mode or in angular position control (APC) mode. Main functions of the chip include filtering and cycle calculation of rotor angular position signals, commutation logic according to rotor cycle and turn-on/turn-off angles (θ on /θ off ), controllable pulse width modulation (PWM) waveforms generation, chopping control with adjustable delay time, and commutation control with adjustable delay time. All the control parameters of the chip are set online by the microcontroller through a serial peripheral interface (SPI). The chip has been designed with the standard cell based design methodology, and implemented in the central semiconductor manufacturing corporation (CSMC) 0.5 μm complementary metal-oxide-semiconductor (CMOS) process technology. After a successful automatic test equipment (ATE) test using the Nextest's Maverick test system, the chip was further validated through an experimental three-phase 6/2-pole SRD system. Both the ATE test and experimental validation results show that the chip can meet the control requirements of high performance SRD systems, and simplify the controller construction. For a resolution of 0.36 deg. (electrical degree), the chip's maximum processable frequency of the rotor angular position signals is 10 kHz, which is 300,000 rev/min when a three-phase 6/2-pole SRM is concerned

GaN-based integrated photonics chip with suspended LED and waveguide

Science.gov (United States)

Li, Xin; Wang, Yongjin; Hane, Kazuhiro; Shi, Zheng; Yan, Jiang

2018-05-01

We propose a GaN-based integrated photonics chip with suspended LED and straight waveguide with different geometric parameters. The integrated photonics chip is prepared by double-side process. Light transmission performance of the integrated chip verse current is quantitatively analyzed by capturing light transmitted to waveguide tip and BPM (beam propagation method) simulation. Reduction of the waveguide width from 8 μm to 4 μm results in an over linear reduction of the light output power while a doubling of the length from 250 μm to 500 μm only results in under linear decrease of the output power. Free-space data transmission with 80 Mbps random binary sequence of the integrated chip is capable of achieving high speed data transmission via visible light. This study provides a potential approach for GaN-based integrated photonics chip as micro light source and passive optical device in VLC (visible light communication).

On-chip spectroscopy with thermally tuned high-Q photonic crystal cavities

Energy Technology Data Exchange (ETDEWEB)

Liapis, Andreas C., E-mail: andreas.liapis@gmail.com; Gao, Boshen; Siddiqui, Mahmudur R. [The Institute of Optics, University of Rochester, Rochester, New York 14627 (United States); Shi, Zhimin [Department of Physics, University of South Florida, Tampa, Florida 33620 (United States); Boyd, Robert W. [The Institute of Optics, University of Rochester, Rochester, New York 14627 (United States); Department of Physics and School of Electrical Engineering and Computer Science, University of Ottawa, Ottawa, Ontario K1N 6N5 (Canada)

2016-01-11

Spectroscopic methods are a sensitive way to determine the chemical composition of potentially hazardous materials. Here, we demonstrate that thermally tuned high-Q photonic crystal cavities can be used as a compact high-resolution on-chip spectrometer. We have used such a chip-scale spectrometer to measure the absorption spectra of both acetylene and hydrogen cyanide in the 1550 nm spectral band and show that we can discriminate between the two chemical species even though the two materials have spectral features in the same spectral region. Our results pave the way for the development of chip-size chemical sensors that can detect toxic substances.

Test of Gb Ethernet with FPGA for HADES upgrade

Energy Technology Data Exchange (ETDEWEB)

Gilardi, C. [II. Physikalisches Inst., Giessen Univ. (Germany)

2007-07-01

Within the HADES experiment, we are investigating a trigger upgrade in order to run heavier systems (Au + Au). We investigate Gigabit Ethernet transfers with Xilinx Virtex II FPGA on the commercial board Celoxica RC300E. We implement the transfer protocols (UDP, ICMP, ARP) with Handel-C. First results of bandwidth and latency will be presented. (orig.)

X-CHIP: an integrated platform for high-throughput protein crystallization and on-the-chip X-ray diffraction data collection

International Nuclear Information System (INIS)

Kisselman, Gera; Qiu, Wei; Romanov, Vladimir; Thompson, Christine M.; Lam, Robert; Battaile, Kevin P.; Pai, Emil F.; Chirgadze, Nickolay Y.

2011-01-01

The X-CHIP (X-ray Crystallography High-throughput Integrated Platform) is a novel microchip that has been developed to combine multiple steps of the crystallographic pipeline from crystallization to diffraction data collection on a single device to streamline the entire process. The X-CHIP (X-ray Crystallization High-throughput Integrated Platform) is a novel microchip that has been developed to combine multiple steps of the crystallographic pipeline from crystallization to diffraction data collection on a single device to streamline the entire process. The system has been designed for crystallization condition screening, visual crystal inspection, initial X-ray screening and data collection in a high-throughput fashion. X-ray diffraction data acquisition can be performed directly on-the-chip at room temperature using an in situ approach. The capabilities of the chip eliminate the necessity for manual crystal handling and cryoprotection of crystal samples, while allowing data collection from multiple crystals in the same drop. This technology would be especially beneficial for projects with large volumes of data, such as protein-complex studies and fragment-based screening. The platform employs hydrophilic and hydrophobic concentric ring surfaces on a miniature plate transparent to visible light and X-rays to create a well defined and stable microbatch crystallization environment. The results of crystallization and data-collection experiments demonstrate that high-quality well diffracting crystals can be grown and high-resolution diffraction data sets can be collected using this technology. Furthermore, the quality of a single-wavelength anomalous dispersion data set collected with the X-CHIP at room temperature was sufficient to generate interpretable electron-density maps. This technology is highly resource-efficient owing to the use of nanolitre-scale drop volumes. It does not require any modification for most in-house and synchrotron beamline systems and offers

X-CHIP: an integrated platform for high-throughput protein crystallization and on-the-chip X-ray diffraction data collection

Energy Technology Data Exchange (ETDEWEB)

Kisselman, Gera; Qiu, Wei; Romanov, Vladimir; Thompson, Christine M.; Lam, Robert [Ontario Cancer Institute, Princess Margaret Hospital, University Health Network, Toronto, Ontario M5G 2C4 (Canada); Battaile, Kevin P. [Argonne National Laboratory, Argonne, Illinois 60439 (United States); Pai, Emil F.; Chirgadze, Nickolay Y., E-mail: nchirgad@uhnresearch.ca [Ontario Cancer Institute, Princess Margaret Hospital, University Health Network, Toronto, Ontario M5G 2C4 (Canada); University of Toronto, Toronto, Ontario M5S 1A8 (Canada)

2011-06-01

The X-CHIP (X-ray Crystallography High-throughput Integrated Platform) is a novel microchip that has been developed to combine multiple steps of the crystallographic pipeline from crystallization to diffraction data collection on a single device to streamline the entire process. The X-CHIP (X-ray Crystallization High-throughput Integrated Platform) is a novel microchip that has been developed to combine multiple steps of the crystallographic pipeline from crystallization to diffraction data collection on a single device to streamline the entire process. The system has been designed for crystallization condition screening, visual crystal inspection, initial X-ray screening and data collection in a high-throughput fashion. X-ray diffraction data acquisition can be performed directly on-the-chip at room temperature using an in situ approach. The capabilities of the chip eliminate the necessity for manual crystal handling and cryoprotection of crystal samples, while allowing data collection from multiple crystals in the same drop. This technology would be especially beneficial for projects with large volumes of data, such as protein-complex studies and fragment-based screening. The platform employs hydrophilic and hydrophobic concentric ring surfaces on a miniature plate transparent to visible light and X-rays to create a well defined and stable microbatch crystallization environment. The results of crystallization and data-collection experiments demonstrate that high-quality well diffracting crystals can be grown and high-resolution diffraction data sets can be collected using this technology. Furthermore, the quality of a single-wavelength anomalous dispersion data set collected with the X-CHIP at room temperature was sufficient to generate interpretable electron-density maps. This technology is highly resource-efficient owing to the use of nanolitre-scale drop volumes. It does not require any modification for most in-house and synchrotron beamline systems and offers

Framed bit error rate testing for 100G ethernet equipment

DEFF Research Database (Denmark)

Rasmussen, Anders; Ruepp, Sarah Renée; Berger, Michael Stübert

2010-01-01

rate. As the need for 100 Gigabit Ethernet equipment rises, so does the need for equipment, which can properly test these systems during development, deployment and use. This paper presents early results from a work-in-progress academia-industry collaboration project and elaborates on the challenges...

Synchronization, retiming and time-division multiplexing of an asynchronous 10 gigabit NRZ Ethernet packet to Terabit Ethernet

DEFF Research Database (Denmark)

Hu, Hao; Laguardia Areal, Janaina; Mulvad, Hans Christian Hansen

2011-01-01

An asynchronous 10 Gb/s Ethernet packet with maximum packet size of 1518 bytes is synchronized and retimed to a master clock with 200 kHz frequency offset using a time lens. The NRZ packet is simultaneously converted into an RZ packet, then further pulse compressed to a FWHM of 400 fs and finally...... time-division multiplexed with a serial 1.28 Tb/s signal including a vacant time slot, thus forming a 1.29 Tb/s time-division multiplexed serial signal. Error-free performance of synchronizing, retiming, time-division multiplexing to a Terabit data stream and finally demultiplexing back to 10 Gb...

A molecular dynamics investigation into the mechanisms of subsurface damage and material removal of monocrystalline copper subjected to nanoscale high speed grinding

International Nuclear Information System (INIS)

Li, Jia; Fang, Qihong; Liu, Youwen; Zhang, Liangchi

2014-01-01

This paper investigates the mechanisms of subsurface damage and material removal of monocrystalline copper when it is under a nanoscale high speed grinding of a diamond tip. The analysis was carried out with the aid of three-dimensional molecular dynamics simulations. The key factors that would influence the deformation of the material were carefully explored by analyzing the chip, dislocation movement, and workpiece deformation, which include grinding speed, depth of cut, grid tip radius, crystal orientation and machining angle of copper. An analytical model was also established to predict the emission of partial dislocations during the nanoscale high speed grinding. The investigation showed that a higher grinding velocity, a larger tip radius or a larger depth of cut would result in a larger chipping volume and a greater temperature rise in the copper workpiece. A lower grinding velocity would produce more intrinsic stacking faults. It was also found that the transition of deformation mechanisms depends on the competition between the dislocations and deformation twinning. There is a critical machining angle, at which a higher velocity, a smaller tip radius, or a smaller depth of cut will reduce the subsurface damage and improve the smoothness of a ground surface. The established analytical model showed that the Shockley dislocation emission is most likely to occur with the crystal orientations of (0 0 1)[1 0 0] at 45° angle.

Rotational microfluidic motor for on-chip microcentrifugation

Science.gov (United States)

Shilton, Richie J.; Glass, Nick R.; Chan, Peggy; Yeo, Leslie Y.; Friend, James R.

2011-06-01

We report on the design of a surface acoustic wave (SAW) driven fluid-coupled micromotor which runs at high rotational velocities. A pair of opposing SAWs generated on a lithium niobate substrate are each obliquely passed into either side of a fluid drop to drive rotation of the fluid, and the thin circular disk set on the drop. Using water for the drop, a 5 mm diameter disk was driven with rotation speeds and start-up torques up to 2250 rpm and 60 nN m, respectively. Most importantly for lab-on-a-chip applications, radial accelerations of 172 m/s2 was obtained, presenting possibilities for microcentrifugation, flow sequencing, assays, and cell culturing in truly microscale lab-on-a-chip devices.

Global On-Chip Differential Interconnects with Optimally-Placed Twists

NARCIS (Netherlands)

Mensink, E.; Schinkel, Daniel; Klumperink, Eric A.M.; van Tuijl, Adrianus Johannes Maria; Nauta, Bram

2005-01-01

Global on-chip communication is receiving quite some attention as global interconnects are rapidly becoming a speed, power and reliability bottleneck for digital CMOS systems. Recently, we proposed a bus-transceiver test chip in 0.13 μm CMOS using 10 mm long uninterrupted differential interconnects

An automatic system for elaboration of chip breaking diagrams

DEFF Research Database (Denmark)

Andreasen, Jan Lasson; De Chiffre, Leonardo

1998-01-01

A laboratory system for fully automatic elaboration of chip breaking diagrams has been developed and tested. The system is based on automatic chip breaking detection by frequency analysis of cutting forces in connection with programming of a CNC-lathe to scan different feeds, speeds and cutting...

On-chip plasmon-induced transparency based on plasmonic coupled nanocavities.

Science.gov (United States)

Zhu, Yu; Hu, Xiaoyong; Yang, Hong; Gong, Qihuang

2014-01-17

On-chip plasmon-induced transparency offers the possibility of realization of ultrahigh-speed information processing chips. Unfortunately, little experimental progress has been made to date because it is difficult to obtain on-chip plasmon-induced transparency using only a single meta-molecule in plasmonic circuits. Here, we report a simple and efficient strategy to realize on-chip plasmon-induced transparency in a nanoscale U-shaped plasmonic waveguide side-coupled nanocavity pair. High tunability in the transparency window is achieved by covering the pair with different organic polymer layers. It is possible to realize ultrafast all-optical tunability based on pump light-induced refractive index change of a graphene cover layer. Compared with previous reports, the overall feature size of the plasmonic nanostructure is reduced by more than three orders of magnitude, while ultrahigh tunability of the transparency window is maintained. This work also provides a superior platform for the study of the various physical effects and phenomena of nonlinear optics and quantum optics.

Bidirectional and simultaneous FTTX/Ethernet services using RSOA based remodulation and polarization multiplexing technique

Science.gov (United States)

Das, Anindya S.; Patra, Ardhendu S.

2015-08-01

A bidirectional and simultaneous transmission of Ethernet, FTTX services through single optical carrier wavelength employing polarization multiplexing technique in the transmitter end and the user end. 10 Gbps and 2.5 Gbps datarates are transmitted over 50 km single mode fiber employing POLMUX technique at OLT and ONU to provide Ethernet and FTTX services concurrently to the user. Reflective semiconductor optical amplifier is used to reuse and remodulate the downlink signal to uplink transmission. The upstream and the downstream transmission performances are observed by the bit error rate values and the eye diagrams obtained by the BER analyzer.

Time synchronization for an Ethernet-based real-time token network

NARCIS (Netherlands)

Hanssen, F.T.Y.; van den Boom, Joost; Jansen, P.G.; Scholten, Johan

We present a distributed clock synchronization algorithm. It performs clock synchronization on an Ethernet-based real-time token local area network, without the use of an external clock source. It is used to enable the token schedulers in each node to agree upon a common time. Its intended use is in

Simultaneous transmission of the IEEE 802.11 radio signal and optical Gbit Ethernet over the multimode fiber link

Science.gov (United States)

Maksymiuk, L.; Podziewski, A.

2015-09-01

In the paper we present a successful joint transmission of the IEEE 802.11 signal and an optical Gbit Ethernet over a multimode fiber based link. Most importantly, the multiplexation of both signals was performed in the optical domain. Due to the utilization of the multimode fiber the OBI noise was avoided and both channels were able to operate at the same wavelength. We prove that potential RoF link for IEEE 802.11 signal distribution may be used to additionally transmit other signals as Gbit Ethernet and therefore utilize the fiber infrastructure installed more effectively. The qualities of both the IEEE 802.11 and Ethernet transmissions fulfilled the requirements imposed by appropriate standards.

Flip-chip bonded optoelectronic integration based on ultrathin silicon (UTSi) CMOS

Science.gov (United States)

Hong, Sunkwang; Ho, Tawei; Zhang, Liping; Sawchuk, Alexander A.

2003-06-01

We describe the design and test of flip-chip bonded optoelectronic CMOS devices based on Peregrine Semiconductor's 0.5 micron Ultra-Thin Silicon on sapphire (UTSi) technology. The UTSi process eliminates the substrate leakage that typically results in crosstalk and reduces parasitic capacitance to the substrate, providing many benefits compared to bulk silicon CMOS. The low-loss synthetic sapphire substrate is optically transparent and has a coefficient of thermal expansion suitable for flip-chip bonding of vertical cavity surface emitting lasers (VCSELs) and detectors. We have designed two different UTSi CMOS chips. One contains a flip-chip bonded 1 x 4 photodiode array, a receiver array, a double edge triggered D-flip flop-based 2047-pattern pseudo random bit stream (PRBS) generator and a quadrature-phase LC-voltage controlled oscillator (VCO). The other chip contains a flip-chip bonded 1 x 4 VCSEL array, a driver array based on high-speed low-voltage differential signals (LVDS) and a full-balanced differential LC-VCO. Each VCSEL driver and receiver has individual input and bias voltage adjustments. Each UTSi chip is mounted on different printed circuit boards (PCBs) which have holes with about 1 mm radius for optical output and input paths through the sapphire substrate. We discuss preliminary testing of these chips.

High speed heterostructure devices

CERN Document Server

Beer, Albert C; Willardson, R K; Kiehl, Richard A; Sollner, T C L Gerhard

1994-01-01

Volume 41 includes an in-depth review of the most important, high-speed switches made with heterojunction technology. This volume is aimed at the graduate student or working researcher who needs a broad overview andan introduction to current literature. Key Features * The first complete review of InP-based HFETs and complementary HFETs, which promise very low power and high speed * Offers a complete, three-chapter review of resonant tunneling * Provides an emphasis on circuits as well as devices.

Compact sub-nanosecond pulse seed source with diode laser driven by a high-speed circuit

Science.gov (United States)

Wang, Xiaoqian; Wang, Bo; Wang, Junhua; Cheng, Wenyong

2018-06-01

A compact sub-nanosecond pulse seed source with 1550 nm diode laser (DL) was obtained by employing a high-speed circuit. The circuit mainly consisted of a short pulse generator and a short pulse driver. The short pulse generator, making up of a complex programmable logic device (CPLD), a level translator, two programmable delay chips and an AND gate chip, output a triggering signal to control metal-oxide-semiconductor field-effect transistor (MOSFET) switch of the short pulse driver. The MOSFET switch with fast rising time and falling time both shorter than 1 ns drove the DL to emit short optical pulses. Performances of the pulse seed source were tested. The results showed that continuously adjustable repetition frequency ranging from 500 kHz to 100 MHz and pulse duration in the range of 538 ps to 10 ns were obtained, respectively. 537 μW output was obtained at the highest repetition frequency of 100 MHz with the shortest pulse duration of 538 ps. These seed pulses were injected into an fiber amplifier, and no optical pulse distortions were found.

The Application of Virtex-II Pro FPGA in High-Speed Image Processing Technology of Robot Vision Sensor

International Nuclear Information System (INIS)

Ren, Y J; Zhu, J G; Yang, X Y; Ye, S H

2006-01-01

The Virtex-II Pro FPGA is applied to the vision sensor tracking system of IRB2400 robot. The hardware platform, which undertakes the task of improving SNR and compressing data, is constructed by using the high-speed image processing of FPGA. The lower level image-processing algorithm is realized by combining the FPGA frame and the embedded CPU. The velocity of image processing is accelerated due to the introduction of FPGA and CPU. The usage of the embedded CPU makes it easily to realize the logic design of interface. Some key techniques are presented in the text, such as read-write process, template matching, convolution, and some modules are simulated too. In the end, the compare among the modules using this design, using the PC computer and using the DSP, is carried out. Because the high-speed image processing system core is a chip of FPGA, the function of which can renew conveniently, therefore, to a degree, the measure system is intelligent

The Application of Virtex-II Pro FPGA in High-Speed Image Processing Technology of Robot Vision Sensor

Science.gov (United States)

Ren, Y. J.; Zhu, J. G.; Yang, X. Y.; Ye, S. H.

2006-10-01

The Virtex-II Pro FPGA is applied to the vision sensor tracking system of IRB2400 robot. The hardware platform, which undertakes the task of improving SNR and compressing data, is constructed by using the high-speed image processing of FPGA. The lower level image-processing algorithm is realized by combining the FPGA frame and the embedded CPU. The velocity of image processing is accelerated due to the introduction of FPGA and CPU. The usage of the embedded CPU makes it easily to realize the logic design of interface. Some key techniques are presented in the text, such as read-write process, template matching, convolution, and some modules are simulated too. In the end, the compare among the modules using this design, using the PC computer and using the DSP, is carried out. Because the high-speed image processing system core is a chip of FPGA, the function of which can renew conveniently, therefore, to a degree, the measure system is intelligent.

Overflow control mechanism (OCM) for Ethernet passive optical networks (EPONs)

Science.gov (United States)

Hajduczenia, Marek; da Silva, Henrique J. A.; Monteiro, Paulo P.

2007-05-01

The nonfragmentable nature of Ethernet data frames, as well as operation of the priority oriented packet schedulers in the optical network units, in conjunction with heavy network load conditions and the lack of detailed knowledge about the queue's composition at the optical line terminal (OLT) level, result in the creation of upstream channel slot remainders. The existing methods, in the form of nonpreemptive packet schedulers and multithreshold reporting process defined vaguely by the IEEE 802.3-2005 standard, result in either increased packet delay or Ethernet passive optical network (EPON) system incompatibility, respectively, since threshold processing was never officially defined in the scope of the respective EPON standard. We propose an alternative approach, based on basic modifications of the standard and extended GATE multipoint control protocol data unit format and meaning, allowing for the OLT packet scheduling agent to grant always exactly the requested slot size, thus preventing creation of any upstream channel slot remainders. It is estimated that, on average, ˜3% of upstream channel bandwidth can be salvaged when slot remainders are absent in the upstream channel transmission.

FY1995 trial production of brain functional chip; 1995 nendo no kino shuseki chip no shisaku

Energy Technology Data Exchange (ETDEWEB)

NONE

1997-03-01

The present computer system will run on a program which is prepared in advance. On the other hand, the human brain can acquire some processes from learning with experiments. It would be very useful us human nature, if these learning process should be build up artificially. Our aim is to reveal basic self-acquiring mechanism of information and its processes of the brain, and preliminary research, including theoretical problems, for building up specialized processor chip. Many research on the brain have been held at the views of scientifically and medically. However; we focused on the principle brain learning process itself. The results of the research was directly realized on a specialized processor chip tuned for high-speed simulation of neural network. We could pointed out some problems on the present brain type processor, and discussed about basic technique for implementation of the next age brain type processor and theories. (NEDO)

Synchronization and NRZ-to-RZ format conversion of 10 G Ethernet packet based on a time lens

DEFF Research Database (Denmark)

Hu, Hao; Laguardia Areal, Janaina; Palushani, Evarist

2010-01-01

10 G Ethernet packet with maximum frame size of 1518 bytes is synchronized to a global clock using a time lens. The 10 Gb/s NRZ signal is converted into RZ signal at the same time.......10 G Ethernet packet with maximum frame size of 1518 bytes is synchronized to a global clock using a time lens. The 10 Gb/s NRZ signal is converted into RZ signal at the same time....

Prediction of 3D chip formation in the facing cutting with lathe machine using FEM

Science.gov (United States)

Prasetyo, Yudhi; Tauviqirrahman, Mohamad; Rusnaldy

2016-04-01

This paper presents the prediction of the chip formation at the machining process using a lathe machine in a more specific way focusing on facing cutting (face turning). The main purpose is to propose a new approach to predict the chip formation with the variation of the cutting directions i.e., the backward and forward direction. In addition, the interaction between stress analysis and chip formation on cutting process was also investigated. The simulations were conducted using three dimensional (3D) finite element method based on ABAQUS software with aluminum and high speed steel (HSS) as the workpiece and the tool materials, respectively. The simulation result showed that the chip resulted using a backward direction depicts a better formation than that using a conventional (forward) direction.

"A Fiber Optic Ethernet With Inherent Migration Capability To FDDI"

Science.gov (United States)

Ferris, Kenneth D.; Chan, Tammy S.

1988-12-01

A Local Area Network (LAN) designed to a standard commercial interface, the Institute of Electrical and Electronics Engineers (IEEE) 802.3 or Ethernet, has been developed using fiber optics as the physical medium. The LAN, WhisperNet, operates in an active ring and thus has an inherent low cost migration path to a Fiber Distributed Data Interface (FDDI) implementation.

14 CFR 23.253 - High speed characteristics.

Science.gov (United States)

2010-01-01

... 14 Aeronautics and Space 1 2010-01-01 2010-01-01 false High speed characteristics. 23.253 Section... Requirements § 23.253 High speed characteristics. If a maximum operating speed VMO/MMO is established under § 23.1505(c), the following speed increase and recovery characteristics must be met: (a) Operating...

Novel High Pressure Pump-on-a-Chip Technology, Phase II

Data.gov (United States)

National Aeronautics and Space Administration — HJ Science & Technology, Inc. proposes to develop a novel high pressure "pump-on-a-chip" (HPPOC) technology capable of generating high pressure and flow rate on...

High-Speed Photography

International Nuclear Information System (INIS)

Paisley, D.L.; Schelev, M.Y.

1998-01-01

The applications of high-speed photography to a diverse set of subjects including inertial confinement fusion, laser surgical procedures, communications, automotive airbags, lightning etc. are briefly discussed. (AIP) copyright 1998 Society of Photo-Optical Instrumentation Engineers

Study on the separation effect of high-speed ultrasonic vibration cutting.

Science.gov (United States)

Zhang, Xiangyu; Sui, He; Zhang, Deyuan; Jiang, Xinggang

2018-07-01

High-speed ultrasonic vibration cutting (HUVC) has been proven to be significantly effective when turning Ti-6Al-4V alloy in recent researches. Despite of breaking through the cutting speed restriction of the ultrasonic vibration cutting (UVC) method, HUVC can also achieve the reduction of cutting force and the improvements in surface quality and cutting efficiency in the high-speed machining field. These benefits all result from the separation effect that occurs during the HUVC process. Despite the fact that the influences of vibration and cutting parameters have been discussed in previous researches, the separation analysis of HUVC should be conducted in detail in real cutting situations, and the tool geometry parameters should also be considered. In this paper, three situations are investigated in details: (1) cutting without negative transient clearance angle and without tool wear, (2) cutting with negative transient clearance angle and without tool wear, and (3) cutting with tool wear. And then, complete separation state, partial separation state and continuous cutting state are deduced according to real cutting processes. All the analysis about the above situations demonstrate that the tool-workpiece separation will take place only if appropriate cutting parameters, vibration parameters, and tool geometry parameters are set up. The best separation effect was obtained with a low feedrate and a phase shift approaching 180 degrees. Moreover, flank face interference resulted from the negative transient clearance angle and tool wear contributes to an improved separation effect that makes the workpiece and tool separate even at zero phase shift. Finally, axial and radial transient cutting force are firstly obtained to verify the separation effect of HUVC, and the cutting chips are collected to weigh the influence of flank face interference. Copyright © 2018 Elsevier B.V. All rights reserved.

SEAL FOR HIGH SPEED CENTRIFUGE

Science.gov (United States)

Skarstrom, C.W.

1957-12-17

A seal is described for a high speed centrifuge wherein the centrifugal force of rotation acts on the gasket to form a tight seal. The cylindrical rotating bowl of the centrifuge contains a closure member resting on a shoulder in the bowl wall having a lower surface containing bands of gasket material, parallel and adjacent to the cylinder wall. As the centrifuge speed increases, centrifugal force acts on the bands of gasket material forcing them in to a sealing contact against the cylinder wall. This arrangememt forms a simple and effective seal for high speed centrifuges, replacing more costly methods such as welding a closure in place.

High-Speed Data Recorder for Space, Geodesy, and Other High-Speed Recording Applications

Science.gov (United States)

Taveniku, Mikael

2013-01-01

A high-speed data recorder and replay equipment has been developed for reliable high-data-rate recording to disk media. It solves problems with slow or faulty disks, multiple disk insertions, high-altitude operation, reliable performance using COTS hardware, and long-term maintenance and upgrade path challenges. The current generation data recor - ders used within the VLBI community are aging, special-purpose machines that are both slow (do not meet today's requirements) and are very expensive to maintain and operate. Furthermore, they are not easily upgraded to take advantage of commercial technology development, and are not scalable to multiple 10s of Gbit/s data rates required by new applications. The innovation provides a softwaredefined, high-speed data recorder that is scalable with technology advances in the commercial space. It maximally utilizes current technologies without being locked to a particular hardware platform. The innovation also provides a cost-effective way of streaming large amounts of data from sensors to disk, enabling many applications to store raw sensor data and perform post and signal processing offline. This recording system will be applicable to many applications needing realworld, high-speed data collection, including electronic warfare, softwaredefined radar, signal history storage of multispectral sensors, development of autonomous vehicles, and more.

Power-over-ethernet for remote measurement and control

International Nuclear Information System (INIS)

Behera, Rajendra Prasad; Murali, N.

2011-01-01

Power-Over-Ethernet (PoE) technology (IEEE standard 802.3af) allows Remote Measurement and Control in harsh environment where human access is difficult in various nuclear research fields. The terminal measurement and control unit receives power for its operation and communicates data over the same LAN cable, without needing to provide power supplies from different source. Almost all data acquisition systems require both data connectivity and a power supply. In a familiar example, telephones are powered from the telephone exchange through the same twisted pair that carries the voice. Now we can do the same thing with Ethernet devices by combining power and data. Only one set of wires is required to bring to the end measurement and control unit which will simplify installation and save space. Remote unit can be easily moved, to wherever a LAN cable can be laid with minimal disruption to the workplace. It is safer as no mains supply is required. Uninterrupted power supply can be guaranteed to the terminal unit during mains power failure. The terminal unit can be shut down and reset remotely without needing for a reset button and power switch. Simple Network Management Protocol (SNMP) can be used to monitor and control the remote unit. PoE will enable to deploy many more embedded systems in nuclear and other industry like Voice over Internet Protocol (VoIP), Security Camera, Tele-information System, Remote Access Control System, Intruder Detection System, and Tele-Medicine System, etc. (author)

High-Tc dc-SQUID gradiometers in flip-chip configuration

International Nuclear Information System (INIS)

Peiselt, K; Schmidl, F; Linzen, S; Anton, A S; Huebner, U; Seidel, P

2003-01-01

We describe a new design of a gradiometric flip-chip antenna, which is inductively coupled to a dc-SQUID gradiometer. Both components are patterned out of thin films of the high-T c superconductor YBa 2 Cu 3 O 7-x (YBCO). For the flip-chip antenna, a 40 mm x 10 mm SrTiO 3 single crystalline substrate is used, while the gradiometer sensors are prepared on 10 mm x 10 mm SrTiO 3 bicrystal substrates. Special attention is paid to the inductive coupling between the flip-chip antenna and the read-out gradiometer antenna. We investigate different designs of coupling loops in order to optimize the coupling inductance between both components of the sensor. With optimized coupling the sensor achieves a field-gradient resolution of 12 fT cm -1 Hz -1/2 in the white noise region and of 310 fT cm -1 Hz -1/2 at 1 Hz in the unshielded laboratory environment

High-Tc dc-SQUID gradiometers in flip-chip configuration

Science.gov (United States)

Peiselt, K.; Schmidl, F.; Linzen, S.; Anton, A. S.; Hübner, U.; Seidel, P.

2003-12-01

We describe a new design of a gradiometric flip-chip antenna, which is inductively coupled to a dc-SQUID gradiometer. Both components are patterned out of thin films of the high-Tc superconductor YBa2Cu3O7-x (YBCO). For the flip-chip antenna, a 40 mm × 10 mm SrTiO3 single crystalline substrate is used, while the gradiometer sensors are prepared on 10 mm × 10 mm SrTiO3 bicrystal substrates. Special attention is paid to the inductive coupling between the flip-chip antenna and the read-out gradiometer antenna. We investigate different designs of coupling loops in order to optimize the coupling inductance between both components of the sensor. With optimized coupling the sensor achieves a field-gradient resolution of 12 fT cm-1 Hz-1/2 in the white noise region and of 310 fT cm-1 Hz-1/2 at 1 Hz in the unshielded laboratory environment.

Nanoliter Centrifugal Liquid Dispenser Coupled with Superhydrophobic Microwell Array Chips for High-Throughput Cell Assays

Directory of Open Access Journals (Sweden)

Yuyi Wang

2018-06-01

Full Text Available Microfluidic systems have been regarded as a potential platform for high-throughput screening technology in drug discovery due to their low sample consumption, high integration, and easy operation. The handling of small-volume liquid is an essential operation in microfluidic systems, especially in investigating large-scale combination conditions. Here, we develop a nanoliter centrifugal liquid dispenser (NanoCLD coupled with superhydrophobic microwell array chips for high-throughput cell-based assays in the nanoliter scale. The NanoCLD consists of a plastic stock block with an array of drilled through holes, a reagent microwell array chip (reagent chip, and an alignment bottom assembled together in a fixture. A simple centrifugation at 800 rpm can dispense ~160 nL reagents into microwells in 5 min. The dispensed reagents are then delivered to cells by sandwiching the reagent chip upside down with another microwell array chip (cell chip on which cells are cultured. A gradient of doxorubicin is then dispensed to the cell chip using the NanoCLD for validating the feasibility of performing drug tests on our microchip platform. This novel nanoliter-volume liquid dispensing method is simple, easy to operate, and especially suitable for repeatedly dispensing many different reagents simultaneously to microwells.

An ultra-high-speed direct digital frequency synthesizer implemented in GaAs HBT technology

International Nuclear Information System (INIS)

Chen Gaopeng; Wu Danyu; Jin Zhi; Liu Xinyu

2010-01-01

This paper presents a 10-GHz 8-bit direct digital synthesizer (DDS) microwave monolithic integrated circuit implemented in 1 μm GaAs HBT technology. The DDS takes a double-edge-trigger (DET) 8-stage pipeline accumulator with sine-weighted DAC-based ROM-less architecture, which can maximize the utilization ratio of the GaAs HBT's high-speed potential. With an output frequency up to 5 GHz, the DDS gives an average spurious free dynamic range of 23.24 dBc through the first Nyquist band, and consumes 2.4 W of DC power from a single -4.6 V DC supply. Using 1651 GaAs HBT transistors, the total area of the DDS chip is 2.4 x 2.0 mm 2 . (semiconductor integrated circuits)

The high speed civil transport and NASA's High Speed Research (HSR) program

Science.gov (United States)

Shaw, Robert J.

1994-01-01

Ongoing studies being conducted not only in this country but in Europe and Asia suggest that a second generation supersonic transport, or High-Speed Civil Transport (HSCT), could become an important part of the 21st century international air transportation system. However, major environmental compatibility and economic viability issues must be resolved if the HSCT is to become a reality. This talk will overview the NASA High-Speed Research (HSR) program which is aimed at providing the U.S. industry with a technology base to allow them to consider launching an HSCT program early in the next century. The talk will also discuss some of the comparable activities going on within Europe and Japan.

Embedded Processor Based Automatic Temperature Control of VLSI Chips

Directory of Open Access Journals (Sweden)

Narasimha Murthy Yayavaram

2009-01-01

Full Text Available This paper presents embedded processor based automatic temperature control of VLSI chips, using temperature sensor LM35 and ARM processor LPC2378. Due to the very high packing density, VLSI chips get heated very soon and if not cooled properly, the performance is very much affected. In the present work, the sensor which is kept very near proximity to the IC will sense the temperature and the speed of the fan arranged near to the IC is controlled based on the PWM signal generated by the ARM processor. A buzzer is also provided with the hardware, to indicate either the failure of the fan or overheating of the IC. The entire process is achieved by developing a suitable embedded C program.

Using a High-Speed Camera to Measure the Speed of Sound

Science.gov (United States)

Hack, William Nathan; Baird, William H.

2012-01-01

The speed of sound is a physical property that can be measured easily in the lab. However, finding an inexpensive and intuitive way for students to determine this speed has been more involved. The introduction of affordable consumer-grade high-speed cameras (such as the Exilim EX-FC100) makes conceptually simple experiments feasible. Since the…

New Ethernet Based Optically Transparent Network for Fiber-to-the-Desk Application

NARCIS (Netherlands)

Radovanovic, Igor; van Etten, Wim

2003-01-01

We present a new optical local area network architecture based on multimode optical fibers and components, short wavelength lasers and detectors and the widely used fast Ethernet protocol. The presented optically transparent network represent a novel approach in fiber-to-the-desk applications. It is

33 CFR 84.24 - High-speed craft.

Science.gov (United States)

2010-07-01

... 33 Navigation and Navigable Waters 1 2010-07-01 2010-07-01 false High-speed craft. 84.24 Section... RULES ANNEX I: POSITIONING AND TECHNICAL DETAILS OF LIGHTS AND SHAPES § 84.24 High-speed craft. (a) The masthead light of high-speed craft with a length to breadth ratio of less than 3.0 may be placed at a...

Modern trends in designing high-speed trains

Directory of Open Access Journals (Sweden)

Golubović Snežana D.

2015-01-01

Full Text Available Increased advantages of railway transportation systems over other types of transportation systems in the past sixty years have been a result of an intensive development of the new generations of high-speed trains. Not only do these types of trains comply with the need for increased speed of transportation and make the duration of the journey shorter, but they also meet the demands for increased reliability, safety and direct application of energy efficiency to the transportation system itself. Along with increased train speed, the motion resistance is increased as well, whereby at speeds over 200 km/h the proportion of air resistance becomes the most dominant member. One of the most efficient measures for reducing air resistance, as well as other negative consequences of high-speed motion, is the development of the aerodynamic shape of the train. This paper presents some construction solutions that affect the aerodynamic properties of high-speed trains, first and foremost, the nose shape, as well as the similarities and differences of individual subsystems necessary for the functioning of modern high-speed rail systems. We analysed two approaches to solving the problem of the aerodynamic shape of the train and the appropriate infrastructure using the examples of Japan and France. Two models of high-speed trains, Shinkansen (Japan and TGV, i.e. AGV (France, have been discussed.

Simple Exact Algorithm for Transistor Sizing of Low-Power High-Speed Arithmetic Circuits

Directory of Open Access Journals (Sweden)

Tooraj Nikoubin

2010-01-01

Full Text Available A new transistor sizing algorithm, SEA (Simple Exact Algorithm, for optimizing low-power and high-speed arithmetic integrated circuits is proposed. In comparison with other transistor sizing algorithms, simplicity, accuracy, independency of order and initial sizing factors of transistors, and flexibility in choosing the optimization parameters such as power consumption, delay, Power-Delay Product (PDP, chip area or the combination of them are considered as the advantages of this new algorithm. More exhaustive rules of grouping transistors are the main trait of our algorithm. Hence, the SEA algorithm dominates some major transistor sizing metrics such as optimization rate, simulation speed, and reliability. According to approximate comparison of the SEA algorithm with MDE and ADC for a number of conventional full adder circuits, delay and PDP have been improved 55.01% and 57.92% on an average, respectively. By comparing the SEA and Chang's algorithm, 25.64% improvement in PDP and 33.16% improvement in delay have been achieved. All the simulations have been performed with 0.13 m technology based on the BSIM3v3 model using HSpice simulator software.

8051 microcontroller to FPGA and ADC interface design for high speed parallel processing systems – Application in ultrasound scanners

Directory of Open Access Journals (Sweden)

J. Jean Rossario Raj

2016-09-01

Full Text Available Microcontrollers perform the hardware control in many instruments. Instruments requiring huge data throughput and parallel computing use FPGA’s for data processing. The microcontroller in turn configures the application hardware devices such as FPGA’s, ADC’s and Ethernet chips etc. The interfacing of these devices uses address/data bus interface, serial interface or serial peripheral interface. The choice of the interface depends upon the input/output pins available with different devices, programming ease and proprietary interfaces supported by devices such as ADC’s. The novelty of this paper is to describe the programming logic used for various types of interface scenarios from microcontroller to different programmable devices. The study presented describes the methods and logic flowcharts for different interfaces. The implementation of the interface logics were in prototype hardware for ultrasound scanner. The internal devices were controlled from the graphical user interface in a laptop and the scan results are taken. It is seen that the optimum solution of the hardware design can be achieved by using a common serial interface towards all the devices.

Changes of indicators of high-speed and high-speed and power preparedness at volleyball players of 12–13 years old

Directory of Open Access Journals (Sweden)

Oleg Shevchenko

2016-04-01

Full Text Available Purpose: to define changes of indicators of high-speed and high-speed and power preparedness of volleyball players of 12–13 years old. Material & Methods: the test exercises, which are recommended by the training program of CYSS on volleyball, were used for the definition of the level of development of high-speed and high-speed and power abilities of volleyball players. 25 young volleyball players from the group of the previous basic preparation took part in the experiment. Sports experience of sportsmen is 3–4 years. The analysis of scientifically-methodical literature, pedagogical testing, pedagogical experiment, methods of mathematical statistics were carried out. Results: the analyzed level of high-speed and high-speed and power abilities of volleyball players. Conclusions: the results had reliable changes (t=2,2–2,4 at р<0,05 of the level of high-speed and high-speed and power abilities of volleyball players of 12–13years old in the experimental group at the end of the experiment, except run on 30 m that demonstrates a positive influence of application of special exercises in the educational-training process.

Reducing Heating In High-Speed Cinematography

Science.gov (United States)

Slater, Howard A.

1989-01-01

Infrared-absorbing and infrared-reflecting glass filters simple and effective means for reducing rise in temperature during high-speed motion-picture photography. "Hot-mirror" and "cold-mirror" configurations, employed in projection of images, helps prevent excessive heating of scenes by powerful lamps used in high-speed photography.

High speed data acquisition

International Nuclear Information System (INIS)

Cooper, P.S.

1997-07-01

A general introduction to high speed data acquisition system techniques in modern particle physics experiments is given. Examples are drawn from the SELEX(E78 1) high statistics charmed baryon production and decay experiment now taking data at Fermilab

Characterization of AGIPD1.0: The full scale chip

Energy Technology Data Exchange (ETDEWEB)

Mezza, D., E-mail: davide.mezza@psi.ch [Paul-Scherrer-Institute (PSI), Villigen (Switzerland); Allahgholi, A.; Arino-Estrada, G.; Bianco, L.; Delfs, A. [Deutsches Elektronensynchrotron DESY, Hamburg (Germany); Dinapoli, R. [Paul-Scherrer-Institute (PSI), Villigen (Switzerland); Goettlicher, P. [Deutsches Elektronensynchrotron DESY, Hamburg (Germany); Graafsma, H. [Deutsches Elektronensynchrotron DESY, Hamburg (Germany); Mid Sweden University, Sundsvall (Sweden); Greiffenberg, D. [Paul-Scherrer-Institute (PSI), Villigen (Switzerland); Hirsemann, H.; Jack, S. [Deutsches Elektronensynchrotron DESY, Hamburg (Germany); Klanner, R. [University of Hamburg, Hamburg (Germany); Klyuev, A. [Deutsches Elektronensynchrotron DESY, Hamburg (Germany); Krueger, H. [University of Bonn, Bonn (Germany); Marras, A. [Deutsches Elektronensynchrotron DESY, Hamburg (Germany); Mozzanica, A. [Paul-Scherrer-Institute (PSI), Villigen (Switzerland); Poehlsen, J. [Deutsches Elektronensynchrotron DESY, Hamburg (Germany); Schmitt, B. [Paul-Scherrer-Institute (PSI), Villigen (Switzerland); Schwandt, J. [University of Hamburg, Hamburg (Germany); Sheviakov, I. [Deutsches Elektronensynchrotron DESY, Hamburg (Germany); and others

2016-12-01

The AGIPD (adaptive gain integrating pixel detector) detector is a high frame rate (4.5 MHz) and high dynamic range (up to 10{sup 4} ·12.4 keV photons) detector with single photon resolution (down to 4 keV taking 5σ as limit and lowest noise settings) developed for the European XFEL (XFEL.EU). This work is focused on the characterization of AGIPD1.0, which is the first full scale version of the chip. The chip is 64×64 pixels and each pixel has a size of 200×200 μm{sup 2}. Each pixel can store up to 352 images at a rate of 4.5 MHz (corresponding to 220 ns). A detailed characterization of the AGIPD1.0 chip has been performed in order to assess the main performance of the ASIC in terms of gain, noise, speed and dynamic range. From the measurements presented in this paper a good uniformity of the gain, a noise around 320 e{sup −} (rms) in standard mode and around 240 e{sup −} (rms) in high gain mode has been measured. Furthermore a detailed discussion about the non-linear behavior after the gain switching is presented with both experimental results and simulations.

Ceramic thermal wind sensor based on advanced direct chip attaching package

International Nuclear Information System (INIS)

Zhou Lin; Qin Ming; Chen Shengqi; Chen Bei

2014-01-01

An advanced direct chip attaching packaged two-dimensional ceramic thermal wind sensor is studied. The thermal wind sensor chip is fabricated by metal lift-off processes on the ceramic substrate. An advanced direct chip attaching (DCA) packaging is adopted and this new packaged method simplifies the processes of packaging further. Simulations of the advanced DCA packaged sensor based on computational fluid dynamics (CFD) model show the sensor can detect wind speed and direction effectively. The wind tunnel testing results show the advanced DCA packaged sensor can detect the wind direction from 0° to 360° and wind speed from 0 to 20 m/s with the error less than 0.5 m/s. The nonlinear fitting based least square method in Matlab is used to analyze the performance of the sensor. (semiconductor devices)

Highly sensitive bacterial susceptibility test against penicillin using parylene-matrix chip.

Science.gov (United States)

Park, Jong-Min; Kim, Jo-Il; Song, Hyun-Woo; Noh, Joo-Yoon; Kang, Min-Jung; Pyun, Jae-Chul

2015-09-15

This work presented a highly sensitive bacterial antibiotic susceptibility test through β-lactamase assay using Parylene-matrix chip. β-lactamases (EC 3.5.2.6) are an important family of enzymes that confer resistance to β-lactam antibiotics by catalyzing the hydrolysis of these antibiotics. Here we present a highly sensitive assay to quantitate β-lactamase-mediated hydrolysis of penicillin into penicilloic acid. Typically, MALDI-TOF mass spectrometry has been used to quantitate low molecular weight analytes and to discriminate them from noise peaks of matrix fragments that occur at low m/z ratios (m/ztest was carried out using Parylene-matrix chip and MALDI-TOF mass spectrometry. The Parylene-matrix chip was successfully used to quantitate penicillin (m/z: [PEN+H](+)=335.1 and [PEN+Na](+)=357.8) and penicilloic acid (m/z: [PA+H](+)=353.1) in a β-lactamase assay with minimal interference of low molecular weight noise peaks. The β-lactamase assay was carried out with an antibiotic-resistant E. coli strain and an antibiotic-susceptible E. coli strain, revealing that the minimum number of E. coli cells required to screen for antibiotic resistance was 1000 cells for the MALDI-TOF mass spectrometry/Parylene-matrix chip assay. Copyright © 2015 Elsevier B.V. All rights reserved.

Wake flow characteristics at high wind speed

DEFF Research Database (Denmark)

Aagaard Madsen, Helge; Larsen, Torben J.; Larsen, Gunner Chr.

2016-01-01

Wake flow characteristic at high wind speeds is the main subject of this paper. Although the wake losses decrease at high wind speeds it has been found in a recent study that for multiple wake inflow the increase in loading due to wake effects are substantial even at wind speeds well above rated ...

Genome-wide association study for milking speed in French Holstein cows

DEFF Research Database (Denmark)

Marete, Andrew Gitahi; Sahana, Goutam; Fritz, Sebastian

2018-01-01

Using a combination of data from the BovineSNP50 BeadChip SNP array (Illumina, San Diego, CA) and a EuroGenomics (Amsterdam, the Netherlands) custom single nucleotide polymorphism (SNP) chip with SNP pre-selected from whole genome sequence data, we carried out an association study of milking speed...... associated with milking speed. As clinical mastitis and somatic cell score have an unfavorable genetic correlation with milking speed, we tested whether the most significant SNP on these 22 chromosomes associated with milking speed were also associated with clinical mastitis or somatic cell score. Nine...... hundred seventy-one genome-wide significant SNP were associated with milking speed. Of these, 86 were associated with clinical mastitis and 198 with somatic cell score. The most significant association signals for milking speed were observed on chromosomes 7, 8, 10, 14, and 18. The most significant signal...

Development of a high-throughput Candida albicans biofilm chip.

Directory of Open Access Journals (Sweden)

Anand Srinivasan

2011-04-01

Full Text Available We have developed a high-density microarray platform consisting of nano-biofilms of Candida albicans. A robotic microarrayer was used to print yeast cells of C. albicans encapsulated in a collagen matrix at a volume as low as 50 nL onto surface-modified microscope slides. Upon incubation, the cells grow into fully formed "nano-biofilms". The morphological and architectural complexity of these biofilms were evaluated by scanning electron and confocal scanning laser microscopy. The extent of biofilm formation was determined using a microarray scanner from changes in fluorescence intensities due to FUN 1 metabolic processing. This staining technique was also adapted for antifungal susceptibility testing, which demonstrated that, similar to regular biofilms, cells within the on-chip biofilms displayed elevated levels of resistance against antifungal agents (fluconazole and amphotericin B. Thus, results from structural analyses and antifungal susceptibility testing indicated that despite miniaturization, these biofilms display the typical phenotypic properties associated with the biofilm mode of growth. In its final format, the C. albicans biofilm chip (CaBChip is composed of 768 equivalent and spatially distinct nano-biofilms on a single slide; multiple chips can be printed and processed simultaneously. Compared to current methods for the formation of microbial biofilms, namely the 96-well microtiter plate model, this fungal biofilm chip has advantages in terms of miniaturization and automation, which combine to cut reagent use and analysis time, minimize labor intensive steps, and dramatically reduce assay costs. Such a chip should accelerate the antifungal drug discovery process by enabling rapid, convenient and inexpensive screening of hundreds-to-thousands of compounds simultaneously.

Neural chips, neural computers and application in high and superhigh energy physics experiments

International Nuclear Information System (INIS)

Nikityuk, N.M.; )

2001-01-01

Architecture peculiarity and characteristics of series of neural chips and neural computes used in scientific instruments are considered. Tendency of development and use of them in high energy and superhigh energy physics experiments are described. Comparative data which characterize the efficient use of neural chips for useful event selection, classification elementary particles, reconstruction of tracks of charged particles and for search of hypothesis Higgs particles are given. The characteristics of native neural chips and accelerated neural boards are considered [ru

High speed non-latching squid binary ripple counter

International Nuclear Information System (INIS)

Silver, A.H.; Phillips, R.R.; Sandell, R.D.

1985-01-01

High speed, single flux quantum (SFQ) binary scalers are important components in superconducting analog-to-digital converters (ADC). This paper reviews the concept for a SQUID ADC and the design of an SFQ binary ripple counter, and reports the simulation of key components, and fabrication and performance of non-latching SQUID scalers and SFQ binary ripple counters. The SQUIDs were fabricated with Nb/Nb 2 O 5 /PbIn junctions and interconnected by monolithic superconducting transmission lines and isolation resistors. Each SQUID functioned as a bistable flip-flop with the input connected to the center of the device and the output across one junction. All junctions were critically damped to optimize the pulse response. Operation was verified by observing the dc I-V curves of successive SQUIDs driven by a cw pulse train generated on the same chip. Each SQUID exhibited constant-voltage current steps at 1/2 the voltage of the preceding device as expected from the Josephson voltage-to-frequency relation. Steps were observed only for the same voltage polarity of successive devices and for proper phase bias of the SQUID. Binary frequency division was recorded up to 40GHz for devices designed to operate to 28GHz

14 CFR 25.253 - High-speed characteristics.

Science.gov (United States)

2010-01-01

... 14 Aeronautics and Space 1 2010-01-01 2010-01-01 false High-speed characteristics. 25.253 Section...-speed characteristics. (a) Speed increase and recovery characteristics. The following speed increase and recovery characteristics must be met: (1) Operating conditions and characteristics likely to cause...

Research on single-chip microcomputer controlled rotating magnetic field mineralization model

Science.gov (United States)

Li, Yang; Qi, Yulin; Yang, Junxiao; Li, Na

2017-08-01

As one of the method of selecting ore, the magnetic separation method has the advantages of stable operation, simple process flow, high beneficiation efficiency and no chemical environment pollution. But the existing magnetic separator are more mechanical, the operation is not flexible, and can not change the magnetic field parameters according to the precision of the ore needed. Based on the existing magnetic separator is mechanical, the rotating magnetic field can be used for single chip microcomputer control as the research object, design and trial a rotating magnetic field processing prototype, and through the single-chip PWM pulse output to control the rotation of the magnetic field strength and rotating magnetic field speed. This method of using pure software to generate PWM pulse to control rotary magnetic field beneficiation, with higher flexibility, accuracy and lower cost, can give full play to the performance of single-chip.

Chicago-St. Louis high speed rail plan

International Nuclear Information System (INIS)

Stead, M.E.

1994-01-01

The Illinois Department of Transportation (IDOT), in cooperation with Amtrak, undertook the Chicago-St. Louis High Speed Rail Financial and Implementation Plan study in order to develop a realistic and achievable blueprint for implementation of high speed rail in the Chicago-St. Louis corridor. This report presents a summary of the Price Waterhouse Project Team's analysis and the Financial and Implementation Plan for implementing high speed rail service in the Chicago-St. Louis corridor

Chicago-St. Louis high speed rail plan

Energy Technology Data Exchange (ETDEWEB)

Stead, M.E.

1994-12-31

The Illinois Department of Transportation (IDOT), in cooperation with Amtrak, undertook the Chicago-St. Louis High Speed Rail Financial and Implementation Plan study in order to develop a realistic and achievable blueprint for implementation of high speed rail in the Chicago-St. Louis corridor. This report presents a summary of the Price Waterhouse Project Team`s analysis and the Financial and Implementation Plan for implementing high speed rail service in the Chicago-St. Louis corridor.

Prototype system tests of the Belle II PXD DAQ system

Energy Technology Data Exchange (ETDEWEB)

Fleischer, Soeren; Gessler, Thomas; Kuehn, Wolfgang; Lange, Jens Soeren; Muenchow, David; Spruck, Bjoern [II. Physikalisches Institut, Justus-Liebig-Universitaet Giessen (Germany); Liu, Zhen' An; Xu, Hao; Zhao, Jingzhou [Institute of High Energy Physics, Chinese Academy of Sciences (China); Collaboration: II PXD Collaboration

2012-07-01

The data acquisition system for the Belle II DEPFET Pixel Vertex Detector (PXD) is designed to cope with a high input data rate of up to 21.6 GB/s. The main hardware component will be AdvancedTCA-based Compute Nodes (CN) equipped with Xilinx Virtex-5 FX70T FPGAs. The design for the third Compute Node generation was completed recently. The xTCA-compliant system features a carrier board and 4 AMC daughter boards. First test results of a prototype board will be presented, including tests of (a) The high-speed optical links used for data input, (b) The two 2 GB DDR2-chips on the board and (c) Output of data via ethernet, using UDP and TCP/IP with both hardware and software protocol stacks.

Development of Neuromorphic Sift Operator with Application to High Speed Image Matching

Science.gov (United States)

Shankayi, M.; Saadatseresht, M.; Bitetto, M. A. V.

2015-12-01

There was always a speed/accuracy challenge in photogrammetric mapping process, including feature detection and matching. Most of the researches have improved algorithm's speed with simplifications or software modifications which increase the accuracy of the image matching process. This research tries to improve speed without enhancing the accuracy of the same algorithm using Neuromorphic techniques. In this research we have developed a general design of a Neuromorphic ASIC to handle algorithms such as SIFT. We also have investigated neural assignment in each step of the SIFT algorithm. With a rough estimation based on delay of the used elements including MAC and comparator, we have estimated the resulting chip's performance for 3 scenarios, Full HD movie (Videogrammetry), 24 MP (UAV photogrammetry), and 88 MP image sequence. Our estimations led to approximate 3000 fps for Full HD movie, 250 fps for 24 MP image sequence and 68 fps for 88MP Ultracam image sequence which can be a huge improvement for current photogrammetric processing systems. We also estimated the power consumption of less than10 watts which is not comparable to current workflows.

Lubrication and cooling for high speed gears

Science.gov (United States)

Townsend, D. P.

1985-01-01

The problems and failures occurring with the operation of high speed gears are discussed. The gearing losses associated with high speed gearing such as tooth mesh friction, bearing friction, churning, and windage are discussed with various ways shown to help reduce these losses and thereby improve efficiency. Several different methods of oil jet lubrication for high speed gearing are given such as into mesh, out of mesh, and radial jet lubrication. The experiments and analytical results for the various methods of oil jet lubrication are shown with the strengths and weaknesses of each method discussed. The analytical and experimental results of gear lubrication and cooling at various test conditions are presented. These results show the very definite need of improved methods of gear cooling at high speed and high load conditions.

The use of high-speed imaging in education

Science.gov (United States)

Kleine, H.; McNamara, G.; Rayner, J.

2017-02-01

Recent improvements in camera technology and the associated improved access to high-speed camera equipment have made it possible to use high-speed imaging not only in a research environment but also specifically for educational purposes. This includes high-speed sequences that are created both with and for a target audience of students in high schools and universities. The primary goal is to engage students in scientific exploration by providing them with a tool that allows them to see and measure otherwise inaccessible phenomena. High-speed imaging has the potential to stimulate students' curiosity as the results are often surprising or may contradict initial assumptions. "Live" demonstrations in class or student- run experiments are highly suitable to have a profound influence on student learning. Another aspect is the production of high-speed images for demonstration purposes. While some of the approaches known from the application of high speed imaging in a research environment can simply be transferred, additional techniques must often be developed to make the results more easily accessible for the targeted audience. This paper describes a range of student-centered activities that can be undertaken which demonstrate how student engagement and learning can be enhanced through the use of high speed imaging using readily available technologies.

Integrating photonics with silicon nanoelectronics for the next generation of systems on a chip.

Science.gov (United States)

Atabaki, Amir H; Moazeni, Sajjad; Pavanello, Fabio; Gevorgyan, Hayk; Notaros, Jelena; Alloatti, Luca; Wade, Mark T; Sun, Chen; Kruger, Seth A; Meng, Huaiyu; Al Qubaisi, Kenaish; Wang, Imbert; Zhang, Bohan; Khilo, Anatol; Baiocco, Christopher V; Popović, Miloš A; Stojanović, Vladimir M; Ram, Rajeev J

2018-04-01

Electronic and photonic technologies have transformed our lives-from computing and mobile devices, to information technology and the internet. Our future demands in these fields require innovation in each technology separately, but also depend on our ability to harness their complementary physics through integrated solutions 1,2 . This goal is hindered by the fact that most silicon nanotechnologies-which enable our processors, computer memory, communications chips and image sensors-rely on bulk silicon substrates, a cost-effective solution with an abundant supply chain, but with substantial limitations for the integration of photonic functions. Here we introduce photonics into bulk silicon complementary metal-oxide-semiconductor (CMOS) chips using a layer of polycrystalline silicon deposited on silicon oxide (glass) islands fabricated alongside transistors. We use this single deposited layer to realize optical waveguides and resonators, high-speed optical modulators and sensitive avalanche photodetectors. We integrated this photonic platform with a 65-nanometre-transistor bulk CMOS process technology inside a 300-millimetre-diameter-wafer microelectronics foundry. We then implemented integrated high-speed optical transceivers in this platform that operate at ten gigabits per second, composed of millions of transistors, and arrayed on a single optical bus for wavelength division multiplexing, to address the demand for high-bandwidth optical interconnects in data centres and high-performance computing 3,4 . By decoupling the formation of photonic devices from that of transistors, this integration approach can achieve many of the goals of multi-chip solutions 5 , but with the performance, complexity and scalability of 'systems on a chip' 1,6-8 . As transistors smaller than ten nanometres across become commercially available 9 , and as new nanotechnologies emerge 10,11 , this approach could provide a way to integrate photonics with state-of-the-art nanoelectronics.

High speed ultra-broadband amplitude modulators with ultrahigh extinction >65 dB.

Science.gov (United States)

Liu, S; Cai, H; DeRose, C T; Davids, P; Pomerene, A; Starbuck, A L; Trotter, D C; Camacho, R; Urayama, J; Lentine, A

2017-05-15

We experimentally demonstrate ultrahigh extinction ratio (>65 dB) amplitude modulators (AMs) that can be electrically tuned to operate across a broad spectral range of 160 nm from 1480 - 1640 nm and 95 nm from 1280 - 1375 nm. Our on-chip AMs employ one extra coupler compared with conventional Mach-Zehnder interferometers (MZI), thus form a cascaded MZI (CMZI) structure. Either directional or adiabatic couplers are used to compose the CMZI AMs and experimental comparisons are made between these two different structures. We investigate the performance of CMZI AMs under extreme conditions such as using 95:5 split ratio couplers and unbalanced waveguide losses. Electro-optic phase shifters are also integrated in the CMZI AMs for high-speed operation. Finally, we investigate the output optical phase when the amplitude is modulated, which provides us valuable information when both amplitude and phase are to be controlled. Our demonstration not only paves the road to applications such as quantum information processing that requires high extinction ratio AMs but also significantly alleviates the tight fabrication tolerance needed for large-scale integrated photonics.

Conversion of asynchronous 10 Gbit/s Ethernet NRZ frame into a synchronous RZ frame and multiplexing to 170 Gbit/s

DEFF Research Database (Denmark)

Laguardia Areal, Janaina; Hu, Hao; Palushani, Evarist

2010-01-01

This paper presents an optical circuit for frame synchronization and pulse compression of 10G Ethernet frames with 12000 bits and multiplexing to a 170 Gbit/s optical time division multiplexed data stream.......This paper presents an optical circuit for frame synchronization and pulse compression of 10G Ethernet frames with 12000 bits and multiplexing to a 170 Gbit/s optical time division multiplexed data stream....

High-speed elevators controlled by inverters

Energy Technology Data Exchange (ETDEWEB)

Sakai, Yoshio; Takahashi, Hideaki; Nakamura, Kiyoshi; Kinoshita, Hiroshi

1988-10-25

The super-high-speed elevator with superiority to 300m/min of speed, requires both the large capacity power and wide range speed controls. Therefore, in order to materialize the smooth and quiet operation characteristics, by applying the inverter control, the low torque ripple control in the low frequency range and high frequency large capacity inverting for lowering the motor in noise are necessary with their being assured of reliability. To satisfy the above necessary items, together with the development of a sine wave pulse width and frequency modulation (PWM/PFM) control system, to more precisely enable the sine wave electric current control, and 3kHz switching power converter, using a 800A power transistor module, a supervoltage control circuit under the extraordinary condition was designed. As a result of commercializing a 360m/min super-high speed inverter elevator, the power source unit, due to the effect of high power factor, could be reduced by 30% in capacity and also the higher harmonic wave including ratio could be considerably lowered to the inferiority to 5%. 2 references, 7 figures, 1 table.

High - speed steel for precise cased tools

International Nuclear Information System (INIS)

Karwiarz, J.; Mazur, A.

2001-01-01

The test results of high-vanadium high - speed steel (SWV9) for precise casted tools are presented. The face -milling cutters of NFCa80A type have been tested in industrial operating conditions. An average life - time of SWV9 steel tools was 3-10 times longer compare to the conventional high - speed milling cutters. Metallography of SWB9 precise casted steel revealed beneficial for tool properties distribution of primary vanadium carbides in the steel matrix. Presented results should be a good argument for wide application of high - vanadium high - speed steel for precise casted tools. (author)

Rapid Development of System-on-Chip (SoC for Network-Enabled Visible Light Communications

Directory of Open Access Journals (Sweden)

Trio Adiono

2018-03-01

Full Text Available Visible Light Communication (VLC is an emerging optical communication technology with rapid development nowadays. VLC is considered as a compliment and successor of radio-frequency (RF wireless communication. There are various typical implementations of VLC in which one of them is for exchanging data TCP/IP packets, thus the user can browse the internet as in established Wireless fidelity (Wi-Fi technology. Briefly, we can call it by Light fidelity (Li-Fi. This paper described the design and implementation of System-on-Chip (SoC subsystem for Li-Fi application where the implemented SoC consists of hardware (H/W and software (S/W. In the H/W aspect, Physical Layer (PHY is made by using UART communication with Ethernet connection to communicate with Host/Device personal-computer (PC. In the S/W aspect, Xillinux operating system (OS is used. The H/W- as well as S/W-SoC, are realized in FPGA Zybo Zynq-7000 EPP development board. The functional test result shows (without optical channel or Zybo-to-Zybo only that the implemented SoC is working as expected. It is able to exchange TCP/IP packets between two PCs. Moreover, Ethernet connection has bandwidth up to 83.6 Mbps and PHY layer baud rate has bandwidth up to 921600 bps.

Mechanisms and FEM Simulation of Chip Formation in Orthogonal Cutting In-Situ TiB₂/7050Al MMC.

Science.gov (United States)

Xiong, Yifeng; Wang, Wenhu; Jiang, Ruisong; Lin, Kunyang; Shao, Mingwei

2018-04-15

The in-situ TiB₂/7050Al composite is a new kind of Al-based metal matrix composite (MMC) with super properties, such as low density, improved strength, and wear resistance. This paper, for a deep insight into its cutting performance, involves a study of the chip formation process and finite element simulation during orthogonal cutting in-situ TiB₂/7050Al MMC. With chips, material properties, cutting forces, and tool geometry parameters, the Johnson-Cook (J-C) constitutive equation of in-situ TiB₂/7050Al composite was established. Then, the cutting simulation model was established by applying the Abaqus-Explicit method, and the serrated chip, shear plane, strain rate, and temperature were analyzed. The experimental and simulation results showed that the obtained material's constitutive equation was of high reliability, and the saw-tooth chips occurred commonly under either low or high cutting speed and small or large feed rate. From result analysis, it was found that the mechanisms of chip formation included plastic deformation, adiabatic shear, shearing slip, and crack extension. In addition, it was found that the existence of small, hard particles reduced the ductility of the MMC and resulted in segmental chips.

High speed global shutter image sensors for professional applications

Science.gov (United States)

Wu, Xu; Meynants, Guy

2015-04-01

Global shutter imagers expand the use to miscellaneous applications, such as machine vision, 3D imaging, medical imaging, space etc. to eliminate motion artifacts in rolling shutter imagers. A low noise global shutter pixel requires more than one non-light sensitive memory to reduce the read noise. But larger memory area reduces the fill-factor of the pixels. Modern micro-lenses technology can compensate this fill-factor loss. Backside illumination (BSI) is another popular technique to improve the pixel fill-factor. But some pixel architecture may not reach sufficient shutter efficiency with backside illumination. Non-light sensitive memory elements make the fabrication with BSI possible. Machine vision like fast inspection system, medical imaging like 3D medical or scientific applications always ask for high frame rate global shutter image sensors. Thanks to the CMOS technology, fast Analog-to-digital converters (ADCs) can be integrated on chip. Dual correlated double sampling (CDS) on chip ADC with high interface digital data rate reduces the read noise and makes more on-chip operation control. As a result, a global shutter imager with digital interface is a very popular solution for applications with high performance and high frame rate requirements. In this paper we will review the global shutter architectures developed in CMOSIS, discuss their optimization process and compare their performances after fabrication.

Adventures in the evolution of a high-bandwidth network for central servers

International Nuclear Information System (INIS)

Swartz, K.L.; Cottrell, L.; Dart, M.

1994-08-01

In a small network, clients and servers may all be connected to a single Ethernet without significant performance concerns. As the number of clients on a network grows, the necessity of splitting the network into multiple sub-networks, each with a manageable number of clients, becomes clear. Less obvious is what to do with the servers. Group file servers on subnets and multihomed servers offer only partial solutions -- many other types of servers do not lend themselves to a decentralized model, and tend to collect on another, well-connected but overloaded Ethernet. The higher speed of FDDI seems to offer an easy solution, but in practice both expense and interoperability problems render FDDI a poor choice. Ethernet switches appear to permit cheaper and more reliable networking to the servers while providing an aggregate network bandwidth greater than a simple Ethernet. This paper studies the evolution of the server networks at SLAC. Difficulties encountered in the deployment of FDDI are described, as are the tools and techniques used to characterize the traffic patterns on the server network. Performance of Ethernet, FDDI, and switched Ethernet networks is analyzed, as are reliability and maintainability issues for these alternatives. The motivations for re-designing the SLAC general server network to use a switched Ethernet instead of FDDI are described, as are the reasons for choosing FDDI for the farm and firewall networks at SLAC. Guidelines are developed which may help in making this choice for other networks

Design and FPGA-implementation of multilayer neural networks with on-chip learning

International Nuclear Information System (INIS)

Haggag, S.S.M.Y

2008-01-01

Artificial Neural Networks (ANN) is used in many applications in the industry because of their parallel structure, high speed, and their ability to give easy solution to complicated problems. For example identifying the orange and apple in the sorting machine with neural network is easier than using image processing techniques to do the same thing. There are different software for designing, training, and testing the ANN, but in order to use the ANN in the industry, it should be implemented on hardware outside the computer. Neural networks are artificial systems inspired on the brain's cognitive behavior, which can learn tasks with some degree of complexity, such as signal processing, diagnosis, robotics, image processing, and pattern recognition. Many applications demand a high computing power and the traditional software implementation are not sufficient.This thesis presents design and FPGA implementation of Multilayer Neural Networks with On-chip learning in re-configurable hardware. Hardware implementation of neural network algorithm is very interesting due their high performance and they can easily be made parallel. The architecture proposed herein takes advantage of distinct data paths for the forward and backward propagation stages and a pipelined adaptation of the on- line backpropagation algorithm to significantly improve the performance of the learning phase. The architecture is easily scalable and able to cope with arbitrary network sizes with the same hardware. The implementation is targeted diagnosis of the Research Reactor accidents to avoid the risk of occurrence of a nuclear accident. The proposed designed circuits are implemented using Xilinx FPGA Chip XC40150xv and occupied 73% of Chip CLBs. It achieved 10.8 μs to take decision in the forward propagation compared with current software implemented of RPS which take 24 ms. The results show that the proposed architecture leads to significant speed up comparing to high end software solutions. On-chip

High-speed ground transportation development outside United States

Energy Technology Data Exchange (ETDEWEB)

Eastham, T.R. [Queen`s Univ., Kingston, Ontario (United Kingdom)

1995-09-01

This paper surveys the state of high-speed (in excess of 200 km/h) ground-transportation developments outside the United States. Both high-speed rail and Maglev systems are covered. Many vehicle systems capable of providing intercity service in the speed range 200--500 km/h are or will soon be available. The current state of various technologies, their implementation, and the near-term plans of countries that are most active in high-speed ground transportation development are reported.

Aerodynamic design on high-speed trains

Science.gov (United States)

Ding, San-San; Li, Qiang; Tian, Ai-Qin; Du, Jian; Liu, Jia-Li

2016-04-01

Compared with the traditional train, the operational speed of the high-speed train has largely improved, and the dynamic environment of the train has changed from one of mechanical domination to one of aerodynamic domination. The aerodynamic problem has become the key technological challenge of high-speed trains and significantly affects the economy, environment, safety, and comfort. In this paper, the relationships among the aerodynamic design principle, aerodynamic performance indexes, and design variables are first studied, and the research methods of train aerodynamics are proposed, including numerical simulation, a reduced-scale test, and a full-scale test. Technological schemes of train aerodynamics involve the optimization design of the streamlined head and the smooth design of the body surface. Optimization design of the streamlined head includes conception design, project design, numerical simulation, and a reduced-scale test. Smooth design of the body surface is mainly used for the key parts, such as electric-current collecting system, wheel truck compartment, and windshield. The aerodynamic design method established in this paper has been successfully applied to various high-speed trains (CRH380A, CRH380AM, CRH6, CRH2G, and the Standard electric multiple unit (EMU)) that have met expected design objectives. The research results can provide an effective guideline for the aerodynamic design of high-speed trains.

NanoTopoChip: High-throughput nanotopographical cell instruction.

Science.gov (United States)

Hulshof, Frits F B; Zhao, Yiping; Vasilevich, Aliaksei; Beijer, Nick R M; de Boer, Meint; Papenburg, Bernke J; van Blitterswijk, Clemens; Stamatialis, Dimitrios; de Boer, Jan

2017-10-15

Surface topography is able to influence cell phenotype in numerous ways and offers opportunities to manipulate cells and tissues. In this work, we develop the Nano-TopoChip and study the cell instructive effects of nanoscale topographies. A combination of deep UV projection lithography and conventional lithography was used to fabricate a library of more than 1200 different defined nanotopographies. To illustrate the cell instructive effects of nanotopography, actin-RFP labeled U2OS osteosarcoma cells were cultured and imaged on the Nano-TopoChip. Automated image analysis shows that of many cell morphological parameters, cell spreading, cell orientation and actin morphology are mostly affected by the nanotopographies. Additionally, by using modeling, the changes of cell morphological parameters could by predicted by several feature shape parameters such as lateral size and spacing. This work overcomes the technological challenges of fabricating high quality defined nanoscale features on unprecedented large surface areas of a material relevant for tissue culture such as PS and the screening system is able to infer nanotopography - cell morphological parameter relationships. Our screening platform provides opportunities to identify and study the effect of nanotopography with beneficial properties for the culture of various cell types. The nanotopography of biomaterial surfaces can be modified to influence adhering cells with the aim to improve the performance of medical implants and tissue culture substrates. However, the necessary knowledge of the underlying mechanisms remains incomplete. One reason for this is the limited availability of high-resolution nanotopographies on relevant biomaterials, suitable to conduct systematic biological studies. The present study shows the fabrication of a library of nano-sized surface topographies with high fidelity. The potential of this library, called the 'NanoTopoChip' is shown in a proof of principle HTS study which

High Voltage Dielectrophoretic and Magnetophoretic Hybrid Integrated Circuit / Microfluidic Chip

Science.gov (United States)

Issadore, David; Franke, Thomas; Brown, Keith A.; Hunt, Thomas P.; Westervelt, Robert M.

2010-01-01

A hybrid integrated circuit (IC) / microfluidic chip is presented that independently and simultaneously traps and moves microscopic objects suspended in fluid using both electric and magnetic fields. This hybrid chip controls the location of dielectric objects, such as living cells and drops of fluid, on a 60 × 61 array of pixels that are 30 × 38 μm2 in size, each of which can be individually addressed with a 50 V peak-to-peak, DC to 10 MHz radio frequency voltage. These high voltage pixels produce electric fields above the chip’s surface with a magnitude , resulting in strong dielectrophoresis (DEP) forces . Underneath the array of DEP pixels there is a magnetic matrix that consists of two perpendicular sets of 60 metal wires running across the chip. Each wire can be sourced with 120 mA to trap and move magnetically susceptible objects using magnetophoresis (MP). The DEP pixel array and magnetic matrix can be used simultaneously to apply forces to microscopic objects, such as living cells or lipid vesicles, that are tagged with magnetic nanoparticles. The capabilities of the hybrid IC / microfluidic chip demonstrated in this paper provide important building blocks for a platform for biological and chemical applications. PMID:20625468

A 16X16 Discrete Cosine Transform Chip

Science.gov (United States)

Sun, M. T.; Chen, T. C.; Gottlieb, A.; Wu, L.; Liou, M. L.

1987-10-01

Among various transform coding techniques for image compression the Discrete Cosine Transform (DCT) is considered to be the most effective method and has been widely used in the laboratory as well as in the market, place. DCT is computationally intensive. For video application at 14.3 MHz sample rate, a direct implementation of a 16x16 DCT requires a throughput, rate of approximately half a billion multiplications per second. In order to reduce the cost of hardware implementation, a single chip DCT implementation is highly desirable. In this paper, the implementation of a 16x16 DCT chip using a concurrent architecture will be presented. The chip is designed for real-time processing of 14.3 MHz sampled video data. It uses row-column decomposition to implement the two-dimensional transform. Distributed arithmetic combined with hit-serial and hit-parallel structures is used to implement the required vector inner products concurrently. Several schemes are utilized to reduce the size of required memory. The resultant circuit only uses memory, shift registers, and adders. No multipliers are required. It achieves high speed performance with a very regular and efficient integrated circuit realization. The chip accepts 0-bit input and produces 14-bit DCT coefficients. 12 bits are maintained after the first one-dimensional transform. The circuit has been laid out using a 2-μm CMOS technology with a symbolic design tool MULGA. The core contains approximately 73,000 transistors in an area of 7.2 x 7.0

Cheetah: A high frame rate, high resolution SWIR image camera

Science.gov (United States)

Neys, Joel; Bentell, Jonas; O'Grady, Matt; Vermeiren, Jan; Colin, Thierry; Hooylaerts, Peter; Grietens, Bob

2008-10-01

A high resolution, high frame rate InGaAs based image sensor and associated camera has been developed. The sensor and the camera are capable of recording and delivering more than 1700 full 640x512pixel frames per second. The FPA utilizes a low lag CTIA current integrator in each pixel, enabling integration times shorter than one microsecond. On-chip logics allows for four different sub windows to be read out simultaneously at even higher rates. The spectral sensitivity of the FPA is situated in the SWIR range [0.9-1.7 μm] and can be further extended into the Visible and NIR range. The Cheetah camera has max 16 GB of on-board memory to store the acquired images and transfer the data over a Gigabit Ethernet connection to the PC. The camera is also equipped with a full CameralinkTM interface to directly stream the data to a frame grabber or dedicated image processing unit. The Cheetah camera is completely under software control.

Analytical thermal modelling of multilayered active embedded chips into high density electronic board

Directory of Open Access Journals (Sweden)

Monier-Vinard Eric

2013-01-01

Full Text Available The recent Printed Wiring Board embedding technology is an attractive packaging alternative that allows a very high degree of miniaturization by stacking multiple layers of embedded chips. This disruptive technology will further increase the thermal management challenges by concentrating heat dissipation at the heart of the organic substrate structure. In order to allow the electronic designer to early analyze the limits of the power dissipation, depending on the embedded chip location inside the board, as well as the thermal interactions with other buried chips or surface mounted electronic components, an analytical thermal modelling approach was established. The presented work describes the comparison of the analytical model results with the numerical models of various embedded chips configurations. The thermal behaviour predictions of the analytical model, found to be within ±10% of relative error, demonstrate its relevance for modelling high density electronic board. Besides the approach promotes a practical solution to study the potential gain to conduct a part of heat flow from the components towards a set of localized cooled board pads.

An Automatic Baseline Regulation in a Highly Integrated Receiver Chip for JUNO

Science.gov (United States)

Muralidharan, P.; Zambanini, A.; Karagounis, M.; Grewing, C.; Liebau, D.; Nielinger, D.; Robens, M.; Kruth, A.; Peters, C.; Parkalian, N.; Yegin, U.; van Waasen, S.

2017-09-01

This paper describes the data processing unit and an automatic baseline regulation of a highly integrated readout chip (Vulcan) for JUNO. The chip collects data continuously at 1 Gsamples/sec. The Primary data processing which is performed in the integrated circuit can aid to reduce the memory and data processing efforts in the subsequent stages. In addition, a baseline regulator compensating a shift in the baseline is described.

Optimizing 10-Gigabit Ethernet for Networks of Workstations, Clusters, and Grids: A Case Study

Energy Technology Data Exchange (ETDEWEB)

Feng, Wu-chun

2003-10-13

This paper presents a case study of the 10-Gigabit Ethernet (10GbE) adapter from Intel(reg sign). Specifically, with appropriate optimizations to the configurations of the 10GbE adapter and TCP, we demonstrate that the 10GbE adapter can perform well in local-area, storage-area, system-area, and wide-area networks. For local-area, storage-area, and system-area networks in support of networks of workstations, network-attached storage, and clusters, respectively, we can achieve over 7-Gb/s end-to-end throughput and 12-{micro}s end-to-end latency between applications running on Linux-based PCs. For the wide-area network in support of grids, we broke the recently-set Internet2 Land Speed Record by 2.5 times by sustaining an end-to-end TCP/IP throughput of 2.38 Gb/s between Sunnyvale, California and Geneva, Switzerland (i.e., 10,037 kilometers) to move over a terabyte of data in less than an hour. Thus, the above results indicate that 10GbE may be a cost-effective solution across a multitude of computing environments.

IP, ethernet and MPLS networks resource and fault management

CERN Document Server

Perez, André

2013-01-01

This book summarizes the key Quality of Service technologies deployed in telecommunications networks: Ethernet, IP, and MPLS. The QoS of the network is made up of two parts: fault and resource management. Network operation quality is among the functions to be fulfilled in order to offer QoS to the end user. It is characterized by four parameters: packet loss, delay, jitter or the variation of delay over time, and availability. Resource management employs mechanisms that enable the first three parameters to be guaranteed or optimized. Fault management aims to ensure continuity of service.

Ethernet based data logger for gaseous detectors

Science.gov (United States)

Swain, S.; Sahu, P. K.; Sahu, S. K.

2018-05-01

A data logger is designed to monitor and record ambient parameters such as temperature, pressure and relative humidity along with gas flow rate as a function of time. These parameters are required for understanding the characteristics of gas-filled detectors such as Gas Electron Multiplier (GEM) and Multi-Wire Proportional Counter (MWPC). The data logger has different microcontrollers and has been interfaced to an ethernet port with a local LCD unit for displaying all measured parameters. In this article, the explanation of the data logger design, hardware, and software description of the master microcontroller and the DAQ system along with LabVIEW interface client program have been presented. We have implemented this device with GEM detector and displayed few preliminary results as a function of above parameters.

Full-frame, high-speed 3D shape and deformation measurements using stereo-digital image correlation and a single color high-speed camera

Science.gov (United States)

Yu, Liping; Pan, Bing

2017-08-01

Full-frame, high-speed 3D shape and deformation measurement using stereo-digital image correlation (stereo-DIC) technique and a single high-speed color camera is proposed. With the aid of a skillfully designed pseudo stereo-imaging apparatus, color images of a test object surface, composed of blue and red channel images from two different optical paths, are recorded by a high-speed color CMOS camera. The recorded color images can be separated into red and blue channel sub-images using a simple but effective color crosstalk correction method. These separated blue and red channel sub-images are processed by regular stereo-DIC method to retrieve full-field 3D shape and deformation on the test object surface. Compared with existing two-camera high-speed stereo-DIC or four-mirror-adapter-assisted singe-camera high-speed stereo-DIC, the proposed single-camera high-speed stereo-DIC technique offers prominent advantages of full-frame measurements using a single high-speed camera but without sacrificing its spatial resolution. Two real experiments, including shape measurement of a curved surface and vibration measurement of a Chinese double-side drum, demonstrated the effectiveness and accuracy of the proposed technique.

High speed VLSI neural network for high energy physics

NARCIS (Netherlands)

Masa, P.; Masa, P.; Hoen, K.; Hoen, Klaas; Wallinga, Hans

1994-01-01

A CMOS neural network IC is discussed which was designed for very high speed applications. The parallel architecture, analog computing and digital weight storage provides unprecedented computing speed combined with ease of use. The circuit classifies up to 70 dimensional vectors within 20

A 6.25 Gb/s equalizer in 0.18 μm CMOS technology for high-speed SerDes

International Nuclear Information System (INIS)

Zhang Mingke; Hu Qingsheng

2013-01-01

This paper presents a 0.18 μm CMOS 6.25 Gb/s equalizer for high speed backplane communication. The proposed equalizer is a combined one consisting of a one-tap feed-forward equalizer (FFE) and a two-tap half-rate decision feedback equalizer (DFE) in order to cancel both pre-cursor and post-cursor ISI. By employing an active-inductive peaking circuit for the delay line, the bandwidth of the FFE is increased and the area cost is minimized. CML-based circuits such as DFFs, summers and multiplexes all help to improve the speed of DFEs. Measurement results illustrate that the equalizer operates well when equalizing 6.25 Gb/s data is passed over a 30-inch channel with a loss of 22 dB and consumes 55.8 mW with the supply voltage of 1.8 V. The overall chip area including pads is 0.3 × 0.5 mm 2 . (semiconductor integrated circuits)

Mixed-signal early vision chip with embedded image and programming memories and digital I/O

Science.gov (United States)

Linan-Cembrano, Gustavo; Rodriguez-Vazquez, Angel; Dominguez-Castro, Rafael; Espejo, Servando

2003-04-01

From a system level perspective, this paper presents a 128x128 flexible and reconfigurable Focal-Plane Analog Programmable Array Processor, which has been designed as a single chip in a 0.35μm standard digital 1P-5M CMOS technology. The core processing array has been designed to achieve high-speed of operation and large-enough accuracy (~7bit) with low power consumption. The chip includes on-chip program memory to allow for the execution of complex, sequential and/or bifurcation flow image processing algorithms. It also includes the structures and circuits needed to guarantee its embedding into conventional digital hosting systems: external data interchange and control are completely digital. The chip contains close to four million transistors, 90% of them working in analog mode. The chip features up to 330GOPs (Giga Operations per second), and uses the power supply (180GOP/Joule) and the silicon area (3.8 GOPS/mm2) efficiently, as it is able to maintain VGA processing throughputs of 100Frames/s with about 15 basic image processing tasks on each frame.

Development of a Metal Cutting Tool Fase in Order to Create the Conditions of Ringed Chips Wrapping

Science.gov (United States)

Korchuganova, M.; Syrbakov, A.; Chernysheva, T.; Ivanov, G.; Korchuganov, M.

2016-08-01

When processing ductile metals with high cutting speed, there is a need to take additional measures for a comfortable and safe formation and removal of chips. In the conditions of large-scale manufacture, it is recommended to produce flow chips in the form of short fragments, while in the conditions of small-lot and single-piece manufacture, it is reasonable to wrap the chips spirally with a rather small turn radius. Such way of chips formation reduces the time of its removal from the working area as well as facilitates its transportation and processing. In order to solve the problem of chip wrapping and breakage, almost all modern manufacturers of tools with replaceable many-sided plates (RMSP) followed the way of complication of tool faces and determination of the areas of effective chip breaking. On the one hand, the suggested solution turns out to be effective; however, as showed the analysis of recommended cutting modes for complex forms of RMSP made by leading manufacturers, they all correspond to the definite cross section of the cut-layer S/t=0.1.

ASIC Wafer Test System for the ATLAS Semiconductor Tracker Front-End Chip

International Nuclear Information System (INIS)

Anghinolfi, F.; Bialas, W.; Busek, N.; Ciocio, A.; Cosgrove, D.; Fadeyev, V.; Flacco, C.; Gilchriese, M.; Grillo, A.A.; Haber, C.; Kaplon, J.; Lacasta, C.; Murray, W.; Niggli, H.; Pritchard, T.; Rosenbaum, F.; Spieler, H.; Stezelberger, T.; Vu, C.; Wilder, M.; Yaver, H.; Zetti, F.

2002-01-01

An ASIC wafer test system has been developed to provide comprehensive production screening of the ATLAS Semiconductor Tracker front-end chip (ABCD3T). The ABCD3T[1] features a 128-channel analog front-end, a digital pipeline, and communication circuitry, clocked at 40 MHz, which is the bunch crossing frequency at the LHC (Large Hadron Collider). The tester measures values and tolerance ranges of all critical IC parameters, including DC parameters, electronic noise, time resolution, clock levels and clock timing. The tester is controlled by an FPGA (ORCA3T) programmed to issue the input commands to the IC and to interpret the output data. This allows the high-speed wafer-level IC testing necessary to meet the production schedule. To characterize signal amplitudes and phase margins, the tester utilizes pin-driver, delay, and DAC chips, which control the amplitudes and delays of signals sent to the IC under test. Output signals from the IC under test go through window comparator chips to measure their levels. A probe card has been designed specifically to reduce pick-up noise that can affect the measurements. The system can operate at frequencies up to 100 MHz to study the speed limits of the digital circuitry before and after radiation damage. Testing requirements and design solutions are presented

Replacing the Ethernet access mechanism with the real-time access mechanism of Twentenet

NARCIS (Netherlands)

Pras, Aiko

1989-01-01

The way in which a Local Area Network access mechanism (Medium Access Control protocol) designed for a specific type of physical service can be used on top of another type of physical service is discussed using a particular example. In the example, an Ethernet physical layer is used to provide

Reliance communications' flag telecom to provide ethernet link between CERN and TIFR

CERN Multimedia

2007-01-01

"Flag Telecom Group Limited (Flag), the undersea cable network arm of Anil Ambani-le Reliance Communications, has announced a landmark deal with CERn (Conseil Européen pour la Recheche Nucléaire), the European organisation for nuclear research based in Geneva, Switzerland and the Tata institute of Fundamental Research (TIFR) in Mumbai to provide gigabit Ethernet connectivity between the two." (1 page)

High-speed and high-fidelity system and method for collecting network traffic

Science.gov (United States)

Weigle, Eric H [Los Alamos, NM

2010-08-24

A system is provided for the high-speed and high-fidelity collection of network traffic. The system can collect traffic at gigabit-per-second (Gbps) speeds, scale to terabit-per-second (Tbps) speeds, and support additional functions such as real-time network intrusion detection. The present system uses a dedicated operating system for traffic collection to maximize efficiency, scalability, and performance. A scalable infrastructure and apparatus for the present system is provided by splitting the work performed on one host onto multiple hosts. The present system simultaneously addresses the issues of scalability, performance, cost, and adaptability with respect to network monitoring, collection, and other network tasks. In addition to high-speed and high-fidelity network collection, the present system provides a flexible infrastructure to perform virtually any function at high speeds such as real-time network intrusion detection and wide-area network emulation for research purposes.

Gate Drive For High Speed, High Power IGBTs

Energy Technology Data Exchange (ETDEWEB)

Nguyen, M.N.; Cassel, R.L.; de Lamare, J.E.; Pappas, G.C.; /SLAC

2007-06-18

A new gate drive for high-voltage, high-power IGBTs has been developed for the SLAC NLC (Next Linear Collider) Solid State Induction Modulator. This paper describes the design and implementation of a driver that allows an IGBT module rated at 800A/3300V to switch up to 3000A at 2200V in 3{micro}S with a rate of current rise of more than 10000A/{micro}S, while still being short circuit protected. Issues regarding fast turn on, high de-saturation voltage detection, and low short circuit peak current will be presented. A novel approach is also used to counter the effect of unequal current sharing between parallel chips inside most high-power IGBT modules. It effectively reduces the collector-emitter peak current, and thus protects the IGBT from being destroyed during soft short circuit conditions at high di/dt.

Gate Drive For High Speed, High Power IGBTs

International Nuclear Information System (INIS)

Nguyen, M.N.; Cassel, R.L.; de Lamare, J.E.; Pappas, G.C.; SLAC

2007-01-01

A new gate drive for high-voltage, high-power IGBTs has been developed for the SLAC NLC (Next Linear Collider) Solid State Induction Modulator. This paper describes the design and implementation of a driver that allows an IGBT module rated at 800A/3300V to switch up to 3000A at 2200V in 3(micro)S with a rate of current rise of more than 10000A/(micro)S, while still being short circuit protected. Issues regarding fast turn on, high de-saturation voltage detection, and low short circuit peak current will be presented. A novel approach is also used to counter the effect of unequal current sharing between parallel chips inside most high-power IGBT modules. It effectively reduces the collector-emitter peak current, and thus protects the IGBT from being destroyed during soft short circuit conditions at high di/dt

High-speed charge-to-time converter ASIC for the Super-Kamiokande detector

Energy Technology Data Exchange (ETDEWEB)

Nishino, H., E-mail: nishino@post.kek.j [Institute for Cosmic Ray Research, University of Tokyo, Chiba 277-8582 (Japan); Awai, K.; Hayato, Y.; Nakayama, S.; Okumura, K.; Shiozawa, M.; Takeda, A. [Institute for Cosmic Ray Research, University of Tokyo, Chiba 277-8582 (Japan); Ishikawa, K.; Minegishi, A. [Iwatsu Test Instruments Corporation, Tokyo 168-8511 (Japan); Arai, Y. [The Institute of Particle and Nuclear Studies, KEK, Ibaraki 305-0801 (Japan)

2009-11-11

A new application-specific integrated circuit (ASIC), the high-speed charge-to-time converter (QTC) IWATSU CLC101, provides three channels, each consisting of preamplifier, discriminator, low-pass filter, and charge integration circuitry, optimized for the waveform of a photomultiplier tube (PMT). This ASIC detects PMT signals using individual built-in discriminators and drives output timing signals whose width represents the integrated charge of the PMT signal. Combined with external input circuits composed of passive elements, the QTC provides full analog signal processing for the detector's PMTs, ready for further processing by time-to-digital converters (TDCs). High-rate (>1MHz) signal processing is achieved by short-charge-conversion-time and baseline-restoration circuits. Wide-range charge measurements are enabled by offering three gain ranges while maintaining a short cycle time. QTC chip test results show good analog performance, with efficient detection for a single photoelectron signal, four orders of magnitude dynamic range (0.3mVapprox3V; 0.2approx2500pC), 1% charge linearity, 0.2 pC charge resolution, and 0.1 ns timing resolution. Test results on ambient temperature dependence, channel isolation, and rate dependence also meet specifications.

High-speed charge-to-time converter ASIC for the Super-Kamiokande detector

International Nuclear Information System (INIS)

Nishino, H.; Awai, K.; Hayato, Y.; Nakayama, S.; Okumura, K.; Shiozawa, M.; Takeda, A.; Ishikawa, K.; Minegishi, A.; Arai, Y.

2009-01-01

A new application-specific integrated circuit (ASIC), the high-speed charge-to-time converter (QTC) IWATSU CLC101, provides three channels, each consisting of preamplifier, discriminator, low-pass filter, and charge integration circuitry, optimized for the waveform of a photomultiplier tube (PMT). This ASIC detects PMT signals using individual built-in discriminators and drives output timing signals whose width represents the integrated charge of the PMT signal. Combined with external input circuits composed of passive elements, the QTC provides full analog signal processing for the detector's PMTs, ready for further processing by time-to-digital converters (TDCs). High-rate (>1MHz) signal processing is achieved by short-charge-conversion-time and baseline-restoration circuits. Wide-range charge measurements are enabled by offering three gain ranges while maintaining a short cycle time. QTC chip test results show good analog performance, with efficient detection for a single photoelectron signal, four orders of magnitude dynamic range (0.3mV∼3V; 0.2∼2500pC), 1% charge linearity, 0.2 pC charge resolution, and 0.1 ns timing resolution. Test results on ambient temperature dependence, channel isolation, and rate dependence also meet specifications.

Flip chip assembly of thinned chips for hybrid pixel detector applications

International Nuclear Information System (INIS)

Fritzsch, T; Zoschke, K; Rothermund, M; Oppermann, H; Woehrmann, M; Ehrmann, O; Lang, K D; Huegging, F

2014-01-01

There is a steady trend to ultra-thin microelectronic devices. Especially for future particle detector systems a reduced readout chip thickness is required to limit the loss of tracking precision due to scattering. The reduction of silicon thickness is performed at wafer level in a two-step thinning process. To minimize the risk of wafer breakage the thinned wafer needs to be handled by a carrier during the whole process chain of wafer bumping. Another key process is the flip chip assembly of thinned readout chips onto thin sensor tiles. Besides the prevention of silicon breakage the minimization of chip warpage is one additional task for a high yield and reliable flip chip process. A new technology using glass carrier wafer will be described in detail. The main advantage of this technology is the combination of a carrier support during wafer processing and the chip support during flip chip assembly. For that a glass wafer is glue-bonded onto the backside of the thinned readout chip wafer. After the bump deposition process the glass-readout chip stack is diced in one step. Finally the glass carrier chip is released by laser illumination after flip chip assembly of the readout chip onto sensor tile. The results of the flip chip assembly process development for the ATLAS IBL upgrade are described more in detail. The new ATLAS FEI4B chip with a size of 20 × 19 mm 2 is flip chip bonded with a thickness of only 150 μm, but the capability of this technology has been demonstrated on hybrid modules with a reduced readout chip thickness of down to 50 μm which is a major step for ultra-thin electronic systems

Interfacing Lab-on-a-Chip Embryo Technology with High-Definition Imaging Cytometry.

Science.gov (United States)

Zhu, Feng; Hall, Christopher J; Crosier, Philip S; Wlodkowic, Donald

2015-08-01

To spearhead deployment of zebrafish embryo biotests in large-scale drug discovery studies, automated platforms are needed to integrate embryo in-test positioning and immobilization (suitable for high-content imaging) with fluidic modules for continuous drug and medium delivery under microperfusion to developing embryos. In this work, we present an innovative design of a high-throughput three-dimensional (3D) microfluidic chip-based device for automated immobilization and culture and time-lapse imaging of developing zebrafish embryos under continuous microperfusion. The 3D Lab-on-a-Chip array was fabricated in poly(methyl methacrylate) (PMMA) transparent thermoplastic using infrared laser micromachining, while the off-chip interfaces were fabricated using additive manufacturing processes (fused deposition modelling and stereolithography). The system's design facilitated rapid loading and immobilization of a large number of embryos in predefined clusters of traps during continuous microperfusion of drugs/toxins. It was conceptually designed to seamlessly interface with both upright and inverted fluorescent imaging systems and also to directly interface with conventional microtiter plate readers that accept 96-well plates. Compared with the conventional Petri dish assays, the chip-based bioassay was much more convenient and efficient as only small amounts of drug solutions were required for the whole perfusion system running continuously over 72 h. Embryos were spatially separated in the traps that assisted tracing single embryos, preventing interembryo contamination and improving imaging accessibility.

Flip chip assembly of thinned chips for hybrid pixel detector applications

CERN Document Server

Fritzsch, T; Woehrmann, M; Rothermund, M; Huegging, F; Ehrmann, O; Oppermann, H; Lang, K.D

2014-01-01

There is a steady trend to ultra-thin microelectronic devices. Especially for future particle detector systems a reduced readout chip thickness is required to limit the loss of tracking precision due to scattering. The reduction of silicon thickness is performed at wafer level in a two-step thinning process. To minimize the risk of wafer breakage the thinned wafer needs to be handled by a carrier during the whole process chain of wafer bumping. Another key process is the flip chip assembly of thinned readout chips onto thin sensor tiles. Besides the prevention of silicon breakage the minimization of chip warpage is one additional task for a high yield and reliable flip chip process. A new technology using glass carrier wafer will be described in detail. The main advantage of this technology is the combination of a carrier support during wafer processing and the chip support during flip chip assembly. For that a glass wafer is glue-bonded onto the backside of the thinned readout chip wafer. After the bump depo...

A new circuit for at-speed scan SoC testing

International Nuclear Information System (INIS)

Lin Wei; Shi Wenlong

2013-01-01

It is very important to detect transition-delay faults and stuck-at faults in system on chip (SoC) under 90 nm processing technology, and the transition-delay faults can only be detected by using an at-speed testing method. In this paper, an on-chip clock (OCC) controller with a bypass function based on an internal phase-locked loop is designed to test faults in SoC. Furthermore, a clock chain logic which can eliminate the metastable state is realized to generate an enable signal for the OCC controller, and then, the test pattern is generated by automatic test pattern generation (ATPG) tools. Next, the scan test pattern is simulated by using the Synopsys tool and the correctness of the design is verified. The result shows that the design of an at-speed scan test in this paper is highly efficient for detecting timing-related defects. Finally, the 89.29% transition-delay fault coverage and the 94.50% stuck-at fault coverage are achieved, and it is successfully applied to an integrated circuit design. (semiconductor integrated circuits)

Potential scenarios of concern for high speed rail operations

Science.gov (United States)

2011-03-16

Currently, multiple operating authorities are proposing the : introduction of high-speed rail service in the United States. : While high-speed rail service shares a number of basic : principles with conventional-speed rail service, the operational : ...

Effect of osmotic dehydration and vacuum-frying parameters to produce high-quality mango chips.

Science.gov (United States)

Nunes, Yolanda; Moreira, Rosana G

2009-09-01

Mango (Mangifera indica L.) is a fruit rich in flavor and nutritional values, which is an excellent candidate for producing chips. The objective of this study was to develop high-quality mango chips using vacuum frying. Mango ("Tommy Atkins") slices were pretreated with different maltodextrin concentrations (40, 50, and 65, w/v), osmotic dehydration times (45, 60, and 70 min), and solution temperatures (22 and 40 degrees C). Pretreated slices were vacuum fried at 120, 130, and 138 degrees C and product quality attributes (oil content, texture, color, carotenoid content) determined. The effect of frying temperatures at optimum osmotic dehydration times (65 [w/v] at 40 degrees C) was assessed. All samples were acceptable (scores > 5) to consumer panelists. The best mango chips were those pretreated with 65 (w/v) concentration for 60 min and vacuum fried at 120 degrees C. Mango chips under atmospheric frying had less carotenoid retention (32%) than those under vacuum frying (up to 65%). These results may help further optimize vacuum-frying processing of high-quality fruit-based snacks.

High-Speed Non-Volatile Optical Memory: Achievements and Challenges

Directory of Open Access Journals (Sweden)

Vadym Zayets

2017-01-01

Full Text Available We have proposed, fabricated, and studied a new design of a high-speed optical non-volatile memory. The recoding mechanism of the proposed memory utilizes a magnetization reversal of a nanomagnet by a spin-polarized photocurrent. It was shown experimentally that the operational speed of this memory may be extremely fast above 1 TBit/s. The challenges to realize both a high-speed recording and a high-speed reading are discussed. The memory is compact, integratable, and compatible with present semiconductor technology. If realized, it will advance data processing and computing technology towards a faster operation speed.

Tractor performance monitor based on a single-chip microcomputer

Energy Technology Data Exchange (ETDEWEB)

Bedri, A.R.; Marley, S.J.; Buchelle, W.F.; Smay, T.A.

1981-01-01

A tractor performance monitor based on a single-chip microcomputer was developed to measure ground speed, slip, fuel consumption (rate and total), total area, theoretical time, and total time. Transducers used are presented in detail. 5 refs.

High speed laser tomography system

Science.gov (United States)

Samsonov, D.; Elsaesser, A.; Edwards, A.; Thomas, H. M.; Morfill, G. E.

2008-03-01

A high speed laser tomography system was developed capable of acquiring three-dimensional (3D) images of optically thin clouds of moving micron-sized particles. It operates by parallel-shifting an illuminating laser sheet with a pair of galvanometer-driven mirrors and synchronously recording two-dimensional (2D) images of thin slices of the imaged volume. The maximum scanning speed achieved was 120000slices/s, sequences of 24 volume scans (up to 256 slices each) have been obtained. The 2D slices were stacked to form 3D images of the volume, then the positions of the particles were identified and followed in the consecutive scans. The system was used to image a complex plasma with particles moving at speeds up to cm/s.

A Historical Review of High Speed Metal Forming

OpenAIRE

Zittel, G.

2010-01-01

This paper will present a Historical Review of High Speed Metal Forming beginning with the first thought of forming metal by using an electromagnetic impulse to today, whereby High Speed Metal Forming is an accepted production process. Although this paper will briefly cover the basic physics of the process, it will not dwell on it. It will rather show how the industrial acceptance of High Speed Metal Forming is tightly connected to the knowledge acquired from many applications studies. These ...

Mechanisms and FEM Simulation of Chip Formation in Orthogonal Cutting In-Situ TiB2/7050Al MMC

Science.gov (United States)

Wang, Wenhu; Jiang, Ruisong; Lin, Kunyang; Shao, Mingwei

2018-01-01

The in-situ TiB2/7050Al composite is a new kind of Al-based metal matrix composite (MMC) with super properties, such as low density, improved strength, and wear resistance. This paper, for a deep insight into its cutting performance, involves a study of the chip formation process and finite element simulation during orthogonal cutting in-situ TiB2/7050Al MMC. With chips, material properties, cutting forces, and tool geometry parameters, the Johnson–Cook (J–C) constitutive equation of in-situ TiB2/7050Al composite was established. Then, the cutting simulation model was established by applying the Abaqus–Explicit method, and the serrated chip, shear plane, strain rate, and temperature were analyzed. The experimental and simulation results showed that the obtained material’s constitutive equation was of high reliability, and the saw-tooth chips occurred commonly under either low or high cutting speed and small or large feed rate. From result analysis, it was found that the mechanisms of chip formation included plastic deformation, adiabatic shear, shearing slip, and crack extension. In addition, it was found that the existence of small, hard particles reduced the ductility of the MMC and resulted in segmental chips. PMID:29662047

A 1,000 Frames/s Programmable Vision Chip with Variable Resolution and Row-Pixel-Mixed Parallel Image Processors

Directory of Open Access Journals (Sweden)

Nanjian Wu

2009-07-01

Full Text Available A programmable vision chip with variable resolution and row-pixel-mixed parallel image processors is presented. The chip consists of a CMOS sensor array, with row-parallel 6-bit Algorithmic ADCs, row-parallel gray-scale image processors, pixel-parallel SIMD Processing Element (PE array, and instruction controller. The resolution of the image in the chip is variable: high resolution for a focused area and low resolution for general view. It implements gray-scale and binary mathematical morphology algorithms in series to carry out low-level and mid-level image processing and sends out features of the image for various applications. It can perform image processing at over 1,000 frames/s (fps. A prototype chip with 64 × 64 pixels resolution and 6-bit gray-scale image is fabricated in 0.18 mm Standard CMOS process. The area size of chip is 1.5 mm × 3.5 mm. Each pixel size is 9.5 μm × 9.5 μm and each processing element size is 23 μm × 29 μm. The experiment results demonstrate that the chip can perform low-level and mid-level image processing and it can be applied in the real-time vision applications, such as high speed target tracking.

On the upgrade of an optical code division PON with a code-sense ethernet MAC protocol

NARCIS (Netherlands)

Huiszoon, B.; Waardt, de H.; Khoe, G.D.; Koonen, A.M.J.

2007-01-01

We propose, for the first time, optical code-sense multiple access / collision detection to upgrade an optical code division passive optical network with minor modifications to transparently deploy Ethernet (or packet) based services.

Parallel Processing Performance Evaluation of Mixed T10/T100 Ethernet Topologies on Linux Pentium Systems

National Research Council Canada - National Science Library

Decato, Steven

1997-01-01

... performed on relatively inexpensive off the shelf components. Alternative network topologies were implemented using 10 and 100 megabit-per-second Ethernet cards under the Linux operating system on Pentium based personal computer platforms...

Transportable GPU (General Processor Units) chip set technology for standard computer architectures

Science.gov (United States)

Fosdick, R. E.; Denison, H. C.

1982-11-01

The USAFR-developed GPU Chip Set has been utilized by Tracor to implement both USAF and Navy Standard 16-Bit Airborne Computer Architectures. Both configurations are currently being delivered into DOD full-scale development programs. Leadless Hermetic Chip Carrier packaging has facilitated implementation of both architectures on single 41/2 x 5 substrates. The CMOS and CMOS/SOS implementations of the GPU Chip Set have allowed both CPU implementations to use less than 3 watts of power each. Recent efforts by Tracor for USAF have included the definition of a next-generation GPU Chip Set that will retain the application-proven architecture of the current chip set while offering the added cost advantages of transportability across ISO-CMOS and CMOS/SOS processes and across numerous semiconductor manufacturers using a newly-defined set of common design rules. The Enhanced GPU Chip Set will increase speed by an approximate factor of 3 while significantly reducing chip counts and costs of standard CPU implementations.

On-chip high-voltage generator design design methodology for charge pumps

CERN Document Server

Tanzawa, Toru

2016-01-01

This book provides various design techniques for switched-capacitor on-chip high-voltage generators, including charge pump circuits, regulators, level shifters, references, and oscillators.  Readers will see these techniques applied to system design in order to address the challenge of how the on-chip high-voltage generator is designed for Flash memories, LCD drivers, and other semiconductor devices to optimize the entire circuit area and power efficiency with a low voltage supply, while minimizing the cost.  This new edition includes a variety of useful updates, including coverage of power efficiency and comprehensive optimization methodologies for DC-DC voltage multipliers, modeling of extremely low voltage Dickson charge pumps, and modeling and optimum design of AC-DC switched-capacitor multipliers for energy harvesting and power transfer for RFID.

High-speed photography. Technique and evolution

International Nuclear Information System (INIS)

Sanchez-Tembleque, R.

1981-01-01

It is intended to present some general considerations about ''Higg-speed photography'' as a tool of work common in mos research laboratories in the world. ''High-speed photography'' relies on the principles of photography of actions, that change rapidly with the time. The evolution of this technique goes along with the discovering of new phenomena in wich higher speeds are involved. At present is normal to deal with changing rates involving picoseconds times (10 -12 s) and new developments on the field of femtosecond (10 -15 s) theoretically are contemplated. (author)

Price of forest chips decreasing

International Nuclear Information System (INIS)

Hakkila, P.

2001-01-01

Use of forest chips was studied in 1999 in the national Puuenergia (Wood Energy) research program. Wood combusting heating plants were questioned about are the main reasons restricting the increment of the use of forest chips. Heating plants, which did not use forest chips at all or which used less than 250 m 3 (625 bulk- m 3 ) in 1999 were excluded. The main restrictions for additional use of forest chips were: too high price of forest chips; lack of suppliers and/or uncertainty of deliveries; technical problems of reception and processing of forest chips; insufficiency of boiler output especially in winter; and unsatisfactory quality of chips. The price of forest chips becomes relatively high because wood biomass used for production of forest chips has to be collected from wide area. Heavy equipment has to be used even though small fragments of wood are processed, which increases the price of chips. It is essential for forest chips that the costs can be pressed down because competition with fossil fuels, peat and industrial wood residues is hard. Low market price leads to the situation in which forest owner gets no price of the raw material, the entrepreneurs operate at the limit of profitability and renovation of machinery is difficult, and forest chips suppliers have to sell the chips at prime costs. Price of forest chips has decreased significantly during the past decade. Nominal price of forest chips is now lower than two decades ago. The real price of chips has decreased even more than the nominal price, 35% during the past decade and 20% during the last five years. Chips, made of small diameter wood, are expensive because the price includes the felling costs and harvesting is carried out at thinning lots. Price is especially high if chips are made of delimbed small diameter wood due to increased the work and reduced amount of chips. The price of logging residue chips is most profitable because cutting does not cause additional costs. Recovery of chips is

Review of High-Speed Fiber Optic Grating Sensors Systems

Energy Technology Data Exchange (ETDEWEB)

Udd, E; Benterou, J; May, C; Mihailov, S J; Lu, P

2010-03-24

Fiber grating sensors can be used to support a wide variety of high speed measurement applications. This includes measurements of vibrations on bridges, traffic monitoring on freeways, ultrasonic detection to support non-destructive tests on metal plates and providing details of detonation events. This paper provides a brief overview of some of the techniques that have been used to support high speed measurements using fiber grating sensors over frequency ranges from 10s of kHz, to MHZ and finally toward frequencies approaching the GHz regime. Very early in the development of fiber grating sensor systems it was realized that a high speed fiber grating sensor system could be realized by placing an optical filter that might be a fiber grating in front of a detector so that spectral changes in the reflection from a fiber grating were amplitude modulated. In principal the only limitation on this type of system involved the speed of the output detector which with the development of high speed communication links moved from the regime of 10s of MHz toward 10s of GHz. The earliest deployed systems involved civil structures including measurements of the strain fields on composite utility poles and missile bodies during break tests, bridges and freeways. This was followed by a series of developments that included high speed fiber grating sensors to support nondestructive testing via ultrasonic wave detection, high speed machining and monitoring ship hulls. Each of these applications involved monitoring mechanical motion of structures and thus interest was in speeds up to a few 10s of MHz. Most recently there has been interest in using fiber grating to monitor the very high speed events such as detonations and this has led to utilization of fiber gratings that are consumed during an event that may require detection speeds of hundreds of MHz and in the future multiple GHz.

Trigger Data Serializer ASIC chip for the ATLAS New Small Wheel sTGC Detector

CERN Document Server

Wang, Jinhong; The ATLAS collaboration

2014-01-01

The small-strip Thin-Gap Chambers (sTGC) will be used as both trigger and precision tracking muon detectors for the Phase-I upgrade of the ATLAS New Small Wheel (NSW) muon detector. Signals from both the sTGC pad and strip detectors will be first read out by the Amplifier-Shaper-Discriminator (ASD) chip designed by the Brookhaven National Laboratory, and then collected and transmitted by a Trigger Data Serializer (TDS) chip at a rate of 4.8 Gbps to other related circuits. The pad-TDS chip checks the presence of pad hits and sends the information together with Bunching Crossing ID to the pad-trigger logic to define roads of interest. The strip-TDS chip collects and buffers strip charge information and transmits a range of strips within the road of interest to the router board located on the rim of the NSW. The large number of input channels (128 differential input channels), short time available to prepare and transmit trigger data (<100 ns), high speed output data rate (4.8 Gbps), harsh radiation environme...

High-speed three-dimensional plasma temperature determination of axially symmetric free-burning arcs

International Nuclear Information System (INIS)

Bachmann, B; Ekkert, K; Bachmann, J-P; Marques, J-L; Schein, J; Kozakov, R; Gött, G; Schöpp, H; Uhrlandt, D

2013-01-01

In this paper we introduce an experimental technique that allows for high-speed, three-dimensional determination of electron density and temperature in axially symmetric free-burning arcs. Optical filters with narrow spectral bands of 487.5–488.5 nm and 689–699 nm are utilized to gain two-dimensional spectral information of a free-burning argon tungsten inert gas arc. A setup of mirrors allows one to image identical arc sections of the two spectral bands onto a single camera chip. Two-different Abel inversion algorithms have been developed to reconstruct the original radial distribution of emission coefficients detected with each spectral window and to confirm the results. With the assumption of local thermodynamic equilibrium we calculate emission coefficients as a function of temperature by application of the Saha equation, the ideal gas law, the quasineutral gas condition and the NIST compilation of spectral lines. Ratios of calculated emission coefficients are compared with measured ones yielding local plasma temperatures. In the case of axial symmetry the three-dimensional plasma temperature distributions have been determined at dc currents of 100, 125, 150 and 200 A yielding temperatures up to 20000 K in the hot cathode region. These measurements have been validated by four different techniques utilizing a high-resolution spectrometer at different positions in the plasma. Plasma temperatures show good agreement throughout the different methods. Additionally spatially resolved transient plasma temperatures have been measured of a dc pulsed process employing a high-speed frame rate of 33000 frames per second showing the modulation of the arc isothermals with time and providing information about the sensitivity of the experimental approach. (paper)

TARGET: A multi-channel digitizer chip for very-high-energy gamma-ray telescopes

Energy Technology Data Exchange (ETDEWEB)

Bechtol, K.; Funk, S.; /Stanford U., HEPL /KIPAC, Menlo Park; Okumura, A.; /JAXA, Sagamihara /Stanford U., HEPL /KIPAC, Menlo Park; Ruckman, L.; /Hawaii U.; Simons, A.; Tajima, H.; Vandenbroucke, J.; /Stanford U., HEPL /KIPAC, Menlo Park; Varner, G.; /Hawaii U.

2011-08-11

The next-generation very-high-energy (VHE) gamma-ray observatory, the Cherenkov Telescope Array, will feature dozens of imaging atmospheric Cherenkov telescopes (IACTs), each with thousands of pixels of photosensors. To be affordable and reliable, reading out such a mega-channel array requires event recording technology that is highly integrated and modular, with a low cost per channel. We present the design and performance of a chip targeted to this application: the TeV Array Readout with GSa/s sampling and Event Trigger (TARGET). This application-specific integrated circuit (ASIC) has 16 parallel input channels, a 4096-sample buffer for each channel, adjustable input termination, self-trigger functionality, and tight window-selected readout. We report the performance of TARGET in terms of sampling frequency, power consumption, dynamic range, current-mode gain, analog bandwidth, and cross talk. The large number of channels per chip allows a low cost per channel ($10 to $20 including front-end and back-end electronics but not including photosensors) to be achieved with a TARGET-based IACT readout system. In addition to basic performance parameters of the TARGET chip itself, we present a camera module prototype as well as a second-generation chip (TARGET 2), both of which have been produced.

High-Speed Videography Instrumentation And Procedures

Science.gov (United States)

Miller, C. E.

1982-02-01

High-speed videography has been an electronic analog of low-speed film cameras, but having the advantages of instant-replay and simplicity of operation. Recent advances have pushed frame-rates into the realm of the rotating prism camera. Some characteristics of videography systems are discussed in conjunction with applications in sports analysis, and with sports equipment testing.

The analysis and compensation of errors of precise simple harmonic motion control under high speed and large load conditions based on servo electric cylinder

Science.gov (United States)

Ma, Chen-xi; Ding, Guo-qing

2017-10-01

Simple harmonic waves and synthesized simple harmonic waves are widely used in the test of instruments. However, because of the errors caused by clearance of gear and time-delay error of FPGA, it is difficult to control servo electric cylinder in precise simple harmonic motion under high speed, high frequency and large load conditions. To solve the problem, a method of error compensation is proposed in this paper. In the method, a displacement sensor is fitted on the piston rod of the electric cylinder. By using the displacement sensor, the real-time displacement of the piston rod is obtained and fed back to the input of servo motor, then a closed loop control is realized. There is compensation of pulses in the next period of the synthetic waves. This paper uses FPGA as the processing core. The software mainly comprises a waveform generator, an Ethernet module, a memory module, a pulse generator, a pulse selector, a protection module, an error compensation module. A durability of shock absorbers is used as the testing platform. The durability mainly comprises a single electric cylinder, a servo motor for driving the electric cylinder, and the servo motor driver.

Experimental investigation on the high chip rate of 2D incoherent optical CDMA system

Science.gov (United States)

Su, Guorui; Wang, Rong; Pu, Tao; Fang, Tao; Zheng, Jilin; Zhu, Huatao; Wu, Weijiang

2015-08-01

An innovative approach to realise high chip rate in OCDMA transmission system is proposed and experimentally investigation, the high chip rate is achieved through a 2-D wavelength-hopping time-spreading en/decoder based on the supercontinuum light source. The source used in the experiment is generated by high nonlinear optical fiber (HNLF), Erbium-doped fiber amplifier (EDFA) which output power is 26 dBm, and distributed feed-back laser diode which works in the gain switch state. The span and the flatness of the light source are 20 nm and 3 dB, respectively, after equalization of wavelength selective switch (WSS). The wavelength-hopping time-spreading coder can be changed 20 nm in the wavelength and 400 ps in the time, is consist of WSS and delay lines. Therefore, the experimental results show that the chip rate can achieve 500 Gchip/s, in the case of 2.5 Gbit/s, while keeping a bit error rate below forward error correction limit after 40 km transmission.

High-speed parallel implementation of a modified PBR algorithm on DSP-based EH topology

Science.gov (United States)

Rajan, K.; Patnaik, L. M.; Ramakrishna, J.

1997-08-01

Algebraic Reconstruction Technique (ART) is an age-old method used for solving the problem of three-dimensional (3-D) reconstruction from projections in electron microscopy and radiology. In medical applications, direct 3-D reconstruction is at the forefront of investigation. The simultaneous iterative reconstruction technique (SIRT) is an ART-type algorithm with the potential of generating in a few iterations tomographic images of a quality comparable to that of convolution backprojection (CBP) methods. Pixel-based reconstruction (PBR) is similar to SIRT reconstruction, and it has been shown that PBR algorithms give better quality pictures compared to those produced by SIRT algorithms. In this work, we propose a few modifications to the PBR algorithms. The modified algorithms are shown to give better quality pictures compared to PBR algorithms. The PBR algorithm and the modified PBR algorithms are highly compute intensive, Not many attempts have been made to reconstruct objects in the true 3-D sense because of the high computational overhead. In this study, we have developed parallel two-dimensional (2-D) and 3-D reconstruction algorithms based on modified PBR. We attempt to solve the two problems encountered by the PBR and modified PBR algorithms, i.e., the long computational time and the large memory requirements, by parallelizing the algorithm on a multiprocessor system. We investigate the possible task and data partitioning schemes by exploiting the potential parallelism in the PBR algorithm subject to minimizing the memory requirement. We have implemented an extended hypercube (EH) architecture for the high-speed execution of the 3-D reconstruction algorithm using the commercially available fast floating point digital signal processor (DSP) chips as the processing elements (PEs) and dual-port random access memories (DPR) as channels between the PEs. We discuss and compare the performances of the PBR algorithm on an IBM 6000 RISC workstation, on a Silicon

Integrated computer network high-speed parallel interface

International Nuclear Information System (INIS)

Frank, R.B.

1979-03-01

As the number and variety of computers within Los Alamos Scientific Laboratory's Central Computer Facility grows, the need for a standard, high-speed intercomputer interface has become more apparent. This report details the development of a High-Speed Parallel Interface from conceptual through implementation stages to meet current and future needs for large-scle network computing within the Integrated Computer Network. 4 figures

High-speed and intercity passenger rail testing strategy.

Science.gov (United States)

2013-05-01

This high-speed and intercity passenger rail (HSIPR) testing strategy addresses the requirements for testing of high-speed train sets and technology before introduction to the North American railroad system. The report documents the results of a surv...

Application of high-speed photography to hydrodynamic instability research

International Nuclear Information System (INIS)

Chang Lihua; Li Zuoyou; Xiao Zhengfei; Zou Liyong; Liu Jinhong; Xiong Xueshi

2012-01-01

High-speed photography is used to study the Rayleigh-Taylor instability of air-water interface driven by high- pressure exploding gas. Clear images illustrating the instability are obtained, along with the air bubble peak speed and turbulent mixing speed. The RM (Richtmyer-Meshkov) instability of air/SF 6 interface driven by shock wave is also researched by using high-speed Schlieren technique on the horizontal shock tube and primary experimental results are obtained, which show the change of the turbulent mixing region clearly. (authors)

Development of high-speed video cameras

Science.gov (United States)

Etoh, Takeharu G.; Takehara, Kohsei; Okinaka, Tomoo; Takano, Yasuhide; Ruckelshausen, Arno; Poggemann, Dirk

2001-04-01

Presented in this paper is an outline of the R and D activities on high-speed video cameras, which have been done in Kinki University since more than ten years ago, and are currently proceeded as an international cooperative project with University of Applied Sciences Osnabruck and other organizations. Extensive marketing researches have been done, (1) on user's requirements on high-speed multi-framing and video cameras by questionnaires and hearings, and (2) on current availability of the cameras of this sort by search of journals and websites. Both of them support necessity of development of a high-speed video camera of more than 1 million fps. A video camera of 4,500 fps with parallel readout was developed in 1991. A video camera with triple sensors was developed in 1996. The sensor is the same one as developed for the previous camera. The frame rate is 50 million fps for triple-framing and 4,500 fps for triple-light-wave framing, including color image capturing. Idea on a video camera of 1 million fps with an ISIS, In-situ Storage Image Sensor, was proposed in 1993 at first, and has been continuously improved. A test sensor was developed in early 2000, and successfully captured images at 62,500 fps. Currently, design of a prototype ISIS is going on, and, hopefully, will be fabricated in near future. Epoch-making cameras in history of development of high-speed video cameras by other persons are also briefly reviewed.

Chip-integrated ultrawide-band all-optical logic comparator in plasmonic circuits.

Science.gov (United States)

Lu, Cuicui; Hu, Xiaoyong; Yang, Hong; Gong, Qihuang

2014-01-27

Optical computing opens up the possibility for the realization of ultrahigh-speed and ultrawide-band information processing. Integrated all-optical logic comparator is one of the indispensable core components of optical computing systems. Unfortunately, up to now, no any nanoscale all-optical logic comparator suitable for on-chip integration applications has been realized experimentally. Here, we report a subtle and effective technical solution to circumvent the obstacles of inherent Ohmic losses of metal and limited propagation length of SPPs. A nanoscale all-optical logic comparator suitable for on-chip integration applications is realized in plasmonic circuits directly. The incident single-bit (or dual-bit) logic signals can be compared and the comparison results are endowed with different logic encodings. An ultrabroad operating wavelength range from 700 to 1000 nm, and an ultrahigh output logic-state contrast-ratio of more than 25 dB are realized experimentally. No high power requirement is needed. Though nanoscale SPP light source and the logic comparator device are integrated into the same plasmonic chip, an ultrasmall feature size is maintained. This work not only paves a way for the realization of complex logic device such as adders and multiplier, but also opens up the possibility for realizing quantum solid chips based on plasmonic circuits.

High-speed AFM of human chromosomes in liquid

Energy Technology Data Exchange (ETDEWEB)

Picco, L M; Dunton, P G; Ulcinas, A; Engledew, D J; Miles, M J [H H Wills Physics Laboratory and IRC in Nanotechnology, University of Bristol, Tyndall Avenue, Bristol BS8 1TL (United Kingdom); Hoshi, O; Ushiki, T [Division of Microscopic Anatomy and Bio-Imaging, Department of Cellular Function, Niigata University Graduate School of Medical and Dental Sciences, Asahimachi-Dori 1, Niigata, 951-8150 (Japan)], E-mail: m.j.miles@bristol.ac.uk

2008-09-24

Further developments of the previously reported high-speed contact-mode AFM are described. The technique is applied to the imaging of human chromosomes at video rate both in air and in water. These are the largest structures to have been imaged with high-speed AFM and the first imaging in liquid to be reported. A possible mechanism that allows such high-speed contact-mode imaging without significant damage to the sample is discussed in the context of the velocity dependence of the measured lateral force on the AFM tip.

Characterizing speed-independence of high-level designs

DEFF Research Database (Denmark)

Kishinevsky, Michael; Staunstrup, Jørgen

1994-01-01

This paper characterizes the speed-independence of high-level designs. The characterization is a condition on the design description ensuring that the behavior of the design is independent of the speeds of its components. The behavior of a circuit is modeled as a transition system, that allows data...... types, and internal as well as external non-determinism. This makes it possible to verify the speed-independence of a design without providing an explicit realization of the environment. The verification can be done mechanically. A number of experimental designs have been verified including a speed-independent...

Development of ultra high speed photographic system using high repetition rate visible laser

International Nuclear Information System (INIS)

Lee, Jong Min; Cha, Byung Hun; Kim, Sung Ho; Kim, Jung Bog; Lim, Chang Hwan; Cha, Hyung Ki; Song, Kyu Seok; Lee, Byung Deok; Rhi, Jong Hoon; Baik, Dae Hyun; Han, Jae Min; Rho, Si Pyo; Lee, Byung Cheol; Jeong, Do Yung; Choi, An Seong; Jeong, Chan Ik; Park, Dae Ung; Jeong, Sung Min; Lee, Sang Kil; Kim, Heon Jun; Jang, Rae gak; Jo, Do Hun; Park, Min Young

1992-12-01

The goal of this project is to develop and commercialize a high speed photographic system equipped with a high repetition rate visible laser. The developed system provides the characteristics of high time resolution and large number of frames. The system consists of 10 W air cooled CVL or a 30 W water cooled CVL, a rotating drum-type high speed camera with the framing rate of 35,000 fps, and a automatic control device. The system has the performance of 10 nsec time resolution, 35,000 fps framing rate, and 250 picture frames. The high speed photographic systems are widely applied to the fields such as high-efficient engine development, high-speed vibration analysis, shock wave propagation study, flow visualization analysis, weapon development, etc. (Author)

Module Integrated GaN Power Stage for High Switching Frequency Operation

DEFF Research Database (Denmark)

Nour, Yasser; Knott, Arnold

2017-01-01

is integrated on a high glass transition temperature 0.4 mmthick FR4 substrate configured as a 70 pin ball grid arraypackage. The power stage is tested up to switching frequency of12 MHz. The power stage achieved 88.5 % peak efficiency whenconfigured as a soft switching buck converter operating at 7MHz......An increased attention has been detected todevelop smaller and lighter high voltage power converters in therange of 50 V to 400 V domains. The applications for theseconverters are mainly focused for Power over Ethernet (PoE),LED lighting and ac adapters. Design for high power density isone...... of the targets for next generation power converters. Thispaper presents an 80 V input capable multi-chip moduleintegration of enhancement mode gallium nitride (GaN) fieldeffect transistors (FETs) based power stage. The module design ispresented and validated through experimental results. The powerstage...

Optical interconnects for in-plane high-speed signal distribution at 10 Gb/s: Analysis and demonstration

Science.gov (United States)

Chang, Yin-Jung

With decreasing transistor size, increasing chip speed, and larger numbers of processors in a system, the performance of a module/system is being limited by the off-chip and off-module bandwidth-distance products. Optical links have moved from fiber-based long distance communications to the cabinet level of 1m--100m, and recently to the backplane-level (10cm--1m). Board-level inter-chip parallel optical interconnects have been demonstrated recently by researchers from Intel, IBM, Fujitsu, NTT and a few research groups in universities. However, the board-level signal/clock distribution function using optical interconnects, the lightwave circuits, the system design, a practically convenient integration scheme committed to the implementation of a system prototype have not been explored or carefully investigated. In this dissertation, the development of a board-level 1 x 4 optical-to-electrical signal distribution at 10Gb/s is presented. In contrast to other prototypes demonstrating board-level parallel optical interconnects that have been drawing much attention for the past decade, the optical link design for the high-speed signal broadcasting is even more complicated and the pitch between receivers could be varying as opposed to fixed-pitch design that has been widely-used in the parallel optical interconnects. New challenges for the board-level high-speed signal broadcasting include, but are not limited to, a new optical link design, a lightwave circuit as a distribution network, and a novel integration scheme that can be a complete radical departure from the traditional assembly method. One of the key building blocks in the lightwave circuit is the distribution network in which a 1 x 4 multimode interference (MMI) splitter is employed. MMI devices operating at high data rates are important in board-level optical interconnects and need to be characterized in the application of board-level signal broadcasting. To determine the speed limitations of MMI devices, the

Chip-Oriented Fluorimeter Design and Detection System Development for DNA Quantification in Nano-Liter Volumes

Directory of Open Access Journals (Sweden)

Da-Sheng Lee

2009-12-01

Full Text Available The chip-based polymerase chain reaction (PCR system has been developed in recent years to achieve DNA quantification. Using a microstructure and miniature chip, the volume consumption for a PCR can be reduced to a nano-liter. With high speed cycling and a low reaction volume, the time consumption of one PCR cycle performed on a chip can be reduced. However, most of the presented prototypes employ commercial fluorimeters which are not optimized for fluorescence detection of such a small quantity sample. This limits the performance of DNA quantification, especially low experiment reproducibility. This study discusses the concept of a chip-oriented fluorimeter design. Using the analytical model, the current study analyzes the sensitivity and dynamic range of the fluorimeter to fit the requirements for detecting fluorescence in nano-liter volumes. Through the optimized processes, a real-time PCR on a chip system with only one nano-liter volume test sample is as sensitive as the commercial real-time PCR machine using the sample with twenty micro-liter volumes. The signal to noise (S/N ratio of a chip system for DNA quantification with hepatitis B virus (HBV plasmid samples is 3 dB higher. DNA quantification by the miniature chip shows higher reproducibility compared to the commercial machine with respect to samples of initial concentrations from 103 to 105 copies per reaction.

Pixel detector readout chip

CERN Multimedia

1991-01-01

Close-up of a pixel detector readout chip. The photograph shows an aera of 1 mm x 2 mm containing 12 separate readout channels. The entire chip contains 1000 readout channels (around 80 000 transistors) covering a sensitive area of 8 mm x 5 mm. The chip has been mounted on a silicon detector to detect high energy particles.

Highly specific detection of genetic modification events using an enzyme-linked probe hybridization chip.

Science.gov (United States)

Zhang, M Z; Zhang, X F; Chen, X M; Chen, X; Wu, S; Xu, L L

2015-08-10

The enzyme-linked probe hybridization chip utilizes a method based on ligase-hybridizing probe chip technology, with the principle of using thio-primers for protection against enzyme digestion, and using lambda DNA exonuclease to cut multiple PCR products obtained from the sample being tested into single-strand chains for hybridization. The 5'-end amino-labeled probe was fixed onto the aldehyde chip, and hybridized with the single-stranded PCR product, followed by addition of a fluorescent-modified probe that was then enzymatically linked with the adjacent, substrate-bound probe in order to achieve highly specific, parallel, and high-throughput detection. Specificity and sensitivity testing demonstrated that enzyme-linked probe hybridization technology could be applied to the specific detection of eight genetic modification events at the same time, with a sensitivity reaching 0.1% and the achievement of accurate, efficient, and stable results.

A novel high electrode count spike recording array using an 81,920 pixel transimpedance amplifier-based imaging chip.

Science.gov (United States)

Johnson, Lee J; Cohen, Ethan; Ilg, Doug; Klein, Richard; Skeath, Perry; Scribner, Dean A

2012-04-15

Microelectrode recording arrays of 60-100 electrodes are commonly used to record neuronal biopotentials, and these have aided our understanding of brain function, development and pathology. However, higher density microelectrode recording arrays of larger area are needed to study neuronal function over broader brain regions such as in cerebral cortex or hippocampal slices. Here, we present a novel design of a high electrode count picocurrent imaging array (PIA), based on an 81,920 pixel Indigo ISC9809 readout integrated circuit camera chip. While originally developed for interfacing to infrared photodetector arrays, we have adapted the chip for neuron recording by bonding it to microwire glass resulting in an array with an inter-electrode pixel spacing of 30 μm. In a high density electrode array, the ability to selectively record neural regions at high speed and with good signal to noise ratio are both functionally important. A critical feature of our PIA is that each pixel contains a dedicated low noise transimpedance amplifier (∼0.32 pA rms) which allows recording high signal to noise ratio biocurrents comparable to single electrode voltage amplifier recordings. Using selective sampling of 256 pixel subarray regions, we recorded the extracellular biocurrents of rabbit retinal ganglion cell spikes at sampling rates up to 7.2 kHz. Full array local electroretinogram currents could also be recorded at frame rates up to 100 Hz. A PIA with a full complement of 4 readout circuits would span 1cm and could acquire simultaneous data from selected regions of 1024 electrodes at sampling rates up to 9.3 kHz. Published by Elsevier B.V.

Minimum Plate Thickness in High-Speed Craft

DEFF Research Database (Denmark)

Pedersen, Preben Terndrup; Zhang, Shengming

1998-01-01

The minimum plate thickness requirements specified by the classification societies for high-speed craft are supposed to ensure adequate resistance to impact loads such as collision with floating objects and objects falling on the deck. The paper presents analytical methods of describing such impact...... phenomena and proposes performance requirements instead of thickness requirements for hull panels in high-speed craft made of different building materials....

The large scale and long term evolution of the solar wind speed distribution and high speed streams

International Nuclear Information System (INIS)

Intriligator, D.S.

1977-01-01

The spatial and temporal evolution of the solar wind speed distribution and of high speed streams in the solar wind are examined. Comparisons of the solar wind streaming speeds measured at Earth, Pioneer 11, and Pioneer 10 indicate that between 1 AU and 6.4 AU the solar wind speed distributions are narrower (i.e. the 95% value minus the 5% value of the solar wind streaming speed is less) at extended heliocentric distances. These observations are consistent with one exchange of momentum in the solar wind between high speed streams and low speed streams as they propagate outward from the Sun. Analyses of solar wind observations at 1 AU from mid 1964 through 1973 confirm the earlier results reported by Intriligator (1974) that there are statistically significant variations in the solar wind in 1968 and 1969, years of solar maximum. High speed stream parameters show that the number of high speed streams in the solar wind in 1968 and 1969 is considerably more than the predicted yearly average, and in 1965 and 1972 less. Histograms of solar wind speed from 1964 through 1973 indicate that in 1968 there was the highest percentage of elevated solar wind speeds and in 1965 and 1972 the lowest. Studies by others also confirm these results although the respective authors did not indicate this fact. The duration of the streams and the histograms for 1973 imply a shifting in the primary stream source. (Auth.)

EXPERIMENTAL INVESTIGATION OF THE TOOL-CHIP INTERFACE TMPERATURES ON UNCOATED CEMENTIDE CARBIDE CUTTING TOOLS

Directory of Open Access Journals (Sweden)

Kasım HABALI

2005-01-01

Full Text Available It is known that the temperature as the result of the heat developed during machining at the tool-chip interface has an influence on the tool life and workpiece surface guality and the methods for measuring this temperature are constantly under investigation. In this study, the measurement of tool-chip interface temperature using toolworkpiece termocouple method was investigated. The test were carried out on a AISI 1040 steel and the toolchip interface temperature variation was examined depending on the cutting speed and feed rate. The obtained groups show that cutting speed has more influence on the temperature than feedrate has.

Time and charge calibration of Cherenkov telescope data acquired by Domino Ring Sampler 4 chips

Energy Technology Data Exchange (ETDEWEB)

Hoerbe, Mario; Doert, Marlene [Ruhr-Universitaet Bochum (Germany); Bruegge, Kai; Buss, Jens; Bockermann, Christian; Egorov, Alexej [TU Dortmund (Germany)

2016-07-01

Very-high-energy gamma-ray astronomy aims to give an insight into the most energetic phenomena in our Universe. Earthbound Cherenkov telescopes can measure Cherenkov light emitted by atmospheric particle showers which are produced by incoming cosmic particles at high energies. Current Cherenkov telescopes, e.g. operated in the FACT and the MAGIC experiments, utilize Domino Ring Sampler 4 (DRS4) chips for recording signals at high speed coming from the telescopes' cameras. DRS4 chips will also be used in the cameras of the Large-Size telescopes of the projected Cherenkov Telescope Array (CTA). We aim at developing a software solution for the calibration of DRS4 data based on the streams-framework, a software tool for streaming analysis which has been developed within the Collaborative Research Center SFB 876. The objectives and the current status of the project are presented.

Rat muscle blood flows during high-speed locomotion

International Nuclear Information System (INIS)

Armstrong, R.B.; Laughlin, M.H.

1985-01-01

We previously studied blood flow distribution within and among rat muscles as a function of speed from walking (15 m/min) through galloping (75 m/min) on a motor-driven treadmill. The results showed that muscle blood flows continued to increase as a function of speed through 75 m/min. The purpose of the present study was to have rats run up to maximal treadmill speeds to determine if blood flows in the muscles reach a plateau as a function of running speed over the animals normal range of locomotory speeds. Muscle blood flows were measured with radiolabeled microspheres at 1 min of running at 75, 90, and 105 m/min in male Sprague-Dawley rats. The data indicate that even at these relatively high treadmill speeds there was still no clear evidence of a plateau in blood flow in most of the hindlimb muscles. Flows in most muscles continued to increase as a function of speed. These observed patterns of blood flow vs. running speed may have resulted from the rigorous selection of rats that were capable of performing the high-intensity exercise and thus only be representative of a highly specific population of animals. On the other hand, the data could be interpreted to indicate that the cardiovascular potential during exercise is considerably higher in laboratory rats than has normally been assumed and that inadequate blood flow delivery to the muscles does not serve as a major limitation to their locomotory performance

High-Speed Photo-Polarimetry of Magnetic Cataclysmic Variables

Directory of Open Access Journals (Sweden)

S. B. Potter

2015-02-01

Full Text Available I review recent highlights of the SAAO High-speed Photo-POlarimeter (HIPPO on the study of magnetic Cataclysmic Variables. Its high-speed capabilities are demonstrated with example observations made of the intermediate polar NY Lup and the polar IGRJ14536-5522.

Trend on High-speed Power Line Communication Technology

Science.gov (United States)

Ogawa, Osamu

High-speed power line communication (PLC) is useful technology to easily build the communication networks, because construction of new infrastructure is not necessary. In Europe and America, PLC has been used for broadband networks since the beginning of 21th century. In Japan, high-speed PLC was deregulated only indoor usage in 2006. Afterward it has been widely used for home area network, LAN in hotels and school buildings and so on. And recently, PLC is greatly concerned as communication technology for smart grid network. In this paper, the author surveys the high-speed PLC technology and its current status.

A high speed digital noise generator

Science.gov (United States)

Obrien, J.; Gaffney, B.; Liu, B.

In testing of digital signal processing hardware, a high speed pseudo-random noise generator is often required to simulate an input noise source to the hardware. This allows the hardware to be exercised in a manner analogous to actual operating conditions. In certain radar and communication environments, a noise generator operating at speeds in excess of 60 MHz may be required. In this paper, a method of generating high speed pseudo-random numbers from an arbitrarily specified distribution (Gaussian, Log-Normal, etc.) using a transformation from a uniform noise source is described. A noise generator operating at 80 MHz has been constructed. Different distributions can be readily obtained by simply changing the ROM set. The hardware and test results will be described. Using this approach, the generation of pseudo-random sequences with arbitrary distributions at word rates in excess of 200 MHz can be readily achieved.

Compressibility, turbulence and high speed flow

CERN Document Server

Gatski, Thomas B

2013-01-01

Compressibility, Turbulence and High Speed Flow introduces the reader to the field of compressible turbulence and compressible turbulent flows across a broad speed range, through a unique complimentary treatment of both the theoretical foundations and the measurement and analysis tools currently used. The book provides the reader with the necessary background and current trends in the theoretical and experimental aspects of compressible turbulent flows and compressible turbulence. Detailed derivations of the pertinent equations describing the motion of such turbulent flows is provided and an extensive discussion of the various approaches used in predicting both free shear and wall bounded flows is presented. Experimental measurement techniques common to the compressible flow regime are introduced with particular emphasis on the unique challenges presented by high speed flows. Both experimental and numerical simulation work is supplied throughout to provide the reader with an overall perspective of current tre...

High-speed solar wind flow parameters at 1 AU

International Nuclear Information System (INIS)

Feldman, W.C.; Asbridge, J.R.; Bame, S.J.; Gosling, J.T.

1976-01-01

To develop a set of constraints for theories of solar wind high-speed streams, a detailed study was made of the fastest streams observed at 1 AU during the time period spanning March 1971 through July 1974. Streams were accepted for study only if (1) the maximum speed exceeded 650 km s -1 ; (2) effects of stream-stream dynamical interaction on the flow parameters could be safely separated from the intrinsic characteristics of the high-speed regions; (3) the full width at half maximum (FWHM) of the stream when mapped back to 20 solar radii by using a constant speed approximation was greater than 45degree in Carrington longitude; and (4) there were no obvious solar-activity-induced contaminating effects. Nineteen streams during this time interval satisfied these criteria. Average parameters at 1 AU for those portions of these streams above V=650 km s -1 are given.Not only is it not presently known why electrons are significantly cooler than the protons within high-speed regions, but also observed particle fluxes and convected energy fluxes for speed greater than 650 km s -1 are substantially larger than those values predicted by any of the existing theories of solar wind high-speed streams. More work is therefore needed in refining present solar wind models to see whether suitable modifications and/or combinations of existing theories based on reasonable coronal conditions can accommodate the above high-speed flow parameters

A Lab-on-Chip Design for Miniature Autonomous Bio-Chemoprospecting Planetary Rovers

Science.gov (United States)

Santoli, S.

The performance of the so-called ` Lab-on-Chip ' devices, featuring micrometre size components and employed at present for carrying out in a very fast and economic way the extremely high number of sequence determinations required in genomic analyses, can be largely improved as to further size reduction, decrease of power consumption and reaction efficiency through development of nanofluidics and of nano-to-micro inte- grated systems. As is shown, such new technologies would lead to robotic, fully autonomous, microwatt consumption and complete ` laboratory on a chip ' units for accurate, fast and cost-effective astrobiological and planetary exploration missions. The theory and the manufacturing technologies for the ` active chip ' of a miniature bio/chemoprospecting planetary rover working on micro- and nanofluidics are investigated. The chip would include micro- and nanoreactors, integrated MEMS (MicroElectroMechanical System) components, nanoelectronics and an intracavity nanolaser for highly accurate and fast chemical analysis as an application of such recently introduced solid state devices. Nano-reactors would be able to strongly speed up reaction kinetics as a result of increased frequency of reactive collisions. The reaction dynamics may also be altered with respect to standard macroscopic reactors. A built-in miniature telemetering unit would connect a network of other similar rovers and a central, ground-based or orbiting control unit for data collection and transmission to an Earth-based unit through a powerful antenna. The development of the ` Lab-on-Chip ' concept for space applications would affect the economy of space exploration missions, as the rover's ` Lab-on-Chip ' development would link space missions with the ever growing terrestrial market and business concerning such devices, largely employed in modern genomics and bioinformatics, so that it would allow the recoupment of space mission costs.

California statewide model for high-speed rail

OpenAIRE

Outwater, Maren; Tierney, Kevin; Bradley, Mark; Sall, Elizabeth; Kuppam, Arun; Modugala, Vamsee

2010-01-01

The California High Speed Rail Authority (CHSRA) and the Metropolitan Transportation Commission (MTC) have developed a new statewide model to support evaluation of high-speed rail alternatives in the State of California. This statewide model will also support future planning activities of the California Department of Transportation (Caltrans). The approach to this statewide model explicitly recognizes the unique characteristics of intraregional travel demand and interregional travel demand. A...

Design of an Electro-Optic Modulator for High Speed Communications

Science.gov (United States)

Espinoza, David

The telecommunications and computer technology industries have been requiring higher communications speeds at all levels for devices, components and interconnected systems. Optical devices and optical interconnections are a viable alternative over other traditional technologies such as copper-based interconnections. Latency reductions can be achieved through the use of optical interconnections. Currently, a particular architecture for optical interconnections is being studied at the University of Colorado at Boulder in the EMT/NANO project, called Broadcast Optical Interconnects for Global Communication in Many-Core Chip Multiprocessor. As with most types of networks, including optical networks, one of the most important components are modulators. Therefore adequate design and fabrication techniques for modulators contribute to higher modulation rates which lead to improve the efficiency and reductions in the latency of the optical network. Electro-optical modulators are presented in this study as an alternative to achieve this end. In recent years, nonlinear optical (NLO) materials have been used for the fabrication of high-speed electro-optical modulators. Polymers doped with chromophores are an alternative among NLO materials because they can develop large electro-optic coefficients and low dielectric constants. These two factors are critical for achieving high-speed modulation rates. These polymer-based electro-optical modulators can be fabricated using standard laboratory techniques, such as polymer spin-coating onto substrates, UV bleaching to achieve a refractive index variation and poling techniques to align the chromophores in cured polymers. The design of the electro-optic modulators require the use of the optical parameters of the materials to be used. Therefore the characterization of these materials is a required previous step. This characterization is performed by the fabrication of chromophores-doped polymer samples and conducting transmission and

A nanofluidic bioarray chip for fast and high-throughput detection of antibodies in biological fluids

Science.gov (United States)

Lee, Jonathan; Gulzar, Naveed; Scott, Jamie K.; Li, Paul C. H.

2012-10-01

Immunoassays have become a standard in secretome analysis in clinical and research analysis. In this field there is a need for a high throughput method that uses low sample volumes. Microfluidics and nanofluidics have been developed for this purpose. Our lab has developed a nanofluidic bioarray (NBA) chip with the goal being a high throughput system that assays low sample volumes against multiple probes. A combination of horizontal and vertical channels are produced to create an array antigens on the surface of the NBA chip in one dimension that is probed by flowing in the other dimension antibodies from biological fluids. We have tested the NBA chip by immobilizing streptavidin and then biotinylated peptide to detect the presence of a mouse monoclonal antibody (MAb) that is specific for the peptide. Bound antibody is detected by an AlexaFluor 647 labeled goat (anti-mouse IgG) polyclonal antibody. Using the NBA chip, we have successfully detected peptide binding by small-volume (0.5 μl) samples containing 50 attomoles (100 pM) MAb.

Research on Aerodynamic Noise Reduction for High-Speed Trains

OpenAIRE

Zhang, Yadong; Zhang, Jiye; Li, Tian; Zhang, Liang; Zhang, Weihua

2016-01-01

A broadband noise source model based on Lighthill’s acoustic theory was used to perform numerical simulations of the aerodynamic noise sources for a high-speed train. The near-field unsteady flow around a high-speed train was analysed based on a delayed detached-eddy simulation (DDES) using the finite volume method with high-order difference schemes. The far-field aerodynamic noise from a high-speed train was predicted using a computational fluid dynamics (CFD)/Ffowcs Williams-Hawkings (FW-H)...

Nugget Structure Evolution with Rotation Speed for High-Rotation-Speed Friction-Stir-Welded 6061 Aluminum Alloy

Science.gov (United States)

Zhang, H. J.; Wang, M.; Zhu, Z.; Zhang, X.; Yu, T.; Wu, Z. Q.

2018-03-01

High-rotation-speed friction stir welding (HRS-FSW) is a promising technique to reduce the welding loads during FSW and thus facilitates the application of FSW for in situ fabrication and repair. In this study, 6061 aluminum alloy was friction stir welded at high-rotation speeds ranging from 3000 to 7000 rpm at a fixed welding speed of 50 mm/min, and the effects of rotation speed on the nugget zone macro- and microstructures were investigated in detail in order to illuminate the process features. Temperature measurements during HRS-FSW indicated that the peak temperature did not increase consistently with rotation speed; instead, it dropped remarkably at 5000 rpm because of the lowering of material shear stress. The nugget size first increased with rotation speed until 5000 rpm and then decreased due to the change of the dominant tool/workpiece contact condition from sticking to sliding. At the rotation speed of 5000 rpm, where the weld material experienced weaker thermal effect and higher-strain-rate plastic deformation, the nugget exhibited relatively small grain size, large textural intensity, and high dislocation density. Consequently, the joint showed superior nugget hardness and simultaneously a slightly low tensile ductility.

Balancing High-Speed Rotors at Low Speed

Science.gov (United States)

Giordano, J.; Zorzi, E.

1986-01-01

Flexible balancing reduces vibrations at operating speeds. Highspeed rotors in turbomachines dynamically balanced at fraction of operating rotor speed. New method takes into account rotor flexible rather than rigid.

High-speed holographic camera

International Nuclear Information System (INIS)

Novaro, Marc

The high-speed holographic camera is a disgnostic instrument using holography as an information storing support. It allows us to take 10 holograms, of an object, with exposures times of 1,5ns, separated in time by 1 or 2ns. In order to get these results easily, no mobile part is used in the set-up [fr

Recent progress on high-speed optical transmission

Directory of Open Access Journals (Sweden)

Jianjun Yu

2016-05-01

Full Text Available The recently reported high spectral efficiency (SE and high-baud-rate signal transmission are all based on digital coherent optical communications and digital signal processing (DSP. DSP simplifies the reception of advanced modulation formats and also enables the major electrical and optical impairments to be processed and compensated in the digital domain, at the transmitter or receiver side. In this paper, we summarize the research progress on high-speed signal generation and detection and also show the progress on DSP for high-speed signal detection. We also report the latest progress on multi-core and multi-mode multiplexing.

Ultrasonic Vibration Assisted Grinding of Bio-ceramic Materials: Modeling, Simulation, and Experimental Investigations on Edge Chipping

Science.gov (United States)

Tesfay, Hayelom D.

Bio-ceramics are those engineered materials that find their applications in the field of biomedical engineering or medicine. They have been widely used in dental restorations, repairing bones, joint replacements, pacemakers, kidney dialysis machines, and respirators. etc. due to their physico-chemical properties, such as excellent corrosion resistance, good biocompatibility, high strength and high wear resistance. Because of their inherent brittleness and hardness nature they are difficult to machine to exact sizes and dimensions. Abrasive machining processes such as grinding is one of the most widely used manufacturing processes for bioceramics. However, the principal technical challenge resulted from these machining is edge chipping. Edge chipping is a common edge failure commonly observed during the machining of bio-ceramic materials. The presence of edge chipping on bio-ceramic products affects dimensional accuracy, increases manufacturing cost, hider their industrial applications and causes potential failure during service. To overcome these technological challenges, a new ultrasonic vibration-assisted grinding (UVAG) manufacturing method has been developed and employed in this research. The ultimate aim of this study is to develop a new cost-effective manufacturing process relevant to eliminate edge chippings in grinding of bio-ceramic materials. In this dissertation, comprehensive investigations will be carried out using experimental, theoretical, and numerical approaches to evaluate the effect of ultrasonic vibrations on edge chipping of bioceramics. Moreover, effects of nine input variables (static load, vibration frequency, grinding depth, spindle speed, grinding distance, tool speed, grain size, grain number, and vibration amplitude) on edge chipping will be studied based on the developed models. Following a description of previous research and existing approaches, a series of experimental tests on three bio-ceramic materials (Lava, partially fired Lava

Single-Photon Tracking for High-Speed Vision

Directory of Open Access Journals (Sweden)

Istvan Gyongy

2018-01-01

Full Text Available Quanta Imager Sensors provide photon detections at high frame rates, with negligible read-out noise, making them ideal for high-speed optical tracking. At the basic level of bit-planes or binary maps of photon detections, objects may present limited detail. However, through motion estimation and spatial reassignment of photon detections, the objects can be reconstructed with minimal motion artefacts. We here present the first demonstration of high-speed two-dimensional (2D tracking and reconstruction of rigid, planar objects with a Quanta Image Sensor, including a demonstration of depth-resolved tracking.

A high-speed interface for multi-channel analyzer

International Nuclear Information System (INIS)

Shen Ji; Zheng Zhong; Qiao Chong; Chen Ziyu; Ye Yunxiu; Ye Zhenyu

2003-01-01

This paper presents a high-speed computer interface for multi-channel analyzer based on DMA technique. Its essential principle and operating procedure are introduced. By the detecting of γ spectrum of 137 Cs with the interface, it's proved that the interface can meet the requirements of high-speed data acquisition

Highly Sensitive and Selective Sensor Chips with Graphene-Oxide Linking Layer

DEFF Research Database (Denmark)

Stebunov, Yury V.; Aftenieva, Olga A.; Arsenin, Aleksey V.

2015-01-01

sensor chip for SPR biosensors based on graphene-oxide linking layers. The biosensing assay model was based on a graphene oxide film containing streptavidin. The proposed sensor chip has three times higher sensitivity than the carboxymethylated dextran surface of a commercial sensor chip. Moreover...

High Speed Magnetostrictive MEMS Actuated Mirror Deflectors, Phase II

Data.gov (United States)

National Aeronautics and Space Administration — The main goal of this proposal is to develop high speed magnetostrictive and MEMS actuators for rapidly deflecting or deforming mirrors. High speed, light-weight,...

IPbus A flexible Ethernet-based control system for xTCA hardware

CERN Document Server

Williams, Thomas Stephen

2014-01-01

The ATCA and uTCA standards include industry-standard data pathway technologies such as Gigabit Ethernet which can be used for control communication, but no specific hardware control protocol is defined. The IPbus suite of software and firmware implements a reliable high-performance control link for particle physics electronics, and has successfully replaced VME control in several large projects. In this paper, we outline the IPbus system architecture, and describe recent developments in the reliability, scalability and performance of IPbus systems, carried out in preparation for deployment of uTCA-based CMS upgrades before the LHC 2015 run. We also discuss plans for future development of the IPbus suite.SUMMARY IPbus will be used for controlling the uTCA electronics in the CMS HCAL, TCDS, Pixel and Level-1 trigger upgrades. IPbus control has already been extensively used in the work of these upgrade projects so far, and final uTCA systems will be deployed in the experiment starting from Autumn 2014. IPbus is...

Study of silicon chip soldering in high-power transistor housing

Directory of Open Access Journals (Sweden)

Vasily S. Anosov

2017-09-01

We experimentally assessed the effect of outer housing layer materials and back side chip metallization. For lead-silver soldering of silicon chips, the best housing is that with a nickel outer layer rather than with a gold-plated one, because the resultant thermal resistance is lower and the absence of gold makes the technology cheaper. We obtained a 0.6 K/W thermal resistance for a 24 mm2 chip area.

Bayesian Modeling of ChIP-chip Data Through a High-Order Ising Model

KAUST Repository

Mo, Qianxing

2010-01-29

ChIP-chip experiments are procedures that combine chromatin immunoprecipitation (ChIP) and DNA microarray (chip) technology to study a variety of biological problems, including protein-DNA interaction, histone modification, and DNA methylation. The most important feature of ChIP-chip data is that the intensity measurements of probes are spatially correlated because the DNA fragments are hybridized to neighboring probes in the experiments. We propose a simple, but powerful Bayesian hierarchical approach to ChIP-chip data through an Ising model with high-order interactions. The proposed method naturally takes into account the intrinsic spatial structure of the data and can be used to analyze data from multiple platforms with different genomic resolutions. The model parameters are estimated using the Gibbs sampler. The proposed method is illustrated using two publicly available data sets from Affymetrix and Agilent platforms, and compared with three alternative Bayesian methods, namely, Bayesian hierarchical model, hierarchical gamma mixture model, and Tilemap hidden Markov model. The numerical results indicate that the proposed method performs as well as the other three methods for the data from Affymetrix tiling arrays, but significantly outperforms the other three methods for the data from Agilent promoter arrays. In addition, we find that the proposed method has better operating characteristics in terms of sensitivities and false discovery rates under various scenarios. © 2010, The International Biometric Society.

Capacity planning for Carrier Ethernet LTE backhaul networks

DEFF Research Database (Denmark)

Checko, Aleksandra; Ellegaard, Lars; Berger, Michael Stübert

2012-01-01

With the introduction of LTE networks operators need to plan a new, IP-based mobile backhaul. In this paper, we provide recommendation on dimensioning LTE backhaul networks links using three methods: delay-, dimensioning formula- and overbooking factor-based. Results are obtained from OPNET simul...... and verified. Simulation in this work proves that Carrier Ethernet, one of the candidate technologies for mobile backhaul, protects the network from users that want to flood the network with their data and manages to keep the delay experienced by other users low....... simulations with traffic model based on traffic forecast for 2015. A delay-based approach gives recommended bandwidth for expected number of users. A dimensioning formula is proposed to calculate link bandwidth when mean value of aggregated traffic in the network is known. An overbooking factor is calculated...

On-chip nanofluidic integration of acoustic sensors towards high Q in liquid

Science.gov (United States)

Liang, Ji; Liu, Zifeng; Zhang, Hongxiang; Liu, Bohua; Zhang, Menglun; Zhang, Hao; Pang, Wei

2017-11-01

This paper reports an on-chip acoustic sensor comprising a piston-mode film bulk acoustic resonator and a monolithically integrated nanochannel. The resonator with the channel exhibits a resonance frequency (f) of 2.5 GHz and a quality (Q) factor of 436 in deionized water. The f × Q product is as high as 1.1 × 1012, which is the highest among all the acoustic wave sensors in the liquid phase. The sensor consumes 2 pl liquid volume and thus greatly saves the precious assays in biomedical testing. The Q factor is investigated, and real-time viscosity tests of glucose solution are demonstrated. The highly miniaturized and integrated sensor is capable to be arrayed with readout-circuitry, which opens an avenue for portable applications and lab-on-chip systems.

Cadence® High High-Speed PCB Design Flow Workshop

CERN Document Server

2006-01-01

Last release of Cadence High-Speed PCB Design methodology (PE142) based on Concept-HDL schematic editor, Constraint Manager, SPECCTRAQuest signal integrity analysis tool and ALLEGRO layout associated with SPECCTRA auto router tools, is now enough developed and stable to be taken into account for high-speed board designs at CERN. The implementation of this methodology, build around the new Constraint Manager program, is essential when you have to develop a board having a lot of high-speed design rules such as terminated lines, large bus structures, maximum length, timing, crosstalk etc.. that could not be under control by traditional method. On more conventional designs, formal aspect of the methodology could avoid misunderstanding between hardware and ALLEGRO layout designers, minimizing prototype iteration, development time and price. The capability to keep trace of the original digital designer intents in schematic or board layout, loading formal constraints in EDMS, could also be considered for LHC electro...

High-speed LWR transients simulation for optimizing emergency response

International Nuclear Information System (INIS)

Wulff, W.; Cheng, H.S.; Lekach, S.V.; Mallen, A.N.; Stritar, A.

1984-01-01

The purpose of computer-assisted emergency response in nuclear power plants, and the requirements for achieving such a response, are presented. An important requirement is the attainment of realistic high-speed plant simulations at the reactor site. Currently pursued development programs for plant simulations are reviewed. Five modeling principles are established and a criterion is presented for selecting numerical procedures and efficient computer hardware to achieve high-speed simulations. A newly developed technology for high-speed power plant simulation is described and results are presented. It is shown that simulation speeds ten times greater than real-time process-speeds are possible, and that plant instrumentation can be made part of the computational loop in a small, on-site minicomputer. Additional technical issues are presented which must still be resolved before the newly developed technology can be implemented in a nuclear power plant

Embedded multi-channel data acquisition system on FPGA for Aditya Tokamak

Energy Technology Data Exchange (ETDEWEB)

Rajpal, Rachana, E-mail: rachana@ipr.res.in [Institute for Plasma Research, Gandhinagar, Gujarat (India); Mandaliya, Hitesh, E-mail: hitesh@ipr.res.in [ITER, Cadarache (France); Patel, Jignesh, E-mail: jjp@ipr.res.in [ITER, Cadarache (France); Kumari, Praveena, E-mail: praveena@ipr.res.in [Institute for Plasma Research, Gandhinagar, Gujarat (India); Gautam, Pramila, E-mail: pramila@ipr.res.in [Institute for Plasma Research, Gandhinagar, Gujarat (India); Raulji, Vismaysinh, E-mail: vismay@ipr.res.in [Institute for Plasma Research, Gandhinagar, Gujarat (India); Edappala, Praveenlal, E-mail: praveen@ipr.res.in [Institute for Plasma Research, Gandhinagar, Gujarat (India); Pujara, H.D, E-mail: pujara@ipr.res [Institute for Plasma Research, Gandhinagar, Gujarat (India); Jha, R., E-mail: jha@ipr.res.in [Institute for Plasma Research, Gandhinagar, Gujarat (India)

2016-11-15

Highlights: • 64 channel data acquisition, interface to PC/104 bus, using single board computer. • Integration of all components in single hardware to make it standalone and portable. • Development of application software in Qt on Linux platform for better performance and low cost compared to Windows. • Explored and utilized FPGA resources for hardware interfacing. - Abstract: The 64 channel data acquisition board is designed to meet the future demand of acquisition channels for plasma diagnostics. The inherent features of the board are 16 bit resolution, programmable sampling rate upto 200 kS/s/ch and simultaneous acquisition. To make system embedded and compact, 8 Analog Inputs ADC chip, 4M × 16 bit RAM memory, Field Programmable Gate Arrays, PC/104 platform and single board computer are used. High speed timing control signals for all ADCs and RAMs are generated by FPGA. The system is standalone, portable and interface through Ethernet. The acquisition application is developed in Qt. on Linux platform, in SBC. Due to ethernet connectivity and onboard processing, system can be integrated into Aditya and SST-1 data acquisition system. The performance of hardware is tested on Linux and Windows Embedded OS. The paper describes design, hardware and software architecture, implementation and results of 64 channel DAQ system.

Embedded multi-channel data acquisition system on FPGA for Aditya Tokamak

International Nuclear Information System (INIS)

Rajpal, Rachana; Mandaliya, Hitesh; Patel, Jignesh; Kumari, Praveena; Gautam, Pramila; Raulji, Vismaysinh; Edappala, Praveenlal; Pujara, H.D; Jha, R.

2016-01-01

Highlights: • 64 channel data acquisition, interface to PC/104 bus, using single board computer. • Integration of all components in single hardware to make it standalone and portable. • Development of application software in Qt on Linux platform for better performance and low cost compared to Windows. • Explored and utilized FPGA resources for hardware interfacing. - Abstract: The 64 channel data acquisition board is designed to meet the future demand of acquisition channels for plasma diagnostics. The inherent features of the board are 16 bit resolution, programmable sampling rate upto 200 kS/s/ch and simultaneous acquisition. To make system embedded and compact, 8 Analog Inputs ADC chip, 4M × 16 bit RAM memory, Field Programmable Gate Arrays, PC/104 platform and single board computer are used. High speed timing control signals for all ADCs and RAMs are generated by FPGA. The system is standalone, portable and interface through Ethernet. The acquisition application is developed in Qt. on Linux platform, in SBC. Due to ethernet connectivity and onboard processing, system can be integrated into Aditya and SST-1 data acquisition system. The performance of hardware is tested on Linux and Windows Embedded OS. The paper describes design, hardware and software architecture, implementation and results of 64 channel DAQ system.

Cutting force model for high speed machining process

International Nuclear Information System (INIS)

Haber, R. E.; Jimenez, J. E.; Jimenez, A.; Lopez-Coronado, J.

2004-01-01

This paper presents cutting force-based models able to describe a high speed machining process. The model considers the cutting force as output variable, essential for the physical processes that are taking place in high speed machining. Moreover, this paper shows the mathematical development to derive the integral-differential equations, and the algorithms implemented in MATLAB to predict the cutting force in real time MATLAB is a software tool for doing numerical computations with matrices and vectors. It can also display information graphically and includes many toolboxes for several research and applications areas. Two end mill shapes are considered (i. e. cylindrical and ball end mill) for real-time implementation of the developed algorithms. the developed models are validated in slot milling operations. The results corroborate the importance of the cutting force variable for predicting tool wear in high speed machining operations. The developed models are the starting point for future work related with vibration analysis, process stability and dimensional surface finish in high speed machining processes. (Author) 19 refs

Performance of a Fast Binary Readout CMOS Active Pixel Sensor Chip Designed for Charged Particle Detection

Science.gov (United States)

Deerli, Yavuz; Besanon, Marc; Besson, Auguste; Claus, Gilles; Deptuch, Grzegorz; Dulinski, Wojciech; Fourches, Nicolas; Goffe, Mathieu; Himmi, Abdelkader; Li, Yan; Lutz, Pierre; Orsini, Fabienne; Szelezniak, Michal

2006-12-01

We report on the performance of the MIMOSA8 (HiMAPS1) chip. The chip is a 128times32 pixels array where 24 columns have discriminated binary outputs and eight columns analog test outputs. Offset correction techniques are used extensively in this chip to overcome process related mismatches. The array is divided in four blocks of pixels with different conversion factors and is controlled by a serially programmable sequencer. MIMOSA8 is a representative of the CMOS sensors development option considered as a promising candidate for the Vertex Detector of the future International Linear Collider (ILC). The readout technique, implemented on the chip, combines high spatial resolution capabilities with high processing readout speed. Data acquisition, providing control of the chip and signal buffering and linked to a VME system, was made on the eight analog outputs. Analog data, without and with a 55Fe X-ray source, were acquired and processed using off-line analysis software. From the reconstruction of pixel clusters, built around a central pixel, we deduce that the charge spread is limited to the closest 25 pixels and almost all the available charge is collected. The position of the total charge collection peak (and subsequently the charge-to-voltage conversion factor) stays unaffected when the clock frequency is increased even up to 150 MHz (13.6 mus readout time per frame). The discriminators, placed in the readout chain, have proved to be fully functional. Beam tests have been made with high energy electrons at DESY (Germany) to study detection efficiency. The results prove that MIMOSA8 is the first and fastest successful monolithic active pixel sensor with on-chip signal discrimination for detection of MIPs

A Dynamic Linear Hashing Method for Redundancy Management in Train Ethernet Consist Network

Directory of Open Access Journals (Sweden)

Xiaobo Nie

2016-01-01

Full Text Available Massive transportation systems like trains are considered critical systems because they use the communication network to control essential subsystems on board. Critical system requires zero recovery time when a failure occurs in a communication network. The newly published IEC62439-3 defines the high-availability seamless redundancy protocol, which fulfills this requirement and ensures no frame loss in the presence of an error. This paper adopts these for train Ethernet consist network. The challenge is management of the circulating frames, capable of dealing with real-time processing requirements, fast switching times, high throughout, and deterministic behavior. The main contribution of this paper is the in-depth analysis it makes of network parameters imposed by the application of the protocols to train control and monitoring system (TCMS and the redundant circulating frames discarding method based on a dynamic linear hashing, using the fastest method in order to resolve all the issues that are dealt with.

arXiv The MuPix System-on-Chip for the Mu3e Experiment

CERN Document Server

Augustin, Heiko

2017-02-11

Mu3e is a novel experiment searching for charged lepton flavor violation in the rare decay $\\mu^+ \\rightarrow e^+e^-e^+$. Decay vertex position, decay time and particle momenta have to be precisely measured in order to reject both accidental and physics background. A silicon pixel tracker based on $50\\,\\mu$m thin high voltage monolithic active pixel sensors (HV-MAPS) in a 1 T solenoidal magnetic field provides precise vertex and momentum information. The MuPix chip combines pixel sensor cells with integrated analog electronics and a periphery with a complete digital readout. The MuPix7 is the first HV-MAPS prototype implementing all functionalities of the final sensor including a readout state machine and high speed serialization with 1.25 Gbit/s data output, allowing for a streaming readout in parallel to the data taking. The observed efficiency of the MuPix7 chip including the full readout system is $\\geq99\\%$ in a high rate test beam.

Research on the tool holder mode in high speed machining

Science.gov (United States)

Zhenyu, Zhao; Yongquan, Zhou; Houming, Zhou; Xiaomei, Xu; Haibin, Xiao

2018-03-01

High speed machining technology can improve the processing efficiency and precision, but also reduce the processing cost. Therefore, the technology is widely regarded in the industry. With the extensive application of high-speed machining technology, high-speed tool system has higher and higher requirements on the tool chuck. At present, in high speed precision machining, several new kinds of clip heads are as long as there are heat shrinkage tool-holder, high-precision spring chuck, hydraulic tool-holder, and the three-rib deformation chuck. Among them, the heat shrinkage tool-holder has the advantages of high precision, high clamping force, high bending rigidity and dynamic balance, etc., which are widely used. Therefore, it is of great significance to research the new requirements of the machining tool system. In order to adapt to the requirement of high speed machining precision machining technology, this paper expounds the common tool holder technology of high precision machining, and proposes how to select correctly tool clamping system in practice. The characteristics and existing problems are analyzed in the tool clamping system.

High-speed photodetectors in optical communication system

Science.gov (United States)

Zhao, Zeping; Liu, Jianguo; Liu, Yu; Zhu, Ninghua

2017-12-01

This paper presents a review and discussion for high-speed photodetectors and their applications on optical communications and microwave photonics. A detailed and comprehensive demonstration of high-speed photodetectors from development history, research hotspots to packaging technologies is provided to the best of our knowledge. A few typical applications based on photodetectors are also illustrated, such as free-space optical communications, radio over fiber and millimeter terahertz signal generation systems. Project supported by the Preeminence Youth Fund of China (No. 61625504).

Analysis and topology optimization design of high-speed driving spindle

Science.gov (United States)

Wang, Zhilin; Yang, Hai

2018-04-01

The three-dimensional model of high-speed driving spindle is established by using SOLIDWORKS. The model is imported through the interface of ABAQUS, A finite element analysis model of high-speed driving spindle was established by using spring element to simulate bearing boundary condition. High-speed driving spindle for the static analysis, the spindle of the stress, strain and displacement nephogram, and on the basis of the results of the analysis on spindle for topology optimization, completed the lightweight design of high-speed driving spindle. The design scheme provides guidance for the design of axial parts of similar structures.

HIGH SPEED RAILWAY LINES – FUTURE PART OF CZECH RAILWAY NETWORK?

Directory of Open Access Journals (Sweden)

Lukáš Týfa

2017-08-01

Full Text Available The paper first describes high speed rail generally and explains the relationship between high speed and conventional railway networks (according to the vehicle types in operation on the network. The core of the paper is comprised of the methodology for choosing the best route for a railway line and its application to the high speed railway connection Praha – Brno. The Algorithm used assumes the existence of more route proposals, which could be different in terms of the operational conception, line routing or types of vehicles used. The optimal variant is the one with the lowest daily cost, which includes infrastructure and vehicle costs; investment and operational costs. The results from applying this model confirmed the assumption, that a dedicated high speed railway line, only for high speed trains, has the same or lower investment costs than a line for both high speed and conventional trains. Furthermore, a dedicated high line also has a lower cost for infrastructure maintenance but a higher cost for buying high speed multiple units.

Proposal of a high rigidity and high speed rotating mechanism using a new concept hydrodynamic bearing in X-ray tube for high speed computed tomography

International Nuclear Information System (INIS)

Hattori, Hitoshi; Fukushima, Harunobu; Yoshii, Yasuo; Nakamuta, Hironori; Iwase, Mitsuo; Kitade, Koichi

2009-01-01

In this paper, a high rigidity and high speed rotating mechanism using a new concept hydrodynamic bearing in X-ray tube for high speed computed tomography is proposed. In order to obtain both the stability and the high load carrying capacity, the hydrodynamic bearing lubricated by liquid metal (Gallium alloy), named as the hybrid hydrodynamic bearing generates the lubricating film by wedge effect on the plane region between the spiral grooves under high loading condition. The parallelism between the bearing and the rotating body can be secured by optimizing the rigidity distribution of stationary shaft in the proposed rotating mechanism. By carrying out the fundamental design by numerical analyses, it has been made clear that the hybrid hydrodynamic bearing and the rotating mechanism are suitable for the X-ray tube used in the CT with ever-increasingly scanning speed. (author)

Application of Fabry-Perot velocimeter to high-speed experiments

International Nuclear Information System (INIS)

Chaw, H.H.; McMillan, C.F.; Osher, J.E.

1988-01-01

The Fabry-Perot (F-P) velocimeter is a useful instrument for measuring the velocity of objects at speeds ranging from fractions of a kilometer per second to a few tens of kilometers per second and up. Because of its immunity to electromagnetic interference and its velocity resolution, it has become the prime diagnostic tool in our electric-gun facility. Examples of its application to high speed experiments are discussed, including: electric-gun flyer studies, spallation of materials under high-speed impact, momentum-transfer studies, pressure pulse created by high-velocity impact, and detonation-wave studies in high-explosive experiments

Application of polarization in high speed, high contrast inspection

Science.gov (United States)

Novak, Matthew J.

2017-08-01

Industrial optical inspection often requires high speed and high throughput of materials. Engineers use a variety of techniques to handle these inspection needs. Some examples include line scan cameras, high speed multi-spectral and laser-based systems. High-volume manufacturing presents different challenges for inspection engineers. For example, manufacturers produce some components in quantities of millions per month, per week or even per day. Quality control of so many parts requires creativity to achieve the measurement needs. At times, traditional vision systems lack the contrast to provide the data required. In this paper, we show how dynamic polarization imaging captures high contrast images. These images are useful for engineers to perform inspection tasks in some cases where optical contrast is low. We will cover basic theory of polarization. We show how to exploit polarization as a contrast enhancement technique. We also show results of modeling for a polarization inspection application. Specifically, we explore polarization techniques for inspection of adhesives on glass.

High speed network sampling

OpenAIRE

Rindalsholt, Ole Arild

2005-01-01

Master i nettverks- og systemadministrasjon Classical Sampling methods play an important role in the current practice of Internet measurement. With today’s high speed networks, routers cannot manage to generate complete Netflow data for every packet. They have to perform restricted sampling. This thesis summarizes some of the most important sampling schemes and their applications before diving into an analysis on the effect of sampling Netflow records.

A High-Voltage SOI CMOS Exciter Chip for a Programmable Fluidic Processor System.

Science.gov (United States)

Current, K W; Yuk, K; McConaghy, C; Gascoyne, P R C; Schwartz, J A; Vykoukal, J V; Andrews, C

2007-06-01

A high-voltage (HV) integrated circuit has been demonstrated to transport fluidic droplet samples on programmable paths across the array of driving electrodes on its hydrophobically coated surface. This exciter chip is the engine for dielectrophoresis (DEP)-based micro-fluidic lab-on-a-chip systems, creating field excitations that inject and move fluidic droplets onto and about the manipulation surface. The architecture of this chip is expandable to arrays of N X N identical HV electrode driver circuits and electrodes. The exciter chip is programmable in several senses. The routes of multiple droplets may be set arbitrarily within the bounds of the electrode array. The electrode excitation waveform voltage amplitude, phase, and frequency may be adjusted based on the system configuration and the signal required to manipulate a particular fluid droplet composition. The voltage amplitude of the electrode excitation waveform can be set from the minimum logic level up to the maximum limit of the breakdown voltage of the fabrication technology. The frequency of the electrode excitation waveform can also be set independently of its voltage, up to a maximum depending upon the type of droplets that must be driven. The exciter chip can be coated and its oxide surface used as the droplet manipulation surface or it can be used with a top-mounted, enclosed fluidic chamber consisting of a variety of materials. The HV capability of the exciter chip allows the generated DEP forces to penetrate into the enclosed chamber region and an adjustable voltage amplitude can accommodate a variety of chamber floor thicknesses. This demonstration exciter chip has a 32 x 32 array of nominally 100 V electrode drivers that are individually programmable at each time point in the procedure to either of two phases: 0deg and 180deg with respect to the reference clock. For this demonstration chip, while operating the electrodes with a 100-V peak-to-peak periodic waveform, the maximum HV electrode

Transparent Nanopore Cavity Arrays Enable Highly Parallelized Optical Studies of Single Membrane Proteins on Chip.

Science.gov (United States)

Diederichs, Tim; Nguyen, Quoc Hung; Urban, Michael; Tampé, Robert; Tornow, Marc

2018-06-13

Membrane proteins involved in transport processes are key targets for pharmaceutical research and industry. Despite continuous improvements and new developments in the field of electrical readouts for the analysis of transport kinetics, a well-suited methodology for high-throughput characterization of single transporters with nonionic substrates and slow turnover rates is still lacking. Here, we report on a novel architecture of silicon chips with embedded nanopore microcavities, based on a silicon-on-insulator technology for high-throughput optical readouts. Arrays containing more than 14 000 inverted-pyramidal cavities of 50 femtoliter volumes and 80 nm circular pore openings were constructed via high-resolution electron-beam lithography in combination with reactive ion etching and anisotropic wet etching. These cavities feature both, an optically transparent bottom and top cap. Atomic force microscopy analysis reveals an overall extremely smooth chip surface, particularly in the vicinity of the nanopores, which exhibits well-defined edges. Our unprecedented transparent chip design provides parallel and independent fluorescent readout of both cavities and buffer reservoir for unbiased single-transporter recordings. Spreading of large unilamellar vesicles with efficiencies up to 96% created nanopore-supported lipid bilayers, which are stable for more than 1 day. A high lipid mobility in the supported membrane was determined by fluorescent recovery after photobleaching. Flux kinetics of α-hemolysin were characterized at single-pore resolution with a rate constant of 0.96 ± 0.06 × 10 -3 s -1 . Here, we deliver an ideal chip platform for pharmaceutical research, which features high parallelism and throughput, synergistically combined with single-transporter resolution.

High Speed On-Wafer Characterization Laboratory

Data.gov (United States)

Federal Laboratory Consortium — At the High Speed On-Wafer Characterization Laboratory, researchers characterize and model devices operating at terahertz (THz) and millimeter-wave frequencies. The...

High-speed Maglev studies in Canada

International Nuclear Information System (INIS)

Atherton, D.L.; Eastham, A.R.

1974-01-01

This paper reports on Canadian studies of superconducting magnetic levitation and variable-speed linear synchronous motor propulsion for high-speed inter-city guided ground transport. Levitation is obtained by the interaction of vehicle-mounted superconducting magnets and the eddy currents induced in aluminium strip conductors on the guideway. Non-contact propulsion by linear synchronous motor (LSM) is obtained by using vehicle-borne superconducting magnets and powered guideway coils. A suggested guidance scheme uses a flat guideway with 'null-flux' loops overlying the LSM windings. The propulsion magnets interact with the loops and the edges of the levitation strips to provide lateral stabilization. The test facility is a 7.6m wheel, rotating with a peripheral speed of 33m/s. (author)

High-speed nonvolatile CMOS/MNOS RAM

International Nuclear Information System (INIS)

Derbenwick, G.F.; Dodson, W.D.; Sokel, R.J.

1979-01-01

A bulk silicon technology for a high-speed static CMOS/MNOS RAM has been developed. Radiation-hardened, high voltage CMOS circuits have been fabricated for the memory array driving circuits and the enhancement-mode p-channel MNOS memory transistors have been fabricated using a native tunneling oxide with a 45 nm CVD Si 3 N 4 insulator deposited at 750 0 C. Read cycle times less than 350 ns and write cycle times of 1 μs are projected for the final 1Kx1 design. The CMOS circuits provide adequate speed for the write and read cycles and minimize the standby power dissipation. Retention times well in excess of 30 min are projected

High-speed cryptography and cryptanalysis

NARCIS (Netherlands)

Schwabe, P.

2011-01-01

Modern digital communication relies heavily on cryptographic protection to ensure data integrity and privacy. In order to deploy state-of-the art cryptographic primitives and protocols in real-world scenarios, one needs to highly optimize software for both speed and security. This requires careful

Advancing high-speed rail policy in the United States.

Science.gov (United States)

2012-06-01

This report builds on a review of international experience with high-speed rail projects to develop recommendations for a High-speed rail policy framework for the United States. The international review looked at the experience of Korea, Taiwan, Chin...

Design and applications of a pneumatic accelerator for high speed punching

International Nuclear Information System (INIS)

Yaldiz, Sueleyman; Saglam, Haci; Unsacar, Faruk; Isik, Hakan

2007-01-01

High speed forming is an important production method that requires specially designed HERF (high energy rate forming) machines. Most of the HERF machines are devices that consist of a system in which energy is stored and a differential piston mechanism is used to release the energy at high rate. In order to eliminate the usage of specially designed HERF machines and to obtain the high speed forming benefits, the accelerator which can be adapted easily onto conventional presses has been designed and manufactured in this study. The designed energy accelerator can be incorporated into mechanical press to convert the low speed operation into high-speed operation of a hammer. Expectations from this work are reduced distortion rates, increased surface quality and precise dimensions in metal forming operations. From the performance test, the accelerator is able to achieve high speed and energy which require for high speed blanking of thick sheet metals

Assessment of rural soundscapes with high-speed train noise.

Science.gov (United States)

Lee, Pyoung Jik; Hong, Joo Young; Jeon, Jin Yong

2014-06-01

In the present study, rural soundscapes with high-speed train noise were assessed through laboratory experiments. A total of ten sites with varying landscape metrics were chosen for audio-visual recording. The acoustical characteristics of the high-speed train noise were analyzed using various noise level indices. Landscape metrics such as the percentage of natural features (NF) and Shannon's diversity index (SHDI) were adopted to evaluate the landscape features of the ten sites. Laboratory experiments were then performed with 20 well-trained listeners to investigate the perception of high-speed train noise in rural areas. The experiments consisted of three parts: 1) visual-only condition, 2) audio-only condition, and 3) combined audio-visual condition. The results showed that subjects' preference for visual images was significantly related to NF, the number of land types, and the A-weighted equivalent sound pressure level (LAeq). In addition, the visual images significantly influenced the noise annoyance, and LAeq and NF were the dominant factors affecting the annoyance from high-speed train noise in the combined audio-visual condition. In addition, Zwicker's loudness (N) was highly correlated with the annoyance from high-speed train noise in both the audio-only and audio-visual conditions. © 2013.

Prototyping of thermoplastic microfluidic chips and their application in high-performance liquid chromatography separations of small molecules.

Science.gov (United States)

Wouters, Sam; De Vos, Jelle; Dores-Sousa, José Luís; Wouters, Bert; Desmet, Gert; Eeltink, Sebastiaan

2017-11-10

The present paper discusses practical aspects of prototyping of microfluidic chips using cyclic olefin copolymer as substrate and the application in high-performance liquid chromatography. The developed chips feature a 60mm long straight separation channel with circular cross section (500μm i.d.) that was created using a micromilling robot. To irreversibly seal the top and bottom chip substrates, a solvent-vapor-assisted bonding approach was optimized, allowing to approximate the ideal circular channel geometry. Four different approaches to establish the micro-to-macro interface were pursued. The average burst pressure of the microfluidic chips in combination with an encasing holder was established at 38MPa and the maximum burst pressure was 47MPa, which is believed to be the highest ever report for these polymer-based microfluidic chips. Porous polymer monolithic frits were synthesized in-situ via UV-initiated polymerization and their locations were spatially controlled by the application of a photomask. Next, high-pressure slurry packing was performed to introduce 3μm silica reversed-phase particles as the stationary phase in the separation channel. Finally, the application of the chip technology is demonstrated for the separation of alkyl phenones in gradient mode yielding baseline peak widths of 6s by applying a steep gradient of 1.8min at a flow rate of 10μL/min. Copyright © 2017 Elsevier B.V. All rights reserved.

High-speed imaging of explosive eruptions: applications and perspectives

Science.gov (United States)

Taddeucci, Jacopo; Scarlato, Piergiorgio; Gaudin, Damien; Capponi, Antonio; Alatorre-Ibarguengoitia, Miguel-Angel; Moroni, Monica

2013-04-01

Explosive eruptions, being by definition highly dynamic over short time scales, necessarily call for observational systems capable of relatively high sampling rates. "Traditional" tools, like as seismic and acoustic networks, have recently been joined by Doppler radar and electric sensors. Recent developments in high-speed camera systems now allow direct visual information of eruptions to be obtained with a spatial and temporal resolution suitable for the analysis of several key eruption processes. Here we summarize the methods employed to gather and process high-speed videos of explosive eruptions, and provide an overview of the several applications of these new type of data in understanding different aspects of explosive volcanism. Our most recent set up for high-speed imaging of explosive eruptions (FAMoUS - FAst, MUltiparametric Set-up,) includes: 1) a monochrome high speed camera, capable of 500 frames per second (fps) at high-definition (1280x1024 pixel) resolution and up to 200000 fps at reduced resolution; 2) a thermal camera capable of 50-200 fps at 480-120x640 pixel resolution; and 3) two acoustic to infrasonic sensors. All instruments are time-synchronized via a data logging system, a hand- or software-operated trigger, and via GPS, allowing signals from other instruments or networks to be directly recorded by the same logging unit or to be readily synchronized for comparison. FAMoUS weights less than 20 kg, easily fits into four, hand-luggage-sized backpacks, and can be deployed in less than 20' (and removed in less than 2', if needed). So far, explosive eruptions have been recorded in high-speed at several active volcanoes, including Fuego and Santiaguito (Guatemala), Stromboli (Italy), Yasur (Vanuatu), and Eyjafiallajokull (Iceland). Image processing and analysis from these eruptions helped illuminate several eruptive processes, including: 1) Pyroclasts ejection. High-speed videos reveal multiple, discrete ejection pulses within a single Strombolian

High-speed microjet generation using laser-induced vapor bubbles

Science.gov (United States)

Oudalov, Nikolai; Tagawa, Yoshiyuki; Peters, Ivo; Visser, Claas-Willem; van der Meer, Devaraj; Prosperetti, Andrea; Sun, Chao; Lohse, Detlef

2011-11-01

The generation and evolution of microjets are studied both experimentally and numerically. The jets are generated by focusing a laser pulse into a microscopic capillary tube (~50 μm) filled with water-based red dye. A vapor bubble is created instantly after shooting the laser (<1 μs), sending out a shockwave towards the curved free surface at which the high-speed microjet forms. The process of jet formation is captured using high-speed recordings at 1.0 × 106 fps. The velocity of the microjets can reach speeds of ~850 m/s while maintaining a very sharp geometry. The high-speed recordings enable us to study the effect of several parameters on the jet velocity, e.g. the absorbed energy and the distance between the laser spot and the free surface.The results show a clear dependence on these variables, even for supersonic speeds. Comparisons with numerical simulations confirm the nature of these dependencies.

DIVERSITY in binding, regulation, and evolution revealed from high-throughput ChIP.

Science.gov (United States)

Mitra, Sneha; Biswas, Anushua; Narlikar, Leelavati

2018-04-23

Genome-wide in vivo protein-DNA interactions are routinely mapped using high-throughput chromatin immunoprecipitation (ChIP). ChIP-reported regions are typically investigated for enriched sequence-motifs, which are likely to model the DNA-binding specificity of the profiled protein and/or of co-occurring proteins. However, simple enrichment analyses can miss insights into the binding-activity of the protein. Note that ChIP reports regions making direct contact with the protein as well as those binding through intermediaries. For example, consider a ChIP experiment targeting protein X, which binds DNA at its cognate sites, but simultaneously interacts with four other proteins. Each of these proteins also binds to its own specific cognate sites along distant parts of the genome, a scenario consistent with the current view of transcriptional hubs and chromatin loops. Since ChIP will pull down all X-associated regions, the final reported data will be a union of five distinct sets of regions, each containing binding sites of one of the five proteins, respectively. Characterizing all five different motifs and the corresponding sets is important to interpret the ChIP experiment and ultimately, the role of X in regulation. We present diversity which attempts exactly this: it partitions the data so that each partition can be characterized with its own de novo motif. Diversity uses a Bayesian approach to identify the optimal number of motifs and the associated partitions, which together explain the entire dataset. This is in contrast to standard motif finders, which report motifs individually enriched in the data, but do not necessarily explain all reported regions. We show that the different motifs and associated regions identified by diversity give insights into the various complexes that may be forming along the chromatin, something that has so far not been attempted from ChIP data. Webserver at http://diversity.ncl.res.in/; standalone (Mac OS X/Linux) from https

High Availability of RAPIENET

International Nuclear Information System (INIS)

Yoon, G.; Oh, J. S.; Kwon, D. H.; Kwon, S. C.; Park, Y. O.

2012-01-01

Many industrial customers are no longer satisfies with conventional Ethernet-based communications. They require a more accurate, more flexible, and more reliable technology for their control and measurement systems. Hence, Ethernet-based high-availability networks are becoming an important topic in the control and measurement fields. In this paper, we introduce a new redundant programmable logic controller (PLC) concept, based on real-time automation protocols for industrial Ethernet (RAPIEnet). RAPIEnet has intrinsic redundancy built into its network topology, with hardware-based recovery time. We define a redundant PLC system switching model and demonstrate its performance, including RAPIEnet recovery time

A multi-chip module for physics experiments

CERN Document Server

Benso, A; Giovannetti, S; Mariani, R; Motto, S; Prinetto, P

1999-01-01

MCMs are widely adopted as assembly solutions for multi-die based systems, where area, performance, and costs are critical constraints. This paper describes both the project strategies and production flow that are to be adopted to realize an MCM-D for data acquisition in high-energy physics experiments. The activity starts from the results of RD/16 CERN project, and is part of the LAP Esprit project. The paper details the most critical issues faced in the production phase, and analyzes how they influenced system partitioning and component design. Moreover, it presents the design-for-testability methodologies adopted at both chip and MCM levels to achieve low defect levels and high production yields, minimizing the overhead in terms of system performance and area occupation. This work should demonstrate the feasibility of the MCM technology in such high speed data processing systems, where both size and cost constraints are important. (10 refs).

High speed railway track dynamics models, algorithms and applications

CERN Document Server

Lei, Xiaoyan

2017-01-01

This book systematically summarizes the latest research findings on high-speed railway track dynamics, made by the author and his research team over the past decade. It explores cutting-edge issues concerning the basic theory of high-speed railways, covering the dynamic theories, models, algorithms and engineering applications of the high-speed train and track coupling system. Presenting original concepts, systematic theories and advanced algorithms, the book places great emphasis on the precision and completeness of its content. The chapters are interrelated yet largely self-contained, allowing readers to either read through the book as a whole or focus on specific topics. It also combines theories with practice to effectively introduce readers to the latest research findings and developments in high-speed railway track dynamics. It offers a valuable resource for researchers, postgraduates and engineers in the fields of civil engineering, transportation, highway & railway engineering.

Plasma-Assisted Chemistry in High-Speed Flow

International Nuclear Information System (INIS)

Leonov, Sergey B.; Yarantsev, Dmitry A.; Napartovich, Anatoly P.; Kochetov, Igor V.

2007-01-01

Fundamental problems related to the high-speed combustion are analyzed. The result of plasma-chemical modeling is presented as a motivation of experimental activity. Numerical simulations of the effect of uniform non-equilibrium discharge on the premixed hydrogen and ethylene-air mixture in supersonic flow demonstrate an advantage of such a technique over a heating. Experimental results on multi-electrode non-uniform discharge maintenance behind wallstep and in cavity of supersonic flow are presented. The model test on hydrogen and ethylene ignition is demonstrated at direct fuel injection to low-temperature high-speed airflow

Thermomechanical simulations and experimental validation for high speed incremental forming

Science.gov (United States)

Ambrogio, Giuseppina; Gagliardi, Francesco; Filice, Luigino; Romero, Natalia

2016-10-01

Incremental sheet forming (ISF) consists in deforming only a small region of the workspace through a punch driven by a NC machine. The drawback of this process is its slowness. In this study, a high speed variant has been investigated from both numerical and experimental points of view. The aim has been the design of a FEM model able to perform the material behavior during the high speed process by defining a thermomechanical model. An experimental campaign has been performed by a CNC lathe with high speed to test process feasibility. The first results have shown how the material presents the same performance than in conventional speed ISF and, in some cases, better material behavior due to the temperature increment. An accurate numerical simulation has been performed to investigate the material behavior during the high speed process confirming substantially experimental evidence.

High Speed Photomicrography

Science.gov (United States)

Hyzer, William G.

1983-03-01

One of the most challenging areas in applying high-speed photography and videography in the plant and laboratory is in the recording of rapid events at macro and microscopic scales. Depth of field, exposure efficiency, working distance, and required exposure time are all reduced as optical magnification is increased, which severely taxes the skill and ingenuity of workers interested in recording any fast moving phenomena through the microscope or with magnifying lenses. This paper defines the problems inherent in photographing within macro and microscopic ranges and offers a systematic approach to optimizing the selection of equipment and choice of applicable techniques.

Material requirements for the High Speed Civil Transport

Science.gov (United States)

Stephens, Joseph R.; Hecht, Ralph J.; Johnson, Andrew M.

1993-01-01

Under NASA-sponsored High Speed Research (HSR) programs, the materials and processing requirements have been identified for overcoming the environmental and economic barriers of the next generation High Speed Civil Transport (HSCT) propulsion system. The long (2 to 5 hours) supersonic cruise portion of the HSCT cycle will place additional durability requirements on all hot section engine components. Low emissions combustor designs will require high temperature ceramic matrix composite liners to meet an emission goal of less than 5g NO(x) per Kg fuel burned. Large axisymmetric and two-dimensional exhaust nozzle designs are now under development to meet or exceed FAR 36 Stage III noise requirements, and will require lightweight, high temperature metallic, intermetallic, and ceramic matrix composites to reduce nozzle weight and meet structural and acoustic component performance goals. This paper describes and discusses the turbomachinery, combustor, and exhaust nozzle requirements of the High Speed Civil Transport propulsion system.

Addressing On-Chip Power Converstion and Dissipation Issues in Many-Core System-on-a-Chip Based on Conventional Silicon and Emerging Nanotechnologies

Science.gov (United States)

Ashenafi, Emeshaw

regulator design very unattractive for SOC integration and multi-/many-core environments. To circumvent the challenges, three alternative techniques based on active circuit elements to replace the passive LC filter of the buck convertor are developed. The first inductorless on-chip switching voltage regulator architecture is based on a cascaded 2nd order multiple feedback (MFB) low-pass filter (LPF). This design has the ability to modulate to multiple voltage settings via pulse-with modulation (PWM). The second approach is a supplementary design utilizing a hybrid low drop-out scheme to lower the output ripple of the switching regulator over a wider frequency range. The third design approach allows the integration of an entire power management system within a single chipset by combining a highly efficient switching regulator with an intermittently efficient linear regulator (area efficient), for robust and highly efficient on-chip regulation. The static power (Pstatic) or subthreshold leakage power (Pleak) increases with technology scaling. To mitigate static power dissipation, power gating techniques are implemented. Power gating is one of the popular methods to manage leakage power during standby periods in low-power high-speed IC design. It works by using transistor based switches to shut down part of the circuit block and put them in the idle mode. The efficiency of a power gating scheme involves minimum Ioff and high Ion for the sleep transistor. A conventional sleep transistor circuit design requires an additional header, footer, or both switches to turn off the logic block. This additional transistor causes signal delay and increases the chip area. We propose two innovative designs for next generation sleep transistor designs. For an above threshold operation, we present a sleep transistor design based on fully depleted silicon-on-insulator (FDSOI) device. For a subthreshold circuit operation, we implement a sleep transistor utilizing the newly developed silicon

High-Speed Sealift Technology Development Plan

National Research Council Canada - National Science Library

2002-01-01

.... The purpose of the project was to define the technology investments required to enable development of the high-speed commercial and military ships needed to provide realistic future mission capabilities...

Diagnostics of high-speed streams and coronal holes using geomagnetic pulsations

International Nuclear Information System (INIS)

Bol'shakova, O.V.; Troitskaya, V.A.

1980-01-01

In order to study the relations of high-speed solar wind streams and coronal holes analyzed are the parameters of geomagnetic pulsations of the Rs3 type and of high-speed streams at the decrease branch and in the minimum of solar activity. On the basis of the analysis of exciting pulsation regime determined are the differences in characteristics of high-speed stream properties. Presented are the graphical distributions of a number of occurrances of high-speed streams, coronal holes and pure regimes of Rs3R pulsations in several sections of 1973 in the Sun rotations of N1903-1919 and of the change of solar wind velocity while passing through the high-speed streams. It is found that Rs3R occurrance can serve an indicator of the high-speed flux connection with the large equatorial coronal hole. On the basis of the analysis of exciting pulsation properties determined are the differences in the stream characteristics. However the preliminary estimates permit to adopt neither the first nor the second of the existing hypotheses on the sourse of formation of high-speed streams

Optimal design of high-speed loading spindle based on ABAQUS

Science.gov (United States)

Yang, Xudong; Dong, Yu; Ge, Qingkuan; Yang, Hai

2017-12-01

The three-dimensional model of high-speed loading spindle is established by using ABAQUS’s modeling module. A finite element analysis model of high-speed loading spindle was established by using spring element to simulate bearing boundary condition. The static and dynamic performance of the spindle structure with different specifications of the rectangular spline and the different diameter neck of axle are studied in depth, and the influence of different spindle span on the static and dynamic performance of the high-speed loading spindle is studied. Finally, the optimal structure of the high-speed loading spindle is obtained. The results provide a theoretical basis for improving the overall performance of the test-bed

Thin film metal sensors in fusion bonded glass chips for high-pressure microfluidics

International Nuclear Information System (INIS)

Andersson, Martin; Ek, Johan; Hedman, Ludvig; Johansson, Fredrik; Sehlstedt, Viktor; Stocklassa, Jesper; Snögren, Pär; Pettersson, Victor; Larsson, Jonas; Vizuete, Olivier; Hjort, Klas; Klintberg, Lena

2017-01-01

High-pressure microfluidics offers fast analyses of thermodynamic parameters for compressed process solvents. However, microfluidic platforms handling highly compressible supercritical CO 2 are difficult to control, and on-chip sensing would offer added control of the devices. Therefore, there is a need to integrate sensors into highly pressure tolerant glass chips. In this paper, thin film Pt sensors were embedded in shallow etched trenches in a glass wafer that was bonded with another glass wafer having microfluidic channels. The devices having sensors integrated into the flow channels sustained pressures up to 220 bar, typical for the operation of supercritical CO 2 . No leakage from the devices could be found. Integrated temperature sensors were capable of measuring local decompression cooling effects and integrated calorimetric sensors measured flow velocities over the range 0.5–13.8 mm s −1 . By this, a better control of high-pressure microfluidic platforms has been achieved. (paper)

Photonic network-on-chip design

CERN Document Server

Bergman, Keren; Biberman, Aleksandr; Chan, Johnnie; Hendry, Gilbert

2013-01-01

This book provides a comprehensive synthesis of the theory and practice of photonic devices for networks-on-chip. It outlines the issues in designing photonic network-on-chip architectures for future many-core high performance chip multiprocessors. The discussion is built from the bottom up: starting with the design and implementation of key photonic devices and building blocks, reviewing networking and network-on-chip theory and existing research, and finishing with describing various architectures, their characteristics, and the impact they will have on a computing system. After acquainting

Optical lattice on an atom chip

DEFF Research Database (Denmark)

Gallego, D.; Hofferberth, S.; Schumm, Thorsten

2009-01-01

Optical dipole traps and atom chips are two very powerful tools for the quantum manipulation of neutral atoms. We demonstrate that both methods can be combined by creating an optical lattice potential on an atom chip. A red-detuned laser beam is retroreflected using the atom chip surface as a high......-quality mirror, generating a vertical array of purely optical oblate traps. We transfer thermal atoms from the chip into the lattice and observe cooling into the two-dimensional regime. Using a chip-generated Bose-Einstein condensate, we demonstrate coherent Bloch oscillations in the lattice....

Comprehensive surface treatment of high-speed steel tool

Science.gov (United States)

Fedorov, Sergey V.; Aleshin, Sergey V.; Swe, Min Htet; Abdirova, Raushan D.; Kapitanov, Alexey V.; Egorov, Sergey B.

2018-03-01

One of the promising directions of hardening of high-speed steel tool is the creation on their surface of the layered structures with the gradient of physic-chemical properties between the wear-resistant coatings to the base material. Among the methods of such surface modification, a special process takes place based on the use of pulsed high-intensity charged particle beams. The high speed of heating and cooling allows structural-phase transformations in the surface layer, which cannot be realized in a stationary mode. The treatment was conducted in a RITM-SP unit, which constitutes a combination of a source of low-energy high-current electron beams "RITM" and two magnetron spraying systems on a single vacuum chamber. The unit enables deposition of films on the surface of the desired product and subsequent liquid-phase mixing of materials of the film and the substrate by an intense pulse electron beam. The article discusses features of the structure of the subsurface layer of high-speed steel M2, modified by surface alloying of a low-energy high-current electron beam, and its effect on the wear resistance of the tool when dry cutting hard to machine Nickel alloy. A significant decrease of intensity of wear of high-speed steel with combined treatment happens due to the displacement of the zone of wear and decrease the radius of rounding of the cutting edge because of changes in conditions of interaction with the material being treated.

Experimental study of the chip morphology in turning hardened AISI D2 steel