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Sample records for charge-to-time converter asic

  1. High-speed charge-to-time converter ASIC for the Super-Kamiokande detector

    CERN Document Server

    Nishino, H; Hayato, Y; Nakayama, S; Okumura, K; Shiozawa, M; Takeda, A; Ishikawa, K; Minegishi, A; Arai, Y; 10.1016/j.nima.2009.09.026

    2009-01-01

    A new application-specific integrated circuit (ASIC), the high-speed charge-to-time converter (QTC) IWATSU CLC101, provides three channels, each consisting of preamplifier, discriminator, low-pass filter, and charge integration circuitry, optimized for the waveform of a photomultiplier tube (PMT). This ASIC detects PMT signals using individual built-in discriminators and drives output timing signals whose width represents the integrated charge of the PMT signal. Combined with external input circuits composed of passive elements, the QTC provides full analog signal processing for the detector's PMTs, ready for further processing by time-to-digital converters (TDCs). High-rate (>1MHz) signal processing is achieved by short-charge-conversion-time and baseline-restoration circuits. Wide-range charge measurements are enabled by offering three gain ranges while maintaining a short cycle time. QTC chip test results show good analog performance, with efficient detection for a single photoelectron signal, four orders ...

  2. Method of signal detection from silicon photomultipliers using fully differential Charge to Time Converter and fast shaper

    Science.gov (United States)

    Baszczyk, M.; Dorosz, P.; Glab, S.; Kucewicz, W.; Mik, L.; Sapor, M.

    2016-07-01

    The paper presents an implementation of fully differential readout method for Silicon Photomultipliers (SiPM). Front-end electronics consists of a fast and slow path. The former creates the trigger signal while the latter produces a pulse of width proportional to the input charge. The fast shaper generates unipolar pulse and utilizes the pole-zero cancelation circuit. The peaking time for single photoelectron is equal to 3.6 ns and the FWHM is 3.8 ns. The pulse width of the Charge to Time Converter (QTC) depends on the number of photons entering the SiPM at the moment of measurement. The QTC response is nonlinear but it allows us to work with signals in a wide dynamic range. The proposed readout method is effective in measurements of random signals where frequent events tend to pile-up. Thermal generation and afterpulses have a strong influence on the width of pulses from QTC. The proposed method enables us to distinguish those overlapping signals and get the reliable information on the number of detected photons.

  3. A multichannel time-to-digital converter ASIC with better than 3 ps RMS time resolution

    International Nuclear Information System (INIS)

    The development of a new multichannel, fine-time resolution time-to-digital converter (TDC) ASIC is currently under development at CERN. A prototype TDC has been designed, fabricated and successfully verified with demonstrated time resolutions of better than 3 ps-rms. Least-significant-bit (LSB) sizes as small as 5 ps with a differential-non-linearity (DNL) of better than ±0.9 LSB and integral-non-linearity (INL) of better than ±1.3 LSB respectively have been achieved. The contribution describes the implemented architecture and presents measurement results of a prototype ASIC implemented in a commercial 130 nm technology

  4. A four channel time-to-digital converter ASIC with in-built calibration and SPI interface

    Energy Technology Data Exchange (ETDEWEB)

    Hari Prasad, K.; Sukhwani, Menka [Electronics Division, Bhabha Atomic Research Center, Mumbai 400085 (India); Saxena, Pooja [Homi Bhabha National Institute, Mumbai 400094 (India); Chandratre, V.B., E-mail: vbc@barc.gov.in [Electronics Division, Bhabha Atomic Research Center, Mumbai 400085 (India); Pithawa, C.K. [Electronics Division, Bhabha Atomic Research Center, Mumbai 400085 (India)

    2014-02-11

    A design of high resolution, wide dynamic range Time-to-Digital Converter (TDC) ASIC, implemented in 0.35 µm commercial CMOS technology is presented. The ASIC features four channel TDC with an in-built calibration and Serial Peripheral Interconnect (SPI) slave interface. The TDC is based on the vernier ring oscillator method in order to achieve both high resolution and wide dynamic range. This TDC ASIC is tested and found to have resolution of 127 ps (LSB), dynamic range of 1.8 µs and precision (σ) of 74 ps. The measured values of differential non-linearity (DNL) and integral non-linearity (INL) are 350 ps and 300 ps respectively.

  5. The Design of an Asic Control Chip for a Forward Active Clamp Converter and the Investigation of Integratable Lateral Power Devices

    OpenAIRE

    Dong, Wei

    1997-01-01

    In Part I, the design of an ASIC control chip for a forward active clamp converter is presented. Integration of the control and drive circuit into one IC chip results in higher power density, higher reliability for the converter module. The designed ASIC control chip uses a 2.0 um N well Analog CMOS process, and is fabricated at MOSIS. The design procedures of the ASIC chip are explained, and experimental results are presented. Part II of the thesis focuses on the numerical investigat...

  6. ASIC and FPGA based DPWM architectures for single-phase and single-output DC-DC converter: a review

    Science.gov (United States)

    Chander, Subhash; Agarwal, Pramod; Gupta, Indra

    2013-12-01

    Pulse width modulation (PWM) has been widely used in power converter control. This paper presents a review of architectures of the Digital Pulse Width Modulators (DPWM) targeting digital control of switching DC-DC converters. An attempt is made to review the reported architectures with emphasis on the ASIC and FPGA implementations in single phase and single-output DC-DC converters. Recent architectures using FPGA's advanced resources for achieving the resolution higher than classical methods have also been discussed. The merits and demerits of different architectures, and their relative comparative performance, are also presented. The Authors intention is to uncover the groundwork and the related references through this review for the benefit of readers and researchers targeting different DPWM architectures for the DC-DC converters.

  7. Switched capacitor DC-DC converter ASICs for the upgraded LHC trackers

    Energy Technology Data Exchange (ETDEWEB)

    Bochenek, M; Faccio, F; Michelis, S [CERN, CH-1211 Geneve 23 (Switzerland); Dabrowski, W, E-mail: Michal.Bochenek@cern.ch [AGH University of Science and Technology, Faculty of Physics and Applied Computer Science, Al. Mickiewicza 30 30-059 Krakow (Poland)

    2010-12-15

    The High Luminosity Upgrade of the ATLAS Inner Tracker puts demanding requirements on the powering system of the silicon strip detector modules due to 10-fold increase of the channel count compared to the existing SemiConductor Tracker. Therefore, new solutions for the powering scheme must be elaborated. Currently two possible approaches, the serial powering and the parallel powering scheme using the DC-DC conversion technique, are under development. This paper describes two switched capacitor DC-DC converters designed in a 130 nm technology. For the optimized step-down converter, foreseen for the parallel powering scheme, power efficiency of 97% has been achieved, while for the charge pump, designed for the serial powering scheme, power efficiency of 85% has been achieved.

  8. Switched capacitor DC-DC converter ASICs for the upgraded LHC trackers

    CERN Document Server

    Bochenek, M; Faccio, F; Michelis, S

    2010-01-01

    The High Luminosity Upgrade of the ATLAS Inner Tracker puts demanding requirements on the powering system of the silicon strip detector modules due to 10-fold increase of the channel count compared to the existing SemiConductor Tracker. Therefore, new solutions for the powering scheme must be elaborated. Currently two possible approaches, the serial powering and the parallel powering scheme using the DC-DC conversion technique, are under development. This paper describes two switched capacitor DC-DC converters designed in a 130 nm technology. For the optimized step-down converter, foreseen for the parallel powering scheme, power efficiency of 97% has been achieved, while for the charge pump, designed for the serial powering scheme, power efficiency of 85% has been achieved

  9. Design and ASIC Implementation of A Converter of A Law and μ Law%一种A率μ率转换器的设计及ASIC实现

    Institute of Scientific and Technical Information of China (English)

    黄海生

    2001-01-01

    根据交换系统的要求,设计了A率μ率转换器ASIC。该转换器具有Intel CPU的接口功能。经硬件实验证实,结果达到设计要求。%According to the requirement of switch system we design an ASIC of converter for A lawand μ law. The converter can interface with Intel CPU.It is proved by hardware experiment that the result can meet requitement of design.

  10. A flexible multi-channel high-resolution time-to-digital converter ASIC

    CERN Document Server

    Mota, M; Debieux, S; Ryzhov, V; Moreira, P; Marchioro, A

    2000-01-01

    A data driven multi-channel Time-to-Digital Converter (TDC) circuit with programmable resolution ( similar to 25ps - 8OOps binning) and a dynamic range of 102.4mus has been implemented in a 0.25mum CMOS technology. An on-chip PLL is used for clock multiplication up to 320MHz from an external 40MHz reference. A 32 element Delay Locked Loop (DLL) performs time interpolation down to 97.5ps. Finally, finer time interpolation is obtained using four samples of the DLL separated by 24.5ps generated by an adjustable on-chip RC delay line. In the lower resolution modes of operation, 32 TDC channels are available. In the highest resolution mode eight channels are available, since four low-resolution channels are used to perform a single fine time interpolation. The TDC is capable of measuring both leading and trailing edges of the input signal. Measurements are initially stored as time stamps in individual four-location deep asynchronous channel buffers. After proper encoding, measurements are written into four 256-dee...

  11. Memory, microprocessor, and ASIC

    CERN Document Server

    Chen, Wai-Kai

    2003-01-01

    System Timing. ROM/PROM/EPROM. SRAM. Embedded Memory. Flash Memories. Dynamic Random Access Memory. Low-Power Memory Circuits. Timing and Signal Integrity Analysis. Microprocessor Design Verification. Microprocessor Layout Method. Architecture. ASIC Design. Logic Synthesis for Field Programmable Gate Array (EPGA) Technology. Testability Concepts and DFT. ATPG and BIST. CAD Tools for BIST/DFT and Delay Faults.

  12. A Readout ASIC for CZT Detectors

    CERN Document Server

    Jones, L

    2008-01-01

    Spectrometers that can identify the energy of gamma radiation and determine the source isotope have until recently used low temperature semiconductors. These require cooling which makes their portability difficult. The material Cadmium Zinc Telluride (CZT) is now available which operates at room temperature and can be used to measure the energy of gamma radiation. In a compton camera configuration the direction of the radiation can also be determined. A read-out ASIC has been developed for such a system and features 100 channels of electronics, each with a charge amplifier, CR-RC shaper, and peak-hold. A 12 bit ADC converts the data which is sparsified before being read out. The energy, signal rise time, and timestamp of any hit channel is read out together with the data from all of its neighbours. The ASIC has a selectable lower dynamic range which could be used for lower energy interactions.

  13. Simultaneous disruption of mouse ASIC1a, ASIC2 and ASIC3 genes enhances cutaneous mechanosensitivity.

    Directory of Open Access Journals (Sweden)

    Sinyoung Kang

    Full Text Available Three observations have suggested that acid-sensing ion channels (ASICs might be mammalian cutaneous mechanoreceptors; they are structurally related to Caenorhabditis elegans mechanoreceptors, they are localized in specialized cutaneous mechanosensory structures, and mechanical displacement generates an ASIC-dependent depolarization in some neurons. However, previous studies of mice bearing a single disrupted ASIC gene showed only subtle or no alterations in cutaneous mechanosensitivity. Because functional redundancy of ASIC subunits might explain limited phenotypic alterations, we hypothesized that disrupting multiple ASIC genes would markedly impair cutaneous mechanosensation. We found the opposite. In behavioral studies, mice with simultaneous disruptions of ASIC1a, -2 and -3 genes (triple-knockouts, TKOs showed increased paw withdrawal frequencies when mechanically stimulated with von Frey filaments. Moreover, in single-fiber nerve recordings of cutaneous afferents, mechanical stimulation generated enhanced activity in A-mechanonociceptors of ASIC TKOs compared to wild-type mice. Responses of all other fiber types did not differ between the two genotypes. These data indicate that ASIC subunits influence cutaneous mechanosensitivity. However, it is unlikely that ASICs directly transduce mechanical stimuli. We speculate that physical and/or functional association of ASICs with other components of the mechanosensory transduction apparatus contributes to normal cutaneous mechanosensation.

  14. Evaluation of a front-end ASIC for the readout of PMTs in large dynamic range

    CERN Document Server

    Wu, Weihao; Liang, Yu; Yu, Li; Liu, Jianfeng; Liu, Shubin; An, Qi

    2015-01-01

    The Large High Altitude Air Shower Observatory (LHAASO) project has been proposed for the survey and study of cosmic rays. In the LHAASO project, the Water Cherenkov Detector Array (WCDA) is one of major detectors for searching gamma ray sources. A Charge-to-Time Convertor (QTC) ASIC (Application Specification Integrated Circuit) fabricated in Global Foundry 0.35 {\\mu}m CMOS technology, has been developed for readout of Photomultiplier Tubes (PMTs) in the WCDA. This paper focuses on the evaluation of this front-end readout ASIC performance. Test results indicate that the time resolution is better than 400 ps and the charge resolution is better than 1% with large input signals and remains better than 15% @ 1 Photo Electron (P.E.), both beyond the application requirement. Moreover, this ASIC has a weak ambient temperature dependence, low input rate dependence and high channel-to-channel isolation.

  15. ASIC-enabled High Resolution Optical Time Domain Reflectometer

    Science.gov (United States)

    Skendzic, Sandra

    Fiber optics has become the preferred technology in communication systems because of what it has to offer: high data transmission rates, immunity to electromagnetic interference, and lightweight, flexible cables. An optical time domain reflectometer (OTDR) provides a convenient method of locating and diagnosing faults (e.g. break in a fiber) along a fiber that can obstruct crucial optical pathways. Both the ability to resolve the precise location of the fault and distinguish between two discrete, closely spaced faults are figures of merit. This thesis presents an implementation of a high resolution OTDR through the use of a compact and programmable ASIC (application specific integrated circuit). The integration of many essential OTDR functions on a single chip is advantageous over existing commercial instruments because it enables small, lightweight packaging, and offers low power and cost efficiency. Furthermore, its compactness presents the option of placing multiple ASICs in parallel, which can conceivably ease the characterization of densely populated fiber optic networks. The OTDR ASIC consists of a tunable clock, pattern generator, precise timer, electrical receiver, and signal sampling circuit. During OTDR operation, the chip generates narrow electrical pulse, which can then be converted to optical format when coupled with an external laser diode driver. The ASIC also works with an external photodetector to measure the timing and amplitude of optical reflections in a fiber. It has a 1 cm sampling resolution, which allows for a 2 cm spatial resolution. While this OTDR ASIC has been previously demonstrated for multimode fiber fault diagnostics, this thesis focuses on extending its functionality to single mode fiber. To validate this novel approach to OTDR, this thesis is divided into five chapters: (1) introduction, (2) implementation, (3), performance of ASIC-based OTDR, (4) exploration in optical pre-amplification with a semiconductor optical amplifier, and

  16. ASIC3 channels in multimodal sensory perception.

    Science.gov (United States)

    Li, Wei-Guang; Xu, Tian-Le

    2011-01-19

    Acid-sensing ion channels (ASICs), which are members of the sodium-selective cation channels belonging to the epithelial sodium channel/degenerin (ENaC/DEG) family, act as membrane-bound receptors for extracellular protons as well as nonproton ligands. At least five ASIC subunits have been identified in mammalian neurons, which form both homotrimeric and heterotrimeric channels. The highly proton sensitive ASIC3 channels are predominantly distributed in peripheral sensory neurons, correlating with their roles in multimodal sensory perception, including nociception, mechanosensation, and chemosensation. Different from other ASIC subunit composing ion channels, ASIC3 channels can mediate a sustained window current in response to mild extracellular acidosis (pH 7.3-6.7), which often occurs accompanied by many sensory stimuli. Furthermore, recent evidence indicates that the sustained component of ASIC3 currents can be enhanced by nonproton ligands including the endogenous metabolite agmatine. In this review, we first summarize the growing body of evidence for the involvement of ASIC3 channels in multimodal sensory perception and then discuss the potential mechanisms underlying ASIC3 activation and mediation of sensory perception, with a special emphasis on its role in nociception. We conclude that ASIC3 activation and modulation by diverse sensory stimuli represent a new avenue for understanding the role of ASIC3 channels in sensory perception. Furthermore, the emerging implications of ASIC3 channels in multiple sensory dysfunctions including nociception allow the development of new pharmacotherapy. PMID:22778854

  17. Characterisation of the NA62 GigaTracker end of column readout ASIC

    CERN Document Server

    Noy, M; Perktold, L; Rinella, G A; Riedler, P; Morel, M; Kluge, A; Kaplon, J; Martin, E; Jarron, P

    2011-01-01

    The architecture and characterisation of the End Of Column demonstrator readout ASIC for the NA62 GigaTracker hybrid pixel detector is presented. This ASIC serves as a proof of principle for a pixel chip with 1800 pixels which must perform time stamping to better than 200 ps (RMS), provide 300 mu m pitch position information and operate with a dead-time of 1\\% or less for 800 MHz-1 GHz beam rate. The demonstrator ASIC comprises a full test column with 45 pixels alongside other test structures. The timewalk correction mechanism employed is measurement of the time-over-threshold, coupled with an off-detector look-up table. The time to digital converter is a delay locked loop with 32 contributing delay cells fed with a 320 MHz to yield a nominal bin size of 97 ps. Recently, P-in-N sensors have been bump-bonded to the ASIC and characterisation of these assemblies has begun.

  18. Rad-Hard Structured ASIC Body of Knowledge

    Science.gov (United States)

    Heidecker, Jason

    2013-01-01

    Structured Application-Specific Integrated Circuit (ASIC) technology is a platform between traditional ASICs and Field-Programmable Gate Arrays (FPGA). The motivation behind structured ASICs is to combine the low nonrecurring engineering costs (NRE) costs of FPGAs with the high performance of ASICs. This report provides an overview of the structured ASIC platforms that are radiation-hardened and intended for space application

  19. Acid-Sensing Ion Channel 2a (ASIC2a) Promotes Surface Trafficking of ASIC2b via Heteromeric Assembly.

    Science.gov (United States)

    Kweon, Hae-Jin; Kim, Dong-Il; Bae, Yeonju; Park, Jae-Yong; Suh, Byung-Chang

    2016-01-01

    Acid-sensing ion channels (ASICs) are proton-activated cation channels that play important roles as typical proton sensors during pathophysiological conditions and normal synaptic activities. Among the ASIC subunits, ASIC2a and ASIC2b are alternative splicing products from the same gene, ACCN1. It has been shown that ASIC2 isoforms have differential subcellular distribution: ASIC2a targets the cell surface by itself, while ASIC2b resides in the ER. However, the underlying mechanism for this differential subcellular localization remained to be further elucidated. By constructing ASIC2 chimeras, we found that the first transmembrane (TM1) domain and the proximal post-TM1 domain (17 amino acids) of ASIC2a are critical for membrane targeting of the proteins. We also observed that replacement of corresponding residues in ASIC2b by those of ASIC2a conferred proton-sensitivity as well as surface expression to ASIC2b. We finally confirmed that ASIC2b is delivered to the cell surface from the ER by forming heteromers with ASIC2a, and that the N-terminal region of ASIC2a is additionally required for the ASIC2a-dependent membrane targeting of ASIC2b. Together, our study supports an important role of ASIC2a in membrane targeting of ASIC2b. PMID:27477936

  20. Driver ASICs for Advanced Deformable Mirrors Project

    Data.gov (United States)

    National Aeronautics and Space Administration — The overall goal of the SBIR program is to develop a new Application Specified Integrated Circuit (ASIC) driver to be used in driver electronics of a deformable...

  1. Driver ASICs for Advanced Deformable Mirrors Project

    Data.gov (United States)

    National Aeronautics and Space Administration — The program leverages on our extensive expertise in developing high-performance driver ASICs for deformable mirror systems and seeks to expand the capacities of the...

  2. ASIC life extension through hardware patch interfaces

    OpenAIRE

    Bryksin, Vladyslav Sergeevich

    2009-01-01

    Specialized processor designs and ASICs offer lower power consumption and greater efficiency compared to general purpose processors. However, the drawback of specialized hardware designs is the reduction in the generality of workloads that they are able to handle. An important characteristic of specialized hardware designs is the inability to manage changes in the underlying applications. This thesis describes and analyzes the concept of ASIC patching in the Arsenal design: a mechanism to mit...

  3. NIRCA ASIC for the readout of focal plane arrays

    Science.gov (United States)

    Pâhlsson, Philip; Steenari, David; Øya, Petter; Otnes Berge, Hans Kristian; Meier, Dirk; Olsen, Alf; Hasanbegovic, Amir; Altan, Mehmet A.; Najafiuchevler, Bahram; Talebi, Jahanzad; Azman, Suleyman; Gheorghe, Codin; Ackermann, Jörg; Mæhlum, Gunnar; Johansen, Tor Magnus; Stein, Timo

    2016-05-01

    This work is a continuation of our preliminary tests on NIRCA - the Near Infrared Readout and Controller ASIC [1]. The primary application for NIRCA is future astronomical science and Earth observation missions where NIRCA will be used with mercury cadmium telluride image sensors (HgCdTe, or MCT) [2], [3]. Recently we have completed the ASIC tests in the cryogenic environment down to 77 K. We have verified that NIRCA provides to the readout integrated circuit (ROIC) regulated power, bias voltages, and fully programmable digital sequences with sample control of the analogue to digital converters (ADC). Both analog and digital output from the ROIC can be acquired and image data is 8b/10bencoded and delivered via serial interface. The NIRCA also provides temperature measurement, and monitors several analog and digital input channels. The preliminary work confirms that NIRCA is latch-up immune and able to operate down to 77 K. We have tested the performance of the 12-bit ADC with pre-amplifier to have 10.8 equivalent number of bits (ENOB) at 1.4 Msps and maximum sampling speed at 2 Msps. The 1.8-V and 3.3-V output regulators and the 10-bit DACs show good linearity and work as expected. A programmable sequencer is implemented as a micro-controller with a custom instruction set. Here we describe the special operations of the sequencer with regards to the applications and a novel approach to parallel real-time hardware outputs. The test results of the working prototype ASIC show good functionality and performance from room temperature down to 77 K. The versatility of the chip makes the architecture a possible candidate for other research areas, defense or industrial applications that require analog and digital acquisition, voltage regulation, and digital signal generation.

  4. Preliminary validation results of an ASIC for the readout and control of near-infrared large array detectors

    Science.gov (United States)

    Pâhlsson, Philip; Meier, Dirk; Otnes Berge, Hans Kristian; Øya, Petter; Steenari, David; Olsen, Alf; Hasanbegovic, Amir; Altan, Mehmet A.; Najafiuchevler, Bahram; Talebi, Jahanzad; Azman, Suleyman; Gheorghe, Codin; Ackermann, Jörg; Mæhlum, Gunnar

    2015-06-01

    In this paper we present initial test results of the Near Infrared Readout and Controller ASIC (NIRCA), designed for large area image sensors under contract from the European Space Agency (ESA) and the Norwegian Space Center. The ASIC is designed to read out image sensors based on mercury cadmium telluride (HgCdTe, or MCT) operating down to 77 K. IDEAS has developed, designed and initiated testing of NIRCA with promising results, showing complete functionality of all ASIC sub-components. The ASIC generates programmable digital signals to clock out the contents of an image array and to amplify, digitize and transfer the resulting pixel charge. The digital signals can be programmed into the ASIC during run-time and allows for windowing and custom readout schemes. The clocked out voltages are amplified by programmable gain amplifiers and digitized by 12-bit, 3-Msps successive approximation register (SAR) analogue-to-digital converters (ADC). Digitized data is encoded using 8-bit to 10-bit encoding and transferred over LVDS to the readout system. The ASIC will give European researchers access to high spectral sensitivity, very low noise and radiation hardened readout electronics for astronomy and Earth observation missions operating at 77 K and room temperature. The versatility of the chip makes the architecture a possible candidate for other research areas, or defense or industrial applications that require analog and digital acquisition, voltage regulation, and digital signal generation.

  5. Development of an ASIC for the readout and control of near-infrared large array detectors

    Science.gov (United States)

    Meier, Dirk; Berge, Hans Kristian Otnes; Hasanbegovic, Amir; Altan, Mehmet A.; Najafiuchevler, Bahram; Azman, Suleyman; Talebi, Jahanzad; Olsen, Alf; Øya, Petter; Paahlsson, Philip; Gheorghe, Codin; Maehlum, Gunnar

    2014-07-01

    The article describes the near infrared readout and controller ASIC (NIRCA) developed by Integrated Detector Electronics AS (IDEAS). The project aims at future astronomical science and Earth observation missions, where the ASIC will be used with image sensors based on mercury cadmium telluride (HgCdTe, or MCT). NIRCA is designed to operate from cryogenic temperatures (77 K) to higher than room temperature (328 K) and in a high radiation environment (LET > 60 MeVcm2/mg). The ASIC connects to the readout integrated circuit (ROIC) and delivers fully digitized data via serial digital output. The ASIC contains an analogue front-end (AFE) with 4 analogue-to-digital converters (ADCs) and programmable gain amplifiers with offset adjustment. The ADCs have a differential input swing of +/-2 V, 12-bit resolution, and a maximum sample rate of 3 MSps. The ASIC contains a programmable sequencer (microcontroller) to generate up to 40 digital signals for the ROIC and to control the analogue front-end and DACs on the chip. The ASIC has two power supply voltage regulators that provide the ROIC with 1.8 V and 3.3 V, and programmable 10-bit DACs to generate 16 independent reference and bias voltages from 0.3 V to 3 V. In addition NIRCA allows one to read 8 external digital signals, and monitor external and internal analogue signals including onchip temperature. NIRCA can be programmed and controlled via SPI interface for all internal functions and allows data forwarding from and to the ROIC SPI interface.

  6. Optical link ASICs for LHC upgrades

    Science.gov (United States)

    Gan, K. K.; Kagan, H. P.; Kass, R. D.; Moore, J. R.; Smith, D. S.

    2011-05-01

    We have designed three ASICs for possible applications in a new pixel layer (insertable B-layer or IBL) for the ATLAS detector for the first phase of the LHC luminosity upgrade. The ASICs are a high-speed driver for the vertical-cavity surface-emitting laser (VCSEL), a receiver/decoder to decode the signal received at the PIN diode to extract the data and clock, and a clock multiplier to produce a higher frequency clock to serialize the data for transmission. These ASICs were designed using a 130 nm CMOS process to enhance the radiation-hardness. We have characterized the ASICs and the submission has been mostly successful. We irradiated the ASICs with 24 GeV/c protons at CERN to a dosage of 70 Mrad. We observed no significant degradation except the driver circuit in the VCSEL driver fabricated using the thick oxide process in order to provide sufficient voltage to drive a VCSEL. The degradation is due to the radiation induced large threshold shifts in the PMOS transistors used.

  7. XAMPS Detectors Readout ASIC for LCLS

    Energy Technology Data Exchange (ETDEWEB)

    Dragone, A; /SLAC; Pratte, J.F.; Rehak, P.; /Brookhaven; Carini, G.A.; /BNL, NSLS; Herbst, R.; /SLAC; O' Connor, P.; /Brookhaven; Siddons, D.P.; /BNL, NSLS

    2008-12-18

    An ASIC for the readout of signals from X-ray Active Matrix Pixel Sensor (XAMPS) detectors to be used at the Linac Coherent Light Source (LCLS) is presented. The X-ray Pump Probe (XPP) instrument, for which the ASIC has been designed, requires a large input dynamic range on the order of 104 photons at 8 keV with a resolution of half a photon FWHM. Due to the size of the pixel and the length of the readout line, large input capacitance is expected, leading to stringent requirement on the noise optimization. Furthermore, the large number of pixels needed for a good position resolution and the fixed LCLS beam period impose limitations on the time available for the single pixel readout. Considering the periodic nature of the LCLS beam, the ASIC developed for this application is a time-variant system providing low-noise charge integration, filtering and correlated double sampling. In order to cope with the large input dynamic range a charge pump scheme implementing a zero-balance measurement method has been introduced. It provides an on chip 3-bit coarse digital conversion of the integrated charge. The residual charge is sampled using correlated double sampling into analog memory and measured with the required resolution. The first 64 channel prototype of the ASIC has been fabricated in TSMC CMOS 0.25 {micro}m technology. In this paper, the ASIC architecture and performances are presented.

  8. Optical Link ASICs for the LHC Upgrade

    CERN Document Server

    Gan, K K; Kass, R D; Moore, J R; Smith, D S

    2009-01-01

    We have designed three ASICs for possible applications in the optical links of a new layer of pixel detector in the ATLAS experiment for the first phase of the LHC luminosity upgrade. The ASICs include a high-speed driver for the VCSEL, a receiver/decoder to decode the signal received at the PIN diode to extract the data and clock, and a clock multiplier to produce a higher frequency clock to serialize the data for transmission. These ASICs were designed using a 130 nm CMOS process to enhance the radiation-hardness. We have characterized the fabricated ASICs and the submission has been mostly successful. We irradiated the ASICs with 24 GeV/c protons at CERN to a dosage of 70 Mrad. We observed no significant degradation except the driver circuit in the VCSEL driver fabricated using the thick oxide process in order to provide sufficient voltage to drive a VCSEL. The degradation is due to a large threshold shifts in the PMOS transistors used.

  9. SIDECAR ASIC firmware for astronomy applications

    Science.gov (United States)

    Chen, Jing; Loose, Markus; Ricardo, Raphael; Beletic, James; Farris, Mark; Xu, Min; Wong, Andre; Cabelli, Craig

    2014-07-01

    The SIDECAR ASIC is a fully integrated system-on-a-chip focal plane array controller that offers low power and low noise, small size and low weight. It has been widely used to operate different image sensors for ground-based and flightbased astronomy applications. A key mechanism to operating analog detectors is the SIDECAR ASIC's high level of programmability. This paper gives an overview of the SIDECAR ASIC architecture, including its optimized microcontroller featuring a customized instruction set. It describes the firmware components, including timing generation, biasing, commanding, housekeeping and synchronization of multiple detectors. The firmware development tools including compiler and supporting development environment and hardware setup are presented. The firmware capability for ground-based HxRG applications and for flight-based applications like the James Webb Space Telescope (JWST), the repair of the Advanced Camera for Surveys (ACS), and others are also discussed.

  10. Timing and control requirements for a 32-channel AMU-ADC ASIC for the PHENIX detector

    Energy Technology Data Exchange (ETDEWEB)

    Emery, M.S.; Ericson, M.N.; Britton, C.L. Jr. [and others

    1998-02-01

    A custom CMOS Application Specific Integrated Circuit (ASIC) has been developed consisting of an analog memory unit (AMU) has been developed consisting of an analog memory unit (AMU) and analog to digital converter (ADC), both of which have been designed for applications in the PHENIX experiment. This IC consists of 32 pipes of analog memory with 64 cells per pipe. Each pipe also has its own ADC channel. Timing and control signal requirements for optimum performance are discussed in this paper.

  11. An analogue front-end ASIC prototype designed for PMT signal readout

    Science.gov (United States)

    Liu, Jian-Feng; Zhao, Lei; Yu, Li; Liang, Yu; Qin, Jia-Jun; Yang, Yun-Fan; Wu, Wei-Hao; Liu, Shu-Bin; An, Qi

    2016-06-01

    The Water Cherenkov Detector Array (WCDA) is one of the core detectors in the Large High Altitude Air Shower Observatory (LHAASO), and it consists of 3600 photomultiplier tubes (PMTs). Both high resolution time and charge measurement are required over a large dynamic range from 1 photoelectron (P.E.) to 4000 P.E. The prototype of an analogue front-end Application Specific Integrated Circuit (ASIC) fabricated using Global Foundry 0.35 μm CMOS technology is designed to read out the PMT signal in the WCDA. This ASIC employs leading edge discrimination and an (RC)4 shaping structure. Combined with the following Time-to-Digital Converter (TDC) and Analog-to-Digital Converter (ADC), both the arrival time and charge of the PMT signal can be measured. Initial test results indicate that time resolution is better than 350 ps and charge resolution is better than 10% at 1 P.E. and better than 1% with large input signals (300 P.E. to 4000 P.E.). Besides, this ASIC has a good channel-to-channel isolation of more than 84 dB and the temperature dependency of charge measurement is less than 5% in the range 0–50°C. Supported by Knowledge Innovation Program of Chinese Academy of Sciences (KJCX2-YW-N27), National Natural Science Foundation of China (11175174) and CAS Center for Excellence in Particle Physics (CCEPP)

  12. Abnormal cardiac autonomic regulation in mice lacking ASIC3.

    Science.gov (United States)

    Cheng, Ching-Feng; Kuo, Terry B J; Chen, Wei-Nan; Lin, Chao-Chieh; Chen, Chih-Cheng

    2014-01-01

    Integration of sympathetic and parasympathetic outflow is essential in maintaining normal cardiac autonomic function. Recent studies demonstrate that acid-sensing ion channel 3 (ASIC3) is a sensitive acid sensor for cardiac ischemia and prolonged mild acidification can open ASIC3 and evoke a sustained inward current that fires action potentials in cardiac sensory neurons. However, the physiological role of ASIC3 in cardiac autonomic regulation is not known. In this study, we elucidate the role of ASIC3 in cardiac autonomic function using Asic3(-/-) mice. Asic3(-/-) mice showed normal baseline heart rate and lower blood pressure as compared with their wild-type littermates. Heart rate variability analyses revealed imbalanced autonomic regulation, with decreased sympathetic function. Furthermore, Asic3(-/-) mice demonstrated a blunted response to isoproterenol-induced cardiac tachycardia and prolonged duration to recover to baseline heart rate. Moreover, quantitative RT-PCR analysis of gene expression in sensory ganglia and heart revealed that no gene compensation for muscarinic acetylcholines receptors and beta-adrenalin receptors were found in Asic3(-/-) mice. In summary, we unraveled an important role of ASIC3 in regulating cardiac autonomic function, whereby loss of ASIC3 alters the normal physiological response to ischemic stimuli, which reveals new implications for therapy in autonomic nervous system-related cardiovascular diseases. PMID:24804235

  13. Abnormal Cardiac Autonomic Regulation in Mice Lacking ASIC3

    Directory of Open Access Journals (Sweden)

    Ching-Feng Cheng

    2014-01-01

    Full Text Available Integration of sympathetic and parasympathetic outflow is essential in maintaining normal cardiac autonomic function. Recent studies demonstrate that acid-sensing ion channel 3 (ASIC3 is a sensitive acid sensor for cardiac ischemia and prolonged mild acidification can open ASIC3 and evoke a sustained inward current that fires action potentials in cardiac sensory neurons. However, the physiological role of ASIC3 in cardiac autonomic regulation is not known. In this study, we elucidate the role of ASIC3 in cardiac autonomic function using Asic3−/− mice. Asic3−/− mice showed normal baseline heart rate and lower blood pressure as compared with their wild-type littermates. Heart rate variability analyses revealed imbalanced autonomic regulation, with decreased sympathetic function. Furthermore, Asic3−/− mice demonstrated a blunted response to isoproterenol-induced cardiac tachycardia and prolonged duration to recover to baseline heart rate. Moreover, quantitative RT-PCR analysis of gene expression in sensory ganglia and heart revealed that no gene compensation for muscarinic acetylcholines receptors and beta-adrenalin receptors were found in Asic3−/− mice. In summary, we unraveled an important role of ASIC3 in regulating cardiac autonomic function, whereby loss of ASIC3 alters the normal physiological response to ischemic stimuli, which reveals new implications for therapy in autonomic nervous system-related cardiovascular diseases.

  14. Optical link ASICs for LHC upgrades

    CERN Document Server

    Gan, K.K.

    2009-01-01

    We have designed several ASICs for possible applications in a new ATLAS pixel layer for the first phase of the LHC luminosity upgrade. The ASICs include a high-speed driver for the VCSEL, a receiver/decoder to decode the signal received at the PIN diode to extract the data and clock, and a clock multiplier to produce a higher frequency clock to serialize the data for transmission. These chips were designed using a 130 nm CMOS process to enhance the radiation-hardness. We have characterized the fabricated chips and the submission has been mostly successful. We irradiated the chips with 24 GeV/c protons at CERN to a dosage of 70 Mrad. We observed no significant degradation except the driver circuit in the VCSEL driver fabricated using the thick oxide process in order to provide sufficient voltage to drive a VCSEL. The degradation is due to the large threshold shifts in the PMOS transistors used.

  15. Latest generation of ASICs for photodetector readout

    Energy Technology Data Exchange (ETDEWEB)

    Seguin-Moreau, N., E-mail: seguin@lal.in2p3.fr [Laboratoire de l’Accélérateur Linéaire, IN2P3-CNRS, Université Paris-Sud, Bâtiment 200, 91898 Orsay Cedex (France)

    2013-08-01

    The OMEGA microelectronics group has designed a new generation of multichannel integrated circuits, the “ROC” family, in AustrianMicroSystem (AMS) SiGe 0.35 μm technology to read out signals from various families of photodetectors. The chip named MAROC (standing for Multi Anode ReadOut Chip) has been designed to read out MultiAnode Photomultipliers (MAPMT), Photomultiplier ARray In SiGe ReadOut Chip (PARISROC) to read out Photomultipliers (PMTs) and SiPM Integrated ReadOut Chip (SPIROC) to readout Silicon PhotoMultiplier (SiPM) detectors and which was the first ASIC to do so. The three of them fulfill the stringent requirements of the future photodetectors, in particular in terms of low noise, radiation hardness, large dynamic range, high density and high speed while keeping low power thanks to the SiGe technology. These multi-channel ASICs are real System on Chip (SoC) as they provide charge, time and photon-counting information which are digitized internally. Their complexity and versatility enable innovative frontier detectors and also cover spin off of these detectors in adjacent fields such as medical or material imaging as well as smart detectors. In this presentation, the three ASIC architectures and test results will be described to give a general panorama of the “ROC” chips.

  16. Latest generation of ASICs for photodetector readout

    Science.gov (United States)

    Seguin-Moreau, N.

    2013-08-01

    The OMEGA microelectronics group has designed a new generation of multichannel integrated circuits, the "ROC" family, in AustrianMicroSystem (AMS) SiGe 0.35 μm technology to read out signals from various families of photodetectors. The chip named MAROC (standing for Multi Anode ReadOut Chip) has been designed to read out MultiAnode Photomultipliers (MAPMT), Photomultiplier ARray In SiGe ReadOut Chip (PARISROC) to read out Photomultipliers (PMTs) and SiPM Integrated ReadOut Chip (SPIROC) to readout Silicon PhotoMultiplier (SiPM) detectors and which was the first ASIC to do so. The three of them fulfill the stringent requirements of the future photodetectors, in particular in terms of low noise, radiation hardness, large dynamic range, high density and high speed while keeping low power thanks to the SiGe technology. These multi-channel ASICs are real System on Chip (SoC) as they provide charge, time and photon-counting information which are digitized internally. Their complexity and versatility enable innovative frontier detectors and also cover spin off of these detectors in adjacent fields such as medical or material imaging as well as smart detectors. In this presentation, the three ASIC architectures and test results will be described to give a general panorama of the "ROC" chips.

  17. VMM - An ASIC for Micropattern Detectors

    CERN Document Server

    Iakovidis, Georgios; The ATLAS collaboration; De Geronimo, Gianluigi

    2015-01-01

    The VMM is a custom Application Specific Integrated Circuit (ASIC) that can be used in a va- riety of charge interpolated tracking detectors. It is designed to be used with the resistive Micromegas and sTGC detectors in the New Small Wheel upgrade of the ATLAS Muon spectrometer. The ASIC is designed at Brookhaven National Laboratory and fabricated in the 130 nm Global Foundries 8RF-DM process. The devices will be packaged in a Ball Grid Array with outline dimensions of 21 × 21 mm2 . It integrates 64 channels, each providing charge amplification, discrimination, neighbour logic, amplitude and timing measurements, analog- to-digital conversions, and either direct output for trigger or multiplexed readout. The front-end amplifier can operate with a wide range of input capacitances, has adjustable polarity, gain and peaking time. The VMM2 is the second version of the VMM ASIC family fabricated in 2014. The design, tests and qualification of the VMM1, VMM2 and roadmap to VMM3 is described.

  18. Latest generation of ASICs for photodetector readout

    International Nuclear Information System (INIS)

    The OMEGA microelectronics group has designed a new generation of multichannel integrated circuits, the “ROC” family, in AustrianMicroSystem (AMS) SiGe 0.35 μm technology to read out signals from various families of photodetectors. The chip named MAROC (standing for Multi Anode ReadOut Chip) has been designed to read out MultiAnode Photomultipliers (MAPMT), Photomultiplier ARray In SiGe ReadOut Chip (PARISROC) to read out Photomultipliers (PMTs) and SiPM Integrated ReadOut Chip (SPIROC) to readout Silicon PhotoMultiplier (SiPM) detectors and which was the first ASIC to do so. The three of them fulfill the stringent requirements of the future photodetectors, in particular in terms of low noise, radiation hardness, large dynamic range, high density and high speed while keeping low power thanks to the SiGe technology. These multi-channel ASICs are real System on Chip (SoC) as they provide charge, time and photon-counting information which are digitized internally. Their complexity and versatility enable innovative frontier detectors and also cover spin off of these detectors in adjacent fields such as medical or material imaging as well as smart detectors. In this presentation, the three ASIC architectures and test results will be described to give a general panorama of the “ROC” chips

  19. Configurable Radiation Hardened High Speed Isolated Interface ASIC Project

    Data.gov (United States)

    National Aeronautics and Space Administration — NVE Corporation will design and build an innovative, low cost, flexible, configurable, radiation hardened, galvanically isolated, interface ASIC chip set that will...

  20. Indigenous design and development of digital ASICs

    International Nuclear Information System (INIS)

    FPGAs and CPLDs were extensively used for the design and development of Instrumentation and Control systems including safety systems of Prototype Fast Breeder Reactor (PFBR). The developed I and C systems have been tested extensively for their functionality and also undergone various qualification tests. Some of these I and C systems have also been deployed in Fast Breeder Test Reactor. The performance of these designs is found to be satisfactory. However FPGAs/CPLDs are rapidly evolving and the devices become obsolete in a short span of time (typically about 5 to 8 years), whereas reactor's life time is typically about 40 years. This obsolescence problem can be handled in different ways. This paper discusses design and fabrication of digital ASICs as one of the alternate for handling obsolescence problems. Aim of this development work is to establish complete digital ASIC design, fabrication and testing flow, so that the same can be used in some of the critical/strategic requirements. (author)

  1. Small Microprocessor for ASIC or FPGA Implementation

    Science.gov (United States)

    Kleyner, Igor; Katz, Richard; Blair-Smith, Hugh

    2011-01-01

    A small microprocessor, suitable for use in applications in which high reliability is required, was designed to be implemented in either an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA). The design is based on commercial microprocessor architecture, making it possible to use available software development tools and thereby to implement the microprocessor at relatively low cost. The design features enhancements, including trapping during execution of illegal instructions. The internal structure of the design yields relatively high performance, with a significant decrease, relative to other microprocessors that perform the same functions, in the number of microcycles needed to execute macroinstructions. The problem meant to be solved in designing this microprocessor was to provide a modest level of computational capability in a general-purpose processor while adding as little as possible to the power demand, size, and weight of a system into which the microprocessor would be incorporated. As designed, this microprocessor consumes very little power and occupies only a small portion of a typical modern ASIC or FPGA. The microprocessor operates at a rate of about 4 million instructions per second with clock frequency of 20 MHz.

  2. ASIC Design and Implementation for Digital Pulse Compression Chip

    Institute of Scientific and Technical Information of China (English)

    高俊峰; 韩月秋; 王巍

    2004-01-01

    A novel ASIC design of changeable-point digital pulse compression (DPC) chip is presented. System hardware resource is reduced to one third of the traditional design method through operations sharing hardware, i.e. let FFT, complex multiplication and IFFT be fulfilled with the same hardware structure. Block-floating-point scaling is used to enhance the dynamic range and computation accuracy. This design applies parallel pipeline structure and the radix-4 butterfly operation to improve the processing speed. In addition, a triple-memory-space(TMS) configuration is used that allows input, computation and output operations to be overlapped, so that the dual-butterfly unit is never left in an idle state waiting for I/O operation. The whole design is implemented with only one chip of XC2V500-5 FPGA. It can implement 1 024-point DPC within 91.6 μs.The output data is converted to floating-point formation to achieve seamless interface with TMS320C6701. The validity of the design is verified by simulation and measurement results.

  3. VHiSSI: Experimental Spacefibre Asic

    Science.gov (United States)

    Gonzalez Villafranca, Alberto; Ferrer, Albert; McLaren, David; McClements, Chris; Parkes, Steve

    2015-09-01

    SpaceFibreis the next generation data link and network technology being developed by University of Dundee for the European Space Agency. This high-speed technology runs over both copper and fibre optic cables and is backwards compatible with the ubiquitous SpaceWire technology. SpaceFibre provides 12 times the throughput of a SpW link (2.5 Gbps) with current flight qualified technology together with inbuilt QoS and FDIR capabilities. This paper details the first implementation of SpaceFibre in a radiation tolerant device in the frame of the VHiSSI project. The functionality of this ASIC chip is explained and the results of the functional and Total Ionising Dose and Single Event Effect radiation testing are detailed.

  4. An Analogue Front-End ASIC Prototype Designed For PMT Signal Readout

    CERN Document Server

    Liu, Jianfeng; Yu, Li; Liang, Yu; Qin, Jiajun; Yang, Yunfang; Wu, Weihao; Liu, Shubin; An, Qi

    2015-01-01

    The Large High Altitude Air Shower Observatory (LHAASO) is designed for high energy gamma ray and cosmic ray detection. A Water Cherenkov Detector Array which is sensitive to gamma ray showers above a few hundred GeV is proposed to survey gamma ray sources. The WCDA consists of 3600 PhotoMultiplier Tubes (PMT) which collect the Cherenkov light produced by the shower particles in water. Both high precision time and charge measurement are required over a large dynamic range from 1 photo electron (P.E.) to 4000 P.E. Prototype of an analogue front-end Application Specific Integrated Circuit (ASIC) fabricated in Chartered 0.35 {\\mu}m CMOS technology is designed to read out PMT signal in the WCDA. This ASIC employs leading edge discrimination and RC4 shaping structure; combined with the following Time-to-Digital Converter (TDC) and Analog-to-Digital Converter (ADC), both the arrival time and charge of the PMT signal can be measured. Initial test results indicate that time resolution is better than 350 ps and charge...

  5. Low-power Cross-Correlator ASIC Project

    Data.gov (United States)

    National Aeronautics and Space Administration — Pacific MicroCHIP Corporation offers to design an ASIC that includes a cross-correlation unit together with the interfaces to be connected to the output of the...

  6. Extreme Temperature, Rad-Hard Power Management ASIC Project

    Data.gov (United States)

    National Aeronautics and Space Administration — Ridgetop Group will design a rad-hard Application Specific Integrated Circuit (ASIC) for spacecraft power management that is functional over a temperature range of...

  7. ASIC1基因敲除小鼠的繁殖及基因鉴定%Reproduction and genotype identification of ASIC1 knockout mice

    Institute of Scientific and Technical Information of China (English)

    周仁鹏; 吴小山; 王志森; 葛金芳; 陈飞虎

    2015-01-01

    To breed and identify acid sensing ion channel 1(ASIC1) gene knockout mice, so as to lay the founda-tion for studying ASIC1 protein. The heterozygote mice were bred and reproduced. Genome DNA extracted from the murine tail was subjected to PCR test for genotype identification. Breeding and reproducing of ASIC1 knockout mice were both successful,and the genotypes of the offspring mice were heterozygous( ASIC1+/ -) ,homozygous( ASIC1-/ -) ,and wild-type( ASIC1+/ +) . Appropriate methods of breeding,reproducing and identifying can effective-ly obtain ASIC1-/ - mice.%饲养并繁殖酸敏感离子通道1(ASIC1)基因敲除杂合子小鼠,提取小鼠尾部组织DNA,采用聚合酶链反应( PCR)方法鉴定子代小鼠基因型. ASIC1 基因敲除小鼠的繁育和鉴定均获得成功,子代小鼠基因型分别为杂合子( ASIC1+/-)、纯合子( ASIC1-/ -)和野生型( ASIC1+/ +).

  8. Monolithic Active Pixel Matrix with Binary Counters (MAMBO) ASIC

    Energy Technology Data Exchange (ETDEWEB)

    Khalid, Farah F.; Deptuch, Grzegorz; Shenai, Alpana; Yarema, Raymond J.; /Fermilab

    2010-11-01

    Monolithic Active Matrix with Binary Counters (MAMBO) is a counting ASIC designed for detecting and measuring low energy X-rays from 6-12 keV. Each pixel contains analogue functionality implemented with a charge preamplifier, CR-RC{sup 2} shaper and a baseline restorer. It also contains a window comparator which can be trimmed by 4 bit DACs to remove systematic offsets. The hits are registered by a 12 bit ripple counter which is reconfigured as a shift register to serially output the data from the entire ASIC. Each pixel can be tested individually. Two diverse approaches have been used to prevent coupling between the detector and electronics in MAMBO III and MAMBO IV. MAMBO III is a 3D ASIC, the bottom ASIC consists of diodes which are connected to the top ASIC using {mu}-bump bonds. The detector is decoupled from the electronics by physically separating them on two tiers and using several metal layers as a shield. MAMBO IV is a monolithic structure which uses a nested well approach to isolate the detector from the electronics. The ASICs are being fabricated using the SOI 0.2 {micro}m OKI process, MAMBO III is 3D bonded at T-Micro and MAMBO IV nested well structure was developed in collaboration between OKI and Fermilab.

  9. Design and characterization of the ePix10k: a high dynamic range integrating pixel ASIC for LCLS detectors

    Science.gov (United States)

    Caragiulo, P.; Dragone, A.; Markovic, B.; Herbst, R.; Nishimura, K.; Reese, B.; Herrmann, S.; Hart, P.; Blaj, G.; Segal, J.; Tomada, A.; Hasi, J.; Carini, G.; Kenney, C.; Haller, G.

    2015-05-01

    ePix10k is a variant of a novel class of integrating pixel ASICs architectures optimized for the processing of signals in second generation LINAC Coherent Light Source (LCLS) X-Ray cameras. The ASIC is optimized for high dynamic range application requiring high spatial resolution and fast frame rates. ePix ASICs are based on a common platform composed of a random access analog matrix of pixel with global shutter, fast parallel column readout, and dedicated sigma-delta analog to digital converters per column. The ePix10k variant has 100um×100um pixels arranged in a 176×192 matrix, a resolution of 140e- r.m.s. and a signal range of 3.5pC (10k photons at 8keV). In its final version it will be able to sustain a frame rate of 2kHz. A first prototype has been fabricated and characterized. Performance in terms of noise, linearity, uniformity, cross-talk, together with preliminary measurements with bump bonded sensors are reported here.

  10. Performance of VATA64HDR16 ASIC for medical physics applications based on continuous crystals and SiPMs

    International Nuclear Information System (INIS)

    Detectors based on Silicon Photomultipliers (SiPMs) coupled to continuous crystals are being tested in medical physics applications due to their potential high resolution and sensitivity. To cope with the high granularity required for a very good spatial resolution, SiPM matrices with a large amount of elements are needed. To be able to read the information coming from each individual channel, dedicated ASICs are employed. The VATA64HDR16 ASIC is a 64-channel, charge-sensitive amplifier that converts the collected charge into a proportional current or voltage signal. A complete assessment of the suitability of that ASIC for medical physics applications based on continuous crystals and SiPMs has been carried out. The input charge range is linear from 0−2 pC up to 55 pC. The energy resolution obtained at 511 keV is 10% FWHM with a LaBr3 crystal and 16% FWHM with a LYSO crystal. A coincidence timing resolution of 24 ns FWHM is obtained with two LYSO crystals

  11. Implementation of an ASIC for Detector Instrumentation in Nuclear Physics Applications

    OpenAIRE

    McIntosh, James Alexander

    1996-01-01

    A prototype ASIC (EFT1) for silicon strip detector instrumentation has been designed and tested. The ASIC design contains the electronics necessary for preamplification, shaping, hit detection, and data readout control.The specific­ ation of the ASIC makes it suitable for charged particle spectroscopy applications with the implementation of multiple channels on a single chip reducing the cost compared to expensive discrete instrumentation. The ASIC contains features wh...

  12. Four-channel readout ASIC for silicon pad detectors

    International Nuclear Information System (INIS)

    A custom front-end readout ASIC has been designed for silicon calorimeters supposed to be used in high-energy physics experiments. The ASIC was produced using BJT-JFET technology. It contains four channels of a fast low-noise charge-sensitive preamplifier (CSP) with inverting outputs summed by a linear adder (LA) followed by an RC-CR shaping amplifier (SA) with 30 ns peaking time. Availability of separate outputs of the CSPs and the LA makes it possible to join any number of silicon detector layers to obtain the longitudinal and transversal resolution required using only this ASIC in any silicon calorimeter minitower configuration. Noise performance is ENC=1800e-+18e-/pF at 30 ns peaking time for detector capacitance up to Cd=400 pF. Rise time is 8 ns at input capacitance Cd=100 pF. Power dissipation is less than 50 mW/ chip at voltage supply 5 V

  13. A 2D 4×4 Channel Readout ASIC for Pixelated CdTe Detectors for Medical Imaging Applications

    OpenAIRE

    Macias-Montero, Jose-Gabriel; Sarraj, Maher; Chmeissani, Mokhtar; Martínez, Ricardo; Puigdengoles, Carles

    2015-01-01

    We present a 16-channel readout integrated circuit (ROIC) with nanosecond-resolution time to digital converter (TDC) for pixelated Cadmium Telluride (CdTe) gamma-ray detectors. The 4 × 4 pixel array ROIC is the proof of concept of the 10 × 10 pixel array readout ASIC for positron-emission tomography (PET) scanner, positron-emission mammography (PEM) scanner, and Compton gamma camera. The electronics of each individual pixel integrates an analog front-end with switchable gain, an analog to dig...

  14. Delay 25 an ASIC for timing adjustment in LHC

    NARCIS (Netherlands)

    Furtado, H.; Schrader, J.H.R.; Marchioro, A.; Moreira, P.

    2005-01-01

    A five channel programmable delay line ASIC was designed featuring 4 channels that allow to phase delay periodic or non-periodic digital signals and a master channel that can be used to phase delay a clock signal. The master channel serves as a calibration reference guaranteeing independence from pr

  15. Beam test performance of the SKIROC2 ASIC

    CERN Document Server

    Frisson, T; Anduze, M; Augustin, J.E; Bonis, J; Boudry, V; Bourgeois, C; Brient, J.C; Callier, S; Cerutti, M; Chen, S; Cornat, R; Cornebise, P; Cuisy, D; David, J; De la Taille, C; Dulucq, F; Frotin, M; Gastaldi, F; Ghislain, P; Giraud, J; Gonnin, A; Grondin, D; Guliyev, E; Hostachy, J.Y; Jeans, D; Kamiya, Y; Kawagoe, K; Kozakai, C; Lacour, D; Lavergne, L; Lee, S.H; Magniette, F; Ono, H; Poeschl, R; Rouëné, J; Seguin-Moreau, N; Song, H.S; Sudo, Y; Thiebault, A; Tran, H; Ueno, H; Van der Kolk, N; Yoshioka, T

    2015-01-01

    Beam tests of the first layers of CALICE silicon tungsten ECAL technological prototype were performed in April and July 2012 using 1–6 GeV electron beam at DESY. This paper presents an analysis of the SKIROC2 readout ASIC performance under test beam conditions.

  16. Three-dimensional stacked structured ASIC devices and methods of fabrication thereof

    Energy Technology Data Exchange (ETDEWEB)

    Shinde, Subhash L.; Teifel, John; Flores, Richard S.; Jarecki Jr., Robert L.; Bauer, Todd

    2015-11-19

    A 3D stacked sASIC is provided that includes a plurality of 2D reconfigurable structured structured ASIC (sASIC) levels interconnected through hard-wired arrays of 3D vias. The 2D sASIC levels may contain logic, memory, analog functions, and device input/output pad circuitry. During fabrication, these 2D sASIC levels are stacked on top of each other and fused together with 3D metal vias. Such 3D vias may be fabricated as through-silicon vias (TSVs). They may connect to the back-side of the 2D sASIC level, or they may be connected to top metal pads on the front-side of the 2D sASIC level.

  17. Radiation-hard ASICs for LHC optical data transmission

    Science.gov (United States)

    Gan, K. K.; Kagan, H. P.; Kass, R. D.; Moore, J. R.; Smith, D. S.

    2010-11-01

    We have designed several ASICs for possible applications in a new ATLAS pixel layer for the first phase of the LHC luminosity upgrade. The ASICs include a high-speed driver for the VCSEL, a receiver/decoder to decode the signal received at the PIN diode to extract the data and clock, and a clock multiplier to produce a higher frequency clock to serialize the data for transmission. These chips were designed using a 130 nm CMOS process to enhance the radiation-hardness. We have characterized the fabricated chips and the submission has been mostly successful. We irradiated the chips with 24 GeV/c protons at CERN to a dosage of 70 Mrad. We observed no significant degradation except the driver circuit in the VCSEL driver fabricated using the thick oxide process in order to provide sufficient voltage to drive a VCSEL. The degradation is due to the radiation induced large threshold shifts in the PMOS transistors used.

  18. Implementation of the Timepix ASIC in the Scalable Readout System

    Science.gov (United States)

    Lupberger, M.; Desch, K.; Kaminski, J.

    2016-09-01

    We report on the development of electronics hardware, FPGA firmware and software to provide a flexible multi-chip readout of the Timepix ASIC within the framework of the Scalable Readout System (SRS). The system features FPGA-based zero-suppression and the possibility to read out up to 4×8 chips with a single Front End Concentrator (FEC). By operating several FECs in parallel, in principle an arbitrary number of chips can be read out, exploiting the scaling features of SRS. Specifically, we tested the system with a setup consisting of 160 Timepix ASICs, operated as GridPix devices in a large TPC field cage in a 1 T magnetic field at a DESY test beam facility providing an electron beam of up to 6 GeV. We discuss the design choices, the dedicated hardware components, the FPGA firmware as well as the performance of the system in the test beam.

  19. ENaCs and ASICs as therapeutic targets

    OpenAIRE

    Qadri, Yawar J.; Rooj, Arun K.; Fuller, Catherine M.

    2012-01-01

    The epithelial Na+ channel (ENaC) and acid-sensitive ion channel (ASIC) branches of the ENaC/degenerin superfamily of cation channels have drawn increasing attention as potential therapeutic targets in a variety of diseases and conditions. Originally thought to be solely expressed in fluid absorptive epithelia and in neurons, it has become apparent that members of this family exhibit nearly ubiquitous expression. Therapeutic opportunities range from hypertension, due to the role of ENaC in ma...

  20. ASIC design and data communications for the Boston retinal prosthesis.

    Science.gov (United States)

    Shire, Douglas B; Ellersick, William; Kelly, Shawn K; Doyle, Patrick; Priplata, Attila; Drohan, William; Mendoza, Oscar; Gingerich, Marcus; McKee, Bruce; Wyatt, John L; Rizzo, Joseph F

    2012-01-01

    We report on the design and testing of a custom application-specific integrated circuit (ASIC) that has been developed as a key component of the Boston retinal prosthesis. This device has been designed for patients who are blind due to age-related macular degeneration or retinitis pigmentosa. Key safety and communication features of the low-power ASIC are described, as are the highly configurable neural stimulation current waveforms that are delivered to its greater than 256 output electrodes. The ASIC was created using an 0.18 micron Si fabrication process utilizing standard 1.8 volt CMOS transistors as well as 20 volt lightly doped drain FETs. The communication system receives frequency-shift keyed inputs at 6.78 MHz from an implanted secondary coil, and transmits data back to the control unit through a lower-bandwidth channel that employs load-shift keying. The design's safety is ensured by on-board electrode voltage monitoring, stimulus charge limits, error checking of data transmitted to the implant, and comprehensive self-test and performance monitoring features. Each stimulus cycle is initiated by a transmitted word with a full 32-bit error check code. Taken together, these features allow researchers to safely and wirelessly tailor retinal stimulation and vision recovery for each patient. PMID:23365888

  1. VeloPix ASIC for the LHCb VELO Upgrade

    CERN Multimedia

    Cid Vidal, Xabier

    2015-01-01

    The LHCb Vertex Detector (VELO) will be upgraded in 2018 along with the other subsystems of LHCb in order to enable full detector readout at 40 MHz. LHCb will run without a hardware trigger and all data will be fed directly to the software triggering algorithms in the CPU farm. The upgraded VELO is a lightweight silicon hybrid pixel detector with 55 um square pixels, operating in vacuum in close proximity to the LHC beams. The readout will be provided by a dedicated front end ASIC, dubbed VeloPix, matched to the LHCb luminosity requirements. VeloPix is a binary pixel chip with a matrix of 256 x 256 pixels, covering an area of 2 cm^2. It is designed in a 130 nm CMOS technology, and is closely related to the Timepix3, from the Medipix family of ASICs. The principal challenge that the chip has to meet is a hit rate of up to 900 Mhits/s/ASIC, resulting in a data rate of more than 16 Gbit/s. Combining pixels into groups of 2x4 super-pixels enables the use of shared logic and a reduction of bandwidth due to combine...

  2. The read-out ASIC for the Space NUCLEON project

    International Nuclear Information System (INIS)

    This paper summarizes the design results for the read-out ASIC for the space NUCLEON project of the Russian Federal Space Agency ROSCOSMOS. The ASIC with a unique high dynamic range (1–40 000 mip) at low power consumption (< 1.5 mW per channel) has been developed. It allows to record signals of relativistic particles and nuclei with charges from Z = 1 up to Z > 50, generated by silicon detectors, having capacitances up to 100 pF. The chip structure includes 32 analog channels, each consisting of a charge sensitive amplifier (CSA) with a p-MOS input transistor (W = 8 mm, L = 0.5 μ m), a shaper (peaking time of 2 us) and a T and H circuit. The ASIC showed a 120 pC dynamic range at a SNR of 2.5 for the particles with minimal ionization energy (1 mip). The chip was fabricated by the 0.35 um CMOS process via Europractice and tested both at lab conditions and in the SPS beam at CERN

  3. An ASIC Low Power Primer Analysis, Techniques and Specification

    CERN Document Server

    Chadha, Rakesh

    2013-01-01

    This book provides an invaluable primer on the techniques utilized in the design of low power digital semiconductor devices.  Readers will benefit from the hands-on approach which starts form the ground-up, explaining with basic examples what power is, how it is measured and how it impacts on the design process of application-specific integrated circuits (ASICs).  The authors use both the Unified Power Format (UPF) and Common Power Format (CPF) to describe in detail the power intent for an ASIC and then guide readers through a variety of architectural and implementation techniques that will help meet the power intent.  From analyzing system power consumption, to techniques that can employed in a low power design, to a detailed description of two alternate standards for capturing the power directives at various phases of the design, this book is filled with information that will give ASIC designers a competitive edge in low-power design. Starts from the ground-up and explains what power is, how it is measur...

  4. Four-channel readout ASIC for silicon pad detectors

    CERN Document Server

    Baturitsky, M A

    2000-01-01

    A custom front-end readout ASIC has been designed for silicon calorimeters supposed to be used in high-energy physics experiments. The ASIC was produced using BJT-JFET technology. It contains four channels of a fast low-noise charge-sensitive preamplifier (CSP) with inverting outputs summed by a linear adder (LA) followed by an RC-CR shaping amplifier (SA) with 30 ns peaking time. Availability of separate outputs of the CSPs and the LA makes it possible to join any number of silicon detector layers to obtain the longitudinal and transversal resolution required using only this ASIC in any silicon calorimeter minitower configuration. Noise performance is ENC=1800e sup - +18e sup - /pF at 30 ns peaking time for detector capacitance up to C sub d =400 pF. Rise time is 8 ns at input capacitance C sub d =100 pF. Power dissipation is less than 50 mW/ chip at voltage supply 5 V.

  5. ASIC3 Channels Integrate Agmatine and Multiple Inflammatory Signals through the Nonproton Ligand Sensing Domain

    Directory of Open Access Journals (Sweden)

    Cao Hui

    2010-12-01

    Full Text Available Abstract Background Acid-sensing ion channels (ASICs have long been known to sense extracellular protons and contribute to sensory perception. Peripheral ASIC3 channels represent natural sensors of acidic and inflammatory pain. We recently reported the use of a synthetic compound, 2-guanidine-4-methylquinazoline (GMQ, to identify a novel nonproton sensing domain in the ASIC3 channel, and proposed that, based on its structural similarity with GMQ, the arginine metabolite agmatine (AGM may be an endogenous nonproton ligand for ASIC3 channels. Results Here, we present further evidence for the physiological correlation between AGM and ASIC3. Among arginine metabolites, only AGM and its analog arcaine (ARC activated ASIC3 channels at neutral pH in a sustained manner similar to GMQ. In addition to the homomeric ASIC3 channels, AGM also activated heteromeric ASIC3 plus ASIC1b channels, extending its potential physiological relevance. Importantly, the process of activation by AGM was highly sensitive to mild acidosis, hyperosmolarity, arachidonic acid (AA, lactic acid and reduced extracellular Ca2+. AGM-induced ASIC3 channel activation was not through the chelation of extracellular Ca2+ as occurs with increased lactate, but rather through a direct interaction with the newly identified nonproton ligand sensing domain. Finally, AGM cooperated with the multiple inflammatory signals to cause pain-related behaviors in an ASIC3-dependent manner. Conclusions Nonproton ligand sensing domain might represent a novel mechanism for activation or sensitization of ASIC3 channels underlying inflammatory pain-sensing under in vivo conditions.

  6. Precision BiCMOS successive approximation analog-to-digital converter with low power consumption

    International Nuclear Information System (INIS)

    An IP block of a successive approximation analog-to-digital converter (ADC) with low power consumption has been developed as a part of an application-specific integrated circuit (ASIC) for an intellectual flow meter. The advantages of the application of the modified “top-down” design method to the design of the chip have been demonstrated. The results of the simulation, verification, and test of the analog-to-digital converter are presented

  7. HDL Design for 1 Zetta Bits Per Second (1 Zbps Multichannel 64:1 LVDS Data Serializer & De-Serializer ASIC Array Card Design for 6th Sense and Future Ultra High Wireless and Mobile Communication Protocol Cards

    Directory of Open Access Journals (Sweden)

    P. N. V. M SASTRY

    2015-01-01

    Full Text Available The Aim is to HDL Design & Implementation for Exa Bit Rate Multichannel 64:1 LVDS Data Serializer & De-Serializer ASIC Array Card for Ultra High Speed Wireless Communication Products like Network On Chip Routers, Data Bus Communication Interface Applications, Cloud Computing Networks , Zetta bit Ethernet at Zetta Bit Rate Of Data Transfer Speed. Basically This Serializer Array Converts 64 bit parallel Data Array in to Serial Array Form on Transmitter Side and Transmission Done through High Speed Wireless Serial Communication Link and also Converts this Same Serial Array Data into Parallel Data Array on the Receiver Side by De-Serializer Array ASIC without any noise, also measure Very High Compressed Jitter Tolerance & Eye Diagram, Bit Error Rate through Analyzer. This LVDS Data SER-De-SER mainly used in High Speed Bus Communication Protocol Transceivers, Interface FPGA Add On Cards. The Process Of Design is Implemented through Verilog HDL / VHDL, Programming & Debugging Done Latest FPGA Board.

  8. ASIC3 Is Required for Development of Fatigue-Induced Hyperalgesia.

    Science.gov (United States)

    Gregory, Nicholas S; Brito, Renan G; Fusaro, Maria Cláudia G Oliveira; Sluka, Kathleen A

    2016-03-01

    An acute bout of exercise can exacerbate pain, hindering participation in regular exercise and daily activities. The mechanisms underlying pain in response to acute exercise are poorly understood. We hypothesized that proton accumulation during muscle fatigue activates acid-sensing ion channel 3 (ASIC3) on muscle nociceptors to produce hyperalgesia. We investigated the role of ASIC3 using genetic and pharmacological approaches in a model of fatigue-enhanced hyperalgesia. This model uses two injections of pH 5.0 saline into muscle in combination with an electrically induced fatigue of the same muscle just prior to the second injection of acid to induce mechanical hyperalgesia. We show a significant decrease in muscle force and decrease in muscle pH after 6 min of electrical stimulation. Genetic deletion of ASIC3 using knockout mice and pharmacological blockade of ASIC3 with APETx2 in muscle prevents the fatigue-enhanced hyperalgesia. However, ASIC3(-/-) mice and APETx2 have no effect on the fatigue response. Genetic deletion of ASIC3 in primary afferents innervating muscle using an HSV-1 expressing microRNA (miRNA) to ASIC3 surprisingly had no effect on the development of the hyperalgesia. Muscle fatigue increased the number of macrophages in muscle, and removal of macrophages from muscle with clodronate liposomes prevented the development of fatigue-enhanced hyperalgesia. Thus, these data suggest that fatigue reduces pH in muscle that subsequently activates ASIC3 on macrophages to enhance hyperalgesia to muscle insult. PMID:25577172

  9. Performance of 2nd generation CALICE/EUDET ASICs

    Science.gov (United States)

    de La Taille, C.; CALICE Collaboration; EUDET Collaboration

    2011-04-01

    The paper reviews the performance of the three ASICs : HARDROC2, SPIROC2 and SKIROC2 developed to readout the ILC calorimeter prototypes. The chips integrate 36 to 64 channels of front-end, digitization and backend electronics in SiGe 0.35 μm technology. This second version was found mature enough to be produced in several hundreds to equip large scale technological prototypes and establish the feasibility of these highly granular "imaging" calorimeters as required for particle flow algorithms at the ILC. The low noise and low power sequential readout as well as power-pulsing operation at detector level and in magnetic field are proven.

  10. 0.18μm CMOS, MONOLITHIC MSTP ASIC

    Institute of Scientific and Technical Information of China (English)

    Wang Peng; Jin Depeng; Zeng Lieguang

    2006-01-01

    A highly integrated monolithic Multi-Service Transport Platform (MSTP) Application Specified Integrated Circuit (ASIC) MSEOSX8-6 has been fabricated with 0.18μm CMOS technology incorporating 26×106 transistors. The chip is designed to provide standard framing and mapping of 10/100/1000Mbit/s Ethernet, Resilient Packet Ring (RPR) and E1 traffics into protected Synchronous Digital Hierarchy (SDH) STM-1 transport payloads using hitless rate adaptation for optimum bandwidth utilization. It consumes 4W of power on average and utilizes 756 pin enhanced BGA package.

  11. HDL code analysis for ASICs in mobile systems

    OpenAIRE

    Wickberg, Fredrik

    2007-01-01

    The complex work of designing new ASICs today and the increasing costs of time to market (TTM) delays are putting high responsibility on the research and development teams to make fault free designs. The main purpose of implementing a static rule checking tool in the design flow today is to find errors and bugs in the hardware definition language (HDL) code as fast and soon as possible. The sooner you find a bug in the design, the shorter the turnaround time becomes, and thereby both time and...

  12. PICK1 regulates the trafficking of ASIC1a and acidotoxicity in a BAR domain lipid binding-dependent manner

    Directory of Open Access Journals (Sweden)

    Jin Wenying

    2010-12-01

    Full Text Available Abstract Background Acid-sensing ion channel 1a (ASIC1a is the major ASIC subunit determining acid-activated currents in brain neurons. Recent studies show that ASIC1a play critical roles in acid-induced cell toxicity. While these studies raise the importance of ASIC1a in diseases, mechanisms for ASIC1a trafficking are not well understood. Interestingly, ASIC1a interacts with PICK1 (protein interacting with C-kinase 1, an intracellular protein that regulates trafficking of several membrane proteins. However, whether PICK1 regulates ASIC1a surface expression remains unknown. Results Here, we show that PICK1 overexpression increases ASIC1a surface level. A BAR domain mutant of PICK1, which impairs its lipid binding capability, blocks this increase. Lipid binding of PICK1 is also required for PICK1-induced clustering of ASIC1a. Consistent with the effect on ASIC1a surface levels, PICK1 increases ASIC1a-mediated acidotoxicity and this effect requires both the PDZ and BAR domains of PICK1. Conclusions Taken together, our results indicate that PICK1 regulates trafficking and function of ASIC1a in a lipid binding-dependent manner.

  13. Multichannel readout ASIC design flow for high energy physics and cosmic rays experiments

    Science.gov (United States)

    Voronin, A.; Malankin, E.

    2016-02-01

    In the large-scale high energy physics and astrophysics experiments multi-channel readout application specific integrated circuits (ASICs) are widely used. The ASICs for such experiments are complicated systems, which usually include both analog and digital building blocks. The complexity and large number of channels in such ASICs require the proper methodological approach to their design. The paper represents the mixed-signal design flow of the ASICs for high energy physics and cosmic rays experiments. This flow was successfully embedded to the development of the read-out ASIC prototype for the muon chambers of the CBM experiment. The approach was approved in UMC CMOS MMRF 180 nm process. The design flow enable to analyse the mixed-signal system operation on the different levels: functional, behavioural, schematic and post layout including parasitic elements. The proposed design flow allows reducing the simulation period and eliminating the functionality mismatches on the very early stage of the design.

  14. Exploring Many-Core Design Templates for FPGAs and ASICs

    Directory of Open Access Journals (Sweden)

    Ilia Lebedev

    2012-01-01

    Full Text Available We present a highly productive approach to hardware design based on a many-core microarchitectural template used to implement compute-bound applications expressed in a high-level data-parallel language such as OpenCL. The template is customized on a per-application basis via a range of high-level parameters such as the interconnect topology or processing element architecture. The key benefits of this approach are that it (i allows programmers to express parallelism through an API defined in a high-level programming language, (ii supports coarse-grained multithreading and fine-grained threading while permitting bit-level resource control, and (iii reduces the effort required to repurpose the system for different algorithms or different applications. We compare template-driven design to both full-custom and programmable approaches by studying implementations of a compute-bound data-parallel Bayesian graph inference algorithm across several candidate platforms. Specifically, we examine a range of template-based implementations on both FPGA and ASIC platforms and compare each against full custom designs. Throughout this study, we use a general-purpose graphics processing unit (GPGPU implementation as a performance and area baseline. We show that our approach, similar in productivity to programmable approaches such as GPGPU applications, yields implementations with performance approaching that of full-custom designs on both FPGA and ASIC platforms.

  15. Replication of Space-Shuttle Computers in FPGAs and ASICs

    Science.gov (United States)

    Ferguson, Roscoe C.

    2008-01-01

    A document discusses the replication of the functionality of the onboard space-shuttle general-purpose computers (GPCs) in field-programmable gate arrays (FPGAs) and application-specific integrated circuits (ASICs). The purpose of the replication effort is to enable utilization of proven space-shuttle flight software and software-development facilities to the extent possible during development of software for flight computers for a new generation of launch vehicles derived from the space shuttles. The replication involves specifying the instruction set of the central processing unit and the input/output processor (IOP) of the space-shuttle GPC in a hardware description language (HDL). The HDL is synthesized to form a "core" processor in an FPGA or, less preferably, in an ASIC. The core processor can be used to create a flight-control card to be inserted into a new avionics computer. The IOP of the GPC as implemented in the core processor could be designed to support data-bus protocols other than that of a multiplexer interface adapter (MIA) used in the space shuttle. Hence, a computer containing the core processor could be tailored to communicate via the space-shuttle GPC bus and/or one or more other buses.

  16. Characterization results of the JUNGFRAU full scale readout ASIC

    Science.gov (United States)

    Mozzanica, A.; Bergamaschi, A.; Brueckner, M.; Cartier, S.; Dinapoli, R.; Greiffenberg, D.; Jungmann-Smith, J.; Maliakal, D.; Mezza, D.; Ramilli, M.; Ruder, C.; Schaedler, L.; Schmitt, B.; Shi, X.; Tinti, G.

    2016-02-01

    The two-dimensional pixel detector JUNGFRAU is designed for high performance photon science applications at free electron lasers and synchrotron light sources. It is developed for the SwissFEL currently under construction at the Paul Scherrer Institut, Switzerland. The detector is a hybrid pixel detector with a charge integration readout ASIC characterized by single photon sensitivity and a low noise performance over a dynamic range of 104 12 keV photons. Geometrically, a JUNGFRAU readout chip consists of 256×256 pixels of 75×75 μm2. The chips are bump bonded to 320 μm thick silicon sensors. Arrays of 2×4 chips are tiled to form modules of 4×8 cm2 area. Several multi-module systems with up to 16 Mpixels per system will be delivered to the two end stations at SwissFEL. The JUNGFRAU full scale readout ASIC and module design are presented along with characterization results of the first systems. Experiments from fluorescence X-ray, visible light illumination, and synchrotron irradiation are shown. The results include an electronic noise of ~50 electrons r.m.s., which enables single photon detection energies below 2 keV and a noise well below the Poisson statistical limit over the entire dynamic range. First imaging experiments are also shown.

  17. Interaction of Acid-sensing Ion Channel (ASIC) 1 with the Tarantula Toxin Psalmotoxin 1 is State Dependent

    OpenAIRE

    Chen, Xuanmao; Kalbacher, Hubert; Gründer, Stefan

    2006-01-01

    Acid-sensing ion channels (ASICs) are Na+ channels gated by extracellular H+. Six ASIC subunits that are expressed in neurons have been characterized. The tarantula toxin psalmotoxin 1 has been reported to potently and specifically inhibit homomeric ASIC1a and has been useful to characterize ASICs in neurons. Recently we have shown that psalmotoxin 1 inhibits ASIC1a by increasing its apparent affinity for H+. However, the mechanism by which PcTx1 increases the apparent H+ affinity remained un...

  18. A 256 channel 8-Bit current digitizer ASIC for the Belle-II PXD

    International Nuclear Information System (INIS)

    The international DEPFET collaboration is developing a silicon pixel vertex detector (PXD), based on monolithic arrays of DEPFET transistors, for the future physics experiment Belle-II at the SuperKEKB particle accelerator in Japan. The matrix elements are read out in a 'rolling shutter mode', i.e. rows are selected consecutively and all columns are read out in each cycle of < 100 ns. One of the major parts in the front-end electronics chain is the DEPFET Current Digitizer ASIC (DCDB). It is now in a close-to-final state. The chip provides 256 channels of analog-to-digital converters with a resolution of six to eight bits. Each converter features an individual dynamic offset correction circuit as well as programmable gain and bandwidth. Several operation modes using single sampling or double correlated sampling are possible. A large synthesized digital block is used for decoding and derandomization of the conversion results. The data is put out on eight 8-bit links, operating at a speed of 400 MHz. Additionally, a JTAG compatible interface is implemented for configuration and debugging purpose. Significant effort was made to reduce the power consumption of the DCDB, since both, voltage drop on the internal power buses and heat sources in the Belle-II experiment are a concern. The chip was realized on a 3.2mm x 5mm die using the UMC 180nm CMOS technology in a multi-project wafer run, provided by EuroPractice. An extra redistribution metal layer with bump bond pads is used, allowing for flipping the chip onto the final all-silicon DEPFET sensor module. Several tests have been performed in order to prove the chip's operation and its quality in terms of noise. The results are presented.

  19. Radiation-hard ASICs for optical data transmission in the first phase of the LHC upgrade

    CERN Document Server

    Gan, K K; Kagan, H P; Kass, R D; Moore, J R; Smith, D S; Wiese, A; Ziolkowskic, M; 10.1088/1748-0221/5/12/C12006

    2010-01-01

    We have designed two ASICs for possible applications in the optical links of a new layer of the pixel detector to be install inside the ATLAS Pixel detector for the first phase of the LHC luminosity upgrade. The ASICs include a high-speed driver for the VCSEL and a receiver/decoder to decode the signal received at the PIN diode to extract the data and clock. Both ASICs contain 4 channels for operation with a VCSEL or PIN array. The ASICs were designed using a 130 nm CMOS process to enhance the radiation-hardness. We have characterized the fabricated ASICs and the performance of the ASICs is satisfactory. The receiver/decoder can properly decode the bi-phase marked input stream with low PIN current and the driver can operate a VCSEL up to ~ 5 Gb/s. The added functionalities are also successful, including redundancy to bypass a broken VCSEL or PIN channel, individual control of VCSEL current, and power-on reset circuit to set all VCSEL currents to a nominal value. The ASICs were irradiated to a dose of 46 Mrad ...

  20. Wavelength Converters

    DEFF Research Database (Denmark)

    Kloch, Allan; Hansen, Peter Bukhave; Wolfson, David;

    1999-01-01

    at 2.5 Gbit/s, the regeneration causes a reduction of the required input power to an in-line EDFA of ~6 dB for a power penalty of 1 dB at a bit error rate of 10-9. If two converters are concatenated the power requirement is reduced ~8 dB. Obviously, the power reduction allows for longer spans between....... It is predicted that jitter accumulation can be minimised by using a 9-10 dB ratio between the signal and CW power also assuring a high extinction ratio. Using this guideline simulations show that 20 cross-gain modulation converters can be cascaded at 10 Gbit/s with only ~20 ps of accumulated jitter...... and an extinction ratio of ~10 dB.The regenerative capabilities of the cross-phase converters are described and verified experimentally at 20 Gbit/s, where the noise redistribution and improvement of the signal-to-noise ratio clearly is demonstrated by controlling the input power to an EDFA. In a similar experiment...

  1. ASIC Design of Floating-Point FFT Processor

    Institute of Scientific and Technical Information of China (English)

    陈禾; 赵忠武

    2004-01-01

    An application specific integrated circuit (ASIC) design of a 1024 points floating-point fast Fourier transform(FFT) processor is presented. It can satisfy the requirement of high accuracy FFT result in related fields. Several novel design techniques for floating-point adder and multiplier are introduced in detail to enhance the speed of the system. At the same time, the power consumption is decreased. The hardware area is effectively reduced as an improved butterfly processor is developed. There is a substantial increase in the performance of the design since a pipelined architecture is adopted, and very large scale integrated (VLSI) is easy to realize due to the regularity. A result of validation using field programmable gate array (FPGA) is shown at the end. When the system clock is set to 50 MHz, 204.8 μs is needed to complete the operation of FFT computation.

  2. Macro Pixel ASIC (MPA): The readout ASIC for the pixel-strip (PS) module of the CMS outer tracker at HL-LHC

    CERN Document Server

    Ceresa, Davide; Kloukinas, Konstantinos; Jan Kaplon; Bialas, Wojciech; Re, Valerio; Traversi, Gianluca; Gaioni, Luigi; Ratti, Lodovico

    2014-01-01

    The CMS tracker at HL-LHC is required to provide prompt information on particles with high transverse momentum to the central Level\\,1 trigger. For this purpose, the innermost part of the outer tracker is based on a combination of a pixelated sensor with a short strip sensor, the so-called Pixel-Strip module (PS). The readout of these sensors is carried out by distinct ASICs, the Strip Sensor ASIC (SSA), for the strip layer, and the Macro Pixel ASIC (MPA) for the pixel layer. The processing of the data directly on the front-end module represents a design challenge due to the large data volume (30720\\,pixels and 1920\\,strips per module) and the limited power budget. This is the reason why several studies have been carried out to find the best compromise between ASICs performance and power consumption. This paper describes the current status of the MPA ASIC development where the logic for generating prompt information on particles with high transverse momentum is implemented. An overview of the readout method i...

  3. ASIC2 is present in human mechanosensory neurons of the dorsal root ganglia and in mechanoreceptors of the glabrous skin.

    Science.gov (United States)

    Cabo, R; Alonso, P; Viña, E; Vázquez, G; Gago, A; Feito, J; Pérez-Moltó, F J; García-Suárez, O; Vega, J A

    2015-03-01

    Mechanosensory neurons lead to the central nervous system touch, vibration and pressure sensation. They project to the periphery and form different kinds of mechanoreceptors. The manner in which they sense mechanical signals is still not fully understood, but electrophysiological experiments have suggested that this may occur through the activation of ion channels that gate in response to mechanical stimuli. The acid-sensing ion channels (ASICs), especially ASIC2, may function as mechanosensors or are required for mechanosensation, and they are expressed in both mechanosensory neurons and mechanoreceptors. Here, we have used double immunohistochemistry for ASIC2 together with neuronal and glial markers associated with laser confocal microscopy and image analysis, to investigate the distribution of ASIC2 in human lumbar dorsal root ganglia, as well as in mechanoreceptors of the hand and foot glabrous skin. In lumbar dorsal root ganglia, ASIC2 immunoreactive neurons were almost all intermediate or large sized (mean diameter ≥20-70 µm), and no ASIC2 was detected in the satellite glial. ASIC2-positive axons were observed in Merkel cell-neurite complexes, Meissner and Pacinian corpuscles, all of them regarded as low-threshold mechanoreceptors. Moreover, a variable percent of Meissner (8 %) and Pacinian corpuscles (27 %) also displayed ASIC2 immunoreactivity in the Schwann-related cells. These results demonstrate the distribution of ASIC2 in the human cutaneous mechanosensory system and suggest the involvement of ASIC2 in mechanosensation.

  4. High-Speed, Low Power 256 Channel Gamma Radiation Array Detector ASIC Project

    Data.gov (United States)

    National Aeronautics and Space Administration — Building on prior success in detector electronics, we propose to design and fabricate a 256 channel readout ASIC for solid state gamma radiation array detectors...

  5. Wide Temperature Rad-Hard ASIC for Process Control of a Fuel Cell System Project

    Data.gov (United States)

    National Aeronautics and Space Administration — Ridgetop Group developed a top-level design of a rad-hard application-specific integrated circuit (ASIC) for spacecraft power management that is functional over a...

  6. Structure and erosion resistance ofNi60A/SiC coatting by laser cladding

    Institute of Scientific and Technical Information of China (English)

    LOU Bai-yang; CHEN Zhen; BAI Wan-jin; DONG Gang

    2006-01-01

    The Ni60A and Ni60A/SiC coatings were obtained by laser cladding on 0.45% C steel. The microstructure and hardness of the coatings were studied by SEM and XRD. The erosion resistances of Ni60A and Ni60A/SiC coatings were also investigated. The results show that the structure of different coatings is up to the temperature gradient and solidifying velocity in metal-melting region during laser cladding process. The coatings consist of a cladding layer, in which dendritic crystal and bulky cell-like crystal exist mainly, and a thermo-affected layer. Ni60A/SiC coating has higher microhardness than that of Ni60A coating, which is mainly caused by SiC and complicated phases formed by Ni, Cr, Fe, C and Si. It is obvious from the erosion test that the Ni60A/SiC coating has high erosion resistance.

  7. Radiation-hard ASICs for optical data transmission in the first phase of the LHC upgrade

    Science.gov (United States)

    Gan, K. K.; Buchholz, P.; Kagan, H. P.; Kass, R. D.; Moore, J. R.; Smith, D. S.; Wiese, A.; Ziolkowskic, M.

    2011-06-01

    We have designed two ASICs for possible applications in the optical links of a new layer of the pixel detector to be install inside the ATLAS Pixel detector for the first phase of the LHC luminosity upgrade. The ASICs include a high-speed driver for a VCSEL and a receiver/decoder to decode the signal received at a PIN diode to extract the data and clock. Both ASICs contain 4 channels for operation with a VCSEL or PIN array. The ASICs were designed using a 130 nm CMOS process to enhance the radiation-hardness. We have characterized the fabricated ASICs and the performance of the ASICs is satisfactory. The receiver/decoder properly decodes the bi-phase marked input stream with low PIN current and the driver can operate a VCSEL up to ˜5 Gb/s. The added functionalities are also successful, including redundancy to bypass a broken VCSEL or PIN channel, individual control of VCSEL current, and power-on reset circuit to set all VCSEL currents to a nominal value.

  8. ASICs Do Not Play a Role in Maintaining Hyperalgesia Induced by Repeated Intramuscular Acid Injections

    Directory of Open Access Journals (Sweden)

    Mamta Gautam

    2012-01-01

    Full Text Available Repeated intramuscular acid injections produce long-lasting mechanical hyperalgesia that depends on activation of ASICs. The present study investigated if pH-activated currents in sensory neurons innervating muscle were altered in response to repeated acid injections, and if blockade of ASICs reverses existing hyperalgesia. In muscle sensory neurons, the mean acid-evoked current amplitudes and the biophysical properties of the ASIC-like currents were unchanged following acidic saline injections when compared to neutral pH saline injections or uninjected controls. Moreover, increased mechanical sensitivity of the muscle and paw after the second acid injection was unaffected by local blockade of ASICs (A-317567 in the muscle. As a control, electron microscopic analysis showed that the tibial nerve was undamaged after acid injections. Our previous studies demonstrated that ASICs are important in the development of hyperalgesia to repeated acid injections. However, the current data suggest that ASICs are not involved in maintaining hyperalgesia to repeated intramuscular acid injections.

  9. ASIC3, an acid-sensing ion channel, is expressed in metaboreceptive sensory neurons

    Directory of Open Access Journals (Sweden)

    Fierro Leonardo

    2005-11-01

    Full Text Available Abstract Background ASIC3, the most sensitive of the acid-sensing ion channels, depolarizes certain rat sensory neurons when lactic acid appears in the extracellular medium. Two functions have been proposed for it: 1 ASIC3 might trigger ischemic pain in heart and muscle; 2 it might contribute to some forms of touch mechanosensation. Here, we used immunocytochemistry, retrograde labelling, and electrophysiology to ask whether the distribution of ASIC3 in rat sensory neurons is consistent with either of these hypotheses. Results Less than half (40% of dorsal root ganglion sensory neurons react with anti-ASIC3, and the population is heterogeneous. They vary widely in cell diameter and express different growth factor receptors: 68% express TrkA, the receptor for nerve growth factor, and 25% express TrkC, the NT3 growth factor receptor. Consistent with a role in muscle nociception, small ( Conclusion Our data indicates that: 1 ASIC3 is expressed in a restricted population of nociceptors and probably in some non-nociceptors; 2 co-expression of ASIC3 and CGRP, and the absence of P2X3, are distinguishing properties of a class of sensory neurons, some of which innervate blood vessels. We suggest that these latter afferents may be muscle metaboreceptors, neurons that sense the metabolic state of muscle and can trigger pain when there is insufficient oxygen.

  10. PETA4: a multi-channel TDC/ADC ASIC for SiPM readout

    Science.gov (United States)

    Sacco, I.; Fischer, P.; Ritzert, M.

    2013-12-01

    The PETA4 ASIC is the latest member of a family of chips targeted mainly at the readout of Silicon Photomultipliers in PET, with possible use in other detector applications. PETA4 houses 36 channels on a 5 × 5mm2 die and is fabricated in the UMC 180nm technology. It uses bump bonds with a convenient pitch of ≈ 270μm to allow the construction of very compact modules at moderate substrate cost. The chip requires nearly no external components by integrating everything (PLL loop filter, bandgap reference, bias DACs,...) on chip. Power consumption is <= 40mW per channel, depending on digital speed and bias settings. Every channel has two independent frontends: an established differential amplifier which has shown to be insensitive to pickup in the target application of PET/MRI, and a single-ended frontend with very low input impedance (Zin ≈ 7Ω) for high channel count operation. A fast discriminator with tunable threshold and a noise of <= 300μV self-triggers time stamping with a bin width of 50ps as well as an integrator with programmable integration time. The amplitude signal is converted by a ≈ 9-bit SAR ADC. After conversion, events with sufficient amplitude are queued for serial readout. The previous chip version PETA3 has achieved a CRT time resolution of ≈ 200ps when reading out scintillation light from a 3 × 3×5mm3 LYSO crystal coupled at room temperature to a 3 × 3mm2 SiPM from FBK. Energy resolution for LYSO is ≈ 12.5%FWHM. LYSO crystals of 1.3mm size could be clearly identified with SiPMs of 4 × 4mm2 when using a light spreader. The architecture of PETA4 and its performance in the lab and with SiPMs will be presented.

  11. Non-ideal effects of MOS capacitor in a switched capacitor waveform recorder ASIC

    Science.gov (United States)

    Zhang, Hong-Yan; Deng, Zhi; Liu, Yi-Nong

    2016-07-01

    SCAs (Switched Capacitor Arrays) have a wide range of uses, especially in high energy physics, nuclear science and astrophysics experiments. This paper presents a method of using a MOS capacitor as a sampling capacitor to gain larger capacitance with small capacitor area in SCA design. It studies the non-ideal effects of the MOS capacitor and comes up with ways to reduce these adverse effects. A prototype SCA ASIC which uses a MOS capacitor to store the samples has been designed and tested to verify this method. The SCA integrates 32 channels and each has 64 cells and a readout amplifier. The stored voltage is converted to a pair of differential currents (±4 mA max) and multiplexed to the output. All the functionalities have been verified. The power consumption is less than 2 mW/ch. The INL of all the cells in one channel are better than 0.39%. The equivalent input noise of the SCA has been tested to be 2.2 mV with 625 kHz full-scale sine wave as input, sampling at 40 MSPS (Mega-samples per Second) and reading out at 5 MHz. The effective resolution is 8.8 bits considering 1 V dynamic range. The maximum sampling rate reaches up to 50 MSPS and readout rate of 15 MHz to keep noise smaller than 2.5 mV. The test results validate the feasibility of the MOS capacitor. Supported by National Natural Science Foundation of China (11375100), Strategic Pioneer Program on Space Sciences, Chinese Academy of Sciences (XDA04060606-06) and State Key Laboratory of Particle Detection and Electronics

  12. PETA4: a multi-channel TDC/ADC ASIC for SiPM readout

    International Nuclear Information System (INIS)

    The PETA4 ASIC is the latest member of a family of chips targeted mainly at the readout of Silicon Photomultipliers in PET, with possible use in other detector applications. PETA4 houses 36 channels on a 5 × 5mm2 die and is fabricated in the UMC 180nm technology. It uses bump bonds with a convenient pitch of ≈ 270μm to allow the construction of very compact modules at moderate substrate cost. The chip requires nearly no external components by integrating everything (PLL loop filter, bandgap reference, bias DACs,...) on chip. Power consumption is ≤ 40mW per channel, depending on digital speed and bias settings. Every channel has two independent frontends: an established differential amplifier which has shown to be insensitive to pickup in the target application of PET/MRI, and a single-ended frontend with very low input impedance (Zin ≈ 7Ω) for high channel count operation. A fast discriminator with tunable threshold and a noise of ≤ 300μV self-triggers time stamping with a bin width of 50ps as well as an integrator with programmable integration time. The amplitude signal is converted by a ≈ 9-bit SAR ADC. After conversion, events with sufficient amplitude are queued for serial readout. The previous chip version PETA3 has achieved a CRT time resolution of ≈ 200ps when reading out scintillation light from a 3 × 3×5mm3 LYSO crystal coupled at room temperature to a 3 × 3mm2 SiPM from FBK. Energy resolution for LYSO is ≈ 12.5%FWHM. LYSO crystals of 1.3mm size could be clearly identified with SiPMs of 4 × 4mm2 when using a light spreader. The architecture of PETA4 and its performance in the lab and with SiPMs will be presented

  13. Design and Performance of a Custom ASIC Digitizer for Wire Chamber Readout in 65 nm CMOS Technology

    CERN Document Server

    Lee, MyeongJae; Chang, Jessica K; Ding, Dawei; Gnani, Dario; Grace, Carl R; Jones, John A; Kolomensky, Yury G; von der Lippe, Henrik; Mcvittie, Patrick J; Stettler, Matthew W; Walder, Jean-Pierre

    2015-01-01

    We present the design and performance of a prototype ASIC digitizer for integrated wire chamber readout, implemented in 65 nm commercial CMOS technology. Each channel of the 4-channel prototype is composed of two 16-bit Time-to-Digital Converters (TDCs), one 8-bit Analog-to-Digital Converter (ADC), a front-end preamplifier and shaper, plus digital and analog buffers that support a variety of digitization chains. The prototype has a multiplexed digital backend that executes a state machine, distributes control and timing signals, and buffers data for serial output. Laboratory bench tests measure the absolute TDC resolution between 74 ps and 480 ps, growing with the absolute delay, and a relative time resolution of 19 ps. Resolution outliers due to cross-talk between clock signals and supply or reference voltages are seen. After calibration, the ADC displays good linearity and noise performance, with an effective number of bits of 6.9. Under normal operating conditions the circuit consumes 32 mW per channel. Po...

  14. Design and performance of a custom ASIC digitizer for wire chamber readout in 65 nm CMOS technology

    Science.gov (United States)

    Lee, M. J.; Brown, D. N.; Chang, J. K.; Ding, D.; Gnani, D.; Grace, C. R.; Jones, J. A.; Kolomensky, Y. G.; von der Lippe, H.; Mcvittie, P. J.; Stettler, M. W.; Walder, J.-P.

    2015-06-01

    We present the design and performance of a prototype ASIC digitizer for integrated wire chamber readout, implemented in 65 nm commercial CMOS technology. Each channel of the 4-channel prototype is composed of two 16-bit Time-to-Digital Converters (TDCs), one 8-bit Analog-to-Digital Converter (ADC), a front-end preamplifier and shaper, plus digital and analog buffers that support a variety of digitization chains. The prototype has a multiplexed digital backend that executes a state machine, distributes control and timing signals, and buffers data for serial output. Laboratory bench tests measure the absolute TDC resolution between 74 ps and 480 ps, growing with the absolute delay, and a relative time resolution of 19 ps. Resolution outliers due to cross-talk between clock signals and supply or reference voltages are seen. After calibration, the ADC displays good linearity and noise performance, with an effective number of bits of 6.9. Under normal operating conditions the circuit consumes 32 mW per channel. Potential design improvements to address the resolution drift and tails are discussed.

  15. Radiation hardness studies of the front-end ASICs for the optical links of the ATLAS semiconductor tracker

    CERN Document Server

    White, D J; Mahout, G; Jovanovic, P; Mandic, I; Weidberg, A R

    2001-01-01

    Studies have been performed on the effects of radiation on ASICs incorporating bipolar npn transistors in the AMS 0.8 mu m BiCMOS process. Radiation effects are reviewed and the approach used to achieve radiation tolerant ASICs is described. The radiation tests required to validate the ASICs for use in the ATLAS detector at the CERN Large Hadron Collider are discussed. The results demonstrate that they are sufficiently radiation tolerant for use in the ATLAS semiconductor tracker. (20 refs).

  16. Development of low-noise high-speed analog ASIC for X-ray CCD cameras and wide-band X-ray imaging sensors

    Science.gov (United States)

    Nakajima, Hiroshi; Hirose, Shin-nosuke; Imatani, Ritsuko; Nagino, Ryo; Anabuki, Naohisa; Hayashida, Kiyoshi; Tsunemi, Hiroshi; Doty, John P.; Ikeda, Hirokazu; Kitamura, Hisashi; Uchihori, Yukio

    2016-09-01

    We report on the development and performance evaluation of the mixed-signal Application Specific Integrated Circuit (ASIC) developed for the signal processing of onboard X-ray CCD cameras and various types of X-ray imaging sensors in astrophysics. The quick and low-noise readout is essential for the pile-up free imaging spectroscopy with a future X-ray telescope. Our goal is the readout noise of 5e- r . m . s . at the pixel rate of 1 Mpix/s that is about 10 times faster than those of the currently working detectors. We successfully developed a low-noise ASIC as the front-end electronics of the Soft X-ray Imager onboard Hitomi that was launched on February 17, 2016. However, it has two analog-to-digital converters per chain due to the limited processing speed and hence we need to correct the difference of gain to obtain the X-ray spectra. Furthermore, its input equivalent noise performance is not satisfactory (> 100 μV) at the pixel rate higher than 500 kpix/s. Then we upgrade the design of the ASIC with the fourth-order ΔΣ modulators to enhance its inherent noise-shaping performance. Its performance is measured using pseudo CCD signals with variable processing speed. Although its input equivalent noise is comparable with the conventional one, the integrated non-linearity (0.1%) improves to about the half of that of the conventional one. The radiation tolerance is also measured with regard to the total ionizing dose effect and the single event latch-up using protons and Xenon, respectively. The former experiment shows that all of the performances does not change after imposing the dose corresponding to 590 years in a low earth orbit. We also put the upper limit on the frequency of the latch-up to be once per 48 years.

  17. ANUSANSKAR: a 16 channel frontend electronics (FEE) ASIC targeted for silicon pixel array detector based prototype Alice FOCAL

    International Nuclear Information System (INIS)

    ANUSANSKAR is a 16 channel pulse processing ASIC with analog multiplexed output designed in 0.7 um standard CMOS technology with each channel consisting of CSA, Semi Gaussian pulse shaper, DC cancellation and pedestal control, track and hold, output buffer blocks. The ASIC's analog multiplexed output can be read serially in daisy-chain topology. Testing, characterization and validation of ANUSANSKAR ASIC as readout for prototype ALICE forward calorimeter (FOCAL) has been carried out in PS beam line at CERN with up to 6 GeV of pion and electron beam. This paper describes the ANUSANSKAR ASIC along with the experimental results. (author)

  18. VeloPix ASIC development for LHCb VELO upgrade

    CERN Document Server

    van Beuzekom, M; Campbell, M; Collins, P; Gromov, V; Kluit, R; Llopart, X; Poikela, T; Wyllie, K; Zivkovic, V

    2013-01-01

    The upgrade of the LHCb experiment, planned for 2018, will transform the readout of the entire experiment to a triggerless system operating at 40 MHz. All data reduction algorithms will be run in a high level software farm, and will have access to event information from all subdetectors. This approach will give great power and fl exibility in accessing the physics channels of interest in the future, in particular the identi fi cation of fl avour tagged events with displaced vertices. The data acquisition and front end electronics systems require signi fi cant modi fi cation to cope with the enormous throughput of data. For the silicon vertex locator (VELO) a dedicated development is underway for a new ASIC, VeloPix, which will be a derivative of the Timepix/Medipix family of chips. The chip will be radiation hard and be able to cope with pixel hit rates of above 500 MHz, highly non-uniformly distributed over the 2 cm 2 chip area. The chip will incorporate local intelligence in the pixels for time-over-thresho...

  19. ASIC Readout Circuit Architecture for Large Geiger Photodiode Arrays

    Science.gov (United States)

    Vasile, Stefan; Lipson, Jerold

    2012-01-01

    The objective of this work was to develop a new class of readout integrated circuit (ROIC) arrays to be operated with Geiger avalanche photodiode (GPD) arrays, by integrating multiple functions at the pixel level (smart-pixel or active pixel technology) in 250-nm CMOS (complementary metal oxide semiconductor) processes. In order to pack a maximum of functions within a minimum pixel size, the ROIC array is a full, custom application-specific integrated circuit (ASIC) design using a mixed-signal CMOS process with compact primitive layout cells. The ROIC array was processed to allow assembly in bump-bonding technology with photon-counting infrared detector arrays into 3-D imaging cameras (LADAR). The ROIC architecture was designed to work with either common- anode Si GPD arrays or common-cathode InGaAs GPD arrays. The current ROIC pixel design is hardwired prior to processing one of the two GPD array configurations, and it has the provision to allow soft reconfiguration to either array (to be implemented into the next ROIC array generation). The ROIC pixel architecture implements the Geiger avalanche quenching, bias, reset, and time to digital conversion (TDC) functions in full-digital design, and uses time domain over-sampling (vernier) to allow high temporal resolution at low clock rates, increased data yield, and improved utilization of the laser beam.

  20. Design Specifications for a Radiation Tolerant Beam Loss Measurement ASIC

    CERN Document Server

    Venturini, G G; Effinger, E; Zamantzas, C

    2009-01-01

    A novel radiation-hardened current digitizer ASIC is in planning stage, aimed at the acquisition of the current signals from the ionization chambers employed in the Beam Loss Monitoring system at CERN. The purpose is to match and exceed the performance of the existing discrete component design, currently in operation in the Large Hadron Collider (LHC). The specifications include: a dynamic range of nine decades, defaulting to the 1 pA-1mA range but adjustable by the user, ability to withstand a total integrated dose of 10 kGy at least in 20 years of operation and user selectable integrating windows, as low as 500 ns. Moreover, the integrated circuit should be able to digitize currents of both polarity with a minimum number of external components and without needing any configuration. The target technology is the IBM 130nm CMOS process. The specifications, the architecture choices and the reasons on which they are based upon are discussed in this paper.

  1. VeloPix ASIC development for LHCb VELO upgrade

    Energy Technology Data Exchange (ETDEWEB)

    Beuzekom, M. van, E-mail: martinb@nikhef.nl [Nikhef, Science Park 105, 1098 XG Amsterdam (Netherlands); Buytaert, J.; Campbell, M.; Collins, P. [CERN, 1211 Geneva 23 (Switzerland); Gromov, V.; Kluit, R. [Nikhef, Science Park 105, 1098 XG Amsterdam (Netherlands); Llopart, X. [CERN, 1211 Geneva 23 (Switzerland); Poikela, T. [University of Turku, Department of Information Technology, FI-20014 Turun yliopisto (Finland); CERN, 1211 Geneva 23 (Switzerland); Wyllie, K. [CERN, 1211 Geneva 23 (Switzerland); Zivkovic, V. [Nikhef, Science Park 105, 1098 XG Amsterdam (Netherlands)

    2013-12-11

    The upgrade of the LHCb experiment, planned for 2018, will transform the readout of the entire experiment to a triggerless system operating at 40 MHz. All data reduction algorithms will be run in a high level software farm, and will have access to event information from all subdetectors. This approach will give great power and flexibility in accessing the physics channels of interest in the future, in particular the identification of flavour tagged events with displaced vertices. The data acquisition and front end electronics systems require significant modification to cope with the enormous throughput of data. For the silicon vertex locator (VELO) a dedicated development is underway for a new ASIC, VeloPix, which will be a derivative of the Timepix/Medipix family of chips. The chip will be radiation hard and be able to cope with pixel hit rates of above 500 MHz, highly non-uniformly distributed over the 2 cm{sup 2} chip area. The chip will incorporate local intelligence in the pixels for time-over-threshold measurements, time-stamping and sparse readout. It must in addition be low power, radiation hard, and immune to single event upsets. In order to cope with the datarates and use the pixel area most effectively, an on-chip data compression scheme will integrated. This paper will describe the requirements of the LHCb VELO upgrade, and give an overview of the digital architecture being developed specifically for the readout chip.

  2. FRONT-END ASIC FOR A SILICON COMPTON TELESCOPE.

    Energy Technology Data Exchange (ETDEWEB)

    DE GERONIMO,G.; FRIED, J.; FROST, E.; PHLIPS, B.; VERNON, E.; WULF, E.A.

    2007-10-27

    We describe a front-end application specific integrated circuit (ASIC) developed for a silicon Compton telescope. Composed of 32 channels, it reads out signals in both polarities from each side of a Silicon strip sensor, 2 mm thick 27 cm long, characterized by a strip capacitance of 30 pF. Each front-end channel provides low-noise charge amplification, shaping with a stabilized baseline, discrimination, and peak detection with an analog memory. The channels can process events simultaneously, and the read out is sparsified. The charge amplifier makes uses a dual-cascode configuration and dual-polarity adaptive reset, The low-hysteresis discriminator and the multi-phase peak detector process signals with a dynamic range in excess of four hundred. An equivalent noise charge (ENC) below 200 electrons was measured at 30 pF, with a slope of about 4.5 electrons/pF at a peaking time of 4 {micro}s. With a total dissipated power of 5 mW the channel covers an energy range up to 3.2 MeV.

  3. Functional and pharmacological characterization of two different ASIC1a/2a heteromers reveals their sensitivity to the spider toxin PcTx1.

    Science.gov (United States)

    Joeres, Niko; Augustinowski, Katrin; Neuhof, Andreas; Assmann, Marc; Gründer, Stefan

    2016-01-01

    Acid Sensing Ion Channels (ASICs) detect extracellular proton signals and are involved in synaptic transmission and pain sensation. ASIC subunits assemble into homo- and heteromeric channels composed of three subunits. Single molecule imaging revealed that heteromers composed of ASIC1a and ASIC2a, which are widely expressed in the central nervous system, have a flexible 2:1/1:2 stoichiometry. It was hitherto not possible, however, to functionally differentiate these two heteromers. To have a homogenous population of ASIC1a/2a heteromers with either 2:1 or 1:2 stoichiometry, we covalently linked subunits in the desired configuration and characterized their functional properties in Xenopus oocytes. We show that the two heteromers have slightly different proton affinity, with an additional ASIC1a subunit increasing apparent affinity. Moreover, we found that zinc, which potentiates ASIC2a-containing ASICs but not homomeric ASIC1a, potentiates both heteromers. Finally, we show that PcTx1, which binds at subunit-subunit interfaces of homomeric ASIC1a, inhibits both heteromers suggesting that ASIC2a can also contribute to a PcTx1 binding site. Using this functional fingerprint, we show that rat cortical neurons predominantly express the ASIC1a/2a heteromer with a 2:1 stoichiometry. Collectively, our results reveal the contribution of individual subunits to the functional properties of ASIC1a/2a heteromers. PMID:27277303

  4. Macro Pixel ASIC (MPA): the readout ASIC for the pixel-strip (PS) module of the CMS outer tracker at HL-LHC

    Science.gov (United States)

    Ceresa, D.; Marchioro, A.; Kloukinas, K.; Kaplon, J.; Bialas, W.; Re, V.; Traversi, G.; Gaioni, L.; Ratti, L.

    2014-11-01

    The CMS tracker at HL-LHC is required to provide prompt information on particles with high transverse momentum to the central Level 1 trigger. For this purpose, the innermost part of the outer tracker is based on a combination of a pixelated sensor with a short strip sensor, the so-called Pixel-Strip module (PS). The readout of these sensors is carried out by distinct ASICs, the Strip Sensor ASIC (SSA), for the strip layer, and the Macro Pixel ASIC (MPA) for the pixel layer. The processing of the data directly on the front-end module represents a design challenge due to the large data volume (30720 pixels and 1920 strips per module) and the limited power budget. This is the reason why several studies have been carried out to find the best compromise between ASICs performance and power consumption. This paper describes the current status of the MPA ASIC development where the logic for generating prompt information on particles with high transverse momentum is implemented. An overview of the readout method is presented with particular attention on the cluster reduction, position encoding and momentum discrimination logic. Concerning the architectural studies, a software test bench capable of reading physics Monte-Carlo generated events has been developed and used to validate the MPA design and to evaluate the MPA performance. The MPA-Light is scheduled to be submitted for fabrication this year and will include the full analog functions and a part of the digital logic of the final version in order to qualify the chosen VLSI technology for the analog front-end, the module assembly and the low voltage digital supply.

  5. Characterization of the ePix100 prototype: a front-end ASIC for second-generation LCLS integrating hybrid pixel detectors

    Science.gov (United States)

    Caragiulo, P.; Dragone, A.; Markovic, B.; Herbst, R.; Nishimura, K.; Reese, B.; Herrmann, S.; Hart, P.; Blaj, G.; Segal, J.; Tomada, A.; Hasi, J.; Carini, G.; Kenney, C.; Haller, G.

    2014-09-01

    ePix100 is the first variant of a novel class of integrating pixel ASICs architectures optimized for the processing of signals in second generation LINAC Coherent Light Source (LCLS) X-Ray cameras. ePix100 is optimized for ultra-low noise application requiring high spatial resolution. ePix ASICs are based on a common platform composed of a random access analog matrix of pixel with global shutter, fast parallel column readout, and dedicated sigma-delta analog to digital converters per column. The ePix100 variant has 50μmx50μm pixels arranged in a 352x384 matrix, a resolution of 50e- r.m.s. and a signal range of 35fC (100 photons at 8keV). In its final version it will be able to sustain a frame rate of 1kHz. A first prototype has been fabricated and characterized and the measurement results are reported here.

  6. A time-based front-end ASIC for the silicon micro strip sensors of the bar PANDA Micro Vertex Detector

    Science.gov (United States)

    Di Pietro, V.; Brinkmann, K.-Th.; Riccardi, A.; Ritman, J.; Rivetti, A.; Rolo, M. D.; Stockmanns, T.; Zambanini, A.

    2016-03-01

    The bar PANDA (Antiproton Annihilation at Darmstadt) experiment foresees many detectors for tracking, particle identification and calorimetry. Among them, the innermost is the MVD (Micro Vertex Detector) responsible for a precise tracking and the reconstruction of secondary vertices. This detector will be built from both hybrid pixel (two inner barrels and six forward disks) and double-sided micro strip (two outer barrels and outer rim of the last two disks) silicon sensors. A time-based approach has been chosen for the readout ASIC of the strip sensors. The PASTA (bar PANDA Strip ASIC) chip aims at high resolution time-stamping and charge information through the Time over Threshold (ToT) technique. It benefits from a Time to Digital Converter (TDC) allowing a time bin width down to 50 ps. The analog front-end was designed to serve both n-type and p-type strips and the performed simulations show remarkable performances in terms of linearity and electronic noise. The TDC consists of an analog interpolator, a digital local controller, and a digital global controller as the common back-end for all of the 64 channels.

  7. A time-based front-end ASIC for the silicon micro strip sensors of the P-bar ANDA Micro Vertex Detector

    International Nuclear Information System (INIS)

    The P-bar ANDA (Antiproton Annihilation at Darmstadt) experiment foresees many detectors for tracking, particle identification and calorimetry. Among them, the innermost is the MVD (Micro Vertex Detector) responsible for a precise tracking and the reconstruction of secondary vertices. This detector will be built from both hybrid pixel (two inner barrels and six forward disks) and double-sided micro strip (two outer barrels and outer rim of the last two disks) silicon sensors. A time-based approach has been chosen for the readout ASIC of the strip sensors. The PASTA ( P-bar ANDA Strip ASIC) chip aims at high resolution time-stamping and charge information through the Time over Threshold (ToT) technique. It benefits from a Time to Digital Converter (TDC) allowing a time bin width down to 50 ps. The analog front-end was designed to serve both n-type and p-type strips and the performed simulations show remarkable performances in terms of linearity and electronic noise. The TDC consists of an analog interpolator, a digital local controller, and a digital global controller as the common back-end for all of the 64 channels

  8. Compatibility Analysis of Space Qualified Intermediate Bus Converter and Point of Load Regulators for Digital Loads

    Science.gov (United States)

    Soderbeerg, Bjarne; Bussarakons, Tiva

    2008-09-01

    Distributed power architecture (DPA) has become the power system solutions of choice for digital loads such as FPGAs and other ASIC devices to optimize the system efficiency and dynamic response due to negative effect of parasitic impedances. IR's ZB with its world class efficiency performance and SBB design platforms are the key power conversion elements of such DPA power system solutions. This paper examines the compatibility of the ZB series, an intermediate bus converter (IBC) and the SBB series, a non-isolated synchronous buck point of load (POL) regulator to insure the stability of the power converters and the power system under various static and dynamic loading conditions.

  9. Atomic force microscopy imaging reveals the formation of ASIC/ENaC cross-clade ion channels

    Energy Technology Data Exchange (ETDEWEB)

    Jeggle, Pia; Smith, Ewan St. J.; Stewart, Andrew P. [Department of Pharmacology, University of Cambridge, Tennis Court Road, Cambridge CB2 1PD (United Kingdom); Haerteis, Silke; Korbmacher, Christoph [Institut für Zelluläre und Molekulare Physiologie, Friedrich-Alexander-Universität Erlangen-Nürnberg, Waldstrasse 6, 91054 Erlangen (Germany); Edwardson, J. Michael, E-mail: jme1000@cam.ac.uk [Department of Pharmacology, University of Cambridge, Tennis Court Road, Cambridge CB2 1PD (United Kingdom)

    2015-08-14

    ASIC and ENaC are co-expressed in various cell types, and there is evidence for a close association between them. Here, we used atomic force microscopy (AFM) to determine whether ASIC1a and ENaC subunits are able to form cross-clade hybrid ion channels. ASIC1a and ENaC could be co-isolated from detergent extracts of tsA 201 cells co-expressing the two subunits. Isolated proteins were incubated with antibodies against ENaC and Fab fragments against ASIC1a. AFM imaging revealed proteins that were decorated by both an antibody and a Fab fragment with an angle of ∼120° between them, indicating the formation of ASIC1a/ENaC heterotrimers. - Highlights: • There is evidence for a close association between ASIC and ENaC. • We used AFM to test whether ASIC1a and ENaC subunits form cross-clade ion channels. • Isolated proteins were incubated with subunit-specific antibodies and Fab fragments. • Some proteins were doubly decorated at ∼120° by an antibody and a Fab fragment. • Our results indicate the formation of ASIC1a/ENaC heterotrimers.

  10. A Trigger Data Serialize ASIC for the ATLAS Forward Muon Detector Upgrade

    CERN Document Server

    Wang, Jinhong; The ATLAS collaboration

    2016-01-01

    The small-strip Thin-Gap Chambers (sTGC) will be used as both trigger and precision tracking muon detectors for the Phase-I upgrade of the ATLAS New Small Wheel (NSW) muon detector. A Trigger data serializer (TDS) ASIC is required to prepare trigger data for both sTGC pad and strip detectors, perform pad-strip matching, and serializer trigger data to the circuits on the rim the rim of the NSW detector. The large number of input channels (128 differential input channels), short time available to prepare and transmit trigger data (<100 ns), high speed output data rate (4.8 Gbps), harsh radiation environment (about 300 kRad), and low power consumption (<1 W) all impose great challenges for the design of this ASIC using the IBM 130 nm CMOS process. We present our design and consderation of the TDS ASIC and the first prototype we built

  11. A Low-Power ASIC Signal Processor for a Vestibular Prosthesis.

    Science.gov (United States)

    Töreyin, Hakan; Bhatti, Pamela T

    2016-06-01

    A low-power ASIC signal processor for a vestibular prosthesis (VP) is reported. Fabricated with TI 0.35 μm CMOS technology and designed to interface with implanted inertial sensors, the digitally assisted analog signal processor operates extensively in the CMOS subthreshold region. During its operation the ASIC encodes head motion signals captured by the inertial sensors as electrical pulses ultimately targeted for in-vivo stimulation of vestibular nerve fibers. To achieve this, the ASIC implements a coordinate system transformation to correct for misalignment between natural sensors and implanted inertial sensors. It also mimics the frequency response characteristics and frequency encoding mappings of angular and linear head motions observed at the peripheral sense organs, semicircular canals and otolith. Overall the design occupies an area of 6.22 mm (2) and consumes 1.24 mW when supplied with ± 1.6 V. PMID:26800546

  12. A Low-Power ASIC Signal Processor for a Vestibular Prosthesis.

    Science.gov (United States)

    Töreyin, Hakan; Bhatti, Pamela T

    2016-06-01

    A low-power ASIC signal processor for a vestibular prosthesis (VP) is reported. Fabricated with TI 0.35 μm CMOS technology and designed to interface with implanted inertial sensors, the digitally assisted analog signal processor operates extensively in the CMOS subthreshold region. During its operation the ASIC encodes head motion signals captured by the inertial sensors as electrical pulses ultimately targeted for in-vivo stimulation of vestibular nerve fibers. To achieve this, the ASIC implements a coordinate system transformation to correct for misalignment between natural sensors and implanted inertial sensors. It also mimics the frequency response characteristics and frequency encoding mappings of angular and linear head motions observed at the peripheral sense organs, semicircular canals and otolith. Overall the design occupies an area of 6.22 mm (2) and consumes 1.24 mW when supplied with ± 1.6 V.

  13. Application specific integrated circuit (ASIC) readout technologies for future ion beam analytical instruments

    Energy Technology Data Exchange (ETDEWEB)

    Whitlow, Harry J. E-mail: harry_j.whitlow@nuclear.lu.se

    2000-03-01

    New possibilities for ion beam analysis (IBA) are afforded by recent developments in detector technology which facilitate the parallel collection of data from a large number of channels. Application specific integrated circuit (ASIC) technologies, which have been widely employed for multi-channel readout systems in nuclear and particle physics, are more net-cost effective (160/channel for 1000 channels) and a more rational solution for readout of a large number of channels than afforded by conventional electronics. Based on results from existing and on-going chip designs, the possibilities and issues of ASIC readout technology are considered from the IBA viewpoint. Consideration is given to readout chip architecture and how the stringent resolution, linearity and stability requirements for IBA may be met. In addition the implications of the restrictions imposed by ASIC technology are discussed.

  14. Test beam analysis of ultra-thin hybrid pixel detector assemblies with Timepix readout ASICs

    CERN Document Server

    Alipour Tehrani, Niloufar; Dannheim, Dominik; Firu, Elena; Kulis, Szymon; Redford, Sophie; Sicking, Eva

    2016-01-01

    The requirements for the vertex detector at the proposed Compact Linear Collider imply a very small material budget: less than 0.2% of a radiation length per detection layer including services and mechanical supports. We present here a study using Timepix readout ASICs hybridised to pixel sensors of 50 − 500 μm thickness, including assemblies with 100 μm thick sensors bonded to thinned 100μm thick ASICs. Sensors from three producers (Advacam, Micron Semiconductor Ltd, Canberra) with different edge termination technologies (active edge, slim edge) were bonded to Timepix ASICs. These devices were characterised with the EUDET telescope at the DESY II test beam using 5.6 GeV electrons. Their performance for the detection and tracking of minimum ionising particles was evaluated in terms of charge sharing, detection efficiency, single-point resolution and energy deposition.

  15. Channel control ASIC for the CMS hadron calorimeter front end readout module

    International Nuclear Information System (INIS)

    The Channel Control ASIC (CCA) is used along with a custom Charge Integrator and Encoder (QIE) ASIC to digitize signals from the hybrid photo diodes (HPDs) and photomultiplier tubes (PMTs) in the CMS hadron calorimeter. The CCA sits between the QIE and the data acquisition system. All digital signals to and from the QIE pass through the CCA chip. One CCA chip interfaces with two QIE channels. The CCA provides individually delayed clocks to each of the QIE chips in addition to various control signals. The QIE sends digitized PMT or HPD signals and time slice information to the CCA, which sends the data to the data acquisition system through an optical link

  16. FRONT-END ASIC FOR HIGH RESOLUTION X-RAY SPECTROMETERS

    International Nuclear Information System (INIS)

    We present an application specific integrated circuit (ASIC) for high-resolution x-ray spectrometers. The ASIC is designed to read out signals from a pixelated silicon drift detector (SDD). Each hexagonal pixel has an area of 15 mmz and an anode capacitance of less than 100 fF. There is no integrated Field Effect transistor (FET) in the pixel, rather, the readout is done by wirebonding the anodes to the inputs of the ASIC. The ASIC provides 14 channels of low-noise charge amplification, high-order shaping with baseline stabilization, and peak detection with analog memory. The readout is sparse and based on low voltage differential signaling. An interposer provides all the interconnections required to bias and operate the system. The channel dissipates 1.6 mW. The complete 14-pixel unit covers an area of 210 mm2, dissipates 12 mW cm-2, and can be tiled to cover an arbitrarily large detection area. We measured a preliminary resolution of 172 eV at -35 C on the 6 keV peak of a 55Fe source

  17. FRONT-END ASIC FOR HIGH RESOLUTION X-RAY SPECTROMETERS.

    Energy Technology Data Exchange (ETDEWEB)

    DE GERONIMO,G.; CHEN, W.; FRIED, J.; LI, Z.; PINELLI, D.A.; REHAK, P.; VERNON, E.; GASKIN, J.A.; RAMSEY, B.D.; ANELLI, G.

    2007-10-27

    We present an application specific integrated circuit (ASIC) for high-resolution x-ray spectrometers. The ASIC is designed to read out signals from a pixelated silicon drift detector (SDD). Each hexagonal pixel has an area of 15 mmz and an anode capacitance of less than 100 fF. There is no integrated Field Effect transistor (FET) in the pixel, rather, the readout is done by wirebonding the anodes to the inputs of the ASIC. The ASIC provides 14 channels of low-noise charge amplification, high-order shaping with baseline stabilization, and peak detection with analog memory. The readout is sparse and based on low voltage differential signaling. An interposer provides all the interconnections required to bias and operate the system. The channel dissipates 1.6 mW. The complete 14-pixel unit covers an area of 210 mm{sup 2}, dissipates 12 mW cm{sup -2}, and can be tiled to cover an arbitrarily large detection area. We measured a preliminary resolution of 172 eV at -35 C on the 6 keV peak of a {sup 55}Fe source.

  18. The GBT-SCA, a radiation tolerant ASIC for detector control applications in SLHC experiments

    CERN Document Server

    Gabrielli, A; Kloukinas, K; Marchioro, A; Moreira, P; Ranieri, A; De Robertis, D

    2009-01-01

    This work describes the architecture of the GigaBit Transceiver – Slow Control Adapter (GBT–SCA) ASIC suitable for the control and monitoring applications of the embedded front-end electronics in the future SLHC experiments. The GBT–SCA is part the GBT chipset currently under development for the SLHC detector upgrades. It is designed for radiation tolerance and it will be fabricated in a commercial 130 nm CMOS technology. The paper discusses the GBT-SCA architecture, the data transfer protocol, the ASIC interfaces, and its integration with the GBT optical link. The GBT–SCA is one the components of the GBT system chipset. It is proposed for the future SLHC experiments and is designed to be configurable matching different front-end system requirements. The GBT-SCA is intended for the slow control and monitoring of the embedded front end electronics and implements a point-to-multi point connection between one GBT optical link ASIC and several front end ASICs. The GBT-SCA connects to a dedicated electrica...

  19. A Prototype PZT Matrix Transducer With Low-Power Integrated Receive ASIC for 3-D Transesophageal Echocardiography.

    Science.gov (United States)

    Chen, Chao; Raghunathan, Shreyas B; Yu, Zili; Shabanimotlagh, Maysam; Chen, Zhao; Chang, Zu-yao; Blaak, Sandra; Prins, Christian; Ponte, Jacco; Noothout, Emile; Vos, Hendrik J; Bosch, Johan G; Verweij, Martin D; de Jong, Nico; Pertijs, Michiel A P

    2016-01-01

    This paper presents the design, fabrication, and experimental evaluation of a prototype lead zirconium titanate (PZT) matrix transducer with an integrated receive ASIC, as a proof of concept for a miniature three-dimensional (3-D) transesophageal echocardiography (TEE) probe. It consists of an array of 9 ×12 piezoelectric elements mounted on the ASIC via an integration scheme that involves direct electrical connections between a bond-pad array on the ASIC and the transducer elements. The ASIC addresses the critical challenge of reducing cable count, and includes front-end amplifiers with adjustable gains and micro-beamformer circuits that locally process and combine echo signals received by the elements of each 3 ×3 subarray. Thus, an order-of-magnitude reduction in the number of receive channels is achieved. Dedicated circuit techniques are employed to meet the strict space and power constraints of TEE probes. The ASIC has been fabricated in a standard 0.18-μm CMOS process and consumes only 0.44 mW/channel. The prototype has been acoustically characterized in a water tank. The ASIC allows the array to be presteered across ±37° while achieving an overall dynamic range of 77 dB. Both the measured characteristics of the individual transducer elements and the performance of the ASIC are in good agreement with expectations, demonstrating the effectiveness of the proposed techniques.

  20. Low-power digital ASIC for on-chip spectral analysis of low-frequency physiological signals

    Institute of Scientific and Technical Information of China (English)

    Nie Zedong; Zhang Fengjuan; Li Jie; Wang Lei

    2012-01-01

    A digital ASIC chip customized for battery-operated body sensing devices is presented.The ASIC incorporates a novel hybrid-architecture fast Fourier transform (FFT) unit that is capable of scalable spectral analysis,a licensed ARM7TDMI IP hardcore and several peripheral IP blocks.Extensive experimental results suggest that the complete chip works as intended.The power consumption of the FFT unit is 0.69 mW @ 1 MHz with 1.8 V power supply.The low-power and programmable features of the ASIC make it suitable for ‘on-the-fly' low-frequency physiological signal processing.

  1. ASIC1-mediated calcium entry stimulates NFATc3 nuclear translocation via PICK1 coupling in pulmonary arterial smooth muscle cells.

    Science.gov (United States)

    Gonzalez Bosc, Laura V; Plomaritas, Danielle R; Herbert, Lindsay M; Giermakowska, Wieslawa; Browning, Carly; Jernigan, Nikki L

    2016-07-01

    The development of chronic hypoxia (CH)-induced pulmonary hypertension is associated with increased pulmonary arterial smooth muscle cell (PASMC) Ca(2+) influx through acid-sensing ion channel-1 (ASIC1) and activation of the Ca(2+)/calcineurin-dependent transcription factor known as nuclear factor of activated T-cells isoform c3 (NFATc3). Whether Ca(2+) influx through ASIC1 contributes to NFATc3 activation in the pulmonary vasculature is unknown. Furthermore, both ASIC1 and calcineurin have been shown to interact with the scaffolding protein known as protein interacting with C kinase-1 (PICK1). In the present study, we tested the hypothesis that ASIC1 contributes to NFATc3 nuclear translocation in PASMC in a PICK1-dependent manner. Using both ASIC1 knockout (ASIC1(-/-)) mice and pharmacological inhibition of ASIC1, we demonstrate that ASIC1 contributes to CH-induced (1 wk at 380 mmHg) and endothelin-1 (ET-1)-induced (10(-7) M) Ca(2+) responses and NFATc3 nuclear import in PASMC. The interaction between ASIC1/PICK1/calcineurin was shown using a Duolink in situ Proximity Ligation Assay. Inhibition of PICK1 by using FSC231 abolished ET-1-induced and ionomycin-induced NFATc3 nuclear import, but it did not alter ET-1-mediated Ca(2+) responses, suggesting that PICK1 acts downstream of Ca(2+) influx. The key findings of the present work are that 1) Ca(2+) influx through ASIC1 mediates CH- and ET-1-induced NFATc3 nuclear import and 2) the scaffolding protein PICK1 is necessary for NFATc3 nuclear import. Together, these data provide an essential link between CH-induced ASIC1-mediated Ca(2+) influx and activation of the NFATc3 transcription factor. Identification of this ASIC1/PICK1/NFATc3 signaling complex increases our understanding of the mechanisms contributing to the vascular remodeling and increased vascular contractility that are associated with CH-induced pulmonary hypertension. PMID:27190058

  2. Wavelength converter technology

    DEFF Research Database (Denmark)

    Kloch, Allan; Hansen, Peter Bukhave; Poulsen, Henrik Nørskov;

    1999-01-01

    Wavelength conversion is important since it ensures full flexibility of the WDM network layer. Progress in optical wavelength converter technology is reviewed with emphasis on air-optical wavelength converter types based on semiconductor optical amplifiers....

  3. Wavelength converter technology

    DEFF Research Database (Denmark)

    Kloch, Allan; Hansen, Peter Bukhave; Poulsen, Henrik Nørskov;

    1999-01-01

    Wavelength conversion is important since it ensures full flexibility of the WDM network layer. Progress in optical wavelength converter technology is reviewed with emphasis on all-optical wavelength converter types based on semiconductor optical amplifiers.......Wavelength conversion is important since it ensures full flexibility of the WDM network layer. Progress in optical wavelength converter technology is reviewed with emphasis on all-optical wavelength converter types based on semiconductor optical amplifiers....

  4. Radiation-hard ASICs for optical data transmission in the ATLAS pixel detector

    CERN Document Server

    Kass, R; Gan, K K; Johnson, M; Kagan, H; Rush, C J; Rahimi, A; Smith, S; Ter-Antonian, R; Zoeller, M M; Ciliox, A; Holder, M; Nderitu, S; Ziolkowski, M

    2003-01-01

    We have developed two radiation-hard ASICs for optical data transmission in the ATLAS pixel detector at the LHC at CERN: a driver chip for a Vertical Cavity Surface Emitting Laser (VCSEL) diode for 80 Mbit/s data transmission from the detector, and a Bi-Phase Mark decoder chip to recover the control data and 40 MHz clock received optically by a PIN diode. We have successfully implemented both ASICs in 0.25 um CMOS technology using enclosed layout transistors and guard rings for increased radiation hardness. We present results from prototype circuits and from irradiation studies with 24 GeV protons up to 57 Mrad (1.9 x 10e15 p/cm2).

  5. Radiation-hard ASICs for optical data transmission in the ATLAS pixel detector

    CERN Document Server

    Gan, K K; Johnson, M; Kagan, H; Kass, R; Rush, C; Smith, S; Ter-Antonian, R; Zoeller, M M; Ciliox, A; Holder, M; Ziolkowski, M

    2005-01-01

    We have developed two radiation-hard ASICs for optical data transmission in the ATLAS pixel detector at the LHC at CERN: a driver chip for a Vertical Cavity Surface Emitting Laser (VCSEL) diode for 80 Mbit/s data transmission from the detector, and a Bi-Phase Mark decoder chip to recover the control data and 40 MHz clock received optically by a PIN diode. We have successfully implemented both ASICs in 0.25 mm CMOS technology using enclosed layout transistors and guard rings for increased radiation hardness. We present results from circuits of final design and from irradiation studies with 24 GeV protons up to 62 Mrad (2.3 x 10^15 p/cm^2).

  6. Radiation-Hard ASICs for Optical Data Transmission in the ATLAS Pixel Detector

    CERN Document Server

    Gan, K K; Johnson, M; Kagan, H; Kass, R; Rush, C; Smith, S; Ter-Antonian, R; Zöller, M; Ciliox, A; Holderb, M; Ziolkowski, M

    2006-01-01

    We have developed two radiation-hard ASICs for optical data transmission in the ATLAS pixel detector at the LHC at CERN: a driver chip for a Vertical Cavity Surface Emitting Laser (VCSEL) diode for 80 Mbit/s data transmission from the detector, and a Bi-Phase Mark decoder chip to recover the control data and 40 MHz clock received optically by a PIN diode. We have successfully implemented both ASICs in 0.25 mm CMOS technology using enclosed layout transistors and guard rings for increased radiation hardness. We present results from circuits of final design and from irradiation studies with 24 GeV protons up to 80 Mrad (2.6 x 10^15 p/cm^2).

  7. Trigger Data Serializer ASIC chip for the ATLAS New Small Wheel sTGC Detector

    Science.gov (United States)

    Meng, Xiangting; Wang, Jinhong; Guan, Liang; Sang, Ziru; Chapman, John; Zhou, Bing; Zhu, Junjie

    2015-04-01

    The small-strip thin-gap chambers (sTGC) will be used as the trigger device for the Phase-I upgrade of the ATLAS new small wheel (nSW) muon detector. An Application-Specific Integrated Circuit (ASIC) chip is needed to collect digital signals from both pad and strip detectors and serialize the outputs to the circuitry located on the rim of the nSW. The large number of input channels (128 differential input channels), short time available to prepare and transmit trigger data (power consumption (<1 W) impose great challenges for the design of this ASIC chip using the IBM 130 nm CMOS process. We will present our design and test results based on the prototype chip we build.

  8. Channel Control ASIC for the CMS hadron calorimeter front end readout module

    CERN Document Server

    Yarema, R J; Boubekeur, A; Elias, J E; Shaw, T

    2002-01-01

    The Channel Control ASIC (CCA) is used along with a custom Charge Integrator and Encoder (QIE) ASIC to digitize signals from the hybrid photo diodes (HPDs) and photomultiplier tubes (PMTs) in the CMS hadron calorimeter. The CCA sits between the QIE and the data acquisition system. All digital signals to and from the QIE pass through the CCA chip. One CCA chip interfaces with two QIE channels. The CCA provides individually delayed clocks to each of the QIE chips in addition to various control signals. The QIE sends digitized PMT or HPD signals and time slice information to the CCA, which sends the data to the data acquisition system through an optical link. (2 refs) .

  9. Comparative Analysis of ALU Implementation with RCA and Sklansky Adders In ASIC Design Flow

    Directory of Open Access Journals (Sweden)

    Abdul Rehman Buzdar

    2016-07-01

    Full Text Available An Arithmetic Logic Unit (ALU is the heart of every central processing unit (CPU which performs basic operations like addition, subtraction, multiplication, division and bitwise logic operations on binary numbers. This paper deals with implementation of a basic ALU unit using two different types of adder circuits, a ripple carry adder and a sklansky type adder. The ALU is designed using application specific integrated circuit (ASIC platform where VHDL hardware description language and standard cells are used. The target process technology is 130nm CMOS from the foundry ST Microelectronics. The Cadence EDA tools are used for the ASIC implementation. A comparative analysis is provided for the two ALU circuits designed in terms of area, power and timing requirements.

  10. Irradiation of the CLARO-CMOS chip, a fast ASIC for single-photon counting

    Energy Technology Data Exchange (ETDEWEB)

    Andreotti, M.; Baldini, W.; Calabrese, R. [Università degli Studi di Ferrara and INFN Sezione di Ferrara (Italy); Carniti, P.; Cassina, L. [Università degli Studi di Milano Bicocca and INFN Sezione di Milano Bicocca (Italy); Cotta Ramusino, A. [Università degli Studi di Ferrara and INFN Sezione di Ferrara (Italy); Fiorini, M., E-mail: fiorini@fe.infn.it [Università degli Studi di Ferrara and INFN Sezione di Ferrara (Italy); Giachero, A.; Gotti, C. [Università degli Studi di Milano Bicocca and INFN Sezione di Milano Bicocca (Italy); Luppi, E. [Università degli Studi di Ferrara and INFN Sezione di Ferrara (Italy); Maino, M. [Università degli Studi di Milano Bicocca and INFN Sezione di Milano Bicocca (Italy); Malaguti, R. [Università degli Studi di Ferrara and INFN Sezione di Ferrara (Italy); Pessina, G. [Università degli Studi di Milano Bicocca and INFN Sezione di Milano Bicocca (Italy); Tomassetti, L. [Università degli Studi di Ferrara and INFN Sezione di Ferrara (Italy)

    2015-07-01

    The CLARO-CMOS is a prototype ASIC that allows fast photon counting with low power consumption, built in AMS 0.35 μm CMOS technology. It is intended to be used as a front-end readout for the upgraded LHCb RICH detectors. In this environment, assuming 10 years of operation at the nominal luminosity expected after the upgrade, the ASIC must withstand a total fluence of about 6×10{sup 12} 1 MeV n{sub eq}/cm{sup 2} and a total ionising dose of 400 krad. Long term stability of the electronics front-end is essential and the effects of radiation damage on the CLARO-CMOS performance must be carefully studied. This paper describes results of multi-step irradiation tests with protons up to the dose of ~8 Mrad, including measurement of single event effects during irradiation and chip performance evaluation before and after each irradiation step.

  11. ASICs in nanometer and 3D technologies for readout of hybrid pixel detectors

    Science.gov (United States)

    Maj, Piotr; Grybos, Pawel; Kmon, Piotr; Szczygiel, Robert

    2013-07-01

    Hybrid pixel detectors working in a single photon counting mode are very attractive solutions for material science and medical X-ray imaging applications. Readout electronics of these detectors has to match the geometry of pixel detectors with an area of readout channel of 100 μm × 100 μm (or even less) and very small power consumption (a few tens of μW). New solutions of readout ASICs are going into directions of better spatial resolutions, higher data throughput and more advanced functionality. We report on the design and measurement results of two pixel prototype ASICs in nanometer technology and 3D technology which offer fast signal processing, low noise performance and advanced functionality per single readout pixel cell.

  12. Irradiation of the CLARO-CMOS chip, a fast ASIC for single-photon counting

    Science.gov (United States)

    Andreotti, M.; Baldini, W.; Calabrese, R.; Carniti, P.; Cassina, L.; Cotta Ramusino, A.; Fiorini, M.; Giachero, A.; Gotti, C.; Luppi, E.; Maino, M.; Malaguti, R.; Pessina, G.; Tomassetti, L.

    2015-07-01

    The CLARO-CMOS is a prototype ASIC that allows fast photon counting with low power consumption, built in AMS 0.35 μm CMOS technology. It is intended to be used as a front-end readout for the upgraded LHCb RICH detectors. In this environment, assuming 10 years of operation at the nominal luminosity expected after the upgrade, the ASIC must withstand a total fluence of about 6×1012 1 MeV neq/cm2 and a total ionising dose of 400 krad. Long term stability of the electronics front-end is essential and the effects of radiation damage on the CLARO-CMOS performance must be carefully studied. This paper describes results of multi-step irradiation tests with protons up to the dose of ~8 Mrad, including measurement of single event effects during irradiation and chip performance evaluation before and after each irradiation step.

  13. Coupled FPGA/ASIC Implementation of Elliptic Curve Crypto-Processor

    OpenAIRE

    Mohsen Machhout; Zied Guitouni; Kholdoun Torki; Lazhar Khriji; Rached Tourki

    2010-01-01

    In this paper, we propose an elliptic curve key generation processor over GF(2163) scheme based on the Montgomery scalar multiplication algorithm. The new architecture is performed using polynomial basis.The Finite Field operations use a cellular automata multiplier and Fermat algorithm for inversion. For real time implementation, the architecture has been tested on an ISE 9.1 Software using Xilinx Virtex II Pro FPGA and on an ASIC CMOS 45 nm technology as well. The proposed implementation pr...

  14. A New Design Reuse Approach for Voip Implementation into Fpsocs and ASICS

    Directory of Open Access Journals (Sweden)

    Fatiha Louiz

    2013-11-01

    Full Text Available The aim of this paper is to present a newdesignreuse approachforautomatic generation ofVoice overInternet protocol (VOIPhardware description andimplementation intoFPSOCs and ASICs.Ourmotivation behind this work is justified by the following arguments:first,VOIP based System on chip(SOC implementation is an emergingresearch and development area, whereinnovativeapplications canbe implemented. Second,these systems are very complex and due to time to market pressure, there is a needto built platforms that help the designer to explore with different architectural possibilities and choose thecircuit that best correspond to the specifications. Third,we aim to develop in hardware,design,methodsand tools that are used in softwarelike the MATLAB tool for VOIP implementation.To achieve our goal,the proposed design approach is basedon a modular design of the VOIP architecture. The originality ofour approach is the application of the design for reuse (DFR and the design with reuse (DWR concepts.To validate the approach, a case study of a SOC based on the OR1K processor is studied.Wedemonstratethat theproposedSoCarchitecture isreconfigurable, scalable and the final RTL code can be reused forany FPSOCor ASIC technology.As an example,Performances measures, in the VIRTEX-5 FPGA devicefamily,and ASIC 65nm technology are shown through this paper

  15. A new front-end ASIC for GEM detectors with time and charge measurement capabilities

    Science.gov (United States)

    Ciciriello, F.; Corsi, F.; De Robertis, G.; Felici, G.; Loddo, F.; Marzocca, C.; Matarrese, G.; Ranieri, A.

    2016-07-01

    A 32 channel CMOS front-end ASIC has been designed to read out the GEM detectors intended to be used for beam monitoring in a new proton-therapy facility currently under construction. In order to improve the spatial resolution by exploiting charge centroid algorithms, the analog channels, based on the classic CSA+shaper architecture, are equipped with a peak detector (PD) which works as an analog memory during the read-out phase. The outputs of the PDs are multiplexed towards an integrated 8-bit subranging ADC. An accurate trigger signal marks the arrival of a valid event and is generated by fast-ORing the outputs of 32 voltage discriminators which compare the shaper outputs with a programmable threshold. The digital part of the ASIC manages the read-out of the channels, the A/D conversion and the configuration of the ASIC. A 100 Mbit/s LVDS serial link is used for data communication. The sensitivity of the analog channel is 15 mV/fC and the dynamic range is 80 fC. The simulated ENC is about 650 e- for a detector capacitance of 10 pF. © 2001 Elsevier Science. All rights reserved

  16. Radiation Hardened Structured ASIC Platform for Rapid Chip Development for Very High Speed System on a Chip (SoC) and Complex Digital Logic Systems Project

    Data.gov (United States)

    National Aeronautics and Space Administration — Radiation Hardened Application Specific Integrated Circuits (ASICs) provide for the highest performance, lowest power and size for Space Missions. In order to...

  17. σ-1 Receptor Inhibition of ASIC1a Channels is Dependent on a Pertussis Toxin-Sensitive G-Protein and an AKAP150/Calcineurin Complex.

    Science.gov (United States)

    Mari, Yelenis; Katnik, Christopher; Cuevas, Javier

    2015-10-01

    ASIC1a channels play a major role in various pathophysiological conditions including depression, anxiety, epilepsy, and neurodegeneration following ischemic stroke. Sigma-1 (σ-1) receptor stimulation depresses the activity of ASIC1a channels in cortical neurons, but the mechanism(s) by which σ-1 receptors exert their influence on ASIC1a remains unknown. Experiments were undertaken to elucidate the signaling cascade linking σ-1 receptors to ASIC1a channels. Immunohistochemical studies showed that σ-1 receptors, ASIC1a and A-kinase anchoring peptide 150 colocalize in the plasma membrane of the cell body and processes of cortical neurons. Fluorometric Ca(2+) imaging experiments showed that disruption of the macromolecular complexes containing AKAP150 diminished the effects of the σ-1 on ASIC1a, as did application of the calcineurin inhibitors, cyclosporin A and FK-506. Moreover, whole-cell patch clamp experiments showed that σ-1 receptors were less effective at decreasing ASIC1a-mediated currents in the presence of the VIVIT peptide, which binds to calcineurin and prevents cellular effects dependent on AKAP150/calcineurin interaction. The coupling of σ-1 to ASIC1a was also disrupted by preincubation of the neurons in the G-protein inhibitor, pertussis toxin (PTX). Taken together, our data reveal that σ-1 receptor block of ASIC1a function is dependent on activation of a PTX-sensitive G-protein and stimulation of AKAP150 bound calcineurin. PMID:24925261

  18. Hierarchical Test Development and Design-For for (a)synchronous Semi-Custom Asics.

    Science.gov (United States)

    Leenstra, Jentje

    The research, described in this thesis, deals in particular with several problems, which arise when trying to automate the process of testing low-volume semi-custom ASICs. For low-volume ASICs one of the major problems is the reduction of the test application costs. To reduce the costs of testing low-volume ASICs, the use of a semi -custom test method with associated design-for-testability techniques is proposed. To be able to start the detection and removal of testability problems during the design, a novel automated hierarchical test program development procedure is presented. It is shown how, by generating a test specification for each hierarchical module, the test program can be developed incrementally. As a result, the testability of each module becomes known and it circumvents the need to generate a complete new test program after changes. To reduce the ASIC test time, the hierarchical test development approach supports the synthesis of a reconfigurable scan path. Thereby, our novel scan path architecture circumvents the need to introduce explicit test controllers by simply loading the reconfiguration information through the scan path itself. Since the hierarchical ASIC test development method as well as the semi-custom test method requires that all test vectors can be applied through a synchronous (reconfigurable) scan path, it is also investigate how asynchronous control circuits can be designed in such a way that they are synchronously scan testable. An implementation model is presented, that uses an explicit stale register composed of SR flip-flops. It is shown that these controllers are synchronously testable and can be derived directly from a state diagram description. Finally, the possibility of using a dedicated test generation procedure is illustrated by showing how the test program for modules composed of a data path and a finite state machine controller can be derived by the use of a novel symbolic test assembly procedure. The automated

  19. Digital to Analog Converter

    NARCIS (Netherlands)

    Westra, Jan R.; Annema, Anne J.; Boom, van den Jeroen M.; Dijkmans, Eise C.

    2002-01-01

    A digital to analog converter (DAC) for converting a digital signal (DS) having a maximum voltage range which corresponds to a first supply voltage (UL) into an analog signal (UOUT) having a maximum voltage range which corresponds to a second supply voltage (UH). The first supply voltage (UL) is off

  20. Digital to Analog Converter

    NARCIS (Netherlands)

    Westra, Jan R.; Annema, Anne J.; Boom, van den Jeroen M.; Dijkmans, Eise C.

    2006-01-01

    A digital to analog converter (DAC) for converting a digital signal (DS) having a maximum voltage range which corresponds to a first supply voltage (UL) into an analog signal (UOUT) having a maximum voltage range which corresponds to a second supply voltage (UH). The first supply voltage (UL) is off

  1. Low noise DC to DC converters for the sLHC experiments

    Energy Technology Data Exchange (ETDEWEB)

    Allongue, B; Blanchot, G; Faccio, F; Fuentes, C; Michelis, S; Orlandi, S, E-mail: georges.blanchot@cern.c [CERN, Route de Meyrin, CH-1211 Geneva 23 (Switzerland)

    2010-11-15

    The development of front-end systems for the ATLAS tracker at the sLHC is now in progress and the availability of radiation tolerant buck converter ASICs enables the implementation of DC to DC converter based powering schemes. The front-end systems powered in this manner will be exposed to the radiated and conducted noise emitted by the converters. The electromagnetic compatibility between DC to DC converters and ATLAS short strip tracker hybrid prototypes has been studied with specific susceptibility tests. Different DC to DC converter prototypes have been designed following a noise optimization methodology to match the noise requirements of these front-end systems. The DC to DC converter developed in this manner presents a negligible emission of noise that was confirmed by system tests on an ATLAS tracker front-end module prototype. As a result of this, power converters can now be integrated in close vicinity of front-end chips without compromising their overall noise performance.

  2. Cascaded resonant bridge converters

    Science.gov (United States)

    Stuart, Thomas A. (Inventor)

    1989-01-01

    A converter for converting a low voltage direct current power source to a higher voltage, high frequency alternating current output for use in an electrical system where it is desired to use low weight cables and other circuit elements. The converter has a first stage series resonant (Schwarz) converter which converts the direct current power source to an alternating current by means of switching elements that are operated by a variable frequency voltage regulator, a transformer to step up the voltage of the alternating current, and a rectifier bridge to convert the alternating current to a direct current first stage output. The converter further has a second stage series resonant (Schwarz) converter which is connected in series to the first stage converter to receive its direct current output and convert it to a second stage high frequency alternating current output by means of switching elements that are operated by a fixed frequency oscillator. The voltage of the second stage output is controlled at a relatively constant value by controlling the first stage output voltage, which is accomplished by controlling the frequency of the first stage variable frequency voltage controller in response to second stage voltage. Fault tolerance in the event of a load short circuit is provided by making the operation of the first stage variable frequency voltage controller responsive to first and second stage current limiting devices. The second stage output is connected to a rectifier bridge whose output is connected to the input of the second stage to provide good regulation of output voltage wave form at low system loads.

  3. PACIFIC: the readout ASIC for the SciFi Tracker of the upgraded LHCb detector

    Science.gov (United States)

    Mazorra, J.; Chanal, H.; Comerma, A.; Gascón, D.; Gómez, S.; Han, X.; Pillet, N.; Vandaele, R.

    2016-02-01

    The LHCb detector will be upgraded during the Long Shutdown 2 (LS2) of the LHC in order to cope with higher instantaneous luminosities and will switch to a 40 MHz readout rate using a trigger-less software based system. All front-end electronics will be replaced and several sub-detectors must be redesigned to cope with the higher detector occupancy and radiation damage. The current tracking detectors downstream of the LHCb dipole magnet will be replaced by the Scintillating Fibre (SciFi) Tracker. The SciFi Tracker will use scintillating fibres read out by Silicon Photomultipliers (SiPMs). State-of-the-art multi-channel SiPM arrays are being developed and a custom ASIC, called the low-Power ASIC for the sCIntillating FIbres traCker (PACIFIC), will be used to digitise the signals from the SiPMs. This article presents an overview of the R&D for the PACIFIC. It is a 64-channel ASIC implemented in 130 nm CMOS technology, aiming at a radiation tolerant design with a power consumption below 10 mW per channel. It interfaces directly with the SiPM anode through a current mode input, and provides a configurable non-linear 2-bit per channel digital output. The SiPM signal is acquired by a current conveyor and processed with a fast shaper and a gated integrator. The digitization is performed using a three threshold non-linear flash ADC operating at 40 MHz. Simulation and test results show the PACIFIC chip prototypes functioning well.

  4. A custom front-end ASIC for the readout and timing of 64 SiPM photosensors

    Energy Technology Data Exchange (ETDEWEB)

    Bagliesi, M.G., E-mail: mg.bagliesi@pi.infn.it [Department of Physics, University of Siena and INFN, Via Roma 56, 53100 Siena (Italy); Avanzini, C. [INFN Sezione di Pisa, Edificio C-Polo Fibonacci Largo Bruno Pontecorvo 3, 56127 Pisa (Italy); Bigongiari, G.; Cecchi, R.; Kim, M.Y.; Maestro, P.; Marrocchesi, P.S. [Department of Physics, University of Siena and INFN, Via Roma 56, 53100 Siena (Italy); Morsani, F. [INFN Sezione di Pisa, Edificio C-Polo Fibonacci Largo Bruno Pontecorvo 3, 56127 Pisa (Italy)

    2011-06-15

    A new class of instruments - based on Silicon PhotoMultiplier (SiPM) photosensors - are currently under development for the next generation of Astroparticle Physics experiments in future space missions. A custom front-end ASIC (Application Specific Integrated Circuit) for the readout of 64 SiPM sensors was specified in collaboration with GM-IDEAS (Norway) that designed and manufactured the ASIC. Our group developed a custom readout board equipped with a 16 bit ADC for the digitization of both pulse height and time information. A time stamp, generated by the ASIC in correspondence of the threshold crossing time, is digitized and recorded for each channel. This allows to define a narrow time window around the physics event that reduces significantly the background due to the SiPM dark count rate. In this paper, we report on the preliminary test results obtained with the readout board prototype.

  5. CLARO-CMOS, an ASIC for single photon counting with Ma-PMTs, MCPs and SiPMs

    Science.gov (United States)

    Carniti, P.; Cibinetto, G.; Cotta Ramusino, A.; Giachero, A.; Gotti, C.; Maino, M.; Malaguti, R.; Pessina, G.

    2013-01-01

    An ASIC named CLARO-CMOS was designed for fast photon counting with MaPMTs, MCPs and SiPMs. The prototype was realized in a .35 μm CMOS technology and has four channels, each with a fast amplifier and a discriminator. The main features of the design are the high speed of operation and the low power dissipation, below 1 mW per channel. This paper focuses on the use of the CLARO for SiPM readout. The ASIC was tested with several SiPMs of various sizes, connected to the input of the chip both directly and through a coaxial cable about one meter long. In the latter case the ASIC is still fully functional although the speed of response is affected by the cable capacitance. The threshold could be set just above the single photoelectron level, and with 1 ×1 mm2 SiPMs the discrete photoelectron peaks could be well resolved.

  6. Development of an ASIC for CCD readout at the vertex detectors of the intrenational linear collider

    CERN Document Server

    Murray, P; Stefanov, K D; Woolliscroft, T

    2007-01-01

    The Linear Collider Flavour Identification Collaboration is developing sensors and readout electronics suitable for the International Linear Collider vertex detector. In order to achieve high data rates the proposed detector utilises column parallel CCDs, each read out by a custom designed ASIC. The prototype chip (CPR2) has 250 channels of electronics, each with a preamplifier, 5-bit flash ADC, data sparsification logic for identification of significant data clusters, and local memory for storage of data awaiting readout. CPR2 also has hierarchical 2-level data multiplexing and intermediate data memory, enabling readout of the sparsified data via the 5-bit data output bus.

  7. Coupled FPGA/ASIC Implementation of Elliptic Curve Crypto-Processor

    Directory of Open Access Journals (Sweden)

    Mohsen Machhout

    2010-04-01

    Full Text Available In this paper, we propose an elliptic curve key generation processor over GF(2163 scheme based on the Montgomery scalar multiplication algorithm. The new architecture is performed using polynomial basis.The Finite Field operations use a cellular automata multiplier and Fermat algorithm for inversion. For real time implementation, the architecture has been tested on an ISE 9.1 Software using Xilinx Virtex II Pro FPGA and on an ASIC CMOS 45 nm technology as well. The proposed implementation provides a time of 2.07 ms and 38 percent of Slices in Xilinx Virtex II Pro FPGA. Such features reveal the highefficiently of this implementation design

  8. Towards Automation of ASIC TSMC 0.18 um Standard Cell Library Development

    OpenAIRE

    Djigbenou, Jeannette Donan

    2008-01-01

    Cell-based design is a widely adopted design approach in current Application Specific Integrated Circuits (ASIC) and System-on-Chip (SOC) designs. A standard cell library is a collection of basic building blocks that can be used in cell-based design. The use of a standard cell library offers shorter design time, induces fewer errors in the design process, and is easier to maintain. Development of a cell library is laborious, prone to errors and even a small error on a library cell can poss...

  9. QIE12: A New High-Performance ASIC for the ATLAS TileCal Upgrade

    CERN Document Server

    Drake, Gary; The ATLAS collaboration; Proudfoot, James; Stanek, Robert; Chekanov, Sergei

    2015-01-01

    We present results on the QIE12, a custom ASIC, being developed for the ATLAS TileCal Phase 2 Upgrade. The design features 1.5 fC sensitivity, more than 17 bits of dynamic range with logarithmic response, and an on-chip TDC with one nanosecond resolution. It has a programmable shunt output for monitoring the integrated current. The device operates with no dead-time at 40 MHz, making it ideal for calorimetry at the LHC. We present bench measurements and integration studies that characterize the performance, radiation tolerance measurements, and the design for the ATLAS TileCal detector for the Phase 2 Upgrade.

  10. 保守的奢华 ASICS GEL-KAYANO 16

    Institute of Scientific and Technical Information of China (English)

    最后的神

    2010-01-01

    素有“跑王”之称的ASICS GEL—KAYANO系列,向来是跑鞋领域的标杆之一,也是ASICS新技术的集大成者。新一代的GEL—KAYANO 16,在沿袭上代已有技术的基础上进一步提升了整鞋的质感,带出了—种保守的奢华。

  11. Performance and Calibration of H2RG Detectors and SIDECAR ASICs for the RATIR Camera

    Science.gov (United States)

    Fox, Ori D.; Kutyrev, Alexander S.; Rapchun, David A.; Klein, Christopher R.; Butler, Nathaniel R.; Bloom, Josh; de Diego, Jos A.; Simn Farah, Alejandro D.; Gehrels, Neil A.; Georgiev, Leonid; Gonzlez-Hernandez, J. Jess; Lee, William H.; Loose, Markus; Lotkin, Gennadiy; Moseley, Samuel H.; Prochaska, J. Xavier; Ramirez-Ruiz, Enrico; Richer, Michael G.; Robinson, Frederick D.; Romn-Zuniga, Carols; Samuel, Mathew V.; Sparr, Leroy M.; Watson, Alan M.

    2012-01-01

    The Reionization And Transient Infra,.Red (RATIR) camera has been built for rapid Gamma,.Ray Burst (GRE) followup and will provide simultaneous optical and infrared photometric capabilities. The infrared portion of this camera incorporates two Teledyne HgCdTe HAWAII-2RG detectors, controlled by Teledyne's SIDECAR ASICs. While other ground-based systems have used the SIDECAR before, this system also utilizes Teledyne's JADE2 interface card and IDE development environment. Together, this setup comprises Teledyne's Development Kit, which is a bundled solution that can be efficiently integrated into future ground-based systems. In this presentation, we characterize the system's read noise, dark current, and conversion gain.

  12. Low-noise multichannel ASIC for high count rate X-ray diffractometry applications

    Energy Technology Data Exchange (ETDEWEB)

    Szczygiel, R. [AGH University of Science and Technology, Department of Measurement and Instrumentation, al. Mickiewicza 30, Krakow (Poland)], E-mail: robert.szczygiel@agh.edu.pl; Grybos, P.; Maj, P. [AGH University of Science and Technology, Department of Measurement and Instrumentation, al. Mickiewicza 30, Krakow (Poland); Tsukiyama, A.; Matsushita, K.; Taguchi, T. [Rigaku Corporation, 3-9-12 Matsubara-cho, Akishima-shi, Tokyo (Japan)

    2009-08-01

    RG64 is a 64-channel ASIC designed for the silicon strip detector readout and optimized for high count rate X-ray imaging applications. In this paper we report on the test results referring to the RG64 noise level, channel uniformity and the operation with a high rate of input signals. The parameters of the RG64-based diffractometry system are compared with the ones based on the scintillation counter. Diffractometry measurement results with silicon strip detectors of different strip lengths and strip pitch are also presented.

  13. FATALIC: A Dedicated Front-End ASIC for the ATLAS TileCal Upgrade

    CERN Document Server

    Royer, Laurent; The ATLAS collaboration

    2015-01-01

    A front-end ASIC (FATALIC) has been developed to fulfil the requirements of the Phase 2 upgrade of the ATLAS Tile Calorimeter. This electronics performs the complete processing of the signal delivered by each PM tube. The first stage is a current conveyor which splits the 17-bit dynamic range of the input signal into three ranges. Each channel is followed by a shaper and a dedicated pipeline 12-bit ADC operating at 40MHz. The chip is developed using a 130nm CMOS technology. Measurements show a linearity better than 0.5% for low energy particles, and an ENC limited to 10 fC.

  14. SSG Wave Energy Converter

    DEFF Research Database (Denmark)

    Margheritini, Lucia; Vicinanza, Diego; Frigaard, Peter

    2008-01-01

    The SSG (Sea Slot-cone Generator) is a wave energy converter of the overtopping type. The structure consists of a number of reservoirs one on the top of each others above the mean water level, in which the water of incoming waves is stored temporary. In each reservoir, expressively designed low...... head hydroturbines are converting the potential energy of the stored water into power. A key to success for the SSG will be the low cost of the structure and its robustness. The construction of the pilot plant is scheduled and this paper aims to describe the concept of the SSG wave energy converter...

  15. Converting Nonclassicality into Entanglement.

    Science.gov (United States)

    Killoran, N; Steinhoff, F E S; Plenio, M B

    2016-02-26

    Quantum mechanics exhibits a wide range of nonclassical features, of which entanglement in multipartite systems takes a central place. In several specific settings, it is well known that nonclassicality (e.g., squeezing, spin squeezing, coherence) can be converted into entanglement. In this work, we present a general framework, based on superposition, for structurally connecting and converting nonclassicality to entanglement. In addition to capturing the previously known results, this framework also allows us to uncover new entanglement convertibility theorems in two broad scenarios, one which is discrete and one which is continuous. In the discrete setting, the classical states can be any finite linearly independent set. For the continuous setting, the pertinent classical states are "symmetric coherent states," connected with symmetric representations of the group SU(K). These results generalize and link convertibility properties from the resource theory of coherence, spin coherent states, and optical coherent states, while also revealing important connections between local and nonlocal pictures of nonclassicality. PMID:26967398

  16. Converting Nonclassicality into Entanglement.

    Science.gov (United States)

    Killoran, N; Steinhoff, F E S; Plenio, M B

    2016-02-26

    Quantum mechanics exhibits a wide range of nonclassical features, of which entanglement in multipartite systems takes a central place. In several specific settings, it is well known that nonclassicality (e.g., squeezing, spin squeezing, coherence) can be converted into entanglement. In this work, we present a general framework, based on superposition, for structurally connecting and converting nonclassicality to entanglement. In addition to capturing the previously known results, this framework also allows us to uncover new entanglement convertibility theorems in two broad scenarios, one which is discrete and one which is continuous. In the discrete setting, the classical states can be any finite linearly independent set. For the continuous setting, the pertinent classical states are "symmetric coherent states," connected with symmetric representations of the group SU(K). These results generalize and link convertibility properties from the resource theory of coherence, spin coherent states, and optical coherent states, while also revealing important connections between local and nonlocal pictures of nonclassicality.

  17. The interaction between the first transmembrane domain and the thumb of ASIC1a is critical for its N-glycosylation and trafficking.

    Directory of Open Access Journals (Sweden)

    Lan Jing

    Full Text Available Acid-sensing ion channel-1a (ASIC1a, the primary proton receptor in the brain, contributes to multiple diseases including stroke, epilepsy and multiple sclerosis. Thus, a better understanding of its biogenesis will provide important insights into the regulation of ASIC1a in diseases. Interestingly, ASIC1a contains a large, yet well organized ectodomain, which suggests the hypothesis that correct formation of domain-domain interactions at the extracellular side is a key regulatory step for ASIC1a maturation and trafficking. We tested this hypothesis here by focusing on the interaction between the first transmembrane domain (TM1 and the thumb of ASIC1a, an interaction known to be critical in channel gating. We mutated Tyr71 and Trp287, two key residues involved in the TM1-thumb interaction in mouse ASIC1a, and found that both Y71G and W287G decreased synaptic targeting and surface expression of ASIC1a. These defects were likely due to altered folding; both mutants showed increased resistance to tryptic cleavage, suggesting a change in conformation. Moreover, both mutants lacked the maturation of N-linked glycans through mid to late Golgi. These data suggest that disrupting the interaction between TM1 and thumb alters ASIC1a folding, impedes its glycosylation and reduces its trafficking. Moreover, reducing the culture temperature, an approach commonly used to facilitate protein folding, increased ASIC1a glycosylation, surface expression, current density and slowed the rate of desensitization. These results suggest that correct folding of extracellular ectodomain plays a critical role in ASIC1a biogenesis and function.

  18. Thermionic photovoltaic energy converter

    Science.gov (United States)

    Chubb, D. L. (Inventor)

    1985-01-01

    A thermionic photovoltaic energy conversion device comprises a thermionic diode mounted within a hollow tubular photovoltaic converter. The thermionic diode maintains a cesium discharge for producing excited atoms that emit line radiation in the wavelength region of 850 nm to 890 nm. The photovoltaic converter is a silicon or gallium arsenide photovoltaic cell having bandgap energies in this same wavelength region for optimum cell efficiency.

  19. DC-DC converters in 0.35μm CMOS technology

    Science.gov (United States)

    Michelis, S.; Allongue, B.; Blanchot, G.; Faccio, F.; Fuentes, C.; Orlandi, S.; Saggini, S.; Cengarle, S.; Ongaro, F.

    2012-01-01

    In view of the upgrade of the LHC experiments, we are developing custom DC/DC converters for a more efficient power distribution scheme. A new prototype have been integrated in ASICs in the selected 0.35μm commercial high voltage technology that has been successfully tested for all radiation effects: TID, displacement damage and Single Event Burnout. This converter has been optimized for high efficiency and improved radiation tolerance. Amongst the new features the most relevant are the presence of internal linear regulators, protection circuits with a state-machine and a new pinout for a modified assembly in package in order to reduce conductive losses. This paper illustrates the design of the prototype followed by functional and radiation tests.

  20. Radiation-hard ASICs for optical data transmission in the ATLAS pixel detector

    CERN Document Server

    Ziolkowski, M; Buchholz, P; Ciliox, A; Gan, K K; Holder, M; Johnson, M; Kagan, H; Kass, R; Nderitu, S; Rahimi, A; Rush, C J; Smith, S; Ter-Antonian, R; Zoeller, M M

    2004-01-01

    We have developed two radiation-hard ASICs for optical data transmission in the ATLAS pixel detector at the CERN Large Hadron Collider (LHC). The first circuit is a driver chip for a Vertical Cavity Surface Emitting Laser (VCSEL) diode to be used for 80 Mbit/s data transmission from the detector. The second circuit is a Bi-Phase Mark, decoder chip to recover the control data and 40 MHz clock received optically by a PIN diode on the detector side. During ten years of operation at the LHC, the ATLAS optical link circuitry will be exposed to a maximum total fluence of 10/sup 15/ 1-MeV-equivalent neutrons per cm/sup 2/. We have successfully implemented both ASICs in a commercial 0.25 mu m CMOS technology using standard layout techniques to enhance the radiation tolerance. Both chips are four- channel devices compatible with common cathode PIN and VCSEL arrays. We present results from final prototype circuits and from irradiation studies of both circuits with 24 GeV protons up to a total dose of 57 Mrad. (3 refs).

  1. Development of arrays of Silicon Drift Detectors and readout ASIC for the SIDDHARTA experiment

    Science.gov (United States)

    Quaglia, R.; Schembari, F.; Bellotti, G.; Butt, A. D.; Fiorini, C.; Bombelli, L.; Giacomini, G.; Ficorella, F.; Piemonte, C.; Zorzi, N.

    2016-07-01

    This work deals with the development of new Silicon Drift Detectors (SDDs) and readout electronics for the upgrade of the SIDDHARTA experiment. The detector is based on a SDDs array organized in a 4×2 format with each SDD square shaped with 64 mm2 (8×8) active area. The total active area of the array is therefore 32×16 mm2 while the total area of the detector (including 1 mm border dead area) is 34 × 18mm2. The SIDDHARTA apparatus requires 48 of these modules that are designed and manufactured by Fondazione Bruno Kessler (FBK). The readout electronics is composed by CMOS preamplifiers (CUBEs) and by the new SFERA (SDDs Front-End Readout ASIC) circuit. SFERA is a 16-channels readout ASIC designed in a 0.35 μm CMOS technology, which features in each single readout channel a high order shaping amplifier (9th order Semi-Gaussian complex-conjugate poles) and a high efficiency pile-up rejection logic. The outputs of the channels are connected to an analog multiplexer for the external analog to digital conversion. An on-chip 12-bit SAR ADC is also included. Preliminary measurements of the detectors in the single SDD format are reported. Also measurements of low X-ray energies are reported in order to prove the possible extension to the soft X-ray range.

  2. Hydrogenated amorphous silicon sensors based on thin film on ASIC technology

    CERN Document Server

    Despeisse, M; Anelli, G; Jarron, P; Kaplon, J; Rusack, R; Saramad, S; Wyrsch, N

    2006-01-01

    The performance and limitations of a novel detector technology based on the deposition of a thin-film sensor on top of processed integrated circuits have been studied. Hydrogenated amorphous silicon (a-Si:H) films have been deposited on top of CMOS circuits developed for these studies and the resulting "thin-film on ASIC" (TFA) detectors are presented. The leakage current of the a-Si:H sensor at high reverse biases turns out to be an important parameter limiting the performance of a TFA detector. Its detailed study and the pixel segmentation of the detector are presented. High internal electric fields (in the order of 10/sup 4/-10/sup 5/ V/cm) can be built in the a-Si:H sensor and overcome the low mobility of electrons and holes in a-Si:H. Signal induction by generated carrier motion and speed in the a-Si:H sensor have been studied with a 660 nm pulsed laser on a TFA detector based on an ASIC integrating 5 ns peaking time pre- amplifiers. The measurement set-up also permits to study the depletion of the senso...

  3. A low power biomedical signal processor ASIC based on hardware software codesign.

    Science.gov (United States)

    Nie, Z D; Wang, L; Chen, W G; Zhang, T; Zhang, Y T

    2009-01-01

    A low power biomedical digital signal processor ASIC based on hardware and software codesign methodology was presented in this paper. The codesign methodology was used to achieve higher system performance and design flexibility. The hardware implementation included a low power 32bit RISC CPU ARM7TDMI, a low power AHB-compatible bus, and a scalable digital co-processor that was optimized for low power Fast Fourier Transform (FFT) calculations. The co-processor could be scaled for 8-point, 16-point and 32-point FFTs, taking approximate 50, 100 and 150 clock circles, respectively. The complete design was intensively simulated using ARM DSM model and was emulated by ARM Versatile platform, before conducted to silicon. The multi-million-gate ASIC was fabricated using SMIC 0.18 microm mixed-signal CMOS 1P6M technology. The die area measures 5,000 microm x 2,350 microm. The power consumption was approximately 3.6 mW at 1.8 V power supply and 1 MHz clock rate. The power consumption for FFT calculations was less than 1.5 % comparing with the conventional embedded software-based solution.

  4. TARGET: A Digitizing And Trigger ASIC For The Cherenkov Telescope Array

    CERN Document Server

    Funk, S; Katagiri, H; Kraus, M; Okumura, A; Schoorlemmer, H; Shigenaka, A; Tajima, H; Tibaldo, L; Varner, G; Zink, A; Zorn, J

    2016-01-01

    The future ground-based gamma-ray observatory Cherenkov Telescope Array (CTA) will feature multiple types of imaging atmospheric Cherenkov telescopes, each with thousands of pixels. To be affordable, camera concepts for these telescopes have to feature low cost per channel and at the same time meet the requirements for CTA in order to achieve the desired scientific goals. We present the concept of the TeV Array Readout Electronics with GSa/s sampling and Event Trigger (TARGET) Application Specific Circuit (ASIC), envisaged to be used in the cameras of various CTA telescopes, e.g. the Gamma-ray Cherenkov Telescope (GCT), a proposed 2-Mirror Small-Sized Telescope, and the Schwarzschild-Couder Telescope (SCT), a proposed Medium-Sized Telescope. In the latest version of this readout concept the sampling and trigger parts are split into dedicated ASICs, TARGET C and T5TEA, both providing 16 parallel input channels. TARGET C features a tunable sampling rate (usually 1 GSa/s), a 16k sample deep buffer for each chann...

  5. The TDCpix Readout ASIC: A 75 ps Resolution Timing Front-End for the Gigatrackerof theNA62 Experiment

    Science.gov (United States)

    Rinella, G. Aglieri; Fiorini, M.; Jarron, P.; Kaplon, J.; Kluge, A.; Martin, E.; Morel, M.; Noy, M.; Perktold, L.; Poltorak, K.

    NA62 is an experiment under development at the CERN Super Proton Synchrotron, aiming at measuring ultra rare kaon decays. The Gigatracker (GTK) detector shall combine on-beam tracking of individual particles with a time resolution of 150 ps rms. The peak flow of particles crossing the detector modules reaches 1.27 MHz/mm2 fora total rateof about 0.75 GHz.Ahybrid siliconpixel detectoris beingdevelopedto meet these requirements. The pixel chip for the Gigatracker (TDCpix) is under design. The TDCpix chip will feature 1800 square pixels of 300×300 μm2 arranged in a matrix of 45 rows × 40 columns. Bump-bonded to a silicon pixel sensor it shall perform time stamping of particle hits with a timing accuracybetter than 200 ps rms and a detection efficiencyabove 99%. The chosen architecture provides full separation of the sensitive analog amplifiers of the pixel matrix from the noisy digital circuits of the TDCs and of the readout blocks. Discriminated hit signals from each pixel are transmitted to the end of column region. An array ofTime to Digital Converters (TDC) is implemented at the bottom of the pixel array. The TDCs are based on time tagging the events with the fine time codes generated by Delay Locked Loops (DLL) and have a nominal time bin of ˜100 ps. Time stamps and time-over-threshold are recorded for each discriminated hit and the correction of the discriminator's time-walk is performed off-detector. Data are continuously transmitted on four 2.4 Gb/s serial output links. Adescription of the on-going design of the final TDCpix is given in this paper. Design choices and some technical implementation details are presented. Aprototype ASIC including thekeycomponents of this architecture has been manufactured. The achievement of specification figures such as a time resolution of the processing chain of 75 ps rms as well as charged particle time stampingwitha resolutionbetterthan200psrmswere demonstratedexperimentally.Asummaryoftheseresultsisalso presented in

  6. 面向 ASIC 实现的 CPA 研究平台及其应用%Design and application of CPA research platform for ASIC

    Institute of Scientific and Technical Information of China (English)

    王晨旭; 张凯峰; 喻明艳; 王进祥

    2013-01-01

    Differential Power Analysis(DPA), a technology of non-invasive side-channel attack, has posed a serious threat for the safety of cipher integrated circuits. In order to evaluate the effectiveness of power analysis attack countermeasure conveniently, following the gate-level power analysis method, a Correlation Power Analysis(CPA)research platform based on PrimeTime PX and MATLAB is built. The auxiliary platform has a strong universality, and only by reworking cipher-specific power model, the algorithm level countermeasures for different ciphers can be evaluated easily. As an application, standard AES algorithm and the improved AES algorithm with threshold countermeasure method is attacked, showing the platform effectiveness.%  差分功耗分析(DPA)是一种非侵入式边信道攻击技术,对各种密码芯片的安全构成了极大威胁。为了能够快速地评估密码算法 ASIC 实现方式的算法级抗功耗分析攻击措施的实际效果,将门级功耗分析方法应用于功耗分析攻击评估技术中,搭建了基于 PrimeTime PX 和 MATLAB 的相关性功耗分析(CPA)研究平台。该平台具有较强的通用性,只需修改算法攻击功耗模型部分,即可快速完成对不同密码算法 ASIC 实现中算法级防护措施的评估。作为应用,利用该平台分别对普通 AES 算法实现和基于 Threshold 技术的 AES 算法实现进行了相关性攻击实验,证明了该平台的有效性和便捷性。

  7. A multi-channel 24.4 ps bin size Time-to-Digital Converter for HEP applications

    CERN Document Server

    Mester, C; Morira, P

    2008-01-01

    A multi-channel time-tagging Time-to-Digital Converter (TDC) ASIC with a resolution of 24.4 ps (bin size) has been implemented and fabricated in a 130 nm CMOS technology. An on-chip PLL is used to generate an internal timing reference from an external 40 MHz clock source. The circuit is based on a 32 element Delay Locked Loop (DLL) which performs the time interpolation. The 32 channel architecture of the TDC is suitable for both triggered and non-triggered applications. The prototype contains test structures such as a substrate noise generator. The paper describes the circuit architecture and its principles of operation.

  8. Improving Power Converter Reliability

    DEFF Research Database (Denmark)

    Ghimire, Pramod; de Vega, Angel Ruiz; Beczkowski, Szymon;

    2014-01-01

    The real-time junction temperature monitoring of a high-power insulated-gate bipolar transistor (IGBT) module is important to increase the overall reliability of power converters for industrial applications. This article proposes a new method to measure the on-state collector?emitter voltage...... of a high-power IGBT module during converter operation, which may play a vital role in improving the reliability of the power converters. The measured voltage is used to estimate the module average junction temperature of the high and low-voltage side of a half-bridge IGBT separately in every fundamental...... cycle of the current by calibrating them at load current. The measurement is very accurate and also measures the voltage at the middle of a pulse-width modulation (PWM) switching. A major objective is that this method is designed to be implemented in real applications. The performance of this technique...

  9. Angiotensin-converting enzyme

    DEFF Research Database (Denmark)

    Sørensen, P G; Rømer, F K; Cortes, D

    1984-01-01

    In order to evaluate bleomycin-associated lung damage in humans, lung function parameters and serum levels of the endothelial-bound angiotensin-converting enzyme (ACE) were determined by serial measurements in 11 patients who were treated for testicular cancer. None developed clinical or radiolog......In order to evaluate bleomycin-associated lung damage in humans, lung function parameters and serum levels of the endothelial-bound angiotensin-converting enzyme (ACE) were determined by serial measurements in 11 patients who were treated for testicular cancer. None developed clinical...

  10. A ±6 ms-Accuracy, 0.68 mm2, and 2.21 μW QRS Detection ASIC

    OpenAIRE

    Sheng-Chieh Huang; Hui-Min Wang; Wei-Yu Chen

    2012-01-01

    Healthcare issues arose from population aging. Meanwhile, electrocardiogram (ECG) is a powerful measurement tool. The first step of ECG is to detect QRS complexes. A state-of-the-art QRS detection algorithm was modified and implemented to an application-specific integrated circuit (ASIC). By the dedicated architecture design, the novel ASIC is proposed with 0.68 mm2 core area and 2.21 μW power consumption. It is the smallest QRS detection ASIC based on 0.18 μm technology. In addition, the sen...

  11. The Convertible Arbitrage Strategy Analyzed

    NARCIS (Netherlands)

    Loncarski, I.; Ter Horst, J.R.; Veld, C.H.

    2006-01-01

    This paper analyzes convertible bond arbitrage on the Canadian market for the period 1998 to 2004.Convertible bond arbitrage is the combination of a long position in convertible bonds and a short position in the underlying stocks. Convertible arbitrage has been one of the most successful strategies

  12. Convertible Proxy Signcryption Scheme

    Institute of Scientific and Technical Information of China (English)

    李继国; 李建中; 曹珍富; 张亦辰

    2004-01-01

    In 1996, Mambo et al introduced the concept of proxy signature. However, proxy signature can only provide the delegated authenticity and cannot provide confidentiality. Recently, Gamage et al and Chan and Wei proposed different proxy signcryption schemes respectively, which extended the concept of proxy signature.However, only the specified receiver can decrypt and verify the validity of proxy signcryption in their schemes.To protect the receiver' s benefit in case of a later dispute, Wu and Hsu proposed a convertible authenticated encryption scheme, which carn enable the receiver to convert signature into an ordinary one that can be verified by anyone. Based on Wu and Hsu' s scheme and improved Kim' s scheme, we propose a convertible proxy signcryption scheme. The security of the proposed scheme is based on the intractability of reversing the one-way hash function and solving the discrete logarithm problem. The proposed scheme can satisfy all properties of strong proxy signature and withstand the public key substitution attack and does not use secure channel. In addition, the proposed scheme can be extended to convertible threshold proxy signcryption scheme.

  13. An Electromagnetic Beam Converter

    DEFF Research Database (Denmark)

    2009-01-01

    The present invention relates to an electromagnetic beam converter and a method for conversion of an input beam of electromagnetic radiation having a bell shaped intensity profile a(x,y) into an output beam having a prescribed target intensity profile l(x',y') based on a further development...

  14. Definition of Power Converters

    CERN Document Server

    Bordry, F

    2015-01-01

    The paper is intended to introduce power conversion principles and to define common terms in the domain. The concept s of sources and switches are defined and classified. From the basic laws of source interconnections, a generic method of power converter synthesis is presented. Some examples illustrate this systematic method. Finally, the commutation cell and soft commuta tion are introduced and discussedd.

  15. Fractional Watt AMTEC Converter

    Science.gov (United States)

    Hunt, T. K.; Rasmussen, J. R.

    2006-01-01

    We report here the long term performance of a small, multi-tube AMTEC converter. This converter was designed to operate and produce approximately 12 watt of electrical output from a small, 4 to 6 watt radioisotope heat source for remote power applications. It was built and put on test in 1999 using electrical heaters as stand-ins for the radioisotope capsule. Since that time it has accumulated more than 5 years of run time at an input heater temperature of 700 °C, with numerous thermal cycles to ambient that were generally related to grid power failures or physical moves of the test apparatus. The power output has remained, with variations due to orientation changes and minor variations due to small temperature changes, essentially constant at 0.40 W to 0.60 W over the test period and operation is ongoing. The converter casing and mechanical structure was fabricated from 316 SS and the electrodes are sputtered titanium nitride films. Separate static tests of a multilayer insulation package suitable for use with the converter showed the capability to reach 700 °C with a thermal input of < 4 watts.

  16. Advanced DC/DC converters

    CERN Document Server

    Luo, Fang Lin

    2003-01-01

    INTRODUCTIONHistorical ReviewMultiple Quadrant ChoppersPump CircuitsDevelopment of DC/DC Conversion TechniqueCategorize Prototypes and DC/DC Converters Family TreeVOLTAGE-LIFT CONVERTERSIntroductionSeven Self-Lift ConvertersPositive Output Luo-ConvertersNegative Output Luo-ConvertersModified Positive Output Luo-Converters Double Output Luo-ConvertersPOSITIVE OUTPUT SUPER-LIFT LUO-CONVERTERS IntroductionMain SeriesAdditional SeriesEnhanced Series Re-Enhanced Series Multiple-Enhanced Series Summary of Positive Output

  17. Design Methodology: ASICs with complex in-pixel processing for Pixel Detectors

    Energy Technology Data Exchange (ETDEWEB)

    Fahim, Farah [Fermilab

    2014-10-31

    The development of Application Specific Integrated Circuits (ASIC) for pixel detectors with complex in-pixel processing using Computer Aided Design (CAD) tools that are, themselves, mainly developed for the design of conventional digital circuits requires a specialized approach. Mixed signal pixels often require parasitically aware detailed analog front-ends and extremely compact digital back-ends with more than 1000 transistors in small areas below 100μm x 100μm. These pixels are tiled to create large arrays, which have the same clock distribution and data readout speed constraints as in, for example, micro-processors. The methodology uses a modified mixed-mode on-top digital implementation flow to not only harness the tool efficiency for timing and floor-planning but also to maintain designer control over compact parasitically aware layout.

  18. SOMA A Tool for Synthesizing and Optimizing Memory Accesses in ASICs

    DEFF Research Database (Denmark)

    Venkataramani, Girish; Bjerregaard, Tobias; Chelcea, Tiberiu;

    2005-01-01

    Arbitrary memory dependencies and variable latency memory systems are major obstacles to the synthesis of large-scale ASIC systems in high-level synthesis. This paper presents SOMA, a synthesis framework for constructing Memory Access Network (MAN) architectures that inherently enforce memory...... consistency in the presence of dynamic memory access dependencies. A fundamental bottleneck in any such network is arbitrating between concurrent accesses to a shared memory resource. To alleviate this bottleneck, SOMA uses an application-specific concurrency analysis technique to predict the dynamic memory...... building blocks. SOMA has been successfully integrated into an automated C-to-hardware synthesis flow, which generates standard cell circuits from unrestricted ANSI-C programs. Post-layout experiments demonstrate that application specific MAN construction significantly improves power and performance....

  19. The eight-channel ASIC bipolar transresistance amplifier D0M AMPL-8.3

    CERN Document Server

    Alexeev, G D; Dvornikov, O V; Khokhlov, A I; Mikhailov, V A; Odnokloubov, I A; Tokmenin, V V

    2001-01-01

    The eight-channel ASIC low-noise bipolar transresistance amplifier D0M Ampl-8.3 has been designed on the basis of BJT-JFET technology for gaseous wire detectors used in high-energy physics experiments. The amplifier has differential gain 130 mV/mu A at 1 k OMEGA, input noise 35 and 60 nA r.m.s. at 0 and 60 pF input capacitance, respectively, leading/trailing edge 7 ns, input resistance approx 50 OMEGA, crosstalks -47 dB, dissipated power 160 triple bond 640 mW/chip for +-3 triple bond 5 V supply. The Ampl-8.3 has been accepted for upgrading the Forward Angle Muon System of the D0 experiment (Fermilab, Batavia, USA), the total number of channels is about 50,000.

  20. Very Low-Power Consumption Analog Pulse Processing ASIC for Semiconductor Radiation Detectors

    International Nuclear Information System (INIS)

    We describe a very-low power consumption circuit for processing the pulses from a semiconductor radiation detector. The circuit was designed for use with a cadmium zinc telluride (CZT) detector for unattended monitoring of stored nuclear materials. The device is intended to be battery powered and operate at low duty-cycles over a long period of time. This system will provide adequate performance for medium resolution gamma-ray pulse-height spectroscopy applications. The circuit incorporates the functions of a charge sensitive preamplifier, shaping amplifier, and peak sample and hold circuit. An application specific integrated circuit (ASIC) version of the design has been designed, built and tested. With the exception of the input field effect transistor (FET), the circuit is constructed using bipolar components. In this paper the design philosophy and measured performance characteristics of the circuit are described

  1. SCOTT: A time and amplitude digitizer ASIC for PMT signal processing

    Energy Technology Data Exchange (ETDEWEB)

    Ferry, S., E-mail: sophie.ferry@cea.fr [CEA/ Irfu/ SPP, Gif-sur-Yvette (France); Guilloux, F.; Anvar, S.; Chateau, F.; Delagnes, E.; Gautard, V.; Louis, F.; Monmarthe, E.; Le Provost, H. [CEA/ Irfu/ SEDI, Gif-sur-Yvette (France); Russo, S. [Dipartimento di Scienze Fisiche Università di Napoli, Napoli (Italy); Schuller, J-P.; Stolarczyk, Th.; Vallage, B. [CEA/ Irfu/ SPP, Gif-sur-Yvette (France); Zonca, E. [CEA/ Irfu/ SEDI, Gif-sur-Yvette (France)

    2013-10-11

    SCOTT is an ASIC designed for the readout electronics of photomultiplier tubes developed for KM3NeT, the cubic-kilometer scale neutrino telescope in Mediterranean Sea. To digitize the PMT signals, the multi-time-over-threshold technique is used with up to 16 adjustable thresholds. Digital outputs of discriminators feed a circular sampling memory and a “first in first out” digital memory. A specific study has shown that five specifically chosen thresholds are suited to reach the required timing accuracy. A dedicated method based on the duration of the signal over a given threshold allows an equivalent timing precision at any charge. To verify that the KM3NeT requirements are fulfilled, this method is applied on PMT signals digitized by SCOTT.

  2. A high speed serializer ASIC for ATLAS Liquid Argon calorimeter upgrade

    CERN Document Server

    Liu, T; The ATLAS collaboration

    2014-01-01

    We have been developing a serializer application-specific integrated circuit (ASIC) based on a commercial 0.25-μm silicon-on-sapphire (SOS) CMOS technology for the ATLAS liquid argon calorimeter front-end electronics upgrade. The first prototype, a 5 Gbps 16:1 serializer has been designed, fabricated, and tested in lab environment and in 200 MeV proton beam. The test results indicate that the first prototype meets the design goals. The second prototype, a double-lane, 8 Gbps per lane serializer is under development. The post layout simulation indicates that 8 Gbps is achievable. In this paper we present the design and the test results of the first prototype and the design and status of the second prototype.

  3. Update on the high speed serializer ASIC development for ATLAS Liquid Argon calorimeter upgrade

    CERN Document Server

    Liu, T; The ATLAS collaboration

    2011-01-01

    We have been developing a serializer application-specific integrated circuit (ASIC) based on a commercial 0.25-μm silicon-on-sapphire (SOS) CMOS technology for the ATLAS liquid argon calorimeter front-end electronics upgrade. The first prototype, a 5 Gbps 16:1 serializer has been designed, fabricated, and tested in lab environment and in a 200 MeV proton beam. The test results indicate that the first prototype meets the design goals. The second prototype, a double-lane, 8 Gbps per lane serializer is under development. The post-layout simulation indicates that 8 Gbps is achievable. In this paper we present the design and the test results of the first prototype and the design and status of the second prototype.

  4. Performance and future development of the ASDBLR ASIC for the ATLAS TRT

    CERN Document Server

    Bevensee, B E; Newcomer, F M; Tyrrell, B; Van Berg, R; Williams, H H; Romaniouk, A

    1998-01-01

    The ATLAS TRT straw tracker will consist of more than 420 K straw tubes filled with a Xenon-based fast gas located in a magnetic field of 2 T. Some tubes will operate at rates in excess of 20 MHz. Stringent signal processing goals $9 have been determined using both simulation tools and measurement standards set by hand tuned discrete component prototypes. These include the ability to detect the earliest clusters from ionizing tracks as well as energetic $9 transition radiation photons without baseline shifts in a low noise and low power design. We report on measurements of two ASIC's fabricated in different processes that appear to be capable of achieving these goals. (2 refs).

  5. A 2.5 gb/s GaAs ATM Mux Demux ASIC

    DEFF Research Database (Denmark)

    Madsen, Jens Kargaard; Lassen, Peter Stuhr

    1995-01-01

    This paper describes the design and implementation of a high speed GaAs ATM Mux Demur ASIC (AMDA) which is the key element in a high speed ATM Add-Drop unit. This unit is used in a new distributed ATM multiplexing-demultiplexing architecture for broadband switching systems. The Add-Drop unit...... provides a cell based interface between networks/systems operating at different data rates, the high speed interface being 2.5 Gb/s and the low speed interface being 155/622 Mb/s. Self-timed FIFOs are used for handling the speed gaps between domains operating at different clock rates, and a Self-Timed At...... Receiver's Input (STARI) interface is used at all high speed chip-to-chip links to eliminate timing skews The AMDA demonstrated operation above 4 Gb/s (500 MHz clock frequency) with an associated power dissipation of 5 W...

  6. Investigation of a Superscalar Operand Stack Using FO4 and ASIC Wire-Delay Metrics

    Directory of Open Access Journals (Sweden)

    Christopher Bailey

    2014-01-01

    Full Text Available Complexity in processor microarchitecture and the related issues of power density, hot spots and wire delay, are seen to be a major concern for design migration into low nanometer technologies of the future. This paper evaluates the hardware cost of an alternative to register-file organization, the superscalar stack issue array (SSIA. We believe this is the first such reported study using discrete stack elements. Several possible implementations are evaluated, using a 90 nm standard cell library as a reference model, yielding delay data and FO4 metrics. The evaluation, including reference to ASIC layout, RC extraction, and timing simulation, suggests a 4-wide issue rate of at least four Giga-ops/sec at 90 nm and opportunities for twofold future improvement by using more advanced design approaches.

  7. An important step forward in continuous spectroscopic imaging of ionising radiations using ASICs

    CERN Document Server

    Fessler, P; Eberle, H; Raad-Iseli, C D; Hilt, B; Huss, D; Krummenacher, F; Lutz, Jean Robert; Prevot, G; Renouprez, Albert Jean; Sigward, M H; Schwaller, B; Voltolini, C

    1999-01-01

    Characterization results are given for an original ASIC allowing continuous acquisition of ionising radiation images in spectroscopic mode. Ionising radiation imaging in general and spectroscopic imaging in particular must primarily be guided by the attempt to decrease statistical noise, which requires detection systems designed to allow very high counting rates. Any source of dead time must therefore be avoided. Thus, the use of on-line corrections of the inevitable dispersion of characteristics between the large number of electronic channels of the detection system, shall be precluded. Without claiming to achieve ultimate noise levels, the work described is focused on how to prevent good individual acquisition channel noise performance from being totally destroyed by the dispersion between channels without introducing dead times. With this goal, we developed an automatic charge amplifier output voltage offset compensation system which operates regardless of the cause of the offset (detector or electronic). ...

  8. Capturing a failure of an ASIC in-situ, using infrared radiometry and image processing software

    Science.gov (United States)

    Ruiz, Ronald P.

    2003-01-01

    Failures in electronic devices can sometimes be tricky to locate-especially if they are buried inside radiation-shielded containers designed to work in outer space. Such was the case with a malfunctioning ASIC (Application Specific Integrated Circuit) that was drawing excessive power at a specific temperature during temperature cycle testing. To analyze the failure, infrared radiometry (thermography) was used in combination with image processing software to locate precisely where the power was being dissipated at the moment the failure took place. The IR imaging software was used to make the image of the target and background, appear as unity. As testing proceeded and the failure mode was reached, temperature changes revealed the precise location of the fault. The results gave the design engineers the information they needed to fix the problem. This paper describes the techniques and equipment used to accomplish this failure analysis.

  9. Very Low-Power Consumption Analog Pulse Processing ASIC for Semiconductor Radiation Detectors

    Energy Technology Data Exchange (ETDEWEB)

    Wessendorf, K.O.; Lund, J.C.; Brunett, B.A.; Laguna, G.R.; Clements, J.W.

    1999-08-23

    We describe a very-low power consumption circuit for processing the pulses from a semiconductor radiation detector. The circuit was designed for use with a cadmium zinc telluride (CZT) detector for unattended monitoring of stored nuclear materials. The device is intended to be battery powered and operate at low duty-cycles over a long period of time. This system will provide adequate performance for medium resolution gamma-ray pulse-height spectroscopy applications. The circuit incorporates the functions of a charge sensitive preamplifier, shaping amplifier, and peak sample and hold circuit. An application specific integrated circuit (ASIC) version of the design has been designed, built and tested. With the exception of the input field effect transistor (FET), the circuit is constructed using bipolar components. In this paper the design philosophy and measured performance characteristics of the circuit are described.

  10. Analogue Sum ASIC for L1 Trigger Decision in Cherenkov Telescope Cameras

    CERN Document Server

    Barrio, Joan Abel; Boix, Joan; Delagnes, Eric; Delgado, Carlos; Coromina, Lluis Freixas; Gascon, David; Guilloux, Fabrice; Coto, Ruben Lopez; Martinez, Gustavo; Sanuy, Andreu; Tejedor, Luis Angel

    2014-01-01

    The Cherenkov Telescope Array (CTA) project aims to build the largest ground-based gamma-ray observatory based on an array of Imaging Atmospheric Cherenkov Telescopes (IACTs). The CTA will implement a multi-level trigger system to distinguish between gamma ray-like induced showers and background images induced by night sky background (NSB) light. The trigger system is based on coincident detections among pixels (level 0 trigger), clusters of pixels (level 1) or telescopes. In this article, the first version of the application specific integrated circuit (ASIC) for Level 1 trigger system is presented, capable of working with different Level 0 strategies and different trigger region sizes. In addition, it complies with all the requirements specified by the CTA project, specially the most critical ones as regards noise, bandwidth, dynamic range and power consumption. All these features make the presented system very suitable for use in the CTA cameras and improve the features of discrete components prototypes of...

  11. Design methodology: edgeless 3D ASICs with complex in-pixel processing for pixel detectors

    Energy Technology Data Exchange (ETDEWEB)

    Fahim Farah, Fahim Farah [Northwestern U. (main); Deptuch, Grzegorz W. [Fermilab; Hoff, James R. [Fermilab; Mohseni, Hooman [Northwestern U. (main)

    2015-08-28

    The design methodology for the development of 3D integrated edgeless pixel detectors with in-pixel processing using Electronic Design Automation (EDA) tools is presented. A large area 3 tier 3D detector with one sensor layer and two ASIC layers containing one analog and one digital tier, is built for x-ray photon time of arrival measurement and imaging. A full custom analog pixel is 65μm x 65μm. It is connected to a sensor pixel of the same size on one side, and on the other side it has approximately 40 connections to the digital pixel. A 32 x 32 edgeless array without any peripheral functional blocks constitutes a sub-chip. The sub-chip is an indivisible unit, which is further arranged in a 6 x 6 array to create the entire 1.248cm x 1.248cm ASIC. Each chip has 720 bump-bond I/O connections, on the back of the digital tier to the ceramic PCB. All the analog tier power and biasing is conveyed through the digital tier from the PCB. The assembly has no peripheral functional blocks, and hence the active area extends to the edge of the detector. This was achieved by using a few flavors of almost identical analog pixels (minimal variation in layout) to allow for peripheral biasing blocks to be placed within pixels. The 1024 pixels within a digital sub-chip array have a variety of full custom, semi-custom and automated timing driven functional blocks placed together. The methodology uses a modified mixed-mode on-top digital implementation flow to not only harness the tool efficiency for timing and floor-planning but also to maintain designer control over compact parasitically aware layout. The methodology uses the Cadence design platform, however it is not limited to this tool.

  12. A 1.0 V 78 mircoW reconfigurable ASIC embedded in an intelligent electrode for continuous remote ECG applications.

    Science.gov (United States)

    Yang, Geng; Chen, Jian; Jonsson, Fredrik; Tenhunen, Hannu; Zheng, Li-Rong

    2009-01-01

    In this paper, a reconfigurable, low-power Application Specific Integrated Circuit (ASIC) that extracts and transmits electrocardiograph (ECG) signals is presented. An Intelligent Electrode is introduced which consists of the proposed ASIC and a micro spike array, permitting onsite ECG signal acquisition, processing and transmission. Fabricated in a standard 0.18 microm CMOS process, the ASIC consumes 78 microW with 1.0 V core voltage at 6 MHz operating frequency and only occupies 2.25 mm(2). The tiny silicon size makes it possible and suitable to embed the proposed ASIC into an Intelligent Electrode, and the low power consumption makes it feasible for long term continuous ECG monitoring. PMID:19965175

  13. A ±6 ms-Accuracy, 0.68 mm2, and 2.21 μW QRS Detection ASIC

    Directory of Open Access Journals (Sweden)

    Sheng-Chieh Huang

    2012-01-01

    Full Text Available Healthcare issues arose from population aging. Meanwhile, electrocardiogram (ECG is a powerful measurement tool. The first step of ECG is to detect QRS complexes. A state-of-the-art QRS detection algorithm was modified and implemented to an application-specific integrated circuit (ASIC. By the dedicated architecture design, the novel ASIC is proposed with 0.68 mm2 core area and 2.21 μW power consumption. It is the smallest QRS detection ASIC based on 0.18 μm technology. In addition, the sensitivity is 95.65% and the positive prediction of the ASIC is 99.36% based on the MIT/BIH arrhythmia database certification.

  14. DSP controlled power converter

    OpenAIRE

    Chan, CH; Pong, MH

    1995-01-01

    A digital controller is designed and implemented by a Digital Signal Processor (DSP) to replace the Pulse Width Modulator (PWM) and error amplifier compensation network in a two wheeler forward converter. The DSP controller is designed in three approaches: a) Discretization of analog controller - the design is based on the transfer function of the error amplifier compensation network. b) Digital PID controller design - the design is based on the general form of the pulse transfer function of ...

  15. The function and regulation of acid-sensing ion channels (ASICs) and the epithelial Na(+) channel (ENaC): IUPHAR Review 19.

    Science.gov (United States)

    Boscardin, Emilie; Alijevic, Omar; Hummler, Edith; Frateschi, Simona; Kellenberger, Stephan

    2016-09-01

    Acid-sensing ion channels (ASICs) and the epithelial Na(+) channel (ENaC) are both members of the ENaC/degenerin family of amiloride-sensitive Na(+) channels. ASICs act as proton sensors in the nervous system where they contribute, besides other roles, to fear behaviour, learning and pain sensation. ENaC mediates Na(+) reabsorption across epithelia of the distal kidney and colon and of the airways. ENaC is a clinically used drug target in the context of hypertension and cystic fibrosis, while ASIC is an interesting potential target. Following a brief introduction, here we will review selected aspects of ASIC and ENaC function. We discuss the origin and nature of pH changes in the brain and the involvement of ASICs in synaptic signalling. We expose how in the peripheral nervous system, ASICs cover together with other ion channels a wide pH range as proton sensors. We introduce the mechanisms of aldosterone-dependent ENaC regulation and the evidence for an aldosterone-independent control of ENaC activity, such as regulation by dietary K(+) . We then provide an overview of the regulation of ENaC by proteases, a topic of increasing interest over the past few years. In spite of the profound differences in the physiological and pathological roles of ASICs and ENaC, these channels share many basic functional and structural properties. It is likely that further research will identify physiological contexts in which ASICs and ENaC have similar or overlapping roles. PMID:27278329

  16. PcTx1 affords neuroprotection in a conscious model of stroke in hypertensive rats via selective inhibition of ASIC1a.

    Science.gov (United States)

    McCarthy, Claudia A; Rash, Lachlan D; Chassagnon, Irène R; King, Glenn F; Widdop, Robert E

    2015-12-01

    Acid-sensing ion channel 1a (ASIC1a) is the primary acid sensor in mammalian brain and plays a major role in neuronal injury following cerebral ischemia. Evidence that inhibition of ASIC1a might be neuroprotective following stroke was previously obtained using "PcTx1 venom" from the tarantula Psalmopeous cambridgei. We show here that the ASIC1a-selective blocker PcTx1 is present at only 0.4% abundance in this venom, leading to uncertainty as to whether the observed neuroprotective effects were due to PcTx1 blockade of ASIC1a or inhibition of other ion channels and receptors by the hundreds of peptides and small molecules present in the venom. We therefore examined whether pure PcTx1 is neuroprotective in a conscious model of stroke via direct inhibition of ASIC1a. A focal reperfusion model of stroke was induced in conscious spontaneously hypertensive rats (SHR) by administering endothelin-1 to the middle cerebral artery via a surgically implanted cannula. Two hours later, SHR were treated with a single intracerebroventricular (i.c.v.) dose of PcTx1 (1 ng/kg), an ASIC1a-inactive mutant of PcTx1 (1 ng/kg), or saline, and ledged beam and neurological tests were used to assess the severity of symptomatic changes. PcTx1 markedly reduced cortical and striatal infarct volumes measured 72 h post-stroke, which correlated with improvements in neurological score, motor function and preservation of neuronal architecture. In contrast, the inactive PcTx1 analogue had no effect on stroke outcome. This is the first demonstration that selective pharmacological inhibition of ASIC1a is neuroprotective in conscious SHRs, thus validating inhibition of ASIC1a as a potential treatment for stroke. PMID:26320544

  17. Convertible bond valuation focusing on Chinese convertible bond market

    OpenAIRE

    Yang, Ke

    2010-01-01

    This paper mainly discusses the methods of valuation of convertible bonds in Chinese market. Different from common convertible bonds in European market, considering the complicate features of Chinese convertible bond, this paper represents specific pricing approaches for pricing convertible bonds with different provisions along with the increment of complexity of these provisions. More specifically, this paper represents the decomposing method and binomial tree method for pricing both of Non-...

  18. Development of New European VLIW Space DSP ASICS, IP Cores and Related Software via ESA Contracts in 2015 and Beyond

    Science.gov (United States)

    Trautner, R.

    2015-09-01

    European space industry needs a new generation of payload data processors in order to cope with in-creasing payload data processing requirements. ESA has defined a roadmap for the development of future payload processor hardware which is being implemented. A key part of this roadmap addresses the development of VLIW Digital Signal Processor (DSP) ASICs, IP cores and associated software. In this paper, we first present an overview of the ESA roadmap and the key development routes. We recapitulate the activities that have created the technology base for the ongoing DSP development, and present the ASIC development and several accompanying activities that will lead to the availability of a new space qualified DSP - the Scalable Sensor Data Processor (SSDP) - in the near future. We then present the expected future evolution of this technology area, and summarize the corresponding ESA roadmap part on VLIW DSPs and related IP and software.

  19. Development and evaluation of an ultra-fast ASIC for future PET scanners using TOF-capable MPPC array detectors

    Energy Technology Data Exchange (ETDEWEB)

    Ambe, T., E-mail: hiro-a-be.n@akane.waseda.jp [Research Institute for Science and Engineering, Waseda University, 3-4-1, Okubo, Shinjuku, Tokyo (Japan); Ikeda, H. [ISAS/JAXA, 3-1-1, Yoshinodai, Chuo-ku, Sagamihara-shi, Kanagawa (Japan); Kataoka, J.; Matsuda, H.; Kato, T. [Research Institute for Science and Engineering, Waseda University, 3-4-1, Okubo, Shinjuku, Tokyo (Japan)

    2015-01-21

    We developed a front-end ASIC for future PET scanners with Time-Of-Flight (TOF) capability to be coupled with 4×4 Multi-Pixel Photon Counter (MPPC) arrays. The ASIC is designed based on the open-IP project proposed by JAXA and realized in TSMC 0.35 μm CMOS technology. The circuit comprises 16-channel, low impedance current conveyors for effectively acquiring fast MPPC signals. For precise measurement of the coincidence timing of 511-keV gamma rays, the leading-edge method was used to discriminate the signals. We first tested the time response of the ASIC by illuminating each channel of a MPPC array device 3×3 mm{sup 2} in size with a Pico-second Light Pulsar with a light emission peak of 655 nm and pulse duration of 54 ps (FWHM). We obtained 105 ps (FWHM) on average for each channel in time jitter measurements. Moreover, we compensated for the time lag of each channel with inner delay circuits and succeeded in suppressing about a 700-ps lag to only 15 ps. This paper reports TOF measurements using back-to-back 511-keV signals, and suggests that the ASIC can be a promising device for future TOF-PET scanners based on the MPPC array. - Highlights: • We developed a newly designed large-area monolithic MPPC array. • We obtained fine gain uniformity, and good energy and time resolutions when coupled to the LYSO scintillator. • We fabricated gamma-ray camera consisting of the MPPC array and the submillimeter pixelized LYSO and GGAG scintillators. • In the flood images, each crystal of scintillator matrices was clearly resolved. • Good energy resolutions for 662 keV gamma-rays for each LYSO and GGAG scintillator matrices were obtained.

  20. Design and performances of a low-noise and radiation-hardened readout ASIC for CdZnTe detectors

    Science.gov (United States)

    Bo, Gan; Tingcun, Wei; Wu, Gao; Yongcai, Hu

    2016-06-01

    In this paper, we present the design and performances of a low-noise and radiation-hardened front-end readout application specific integrated circuit (ASIC) dedicated to CdZnTe detectors for a hard X-ray imager in space applications. The readout channel is comprised of a charge sensitive amplifier, a CR-RC shaping amplifier, an analog output buffer, a fast shaper, and a discriminator. An 8-channel prototype ASIC is designed and fabricated in TSMC 0.35-μm mixed-signal CMOS technology, the die size of the prototype chip is 2.2 × 2.2 mm2. The input energy range is from 5 to 350 keV. For this 8-channel prototype ASIC, the measured electrical characteristics are as follows: the overall gain of the readout channel is 210 V/pC, the linearity error is less than 2%, the crosstalk is less than 0.36%, The equivalent noise charge of a typical channel is 52.9 e‑ at zero farad plus 8.2 e‑ per picofarad, and the power consumption is less than 2.4 mW/channel. Through the measurement together with a CdZnTe detector, the energy resolution is 5.9% at the 59.5-keV line under the irradiation of the radioactive source 241Am. The radiation effect experiments show that the proposed ASIC can resist the total ionization dose (TID) irradiation of higher than 200 krad(Si). Project supported by the National Key Scientific Instrument and Equipment Development Project (No. 2011YQ040082), the National Natural Science Foundation of China (Nos. 11475136, 11575144, 61176094), and the Shaanxi Natural Science Foundation of China (No. 2015JM1016).

  1. Development of Charge Sensitive Preamplifier and Readout Integrate Circuit Board for High Resolution Detector using ASIC Process

    International Nuclear Information System (INIS)

    - Design of discrete type charge sensitive amplifier for high resolution semi-conductor sensor - Design and develop the test board for the performance of charge sensitive amplifier with sensor - Performance of electrical test for the sensor and charge sensitive amplifier - Development of prototype 8 x 8 array type detector module - Noise equivalent charge test for the charge sensitive amplifier - Design and development of Micro SMD discrete type amplifier applying ASIC procedure - Development of Hybrid type charge sensitive amplifier including shape

  2. Resonant power converters

    CERN Document Server

    Kazimierczuk, Marian K

    2012-01-01

    This book is devoted to resonant energy conversion in power electronics. It is a practical, systematic guide to the analysis and design of various dc-dc resonant inverters, high-frequency rectifiers, and dc-dc resonant converters that are building blocks of many of today's high-frequency energy processors. Designed to function as both a superior senior-to-graduate level textbook for electrical engineering courses and a valuable professional reference for practicing engineers, it provides students and engineers with a solid grasp of existing high-frequency technology, while acquainting them wit

  3. Cycloidal Wave Energy Converter

    Energy Technology Data Exchange (ETDEWEB)

    Stefan G. Siegel, Ph.D.

    2012-11-30

    This program allowed further advancing the development of a novel type of wave energy converter, a Cycloidal Wave Energy Converter or CycWEC. A CycWEC consists of one or more hydrofoils rotating around a central shaft, and operates fully submerged beneath the water surface. It operates under feedback control sensing the incoming waves, and converts wave power to shaft power directly without any intermediate power take off system. Previous research consisting of numerical simulations and two dimensional small 1:300 scale wave flume experiments had indicated wave cancellation efficiencies beyond 95%. The present work was centered on construction and testing of a 1:10 scale model and conducting two testing campaigns in a three dimensional wave basin. These experiments allowed for the first time for direct measurement of electrical power generated as well as the interaction of the CycWEC in a three dimensional environment. The Atargis team successfully conducted two testing campaigns at the Texas A&M Offshore Technology Research Center and was able to demonstrate electricity generation. In addition, three dimensional wave diffraction results show the ability to achieve wave focusing, thus increasing the amount of wave power that can be extracted beyond what was expected from earlier two dimensional investigations. Numerical results showed wave cancellation efficiencies for irregular waves to be on par with results for regular waves over a wide range of wave lengths. Using the results from previous simulations and experiments a full scale prototype was designed and its performance in a North Atlantic wave climate of average 30kW/m of wave crest was estimated. A full scale WEC with a blade span of 150m will deliver a design power of 5MW at an estimated levelized cost of energy (LCOE) in the range of 10-17 US cents per kWh. Based on the new results achieved in the 1:10 scale experiments these estimates appear conservative and the likely performance at full scale will

  4. SIGN LANGUAGE CONVERTER

    Directory of Open Access Journals (Sweden)

    Taner Arsan

    2015-08-01

    Full Text Available The aim of this paper is to design a convenient system that is helpful for the people who have hearing difficulties and in general who use very simple and effective method; sign language. This system can be used for converting sign language to voice and also voice to sign language. A motion capture system is used for sign language conversion and a voice recognition system for voice conversion. It captures the signs and dictates on the screen as writing. It also captures the voice and displays the sign language meaning on the screen as motioned image or video.

  5. SIGN LANGUAGE CONVERTER

    OpenAIRE

    Taner Arsan; Oğuz Ülgen

    2015-01-01

    The aim of this paper is to design a convenient system that is helpful for the people who have hearing difficulties and in general who use very simple and effective method; sign language. This system can be used for converting sign language to voice and also voice to sign language. A motion capture system is used for sign language conversion and a voice recognition system for voice conversion. It captures the signs and dictates on the screen as writing. It also captures the voice ...

  6. Studies and development of a readout ASIC for pixelated CdTe detectors for space applications

    International Nuclear Information System (INIS)

    The work presented in this thesis is part of a project where a new instrument is developed: a camera for hard X-rays imaging spectroscopy. It is dedicated to fundamental research for observations in astrophysics, at wavelengths which can only be observed using space-borne instruments. In this domain the spectroscopic accuracy as well as the imaging details are of high importance. This work has been realized at CEA/IRFU (Institut de Recherche sur les lois Fondamentales de l'Univers), which has a long-standing and successful experience in instruments for high energy physics and space physics instrumentation. The objective of this thesis is the design of the readout electronics for a pixelated CdTe detector, suitable for a stacked assembly. The principal parameters of this integrated circuit are a very low noise for reaching a good accuracy in X-ray energy measurement, very low power consumption, a critical parameter in space-borne applications, and a small dead area for the full system combining the detector and the readout electronics. In this work I have studied the limits of these three parameters in order to optimize the circuit. In terms of the spectral resolution, two categories of noise had to be distinguished to determine the final performance. The first is the Fano noise limit, related to detector interaction statistics, which cannot be eliminated. The second is the electronic noise, also unavoidable; however it can be minimized through optimization of the detection chain. Within the detector, establishing a small pixel pitch of 300 μm reduces the input capacitance and the dark current. This limits the effects of the electronic noise. Also in order to limit the input capacitance the future camera is designed as a stacked assembly of the detector with the readout ASIC. This allows to reach extremely good input parameters seen by the readout electronics: a capacitance in range of 0.3 pF-1 pF and a dark current below 5 pA. In the frame of this thesis I have

  7. Development of a CdTe pixel detector with a window comparator ASIC for high energy X-ray applications

    Science.gov (United States)

    Hirono, T.; Toyokawa, H.; Furukawa, Y.; Honma, T.; Ikeda, H.; Kawase, M.; Koganezawa, T.; Ohata, T.; Sato, M.; Sato, G.; Takagaki, M.; Takahashi, T.; Watanabe, S.

    2011-09-01

    We have developed a photon-counting-type CdTe pixel detector (SP8-01). SP8-01 was designed as a prototype of a high-energy X-ray imaging detector for experiments using synchrotron radiation. SP8-01 has a CdTe sensor of 500 μm thickness, which has an absorption efficiency of almost 100% up to 50 keV and 45% even at 100 keV. A full-custom application specific integrated circuit (ASIC) was designed as a readout circuit of SP8-01, which is equipped with a window-type discriminator. The upper discriminator realizes a low-background measurement, because X-ray beams from the monochromator contain higher-order components beside the fundamental X-rays in general. ASIC chips were fabricated with a TSMC 0.25 μm CMOS process, and CdTe sensors were bump-bonded to the ASIC chips by a gold-stud bonding technique. Beam tests were performed at SPring-8. SP8-01 detected X-rays up to 120 keV. The capability of SP8-01 as an imaging detector for high-energy X-ray synchrotron radiation was evaluated with its performance characteristics.

  8. A 58 nW ECG ASIC With Motion-Tolerant Heartbeat Timing Extraction for Wearable Cardiovascular Monitoring.

    Science.gov (United States)

    Da He, David; Sodini, Charles G

    2015-06-01

    An ASIC for wearable cardiovascular monitoring is implemented using a topology that takes advantage of the electrocardiogram's (ECG) waveform to replace the traditional ECG instrumentation amplifier, ADC, and signal processor with a single chip solution. The ASIC can extract heartbeat timings in the presence of baseline drift, muscle artifact, and signal clipping. The circuit can operate with ECGs ranging from the chest location to remote locations where the ECG magnitude is as low as 30 μV. Besides heartbeat detection, a midpoint estimation method can accurately extract the ECG R-wave timing, enabling the calculations of heart rate variability. With 58 nW of power consumption at 0.8 V supply voltage and 0.76 mm (2) of active die area in standard 0.18 μm CMOS technology, the ECG ASIC is sufficiently low power and compact to be suitable for long term and wearable cardiovascular monitoring applications under stringent battery and size constraints. PMID:25252285

  9. Inhibition of acid-induced apoptosis by targeting ASIC1a mRNA with short hairpin RNA

    Institute of Scientific and Technical Information of China (English)

    Xie-chuan WENG; Jian-quan ZHENG; Qing-e JIN; Xiao-yun MA

    2007-01-01

    Aim: To study the role of acid-sensing ion channel (ASIC) la in the cell death and apoptosis induced by extracellular acid in C6 glioma cells. Methods: The stable ASICla-silenced C6 cell line, built with RNA interference technology, were con-firmed by RT-PCR and Western blot analysis. The cell viability following acid exposure was analyzed with lactate dehydrogenase (LDH) and 3-(4,5-dimethylthiazol-2-yl)-2, 5-diphenyltetrazolium bromide (MTT) assay. The apoptotic cells dyed with Annexin-V and propidium iodide were measured with a flow cytometer, while the changes of cell cycle were also assayed. Results: The downregulation of ASIC 1 a proteins by stable transfection of short hairpin RNA decreased the cell death percentage and increased cell viability following acid exposure with LDH and the MTT assay. The rate of apoptosis was lower in the ASIC la-silenced cell line than that in the wild-type C6 cell line. The percentage of sub-G0 cells was lower in the ASICla-silenced C6 cells than that in the wild-type cells. Conclusion: Extracellular acid induced cell death and apoptosis viaASICla mechanisms in the C6 glioma cells.

  10. Design and ASIC Implemenatation of DUC/DDC for Communication Systems

    Directory of Open Access Journals (Sweden)

    Naagesh S. Bhat

    2012-01-01

    Full Text Available Communication systems use the concept of transmitting information using the electrical distribution network as a communication channel. To enable the transmission data signal modulated on a carrier signal is superimposed on the electrical wires. Typical power lines are designed to handle 50/60 Hz of AC power signal; however they can carry the signals up to 500 KHz frequency. This work aims to aid transmission/reception of an audio signal in the spectrum from 300 Hz to 4000 Hz using PLCC on a tunable carrier frequency in the spectrum from 200 KHz to 500 KHz. For digital amplitude modulation the sampling rate of the carrier and the audio signal has to be matched. Tunable carrier generation can be achieved with Direct Digital Synthesizers at a desired sampling rate. DSP Sample rate conversion techniques are very useful to make the sampling circuits to work on their own sampling rates which are fine for the data/modulated-carrier signal’s bandwidth. This also simplifies the complexity of the samplingcircuits. Digital Up Conversion (DUC and Digital Down Conversion (DDC are DSP sample rate conversion techniques which refer to increasing and decreasing the sampling rate of a signal respectively. The objective was to design and implement low power ASIC of DUC and DDC designs at 65nm for PLCC. Low power implementation was carried out using Multi-VDD technique. MATLAB software models were used to understand the DUC and DDC designs. RTL to GDS flow was executed using Synopsys tools such as VCS, Design Compiler, IC Compiler and PrimeTime. Key milestones of this activity are RTL verification, synthesis, gate-level simulations, low power architecture definitions, physical implementation, ASIC signoff checks and postroute delay based simulations. Multi-VDD technique deployed on DUC and DDC helped to reduce the power consumption from 280.9uW to 198.07uW and from 176.26uW to 124.47uW respectively. DUC and DUC designs have met functionality at 64MHz clock

  11. Design and ASIC Implemenatation of DUC/DDC for Communication Systems

    Directory of Open Access Journals (Sweden)

    Naagesh S. Bhat

    2011-12-01

    Full Text Available Communication systems use the concept of transmitting information using the electrical distribution network as a communication channel. To enable the transmission data signal modulated on a carrier signal is superimposed on the electrical wires. Typical power lines are designed to handle 50/60 Hz of AC power signal; however they can carry the signals up to 500 KHz frequency. This work aims to aid transmission/reception of an audio signal in the spectrum from 300 Hz to 4000 Hz using PLCC on a t unable carrier frequency in the spectrum from 200 KHz to 500 KHz. For digital amplitude modulation the sampling rate of the carrier and the audio signal has to be matched. T unable carrier generation can be achieved with Direct Digital Synthesizers at a desired sampling rate. DSP Sample rate conversion techniques are very useful to make the sampling circuits to work on their own sampling rates which are fine for the data/modulated-carrier signal’s bandwidth. This also simplifies the complexity of the sampling circuits. Digital Up Conversion (DUC and Digital Down Conversion (DDC are DSP sample rate conversion techniques which refer to increasing and decreasing the sampling rate of a signal respectively. The objective was to design and implement low power ASIC of DUC and DDC designs at 65nm for PLCC. Low power implementation was carried out using Multi-VDD technique. MATLAB software models were used to understand the DUC and DDC designs. RTL to GDS flow was executed using Synopsys tools such as VCS, Design Compiler, IC Compiler and Prime Time. Key milestones of this activity are RTL verification, synthesis, gate-level simulations, low power architecture definitions, physical implementation, ASIC signoff checks and post route delay based simulations. Multi-VDD technique deployed on DUC and DDC helped to reduce the power consumption from 280.9uW to 198.07uW and from 176.26uW to 124.47uW respectively. DUC and DUC designs have met functionality at 64MHz clock

  12. Systematic study of new types of Hamamatsu MPPCs read out with the NINO ASIC

    CERN Document Server

    Doroud, K; Williams, M C S; Yamamoto, K; Zichichi, A; Zuyeuski, R

    2014-01-01

    Over the last decade there have been commercial TOF-PET scanners constructed using Photo-Multiplier Tubes (PMT) that have achieved View the MathML source~500ps FWHM Coincidence Time Resolution (CTR). A new device known as the Silicon PhotoMultiplier (SiPM) has the potential to overcome some of the limitations of the PMT. Therefore implementing a SiPM based TOF-PET scanner is of high interest. Recently Philips has introduced a TOF-PET scanner that uses digital Silicon PhotoMultipliers (d-SiPMs) which has a CTR of 350 ps. Here we will report on the timing performance of two Hamamatsu 3×3 mm2 analogue-SiPMs read out with the NINO ASIC: this is an ultra-fast amplifier/discriminator with a differential architecture. The differential architecture is very important since the single-ended readout uses the ground as the signal return; as the ground is also the reference level for the discriminators, the result is high crosstalk and degraded time resolution. However differential readout allows the scaling up from a si...

  13. A 15 GSa/s, 1.5 GHz Bandwidth Waveform Digitizing ASIC

    CERN Document Server

    Oberla, E; Grabas, H; Frisch, H; Nishimura, K; Varner, G

    2013-01-01

    The PSEC4 custom integrated circuit was designed for the recording of fast waveforms for use in large-area time-of-flight detector systems. The ASIC has been fabricated using the IBM-8RF 0.13 micron CMOS process. On each of 6 analog channels, PSEC4 employs a switched capacitor array (SCA) 256 samples deep, a ramp-compare ADC with 10.5 bits of DC dynamic range, and a serial data readout with the capability of region-of-interest windowing to reduce dead time. The sampling rate can be adjusted between 4 and 15 Gigasamples/second [GSa/s] on all channels and is servo-controlled on-chip with a low-jitter delay-locked loop (DLL). The input signals are passively coupled on-chip with a -3 dB analog bandwidth of 1.5 GHz. The power consumption in quiescent sampling mode is less than 50 mW/chip; at a sustained trigger and readout rate of 50 kHz the chip draws 100 mW. After fixed-pattern pedestal subtraction, the uncorrected integral non-linearity is 0.15% over an 750 mV dynamic range. With a linearity correction, a full ...

  14. Sensor-based whole-arm obstacle avoidance utilizing ASIC technology

    International Nuclear Information System (INIS)

    Operation of manipulator systems in poorly defined work environments often presents a significant hazard to both the robotic assembly and the environment. In applications relating to the Environmental Restoration and Waste Management (ER ampersand WM) Program, many of the environments are considered hazardous, both, in the structure and composition of the environment Use of a sensing system that provides information to the manipulator control unit regarding obstacles in close proximity will provide protection against collisions. In this paper, a hierarchical design and implementation of a whole-arm obstacle avoidance system is presented. The system is based on capacitive sensors configured as bracelets for proximity sensing. Each bracelet contains a number of sensor nodes and a processor for sensor node control and readout, and communications with a higher level host, common to all bracelets. The host controls the entire sensing network and communicates proximity information to the manipulator controller. The overall architecture of this system is discussed with detail on the individual system modules. Details of an application specific integrated circuit (ASIC) designed to implement the sensor node electronics are presented. Justifications for the general measurement methods and associated implementation are discussed. Additionally, the current state of development including measured dam is presented

  15. Development of the analog ASIC for multi-channel readout X-ray CCD camera

    CERN Document Server

    Nakajima, Hiroshi; Idehara, Toshihiro; Anabuki, Naohisa; Tsunemi, Hiroshi; Doty, John P; Ikeda, Hirokazu; Katayama, Haruyoshi; Kitamura, Hisashi; Uchihori, Yukio; 10.1016/j.nima.2010.12.174

    2011-01-01

    We report on the performance of an analog application-specific integrated circuit (ASIC) developed aiming for the front-end electronics of the X-ray CCDcamera system onboard the next X-ray astronomical satellite, ASTRO-H. It has four identical channels that simultaneously process the CCD signals. Distinctive capability of analog-to-digital conversion enables us to construct a CCD camera body that outputs only digital signals. As the result of the front-end electronics test, it works properly with low input noise of =<30 uV at the pixel rate below 100 kHz. The power consumption is sufficiently low of about 150 mW/chip. The input signal range of 720 mV covers the effective energy range of the typical X-ray photon counting CCD (up to 20 keV). The integrated non-linearity is 0.2% that is similar as those of the conventional CCDs in orbit. We also performed a radiation tolerance test against the total ionizing dose (TID) effect and the single event effect. The irradiation test using 60Co and proton beam showed ...

  16. The coincidence matrix ASIC of the level-1 muon barrel trigger of the ATLAS experiment

    CERN Document Server

    Bocci, V; Salamon, A; Vari, R; Veneziano, Stefano

    2003-01-01

    The ATLAS barrel level-1 muon trigger processes hit information from the resistive plate chamber detector, identifying candidate muon tracks and assigning them to a programmable p/sub T/ range and to a unique bunch crossing number. The trigger system uses up to seven detector layers and seeks hit patterns compatible with muon tracks in the bending and nonbending projection. The basic principle of the algorithm is to demand a coincidence of hits in the different chamber layers within a path. The width of the road is related to the p/sub T / threshold to be applied. The system is split into an on-detector and an off-detector part. The on-detector electronics reduces the information from about 350 k channels to about 400 32-bit data words sent via optical fiber to the so-called sector logic (SL). The off- detector SL electronics collects muon candidates and associates them to detector regions-of-interest of Delta eta * Delta Phi of 0.1*0.1. The core of the on-detector electronics is the coincidence matrix ASIC (...

  17. A pixel detector asic for dosimetry using time-over-threshold energy measurements

    CERN Document Server

    Wong, W S; Ballabriga, R; Bohnel, M; Campbell, M; Heijne, E; Llopart, X; Michel, T; Munster, I; Plackett, R; Sievers, P; Takoukam, P; Tlustos, L; Valerio, P

    2011-01-01

    In this work we present the design of a chip which provides the readout of a highly segmented diode array, in which signals induced by individual X-ray photons are processed discretely. There are several benefits to this approach, including the ability to achieve a high signal to noise ratio due to the inherently low sensor capacitance, and the suppression of background noise (e.g. dark current) using an analogue threshold. The segmentation also ensures a linear behaviour even at very high dose rates. A time over threshold (ToT) energy measurement technique provides an immediate digital value corresponding to the energy deposited onto the diode by each individual photon. Deadtime-free operation is achieved by reading out a subset of the detector segments at a time while the rest of the detector continues to process signals. This paper describes the application-specific integrated circuit (ASIC) chip which was designed to provide pre-processing of photo-induced signals in the detector and readout of the proces...

  18. IDeF-X ASIC for Cd(Zn)Te spectro-imaging systems

    CERN Document Server

    Limousin, O; Lugiez, F; Chipaux, Rémi; Delagnes, E; Dirks, B; Horeau, B

    2004-01-01

    Joint progresses in Cd(Zn)Te detectors, microelectronics and interconnection technologies open the way for a new generation of instruments for physics and astrophysics applications in the energy range from 1 to 1000 keV. Even working between -20 and 20 degrees Celsius, these instruments will offer high spatial resolution (pixel size ranging from 300 x 300 square micrometers to few square millimeters), high spectral response and high detection efficiency. To reach these goals, reliable, highly integrated, low noise and low power consumption electronics is mandatory. Our group is currently developing a new ASIC detector front-end named IDeF-X, for modular spectro-imaging system based on the use of Cd(Zn)Te detectors. We present here the first version of IDeF-X which consists in a set of ten low noise charge sensitive preamplifiers (CSA). It has been processed with the standard AMS 0.35 micrometer CMOS technology. The CSA are designed to be DC coupled to detectors having a low dark current at room temperature. T...

  19. A Serializer ASIC at 5 Gbps for Detector Front-end Electronics Readout

    CERN Document Server

    Gong, D; The ATLAS collaboration; Liu, T; Xiang, A; Ye, J

    2010-01-01

    High speed and ultra low power serial data transmission over fiber optics plays an essential roll in detector front-end electronics readout for experiments at the LHC. The ATLAS Liquid Argon Calorimeter front-end readout upgrade for the sLHC calls for an optical link system with a data bandwidth of 100 Gbps per each front-end board (FEB), a factor of 62 increase compared with the present optical link system. The transmitter of this optical link will have to withstand the radiation environment where the front-end crates are situated, and stay within the current power dissipation budget limited by the present FEB cooling capacity. To meet these challenges, we developed a 16:1 serializer based on a commercial 0.25 μm silicon-on-sapphire (SOS) CMOS technology. This serializer, designed to work at 5 Gbps, is a key component in an optical link system. Test results of this ASIC will be reported. A system design for the 100 Gbps optical link system will also be presented, with discussions about key components identi...

  20. AFTER, the front end ASIC of the T2K Time Projection Chambers

    CERN Document Server

    Baron, P; Calvet, D; de la Broise, X; Delagnes, E; Delbart, A; Druillole, F; Le Coguie, A; Mazzucato, E; Monmarthe, E; Zito, M

    2009-01-01

    The T2K (Tokai-to-Kamioka) experiment is a long baseline neutrino oscillation experiment in Japan. A near detector, located at 280m of the production target, is used to characterize the beam. One of its key elements is a tracker, made of three Time Projection Chambers (TPC) read by Micromegas endplates. A new readout system has been developed to collect, amplify, condition and acquire the data produced by the 124,000 detector channels of these detectors. The front-end element of this system is a a new 72-channel application specific integrated circuit. Each channel includes a low noise charge preamplifier, a pole zero compensation stage, a second order Sallen-Key low pass filter and a 511-cell Switched Capacitor Array. This electronics offers a large flexibility in sampling frequency, shaping time, gain, while taking advantage of the low physics events rate of 0.3 Hz. We detail the design and the performance of this ASIC and report on the deployment of the frond-end electronics on-site.

  1. Calibration of ultra-thin hybrid pixel detector assemblies with Timepix readout ASICs

    CERN Document Server

    AUTHOR|(SzGeCERN)734627; Arfaoui, Samir; Benoit, Mathieu; Celeste, Damiano; Dannheim, Dominik; Pfleger, Florentina; Redford, Sophie

    2015-01-01

    In the framework of vertex detector R&D for a future Compact Linear Collider, the charac- terisation of ultra-thin hybrid pixel detector assemblies comprising 50 − 300 μm thick silicon sensors and Timepix readout ASICs is underway through beam tests at DESY and CERN. The work presented here supports the beam test data analysis by providing an energy calibra- tion of certain assemblies, so giving access to energy measurements in addition to recorded Time Over Threshold counts. Photons from a variety of radioactive sources and X-ray fluorescence are used to measure the response of the assemblies in the region of 3 − 60 keV. Threshold measurements are also performed. Global and pixel-by-pixel calibrations of the assemblies are parametrised and the uniformity of the response of the pixel matrices are discussed. Data samples recorded in beam tests are calibrated and the resulting energy spectra presented. For the first time calibration parameters are estimated for two 50 μm thick sensors which are forese...

  2. Front-end ASICs development for W-Si calorimeter at ILC

    International Nuclear Information System (INIS)

    An ASIC (FLCPHY3) has been developed to read out the test-beam prototype of the future international linear collider (ILC) tungsten-silicon calorimeter. It consists of 18 channels low-noise charge preamplifiers, bi-gain CRRC2 180 ns shapers, 12-bit track-and-hold, and a 5 MHz output multiplexer. It covers a dynamic range of 14 bits with a noise of 3500 e- with the 70 pF detector and a linearity at the per-mil level. The chip dissipates 6 mW/channel and 1000 chips have been produced in AMS 0.8 μm BiCMOS technology in 2003. One channel has recently been migrated into 0.35 μm, improving the series noise by 20% and the 1/f noise by two. Besides, a power pulsing feature has been added in order to exploit the 1% duty cycle of the accelerator. This feature is a key parameter for ILC, as it is mandatory to embed the front-end inside the detector, without spoiling the Moliere radius with cooling pipes. Preliminary results indicate a good behavior in pulsing mode and several hundred channels have been produced of the recent version including this feature (FLCPHY4), to be tested extensively in test beam at CERN in autumn 2006. FLCPHY4 also includes a 12-bit ADC in order to take a step to the final version, which will send digital data out

  3. The PASTA chip - A free-running readout ASIC for silicon strip sensors in PANDA

    Energy Technology Data Exchange (ETDEWEB)

    Goerres, Andre; Stockmanns, Tobias; Ritman, James [Institut fuer Kernphysik, Forschungszentrum Juelich, Juelich (Germany); Rivetti, Angelo [INFN Sezione di Torino, Torino (Italy); Collaboration: PANDA-Collaboration

    2014-07-01

    The PANDA experiment is a multi purpose detector, investigating hadron physics in the charm quark mass regime. It is one of the main experiments at the future FAIR accelerator facility, using pp annihilations from a 1.5-15 GeV/c anti-proton beam. Because of the broad physics spectrum and the similarity of event and background signals, PANDA does not rely on a hardware-level trigger decision. The innermost of PANDA's sub-systems is the Micro Vertex Detector (MVD), consisting of silicon pixel and strip sensors. The latter will be read out by a specialized, free-running readout front-end called PANDA Strip ASIC (PASTA). It has to face a high event rate of up to 40 kHz/ch in an radiation-intense environment. To fulfill the MVD's requirements, it has to give accurate timing information to incoming events (<10 ns) and determine the collected charge with an 8-bit precision. The design has to meet cooling and placing restrictions, leading to a very low power consumption (<4 mW/ch) and limited dimensions. Therefore, a simple, time-based readout approach is chosen. In this talk, the conceptual design of the front-end is presented.

  4. Reading a GEM with a VLSI pixel ASIC used as a direct charge collecting anode

    CERN Document Server

    Bellazzini, R; Baldini, L; Bitti, F; Brez, A; Latronico, L; Massai, M M; Minuti, M; Omodei, N; Razzano, M; Sgro, C; Spandre, G; Costa, E; Soffitta, P

    2004-01-01

    In MicroPattern Gas Detectors (MPGD) when the pixel size is below 100 micron and the number of pixels is large (above 1000) it is virtually impossible to use the conventional PCB read-out approach to bring the signal charge from the individual pixel to the external electronics chain. For this reason a custom CMOS array of 2101 active pixels with 80 micron pitch, directly used as the charge collecting anode of a GEM amplifying structure, has been developed and built. Each charge collecting pad, hexagonally shaped, realized using the top metal layer of a deep submicron VLSI technology is individually connected to a full electronics chain (pre-amplifier, shaping-amplifier, sample and hold, multiplexer) which is built immediately below it by using the remaining five active layers. The GEM and the drift electrode window are assembled directly over the chip so the ASIC itself becomes the pixelized anode of a MicroPattern Gas Detector. With this approach, for the first time, gas detectors have reached the level of i...

  5. ASIC Wafer Test System for the ATLAS Semiconductor Tracker Front-End Chip

    International Nuclear Information System (INIS)

    An ASIC wafer test system has been developed to provide comprehensive production screening of the ATLAS Semiconductor Tracker front-end chip (ABCD3T). The ABCD3T[1] features a 128-channel analog front-end, a digital pipeline, and communication circuitry, clocked at 40 MHz, which is the bunch crossing frequency at the LHC (Large Hadron Collider). The tester measures values and tolerance ranges of all critical IC parameters, including DC parameters, electronic noise, time resolution, clock levels and clock timing. The tester is controlled by an FPGA (ORCA3T) programmed to issue the input commands to the IC and to interpret the output data. This allows the high-speed wafer-level IC testing necessary to meet the production schedule. To characterize signal amplitudes and phase margins, the tester utilizes pin-driver, delay, and DAC chips, which control the amplitudes and delays of signals sent to the IC under test. Output signals from the IC under test go through window comparator chips to measure their levels. A probe card has been designed specifically to reduce pick-up noise that can affect the measurements. The system can operate at frequencies up to 100 MHz to study the speed limits of the digital circuitry before and after radiation damage. Testing requirements and design solutions are presented

  6. Sensor-based whole-arm obstacle avoidance utilizing ASIC technology

    Science.gov (United States)

    Wintenberg, A. L.; Ericson, M. N.; Babcock, S. M.; Armstrong, G. A.; Britton, C. L., Jr.; Butler, P. L.; Hamel, W. R.; Newport, D. F.

    Operation of manipulator systems in poorly defined work environments often presents a significant hazard to both the robotic assembly and the environment. In applications relating to the Environmental Restoration and Waste Management (ER&WM) Program, many of the environments are considered hazardous, both, in the structure and composition of the environment. Use of a sensing system that provides information to the manipulator control unit regarding obstacles in close proximity will provide protection against collisions. A hierarchical design and implementation of a whole-arm obstacle avoidance system is presented. The system is based on capacitive sensors configured as bracelets for proximity sensing. Each bracelet contains a number of sensor nodes and a processor for sensor node control and readout, and communications with a higher level host, common to all bracelets. The host controls the entire sensing network and communicates proximity information to the manipulator controller. The overall architecture of this system is discussed with detail on the individual system modules. Details of an application specific integrated circuit (ASIC) designed to implement the sensor node electronics are presented. Justifications for the general measurement methods and associated implementation are discussed. Additionally, the current state of development including measured data is presented.

  7. CLARO-CMOS, a very low power ASIC for fast photon counting with pixellated photodetectors

    Science.gov (United States)

    Carniti, P.; De Matteis, M.; Giachero, A.; Gotti, C.; Maino, M.; Pessina, G.

    2012-11-01

    The CLARO-CMOS is an application specific integrated circuit (ASIC) designed for fast photon counting with pixellated photodetectors such as multi-anode photomultiplier tubes (Ma-PMT), micro-channel plates (MCP), and silicon photomultipliers (SiPM). The first prototype has four channels, each with a charge sensitive amplifier with settable gain and a discriminator with settable threshold, providing fast hit information for each channel independently. The design was realized in a long-established, stable and inexpensive 0.35 μm CMOS technology, and provides outstanding performance in terms of speed and power dissipation. The prototype consumes less than 1 mW per channel at low rate, and less than 2 mW at an event rate of 10 MHz per channel. The recovery time after each pulse is less than 25 ns for input signals within a factor of 10 above threshold. Input referred RMS noise is about 7.7 ke- (1.2 fC) with an input capacitance of 3.3 pF. With this value of input capacitance a timing resolution down to 10 ps RMS was measured for pulser signals of a few million electrons, corresponding to the single photon response for these detectors.

  8. CLARO-CMOS, a very low power ASIC for fast photon counting with pixellated photodetectors

    CERN Document Server

    Carniti, Paolo

    2012-01-01

    The CLARO-CMOS is an application specific integrated circuit (ASIC) designed for fast photon counting with pixellated photodetectors such as multi-anode photomultiplier tubes (Ma-PMT), micro-channel plates (MCP), and silicon photomultipliers (SiPM). The first prototype has four channels, each with a charge sensitive amplifier with settable gain and a discriminator with settable threshold, providing fast hit information for each channel independently. The design was realized in a long-established, stable and inexpensive 0.35 um CMOS technology, and provides outstanding performance in terms of speed and power dissipation. The prototype consumes less than 1 mW per channel at low rate, and less than 2 mW at an event rate of 10 MHz per channel. The recovery time after each pulse is less than 25 ns for input signals within a factor of 10 above threshold. Input referred RMS noise is about 7.7 ke^- (1.2 fC) with an input capacitance of 3.3 pF. Thanks to the low noise and high speed, a timing resolution down to 10 ps ...

  9. An important step forward in continuous spectroscopic imaging of ionising radiations using ASICs

    Energy Technology Data Exchange (ETDEWEB)

    Fessler, P. [11 rue Rabelais, 92170 Vanves (France); Coffin, J. [Institut de Recherches Subatomiques, B.P. 28, 67037 Strasbourg (France); Eberle, H. [Institut de Recherches Subatomiques, B.P. 28, 67037 Strasbourg (France); Raad Iseli, C. de [Smart Silicon Systems SA, Ch. de la Graviere 6, CH-1007 Lausanne (Switzerland); Hilt, B. [Universite de Haute-Alsace, GRPHE, 61, rue Albert Camus, 68093 Mulhouse (France); Huss, D. [Universite de Haute-Alsace, GRPHE, 61, rue Albert Camus, 68093 Mulhouse (France); Krummenacher, F. [Smart Silicon Systems SA, Ch. de la Graviere 6, CH-1007 Lausanne (Switzerland); Lutz, J.R. [Institut de Recherches Subatomiques, B.P. 28, 67037 Strasbourg (France); Prevot, G. [Institut de Recherches Subatomiques, B.P. 28, 67037 Strasbourg (France); Renouprez, A. [Institut de Recherche sur la Catalyse, 2 Avenue Albert Einstein, 69626 Villeurbanne (France); Sigward, M.H. [Institut de Recherches Subatomiques, B.P. 28, 67037 Strasbourg (France); Schwaller, B. [Universite de Haute-Alsace, GRPHE, 61, rue Albert Camus, 68093 Mulhouse (France); Voltolini, C. [Institut de Recherches Subatomiques, B.P. 28, 67037 Strasbourg (France)

    1999-01-21

    Characterization results are given for an original ASIC allowing continuous acquisition of ionising radiation images in spectroscopic mode. Ionising radiation imaging in general and spectroscopic imaging in particular must primarily be guided by the attempt to decrease statistical noise, which requires detection systems designed to allow very high counting rates. Any source of dead time must therefore be avoided. Thus, the use of on-line corrections of the inevitable dispersion of characteristics between the large number of electronic channels of the detection system, shall be precluded. Without claiming to achieve ultimate noise levels, the work described is focused on how to prevent good individual acquisition channel noise performance from being totally destroyed by the dispersion between channels without introducing dead times. With this goal, we developed an automatic charge amplifier output voltage offset compensation system which operates regardless of the cause of the offset (detector or electronic). The main performances of the system are the following: the input equivalent noise charge is 190 e rms (input non connected, peaking time 500 ns), the highest gain is 255 mV/fC, the peaking time is adjustable between 200 ns and 2 {mu}s and the power consumption is 10 mW per channel. The agreement between experimental data and theoretical simulation results is excellent.

  10. Unity power factor converter

    Science.gov (United States)

    Wester, Gene W. (Inventor)

    1980-01-01

    A unity power factor converter capable of effecting either inversion (dc-to-dc) or rectification (ac-to-dc), and capable of providing bilateral power control from a DC source (or load) through an AC transmission line to a DC load (or source) for power flow in either direction, is comprised of comparators for comparing the AC current i with an AC signal i.sub.ref (or its phase inversion) derived from the AC ports to generate control signals to operate a switch control circuit for high speed switching to shape the AC current waveform to a sine waveform, and synchronize it in phase and frequency with the AC voltage at the AC ports, by selectively switching the connections to a series inductor as required to increase or decrease the current i.

  11. Heated catalytic converter

    Energy Technology Data Exchange (ETDEWEB)

    1994-09-01

    This article describes how the use of an auxiliary burner to heat the converter promptly can provide substantially decreased emission levels. While, in principle, there may well be solutions to decreasing warm-up phase hydrocarbon emissions, their production-level implementation is hindered by conflicting requirements, insufficiently mature technologies, and significant technical and financial restraints. The US, California, and the European Community are tightening emission standards for the transitional-low-, low-, and ultra-low-emission vehicles throughout the coming decade. The lead figure shows the fundamental possibilities for reducing harmful substances in exhaust emissions. While one can distinguish between measures taken within the engine (internal), and others outside it (external), it currently seems that only a combination of both will provide a suitable overall concept.

  12. Integrated power electronic converters and digital control

    CERN Document Server

    Emadi, Ali; Nie, Zhong

    2009-01-01

    Non-isolated DC-DC ConvertersBuck ConverterBoost ConverterBuck-Boost ConverterIsolated DC-DC ConvertersFlyback ConverterForward ConverterPush-Pull ConverterFull-Bridge ConverterHalf-Bridge ConverterPower Factor CorrectionConcept of PFCGeneral Classification of PFC CircuitsHigh Switching Frequency Topologies for PFCApplication of PFC in Advanced Motor DrivesIntegrated Switched-Mode Power ConvertersSwitched-Mode Power SuppliesThe Concept of Integrated ConverterDefinition of Integrated Switched-Mode Power Supplies (ISMPS)Boost-Type Integrated TopologiesGeneral Structure of Boost-Type Integrated T

  13. Advanced power electronics converters PWM converters processing AC voltages

    CERN Document Server

    dos Santos, Euzeli

    2014-01-01

    This book covers power electronics, in depth, by presenting the basic principles and application details, which can be used both as a textbook and reference book.  Introduces a new method to present power electronics converters called Power Blocks Geometry. Applicable for courses focusing on power electronics, power electronics converters, and advanced power converters. Offers a comprehensive set of simulation results to help understand the circuits presented throughout the book

  14. Impedance source power electronic converters

    CERN Document Server

    Liu, Yushan; Ge, Baoming; Blaabjerg, Frede; Ellabban, Omar; Loh, Poh Chiang

    2016-01-01

    Impedance Source Power Electronic Converters brings together state of the art knowledge and cutting edge techniques in various stages of research related to the ever more popular impedance source converters/inverters. Significant research efforts are underway to develop commercially viable and technically feasible, efficient and reliable power converters for renewable energy, electric transportation and for various industrial applications. This book provides a detailed understanding of the concepts, designs, controls, and application demonstrations of the impedance source converters/inverters. Key features: Comprehensive analysis of the impedance source converter/inverter topologies, including typical topologies and derived topologies. Fully explains the design and control techniques of impedance source converters/inverters, including hardware design and control parameter design for corresponding control methods. Presents the latest power conversion solutions that aim to advance the role of pow...

  15. Nanostructure Neutron Converter Layer Development

    Science.gov (United States)

    Park, Cheol (Inventor); Sauti, Godfrey (Inventor); Kang, Jin Ho (Inventor); Lowther, Sharon E. (Inventor); Thibeault, Sheila A. (Inventor); Bryant, Robert G. (Inventor)

    2016-01-01

    Methods for making a neutron converter layer are provided. The various embodiment methods enable the formation of a single layer neutron converter material. The single layer neutron converter material formed according to the various embodiments may have a high neutron absorption cross section, tailored resistivity providing a good electric field penetration with submicron particles, and a high secondary electron emission coefficient. In an embodiment method a neutron converter layer may be formed by sequential supercritical fluid metallization of a porous nanostructure aerogel or polyimide film. In another embodiment method a neutron converter layer may be formed by simultaneous supercritical fluid metallization of a porous nanostructure aerogel or polyimide film. In a further embodiment method a neutron converter layer may be formed by in-situ metalized aerogel nanostructure development.

  16. Venturini Method Based Matrix Converter

    Directory of Open Access Journals (Sweden)

    Derick Mathew

    2015-03-01

    Full Text Available Recently, matrix converter has received considerable interest as a viable alternative to the conventional ac-dc-ac converter. This direct ac-ac converter provides some attractive characteristics such as: four quadrant operation, absence of bulky dc-link electrolyte capacitors, clean input power characteristics. Due to the absence of dc link energy storage elements any disturbance in the input voltage will be immediately reflected to the output voltages. In this paper venturini method for matrix converter has been presented. Three phase sinusoidal symmetrical voltage or current can obtained .

  17. A thermochemical energy converter

    Energy Technology Data Exchange (ETDEWEB)

    Toyeguti, K.; Indzima, T.

    1982-08-09

    Mercury is used as the active mass of the anode in the converter and 0/sub 2/ is used as the active cathode material. The reaction of Mercury + 1/2 0/sub 2/-Hg0 occurs with a discharge. With heating to 500/sup 0/C the regeneration of the Mercury, Hg0 yields Mercury + 1/2 0/sub 2/, occurs. The device for performing the thermochenical conversion of energy contains an element body, an oxygen chamber, an oxygen electrode, a chamber with an alkaline liquid electrolyte, a separator, an auxiliary separator, an electrode and a chamber with the Mercury. The thermochemical reaction occurs in the reactor to which the Hg0 is transported along a pipe which has a refrigerator and a valve. The Mercury is fed into the element from a reservoir. The Mercury reduced in the reactor and in a reaction tower is fed into it through a closed cycle. The bellows is connected with the reactor by a pipe with a refrigerator. Through it the 0/sub 2/ goes in a closed cycle to the chamber. The current forming reactions are Hg + 20H-anion yields Hg0 + H/sub 2/0 + 2e and 1/2 0/sub 2/ + H/sub 2/0 + 2e yields 20H-anion. The voltage on the outleads of the element is approximately 0.3 volts.

  18. Systematic study of new types of Hamamatsu MPPCs read out with the NINO ASIC

    Science.gov (United States)

    Doroud, K.; Rodriguez, A.; Williams, M. C. S.; Yamamoto, K.; Zichichi, A.; Zuyeuski, R.

    2014-07-01

    Over the last decade there have been commercial TOF-PET scanners constructed using Photo-Multiplier Tubes (PMT) that have achieved ~ 500 ps FWHM Coincidence Time Resolution (CTR). A new device known as the Silicon PhotoMultiplier (SiPM) has the potential to overcome some of the limitations of the PMT. Therefore implementing a SiPM based TOF-PET scanner is of high interest. Recently Philips has introduced a TOF-PET scanner that uses digital Silicon PhotoMultipliers (d-SiPMs) which has a CTR of 350 ps. Here we will report on the timing performance of two Hamamatsu 3×3 mm2 analogue-SiPMs read out with the NINO ASIC: this is an ultra-fast amplifier/discriminator with a differential architecture. The differential architecture is very important since the single-ended readout uses the ground as the signal return; as the ground is also the reference level for the discriminators, the result is high crosstalk and degraded time resolution. However differential readout allows the scaling up from a single cell to a multi-cell device with no loss of time resolution; this becomes increasingly important for the highly segmented detectors that are being built today, both for particle and for medical instrumentation. We obtained excellent results for both the Single Photon Time Resolution (SPTR) and for the CTR using a LYSO crystal of 15 mm length. Such a crystal length has sufficient detection efficiency for 511 keV gammas to make an excellent PET device. The results presented here are proof that a TOF-PET detector with a CTR of 175 ps is indeed possible. This is the first step that defines the starting point of our SuperNINO project.

  19. Systematic study of new types of Hamamatsu MPPCs read out with the NINO ASIC

    Energy Technology Data Exchange (ETDEWEB)

    Doroud, K. [Museo Storico della Fisica e Centro Studi e Ricerche E. Fermi, Roma (Italy); Rodriguez, A. [CERN, Geneva (Switzerland); ICSC World Laboratory, Geneva (Switzerland); Williams, M.C.S., E-mail: crispin.williams@cern.ch [CERN, Geneva (Switzerland); INFN and Dipartimento di Fisica e Astronomia, Università di Bologna (Italy); Yamamoto, K. [Solid State Division, Hamamatsu Photonics K.K., Hamamatsu (Japan); Zichichi, A. [Museo Storico della Fisica e Centro Studi e Ricerche E. Fermi, Roma (Italy); CERN, Geneva (Switzerland); INFN and Dipartimento di Fisica e Astronomia, Università di Bologna (Italy); Zuyeuski, R. [CERN, Geneva (Switzerland); ICSC World Laboratory, Geneva (Switzerland)

    2014-07-01

    Over the last decade there have been commercial TOF-PET scanners constructed using Photo-Multiplier Tubes (PMT) that have achieved ∼500ps FWHM Coincidence Time Resolution (CTR). A new device known as the Silicon PhotoMultiplier (SiPM) has the potential to overcome some of the limitations of the PMT. Therefore implementing a SiPM based TOF-PET scanner is of high interest. Recently Philips has introduced a TOF-PET scanner that uses digital Silicon PhotoMultipliers (d-SiPMs) which has a CTR of 350 ps. Here we will report on the timing performance of two Hamamatsu 3×3 mm{sup 2} analogue-SiPMs read out with the NINO ASIC: this is an ultra-fast amplifier/discriminator with a differential architecture. The differential architecture is very important since the single-ended readout uses the ground as the signal return; as the ground is also the reference level for the discriminators, the result is high crosstalk and degraded time resolution. However differential readout allows the scaling up from a single cell to a multi-cell device with no loss of time resolution; this becomes increasingly important for the highly segmented detectors that are being built today, both for particle and for medical instrumentation. We obtained excellent results for both the Single Photon Time Resolution (SPTR) and for the CTR using a LYSO crystal of 15 mm length. Such a crystal length has sufficient detection efficiency for 511 keV gammas to make an excellent PET device. The results presented here are proof that a TOF-PET detector with a CTR of 175 ps is indeed possible. This is the first step that defines the starting point of our SuperNINO project.

  20. The charge pump PLL clock generator designed for the 1.56 ns bin size time-to-digital converter pixel array of the Timepix3 readout ASIC

    CERN Document Server

    Fu, Y et al.

    2014-01-01

    Timepix3 is a newly developed pixel readout chip which is expected to be operated in a wide range of gaseous and silicon detectors. It is made of 256×256 pixels organized in a square pixel-array with 55 µm pitch. Oscillators running at 640 MHz are distributed across the pixel-array and allow for a highly accurate measurement of the arrival time of a hit. This paper concentrates on a low-jitter phase locked loop (PLL) that is located in the chip periphery. This PLL provides a control voltage which regulates the actual frequency of the individual oscillators, allowing for compensation of process, voltage, and temperature variations.

  1. Detector Control and Data Acquisition for the Wide-Field Infrared Survey Telescope (WFIRST) with a Custom ASIC

    Science.gov (United States)

    Smith, Brian S.; Loose, Markus; Alkire, Greg; Joshi, Atul; Kelly, Daniel; Siskind, Eric; Rossetti, Dino; Mah, Jonathan; Cheng, Edward; Miko, Laddawan; Luppino, Gerard; Culver, Harry; Wollack, Edward; Content, David

    2016-01-01

    The Wide-Field Infrared Survey Telescope (WFIRST) will have the largest near-IR focal plane ever flown by NASA, a total of 18 4K x 4K devices. The project has adopted a system-level approach to detector control and data acquisition where 1) control and processing intelligence is pushed into components closer to the detector to maximize signal integrity, 2) functions are performed at the highest allowable temperatures, and 3) the electronics are designed to ensure that the intrinsic detector noise is the limiting factor for system performance. For WFIRST, the detector arrays operate at 90 to 100 K, the detector control and data acquisition functions are performed by a custom ASIC at 150 to 180 K, and the main data processing electronics are at the ambient temperature of the spacecraft, notionally approx.300 K. The new ASIC is the main interface between the cryogenic detectors and the warm instrument electronics. Its single-chip design provides basic clocking for most types of hybrid detectors with CMOS ROICs. It includes a flexible but simple-to-program sequencer, with the option of microprocessor control for more elaborate readout schemes that may be data-dependent. All analog biases, digital clocks, and analog-to-digital conversion functions are incorporated and are connected to the nearby detectors with a short cable that can provide thermal isolation. The interface to the warm electronics is simple and robust through multiple LVDS channels. It also includes features that support parallel operation of multiple ASICs to control detectors that may have more capability or requirements than can be supported by a single chip.

  2. Irradiation tests of ROHM 0.35um ASIC and Actel Anti-fuse FPGA for the ATLAS Muon Endcap Level-1 Trigger System

    CERN Document Server

    Ichimiya, R; Arai, Y; Ikeno, M; Sasaki, O; Ohshita, H; Takada, N; Hane, Y; Hasuko, K; Nomoto, H; Sakamoto, H; Shibuya, K; Takemoto, T; Fukunaga, C; Toshima, K; Sakuma, T; 10th Workshop on Electronics for LHC and Future Experiments

    2004-01-01

    In order to implement a level-1 trigger logic in an efficient manner from timing and space consumption point of view, application specific IC chips (ASIC) as well as FPGA ones are vitally used in the ATLAS muon end-cap level-1 trigger system. Various subsidiary logics are implemented in FPGAs while the core trigger logic is implemented in ASICs. These components will suffer for ten years the radiation of approximately 100Gy of total ionizing dose (TID) and a hadron fluence of 2x10^10hadrons/cm^2, which will cause single event upset (SEU) or single event latch up (SEL). We intend to use Rohm 0.35um gate width CMOS technology for ASIC and Actel anti-fuse based FPGA. In this presentation we report the result of irradiation test of devices made with these technologies and discuss validity of them to use in the system.

  3. Conception and test of an integrated circuit (ASIC): application to multiwire chambers and photomultipliers of the GRAAL experience; Conception et test d`un circuit integre (ASIC): application aux chambres multifils et aux photomultiplicateurs de l`experience GRAAL

    Energy Technology Data Exchange (ETDEWEB)

    Bugnet, H.

    1995-11-21

    The nuclear physics project GRAAL (GRenoble Anneau Accelerateur Laser) located at the European Synchrotron Radiation Facility (ESRF) in Grenoble produces a high energy photon beam with a maximum energy of 1.5 GeV. This gamma beam is obtained by Compton backscattering and can be polarized easily. It permits to probe, in an original way, the structure of the nucleon. The associated detector system includes multiwire proportional chambers and scintillator hodoscopes. A kit of six ASICs (Application Specific Integrated Circuit) has been developed and used for the signal processing and data conditioning up to the level of the data acquisition. This integrated electronics can be mounted right on the detectors. Obvious advantages, due to the reduction of the length of the wires and the number of connections, are an improvement of the signal quality and an increase of the reliability. The Wire Processor (WP), ASIC designed and tested during this thesis, treats the signals from the chamber wires and the photomultipliers. In one chip, there are two identical channels permitting the amplification, the amplitude discrimination, the generation of a programmable delay and the writing in a two state memory in case of coincidence with an external strobe signal. The measurement of the multiwire chamber efficiency demonstrates the functioning of the WP, the data conditioning electronics, the data acquisition and the chamber itself. (author). 62 refs., 111 figs., 13 tabs.

  4. Radiation tolerant power converter controls

    CERN Document Server

    Todd, B; King, Q; Uznanski, S

    2012-01-01

    The Large Hadron Collider (LHC) at the European Organisation for Nuclear Research (CERN) is the world's most powerful particle collider. The LHC has several thousand magnets, both warm and super-conducting, which are supplied with current by power converters. Each converter is controlled by a purpose-built electronic module called a Function Generator Controller (FGC). The FGC allows remote control of the power converter and forms the central part of a closed-loop control system where the power converter voltage is set, based on the converter output current and magnet-circuit characteristics. Some power converters and FGCs are located in areas which are exposed to beam-induced radiation. There are numerous radiation induced effects, some of which lead to a loss of control of the power converter, having a direct impact upon the accelerator's availability. Following the first long shut down (LS1), the LHC will be able to run with higher intensity beams and higher beam energy. This is expected to lead to signifi...

  5. PWM DC/DC Converter

    OpenAIRE

    Chen, Juan

    2008-01-01

    This report is the result of a Master Thesis work done at Seaward Electronics Inc. in Beijing, China from June to December in 2007. The main goal for this thesis is to verify and improve the performance of Honey-PWM DC-DC converter, which has been fabricated by a standard 0.6um CMOS processes. The project was started with studying of Buck converter structure. After the understanding of the converter structure, the project goes in to the analyses phase for each sub-cells, including the theory,...

  6. Histone Modifications in a Mouse Model of Early Adversities and Panic Disorder: Role for Asic1 and Neurodevelopmental Genes.

    Science.gov (United States)

    Cittaro, Davide; Lampis, Valentina; Luchetti, Alessandra; Coccurello, Roberto; Guffanti, Alessandro; Felsani, Armando; Moles, Anna; Stupka, Elia; D' Amato, Francesca R; Battaglia, Marco

    2016-01-01

    Hyperventilation following transient, CO2-induced acidosis is ubiquitous in mammals and heritable. In humans, respiratory and emotional hypersensitivity to CO2 marks separation anxiety and panic disorders, and is enhanced by early-life adversities. Mice exposed to the repeated cross-fostering paradigm (RCF) of interference with maternal environment show heightened separation anxiety and hyperventilation to 6% CO2-enriched air. Gene-environment interactions affect CO2 hypersensitivity in both humans and mice. We therefore hypothesised that epigenetic modifications and increased expression of genes involved in pH-detection could explain these relationships. Medullae oblongata of RCF- and normally-reared female outbred mice were assessed by ChIP-seq for H3Ac, H3K4me3, H3K27me3 histone modifications, and by SAGE for differential gene expression. Integration of multiple experiments by network analysis revealed an active component of 148 genes pointing to the mTOR signalling pathway and nociception. Among these genes, Asic1 showed heightened mRNA expression, coherent with RCF-mice's respiratory hypersensitivity to CO2 and altered nociception. Functional enrichment and mRNA transcript analyses yielded a consistent picture of enhancement for several genes affecting chemoception, neurodevelopment, and emotionality. Particularly, results with Asic1 support recent human findings with panic and CO2 responses, and provide new perspectives on how early adversities and genes interplay to affect key components of panic and related disorders. PMID:27121911

  7. Multi-time-over-threshold technique for photomultiplier signal processing: Description and characterization of the SCOTT ASIC

    Energy Technology Data Exchange (ETDEWEB)

    Ferry, S. [CEA/Irfu/SPP, Gif-sur-Yvette (France); Guilloux, F., E-mail: fabrice.guilloux@cea.fr [CEA/Irfu/SEDI, Gif-sur-Yvette (France); Anvar, S.; Chateau, F.; Delagnes, E.; Gautard, V.; Louis, F.; Monmarthe, E.; Le Provost, H. [CEA/Irfu/SEDI, Gif-sur-Yvette (France); Russo, S. [Dipartimento di Scienze Fisiche Universita di Napoli, Napoli (Italy); Schuller, J.-P.; Stolarczyk, Th.; Vallage, B. [CEA/Irfu/SPP, Gif-sur-Yvette (France); Zonca, E. [CEA/Irfu/SEDI, Gif-sur-Yvette (France)

    2012-12-11

    KM3NeT aims to build a cubic-kilometer scale neutrino telescope in the Mediterranean Sea based on a 3D array of photomultiplier tubes. A dedicated ASIC, named SCOTT, has been developed for the readout electronics of the PMTs: it uses up to 16 adjustable thresholds to digitize the signals with the multi-time-over-threshold technique. Digital outputs of discriminators feed a circular sampling memory and a 'first in first out' digital memory for derandomization. At the end of the data processing, the ASIC produces a digital waveform sampled at 800 MHz. A specific study was carried out to process PMT data and has showed that five specifically chosen thresholds are suited to reach the required timing precision. A dedicated method based on the duration of the signal over a given threshold allows an equivalent timing precision at any charge. A charge estimator using the information from the thresholds allows a charge determination within less than 20% up to 60 pe.

  8. An efficient ASIC implementation of 16-channel on-line recursive ICA processor for real-time EEG system.

    Science.gov (United States)

    Fang, Wai-Chi; Huang, Kuan-Ju; Chou, Chia-Ching; Chang, Jui-Chung; Cauwenberghs, Gert; Jung, Tzyy-Ping

    2014-01-01

    This is a proposal for an efficient very-large-scale integration (VLSI) design, 16-channel on-line recursive independent component analysis (ORICA) processor ASIC for real-time EEG system, implemented with TSMC 40 nm CMOS technology. ORICA is appropriate to be used in real-time EEG system to separate artifacts because of its highly efficient and real-time process features. The proposed ORICA processor is composed of an ORICA processing unit and a singular value decomposition (SVD) processing unit. Compared with previous work [1], this proposed ORICA processor has enhanced effectiveness and reduced hardware complexity by utilizing a deeper pipeline architecture, shared arithmetic processing unit, and shared registers. The 16-channel random signals which contain 8-channel super-Gaussian and 8-channel sub-Gaussian components are used to analyze the dependence of the source components, and the average correlation coefficient is 0.95452 between the original source signals and extracted ORICA signals. Finally, the proposed ORICA processor ASIC is implemented with TSMC 40 nm CMOS technology, and it consumes 15.72 mW at 100 MHz operating frequency.

  9. Time-to-digital converters

    CERN Document Server

    Henzler, Stephan

    2010-01-01

    This text covers the fundamentals of time-to-digital converters on analog and digital conversion principles. It includes a theoretical investigation into quantization, linearity, noise and variability, and it details a range of advanced TDC architectures.

  10. Laser system with wavelength converter

    DEFF Research Database (Denmark)

    2012-01-01

    The present invention relates to an apparatus comprising a diode laser (10) providing radiation in a first wavelength interval, a radiation conversion unit (12) having an input and an output, the radiation converter configured to receive the radiation in the first wavelength interval from the diode...... laser at the input, the radiation conversion unit configured to convert the radiation in the first wavelength interval to radiation in a second wavelength interval and the output configured to output the converted radiation, the second wavelength interval having one end point outside the first...... wavelength interval. Further, the invention relates to a method of optically pumping a target laser (14) in a laser system, the laser system comprising a laser source providing radiation at a first frequency, the laser source being optically connected to an input of a frequency converter, the frequency...

  11. PHASE CONVERTER OF COMPOSING DISPLACEMENT

    OpenAIRE

    SMIRNOV YU.S.; Lysov, A. N.; E.V. Yurasova; SAFRONOV V.V.; VSTAVSKAYA E.V.

    2016-01-01

    Minimax strategy of mechatronic converters efficiency improving relative to error decrease with velocity increase at the same time provides common dataware level rise. The analysis of usage possibilities of different type position transducers (PT) gives the advantages of resolvers. The subsequent processing of their output signals is performed by “Resolver-to-Digit” Converter (RDC) which provides displacement digital equivalent and digital or analog signals specifying its velocity and acceler...

  12. Boron nitride converted carbon fiber

    Energy Technology Data Exchange (ETDEWEB)

    Rousseas, Michael; Mickelson, William; Zettl, Alexander K.

    2016-04-05

    This disclosure provides systems, methods, and apparatus related to boron nitride converted carbon fiber. In one aspect, a method may include the operations of providing boron oxide and carbon fiber, heating the boron oxide to melt the boron oxide and heating the carbon fiber, mixing a nitrogen-containing gas with boron oxide vapor from molten boron oxide, and converting at least a portion of the carbon fiber to boron nitride.

  13. Transformerless dc-Isolated Converter

    Science.gov (United States)

    Rippel, Wally E.

    1987-01-01

    Efficient voltage converter employs capacitive instead of transformer coupling to provide dc isolation. Offers buck/boost operation, minimal filtering, and low parts count, with possible application in photovoltaic power inverters, power supplies and battery charges. In photovoltaic inverter circuit with transformerless converter, Q2, Q3, Q4, and Q5 form line-commutated inverter. Switching losses and stresses nil because switching performed when current is zero.

  14. Current status of converter steelmaking

    Energy Technology Data Exchange (ETDEWEB)

    Oghbasialasie, H.; Holappa, L.

    1995-12-31

    This literature work is mainly focusing on the mechanisms of modern converter steelmaking and related with the evaluation of converter technology applied during the last decades and further to the future. The history of steelmaking has been briefly reviewed from bloomeries and early-steelmaking processes to the progress of modern converter process. The pneumatic converter processes were developed in the 1850`s and thereafter the basis for the rapid growth of steel industries was established for the next 100 years. The world production of steel has not continuously grown but fluctuating quite much. It reached 723 Mt in 1994. The production is believed to grow the forecast for the year 2003 being approximately 800 Mt. Electric arc furnace production is estimated to reach 280 Mt by 2003, and BOFIOH will reach 520 Mt by 2003. The current status of the converter steelmaking process is briefly described both on its theoretical bases and practical technological progresses. Developments which significantly improve the process are briefly discussed. Several more recent developments such as combined oxygen blowing process, increased scrap melting, post combustion and hot metal pretreatment are discussed. The future progress will be in further development of these process characteristics as well as in eventual emerging of the continuous converter process. (author)

  15. Development of a compact radiation-hardened low-noise front-end readout ASIC for CZT-based hard X-ray imager

    Energy Technology Data Exchange (ETDEWEB)

    Gao, W., E-mail: gaowu@nwpu.edu.cn; Gan, B.; Li, X.; Wei, T.; Gao, D.; Hu, Y.

    2015-04-21

    In this paper, we present the development and performances of a radiation-hardened front-end readout application-specific integrated circuit (ASIC) dedicated to CZT detectors for a hard X-ray imager in space applications. The readout channel consists of a charge sensitive amplifier (CSA), a CR-RC shaper, a fast shaper, a discriminator and a driving buffer. With the additional digital filtering, the readout channel can achieve very low noise performances and low power dissipation. An eight-channel prototype ASIC is designed and fabricated in 0.35 μm CMOS process. The energy range of the detected X-rays is evaluated as 1.45 keV to 281 keV. The gain is larger than 100 mV/fC. The equivalent noise charge (ENC) of the ASIC is 53 e{sup −} at zero farad plus 10 e{sup −} per picofarad. The power dissipation is less than 4.4 mW/channel. Through the measurement with a CZT detector, the energy resolution is less than 3.45 keV (FWHM) under the irradiation of the radioactive source {sup 241}Am. The radiation effect experiments indicate that the proposed ASIC can resist the total ionization dose (TID) irradiation of higher than 200 krad (Si)

  16. The VFAT3-Comm-Port: a complete communication port for front-end ASICs intended for use within the high luminosity radiation environments of the LHC

    International Nuclear Information System (INIS)

    This paper presents the VFAT3 Comm-Port (V3CP), which offers a single port for all communication to and from a front-end ASIC within the HL-LHC environment. This includes synchronization to the LHC clock, slow control communication, the execution of fast control commands and the readout of data

  17. Development of a compact radiation-hardened low-noise front-end readout ASIC for CZT-based hard X-ray imager

    International Nuclear Information System (INIS)

    In this paper, we present the development and performances of a radiation-hardened front-end readout application-specific integrated circuit (ASIC) dedicated to CZT detectors for a hard X-ray imager in space applications. The readout channel consists of a charge sensitive amplifier (CSA), a CR-RC shaper, a fast shaper, a discriminator and a driving buffer. With the additional digital filtering, the readout channel can achieve very low noise performances and low power dissipation. An eight-channel prototype ASIC is designed and fabricated in 0.35 μm CMOS process. The energy range of the detected X-rays is evaluated as 1.45 keV to 281 keV. The gain is larger than 100 mV/fC. The equivalent noise charge (ENC) of the ASIC is 53 e− at zero farad plus 10 e− per picofarad. The power dissipation is less than 4.4 mW/channel. Through the measurement with a CZT detector, the energy resolution is less than 3.45 keV (FWHM) under the irradiation of the radioactive source 241Am. The radiation effect experiments indicate that the proposed ASIC can resist the total ionization dose (TID) irradiation of higher than 200 krad (Si)

  18. A 75 ps rms time resolution BiCMOS time to digital converter optimized for high rate imaging detectors

    CERN Document Server

    Hervé, C

    2002-01-01

    This paper presents an integrated time to digital converter (TDC) with a bin size adjustable in the range of 125 to 175 ps and a differential nonlinearity of +-0.3%. The TDC has four channels. Its architecture has been optimized for the readout of imaging detectors in use at Synchrotron Radiation facilities. In particular, a built-in logic flags piled-up events. Multi-hit patterns are also supported for other applications. Time measurements are extracted off chip at the maximum throughput of 40 MHz. The dynamic range is 14 bits. It has been fabricated in 0.8 mu m BiCMOS technology. Time critical inputs are PECL compatible whereas other signals are CMOS compatible. A second application specific integrated circuit (ASIC) has been developed which translates NIM electrical levels to PECL ones. Both circuits are used to assemble board level TDCs complying with industry standards like VME, NIM and PCI.

  19. The TDCpix readout ASIC: A 75 ps resolution timing front-end for the NA62 Gigatracker hybrid pixel detector

    Energy Technology Data Exchange (ETDEWEB)

    Kluge, A., E-mail: alexander.kluge@cern.ch; Aglieri Rinella, G.; Bonacini, S.; Jarron, P.; Kaplon, J.; Morel, M.; Noy, M.; Perktold, L.; Poltorak, K.

    2013-12-21

    The TDCpix is a novel pixel readout ASIC for the NA62 Gigatracker detector. NA62 is a new experiment being installed at the CERN Super Proton Synchrotron. Its Gigatracker detector shall provide on-beam tracking and time stamping of individual particles with a time resolution of 150 ps rms. It will consist of three tracking stations, each with one hybrid pixel sensor. The peak flow of particles crossing the detector modules reaches 1.27 MHz/mm{sup 2} for a total rate of about 0.75 GHz. Ten TDCpix chips will be bump-bonded to every silicon pixel sensor. Each chip shall perform time stamping of 100 M particle hits per second with a detection efficiency above 99% and a timing accuracy better than 200 ps rms for an overall three-station-setup time resolution of better than 150 ps. The TDCpix chip has been designed in a 130 nm CMOS technology. It will feature 45×40 square pixels of 300×300μm{sup 2} and a complex End of Column peripheral region including an array of TDCs based on DLLs, four high speed serializers, a low-jitter PLL, readout and control circuits. This contribution will describe the complete design of the final TDCpix ASIC. It will discuss design choices, the challenges faced and some of the lessons learned. Furthermore, experimental results from the testing of circuit prototypes will be presented. These demonstrate the achievement of key performance figures such as a time resolution of the processing chain of 75 ps rms with a laser sent to the center of the pixel and the capability of time stamping charged particles with an overall resolution below 200 ps rms. -- Highlights: • Feasibility demonstration of a silicon pixel detector with sub-ns time tagging capability. • Demonstrator detector assembly with a time resolution of 75 ps RMS with laser charge injection; 170 ps RMS with particle beam. • Design of trigger-less TDCpix ASIC with 1800 pixels, 720 TDC channels and 4 3.2 Gbit/s serializers.

  20. Modeling of asymmetrical boost converters

    Directory of Open Access Journals (Sweden)

    Eliana Isabel Arango Zuluaga

    2014-03-01

    Full Text Available The asymmetrical interleaved dual boost (AIDB is a fifth-order DC/DC converter designed to interface photovoltaic (PV panels. The AIDB produces small current harmonics to the PV panels, reducing the power losses caused by the converter operation. Moreover, the AIDB provides a large voltage conversion ratio, which is required to step-up the PV voltage to the large dc-link voltage used in grid-connected inverters. To reject irradiance and load disturbances, the AIDB must be operated in a closed-loop and a dynamic model is required. Given that the AIDB converter operates in Discontinuous Conduction Mode (DCM, classical modeling approaches based on Continuous Conduction Mode (CCM are not valid. Moreover, classical DCM modeling techniques are not suitable for the AIDB converter. Therefore, this paper develops a novel mathematical model for the AIDB converter, which is suitable for control-pur-poses. The proposed model is based on the calculation of a diode current that is typically disregarded. Moreover, because the traditional correction to the second duty cycle reported in literature is not effective, a new equation is designed. The model accuracy is contrasted with circuital simulations in time and frequency domains, obtaining satisfactory results. Finally, the usefulness of the model in control applications is illustrated with an application example.

  1. Increasing of Reliability of Converter

    Directory of Open Access Journals (Sweden)

    Trebuňa, F.

    2006-01-01

    Full Text Available The innovative activities in steel production invoke exploitation of new machines with the higher production capacity and productivity of labor. The paper deals with deformation and stress analysis of carrying parts of converter pedestal on the base of which the proposals and supporting measures were made that had the aim to increase reliability of the converter during steel production. This was achieved by lifespan prolongation of anchor and connecting bolts of converter pedestal, by change of stiffness of connected elements as well as by correction of nuts of bolted connections. The realization of structural changes decreased loading amplitudes and consequently the vibrations of pedestal. Solution was verified by numerical and experimental procedures of mechanics.

  2. Post combustion in converter steelmaking

    Energy Technology Data Exchange (ETDEWEB)

    Oghbasilasie, H.; Holappa, L.

    1997-12-31

    The purpose of this work is to study the fundamentals of post combustion and the effect of different process parameters on the post combustion ratio (PCR) and heat transfer efficiency (HTE) in converter steelmaking process. The PCR and HTE have been determined under normal operating conditions. Trials assessed the effect of lance height, vessel volume, foaming slag and pellet additions on PCR and HTE. Based on enthalpy considerations, post combustion of CO gas is regarded as one of the most effective means of increasing the heat supply to the BOP. The thermodynamic study of gas-metal-slag reactions gives the limiting conditions for post combustion inside the converter reactor. Different process parameters influencing both thermodynamic equilibria and kinetic conditions can greatly affect the post combustion ratio. Different features of converter processes as well smelting reduction processes utilizing post combustion have been reviewed. (orig.) SULA 2 Research Programme; 26 refs.

  3. Developments of gamma-ray imagers using CdTe semiconductors based on the analog ASIC technology

    International Nuclear Information System (INIS)

    Cadmium Telluride (CdTe) is one of the most promising semiconductor materials for hard X-ray and gamma-ray detection because of the high detection efficiency, and of the good energy resolution. Moreover, CdTe detectors with Schottky junction work as diode detectors, and show superior energy resolution. Based on the CdTe diode devices, we have developed CdTe pixel/strip imagers, and also realized a Si/CdTe Compton camera. These devices will be used for the Hard X-ray Imager (HXI) and the Soft Gamma-ray Detector (SGD) onboard ASTRO-H X-ray satellite to be launched in 2015. These developments are briefly reported in this article. We also describe our recent development of low-noise analog readout ASICs to be used for future development of CdTe gamma-ray imagers. (author)

  4. The bile acid-sensitive ion channel (BASIC), the ignored cousin of ASICs and ENaC.

    Science.gov (United States)

    Wiemuth, Dominik; Assmann, Marc; Gründer, Stefan

    2014-01-01

    The DEG/ENaC gene family of ion channels is characterized by a high degree of structural similarity and an equally high degree of diversity concerning the physiological function. In humans and rodents, the DEG/ENaC family comprises 2 main subgroups: the subunits of the epithelial Na(+) channel (ENaC) and the subunits of the acid sensing ion channels (ASICs). The bile acid-sensitive channel (BASIC), previously known as BLINaC or INaC, represents a third subgroup within the DEG/ENaC family. Although BASIC was identified more than a decade ago, very little is known about its physiological function. Recent progress in the characterization of this neglected member of the DEG/ENaC family, which is summarized in this focused review, includes the discovery of surprising species differences, its pharmacological characterization, and the identification of bile acids as putative natural activators.

  5. A wide dynamic range multi-channel preamplifier/shaper ASIC family for universal low power applications

    CERN Document Server

    Baturitsky, M A; Tchekhovski, V A; Zamiatin, N I

    2003-01-01

    A universal ASIC family for intermediate energy physics detectors has been designed using a bipolar/JFET technology. The family consists of two 8-channel charge-sensitive preamplifiers (CSP) ZENIT-A2, ZENIT-A3 and a shaper ZENIT-B. The values of switched gain of both CSPs are 80 and 240 mV/pC for ZENIT-A2 and 500 and 1000 mV/pC for ZENIT-A3 with channel-to-channel non-identity not more than +-5%. The CSPs can operate with input capacitance up to 300 pF for low gain and 150 pF for high gain mode. The input signal dynamic range of the shaper is matched to the outputs of both CSPs. The shaper has fast and slow outputs. The CSPs have a power consumption of 13 mW/channel; the shaper of 44 mW/channel.

  6. SENSROC4: An Multichannel Low-Noise Front-End Readout ASIC Dedicated to CZT Detectors for PET Imaging

    International Nuclear Information System (INIS)

    In this paper, we present the design of a novel low-noise front-end readout application-specific integrated circuit (ASIC) for our small animal PET systems which objective is to achieve the following performances, the spatial resolution of 1 mm3, the detection efficiency of 15 % and the time resolution of 1 ns. A cascade amplifier based on the PMOS input transistor is selected to realize the charge-sensitive amplifier (CSA) for the sake of good noise performances. The output of the CSA is split into two branches. One is connected to a slow shaper for energy measurements. The other is connected to a fast shaper for time acquisition. A novel monostable circuit is designed to adjust the time delay of the trigger signals so that the peak value of the shaped voltages can be sampled and stored. Based on the above techniques, an eight-channel front-end readout prototype chip is designed and implemented in 0.35 μm CMOS process. The die size is 2.286 mm x 2.282 mm. The input range of the ASIC is from 2000 e- to 180000 e-, reflecting to the energy of the gamma ray from 11.2 keV to 1 MeV. The gain of the readout channel is 65 V/pC. The best test result of ENC is 86.5 e- at zero farad plus 9.3 e- per pico-farad. The nonlinearity is less than 3 %. The crosstalk is less than 2 %. The power dissipation is about 9 mW/channel (authors)

  7. Converting accounts receivable into cash.

    Science.gov (United States)

    Folk, M D; Roest, P R

    1995-09-01

    In recent years, increasing numbers of healthcare providers have converted their accounts receivable into cash through a process called securitization. This practice has gained popularity because it provides a means to raise capital necessary to healthcare organizations. Although securitization transactions can be complex, they may provide increased financial flexibility to providers as they prepare for continuing change in the healthcare industry. PMID:10145096

  8. Parametric study of laser photovoltaic energy converters

    Science.gov (United States)

    Walker, G. H.; Heinbockel, J. H.

    1987-01-01

    Photovoltaic converters are of interest for converting laser power to electrical power in a space-based laser power system. This paper describes a model for photovoltaic laser converters and the application of this model to a neodymium laser silicon photovoltaic converter system. A parametric study which defines the sensitivity of the photovoltaic parameters is described. An optimized silicon photovoltaic converter has an efficiency greater than 50 percent for 1000 W/sq cm of neodymium laser radiation.

  9. Reaching a few picosecond timing precision with the 16-channel digitizer and timestamper SAMPIC ASIC

    Energy Technology Data Exchange (ETDEWEB)

    Delagnes, E., E-mail: eric.delagnes@cea.fr [CEA/IRFU/SEDI, Saclay (France); Breton, D. [Laboratoire de L’accélérateur Linéaire from CNRS/IN2P3, Centre scientifique d’Orsay, Bâtiment 200, 91898, Orsay, Cedex (France); Grabas, H. [CEA/IRFU/SEDI, Saclay (France); Maalmi, J.; Rusquart, P. [Laboratoire de L’accélérateur Linéaire from CNRS/IN2P3, Centre scientifique d’Orsay, Bâtiment 200, 91898, Orsay, Cedex (France)

    2015-07-01

    SAMPIC is a Time and Waveform to Digital Converter (TWDC) multichannel chip. It integrates 16 channels each including DLL-based TDC providing a raw time associated with an ultra-fast analog memory sampling the signal used for precise timing measurements as well as other parameters of the pulse. Every channel also integrates a discriminator that can trigger it independently or participate to a more complex trigger. After triggering, the analog samples are digitized by on-chip ADCs and are sent serially to the acquisition. The paper describes the architecture of SAMPIC and reports the main performance measured on the first prototype chip with a focus on timing resolution in the range of 15 ps RMS using raw data improved to less than 5 ps RMS after a simple calibration.

  10. Development of Formulations for a-SiC and Manganese CMP and Post-CMP Cleaning of Cobalt

    Science.gov (United States)

    Lagudu, Uma Rames Krishna

    We have investigated the chemical mechanical polishing (CMP) of amorphous SiC (a-SiC) and Mn and Post CMP cleaning of cobalt for various device applications. During the manufacture of copper interconnects using the damascene process the polishing of copper is followed by the polishing of the barrier material (Co, Mn, Ru and their alloys) and its post CMP cleaning. This is followed by the a-SiC hard mask CMP. Silicon carbide thin films, though of widespread use in microelectronic engineering, are difficult to process by CMP because of their hardness and chemical inertness. The earlier part of the SiC work discusses the development of slurries based on silica abrasives that resulted in high a-SiC removal rates (RRs). The ionic strength of the silica dispersion was found to play a significant role in enhancing material removal rate, while also providing very good post-polish surface-smoothness. For example, the addition of 50 mM potassium nitrate to a pH 8 aqueous slurry consisting of 10 wt % of silica abrasives and 1.47 M hydrogen peroxide increased the RR from about 150 nm/h to about 2100 nm/h. The role of ionic strength in obtaining such high RRs was investigated using surface zeta-potentials measurements and X-ray photoelectron spectroscopy (XPS). Evidently, hydrogen peroxide promoted the oxidation of Si and C to form weakly adhered species that were subsequently removed by the abrasive action of the silica particles. The effect of potassium nitrate in increasing material removal is attributed to the reduction in the electrostatic repulsion between the abrasive particles and the SiC surface because of screening of surface charges by the added electrolyte. We also show that transition metal compounds when used as additives to silica dispersions enhance a-SiC removal rates (RRs). Silica slurries containing potassium permanganate gave RRs as high as 2000 nm/h at pH 4. Addition of copper sulfate to this slurry further enhanced the RRs to ˜3500 nm/h at pH 6

  11. Vibration converter with magnetic levitation

    Science.gov (United States)

    Gladilin, A. V.; Pirogov, V. A.; Golyamina, I. P.; Kulaev, U. V.; Kurbatov, P. A.; Kurbatova, E. P.

    2015-05-01

    The paper presents a mathematical model, the results of computational and theoretical research, and the feasibility of creating a vibration converter with full magnetic levitation in the suspension of a high-temperature superconductor (HTSC). The axial and radial stability of the active part of the converter is provided by the interaction of the magnetic field of ring-shaped permanent magnets and a hollow cylinder made of the ceramic HTSC material. The force is created by a system of current-carrying coils whose magnetic field is polarized by permanent magnets and interacts with induced currents in the superconducting cylinder. The case of transition to the superconducting state of HTSC material in the field of the permanent magnets (FC mode) is considered. The data confirm the outlook for the proposed technical solutions.

  12. Photoelectric converters with quantum coherence

    Science.gov (United States)

    Su, Shan-He; Sun, Chang-Pu; Li, Sheng-Wen; Chen, Jin-Can

    2016-05-01

    Photon impingement is capable of liberating electrons in electronic devices and driving the electron flux from the lower chemical potential to higher chemical potential. Previous studies hinted that the thermodynamic efficiency of a nanosized photoelectric converter at maximum power is bounded by the Curzon-Ahlborn efficiency ηCA. In this study, we apply quantum effects to design a photoelectric converter based on a three-level quantum dot (QD) interacting with fermionic baths and photons. We show that, by adopting a pair of suitable degenerate states, quantum coherences induced by the couplings of QDs to sunlight and fermion baths can coexist steadily in nanoelectronic systems. Our analysis indicates that the efficiency at maximum power is no longer limited to ηCA through manipulation of carefully controlled quantum coherences.

  13. Reducing catalytic converter pressure loss

    Energy Technology Data Exchange (ETDEWEB)

    NONE

    1996-06-01

    This article examines why approximately 30--40% of total exhaust-system pressure loss occurs in the catalytic converter and what can be done to reduce pressure loss. High exhaust-system backpressure is of concern in the design of power trains for passenger cars and trucks because it penalizes fuel economy and limits peak power. Pressure losses occur due to fluid shear and turning during turbulent flow in the converter headers and in entry separation and developing laminar-flow boundary layers within the substrate flow passages. Some of the loss mechanisms are coupled. For example, losses in the inlet header are influenced by the presence of the flow resistance of a downstream substrate. Conversely, the flow maldistribution and pressure loss of the substrate(s) depend on the design of the inlet header.

  14. Collector for thermionic energy converter

    International Nuclear Information System (INIS)

    An improved collector is provided for a thermionic energy converter. The collector comprises a p-type layer of a semiconductor material formed on an n-type layer of a semiconductor material. The p-n junction is maintained in a forward biased condition. The electron affinity of the exposed surface of the p-type layer is effectively lowered to a low level near zero by the presence of a work function lowering activator. The dissipation of energy during collection is reduced by the passage of electrons through the p-type layer in the metastable conduction band state. A significant portion of the electron current remains at the potential of the fermi level of the n-type layer rather than dropping to the fermi level of the p-type layer. Less energy is therefore dissipated as heat and a higher net power output is delivered from a thermionic energy converter incorporating the collector

  15. Efficiency of Capacitively Loaded Converters

    DEFF Research Database (Denmark)

    Andersen, Thomas; Huang, Lina; Andersen, Michael A. E.;

    2012-01-01

    is introduced as a definition of efficiency. The calculated and measured efficiency curves for charging DEAP actuator, polypropylene film capacitor and X7R MLCC are provided and compared. The attention has to be paid for the voltage dependent capacitive load, like X7R MLCC, when evaluating the charging......This paper explores the characteristic of capacitance versus voltage for dielectric electro active polymer (DEAP) actuator, 2kV polypropylene film capacitor as well as 3kV X7R multi layer ceramic capacitor (MLCC) at the beginning. An energy efficiency for capacitively loaded converters...... efficiency of converter. Based on the capacitancevoltage curve, the correct capacitance should be chosen when calculating the stored energy; otherwise misleading optimistic efficiency can always be obtained. Actually, when DEAP actuator is not available at the early developing stage, the voltage independent...

  16. Radiated EMI from power converters

    Directory of Open Access Journals (Sweden)

    Arnautovski-Toševa Vesna

    2005-01-01

    Full Text Available With the continuous increase of switching frequency together with the ongoing trend to higher complexity and functionality, power converters as a part of electronic systems have raised more and more electromagnetic energy pollution to the local system environment. In the same time, stringent demands are imposed on the designers of new circuits that electromagnetic interference (EMI has to be suppressed at its source before it is allowed to propagate into other circuits and systems. In this paper, the authors present a full-wave numerical method for calculation and simulation of electromagnetic field radiated by power converter circuitry. The main objective is to analyze the layout geometry in order to obtain competitive PCB layout that will enable suitably attenuated level of the radiated electric field to safe level. By this it would be possible to ensure reliable operation of the sensitive electronic components in the proximity.

  17. Photoelectric converters with quantum coherence.

    Science.gov (United States)

    Su, Shan-He; Sun, Chang-Pu; Li, Sheng-Wen; Chen, Jin-Can

    2016-05-01

    Photon impingement is capable of liberating electrons in electronic devices and driving the electron flux from the lower chemical potential to higher chemical potential. Previous studies hinted that the thermodynamic efficiency of a nanosized photoelectric converter at maximum power is bounded by the Curzon-Ahlborn efficiency η_{CA}. In this study, we apply quantum effects to design a photoelectric converter based on a three-level quantum dot (QD) interacting with fermionic baths and photons. We show that, by adopting a pair of suitable degenerate states, quantum coherences induced by the couplings of QDs to sunlight and fermion baths can coexist steadily in nanoelectronic systems. Our analysis indicates that the efficiency at maximum power is no longer limited to η_{CA} through manipulation of carefully controlled quantum coherences.

  18. Development of a Compact Matrix Converter

    Directory of Open Access Journals (Sweden)

    J. Bauer

    2009-01-01

    Full Text Available This paper deals with the development of a matrix converter. Matrix converters belong to the category of direct frequency converters. A converter does not contain DC-link and the output voltage is provided by direct switching of voltage from the input phases. This is enabled by 9 bidirectional switches, which are provided by anti-serial connection of 18 IGBT transistors. The absence of a DC-link is great advantage of the matrix converter, but it also increases the requirements on the converter control. For this reason a new prototype of a matrix converter is being developed with sophisticated modern components (FPGA, Power PC equipped in the control part of the converter. The converter will be used for testing new control algorithms and commutation methods. 

  19. A Spacecraft Housekeeping System-on-Chip in a Radiation Hardened Structured ASIC

    Science.gov (United States)

    Suarez, George; DuMonthier, Jeffrey J.; Sheikh, Salman S.; Powell, Wesley A.; King, Robyn L.

    2012-01-01

    Housekeeping systems are essential to health monitoring of spacecraft and instruments. Typically, sensors are distributed across various sub-systems and data is collected using components such as analog-to-digital converters, analog multiplexers and amplifiers. In most cases programmable devices are used to implement the data acquisition control and storage, and the interface to higher level systems. Such discrete implementations require additional size, weight, power and interconnect complexity versus an integrated circuit solution, as well as the qualification of multiple parts. Although commercial devices are readily available, they are not suitable for space applications due the radiation tolerance and qualification requirements. The Housekeeping System-o n-A-Chip (HKSOC) is a low power, radiation hardened integrated solution suitable for spacecraft and instrument control and data collection. A prototype has been designed and includes a wide variety of functions including a 16-channel analog front-end for driving and reading sensors, analog-to-digital and digital-to-analog converters, on-chip temperature sensor, power supply current sense circuits, general purpose comparators and amplifiers, a 32-bit processor, digital I/O, pulse-width modulation (PWM) generators, timers and I2C master and slave serial interfaces. In addition, the device can operate in a bypass mode where the processor is disabled and external logic is used to control the analog and mixed signal functions. The device is suitable for stand-alone or distributed systems where multiple chips can be deployed across different sub-systems as intelligent nodes with computing and processing capabilities.

  20. Biomass compounds converted to gasoline

    Energy Technology Data Exchange (ETDEWEB)

    1979-10-08

    It is claimed that corn, castor, and jojoba oils as well as Hevea latex can be converted in high yields to gasoline by passage over zeolite catalysts at 450 degrees to 500 degrees centigrade. Gasoline yields are 60% from corn oil (essentially tristearin), compared with 50% yields from methanol. Latex depolymerizes before conversion. Fat and oil molecules adopt conformations that enable them to enter zeolite interstices, resulting in high yields of C6 to C9 aromatics.

  1. Combined catalytic converter and afterburner

    Energy Technology Data Exchange (ETDEWEB)

    Ma, T.T.-H.

    1994-11-30

    This patent describes the combined use of a catalytic converter and afterburner. An afterburner chamber and a catalyst matrix are disposed in series within a casing. A combustible premixed charge is ignited in the afterburner chamber before it enters the catalyst matrix. This invention overcomes the problem encountered in previous designs of some of the premixed charge passing unreacted through the device unless a very long afterburner chamber is used. (UK)

  2. EMI Prediction of Switching Converters

    OpenAIRE

    Trinchero, Riccardo; Stievano, Igor Simone; Canavero, Flavio

    2015-01-01

    This paper addresses the simulation of the conducted electromagnetic interference produced by circuits with periodically switching elements. The proposed method allows for the computation of their steady-state responses by means of augmented linear time-invariant equivalents built from circuit inspection only, and standard tools for circuit analysis. The approach is demonstrated on a real dc-dc boost converter by comparing simulation results with real measurements

  3. Resonant Demagnetization PWM Forward Converter

    OpenAIRE

    BİLGİN, Bülent

    2003-01-01

    In this paper, a new approach to demagnetization process of a PWM forward converter (FC) is proposed. According to this approach, the demagnetization winding and diode of a conventional FC are removed, and an external capacitor is added in parallel with the secondary diode. This replacement changes the linear demagnetization process of a conventional FC into a resonant demagnetization process. The theoretical performance results of the proposed resonant demagnetization forward conve...

  4. Radiated EMI from power converters

    OpenAIRE

    Arnautovski-Toševa Vesna; Rousset Yanis; Drissi El Khamlichi Khalil; Grčev Leonid

    2005-01-01

    With the continuous increase of switching frequency together with the ongoing trend to higher complexity and functionality, power converters as a part of electronic systems have raised more and more electromagnetic energy pollution to the local system environment. In the same time, stringent demands are imposed on the designers of new circuits that electromagnetic interference (EMI) has to be suppressed at its source before it is allowed to propagate into other circuits and systems. In this p...

  5. KLauS: an ASIC for silicon photomultiplier readout and its application in a setup for production testing of scintillating tiles

    CERN Document Server

    Briggl, K; Hagdorn, R; Harion, T; Schultz-Coulon, H.C; Shen, W

    2014-01-01

    signals from silicon photomultipliers. Developed as an analog front-end for future calorimeters with high granularity as pursued by the AHCAL concept in the CALICE collaboration, the ASIC is designed to measure the charge signal of the sensors in a large dynamic range and with low electronic noise contributions. In order to tune the operation voltage of each sensor individually, an 8-bit DAC to tune the voltage at the input terminal within a range of 2V is implemented. Using an integrated fast comparator with low jitter, the time information can be measured with subnanosecond resolution. The low power consumption of the ASIC can be further decreased using power gating techniques. Future versions of KLauS are under development and will incorporate an ADC with a resolution of up to 12-bits and blocks for digital data transmission. The chip is used in a setup for mass testing and characterization of scintillator tiles for the AHCAL ...

  6. Design and performance of a low noise, 128-channel ASIC preamplifier for readout of active matrix flat-panel imaging arrays

    CERN Document Server

    Maolinbay, M; Yarema, R J; Antonuk, L E; El-Mohri, Y; Yeakey, M

    2002-01-01

    Design architecture and performance measurements of a low noise, 128-channel application-specific-integrated-circuit (ASIC) preamplifier are reported. The ASIC was designed for readout of active matrix flat-panel imager (AMFPI) arrays. Such arrays, which presently can be made as large as 41 cmx41 cm and with pixel-to-pixel pitches down to approx 70 mu m, require large numbers of low noise, high density, custom integrated readout circuits. The design of this new chip is specifically tailored for research and development of active matrix flat-panel arrays for various medical imaging applications. The design architecture includes the following features: (1) Programmable signal gain which allows acquisition of a wide range of signal sizes from various array designs so as to optimize the signal-to-noise ratio; (2) Correlated double sampling (CDS) which significantly reduces certain noise components; (3) Pipelined readout (simultaneously sampling and multiplexing signals) which reduces image acquisition time; (4) P...

  7. Development of a low-noise, 4th-order readout ASIC for CdZnTe detectors in gamma spectrometer applications

    Science.gov (United States)

    Wang, Jia; Su, Lin; Wei, Xiaomin; Zheng, Ran; Hu, Yann

    2016-09-01

    This paper presents an ASIC readout circuit development, which aims to achieve low noise. In order to compensate the leakage current and improve gain, a dual-stage CSA has been utilized. A 4th-order high-linearity shaper is proposed to obtain a Semi-Gaussian wave and further decrease the noise induced by the leakage current. The ASIC has been designed and fabricated in a standard commercial 2P4M 0.35 μm CMOS process. Die area of one channel is about 1190 μm×147 μm. The input charge range is 1.8 fC. The peaking time can be adjusted from 1 μs to 3 μs. Measured ENC is about 55e- (rms) at input capacitor of 0 F. The gain is 271 mV/fC at the peaking time of 1 μs.

  8. A 4×8-Gbps VCSEL array driver ASIC and integration with a custom array transmitter module for the LHC front-end transmission

    Science.gov (United States)

    Guo, Di; Liu, Chonghan; Chen, Jinghong; Chramowicz, John; Gong, Datao; He, Huiqin; Hou, Suen; Liu, Tiankuan; Prosser, Alan; Teng, Ping-Kun; Xiang, Annie C.; Xiao, Le; Ye, Jingbo

    2016-09-01

    This paper describes the design, fabrication and experiment results of a 4×8-Gbps Vertical-Cavity Surface-Emitting Laser (VCSEL) array driver ASIC with the adjustable active-shunt peaking technique and the novel balanced output structure under the Silicon-on-Sapphire (SOS) process, and a custom array optical transmitter module, featuring a compact size of 10 mm×15 mm×5.3 mm. Both the array driver ASIC and the module have been fully tested after integration as a complete parallel transmitter. Optical eye diagram of each channel passes the eye mask at 8 Gbps/ch with adjacent channel working simultaneously with a power consumption of 150 mW/ch. The optical transmission of Bit-Error Rate (BER) less than 10E-12 is achieved at an aggregated data rate of 4×8-Gbps.

  9. Design and Control for the Buck-Boost Converter Combining 1-Plus-D Converter and Synchronous Rectified Buck Converters

    Directory of Open Access Journals (Sweden)

    Jeevan Naik

    2015-06-01

    Full Text Available In this paper, a design and control for the buck-boost converter, i.e., 1-plus-D converter with a positive output voltage, is presented, which combines the 1-plus-D converter and the synchronous rectified (SR buck converter. By doing so, the problem in voltage bucking of the 1-plus-D converter can be solved, thereby increasing the application capability of the 1-plus-D converter. Since such a converter operates in continuous conduction mode inherently, it possesses the nonpulsating output current, thereby not only decreasing the current stress on the output capacitor but also reducing the output voltage ripple. Above all, both the 1-plus-D converter and the SR buck converter, combined into a buck–boost converter with no right-half plane zero, use the same power switches, thereby causing the required circuit to be compact and the corresponding cost to be down. Furthermore, during the magnetization period, the input voltage of the 1-plus-D converter comes from the input voltage source, whereas during the demagnetization period, the input voltage of the 1-plus-D converter comes from the output voltage of the SR buck converter.

  10. Computerized simulation of converter process

    Energy Technology Data Exchange (ETDEWEB)

    Jalkanen, H.; Suomi, M.L.; Wallgren, M. [Helsinki Univ. of Technology, Otaniemi (Finland). Lab. of Metallurgy

    1996-12-31

    Converter process is essentially an oxidising refining process aiming in addition to (1) the primary refining action, decarburisation of high carbon iron melt, also to (2) maximal elimination of impurity elements, especially silicon, phosphorus and sulphur, (3) melting of substantial amounts of scrap using the extra heat released in oxidation reactions and (4) to exact final steel temperature control, optimal for further treatments. `Quantitative modelling of such a complex non-stationary chemical process as oxygen converting necessitates extensive formulation of chemical and thermal evolution of the process in connection with the technological properties of the reactor and the process control measures. A comprehensive converter simulation program like CONSIM-3. 1 and its preceding versions that is based on the theoretical and practical knowledge on the process can be used for (1) educating specialists and smelter personnel, (2) planning of the blowing programs, (3) developing and testing of process control systems and after some elaboration and restructuring (4) it can be integrated to static or dynamic process control systems. (orig.) SULA 2 Research Programme; 10 refs.

  11. Sour ageusia in two individuals implicates ion channels of the ASIC and PKD families in human sour taste perception at the anterior tongue.

    Directory of Open Access Journals (Sweden)

    Taufiqul Huque

    Full Text Available BACKGROUND: The perception of sour taste in humans is incompletely understood at the receptor cell level. We report here on two patients with an acquired sour ageusia. Each patient was unresponsive to sour stimuli, but both showed normal responses to bitter, sweet, and salty stimuli. METHODS AND FINDINGS: Lingual fungiform papillae, containing taste cells, were obtained by biopsy from the two patients, and from three sour-normal individuals, and analyzed by RT-PCR. The following transcripts were undetectable in the patients, even after 50 cycles of amplification, but readily detectable in the sour-normal subjects: acid sensing ion channels (ASICs 1a, 1beta, 2a, 2b, and 3; and polycystic kidney disease (PKD channels PKD1L3 and PKD2L1. Patients and sour-normals expressed the taste-related phospholipase C-beta2, the delta-subunit of epithelial sodium channel (ENaC and the bitter receptor T2R14, as well as beta-actin. Genomic analysis of one patient, using buccal tissue, did not show absence of the genes for ASIC1a and PKD2L1. Immunohistochemistry of fungiform papillae from sour-normal subjects revealed labeling of taste bud cells by antibodies to ASICs 1a and 1beta, PKD2L1, phospholipase C-beta2, and delta-ENaC. An antibody to PKD1L3 labeled tissue outside taste bud cells. CONCLUSIONS: These data suggest a role for ASICs and PKDs in human sour perception. This is the first report of sour ageusia in humans, and the very existence of such individuals ("natural knockouts" suggests a cell lineage for sour that is independent of the other taste modalities.

  12. VEGA: A low-power front-end ASIC for large area multi-linear X-ray silicon drift detectors: Design and experimental characterization

    Energy Technology Data Exchange (ETDEWEB)

    Ahangarianabhari, Mahdi; Macera, Daniele [Politecnico di Milano, Department of Electronics Engineering, Information Science and Bioengineering, P.za L. da Vinci 32, 20133 Milano (Italy); National Institute of Nuclear Physics, INFN sez. Milano (Italy); Bertuccio, Giuseppe, E-mail: Giuseppe.Bertuccio@polimi.it [Politecnico di Milano, Department of Electronics Engineering, Information Science and Bioengineering, P.za L. da Vinci 32, 20133 Milano (Italy); National Institute of Nuclear Physics, INFN sez. Milano (Italy); Malcovati, Piero; Grassi, Marco [University of Pavia, Department of Electrical Engineering, and National Institute of Nuclear Physics, INFN sez. Pavia, Pavia (Italy)

    2015-01-11

    We present the design and the first experimental characterization of VEGA, an Application Specific Integrated Circuit (ASIC) designed to read out large area monolithic linear Silicon Drift Detectors (SDD’s). VEGA consists of an analog and a digital/mixed-signal section to accomplish all the functionalities and specifications required for high resolution X-ray spectroscopy in the energy range between 500 eV and 50 keV. The analog section includes a charge sensitive preamplifier, a shaper with 3-bit digitally selectable shaping times from 1.6 µs to 6.6 µs and a peak stretcher/sample-and-hold stage. The digital/mixed-signal section includes an amplitude discriminator with coarse and fine threshold level setting, a peak discriminator and a logic circuit to fulfill pile-up rejection, signal sampling, trigger generation, channel reset and the preamplifier and discriminators disabling functionalities. A Serial Peripherical Interface (SPI) is integrated in VEGA for loading and storing all configuration parameters in an internal register within few microseconds. The VEGA ASIC has been designed and manufactured in 0.35 µm CMOS mixed-signal technology in single and 32 channel versions with dimensions of 200 µm×500 µm per channel. A minimum intrinsic Equivalent Noise Charge (ENC) of 12 electrons r.m.s. at 3.6 µs peaking time and room temperature is measured and the linearity error is between −0.9% and +0.6% in the whole input energy range. The total power consumption is 481 µW and 420 µW per channel for the single and 32 channels version, respectively. A comparison with other ASICs for X-ray SDD’s shows that VEGA has a suitable low noise and offers high functionality as ADC-ready signal processing but at a power consumption that is a factor of four lower than other similar existing ASICs.

  13. Simulation Results of Double Forward Converter

    Directory of Open Access Journals (Sweden)

    P. Vijaya KUMAR

    2009-12-01

    Full Text Available This work aims to find a better forward converter for DC to DC conversion.Simulation of double forward converter in SMPS system is discussed in this paper. Aforward converter with RCD snubber to synchronous rectifier and/or to current doubleris also discussed. The evolution of the forward converter is first reviewed in a tutorialfashion. Performance parameters are discussed including operating principle, voltageconversion ratio, efficiency, device stress, small-signal dynamics, noise and EMI. Itscircuit operation and its performance characteristics of the forward converter with RCDsnubber and double forward converter are described and the simulation results arepresented.

  14. OAM mode converter in twisted fibers

    DEFF Research Database (Denmark)

    Usuga Castaneda, Mario A.; Beltran-Mejia, Felipe; Cordeiro, Cristiano;

    2014-01-01

    We analyze the case of an OAM mode converter based on a twisted fiber, through finite element simulations where we exploit an equivalence between geometric and material transformations. The obtained converter has potential applications in MDM. © 2014 OSA....

  15. Dedicated multichannel readout ASIC coupled with single crystal diamond for dosimeter application

    Science.gov (United States)

    Fabbri, A.; Falco, M. D.; De Notaristefani, F.; Galasso, M.; Marinelli, M.; Orsolini Cencelli, V.; Tortora, L.; Verona, C.; Verona Rinati, G.

    2013-02-01

    This paper reports on the tests of a low-noise, multi-channel readout integrated circuit used as a readout electronic front-end for a diamond multi-pixel dosimeter. The system is developed for dose distribution measurement in radiotherapy applications. The first 10-channel prototype chip was designed and fabricated in a 0.18 um CMOS process. Every channel includes a charge integrator with a 10 pF capacitor and a double slope A/D converter. The diamond multi-pixel detector, based on CVD synthetic single crystal diamond Schottky diodes, is made by a 3 × 3 sensor matrix. The overall device has been tested under irradiation with 6 MeV radio therapeutic photon beams at the Policlinico ``Tor Vergata'' (PTV) hospital. Measurements show a 20 fA RMS leakage current from the front-end input stage and a negligible dark current from the diamond detector, a stable temporal response and a good linear behaviour as a function of both dose and dose rate. These characteristics were common to each tested channel.

  16. Analysis Of Single Phase Matrix Converter

    OpenAIRE

    Divya Ahirrao; Bhagyashri Gaware

    2014-01-01

    This paper presents concept of single phase matrix converter. Single phase matrix converter (SPMC) performs a function such as frequency changer, rectifier, inverter; chopper. This reduces the need for new converter hardware. Pulse width modulation (SPWM) techniques are used to calculate the switch duty ratio to synthesis the output. The simulation of converter is carried out in MATLAB/SIMULINK. Hardware design is obtained using readily available IC‟s and other components. Thi...

  17. Simulation Results of Double Forward Converter

    OpenAIRE

    P. Vijaya Kumar; S. Rama Reddy

    2009-01-01

    This work aims to find a better forward converter for DC to DC conversion.Simulation of double forward converter in SMPS system is discussed in this paper. Aforward converter with RCD snubber to synchronous rectifier and/or to current doubleris also discussed. The evolution of the forward converter is first reviewed in a tutorialfashion. Performance parameters are discussed including operating principle, voltageconversion ratio, efficiency, device stress, small-signal dynamics, noise and EMI....

  18. Digital to Analog Converter Description

    OpenAIRE

    Tuijl, van, B.A.J.

    2003-01-01

    A circuit for analogue to digital or digital to analogue conversion comprising at least 2n matched current sources (40-1, 40-2, 40-n), where n is the resolution required of the conversion. Preferably more than 2n current sources (40-1, 40-2, 40-n) are used. The order in which the sources (40-1, 40-2, 40-n) are used may be changed in different samples. The current sources (40-1, 40-2, 40-n) may be replaced by one bit switched capacitor converters or by inverters connected to one end of a set o...

  19. Reliability of Wave Energy Converters

    DEFF Research Database (Denmark)

    Ambühl, Simon

    There are many different working principles for wave energy converters (WECs) which are used to produce electricity from waves. In order for WECs to become successful and more competitive to other renewable electricity sources, the consideration of the structural reliability of WECs is essential...... approach that includes uncertainties related to the limited amount of data and the considered models used to calculate the loads/stresses as well as uncertainties given by Mother Nature (e.g. inter-annual variation of extreme values) and measurement uncertainties. Due to limited amount of knowledge...

  20. Reliability of Wave Energy Converters

    DEFF Research Database (Denmark)

    Ambühl, Simon

    There are many different working principles for wave energy converters (WECs) which are used to produce electricity from waves. In order for WECs tobecome successful and more competitive to other renewable electricity sources,the consideration of the structural reliability of WECs is essential...... uncertaintiesrelated to the limited amount of data and the considered models used tocalculate the loads/stresses as well as uncertainties given by Mother Nature (e.g. inter-annual variation of extreme values) and measurement uncertainties. Due to limited amount of knowledge, reliability considerations for WEC...

  1. Power Converters and Power Quality

    CERN Document Server

    Kahle, K

    2015-01-01

    This paper discusses the subject of power quality for power converters. The first part gives an overview of most of the common disturbances and power quality issues in electrical networks for particle accelerators, and explains their consequences for accelerator operation. The propagation of asymmetrical network disturbances into a network is analysed. Quantitative parameters for network disturbances in a typical network are presented, and immunity levels for users’ electrical equipment are proposed. The second part of this paper discusses the technologies and strategies used in particle accelerator networks for power quality improvement . Particular focus is given to networks supplying loads with cycling active and reactive power

  2. Simulation of the High Performance Time to Digital Converter for the ATLAS Muon Spectrometer trigger upgrade

    Science.gov (United States)

    Meng, X. T.; Levin, D. S.; Chapman, J. W.; Zhou, B.

    2016-09-01

    The ATLAS Muon Spectrometer endcap thin-Resistive Plate Chamber trigger project compliments the New Small Wheel endcap Phase-1 upgrade for higher luminosity LHC operation. These new trigger chambers, located in a high rate region of ATLAS, will improve overall trigger acceptance and reduce the fake muon trigger incidence. These chambers must generate a low level muon trigger to be delivered to a remote high level processor within a stringent latency requirement of 43 bunch crossings (1075 ns). To help meet this requirement the High Performance Time to Digital Converter (HPTDC), a multi-channel ASIC designed by CERN Microelectronics group, has been proposed for the digitization of the fast front end detector signals. This paper investigates the HPTDC performance in the context of the overall muon trigger latency, employing detailed behavioral Verilog simulations in which the latency in triggerless mode is measured for a range of configurations and under realistic hit rate conditions. The simulation results show that various HPTDC operational configurations, including leading edge and pair measurement modes can provide high efficiency (>98%) to capture and digitize hits within a time interval satisfying the Phase-1 latency tolerance.

  3. Underwater noise from a wave energy converter

    DEFF Research Database (Denmark)

    Tougaard, Jakob

    A recent addition to the anthropogenic sources of underwater noise is offshore wave energy converters. Underwater noise was recorded from the Wavestar wave energy converter located at Hastholm, Denmark (57°7.73´N, 8°37.23´E). The Wavestar is a full-scale test and demonstration converter...

  4. An Implemention of AES Algorithm in ASIC%一种AES算法的ASIC设计实现

    Institute of Scientific and Technical Information of China (English)

    史亚峰; 赵毅强

    2013-01-01

    为保证信息系统的安全性,基于现代集成电路设计方法,采用Chartered 0.35um CMOS工艺完成一款基于AES算法的密码芯片的ASIC设计.设计中首先完成了芯片的架构设计和模块划分,然后使用Verilog HDL完成了AES算法的描述.功能仿真结果表明该设计的加解密功能完全正确.最后使用Synopsys公司的Astro完成了芯片的物理设计.%In order to ensure the security of information systems, an ASIC implemention of AES based on Chartered 0. 35um CMOS process technology is shown. The Verilog HDL of AES algorithm is developed after the architecture design and module partition. The function simulation results demonstrate that the design works well. Finally, the physical design of the cipher chip is completed by Astro.

  5. Characteristics of a multichannel low-noise front-end ASIC for CZT-based small animal PET imaging

    Energy Technology Data Exchange (ETDEWEB)

    Gao, W., E-mail: gaowu@nwpu.edu.cn [Institute of Microelectronics, School of Computer S and T, Northwestern Polytechnical University, Xi’an (China); Liu, H., E-mail: newhui.cn@gmail.com [Institute of Microelectronics, School of Computer S and T, Northwestern Polytechnical University, Xi’an (China); Gan, B., E-mail: shadow524@163.com [Institute of Microelectronics, School of Computer S and T, Northwestern Polytechnical University, Xi’an (China); Hu, Y., E-mail: Yann.Hu@ires.in2p3.fr [Institut Pluridisciplinaire Hubert Curien, IN2P3/CNRS/UDS, Strasbourg (France)

    2014-05-01

    In this paper, we present the design and characteristics of a novel low-noise front-end readout application-specific integrated circuit dedicated to CdZnTe (CZT) detectors for a small animal PET imaging system. A low-noise readout method based on the charge integration and the delayed peak detection is proposed. An eight-channel front-end readout prototype chip is designed and implemented in a 0.35 μm CMOS process. The die size is 2.3 mm ×2.3 mm. The prototype chip is tested in different methods including electronic test, energy spectrum test and irradiation test. The input range of the ASIC is from 2000e{sup −} to 180,000e{sup −}, reflecting the energy of the gamma ray from 11.2 keV to 1 MeV. The gain of the readout channel is 65 mV/fC at the shaping time of 1 μs. The best test result of the equivalent noise charge (ENC) is 58.9 e{sup −} at zero farad plus 5.4 e{sup −} per picofarad. The nonlinearity and the crosstalk are less than 3% and less than 2%, respectively, at the room temperature. The static power dissipation is about 3 mW/channel.

  6. Characteristics of a multichannel low-noise front-end ASIC for CZT-based small animal PET imaging

    Science.gov (United States)

    Gao, W.; Liu, H.; Gan, B.; Hu, Y.

    2014-05-01

    In this paper, we present the design and characteristics of a novel low-noise front-end readout application-specific integrated circuit dedicated to CdZnTe (CZT) detectors for a small animal PET imaging system. A low-noise readout method based on the charge integration and the delayed peak detection is proposed. An eight-channel front-end readout prototype chip is designed and implemented in a 0.35 μm CMOS process. The die size is 2.3 mm ×2.3 mm. The prototype chip is tested in different methods including electronic test, energy spectrum test and irradiation test. The input range of the ASIC is from 2000e- to 180,000e-, reflecting the energy of the gamma ray from 11.2 keV to 1 MeV. The gain of the readout channel is 65 mV/fC at the shaping time of 1 μs. The best test result of the equivalent noise charge (ENC) is 58.9 e- at zero farad plus 5.4 e- per picofarad. The nonlinearity and the crosstalk are less than 3% and less than 2%, respectively, at the room temperature. The static power dissipation is about 3 mW/channel.

  7. STiC — a mixed mode silicon photomultiplier readout ASIC for time-of-flight applications

    Science.gov (United States)

    Harion, T.; Briggl, K.; Chen, H.; Fischer, P.; Gil, A.; Kiworra, V.; Ritzert, M.; Schultz-Coulon, H.-C.; Shen, W.; Stankova, V.

    2014-02-01

    STiC is an application specific integrated circuit (ASIC) for the readout of silicon photomultipliers. The chip has been designed to provide a very high timing resolution for time-of-flight applications in medical imaging and particle physics. It is dedicated in particular to the EndoToFPET-US project, which is developing an endoscopic PET detector combined with ultrasound imaging for early pancreas and prostate cancer detection. This PET system aims to provide a spatial resolution of 1 mm and a time-of-flight resolution of 200 ps FWHM. The analog frontend of STiC can use either a differential or single ended connection to the SiPM. The time and energy information of the detector signal is encoded into two time stamps. A special linearized time-over-threshold method is used to obtain a linear relation between the signal charge and the measured signal width, improving the energy resolution. The trigger signals are digitized by an integrated TDC module with a resolution of less than 20 ps. The TDC data is stored in an internal memory and transfered over a 160 MBit/s serial link using 8/10 bit encoding. First coincidence measurements using a 3.1 × 3.1 × 15 mm3 LYSO crystal and a S10362-33-50 Hamamtsu MPPC show a coincidence time resolution of less than 285 ps. We present details on the chip design as well as first characterization measurements.

  8. Single Event Effect Hardness for the Front-end ASICs Applied in BGO Calorimeter of DAMPE Satellite

    CERN Document Server

    Gao, Shan-Shan; Feng, Chang-Qing; Xi, Kai; Liu, Shu-Bin; An, Qi

    2016-01-01

    Dark Matter Particle Explorer (DAMPE) is a Chinese scientific satellite designed for cosmic ray study with a primary scientific goal of indirect search of dark matter particles. As a crucial sub-detector, BGO calorimeter measures the energy spectrum of cosmic rays in the energy range from 5 GeV to 10 TeV. In order to implement high-density front-end electronics (FEE) with the ability to measure 1848 signals from 616 photomultiplier tubes on the strictly constrained satellite platform, two kinds of 32-channel front-end ASICs, VA160 and VATA160, are customized. However, a space mission period of more than 3 years makes single event effect (SEE) a probable threat to reliability. In order to evaluate the SEE sensitivity of the chips and verify the effectiveness of mitigation methods, a series of laser-induced and heavy ion-induced SEE tests were performed. Benefiting from the single event latch-up (SEL) protection circuit for power supply, the triple module redundancy (TMR) technology for the configuration regist...

  9. Conceptual design of the TRACE detector readout using a compact, dead time-less analog memory ASIC

    Science.gov (United States)

    Aliaga, R. J.; Herrero-Bosch, V.; Capra, S.; Pullia, A.; Dueñas, J. A.; Grassi, L.; Triossi, A.; Domingo-Pardo, C.; Gadea, R.; González, V.; Hüyük, T.; Sanchís, E.; Gadea, A.; Mengoni, D.

    2015-11-01

    The new TRacking Array for light Charged particle Ejectiles (TRACE) detector system requires monitorization and sampling of all pulses in a large number of channels with very strict space and power consumption restrictions for the front-end electronics and cabling. Its readout system is to be based on analog memory ASICs with 64 channels each that sample a 1 μs window of the waveform of any valid pulses at 200 MHz while discarding any other signals and are read out at 50 MHz with external ADC digitization. For this purpose, a new, compact analog memory architecture is described that allows pulse capture with zero dead time in any channel while vastly reducing the total number of storage cells, particularly for large amounts of input channels. This is accomplished by partitioning the typical Switched Capacitor Array structure into two pipelined, asymmetric stages and introducing FIFO queue-like control circuitry for captured data, achieving total independence between the capture and readout operations.

  10. A 65 nm pixel readout ASIC with quick transverse momentum discrimination capabilities for the CMS Tracker at HL-LHC

    CERN Document Server

    Ceresa, Davide; Francisco, R; Caratelli, Alessandro; Kloukinas, Konstantinos; Marchioro, Alessandro

    2015-01-01

    A readout ASIC for the hybrid pixel detector with the capability of performing quick recognition of particles with high transverse momentum has been designed for the requirements of the CMS Outer Tracker at the High Luminosity LHC. The particle momentum dicrimination capability represents the main challenge for this design together with the low power requirement: the constraint of low mass for the new tracker dictates a total power budget of less than 100\\,mW/cm$^2$. The choice of a 65\\,nm CMOS technology has made it possible to satisfy this power requirement despite the fairly large amount of logic necessary to perform the momentum discrimination and the continuous operation at 40\\,MHz. Several techniques for low power have been used to implement this logic that performs cluster reduction, position offset correction and coordinate encoding. A prototype chip including a large part of the final functionality and the full front-end has been realized and comprises a matrix of 16 by 3 rectangular pixels of 100\\,$...

  11. Low power BiCMOS ASIC for wide energy range X-{gamma} ray imaging and spectroscopic detectors

    Energy Technology Data Exchange (ETDEWEB)

    Bertuccio, Giuseppe E-mail: giuseppe.bertuccio@polimi.it; Caccia, Stefano; Caroli, Ezio; Castorina, Stefano; Corradi, Andrea; D' Alesio, Gianluca; Gallina, Pietro; Sampietro, Marco

    2004-02-01

    A low-power, low noise Application Specific Integrated Circuit (ASIC), designed to read out CdTe array detectors for X-{gamma} ray imaging and spectroscopy on satellite or balloon telescopes, is presented. The chip ELBA has been realized in 0.8 {mu}m BiCMOS technology; the front-end includes preamplifier, shaper, peak stretcher, discriminator with a dynamic range from 20 keV to 2 MeV of photon energy. The reset of the preamplifier and the high time constant of the shaper are obtained with a very compact current conveyor feedback. A multichannel prototype has been realized with a digital back-end including multiplexer, decoder, double pulse detect and logic circuitry for chip testing and calibration. The measured noise level is in between 150 and 500 electrons r.m.s. corresponding to 1.5-5 keV FWHM in CdTe detectors. The total non-linearity is below {+-}1.5% and the cross-talk between two neighboring channels is about 0.7%. The circuit is powered with a single supply at +4 V with a total power consumption of 1 mW/channel.

  12. Characteristics of a multichannel low-noise front-end ASIC for CZT-based small animal PET imaging

    International Nuclear Information System (INIS)

    In this paper, we present the design and characteristics of a novel low-noise front-end readout application-specific integrated circuit dedicated to CdZnTe (CZT) detectors for a small animal PET imaging system. A low-noise readout method based on the charge integration and the delayed peak detection is proposed. An eight-channel front-end readout prototype chip is designed and implemented in a 0.35 μm CMOS process. The die size is 2.3 mm ×2.3 mm. The prototype chip is tested in different methods including electronic test, energy spectrum test and irradiation test. The input range of the ASIC is from 2000e− to 180,000e−, reflecting the energy of the gamma ray from 11.2 keV to 1 MeV. The gain of the readout channel is 65 mV/fC at the shaping time of 1 μs. The best test result of the equivalent noise charge (ENC) is 58.9 e− at zero farad plus 5.4 e− per picofarad. The nonlinearity and the crosstalk are less than 3% and less than 2%, respectively, at the room temperature. The static power dissipation is about 3 mW/channel

  13. Reactive Power Compensation using a Matrix Converter

    OpenAIRE

    Holtsmark, Nathalie Marie-Anna

    2010-01-01

    This Master's thesis investigates a new application for the matrix converter: Shunt reactive power compensation. The suggested Matrix Converter-based Reactive power Compensation (MCRC) device is composed of a matrix converter, which input is connected to the grid and an electric machine at the output of the converter. The reactive power flowing in or out of the grid can be regulated with the matrix converter by controlling the magnitude and/or phase angle of the current at the input of the co...

  14. Valuing Convertible Bonds Based on LSRQM Method

    Directory of Open Access Journals (Sweden)

    Jian Liu

    2014-01-01

    Full Text Available Convertible bonds are one of the essential financial products for corporate finance, while the pricing theory is the key problem to the theoretical research of convertible bonds. This paper demonstrates how to price convertible bonds with call and put provisions using Least-Squares Randomized Quasi-Monte Carlo (LSRQM method. We consider the financial market with stochastic interest rates and credit risk and present a detailed description on calculating steps of convertible bonds value. The empirical results show that the model fits well the market prices of convertible bonds in China’s market and the LSRQM method is effective.

  15. Analysis Of Single Phase Matrix Converter

    Directory of Open Access Journals (Sweden)

    Divya Ahirrao

    2014-03-01

    Full Text Available This paper presents concept of single phase matrix converter. Single phase matrix converter (SPMC performs a function such as frequency changer, rectifier, inverter; chopper. This reduces the need for new converter hardware. Pulse width modulation (SPWM techniques are used to calculate the switch duty ratio to synthesis the output. The simulation of converter is carried out in MATLAB/SIMULINK. Hardware design is obtained using readily available IC‟s and other components. This paper discusses the new multiple converter for single phase input using matrix topology using just a single control logic.

  16. Radiation-hard ASICS for sLHC optical data transmission

    International Nuclear Information System (INIS)

    High-speed data transmission in a high radiation environment poses an immense challenge in the detector design. We investigate the feasibility of using optical links for the silicon trackers of the ATLAS experiment for the planned upgrade of the LHC. The planned upgrade with ten times higher collision rate will produce a similar increase in the radiation. One possibility for the optical transmission is to use VCSEL arrays operating at 850 nm to transmit optical signals while using PIN arrays to convert the optical signals into electrical signals. We have designed a prototype chip containing building blocks for future SLHC optical links using a 130 nm CMOS 8RF process. The chip contains four main blocks; a VCSEL driver optimized for operation at 640 Mb/s, a VCSEL driver optimized for 3.2 Gb/s, a PIN receiver with a clock/data recovery circuit for operation at 40, 160, and 320 Mb/s, and two clock multipliers designed to operate at 640 Mb/s. The clock multiplier is designed to produce the high speed clock to serialize the data for transmission. All circuitry was designed following test results and guidelines from CERN on radiation tolerant design for the process. We have irradiated the chips with 24 GeV protons at CERN. For the VDC, the duty cycle of the output signal and the current consumption of the LVDS receiver remained constant during the irradiation. However, we observed significant decreases in the current consumption of the VCSEL driver circuit and the output drive current. This indicated that the think oxide layout used in the VCSEL driver portion of the chip might not be as radiation-hard and the circuit had been redesigned to minimize this sensitivity. For the PIN receiver, we found that the radiation produced no significant degradation, including the single event upset rate. The upset rate decreased with larger PIN current and was higher for a chip coupled to a PIN diode as expected. For the clock multipliers, we observed that the clocks of some chips

  17. High-Performance Data Converters

    DEFF Research Database (Denmark)

    Steensgaard-Madsen, Jesper

    -order difference of the output signal from the loop filter's first integrator stage. This technique avoids the need for accurate matching of analog and digital filters that characterizes the MASH topology, and it preserves the signal-band suppression of quantization errors. Simulations show that quantizers...... in a standard CMOS technology, they can be designed to yield 100 dB performance at 10 times oversampling. The proposed scaled-element mismatch-shaping D/A converters are well suited for use as the feedback stage in oversampled delta-sigma quantizers. It is, however, not easy to make full use of their potential......, because that requires a high-resolution loop quantizer which introduces only a small delay. Generally, it is not acceptable to design the loop quantizer as a high-resolution flash quantizer because they require a large chip area and high power consumption. Pipeline techniques are proposed to circumvent...

  18. The SSG Wave Energy Converter

    DEFF Research Database (Denmark)

    Vicinanza, Diego; Margheritini, Lucia; Kofoed, Jens Peter;

    2012-01-01

    The Sea-wave Slot-cone Generator concept (SSG) is a Wave Energy Converter based on the wave overtopping principle utilizing several reservoirs placed on top of each other, in which the energy of the incoming wave will be stored as potential energy. The water captured in the reservoirs will then run...... through turbines for electricity production. The system utilizes a wide spectrum of different wave conditions by means of multiple reservoirs, located at different levels above the still water level. Thereby, it obtains a high overall efficiency and it can be suitable for shoreline and breakwater...... applications, presenting particular advantages such as: sharing structure costs, availability of grid connection and infrastructures, recirculation of water inside the harbor, as the outlet of the turbines is on the rear part of the system. Recently, plans for the SSG pilot installation were in progress...

  19. Converting pest insects into food

    DEFF Research Database (Denmark)

    Offenberg, Hans Joachim; Wiwatwittaya, Decha

    2010-01-01

    by pest insects, problematic pests are converted into food and additional earnings. To assess the profitability of providing additional food for the ants, O. smaragdina food conversion efficiency (ECI) was estimated in the laboratory. This estimate suggests the feeding of weaver ants in ant farms......Canopy dwelling weaver ants (Oecophylla spp.) are used to control a variety of pests in a number of tropical tree crops. What is less familiar is the existence of commercial markets where these ants and their brood are sold for (i) human consumption, (ii) pet food or (iii) traditional medicine...... on management, 32-115 kg ant brood (mainly new queens) was harvested per ha per year without detrimental effect on colony survival and worker ant densities. This suggest that ant biocontrol and ant harvest can be sustainable integrated in plantations and double benefits derived. As ant production is fuelled...

  20. Three-phase AC-AC power converters based on matrix converter topology matrix-reactance frequency converters concept

    CERN Document Server

    Szczesniak, Pawel

    2013-01-01

    AC voltage frequency changes is one of the most important functions of solid state power converters. The most desirable features in frequency converters are the ability to generate load voltages with arbitrary amplitude and frequency, sinusoidal currents and voltages waveforms; the possibility of providing unity power factor for any load; and, finally, a simple and compact power circuit. Over the past decades, a number of different frequency converter topologies have appeared in the literature, but only the converters with either a voltage or current DC link are commonly used in industrial app

  1. Investigation of CMOS photodiodes integrated on an ASIC by a 0.5-µm analog CMOS process

    Science.gov (United States)

    Luo, H.; Ricklefs, U.; Hillmer, H.

    2010-04-01

    The characteristics of photodiodes integrated on CMOS ASICs depend on wavelength of radiation, structure of the photodiode itself and the parameters of the process of production. In this paper, the influence of the structure of integrated CMOS photodiodes produced in a standard 0.5 μm mixed signal CMOS process on the sensitivity is described. These photodiodes are used as image sensor elements arranged in an array for noncontact optoelectronic measurements. Models of integrated photodiodes distinguish the lateral and the vertical region of the photodiodes. The standard 0.5 μm CMOS process offers three types of pn-junctions: n+/p-substrate, p+/n-well and n-well/p-substrate. Based on our previous research and on the results from other authors the p+/n-well is chosen due to its better sensitivity and isolation against other structures. The local sensitivity is measured with a scanning setup by applying a diffraction limited spot spot of light on the surface of the diodes. Independent of the wavelength of radiation the charge carriers are generated mainly in the lateral region and not - as expected - in the vertical region. The maximum value of the local sensitivity is found in photodiodes with subdivided p+ regions showing a distance of 1.5 μm between these regions in the space between these two adjacent p+ regions. This local sensitivity is three times smaller than that of a reference PIN photodiode. According to this result, the new photodiodes will be constructed with optimized geometries. All examined structures of this type of photodiodes show a maximal spectral sensitivity in the range of 650 nm - 700 nm.

  2. Radiation-Tolerant DC-DC Converters

    Science.gov (United States)

    Skutt, Glenn; Sable, Dan; Leslie, Leonard; Graham, Shawn

    2012-01-01

    A document discusses power converters suitable for space use that meet the DSCC MIL-PRF-38534 Appendix G radiation hardness level P classification. A method for qualifying commercially produced electronic parts for DC-DC converters per the Defense Supply Center Columbus (DSCC) radiation hardened assurance requirements was developed. Development and compliance testing of standard hybrid converters suitable for space use were completed for missions with total dose radiation requirements of up to 30 kRad. This innovation provides the same overall performance as standard hybrid converters, but includes assurance of radiation- tolerant design through components and design compliance testing. This availability of design-certified radiation-tolerant converters can significantly reduce total cost and delivery time for power converters for space applications that fit the appropriate DSCC classification (30 kRad).

  3. Converting Relational Database Into Xml Document

    Directory of Open Access Journals (Sweden)

    Kanagaraj.S

    2012-03-01

    Full Text Available XML (Extensible Markup Language is emerging and gradually accepted as the standard for data interchange in the Internet world. Interoperation of relational database and XML database involves schema and data translations. Through EER (extended entity relationship model can convert the schema of relational database into XML. The semantics of the relational database, captured in EER diagram, are mapped to XML schema using stepwise procedures and mapped to XML document under the definitions of the XML schema. Converting Relational Database into XML Document is a process of converting the existing databases into XML file format. Existing conversion techniques convert a single database into xml. The proposed approach performs the conversion of databases like Ms-Access, MS-SQL to XML file format. Read the tables information from the corresponding database and generate code for the appropriate databases and convert the tables into XML flat file format. This converted XML file is been presented to the user.

  4. High Efficiency Reversible Fuel Cell Power Converter

    DEFF Research Database (Denmark)

    Pittini, Riccardo

    entitled "High Efficiency Reversible Fuel Cell Power Converter" and it presents the design of a high efficiency dc-dc converter developed and optimized for bidirectional fuel cell applications. First, a brief overview of fuel cell and energy storage technologies is presented. Different system topologies...... as well as different dc-ac and dc-dc converter topologies are presented and analyzed. A new ac-dc topology for high efficiency data center applications is proposed and an efficiency characterization based on the fuel cell stack I-V characteristic curve is presented. The second part discusses the main...... of magnetic components especially for large production volumes. At last, the complete converter design is presented in detailed and characterized in efficiency terms. Both benefits, provided by SiC power devices and by a redesign of the converter layout increased the converter power density up to 2.2 k...

  5. Efficient Implementation of Sample Rate Converter

    OpenAIRE

    Charanjit singh; Manjeet Singh patterh; Sanjay Sharma

    2011-01-01

    Within wireless base station system design, manufacturers continue to seek ways to add value and performance while increasing differentiation. Transmit/receive functionality has become an area of focus as designers attempt to address the need to move data from very high frequency sample rates to chip processing rates. Digital Up Converter (DUC) and Digital Down Converter (DDC) are used as sample rate converters. These are the important block in every digital communication system; hence there ...

  6. Silicon waveguide based TE mode converter.

    Science.gov (United States)

    Zhang, Jing; Liow, Tsung-Yang; Yu, Mingbin; Lo, Guo-Qiang; Kwong, Dim-Lee

    2010-11-22

    A silicon waveguide based TE mode converter was designed for the mode conversion between a horizontal waveguide and vertical waveguide in the two-layer structure waveguide based polarization diversity circuit. The TE mode converter's performance was studied. The polarization mode converter with minimum length of 5 μm was demonstrated to provide the TE mode conversion while maintaining the polarization status. The insertion loss at the transition region was less than 2 dB. PMID:21164874

  7. Ocean floor mounting of wave energy converters

    Science.gov (United States)

    Siegel, Stefan G

    2015-01-20

    A system for mounting a set of wave energy converters in the ocean includes a pole attached to a floor of an ocean and a slider mounted on the pole in a manner that permits the slider to move vertically along the pole and rotate about the pole. The wave energy converters can then be mounted on the slider to allow adjustment of the depth and orientation of the wave energy converters.

  8. Estimating the temperature of a catalytic converter

    Energy Technology Data Exchange (ETDEWEB)

    Ma, T.T.-H.

    1994-11-02

    A method is described for estimating the temperature in a catalytic converter used in the exhaust system of an internal combustion engine. Pressure sensors monitor the flow resistance across the catalytic converter to provide an indication of the temperature inside. This feedback system allows heating devices to be switched off and thus avoid overheating, while maintaining the catalytic converter's efficiency by assuring that it does not operate below its light off temperature. (UK)

  9. Estimating the temperature of a catalytic converter

    Energy Technology Data Exchange (ETDEWEB)

    Ma, T.T.-H.

    1994-11-02

    A method of estimating the temperature of a catalytic converter used in the exhaust system of an internal combustion engine is described. Heated exhaust gas oxygen (HEGO) sensors are placed upstream and downstream of the catalytic converter. The temperature of the catalytic converter shortly after start-up is measured by monitoring the resistance of the HEGO sensor's heating element. The downstream sensor is used for mixture control and to double check results of the upstream sensor. (UK)

  10. Timing of Convertible Debt Financing and Investment

    OpenAIRE

    Kyoko Yagi; Ryuta Takashima; Hiroshi Takamori; Katsushige Sawaki

    2008-01-01

    In this paper, we examine the optimal investment policy of the firm which is financed by issuing equity, straight debt and convertible debt. We extend the model in Mauer and Sarkar (2005) over financing with convertible debt. We examine two different investment policies that maximize the equity value and the firm value and show the agency cost as the difference between each policy value. Furthermore, we investigate how the issuance of convertible debt affects investment.

  11. Regeneration of ZVS converter with Resonant inductor

    Directory of Open Access Journals (Sweden)

    J.Sivavara Prasad

    2011-09-01

    Full Text Available This paper presents an analysis of the regeneration of zero-voltage-switching converter with resonant inductor, quasi-resonant converters, and full-bridge zero-voltage-switched PWM Converter. The design of a clamping circuit considering a saturable resonant inductor is presented and compared with the design of a clamping circuit with a linear resonant inductor. A diode model with reverse recovery is employed to simulate the effects.

  12. Commutation Processes in Multiresonant ZVS Bridge Converter

    Directory of Open Access Journals (Sweden)

    Miroslaw Luft

    2008-01-01

    Full Text Available The analysis of the multiresonant ZVS DC/DC bridge converter is presented. The control system of the converter is basedon the method of frequency control at the constant time of transistor turn-off with a phase shift. The operation of the circuit is givenand the operating range of the converter is defined where ZVS switching operation is assured. Control characteristics are given andthe converter’s efficiency is defined. The circuit’s operation is analysed on the basis of results of the converter simulation tests using Simplorer programme.

  13. A photon-counting silicon-strip detector for digital mammography with an ultrafast 0.18-μm CMOS ASIC

    Energy Technology Data Exchange (ETDEWEB)

    Chen, Han, E-mail: hanchen@kth.se [Department of Physics, Royal Institute of Technology (KTH), AlbaNova University Center, 106 91 Stockholm (Sweden); Cederström, Björn [Department of Physics, Royal Institute of Technology (KTH), AlbaNova University Center, 106 91 Stockholm (Sweden); Philips Healthcare, Smidesvägen 5, 171 41 Solna (Sweden); Xu, Cheng; Persson, Mats; Karlsson, Staffan; Danielsson, Mats [Department of Physics, Royal Institute of Technology (KTH), AlbaNova University Center, 106 91 Stockholm (Sweden)

    2014-06-01

    We have evaluated a silicon-strip detector with a 0.18-μm CMOS application specific integrated circuits (ASIC) containing 160 channels for use in photon-counting digital mammography. Measurements were performed at the Elettra light source using monochromatic X-ray beams with different energies and intensities. Energy resolution, ΔE/E{sub in}, was measured to vary between 0.10 and 0.23 in the energy range of 15–40 keV. Pulse pileup has shown little effect on energy resolution.

  14. Vacuum-insulated catalytic converter

    Energy Technology Data Exchange (ETDEWEB)

    Benson, David K. (Golden, CO)

    2001-01-01

    A catalytic converter has an inner canister that contains catalyst-coated substrates and an outer canister that encloses an annular, variable vacuum insulation chamber surrounding the inner canister. An annular tank containing phase-change material for heat storage and release is positioned in the variable vacuum insulation chamber a distance spaced part from the inner canister. A reversible hydrogen getter in the variable vacuum insulation chamber, preferably on a surface of the heat storage tank, releases hydrogen into the variable vacuum insulation chamber to conduct heat when the phase-change material is hot and absorbs the hydrogen to limit heat transfer to radiation when the phase-change material is cool. A porous zeolite trap in the inner canister absorbs and retains hydrocarbons from the exhaust gases when the catalyst-coated substrates and zeolite trap are cold and releases the hydrocarbons for reaction on the catalyst-coated substrate when the zeolite trap and catalyst-coated substrate get hot.

  15. Catalytic converter with thermoelectric generator

    Energy Technology Data Exchange (ETDEWEB)

    Parise, R.J.

    1998-07-01

    The unique design of an electrically heated catalyst (EHC) and the inclusion of an ECO valve in the exhaust of an internal combustion engine will meet the strict new emission requirements, especially at vehicle cold start, adopted by several states in this country as well as in Europe and Japan. The catalytic converter (CC) has been a most useful tool in pollution abatement for the automobile. But the emission requirements are becoming more stringent and, along with other improvements, the CC must be improved to meet these new standards. Coupled with the ECO valve, the EHC can meet these new emission limits. In an internal combustion engine vehicle (ICEV), approximately 80% of the energy consumed leaves the vehicle as waste heat: out the tail pipe, through the radiator, or convected/radiated off the engine. Included with the waste heat out the tail pipe are the products of combustion which must meet strict emission requirements. The design of a new CC is presented here. This is an automobile CC that has the capability of producing electrical power and reducing the quantity of emissions at vehicle cold start, the Thermoelectric Catalytic Power Generator. The CC utilizes the energy of the exothermic reactions that take place in the catalysis substrate to produce electrical energy with a thermoelectric generator. On vehicle cold start, the thermoelectric generator is used as a heat pump to heat the catalyst substrate to reduce the time to catalyst light-off. Thus an electrically heated catalyst (EHC) will be used to augment the abatement of tail pipe emissions. Included with the EHC in the exhaust stream of the automobile is the ECO valve. This valve restricts the flow of pollutants out the tail pipe of the vehicle for a specified amount of time until the EHC comes up to operating temperature. Then the ECO valve opens and allows the full exhaust, now treated by the EHC, to leave the vehicle.

  16. Passive Resonant Bidirectional Converter with Galvanic Barrier

    Science.gov (United States)

    Rosenblad, Nathan S. (Inventor)

    2014-01-01

    A passive resonant bidirectional converter system that transports energy across a galvanic barrier includes a converter using at least first and second converter sections, each section including a pair of transfer terminals, a center tapped winding; a chopper circuit interconnected between the center tapped winding and one of the transfer terminals; an inductance feed winding interconnected between the other of the transfer terminals and the center tap and a resonant tank circuit including at least the inductance of the center tap winding and the parasitic capacitance of the chopper circuit for operating the converter section at resonance; the center tapped windings of the first and second converter sections being disposed on a first common winding core and the inductance feed windings of the first and second converter sections being disposed on a second common winding core for automatically synchronizing the resonant oscillation of the first and second converter sections and transferring energy between the converter sections until the voltage across the pairs of transfer terminals achieves the turns ratio of the center tapped windings.

  17. Multilevel converters for 10 MW Wind Turbines

    DEFF Research Database (Denmark)

    Ma, Ke; Blaabjerg, Frede

    2011-01-01

    Several promising multi-level converter configurations for 10 MW Wind Turbines both with direct drive and one-stage gear box drive using Permanent Magnet Synchronous Generator (PMSG) are proposed, designed and compared. Reliability is a crucial indicator for large scale wind power converters...

  18. Power Converters Secure Electronics in Harsh Environments

    Science.gov (United States)

    2013-01-01

    In order to harden power converters for the rigors of space, NASA awarded multiple SBIR contracts to Blacksburg, Virginia-based VPT Inc. The resulting hybrid DC-DC converters have proven valuable in aerospace applications, and as a result the company has generated millions in revenue from the product line and created four high-tech jobs to handle production.

  19. Switched-mode converters (one quadrant)

    CERN Document Server

    Barrade, P

    2006-01-01

    Switched-mode converters are DC/DC converters that supply DC loads with a regulated output voltage, and protection against overcurrents and short circuits. These converters are generally fed from an AC network via a transformer and a conventional diode rectifier. Switched-mode converters (one quadrant) are non-reversible converters that allow the feeding of a DC load with unipolar voltage and current. The switched-mode converters presented in this contribution are classified into two families. The first is dedicated to the basic topologies of DC/DC converters, generally used for low- to mid-power applications. As such structures enable only hard commutation processes, the main drawback of such topologies is high commutation losses. A typical multichannel evolution is presented that allows an interesting decrease in these losses. Deduced from this direct DC/DC converter, an evolution is also presented that allows the integration of a transformer into the buck and the buck–boost structure. This enables an int...

  20. Modeling and Simulation of Matrix Converter

    DEFF Research Database (Denmark)

    Liu, Fu-rong; Klumpner, Christian; Blaabjerg, Frede

    2005-01-01

    This paper discusses the modeling and simulation of matrix converter. Two models of matrix converter are presented: one is based on indirect space vector modulation and the other is based on power balance equation. The basis of these two models is• given and the process on modeling is introduced in...

  1. High Precision Current Measurement for Power Converters

    CERN Document Server

    Cerqueira Bastos, M

    2015-01-01

    The accurate measurement of power converter currents is essential to controlling and delivering stable and repeatable currents to magnets in particle accelerators. This paper reviews the most commonly used devices for the measurement of power converter currents and discusses test and calibration methods.

  2. High Precision Current Measurement for Power Converters

    OpenAIRE

    Bastos, M. Cerqueira

    2016-01-01

    The accurate measurement of power converter currents is essential to controlling and delivering stable and repeatable currents to magnets in particle accelerators. This paper reviews the most commonly used devices for the measurement of power converter currents and discusses test and calibration methods.

  3. Selective harmonic control for power converters

    DEFF Research Database (Denmark)

    Zhou, Keliang; Yang, Yongheng; Blaabjerg, Frede;

    2014-01-01

    This paper proposes an Internal Model Principle (IMP) based Selective Harmonic Controller (SHC) for power converters. The proposed SHC offers an optimal control solution for power converters to mitigate power harmonics. It makes a good trade-off among cost, complexity and performance. It has high...

  4. Present trends in HVDC converter station design

    Energy Technology Data Exchange (ETDEWEB)

    Carlsson, Lennart; Asplund, Gunnar; Bjorklund, Hans; Flisberg, Gunnar [ABB Power Systems AB, Ludvika (Sweden)

    1994-12-31

    HVDC converter station technology has developed rapidly to satisfy increasing requirements during past 10 - 15 years, but there has not been any dramatic changes since thyristor valves were introduced in the mid 70s. This paper describes some recent and expected future developments, that will substantiality change and simplify future converter stations. (author) 4 refs., 7 figs.

  5. Radiation Effects on DC-DC Converters

    Science.gov (United States)

    Zhang, De-Xin; AbdulMazid, M. D.; Attia, John O.; Kankam, Mark D. (Technical Monitor)

    2001-01-01

    In this work, several DC-DC converters were designed and built. The converters are Buck Buck-Boost, Cuk, Flyback, and full-bridge zero-voltage switched. The total ionizing dose radiation and single event effects on the converters were investigated. The experimental results for the TID effects tests show that the voltages of the Buck Buck-Boost, Cuk, and Flyback converters increase as total dose increased when using power MOSFET IRF250 as a switching transistor. The change in output voltage with total dose is highest for the Buck converter and the lowest for Flyback converter. The trend of increase in output voltages with total dose in the present work agrees with those of the literature. The trends of the experimental results also agree with those obtained from PSPICE simulation. For the full-bridge zero-voltage switch converter, it was observed that the dc-dc converter with IRF250 power MOSFET did not show a significant change of output voltage with total dose. In addition, for the dc-dc converter with FSF254R4 radiation-hardened power MOSFET, the output voltage did not change significantly with total dose. The experimental results were confirmed by PSPICE simulation that showed that FB-ZVS converter with IRF250 power MOSFET's was not affected with the increase in total ionizing dose. Single Event Effects (SEE) radiation tests were performed on FB-ZVS converters. It was observed that the FB-ZVS converter with the IRF250 power MOSFET, when the device was irradiated with Krypton ion with ion-energy of 150 MeV and LET of 41.3 MeV-square cm/mg, the output voltage increased with the increase in fluence. However, for Krypton with ion-energy of 600 MeV and LET of 33.65 MeV-square cm/mg, and two out of four transistors of the converter were permanently damaged. The dc-dc converter with FSF254R4 radiation hardened power MOSFET's did not show significant change at the output voltage with fluence while being irradiated by Krypton with ion energy of 1.20 GeV and LET of 25

  6. SPECTRAL ANALYSIS OF BUCK AND SEPIC CONVERTERS

    Directory of Open Access Journals (Sweden)

    CHAKIB ALAOUI

    2011-02-01

    Full Text Available Switched mode power converters generate harmonic currents, which will be injected into the utility grid, causing distortion of the utility waveform. They also become a source for the generation of EMI, which may affect the communication systems. This work is about the design and evaluation of the two most frequently used SMPS used in step down mode of operation: the Buck converter and the Sepic converter working in step-down mode of operation. These converters were designed using optimized equations for their components ratings. Simulation results show that although the Buck output voltage is low in harmonics, it has high harmonic contents in currents circulating in its inductor and diode, and hence requires strong filtering. The Sepic converterhas lower harmonic contents than the Buck converter.

  7. Switched Mode Four-Quadrant Converters

    CERN Document Server

    Thurel, Y

    2015-01-01

    This paper was originally presented at CAS-2004, and was slightly modified for CAS-2014. It presents a review of the key parameters that impact the design choices for a true four-quadrant power converter, in the range 1-10 kW, mainly based on switching mode converter topology. This paper will first describe the state-of-the-art for this power converter family, giving the drawbacks and advantages of different possible solutions. It will also present practical results obtained from the CERN-designed converter. It will finally give some important tips regarding critical phases like test one, when conducting a project dealing with this type of power converter.

  8. Reliability of Power Electronic Converter Systems

    DEFF Research Database (Denmark)

    The main aims of power electronic converter systems (PECS) are to control, convert, and condition electrical power flow from one form to another through the use of solid-state electronics. This book outlines current research into the scientific modeling, experimentation, and remedial measures...... electronic converter systems; anomaly detection and remaining-life prediction for power electronics; reliability of DC-link capacitors in power electronic converters; reliability of power electronics packaging; modeling for life-time prediction of power semiconductor modules; minimization of DC......-link capacitance in power electronic converter systems; wind turbine systems; smart control strategies for improved reliability of power electronics system; lifetime modelling; power module lifetime test and state monitoring; tools for performance and reliability analysis of power electronics systems; fault...

  9. PERFORMANCE ANALYSIS OF 2D CONVERTER BY COMBINING SR & KY CONVERTERS

    Directory of Open Access Journals (Sweden)

    V. Manoj Kumar

    2014-03-01

    Full Text Available Most of the portable equipments use battery as power source. The increasing use of low voltage portable devices and growing requirements of functionalities embedded into such devices. Thus an efficient power management technique is needed for longer battery life for them. Highly variable nature of batteries systems often require supply voltages to be both higher and lower than the battery. This is most efficiently generated by a buck-boost switching converter. But here the converter efficiency is decreased since the power loss occurs in the storage devices. Step by step, process of designing, feedback control and simulation of a novel voltage-buck boost converter, combining KY and synchronous Rectifier buck converter for battery power applications. Unlike the traditional buck–boost converter, this converter has the positive output voltage and system is stable, different from the negative output voltage and low stable of the traditional inverting buck–boost converters. Since such a converter operates in continuous conduction mode. Also it possesses the non-pulsating output current, thereby not only decreasing the current stress on the output capacitor but also reducing the output voltage ripple. Both the KY converter and the synchronous buck converter, combined into a positive buck– boost converter, uses the same power switches. Here it makes the circuit to be compact and the corresponding cost to be down. Voltage conversion ratio is 2D,so it is also called 2D converter.

  10. Boost matrix converters in clean energy systems

    Science.gov (United States)

    Karaman, Ekrem

    This dissertation describes an investigation of novel power electronic converters, based on the ultra-sparse matrix topology and characterized by the minimum number of semiconductor switches. The Z-source, Quasi Z-source, Series Z-source and Switched-inductor Z-source networks were originally proposed for boosting the output voltage of power electronic inverters. These ideas were extended here on three-phase to three-phase and three-phase to single-phase indirect matrix converters. For the three-phase to three-phase matrix converters, the Z-source networks are placed between the three-switch input rectifier stage and the output six-switch inverter stage. A brief shoot-through state produces the voltage boost. An optimal pulse width modulation technique was developed to achieve high boosting capability and minimum switching losses in the converter. For the three-phase to single-phase matrix converters, those networks are placed similarly. For control purposes, a new modulation technique has been developed. As an example application, the proposed converters constitute a viable alternative to the existing solutions in residential wind-energy systems, where a low-voltage variable-speed generator feeds power to the higher-voltage fixed-frequency grid. Comprehensive analytical derivations and simulation results were carried out to investigate the operation of the proposed converters. Performance of the proposed converters was then compared between each other as well as with conventional converters. The operation of the converters was experimentally validated using a laboratory prototype.

  11. Radiation hardness tests and characterization of the CLARO-CMOS, a low power and fast single-photon counting ASIC in 0.35 micron CMOS technology

    Science.gov (United States)

    Fiorini, M.; Andreotti, M.; Baldini, W.; Calabrese, R.; Carniti, P.; Cassina, L.; Cotta Ramusino, A.; Giachero, A.; Gotti, C.; Luppi, E.; Maino, M.; Malaguti, R.; Pessina, G.; Tomassetti, L.

    2014-12-01

    The CLARO-CMOS is a prototype ASIC that allows fast photon counting with 5 ns peaking time, a recovery time to baseline smaller than 25 ns, and a power consumption of less than 1 mW per channel. This chip is capable of single-photon counting with multi-anode photomultipliers and finds applications also in the read-out of silicon photomultipliers and microchannel plates. The prototype is realized in AMS 0.35 micron CMOS technology. In the LHCb RICH environment, assuming 10 years of operation at the nominal luminosity expected after the upgrade in Long Shutdown 2 (LS2), the ASIC must withstand a total fluence of about 6×1012 1 MeV neq /cm2 and a total ionizing dose of 400 krad. A systematic evaluation of the radiation effects on the CLARO-CMOS performance is therefore crucial to ensure long term stability of the electronics front-end. The results of multi-step irradiation tests with neutrons and X-rays up to the fluence of 1014 cm-2 and a dose of 4 Mrad, respectively, are presented, including measurement of single event effects during irradiation and chip performance evaluation before and after each irradiation step.

  12. Electromagnetic Compatibility of Matrix Converter System

    Directory of Open Access Journals (Sweden)

    S. Fligl

    2006-12-01

    Full Text Available The presented paper deals with matrix converters pulse width modulation strategies design with emphasis on the electromagnetic compatibility. Matrix converters provide an all-silicon solution to the problem of converting AC power from one frequency to another, offering almost all the features required of an ideal static frequency changer. They possess many advantages compared to the conventional voltage or current source inverters. A matrix converter does not require energy storage components as a bulky capacitor or an inductance in the DC-link, and enables the bi-directional power flow between the power supply and load. The most of the contemporary modulation strategies are able to provide practically sinusoidal waveforms of the input and output currents with negligible low order harmonics, and to control the input displacement factor. The perspective of matrix converters regarding EMC in comparison with other types of converters is brightly evident because it is no need to use any equipment for power factor correction and current and voltage harmonics reduction. Such converter with proper control is properly compatible both with the supply mains and with the supplied load. A special digital control system was developed for the realized experimental test bed which makes it possible to achieve greater throughput of the digital control system and its variability.

  13. Acoustics of automotive catalytic converter assemblies

    Science.gov (United States)

    Dickey, Nolan S.; Selamet, Ahmet; Parks, Steve J.; Tallio, Kevin V.; Miazgowicz, Keith D.; Radavich, Paul M.

    2003-10-01

    In an automotive exhaust system, the purpose of the catalytic converter is to reduce pollutant emissions. However, catalytic converters also affect the engine and exhaust system breathing characteristics; they increase backpressure, affect exhaust system acoustic characteristics, and contribute to exhaust manifold tuning. Thus, radiated sound models should include catalytic converters since they can affect both the source characteristics and the exhaust system acoustic behavior. A typical catalytic converter assembly employs a ceramic substrate to carry the catalytically active noble metals. The substrate has numerous parallel tubes and is mounted in a housing with swelling mat or wire mesh around its periphery. Seals at the ends of the substrate can be used to help force flow through the substrate and/or protect the mat material. Typically, catalytic converter studies only consider sound propagation in the small capillary tubes of the substrate. Investigations of the acoustic characteristics of entire catalytic converter assemblies (housing, substrate, seals, and mat) do not appear to be available. This work experimentally investigates the acoustic behavior of catalytic converter assemblies and the contributions of the separate components to sound attenuation. Experimental findings are interpreted with respect to available techniques for modeling sound propagation in ceramic substrates.

  14. Propagation characteristics of converted refracted wave and its application in static correction of converted wave

    Institute of Scientific and Technical Information of China (English)

    2008-01-01

    Three-component seismic exploration through P-wave source and three-component geophone is an effective technique used in complicated reservoir exploration. In three-component seismic exploration data processing,one of the difficulties is static correction of converted wave. This paper analyzes propagation characteristics of non-converted and converted refracted waves,and discovers a favor-able condition for the formation of converted refracted wave,i.e. the velocity of overlaying medium S wave is much lower than that of underlying medium S wave. In addition,the paper proposes the static correction method of converted wave based on PPS converted refracted wave,and processes the real three-component seismic data with better results of static correction of converted wave.

  15. Application of AGPU for Matrix Converters

    Directory of Open Access Journals (Sweden)

    Nithin T Abraham

    2014-07-01

    Full Text Available A simple PI control loop for the matrix converter system is designed in the simulation to maintain a constant output voltage inspite of any disturbance in the source. The single phase matrix converter employs a modified safe-commutation strategy, which results in the elimination of voltage spikes on switches, without the need of a snubber circuit when there is an inductive load being utilized. This is facilitated through the proper switching control algorithm. The sine PWM pulses are generated as switching pulses to the converter to reduce the THD.

  16. Matrix laser IR-visible image converter

    International Nuclear Information System (INIS)

    A new type of a focal matrix IR-visible image converter is proposed. The pixel IR detectors of the matrix are tunable microcavities of VCSEL (vertical-cavity surface emitting laser) semiconductor microstructures. The image conversion is performed due to the displacements of highly reflecting cavity mirrors caused by thermoelastic stresses in their microsuspensions appearing upon absorption of IR radiation. Analysis of the possibilities of the converter shows that its sensitivity is 10-3-10-2 K and the time response is 10-4-10-3 s. These characteristics determine the practical application of the converter. (laser applications and other topics in quantum electronics)

  17. Data Converter for Multistandard Mobile Phones

    DEFF Research Database (Denmark)

    Yurttas, Aziz; Bruun, Erik; Jensen, Rasmus Glarborg

    2004-01-01

    This paper describes an analog to digital converter (ADC) for mobile communication systems using a direct down conversion architecture. The ADC can be programmed to meet the requirements of different communication standards, including GSM (Global System for Mobile communication) and WCDMA (Wideband...... Code Division Multiple Access). The ADC is realized with a pipeline ADC architecture for WCDMA and a Sigma-Delta architecture for GSM. In order to have an optimized area and power consumption, the basic building blocks (opamps) of the converters are shared between the two converter architectures...

  18. Spectral Analysis of Sample Rate Converter

    Directory of Open Access Journals (Sweden)

    Manish Sabraj

    2010-10-01

    Full Text Available The aim of digital sample rate conversion is to bring a digital audio signal from one sample frequency to another. The distortion of the audio signal introduced by the sample rate converter should be as low as possible. The generation of the output samples from the input samples may be performed by the application of various methods. In this paper, a new technique of digital sample-rate converter is proposed. We perform the spectral analysis of proposed digital sample rate converter.

  19. Converters for Distributed Power Generation Systems

    DEFF Research Database (Denmark)

    Blaabjerg, Frede; Yang, Yongheng

    2015-01-01

    presents an overview of the power converters for the DPGS, mainly based on wind turbine systems and photovoltaic systems, covering a wide range of applications. Moreover, the modulation schemes and interfacing power filters for the power converters are also exemplified. Finally, the general control......Power electronics technology has become the enabling technology for the integration of distributed power generation systems (DPGS) such as offshore wind turbine power systems and commercial photovoltaic power plants. Depending on the applications, a vast array of DPGS-based power converter...

  20. Reliability of power electronic converter systems

    CERN Document Server

    Chung, Henry Shu-hung; Blaabjerg, Frede; Pecht, Michael

    2016-01-01

    This book outlines current research into the scientific modeling, experimentation, and remedial measures for advancing the reliability, availability, system robustness, and maintainability of Power Electronic Converter Systems (PECS) at different levels of complexity.

  1. Energy saving dc-dc converter circuit

    International Nuclear Information System (INIS)

    An energy saving dc-dc converter circuit is disclosed having two energy efficient means which operate in tandem, an energy conserving means and a voltage doubling means. These energy efficient means are applied in combination with elements commonly found in dc-dc converter circuits, namely an ac voltage generator, a transformer for stepping up the generated ac voltage, and means for storing the converted dc voltage. The energy conserving means is connected to the dc voltage storage means. It comprises a resettable inhibit circuit which cuts off the provision of dc voltage for conversion for a predetermined interval when the output of the converter exceeds a predetermined level. The voltage doubling means is reponsive to outputs of the inhibit circuit of the energy conserving means and the ac voltage generator. It provides a phase inverted waveform of the generated ac voltage on one of two leads to the ac voltage step-up transformer

  2. Input-output rearrangement of isolated converters

    DEFF Research Database (Denmark)

    Madsen, Mickey Pierre; Kovacevic, Milovan; Mønster, Jakob Døllner;

    2015-01-01

    This paper presents a new way of rearranging the input and output of isolated converters. The new arrangement posses several advantages, as increased voltage range, higher power handling capabilities, reduced voltage stress and improved efficiency, for applications where galvanic isolation...

  3. Interface of magnetoresistive converter of active power

    Directory of Open Access Journals (Sweden)

    A. I. Vytiaganets

    2009-10-01

    Full Text Available The vehicle and programmatic interfaces of magnetoresistive converter of active power are considered, the results of statistical treatment of the multiple measuring of active-power are analysed.

  4. Converter station of Juebek; Umrichterwerk Juebek

    Energy Technology Data Exchange (ETDEWEB)

    Zimmert, G. [AEG Bahnfahrwegsysteme GmbH, Frankfurt am Main (Germany); Scheuring, J. [AEG Bahnfahrwegsysteme GmbH, Frankfurt am Main (Germany); Werth, L. [AEG Bahnfahrwegsysteme GmbH, Frankfurt am Main (Germany); Koeltzsch, W. [Deutsche Bahn AG, Hamburg (Germany); Niehage, H. [AEG Anlagen- und Antriebssysteme GmbH, Berlin (Germany); Tadros, Y. [Daimler Benz AG, Berlin (Germany). Forschungsinstitut fuer Antriebstechnik und Leistungselektronik

    1995-09-01

    Most northern electrified lines in Schleswig-Holstein will be supplied with a.c. 16 2/3 Hz 15 kV traction energy from de-central converter station of Juebek which is under construction as a turn-key project. Converter technology based on semiconductor power elements will replace the conventional technology of rotating converters in the future. The paper gives a survey about importance and conception of Juebek converter station, incorporated technology and its state of construction. (orig.) [Deutsch] Zur Bahnenergieversorgung des noerdlichsten Bereiches der elektrifizierten Strecken in Schleswig-Holstein mit AC 16 2/3 Hz 15 kV wird zur Zeit das dezentrale Umrichterwerk Juebek als schluesselfertige Anlage errichtet. Die Umrichtertechnik auf der Basis leistungselektronischer Stromrichter wird in den kommenden Jahren die bisherige Maschinenumformertechnik abloesen. Der Beitrag gibt einen Ueberblick ueber die Bedeutung und das Konzept des Umrichterwerkes Juebek, die eingesetzte Technik und den Stand des Bauablaufes. (orig.)

  5. Three-phase Resonant DC-link Converter

    DEFF Research Database (Denmark)

    Munk-Nielsen, Stig

    The purpose of the project is to develop a three-phase resonant converter suitable for standard speed drives. The motivation for working with resonant converters is found in the problem of the standard converter type used today. In standard converter type Pulse Width Modulated-Voltage Source...... frequency three phase parallel resonant converter is realized....

  6. A Multiport Isolated DC-DC Converter

    OpenAIRE

    Tran, Yan-Kim; Dujic, Drazen

    2016-01-01

    This paper presents a multi-port isolated DC-DC converter for DC applications. A three-port structure is presented, characterized with full bidirectional power flow and simple control. Galvanic isolation is achieved by means of a multi-winding medium frequency transformer which is a part of a resonant LLC converter. To provide controllable power exchange with external DC ports, two out of three ports are equipped with additional bidirectional buck/boost stages. They serve to provide active po...

  7. AC – AC Converters for UPS

    Directory of Open Access Journals (Sweden)

    Rusalin Lucian R. Păun

    2008-05-01

    Full Text Available This paper propose a new control technique forsingle – phase AC – AC converters used for a on-line UPSwith a good dynamic response, a reduced-partscomponents, a good output characteristic, a good powerfactorcorrection(PFC. This converter no needs anisolation transformer. A power factor correction rectifierand an inverter with the proposed control scheme has beendesigned and simulated using Caspoc2007, validating theconcept.

  8. Torus bifurcations in multilevel converter systems

    DEFF Research Database (Denmark)

    Zhusubaliyev, Zhanybai T.; Mosekilde, Erik; Yanochkina, Olga O.

    2011-01-01

    This paper considers the processes of torus formation and reconstruction through smooth and nonsmooth bifurcations in a pulse-width modulated DC/DC converter with multilevel control. When operating in a regime of high corrector gain, converters of this type can generate structures of stable tori....... The paper also demonstrates how pairs of attracting and repelling tori emerge through border-collision torus-birth and border-collision torus-fold bifurcations. © 2011 World Scientific Publishing Company....

  9. Mathematical efficiency modeling of static power converters

    OpenAIRE

    Hoff Dupont, Fabrício; Zaragoza Bertomeu, Jordi; Rech, Cassiano; Pinheiro, José Renes

    2015-01-01

    This paper presents a review and a comparative analysis between mathematical models for the efficiency of power converters. Two different types of models are considered, being one for converters subject solely for output power variations, and a second one also considering input voltage variations. Both cases are particularly important for systems fed by renewable sources as photovoltaic panels or wind turbines. Knowledge of the appropriate models is of interest in the dev...

  10. Resonant Wave Energy Converters: Concept development

    International Nuclear Information System (INIS)

    The Resonant Wave Energy Converter (REWEC) is a device for converting sea wave energy to electrical energy. It belongs to the family of Oscillating Water Columns and is composed by an absorbing chamber connected to the open sea via a vertical duct. The paper gives a holistic view on the concept development of the device, starting from its implementation in the context of submerged breakwaters to the recently developed vertical breakwaters.

  11. Switching power converters medium and high power

    CERN Document Server

    Neacsu, Dorin O

    2013-01-01

    An examination of all of the multidisciplinary aspects of medium- and high-power converter systems, including basic power electronics, digital control and hardware, sensors, analog preprocessing of signals, protection devices and fault management, and pulse-width-modulation (PWM) algorithms, Switching Power Converters: Medium and High Power, Second Edition discusses the actual use of industrial technology and its related subassemblies and components, covering facets of implementation otherwise overlooked by theoretical textbooks. The updated Second Edition contains many new figures, as well as

  12. Design of fission neutron converter in HFETR

    International Nuclear Information System (INIS)

    In order to increase local fast neutron fluence rate in High Flux Engineering Test Reactor (HFETR), the fission neutron converter adopted the crisscross fuel rod whose fuel pellet was made of high fission density alloy UMo with 7% Mo. 62 fuel rods in the converter were arranged with triangle dot-matrix between outer tube with diameter of 6.3 mm and inner tube with diameter of 24 mm. And the converter has an irradiation hole with diameter of 20 mm in the center. The calculation result with MCNP shows that fast neutron (E>1 MeV) fluence rate of irradiated samples in the converter can achieve up to 3.34 × 1014 cm-2·s-1, which is about 40% higher than that in the HFETR core at the same position without converter. On the other hand, under the condition of design flow velocity and pressure, the analysis results with ANSYS/CFX show that the maximum permission power can reach 2.4 MW and the maximum power density of fuel pellet is S. 007 kW/cm3. Here, the cladding temperature of the fuel rod is 193.6 ℃, and the converter can fulfill the requirement of thermal-hydraulic design criteria of HFETR and flow instability will not occur. (authors)

  13. LHC Power Converters: A Precision Game

    CERN Multimedia

    2001-01-01

    The LHC test-bed, String 2, is close to commissioning and one important element to get a first chance to prove what it can do is the power converter system. In String 2 there are 16 converters, in the full LHC there will be almost 1800. This article takes a look at what is so special about the power converters for the LHC. The 13 000 Amps power converters with the watercooled cables going to the String 2 feedboxes. The LHC's superconducting magnets will be the pinnacle of high technology. But to work, they'll need the help of high-precision power converters to supply them with extremely stable DC current. Perfection will be the name of the game, with an accuracy of just 1-2 parts per million (ppm) required. LEP, for the sake of comparison, could live with 10-20 ppm. The LHC's power converters will be very different from those of LEP or the SPS since the new accelerator's magnets are mostly superconducting. That means that they require much higher currents at a lower voltage since superconductors have no re...

  14. Performance and Analysis of Modular Multilevel Converter

    Directory of Open Access Journals (Sweden)

    T.Yuvaraja

    2016-07-01

    Full Text Available The Modular Multilevel Converter (MMC represents an emerging topology with a scalable technology making high voltage and power capability possible. The MMC is built up by identical, but individually controllable sub modules. The Modular Multilevel Converter (MMC is a new topology for multilevel converters with potential for medium voltage and high voltage applications. Equivalent Circuit models and dynamic models for the MMC that provide a faithful representation of system behavior are quite complex given the large number of energy states and control variables. They are not particularly useful in studying the terminal behavior of the converter and for the development of an intuitive control approach to regulate power transfer. A control scheme with a new sub module capacitor voltage balancing method is also proposed in this paper. Modular multilevel converters, based on cascading of half bridge converter cells, can combine low switching frequency with low harmonic interference. They can be designed for high operating voltages without direct series connection of semiconductor element

  15. Simulation of Multi output Fly back Converter with Integrated Auxiliary Buck Converter with reduced components

    Directory of Open Access Journals (Sweden)

    J.KOMATHI

    2015-04-01

    Full Text Available The fly back converter has been widely used for multi outputs due to the simple structure and low cost in low-power applications. This paper presents a new multi output converter. It consists of a half-bridge inverter with boost converter in primary side and a fly back rectifier that is integrated with an auxiliary buck converter in secondary side. The boost converter is used to generate high voltage dc from Low voltage PV cells. The primary switches control the main output voltage and the secondary synchronous switches control the auxiliary output voltage. The main advantages of the proposed converter are that the transformer size can be reduced due to the less magnetizing offset current, all the power switches including synchronous ones can achieve the zero-voltage switching (ZVS and it has no output cross regulation problems. The circuit is simulated using MATLAB. The performance is verified with simulation results.

  16. Dual Converter Fed Open-End Transformer Topology with Parallel Converters and Integrated Magnetics

    DEFF Research Database (Denmark)

    Gohil, Ghanshyamsinh Vijaysinh; Bede, Lorand; Teodorescu, Remus;

    2016-01-01

    converter group comprises of two parallel Voltage Source Converters (VSCs), whose carrier signals are interleaved to improve the harmonic quality of the resultant switched output voltage of that converter group. However, an additional inductive component is required to suppress the circulating current...... procedure is also described. The volume and the losses of the proposed solution are compared with that of the state-of-art solution. The control of the proposed converter system is also discussed. The analysis has been verified by the simulation and experimental results....

  17. Cryogenic low noise and low dissipation multiplexing electronics, using HEMT+SiGe ASICs, for the readout of high impedance sensors: New version

    Energy Technology Data Exchange (ETDEWEB)

    Broïse, Xavier de la, E-mail: labroise@cea.fr; Lugiez, Francis; Bounab, Ayoub; Le Coguie, Alain

    2015-07-01

    High Electron Mobility Transistors (HEMTs), optimized by CNRS/LPN laboratory for ultra-low noise at very low temperature, have demonstrated their capacity to be used in place of Si JFETs when working temperatures below 100 K are required. We associated them with specific SiGe ASICs that we developed, to implement a complete readout channel able to read highly segmented high impedance detectors within a framework of very low thermal dissipation. Our electronics is dimensioned to read 4096 detection channels, of typically 1 MΩ impedance, and performs 32:1 multiplexing and amplifying, dissipating only 6 mW at 2.5 K and 100 mW at 15 K thanks to high impedance commuting of input stage, with a typical noise of 1 nV/√Hz at 1 kHz.

  18. 60 Gbit/s宽带电路交换ASIC芯片设计%Design of ASIC chips for 60 Gbit/s broadband circuit switching

    Institute of Scientific and Technical Information of China (English)

    孟李林

    2007-01-01

    文章提出了一种60 Gbit/s宽带电路交换专用集成电路(ASIC)芯片的设计实现方案.针对设计芯片速度快、规模大和功耗大等特点,给出了采用流水线设计思想和优化结构处理技术的电路设计解决方案.同时还给出了采用现场可编程门阵列(FPGA)芯片对设计电路进行功能验证的结果和ASIC流片的基本数据.

  19. A New Hard Switching Bidirectional Converter With High Power Density

    OpenAIRE

    Bahador Fani; Majid Delshad; Daryoosh Nazarpour

    2010-01-01

    In this paper, a new isolated dc-dc bidirectional converter is proposed. This converter consists of two transformers (flyback and forward) and only one switch in primary side and one switch in secondary side of transformers. In this converter energy transfers to the output in both on and off switch states so power density of this converter is high This converter controlled by PWM signal. Also this converter operates over a wide input voltage range. Theoretical analysis is presented and compu...

  20. Combined, but not individual, blockade of ASIC3, P2X, and EP4 receptors attenuates the exercise pressor reflex in rats with freely perfused hindlimb muscles.

    Science.gov (United States)

    Stone, Audrey J; Copp, Steven W; Kim, Joyce S; Kaufman, Marc P

    2015-12-01

    In healthy humans, tests of the hypothesis that lactic acid, PGE2, or ATP plays a role in evoking the exercise pressor reflex proved controversial. The findings in humans resembled ours in decerebrate rats that individual blockade of the receptors to lactic acid, PGE2, and ATP had only small effects on the exercise pressor reflex provided that the muscles were freely perfused. This similarity between humans and rats prompted us to test the hypothesis that in rats with freely perfused muscles combined receptor blockade is required to attenuate the exercise pressor reflex. We first compared the reflex before and after injecting either PPADS (10 mg/kg), a P2X receptor antagonist, APETx2 (100 μg/kg), an activating acid-sensing ion channel 3 (ASIC) channel antagonist, or L161982 (2 μg/kg), an EP4 receptor antagonist, into the arterial supply of the hindlimb of decerebrated rats. We then examined the effects of combined blockade of P2X receptors, ASIC3 channels, and EP4 receptors on the exercise pressor reflex using the same doses, intra-arterial route, and time course of antagonist injections as those used for individual blockade. We found that neither PPADS (n = 5), APETx2 (n = 6), nor L161982 (n = 6) attenuated the reflex. In contrast, combined blockade of these receptors (n = 7) attenuated the peak (↓27%, P channels, and EP4 receptors on the endings of thin fiber muscle afferents is required to attenuate the exercise pressor reflex in rats with freely perfused hindlimbs. PMID:26472871

  1. Radiation hardness tests and characterization of the CLARO-CMOS, a low power and fast single-photon counting ASIC in 0.35 micron CMOS technology

    Energy Technology Data Exchange (ETDEWEB)

    Fiorini, M., E-mail: fiorini@fe.infn.it [Università degli Studi di Ferrara and INFN Sezione di Ferrara (Italy); Andreotti, M.; Baldini, W.; Calabrese, R. [Università degli Studi di Ferrara and INFN Sezione di Ferrara (Italy); Carniti, P.; Cassina, L. [Università degli Studi di Milano Bicocca and INFN Sezione di Milano Bicocca (Italy); Cotta Ramusino, A. [Università degli Studi di Ferrara and INFN Sezione di Ferrara (Italy); Giachero, A.; Gotti, C. [Università degli Studi di Milano Bicocca and INFN Sezione di Milano Bicocca (Italy); Luppi, E. [Università degli Studi di Ferrara and INFN Sezione di Ferrara (Italy); Maino, M. [Università degli Studi di Milano Bicocca and INFN Sezione di Milano Bicocca (Italy); Malaguti, R. [Università degli Studi di Ferrara and INFN Sezione di Ferrara (Italy); Pessina, G. [Università degli Studi di Milano Bicocca and INFN Sezione di Milano Bicocca (Italy); Tomassetti, L. [Università degli Studi di Ferrara and INFN Sezione di Ferrara (Italy)

    2014-12-01

    The CLARO-CMOS is a prototype ASIC that allows fast photon counting with 5 ns peaking time, a recovery time to baseline smaller than 25 ns, and a power consumption of less than 1 mW per channel. This chip is capable of single-photon counting with multi-anode photomultipliers and finds applications also in the read-out of silicon photomultipliers and microchannel plates. The prototype is realized in AMS 0.35 micron CMOS technology. In the LHCb RICH environment, assuming 10 years of operation at the nominal luminosity expected after the upgrade in Long Shutdown 2 (LS2), the ASIC must withstand a total fluence of about 6×10{sup 12} 1 MeV n{sub eq}/cm{sup 2} and a total ionizing dose of 400 krad. A systematic evaluation of the radiation effects on the CLARO-CMOS performance is therefore crucial to ensure long term stability of the electronics front-end. The results of multi-step irradiation tests with neutrons and X-rays up to the fluence of 10{sup 14} cm{sup −2} and a dose of 4 Mrad, respectively, are presented, including measurement of single event effects during irradiation and chip performance evaluation before and after each irradiation step. - Highlights: • CLARO chip capable of single-photon counting with 5 ns peaking time. • Chip irradiated up to very high neutron, proton and X-rays fluences, as expected for upgraded LHCb RICH detectors. • No significant performance degradation is observed after irradiation.

  2. Efficiency of Thermionic and Thermoelectric Converters

    Science.gov (United States)

    Gerstenmaier, York Christian; Wachutka, Gerhard

    2007-02-01

    Thermoelectric and thermionic converters — also in micro- and nano-meter design — are considered for power generation and cooling applications. The potential of thermionic vacuum gap converters is investigated precisely by a new advanced theory with inclusion of backward currents from the 2nd electrode, losses due to thermal radiation and ohmic resistance in the electrodes, tunneling through the gap, image forces, and space charge effects. The efficiency of nano-meter gap thermionic converters is by far higher than for thermoelectric devices (including nano-structured superlattices) for operating temperatures above 800°K, however, there is no chance of realization with today's technology. For a vacuum gap width of about 1 μm the performance is higher than for hypothetical bulk- thermoelectric generators (TEGs) with ZT = 1 for T > 1000°K and also higher than for hypothetical nano-structured superlattices (ZT = 2.4) for T > 1200°K. A thermionic converter with gap width of 5μm has lower performance than a TEG with ZT = 1, however, also operates at T > 1200°K. Reasonable performance of thermionic converters at T ⩽ 500°K necessitates materials with workfunctions ⩽ 0.5 eV.

  3. Ac-dc converter firing error detection

    International Nuclear Information System (INIS)

    Each of the twelve Booster Main Magnet Power Supply modules consist of two three-phase, full-wave rectifier bridges in series to provide a 560 VDC maximum output. The harmonic contents of the twelve-pulse ac-dc converter output are multiples of the 60 Hz ac power input, with a predominant 720 Hz signal greater than 14 dB in magnitude above the closest harmonic components at maximum output. The 720 Hz harmonic is typically greater than 20 dB below the 500 VDC output signal under normal operation. Extracting specific harmonics from the rectifier output signal of a 6, 12, or 24 pulse ac-dc converter allows the detection of SCR firing angle errors or complete misfires. A bandpass filter provides the input signal to a frequency-to-voltage converter. Comparing the output of the frequency-to-voltage converter to a reference voltage level provides an indication of the magnitude of the harmonics in the ac-dc converter output signal

  4. Synchronous Control of Modular Multilevel Converters

    DEFF Research Database (Denmark)

    Oleschuk, Valentin; Blaabjerg, Frede; Bose, Bimal K.

    2002-01-01

    A novel method of direct synchronous pulsewidth modulation (PWM) is applied for control of modular multilevel converters consisting from three standard triphase inverter modules along with an 0.33 p.u. output transformer. The proposed method provides synchronisation of the voltage waveforms...... for determination of the pulse patterns, have been analysed and compared using simulations of the systems with low switching frequencies, which normally are used in high power systems....... for each module and the composed voltage at the output of the converter. Multilevel output voltage of the converter has quarter-wave symmetry during the whole range including the zone of overmodulation. Both continuous and discontinuous versions of synchronous PWM, based on vector approach...

  5. Metamaterial polarization converter analysis: limits of performance

    DEFF Research Database (Denmark)

    Markovich, Dmitry L.; Andryieuski, Andrei; Zalkovskij, Maksim;

    2013-01-01

    In this paper, we analyze the theoretical limits of a metamaterial-based converter with orthogonal linear eigenpolarizations that allow linear-to-elliptical polarization transformation with any desired ellipticity and ellipse orientation. We employ the transmission line approach providing a needed...... level of the design generalization. Our analysis reveals that the maximal conversion efficiency for transmission through a single metamaterial layer is 50 %, while the realistic reflection configuration can give the conversion efficiency up to 90 %. We show that a double layer transmission converter...... and a single layer with a ground plane can have 100 % polarization conversion efficiency. We tested our conclusions numerically reaching the designated limits of efficiency using a simple metamaterial design. Our general analysis provides useful guidelines for the metamaterial polarization converter design...

  6. SIG Galileo final converter technical summary report

    International Nuclear Information System (INIS)

    The report is primarily concerned with the work performed for DOE on converter development and fabrication for the NASA Galileo Jupiter mission as a DOE prime contractor with interface primarily with Teledyne Energy Systems. The activities reported on were directed toward design, analysis and testing of modules and converters SN-1 thru SN-7 and attendant Quality Control and Reliability effort. Although assembly and testing of SN-1 was not accomplished due to the stop work order, the design was virtually completed and a significant amount of subcontracting and manufacturing of both module and converter components was underway. These subcontracting and manufacturing activities were selectively closed down depending upon degree of completion and material or hardware potential usage in the Technology Program

  7. Power system applications for PASC converter systems

    Energy Technology Data Exchange (ETDEWEB)

    Donnelly, M.K. [Pacific Northwest Lab., Richland, WA (United States); Johnson, R.M. [Montana State Univ., Bozeman, MT (United States)

    1994-04-01

    This paper shows, using computer EMTP simulations, some preliminary results of applying pulse amplitude synthesis and control (PASC) technology to single-source level voltage converter system. The method can be applied to any single terminal pair source with appropriate modifications in power extraction interface and computer control program to match source and load impedance characteristics. The PASC realization as discussed here employs banks of transformers, one bank per phase, in which the primaries are connected in parallel through a switch matrix to the dc source. Two opposite polarity primaries per transformer are pulsed alternatively in time to produce an oscillatory sinusoidal output waveform. PASC conversion system capabilities to produce both leading and lagging power factor power output in single-phase and three-phase {Delta} or Y configurations are illustrated. EMTP simulations are used to demonstrate the converter capabilities. Also included are discussions regarding harmonics and potential control strategies to adapt the converter to an application or to minimize harmonics.

  8. Self-oscillating resonant power converter

    DEFF Research Database (Denmark)

    2014-01-01

    The present invention relates to resonant power converters and inverters comprising a self-oscillating feedback loop coupled from a switch output to a control input of a switching network comprising one or more semiconductor switches. The self-oscillating feedback loop sets a switching frequency...... of the power converter and comprises a first intrinsic switch capacitance coupled between a switch output and a control input of the switching network and a first inductor. The first inductor is coupled in-between a first bias voltage source and the control input of the switching network and has...... a substantially fixed inductance. The first bias voltage source is configured to generate an adjustable bias voltage applied to the first inductor. The output voltage of the power converter is controlled in a flexible and rapid manner by controlling the adjustable bias voltage....

  9. CMOS Integrated Capacitive DC-DC Converters

    CERN Document Server

    Van Breussegem, Tom

    2013-01-01

    This book provides a detailed analysis of all aspects of capacitive DC-DC converter design: topology selection, control loop design and noise mitigation. Readers will benefit from the authors’ systematic overview that starts from the ground up, in-depth circuit analysis and a thorough review of recently proposed techniques and design methodologies.  Not only design techniques are discussed, but also implementation in CMOS is shown, by pinpointing the technological opportunities of CMOS and demonstrating the implementation based on four state-of-the-art prototypes.  Provides a detailed analysis of all aspects of capacitive DC-DC converter design;  Analyzes the potential of this type of DC-DC converter and introduces a number of techniques to unleash their full potential; Combines system theory with practical implementation techniques; Includes unique analysis of CMOS technology for this application; Provides in-depth analysis of four fabricated prototypes.

  10. Single phase AC-DC power factor corrected converter with high frequency isolation using buck converter

    Directory of Open Access Journals (Sweden)

    R. Ramesh,

    2014-03-01

    Full Text Available Single phase ac-dc converters having high frequency isolation are implemented in buck, boost, buck-boost configuration with improving the power quality in terms of reducing the harmonics of input current. The paperpropose the circuit configuration, control mechanism, and simulation result for the single phase ac-dc converter.

  11. Efficient polarization converter for projection displays.

    Science.gov (United States)

    Yip, W C; Huang, H C; Kwok, H S

    1997-09-01

    In the waveguiding limit, a twisted nematic liquid crystal cell behaves as an achromatic polarization rotator. We propose and demonstrate the application of such a polarization rotator to convert unpolarized light into linearly polarized light with almost 100% efficiency. This polarization converter has a 2:1 aspect ratio, which is close to the 16:9 ratio for modern televisions. It can be used therefore in a projection display with polarization-dependent light valves such as a liquid crystal light valve. Both transmittive and reflective light valves can be used. The temperature dependence of the achromatic polarization rotator is also studied. PMID:18259503

  12. A linear temperature-to-frequency converter

    DEFF Research Database (Denmark)

    Løvborg, Leif

    1965-01-01

    , and that the maximum value of the temperature-frequency coefficient beta in this point is-1/3 alpha, where a is the temperature coefficient of the thermistor at the corresponding temperature. Curves showing the range in which the converter is expected to be linear to within plusmn0.1 degC are given. A laboratory......-built converter having beta = 1.0% degC-1 at 25degC is found to be linear to within plusmn0. 1 degC from 10 to 40degC....

  13. Electrodes For Alkali-Metal Thermoelectric Converters

    Science.gov (United States)

    Williams, Roger M.; Wheeler, Bob L.; Jeffries-Nakamura, Barbara; Lamb, James L.; Bankston, C. Perry; Cole, Terry

    1989-01-01

    Combination of thin, porous electrode and overlying collector grid reduces internal resistance of alkali-metal thermoelectric converter cell. Low resistance of new electrode and grid boosts power density nearly to 1 W/cm2 of electrode area at typical operating temperatures of 1,000 to 1,300 K. Conductive grid encircles electrode film on alumina tube. Bus wire runs along tube to collect electrical current from grid. Such converters used to transform solar, nuclear, and waste heat into electric power.

  14. Solar energy converter using surface plasma waves

    Science.gov (United States)

    Anderson, L. M. (Inventor)

    1984-01-01

    Sunlight is dispersed over a diffraction grating formed on the surface of a conducting film on a substrate. The angular dispersion controls the effective grating period so that a matching spectrum of surface plasmons is excited for parallel processing on the conducting film. The resulting surface plasmons carry energy to an array of inelastic tunnel diodes. This solar energy converter does not require different materials for each frequency band, and sunlight is directly converted to electricity in an efficient manner by extracting more energy from the more energetic photons.

  15. Efficient modelling of a modular multilevel converter

    DEFF Research Database (Denmark)

    El-Khatib, Walid Ziad; Holbøll, Joachim; Rasmussen, Tonny Wederberg

    2013-01-01

    Looking at the near future, we see that offshore wind penetration into the electrical grid will continue increasing rapidly. Until very recently, the trend has been to place the offshore wind farms close to shore within the reach for transmission using HVAC cables but for larger distances HVDC...... calculated for the converter. Time-domain simulations on a MMC HVDC test system are performed in the PSCAD/EMTDC software environment based on the new model. The results demonstrate that the modeled MMC-HVDC system with or without converter transformer is able to operate under specific fault conditions....

  16. Is China Ready for Full Yuan Convertibility?

    Institute of Scientific and Technical Information of China (English)

    2011-01-01

    Although China has made headway in reforming the exchange rate regime of its currency,the yuan,and expanding the use of it in cross-border trade during the past year,the yuan is far from fully convertible.Huang Yiping,a professor at the National School of Development of Peking University,said in an article for Beijing Review that China has the conditions for capital account liberalization and should strive for basic convertibility within five years. Edited excerpts follow

  17. All linear optical devices are mode converters

    OpenAIRE

    Miller, David A. B.

    2012-01-01

    We show that every linear optical component can be completely described as a device that converts one set of orthogonal input modes, one by one, to a matching set of orthogonal output modes. This result holds for any linear optical structure with any specific variation in space and/or time of its structure. There are therefore preferred orthogonal "mode converter" basis sets of input and output functions for describing any linear optical device, in terms of which the device can be described b...

  18. Combination solar photovoltaic heat engine energy converter

    Science.gov (United States)

    Chubb, Donald L.

    1987-01-01

    A combination solar photovoltaic heat engine converter is proposed. Such a system is suitable for either terrestrial or space power applications. The combination system has a higher efficiency than either the photovoltaic array or the heat engine alone can attain. Advantages in concentrator and radiator area and receiver mass of the photovoltaic heat engine system over a heat-engine-only system are estimated. A mass and area comparison between the proposed space station organic Rankine power system and a combination PV-heat engine system is made. The critical problem for the proposed converter is the necessity for high temperature photovoltaic array operation. Estimates of the required photovoltaic temperature are presented.

  19. Faults and Diagnosis Systems in Power Converters

    DEFF Research Database (Denmark)

    Lee, Kyo-Beum; Choi, Uimin

    2014-01-01

    A power converter is needed in almost all kinds of renewable energy systems and drive systems. It is used both for controlling the renewable source and for interfacing with the load, which can be grid-connected or working in standalone mode. Further, it drives the motors efficiently. Increasing...... efforts have been put into making these systems better in terms of reliability in order to achieve high power source availability, reduce the cost of energy and also increase the reliability of overall systems. Among the components used in power converters, a power device and a capacitor fault occurs most...

  20. Bidirectional converter interface for a battery energy storage test bench

    DEFF Research Database (Denmark)

    Trintis, Ionut; Thomas, Stephan; Blank, Tobias;

    2011-01-01

    This paper presents the bidirectional converter interface for a 6 kV battery energy storage test bench. The power electronic interface consists a two stage converter topology having a low voltage dc-ac grid connected converter and a new dual active bridge dc-dc converter with high transformation...

  1. Integrated multilevel converter and battery management

    OpenAIRE

    K. Wilkie; Stone, D.; Bingham, C.; Foster, M.

    2008-01-01

    A cascaded H-bridge multilevel converter is proposed as a BLDC drive incorporating real-time battery management. Intelligent H-bridges are used to monitor battery cells whilst simultaneously increasing their performance by reducing the variation between cells and controlling their discharge profiles.

  2. Angiotensin converting enzyme inhibitor induced hyperkalaemic paralysis

    OpenAIRE

    Dutta., D; Fischler, M; McClung, A

    2001-01-01

    Secondary hyperkalaemic paralysis is a rare condition often mimicking the Guillain-Barré syndrome. There have been a few case reports of hyperkalaemia caused by renal failure, trauma, and drugs where the presentation has been with muscle weakness. A case of hyperkalaemic paralysis caused by an angiotensin converting enzyme inhibitor is reported.


Keywords: hyperkalaemia; paralysis; ACE inhibitors

  3. China to Gradually Make Capital Account Convertible

    Institute of Scientific and Technical Information of China (English)

    2006-01-01

    @@ China is pushing forward its currency Renminbi (RMB)'s capital account convertibility gradually and in a stable manner, said an official with the State Administration of Foreign Exchange (SAFE), ruling out both an adventurous leap and conservative cautiousness, according to a report of Xinhua on April 12.

  4. China to Gradually Make Capital Account Convertible

    Institute of Scientific and Technical Information of China (English)

    2006-01-01

      China is pushing forward its currency Renminbi (RMB)'s capital account convertibility gradually and in a stable manner, said an official with the State Administration of Foreign Exchange (SAFE), ruling out both an adventurous leap and conservative cautiousness, according to a report of Xinhua on April 12.……

  5. Online Scheduling in Distributed Message Converter Systems

    NARCIS (Netherlands)

    Risse, Thomas; Wombacher, Andreas; Surridge, Mike; Taylor, Steve; Aberer, Karl

    2001-01-01

    The optimal distribution of jobs among hosts in distributed environments is an important factor to achieve high performance. The optimal strategy depends on the application. In this paper we present a new online scheduling strategy for distributed EDI converter system. The strategy is based on the B

  6. Impedance interactions in bidirectional cascaded converter

    DEFF Research Database (Denmark)

    Tian, Yanjun; Loh, Poh Chiang; Chen, Zhe;

    2016-01-01

    here for showing that forward and reverse interactions are prominently different in terms of dynamics and stability, even though the cascaded converter control remains unchanged. The concluded findings have been verified by simulation and experimental results, from which, important guidelines have been...

  7. Catalytic Converters Maintain Air Quality in Mines

    Science.gov (United States)

    2014-01-01

    At Langley Research Center, engineers developed a tin-oxide based washcoat to prevent oxygen buildup in carbon dioxide lasers used to detect wind shears. Airflow Catalyst Systems Inc. of Rochester, New York, licensed the technology and then adapted the washcoat for use as a catalytic converter to treat the exhaust from diesel mining equipment.

  8. Power electronics converters for wind turbine systems

    DEFF Research Database (Denmark)

    Blaabjerg, Frede; Liserre, Marco; Ma, Ke

    2011-01-01

    The steady growth of installed wind power which reached 200 GW capacity in 2010, together with the up-scaling of the single wind turbine power capability - 7 MW’s has been announced by manufacturers - has pushed the research and development of power converters towards full scale power conversion,...

  9. Power Electronics Converters for Wind Turbine Systems

    DEFF Research Database (Denmark)

    Blaabjerg, Frede; Liserre, Marco; Ma, Ke

    2012-01-01

    The steady growth of installed wind power together with the upscaling of the single wind turbine power capability has pushed the research and development of power converters toward full-scale power conversion, lowered cost pr kW, increased power density, and also the need for higher reliability. ...

  10. Generalized modular multilevel converter and modulation

    DEFF Research Database (Denmark)

    Liu, Hui; Loh, Poh Chiang; Blaabjerg, Frede

    2014-01-01

    Modular multilevel converter (MMC) has gained popularity recently with its modulation, capacitor voltage balancing and circulating current issues widely discussed. Contributing to this effort, a study is presented here to show how the MMC topology can be derived from the viewpoint of two series c...

  11. Performance Evaluation of Wave Energy Converters

    DEFF Research Database (Denmark)

    Pecher, Arthur

    stages, and results thereby in a need for specific test objectives and procedures for each development stage. This PhD thesis has looked into the different development stages and more specifically in the performance assessment of wave energy converters based on tank testing and sea trials. The objective...

  12. Performance Evaluation of Wave Energy Converters

    DEFF Research Database (Denmark)

    Pecher, Arthur

    stages, and results thereby in a need for specific testobjectives and procedures for each development stage. This PhD thesis has looked into the different development stages and more specifically in the performance assessment of wave energy converters based on tank testing and sea trials. The objective...

  13. Efficient, lightweight dc/dc switching converter

    Science.gov (United States)

    Cuk, S.; Middlebrook, R. D.

    1981-01-01

    Converters have input properties of boost power stage and output properties of buck power stage, yet they perform general conversion function with high efficiency. Other features include non-pulsating input/output currents, use of capacitive energy transfer, low output voltage ripple, reduced EMI, and small size.

  14. Convertible bonds and bank risk-taking

    NARCIS (Netherlands)

    N. Martynova; E. Perotti

    2015-01-01

    We study how contingent capital that converts in equity ahead of default affects bankrisk-shifting. Going concern conversion restores equity value in highly levered states,thus reducing heightened risk incentives. In contrast, conversion at default for traditionalbail-inable debt has no effect on en

  15. Mathematical modeling of the flash converting process

    Energy Technology Data Exchange (ETDEWEB)

    Sohn, H.Y.; Perez-Tello, M.; Riihilahti, K.M. [Utah Univ., Salt Lake City, UT (United States)

    1996-12-31

    An axisymmetric mathematical model for the Kennecott-Outokumpu flash converting process for converting solid copper matte to copper is presented. The model is an adaptation of the comprehensive mathematical model formerly developed at the University of Utah for the flash smelting of copper concentrates. The model incorporates the transport of momentum, heat, mass, and reaction kinetics between gas and particles in a particle-laden turbulent gas jet. The standard k-{epsilon} model is used to describe gas-phase turbulence in an Eulerian framework. The particle-phase is treated from a Lagrangian viewpoint which is coupled to the gas-phase via the source terms in the Eulerian gas-phase governing equations. Matte particles were represented as Cu{sub 2}S yFeS, and assumed to undergo homogeneous oxidation to Cu{sub 2}O, Fe{sub 3}O{sub 4}, and SO{sub 2}. A reaction kinetics mechanism involving both external mass transfer of oxygen gas to the particle surface and diffusion of oxygen through the porous oxide layer is proposed to estimate the particle oxidation rate Predictions of the mathematical model were compared with the experimental data collected in a bench-scale flash converting facility. Good agreement between the model predictions and the measurements was obtained. The model was used to study the effect of different gas-injection configurations on the overall fluid dynamics in a commercial size flash converting shaft. (author)

  16. Converting Student Support Services to Online Delivery.

    Science.gov (United States)

    Brigham, David E.

    2001-01-01

    Uses a systems framework to analyze the creation of student support services for distance education at Regents College: electronic advising, electronic peer network, online course database, online bookstore, virtual library, and alumni services website. Addresses the issues involved in converting distance education programs from print-based and…

  17. Hybrid switch for resonant power converters

    Science.gov (United States)

    Lai, Jih-Sheng; Yu, Wensong

    2014-09-09

    A hybrid switch comprising two semiconductor switches connected in parallel but having different voltage drop characteristics as a function of current facilitates attainment of zero voltage switching and reduces conduction losses to complement reduction of switching losses achieved through zero voltage switching in power converters such as high-current inverters.

  18. Development of the Wave Energy Converter

    DEFF Research Database (Denmark)

    Kofoed, Jens Peter; Frigaard, Peter; Sørensen, Hans Christian;

    2000-01-01

    The development of the wave energy converter Wave Dragon (WD) is presented. The WD is based on the overtopping principle. Initially a description of the WD is given. Then the development over time in terms of the various research and development projects working with the concept is described...

  19. Aquabuoy Wave Energy Converter

    DEFF Research Database (Denmark)

    Vicinanza, Diego; Margheritini, Lucia; Frigaard, Peter

    The work reported here is part of the contract agreement between the Finavera Renewables Ocean Energy Ltd. and the Department of Civil Engineering Hydraulics and Coastal Engineering Laboratory to instrument a model in scale 1:10 to prototype of the AquaBuOY (AB) wave energy converter and to analyse...

  20. A New Hard Switching Bidirectional Converter With High Power Density

    Directory of Open Access Journals (Sweden)

    Bahador Fani

    2010-01-01

    Full Text Available In this paper, a new isolated dc-dc bidirectional converter is proposed. This converter consists of two transformers (flyback and forward and only one switch in primary side and one switch in secondary side of transformers. In this converter energy transfers to the output in both on and off switch states so power density of this converter is high This converter controlled by PWM signal. Also this converter operates over a wide input voltage range. Theoretical analysis is presented and computer simulation and experimental results verify the converter analysis.

  1. A low-voltage boost converter using a forward converter with integrated Meissner oscillator

    International Nuclear Information System (INIS)

    This paper describes a novel boost converter to be used with energy harvesters that provide only low output voltages. The device is self-supplied from electric power delivered to its input. With peak power conversion efficiencies above 30% at start-up voltages down to 10 mV this circuit sets best values in comparison with the state-of-the-art. This is achieved by the novel combination of a Meissner oscillator, used as stand-alone in most low-voltage step-up converters today, with a forward converter usually applied in high power systems

  2. Multi-output DC-DC converters based on diode-clamped converters configuration

    DEFF Research Database (Denmark)

    Nami, A.; Zare, F.; Ghosh, A.;

    2010-01-01

    for a diode-clamed inverter in the grid connection systems, where boosting low rectified output-voltage and series DC link capacitors is required. To verify the proposed topology, steady-state and dynamic analyses of a MOB converter are examined. A simple control strategy has been proposed to demonstrate...... the performance of the proposed topology for a double-output boost converter. The topology and its control strategy can easily be extended to offer multiple outputs. Simulation and experimental results are presented to show the validity of the control strategy for the proposed converter....

  3. A low-voltage boost converter using a forward converter with integrated Meissner oscillator

    Science.gov (United States)

    Woias, P.; Islam, M.; Heller, S.; Roth, R.

    2013-12-01

    This paper describes a novel boost converter to be used with energy harvesters that provide only low output voltages. The device is self-supplied from electric power delivered to its input. With peak power conversion efficiencies above 30% at start-up voltages down to 10 mV this circuit sets best values in comparison with the state-of-the-art. This is achieved by the novel combination of a Meissner oscillator, used as stand-alone in most low-voltage step-up converters today, with a forward converter usually applied in high power systems.

  4. Research on Converter Valve Overvoltage Mechanism and Calculation Conditions of ± 800 kV Converter Station

    Institute of Scientific and Technical Information of China (English)

    WANG Dongju; DENG Xu; ZHOU Hao; CHEN Xilei; XU Anwen; SHEN Yang

    2012-01-01

    The thyristor converter valve is the key equipment of commutation in ultra high voltage direct current (UHVDC) transmission systems. Owing to the limited voltage and current overload capacity, any transient overvoltage may cause permanent damage to the thyristor converter valve. In order to specify the converter valves' overvoltage levels of the ±800 kV UHVDC transmission system, the mechanisms of its generation and development are discussed in detail, from which the calculation conditions for the highest stresses of the converter valves are given. Finally, the converter valve's overvoltage of Xiluodu UHV converter station is simulated. The research results show that the overvoltages of the converter valves in the upper 3-pulse group of the high voltage(HV) and low voltage(LV) 12-pulse converter are generated jointly by the DC line voltage and the converter transformer's voltage at its valve side. Calculation conditions for this overvoltage are: DC system in bipolar operation mode, converter station operating as rectifier, maximum DC system operating voltage, minimum DC current, minimum AC system voltage of the converter station. Furthermore, the other converter valves' overvoltage is caused by the phase-to-phase switching surge generated at the converter station's AC side, penetrating into the valve hall. Overall, the maximum overvoltages of Xiluodu converter station in the upper 3-pulse group of the HV and LV 12-pulse converter are 379.1 kV and 384.9 kV, for other converter valves the maximum overvoltage is 375.3 kV.

  5. Imbalance between pulmonary angiotensin-converting enzyme and angiotensin-converting enzyme 2 activity in acute respiratory distress syndrome

    NARCIS (Netherlands)

    Wosten-van Asperen, Roelie M.; Bos, Albert; Bem, Reinout A.; Dierdorp, Barbara S.; Dekker, Tamara; van Goor, Harry; Kamilic, Jelena; van der Loos, Chris M.; van den Berg, Elske; Bruijn, Martijn; van Woensel, Job B.; Lutter, Rene

    2013-01-01

    Objective: Angiotensin-converting enzyme and its effector peptide angiotensin II have been implicated in the pathogenesis of acute respiratory distress syndrome. Recently, angiotensin-converting enzyme 2 was identified as the counter-regulatory enzyme of angiotensin-converting enzyme that converts a

  6. Efficient Wide Range Converters (EWiRaC): A new family of high efficient AC-DC Converters

    DEFF Research Database (Denmark)

    Petersen, Lars; Andersen, Michael Andreas E.

    2006-01-01

    The performance in terms of efficiency of the existing power supplies used for PFC is very dependent on the input voltage range. The boost converter is the most commonly used PFC converter because of its simplicity and high efficiency. But, the boost converter as well as other known converters...... the converter topology according to the input voltage. This new converter type has been named: efficient wide range converter (EWiRaC). The performance of the EWiRaC is experimental verified in a universal input range (90-270VAC) application with an output voltage of 185VDC capable of 500W output power. The EWi...

  7. TiConverter: A training image converting tool for multiple-point geostatistics

    Science.gov (United States)

    Fadlelmula F., Mohamed M.; Killough, John; Fraim, Michael

    2016-11-01

    TiConverter is a tool developed to ease the application of multiple-point geostatistics whether by the open source Stanford Geostatistical Modeling Software (SGeMS) or other available commercial software. TiConverter has a user-friendly interface and it allows the conversion of 2D training images into numerical representations in four different file formats without the need for additional code writing. These are the ASCII (.txt), the geostatistical software library (GSLIB) (.txt), the Isatis (.dat), and the VTK formats. It performs the conversion based on the RGB color system. In addition, TiConverter offers several useful tools including image resizing, smoothing, and segmenting tools. The purpose of this study is to introduce the TiConverter, and to demonstrate its application and advantages with several examples from the literature.

  8. Analog-digital converters for industrial applications including an introduction to digital-analog converters

    CERN Document Server

    Ohnhäuser, Frank

    2015-01-01

    This book offers students and those new to the topic of analog-to-digital converters (ADCs) a broad introduction, before going into details of the state-of-the-art design techniques for SAR and DS converters, including the latest research topics, which are valuable for IC design engineers as well as users of ADCs in applications. The book then addresses important topics, such as correct connectivity of ADCs in an application, the verification, characterization and testing of ADCs that ensure high-quality end products. Analog-to-digital converters are the central element in any data processing system and regulation loops such as modems or electrical motor drives. They significantly affect the performance and resolution of a system or end product. System development engineers need to be familiar with the performance parameters of the converters and understand the advantages and disadvantages of the various architectures. Integrated circuit development engineers have to overcome the problem of achieving high per...

  9. Enhancing the efficiency of silicon Raman converters

    Science.gov (United States)

    Vermeulen, Nathalie; Sipe, John E.; Thienpont, Hugo

    2010-05-01

    We propose a silicon ring Raman converter in which the spatial variation of the Raman gain along the ring for TE polarization is used to quasi-phase-match the CARS process. If in addition the pump, Stokes, and anti-Stokes waves involved in the CARS interaction are resonantly enhanced by the ring structure, the Stokes-to-anti-Stokes conversion efficiency can be increased by at least four orders of magnitude over that of one-dimensional perfectly phase-matched silicon Raman converters, and can reach values larger than unity with relatively low input pump intensities. These improvements in conversion performance could substantially expand the practical applicability of the CARS process for optical wavelength conversion.

  10. Integrated mode converter for mode division multiplexing

    Science.gov (United States)

    Perez-Galacho, Diego; Alonso-Ramos, Carlos Alberto; Marris-Morini, Delphine; Vakarin, Vladyslav; Le Roux, Xavier; Ortega-Moñux, Alejandro; Wangüemert-Perez, Juan Gonzalo; Vivien, Laurent

    2016-05-01

    The ever growing demands of bandwidth in optical communication systems are making traditional Wavelength Division Multiplexing (WDM) based systems to reach its limit. In order to cope with future bandwidth demand is necessary to use new levels of orthogonality, such as the waveguide mode or the polarization state. Mode Division Multiplexing (MDM) has recently attracted attention as a possible solution to increase aggregate bandwidth. In this work we discuss the proposition a of mode converter that can cover the whole C-Band of optical communications. The Mode Converter is based on two Multimode Interference (MMI) couplers and a phase shifter. Insertion loss (IL) below 0.2 dB and Extinction ratio (ER) higher than 20 dB in a broad bandwidth range of 1.5 μm to 1.6 μm have been estimated. The total length of the device is less than 30 μm.

  11. Strained quantum well photovoltaic energy converter

    Science.gov (United States)

    Freundlich, Alexandre (Inventor); Renaud, Philippe (Inventor); Vilela, Mauro Francisco (Inventor); Bensaoula, Abdelhak (Inventor)

    1998-01-01

    An indium phosphide photovoltaic cell is provided where one or more quantum wells are introduced between the conventional p-conductivity and n-conductivity indium phosphide layer. The approach allows the cell to convert the light over a wider range of wavelengths than a conventional single junction cell and in particular convert efficiently transparency losses of the indium phosphide conventional cell. The approach hence may be used to increase the cell current output. A method of fabrication of photovoltaic devices is provided where ternary InAsP and InGaAs alloys are used as well material in the quantum well region and results in an increase of the cell current output.

  12. Serum angiotensin converting enzyme in pneumonias.

    OpenAIRE

    Kerttula, Y; Weber, T H

    1986-01-01

    Serum concentrations of angiotensin converting enzyme (ACE) were studied in pneumonias caused by different pathogens and in cases in which the aetiology could not be defined. In all aetiological groups, except in viral pneumonia, there was a significant increase in ACE during recovery (p less than 0.001). In several patients the lowest values during the acute phase of disease and the highest values during recovery were outside the reference limits. In cases with known aetiology the highest AC...

  13. Emergency braking for free piston energy converters

    OpenAIRE

    West, M.; Long, S.; Wang, J; Bingham, Chris; Howe, D.

    2005-01-01

    Free piston energy converters are a potential technology for future hybrid vehicles, as well as stationary power generation applications. A candidate 2-stroke system comprises of two opposing combustion chambers with a common piston rod, and integrated with a tubular permanent magnet electrical machine for the conversion of mechanical to electrical energy. A key issue for the ultimate adoption of such systems, however, is their robustness in the event of a fault to enable a safe shutdown, wit...

  14. Modeling the bremsstrahlung emission from converters

    CERN Document Server

    Mirea, M; Clapier, F; Hassaïne, M; Ibrahim, F; Müller, A C; Pauwels, N; Proust, J; Verney, D; Antoni, R; Bourgeois, L; Kandri-Rody, S

    2001-01-01

    The bremsstrahlung angular and energy theoretical distributions delivered from W and UCx thick converters are reported. This study is focussed on initial kinetic energies of the electron beam included in the range 30-60 MeV, suitable for the production of large radiative yields able to induce the $^{238}$U fission. These results offer the possibility to evaluate the required shielding for a neutron rich nuclei source.

  15. Metamaterial Polarization Converter Analysis: Limits of Performance

    OpenAIRE

    Markovich, Dmitry L.; Andryieuski, Andrei; Zalkovskij, Maksim; Malureanu, Radu; Lavrinenko, Andrei V.

    2012-01-01

    In this paper we analyze the theoretical limits of a metamaterial converter that allows for linear-to- elliptical polarization transformation with any desired ellipticity and ellipse orientation. We employ the transmission line approach providing a needed level of the design generalization. Our analysis reveals that the maximal conversion e?ciency for transmission through a single metamaterial layer is 50%, while the realistic re ection con?guration can give the conversion e?ciency up to 90%....

  16. Multiport Resonant DC-DC Converter

    OpenAIRE

    Tran, Yan-Kim; Dujic, Drazen; Barrade, Philippe

    2015-01-01

    his paper presents a multiport galvanically isolated LLC resonant DC-DC converter suitable for DC applications. A three-port structure is analyzed, with full bidirectional power flow capabilities, simple control and behavior similar to that expected from a DC transformer. Each port is equipped with half-bridge modules accompanied with tuned resonant tank, partly realized with elements of a multi- winding high frequency transformer. With some restrictions that are explained in the paper, each ...

  17. Converting digital learning content into learning objects

    OpenAIRE

    Schreurs, Jeanne; Moreau, Rachel

    2006-01-01

    Our learning content can be structured as learning objects( LO) and as atomic learning objects (ALO). For both of them a set of metadata has been defined. The metadata follows the international standards on learning content. As a result the interoperability of the learning objects in different learning systems is being guaranteed. We are converting the digital learning content into LO's. A learning object is seen as a composition or a scenario model of a set of blocks. The blocks, presenting ...

  18. (Convertible) Undeniable Signatures Without Random Oracles

    Science.gov (United States)

    Yuen, Tsz Hon; Au, Man Ho; Liu, Joseph K.; Susilo, Willy

    We propose a convertible undeniable signature scheme without random oracles. Our construction is based on Waters' and Kurosawa and Heng's schemes that were proposed in Eurocrypt 2005. The security of our scheme is based on the CDH and the decision linear assumption. Comparing only the part of undeniable signatures, our scheme uses more standard assumptions than the existing undeniable signatures without random oracles due to Laguillamie and Vergnaud.

  19. Angiotensin Converting Enzyme Activity in Alopecia Areata

    OpenAIRE

    Mohammad Reza Namazi; Armaghan Ashraf; Farhad Handjani; Ebrahim Eftekhar; Amir Kalafi

    2014-01-01

    Background. Alopecia areata (AA) is a chronic inflammatory disease of the hair follicle. The exact pathogenesis of AA remains unknown, although recent studies support a T-cell mediated autoimmune process. On the other hand, some studies have proposed that the renin-angiotensin-aldosterone system (RAAS) may play a role in autoimmunity. Therefore, we assessed serum activity of angiotensin converting enzyme (ACE), a component of this system, in AA. Methods. ACE activity was measured in the sera ...

  20. Reversible thyristor converters of brushless synchronous compensators

    Directory of Open Access Journals (Sweden)

    А.М.Galynovskiy

    2013-12-01

    Full Text Available Behavior of models of three-phase-to-single-phase rotary reversible thyristor converters of brushless synchronous compensators in a circuit simulation system is analyzed. It is shown that combined control mode of opposite-connected thyristors may result in the exciter armature winding short circuits both at the thyristor feed-forward and lagging current delay angles. It must be taken into consideration when developing brushless compensator excitation systems.

  1. Online Scheduling in Distributed Message Converter Systems

    OpenAIRE

    Risse, Thomas; Wombacher, Andreas; Surridge, Mike; Taylor, Steve; Aberer, Karl

    2001-01-01

    The optimal distribution of jobs among hosts in distributed environments is an important factor to achieve high performance. The optimal strategy depends on the application. In this paper we present a new online scheduling strategy for distributed EDI converter system. The strategy is based on the Bin-Stretching approach. The original algorithm has been enhanced to satisfy the business goals of meeting deadlines, priority processing, low response time and high throughput. The algorithm can be...

  2. Fracture imaging with converted elastic waves

    Energy Technology Data Exchange (ETDEWEB)

    Nihei, K.T.; Nakagawa, S.; Myer, L.R.

    2001-05-29

    This paper examines the seismic signatures of discrete, finite-length fractures, and outlines an approach for elastic, prestack reverse-time imaging of discrete fractures. The results of this study highlight the importance of incorporating fracture-generated P-S converted waves into the imaging method, and presents an alternate imaging condition that can be used in elastic reverse-time imaging when a direct wave is recorded (e.g., for crosswell and VSP acquisition geometries).

  3. Optimizing Design of UHVDC Converter Stations

    Institute of Scientific and Technical Information of China (English)

    MA Weimin; NIE Dingzhen; CAO Yanming

    2012-01-01

    Based on the consultation and study for Xiangjiaba-Shanghai ±800 kV UHVDC(ultra high voltage direct current) project, this paper presents an optimal design for key technique solutions. In this paper, the DC system electrical scheme design, the DC filter design, the DC harmonic component suppression, the over voltage and insulation coordination, the requirements for converter station equipment, the main equipment technical parameters of equipment (including thyristor valve, converter transformer, smoothing reactor, DC breaker), the configuration of measuring device and DC control protection system, and the de-icing operation design are investigated. According to the UHVDC technology researched conclusions and the development of the project construction, the UHVDC system design for converter stations becomes an optimal combination. The optimized design solves numbers of technical problems of the world's first UHVDC project, and it is applied to the project's construction. Under the actual operating condition, the optimized design is proved to be correct and superior. These optimal design conclusions are impartment for developing UHVDC technique and equipment, and provide reference for future UHVDC projects.

  4. One-Quadrant Switched-Mode Power Converters

    CERN Document Server

    Petrocelli, R

    2015-01-01

    This article presents the main topics related to one-quadrant power convert- ers. The basic topologies are analysed and a simple methodology to obtain the steady-state output–input voltage ratio is set out. A short discussion of dif- ferent methods to control one-quadrant power converters is presented. Some of the reported derived topologies of one-quadrant power converters are also considered. Some topics related to one-quadrant power converters such as syn- chronous rectification, hard and soft commutation, and interleaved converters are discussed. Finally, a brief introduction to resonant converters is given.

  5. Fault isolation in parallel coupled wind turbine converters

    DEFF Research Database (Denmark)

    Odgaard, Peter Fogh; Thøgersen, Paul Bach; Stoustrup, Jakob

    2010-01-01

    Parallel converters in wind turbine give a number advantages, such as fault tolerance due to the redundant converters. However, it might be difficult to isolate gain faults in one of the converters if only a combined power measurement is available. In this paper a scheme using orthogonal power...... references to the converters is proposed. Simulations on a wind turbine with 5 parallel converters show a clear potential of this scheme for isolation of this gain fault to the correct converter in which the fault occurs....

  6. Chromatic X-Ray imaging with a fine pitch CdTe sensor coupled to a large area photon counting pixel ASIC

    CERN Document Server

    Bellazzini, R; Brez, A; Minuti, M; Pinchera, M; Mozzo, P

    2012-01-01

    An innovative X-ray imaging sensor with intrinsic digital characteristics is presented. It is based on Chromatic Photon Counting technology. The detector is able to count individually the incident X-ray photons and to separate them according to their energy (two 'color' images per exposure). The energy selection occurs in real time and at radiographic imaging speed (GHz global counting rate). Photon counting, color mode and a very high spatial resolution (more than 10 l.p./mm at MTF50) allow to obtain an optimal ratio between image quality and absorbed dose. The individual block of the imaging system is a two-side buttable semiconductor radiation detector made of a thin pixellated CdTe crystal (the sensor) coupled to a large area VLSI CMOS pixel ASIC. 1, 2, 4, 8 tile units have been built. The 8 tiles unit has 25cm x 2.5cm sensitive area. Results and images obtained from in depth testing of several configurations of the system are presented. The X-Ray imaging system is the technological platform of PIXIRAD Im...

  7. Morphological study of lipid vesicles in presence of amphotericin B via modification of the microfluidic CellASIC platform and LED illumination microscopy

    Science.gov (United States)

    Genova, J.; Decheva-Zarkova, M.; Pavlič, J. I.

    2016-02-01

    Giant lipid vesicles (liposomes) are the simplest model of the biological cell and can be easily formed from natural or synthetic lipid species with controlled composition and properties. This is the reason why they are the preferred objects for various scientific investigations. Amphotericin B (AmB) is a membrane active drug, used for treatment of systemic fungal infections. In this work we studied the morphological behavior of giant SOPC vesicles in asymmetrical presence of amphotericin B antibiotic in the vicinity of the lipid membrane. The visualization of the vesicles was carried out via inverted phase contrast microscopy. The illumination source was modified in a way that tungsten light bulb was replaced by 10 W white LED chip. All the experiments were performed using CellASIC ONIX Microfluidic Platform. The setup has been modified thus opening new opportunities for a variety of experimental realizations. The performed morphological studies showed strong and irreversible effect on the vesicle shape at the presence of amphotericin B in concentration 10-5 g/l in the outer for the liposome's membrane solution. At concentration 10-3 g/l AmB the effect was less visible and in 15-20 minutes the vesicles regained its initial spherical shape.

  8. CLARO-CMOS: a fast, low power and radiation-hard front-end ASIC for single-photon counting in 0.35 micron CMOS technology

    Science.gov (United States)

    Andreotti, M.; Baldini, W.; Calabrese, R.; Carniti, P.; Cassina, L.; Cotta Ramusino, A.; Fiorini, M.; Giachero, A.; Gotti, C.; Luppi, E.; Maino, M.; Malaguti, R.; Pessina, G.; Tomassetti, L.

    2015-01-01

    The CLARO-CMOS is a prototype ASIC designed for fast photon counting with multi-anode photomultiplier tubes (MaPMT). The CLARO features a 5 ns peaking time, a recovery time to baseline smaller than 25 ns, and a power consumption of less than 1 mW per channel. The chip was designed in 0.35 μm CMOS technology, and was tested for radiation hardness with neutrons up to 1014 1 MeV neq/cm2, X-rays up to 40 kGy and protons up to 76 kGy. Its capability to read out single photons at high rate from a Hamamatsu R11265 MaPMT, the baseline photon detector for the LHCb RICH upgrade, was demonstrated both with test bench measurements and with actual signals from a R11265 MaPMT. The presented results allowed CLARO to be chosen as the front-end readout chip in the upgraded LHCb RICH detector.

  9. Comparison between the Performance of Basic SEPIC Converter and modified SEPIC Converter with PI Controller

    Directory of Open Access Journals (Sweden)

    Satyendra Kumar Gupta

    2014-08-01

    Full Text Available There are multiple solutions in which line current is sinusoidal. In addition, in the recent years, a great number of circuits have been proposed with non sinusoidal line current. In this paper, a review of the most interesting solutions for single phase and low power applications is carried out. They are classified attending to the line current waveform, energy processing, number of switches, control loops, etc. The major advantages and disadvantages are highlighted and the field of application is found. The paper presents performance analysis of modified SEPIC dc-dc converter with low input voltage and wide output voltage range. The operational analysis and the design is done for the 380W power output of the modified converter. The simulation results of modified SEPIC converter are obtained with PI controller for the output voltage. The results obtained with the modified converter are compared with the basic SEPIC converter topology for the rise time, peak time, settling time and steady state error of the output response for open loop. Voltage tracking curve is also shown for wide output voltage range.

  10. A resonant dc-dc power converter assembly

    DEFF Research Database (Denmark)

    2015-01-01

    The present invention relates to a resonant DC-DC power converter assembly comprising a first resonant DC-DC power converter and a second resonant DC-DC power converter having identical circuit topologies. A first inductor of the first resonant DC-DC power converter and a second inductor...... of the second resonant DC-DC power converter are configured for magnetically coupling the first and second resonant DC-DC power converters to each other to forcing substantially 180 degrees phase shift, or forcing substantially 0 degree phase shift, between corresponding resonant voltage waveforms of the first...... and second resonant DC-DC power converters. The first and second inductors are corresponding components of the first and second resonant DC-DC power converters....

  11. Dc to ac converter operates efficiently at low input voltages

    Science.gov (United States)

    1965-01-01

    Self-oscillating dc to ac converter with transistor switching to produce a square wave output is used for low and high voltage power sources. The converter has a high efficiency throughout a wide range of loads.

  12. A Three-Phase Interleaved Floating Output Boost Converter

    Directory of Open Access Journals (Sweden)

    Ajmal Farooq

    2015-01-01

    Full Text Available High step-up dc-dc converter is an essential part in several renewable energy systems. In this paper, a new topology of step-up dc-dc converter based on interleaved structure is proposed. The proposed converter uses three energy storing capacitors to achieve a high voltage gain. Besides the high voltage gain feature, the proposed converter also reduces the voltage stress across the semiconductor switches. This helps in using low rating switching devices which can reduce the overall size and cost of the converter. The operating principle of the proposed converter is discussed in detail and its principle waveforms are analyzed. An experiment is carried out on a 20 V input, 130 V output, and 21 W power prototype of the proposed converter in the laboratory to verify the performance of the proposed converter. An efficiency of 91.3% is achieved at the rated load.

  13. Induction heating: fundamentals and choice criteria for frequency converters

    Energy Technology Data Exchange (ETDEWEB)

    Nuns, J.; Peureux, J.L. [Electricite de France (EDF), 75 - Paris (France)

    1995-10-01

    Induction heating imposes the induced current frequency; this frequency depends on the size and the materials to heat, thus a frequency converter is often necessary. In the case of induction heating, those converters are always resonance power supplies. Modern frequency converters include power electronics switches (thyristors, GTO thyristors, bipolar transistors, IGBT, field effect transistors). The more used converter is the current inverter which feeds a parallel oscillating circuit. (authors). 3 refs., 16 figs., 1 tab.

  14. Three-phase Resonant DC-link Converter

    OpenAIRE

    Munk-Nielsen, Stig

    1997-01-01

    The purpose of the project is to develop a three-phase resonant converter suitable for standard speed drives. The motivation for working with resonant converters is found in the problem of the standard converter type used today. In standard converter type Pulse Width Modulated-Voltage Source Inverter, PWM-VSI, the switches are subject to high current and voltage stress during switching, which causes losses. The fast switching of modern switches reduces switching losses. Unfortunately this pro...

  15. Design & Implementation of Zero Voltage Switching Buck Converter

    OpenAIRE

    A.Suresh Kumar; P.Krishna Reddy

    2014-01-01

    Zero voltage switching (ZVS) buck converter is more preferable over hard switched buck converter for low power, high frequency DC-DC conversion applications. In Zero voltage switching converter, turn on & turn off of a switch occurs at zero voltage that results in lower switching losses. In this converter soft switching is achieved by using resonant components. The optimal values of resonant components are determined by using electric functions derived from circuit configurati...

  16. Design of Monolithic Integrator for Strain-to-Frequency Converter

    OpenAIRE

    Tuan Mohd. Khairi Tuan Mat; Chew Sue Ping; Akram Abdul Azid

    2012-01-01

    Strain-to-Frequency converter (SFC) is a one of the analog conditioner tools that converts any strain signal to the frequency signal. The basic concept of SFC is by detecting any changing of strains, then converting the strain to the voltage signal and converting the voltage signal to the frequency signal. This tool consists of 3 main  components which are strain gauge, differential integrator and comparator. This paper presents the designing and analysis of monolithic integrator that to be u...

  17. A Composite PWM Control Strategy for Boost Converter

    Science.gov (United States)

    Qingfeng, Liu; Zhaoxia, Leng; Jinkun, Sun; Huamin, Wang

    In order to improve the control performance of boost converter with large signal disturbance, a composite PWM control strategy for boost converter operating in continuous condition mode (CCM) was proposed in this paper. The parasitical loss of Boost converter was analyzed and a loss compensation strategy was adopted to design feed-forward tracker for converter. The composite PWM controller consisted of the tracker and PID controller. Simulation and experiment results validated the validity of the control strategy presented in this paper.

  18. Convertible Subordinated Debt Financing and Optimal Investment Timing

    OpenAIRE

    Kyoko Yagi; Ryuta Takashima

    2010-01-01

    In this paper, we examine the optimal investment policy of the firm which is financed by issuing equity, straight debt and convertible debt with the senior-sub structure. The senior-sub structure gives preference to straight debt over convertible debt and to convertible debt over equity when the default occurs. We investigate how the senior-sub structure affects the optimal policies for default, conversion and investment the values of equity, straight debt, convertible debt and investment. In...

  19. Simulation of New Switched Capacitance Power Converter for Srm

    Directory of Open Access Journals (Sweden)

    S. M. Mohamed Saleem

    2014-06-01

    Full Text Available In this paper, design and simulation of switched capacitance power converter are proposed for 6/4 switched reluctance motor (SRM drive. The operating principle and design consideration of the proposed converter is explained. The proposed converter performance is better in reduction of torque ripple and constant speed can be achieved quickly with reduced power loss when compared with asymmetric converter. The proposed system is simulated by using MATLAB Simulink and their results are clearly presented.

  20. A New Modular Multilevel Converter with Integrated Energy Storage

    DEFF Research Database (Denmark)

    Trintis, Ionut; Munk-Nielsen, Stig; Teodorescu, Remus

    2011-01-01

    This paper introduces a new modular converter with integrated energy storage based on the cascaded half-bridge modular multilevel converter with common DC bus. It represents a complete modular solution with power electronics and energy storage building blocks, for medium and high voltage...... in the future HVDC meshed grids. Its functionality and flexibility makes the converter independent on the energy storage unit characteristic. The converter concept with its basic functions and control schemes are described and evaluated in this paper....

  1. Pricing Chinese Convertible Bonds with Dynamic Credit Risk

    OpenAIRE

    Ping Li; Jing Song

    2014-01-01

    To price convertible bonds more precisely, least squares Monte Carlo (LSM) method is used in this paper for its advantage in handling the dependence of derivatives on the path, and dynamic credit risk is used to replace the fixed one to make the value of convertible bonds reflect the real credit risk. In the empirical study, we price convertible bonds based on static credit risk and dynamic credit risk, respectively. Empirical results indicate that the ICBC convertible bond has been overprice...

  2. Microcontroller based phase control circuit for resonant power converters

    OpenAIRE

    Milcevski, Dejan; Stefanov, Goce; Karadzinov, Ljupco

    2011-01-01

    A microcontroller based circuit is developed for driving the IGBT switches of a bridge resonant power converter used for induction heating of metals. When a resonant power converter is used for induction heating the load is variable due to the effects of the heating process making the converter to operate out of resonance. This effect decreases the converter output power and increases switching loses. In order to maintain constant output power operating constantly on the resonant frequency a ...

  3. Estimation on the switching losses at IGBT bridges power converter

    OpenAIRE

    Stefanov, Goce; Karacinov, Ljupco; Cundev, Dobri

    2011-01-01

    ABSTRACT. In the paper estimation on the switching losses at IGBT bridge converter with the output serial resonant load is given. The converter works on frequency higher than resonant frequency and supports the work of IGBT transistors in the bridge with zero voltage turn on. In the analysis of the converter, PowerSim and SemiSiel simulation programs is used. The results to the switching losses estimated by simulation are compared with the results in a practical realized converter.

  4. Method for Converter Synchronization with RF Injection

    Directory of Open Access Journals (Sweden)

    Joshua P. Bruckmeyer

    2015-09-01

    Full Text Available This paper presents an injection method for synchronizing analog to digital converters (ADC. This approach can eliminate the need for precision routed discrete synchronization signals of current technologies, such as JESD204. By eliminating the setup and hold time requirements at the conversion (or near conversion clock rate, higher sample rate systems can be synchronized. Measured data from an existing multiple ADC conversion system was used to evaluate the method. Coherent beams were simulated to measure the effectiveness of the method. The results show near theoretical coherent processing gain.

  5. Nonlinear control design for wave energy converter

    OpenAIRE

    Galván García, Bruno

    2013-01-01

    In this thesis, we study the optimization of a single-piston pump system for use in a new wave energy converter by using a feedback mechanism. The first part of the thesis is dedicated to the optimal determination of control variables using the dynamical model of the single-piston pump system, which is a switched system that is built on first principles and describes the dynamics of four main important elements of the system: the buoy, the rod, the piston and the pumped water. ...

  6. Waste Plastic Converting into Hydrocarbon Fuel Materials

    Energy Technology Data Exchange (ETDEWEB)

    Sarker, Moinuddin; Mamunor Rashid, Mohammad; Molla, Mohammad

    2010-09-15

    The increased demand and high prices for energy sources are driving efforts to convert organic compounds into useful hydrocarbon fuels. Although much of this work has focused on biomass, there are strong benefits to deriving fuels from waste plastic material. Natural State Research Inc. (NSR) has invented a simple and economically viable process to decompose the hydrocarbon polymers of waste plastic into the shorter chain hydrocarbon of liquid fuel (patent pending). The method and principle of the production / process will be discussed. Initial tests with several widely used polymers indicate a high potential for commercialization.

  7. Power converters for medium voltage networks

    CERN Document Server

    Islam, Md Rabiul; Zhu, Jianguo

    2014-01-01

    This book examines a number of topics, mainly in connection with advances in semiconductor devices and magnetic materials and developments in medium and large-scale renewable power plant technologies, grid integration techniques and new converter topologies, including advanced digital control systems for medium-voltage networks. The book's individual chapters provide an extensive compilation of fundamental theories and in-depth information on current research and development trends, while also exploring new approaches to overcoming some critical limitations of conventional grid integration te

  8. Converting energy from fusion into useful forms

    OpenAIRE

    Kovari, M.; Harrington, C.; Jenkins, I; Kiely, C

    2013-01-01

    If fusion power reactors are to be feasible, it will still be necessary to convert the energy of the nuclear reaction into usable form. The heat produced will be removed from the reactor core by a primary coolant, which might be water, helium, molten lithium-lead, molten lithium-containing salt, or CO2. The heat could then be transferred to a conventional Rankine cycle or Brayton (gas turbine) cycle. Alternatively it could be used for thermochemical processes such as producing hydrogen or oth...

  9. EMI filter techniques in power electronic converters

    Directory of Open Access Journals (Sweden)

    Fredy Edimer Hoyos Velasco

    2012-04-01

    Full Text Available This paper presents the results of EMI reduction techniques applied to power electronic converters. The techniques applied included shielding control and power signals, separating power system references regarding reference for instrumentation and measurement signals, implementing analog filters and configuring an appropriate switch trigger system for electronic power to decrease shifting EMI emissions to the maximum. This paper presents the results before and after applying the techniques to reduce interference. The results were also veryfied by using two real time control strategies rapid control prototyping (RCP.

  10. Converting skeletal structures to quad dominant meshes

    DEFF Research Database (Denmark)

    Bærentzen, Jakob Andreas; Misztal, Marek Krzysztof; Welnicka, Katarzyna

    2012-01-01

    We propose the Skeleton to Quad-dominant polygonal Mesh algorithm (SQM), which converts skeletal structures to meshes composed entirely of polar and annular regions. Both types of regions have a regular structure where all faces are quads except for a single ring of triangles at the center of each...... polar region. The algorithm produces high quality meshes which contain irregular vertices only at the poles or where several regions join. It is trivial to produce a stripe parametrization for the output meshes which also lend themselves well to polar subdivision. After an initial description of SQM, we...

  11. Solid state transport-based thermoelectric converter

    Science.gov (United States)

    Hu, Zhiyu

    2010-04-13

    A solid state thermoelectric converter includes a thermally insulating separator layer, a semiconducting collector and an electron emitter. The electron emitter comprises a metal nanoparticle layer or plurality of metal nanocatalyst particles disposed on one side of said separator layer. A first electrically conductive lead is electrically coupled to the electron emitter. The collector layer is disposed on the other side of the separator layer, wherein the thickness of the separator layer is less than 1 .mu.m. A second conductive lead is electrically coupled to the collector layer.

  12. Near-Shore Floating Wave Energy Converters

    DEFF Research Database (Denmark)

    Ruol, Piero; Zanuttigh, Barbara; Martinelli, Luca;

    2011-01-01

    and transmission characteristics are approximated to functions of wave height, period and obliquity. Their order of magnitude are 20% and 80%, respectively. It is imagined that an array of DEXA is deployed in front of Marina di Ravenna beach (IT), a highly touristic site of the Adriatic Coast. Based on the CERC......Aim of this note is to analyse the possible application of a Wave Energy Converter (WEC) as a combined tool to protect the coast and harvest energy. Physical model tests are used to evaluate wave transmission past a near-shore floating WEC of the wave activated body type, named DEXA. Efficiency...

  13. Design, modeling and testing of data converters

    CERN Document Server

    Kiaei, Sayfe; Xu, Fang

    2014-01-01

    This book presents the a scientific discussion of the state-of-the-art techniques and designs for modeling, testing and for the performance analysis of data converters. The focus is put on sustainable data conversion. Sustainability has become a public issue that industries and users can not ignore. Devising environmentally friendly solutions for data conversion designing, modeling and testing is nowadays a requirement that researchers and practitioners must consider in their activities. This book presents the outcome of the IWADC workshop 2011, held in Orvieto, Italy.

  14. Converting Student Support Services to Online Delivery

    Directory of Open Access Journals (Sweden)

    David E. Brigham

    2001-01-01

    Full Text Available This case study describes how Regents College (soon to be Excelsior College, an accredited, private, distance education institution with administrative offices in Albany, New York addressed the structural, management, and resource issues that came into play when converting distance education programs from print-based and telephone delivery to online delivery. The study uses a systems framework to describe and analyze the circumstances and issues surrounding the creation of six student support services: electronic advising, an electronic peer network, an online database of distance courses, an online bookstore, a virtual library, and an alumni services website.

  15. Multi Port Single Stage Power Electronics Converter and Wind PFC Converter for DC Micro Grid Applications

    Directory of Open Access Journals (Sweden)

    M. Hemachandran

    2014-08-01

    Full Text Available In this study multi port AC/DC-DC single stage power electronics converter proposed for grid power supply. The topology includes reduced number of active element and passive element. Passive element is used to provide to achieve improved voltage gain and to reduce the voltage stress of input side switches. The active-clamp circuits are used to recycle the energy stored in the leakage inductors and to improve the system performances. Here two input port (wind and battery unit and output port connected to dc grid, battery act as charge unit and source. Efficient wind power conversion is achieved by PFC boost dc-dc converter. Controlled and high step up voltage is supplied to multi-port converter from wind source.

  16. Convertible Arbitrage Price Pressure and Short-Sale Constraints

    NARCIS (Netherlands)

    de Jong, Abe; Dutordoir, Marie; van Genuchten, Nathalie; Verwijmeren, Patrick

    2012-01-01

    Using a sample of 4,148 convertibles issued over 1990-2009 by companies listed in 35 countries, the authors exploited worldwide differences in short-sale constraints to examine whether short selling by convertible arbitrageurs creates downward pressure on convertible issuers' stock prices. They foun

  17. 40 CFR 90.319 - NOX converter check.

    Science.gov (United States)

    2010-07-01

    ... 40 Protection of Environment 20 2010-07-01 2010-07-01 false NOX converter check. 90.319 Section 90... Provisions § 90.319 NOX converter check. (a) The efficiency of the converter used for the conversion of NO2... percent of the NO concentration). The NOX analyzer must be in the NO mode so that the span gas does...

  18. SWITCHED-CAPACITOR BASED STEP-DOWN RESONANT CONVERTERS

    Institute of Scientific and Technical Information of China (English)

    Y.P.B.Yeung; K.W.E.Cheng; K.K.Law

    2001-01-01

    A family of switched-capacitor based resonant converters is present.All converters are in step-downmode.By adding different number of switched-capacitor cells,different output voltage conversion ratio can beobtained.All switching devices in the converters operate under zero-current switching.Both high frequencyoperations and high efficiency are possible.

  19. 31 CFR 800.206 - Convertible voting instrument.

    Science.gov (United States)

    2010-07-01

    ... 31 Money and Finance: Treasury 3 2010-07-01 2010-07-01 false Convertible voting instrument. 800..., AND TAKEOVERS BY FOREIGN PERSONS Definitions § 800.206 Convertible voting instrument. The term convertible voting instrument means a financial instrument that currently does not entitle its owner or...

  20. New active load voltage clamp for HF-link converters

    DEFF Research Database (Denmark)

    Ljusev, Petar; Andersen, Michael Andreas E.

    2005-01-01

    This paper proposes a new active clamp for HF-link converters, which features very high efficiency by returning the clamped energy back to the primary side through a small auxiliary converter. It also increases the reliability of HF-link converters by providing an alternative load current path du...

  1. Impedance Interaction Modeling and Analysis for Bidirectional Cascaded Converters

    DEFF Research Database (Denmark)

    Tian, Yanjun; Deng, Fujin; Chen, Zhe;

    2015-01-01

    For the cascaded converter system, the output impedance of source converter interacts with the input impedance of load converter, and the interaction may cause the system instability. In bidirectional applications, when the power flow is reversed, the impedance interaction also varies, which brin...

  2. Efficiency and reliability improvement in wind turbine converters by grid converter adaptive control

    DEFF Research Database (Denmark)

    Trintis, Ionut; Munk-Nielsen, Stig; Abrahamsen, Flemming;

    2013-01-01

    and generator side. Operating in this way, the electrical and thermal stress factors are decreased on the power electronic devices, increasing their lifetime. The simulation results using this method show efficiency increase and devices temperature cycles slightly decreased. Experimental results on a...... wind turbine power stack shows efficiency increase in the high power region.......This paper presents a control method that reduces the losses in wind turbine converters adaptively controlling the grid converter. The dc-link voltage adapts its reference based on the system state and therefore reduces the stored energy, and is therefore kept at the minimum necessary for the grid...

  3. A waveguide-typed plasmonic mode converter.

    Science.gov (United States)

    Park, Hae-Ryeong; Park, Jong-Moon; Kim, Min-Su; Lee, Myung-Hyun

    2012-08-13

    Waveguide-typed plasmonic mode converters (WPMCs) at a wavelength of 1.55 μm are presented. The WPMC is composed of an insulator-metal-insulator waveguide (IMI-W), a 1st reversely tapered insulator-metal-insulator-metal-insulator waveguide (RT-IMIMI-W), an insulator-metal-insulator-metal-insulator waveguide (IMIMI-W), a 2nd RT-IMIMI-W with lateral silver mirrors (LSMs), and a metal-insulator-metal waveguide (MIM-W) in series. The mode sizes for the IMI-W, IMIMI-W, and MIM-W via the IMIMI-W with LSMs were not only calculated using a finite element method but were also experimentally measured. The input mode size of 10.3 μm × 10.3 μm from a polarization-maintaining single-mode fiber was squeezed to the mode size of ~2.9 μm × 2.9 μm in measurement by converting an s0 mode to an Sa0 mode via an Ss0 mode. The WPMC may be potentially useful for bridging micro- to nano-plasmonic integrated circuits. PMID:23038504

  4. A novel converter topology for TEM applications

    Indian Academy of Sciences (India)

    S Kedarnath; Krishna Vasudevan

    2008-10-01

    Time-domain Electro Magnetic (TEM) systems, are used for remote sensing of conductive mineral deposits buried under the surface of the earth. A low frequency trapezoidal current excitation set-up in an exciter coil loop causes a flux that penetrates deep into the earth. When the excitation is cut off sharply, conductive deposits in the earth carrying flux react by causing eddy current flows within them. The flux produced by such eddy currents is picked up by a sensor coil. By comparing the emf induced in the sensor coil with a priori known emf patterns for mineral deposits, the presence of mineral deposits can be ascertained. The voltage, current and energy levels of the TEM system, require special type of excitation technique. Power converters for such non-standard requirements are not reported in the literature, particularly for TEM applications. This paper introduces TEM systems to the reader and presents the requirements for excitation. A converter topology to meet the requirements, it’s analysis, control and performance are presented. Among other alternatives that the authors have attempted, the topology presented features reduced number of passive elements, high voltage gain and low losses. These features enable the sensor head to be operated from the normal low level battery.

  5. Wind Energy Conversion Based on Matrix Converter

    Directory of Open Access Journals (Sweden)

    Mutharasan Anburaj

    2014-07-01

    Full Text Available In recent years renewable sources such as solar, wave and wind are used for the generation of electricity. Wind is one of the major renewable sources. The amount of energy from a Wind Energy Conversion System (WECS depends not only on the wind at the site, but also on the control strategy used for the WECS. In assistance to get the appropriate wind energy from the conversion system, wind turbine generator will be run in variable speed mode. The variable speed capability is achieved through the use of an advanced power electronic converter. Fixed speed wind turbines and induction generators are often used in wind farms. But the limitations of such generators are low efficiency and poor power quality which necessitates the variable speed wind turbine generators such as Doubly Fed Induction Generator (DFIG and Permanent Magnet Synchronous Generator (PMSG. A high-performance configuration can be obtained by using Scherbius drive composed of a DFIG and a converter in combination AC-DC-AC connect between stator & rotor points for providing the required variable speed operation

  6. CCLIBS: The CERN Power Converter Control Libraries

    CERN Document Server

    AUTHOR|(SzGeCERN)404953; Lebioda, Krzysztof Tomasz; Magrans De Abril, Marc; Martino, Michele; Murillo Garcia, Raul; Nicoletti, Achille

    2015-01-01

    Accurate control of power converters is a vital activity in large physics projects. Several different control scenarios may coexist, including regulation of a circuit’s voltage, current, or field strength within a magnet. Depending on the type of facility, a circuit’s reference value may be changed asynchronously or synchronously with other circuits. Synchronous changes may be on demand or under the control of a cyclic timing system. In other cases, the reference may be calculated in real-time by an outer regulation loop of some other quantity, such as the tune of the beam in a synchrotron. The power stage may be unipolar or bipolar in voltage and current. If it is unipolar in current, it may be used with a polarity switch. Depending on the design, the power stage may be controlled by a firing angle or PWM duty-cycle reference, or a voltage or current reference. All these cases are supported by the CERN Converter Control Libraries (CCLIBS). These open-source C libraries include advanced reference generati...

  7. Forback DC-to-DC converter

    Science.gov (United States)

    Lukemire, Alan T.

    1995-05-01

    A pulse-width modulated DC-to-DC power converter including a first inductor, i.e. a transformer or an equivalent fixed inductor equal to the inductance of the secondary winding of the transformer, coupled across a source of DC input voltage via a transistor switch which is rendered alternately conductive (ON) and nonconductive (OFF) in accordance with a signal from a feedback control circuit is described. A first capacitor capacitively couples one side of the first inductor to a second inductor which is connected to a second capacitor which is coupled to the other side of the first inductor. A circuit load shunts the second capacitor. A semiconductor diode is additionally coupled from a common circuit connection between the first capacitor and the second inductor to the other side of the first inductor. A current sense transformer generating a current feedback signal for the switch control circuit is directly coupled in series with the other side of the first inductor so that the first capacitor, the second inductor and the current sense transformer are connected in series through the first inductor. The inductance values of the first and second inductors, moreover, are made identical. Such a converter topology results in a simultaneous voltsecond balance in the first inductance and ampere-second balance in the current sense transformer.

  8. Serial Pixel Analog-to-Digital Converter

    Energy Technology Data Exchange (ETDEWEB)

    Larson, E D

    2010-02-01

    This method reduces the data path from the counter to the pixel register of the analog-to-digital converter (ADC) from as many as 10 bits to a single bit. The reduction in data path width is accomplished by using a coded serial data stream similar to a pseudo random number (PRN) generator. The resulting encoded pixel data is then decoded into a standard hexadecimal format before storage. The high-speed serial pixel ADC concept is based on the single-slope integrating pixel ADC architecture. Previous work has described a massively parallel pixel readout of a similar architecture. The serial ADC connection is similar to the state-of-the art method with the exception that the pixel ADC register is a shift register and the data path is a single bit. A state-of-the-art individual-pixel ADC uses a single-slope charge integration converter architecture with integral registers and “one-hot” counters. This implies that parallel data bits are routed among the counter and the individual on-chip pixel ADC registers. The data path bit-width to the pixel is therefore equivalent to the pixel ADC bit resolution.

  9. Converting DYNAMO simulations to Powersim Studio simulations

    Energy Technology Data Exchange (ETDEWEB)

    Walker, La Tonya Nicole; Malczynski, Leonard A.

    2014-02-01

    DYNAMO is a computer program for building and running 'continuous' simulation models. It was developed by the Industrial Dynamics Group at the Massachusetts Institute of Technology for simulating dynamic feedback models of business, economic, and social systems. The history of the system dynamics method since 1957 includes many classic models built in DYANMO. It was not until the late 1980s that software was built to take advantage of the rise of personal computers and graphical user interfaces that DYNAMO was supplanted. There is much learning and insight to be gained from examining the DYANMO models and their accompanying research papers. We believe that it is a worthwhile exercise to convert DYNAMO models to more recent software packages. We have made an attempt to make it easier to turn these models into a more current system dynamics software language, Powersim © Studio produced by Powersim AS2 of Bergen, Norway. This guide shows how to convert DYNAMO syntax into Studio syntax.

  10. Realization of the LEP power converters

    International Nuclear Information System (INIS)

    After a phase of intensive and detailed preparation, which included preliminary inquiries to a wide variety of firms, more than forty contracts and large orders were placed with industry. They cover the power part of the converters for the magnet system, the RF klystrons and the vacuum pumps as well as the electronics for the supervision, control and local intelligence for these high-precision equipments. The first deliveries of the series production started in the second half of 1986 and by the end of 1987 most of the high-power units for the magnet system have been delivered to CERN. After thorough tests they are being installed in the LEP equipment buildings. This includes all the equipment necessary for the injection tests into LEP octant 1 to 2, scheduled for July '88. This paper reports that the tests on the prototype 100 kV, 40 A converter for the RF klystrons were successfully terminated with a full power run on the RF test string. The first sets of the series units are being delivered, tested and installed. An important aspect for obtaining high reliability lies in the automatic test procedures which are rigorously carried out, starting at the module level and ending at the complete equipment

  11. A nanoscale linear-to-linear motion converter of graphene.

    Science.gov (United States)

    Dai, Chunchun; Guo, Zhengrong; Zhang, Hongwei; Chang, Tienchong

    2016-08-14

    Motion conversion plays an irreplaceable role in a variety of machinery. Although many macroscopic motion converters have been widely used, it remains a challenge to convert motion at the nanoscale. Here we propose a nanoscale linear-to-linear motion converter, made of a flake-substrate system of graphene, which can convert the out-of-plane motion of the substrate into the in-plane motion of the flake. The curvature gradient induced van der Waals potential gradient between the flake and the substrate provides the driving force to achieve motion conversion. The proposed motion converter may have general implications for the design of nanomachinery and nanosensors.

  12. Width effects on hydrodynamics of pendulum wave energy converter

    Institute of Scientific and Technical Information of China (English)

    王冬姣; 邱守强; 叶家玮

    2014-01-01

    Based on two- and three-dimensional potential flow theories, the width effects on the hydrodynamics of a bottom-hinged trapezoidal pendulum wave energy converter are discussed. The two-dimensional eigenfunction expansion method is used to obtain the diffraction and radiation solutions when the converter width tends to be infinity. The trapezoidal section of the converter is approximated by a rectangular section for simplification. The nonlinear viscous damping effects are accounted for by including a drag term in the two- and three-dimensional methods. It is found that the three-dimensional results are in good agreement with the two-dimensional results when the converter width becomes larger, especially when the converter width is infinity, which shows that both of the methods are reasonable. Meantime, it is also found that the peak value of the conversion efficiency decreases as the converter width increases in short wave periods while increases when the converter width increases in long wave periods.

  13. Bifurcation behaviours of peak current controlled PFC boost converter

    Institute of Scientific and Technical Information of China (English)

    Ren Hai-Peng; Liu Ding

    2005-01-01

    Bifurcation behaviours of the peak current controlled power-factor-correction (PFC) boost converter, including fast-scale instability and low-frequency bifurcation, are investigated in this paper. Conventionally, the PFC converter is analysed in continuous conduction mode (CCM). This prevents us from recognizing the overall dynamics of the converter. It has been pointed out that the discontinuous conduction mode (DCM) can occur in the PFC boost converter, especially in the light load condition. Therefore, the DCM model is employed to analyse the PFC converter to cover the possible DCM operation. By this way, the low-frequency bifurcation diagram is derived, which makes the route from period-double bifurcation to chaos clear. The bifurcation diagrams versus the load resistance and the output capacitance also indicate the stable operation boundary of the converter, which is useful for converter design.

  14. Converter applications and their influence on large electrical machines

    CERN Document Server

    Drubel, Oliver

    2013-01-01

    Converter driven applications are applied in more and more processes. Almost any installed wind-farm, ship drives, steel mills, several boiler feed water pumps, extruder and many other applications operate much more efficient and economic in case of variable speed solutions. The boundary conditions for a motor or generator will change, if it is supplied by a converter. An electrical machine, which is operated by a converter, can no longer be regarded as an independent component, but is embedded in a system consisting of converter and machine. This book gives an overview of existing converter designs for large electrical machines. Methods for the appropriate calculation of machine phenomena, which are implied by converters are derived in the power range above 500kVA. It is shown how due to the converter inherent higher voltage harmonics and pulse frequencies special phenomena are caused inside the machine which can be the reason for malfunction. It is demonstrated that additional losses create additional tempe...

  15. Pricing Chinese Convertible Bonds with Dynamic Credit Risk

    Directory of Open Access Journals (Sweden)

    Ping Li

    2014-01-01

    Full Text Available To price convertible bonds more precisely, least squares Monte Carlo (LSM method is used in this paper for its advantage in handling the dependence of derivatives on the path, and dynamic credit risk is used to replace the fixed one to make the value of convertible bonds reflect the real credit risk. In the empirical study, we price convertible bonds based on static credit risk and dynamic credit risk, respectively. Empirical results indicate that the ICBC convertible bond has been overpriced, resulting from the underestimation of credit risk. In addition, when there is an issue of dividend, the conversion price will change in China's convertible bonds, while it does not change in the international convertible bonds. So we also empirically study the difference between the convertible bond's prices by assuming whether the conversion price changes or not.

  16. A Low Cost Single-Switch Bridgeless Boost PFC Converter

    Directory of Open Access Journals (Sweden)

    Younghoon Cho

    2014-03-01

    Full Text Available This paper proposes the single-switch bridgeless boost power factor correction (PFC converter to achieve high efficiency in low cost. The proposed converter utilizes only one active switching device for PFC operation as well as expecting higher efficiency than typical boost PFC converters. On the other hand, the implementation cost is less than traditional bridgeless boost PFC converters, in where two active switching deivces are necessary. The operational principle, the modeling, and the control scheme of the proposed converter are discussed in detail. In order to verify the operation of the proposed converter, a 500W switching model is built in PSIM software package. The simulation results show that the proposed converter perfectly achieves PFC operation with only a single active switch.

  17. Affecting Factors and Improving Measures for Converter Gas Recovery

    Institute of Scientific and Technical Information of China (English)

    2007-01-01

    To change the undesirable present situation of recovering and using converter gas in steel plants in China,the basic approaches to improving the converter gas recovery rate were analyzed theoretically along with the change curves of the converter gas component content, based on the converter gas recovery system of Baosteel No. 2 steelmaking plant. The effects of converter device, raw material, air imbibed quantity, recovery restricted condition, and intensity of oxygen blowing on the converter gas recovery rate were studied. Among these, the effects of the air imbibed quantity, recovery restricted condition, and intensity of oxygen blowing are remarkable. Comprehensive measures were put forward for improving the converter gas recovery from the point of devices, etc. , and good results were achieved.

  18. Bifurcation behaviours of peak current controlled PFC boost converter

    Science.gov (United States)

    Ren, Hai-Peng; Liu, Ding

    2005-07-01

    Bifurcation behaviours of the peak current controlled power-factor-correction (PFC) boost converter, including fast-scale instability and low-frequency bifurcation, are investigated in this paper. Conventionally, the PFC converter is analysed in continuous conduction mode (CCM). This prevents us from recognizing the overall dynamics of the converter. It has been pointed out that the discontinuous conduction mode (DCM) can occur in the PFC boost converter, especially in the light load condition. Therefore, the DCM model is employed to analyse the PFC converter to cover the possible DCM operation. By this way, the low-frequency bifurcation diagram is derived, which makes the route from period-double bifurcation to chaos clear. The bifurcation diagrams versus the load resistance and the output capacitance also indicate the stable operation boundary of the converter, which is useful for converter design.

  19. Breakup of loosely bound nuclei at intermediate energies for nuclear astrophysics and the development of a position sensitive microstrip detector system and its readout electronics using ASICs technologies

    Energy Technology Data Exchange (ETDEWEB)

    Bertulani, Carlos A. [Texas A & M Univ., Commerce, TX (United States)

    2016-01-12

    The work performed under this grant has led to the development of a detection system that will be used to measure reaction rates for proton or neutron capture reactions at stellar energies on radioactive ions far from stability. The reaction rates are needed to better understand the physics of nucleosynthesis in explosive stellar processes such as supernovae and x-ray burst events. The radioactive ions will be produced at the Radioactive Ion Beam Facility (RIBF) at RIKEN near Tokyo, Japan. During the course of this work, the group involved in this project has expanded by several institutions in Europe and Japan and now involves collaborators from the U.S., Japan, Hungary, Romania, Germany, Spain, Italy, China, and South Korea. As part of the project, a novel design based on large-area silicon detectors has been built and tested. The work has involved mechanical construction of a special purpose vacuum chamber, with a precision mounting system for the silicon detectors, development of a new ASICs readout system that has applications with a wide variety of silicon detector systems, and the development of a data acquisition system that is integrated into the computer system being used at RIBF. The parts noted above that are needed to carry out the research program are completed and ready for installation. Several approved experiments that will use this system will be carried out in the near future. The experimental work has been delayed due to a large increase in the cost and availability of electrical power for RIBF that occurred following the massive earthquake and tsunami that hit Japan in the spring of 2011. Another component of the research carried out with this grant involved developing the theoretical tools that are required to extract the information from the experiments that is needed to determine the stellar reaction rates. The tools developed through this part of the work will be made freely available for general use.

  20. Structure and Control of Flywheel Energy Converter

    Directory of Open Access Journals (Sweden)

    Yiming He

    2011-02-01

    Full Text Available On the basis of the flywheel energy converter’s structure in wind power turbine, we have used permanent-magnet synchronism motor as energy converter and built mathematical model. We have studied and realized control method of wind power turbine’s constant output power. By analyzing the mathematical model, we have concluded that the needed time of stored energy is three times longer than constant torque control time, and the needed motor power is one second of constant torque control. When flywheel starts from zero speed to basic speed ([(ω_max/5], the constant torque control method will be acquired. When flywheel speeds up between [(ω_max/5] and ω_max , the amplitude power control will be acquired. What we have studied is very important to realize constant output power.