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Sample records for charge-to-time converter asic

  1. High-speed charge-to-time converter ASIC for the Super-Kamiokande detector

    Energy Technology Data Exchange (ETDEWEB)

    Nishino, H., E-mail: nishino@post.kek.j [Institute for Cosmic Ray Research, University of Tokyo, Chiba 277-8582 (Japan); Awai, K.; Hayato, Y.; Nakayama, S.; Okumura, K.; Shiozawa, M.; Takeda, A. [Institute for Cosmic Ray Research, University of Tokyo, Chiba 277-8582 (Japan); Ishikawa, K.; Minegishi, A. [Iwatsu Test Instruments Corporation, Tokyo 168-8511 (Japan); Arai, Y. [The Institute of Particle and Nuclear Studies, KEK, Ibaraki 305-0801 (Japan)

    2009-11-11

    A new application-specific integrated circuit (ASIC), the high-speed charge-to-time converter (QTC) IWATSU CLC101, provides three channels, each consisting of preamplifier, discriminator, low-pass filter, and charge integration circuitry, optimized for the waveform of a photomultiplier tube (PMT). This ASIC detects PMT signals using individual built-in discriminators and drives output timing signals whose width represents the integrated charge of the PMT signal. Combined with external input circuits composed of passive elements, the QTC provides full analog signal processing for the detector's PMTs, ready for further processing by time-to-digital converters (TDCs). High-rate (>1MHz) signal processing is achieved by short-charge-conversion-time and baseline-restoration circuits. Wide-range charge measurements are enabled by offering three gain ranges while maintaining a short cycle time. QTC chip test results show good analog performance, with efficient detection for a single photoelectron signal, four orders of magnitude dynamic range (0.3mVapprox3V; 0.2approx2500pC), 1% charge linearity, 0.2 pC charge resolution, and 0.1 ns timing resolution. Test results on ambient temperature dependence, channel isolation, and rate dependence also meet specifications.

  2. High-speed charge-to-time converter ASIC for the Super-Kamiokande detector

    International Nuclear Information System (INIS)

    Nishino, H.; Awai, K.; Hayato, Y.; Nakayama, S.; Okumura, K.; Shiozawa, M.; Takeda, A.; Ishikawa, K.; Minegishi, A.; Arai, Y.

    2009-01-01

    A new application-specific integrated circuit (ASIC), the high-speed charge-to-time converter (QTC) IWATSU CLC101, provides three channels, each consisting of preamplifier, discriminator, low-pass filter, and charge integration circuitry, optimized for the waveform of a photomultiplier tube (PMT). This ASIC detects PMT signals using individual built-in discriminators and drives output timing signals whose width represents the integrated charge of the PMT signal. Combined with external input circuits composed of passive elements, the QTC provides full analog signal processing for the detector's PMTs, ready for further processing by time-to-digital converters (TDCs). High-rate (>1MHz) signal processing is achieved by short-charge-conversion-time and baseline-restoration circuits. Wide-range charge measurements are enabled by offering three gain ranges while maintaining a short cycle time. QTC chip test results show good analog performance, with efficient detection for a single photoelectron signal, four orders of magnitude dynamic range (0.3mV∼3V; 0.2∼2500pC), 1% charge linearity, 0.2 pC charge resolution, and 0.1 ns timing resolution. Test results on ambient temperature dependence, channel isolation, and rate dependence also meet specifications.

  3. Seven channel gated charge to time converter

    Energy Technology Data Exchange (ETDEWEB)

    Stubbs, R J; Waddoup, W D [Durham Univ. (UK)

    1977-11-01

    By using a hybrid integrated circuit seven independent gated charge to time converters have been constructed in a single width NIM module. Gate widths from < approximately 10 ns to approximately 300 ns are possible with a resolution of 0.25 pC, linearity is better than +-1 pC over 2.5 decades of input signal height. Together with a multichannel scaling system described in the following paper one has a very powerful multichannel gated ADC system.

  4. Monolitic integrated circuit for the strobed charge-to-time converter

    International Nuclear Information System (INIS)

    Bel'skij, V.I.; Bushnin, Yu.B.; Zimin, S.A.; Punzhin, Yu.N.; Sen'ko, V.A.; Soldatov, M.M.; Tokarchuk, V.P.

    1985-01-01

    The developed and comercially produced semiconducting circuit - gating charge-to-time converter KR1101PD1 is described. The considered integrated circuit is a short pulse charge-to-time converter with integration of input current. The circuit is designed for construction of time-to-pulse analog-to-digital converters utilized in multichannel detection systems when studying complex topology processes. Input resistance of the circuit is 0.1 Ω permissible input current is 50 mA, maximum measured charge is 300-1000 pC

  5. Method of signal detection from silicon photomultipliers using fully differential Charge to Time Converter and fast shaper

    International Nuclear Information System (INIS)

    Baszczyk, M.; Dorosz, P.; Glab, S.; Kucewicz, W.; Mik, L.; Sapor, M.

    2016-01-01

    The paper presents an implementation of fully differential readout method for Silicon Photomultipliers (SiPM). Front-end electronics consists of a fast and slow path. The former creates the trigger signal while the latter produces a pulse of width proportional to the input charge. The fast shaper generates unipolar pulse and utilizes the pole-zero cancelation circuit. The peaking time for single photoelectron is equal to 3.6 ns and the FWHM is 3.8 ns. The pulse width of the Charge to Time Converter (QTC) depends on the number of photons entering the SiPM at the moment of measurement. The QTC response is nonlinear but it allows us to work with signals in a wide dynamic range. The proposed readout method is effective in measurements of random signals where frequent events tend to pile-up. Thermal generation and afterpulses have a strong influence on the width of pulses from QTC. The proposed method enables us to distinguish those overlapping signals and get the reliable information on the number of detected photons.

  6. Method of signal detection from silicon photomultipliers using fully differential Charge to Time Converter and fast shaper

    Energy Technology Data Exchange (ETDEWEB)

    Baszczyk, M., E-mail: baszczyk@agh.edu.pl [AGH University of Science and Technology, Department of Electronics, Krakow (Poland); Dorosz, P.; Glab, S.; Kucewicz, W. [AGH University of Science and Technology, Department of Electronics, Krakow (Poland); Mik, L. [AGH University of Science and Technology, Department of Electronics, Krakow (Poland); State Higher Vocational School, Tarnow (Poland); Sapor, M. [AGH University of Science and Technology, Department of Electronics, Krakow (Poland)

    2016-07-11

    The paper presents an implementation of fully differential readout method for Silicon Photomultipliers (SiPM). Front-end electronics consists of a fast and slow path. The former creates the trigger signal while the latter produces a pulse of width proportional to the input charge. The fast shaper generates unipolar pulse and utilizes the pole-zero cancelation circuit. The peaking time for single photoelectron is equal to 3.6 ns and the FWHM is 3.8 ns. The pulse width of the Charge to Time Converter (QTC) depends on the number of photons entering the SiPM at the moment of measurement. The QTC response is nonlinear but it allows us to work with signals in a wide dynamic range. The proposed readout method is effective in measurements of random signals where frequent events tend to pile-up. Thermal generation and afterpulses have a strong influence on the width of pulses from QTC. The proposed method enables us to distinguish those overlapping signals and get the reliable information on the number of detected photons.

  7. A multichannel time-to-digital converter ASIC with better than 3 ps RMS time resolution

    International Nuclear Information System (INIS)

    Perktold, L; Christiansen, J

    2014-01-01

    The development of a new multichannel, fine-time resolution time-to-digital converter (TDC) ASIC is currently under development at CERN. A prototype TDC has been designed, fabricated and successfully verified with demonstrated time resolutions of better than 3 ps-rms. Least-significant-bit (LSB) sizes as small as 5 ps with a differential-non-linearity (DNL) of better than ±0.9 LSB and integral-non-linearity (INL) of better than ±1.3 LSB respectively have been achieved. The contribution describes the implemented architecture and presents measurement results of a prototype ASIC implemented in a commercial 130 nm technology

  8. A 9-Channel, 100 ps LSB Time-to-Digital Converter for the NA62 Gigatracker Readout ASIC (TDCpix)

    International Nuclear Information System (INIS)

    Perktold, L; Rinella, G Aglieri; Noy, M; Kluge, A; Kloukinas, K; Kaplon, J; Jarron, P; Morel, M; Fiorini, M; Martin, E

    2012-01-01

    The TDCpix ASIC is the readout chip for the Gigatracker station of the NA62 experiment. Each station of the Gigatracker needs to provide time stamping of individual particles to 200 ps-rms or better. Bump-bonded to the pixel sensor the ASIC serves an array of 40 columns x 40 pixels. The high precision time measurement of the discriminated hit signals is accomplished with a set of 40 TDCs sitting in the End-Of-Column region of the ASIC. Each TDC provides 9 channels per column. For the time-to-digital converter (TDC) a delay-locked-loop (DLL) approach is employed to achieve a constant time binning of 100 ps. Simulation results show that an average rms time resolution of 33 ps with a power consumption of the TDC better than 33 mW per column is achieved. This contribution will present the design, simulation results and implementation challenges of the TDC.

  9. A four channel time-to-digital converter ASIC with in-built calibration and SPI interface

    International Nuclear Information System (INIS)

    Hari Prasad, K.; Sukhwani, Menka; Saxena, Pooja; Chandratre, V.B.; Pithawa, C.K.

    2014-01-01

    A design of high resolution, wide dynamic range Time-to-Digital Converter (TDC) ASIC, implemented in 0.35 µm commercial CMOS technology is presented. The ASIC features four channel TDC with an in-built calibration and Serial Peripheral Interconnect (SPI) slave interface. The TDC is based on the vernier ring oscillator method in order to achieve both high resolution and wide dynamic range. This TDC ASIC is tested and found to have resolution of 127 ps (LSB), dynamic range of 1.8 µs and precision (σ) of 74 ps. The measured values of differential non-linearity (DNL) and integral non-linearity (INL) are 350 ps and 300 ps respectively

  10. Hybrid integrated circuit for charge-to-time interval conversion

    Energy Technology Data Exchange (ETDEWEB)

    Basiladze, S.G.; Dotsenko, Yu.Yu.; Man' yakov, P.K.; Fedorchenko, S.N. (Joint Inst. for Nuclear Research, Dubna (USSR))

    The hybrid integrated circuit for charge-to time interval conversion with nanosecond input fast response is described. The circuit can be used in energy measuring channels, time-to-digital converters and in the modified variant in amplitude-to-digital converters. The converter described consists of a buffer amplifier, a linear transmission circuit, a direct current source and a unit of time interval separation. The buffer amplifier represents a current follower providing low input and high output resistances by the current feedback. It is concluded that the described converter excelled the QT100B circuit analogous to it in a number of parameters especially, in thermostability.

  11. Development of a time-to-digital converter ASIC for the upgrade of the ATLAS Monitored Drift Tube detector

    Science.gov (United States)

    Wang, Jinhong; Liang, Yu; Xiao, Xiong; An, Qi; Chapman, John W.; Dai, Tiesheng; Zhou, Bing; Zhu, Junjie; Zhao, Lei

    2018-02-01

    The upgrade of the ATLAS muon spectrometer for the high-luminosity LHC requires new trigger and readout electronics for various elements of the detector. We present the design of a time-to-digital converter (TDC) ASIC prototype for the ATLAS Monitored Drift Tube (MDT) detector. The chip was fabricated in a GlobalFoundries 130 nm CMOS technology. Studies indicate that its timing and power dissipation characteristics meet the design specifications, with a timing bin variation of ±40 ps for all 48 TDC slices and a power dissipation of about 6.5 mW per slice.

  12. A 41 ps ASIC time-to-digital converter for physics experiments

    International Nuclear Information System (INIS)

    Russo, Stefano; Petra, Nicola; De Caro, Davide; Barbarino, Giancarlo; Strollo, Antonio G.M.

    2011-01-01

    We present a novel Time-to-Digital (TDC) converter for physics experiments. Proposed TDC is based on a synchronous counter and an asynchronous fine interpolator. The fine part of the measurement is obtained using NORA inverters that provide improved resolution. A prototype IC was fabricated in 180 nm CMOS technology. Experimental measurements show that proposed TDC features 41 ps resolution associated with 0.35LSB differential non-linearity, 0.77LSB integral non-linearity and a negligible single shot precision. The whole dynamic range is equal to 18μs. The proposed TDC is designed using a flash architecture that reduces dead time. Data reported in the paper show that our design is well suited for present and future particle physics experiments.

  13. SPACIROC2: a front-end readout ASIC for the JEM-EUSO observatory

    International Nuclear Information System (INIS)

    Ahmad, S; Barrillon, P; Blin-Bondil, S; Dagoret-Campagne, S; Taille, C de La; Dulucq, F; Martin-Chassard, G; Kawasaki, Y; Miyamoto, H; Ikeda, H; Iguchi, T; Kajino, F

    2013-01-01

    The SPACIROC ASIC is designed for the JEM-EUSO observatory onboard of the International Space Station (ISS). The main goal of JEM-EUSO is to observe Extensive Air Shower (EAS) produced in the atmosphere by the passage of the high energetic extraterrestrial particles above a few 10 19 eV. A low-power, rad-hard ASIC is proposed for reading out the 64-channel Multi-Anode Photomultipliers which are going to equip the detection surface of JEM-EUSO. The two main features of this ASIC are the photon counting mode for each input and the charge-to-time (Q-to-T) conversion for the multiplexed channels. In the photon counting mode, the 100% triggering efficiency is achieved for 50 fC input charges. For the Q-to-T converter, the ASIC requires a minimum input of 2 pC. In order to comply with the strict power budget available from the ISS, the ASIC is needed to dissipate less than 1 mW/channel. The design of SPACIROC and the test results are presented in this paper.

  14. A multichannel front end ASIC for PMT readout in LHAASO WCDA

    Science.gov (United States)

    Liang, Y.; Zhao, L.; Guo, Y.; Qin, J.; Yang, Y.; Cheng, B.; Liu, S.; An, Q.

    2018-01-01

    Time and charge measurements over a large dynamic range from 1 Photo Electron (P.E.) to 4000 P.E. are required for the Water Cherenkov Detector Array (WCDA), which is one of the key components in the Large High Altitude Air Shower Observatory (LHAASO). To simplify the circuit structure of the readout electronics, a front end ASIC was designed. Based on the charge-to-time conversion method, the output pulse width of the ASIC corresponds to the input signal charge information while time information of the input signal is picked off through a discriminator, and thus the time and charge information can be digitized simultaneously using this ASIC and a following Time-to-Digital Converter (TDC). To address the challenge of mismatch among the channels observed in the previous prototype version, this work presents approaches for analyzing the problem and optimizing the circuits. A new version of the ASIC was designed and fabricated in the GLOBALFOUNDRIES 0.35 μm CMOS technology, which integrates 6 channels (corresponding to the readout of the 3 PMTs) in each chip. The test results indicate that the mismatch between the channels is significantly reduced to less than 20% using the proposed approach. The time measurement resolution better than 300 ps is achieved, and the charge measurement resolution is better than 10% at 1 P.E., and 1% at 4000 P.E., which meets the application requirements.

  15. SODR Memory Control Buffer Control ASIC

    Science.gov (United States)

    Hodson, Robert F.

    1994-01-01

    The Spacecraft Optical Disk Recorder (SODR) is a state of the art mass storage system for future NASA missions requiring high transmission rates and a large capacity storage system. This report covers the design and development of an SODR memory buffer control applications specific integrated circuit (ASIC). The memory buffer control ASIC has two primary functions: (1) buffering data to prevent loss of data during disk access times, (2) converting data formats from a high performance parallel interface format to a small computer systems interface format. Ten 144 p in, 50 MHz CMOS ASIC's were designed, fabricated and tested to implement the memory buffer control function.

  16. Command Interface ASIC - Analog Interface ASIC Chip Set

    Science.gov (United States)

    Ruiz, Baldes; Jaffe, Burton; Burke, Gary; Lung, Gerald; Pixler, Gregory; Plummer, Joe; Katanyoutanant,, Sunant; Whitaker, William

    2003-01-01

    A command interface application-specific integrated circuit (ASIC) and an analog interface ASIC have been developed as a chip set for remote actuation and monitoring of a collection of switches, which can be used to control generic loads, pyrotechnic devices, and valves in a high-radiation environment. The command interface ASIC (CIA) can be used alone or in combination with the analog interface ASIC (AIA). Designed primarily for incorporation into spacecraft control systems, they are also suitable for use in high-radiation terrestrial environments (e.g., in nuclear power plants and facilities that process radioactive materials). The primary role of the CIA within a spacecraft or other power system is to provide a reconfigurable means of regulating the power bus, actuating all valves, firing all pyrotechnic devices, and controlling the switching of power to all switchable loads. The CIA is a mixed-signal (analog and digital) ASIC that includes an embedded microcontroller with supporting fault-tolerant switch control and monitoring circuitry that is capable of connecting to a redundant set of interintegrated circuit (I(sup 2)C) buses. Commands and telemetry requests are communicated to the CIA. Adherence to the I(sup 2)C bus standard helps to reduce development costs by facilitating the use of previously developed, commercially available components. The AIA is a mixed-signal ASIC that includes the analog circuitry needed to connect the CIA to a custom higher powered version of the I(sup 2)C bus. The higher-powered version is designed to enable operation with bus cables longer than those contemplated in the I(sup 2)C standard. If there are multiple higher-power I(sup 2)C-like buses, then there must an AIA between the CIA and each such bus. The AIA includes two identical interface blocks: one for the side-A I(sup 2)C clock and data buses and the other for the side B buses. All the AIAs on each side are powered from a common power converter module (PCM). Sides A and B

  17. Estimating Delays In ASIC's

    Science.gov (United States)

    Burke, Gary; Nesheiwat, Jeffrey; Su, Ling

    1994-01-01

    Verification is important aspect of process of designing application-specific integrated circuit (ASIC). Design must not only be functionally accurate, but must also maintain correct timing. IFA, Intelligent Front Annotation program, assists in verifying timing of ASIC early in design process. This program speeds design-and-verification cycle by estimating delays before layouts completed. Written in C language.

  18. ASIC design at Fermilab

    International Nuclear Information System (INIS)

    Yarema, R.

    1991-06-01

    In the past few years, ASIC (Application Specific Integrated Circuit) design has become important at Fermilab. The purpose of this paper is to present an overview of the in-house ASIC design activity which has taken place. This design effort has added much value to the high energy physics program and physics capability at Fermilab. The two approaches to ASIC development being pursued at Fermilab are examined by looking at some of the types of projects where ASICs are being used or contemplated. To help estimate the cost of future designs, a cost comparison is given to show the relative development and production expenses for these two ASIC approaches. 5 refs., 14 figs., 7 tabs

  19. ASIC proteins regulate smooth muscle cell migration.

    Science.gov (United States)

    Grifoni, Samira C; Jernigan, Nikki L; Hamilton, Gina; Drummond, Heather A

    2008-03-01

    The purpose of the present study was to investigate Acid Sensing Ion Channel (ASIC) protein expression and importance in cellular migration. We recently demonstrated that Epithelial Na(+)Channel (ENaC) proteins are required for vascular smooth muscle cell (VSMC) migration; however, the role of the closely related ASIC proteins has not been addressed. We used RT-PCR and immunolabeling to determine expression of ASIC1, ASIC2, ASIC3 and ASIC4 in A10 cells. We used small interference RNA to silence individual ASIC expression and determine the importance of ASIC proteins in wound healing and chemotaxis (PDGF-bb)-initiated migration. We found ASIC1, ASIC2, and ASIC3, but not ASIC4, expression in A10 cells. ASIC1, ASIC2, and ASIC3 siRNA molecules significantly suppressed expression of their respective proteins compared to non-targeting siRNA (RISC) transfected controls by 63%, 44%, and 55%, respectively. Wound healing was inhibited by 10, 20, and 26% compared to RISC controls following suppression of ASIC1, ASIC2, and ASIC3, respectively. Chemotactic migration was inhibited by 30% and 45%, respectively, following suppression of ASIC1 and ASIC3. ASIC2 suppression produced a small, but significant, increase in chemotactic migration (4%). Our data indicate that ASIC expression is required for normal migration and may suggest a novel role for ASIC proteins in cellular migration.

  20. Memory, microprocessor, and ASIC

    CERN Document Server

    Chen, Wai-Kai

    2003-01-01

    System Timing. ROM/PROM/EPROM. SRAM. Embedded Memory. Flash Memories. Dynamic Random Access Memory. Low-Power Memory Circuits. Timing and Signal Integrity Analysis. Microprocessor Design Verification. Microprocessor Layout Method. Architecture. ASIC Design. Logic Synthesis for Field Programmable Gate Array (EPGA) Technology. Testability Concepts and DFT. ATPG and BIST. CAD Tools for BIST/DFT and Delay Faults.

  1. Simultaneous Disruption of Mouse ASIC1a, ASIC2 and ASIC3 Genes Enhances Cutaneous Mechanosensitivity

    Science.gov (United States)

    Kang, Sinyoung; Jang, Jun Ho; Price, Margaret P.; Gautam, Mamta; Benson, Christopher J.; Gong, Huiyu; Welsh, Michael J.; Brennan, Timothy J.

    2012-01-01

    Three observations have suggested that acid-sensing ion channels (ASICs) might be mammalian cutaneous mechanoreceptors; they are structurally related to Caenorhabditis elegans mechanoreceptors, they are localized in specialized cutaneous mechanosensory structures, and mechanical displacement generates an ASIC-dependent depolarization in some neurons. However, previous studies of mice bearing a single disrupted ASIC gene showed only subtle or no alterations in cutaneous mechanosensitivity. Because functional redundancy of ASIC subunits might explain limited phenotypic alterations, we hypothesized that disrupting multiple ASIC genes would markedly impair cutaneous mechanosensation. We found the opposite. In behavioral studies, mice with simultaneous disruptions of ASIC1a, -2 and -3 genes (triple-knockouts, TKOs) showed increased paw withdrawal frequencies when mechanically stimulated with von Frey filaments. Moreover, in single-fiber nerve recordings of cutaneous afferents, mechanical stimulation generated enhanced activity in A-mechanonociceptors of ASIC TKOs compared to wild-type mice. Responses of all other fiber types did not differ between the two genotypes. These data indicate that ASIC subunits influence cutaneous mechanosensitivity. However, it is unlikely that ASICs directly transduce mechanical stimuli. We speculate that physical and/or functional association of ASICs with other components of the mechanosensory transduction apparatus contributes to normal cutaneous mechanosensation. PMID:22506072

  2. Acid-sensing ion channels (ASICs) in mouse skeletal muscle afferents are heteromers composed of ASIC1a, ASIC2, and ASIC3 subunits

    Science.gov (United States)

    Gautam, Mamta; Benson, Christopher J.

    2013-01-01

    Acid-sensing ion channels (ASICs) are expressed in skeletal muscle afferents, in which they sense extracellular acidosis and other metabolites released during ischemia and exercise. ASICs are formed as homotrimers or heterotrimers of several isoforms (ASIC1a, ASIC1b, ASIC2a, ASIC2b, and ASIC3), with each channel displaying distinct properties. To dissect the ASIC composition in muscle afferents, we used whole-cell patch-clamp recordings to study the properties of acid-evoked currents (amplitude, pH sensitivity, the kinetics of desensitization and recovery from desensitization, and pharmacological modulation) in isolated, labeled mouse muscle afferents from wild-type (C57BL/6J) and specific ASIC−/− mice. We found that ASIC-like currents in wild-type muscle afferents displayed fast desensitization, indicating that they are carried by heteromeric channels. Currents from ASIC1a−/− muscle afferents were less pH-sensitive and displayed faster recovery, currents from ASIC2−/− mice showed diminished potentiation by zinc, and currents from ASIC3−/− mice displayed slower desensitization than those from wild-type mice. Finally, ASIC-like currents were absent from triple-null mice lacking ASIC1a, ASIC2a, and ASIC3. We conclude that ASIC1a, ASIC2a, and ASIC3 heteromers are the principle channels in skeletal muscle afferents. These results will help us understand the role of ASICs in exercise physiology and provide a molecular target for potential drug therapies to treat muscle pain.—Gautam, M., Benson, C. J. Acid-sensing ion channels (ASICs) in mouse skeletal muscle afferents are heteromers composed of ASIC1a, ASIC2, and ASIC3 subunits. PMID:23109675

  3. The expression profile of acid-sensing ion channel (ASIC) subunits ASIC1a, ASIC1b, ASIC2a, ASIC2b, and ASIC3 in the esophageal vagal afferent nerve subtypes.

    Science.gov (United States)

    Dusenkova, Svetlana; Ru, Fei; Surdenikova, Lenka; Nassenstein, Christina; Hatok, Jozef; Dusenka, Robert; Banovcin, Peter; Kliment, Jan; Tatar, Milos; Kollarik, Marian

    2014-11-01

    Acid-sensing ion channels (ASICs) have been implicated in esophageal acid sensing and mechanotransduction. However, insufficient knowledge of ASIC subunit expression profile in esophageal afferent nerves hampers the understanding of their role. This knowledge is essential because ASIC subunits form heteromultimeric channels with distinct functional properties. We hypothesized that the esophageal putative nociceptive C-fiber nerves (transient receptor potential vanilloid 1, TRPV1-positive) express multiple ASIC subunits and that the ASIC expression profile differs between the nodose TRPV1-positive subtype developmentally derived from placodes and the jugular TRPV1-positive subtype derived from neural crest. We performed single cell RT-PCR on the vagal afferent neurons retrogradely labeled from the esophagus. In the guinea pig, nearly all (90%-95%) nodose and jugular esophageal TRPV1-positive neurons expressed ASICs, most often in a combination (65-75%). ASIC1, ASIC2, and ASIC3 were expressed in 65-75%, 55-70%, and 70%, respectively, of both nodose and jugular TRPV1-positive neurons. The ASIC1 splice variants ASIC1a and ASIC1b and the ASIC2 splice variant ASIC2b were similarly expressed in both nodose and jugular TRPV1-positive neurons. However, ASIC2a was found exclusively in the nodose neurons. In contrast to guinea pig, ASIC3 was almost absent from the mouse vagal esophageal TRPV1-positive neurons. However, ASIC3 was similarly expressed in the nonnociceptive TRPV1-negative (tension mechanoreceptors) neurons in both species. We conclude that the majority of esophageal vagal nociceptive neurons express multiple ASIC subunits. The placode-derived nodose neurons selectively express ASIC2a, known to substantially reduce acid sensitivity of ASIC heteromultimers. ASIC3 is expressed in the guinea pig but not in the mouse vagal esophageal TRPV1-positive neurons, indicating species differences in ASIC expression. Copyright © 2014 the American Physiological Society.

  4. Acid-sensing ion channels (ASICs) in mouse skeletal muscle afferents are heteromers composed of ASIC1a, ASIC2, and ASIC3 subunits

    OpenAIRE

    Gautam, Mamta; Benson, Christopher J.

    2013-01-01

    Acid-sensing ion channels (ASICs) are expressed in skeletal muscle afferents, in which they sense extracellular acidosis and other metabolites released during ischemia and exercise. ASICs are formed as homotrimers or heterotrimers of several isoforms (ASIC1a, ASIC1b, ASIC2a, ASIC2b, and ASIC3), with each channel displaying distinct properties. To dissect the ASIC composition in muscle afferents, we used whole-cell patch-clamp recordings to study the properties of acid-evoked currents (amplitu...

  5. A Radiation Hardened by Design CMOS ASIC for Thermopile Readouts

    Science.gov (United States)

    Quilligan, G.; Aslam, S.; DuMonthier, J.

    2012-01-01

    A radiation hardened by design (RHBD) mixed-signal application specific integrated circuit (ASIC) has been designed for a thermopile readout for operation in the harsh Jovian orbital environment. The multi-channel digitizer (MCD) ASIC includes 18 low noise amplifier channels which have tunable gain/filtering coefficients, a 16-bit sigma-delta analog-digital converter (SDADC) and an on-chip controller. The 18 channels, SDADC and controller were designed to operate with immunity to single event latchup (SEL) and to at least 10 Mrad total ionizing dose (TID). The ASIC also contains a radiation tolerant 16-bit 20 MHz Nyquist ADC for general purpose instrumentation digitizer needs. The ASIC is currently undergoing fabrication in a commercial 180 nm CMOS process. Although this ASIC was designed specifically for the harsh radiation environment of the NASA led JEO mission it is suitable for integration into instrumentation payloads 011 the ESA JUICE mission where the radiation hardness requirements are slightly less stringent.

  6. ASIC1 and ASIC3 Play Different Roles in the Development of Hyperalgesia Following Inflammatory Muscle Injury

    OpenAIRE

    Walder, R.Y.; Rasmussen, L.A.; Rainier, J.D.; Light, A.R.; Wemmie, J.A.; Sluka, K.A.

    2009-01-01

    Acid-sensing ion channels (ASICs) respond to acidosis that normally occurs after inflammation. We examined the expression of ASIC1, ASIC2, and ASIC3 mRNAs in lumbar DRG neurons before and 24h after carrageenan-induced muscle inflammation. Muscle inflammation causes bilateral increases of ASIC2 and ASIC3, but not ASIC1 (neither ASIC1a nor ASIC1b) mRNA, suggesting differential regulation of ASIC1 versus ASIC2 and ASIC3 mRNA. Similar mRNA increases were observed following inflammation in knockou...

  7. Beamsteerable GNSS Radio Occultation ASIC

    Data.gov (United States)

    National Aeronautics and Space Administration — We will develop an integrated RF ASIC to enable high quality radio occultation (RO) weather observations using the Global Navigations System Satellite (GNSS)...

  8. Mongoose ASIC microcontroller programming guide

    Science.gov (United States)

    Smith, Brian S.

    1993-01-01

    The 'Mongoose' ASIC microcontroller is a radiation-hard implementation of the R3000 microprocessor. This document describes the internals of the microcontroller in a level of detail necessary for someone implementing a software design.

  9. ASIC-enabled High Resolution Optical Time Domain Reflectometer

    Science.gov (United States)

    Skendzic, Sandra

    Fiber optics has become the preferred technology in communication systems because of what it has to offer: high data transmission rates, immunity to electromagnetic interference, and lightweight, flexible cables. An optical time domain reflectometer (OTDR) provides a convenient method of locating and diagnosing faults (e.g. break in a fiber) along a fiber that can obstruct crucial optical pathways. Both the ability to resolve the precise location of the fault and distinguish between two discrete, closely spaced faults are figures of merit. This thesis presents an implementation of a high resolution OTDR through the use of a compact and programmable ASIC (application specific integrated circuit). The integration of many essential OTDR functions on a single chip is advantageous over existing commercial instruments because it enables small, lightweight packaging, and offers low power and cost efficiency. Furthermore, its compactness presents the option of placing multiple ASICs in parallel, which can conceivably ease the characterization of densely populated fiber optic networks. The OTDR ASIC consists of a tunable clock, pattern generator, precise timer, electrical receiver, and signal sampling circuit. During OTDR operation, the chip generates narrow electrical pulse, which can then be converted to optical format when coupled with an external laser diode driver. The ASIC also works with an external photodetector to measure the timing and amplitude of optical reflections in a fiber. It has a 1 cm sampling resolution, which allows for a 2 cm spatial resolution. While this OTDR ASIC has been previously demonstrated for multimode fiber fault diagnostics, this thesis focuses on extending its functionality to single mode fiber. To validate this novel approach to OTDR, this thesis is divided into five chapters: (1) introduction, (2) implementation, (3), performance of ASIC-based OTDR, (4) exploration in optical pre-amplification with a semiconductor optical amplifier, and

  10. The multichannel amplifier/discriminator CMOS ASIC for visual light photon counters

    International Nuclear Information System (INIS)

    Baturitsky, M.A.; Yurenya, Yu.P.Yu.P.

    2002-01-01

    The 18-channel CMOS custom monolithic amplifier/discriminator ASIC was designed as a front-end electronics chip for Visual Light Photon Counters which convert photons from scintillation fibre/strip detectors to electrical signals. One ASICs channel contains a charge-sensitive preamplifier, a discriminator to mark the arrival time of signals, and a charge divider to provide analog outputs for analog-to-digital conversion being performed by SVX2. The ASIC is proposed as one of the variants for possible future front-end electronics upgrading the D0 Central Fibre Tracker, Central and Forward Pre-Showers (Fermilab, Batavia, USA)

  11. ASIC PROTEINS REGULATE SMOOTH MUSCLE CELL MIGRATION

    OpenAIRE

    Grifoni, Samira C.; Jernigan, Nikki L.; Hamilton, Gina; Drummond, Heather A.

    2007-01-01

    The purpose of the present study was to investigate Acid Sensing Ion Channel (ASIC) protein expression and importance in cellular migration. We recently demonstrated Epithelial Na+ Channel (ENaC) proteins are required for vascular smooth muscle cell (VSMC) migration, however the role of the closely related ASIC proteins has not been addressed. We used RT-PCR and immunolabeling to determine expression of ASIC1, ASIC2, ASIC3 and ASIC4 in A10 cells. We used small interference RNA to silence indi...

  12. Localization and Behaviors in Null Mice Suggest that ASIC1 and ASIC2 Modulate Responses to Aversive Stimuli

    OpenAIRE

    Price, Margaret P.; Gong, Huiyu; Parsons, Meredith G.; Kundert, Jacob R.; Reznikov, Leah R.; Bernardinelli, Luisa; Chaloner, Kathryn; Buchanan, Gordon F.; Wemmie, John A.; Richerson, George B.; Cassell, Martin D.; Welsh, Michael J.

    2013-01-01

    Acid sensing ion channels (ASICs) generate H+-gated Na+ currents that contribute to neuronal function and animal behavior. Like ASIC1, ASIC2 subunits are expressed in the brain and multimerize with ASIC1 to influence acid-evoked currents and facilitate ASIC1 localization to dendritic spines. To better understand how ASIC2 contributes to brain function, we localized the protein and tested the behavioral consequences of ASIC2 gene disruption. For comparison, we also localized ASIC1 and studied ...

  13. ASIC design in the KM3NeT detector

    International Nuclear Information System (INIS)

    Gajanana, D; Gromov, V; Timmer, P

    2013-01-01

    In the KM3NeT project [1], Cherenkov light from the muon interactions with transparent matter around the detector, is used to detect neutrinos. Photo multiplier tubes (PMT) used as photon sensor, are housed in a glass sphere (aka Optical Module) to detect single photons from the Cherenkov light. The PMT needs high operational voltage ( ∼ 1.5 kV) and is generated by a Cockroft-Walton (CW) multiplier circuit. The electronics required to control the PMT's and collect the signals is integrated in two ASIC's namely: 1) a front-end mixed signal ASIC (PROMiS) for the readout of the PMT and 2) an analog ASIC (CoCo) to generate pulses for charging the CW circuit and to control the feedback of the CW circuit. In this article, we discuss the two integrated circuits and test results of the complete setup. PROMiS amplifies the input charge, converts it to a pulse width and delivers the information via LVDS signals. These LVDS signals carry accurate information on the Time of arrival ( 2 C bus. This unique combination of the ASIC's results in a very cost and power efficient PMT base design.

  14. ASIC3 channels in multimodal sensory perception.

    Science.gov (United States)

    Li, Wei-Guang; Xu, Tian-Le

    2011-01-19

    Acid-sensing ion channels (ASICs), which are members of the sodium-selective cation channels belonging to the epithelial sodium channel/degenerin (ENaC/DEG) family, act as membrane-bound receptors for extracellular protons as well as nonproton ligands. At least five ASIC subunits have been identified in mammalian neurons, which form both homotrimeric and heterotrimeric channels. The highly proton sensitive ASIC3 channels are predominantly distributed in peripheral sensory neurons, correlating with their roles in multimodal sensory perception, including nociception, mechanosensation, and chemosensation. Different from other ASIC subunit composing ion channels, ASIC3 channels can mediate a sustained window current in response to mild extracellular acidosis (pH 7.3-6.7), which often occurs accompanied by many sensory stimuli. Furthermore, recent evidence indicates that the sustained component of ASIC3 currents can be enhanced by nonproton ligands including the endogenous metabolite agmatine. In this review, we first summarize the growing body of evidence for the involvement of ASIC3 channels in multimodal sensory perception and then discuss the potential mechanisms underlying ASIC3 activation and mediation of sensory perception, with a special emphasis on its role in nociception. We conclude that ASIC3 activation and modulation by diverse sensory stimuli represent a new avenue for understanding the role of ASIC3 channels in sensory perception. Furthermore, the emerging implications of ASIC3 channels in multiple sensory dysfunctions including nociception allow the development of new pharmacotherapy.

  15. SPIDR, a general-purpose readout system for pixel ASICs

    International Nuclear Information System (INIS)

    Heijden, B. van der; Visser, J.; Beuzekom, M. van; Boterenbrood, H.; Munneke, B.; Schreuder, F.; Kulis, S.

    2017-01-01

    The SPIDR (Speedy PIxel Detector Readout) system is a flexible general-purpose readout platform that can be easily adapted to test and characterize new and existing detector readout ASICs. It is originally designed for the readout of pixel ASICs from the Medipix/Timepix family, but other types of ASICs or front-end circuits can be read out as well. The SPIDR system consists of an FPGA board with memory and various communication interfaces, FPGA firmware, CPU subsystem and an API library on the PC . The FPGA firmware can be adapted to read out other ASICs by re-using IP blocks. The available IP blocks include a UDP packet builder, 1 and 10 Gigabit Ethernet MAC's and a 'soft core' CPU . Currently the firmware is targeted at the Xilinx VC707 development board and at a custom board called Compact-SPIDR . The firmware can easily be ported to other Xilinx 7 series and ultra scale FPGAs. The gap between an ASIC and the data acquisition back-end is bridged by the SPIDR system. Using the high pin count VITA 57 FPGA Mezzanine Card (FMC) connector only a simple chip carrier PCB is required. A 1 and a 10 Gigabit Ethernet interface handle the connection to the back-end. These can be used simultaneously for high-speed data and configuration over separate channels. In addition to the FMC connector, configurable inputs and outputs are available for synchronization with other detectors. A high resolution (≈ 27 ps bin size) Time to Digital converter is provided for time stamping events in the detector. The SPIDR system is frequently used as readout for the Medipix3 and Timepix3 ASICs. Using the 10 Gigabit Ethernet interface it is possible to read out a single chip at full bandwidth or up to 12 chips at a reduced rate. Another recent application is the test-bed for the VeloPix ASIC, which is developed for the Vertex Detector of the LHCb experiment. In this case the SPIDR system processes the 20 Gbps scrambled data stream from the VeloPix and distributes it over four

  16. Multi-channel Waveform Sampling ASIC for radiation detection and measurement

    International Nuclear Information System (INIS)

    Shimazoe, K.; Takahashi, H.; Yeom, J.Y.; Furumiya, T.; Ohi, J.

    2013-01-01

    We have designed and fabricated a 16-channel Waveform Sampling ASIC for radiation detection and measurement. Waveform sampling is very important for the pulse shape analysis and discrimination, which is often used in radiation detection to discriminate different radiations such as alpha, beta and gamma rays. One channel of the fabricated ASIC consists of a charge-sensitive preamplifier, a VGA (Variable Gain Amplifier), an ADC (Analog to Digital Converter) and digital circuits. The preamplifier converts the current signal to the voltage signal, and the VGA amplifies the signal to appropriate level for the ADC. The ADC was designed to digitize the waveform with a frequency of 100 MHz and a resolution of 6bits. Digital circuits consist of a free-running ADC and a multiplexer which were designed to convert a digitized 100 MHz/6bit signal to a 200 MHz/3bit one, which is effective for the reduction of the number and for the achievement of the high integration in one chip. This chip was designed and fabricated with 0.35 μm CMOS technology by ROHM and the size of the ASIC is 4.9 mm by 4.9 mm. The design concept and some experimental results are shown in this paper. -- Highlights: ► Waveform sampling (WS) ASIC is newly developed for pulse shape discrimination. ► WS ASIC can be used for radiation measurement and discrimination. ► WS ASIC is fabricated by submicron CMOS technology for 5 mm × 5 mm area. ► WS ASIC achieves high integration and can be used in very limited space

  17. Rad-Hard Structured ASIC Body of Knowledge

    Science.gov (United States)

    Heidecker, Jason

    2013-01-01

    Structured Application-Specific Integrated Circuit (ASIC) technology is a platform between traditional ASICs and Field-Programmable Gate Arrays (FPGA). The motivation behind structured ASICs is to combine the low nonrecurring engineering costs (NRE) costs of FPGAs with the high performance of ASICs. This report provides an overview of the structured ASIC platforms that are radiation-hardened and intended for space application

  18. Digital Heart-Rate Variability Parameter Monitoring and Assessment ASIC.

    Science.gov (United States)

    Massagram, W; Hafner, N; Mingqi Chen; Macchiarulo, L; Lubecke, V M; Boric-Lubecke, O

    2010-02-01

    This paper describes experimental results for an application-specific integrated circuit (ASIC), designed for digital heart rate variability (HRV) parameter monitoring and assessment. This ASIC chip measures beat-to-beat (RR) intervals and stores HRV parameters into its internal memory in real time. A wide range of short-term and long-term ECG signals obtained from Physionet was used for testing. The system detects R peaks with millisecond accuracy, and stores up to 2 min of continuous RR interval data and up to 4 min of RR interval histogram. The prototype chip was fabricated in a 0.5 ¿m complementary metal-oxide semiconductor technology on a 3×3 mm(2) die area, with a measured dynamic power consumption of 10 ¿W and measured leakage current of 2.62 nA. The HRV monitoring system including this HRV ASIC, an analog-to-digital converter, and a low complexity microcontroller was estimated to consume 32.5 ¿V, which is seven times lower power than a stand-alone microcontroller performing the same functions. Compact size, low cost, and low power consumption make this chip suitable for a miniaturized portable HRV monitoring system.

  19. Phase-II Associative Memory ASIC Specifications

    CERN Document Server

    Stabile, Alberto; Warren, Matthew; Green, Barry; Konstantinidis, Nikolaos; Motuk, Halil Erdem; Frontini, Luca; Liberali, Valentino; Crescioli, Francesco; Fedi, Giacomo; Sotiropoulou, Calliope-louisa; De Canio, Francesco; Traversi, Gianluca; Shojaii, Seyed Ruhollah; Kubota, Takashi; Calderini, Giovanni; Palla, Fabrizio; Checcucci, Bruno; Spiller, Laurence Anthony; Mcnamara, Peter Charles

    2018-01-01

    This documents defines the specifications for the Associative Memory ASIC for Phase-II. The work-flow toward the final ASIC is organized in the following three steps • AM08 prototype: small area MPW prototype to test all the full custom features, the VHDL logic and the I/O. This chip must be fully functional with smaller memory area than the final ASIC; • AM09pre pre-production: full area ASIC to be fabricated with a full-mask set pilot run. Production corner wafers will be created; • AM09 production: full area ASIC with refinements for the mass production. The AM09 will be developed built on the AM08 extending the memory area, therefore the specification of both versions must be compatible.

  20. A new interface weak-capacitance detection ASIC of capacitive liquid level sensor in the rocket

    Science.gov (United States)

    Yin, Liang; Qin, Yao; Liu, Xiao-Wei

    2017-11-01

    A new capacitive liquid level sensing interface weak-capacitance detection ASIC has been designed. This ASIC realized the detection of the output capacitance of the capacitive liquid level sensor, which converts the output capacitance of the capacitive liquid level sensor to voltage. The chip is fabricated in a standard 0.5μm CMOS process. The test results show that the linearity of capacitance detection of the ASIC is 0.05%, output noise is 3.7aF/Hz (when the capacitance which will be detected is 40 pF), the stability of capacitance detection is 7.4 × 10-5pF (1σ, 1h), the output zero position temperature coefficient is 4.5 uV/∘C. The test results prove that this interface ASIC can meet the requirement of high accuracy capacitance detection. Therefore, this interface ASIC can be applied in capacitive liquid level sensing and capacitive humidity sensing field.

  1. ASIC subunit ratio and differential surface trafficking in the brain.

    Science.gov (United States)

    Wu, Junjun; Xu, Yuanyuan; Jiang, Yu-Qing; Xu, Jiangping; Hu, Youjia; Zha, Xiang-ming

    2016-01-08

    Acid-sensing ion channels (ASICs) are key mediators of acidosis-induced responses in neurons. However, little is known about the relative abundance of different ASIC subunits in the brain. Such data are fundamental for interpreting the relative contribution of ASIC1a homomers and 1a/2 heteromers to acid signaling, and essential for designing therapeutic interventions to target these channels. We used a simple biochemical approach and semi-quantitatively determined the molar ratio of ASIC1a and 2 subunits in mouse brain. Further, we investigated differential surface trafficking of ASIC1a, ASIC2a, and ASIC2b. ASIC1a subunits outnumber the sum of ASIC2a and ASIC2b. There is a region-specific variation in ASIC2a and 2b expression, with cerebellum and striatum expressing predominantly 2b and 2a, respectively. Further, we performed surface biotinylation and found that surface ASIC1a and ASIC2a ratio correlates with their total expression. In contrast, ASIC2b exhibits little surface presence in the brain. This result is consistent with increased co-localization of ASIC2b with an ER marker in 3T3 cells. Our data are the first semi-quantitative determination of relative subunit ratio of various ASICs in the brain. The differential surface trafficking of ASICs suggests that the main functional ASICs in the brain are ASIC1a homomers and 1a/2a heteromers. This finding provides important insights into the relative contribution of various ASIC complexes to acid signaling in neurons.

  2. Acid-Sensing Ion Channel 2a (ASIC2a) Promotes Surface Trafficking of ASIC2b via Heteromeric Assembly

    OpenAIRE

    Kweon, Hae-Jin; Kim, Dong-Il; Bae, Yeonju; Park, Jae-Yong; Suh, Byung-Chang

    2016-01-01

    Acid-sensing ion channels (ASICs) are proton-activated cation channels that play important roles as typical proton sensors during pathophysiological conditions and normal synaptic activities. Among the ASIC subunits, ASIC2a and ASIC2b are alternative splicing products from the same gene, ACCN1. It has been shown that ASIC2 isoforms have differential subcellular distribution: ASIC2a targets the cell surface by itself, while ASIC2b resides in the ER. However, the underlying mechanism for this d...

  3. Heteromeric ASIC channels composed of ASIC2b and ASIC1a display novel channel properties and contribute to acidosis-induced neuronal death

    Science.gov (United States)

    Sherwood, Thomas W.; Lee, Kirsten G.; Gormley, Matthew G.; Askwith, Candice C.

    2011-01-01

    Acid-sensing ion channel (ASIC) subunits associate to form homomeric or heteromeric proton-gated ion channels in neurons throughout the nervous system. The ASIC1a subunit plays an important role in establishing the kinetics of proton-gated currents in the central nervous system and activation of ASIC1a homomeric channels induces neuronal death following local acidosis that accompanies cerebral ischemia. The ASIC2b subunit is expressed in the brain in a pattern that overlaps ASIC1a, yet the contribution of ASIC2b has remained elusive. We find that co-expression of ASIC2b with ASIC1a in Xenopus oocytes results in novel proton-gated currents with properties distinct from ASIC1a homomeric channels. In particular, ASIC2b/1a heteromeric channels are inhibited by the non-selective potassium channel blockers tetraethylammonium (TEA) and barium. In addition, steady-state desensitization is induced at more basic pH values and Big Dynorphin sensitivity is enhanced in these unique heteromeric channels. Cultured hippocampal neurons show proton-gated currents consistent with ASIC2b contribution and these currents are lacking in neurons from mice with an ACCN1 (ASIC2) gene disruption. Finally, we find that these ASIC2b/1a heteromeric channels contribute to acidosis-induced neuronal death. Together, our results show that ASIC2b confers unique properties to heteromeric channels in central neurons. Further, these data indicate that ASIC2, like ASIC1, plays a role in acidosis-induced neuronal death and implicate the ASIC2b/1a subtype as a novel pharmacological target to prevent neuronal injury following stroke. PMID:21715637

  4. High Rate Digital Demodulator ASIC

    Science.gov (United States)

    Ghuman, Parminder; Sheikh, Salman; Koubek, Steve; Hoy, Scott; Gray, Andrew

    1998-01-01

    The architecture of High Rate (600 Mega-bits per second) Digital Demodulator (HRDD) ASIC capable of demodulating BPSK and QPSK modulated data is presented in this paper. The advantages of all-digital processing include increased flexibility and reliability with reduced reproduction costs. Conventional serial digital processing would require high processing rates necessitating a hardware implementation in other than CMOS technology such as Gallium Arsenide (GaAs) which has high cost and power requirements. It is more desirable to use CMOS technology with its lower power requirements and higher gate density. However, digital demodulation of high data rates in CMOS requires parallel algorithms to process the sampled data at a rate lower than the data rate. The parallel processing algorithms described here were developed jointly by NASA's Goddard Space Flight Center (GSFC) and the Jet Propulsion Laboratory (JPL). The resulting all-digital receiver has the capability to demodulate BPSK, QPSK, OQPSK, and DQPSK at data rates in excess of 300 Mega-bits per second (Mbps) per channel. This paper will provide an overview of the parallel architecture and features of the HRDR ASIC. In addition, this paper will provide an over-view of the implementation of the hardware architectures used to create flexibility over conventional high rate analog or hybrid receivers. This flexibility includes a wide range of data rates, modulation schemes, and operating environments. In conclusion it will be shown how this high rate digital demodulator can be used with an off-the-shelf A/D and a flexible analog front end, both of which are numerically computer controlled, to produce a very flexible, low cost high rate digital receiver.

  5. AVME readout module for multichannel ASIC characterization

    International Nuclear Information System (INIS)

    Borkar, S.P.; Lalwani, S.K.; Ghodgaonkar, M.D.; Kataria, S.K.; Reynaud, Serge; )

    2004-01-01

    Electronics Division, BARC has been working on the development of multi-channel ASIC, called SPAIR (Silicon-strip Pulse Amplifier Integrated Readout). It contains 8 channels of preamplifier, shaper and track-and-hold circuitry. Electronics Division has also actively participated in development of test setup for the front-end ASIC, called PACE, for the preshower detector of the Compact Muon Solenoid (CMS) Experiment at CERN, Geneva. PACE is a 32 channel ASIC for silicon strip detector, containing preamplifier, shaper, calibration circuitry, switched capacitor array, readout amplifier per channel and an analog multiplexer. A VME Readout Module, (VRM) is developed which can be utilized in data acquisition from ASICs like PACE and SPAIR. The VRM can also be used as the Detector Dependent Unit for digitally processing the data received from the front-end electronics on the 16-bit LVDS port. The processed, data can be read by the VME system. Thus the VRM is very useful in building an ASIC characterization system and/or the automated ASIC production testing system. It can be used also to build the applications using such ASICs. To cater to various requirements arising in future, variety of VME modules are to be developed like ADCs, DACs and D 1/0. VME interface remains a common part to all these modules. The different functional blocks of these modules can be designed and fabricated on small piggyback boards (called Test Boards) and mounted on the VRM, which provides the common VME interface. The design details and uses of VRM are presented here. (author)

  6. The Panda Strip Asic: Pasta

    Science.gov (United States)

    Lai, A.

    2018-01-01

    PASTA is the 64 channel front-end chip, designed in a 110 nm CMOS technology to read out the strip sensors of the Micro Vertex Detector (MVD) of the PANDA experiment. This chip provides high resolution timestamp and deposited charge information by means of the time-over-threshold technique. Its working principle is based on a predecessor, the TOFPET ASIC, that was designed for medical applications. A general restructuring of the architecture was needed, in order to meet the specific requirements imposed by the physics programme of PANDA, especially in terms of radiation tolerance, spatial constraints, and readout in absence of a first level hardware trigger. The first revision of PASTA is currently under evaluation at the Forschungszentrum Jülich, where a data acquisition system dedicated to the MVD prototypes has been developed. This paper describes the main aspect of the chip design, gives an overview of the data acquisition system used for the verification, and shows the first results regarding the performance of PASTA.

  7. AMPLITUDE AND TIME MEASUREMENT ASIC WITH ANALOG DERANDOMIZATION

    International Nuclear Information System (INIS)

    O CONNOR, P.; DE GERONIMO, G.; KANDASAMY, A.

    2002-01-01

    We describe a new ASIC for accurate and efficient processing of high-rate pulse signals from highly segmented detectors. In contrast to conventional approaches, this circuit affords a dramatic reduction in data volume through the use of analog techniques (precision peak detectors and time-to-amplitude converters) together with fast arbitration and sequencing logic to concentrate the data before digitization. In operation the circuit functions like a data-driven analog first-in, first-out (FIFO) memory between the preamplifiers and the ADC. Peak amplitudes of pulses arriving at any one of the 32 inputs are sampled, stored, and queued for readout and digitization through a single output port. Hit timing, pulse risetime, and channel address are also available at the output. Prototype chips have been fabricated in 0.35 micron CMOS and tested. First results indicate proper functionality for pulses down to 30 ns peaking time and input rates up to 1.6 MHz/channel. Amplitude accuracy of the peak detect and hold circuit is 0.3% (absolute). TAC accuracy is within 0.3% of full scale. Power consumption is less than 2 mW/channel. Compared with conventional techniques such as track-and-hold and analog memory, this new ASIC will enable efficient pulse height measurement at 20 to 300 times higher rates

  8. Timing and control requirements for a 32-channel AMU-ADC ASIC for the PHENIX detector

    International Nuclear Information System (INIS)

    Emery, M.S.; Ericson, M.N.; Britton, C.L. Jr.

    1998-01-01

    A custom CMOS Application Specific Integrated Circuit (ASIC) has been developed consisting of an analog memory unit (AMU) has been developed consisting of an analog memory unit (AMU) and analog to digital converter (ADC), both of which have been designed for applications in the PHENIX experiment. This IC consists of 32 pipes of analog memory with 64 cells per pipe. Each pipe also has its own ADC channel. Timing and control signal requirements for optimum performance are discussed in this paper

  9. 2nd generation ASICs for CALICE/EUDET calorimeters

    International Nuclear Information System (INIS)

    Dulucq, F; Fleury, J; La Taille, C de; Martin-Chassard, G; Raux, L; Seguin-Moreau, N

    2009-01-01

    Imaging calorimetry depends heavily on the development of high performance, highly integrated readout ASICs embedded inside the detector which readout the millions of foreseen channels. Suitable ASICs prototypes have been fabricated in 2006-2007 and show good preliminary performance.

  10. Burst Mode ASIC-Based Modem

    Science.gov (United States)

    1997-01-01

    The NASA Lewis Research Center is sponsoring the Advanced Communication Technology Insertion (ACTION) for Commercial Space Applications program. The goal of the program is to expedite the development of new technology with a clear path towards productization and enhancing the competitiveness of U.S. manufacturers. The industry has made significant investment in developing ASIC-based modem technology for continuous-mode applications and has made investigations into East, reliable acquisition of burst-mode digital communication signals. With rapid advances in analog and digital communications ICs, it is expected that more functions will be integrated onto these parts in the near future. In addition custom ASIC's can also be developed to address the areas not covered by the other IC's. Using the commercial chips and custom ASIC's, lower-cost, compact, reliable, and high-performance modems can be built for demanding satellite communication application. This report outlines a frequency-hop burst modem design based on commercially available chips.

  11. Characterisation of the NA62 GigaTracker end of column readout ASIC

    International Nuclear Information System (INIS)

    Noy, M; Rinella, G Aglieri; Fiorini, M; Jarron, P; Kaplon, J; Kluge, A; Morel, M; Perktold, L; Riedler, P; Martin, E

    2011-01-01

    The architecture and characterisation of the End Of Column demonstrator readout ASIC for the NA62 GigaTracker hybrid pixel detector is presented. This ASIC serves as a proof of principle for a pixel chip with 1800 pixels which must perform time stamping to better than 200 ps (RMS), provide 300 μm pitch position information and operate with a dead-time of 1% or less for 800 MHz-1 GHz beam rate. The demonstrator ASIC comprises a full test column with 45 pixels alongside other test structures. The timewalk correction mechanism employed is measurement of the time-over-threshold, coupled with an off-detector look-up table. The time to digital converter is a delay locked loop with 32 contributing delay cells fed with a 320 MHz to yield a nominal bin size of 97 ps. Recently, P-in-N sensors have been bump-bonded to the ASIC and characterisation of these assemblies has begun.

  12. A wireless capsule system with ASIC for monitoring the physiological signals of the human gastrointestinal tract.

    Science.gov (United States)

    Xu, Fei; Yan, Guozheng; Zhao, Kai; Lu, Li; Gao, Jinyang; Liu, Gang

    2014-12-01

    This paper presents the design of a wireless capsule system for monitoring the physiological signals of the human gastrointestinal (GI) tract. The primary components of the system include a wireless capsule, a portable data recorder, and a workstation. Temperature, pH, and pressure sensors; an RF transceiver; a controlling and processing application specific integrated circuit (ASIC); and batteries were applied in a wireless capsule. Decreasing capsule size, improving sensor precision, and reducing power needs were the primary challenges; these were resolved by employing micro sensors, optimized architecture, and an ASIC design that include power management, clock management, a programmable gain amplifier (PGA), an A/D converter (ADC), and a serial peripheral interface (SPI) communication unit. The ASIC has been fabricated in 0.18- μm CMOS technology with a die area of 5.0 mm × 5.0 mm. The wireless capsule integrating the ASIC controller measures Φ 11 mm × 26 mm. A data recorder and a workstation were developed, and 20 cases of human experiments were conducted in hospitals. Preprocessing in the workstation can significantly improve the quality of the data, and 76 original features were determined by mathematical statistics. Based on the 13 optimal features achieved in the evaluation of the features, the clustering algorithm can identify the patients who lack GI motility with a recognition rate reaching 83.3%.

  13. Test vehicles for CMS HGCAL readout ASIC

    CERN Document Server

    Thienpont, Damien

    2017-01-01

    This paper presents first measurement results of two test vehicles ASIC embedding some building blocks for the future CMS High Granularity CALorimeter (HGCAL) read-out ASIC. They were fabricated in CMOS 130 nm, in order to first design the Analog and Mixed-Signal blocks before going to a complete and complex chip. Such a circuit needs to achieve low noise high dynamic range charge measurement and 20 ps resolution timing capability. The results show good analog performance but with higher noise levels compared to simulations. We present the results of the preamplifiers, shapers and ADCs.

  14. Proton and non-proton activation of ASIC channels.

    Directory of Open Access Journals (Sweden)

    Ivan Gautschi

    Full Text Available The Acid-Sensing Ion Channels (ASIC exhibit a fast desensitizing current when activated by pH values below 7.0. By contrast, non-proton ligands are able to trigger sustained ASIC currents at physiological pHs. To analyze the functional basis of the ASIC desensitizing and sustained currents, we have used ASIC1a and ASIC2a mutants with a cysteine in the pore vestibule for covalent binding of different sulfhydryl reagents. We found that ASIC1a and ASIC2a exhibit two distinct currents, a proton-induced desensitizing current and a sustained current triggered by sulfhydryl reagents. These currents differ in their pH dependency, their sensitivity to the sulfhydryl reagents, their ionic selectivity and their relative magnitude. We propose a model for ASIC1 and ASIC2 activity where the channels can function in two distinct modes, a desensitizing mode and a sustained mode depending on the activating ligands. The pore vestibule of the channel represents a functional site for binding non-proton ligands to activate ASIC1 and ASIC2 at neutral pH and to prevent channel desensitization.

  15. Proton and non-proton activation of ASIC channels.

    Science.gov (United States)

    Gautschi, Ivan; van Bemmelen, Miguel Xavier; Schild, Laurent

    2017-01-01

    The Acid-Sensing Ion Channels (ASIC) exhibit a fast desensitizing current when activated by pH values below 7.0. By contrast, non-proton ligands are able to trigger sustained ASIC currents at physiological pHs. To analyze the functional basis of the ASIC desensitizing and sustained currents, we have used ASIC1a and ASIC2a mutants with a cysteine in the pore vestibule for covalent binding of different sulfhydryl reagents. We found that ASIC1a and ASIC2a exhibit two distinct currents, a proton-induced desensitizing current and a sustained current triggered by sulfhydryl reagents. These currents differ in their pH dependency, their sensitivity to the sulfhydryl reagents, their ionic selectivity and their relative magnitude. We propose a model for ASIC1 and ASIC2 activity where the channels can function in two distinct modes, a desensitizing mode and a sustained mode depending on the activating ligands. The pore vestibule of the channel represents a functional site for binding non-proton ligands to activate ASIC1 and ASIC2 at neutral pH and to prevent channel desensitization.

  16. ASIC For Complex Fixed-Point Arithmetic

    Science.gov (United States)

    Petilli, Stephen G.; Grimm, Michael J.; Olson, Erlend M.

    1995-01-01

    Application-specific integrated circuit (ASIC) performs 24-bit, fixed-point arithmetic operations on arrays of complex-valued input data. High-performance, wide-band arithmetic logic unit (ALU) designed for use in computing fast Fourier transforms (FFTs) and for performing ditigal filtering functions. Other applications include general computations involved in analysis of spectra and digital signal processing.

  17. Abnormal Cardiac Autonomic Regulation in Mice Lacking ASIC3

    Directory of Open Access Journals (Sweden)

    Ching-Feng Cheng

    2014-01-01

    Full Text Available Integration of sympathetic and parasympathetic outflow is essential in maintaining normal cardiac autonomic function. Recent studies demonstrate that acid-sensing ion channel 3 (ASIC3 is a sensitive acid sensor for cardiac ischemia and prolonged mild acidification can open ASIC3 and evoke a sustained inward current that fires action potentials in cardiac sensory neurons. However, the physiological role of ASIC3 in cardiac autonomic regulation is not known. In this study, we elucidate the role of ASIC3 in cardiac autonomic function using Asic3−/− mice. Asic3−/− mice showed normal baseline heart rate and lower blood pressure as compared with their wild-type littermates. Heart rate variability analyses revealed imbalanced autonomic regulation, with decreased sympathetic function. Furthermore, Asic3−/− mice demonstrated a blunted response to isoproterenol-induced cardiac tachycardia and prolonged duration to recover to baseline heart rate. Moreover, quantitative RT-PCR analysis of gene expression in sensory ganglia and heart revealed that no gene compensation for muscarinic acetylcholines receptors and beta-adrenalin receptors were found in Asic3−/− mice. In summary, we unraveled an important role of ASIC3 in regulating cardiac autonomic function, whereby loss of ASIC3 alters the normal physiological response to ischemic stimuli, which reveals new implications for therapy in autonomic nervous system-related cardiovascular diseases.

  18. Prototype of a transient waveform recording ASIC

    Science.gov (United States)

    Qin, J.; Zhao, L.; Cheng, B.; Chen, H.; Guo, Y.; Liu, S.; An, Q.

    2018-01-01

    The paper presents the design and measurement results of a transient waveform recording ASIC based on the Switched Capacitor Array (SCA) architecture. This 0.18 μm CMOS prototype device contains two channels and each channel employs a SCA of 128 samples deep, a 12-bit Wilkinson ADC and a serial data readout. A series of tests have been conducted and the results indicate that: a full 1 V signal voltage range is available, the input analog bandwidth is approximately 450 MHz and the sampling speed is adjustable from 0.076 to 3.2 Gsps (Gigabit Samples Per Second). For precision waveform timing extraction, careful calibration of timing intervals between samples is conducted to improve the timing resolution of such chips, and the timing precision of this ASIC is proved to be better than 15 ps RMS.

  19. A distributed current stimulator ASIC for high density neural stimulation.

    Science.gov (United States)

    Jeong Hoan Park; Chaebin Kim; Seung-Hee Ahn; Tae Mok Gwon; Joonsoo Jeong; Sang Beom Jun; Sung June Kim

    2016-08-01

    This paper presents a novel distributed neural stimulator scheme. Instead of a single stimulator ASIC in the package, multiple ASICs are embedded at each electrode site for stimulation with a high density electrode array. This distributed architecture enables the simplification of wiring between electrodes and stimulator ASIC that otherwise could become too complex as the number of electrode increases. The individual ASIC chip is designed to have a shared data bus that independently controls multiple stimulating channels. Therefore, the number of metal lines is determined by the distributed ASICs, not by the channel number. The function of current steering is also implemented within each ASIC in order to increase the effective number of channels via pseudo channel stimulation. Therefore, the chip area can be used more efficiently. The designed chip was fabricated with area of 0.3 mm2 using 0.18 μm BCDMOS process, and the bench-top test was also conducted to validate chip performance.

  20. VMM - An ASIC for Micropattern Detectors

    Directory of Open Access Journals (Sweden)

    Iakovidis George

    2018-01-01

    Full Text Available The VMM is a custom Application Specific Integrated Circuit (ASIC that can be used in a variety of charge interpolating tracking detectors. It is designed to be used with the resistive strip micromegas and sTGC detectors in the New Small Wheel upgrade of the ATLAS Muon spectrometer. The ASIC is designed at Brookhaven National Laboratory and fabricated in the 130 nm Global Foundries 8RF-DM process. It is packaged in a Ball Grid Array with outline dimensions of 21×21 mm2. It integrates 64 channels, each providing charge amplification, discrimination, neighbour logic, amplitude and timing measurements, analog-to-digital conversions, and either direct output for trigger or multiplexed readout. The front-end amplifier can operate with a wide range of input capacitances, has adjustable polarity, gain and peaking time. The VMM1 and VMM2 are the first two versions of the VMM ASIC family fabricated in 2012 and 2014 respectively. The design, tests and qualification of the VMM1, VMM2 and roadmap to VMM3 are described.

  1. Latest generation of ASICs for photodetector readout

    International Nuclear Information System (INIS)

    Seguin-Moreau, N.

    2013-01-01

    The OMEGA microelectronics group has designed a new generation of multichannel integrated circuits, the “ROC” family, in AustrianMicroSystem (AMS) SiGe 0.35 μm technology to read out signals from various families of photodetectors. The chip named MAROC (standing for Multi Anode ReadOut Chip) has been designed to read out MultiAnode Photomultipliers (MAPMT), Photomultiplier ARray In SiGe ReadOut Chip (PARISROC) to read out Photomultipliers (PMTs) and SiPM Integrated ReadOut Chip (SPIROC) to readout Silicon PhotoMultiplier (SiPM) detectors and which was the first ASIC to do so. The three of them fulfill the stringent requirements of the future photodetectors, in particular in terms of low noise, radiation hardness, large dynamic range, high density and high speed while keeping low power thanks to the SiGe technology. These multi-channel ASICs are real System on Chip (SoC) as they provide charge, time and photon-counting information which are digitized internally. Their complexity and versatility enable innovative frontier detectors and also cover spin off of these detectors in adjacent fields such as medical or material imaging as well as smart detectors. In this presentation, the three ASIC architectures and test results will be described to give a general panorama of the “ROC” chips

  2. VMM - An ASIC for Micropattern Detectors

    Science.gov (United States)

    Iakovidis, George

    2018-02-01

    The VMM is a custom Application Specific Integrated Circuit (ASIC) that can be used in a variety of charge interpolating tracking detectors. It is designed to be used with the resistive strip micromegas and sTGC detectors in the New Small Wheel upgrade of the ATLAS Muon spectrometer. The ASIC is designed at Brookhaven National Laboratory and fabricated in the 130 nm Global Foundries 8RF-DM process. It is packaged in a Ball Grid Array with outline dimensions of 21×21 mm2. It integrates 64 channels, each providing charge amplification, discrimination, neighbour logic, amplitude and timing measurements, analog-to-digital conversions, and either direct output for trigger or multiplexed readout. The front-end amplifier can operate with a wide range of input capacitances, has adjustable polarity, gain and peaking time. The VMM1 and VMM2 are the first two versions of the VMM ASIC family fabricated in 2012 and 2014 respectively. The design, tests and qualification of the VMM1, VMM2 and roadmap to VMM3 are described.

  3. Latest generation of ASICs for photodetector readout

    Science.gov (United States)

    Seguin-Moreau, N.

    2013-08-01

    The OMEGA microelectronics group has designed a new generation of multichannel integrated circuits, the "ROC" family, in AustrianMicroSystem (AMS) SiGe 0.35 μm technology to read out signals from various families of photodetectors. The chip named MAROC (standing for Multi Anode ReadOut Chip) has been designed to read out MultiAnode Photomultipliers (MAPMT), Photomultiplier ARray In SiGe ReadOut Chip (PARISROC) to read out Photomultipliers (PMTs) and SiPM Integrated ReadOut Chip (SPIROC) to readout Silicon PhotoMultiplier (SiPM) detectors and which was the first ASIC to do so. The three of them fulfill the stringent requirements of the future photodetectors, in particular in terms of low noise, radiation hardness, large dynamic range, high density and high speed while keeping low power thanks to the SiGe technology. These multi-channel ASICs are real System on Chip (SoC) as they provide charge, time and photon-counting information which are digitized internally. Their complexity and versatility enable innovative frontier detectors and also cover spin off of these detectors in adjacent fields such as medical or material imaging as well as smart detectors. In this presentation, the three ASIC architectures and test results will be described to give a general panorama of the "ROC" chips.

  4. Latest generation of ASICs for photodetector readout

    Energy Technology Data Exchange (ETDEWEB)

    Seguin-Moreau, N., E-mail: seguin@lal.in2p3.fr [Laboratoire de l’Accélérateur Linéaire, IN2P3-CNRS, Université Paris-Sud, Bâtiment 200, 91898 Orsay Cedex (France)

    2013-08-01

    The OMEGA microelectronics group has designed a new generation of multichannel integrated circuits, the “ROC” family, in AustrianMicroSystem (AMS) SiGe 0.35 μm technology to read out signals from various families of photodetectors. The chip named MAROC (standing for Multi Anode ReadOut Chip) has been designed to read out MultiAnode Photomultipliers (MAPMT), Photomultiplier ARray In SiGe ReadOut Chip (PARISROC) to read out Photomultipliers (PMTs) and SiPM Integrated ReadOut Chip (SPIROC) to readout Silicon PhotoMultiplier (SiPM) detectors and which was the first ASIC to do so. The three of them fulfill the stringent requirements of the future photodetectors, in particular in terms of low noise, radiation hardness, large dynamic range, high density and high speed while keeping low power thanks to the SiGe technology. These multi-channel ASICs are real System on Chip (SoC) as they provide charge, time and photon-counting information which are digitized internally. Their complexity and versatility enable innovative frontier detectors and also cover spin off of these detectors in adjacent fields such as medical or material imaging as well as smart detectors. In this presentation, the three ASIC architectures and test results will be described to give a general panorama of the “ROC” chips.

  5. VMM - An ASIC for micropattern detectors

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00215906; The ATLAS collaboration; Polychronakos, Venetios; De Geronimo, Gianluigi

    2015-01-01

    The VMM is a custom Application Specific Integrated Circuit (ASIC) that can be used in a variety of charge interpolating tracking detectors. It is designed to be used with the resistive strip micromegas and sTGC detectors in the New Small Wheel upgrade of the ATLAS Muon spectrometer. The ASIC is designed at Brookhaven National Laboratory and fabricated in the 130 nm Global Foundries 8RF-DM process. It is packaged in a Ball Grid Array with outline dimensions of 21 $\\times$ 21 mm$^2$. It integrates 64 channels, each providing charge amplification, discrimination, neighbour logic, amplitude and timing measurements, analog-to-digital conversions, and either direct output for trigger or multiplexed readout. The front-end amplifier can operate with a wide range of input capacitances, has adjustable polarity, gain and peaking time. The VMM1 and VMM2 are the first two versions of the VMM ASIC family fabricated in 2012 and 2014 respectively. The design, tests and qualification of the VMM1, VMM2 and roadmap to VMM3 are...

  6. Two Aspects of ASIC Function: Synaptic Plasticity and Neuronal Injury.

    Science.gov (United States)

    Huang, Yan; Jiang, Nan; Li, Jun; Ji, Yong-Hua; Xiong, Zhi-Gang; Zha, Xiang-ming

    2015-01-01

    Extracellular brain pH fluctuates in both physiological and disease conditions. The main postsynaptic proton receptor is the acid-sensing ion channels (ASICs). During the past decade, much progress has been made on protons, ASICs, and neurological disease. This review summarizes the recent progress on synaptic role of protons and our current understanding of how ASICs contribute to various types of neuronal injury in the brain. PMID:25582290

  7. Expert System for ASIC Imaging

    Science.gov (United States)

    Gupta, Shri N.; Arshak, Khalil I.; McDonnell, Pearse; Boyce, Conor; Duggan, Andrew

    1989-07-01

    With the developments in the techniques of artificial intelligence over the last few years, development of advisory, scheduling and similar class of problems has become very convenient using tools such as PROLOG. In this paper an expert system has been described which helps lithographers and process engineers in several ways. The methodology used is to model each work station according to its input, output and control parameters, combine these work stations in a logical sequence based on past experience and work out process schedule for a job. In addition, all the requirements vis-a-vis a particular job parameters are converted into decision rules. One example is the exposure time, develop time for a wafer with different feature sizes would be different. This expert system has been written in Turbo Prolog. By building up a large number of rules, one can tune the program to any facility and use it for as diverse applications as advisory help, trouble shooting etc. Leitner (1) has described an advisory expert system that is being used at National Semiconductor. This system is quite different from the one being reported in the present paper. The approach is quite different for one. There is stress on job flow and process for another.

  8. The Role of Custom Design in ASIC Chips

    National Research Council Canada - National Science Library

    Dally, William

    1998-01-01

    The performance of an ASIC can be greatly improved without increasing design time by judiciously employing a number of custom design techniques, including floorplanning, prerouting critical signals...

  9. Low noise preamplifier ASIC for the PANDA experiment

    International Nuclear Information System (INIS)

    Flemming, H; Wieczorek, P

    2011-01-01

    For the electromagnetic calorimeter of the PANDA detector a preamplifier ASIC named APFEL (ASIC for Panda Front-end ELectronics) has been developed at GSI. It is optimized for the readout of large area avalanche photodiodes (LAAPDs) with a capacitance of 300 pF and an event rate of 350 kHz. The ASIC has two equivalent analog channels each consisting of a charge sensitive amplifier, a shaper stage and differential output drivers. For operating the ASIC in a wide temperature range programmable voltage references are implemented on chip.

  10. Configurable Radiation Hardened High Speed Isolated Interface ASIC, Phase I

    Data.gov (United States)

    National Aeronautics and Space Administration — NVE Corporation will design and build an innovative, low cost, flexible, configurable, radiation hardened, galvanically isolated, interface ASIC chip set that will...

  11. A 130 nm ASIC prototype for the NA62 Gigatracker readout

    Energy Technology Data Exchange (ETDEWEB)

    Dellacasa, G., E-mail: gdellaca@to.infn.it [I.N.F.N. sez. Torino, via Giuria 1, 10125 Torino (Italy); Garbolino, S. [Universita degli Studi di Torino, Dip. Fisica Sperimentale, via Giuria 1, 10125 Torino (Italy); Marchetto, F. [I.N.F.N. sez. Torino, via Giuria 1, 10125 Torino (Italy); Martoiu, S. [I.N.F.N. sez. Torino, via Giuria 1, 10125 Torino (Italy); CERN CH-1211, Geneve 23 (Switzerland); Mazza, G.; Rivetti, A.; Wheadon, R. [I.N.F.N. sez. Torino, via Giuria 1, 10125 Torino (Italy)

    2011-09-11

    One of the most challenging detectors of the NA62 experiment is the silicon tracker, called Gigatracker. It consists of three hybrid silicon pixel stations, each one covering an area of 27 mmx60 mm. While the maximum pixel size is fairly large, 300{mu}mx300{mu}m the system has to sustain a very high particle rate, 1.5 MHz/mm{sup 2}, which corresponds to 800 MHz for each station. To obtain an efficient tracking with such a high rate the required track timing resolution is 150 ps (rms). Therefore the front-end ASIC should provide for each pixel a 200 ps time measurement capability, thus leading to the requirement of time walk compensation and very compact TDCs. Moreover, Single Event Upset protection has to be implemented in order to protect the digital circuitry. An ASIC prototype has been realized in CMOS 130 nm technology, containing three pixel columns. The chip performs the time walk compensation by a Constant Fraction Discriminator circuit, while the time measurement is performed by a Time to Amplitude Converter based TDC, both of them implemented on each pixel cell. The End of Column circuit containing only digital logic is responsible for the data readout from the pixel cell. The whole chip works with a system clock of 160 MHz and the digital logic is SEU protected by the use of Hamming codes. The detailed architecture of the ASIC prototype and test results are presented.

  12. PARISROC, an autonomous front-end ASIC for triggerless acquisition in next generation neutrino experiments

    International Nuclear Information System (INIS)

    Conforti Di Lorenzo, S.; Campagne, J.E.; Drouet, S.; Dulucq, F.; El Berni, M.; Genolini, B.; La Taille, C. de; Martin-Chassard, G.; Seguin Moreau, N.; Wanlin, E.; Xiangbo, Y.

    2012-01-01

    PARISROC (Photomultiplier ARray Integrated in SiGe ReadOut Chip) is a complete readout chip in AustriaMicroSystems (AMS) SiGe 0.35 μm technology designed to read array of 16 Photomultipliers (PMTs). The ASIC is realized in the context of the PMm2 (square meter PhotoMultiplier) project that has proposed a new system of “smart photo-detectors” composed by sensor and read-out electronics dedicated to next generation neutrino experiments. The future water Cherenkov detectors will take place in megaton size water tanks then with a large surface of photo-detection. We propose to segment the large surface in arrays with a single front-end electronics and only the useful data send in surface to be stocked and analyzed. This paper describes the second version of the ASIC and illustrates the chip principle of operation and the main characteristics thank to a series of measurements. It is a 16-channel ASIC with channels that work independently, in triggerless mode and all managed by a common digital part. Then main innovation is that all the channels are handled independently by the digital part so that only channels that have triggered are digitized. Then the data are transferred to the internal memory and sent out in a data driven way. The ASIC allows charge and time measurement. We measured a charge measurement range starting from 160 fC (1 photoelectron-p.e., at PMT gain of 10 6 ) to 100 pC (around 600 p.e.) at 1% of linearity; time tagging at 1 ns thanks to a 24-bit counter at 10 MHz and a Time to Digital Converter (TDC) on a 100 ns ramp.

  13. PARISROC, an autonomous front-end ASIC for triggerless acquisition in next generation neutrino experiments

    Science.gov (United States)

    Conforti Di Lorenzo, S.; Campagne, J. E.; Drouet, S.; Dulucq, F.; El Berni, M.; Genolini, B.; de La Taille, C.; Martin-Chassard, G.; Seguin Moreau, N.; Wanlin, E.; Xiangbo, Y.

    2012-12-01

    PARISROC (Photomultiplier ARray Integrated in SiGe ReadOut Chip) is a complete readout chip in AustriaMicroSystems (AMS) SiGe 0.35 μm technology designed to read array of 16 Photomultipliers (PMTs). The ASIC is realized in the context of the PMm2 (square meter PhotoMultiplier) project that has proposed a new system of “smart photo-detectors” composed by sensor and read-out electronics dedicated to next generation neutrino experiments. The future water Cherenkov detectors will take place in megaton size water tanks then with a large surface of photo-detection. We propose to segment the large surface in arrays with a single front-end electronics and only the useful data send in surface to be stocked and analyzed. This paper describes the second version of the ASIC and illustrates the chip principle of operation and the main characteristics thank to a series of measurements. It is a 16-channel ASIC with channels that work independently, in triggerless mode and all managed by a common digital part. Then main innovation is that all the channels are handled independently by the digital part so that only channels that have triggered are digitized. Then the data are transferred to the internal memory and sent out in a data driven way. The ASIC allows charge and time measurement. We measured a charge measurement range starting from 160 fC (1 photoelectron-p.e., at PMT gain of 106) to 100 pC (around 600 p.e.) at 1% of linearity; time tagging at 1 ns thanks to a 24-bit counter at 10 MHz and a Time to Digital Converter (TDC) on a 100 ns ramp.

  14. A 64ch readout module for PPD/MPPC/SiPM using EASIROC ASIC

    Energy Technology Data Exchange (ETDEWEB)

    Nakamura, Isamu, E-mail: isamu.nakamura@kek.jp [KEK, 1-1 Oho Tsukuba 305-0801 (Japan); Ishijima, N.; Hanagaki, K. [Osaka University, 1-1 Machikaneyama, Toyonaka, Osaka 560-0043 (Japan); Yoshimura, K. [Okayama University, 1-1 Tsushimanaka, Kita-ku, Okayama 700-8530 (Japan); Nakai, Y. [Kyushu University, 6-10-1 Hakozaki, Higashi-ku, Fukuoka 812-8581 (Japan); Ueno, K. [KEK, 1-1 Oho Tsukuba 305-0801 (Japan)

    2015-07-01

    A readout module for PPD/MPPC/GAPD/SiPM is developed using EASIROC ASIC. The module can handle 64 PPDs and has on-board bias power supply, ADC for energy measurement, 1 ns TDC on FPGA as well as 64ch Logic output for external trigger. Controls and data transfer are through SiTCP technology implemented in FPGA. The module has NIM format for convenience, but can be operated without crate with 5 V AC/DC converter. Basic performance of production module was tested and the results are presented in the poster.

  15. A front-end ASIC for ionising radiation monitoring with femto-amp capabilities

    International Nuclear Information System (INIS)

    Voulgari, E.; Noy, M.; Anghinolfi, F.; Perrin, D.; Krummenacher, F.; Kayal, M.

    2016-01-01

    An ultra-low leakage current Application Specific Integrated Circuit (ASIC) called Utopia (Ultralow Picoammeter) has been designed and fabricated in AMS 0.35 μm CMOS, in order to be used as the front-end for ionising radiation monitoring at CERN. It is based on the topology of a Current to Frequency Converter (CFC) through charge balancing and demonstrates a wide dynamic range of 8.5 decades without range changing. Due to a design aimed at minimising input leakage currents, input currents as low as 01 fA can be measured

  16. ASIC design used in high energy physics experiments

    International Nuclear Information System (INIS)

    Zhang Hongyu; Lin Tao; Wu Ling; Zhao jingwei; Gu Shudi

    1997-01-01

    The author introduces an ASIC (Application Specific Integrated Circuit) design environment based on PC. Some design tools used in such environment are also introduced. A kind of ASIC chip used in high energy physics experiment, weighting mean timer, is being developed now

  17. Introduction to the Highlights of the 26th ASIC Conference.

    Science.gov (United States)

    Nehlig, Astrid

    2017-09-10

    The 26th ASIC Conference that was held in 2016 in Kunming, China has been marking the 50th anniversary of the creation of ASIC. The meeting in China was well attended by over 400 participants from all over the world and allowed fruitful exchanges among participants from all horizons of coffee science.

  18. Smart Sensor ASIC for Nuclear Power Monitoring

    International Nuclear Information System (INIS)

    Kerwin, David B.; Merkel, Kenneth G.; Rouxel, Olivier

    2013-06-01

    Mixed-signal integrated circuits are used in a variety of applications where ionizing radiation is present, including satellites, space vehicles, nuclear reactor monitoring, medical imaging, and cancer therapy. While total ionizing radiation is present in each of these environments, the type of radiation (e.g. heavy ions vs. high-energy x-rays) and other environmental factors present unique challenges to the mixed-signal designer. This paper discusses a Smart Sensor radiation hardened, mixed-signal, application specific integrated circuit (ASIC) specifically designed for sensor monitoring in a nuclear reactor environment. Results after exposure to gamma rays, neutrons, and temperatures up to 200 deg. C are reported. (authors)

  19. The STAR cluster-finder ASIC

    Energy Technology Data Exchange (ETDEWEB)

    Botlo, M.; LeVine, M.J.; Scheetz, R.A.; Schulz, M.W. [Brookhaven National Lab., Upton, NY (United States); Short, P.; Woods, J. [InnovASIC, Inc., Albuquerque, NM (United States); Crosetto, D. [Rice Univ., Houston, TX (United States). Bonner Nuclear Lab.

    1997-12-01

    STAR is a large TPC-based experiment at RHIC, the relativistic heavy ion collider at Brookhaven National Laboratory. The STAR experiment reads out a TPC and an SVT (silicon vertex tracker), both of which require in-line pedestal subtraction, compression of ADC values from 10-bit to 8-bit, and location of time sequences representing responses to charged-particle tracks. The STAR cluster finder ASIC responds to all of these needs. Pedestal subtraction and compression are performed using lookup tables in attached RAM. The authors describe its design and implementation, as well as testing methodology and results of tests performed on foundry prototypes.

  20. CASAGEM: a readout ASIC for micro pattern gas detectors

    International Nuclear Information System (INIS)

    He Li; Deng Zhi; Liu Yinong

    2012-01-01

    A readout ASIC for micro pattern gas detectors has been designed This ASIC integrates 16 channels for anode readout and 1 channel for cathode readout which can make use of the signal of detector's cathode to generate a trigger Every channel can provide amplification and shaping of detector signals. The ASIC can also provide adjustable gain which can be adjusted from 2 mV/fC to 40 mV/fC, and adjustable shaping time which can be adjusted from 20 ns to 80 ns; so this ASIC can be applied to detectors with wide range output signal and different counting rate. The ASIC is fabricated with Chartered 0.35 μm CMOS process More circuit design Details and test results will be presented. (authors)

  1. Readout ASIC of pair-monitor for international linear collider

    International Nuclear Information System (INIS)

    Sato, Yutaro; Ikeda, Hirokazu; Ito, Kazutoshi; Miyamoto, Akiya; Nagamine, Tadashi; Sasaki, Rei; Takubo, Yosuke; Tauchi, Toshiaki; Yamamoto, Hitoshi

    2010-01-01

    The pair-monitor is a beam profile monitor at the interaction point of the international linear collider. A prototype of the readout ASIC for the pair-monitor has been designed and tested. Since the pair-monitor uses the hit distribution of electrons and positrons generated by the beam-crossing to measure the beam profile, the readout ASIC is designed to count the number of hits. In a prototype ASIC, 36 readout cells were implemented by TSMC 0.25-μm CMOS process. Each readout cell is equipped with an amplifier, comparator, 8-bit counter and 16 count-registers. By the operation test, all the ASIC component were confirmed to work correctly. As the next step, we develop the prototype ASIC with the silicon on insulator technology. It is produced with OKI 0.2-μm FD-SOI CMOS process.

  2. Small Microprocessor for ASIC or FPGA Implementation

    Science.gov (United States)

    Kleyner, Igor; Katz, Richard; Blair-Smith, Hugh

    2011-01-01

    A small microprocessor, suitable for use in applications in which high reliability is required, was designed to be implemented in either an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA). The design is based on commercial microprocessor architecture, making it possible to use available software development tools and thereby to implement the microprocessor at relatively low cost. The design features enhancements, including trapping during execution of illegal instructions. The internal structure of the design yields relatively high performance, with a significant decrease, relative to other microprocessors that perform the same functions, in the number of microcycles needed to execute macroinstructions. The problem meant to be solved in designing this microprocessor was to provide a modest level of computational capability in a general-purpose processor while adding as little as possible to the power demand, size, and weight of a system into which the microprocessor would be incorporated. As designed, this microprocessor consumes very little power and occupies only a small portion of a typical modern ASIC or FPGA. The microprocessor operates at a rate of about 4 million instructions per second with clock frequency of 20 MHz.

  3. Status Report on the LOC ASIC

    CERN Document Server

    Ye, J

    2008-01-01

    Based on a commercially available 0.25 μm Silicon on Sapphire CMOS technology, we are developing the LOC ASIC for high speed serial data transmission in the front-end electronics systems of the ATLAS upgrade for the SLHC1. Evaluation of this technology for applications in the SLHC, based on a dedicated test chip, has been performed with irradiation tests in gamma (Co-60) and in 230 MeV proton beams. Test results indicate that this may be a candidate technology of ASIC developments for the SLHC. More thorough evaluation tests will be carried out under another R&D program supported through the Advanced Detector Research (ADR) from the Department of Energy. Characterization tests on the first prototype serializer, LOC1, have been carried out in lab. Based on the lessons learned from this chip, we propose a new architecture design of the second prototype, LOC2, aiming for a serial data rate in the range of 5 Gbps. Simulation on key components of LOC2 are being carried out and the results we have so far are p...

  4. VMM3, an ASIC for Micropattern Detectors

    CERN Document Server

    Iakovidis, Georgios; The ATLAS collaboration

    2018-01-01

    The VMM is a custom Application Specific Integrated Circuit (ASIC). It will be used in the front- end readout electronics of both the Micromegas and sTGC detectors of the New Small Wheel upgrade of the ATLAS experiment at CERN. It is being developed at Brookhaven National Laboratory and fabricated in the 130nm Global Foundries 8RF-DM process (former IBM 8RF- DM). The 64 channels ASIC has highly configurable parameters and is able to handle signals of opposite polarities and a high range of capacitances while being low noise and low on power consumption. The VMM has four independent data output paths. First is the “precision” (10-bit) amplitude and (effective) 20-bit time stamp read out continuously (250 ns dead-time per channel) or at when a trigger occurs. Second, a serial output called Address in Real Time (ART). This is the address of the channel which had a signal above threshold within the bunch crossing clock. Third, the parallel prompt outputs from all 64 channels in a variety of selectable formats...

  5. Indigenous design and development of digital ASICs

    International Nuclear Information System (INIS)

    Misra, M.K.; Kishore, G.V.; Sridhar, N.; Palanisami, K.; Thirugnana Murthy, D.

    2013-01-01

    FPGAs and CPLDs were extensively used for the design and development of Instrumentation and Control systems including safety systems of Prototype Fast Breeder Reactor (PFBR). The developed I and C systems have been tested extensively for their functionality and also undergone various qualification tests. Some of these I and C systems have also been deployed in Fast Breeder Test Reactor. The performance of these designs is found to be satisfactory. However FPGAs/CPLDs are rapidly evolving and the devices become obsolete in a short span of time (typically about 5 to 8 years), whereas reactor's life time is typically about 40 years. This obsolescence problem can be handled in different ways. This paper discusses design and fabrication of digital ASICs as one of the alternate for handling obsolescence problems. Aim of this development work is to establish complete digital ASIC design, fabrication and testing flow, so that the same can be used in some of the critical/strategic requirements. (author)

  6. Hsc70 regulates cell surface ASIC2 expression and vascular smooth muscle cell migration.

    Science.gov (United States)

    Grifoni, Samira C; McKey, Susan E; Drummond, Heather A

    2008-05-01

    Recent studies suggest members of the degenerin (DEG)/epithelial Na(+) channel (ENaC)/acid-sensing ion channel (ASIC) protein family play an important role in vascular smooth muscle cell (VSMC) migration. In a previous investigation, we found suppression of a certain DEG/ENaC/ASIC member, ASIC2, increased VSMC chemotactic migration, raising the possibility that ASIC2 may play an inhibitory role. Because ASIC2 protein was retained in the cytoplasm, we reasoned increasing surface expression of ASIC2 might unmask the inhibitory role of ASIC2 in VSMC migration so we could test the hypothesis that ASIC2 inhibits VSMC migration. Therefore, we used the chemical chaperone glycerol to enhance ASIC2 expression. Glycerol 1) increased cytoplasm ASIC2 expression, 2) permitted detection of ASIC2 at the cell surface, and 3) inhibited platelet-derived growth factor (PDGF)-bb mediated VSMC migration. Furthermore, ASIC2 silencing completely abolished the inhibitory effect of glycerol on migration, suggesting upregulation of ASIC2 is responsible for glycerol-induced inhibition of VSMC migration. Because other investigators have shown that glycerol regulates ENaC/ASIC via interactions with a certain heat shock protein, heat shock protein 70 (Hsc70), we wanted to determine the importance of Hsc70 on ASIC2 expression in VSMCs. We found that Hsc70 silencing increases ASIC2 cell surface expression and inhibits VSMC migration, which is abolished by cosilencing ASIC2. These data demonstrate that Hsc70 inhibits ASIC2 expression, and, when the inhibitory effect of Hsc70 is removed, ASIC2 expression increases, resulting in reduced VSMC migration. Because VSMC migration contributes to vasculogenesis and remodeling following vascular injury, our findings raise the possibility that ASIC2-Hsc70 interactions may play a role in these processes.

  7. A Stimulator ASIC Featuring Versatile Management for Vestibular Prostheses.

    Science.gov (United States)

    Dai Jiang; Demosthenous, Andreas; Perkins, Timothy; Xiao Liu; Donaldson, Nick

    2011-04-01

    This paper presents a multichannel stimulator ASIC for an implantable vestibular prosthesis. The system features versatile stimulation management which allows fine setting of the parameters for biphasic stimulation pulses. To address the problem of charge imbalance due to rounding errors, the digital processor can calculate and provide accurate charge correction. A technique to reduce the data rate to the stimulator is described. The stimulator ASIC was implemented in 0.6-μ m high-voltage CMOS technology occupying an area of 2.27 mm(2). The measured performance of the ASIC has been verified using vestibular electrodes in saline.

  8. Two aspects of ASIC function: Synaptic plasticity and neuronal injury.

    Science.gov (United States)

    Huang, Yan; Jiang, Nan; Li, Jun; Ji, Yong-Hua; Xiong, Zhi-Gang; Zha, Xiang-ming

    2015-07-01

    Extracellular brain pH fluctuates in both physiological and disease conditions. The main postsynaptic proton receptor is the acid-sensing ion channels (ASICs). During the past decade, much progress has been made on protons, ASICs, and neurological disease. This review summarizes the recent progress on synaptic role of protons and our current understanding of how ASICs contribute to various types of neuronal injury in the brain. This article is part of the Special Issue entitled 'Acid-Sensing Ion Channels in the Nervous System'. Copyright © 2015 Elsevier Ltd. All rights reserved.

  9. CODA : Compact front-end analog ASIC for silicon detectors

    International Nuclear Information System (INIS)

    Chandratre, V.B.; Sardesai, S.V.; Kataria, S.K.

    2004-01-01

    The paper presents the design of a front-end signal processing ASIC to be used with Silicon detectors having full depletion capacitance up to 40 pf. The ASIC channel consists of a charge amplifier, a shaper amplifier (CR-RC 3 ) and a comparator. There is provision for changing gain and polarity. The circuit has an estimated power dissipation of 16 mw. The ASIC is fabricated in 1.2 um CMOS technology. The 0pf noise is ∼400e. The chip has an area of 3 by 4 mm is packaged in 48 pin CLCC and COB option (Chip on Board). (author)

  10. A 2D 4×4 Channel Readout ASIC for Pixelated CdTe Detectors for Medical Imaging Applications.

    Science.gov (United States)

    Macias-Montero, Jose-Gabriel; Sarraj, Maher; Chmeissani, Mokhtar; Martínez, Ricardo; Puigdengoles, Carles

    2015-10-01

    We present a 16-channel readout integrated circuit (ROIC) with nanosecond-resolution time to digital converter (TDC) for pixelated Cadmium Telluride (CdTe) gamma-ray detectors. The 4 × 4 pixel array ROIC is the proof of concept of the 10 × 10 pixel array readout ASIC for positron-emission tomography (PET) scanner, positron-emission mammography (PEM) scanner, and Compton gamma camera. The electronics of each individual pixel integrates an analog front-end with switchable gain, an analog to digital converter (ADC), configuration registers, and a 4-state digital controller. For every detected photon, the pixel electronics provides the energy deposited in the detector with 10-bit resolution, and a fast trigger signal for time stamp. The ASIC contains the 16-pixel matrix electronics, a digital controller, five global voltage references, a TDC, a temperature sensor, and a band-gap based current reference. The ASIC has been fabricated with TSMC 0.25 μ m mixed-signal CMOS technology and occupies an area of 5.3 mm × 6.8 mm. The TDC shows a resolution of 95.5 ps, a precision of 600 ps at full width half maximum (FWHM), and a power consumption of 130 μ W. In acquisition mode, the total power consumption of every pixel is 200 μ W. An equivalent noise charge (ENC) of 160 e - RMS at maximum gain and negative polarity conditions has been measured at room temperature.

  11. Acid-sensing ion channels (ASICs) in the taste buds of adult zebrafish.

    Science.gov (United States)

    Viña, E; Parisi, V; Cabo, R; Laurà, R; López-Velasco, S; López-Muñiz, A; García-Suárez, O; Germanà, A; Vega, J A

    2013-03-01

    In detecting chemical properties of food, different molecules and ion channels are involved including members of the acid-sensing ion channels (ASICs) family. Consistently ASICs are present in sensory cells of taste buds of mammals. In the present study the presence of ASICs (ASIC1, ASIC2, ASIC3 and ASIC4) was investigated in the taste buds of adult zebrafish (zASICs) using Western blot and immunohistochemistry. zASIC1 and zASIC3 were regularly absent from taste buds, whereas faint zASIC2 and robust zASIC4 immunoreactivities were detected in sensory cells. Moreover, zASIC2 also immunolabelled nerves supplying taste buds. The present results demonstrate for the first time the presence of zASICs in taste buds of teleosts, with different patterns to that occurring in mammals, probably due to the function of taste buds in aquatic environment and feeding. Nevertheless, the role of zASICs in taste remains to be demonstrated. Copyright © 2013 Elsevier Ireland Ltd. All rights reserved.

  12. READ - Remote Analog ASIC Design System

    Directory of Open Access Journals (Sweden)

    Michael E. Auer

    2006-11-01

    Full Text Available The scope of this work is to present a solution to implement a remote electronic laboratory for testing and designing analog ASICs (ispPAC10. The application allows users to create circuit schematics, upload the design to the device and perform measurements. The software used for designing circuits is the PAC-Designer and it runs on a Citrix server. The signals are generated and the responses are acquired by a data acquisition board controlled by LabView. The virtual instruments interact with some ActiveX controls specially designed to look like real oscilloscope and function generator devices and represent the user interface of the lab. These ActiveX give users the control over the LabView VIs and the access to its facilities in order to perform electronic exercises.

  13. Synthesis algorithm of VLSI multipliers for ASIC

    Science.gov (United States)

    Chua, O. H.; Eldin, A. G.

    1993-01-01

    Multipliers are critical sub-blocks in ASIC design, especially for digital signal processing and communications applications. A flexible multiplier synthesis tool is developed which is capable of generating multiplier blocks for word size in the range of 4 to 256 bits. A comparison of existing multiplier algorithms is made in terms of speed, silicon area, and suitability for automated synthesis and verification of its VLSI implementation. The algorithm divides the range of supported word sizes into sub-ranges and provides each sub-range with a specific multiplier architecture for optimal speed and area. The algorithm of the synthesis tool and the multiplier architectures are presented. Circuit implementation and the automated synthesis methodology are discussed.

  14. A 32-channels, 025 mu m CMOS ASIC for the readout of the Silicon Drift Detectors of the ALICE experiment

    CERN Document Server

    Mazza, G; Anelli, G; Anghinolfi, F; Martínez, M I; Rotondo, F

    2004-01-01

    In this paper we present a 32 channel ASIC prototype for the readout of the Silicon Drift Detectors (SDDs) of the ALICE experiment. The ASIC integrates on the same chip 32 transimpedance amplifiers, a 32*256 cells analogue memory and 16 successive approximation 10 bit A /D converters. The circuit amplifies and samples at 40 MS/s the input signal in a continuous way; when an external trigger signal validates the acquisition, the sampling is stopped and the data are digitized at lower speed (0.5 MS/s). The chip has been designed and fabricated in a commercial. 0.25 mu m CMOS technology. It has been extensively tested both on a bench and connected with the detector in several beam tests. In this paper both design issues and test results are presented. The commercial technology used for the design has been yield radiation tolerant with special layout techniques. Total dose irradiation tests are also presented. (13 refs).

  15. A 32-channel, 025 mum CMOS ASIC for the readout of the silicon drift detectors of the ALICE experiment

    CERN Document Server

    Mazza, G; Anghinolfi, F; Martínez, M I; Rivetti, A; Rotondo, F

    2004-01-01

    In this paper we present a 32 channel ASIC prototype for the readout of the silicon drift detectors (SDDs) of the ALICE experiment. The ASIC integrates on the same substrate 32 transimpedance amplifiers, a 32 x 256 cell analogue memory and 16 successive approximation 10 bit A/D converters. The circuit amplifies and samples at 40 MS/s the input signal in a continuous way. When an external trigger signal validates the acquisition, the sampling is stopped and the data are digitized at lower speed (0.5 MS/s). The chip has been designed and fabricated in a commercial 0.25 mum CMOS technology. It has been extensively tested both on a bench and connected with a detector in several beam tests. In this paper both design issues and test results are presented. The radiation tolerance of the design has been increased by special layout techniques. Total dose irradiation tests are also presented.

  16. A Radiation Hardened Housekeeping Slave Node (RH-HKSN) ASIC

    Data.gov (United States)

    National Aeronautics and Space Administration — This projects seeks to continue the development of the Radiation Hardened Housekeeping Slave Node (RH-HKSN) ASIC. The effort has taken parallel paths by implementing...

  17. The 'KATOD-1' strip readout ASIC for cathode strip chamber

    International Nuclear Information System (INIS)

    Golutvin, I.A.; Gorbunov, N.V.; Karzhavin, V.Yu.; Khabarov, V.S.; Movchan, S.A.; Smolin, D.A.; Dvornikov, O.V.; Shumejko, N.M.; Chekhovskij, V.A.

    2001-01-01

    The 'KATOD-1', a 16-channels readout ASIC, has been designed to perform tests of P3 and P4 full-scale prototypes of the cathode strip chamber for the ME1/1 forward muon station of the Compact Muon Solenoid (CMS) experiment. The ASIC channel consists of two charge-sensitive preamplifiers, a three-stage shaper with cancellation, and an output driver. The ASIC is instrumented with control of gain, in the range of (-4.2 : +5.0) mV/fC, and control of output pulse-shape. The equivalent input noise is equal to 2400 e with the slope of 12 e/pF for detector capacity up to 200 pF. The peaking time is 100 ns for the chamber signal. The ASIC has been produced by a microwave Bi-jFET technology

  18. Driver ASICs for Advanced Deformable Mirrors, Phase II

    Data.gov (United States)

    National Aeronautics and Space Administration — The overall goal of the SBIR program is to develop a new Application Specified Integrated Circuit (ASIC) driver to be used in driver electronics of a deformable...

  19. Extreme Temperature, Rad-Hard Power Management ASIC, Phase I

    Data.gov (United States)

    National Aeronautics and Space Administration — Ridgetop Group will design a rad-hard Application Specific Integrated Circuit (ASIC) for spacecraft power management that is functional over a temperature range of...

  20. The "KATOD-1" Strip Readout ASIC for Cathode Strip Chamber

    CERN Document Server

    Golutvin, I A; Karjavin, V Yu; Khabarov, V S; Movchan, S A; Smolin, D A; Dvornikov, O V; Shumeiko, N M; Tchekhovski, V A

    2001-01-01

    The "KATOD-1", a 16-channels readout ASIC, has been designed to perform tests of P3 and P4 full-scale prototypes of the cathode strip chamber for the ME1/1 forward muon station of the Compact Muon Solenoid (CMS) experiment. The ASIC channel consists of two charge-sensitive preamplifiers, a three-stage shaper with tail cancellation, and an output driver. The ASIC is instrumented with control of gain, in the range of (-4.2\\div +5.0) mV/fC, and control of output pulse-shape. The equivalent input noise is equal to 2400 e with the slope of 12 e/pF for detector capacity up to 200 pF. The peaking time is 100 ns for the chamber signal. The ASIC has been produced by a microwave Bi-jFET technology.

  1. Readout ASIC for ILC-FPCCD vertex detector

    International Nuclear Information System (INIS)

    Takubo, Yosuke; Miyamoto, Akiya; Ikeda, Hirokazu; Yamamoto, Hitoshi; Itagaki, Kennosuke; Nagamine, Tadashi; Sugimoto, Yasuhiro

    2010-01-01

    The concept of FPCCD (Fine Pixel CCD) whose pixel size is 5x5μm 2 has been proposed as vertex detector at ILC. Since FPCCD has 128 x20,000 pixels in one readout channel, its readout poses a considerable challenge. We have developed a prototype of readout ASIC to readout the large number of pixels during the inter-train gap of the ILC beam. In this paper, we report the design and performance of the readout ASIC.

  2. Monolithic Active Pixel Matrix with Binary Counters (MAMBO) ASIC

    International Nuclear Information System (INIS)

    Khalid, Farah F.; Deptuch, Grzegorz; Shenai, Alpana; Yarema, Raymond J.

    2010-01-01

    Monolithic Active Matrix with Binary Counters (MAMBO) is a counting ASIC designed for detecting and measuring low energy X-rays from 6-12 keV. Each pixel contains analogue functionality implemented with a charge preamplifier, CR-RC 2 shaper and a baseline restorer. It also contains a window comparator which can be trimmed by 4 bit DACs to remove systematic offsets. The hits are registered by a 12 bit ripple counter which is reconfigured as a shift register to serially output the data from the entire ASIC. Each pixel can be tested individually. Two diverse approaches have been used to prevent coupling between the detector and electronics in MAMBO III and MAMBO IV. MAMBO III is a 3D ASIC, the bottom ASIC consists of diodes which are connected to the top ASIC using μ-bump bonds. The detector is decoupled from the electronics by physically separating them on two tiers and using several metal layers as a shield. MAMBO IV is a monolithic structure which uses a nested well approach to isolate the detector from the electronics. The ASICs are being fabricated using the SOI 0.2 (micro)m OKI process, MAMBO III is 3D bonded at T-Micro and MAMBO IV nested well structure was developed in collaboration between OKI and Fermilab.

  3. Monolithic Active Pixel Matrix with Binary Counters (MAMBO) ASIC

    Energy Technology Data Exchange (ETDEWEB)

    Khalid, Farah F.; Deptuch, Grzegorz; Shenai, Alpana; Yarema, Raymond J.; /Fermilab

    2010-11-01

    Monolithic Active Matrix with Binary Counters (MAMBO) is a counting ASIC designed for detecting and measuring low energy X-rays from 6-12 keV. Each pixel contains analogue functionality implemented with a charge preamplifier, CR-RC{sup 2} shaper and a baseline restorer. It also contains a window comparator which can be trimmed by 4 bit DACs to remove systematic offsets. The hits are registered by a 12 bit ripple counter which is reconfigured as a shift register to serially output the data from the entire ASIC. Each pixel can be tested individually. Two diverse approaches have been used to prevent coupling between the detector and electronics in MAMBO III and MAMBO IV. MAMBO III is a 3D ASIC, the bottom ASIC consists of diodes which are connected to the top ASIC using {mu}-bump bonds. The detector is decoupled from the electronics by physically separating them on two tiers and using several metal layers as a shield. MAMBO IV is a monolithic structure which uses a nested well approach to isolate the detector from the electronics. The ASICs are being fabricated using the SOI 0.2 {micro}m OKI process, MAMBO III is 3D bonded at T-Micro and MAMBO IV nested well structure was developed in collaboration between OKI and Fermilab.

  4. Charged Particle Tracking with the Timepix ASIC

    CERN Document Server

    Akiba, Kazuyoshi; Collins, P; Crossley, M; Dumps, R; Gersabeck, M; Gligorov, Vladimir V; Llopart, X; Nicol, M; Poikela, T; Cabruja, Enric; Fleta, C; Lozano, M; Pellegrini, G; Bates, R; Eklund, L; Hynds, D; Ferre Llin, L; Maneuski, D; Parkes, C; Plackett, R; Rodrigues, E; Stewart, G; Akiba, K; van Beuzekom, M; Heijne, V; Heijne, E H M; Gordon, H; John, M; Gandelman, M; Esperante, D; Gallas, A; Vazquez Regueiro, P; Bayer, F; Michel, T; Needham, M; Artuso, M; Badman, R; Borgia, A; Garofoli, J; Wang, J; Xing, Z; Buytaert, Jan; Leflat, Alexander

    2012-01-01

    A prototype particle tracking telescope has been constructed using Timepix and Medipix ASIC hybrid pixel assemblies as the six sensing planes. Each telescope plane consisted of one 1.4 cm2 assembly, providing a 256x256 array of 55 micron square pixels. The telescope achieved a pointing resolution of 2.3 micron at the position of the device under test. During a beam test in 2009 the telescope was used to evaluate in detail the performance of two Timepix hybrid pixel assemblies; a standard planar 300 micron thick sensor, and 285 micron thick double sided 3D sensor. This paper describes a detailed charge calibration study of the pixel devices, which allows the true charge to be extracted, and reports on measurements of the charge collection characteristics and Landau distributions. The planar sensor achieved a best resolution of 4.0 micron for angled tracks, and resolutions of between 4.4 and 11 micron for perpendicular tracks, depending on the applied bias voltage. The double sided 3D sensor, which has signific...

  5. ASIC-like, proton-activated currents in rat hippocampal neurons.

    Science.gov (United States)

    Baron, Anne; Waldmann, Rainer; Lazdunski, Michel

    2002-03-01

    The expression of mRNA for acid sensing ion channels (ASIC) subunits ASIC1a, ASIC2a and ASIC2b has been reported in hippocampal neurons, but the presence of functional hippocampal ASIC channels was never assessed. We report here the first characterization of ASIC-like currents in rat hippocampal neurons in primary culture. An extracellular pH drop induces a transient Na(+) current followed by a sustained non-selective cation current. This current is highly sensitive to pH with an activation threshold around pH 6.9 and a pH(0.5) of 6.2. About half of the total peak current is inhibited by the spider toxin PcTX1, which is specific for homomeric ASIC1a channels. The remaining PcTX1-resistant ASIC-like current is increased by 300 microM Zn(2+) and, whereas not fully activated at pH 5, it shows a pH(0.5) of 6.0 between pH 7.4 and 5. We have previously shown that Zn(2+) is a co-activator of ASIC2a-containing channels. Thus, the hippocampal transient ASIC-like current appears to be generated by a mixture of homomeric ASIC1a channels and ASIC2a-containing channels, probably heteromeric ASIC1a+2a channels. The sustained non-selective current suggests the involvement of ASIC2b-containing heteromeric channels. Activation of the hippocampal ASIC-like current by a pH drop to 6.9 or 6.6 induces a transient depolarization which itself triggers an initial action potential (AP) followed by a sustained depolarization and trains of APs. Zn(2+) increases the acid sensitivity of ASIC channels, and consequently neuronal excitability. It is probably an important co-activator of ASIC channels in the central nervous system.

  6. A 32-channel front-end ASIC for GEM detectors used in beam monitoring applications

    Science.gov (United States)

    Ciciriello, F.; Altieri, P. R.; Corsi, F.; De Robertis, G.; Felici, G.; Loddo, F.; Lorusso, L.; Marzocca, C.; Matarrese, G.; Ranieri, A.; Stamerra, A.

    2017-11-01

    A multichannel, mixed-signal, front-end ASIC for GEM detectors, intended for beam monitoring in hadron therapy applications, has been designed and prototyped in a standard 0.35 μm CMOS technology. The analog channels are based on the classic CSA + shaper processing chain, followed by a peak detector which can work as an analog memory, to simplifiy the analog-to-digital conversion of the peak voltage of the output pulse, proportional to the energy of the detected event. The available hardware resources include an 8-bit A/D converter and a standard-cell digital part, which manages the read-out procedure, in sparse or serial mode. The ASIC is self-triggered and transfers energy and address data to the external DAQ via a fast 100 MHz LVDS link. Preliminary characterization results show that the non-linearity error is limited to 5% for a maximum input charge of about 70 fC, the measured ENC is about 1400e- and the time jitter of the trigger signal generated in response to an injected charge of 60 fC is close to 200 ps.

  7. Design and prototyping of a readout aggregation ASIC

    Energy Technology Data Exchange (ETDEWEB)

    Lemke, Frank; Schatral, Sven; Bruening, Ulrich [ZITI, Universitaet Heidelberg (Germany); Som, Indranil; Bhattacharyya, Tarun [Indian Institute of Technology, Kharagpur (India); Collaboration: CBM-Collaboration

    2015-07-01

    In close collaboration between the Indian Institute of Technology Kharagpur (IITKGP) and the Institute for Computer Engineering (ZITI) at the University of Heidelberg a readout aggregation ASIC was designed. This happened in the context of the Compressed Baryonic Matter (CBM) experiment at the Facility for Antiproton and Ion Research (FAIR). The ASIC is designed in 65nm TSMC technology. Its miniASIC tapeout to verify the analog and high-speed components is scheduled to the first quarter of 2015. This mixed-signal ASIC consists of a full-custom 5Gb/s serializer/deserializer, designed by the IITKGP including design elements such as phase-locked loop, bandgap reference, and clock data recovery, and a digital designed network communication and aggregation part designed by the ZITI. In addition, there are test structures and an I2C readout integrated to ease bring up and monitoring. A specialty of this test ASIC is the aggregation of links featuring different data rates, running with bundles of 500 MB/s LVDS. This enables flexible readout setups of mixed detectors respectively readout of various chips. As communication protocol, a unified link protocol is used including control messages, data messages, and synchronization messages on an identical lane. The design has been simulated, verified, and hardware emulated using Spartan 6 FPGAs.

  8. DST9-1, an ASIC for receiving and delivery of time signals

    International Nuclear Information System (INIS)

    Cuzon, J.C.

    1999-01-01

    In order to evaluate the 1.2 μ BiCMOS technology of AMS foundry the electronics department developed a full custom ASIC for time signal receiving and shaping according to our fast TDC pre-diffused ASIC. (author)

  9. A Low Power Application-Specific Integrated Circuit (ASIC) Implementation of Wavelet Transform/Inverse Transform

    National Research Council Canada - National Science Library

    Harvala, Daniel

    2001-01-01

    .... The ASIC is based on an existing four-chip FPGA implementation. Implementing the design using a dedicated ASIC enhances the speed, decreases chip count to a single die, and uses significantly less power compared to the FPGA implementation...

  10. Decimal multiplication using compressor based-BCD to binary converter

    Directory of Open Access Journals (Sweden)

    Sasidhar Mukkamala

    2018-02-01

    Full Text Available The objective of this work is to implement a scalable decimal to binary converter from 8 to 64 bits (i.e 2-digit to 16-digit using parallel architecture. The proposed converters, along with binary coded decimal (BCD adder and binary to BCD converters, are used in parallel implementation of Urdhva Triyakbhyam (UT-based 32-bit BCD multiplier. To increase the performance, compressor circuits were used in converters and multiplier. The designed hardware circuits were verified by behavioural and post layout simulations. The implementation was carried out using Virtex-6 Field Programmable Gate Array (FPGA and Application Specific Integrated Circuit (ASIC with 90-nm technology library platforms. The results on FPGA shows that compressor based converters and multipliers produced less amount of propagation delay with a slight increase of hardware resources. In case of ASIC implementation, a compressor based converter delay is equivalent to conventional converter with a slight increase of gate count. However, the reduction of delay is evident in case of compressor based multiplier.

  11. ASIC1A in neurons is critical for fear-related behaviors.

    Science.gov (United States)

    Taugher, R J; Lu, Y; Fan, R; Ghobbeh, A; Kreple, C J; Faraci, F M; Wemmie, J A

    2017-11-01

    Acid-sensing ion channels (ASICs) have been implicated in fear-, addiction- and depression-related behaviors in mice. While these effects have been attributed to ASIC1A in neurons, it has been reported that ASICs may also function in nonneuronal cells. To determine if ASIC1A in neurons is indeed required, we generated neuron-specific knockout (KO) mice with floxed Asic1a alleles disrupted by Cre recombinase driven by the neuron-specific synapsin I promoter (SynAsic1a KO mice). We confirmed that Cre expression occurred in neurons, but not all neurons, and not in nonneuronal cells including astrocytes. Consequent loss of ASIC1A in some but not all neurons was verified by western blotting, immunohistochemistry and electrophysiology. We found ASIC1A was disrupted in fear circuit neurons, and SynAsic1a KO mice exhibited prominent deficits in multiple fear-related behaviors including Pavlovian fear conditioning to cue and context, predator odor-evoked freezing and freezing responses to carbon dioxide inhalation. In contrast, in the nucleus accumbens ASIC1A expression was relatively normal in SynAsic1a KO mice, and consistent with this observation, cocaine conditioned place preference (CPP) was normal. Interestingly, depression-related behavior in the forced swim test, which has been previously linked to ASIC1A in the amygdala, was also normal. Together, these data suggest neurons are an important site of ASIC1A action in fear-related behaviors, whereas other behaviors likely depend on ASIC1A in other neurons or cell types not targeted in SynAsic1a KO mice. These findings highlight the need for further work to discern the roles of ASICs in specific cell types and brain sites. © 2017 John Wiley & Sons Ltd and International Behavioural and Neural Genetics Society.

  12. Acid-sensing ion channel (ASIC) 1a/2a heteromers have a flexible 2:1/1:2 stoichiometry.

    Science.gov (United States)

    Bartoi, Tudor; Augustinowski, Katrin; Polleichtner, Georg; Gründer, Stefan; Ulbrich, Maximilian H

    2014-06-03

    Acid-sensing ion channels (ASICs) are widely expressed proton-gated Na(+) channels playing a role in tissue acidosis and pain. A trimeric composition of ASICs has been suggested by crystallization. Upon coexpression of ASIC1a and ASIC2a in Xenopus oocytes, we observed the formation of heteromers and their coexistence with homomers by electrophysiology, but could not determine whether heteromeric complexes have a fixed subunit stoichiometry or whether certain stoichiometries are preferred over others. We therefore imaged ASICs labeled with green and red fluorescent proteins on a single-molecule level, counted bleaching steps from GFP and colocalized them with red tandem tetrameric mCherry for many individual complexes. Combinatorial analysis suggests a model of random mixing of ASIC1a and ASIC2a subunits to yield both 2:1 and 1:2 ASIC1a:ASIC2a heteromers together with ASIC1a and ASIC2a homomers.

  13. Generic testability and test methods guidelines for ASIC devices

    International Nuclear Information System (INIS)

    Puri, K.; Takeda, H.

    1996-04-01

    Many industries are switching from analog equipment to digital equipment. This change has become desirable because digital devices have become cost-effective, easily available, highly reliable, easy to qualify and easy to test and replace when needed. The nuclear power industry is beginning to upgrade some of its instrumentation and control equipment from an analog design to digital design. A digital application specific integrated circuit (ASIC) device can be designed to perform the same functions as performed by analog modules. However, the ASIC must be designed for cost-effective testability and qualification. This report provides generic guidelines for designing cost-effective methods for testing and characterizing ASIC devices to accomplish qualification

  14. Advanced type 1 diabetes is associated with ASIC alterations in mouse lower thoracic dorsal root ganglia neurons.

    Science.gov (United States)

    Radu, Beatrice Mihaela; Dumitrescu, Diana Ionela; Marin, Adela; Banciu, Daniel Dumitru; Iancu, Adina Daniela; Selescu, Tudor; Radu, Mihai

    2014-01-01

    Acid-sensing ion channels (ASICs) from dorsal root ganglia (DRG) neurons are proton sensors during ischemia and inflammation. Little is known about their role in type 1 diabetes (T1D). Our study was focused on ASICs alterations determined by advanced T1D status. Primary neuronal cultures were obtained from lower (T9-T12) thoracic DRG neurons from Balb/c and TCR-HA(+/-)/Ins-HA(+/-) diabetic male mice (16 weeks of age). Patch-clamp recordings indicate a change in the number of small DRG neurons presenting different ASIC-type currents. Multiple molecular sites of ASICs are distinctly affected in T1D, probably due to particular steric constraints for glycans accessibility to the active site: (i) ASIC1 current inactivates faster, while ASIC2 is slower; (ii) PcTx1 partly reverts diabetes effects against ASIC1- and ASIC2-inactivations; (iii) APETx2 maintains unaltered potency against ASIC3 current amplitude, but slows ASIC3 inactivation. Immunofluorescence indicates opposite regulation of different ASIC transcripts while qRT-PCR shows that ASIC mRNA ranking (ASIC2 > ASIC1 > ASIC3) remains unaltered. In conclusion, our study has identified biochemical and biophysical ASIC changes in lower thoracic DRG neurons due to advanced T1D. As hypoalgesia is present in advanced T1D, ASICs alterations might be the cause or the consequence of diabetic insensate neuropathy.

  15. Distinct ASIC currents are expressed in rat putative nociceptors and are modulated by nerve injury.

    Science.gov (United States)

    Poirot, Olivier; Berta, Temugin; Decosterd, Isabelle; Kellenberger, Stephan

    2006-10-01

    The H(+)-gated acid-sensing ion channels (ASICs) are expressed in dorsal root ganglion (DRG) neurones. Studies with ASIC knockout mice indicated either a pro-nociceptive or a modulatory role of ASICs in pain sensation. We have investigated in freshly isolated rat DRG neurones whether neurones with different ASIC current properties exist, which may explain distinct cellular roles, and we have investigated ASIC regulation in an experimental model of neuropathic pain. Small-diameter DRG neurones expressed three different ASIC current types which were all preferentially expressed in putative nociceptors. Type 1 currents were mediated by ASIC1a homomultimers and characterized by steep pH dependence of current activation in the pH range 6.8-6.0. Type 3 currents were activated in a similar pH range as type 1, while type 2 currents were activated at pH ASIC current density. Nerve injury induced differential regulation of ASIC subunit expression and selective changes in ASIC function in DRG neurones, suggesting a complex reorganization of ASICs during the development of neuropathic pain. In summary, we describe a basis for distinct cellular functions of different ASIC types in small-diameter DRG neurones.

  16. First results of the front-end ASIC for the strip detector of the PANDA MVD

    Science.gov (United States)

    Quagli, T.; Brinkmann, K.-T.; Calvo, D.; Di Pietro, V.; Lai, A.; Riccardi, A.; Ritman, J.; Rivetti, A.; Rolo, M. D.; Stockmanns, T.; Wheadon, R.; Zambanini, A.

    2017-03-01

    PANDA is a key experiment of the future FAIR facility and the Micro Vertex Detector (MVD) is the innermost part of its tracking system. PASTA (PAnda STrip ASIC) is the readout chip for the strip part of the MVD. The chip is designed to provide high resolution timestamp and charge information with the Time over Threshold (ToT) technique. Its architecture is based on Time to Digital Converters with analog interpolators, with a time bin width of 50 ps. The chip implements Single Event Upset (SEU) protection techniques for its digital parts. A first full-size prototype with 64 channels was produced in a commercial 110 nm CMOS technology and the first characterizations of the prototype were performed.

  17. The Detector Control Unit An ASIC for the monitoring of the CMS silicon tracker

    CERN Document Server

    Magazzù, G; Moreira, P

    2004-01-01

    The Detector Control Unit (DCU) is an ASIC developed as the central building block of a monitoring system for the CMS Tracker. Leakage currents in the Silicon detectors, power supply voltages of the readout electronics and local temperatures will be monitored in order to guarantee safe operating conditions during the 10-years lifetime in the LHC environment. All these measurements can be performed by an A/D converter preceded by an analog multiplexer and properly interfaced to the central control system. The requirements in terms of radiation tolerance, low-power dissipation and integration with the rest of the system led to the design of a custom integrated circuit. Its structure and characteristics are described in this paper. (6 refs).

  18. Acid-sensing ion channel (ASIC) 4 predominantly localizes to an early endosome-related organelle upon heterologous expression.

    Science.gov (United States)

    Schwartz, Verena; Friedrich, Katharina; Polleichtner, Georg; Gründer, Stefan

    2015-12-15

    Acid-sensing ion channels (ASICs) are voltage-independent proton-gated amiloride sensitive sodium channels, belonging to the DEG/ENaC gene family. Six different ASICs have been identified (ASIC1a, ASIC1b, ASIC2a, ASIC2b, ASIC3, ASIC4) that are activated by a drop in extracellular pH, either as homo- or heteromers. An exception is ASIC4, which is not activated by protons as a homomer and which does not contribute to functional heteromeric ASICs. Insensitivity of ASIC4 to protons and its comparatively low sequence identity to other ASICs (45%) raises the question whether ASIC4 may have different functions than other ASICs. In this study, we therefore investigated the subcellular localization of ASIC4 in heterologous cell lines, which revealed a surprising accumulation of the channel in early endosome-related vacuoles. Moreover, we identified an unique amino-terminal motif as important for forward-trafficking from the ER/Golgi to the early endosome-related compartment. Collectively, our results show that heterologously expressed ASIC4 predominantly resides in an intracellular endosomal compartment.

  19. The design and development of low- and high-voltage ASICs for space-borne CCD cameras

    Science.gov (United States)

    Waltham, N.; Morrissey, Q.; Clapp, M.; Bell, S.; Jones, L.; Torbet, M.

    2017-12-01

    The CCD remains the pre-eminent visible and UV wavelength image sensor in space science, Earth and planetary remote sensing. However, the design of space-qualified CCD readout electronics is a significant challenge with requirements for low-volume, low-mass, low-power, high-reliability and tolerance to space radiation. Space-qualified components are frequently unavailable and up-screened commercial components seldom meet project or international space agency requirements. In this paper, we describe an alternative approach of designing and space-qualifying a series of low- and high-voltage mixed-signal application-specific integrated circuits (ASICs), the ongoing development of two low-voltage ASICs with successful flight heritage, and two new high-voltage designs. A challenging sub-system of any CCD camera is the video processing and digitisation electronics. We describe recent developments to improve performance and tolerance to radiation-induced single event latchup of a CCD video processing ASIC originally developed for NASA's Solar Terrestrial Relations Observatory and Solar Dynamics Observatory. We also describe a programme to develop two high-voltage ASICs to address the challenges presented with generating a CCD's bias voltages and drive clocks. A 0.35 μm, 50 V tolerant, CMOS process has been used to combine standard low-voltage 3.3 V transistors with high-voltage 50 V diffused MOSFET transistors that enable output buffers to drive CCD bias drains, gates and clock electrodes directly. We describe a CCD bias voltage generator ASIC that provides 24 independent and programmable 0-32 V outputs. Each channel incorporates a 10-bit digital-to-analogue converter, provides current drive of up to 20 mA into loads of 10 μF, and includes current-limiting and short-circuit protection. An on-chip telemetry system with a 12-bit analogue-to-digital converter enables the outputs and multiple off-chip camera voltages to be monitored. The ASIC can drive one or more CCDs and

  20. Evidence for the involvement of ASIC3 in sensory mechanotransduction in proprioceptors

    Science.gov (United States)

    Lin, Shing-Hong; Cheng, Yuan-Ren; Banks, Robert W.; Min, Ming-Yuan; Bewick, Guy S.; Chen, Chih-Cheng

    2016-01-01

    Acid-sensing ion channel 3 (ASIC3) is involved in acid nociception, but its possible role in neurosensory mechanotransduction is disputed. We report here the generation of Asic3-knockout/eGFPf-knockin mice and subsequent characterization of heterogeneous expression of ASIC3 in the dorsal root ganglion (DRG). ASIC3 is expressed in parvalbumin (Pv+) proprioceptor axons innervating muscle spindles. We further generate a floxed allele of Asic3 (Asic3f/f) and probe the role of ASIC3 in mechanotransduction in neurite-bearing Pv+ DRG neurons through localized elastic matrix movements and electrophysiology. Targeted knockout of Asic3 disrupts spindle afferent sensitivity to dynamic stimuli and impairs mechanotransduction in Pv+ DRG neurons because of substrate deformation-induced neurite stretching, but not to direct neurite indentation. In behavioural tasks, global knockout (Asic3−/−) and Pv-Cre::Asic3f/f mice produce similar deficits in grid and balance beam walking tasks. We conclude that, at least in mouse, ASIC3 is a molecular determinant contributing to dynamic mechanosensitivity in proprioceptors. PMID:27161260

  1. ASIC2 Subunits Target Acid-Sensing Ion Channels to the Synapse via an Association with PSD-95

    OpenAIRE

    Zha, Xiang-ming; Costa, Vivian; Harding, Anne Marie S.; Reznikov, Leah; Benson, Christopher J.; Welsh, Michael J.

    2009-01-01

    Acid-sensing ion channel-1a (ASIC1a) mediates H+-gated current to influence normal brain physiology and impact several models of disease. Although ASIC2 subunits are widely expressed in brain and modulate ASIC1a current, their function remains poorly understood. We identified ASIC2a in dendrites, dendritic spines, and brain synaptosomes. This localization largely relied on ASIC2a binding to PSD-95 and matched that of ASIC1a, which does not co-immunoprecipitate with PSD-95. We found that ASIC2...

  2. An external control unit implemented for stimulator ASIC testing ...

    African Journals Online (AJOL)

    ) for a stimulator ASIC testing purposes. The ECU consists of a graphical user interface (GUI) from the PC, a data transceiver and a power transmitter. The GUI was developed using MATLAB for stimulation data setup. The data transceiver was ...

  3. A Batteryless Sensor ASIC for Implantable Bio-Impedance Applications.

    Science.gov (United States)

    Rodriguez, Saul; Ollmar, Stig; Waqar, Muhammad; Rusu, Ana

    2016-06-01

    The measurement of the biological tissue's electrical impedance is an active research field that has attracted a lot of attention during the last decades. Bio-impedances are closely related to a large variety of physiological conditions; therefore, they are useful for diagnosis and monitoring in many medical applications. Measuring living tissues, however, is a challenging task that poses countless technical and practical problems, in particular if the tissues need to be measured under the skin. This paper presents a bio-impedance sensor ASIC targeting a battery-free, miniature size, implantable device, which performs accurate 4-point complex impedance extraction in the frequency range from 2 kHz to 2 MHz. The ASIC is fabricated in 150 nm CMOS, has a size of 1.22 mm × 1.22 mm and consumes 165 μA from a 1.8 V power supply. The ASIC is embedded in a prototype which communicates with, and is powered by an external reader device through inductive coupling. The prototype is validated by measuring the impedances of different combinations of discrete components, measuring the electrochemical impedance of physiological solution, and performing ex vivo measurements on animal organs. The proposed ASIC is able to extract complex impedances with around 1 Ω resolution; therefore enabling accurate wireless tissue measurements.

  4. Delay 25 an ASIC for timing adjustment in LHC

    NARCIS (Netherlands)

    Furtado, H.; Schrader, J.H.R.; Marchioro, A.; Moreira, P.

    A five channel programmable delay line ASIC was designed featuring 4 channels that allow to phase delay periodic or non-periodic digital signals and a master channel that can be used to phase delay a clock signal. The master channel serves as a calibration reference guaranteeing independence from

  5. The Mixed-Signal ASIC design course at Twente

    NARCIS (Netherlands)

    Stehelin, G.; Tangelder, R.J.W.T.; Gerez, Sabih H.; Kerkhoff, Hans G.; Klumperink, Eric A.M.; Smit, J.; Snijders, H.; Speek, H.; de Vries, H.

    2000-01-01

    In this paper we give a detailed overview of the ASIC design course as it is being given at the Department of Electrical Engineering of the University of Twente. This course covers the complete trajectory from system design via circuit design and actual implementation to testing. Design and testing

  6. Beam test performance of the SKIROC2 ASIC

    CERN Document Server

    Frisson, T; Anduze, M; Augustin, J.E; Bonis, J; Boudry, V; Bourgeois, C; Brient, J.C; Callier, S; Cerutti, M; Chen, S; Cornat, R; Cornebise, P; Cuisy, D; David, J; De la Taille, C; Dulucq, F; Frotin, M; Gastaldi, F; Ghislain, P; Giraud, J; Gonnin, A; Grondin, D; Guliyev, E; Hostachy, J.Y; Jeans, D; Kamiya, Y; Kawagoe, K; Kozakai, C; Lacour, D; Lavergne, L; Lee, S.H; Magniette, F; Ono, H; Poeschl, R; Rouëné, J; Seguin-Moreau, N; Song, H.S; Sudo, Y; Thiebault, A; Tran, H; Ueno, H; Van der Kolk, N; Yoshioka, T

    2015-01-01

    Beam tests of the first layers of CALICE silicon tungsten ECAL technological prototype were performed in April and July 2012 using 1–6 GeV electron beam at DESY. This paper presents an analysis of the SKIROC2 readout ASIC performance under test beam conditions.

  7. Three-dimensional stacked structured ASIC devices and methods of fabrication thereof

    Science.gov (United States)

    Shinde, Subhash L.; Teifel, John; Flores, Richard S.; Jarecki Jr., Robert L.; Bauer, Todd

    2015-11-19

    A 3D stacked sASIC is provided that includes a plurality of 2D reconfigurable structured structured ASIC (sASIC) levels interconnected through hard-wired arrays of 3D vias. The 2D sASIC levels may contain logic, memory, analog functions, and device input/output pad circuitry. During fabrication, these 2D sASIC levels are stacked on top of each other and fused together with 3D metal vias. Such 3D vias may be fabricated as through-silicon vias (TSVs). They may connect to the back-side of the 2D sASIC level, or they may be connected to top metal pads on the front-side of the 2D sASIC level.

  8. Altered myogenic vasoconstriction and regulation of whole kidney blood flow in the ASIC2 knockout mouse.

    Science.gov (United States)

    Gannon, Kimberly P; McKey, Susan E; Stec, David E; Drummond, Heather A

    2015-02-15

    Previous studies from our laboratory have suggested that degenerin proteins contribute to myogenic constriction, a mechanism of blood flow regulation and protection against pressure-dependent organ injury, in renal vessels. The goal of the present study was to determine the importance of one family member, acid-sensing ion channel 2 (ASIC2), in myogenic constriction of renal interlobar arteries, myogenic regulation of whole kidney blood flow, renal injury, and blood pressure using ASIC2(+/+), ASIC2(+/-), and ASIC2(-/-) mice. Myogenic constriction in renal interlobar arteries was impaired in ASIC2(+/-) and ASIC2(-/-) mice, whereas constriction to KCl/phenylephrine was unchanged. Correction of whole kidney renal vascular resistance (RVR) during the first 5 s after a 10- to 20-mmHg step increase in perfusion pressure, a timeframe associated with myogenic-mediated correction of RVR, was slowed (4.2 ± 0.9, 0.3 ± 0.7, and 2.4 ± 0.3 resistance units/s in ASIC2(+/+), ASIC2(+/-), and ASIC2(-/-) mice). Although modest reductions in function were observed in ASIC2(-/-) mice, greater reductions were observed in ASIC2(+/-) mice, which may be explained by protein-protein interactions of ASIC2 with other degenerins. Isolated glomeruli from ASIC2(+/-) and ASIC2(-/-) mice had modest alterations in the expression of inflammation and injury markers (transforming growth factor-β, mouse anti-target of antiproliferative antibody-1, and nephrin), whereas ASIC2(+/-) mice had an increase in the remodeling marker collagen type III. Consistent with a more severe loss of function, mean arterial pressure was increased in ASIC2(+/-) mice (131 ± 3 mmHg) but not in ASIC2(-/-) mice (122 ± 3 vs. 117 ± 2 mmHg in ASIC2(+/+) mice). These results suggest that ASIC2 contributes to transduction of the renal myogenic response and are consistent with the protective role of myogenic constriction against renal injury and hypertension. Copyright © 2015 the American Physiological Society.

  9. Glioblastoma cancer stem cell lines express functional acid sensing ion channels ASIC1a and ASIC3

    DEFF Research Database (Denmark)

    Tian, Yuemin; Bresenitz, Pia; Reska, Anna

    2017-01-01

    Acidic microenvironment is commonly observed in tumour tissues, including glioblastoma (GBM), the most aggressive and lethal brain tumour in adults. Acid sensing ion channels (ASICs) are neuronal voltage-insensitive sodium channels, which are sensors of extracellular protons. Here we studied...

  10. Hydrogen converters

    International Nuclear Information System (INIS)

    Mondino, Angel V.

    2003-01-01

    The National Atomic Energy Commission of Argentina developed a process of 99 Mo production from fission, based on irradiation of uranium aluminide targets with thermal neutrons in the RA-3 reactor of the Ezeiza Atomic Centre. These targets are afterwards dissolved in an alkaline solution, with the consequent liberation of hydrogen as the main gaseous residue. This work deals with the use of a first model of metallic converter and a later prototype of glass converter at laboratory scale, adjusted to the requirements and conditions of the specific redox process. Oxidized copper wires were used, which were reduced to elementary copper at 400 C degrees and then regenerated by oxidation with hot air. Details of the bed structure and the operation conditions are also provided. The equipment required for the assembling in cells is minimal and, taking into account the operation final temperature and the purge with nitrogen, the procedure is totally safe. Finally, the results are extrapolated for the design of a converter to be used in a hot cell. (author)

  11. Multichannel wireless ECoG array ASIC devices.

    Science.gov (United States)

    DeMichele, Glenn A; Cogan, Stuart F; Troyk, Philip R; Chen, Hongnan; Hu, Zhe

    2014-01-01

    Surgical resection of epileptogenic foci is often a beneficial treatment for patients suffering debilitating seizures arising from intractable epilepsy [1], [2], [3]. Electrodes placed subdurally on the surface of the brain in the form of an ECoG array is one of the multiple methods for localizing epileptogenic zones for the purpose of defining the region for surgical resection. Currently, transcutaneous wires from ECoG grids limit the duration of time that implanted grids can be used for diagnosis. A wireless ECoG recording and stimulation system may be a solution to extend the diagnostic period. To avoid the transcutaneous connections, a 64-channel wireless silicon recording/stimulating ASIC was developed as the electronic component of a wireless ECoG array that uses SIROF electrodes on a polyimide substrate[4]. Here we describe two new ASIC devices that have been developed and tested as part of the on-going wireless ECoG system design.

  12. FROST: an ASIC for digital mammography with synchrotron radiation

    International Nuclear Information System (INIS)

    Bergamaschi, A.; Prest, M.; Vallazza, E.; Arfelli, F.; Dreossi, D.; Longo, R.; Olivo, A.; Pani, S.; Castelli, E.

    2003-01-01

    The FRONTier RADiography (FRONTRAD) collaboration is developing a digital system for mammography at the Elettra Synchrotron Light Source in Trieste. The system is based on a silicon microstrip detector array. The ASIC FROST (FRONTRAD Read Out sySTem) was developed as a collaboration between INFN Trieste and Aurelia Microelettronica and is designed to operate in single photon counting mode. FROST provides low-noise and high-gain performances and is able to work at incident photon rates higher than 100 kHz with almost 100% efficiency. The ASIC has been tested and the first images of mammographic test objects will be shown. The acquisition time per breast image should be of about 10 s

  13. A high performance multi-channel preamplifier ASIC

    Energy Technology Data Exchange (ETDEWEB)

    Yarema, R.J.; Zimmerman, T.; Williams, W.; Binkley, M.; Huffman, T.; Wagner, R.

    1991-11-01

    A new preamplifier ASIC has been designed and built to improve performance of the VTPC (Vertex Time Projection Chamber) at Fermilab's Colliding Detector Facility. Design of the semicustom IC was completed using a Tektronix Quick-Chip 2S bipolar linear array. The ASIC has 6 channels on a chip and provides lower noise, higher gain, lower power, and lower mass packaging than the device which it replaces. Actual performance of the preamplifier was found to match very closely the simulated performance. To reduce the mass of the complete circuit board, bare IC dice were mounted directly on a G-10 substrate using COB (chip on board) techniques. The preamplifier and packaging should be applicable to numerous other systems. 1 ref.

  14. PADI ASIC for straw tube read-out

    Energy Technology Data Exchange (ETDEWEB)

    Pietraszko, Jerzy; Traeger, Michael; Fruehauf, Jochen; Schmidt, Christian [GSI, Darmstadt (Germany); Ciobanu, Mircea [ISS, Bucharest (Romania); Collaboration: CBM-Collaboration

    2016-07-01

    A prototype of the CBM MUCH straw tube detector consisting of six individual straws of 6mm inner diameter and 220 mm length filled with Ar/CO{sub 2} gas mixture has been tested at the COSY accelerator in Juelich. The straw tubes were connected to the FEET-PADI6-HDa PCB equipped with PADI-6 fast amplifier/discriminator ASIC. As a reference counter in this measurement the scCVD diamond detector has been used delivering excellent timing, time resolution below 100 ps (sigma), and very precise position information, below 50 μm. The demonstrated position resolution of about 160 μm of the straw tube read out with PADI-6 ASIC confirms the capability of the PADI chip and puts this development as a very attractive readout option for straw tubes and wire chambers.

  15. ASIC and HMC designs for portable nuclear instruments

    International Nuclear Information System (INIS)

    Chandratre, V.B.

    2005-01-01

    This paper describes the seed activity done so far for realizing the goal of compact portable nuclear instruments and related instrumentation that can be designed, developed and manufactured without external constraints. This important activity requires critical components to be made in the country by tapping and gearing the established industrial units for this activity. A good deal of ground work has been carried out over a period of time in setting up IC design facility and CAD-FAB interface. There has been a close interaction with the production and semiconductor facilities to design and develop ASIC, hybrids, display devices, detectors/sensors etc. Efforts are also undertaken to develop the critical technologies that are required to fulfill the requirement. A status report on various technologies, ASIC, hybrids and their application development done in the face of out-standing challenges is being presented here. (author)

  16. Development of the ASICs for the NA62 pixel Gigatracker

    CERN Document Server

    Jarron, P

    2008-01-01

    We present the ASIC development for the readout electronics of the Gigatracker pixel detector of NA62. Specifications of this detector are challenging in terms of timing precision with a hit time stamp accuracy of 100 ps and a peak hit rate of 50 Mhits/cm2/s. A timing precision and hit rate are more than one order of magnitude faster than pixel LHC readout ASIC. The research for pixel cell design and the readout architectures are following two approaches, which are presented and discussed in this paper. Presently demonstrator prototypes are under development and SPICE simulation results of the frontend, the readout strategy and and the pixelcolumn are also presented and discussed.

  17. A high performance multi-channel preamplifier ASIC

    International Nuclear Information System (INIS)

    Yarema, R.J.; Zimmerman, T.; Williams, W.; Binkley, M.; Huffman, T.; Wagner, R.

    1992-01-01

    This paper reports on a new preamplifier ASIC that has been designed and built to improve performance of the VTPC (Vertex Time Projection Chamber) at Fermilab's Collliding Detector Facility. Design of the semicustom IC was completed using a Tektronix QuickChip 2S bipolar linear array. The ASIC has 6 channels on a chip and provides lower noise, higher gain, lower power, and lower mass packaging than the device which it replaces. Actual performance of the preamplifier was found to match very closely the simulated performance. To reduce the mass of the complete circuit board, bare IC dice were mounted directly on a G-10 substrate using COB (chip on board) techniques. The preamplifier and packaging should be applicable to numerous other systems

  18. NINO ASIC electronics used in MRPC/TOF experiment

    International Nuclear Information System (INIS)

    Sun Yongjie; Li Cheng

    2008-01-01

    In order to meet the excellent properties of MRPC, an front-end amplifier/discriminator chip-NINO ASIC, was developed in ALICE TOF group at CERN. This ASIC was fabricated with the 0.25 μm CMOS technology. It is highly integrated and can deal with 8 channels per chip. It has differential input and is differential signal shaping and throughout transition. The peaking time of the amplifier is less than 1 ns. It has LVDS outputs and the width of the output signal depended on the charge of input. This allows the TOT measurement of HPTDC system. A position sensitive MRPC was tested with beam facility using the front-end electronics based on NINO and good results were obtained. (authors)

  19. Implementation of the Timepix ASIC in the Scalable Readout System

    Energy Technology Data Exchange (ETDEWEB)

    Lupberger, M., E-mail: lupberger@physik.uni-bonn.de; Desch, K.; Kaminski, J.

    2016-09-11

    We report on the development of electronics hardware, FPGA firmware and software to provide a flexible multi-chip readout of the Timepix ASIC within the framework of the Scalable Readout System (SRS). The system features FPGA-based zero-suppression and the possibility to read out up to 4×8 chips with a single Front End Concentrator (FEC). By operating several FECs in parallel, in principle an arbitrary number of chips can be read out, exploiting the scaling features of SRS. Specifically, we tested the system with a setup consisting of 160 Timepix ASICs, operated as GridPix devices in a large TPC field cage in a 1 T magnetic field at a DESY test beam facility providing an electron beam of up to 6 GeV. We discuss the design choices, the dedicated hardware components, the FPGA firmware as well as the performance of the system in the test beam.

  20. A high performance multi-channel preamplifier ASIC

    International Nuclear Information System (INIS)

    Yarema, R.J.; Zimmerman, T.; Williams, W.; Binkley, M.; Huffman, T.; Wagner, R.

    1991-11-01

    A new preamplifier ASIC has been designed and built to improve performance of the VTPC (Vertex Time Projection Chamber) at Fermilab's Colliding Detector Facility. Design of the semicustom IC was completed using a Tektronix Quick-Chip 2S bipolar linear array. The ASIC has 6 channels on a chip and provides lower noise, higher gain, lower power, and lower mass packaging than the device which it replaces. Actual performance of the preamplifier was found to match very closely the simulated performance. To reduce the mass of the complete circuit board, bare IC dice were mounted directly on a G-10 substrate using COB (chip on board) techniques. The preamplifier and packaging should be applicable to numerous other systems. 1 ref

  1. An SEU analysis approach for error propagation in digital VLSI CMOS ASICs

    International Nuclear Information System (INIS)

    Baze, M.P.; Bartholet, W.G.; Dao, T.A.; Buchner, S.

    1995-01-01

    A critical issue in the development of ASIC designs is the ability to achieve first pass fabrication success. Unsuccessful fabrication runs have serious impact on ASIC costs and schedules. The ability to predict an ASICs radiation response prior to fabrication is therefore a key issue when designing ASICs for military and aerospace systems. This paper describes an analysis approach for calculating static bit error propagation in synchronous VLSI CMOS circuits developed as an aid for predicting the SEU response of ASIC's. The technique is intended for eventual application as an ASIC development simulation tool which can be used by circuit design engineers for performance evaluation during the pre-fabrication design process in much the same way that logic and timing simulators are used

  2. ASIC design and data communications for the Boston retinal prosthesis.

    Science.gov (United States)

    Shire, Douglas B; Ellersick, William; Kelly, Shawn K; Doyle, Patrick; Priplata, Attila; Drohan, William; Mendoza, Oscar; Gingerich, Marcus; McKee, Bruce; Wyatt, John L; Rizzo, Joseph F

    2012-01-01

    We report on the design and testing of a custom application-specific integrated circuit (ASIC) that has been developed as a key component of the Boston retinal prosthesis. This device has been designed for patients who are blind due to age-related macular degeneration or retinitis pigmentosa. Key safety and communication features of the low-power ASIC are described, as are the highly configurable neural stimulation current waveforms that are delivered to its greater than 256 output electrodes. The ASIC was created using an 0.18 micron Si fabrication process utilizing standard 1.8 volt CMOS transistors as well as 20 volt lightly doped drain FETs. The communication system receives frequency-shift keyed inputs at 6.78 MHz from an implanted secondary coil, and transmits data back to the control unit through a lower-bandwidth channel that employs load-shift keying. The design's safety is ensured by on-board electrode voltage monitoring, stimulus charge limits, error checking of data transmitted to the implant, and comprehensive self-test and performance monitoring features. Each stimulus cycle is initiated by a transmitted word with a full 32-bit error check code. Taken together, these features allow researchers to safely and wirelessly tailor retinal stimulation and vision recovery for each patient.

  3. Four-channel readout ASIC for silicon pad detectors

    International Nuclear Information System (INIS)

    Baturitsky, M.A.; Zamiatin, N.I.

    2000-01-01

    A custom front-end readout ASIC has been designed for silicon calorimeters supposed to be used in high-energy physics experiments. The ASIC was produced using BJT-JFET technology. It contains four channels of a fast low-noise charge-sensitive preamplifier (CSP) with inverting outputs summed by a linear adder (LA) followed by an RC-CR shaping amplifier (SA) with 30 ns peaking time. Availability of separate outputs of the CSPs and the LA makes it possible to join any number of silicon detector layers to obtain the longitudinal and transversal resolution required using only this ASIC in any silicon calorimeter minitower configuration. Noise performance is ENC=1800e - +18e - /pF at 30 ns peaking time for detector capacitance up to C d =400 pF. Rise time is 8 ns at input capacitance C d =100 pF. Power dissipation is less than 50 mW/ chip at voltage supply 5 V

  4. VeloPix ASIC for the LHCb VELO Upgrade

    CERN Multimedia

    Cid Vidal, Xabier

    2015-01-01

    The LHCb Vertex Detector (VELO) will be upgraded in 2018 along with the other subsystems of LHCb in order to enable full detector readout at 40 MHz. LHCb will run without a hardware trigger and all data will be fed directly to the software triggering algorithms in the CPU farm. The upgraded VELO is a lightweight silicon hybrid pixel detector with 55 um square pixels, operating in vacuum in close proximity to the LHC beams. The readout will be provided by a dedicated front end ASIC, dubbed VeloPix, matched to the LHCb luminosity requirements. VeloPix is a binary pixel chip with a matrix of 256 x 256 pixels, covering an area of 2 cm^2. It is designed in a 130 nm CMOS technology, and is closely related to the Timepix3, from the Medipix family of ASICs. The principal challenge that the chip has to meet is a hit rate of up to 900 Mhits/s/ASIC, resulting in a data rate of more than 16 Gbit/s. Combining pixels into groups of 2x4 super-pixels enables the use of shared logic and a reduction of bandwidth due to combine...

  5. ASIC channel inhibition enhances excitotoxic neuronal death in an in vitro model of spinal cord injury.

    Science.gov (United States)

    Mazzone, Graciela L; Veeraraghavan, Priyadharishini; Gonzalez-Inchauspe, Carlota; Nistri, Andrea; Uchitel, Osvaldo D

    2017-02-20

    In the spinal cord high extracellular glutamate evokes excitotoxic damage with neuronal loss and severe locomotor impairment. During the cell dysfunction process, extracellular pH becomes acid and may activate acid-sensing ion channels (ASICs) which could be important contributors to neurodegenerative pathologies. Our previous studies have shown that transient application of the glutamate analog kainate (KA) evokes delayed excitotoxic death of spinal neurons, while white matter is mainly spared. The present goal was to enquire if ASIC channels modulated KA damage in relation to locomotor network function and cell death. Mouse spinal cord slices were treated with KA (0.01 or 0.1mM) for 1h, and then washed out for 24h prior to analysis. RT-PCR results showed that KA (at 0.01mM concentration that is near-threshold for damage) increased mRNA expression of ASIC1a, ASIC1b, ASIC2 and ASIC3, an effect reversed by the ASIC inhibitor 4',6-diamidino-2-phenylindole (DAPI). A KA neurotoxic dose (0.1mM) reduced ASIC1a and ASIC2 expression. Cell viability assays demonstrated KA-induced large damage in spinal slices from mice with ASIC1a gene ablation. Likewise, immunohistochemistry indicated significant neuronal loss when KA was followed by the ASIC inhibitors DAPI or amiloride. Electrophysiological recording from ventral roots of isolated spinal cords showed that alternating oscillatory cycles were slowed down by 0.01mMKA, and intensely inhibited by subsequently applied DAPI or amiloride. Our data suggest that early rise in ASIC expression and function counteracted deleterious effects on spinal networks by raising the excitotoxicity threshold, a result with potential implications for improving neuroprotection. Copyright © 2016 IBRO. Published by Elsevier Ltd. All rights reserved.

  6. ASIC3 Channels Integrate Agmatine and Multiple Inflammatory Signals through the Nonproton Ligand Sensing Domain

    Directory of Open Access Journals (Sweden)

    Cao Hui

    2010-12-01

    Full Text Available Abstract Background Acid-sensing ion channels (ASICs have long been known to sense extracellular protons and contribute to sensory perception. Peripheral ASIC3 channels represent natural sensors of acidic and inflammatory pain. We recently reported the use of a synthetic compound, 2-guanidine-4-methylquinazoline (GMQ, to identify a novel nonproton sensing domain in the ASIC3 channel, and proposed that, based on its structural similarity with GMQ, the arginine metabolite agmatine (AGM may be an endogenous nonproton ligand for ASIC3 channels. Results Here, we present further evidence for the physiological correlation between AGM and ASIC3. Among arginine metabolites, only AGM and its analog arcaine (ARC activated ASIC3 channels at neutral pH in a sustained manner similar to GMQ. In addition to the homomeric ASIC3 channels, AGM also activated heteromeric ASIC3 plus ASIC1b channels, extending its potential physiological relevance. Importantly, the process of activation by AGM was highly sensitive to mild acidosis, hyperosmolarity, arachidonic acid (AA, lactic acid and reduced extracellular Ca2+. AGM-induced ASIC3 channel activation was not through the chelation of extracellular Ca2+ as occurs with increased lactate, but rather through a direct interaction with the newly identified nonproton ligand sensing domain. Finally, AGM cooperated with the multiple inflammatory signals to cause pain-related behaviors in an ASIC3-dependent manner. Conclusions Nonproton ligand sensing domain might represent a novel mechanism for activation or sensitization of ASIC3 channels underlying inflammatory pain-sensing under in vivo conditions.

  7. Ray converter

    International Nuclear Information System (INIS)

    Reiss, K.H.

    1976-01-01

    In a radiographic system a converter is used for changing image forming intensity distribution in a bundle of penetrating rays into a flow of electrically charged particles by electrodes located in a gas space and partly latticed (grids) which lie at potentials stepped from cathode to anode. The invention is particularly characterized by the provision of at least two grids extending between and parallel to the cathode and the anode. The electrical field which lies between two electrodes lies at least between the grids located closest to the cathode being to the extent of between 1 and 10 percent, in the average preferably 3 percent below the electrical break down field in the gas in a homogeneous electrical field

  8. Acid-sensing ion channel 2 (asic 2) and trkb interrelationships within the intervertebral disc.

    Science.gov (United States)

    Cuesta, Antonio; Viña, Eliseo; Cabo, Roberto; Vázquez, Gorka; Cobo, Ramón; García-Suárez, Olivia; García-Cosamalón, José; Vega, José A

    2015-01-01

    The cells of the intervertebral disc (IVD) have an unusual acidic and hyperosmotic microenvironment. They express acid-sensing ion channels (ASICs), gated by extracellular protons and mechanical forces, as well as neurotrophins and their signalling receptors. In the nervous tissues some neurotrophins regulate the expression of ASICs. The expression of ASIC2 and TrkB in human normal and degenerated IVD was assessed using quantitative-PCR, Western blot, and immunohistochemistry. Moreover, we investigated immunohistochemically the expression of ASIC2 in the IVD of TrkB-deficient mice. ASIC2 and TrkB mRNAs were found in normal human IVD and both increased significantly in degenerated IVD. ASIC2 and TrkB proteins were also found co-localized in a variable percentage of cells, being significantly higher in degenerated IVD than in controls. The murine IVD displayed ASIC2 immunoreactivity which was absent in the IVD of TrkB-deficient mice. Present results demonstrate the occurrence of ASIC2 and TrkB in the human IVD, and the increased expression of both in pathological IVD suggest their involvement in IVD degeneration. These data also suggest that TrkB-ligands might be involved in the regulation of ASIC2 expression, and therefore in mechanisms by which the IVD cells accommodate to low pH and hypertonicity.

  9. Identification of a novel protein complex containing ASIC1a and GABAA receptors and their interregulation.

    Directory of Open Access Journals (Sweden)

    Dongbo Zhao

    Full Text Available Acid-sensing ion channels (ASICs belong to the family of the epithelial sodium channel/degenerin (ENaC/DEG and are activated by extracellular protons. They are widely distributed within both the central and peripheral nervous systems. ASICs were modified by the activation of γ-aminobutyric acid receptors (GABAA, a ligand-gated chloride channels, in hippocampal neurons. In contrast, the activity of GABAA receptors were also modulated by extracellular pH. However so far, the mechanisms underlying this intermodulation remain obscure. We hypothesized that these two receptors-GABAA receptors and ASICs channels might form a novel protein complex and functionally interact with each other. In the study reported here, we found that ASICs were modified by the activation of GABAA receptors either in HEK293 cells following transient co-transfection of GABAA and ASIC1a or in primary cultured dorsal root ganglia (DRG neurons. Conversely, activation of ASIC1a also modifies the GABAA receptor-channel kinetics. Immunoassays showed that both GABAA and ASIC1a proteins were co-immunoprecipitated mutually either in HEK293 cells co-transfected with GABAA and ASIC1a or in primary cultured DRG neurons. Our results indicate that putative GABAA and ASIC1a channels functionally interact with each other, possibly via an inter-molecular association by forming a novel protein complex.

  10. [Effect of Scalp-acupuncture Stimulation on Neurological Function and Expression of ASIC 1 a and ASIC 2 b of Hippocampal CA 1 Region in Cerebral Ischemia Rats].

    Science.gov (United States)

    Tian, Liang; Wang, Jin-Hai; Zhao, Min; Bao, Ying-Cun; Shang, Jun-Fang; Yan, Qi; Zhang, Zhen-Chang; Du, Xiao-Zheng; Jiang, Hua; Sun, Run-Jie; Yuan, Bo; Zhang, Xing-Hua; Zhang, Ting-Zhuo; Li, Xing-Lan

    2016-10-25

    To observe the influence of scalp-acupuncture on the expression of acid-sensing ion channels (ASICs) 1 a and 2 b of hippocampal CA 1 region in cerebral ischemia (CI) rats, so as to investigate its mechanism underlying improvement of ischemic stroke. Thirty-two male SD rats were randomly allocated to normal control, model, scalp-acupuncture and Amiloride group ( n =8 in each group). The model of focal CI was established by middle cerebral artery occlusion (MCAO). Scalp acupuncture stimulation was applied to bilateral Dingnieqianxiexian (MS 6) and Dingniehouxiexian (MS 7), once daily for 7 days. Rats of the Amiloride group were fed with Amiloride solution, twice a day for 7 days, and those of the normal control and model groups were grabbled and fixed in the same way with the acupuncture and Amiloride groups. The neurological deficit score was given according to Longa's method. The expression of hippocampal ASIC 1 a and ASIC 2 b was detected by immunohistochemistry, and the Ca 2+ concentration in the hippocampal tissue assayed using flowing cytometry. After the intervention, the neurological deficit score of both the scalp-acupuncture and Amiloride groups were significantly decreased in comparison with pre-treatment ( P ASIC 1 a and ASIC 2 b in the hippocampal CA 1 region and hip-pocampal Ca 2+ concentration were significantly up-regulated in the model group compared with the normal control group ( P ASIC 1 a and ASIC 2 b expression and Ca 2+ concentration ( P >0.05). Scalp-acupuncture stimulation can improve neurological function in CI rats, which may be related to its effects in suppressing the increased expression of hippocampal ASIC 1 a and ASIC 2 b proteins and in reducing calcium overload in hip-pocampal neurocytes.

  11. The role of periodontal ASIC3 in orofacial pain induced by experimental tooth movement in rats.

    Science.gov (United States)

    Gao, Meiya; Long, Hu; Ma, Wenqiang; Liao, Lina; Yang, Xin; Zhou, Yang; Shan, Di; Huang, Renhuan; Jian, Fan; Wang, Yan; Lai, Wenli

    2016-12-01

    This study aimed to clarify the roles of Acid-sensing ion channel 3 (ASIC3) in orofacial pain following experimental tooth movement. Sixty male Sprague-Dawley rats were divided into the experimental group (40g, n = 30) and the sham group (0g, n = 30). Closed coil springs were ligated between maxillary incisor and molars to achieve experimental tooth movement. Rat grimace scale (RGS) scores were assessed at 0, 1, 3, 5, 7, and 14 days after the placement of the springs. ASIC3 immunostaining was performed and the expression levels of ASIC3 were measured through integrated optical density/area in Image-Pro Plus 6.0. Moreover, 18 rats were divided into APETx2 group (n = 6), amiloride group (n = 6), and vehicle group (n = 6), and RGS scores were obtained compared among them to verify the roles of ASIC3 in orofacial pain following tooth movement. ASIC3 expression levels became significantly higher in the experimental group than in sham group on 1, 3, and 5 days and became similar on 7 and 14 days. Pain levels (RGS scores) increased in both groups and were significantly higher in the experimental group on 1, 3, 5, and 7 days and were similar on 14 days. Periodontal ASIC3 expression levels were correlated with orofacial pain levels following experimental tooth movement. Periodontal administrations of ASIC3 antagonists (APETx2 and amiloride) could alleviate pain. This study needs to be better evidenced by RNA interference of ASIC3 in periodontal tissues in rats following experimental tooth movement. Moreover, we hope further studies would concentrate on the pain perception of ASIC3 knockout (ASIC3 -/- ) mice. Our results suggest that periodontal ASIC3 plays an important role in orofacial pain induced by experimental tooth movement. © The Author 2015. Published by Oxford University Press on behalf of the European Orthodontic Society. All rights reserved. For permissions, please email: journals.permissions@oup.com.

  12. ASIC-dependent LTP at multiple glutamatergic synapses in amygdala network is required for fear memory.

    Science.gov (United States)

    Chiang, Po-Han; Chien, Ta-Chun; Chen, Chih-Cheng; Yanagawa, Yuchio; Lien, Cheng-Chang

    2015-05-19

    Genetic variants in the human ortholog of acid-sensing ion channel-1a subunit (ASIC1a) gene are associated with panic disorder and amygdala dysfunction. Both fear learning and activity-induced long-term potentiation (LTP) of cortico-basolateral amygdala (BLA) synapses are impaired in ASIC1a-null mice, suggesting a critical role of ASICs in fear memory formation. In this study, we found that ASICs were differentially expressed within the amygdala neuronal population, and the extent of LTP at various glutamatergic synapses correlated with the level of ASIC expression in postsynaptic neurons. Importantly, selective deletion of ASIC1a in GABAergic cells, including amygdala output neurons, eliminated LTP in these cells and reduced fear learning to the same extent as that found when ASIC1a was selectively abolished in BLA glutamatergic neurons. Thus, fear learning requires ASIC-dependent LTP at multiple amygdala synapses, including both cortico-BLA input synapses and intra-amygdala synapses on output neurons.

  13. Design for ASIC reliability for low-temperature applications

    Science.gov (United States)

    Chen, Yuan; Mojaradi, Mohammad; Westergard, Lynett; Billman, Curtis; Cozy, Scott; Burke, Gary; Kolawa, Elizabeth

    2005-01-01

    In this paper, we present a methodology to design for reliability for low temperature applications without requiring process improvement. The developed hot carrier aging lifetime projection model takes into account both the transistor substrate current profile and temperature profile to determine the minimum transistor size needed in order to meet reliability requirements. The methodology is applicable for automotive, military, and space applications, where there can be varying temperature ranges. A case study utilizing this methodology is given to design for reliability into a custom application-specific integrated circuit (ASIC) for a Mars exploration mission.

  14. Coarse Grain Reconfigurable ASIC through Multiplexer Based Switches

    Science.gov (United States)

    2015-09-15

    chip area (0.5 mm2), and from simulation their power consumption is negligible (0.002% from simulation, too small to measure in physical system...performing implementation that is also flexible. REFERENCES [1] I. Kuon and J. Rose, “ Measuring the gap between FPGAs and ASICs,” IEEE Trans...A 3GPP- LTE Example," Solid-State Circuits, IEEE Journal of , vol.47, no.3, pp.757,768, March 2012. [5] Agarwal, A.; Hassanieh, H.; Abari, O

  15. PICK1 regulates the trafficking of ASIC1a and acidotoxicity in a BAR domain lipid binding-dependent manner

    Directory of Open Access Journals (Sweden)

    Jin Wenying

    2010-12-01

    Full Text Available Abstract Background Acid-sensing ion channel 1a (ASIC1a is the major ASIC subunit determining acid-activated currents in brain neurons. Recent studies show that ASIC1a play critical roles in acid-induced cell toxicity. While these studies raise the importance of ASIC1a in diseases, mechanisms for ASIC1a trafficking are not well understood. Interestingly, ASIC1a interacts with PICK1 (protein interacting with C-kinase 1, an intracellular protein that regulates trafficking of several membrane proteins. However, whether PICK1 regulates ASIC1a surface expression remains unknown. Results Here, we show that PICK1 overexpression increases ASIC1a surface level. A BAR domain mutant of PICK1, which impairs its lipid binding capability, blocks this increase. Lipid binding of PICK1 is also required for PICK1-induced clustering of ASIC1a. Consistent with the effect on ASIC1a surface levels, PICK1 increases ASIC1a-mediated acidotoxicity and this effect requires both the PDZ and BAR domains of PICK1. Conclusions Taken together, our results indicate that PICK1 regulates trafficking and function of ASIC1a in a lipid binding-dependent manner.

  16. The Human Acid-Sensing Ion Channel ASIC1a: Evidence for a Homotetrameric Assembly State at the Cell Surface.

    Directory of Open Access Journals (Sweden)

    Miguel Xavier van Bemmelen

    Full Text Available The chicken acid-sensing ion channel ASIC1 has been crystallized as a homotrimer. We address here the oligomeric state of the functional ASIC1 in situ at the cell surface. The oligomeric states of functional ASIC1a and mutants with additional cysteines introduced in the extracellular pore vestibule were resolved on SDS-PAGE. The functional ASIC1 complexes were stabilized at the cell surface of Xenopus laevis oocytes or CHO cells either using the sulfhydryl crosslinker BMOE, or sodium tetrathionate (NaTT. Under these different crosslinking conditions ASIC1a migrates as four distinct oligomeric states that correspond by mass to multiples of a single ASIC1a subunit. The relative importance of each of the four ASIC1a oligomers was critically dependent on the availability of cysteines in the transmembrane domain for crosslinking, consistent with the presence of ASIC1a homo-oligomers. The expression of ASIC1a monomers, trimeric or tetrameric concatemeric cDNA constructs resulted in functional channels. The resulting ASIC1a complexes are resolved as a predominant tetramer over the other oligomeric forms, after stabilization with BMOE or NaTT and SDS-PAGE/western blot analysis. Our data identify a major ASIC1a homotetramer at the surface membrane of the cell expressing functional ASIC1a channel.

  17. Design and characterization of a 64 channels ASIC front-end electronics for high-flux particle beam detectors

    Science.gov (United States)

    Fausti, F.; Mazza, G.; Attili, A.; Mazinani, M. Fadavi; Giordanengo, S.; Lavagno, M.; Manganaro, L.; Marchetto, F.; Monaco, V.; Sacchi, R.; Vignati, A.; Cirio, R.

    2017-09-01

    A new wide-input range 64-channels current-to-frequency converter ASIC has been developed and characterized for applications in beam monitoring of therapeutic particle beams. This chip, named TERA09, has been designed to extend the input current range, compared to the previous versions of the chip, for dealing with high-flux pulsed beams. A particular care was devoted in achieving a good conversion linearity over a wide bipolar input current range. Using a charge quantum of 200 fC, a linearity within ±2% for an input current range between 3 nA and 12 μA is obtained for individual channels, with a gain spread among the channels of about 3%. By connecting all the 64 channels of the chip to a common input, the current range can be increased 64 times preserving a linearity within ±3% in the range between and 20 μA and 750 μA.

  18. Multichannel readout ASIC design flow for high energy physics and cosmic rays experiments

    International Nuclear Information System (INIS)

    Voronin, A; Malankin, E

    2016-01-01

    In the large-scale high energy physics and astrophysics experiments multi-channel readout application specific integrated circuits (ASICs) are widely used. The ASICs for such experiments are complicated systems, which usually include both analog and digital building blocks. The complexity and large number of channels in such ASICs require the proper methodological approach to their design. The paper represents the mixed-signal design flow of the ASICs for high energy physics and cosmic rays experiments. This flow was successfully embedded to the development of the read-out ASIC prototype for the muon chambers of the CBM experiment. The approach was approved in UMC CMOS MMRF 180 nm process. The design flow enable to analyse the mixed-signal system operation on the different levels: functional, behavioural, schematic and post layout including parasitic elements. The proposed design flow allows reducing the simulation period and eliminating the functionality mismatches on the very early stage of the design. (paper)

  19. Characterisation of the VMM3 Front-end read-out ASIC

    CERN Document Server

    Bartels, Lara Maria

    2018-01-01

    This research project was conducted in the RD51 collaboration at CERN, which is involved in the development of micropattern gaseous detector technologies and read-out systems. One example in the broad range of possible applications of such gaseous detectors is the NMX macromolecular diffractometer instrument planned for the European spallation source (ESS) which is currently under construction in Lund, Sweden. For the NMX instrument neutron detectors with high rate capabilities, high stability and excellent spatial resolution are required. A group working in the RD51 collaboration at CERN within the BrightnESS project aims to fulfil those requirements using gas electron multiplier (GEM) detectors with Gadolinium foils as neutron converters [PFE]. In order to match the high rate capability of the detectors, new front-end read-out systems need to be tested and implemented. This project aims to understand and test the capabilities of the VMM3 as the front-end read-out ASIC for GEM detectors.

  20. Development of 40 channel waveform sampling CMOS ASIC board for Positron Emission Tomography

    International Nuclear Information System (INIS)

    Shimazoe, Kenji; Yeol, Yeom-Jung; Minamikawa, Yasuhiro; Tomida, Yuki; Takahashi, Hiroyuki; Fujita, Kaoru; Nakazawa, Masaharu; Murayama, Hideo

    2007-01-01

    We have designed and fabricated 10 channel/6-bit waveform sampling ASICs using ROHM 0.35 μm CMOS technology. This chip was designed for GSO-APD γ-ray detector and provides a function of 'waveform recording' at a sampling frequency of 100 MHz. This chip has 10 channel inputs and each channel has preamp/variable gain amplifier/6-bit folding ADC. The folding ADC greatly reduces the number of comparators and the power consumption of the chip. This chip provides a full function of recording a transient behavior of detector charge signals for each pulse. Self-trigger function is equipped with the system and this will enable simultaneous record of all input waveforms. Each channel has 64 words FIFO where each waveform data are stored. Stored data are converted to serial data and passed to an FPGA where we can implement a detailed signal processing. This chip is operated at 3.3 V and the power consumption is 1.2 W/chip. We have developed a data acquisition board using four bare chips. This board has 40 input channels and we plan to use this board for APD-based DOI-PET detector system which utilizes several different crystals to recognize depth positions by the difference in their decay times

  1. ASIC for time-of-flight measurements with picosecond timing resolution

    Energy Technology Data Exchange (ETDEWEB)

    Stankova, Vera; Shen, Wei; Harion, Tobias [Kirchhoff-Institute for Physics, Heidelberg Univ. (Germany)

    2015-07-01

    The Positron Emission Tomography (PET) images are especially affected by a high level of noise. This noise affects the potential to detect and discriminate the tumor in relation to the background. Including Time-of-Flight information, with picosecond time resolution, within the conventional PET scanners will improve the signal-to-noise ratio (SNR) and in sequence the quality of the medical images. A mix-mode ASIC (STIC3) has been developed for high precision timing measurements with Silicon Photomultipliers (SiPM). The STiC3 is 64-channel chip, with fully differential analog front-end for crosstalk and electronic noise immunity. It integrates Time to Digital Converters (TDC) with time binning of 50.2 ps for time and energy measurements. Measurements of the of the analog front-end show a time jitter less than 20 ps and jitter of the TDC together with the digital part is around 37 ps. Further the timing of a channel has been tested by injecting a pulse into two channels and measuring the time difference of the recorded timestamps. A Coincidence Time Resolution (CTR) of 215 ps FWHM has been obtained with 3.1 x 3.1 x 15 mm{sup 2} LYSO:Ce scintillator crystals and Hamamatsu SiPM matric (S12643-050CN(x)). Characterization measurements with the chip and its performances are presented.

  2. Development of X-ray CCD camera system with high readout rate using ASIC

    International Nuclear Information System (INIS)

    Nakajima, Hiroshi; Matsuura, Daisuke; Anabuki, Naohisa; Miyata, Emi; Tsunemi, Hiroshi; Doty, John P.; Ikeda, Hirokazu; Katayama, Haruyoshi

    2009-01-01

    We report on the development of an X-ray charge-coupled device (CCD) camera system with high readout rate using application-specific integrated circuit (ASIC) and Camera Link standard. The distinctive ΔΣ type analog-to-digital converter is introduced into the chip to achieve effective noise shaping and to obtain a high resolution with relatively simple circuits. The unit test proved moderately low equivalent input noise of 70μV with a high readout pixel rate of 625 kHz, while the entire chip consumes only 100 mW. The Camera Link standard was applied for the connectivity between the camera system and frame grabbers. In the initial test of the whole system, we adopted a P-channel CCD with a thick depletion layer developed for X-ray CCD camera onboard the next Japanese X-ray astronomical satellite. The characteristic X-rays from 109 Cd were successfully read out resulting in the energy resolution of 379(±7)eV (FWHM) at 22.1 keV, that is, ΔE/E=1.7% with a readout rate of 44 kHz.

  3. A CMOS ASIC Design for SiPM Arrays.

    Science.gov (United States)

    Dey, Samrat; Banks, Lushon; Chen, Shaw-Pin; Xu, Wenbin; Lewellen, Thomas K; Miyaoka, Robert S; Rudell, Jacques C

    2011-12-01

    Our lab has previously reported on novel board-level readout electronics for an 8×8 silicon photomultiplier (SiPM) array featuring row/column summation technique to reduce the hardware requirements for signal processing. We are taking the next step by implementing a monolithic CMOS chip which is based on the row-column architecture. In addition, this paper explores the option of using diagonal summation as well as calibration to compensate for temperature and process variations. Further description of a timing pickoff signal which aligns all of the positioning (spatial channels) pulses in the array is described. The ASIC design is targeted to be scalable with the detector size and flexible to accommodate detectors from different vendors. This paper focuses on circuit implementation issues associated with the design of the ASIC to interface our Phase II MiCES FPGA board with a SiPM array. Moreover, a discussion is provided for strategies to eventually integrate all the analog and mixed-signal electronics with the SiPM, on either a single-silicon substrate or multi-chip module (MCM).

  4. Exploring Many-Core Design Templates for FPGAs and ASICs

    Directory of Open Access Journals (Sweden)

    Ilia Lebedev

    2012-01-01

    Full Text Available We present a highly productive approach to hardware design based on a many-core microarchitectural template used to implement compute-bound applications expressed in a high-level data-parallel language such as OpenCL. The template is customized on a per-application basis via a range of high-level parameters such as the interconnect topology or processing element architecture. The key benefits of this approach are that it (i allows programmers to express parallelism through an API defined in a high-level programming language, (ii supports coarse-grained multithreading and fine-grained threading while permitting bit-level resource control, and (iii reduces the effort required to repurpose the system for different algorithms or different applications. We compare template-driven design to both full-custom and programmable approaches by studying implementations of a compute-bound data-parallel Bayesian graph inference algorithm across several candidate platforms. Specifically, we examine a range of template-based implementations on both FPGA and ASIC platforms and compare each against full custom designs. Throughout this study, we use a general-purpose graphics processing unit (GPGPU implementation as a performance and area baseline. We show that our approach, similar in productivity to programmable approaches such as GPGPU applications, yields implementations with performance approaching that of full-custom designs on both FPGA and ASIC platforms.

  5. Robust Multivariable Optimization and Performance Simulation for ASIC Design

    Science.gov (United States)

    DuMonthier, Jeffrey; Suarez, George

    2013-01-01

    Application-specific-integrated-circuit (ASIC) design for space applications involves multiple challenges of maximizing performance, minimizing power, and ensuring reliable operation in extreme environments. This is a complex multidimensional optimization problem, which must be solved early in the development cycle of a system due to the time required for testing and qualification severely limiting opportunities to modify and iterate. Manual design techniques, which generally involve simulation at one or a small number of corners with a very limited set of simultaneously variable parameters in order to make the problem tractable, are inefficient and not guaranteed to achieve the best possible results within the performance envelope defined by the process and environmental requirements. What is required is a means to automate design parameter variation, allow the designer to specify operational constraints and performance goals, and to analyze the results in a way that facilitates identifying the tradeoffs defining the performance envelope over the full set of process and environmental corner cases. The system developed by the Mixed Signal ASIC Group (MSAG) at the Goddard Space Flight Center is implemented as a framework of software modules, templates, and function libraries. It integrates CAD tools and a mathematical computing environment, and can be customized for new circuit designs with only a modest amount of effort as most common tasks are already encapsulated. Customization is required for simulation test benches to determine performance metrics and for cost function computation.

  6. Radiation-hard ASICs for optical data transmission in the first phase of the LHC upgrade

    International Nuclear Information System (INIS)

    Gan, K K; Kagan, H P; Kass, R D; Moore, J R; Smith, D S; Buchholz, P; Wiese, A; Ziolkowskic, M

    2010-01-01

    We have designed two ASICs for possible applications in the optical links of a new layer of the pixel detector to be install inside the ATLAS Pixel detector for the first phase of the LHC luminosity upgrade. The ASICs include a high-speed driver for the VCSEL and a receiver/decoder to decode the signal received at the PIN diode to extract the data and clock. Both ASICs contain 4 channels for operation with a VCSEL or PIN array. The ASICs were designed using a 130 nm CMOS process to enhance the radiation-hardness. We have characterized the fabricated ASICs and the performance of the ASICs is satisfactory. The receiver/decoder can properly decode the bi-phase marked input stream with low PIN current and the driver can operate a VCSEL up to ∼ 5 Gb/s. The added functionalities are also successful, including redundancy to bypass a broken VCSEL or PIN channel, individual control of VCSEL current, and power-on reset circuit to set all VCSEL currents to a nominal value. The ASICs were irradiated to a dose of 46 Mrad with 24 GeV/c protons. The observed modest degradation is acceptable and the single event upset rate is negligible.

  7. Radiation-hard ASICs for optical data transmission in the first phase of the LHC upgrade

    CERN Document Server

    Gan, K K; Kagan, H P; Kass, R D; Moore, J R; Smith, D S; Wiese, A; Ziolkowskic, M; 10.1088/1748-0221/5/12/C12006

    2010-01-01

    We have designed two ASICs for possible applications in the optical links of a new layer of the pixel detector to be install inside the ATLAS Pixel detector for the first phase of the LHC luminosity upgrade. The ASICs include a high-speed driver for the VCSEL and a receiver/decoder to decode the signal received at the PIN diode to extract the data and clock. Both ASICs contain 4 channels for operation with a VCSEL or PIN array. The ASICs were designed using a 130 nm CMOS process to enhance the radiation-hardness. We have characterized the fabricated ASICs and the performance of the ASICs is satisfactory. The receiver/decoder can properly decode the bi-phase marked input stream with low PIN current and the driver can operate a VCSEL up to ~ 5 Gb/s. The added functionalities are also successful, including redundancy to bypass a broken VCSEL or PIN channel, individual control of VCSEL current, and power-on reset circuit to set all VCSEL currents to a nominal value. The ASICs were irradiated to a dose of 46 Mrad ...

  8. Subtype-specific Modulation of Acid-sensing Ion Channel (ASIC) Function by 2-Guanidine-4-methylquinazoline*

    Science.gov (United States)

    Alijevic, Omar; Kellenberger, Stephan

    2012-01-01

    Acid-sensing ion channels (ASICs) are neuronal Na+-selective channels that are transiently activated by extracellular acidification. ASICs are involved in fear and anxiety, learning, neurodegeneration after ischemic stroke, and pain sensation. The small molecule 2-guanidine-4-methylquinazoline (GMQ) was recently shown to open ASIC3 at physiological pH. We have investigated the mechanisms underlying this effect and the possibility that GMQ may alter the function of other ASICs besides ASIC3. GMQ shifts the pH dependence of activation to more acidic pH in ASIC1a and ASIC1b, whereas in ASIC3 this shift goes in the opposite direction and is accompanied by a decrease in its steepness. GMQ also induces an acidic shift of the pH dependence of inactivation of ASIC1a, -1b, -2a, and -3. As a consequence, the activation and inactivation curves of ASIC3 but not other ASICs overlap in the presence of GMQ at pH 7.4, thereby creating a window current. At concentrations >1 mm, GMQ decreases maximal peak currents by reducing the unitary current amplitude. Mutation of residue Glu-79 in the palm domain of ASIC3, previously shown to be critical for channel opening by GMQ, disrupted the GMQ effects on inactivation but not activation. This suggests that this residue is involved in the consequences of GMQ binding rather than in the binding interaction itself. This study describes the mechanisms underlying the effects of a novel class of ligands that modulate the function of all ASICs as well as activate ASIC3 at physiological pH. PMID:22948146

  9. Subtype-specific modulation of acid-sensing ion channel (ASIC) function by 2-guanidine-4-methylquinazoline.

    Science.gov (United States)

    Alijevic, Omar; Kellenberger, Stephan

    2012-10-19

    Acid-sensing ion channels (ASICs) are neuronal Na(+)-selective channels that are transiently activated by extracellular acidification. ASICs are involved in fear and anxiety, learning, neurodegeneration after ischemic stroke, and pain sensation. The small molecule 2-guanidine-4-methylquinazoline (GMQ) was recently shown to open ASIC3 at physiological pH. We have investigated the mechanisms underlying this effect and the possibility that GMQ may alter the function of other ASICs besides ASIC3. GMQ shifts the pH dependence of activation to more acidic pH in ASIC1a and ASIC1b, whereas in ASIC3 this shift goes in the opposite direction and is accompanied by a decrease in its steepness. GMQ also induces an acidic shift of the pH dependence of inactivation of ASIC1a, -1b, -2a, and -3. As a consequence, the activation and inactivation curves of ASIC3 but not other ASICs overlap in the presence of GMQ at pH 7.4, thereby creating a window current. At concentrations >1 mM, GMQ decreases maximal peak currents by reducing the unitary current amplitude. Mutation of residue Glu-79 in the palm domain of ASIC3, previously shown to be critical for channel opening by GMQ, disrupted the GMQ effects on inactivation but not activation. This suggests that this residue is involved in the consequences of GMQ binding rather than in the binding interaction itself. This study describes the mechanisms underlying the effects of a novel class of ligands that modulate the function of all ASICs as well as activate ASIC3 at physiological pH.

  10. Design and Characteristics of a Multichannel Front-End ASIC Using Current-Mode CSA for Small-Animal PET Imaging.

    Science.gov (United States)

    Ollivier-Henry, N; Wu Gao; Xiaochao Fang; Mbow, N A; Brasse, D; Humbert, B; Hu-Guo, C; Colledani, C; Yann Hu

    2011-02-01

    This paper presents the design and characteristics of a front-end readout application-specific integrated circuit (ASIC) dedicated to a multichannel-plate photodetector coupled to LYSO scintillating crystals. In our configuration, the crystals are oriented in the axial direction readout on both sides by individual photodetector channels allowing the spatial resolution and the detection efficiency to be independent of each other. Both energy signals and timing triggers from the photodetectors are required to be read out by the front-end ASIC. A current-mode charge-sensitive amplifier is proposed for this application. This paper presents performance characteristics of a 10-channel prototype chip designed and fabricated in a 0.35-μm complementary metal-oxide semiconductor process. The main results of simulations and measurements are presented and discussed. The gain of the chip is 13.1 mV/pC while the peak time of a CR-RC pulse shaper is 280 ns. The signal-to-noise ratio is 39 dB and the rms noise is 300 μV/√(Hz). The nonlinearity is less than 3% and the crosstalk is about 0.2%. The power dissipation is less than 15 mW/channel. This prototype will be extended to a 64-channel circuit with integrated time-to-digital converter and analog-to-digital converter together for a high-sensitive small-animal positron emission tomography imaging system.

  11. ASIC Development for Three-Dimensional Silicon Imaging Array for Cold Neutrons

    International Nuclear Information System (INIS)

    Britton, C.L.; Jagadish, U.; Bryan, W.L.

    2004-01-01

    An Integrated Circuit (IC) readout chip with four channels arranged so as to receive input charge from the corners of the chip was designed for use with 5- to 7-mm pixel detectors. This Application Specific IC (ASIC) can be used for cold neutron imaging, for study of structural order in materials using cold neutron scattering or for particle physics experiments. The ASIC is fabricated in a 0.5-(micro)m n-well AMI process. The design of the ASIC and the test measurements made is reported. Noise measurements are also reported

  12. Characterization of low-mass deformable mirrors and ASIC drivers for high-contrast imaging

    Science.gov (United States)

    Mejia Prada, Camilo; Yao, Li; Wu, Yuqian; Roberts, Lewis C.; Shelton, Chris; Wu, Xingtao

    2017-09-01

    The development of compact, high performance Deformable Mirrors (DMs) is one of the most important technological challenges for high-contrast imaging on space missions. Microscale Inc. has fabricated and characterized piezoelectric stack actuator deformable mirrors (PZT-DMs) and Application-Specific Integrated Circuit (ASIC) drivers for direct integration. The DM-ASIC system is designed to eliminate almost all cables, enabling a very compact optical system with low mass and low power consumption. We report on the optical tests used to evaluate the performance of the DM and ASIC units. We also compare the results to the requirements for space-based high-contrast imaging of exoplanets.

  13. Study of preamplifier, shaper and peak detector in readout ASIC for particle detector

    International Nuclear Information System (INIS)

    Wang Ke; Zhang Shengjun; Fan Lei; Li Xian

    2014-01-01

    Recently, kinds of particle detectors have used Application Specific Integrated Circuits (ASIC) in their electronics readout system and ASICs have been designed in China now. This project designed a multi-channel readout ASIC for general detector. The chip has Preamplifier, Shaper and Peak Detector embedded for easy readout. For each channel, signal which is preprocessed by a low-noise preamplifier is sent to the shaper to form a quasi-Gaussian pulse and keep its peak for readout. This chip and modules of individual Preamplifier, Shaper and Peak Detector have been manufactured, results will be reported in time. (authors)

  14. First irradiation test results of the ALICE SAMPA ASIC

    CERN Document Server

    Mahmood, Sohail Musa; Winje, Fredrik Lindseth; Velure, Arild

    2018-01-01

    With the continuous scaling of the CMOS technology, the CMOS circuits are considered to be more tolerant to Single event Latchup (SEL) effects due to the reduction in the supply voltages. This paper reports the results from SEL testing performed on the first two prototypes for the new readout ASIC (SAMPA). During RUN 3/RUN 4 at the Large Hadron Collider (LHC), the SAMPA chip will be used for the upgrade of read-out front end electronics of the ALICE (A Large Ion Collider Experiment) Time Projection Chamber (TPC) and Muon Chambers (MCH). The first prototype MPW1 and the second prototype V2 of the SAMPA chip were delivered in 2015 and 2016, respectively. The results are summarized from two different proton beam irradiation campaigns, conducted for SAMPA MPW1 and V2 prototypes at The Svedberg Laboratory (TSL) in Uppsala, and the Center of Advanced Radiation Technology (KVI) in Groningen, respectively.

  15. Macro Pixel ASIC (MPA): The readout ASIC for the pixel-strip (PS) module of the CMS outer tracker at HL-LHC

    CERN Document Server

    Ceresa, Davide; Kloukinas, Konstantinos; Jan Kaplon; Bialas, Wojciech; Re, Valerio; Traversi, Gianluca; Gaioni, Luigi; Ratti, Lodovico

    2014-01-01

    The CMS tracker at HL-LHC is required to provide prompt information on particles with high transverse momentum to the central Level\\,1 trigger. For this purpose, the innermost part of the outer tracker is based on a combination of a pixelated sensor with a short strip sensor, the so-called Pixel-Strip module (PS). The readout of these sensors is carried out by distinct ASICs, the Strip Sensor ASIC (SSA), for the strip layer, and the Macro Pixel ASIC (MPA) for the pixel layer. The processing of the data directly on the front-end module represents a design challenge due to the large data volume (30720\\,pixels and 1920\\,strips per module) and the limited power budget. This is the reason why several studies have been carried out to find the best compromise between ASICs performance and power consumption. This paper describes the current status of the MPA ASIC development where the logic for generating prompt information on particles with high transverse momentum is implemented. An overview of the readout method i...

  16. Acid-sensing ion channel (ASIC) structure and function: Insights from spider, snake and sea anemone venoms.

    Science.gov (United States)

    Cristofori-Armstrong, Ben; Rash, Lachlan D

    2017-12-01

    Acid-sensing ion channels (ASICs) are proton-activated cation channels that are expressed in a variety of neuronal and non-neuronal tissues. As proton-gated channels, they have been implicated in many pathophysiological conditions where pH is perturbed. Venom derived compounds represent the most potent and selective modulators of ASICs described to date, and thus have been invaluable as pharmacological tools to study ASIC structure, function, and biological roles. There are now ten ASIC modulators described from animal venoms, with those from snakes and spiders favouring ASIC1, while the sea anemones preferentially target ASIC3. Some modulators, such as the prototypical ASIC1 modulator PcTx1 have been studied in great detail, while some of the newer members of the club remain largely unstudied. Here we review the current state of knowledge on venom derived ASIC modulators, with a particular focus on their molecular interaction with ASICs, what they have taught us about channel structure, and what they might still reveal about ASIC function and pathophysiological roles. This article is part of the Special Issue entitled 'Venom-derived Peptides as Pharmacological Tools.' Copyright © 2017 Elsevier Ltd. All rights reserved.

  17. An ASIC implementation of digital front-end electronics for a high resolution PET scanner

    International Nuclear Information System (INIS)

    Newport, D.F.; Young, J.W.

    1993-01-01

    AN Application Specific Integrated Circuit (ASIC) has been designed and fabricated which implements many of the current functions found in the digital front-end electronics for a high resolution Positron Emission Tomography (PET) scanner. The ASIC performs crystal selection, energy qualification, time correction, and event counting functions for block technology high resolution PET scanners. Digitized x and y position, event energy, and time information are used by the ASIC to determine block crystal number, qualify the event based on energy, and correct the event time. In addition, event counting and block dead time calculations are performed for system dead time corrections. A loadable sequencer for controlling the analog front-end electronics is also implemented. The ASIC is implemented in a 37,000 gate, 1.0 micron CMOS gate-array and is capable of handling 4 million events/second while reducing parts count, cost, and power consumption over current board-level designs

  18. Low power frontend ASIC (Anusuchak) for dosimeter using Si-PIN detector

    International Nuclear Information System (INIS)

    Darad, A.; Chandratre, V.B.

    2010-01-01

    A low power ASIC (Anusuchak) for silicon PIN detector signal processing channel designed for pocket dosimeter in 0.35 μm CMOS process. The ASIC contains two channels one for Beta particle and other for Gamma ray. The channel is a CSA integrated with a shaper, gain stage and comparator with total power consumption of 4.6 mW. The ASIC has gain of 12 mV/fC and can be raised to 29 mV/fC without degrading the noise, power or linearity specification of the channel. The channel has a peaking time of 1.2 μs with baseline recovery within 5.3 μs and noise figure of 420 e- at 0 pF. The noise slope is 17 e-/pF. The ASIC is designed for single supply of 3.3 V for which battery is available. (author)

  19. A High-Performance Deformable Mirror with Integrated Driver ASIC for Space Based Active Optics

    Science.gov (United States)

    Shelton, Chris

    Direct imaging of exoplanets is key to fully understanding these systems through spectroscopy and astrometry. The primary impediment to direct imaging of exoplanets is the extremely high brightness ratio between the planet and its parent star. Direct imaging requires a technique for contrast suppression, which include coronagraphs, and nulling interferometers. Deformable mirrors (DMs) are essential to both of these techniques. With space missions in mind, Microscale is developing a novel DM with direct integration of DM and its electronic control functions in a single small envelope. The Application Specific Integrated Circuit (ASIC) is key to the shrinking of the electronic control functions to a size compatible with direct integration with the DM. Through a NASA SBIR project, Microscale, with JPL oversight, has successfully demonstrated a unique deformable mirror (DM) driver ASIC prototype based on an ultra-low power switch architecture. Microscale calls this the Switch-Mode ASIC, or SM-ASIC, and has characterized it for a key set of performance parameters, and has tested its operation with a variety of actuator loads, such as piezo stack and unimorph, and over a wide temperature range. These tests show the SM-ASIC's capability of supporting active optics in correcting aberrations of a telescope in space. Microscale has also developed DMs to go with the SM-ASIC driver. The latest DM version produced uses small piezo stack elements in an 8x8 array, bonded to a novel silicon facesheet structure fabricated monolithically into a polished mirror on one side and mechanical linkage posts that connect to the piezoelectric stack actuators on the other. In this Supporting Technology proposal we propose to further develop the ASIC-DM and have assembled a very capable team to do so. It will be led by JPL, which has considerable expertise with DMs used in Adaptive Optics systems, with high-contrast imaging systems for exoplanet missions, and with designing DM driver

  20. A Serializer ASIC for High Speed Data Transmission in Cryogenic and HiRel Environment

    CERN Document Server

    Liu, T; The ATLAS collaboration

    2010-01-01

    A high speed 16:1 serializer ASIC has been developed using a commercial 0.25 μm silicon-on-sapphire CMOS technology. At room temperature the ASIC operates from 4.0 to 5.7 Gbps with power consumption of 463 mW. The total jitter is 62 ps at the bit error rate of 10-12 at 5 Gbps. A 200-MeV proton beam test indicates that the ASIC is suitable for high energy physics applications. A liquid nitrogen temperature test indicates that the ASIC may be used at cryogenic temperature applications. The reliability of the serializer at liquid nitrogen temperature is to be studied. A 6-lane serializer array with 10 Gbps/lane with redundancy capability is under development.

  1. Wide Temperature Rad-Hard ASIC for Process Control of a Fuel Cell System, Phase II

    Data.gov (United States)

    National Aeronautics and Space Administration — Ridgetop Group developed a top-level design of a rad-hard application-specific integrated circuit (ASIC) for spacecraft power management that is functional over a...

  2. Local ASIC3 modulates pain and disease progression in a rat model of osteoarthritis

    Directory of Open Access Journals (Sweden)

    Izumi Masashi

    2012-08-01

    Full Text Available Abstract Background Recent data have suggested a relationship between acute arthritic pain and acid sensing ion channel 3 (ASIC3 on primary afferent fibers innervating joints. The purpose of this study was to clarify the role of ASIC3 in a rat model of osteoarthritis (OA which is considered a degenerative rather than an inflammatory disease. Methods We induced OA via intra-articular mono-iodoacetate (MIA injection, and evaluated pain-related behaviors including weight bearing measured with an incapacitance tester and paw withdrawal threshold in a von Frey hair test, histology of affected knee joint, and immunohistochemistry of knee joint afferents. We also assessed the effect of ASIC3 selective peptide blocker (APETx2 on pain behavior, disease progression, and ASIC3 expression in knee joint afferents. Results OA rats showed not only weight-bearing pain but also mechanical hyperalgesia outside the knee joint (secondary hyperalgesia. ASIC3 expression in knee joint afferents was significantly upregulated approximately twofold at Day 14. Continuous intra-articular injections of APETx2 inhibited weight distribution asymmetry and secondary hyperalgesia by attenuating ASIC3 upregulation in knee joint afferents. Histology of ipsilateral knee joint showed APETx2 worked chondroprotectively if administered in the early, but not late phase. Conclusions Local ASIC3 immunoreactive nerve is strongly associated with weight-bearing pain and secondary hyperalgesia in MIA-induced OA model. APETx2 inhibited ASIC3 upregulation in knee joint afferents regardless of the time-point of administration. Furthermore, early administration of APETx2 prevented cartilage damage. APETx2 is a novel, promising drug for OA by relieving pain and inhibiting disease progression.

  3. Extracellular acidosis activates ASIC-like channels in freshly isolated cerebral artery smooth muscle cells.

    Science.gov (United States)

    Chung, Wen-Shuo; Farley, Jerry M; Swenson, Alyssa; Barnard, John M; Hamilton, Gina; Chiposi, Rumbidzayi; Drummond, Heather A

    2010-05-01

    Recent studies suggest that certain acid-sensing ion channels (ASIC) are expressed in vascular smooth muscle cells (VSMCs) and are required for VSMC functions. However, electrophysiological evidence of ASIC channels in VSMCs is lacking. The purpose of this study was to test the hypothesis that isolated cerebral artery VSMCs express ASIC-like channels. To address this hypothesis, we used RT-PCR, Western blotting, immunolabeling, and conventional whole cell patch-clamp technique. We found extracellular H(+)-induced inward currents in 46% of cells tested (n = 58 of 126 VSMCs, pH 6.5-5.0). The percentage of responsive cells and the current amplitude increased as the external H(+) concentration increased (pH(6.0), n = 28/65 VSMCs responsive, mean current density = 8.1 +/- 1.2 pA/pF). Extracellular acidosis (pH(6.0)) shifted the whole cell reversal potential toward the Nernst potential of Na(+) (n = 6) and substitution of extracellular Na(+) by N-methyl-d-glucamine abolished the inward current (n = 6), indicating that Na(+) is a major charge carrier. The broad-spectrum ASIC blocker amiloride (20 microM) inhibited proton-induced currents to 16.5 +/- 8.7% of control (n = 6, pH(6.0)). Psalmotoxin 1 (PcTx1), an ASIC1a inhibitor and ASIC1b activator, had mixed effects: PcTx1 either 1) abolished H(+)-induced currents (11% of VSMCs, 5/45), 2) enhanced or promoted activation of H(+)-induced currents (76%, 34/45), or 3) failed to promote H(+) activation in nonresponsive VSMCs (13%, 6/45). These findings suggest that freshly dissociated cerebral artery VSMCs express ASIC-like channels, which are predominantly formed by ASIC1b.

  4. E-beam direct write versus reticle/stepper technology for ASICS in small volume production

    International Nuclear Information System (INIS)

    Wheeler, M.J.

    1987-01-01

    The pros and cons of using e-beam direct writing or reticles plus optical/UV steppers in fast prototyping and the small volume production of ASICs are discussed. The main conclusion is that fast prototyping is best achieved by e-beam direct write whereas small volume production of ASICs is best done via reticles and optical/UV stepping provided that the reticles are made in-house rather than by commercial maskhouses

  5. ASIC1a Deficient Mice Show Unaltered Neurodegeneration in the Subacute MPTP Model of Parkinson Disease.

    Directory of Open Access Journals (Sweden)

    Daniel Komnig

    Full Text Available Inflammation contributes to the death of dopaminergic neurons in Parkinson disease and can be accompanied by acidification of extracellular pH, which may activate acid-sensing ion channels (ASIC. Accordingly, amiloride, a non-selective inhibitor of ASIC, was protective in an acute 1-methyl-4-phenyl-1,2,3,6-tetrahydropyridine (MPTP mouse model of Parkinson disease. To complement these findings we determined MPTP toxicity in mice deficient for ASIC1a, the most common ASIC isoform in neurons. MPTP was applied i.p. in doses of 30 mg per kg on five consecutive days. We determined the number of dopaminergic neurons in the substantia nigra, assayed by stereological counting 14 days after the last MPTP injection, the number of Nissl positive neurons in the substantia nigra, and the concentration of catecholamines in the striatum. There was no difference between ASIC1a-deficient mice and wildtype controls. We are therefore not able to confirm that ASIC1a are involved in MPTP toxicity. The difference might relate to the subacute MPTP model we used, which more closely resembles the pathogenesis of Parkinson disease, or to further targets of amiloride.

  6. Radiation-hard ASICs for optical data transmission in the first phase of the LHC upgrade

    International Nuclear Information System (INIS)

    Gan, K.K.; Buchholz, P.; Kagan, H.P.; Kass, R.D.; Moore, J.R.; Smith, D.S.; Wiese, A.; Ziolkowskic, M.

    2011-01-01

    We have designed two ASICs for possible applications in the optical links of a new layer of the pixel detector to be install inside the ATLAS Pixel detector for the first phase of the LHC luminosity upgrade. The ASICs include a high-speed driver for a VCSEL and a receiver/decoder to decode the signal received at a PIN diode to extract the data and clock. Both ASICs contain 4 channels for operation with a VCSEL or PIN array. The ASICs were designed using a 130 nm CMOS process to enhance the radiation-hardness. We have characterized the fabricated ASICs and the performance of the ASICs is satisfactory. The receiver/decoder properly decodes the bi-phase marked input stream with low PIN current and the driver can operate a VCSEL up to ∼5 Gb/s. The added functionalities are also successful, including redundancy to bypass a broken VCSEL or PIN channel, individual control of VCSEL current, and power-on reset circuit to set all VCSEL currents to a nominal value.

  7. A comparative study of the time performance between NINO and FlexToT ASICs

    International Nuclear Information System (INIS)

    Sarasola, I.; Rato, P.; Marín, J.; Nemallapudi, M.V.; Gundacker, S.; Auffray, E.; Sánchez, D.; Gascón, D.

    2017-01-01

    Universitat de Barcelona (UB) and CIEMAT have designed the FlexToT ASIC for the front-end readout of SiPM-based scintillator detectors. This ASIC is aimed at time of flight (ToF) positron emission tomography (PET) applications. In this work we have evaluated the time performance of the FlexToT v2 ASIC compared to the NINO ASIC, a fast ASIC developped at CERN. NINO electronics give 64 ps sigma for single-photon time resolution (SPTR) and 93 ps FWHM for coincidence time resolution (CTR) with 2 × 2 × 5 mm 3 LSO:Ce,Ca crystals and S13360-3050CS SiPMs. Using the same SiPMs and crystals, the FlexToT v2 ASIC yields 91 ps sigma for SPTR and 123 ps FWHM for CTR. Despite worse time performace than NINO, FlexToT v2 features lower power consumption (11 vs. 27 mW/ch) and linear ToT energy measurement.

  8. ASIC3, an acid-sensing ion channel, is expressed in metaboreceptive sensory neurons

    Directory of Open Access Journals (Sweden)

    Fierro Leonardo

    2005-11-01

    Full Text Available Abstract Background ASIC3, the most sensitive of the acid-sensing ion channels, depolarizes certain rat sensory neurons when lactic acid appears in the extracellular medium. Two functions have been proposed for it: 1 ASIC3 might trigger ischemic pain in heart and muscle; 2 it might contribute to some forms of touch mechanosensation. Here, we used immunocytochemistry, retrograde labelling, and electrophysiology to ask whether the distribution of ASIC3 in rat sensory neurons is consistent with either of these hypotheses. Results Less than half (40% of dorsal root ganglion sensory neurons react with anti-ASIC3, and the population is heterogeneous. They vary widely in cell diameter and express different growth factor receptors: 68% express TrkA, the receptor for nerve growth factor, and 25% express TrkC, the NT3 growth factor receptor. Consistent with a role in muscle nociception, small ( Conclusion Our data indicates that: 1 ASIC3 is expressed in a restricted population of nociceptors and probably in some non-nociceptors; 2 co-expression of ASIC3 and CGRP, and the absence of P2X3, are distinguishing properties of a class of sensory neurons, some of which innervate blood vessels. We suggest that these latter afferents may be muscle metaboreceptors, neurons that sense the metabolic state of muscle and can trigger pain when there is insufficient oxygen.

  9. Effect of a temperature increase in the non-noxious range on proton-evoked ASIC and TRPV1 activity.

    Science.gov (United States)

    Blanchard, Maxime G; Kellenberger, Stephan

    2011-01-01

    Acid-sensing ion channels (ASICs) are neuronal H(+)-gated cation channels, and the transient receptor potential vanilloid 1 channel (TRPV1) is a multimodal cation channel activated by low pH, noxious heat, capsaicin, and voltage. ASICs and TRPV1 are present in sensory neurons. It has been shown that raising the temperature increases TRPV1 and decreases ASIC H(+)-gated current amplitudes. To understand the underlying mechanisms, we have analyzed ASIC and TRPV1 function in a recombinant expression system and in dorsal root ganglion (DRG) neurons at room and physiological temperature. We show that temperature in the range studied does not affect the pH dependence of ASIC and TRPV1 activation. A temperature increase induces, however, a small alkaline shift of the pH dependence of steady-state inactivation of ASIC1a, ASIC1b, and ASIC2a. The decrease in ASIC peak current amplitudes at higher temperatures is likely in part due to the observed accelerated open channel inactivation kinetics and for some ASIC types to the changed pH dependence of steady-state inactivation. The increase in H(+)-activated TRPV1 current at the higher temperature is at least in part due to a hyperpolarizing shift in its voltage dependence. The contribution of TRPV1 relative to ASICs to H(+)-gated currents in DRG neurons increases with higher temperature and acidity. Still, ASICs remain the principal pH sensors of DRG neurons at 35°C in the pH range ≥6.

  10. ANUSANSKAR: a 16 channel frontend electronics (FEE) ASIC targeted for silicon pixel array detector based prototype Alice FOCAL

    International Nuclear Information System (INIS)

    Mukhopadhyay, Sourav; Chandratre, V.B.; Sukhwani, Menka; Pithawa, C.K.; Singaraju, Ramnarayan; Muhuri, Sanjib; Nayak, T.; Khan, S.A.; Saini, Jogendra

    2013-01-01

    ANUSANSKAR is a 16 channel pulse processing ASIC with analog multiplexed output designed in 0.7 um standard CMOS technology with each channel consisting of CSA, Semi Gaussian pulse shaper, DC cancellation and pedestal control, track and hold, output buffer blocks. The ASIC's analog multiplexed output can be read serially in daisy-chain topology. Testing, characterization and validation of ANUSANSKAR ASIC as readout for prototype ALICE forward calorimeter (FOCAL) has been carried out in PS beam line at CERN with up to 6 GeV of pion and electron beam. This paper describes the ANUSANSKAR ASIC along with the experimental results. (author)

  11. Synthesis, structure-activity relationship, and pharmacological profile of analogs of the ASIC-3 inhibitor A-317567.

    Science.gov (United States)

    Kuduk, Scott D; Di Marco, Christina N; Bodmer-Narkevitch, Vera; Cook, Sean P; Cato, Matthew J; Jovanovska, Aneta; Urban, Mark O; Leitl, Michael; Sain, Nova; Liang, Annie; Spencer, Robert H; Kane, Stefanie A; Hartman, George D; Bilodeau, Mark T

    2010-01-20

    The synthesis, structure-activity relationship (SAR), and pharmacological evaluation of analogs of the acid-sensing ion channel (ASIC) inhibitor A-317567 are reported. It was found that the compound with an acetylenic linkage was the most potent ASIC-3 channel blocker. This compound reversed mechanical hypersensitivity in the rat iodoacetate model of osteoarthritis pain, although sedation was noted. Sedation was also observed in ASIC-3 knockout mice, questioning whether sedation and antinociception are mediated via a non-ASIC-3 specific mechanism.

  12. ASIC1a regulates insular long-term depression and is required for the extinction of conditioned taste aversion

    OpenAIRE

    Li, Wei-Guang; Liu, Ming-Gang; Deng, Shining; Liu, Yan-Mei; Shang, Lin; Ding, Jing; Hsu, Tsan-Ting; Jiang, Qin; Li, Ying; Li, Fei; Zhu, Michael Xi; Xu, Tian-Le

    2016-01-01

    Acid-sensing ion channel 1a (ASIC1a) has been shown to play important roles in synaptic plasticity, learning and memory. Here we identify a crucial role for ASIC1a in long-term depression (LTD) at mouse insular synapses. Genetic ablation and pharmacological inhibition of ASIC1a reduced the induction probability of LTD without affecting that of long-term potentiation in the insular cortex. The disruption of ASIC1a also attenuated the extinction of established taste aversion memory without alte...

  13. Technologies for converter topologies

    Science.gov (United States)

    Zhou, Yan; Zhang, Haiyu

    2017-02-28

    In some embodiments of the disclosed inverter topologies, an inverter may include a full bridge LLC resonant converter, a first boost converter, and a second boost converter. In such embodiments, the first and second boost converters operate in an interleaved manner. In other disclosed embodiments, the inverter may include a half-bridge inverter circuit, a resonant circuit, a capacitor divider circuit, and a transformer.

  14. Wavelength converter technology

    DEFF Research Database (Denmark)

    Kloch, Allan; Hansen, Peter Bukhave; Poulsen, Henrik Nørskov

    1999-01-01

    Wavelength conversion is important since it ensures full flexibility of the WDM network layer. Progress in optical wavelength converter technology is reviewed with emphasis on all-optical wavelength converter types based on semiconductor optical amplifiers.......Wavelength conversion is important since it ensures full flexibility of the WDM network layer. Progress in optical wavelength converter technology is reviewed with emphasis on all-optical wavelength converter types based on semiconductor optical amplifiers....

  15. ASIC Readout Circuit Architecture for Large Geiger Photodiode Arrays

    Science.gov (United States)

    Vasile, Stefan; Lipson, Jerold

    2012-01-01

    The objective of this work was to develop a new class of readout integrated circuit (ROIC) arrays to be operated with Geiger avalanche photodiode (GPD) arrays, by integrating multiple functions at the pixel level (smart-pixel or active pixel technology) in 250-nm CMOS (complementary metal oxide semiconductor) processes. In order to pack a maximum of functions within a minimum pixel size, the ROIC array is a full, custom application-specific integrated circuit (ASIC) design using a mixed-signal CMOS process with compact primitive layout cells. The ROIC array was processed to allow assembly in bump-bonding technology with photon-counting infrared detector arrays into 3-D imaging cameras (LADAR). The ROIC architecture was designed to work with either common- anode Si GPD arrays or common-cathode InGaAs GPD arrays. The current ROIC pixel design is hardwired prior to processing one of the two GPD array configurations, and it has the provision to allow soft reconfiguration to either array (to be implemented into the next ROIC array generation). The ROIC pixel architecture implements the Geiger avalanche quenching, bias, reset, and time to digital conversion (TDC) functions in full-digital design, and uses time domain over-sampling (vernier) to allow high temporal resolution at low clock rates, increased data yield, and improved utilization of the laser beam.

  16. VeloPix ASIC development for LHCb VELO upgrade

    CERN Document Server

    van Beuzekom, M; Campbell, M; Collins, P; Gromov, V; Kluit, R; Llopart, X; Poikela, T; Wyllie, K; Zivkovic, V

    2013-01-01

    The upgrade of the LHCb experiment, planned for 2018, will transform the readout of the entire experiment to a triggerless system operating at 40 MHz. All data reduction algorithms will be run in a high level software farm, and will have access to event information from all subdetectors. This approach will give great power and fl exibility in accessing the physics channels of interest in the future, in particular the identi fi cation of fl avour tagged events with displaced vertices. The data acquisition and front end electronics systems require signi fi cant modi fi cation to cope with the enormous throughput of data. For the silicon vertex locator (VELO) a dedicated development is underway for a new ASIC, VeloPix, which will be a derivative of the Timepix/Medipix family of chips. The chip will be radiation hard and be able to cope with pixel hit rates of above 500 MHz, highly non-uniformly distributed over the 2 cm 2 chip area. The chip will incorporate local intelligence in the pixels for time-over-thresho...

  17. VeloPix ASIC development for LHCb VELO upgrade

    International Nuclear Information System (INIS)

    Beuzekom, M. van; Buytaert, J.; Campbell, M.; Collins, P.; Gromov, V.; Kluit, R.; Llopart, X.; Poikela, T.; Wyllie, K.; Zivkovic, V.

    2013-01-01

    The upgrade of the LHCb experiment, planned for 2018, will transform the readout of the entire experiment to a triggerless system operating at 40 MHz. All data reduction algorithms will be run in a high level software farm, and will have access to event information from all subdetectors. This approach will give great power and flexibility in accessing the physics channels of interest in the future, in particular the identification of flavour tagged events with displaced vertices. The data acquisition and front end electronics systems require significant modification to cope with the enormous throughput of data. For the silicon vertex locator (VELO) a dedicated development is underway for a new ASIC, VeloPix, which will be a derivative of the Timepix/Medipix family of chips. The chip will be radiation hard and be able to cope with pixel hit rates of above 500 MHz, highly non-uniformly distributed over the 2 cm 2 chip area. The chip will incorporate local intelligence in the pixels for time-over-threshold measurements, time-stamping and sparse readout. It must in addition be low power, radiation hard, and immune to single event upsets. In order to cope with the datarates and use the pixel area most effectively, an on-chip data compression scheme will integrated. This paper will describe the requirements of the LHCb VELO upgrade, and give an overview of the digital architecture being developed specifically for the readout chip

  18. FRONT-END ASIC FOR A SILICON COMPTON TELESCOPE.

    Energy Technology Data Exchange (ETDEWEB)

    DE GERONIMO,G.; FRIED, J.; FROST, E.; PHLIPS, B.; VERNON, E.; WULF, E.A.

    2007-10-27

    We describe a front-end application specific integrated circuit (ASIC) developed for a silicon Compton telescope. Composed of 32 channels, it reads out signals in both polarities from each side of a Silicon strip sensor, 2 mm thick 27 cm long, characterized by a strip capacitance of 30 pF. Each front-end channel provides low-noise charge amplification, shaping with a stabilized baseline, discrimination, and peak detection with an analog memory. The channels can process events simultaneously, and the read out is sparsified. The charge amplifier makes uses a dual-cascode configuration and dual-polarity adaptive reset, The low-hysteresis discriminator and the multi-phase peak detector process signals with a dynamic range in excess of four hundred. An equivalent noise charge (ENC) below 200 electrons was measured at 30 pF, with a slope of about 4.5 electrons/pF at a peaking time of 4 {micro}s. With a total dissipated power of 5 mW the channel covers an energy range up to 3.2 MeV.

  19. A time-based front-end ASIC for the silicon micro strip sensors of the P-bar ANDA Micro Vertex Detector

    International Nuclear Information System (INIS)

    Pietro, V. Di; Brinkmann, K.-Th.; Riccardi, A.; Ritman, J.; Stockmanns, T.; Zambanini, A.; Rivetti, A.; Rolo, M.D.

    2016-01-01

    The P-bar ANDA (Antiproton Annihilation at Darmstadt) experiment foresees many detectors for tracking, particle identification and calorimetry. Among them, the innermost is the MVD (Micro Vertex Detector) responsible for a precise tracking and the reconstruction of secondary vertices. This detector will be built from both hybrid pixel (two inner barrels and six forward disks) and double-sided micro strip (two outer barrels and outer rim of the last two disks) silicon sensors. A time-based approach has been chosen for the readout ASIC of the strip sensors. The PASTA ( P-bar ANDA Strip ASIC) chip aims at high resolution time-stamping and charge information through the Time over Threshold (ToT) technique. It benefits from a Time to Digital Converter (TDC) allowing a time bin width down to 50 ps. The analog front-end was designed to serve both n-type and p-type strips and the performed simulations show remarkable performances in terms of linearity and electronic noise. The TDC consists of an analog interpolator, a digital local controller, and a digital global controller as the common back-end for all of the 64 channels

  20. A time-based front-end ASIC for the silicon micro strip sensors of the bar PANDA Micro Vertex Detector

    Science.gov (United States)

    Di Pietro, V.; Brinkmann, K.-Th.; Riccardi, A.; Ritman, J.; Rivetti, A.; Rolo, M. D.; Stockmanns, T.; Zambanini, A.

    2016-03-01

    The bar PANDA (Antiproton Annihilation at Darmstadt) experiment foresees many detectors for tracking, particle identification and calorimetry. Among them, the innermost is the MVD (Micro Vertex Detector) responsible for a precise tracking and the reconstruction of secondary vertices. This detector will be built from both hybrid pixel (two inner barrels and six forward disks) and double-sided micro strip (two outer barrels and outer rim of the last two disks) silicon sensors. A time-based approach has been chosen for the readout ASIC of the strip sensors. The PASTA (bar PANDA Strip ASIC) chip aims at high resolution time-stamping and charge information through the Time over Threshold (ToT) technique. It benefits from a Time to Digital Converter (TDC) allowing a time bin width down to 50 ps. The analog front-end was designed to serve both n-type and p-type strips and the performed simulations show remarkable performances in terms of linearity and electronic noise. The TDC consists of an analog interpolator, a digital local controller, and a digital global controller as the common back-end for all of the 64 channels.

  1. ChromAIX2: A large area, high count-rate energy-resolving photon counting ASIC for a Spectral CT Prototype

    Science.gov (United States)

    Steadman, Roger; Herrmann, Christoph; Livne, Amir

    2017-08-01

    Spectral CT based on energy-resolving photon counting detectors is expected to deliver additional diagnostic value at a lower dose than current state-of-the-art CT [1]. The capability of simultaneously providing a number of spectrally distinct measurements not only allows distinguishing between photo-electric and Compton interactions but also discriminating contrast agents that exhibit a K-edge discontinuity in the absorption spectrum, referred to as K-edge Imaging [2]. Such detectors are based on direct converting sensors (e.g. CdTe or CdZnTe) and high-rate photon counting electronics. To support the development of Spectral CT and show the feasibility of obtaining rates exceeding 10 Mcps/pixel (Poissonian observed count-rate), the ChromAIX ASIC has been previously reported showing 13.5 Mcps/pixel (150 Mcps/mm2 incident) [3]. The ChromAIX has been improved to offer the possibility of a large area coverage detector, and increased overall performance. The new ASIC is called ChromAIX2, and delivers count-rates exceeding 15 Mcps/pixel with an rms-noise performance of approximately 260 e-. It has an isotropic pixel pitch of 500 μm in an array of 22×32 pixels and is tile-able on three of its sides. The pixel topology consists of a two stage amplifier (CSA and Shaper) and a number of test features allowing to thoroughly characterize the ASIC without a sensor. A total of 5 independent thresholds are also available within each pixel, allowing to acquire 5 spectrally distinct measurements simultaneously. The ASIC also incorporates a baseline restorer to eliminate excess currents induced by the sensor (e.g. dark current and low frequency drifts) which would otherwise cause an energy estimation error. In this paper we report on the inherent electrical performance of the ChromAXI2 as well as measurements obtained with CZT (CdZnTe)/CdTe sensors and X-rays and radioactive sources.

  2. Design and screening of ASIC inhibitors based on aromatic diamidines for combating neurological disorders.

    Science.gov (United States)

    Chen, Xuanmao; Orser, Beverley A; MacDonald, John F

    2010-12-01

    Acid sensing ion channels (ASICs) are implicated in various brain functions including learning and memory and are involved in a number of neurological disorders such as pain, ischemic stroke, depression, and multiple sclerosis. We have recently defined ASICs as one of receptor targets of aromatic diamidines in neurons. Aromatic diamidines are DNA-binding agents and have long been used in the treatment of leishmaniasis, trypanosomiasis, pneumocystis pneumonia and babesiosis. Moreover, some aromatic diamidines are used as skin-care and baby products and others have potential to suppress tumor growth or to combat malaria. A large number of aromatic diamidines or analogs have been synthesized. Many efforts are being made to optimize the therapeutic spectrum of aromatic diamidines, i.e. to reduce toxicity, increase oral bioavailability and enhance their penetration of the blood-brain barrier. Aromatic diamidines therefore provide a shortcut of screening for selective ASIC inhibitors with therapeutic potential. Intriguingly nafamostat, a protease inhibitor for treating acute pancreatitis, also inhibits ASIC activities. Aromatic diamidines and nafamostat have many similarities although they belong to distinct classes of medicinal agents for curing different diseases. Here we delineate background, clinical application and drug development of aromatic diamidines that could facilitate the screening for selective ASIC inhibitors for research purposes. Further studies may lead to a drug with therapeutic value and extend the therapeutic scope of aromatic diamidines to combat neurological diseases. Copyright © 2010 Elsevier B.V. All rights reserved.

  3. A design of a valid signal selecting and position decoding ASIC for PET using silicon photomultipliers

    International Nuclear Information System (INIS)

    Cho, M.; Lim, K.-T.; Kim, J.; Lee, C.; Cho, G.; Kim, H.; Yeom, J.-Y.; Choi, H.

    2017-01-01

    In most cases, a PET system has numerous electrical components and channel circuits and thus it would rather be a bulky product. Also, most existing systems receive analog signals from detectors which make them vulnerable to signal distortions. For these reasons, channel reduction techniques are important. In this work, an ASIC for PET module is being proposed. An ASIC chip for 16 PET detector channels, VSSPDC, has been designed and simulated. The main function of the chip is 16-to-1 channel reduction, i.e., finding the position of only the valid signals, signal timing, and magnitudes in all 16 channels at every recorded event. The ASIC comprises four of 4-channel modules and a 2 nd 4-to-1 router. A single channel module comprises a transimpedance amplifier for the silicon photomultipliers, dual comparators with high and low level references, and a logic circuitry. While the high level reference was used to test the validity of the signal, the low level reference was used for the timing. The 1-channel module of the ASIC produced an energy pulse by time-over-threshold method and it also produced a time pulse with a fixed delayed time. Since the ASIC chip outputs only a few digital pulses and does not require an external clock, it has an advantage over noise properties. The cadence simulation showed the good performance of the chip as designed.

  4. Atomic force microscopy imaging reveals the formation of ASIC/ENaC cross-clade ion channels

    International Nuclear Information System (INIS)

    Jeggle, Pia; Smith, Ewan St. J.; Stewart, Andrew P.; Haerteis, Silke; Korbmacher, Christoph; Edwardson, J. Michael

    2015-01-01

    ASIC and ENaC are co-expressed in various cell types, and there is evidence for a close association between them. Here, we used atomic force microscopy (AFM) to determine whether ASIC1a and ENaC subunits are able to form cross-clade hybrid ion channels. ASIC1a and ENaC could be co-isolated from detergent extracts of tsA 201 cells co-expressing the two subunits. Isolated proteins were incubated with antibodies against ENaC and Fab fragments against ASIC1a. AFM imaging revealed proteins that were decorated by both an antibody and a Fab fragment with an angle of ∼120° between them, indicating the formation of ASIC1a/ENaC heterotrimers. - Highlights: • There is evidence for a close association between ASIC and ENaC. • We used AFM to test whether ASIC1a and ENaC subunits form cross-clade ion channels. • Isolated proteins were incubated with subunit-specific antibodies and Fab fragments. • Some proteins were doubly decorated at ∼120° by an antibody and a Fab fragment. • Our results indicate the formation of ASIC1a/ENaC heterotrimers

  5. ASIC1a regulates insular long-term depression and is required for the extinction of conditioned taste aversion.

    Science.gov (United States)

    Li, Wei-Guang; Liu, Ming-Gang; Deng, Shining; Liu, Yan-Mei; Shang, Lin; Ding, Jing; Hsu, Tsan-Ting; Jiang, Qin; Li, Ying; Li, Fei; Zhu, Michael Xi; Xu, Tian-Le

    2016-12-07

    Acid-sensing ion channel 1a (ASIC1a) has been shown to play important roles in synaptic plasticity, learning and memory. Here we identify a crucial role for ASIC1a in long-term depression (LTD) at mouse insular synapses. Genetic ablation and pharmacological inhibition of ASIC1a reduced the induction probability of LTD without affecting that of long-term potentiation in the insular cortex. The disruption of ASIC1a also attenuated the extinction of established taste aversion memory without altering the initial associative taste learning or its long-term retention. Extinction of taste aversive memory led to the reduced insular synaptic efficacy, which precluded further LTD induction. The impaired LTD and extinction learning in ASIC1a null mice were restored by virus-mediated expression of wild-type ASIC1a, but not its ion-impermeable mutant, in the insular cortices. Our data demonstrate the involvement of an ASIC1a-mediated insular synaptic depression mechanism in extinction learning, which raises the possibility of targeting ASIC1a to manage adaptive behaviours.

  6. Atomic force microscopy imaging reveals the formation of ASIC/ENaC cross-clade ion channels

    Energy Technology Data Exchange (ETDEWEB)

    Jeggle, Pia; Smith, Ewan St. J.; Stewart, Andrew P. [Department of Pharmacology, University of Cambridge, Tennis Court Road, Cambridge CB2 1PD (United Kingdom); Haerteis, Silke; Korbmacher, Christoph [Institut für Zelluläre und Molekulare Physiologie, Friedrich-Alexander-Universität Erlangen-Nürnberg, Waldstrasse 6, 91054 Erlangen (Germany); Edwardson, J. Michael, E-mail: jme1000@cam.ac.uk [Department of Pharmacology, University of Cambridge, Tennis Court Road, Cambridge CB2 1PD (United Kingdom)

    2015-08-14

    ASIC and ENaC are co-expressed in various cell types, and there is evidence for a close association between them. Here, we used atomic force microscopy (AFM) to determine whether ASIC1a and ENaC subunits are able to form cross-clade hybrid ion channels. ASIC1a and ENaC could be co-isolated from detergent extracts of tsA 201 cells co-expressing the two subunits. Isolated proteins were incubated with antibodies against ENaC and Fab fragments against ASIC1a. AFM imaging revealed proteins that were decorated by both an antibody and a Fab fragment with an angle of ∼120° between them, indicating the formation of ASIC1a/ENaC heterotrimers. - Highlights: • There is evidence for a close association between ASIC and ENaC. • We used AFM to test whether ASIC1a and ENaC subunits form cross-clade ion channels. • Isolated proteins were incubated with subunit-specific antibodies and Fab fragments. • Some proteins were doubly decorated at ∼120° by an antibody and a Fab fragment. • Our results indicate the formation of ASIC1a/ENaC heterotrimers.

  7. Optical data transmission ASICs for the high-luminosity LHC (HL-LHC) experiments

    International Nuclear Information System (INIS)

    Li, X; Huang, G; Sun, X; Liu, G; Deng, B; Gong, D; Guo, D; Liu, C; Liu, T; Xiang, A C; Ye, J; Zhao, X; Chen, J; You, Y; He, M; Hou, S; Teng, P-K; Jin, G; Liang, H; Liang, F

    2014-01-01

    We present the design and test results of two optical data transmission ASICs for the High-Luminosity LHC (HL-LHC) experiments. These ASICs include a two-channel serializer (LOCs2) and a single-channel Vertical Cavity Surface Emitting Laser (VCSEL) driver (LOCld1V2). Both ASICs are fabricated in a commercial 0.25-μm Silicon-on-Sapphire (SoS) CMOS technology and operate at a data rate up to 8 Gbps per channel. The power consumption of LOCs2 and LOCld1V2 are 1.25 W and 0.27 W at 8-Gbps data rate, respectively. LOCld1V2 has been verified meeting the radiation-tolerance requirements for HL-LHC experiments

  8. The CaloRIC ASIC: Signal Processing for High Granularity Calorimeter

    International Nuclear Information System (INIS)

    Royer, L; Manen, S; Soumpholphakdy, X; Bonnard, J; Gay, P

    2013-01-01

    A readout ASIC called CaloRIC, has been developed to fulfil the signal processing requirements for the Silicon-Tungsten (Si-W) electromagnetic calorimeter of the International Linear Collider (ILC). This ASIC performs the complete processing of the signal delivered by the Si-PIN diode of the detector: charge sensitive amplification, shaping, analog memorization and digitization. Measurements show a global integral non-linearity better than 0.2% for low energy particles, and limited to 2% for high energy particles. The measured Equivalent Noise Charge (ENC) is evaluated at 0.6 fC, which corresponds to 1/6 times the signal released by a Minimum Ionizing Particle (MIP). With the timing sequence of the ILC, the power consumption of the complete channel is evaluated at 43 μW using a power pulsing. A new ASIC (CaloRIC 4 ch) with four improved readout channels has been designed and is ready for manufacturing.

  9. A Low-Power ASIC Signal Processor for a Vestibular Prosthesis.

    Science.gov (United States)

    Töreyin, Hakan; Bhatti, Pamela T

    2016-06-01

    A low-power ASIC signal processor for a vestibular prosthesis (VP) is reported. Fabricated with TI 0.35 μm CMOS technology and designed to interface with implanted inertial sensors, the digitally assisted analog signal processor operates extensively in the CMOS subthreshold region. During its operation the ASIC encodes head motion signals captured by the inertial sensors as electrical pulses ultimately targeted for in-vivo stimulation of vestibular nerve fibers. To achieve this, the ASIC implements a coordinate system transformation to correct for misalignment between natural sensors and implanted inertial sensors. It also mimics the frequency response characteristics and frequency encoding mappings of angular and linear head motions observed at the peripheral sense organs, semicircular canals and otolith. Overall the design occupies an area of 6.22 mm (2) and consumes 1.24 mW when supplied with ± 1.6 V.

  10. A 64-channel readout ASIC for nanowire biosensor array with electrical calibration scheme.

    Science.gov (United States)

    Chai, Kevin T C; Choe, Kunil; Bernal, Olivier D; Gopalakrishnan, Pradeep K; Zhang, Guo-Jun; Kang, Tae Goo; Je, Minkyu

    2010-01-01

    A 1.8-mW, 18.5-mm(2) 64-channel current readout ASIC was implemented in 0.18-µm CMOS together with a new calibration scheme for silicon nanowire biosensor arrays. The ASIC consists of 64 channels of dedicated readout and conditioning circuits which incorporate correlated double sampling scheme to reduce the effect of 1/f noise and offset from the analog front-end. The ASIC provides a 10-bit digital output with a sampling rate of 300 S/s whilst achieving a minimum resolution of 7 pA(rms). A new electrical calibration method was introduced to mitigate the issue of large variations in the nano-scale sensor device parameters and optimize the sensor sensitivity. The experimental results show that the proposed calibration technique improved the sensitivity by 2 to 10 times and reduced the variation between dataset by 9 times.

  11. Femtosecond Resolution Timing in Multi-GS/s Waveform Digitizing ASICs

    Science.gov (United States)

    Orel, Peter; Varner, Gary S.

    2017-07-01

    A waveform digitizer with high-resolution timing provides with the possibility of a novel approach to vertex detectors for high-luminosity particle colliders. Present efforts are centered on the development of an application specific integrated circuit (ASIC) intended to measure signal arrival times with timing resolution in the range of 100 fs or less. The design of such an ASIC requires very good understanding of the effects that impact the timing resolution. This paper presents the simulation results that clearly identify and quantify the sources of error and the underlying coupling mechanisms. In addition, a synthetic waveform generator, developed solely for this purpose, is presented and validated through the measurement results. Crucial knowledge, insights, and confidence have been gained for the development of the ASIC or any other fast, wideband RF systems that aim to achieve such performance.

  12. Application specific integrated circuit (ASIC) readout technologies for future ion beam analytical instruments

    Energy Technology Data Exchange (ETDEWEB)

    Whitlow, Harry J. E-mail: harry_j.whitlow@nuclear.lu.se

    2000-03-01

    New possibilities for ion beam analysis (IBA) are afforded by recent developments in detector technology which facilitate the parallel collection of data from a large number of channels. Application specific integrated circuit (ASIC) technologies, which have been widely employed for multi-channel readout systems in nuclear and particle physics, are more net-cost effective (160/channel for 1000 channels) and a more rational solution for readout of a large number of channels than afforded by conventional electronics. Based on results from existing and on-going chip designs, the possibilities and issues of ASIC readout technology are considered from the IBA viewpoint. Consideration is given to readout chip architecture and how the stringent resolution, linearity and stability requirements for IBA may be met. In addition the implications of the restrictions imposed by ASIC technology are discussed.

  13. Readout ASICs and Electronics for the 144-channel HAPDs for the Aerogel RICH at Belle II

    Science.gov (United States)

    Nishida, S.; Adachi, I.; Ikeda, H.; Hara, K.; Iijima, T.; Iwata, S.; Korpar, S.; Križan, P.; Kuroda, E.; Pestotnik, R.; Seljak, A.; Sumiyoshi, T.; Takagaki, H.

    The particle identification (PID) device in the endcap of the Belle detector will be upgraded to a ring imaging Cherenkov counter (RICH) using aerogel as a radiator at the Belle II experiment. We develop the electronics to read out the 70,000 channels of hit information from the 144-channel hybrid avalanche photodetectors (HAPD), of the aerogel RICH detector. A readout ASIC is developed to digitize the HAPD signals, and was used in a beam test with the prototype detector. The performance and plan of the ASIC is reported in this study. We have also designed the readout electronics for the aerogel RICH, which consist of front-end boards with the ASICs merger boards to collect data from the front-end boards. A front-end board that fits in the actual available space for the aerogel RICH electronics was produced.

  14. Test beam analysis of ultra-thin hybrid pixel detector assemblies with Timepix readout ASICs

    CERN Document Server

    Alipour Tehrani, Niloufar; Dannheim, Dominik; Firu, Elena; Kulis, Szymon; Redford, Sophie; Sicking, Eva

    2016-01-01

    The requirements for the vertex detector at the proposed Compact Linear Collider imply a very small material budget: less than 0.2% of a radiation length per detection layer including services and mechanical supports. We present here a study using Timepix readout ASICs hybridised to pixel sensors of 50 − 500 μm thickness, including assemblies with 100 μm thick sensors bonded to thinned 100μm thick ASICs. Sensors from three producers (Advacam, Micron Semiconductor Ltd, Canberra) with different edge termination technologies (active edge, slim edge) were bonded to Timepix ASICs. These devices were characterised with the EUDET telescope at the DESY II test beam using 5.6 GeV electrons. Their performance for the detection and tracking of minimum ionising particles was evaluated in terms of charge sharing, detection efficiency, single-point resolution and energy deposition.

  15. ITER convertible blanket evaluation

    International Nuclear Information System (INIS)

    Wong, C.P.C.; Cheng, E.

    1995-01-01

    Proposed International Thermonuclear Experimental Reactor (ITER) convertible blankets were reviewed. Key design difficulties were identified. A new particle filter concept is introduced and key performance parameters estimated. Results show that this particle filter concept can satisfy all of the convertible blanket design requirements except the generic issue of Be blanket lifetime. If the convertible blanket is an acceptable approach for ITER operation, this particle filter option should be a strong candidate

  16. Asic3(-/- female mice with hearing deficit affects social development of pups.

    Directory of Open Access Journals (Sweden)

    Wei-Li Wu

    Full Text Available BACKGROUND: Infant crying is an important cue for mothers to respond adequately. Inappropriate response to infant crying can hinder social development in infants. In rodents, the pup-mother interaction largely depends on pup's calls. Mouse pups emit high frequency to ultrasonic vocalization (2-90 kHz to communicate with their dam for maternal care. However, little is known about how the maternal response to infant crying or pup calls affects social development over the long term. METHODOLOGY/PRINCIPAL FINDINGS: Here we used mice lacking acid-sensing ion channel 3 (Asic3(-/- to create a hearing deficit to probe the effect of caregiver hearing on maternal care and adolescent social development. Female Asic3(-/- mice showed elevated hearing thresholds for low to ultrasonic frequency (4-32 kHz on auditory brain stem response, which thus hindered their response to their pups' wriggling calls and ultrasonic vocalization, as well as their retrieval of pups. In adolescence, pups reared by Asic3(-/- mice showed a social deficit in juvenile social behaviors as compared with those reared by wild-type or heterozygous dams. The social-deficit phenotype in juvenile mice reared by Asic3(-/- mice was associated with the reduced serotonin transmission of the brain. However, Asic3(-/- pups cross-fostered to wild-type dams showed rescued social deficit. CONCLUSIONS/SIGNIFICANCE: Inadequate response to pups' calls as a result of ASIC3-dependent hearing loss confers maternal deficits in caregivers and social development deficits in their young.

  17. ARTROC—a readout ASIC for GEM-based full-field XRF imaging system

    Science.gov (United States)

    Fiutowski, T.; Koperny, S.; Łach, B.; Mindur, B.; Świentek, K.; Wiącek, P.; Dąbrowski, W.

    2017-12-01

    In the paper we report on development of an Application Specific Integrated Circuit (ASIC), called ARTROC, being part of a full-field X-ray fluorescence spectroscopy (XRF) imaging system equipped with a standard three stage Gas Electron Multiplier (GEM) detector of 10×10 cm2 area. The ARTROC consists of 64 independent channels, allowing for simultaneous recording of the amplitudes (energy sub-channel) and time stamps (timing sub-channel) of incoming signals. Thanks to the implemented token-based read out of derandomizing buffers, the ASIC also provides data sparsification and full zero suppression. Reconstruction of the hit positions is performed in an external data acquisition system by matching the time stamps of signals recorded in X- and Y-strips. The amplitude information is used for centre of gravity finding in clusters of signals on neighbouring strips belonging to the same detection events. The ASIC could work in one of six gain modes and one of two speed modes. In a slower mode the maximum count rate per channel is 105/s while in a faster mode it is three times higher. The ARTROC comprises also input protection circuits against possible random discharges inside active detector volume, so it can be used without any additional input components. The ASIC has been designed in 350 nm CMOS process. The basic functionality and parameters have been evaluated using the testability functions implemented in the ASIC design. The ASIC has been also tested in a fully equipped GEM detector set-up with X-rays source.

  18. Atomic force microscopy imaging reveals the formation of ASIC/ENaC cross-clade ion channels.

    Science.gov (United States)

    Jeggle, Pia; Smith, Ewan St J; Stewart, Andrew P; Haerteis, Silke; Korbmacher, Christoph; Edwardson, J Michael

    2015-08-14

    ASIC and ENaC are co-expressed in various cell types, and there is evidence for a close association between them. Here, we used atomic force microscopy (AFM) to determine whether ASIC1a and ENaC subunits are able to form cross-clade hybrid ion channels. ASIC1a and ENaC could be co-isolated from detergent extracts of tsA 201 cells co-expressing the two subunits. Isolated proteins were incubated with antibodies against ENaC and Fab fragments against ASIC1a. AFM imaging revealed proteins that were decorated by both an antibody and a Fab fragment with an angle of ∼120° between them, indicating the formation of ASIC1a/ENaC heterotrimers. Copyright © 2015 Elsevier Inc. All rights reserved.

  19. A low noise ASIC for two dimensional neutron gas detector with performance of high spatial resolution (Contract research)

    International Nuclear Information System (INIS)

    Yamagishi, Hideshi; Toh, Kentaro; Nakamura, Tatsuya; Sakasai, Kaoru; Soyama, Kazuhiko

    2012-02-01

    An ASD-ASIC (Amplifier-Shaper-Discriminator ASIC) with fast response and low noise performances has been designed for two-dimensional position sensitive neutron gas detectors (InSPaD). The InSPaD is a 2D neutron detector system with 3 He gas and provides a high spatial resolution by making distinction between proton and triton particles generated in the gas chamber. The new ASD-ASIC is required to have very low noise, a wide dynamic range, good output linearity and high counting rate. The new ASD-ASIC has been designed by using CMOS and consisted of 64-channel ASDs, a 16-channel multiplexer with LVTTL drivers and sum amplifier system for summing all analog signals. The performances were evaluated by the Spice simulation. It was confirmed that the new ASD-ASIC had very low noise performance, wide dynamic range and fast signal processing functions. (author)

  20. Power converters definitions, classification and converter topologies

    CERN Document Server

    Bordry, Frederick

    2006-01-01

    This paper introduces power conversion principles and defines the terminology. The concepts of sources and switches are defined and classified. From the basic laws of source interconnections, a generic method of power converter synthesis is presented. Some examples illustrate this systematic method. Finally, the notions of commutation cell and soft commutation are introduced and discussed.

  1. A 128-channel event driven readout ASIC for the R3B tracker

    International Nuclear Information System (INIS)

    Jones, L.; Bell, S.; Morrissey, Q.; Prydderch, M.; Church, I.; Lazarus, I.; Kogimtzis, M.; Pucknell, V.; Labiche, M.; Thornhill, J.; Borri, M.

    2016-01-01

    R 3 B is a detector with high efficiency, acceptance, and resolution for kinematically complete measurements of reactions with high-energy radioactive beams. Detectors track and identify radioactive beams into and out of a reaction target. Three layers of double-sided stereoscopic silicon strips form the tracker detector which must provide precise tracking and vertex determination and in addition include energy and multiplicity measurements. The R 3 B ASIC has been manufactured and is intended for processing and digitising signals generated by ionising particles passing through the tracker. The ASIC processes signals and provides spatial, energy and time measurements

  2. A Low-Power Correlator ASIC for Arrays with Many Antennas

    Science.gov (United States)

    D'Addario, Larry R.; Wang, Douglas

    2016-01-01

    We report the design of a new application-specific integrated circuit (ASIC) for use in radio telescope correlators. It supports the construction of correlators for an arbitrarily large number of signals. The ASIC uses an intrinsically low-power architecture along with design techniques and a process that together result in unprecedentedly low power consumption. The design is flexible in that it can support telescopes with almost any number of antennas N. It is intended for use in an "FX" correlator, where a uniform filter bank breaks each signal into separate frequency channels prior to correlation.

  3. Integrated input protection against discharges for Micro Pattern Gas Detectors readout ASICs

    International Nuclear Information System (INIS)

    Fiutowski, T.; Dąbrowski, W.; Koperny, S.; Wiącek, P.

    2017-01-01

    Immunity against possible random discharges inside active detector volume of MPGDs is one of the key aspects that should be addressed in the design of the front-end electronics. This issue becomes particularly critical for systems with high channel counts and high density readout employing the front-end electronics built as multichannel ASICs implemented in modern CMOS technologies, for which the breakdown voltages are in the range of a few Volts. The paper presents the design of various input protection structures integrated in the ASIC manufactured in a 350 nm CMOS process and test results using an electrical circuit to mimic discharges in the detectors.

  4. Performance study of SKIROC2/A ASIC for ILD Si-W ECAL

    Science.gov (United States)

    Suehara, T.; Sekiya, I.; Callier, S.; Balagura, V.; Boudry, V.; Brient, J.-C.; de la Taille, C.; Kawagoe, K.; Irles, A.; Magniette, F.; Nanni, J.; Pöschl, R.; Yoshioka, T.

    2018-03-01

    The ILD Si-W ECAL is a sampling calorimeter with tungsten absorber and highly segmented silicon layers for the International Large Detector (ILD), one of the two detector concepts for the International Linear Collider. SKIROC2 is an ASIC for the ILD Si-W ECAL. To investigate the issues found in prototype detectors, we prepared dedicated ASIC evaluation boards with either BGA sockets or directly soldered SKIROC2. We report a performance study with the evaluation boards, including signal-to-noise ratio and TDC performance with comparing SKIROC2 and an updated version, SKIROC2A.

  5. Design and characterization of the readout ASIC for the BESIII CGEM detector

    CERN Document Server

    Cossio, Fabio; Bugalho, Ricardo; Chai, Junying; Cheng, Weishuai; Da Rocha Rolo, Manuel Dionisio; Di Francesco, Agostino; Greco, Michela; Leng, Chongyang; Li, Huaishen; Maggiora, Marco; Marcello, Simonetta; Mignone, Marco; Rivetti, Angelo; Varela, Joao; Wheadon, Richard

    2018-01-01

    TIGER (Turin Integrated Gem Electronics for Readout) is a mixed-mode ASIC for the readout of signals from CGEM (Cylindrical Gas Electron Multiplier) detector in the upgraded inner tracker of the BESIII experiment, carried out at BEPCII in Beijing. The ASIC includes 64 channels, each of which features a dual-branch architecture optimized for timing and energy measurement. The input signal time-of-arrival and charge measurement is provided by low-power TDCs, based on analogue interpolation techniques, and Wilkinson ADCs, with a fully-digital output. The silicon results of TIGER first prototype are presented showing its full functionality.

  6. Cryogenic and radiation hard ASIC design for large format NIR/SWIR detector

    Science.gov (United States)

    Gao, Peng; Dupont, Benoit; Dierickx, Bart; Müller, Eric; Verbruggen, Geert; Gielis, Stijn; Valvekens, Ramses

    2014-10-01

    An ASIC is developed to control and data quantization for large format NIR/SWIR detector arrays. Both cryogenic and space radiation environment issue are considered during the design. Therefore it can be integrated in the cryogenic chamber, which reduces significantly the vast amount of long wires going in and out the cryogenic chamber, i.e. benefits EMI and noise concerns, as well as the power consumption of cooling system and interfacing circuits. In this paper, we will describe the development of this prototype ASIC for image sensor driving and signal processing as well as the testing in both room and cryogenic temperature.

  7. Cryogenic and radiation-hard asic for interfacing large format NIR/SWIR detector arrays

    Science.gov (United States)

    Gao, Peng; Dupont, Benoit; Dierickx, Bart; Müller, Eric; Verbruggen, Geert; Gielis, Stijn; Valvekens, Ramses

    2017-11-01

    For scientific and earth observation space missions, weight and power consumption is usually a critical factor. In order to obtain better vehicle integration, efficiency and controllability for large format NIR/SWIR detector arrays, a prototype ASIC is designed. It performs multiple detector array interfacing, power regulation and data acquisition operations inside the cryogenic chambers. Both operation commands and imaging data are communicated via the SpaceWire interface which will significantly reduce the number of wire goes in and out the cryogenic chamber. This "ASIC" prototype is realized in 0.18um CMOS technology and is designed for radiation hardness.

  8. Channel control ASIC for the CMS hadron calorimeter front end readout module

    International Nuclear Information System (INIS)

    Ray Yarema et al.

    2002-01-01

    The Channel Control ASIC (CCA) is used along with a custom Charge Integrator and Encoder (QIE) ASIC to digitize signals from the hybrid photo diodes (HPDs) and photomultiplier tubes (PMTs) in the CMS hadron calorimeter. The CCA sits between the QIE and the data acquisition system. All digital signals to and from the QIE pass through the CCA chip. One CCA chip interfaces with two QIE channels. The CCA provides individually delayed clocks to each of the QIE chips in addition to various control signals. The QIE sends digitized PMT or HPD signals and time slice information to the CCA, which sends the data to the data acquisition system through an optical link

  9. Cascaded resonant bridge converters

    Science.gov (United States)

    Stuart, Thomas A. (Inventor)

    1989-01-01

    A converter for converting a low voltage direct current power source to a higher voltage, high frequency alternating current output for use in an electrical system where it is desired to use low weight cables and other circuit elements. The converter has a first stage series resonant (Schwarz) converter which converts the direct current power source to an alternating current by means of switching elements that are operated by a variable frequency voltage regulator, a transformer to step up the voltage of the alternating current, and a rectifier bridge to convert the alternating current to a direct current first stage output. The converter further has a second stage series resonant (Schwarz) converter which is connected in series to the first stage converter to receive its direct current output and convert it to a second stage high frequency alternating current output by means of switching elements that are operated by a fixed frequency oscillator. The voltage of the second stage output is controlled at a relatively constant value by controlling the first stage output voltage, which is accomplished by controlling the frequency of the first stage variable frequency voltage controller in response to second stage voltage. Fault tolerance in the event of a load short circuit is provided by making the operation of the first stage variable frequency voltage controller responsive to first and second stage current limiting devices. The second stage output is connected to a rectifier bridge whose output is connected to the input of the second stage to provide good regulation of output voltage wave form at low system loads.

  10. FRONT-END ASIC FOR HIGH RESOLUTION X-RAY SPECTROMETERS

    International Nuclear Information System (INIS)

    DE GERONIMO, G.; CHEN, W.; FRIED, J.; LI, Z.; PINELLI, D.A.; REHAK, P.; VERNON, E.; GASKIN, J.A.; RAMSEY, B.D.; ANELLI, G.

    2007-01-01

    We present an application specific integrated circuit (ASIC) for high-resolution x-ray spectrometers. The ASIC is designed to read out signals from a pixelated silicon drift detector (SDD). Each hexagonal pixel has an area of 15 mmz and an anode capacitance of less than 100 fF. There is no integrated Field Effect transistor (FET) in the pixel, rather, the readout is done by wirebonding the anodes to the inputs of the ASIC. The ASIC provides 14 channels of low-noise charge amplification, high-order shaping with baseline stabilization, and peak detection with analog memory. The readout is sparse and based on low voltage differential signaling. An interposer provides all the interconnections required to bias and operate the system. The channel dissipates 1.6 mW. The complete 14-pixel unit covers an area of 210 mm 2 , dissipates 12 mW cm -2 , and can be tiled to cover an arbitrarily large detection area. We measured a preliminary resolution of 172 eV at -35 C on the 6 keV peak of a 55 Fe source

  11. An Implantable Versatile Electrode-Driving ASIC for Chronic Epidural Stimulation in Rats.

    Science.gov (United States)

    Giagka, Vasiliki; Eder, Clemens; Donaldson, Nick; Demosthenous, Andreas

    2015-06-01

    This paper presents the design and testing of an electrode driving application specific integrated circuit (ASIC) intended for epidural spinal cord electrical stimulation in rats. The ASIC can deliver up to 1 mA fully programmable monophasic or biphasic stimulus current pulses, to 13 electrodes selected in any possible configuration. It also supports interleaved stimulation. Communication is achieved via only 3 wires. The current source and the control of the stimulation timing were kept off-chip to reduce the heat dissipation close to the spinal cord. The ASIC was designed in a 0.18- μm high voltage CMOS process. Its output voltage compliance can be up to 25 V. It features a small core area (ASIC was developed to be suitable for integration on the epidural electrode array, and two different versions were fabricated and electrically tested. Results from both versions were almost indistinguishable. The performance of the system was verified for different loads and stimulation parameters. Its suitability to drive a passive epidural 12-electrode array in saline has also been demonstrated.

  12. Test of a 32-channel Prototype ASIC for Photon Counting Application.

    Science.gov (United States)

    Chen, Y; Cui, Y; O'Connor, P; Seo, Y; Camarda, G S; Hossain, A; Roy, U; Yang, G; James, R B

    2015-01-01

    A new low-power application-specific integrated circuit (ASIC) for Cadmium Zinc Telluride (CZT) detectors for single-photon emission computed tomography (SPECT) application is being developed at BNL. As the first step, a 32-channel prototype ASIC was designed and tested recently. Each channel has a preamplifier followed by CR-RC 3 shaping circuits and three independent energy bins with comparators and 16-bit counters. The ASIC was fabricated with TSMC 0.35-μm complementary metal-oxide-semiconductor (CMOS) process and tested in laboratories. The power consumption is around 1 mW/ch with a 2.5-V supply. With a gain of 400 mV/fC and the peaking time of 500 ns, the equivalent noise charge (ENC) of 360 e- has been measured in room temperature while the crosstalk rate is less than 0.3%. The 10-bit DACs for global thresholds have an integral nonlinearity (INL) less than 0.56% and differential nonlinearity (DNL) less than 0.33%. In the presentation, we will report the detailed test results with this ASIC.

  13. Asic developments for radiation imaging applications: The medipix and timepix family

    Science.gov (United States)

    Ballabriga, Rafael; Campbell, Michael; Llopart, Xavier

    2018-01-01

    Hybrid pixel detectors were developed to meet the requirements for tracking in the inner layers at the LHC experiments. With low input capacitance per channel (10-100 fF) it is relatively straightforward to design pulse processing readout electronics with input referred noise of ∼ 100 e-rms and pulse shaping times consistent with tagging of events to a single LHC bunch crossing providing clean 'images' of the ionising tracks generated. In the Medipix Collaborations the same concept has been adapted to provide practically noise hit free imaging in a wide range of applications. This paper reports on the development of three generations of readout ASICs. Two distinctive streams of development can be identified: the Medipix ASICs which integrate data from multiple hits on a pixel and provide the images in the form of frames and the Timepix ASICs who aim to send as much information about individual interactions as possible off-chip for further processing. One outstanding circumstance in the use of these devices has been their numerous successful applications, thanks to a large and active community of developers and users. That process has even permitted new developments for detectors for High Energy Physics. This paper reviews the ASICs themselves and details some of the many applications.

  14. A DES ASIC Suitable for Network Encryption at 10 Gbps and Beyond

    International Nuclear Information System (INIS)

    Gass, Karl; Pierson, Lyndon G.; Robertson, Perry J.; Wilcox, D. Craig; Witzke, Edward L.

    1999-01-01

    The Sandia National Laboratories (SNL) Data Encryption Standard (DES) Application Specific Integrated Circuit (ASIC) is the fastest known implementation of the DES algorithm as defined in the Federal Information Processing Standards (FIPS) Publication 46-2. DES is used for protecting data by cryptographic means. The SNL DES ASIC, over 10 times faster than other currently available DES chips, is a high-speed, filly pipelined implementation offering encryption, decryption, unique key input, or algorithm bypassing on each clock cycle. Operating beyond 105 MHz on 64 bit words, this device is capable of data throughputs greater than 6.7 Billion bits per second (tester limited). Simulations predict proper operation up to 9.28 Billion bits per second. In low frequency, low data rate applications, the ASIC consumes less that one milliwatt of power. The device has features for passing control signals synchronized to throughput data. Three SNL DES ASICS may be easily cascaded to provide the much greater security of triple-key, triple-DES

  15. Development of advanced I and C in nuclear power plants: ADIOS and ASICS

    International Nuclear Information System (INIS)

    Kim, Jung-Taek; Kwon, Kee-Choon; Hwang, In-Koo; Lee, Dong-Young; Park, Won-Man; Kim, Jung-Soo; Lee, Sang-Jeong

    2001-01-01

    In this paper Automatic Startup Intelligent Control System (ASICS) that automatically controls the PWR plant from cold shutdown to 5% of reactor power and Alarm and Diagnosis-Integrated Operator Support System (ADIOS) that is integrated with alarms, process values, and diagnostic information to an expert system focused on alarm processing are described. Nuclear Power Plant is manually controlled from cold shutdown to 5% according to the general operation procedures for startup operation of nuclear power plant. Alarm information is the primary sources to detect abnormalities in nuclear power plants or other process plants. The conventional hardwired alarm systems, characterized by one sensor-one indicator may lead the control room operators to be confused with avalanching alarms during plant transients. ASICS and ADIOS are designed to reduce the operator burden. The advances in computer software and hardware technology and also in information processing provide a good opportunity to improve the control systems and the annunciator systems of nuclear power plants or other similar process plants. It is very important to test and evaluate the performance and the function of the computer- or software-based systems like ASICS and ADIOS. The performance and the function of ASICS and ADIOS are evaluated with the real-time functional test facility and the results have shown that the developed systems are efficient and useful for operation and operator support

  16. Development of advanced I and C in nuclear power plants: ADIOS and ASICS

    Energy Technology Data Exchange (ETDEWEB)

    Kim, Jung-Taek E-mail: jtkim@nanum.kaeri.re.kr; Kwon, Kee-Choon; Hwang, In-Koo; Lee, Dong-Young; Park, Won-Man; Kim, Jung-Soo; Lee, Sang-Jeong

    2001-07-01

    In this paper Automatic Startup Intelligent Control System (ASICS) that automatically controls the PWR plant from cold shutdown to 5% of reactor power and Alarm and Diagnosis-Integrated Operator Support System (ADIOS) that is integrated with alarms, process values, and diagnostic information to an expert system focused on alarm processing are described. Nuclear Power Plant is manually controlled from cold shutdown to 5% according to the general operation procedures for startup operation of nuclear power plant. Alarm information is the primary sources to detect abnormalities in nuclear power plants or other process plants. The conventional hardwired alarm systems, characterized by one sensor-one indicator may lead the control room operators to be confused with avalanching alarms during plant transients. ASICS and ADIOS are designed to reduce the operator burden. The advances in computer software and hardware technology and also in information processing provide a good opportunity to improve the control systems and the annunciator systems of nuclear power plants or other similar process plants. It is very important to test and evaluate the performance and the function of the computer- or software-based systems like ASICS and ADIOS. The performance and the function of ASICS and ADIOS are evaluated with the real-time functional test facility and the results have shown that the developed systems are efficient and useful for operation and operator support.

  17. A 2.5 gb/s GaAs ATM Mux Demux ASIC

    DEFF Research Database (Denmark)

    Madsen, Jens Kargaard; Lassen, Peter Stuhr

    1995-01-01

    This paper describes the design and implementation of a high speed GaAs ATM Mux Demur ASIC (AMDA) which is the key element in a high speed ATM Add-Drop unit. This unit is used in a new distributed ATM multiplexing-demultiplexing architecture for broadband switching systems. The Add-Drop unit...

  18. Development of front-end ASIC for radiation detection and measurement

    International Nuclear Information System (INIS)

    Shimazoe, K.

    2014-01-01

    For realizing the multichannel spectroscopy of gamma rays, the technology of integrated circuits is necessary. Multi-channel gamma ray spectroscopy is very important for many applications including the medical imaging and the environmental monitoring. The current progress in the development of application specific integrated circuit (ASIC) for multi-channel radiation detection is introduced and reviewed. (author)

  19. Front-End ASICs for 3-D Ultrasound : From Beamforming to Digitization

    NARCIS (Netherlands)

    Chen, C.

    2018-01-01

    This thesis describes the analysis, design and evaluation of front-end application-specific integrated circuits (ASICs) for 3-D medical ultrasound imaging, with the focus on the receive electronics. They are specifically designed for next-generation miniature 3-D ultrasound devices, such as

  20. A Wireless Capsule Endoscope System With Low-Power Controlling and Processing ASIC.

    Science.gov (United States)

    Xinkai Chen; Xiaoyu Zhang; Linwei Zhang; Xiaowen Li; Nan Qi; Hanjun Jiang; Zhihua Wang

    2009-02-01

    This paper presents the design of a wireless capsule endoscope system. The proposed system is mainly composed of a CMOS image sensor, a RF transceiver and a low-power controlling and processing application specific integrated circuit (ASIC). Several design challenges involving system power reduction, system miniaturization and wireless wake-up method are resolved by employing optimized system architecture, integration of an area and power efficient image compression module, a power management unit (PMU) and a novel wireless wake-up subsystem with zero standby current in the ASIC design. The ASIC has been fabricated in 0.18-mum CMOS technology with a die area of 3.4 mm * 3.3 mm. The digital baseband can work under a power supply down to 0.95 V with a power dissipation of 1.3 mW. The prototype capsule based on the ASIC and a data recorder has been developed. Test result shows that proposed system architecture with local image compression lead to an average of 45% energy reduction for transmitting an image frame.

  1. An Energy-Efficient ASIC for Wireless Body Sensor Networks in Medical Applications.

    Science.gov (United States)

    Xiaoyu Zhang; Hanjun Jiang; Lingwei Zhang; Chun Zhang; Zhihua Wang; Xinkai Chen

    2010-02-01

    An energy-efficient application-specific integrated circuit (ASIC) featured with a work-on-demand protocol is designed for wireless body sensor networks (WBSNs) in medical applications. Dedicated for ultra-low-power wireless sensor nodes, the ASIC consists of a low-power microcontroller unit (MCU), a power-management unit (PMU), reconfigurable sensor interfaces, communication ports controlling a wireless transceiver, and an integrated passive radio-frequency (RF) receiver with energy harvesting ability. The MCU, together with the PMU, provides quite flexible communication and power-control modes for energy-efficient operations. The always-on passive RF receiver with an RF energy harvesting block offers the sensor nodes the capability of work-on-demand with zero standby power. Fabricated in standard 0.18-¿m complementary metal-oxide semiconductor technology, the ASIC occupies a die area of 2 mm × 2.5 mm. A wireless body sensor network sensor-node prototype using this ASIC only consumes < 10-nA current under the passive standby mode, and < 10 ¿A under the active standby mode, when supplied by a 3-V battery.

  2. Development of a 32-channel ASIC for an X-ray APD detector onboard the ISS

    Science.gov (United States)

    Arimoto, Makoto; Harita, Shohei; Sugita, Satoshi; Yatsu, Yoichi; Kawai, Nobuyuki; Ikeda, Hirokazu; Tomida, Hiroshi; Isobe, Naoki; Ueno, Shiro; Mihara, Tatehiro; Serino, Motoko; Kohmura, Takayoshi; Sakamoto, Takanori; Yoshida, Atsumasa; Tsunemi, Hiroshi; Hatori, Satoshi; Kume, Kyo; Hasegawa, Takashi

    2018-02-01

    We report on the design and performance of a mixed-signal application specific integrated circuit (ASIC) dedicated to avalanche photodiodes (APDs) in order to detect hard X-ray emissions in a wide energy band onboard the International Space Station. To realize wide-band detection from 20 keV to 1 MeV, we use Ce:GAGG scintillators, each coupled to an APD, with low-noise front-end electronics capable of achieving a minimum energy detection threshold of 20 keV. The developed ASIC has the ability to read out 32-channel APD signals using 0.35 μm CMOS technology, and an analog amplifier at the input stage is designed to suppress the capacitive noise primarily arising from the large detector capacitance of the APDs. The ASIC achieves a performance of 2099 e- + 1.5 e-/pF at root mean square (RMS) with a wide 300 fC dynamic range. Coupling a reverse-type APD with a Ce:GAGG scintillator, we obtain an energy resolution of 6.7% (FWHM) at 662 keV and a minimum detectable energy of 20 keV at room temperature (20 °C). Furthermore, we examine the radiation tolerance for space applications by using a 90 MeV proton beam, confirming that the ASIC is free of single-event effects and can operate properly without serious degradation in analog and digital processing.

  3. The GBT-SCA, a radiation tolerant ASIC for detector control applications in SLHC experiments

    CERN Document Server

    Gabrielli, A; Kloukinas, K; Marchioro, A; Moreira, P; Ranieri, A; De Robertis, D

    2009-01-01

    This work describes the architecture of the GigaBit Transceiver – Slow Control Adapter (GBT–SCA) ASIC suitable for the control and monitoring applications of the embedded front-end electronics in the future SLHC experiments. The GBT–SCA is part the GBT chipset currently under development for the SLHC detector upgrades. It is designed for radiation tolerance and it will be fabricated in a commercial 130 nm CMOS technology. The paper discusses the GBT-SCA architecture, the data transfer protocol, the ASIC interfaces, and its integration with the GBT optical link. The GBT–SCA is one the components of the GBT system chipset. It is proposed for the future SLHC experiments and is designed to be configurable matching different front-end system requirements. The GBT-SCA is intended for the slow control and monitoring of the embedded front end electronics and implements a point-to-multi point connection between one GBT optical link ASIC and several front end ASICs. The GBT-SCA connects to a dedicated electrica...

  4. Development of a two-dimensional ASIC for hard X-ray spectroscopy and imaging with a CdTe pixel detector

    International Nuclear Information System (INIS)

    Hiruta, Tatsuro; Tamura, K.; Ikeda, H.; Nakazawa, K.; Takasima, T.; Takahashi, T.

    2006-01-01

    We are developing a two-dimensional analog ASIC for the readout of pixel sensors based on silicon (Si) or cadmium telluride (CdTe) for spectroscopic imaging observations in the X-ray and gamma-ray regions. The aim for the ASIC is to obtain a low-noise performance better than 100 electrons (rms) with self-triggering capabilities. As the first step of prototyping, we have fabricated several ASICs. We obtained an energy resolution of 5.4 keV (FWHM) for 81 keV gamma-rays from 133 Ba with a one-dimensional ASIC connected to a CdTe diode and also verified a readout architecture via a two-dimensional ASIC with 144 pixel channels. Based on the results obtained and experience gained through prototype ASICs, we are developing a 4096-channel two-dimensional analog ASIC

  5. A Prototype PZT Matrix Transducer With Low-Power Integrated Receive ASIC for 3-D Transesophageal Echocardiography.

    Science.gov (United States)

    Chen, Chao; Raghunathan, Shreyas B; Yu, Zili; Shabanimotlagh, Maysam; Chen, Zhao; Chang, Zu-yao; Blaak, Sandra; Prins, Christian; Ponte, Jacco; Noothout, Emile; Vos, Hendrik J; Bosch, Johan G; Verweij, Martin D; de Jong, Nico; Pertijs, Michiel A P

    2016-01-01

    This paper presents the design, fabrication, and experimental evaluation of a prototype lead zirconium titanate (PZT) matrix transducer with an integrated receive ASIC, as a proof of concept for a miniature three-dimensional (3-D) transesophageal echocardiography (TEE) probe. It consists of an array of 9 ×12 piezoelectric elements mounted on the ASIC via an integration scheme that involves direct electrical connections between a bond-pad array on the ASIC and the transducer elements. The ASIC addresses the critical challenge of reducing cable count, and includes front-end amplifiers with adjustable gains and micro-beamformer circuits that locally process and combine echo signals received by the elements of each 3 ×3 subarray. Thus, an order-of-magnitude reduction in the number of receive channels is achieved. Dedicated circuit techniques are employed to meet the strict space and power constraints of TEE probes. The ASIC has been fabricated in a standard 0.18-μm CMOS process and consumes only 0.44 mW/channel. The prototype has been acoustically characterized in a water tank. The ASIC allows the array to be presteered across ±37° while achieving an overall dynamic range of 77 dB. Both the measured characteristics of the individual transducer elements and the performance of the ASIC are in good agreement with expectations, demonstrating the effectiveness of the proposed techniques.

  6. SSG Wave Energy Converter

    DEFF Research Database (Denmark)

    Margheritini, Lucia; Vicinanza, Diego; Frigaard, Peter

    2008-01-01

    The SSG (Sea Slot-cone Generator) is a wave energy converter of the overtopping type. The structure consists of a number of reservoirs one on the top of each others above the mean water level, in which the water of incoming waves is stored temporary. In each reservoir, expressively designed low...... head hydroturbines are converting the potential energy of the stored water into power. A key to success for the SSG will be the low cost of the structure and its robustness. The construction of the pilot plant is scheduled and this paper aims to describe the concept of the SSG wave energy converter...

  7. Acid sensing ion channel (ASIC) inhibitors exhibit anxiolytic-like activity in preclinical pharmacological models.

    Science.gov (United States)

    Dwyer, Jason M; Rizzo, Stacey J Sukoff; Neal, Sarah J; Lin, Qian; Jow, Flora; Arias, Robert L; Rosenzweig-Lipson, Sharon; Dunlop, John; Beyer, Chad E

    2009-03-01

    Acid sensing ion channels (ASICs) are proton-gated ion channels located in the central and peripheral nervous systems. Of particular interest is ASIC1a, which is located in areas associated with fear and anxiety behaviors. Recent reports suggest a role for ASIC1a in preclinical models of fear conditioning and anxiety. The present experiments evaluated various ASIC inhibitors in preclinical models of autonomic and behavioral parameters of anxiety. In addition, neurochemical studies evaluated the effects of an ASIC inhibitor (A-317567) on neurotransmitter levels in the amygdala. In electrophysiological studies using hippocampal primary neuronal cultures, three ASIC inhibitors (PcTX-1, A-317567, and amiloride) produced concentration-dependent inhibition of acid-evoked currents. In the stress-induced hyperthermia model, acute administration of psalmotoxin 1 (PcTX-1; 10-56 ng, i.c.v.), A-317567 (0.1-1.0 mg/kg, i.p.), and amiloride (10-100 mg/kg, i.p.) prevented stress-induced elevations in core body temperature. In the four-plate test, acute treatment with PcTX-1 (10-56 ng, i.c.v.) and A-317567 (0.01-0.1 mg/kg, i.p.), but not amiloride (3-100 mg/kg, i.p.), produced dose-dependent and significant increases in the number of punished crossings relative to vehicle-treated animals. Additionally, PcTX-1 (56-178 ng, i.c.v.), A-317567 (0.1-10 mg/kg, i.p.), and amiloride (10-100 mg/kg, i.p.) lacked significant anxiolytic-like activity in the elevated zero maze. In neurochemical studies, an infusion of A-317567 (100 microM) into the amygdala significantly elevated the extracellular levels of GABA, but not glutamate, in this brain region. These findings demonstrate that ASIC inhibition produces anxiolytic-like effects in some behavioral models and indicate a potential role for GABAergic mechanisms to underlie these anxiolytic-like effects.

  8. Role of TRPV1 and ASIC3 channels in experimental occlusal interference-induced hyperalgesia in rat masseter muscle.

    Science.gov (United States)

    Xu, X X; Cao, Y; Ding, T T; Fu, K Y; Li, Y; Xie, Q F

    2016-04-01

    Masticatory muscle pain may occur following immediate occlusal alteration by dental treatment. The underlying mechanisms are poorly understood. Transient receptor potential vanilloid-1 (TRPV1) and acid-sensing ion channel-3 (ASIC3) mediate muscle hyperalgesia under various pathologic conditions. We have developed a rat model of experimental occlusal interference (EOI) that consistently induces mechanical hyperalgesia in jaw muscles. Whether TRPV1 and ASIC3 mediate this EOI-induced hyperalgesia is unknown. Rat model of EOI-induced masseter hyperalgesia was established. Real-time polymerase chain reaction, Western blot and retrograde labelling combined with immunofluorescence were performed to evaluate the modulation of TRPV1 and ASIC3 expression in trigeminal ganglia (TGs) and masseter afferents of rats after EOI. The effects of intramuscular administration of TRPV1 and ASIC3 antagonists on the EOI-induced hyperalgesia in masseter muscle were examined. After EOI, gene expressions and protein levels of TRPV1 and ASIC3 in bilateral TGs were up-regulated. The percentage of ASIC3- (but not TRPV1-) positive neurons in masseter afferents increased after EOI. More small-sized and small to medium-sized masseter afferents expressed TRPV1 and ASIC3 separately following EOI. These changes peaked at day 7 and then returned to original status within 10 days after EOI. Intramuscular administration of the TRPV1 antagonist AMG-9810 partially reversed this mechanical hyperalgesia in masseter muscle. No improvement was exhibited after administration of the ASIC3 antagonist APETx2. Co-injection of AMG-9810 and APETx2 enhanced the effect of AMG-9810 administration alone. Peripheral TRPV1 and ASIC3 contribute to the development of the EOI-induced mechanical hyperalgesia in masseter muscle. © 2015 European Pain Federation - EFIC®

  9. Modulation of ASIC channels in rat cerebellar purkinje neurons by ischaemia-related signals

    Science.gov (United States)

    Allen, Nicola J; Attwell, David

    2002-01-01

    Acid-sensing ion channels (ASICs), activated by a decrease of extracellular pH, are found in neurons throughout the nervous system. They have an amino acid sequence similar to that of ion channels activated by membrane stretch, and have been implicated in touch sensation. Here we characterize the pH-dependent activation of ASICs in cerebellar Purkinje cells and investigate how they are modulated by factors released in ischaemia. Lowering the external pH from 7.4 activated an inward current at −66 mV, carried largely by Na+ ions, which was half-maximal for a step to pH 6.4 and was blocked by amiloride and gadolinium. The H+-gated current desensitized within a few seconds, but approximately 30% of cells showed a sustained inward current (11% of the peak current) in response to the maintained presence of pH 6 solution. The peak H+-evoked current was potentiated by membrane stretch (which occurs in ischaemia when [K+]o rises) and by arachidonic acid (which is released when [Ca2+]i rises in ischaemia). Arachidonic acid increased to 77% the fraction of cells showing a sustained current evoked by acid pH. The ASIC currents were also potentiated by lactate (which is released when metabolism becomes anaerobic in ischaemia) and by FMRFamide (which may mimic the action of related mammalian RFamide transmitters). These data reinforce suggestions of a mechanosensory aspect to ASIC channel function, and show that the activation of ASICs reflects the integration of multiple signals which are present during ischaemia. PMID:12205186

  10. Design of a video capsule endoscopy system with low-power ASIC for monitoring gastrointestinal tract.

    Science.gov (United States)

    Liu, Gang; Yan, Guozheng; Zhu, Bingquan; Lu, Li

    2016-11-01

    In recent years, wireless capsule endoscopy (WCE) has been a state-of-the-art tool to examine disorders of the human gastrointestinal tract painlessly. However, system miniaturization, enhancement of the image-data transfer rate and power consumption reduction for the capsule are still key challenges. In this paper, a video capsule endoscopy system with a low-power controlling and processing application-specific integrated circuit (ASIC) is designed and fabricated. In the design, these challenges are resolved by employing a microimage sensor, a novel radio frequency transmitter with an on-off keying modulation rate of 20 Mbps, and an ASIC structure that includes a clock management module, a power-efficient image compression module and a power management unit. An ASIC-based prototype capsule, which measures Φ11 mm × 25 mm, has been developed here. Test results show that the designed ASIC consumes much less power than most of the other WCE systems and that its total power consumption per frame is the least. The image compression module can realize high near-lossless compression rate (3.69) and high image quality (46.2 dB). The proposed system supports multi-spectral imaging, including white light imaging and autofluorescence imaging, at a maximum frame rate of 24 fps and with a resolution of 400 × 400. Tests and in vivo trials in pigs have proved the feasibility of the entire system, but further improvements in capsule control and compression performance inside the ASIC are needed in the future.

  11. Electric current - frequency converter

    International Nuclear Information System (INIS)

    Kumahara, Tadashi; Kinbana, Setsuro.

    1967-01-01

    Herein disclosed is an improved simple electric current-frequency converter, the input current and output frequency linearity of which is widened to a range of four to five figures while compensating, for temperature. The converter may be used for computor processing and for telemetering the output signals from a nuclear reactor. The converter is an astable multivibrator which includes charging circuits comprising emitter-voltage compensated NPN transistors, a charged voltage detecting circuit of temperature compensated field effect transistors, and a transistor switching circuit for generating switching pulses independent of temperature. The converter exhibited a 0.7% frequency change within a range of 5 - 45 0 C and less than a 0.1% frequency drift after six hours of operation when the input current was maintained constant. (Yamaguchi, T.)

  12. Improving Power Converter Reliability

    DEFF Research Database (Denmark)

    Ghimire, Pramod; de Vega, Angel Ruiz; Beczkowski, Szymon

    2014-01-01

    of a high-power IGBT module during converter operation, which may play a vital role in improving the reliability of the power converters. The measured voltage is used to estimate the module average junction temperature of the high and low-voltage side of a half-bridge IGBT separately in every fundamental......The real-time junction temperature monitoring of a high-power insulated-gate bipolar transistor (IGBT) module is important to increase the overall reliability of power converters for industrial applications. This article proposes a new method to measure the on-state collector?emitter voltage...... is measured in a wind power converter at a low fundamental frequency. To illustrate more, the test method as well as the performance of the measurement circuit are also presented. This measurement is also useful to indicate failure mechanisms such as bond wire lift-off and solder layer degradation...

  13. Development and validation of a 64 channel front end ASIC for 3D directional detection for MIMAC

    International Nuclear Information System (INIS)

    Richer, J P; Bourrion, O; Bosson, G; Guillaudin, O; Mayet, F; Santos, D

    2011-01-01

    A front end ASIC has been designed to equip the μTPC prototype developed for the MIMAC project, which requires 3D reconstruction of low energy particle tracks in order to perform directional detection of galactic Dark Matter. Each ASIC is able to monitor 64 strips of pixels and provides the 'Time Over Threshold' information for each of those. These 64 digital informations, sampled at a rate of 50 MHz, can be transferred at 400 MHz by eight LVDS serial links. Eight ASIC were validated on a 2 × 256 strips of pixels prototype.

  14. Neuroprotective Effects of Psalmotoxin-1, an Acid-Sensing Ion Channel (ASIC) Inhibitor, in Ischemia Reperfusion in Mouse Eyes.

    Science.gov (United States)

    Dibas, Adnan; Millar, Cameron; Al-Farra, Abraham; Yorio, Thomas

    2018-03-29

    The purpose of the current study is to assess changes in the expression of Acid-Sensing Ion Channel (ASIC)1a and ASIC2 in retinal ganglion cells (RGCs) after retinal ischemia and reperfusion (I/R) injury and to test if inhibition of ASIC1a provides RGC neuroprotection. Transient ischemia was induced in one eye of C57BL/6 mice by raising intraocular pressure to 120 mmHg for 60 min followed by retinal reperfusion by restoring normal pressure. RGC function was measured by Pattern electroretinography (PERG). In addition, retinal ASIC1a and ASIC2 were observed by immunohistochemistry and western blot. Changes in calpain, fodrin, heat shock protein 70 (HSP70), Brn3a, super oxide dismutase-1 (SOD1), catalase, and glutathione perioxidase-4 (GPX4) protein levels were assessed by western blot. RGC numbers were measured by immunohistochemistry on whole retinal flat mounts using anti-RNA binding protein with multiple splicing (RBPMS) antibodies. Intravitreal injection of psalmotoxin-1, a selective ASIC1a blocker, was used to assess the neuroprotective effect of ASIC1a inhibition. Levels of ASIC1a and ASIC2 after I/R increased in RGCs. Upregulation of ASIC1a but not ASIC2 was attenuated by intravitreal injection of psalmotoxin-1. I/R induced activation of calpain and degradation of fodrin, HSP70, and reduction in Brn3a. In contrast, while psalmotoxin-1 attenuated calpain activation and increased Brn3a levels, it failed to block HSP70 degradation. Unlike SOD1 protein which was reduced, catalase protein levels increased after I/R. Psalmotoxin-1, although not affecting SOD1 and GPX4, increased catalase levels significantly. Psalmotoxin-1 also increased RBPMS-labeled RGCs following I/R as judged by immunohistochemistry of retinal flat mounts. Finally, psalmotoxin-1 enhanced the amplitude of PERG following I/R, suggesting partial rescue of RGC function. Psalmotoxin-1 appears to exert a neuroprotective effect under ischemic insults and targeting inhibition of ASICs may represent a

  15. Low-power digital ASIC for on-chip spectral analysis of low-frequency physiological signals

    International Nuclear Information System (INIS)

    Nie Zedong; Zhang Fengjuan; Li Jie; Wang Lei

    2012-01-01

    A digital ASIC chip customized for battery-operated body sensing devices is presented. The ASIC incorporates a novel hybrid-architecture fast Fourier transform (FFT) unit that is capable of scalable spectral analysis, a licensed ARM7TDMI IP hardcore and several peripheral IP blocks. Extensive experimental results suggest that the complete chip works as intended. The power consumption of the FFT unit is 0.69 mW at 1 MHz with 1.8 V power supply. The low-power and programmable features of the ASIC make it suitable for ‘on-the-fly’ low-frequency physiological signal processing. (semiconductor integrated circuits)

  16. Thermionic photovoltaic energy converter

    Science.gov (United States)

    Chubb, D. L. (Inventor)

    1985-01-01

    A thermionic photovoltaic energy conversion device comprises a thermionic diode mounted within a hollow tubular photovoltaic converter. The thermionic diode maintains a cesium discharge for producing excited atoms that emit line radiation in the wavelength region of 850 nm to 890 nm. The photovoltaic converter is a silicon or gallium arsenide photovoltaic cell having bandgap energies in this same wavelength region for optimum cell efficiency.

  17. Driver ASIC Environmental Testing and Performance Optimization for SpaceBased Active Mirrors

    Science.gov (United States)

    Mejia Prada, Camilo

    Direct imaging of Earth-like planets requires techniques for light suppression, such as coronagraphs or nulling interferometers, in which deformable mirrors (DM) are a principal component. On ground-based systems, DMs are used to correct for turbulence in the Earth’s atmosphere in addition to static aberrations in the optics. For space-based observations, DMs are used to correct for static and quasi- static aberrations in the optical train. State-of-the-art, high-actuator count deformable mirrors suffer from external heavy and bulky electronics in which electrical connections are made through thousands of wires. We are instead developing Application Specific Integrated Circuits (ASICs) capable of direct integration with the DM in a single small package. This integrated ASIC-DM is ideal for space missions, where it offers significant reduction in mass, power and complexity, and performance compatible with high-contrast observations of exoplanets. We have successfully prototyped and tested a 32x32 format Switch-Mode (SM) ASIC which consumes only 2mW static power (total, not per-actuator). A number of constraints were imposed on key parameters of this ASIC design, including sub-picoamp levels of leakage across turned-off switches and from switch-to-substrate, control resolution of 0.04 mV, satisfactory rise/fall times, and a near-zero on-chip crosstalk over a useful range of operating temperatures. This driver ASIC technology is currently at TRL 4. This Supporting Technology proposal will further develop the ASIC technology to TRL 5 by carrying on environmental tests and further optimizing performance, with the end goal of making ASICs suitable for space-based deployment. The effort will be led by JPL, which has considerable expertise with DMs used in highcontrast imaging systems for exoplanet missions and in adaptive optic systems, and in design of DM driver electronics. Microscale, which developed the prototype of the ASICDM, will continue its development. We

  18. Design Implementation and Testing of a VLSI High Performance ASIC for Extracting the Phase of a Complex Signal

    National Research Council Canada - National Science Library

    Altmeyer, Ronald

    2002-01-01

    This thesis documents the research, circuit design, and simulation testing of a VLSI ASIC which extracts phase angle information from a complex sampled signal using the arctangent relationship: (phi=tan/-1 (Q/1...

  19. ASIC and ENaC type sodium channels: conformational states and the structures of the ion selectivity filters.

    Science.gov (United States)

    Hanukoglu, Israel

    2017-02-01

    The acid-sensing ion channels (ASICs) and epithelial sodium channels (ENaC) are members of a superfamily of channels that play critical roles in mechanosensation, chemosensation, nociception, and regulation of blood volume and pressure. These channels look and function like a tripartite funnel that directs the flow of Na + ions into the cytoplasm via the channel pore in the membrane. The subunits that form these channels share a common structure with two transmembrane segments (TM1 and TM2) and a large extracellular part. In most vertebrates, there are five paralogous genes that code for ASICs (ASIC1-ASIC5), and four for ENaC subunits alpha, beta, gamma, and delta (α, β, γ, and δ). While ASICs can form functional channels as a homo- or heterotrimer, ENaC functions as an obligate heterotrimer composed of α-β-γ or β-γ-δ subunits. The structure of ASIC has been determined in several conformations, including desensitized and open states. This review presents a comparison of the structures of these states using easy-to-understand molecular models of the full complex, the central tunnel that includes an outer vestibule, the channel pore, and ion selectivity filter. The differences in the secondary, tertiary, and quaternary structures of the states are summarized to pinpoint the conformational changes responsible for channel opening. Results of site-directed mutagenesis studies of ENaC subunits are examined in light of ASIC1 models. Based on these comparisons, a molecular model for the selectivity filter of ENaC is built by in silico mutagenesis of an ASIC1 structure. These models suggest that Na + ions pass through the filter in a hydrated state. © 2016 Federation of European Biochemical Societies.

  20. Resveratrol attenuates bone cancer pain through regulating the expression levels of ASIC3 and activating cell autophagy.

    Science.gov (United States)

    Zhu, Haili; Ding, Jieqiong; Wu, Ji; Liu, Tingting; Liang, Jing; Tang, Qiong; Jiao, Ming

    2017-11-01

    Bone cancer pain (BCP) is one of the most common pains in patients with malignant cancers. The mechanism underlying BCP is largely unknown. Our previous studies and the increasing evidence both have shown that acid-sensing ion channels 3 (ASIC3) is an important protein in the pathological pain state in some pain models. We hypothesized that the expression change of ASIC3 might be one of the factors related to BCP. In this study, we established the BCP model through intrathecally injecting rat mammary gland carcinoma cells (MRMT-1) into the left tibia of Sprague-Dawley female rats, and found that the BCP rats showed bone destruction, increased mechanical pain sensitivities and up-regulated ASIC3 protein expression levels in L4-L6 dorsal root ganglion. Then, resveratrol, which was intraperitoneally injected into the BCP rats on post-operative Day 21, dose-dependently increased the paw withdrawal threshold of BCP rats, reversed the pain behavior, and had an antinociceptive effect on BCP rats. In ASIC3-transfected SH-SY5Y cells, the ASIC3 protein expression levels were regulated by resveratrol in a dose- and time-dependent manner. Meanwhile, resveratrol also had an antinociceptive effect in ASIC3-mediated pain rat model. Furthermore, resveratrol also enhanced the phosphorylation of AMPK, SIRT1, and LC3-II levels in ASIC3-transfected SH-SY5Y cells, indicating that resveratrol could activate the AMPK-SIRT1-autophagy signal pathway in ASIC3-transfected SH-SY5Y cells. In BCP rats, SIRT1 and LC3-II were also down-regulated. These findings provide new evidence for the use of resveratrol as a therapeutic treatment during BCP states. © The Author 2017. Published by Oxford University Press on behalf of the Institute of Biochemistry and Cell Biology, Shanghai Institutes for Biological Sciences, Chinese Academy of Sciences. All rights reserved. For permissions, please e-mail: journals.permissions@oup.com.

  1. Differential regulation of proton-sensitive ion channels by phospholipids: a comparative study between ASICs and TRPV1.

    Directory of Open Access Journals (Sweden)

    Hae-Jin Kweon

    Full Text Available Protons are released in pain-generating pathological conditions such as inflammation, ischemic stroke, infection, and cancer. During normal synaptic activities, protons are thought to play a role in neurotransmission processes. Acid-sensing ion channels (ASICs are typical proton sensors in the central nervous system (CNS and the peripheral nervous system (PNS. In addition to ASICs, capsaicin- and heat-activated transient receptor potential vanilloid 1 (TRPV1 channels can also mediate proton-mediated pain signaling. In spite of their importance in perception of pH fluctuations, the regulatory mechanisms of these proton-sensitive ion channels still need to be further investigated. Here, we compared regulation of ASICs and TRPV1 by membrane phosphoinositides, which are general cofactors of many receptors and ion channels. We observed that ASICs do not require membrane phosphatidylinositol 4-phosphate (PI(4P or phosphatidylinositol 4,5-bisphosphate (PI(4,5P2 for their function. However, TRPV1 currents were inhibited by simultaneous breakdown of PI(4P and PI(4,5P2. By using a novel chimeric protein, CF-PTEN, that can specifically dephosphorylate at the D3 position of phosphatidylinositol 3,4,5-trisphosphate (PI(3,4,5P3, we also observed that neither ASICs nor TRPV1 activities were altered by depletion of PI(3,4,5P3 in intact cells. Finally, we compared the effects of arachidonic acid (AA on two proton-sensitive ion channels. We observed that AA potentiates the currents of both ASICs and TRPV1, but that they have different recovery aspects. In conclusion, ASICs and TRPV1 have different sensitivities toward membrane phospholipids, such as PI(4P, PI(4,5P2, and AA, although they have common roles as proton sensors. Further investigation about the complementary roles and respective contributions of ASICs and TRPV1 in proton-mediated signaling is necessary.

  2. Blind channel estimation for MLSE receiver in high speed optical communications: theory and ASIC implementation.

    Science.gov (United States)

    Gorshtein, Albert; Levy, Omri; Katz, Gilad; Sadot, Dan

    2013-09-23

    Blind channel estimation is critical for digital signal processing (DSP) compensation of optical fiber communications links. The overall channel consists of deterministic distortions such as chromatic dispersion, as well as random and time varying distortions including polarization mode dispersion and timing jitter. It is critical to obtain robust acquisition and tracking methods for estimating these distortions effects, which, in turn, can be compensated by means of DSP such as Maximum Likelihood Sequence Estimation (MLSE). Here, a novel blind estimation algorithm is developed, accompanied by inclusive mathematical modeling, and followed by extensive set of real time experiments that verify quantitatively its performance and convergence. The developed blind channel estimation is used as the basis of an MLSE receiver. The entire scheme is fully implemented in a 65 nm CMOS Application Specific Integrated Circuit (ASIC). Experimental measurements and results are presented, including Bit Error Rate (BER) measurements, which demonstrate the successful data recovery by the MLSE ASIC under various channel conditions and distances.

  3. An ASIC memory buffer controller for a high speed disk system

    Science.gov (United States)

    Hodson, Robert F.; Campbell, Steve

    1993-01-01

    The need for large capacity, high speed mass memory storage devices has become increasingly evident at NASA during the past decade. High performance mass storage systems are crucial to present and future NASA systems. Spaceborne data storage system requirements have grown in response to the increasing amounts of data generated and processed by orbiting scientific experiments. Predictions indicate increases in the volume of data by orders of magnitude during the next decade. Current predictions are for storage capacities on the order of terabits (Tb), with data rates exceeding one gigabit per second (Gbps). As part of the design effort for a state of the art mass storage system, NASA Langley has designed a 144 CMOS ASIC to support high speed data transfers. This paper discusses the system architecture, ASIC design and some of the lessons learned in the development process.

  4. Design and Characterization of the VMM1 ASIC for Micropattern Gas Detectors

    CERN Document Server

    Metcalfe, J; The ATLAS collaboration; Fried, J; Li, S; Nambiar, N; Polychronakos, V; Vernon, E

    2013-01-01

    We present here the measurements of the first prototype VMM1 ASIC designed at Brookhaven National Laboratory in 130 nm CMOS and fabricated in spring 2012. The 64-channel ASIC features a novel design for use with several types of micropattern gas detectors. The data driven system measures peak amplitude and timing information in tracking mode and first channel hit address in trigger mode. Several programmable gain and integration times allows the flexibility to work with Micromegas, Thin Gap Chambers (TGCs), and Gas Electron Multiplier (GEM) detectors. The IC design architecture and features will be presented along with measurements characterizing the performance of the VMM1 such as noise, linearity of the response, time walk, and calibration range. The concept for use with Micromegas in ATLAS Upgrade will also be covered including characterization under test beam conditions.

  5. Measurements of low noise 64 channel counting ASIC for Si and CdTe strip detectors

    International Nuclear Information System (INIS)

    Kachel, M; Grybos, P; Szczygiel, R; Takeyoshi, T

    2011-01-01

    We present the design and performance of a 64-channel ASIC called SXDR64. The circuit is intended to work with DC coupled CdTe detectors as well as with standard AC coupled Si detectors. A single channel of the ASIC consists of a charge sensitive amplifier with a pole-zero cancellation circuit, a 4 th order programmable shaper, a base-line restorer and two independent discriminators with 20-bit counters equipped with RAM. The circuit is able to operate correctly with both polarities of the input signal and the detectors leakage current in a few nA range, with the average rate of input pulses up to 1 Mcps.

  6. ENC Measurement for ASIC Preamp Board as a Detector Module for PET System

    Directory of Open Access Journals (Sweden)

    N. Nagara

    2016-08-01

    Full Text Available We developed a gamma ray detector with an LuAG:Pr scintillator and an avalanche photodiode as a detector for a positron emission tomography (PET system. Studies have been performed on the influences of gamma irradiation on application-specific integrated circuit (ASIC preamp boards used as a detector module. As a device used in nuclear environments for substantial durations, the ASIC has to have a lifetime long enough to ensure that there will be a negligible failure rate during this period. These front-end systems must meet the requirements for standard positron emission tomography (PET systems. Therefore, an equivalent noise charge (ENC experiment is needed to measure the front-end system's characteristics. This study showed that minimum ENC conditions can be achieved if a shorter shaping time could be applied.

  7. Irradiation of the CLARO-CMOS chip, a fast ASIC for single-photon counting

    International Nuclear Information System (INIS)

    Andreotti, M.; Baldini, W.; Calabrese, R.; Carniti, P.; Cassina, L.; Cotta Ramusino, A.; Fiorini, M.; Giachero, A.; Gotti, C.; Luppi, E.; Maino, M.; Malaguti, R.; Pessina, G.; Tomassetti, L.

    2015-01-01

    The CLARO-CMOS is a prototype ASIC that allows fast photon counting with low power consumption, built in AMS 0.35 μm CMOS technology. It is intended to be used as a front-end readout for the upgraded LHCb RICH detectors. In this environment, assuming 10 years of operation at the nominal luminosity expected after the upgrade, the ASIC must withstand a total fluence of about 6×10 12 1 MeV n eq /cm 2 and a total ionising dose of 400 krad. Long term stability of the electronics front-end is essential and the effects of radiation damage on the CLARO-CMOS performance must be carefully studied. This paper describes results of multi-step irradiation tests with protons up to the dose of ~8 Mrad, including measurement of single event effects during irradiation and chip performance evaluation before and after each irradiation step

  8. Study of multi-channel readout ASIC and its discrete module for particle detector

    International Nuclear Information System (INIS)

    Wang Ke; Fan Lei; Zhang Shengjun; Li Xian

    2013-01-01

    Recently, kinds of particle detectors have used Application Specific Integrated Circuits (ASIC) in their electronics readout systems, it is the key part for the whole system. This project designed a multi-channel readout ASIC for general detectors. The chip has Preamplifier, Shaper and Peak Detector embedded for easy readout. For each channel, signal which is preprocessed by a low-noise preamplifier is sent to the shaper to form a quasi-Gaussian pulse and keep its peak for readout. This chip and modules of individual Preamplifier, Shaper and Peak Detector have been manufactured and tested. The discrete modules work well, and the 6-channel chip NPRE 6 is ready for test in some particle detection system. (authors)

  9. An Electromagnetic Beam Converter

    DEFF Research Database (Denmark)

    2009-01-01

    The present invention relates to an electromagnetic beam converter and a method for conversion of an input beam of electromagnetic radiation having a bell shaped intensity profile a(x,y) into an output beam having a prescribed target intensity profile l(x',y') based on a further development...

  10. Converting the reset

    NARCIS (Netherlands)

    J.K. Hoogland (Jiri); C.D.D. Neumann; D. Bloch

    2001-01-01

    textabstractWe give a simple algorithm to incorporate the effects of resets in convertible bond prices, without having to add an extra factor to take into account the value of the reset. Furthermore we show that the effect of a notice period, and additional make-whole features, can be treated in a

  11. Definition of Power Converters

    CERN Document Server

    Bordry, F

    2015-01-01

    The paper is intended to introduce power conversion principles and to define common terms in the domain. The concept s of sources and switches are defined and classified. From the basic laws of source interconnections, a generic method of power converter synthesis is presented. Some examples illustrate this systematic method. Finally, the commutation cell and soft commuta tion are introduced and discussedd.

  12. Thermoelectrode for thermoelectric converter

    International Nuclear Information System (INIS)

    Bodiul, Pavel; Bondarciuc, Nicolae; Ghitu, Dumitru; Nikolaeva, Albina; Konopko, Leonid; Turcan, Ana

    2008-01-01

    The invention relates to the electronic engneering and can be used for manufacturing of thermoelectrodes for thermoelectric converters. The thermoelectrode is made of semiconductor anisotropic material in the form of thread in glass insulation. At the same timer, the thread is made of stannum-doped tellurium in the ratio of 0.1...3 at.%.

  13. The Convertible Arbitrage Strategy Analyzed

    NARCIS (Netherlands)

    Loncarski, I.; Ter Horst, J.R.; Veld, C.H.

    2006-01-01

    This paper analyzes convertible bond arbitrage on the Canadian market for the period 1998 to 2004.Convertible bond arbitrage is the combination of a long position in convertible bonds and a short position in the underlying stocks. Convertible arbitrage has been one of the most successful strategies

  14. Design of a Trigger Data Serializer ASIC for the Upgrade of the ATLAS Forward Muon Spectrometer

    Science.gov (United States)

    Wang, Jinhong; Guan, Liang; Chapman, J. W.; Zhou, Bing; Zhu, Junjie

    2017-12-01

    The small-strip Thin Gap Chamber (sTGC) will be used for both triggering and precision tracking purposes in the upgrade of the ATLAS forward muon spectrometer. Both sTGC pad and strip detectors are readout by a Trigger Data Serializer (TDS) ASIC in the trigger path. This ASIC has two operation modes to prepare trigger data from pad and strip detectors respectively. The pad mode (pad-TDS) collects the firing status for up to 104 pads from one detector layer and transmits the data at 4.8 Gbps to the pad trigger extractor every 25 ns. The pad trigger extractor collects pad-TDS data from eight detector layers and defines a region of interest along the path of a muon candidate. In the strip mode (strip-TDS), the deposited charges from up to 128 strips are buffered, time-stamped, and a trigger matching procedure is performed to read out strips underneath the region of interest. The strip-TDS output is also transmitted at 4.8 Gbps to the following FPGA processing circuits. Details about the ASIC design and test results are presented in this paper.

  15. Monolithic Active Pixel Matrix with Binary Counters ASIC with nested wells

    International Nuclear Information System (INIS)

    Fahim, F; Deptuch, G; Holm, S; Shenai, A; Lipton, R

    2013-01-01

    Monolithic Active Matrix with Binary Counters (MAMBO) V ASIC has been designed for detecting and measuring low energy X-rays. A nested well structure with a buried n-well (BNW) and a deeper buried p-well (BPW) is used to electrically isolate the detector from the electronics. BNW acts as an AC ground to electrical signals and behaves as a shield. BPW allows for a homogenous electric field in the entire detector volume. The ASIC consists of a matrix of 50 × 52 pixels, each of 105x105μm 2 . Each pixel contains analog functionality accomplished by a charge preamplifier, CR-RC 2 shaper and a baseline restorer. It also contains a window comparator with Upper and Lower thresholds which can be individually trimmed by 4 bit DACs to remove systematic offsets. The hits are registered by a 12 bit counter which is reconfigured as a shift register to serially output the data from the entire ASIC.

  16. CLARO: an ASIC for high rate single photon counting with multi-anode photomultipliers

    Science.gov (United States)

    Baszczyk, M.; Carniti, P.; Cassina, L.; Cotta Ramusino, A.; Dorosz, P.; Fiorini, M.; Gotti, C.; Kucewicz, W.; Malaguti, R.; Pessina, G.

    2017-08-01

    The CLARO is a radiation-hard 8-channel ASIC designed for single photon counting with multi-anode photomultiplier tubes. Each channel outputs a digital pulse when the input signal from the photomultiplier crosses a configurable threshold. The fast return to baseline, typically within 25 ns, and below 50 ns in all conditions, allows to count up to 107 hits/s on each channel, with a power consumption of about 1 mW per channel. The ASIC presented here is a much improved version of the first 4-channel prototype. The threshold can be precisely set in a wide range, between 30 ke- (5 fC) and 16 Me- (2.6 pC). The noise of the amplifier with a 10 pF input capacitance is 3.5 ke- (0.6 fC) RMS. All settings are stored in a 128-bit configuration and status register, protected against soft errors with triple modular redundancy. The paper describes the design of the ASIC at transistor-level, and demonstrates its performance on the test bench.

  17. A generic miniature multi-feature programmable wireless powering headstage ASIC for implantable biomedical systems.

    Science.gov (United States)

    Kubendran, Rajkumar; Krishnan, Harish; Manola, Bhupendra; John, Simon W M; Chappell, William J; Irazoqui, Pedro P

    2011-01-01

    Wireless powering holds immense promise to enable a variety of implantable biomedical measurement systems with different power supply and current budget requirements. Effective power management demands more functionality in the headstage design like power level detection for range estimation and power save modes for sleep-wake operation. This paper proposes a single chip ASIC solution that addresses these problems by incorporating digitally programmable features and thus has the potential to enable wireless powering for many implantable systems. The ASIC includes an RF rectifier which has a peak efficiency of 17.9% at 900 MHz and 11.0% at 2.4 GHz, a robust 1 V bandgap reference and LDO voltage regulator whose output can be programmed in the range of 1 V-1.5 V, and can drive upto 4 mA of load current. The input RF power level detector has a threshold of 1.6 V and the power management block can be programmed to give a 6%, 12.5% or 25% duty cycle power line to the transmitter resulting in upto 60% reduction in average power. The ASIC was fabricated using the TSMC 65 nm process, occupies 1mm(2) die area and the headstage consumes ~300 μA at 1.2V regulated supply.

  18. Chemical synthesis, 3D structure, and ASIC binding site of the toxin mambalgin-2.

    Science.gov (United States)

    Schroeder, Christina I; Rash, Lachlan D; Vila-Farrés, Xavier; Rosengren, K Johan; Mobli, Mehdi; King, Glenn F; Alewood, Paul F; Craik, David J; Durek, Thomas

    2014-01-20

    Mambalgins are a novel class of snake venom components that exert potent analgesic effects mediated through the inhibition of acid-sensing ion channels (ASICs). The 57-residue polypeptide mambalgin-2 (Ma-2) was synthesized by using a combination of solid-phase peptide synthesis and native chemical ligation. The structure of the synthetic toxin, determined using homonuclear NMR, revealed an unusual three-finger toxin fold reminiscent of functionally unrelated snake toxins. Electrophysiological analysis of Ma-2 on wild-type and mutant ASIC1a receptors allowed us to identify α-helix 5, which borders on the functionally critical acidic pocket of the channel, as a major part of the Ma-2 binding site. This region is also crucial for the interaction of ASIC1a with the spider toxin PcTx1, thus suggesting that the binding sites for these toxins substantially overlap. This work lays the foundation for structure-activity relationship (SAR) studies and further development of this promising analgesic peptide. Copyright © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  19. α-Dendrotoxin inhibits the ASIC current in dorsal root ganglion neurons from rat.

    Science.gov (United States)

    Báez, Adriana; Salceda, Emilio; Fló, Martín; Graña, Martín; Fernández, Cecilia; Vega, Rosario; Soto, Enrique

    2015-10-08

    Dendrotoxins are a group of peptide toxins purified from the venom of several mamba snakes. α-Dendrotoxin (α-DTx, from the Eastern green mamba Dendroaspis angusticeps) is a well-known blocker of voltage-gated K(+) channels and specifically of K(v)1.1, K(v)1.2 and K(v)1.6. In this work we show that α-DTx inhibited the ASIC currents in DRG neurons (IC50=0.8 μM) when continuously perfused during 25 s (including a 5 s pulse to pH 6.1), but not when co-applied with the pH drop. Additionally, we show that α-DTx abolished a transient component of the outward current that, in some experiments, appeared immediately after the end of the acid pulse. Our data indicate that α-DTx inhibits ASICs in the high nM range while some Kv are inhibited in the low nM range. The α-DTx selectivity and its potential interaction with ASICs should be taken in consideration when DTx is used in the high nM range. Copyright © 2015 Elsevier Ireland Ltd. All rights reserved.

  20. A Muscle Fibre Conduction Velocity Tracking ASIC for Local Fatigue Monitoring.

    Science.gov (United States)

    Koutsos, Ermis; Cretu, Vlad; Georgiou, Pantelis

    2016-12-01

    Electromyography analysis can provide information about a muscle's fatigue state by estimating Muscle Fibre Conduction Velocity (MFCV), a measure of the travelling speed of Motor Unit Action Potentials (MUAPs) in muscle tissue. MFCV better represents the physical manifestations of muscle fatigue, compared to the progressive compression of the myoelectic Power Spectral Density, hence it is more suitable for a muscle fatigue tracking system. This paper presents a novel algorithm for the estimation of MFCV using single threshold bit-stream conversion and a dedicated application-specified integrated circuit (ASIC) for its implementation, suitable for a compact, wearable and easy to use muscle fatigue monitor. The presented ASIC is implemented in a commercially available AMS 0.35 [Formula: see text] CMOS technology and utilizes a bit-stream cross-correlator that estimates the conduction velocity of the myoelectric signal in real time. A test group of 20 subjects was used to evaluate the performance of the developed ASIC, achieving good accuracy with an error of only 3.2% compared to Matlab.

  1. A new front-end ASIC for GEM detectors with time and charge measurement capabilities

    Science.gov (United States)

    Ciciriello, F.; Corsi, F.; De Robertis, G.; Felici, G.; Loddo, F.; Marzocca, C.; Matarrese, G.; Ranieri, A.

    2016-07-01

    A 32 channel CMOS front-end ASIC has been designed to read out the GEM detectors intended to be used for beam monitoring in a new proton-therapy facility currently under construction. In order to improve the spatial resolution by exploiting charge centroid algorithms, the analog channels, based on the classic CSA+shaper architecture, are equipped with a peak detector (PD) which works as an analog memory during the read-out phase. The outputs of the PDs are multiplexed towards an integrated 8-bit subranging ADC. An accurate trigger signal marks the arrival of a valid event and is generated by fast-ORing the outputs of 32 voltage discriminators which compare the shaper outputs with a programmable threshold. The digital part of the ASIC manages the read-out of the channels, the A/D conversion and the configuration of the ASIC. A 100 Mbit/s LVDS serial link is used for data communication. The sensitivity of the analog channel is 15 mV/fC and the dynamic range is 80 fC. The simulated ENC is about 650 e- for a detector capacitance of 10 pF.

  2. Active counter electrode in a-SiC electrochemical metallization memory

    Science.gov (United States)

    Morgan, K. A.; Fan, J.; Huang, R.; Zhong, L.; Gowers, R.; Ou, J. Y.; Jiang, L.; De Groot, C. H.

    2017-08-01

    Cu/amorphous-SiC (a-SiC) electrochemical metallization memory cells have been fabricated with two different counter electrode (CE) materials, W and Au, in order to investigate the role of CEs in a non-oxide semiconductor switching matrix. In a positive bipolar regime with Cu filaments forming and rupturing, the CE influences the OFF state resistance and minimum current compliance. Nevertheless, a similarity in SET kinetics is seen for both CEs, which differs from previously published SiO2 memories, confirming that CE effects are dependent on the switching layer material or type. Both a-SiC memories are able to switch in the negative bipolar regime, indicating Au and W filaments. This confirms that CEs can play an active role in a non-oxide semiconducting switching matrix, such as a-SiC. By comparing both Au and W CEs, this work shows that W is superior in terms of a higher R OFF/R ON ratio, along with the ability to switch at lower current compliances making it a favourable material for future low energy applications. With its CMOS compatibility, a-SiC/W is an excellent choice for future resistive memory applications.

  3. A new front-end ASIC for GEM detectors with time and charge measurement capabilities

    Energy Technology Data Exchange (ETDEWEB)

    Ciciriello, F., E-mail: fabio.ciciriello@poliba.it [DEI-Politecnico di Bari, Via Orabona 4, I-70125 Bari (Italy); INFN, Sezione di Bari, Via Orabona 4, I-70125 Bari (Italy); Corsi, F. [DEI-Politecnico di Bari, Via Orabona 4, I-70125 Bari (Italy); INFN, Sezione di Bari, Via Orabona 4, I-70125 Bari (Italy); De Robertis, G. [INFN, Sezione di Bari, Via Orabona 4, I-70125 Bari (Italy); Felici, G. [INFN, Laboratori Nazionali di Frascati, Via E. Fermi 40, I-00044 Frascati (Italy); Loddo, F. [INFN, Sezione di Bari, Via Orabona 4, I-70125 Bari (Italy); Marzocca, C.; Matarrese, G. [DEI-Politecnico di Bari, Via Orabona 4, I-70125 Bari (Italy); INFN, Sezione di Bari, Via Orabona 4, I-70125 Bari (Italy); Ranieri, A. [INFN, Sezione di Bari, Via Orabona 4, I-70125 Bari (Italy)

    2016-07-11

    A 32 channel CMOS front-end ASIC has been designed to read out the GEM detectors intended to be used for beam monitoring in a new proton-therapy facility currently under construction. In order to improve the spatial resolution by exploiting charge centroid algorithms, the analog channels, based on the classic CSA+shaper architecture, are equipped with a peak detector (PD) which works as an analog memory during the read-out phase. The outputs of the PDs are multiplexed towards an integrated 8-bit subranging ADC. An accurate trigger signal marks the arrival of a valid event and is generated by fast-ORing the outputs of 32 voltage discriminators which compare the shaper outputs with a programmable threshold. The digital part of the ASIC manages the read-out of the channels, the A/D conversion and the configuration of the ASIC. A 100 Mbit/s LVDS serial link is used for data communication. The sensitivity of the analog channel is 15 mV/fC and the dynamic range is 80 fC. The simulated ENC is about 650 e{sup −} for a detector capacitance of 10 pF. © 2001 Elsevier Science. All rights reserved.

  4. Radiation Hardened Structured ASIC Platform for Rapid Chip Development for Very High Speed System on a Chip (SoC) and Complex Digital Logic Systems, Phase I

    Data.gov (United States)

    National Aeronautics and Space Administration — Radiation Hardened Application Specific Integrated Circuits (ASICs) provide for the highest performance, lowest power and size for Space Missions. In order to...

  5. Converter topologies and control

    Energy Technology Data Exchange (ETDEWEB)

    Rodriguez, Fernando; Qin, Hengsi; Chapman, Patrick

    2018-05-01

    An inverter includes a transformer that includes a first winding, a second winding, and a third winding, a DC-AC inverter electrically coupled to the first winding of the transformer, a cycloconverter electrically coupled to the second winding of the transformer, an active filter electrically coupled to the third winding of the transformer. The DC-AC inverter is adapted to convert the input DC waveform to an AC waveform delivered to the transformer at the first winding. The cycloconverter is adapted to convert an AC waveform received at the second winding of the transformer to the output AC waveform having a grid frequency of the AC grid. The active filter is adapted to sink and source power with one or more energy storage devices based on a mismatch in power between the DC source and the AC grid.

  6. Converting high boiling hydrocarbons

    Energy Technology Data Exchange (ETDEWEB)

    Terrisse, H; DuFour, L

    1929-02-12

    A process is given for converting high boiling hydrocarbons into low boiling hydrocarbons, characterized in that the high boiling hydrocarbons are heated to 200 to 500/sup 0/C in the presence of ferrous chloride and of such gases as hydrogen, water gas, and the like gases under a pressure of from 5 to 40 kilograms per square centimeter. The desulfurization of the hydrocarbons occurs simultaneously.

  7. Advanced converters and reactors

    International Nuclear Information System (INIS)

    Haefele, W.; Kessler, G.

    1984-01-01

    As Western Europe and most countries of the Asia-Pacific region (except Australia) have only small natural uranium resources, they must import nuclear fuel from the major uranium supplier countries. The introduction of advanced converter and breeder reactor technology allows a fuel utilization of a factor of 4 to 100 higher than with present low converters (LWRs) and will make uranium-importing countries less vulnerable to price jumps and supply stops in the uranium market. In addition, breeder-reactor technology will open up a potential that can cover world energy requirements for several thousand years. The enormous development costs of advanced converter and breeder technologies can probably be raised only by highly industrialized countries. Those highly industrialized countries that have little or no uranium resources (Western Europe, Japan) will probably be the first to introduce this advanced reactor technology on a commercial scale. A number of small countries and islands will need only small power reactors with inherent safety capabilities, especially in the beginning of their nuclear energy programs. For economic reasons, the fuel cycle services should come from large reprocessing centers of countries having sufficiently large nuclear power programs or from international fuel cycle centers. (author)

  8. Convertible bond valuation focusing on Chinese convertible bond market

    OpenAIRE

    Yang, Ke

    2010-01-01

    This paper mainly discusses the methods of valuation of convertible bonds in Chinese market. Different from common convertible bonds in European market, considering the complicate features of Chinese convertible bond, this paper represents specific pricing approaches for pricing convertible bonds with different provisions along with the increment of complexity of these provisions. More specifically, this paper represents the decomposing method and binomial tree method for pricing both of Non-...

  9. Development of n+-in-p planar pixel quadsensor flip-chipped with FE-I4 readout ASICs

    International Nuclear Information System (INIS)

    Unno, Y.; Hanagaki, K.; Hori, R.; Ikegami, Y.; Nakamura, K.; Takubo, Y.; Kamada, S.; Yamamura, K.; Yamamoto, H.; Takashima, R.; Tojo, J.; Kono, T.; Nagai, R.; Saito, S.; Sugibayashi, K.; Hirose, M.; Jinnouchi, O.; Sato, S.; Sawai, H.; Hara, K.

    2017-01-01

    We have developed flip-chip modules applicable to the pixel detector for the HL-LHC. New radiation-tolerant n + -in-p planar pixel sensors of a size of four FE-I4 application-specific integrated circuits (ASICs) are laid out in a 6-in wafer. Variation in readout connection for the pixels at the boundary of ASICs is implemented in the design of quadsensors. Bump bonding technology is developed for four ASICs onto one quadsensor. Both sensors and ASICs are thinned to 150 μm before bump bonding, and are held flat with vacuum chucks. Using lead-free SnAg solder bumps, we encounter deficiency with large areas of disconnected bumps after thermal stress treatment, including irradiation. Surface oxidation of the solder bumps is identified as a critical source of this deficiency after bump bonding trials, using SnAg bumps with solder flux, indium bumps, and SnAg bumps with a newly-introduced hydrogen-reflow process. With hydrogen-reflow, we establish flux-less bump bonding technology with SnAg bumps, appropriate for mass production of the flip-chip modules with thin sensors and thin ASICs.

  10. Petiroc and Citiroc: front-end ASICs for SiPM read-out and ToF applications

    International Nuclear Information System (INIS)

    Fleury, J; Ahmad, S; Callier, S; Taille, C de La; Seguin, N; Thienpont, D; Dulucq, F; Martin, G

    2014-01-01

    Petiroc and Citiroc are the two latest ASIC from Weeroc dedicated to SiPM read-out. Petiroc is a 16-channel front-end ASIC designed to readout silicon photomultipliers (SiPMs) for particle time-of-flight measurement applications. It combines a very fast and low-jitter trigger with an accurate charge measurement. Citiroc is a 32-channel front-end ASIC designed to readout silicon photo-multipliers (SiPM). It allows triggering down to 1/3 pe and provides the charge measurement with a good noise rejection. Moreover, Citiroc outputs the 32-channel triggers with a high accuracy (100 ps). Each channel of both ASICs combines a trigger path with an accurate charge measurement path. An adjustment of the SiPM high voltage is possible using a channel-by-channel input DAC. That allows a fine SiPM gain and dark noise adjustment at the system level to correct for the non-uniformity of SiPMs. Timing measurement down to 16 ps RMS jitter for Petiroc and 100 ps RMS for Citiroc is possible along with 1% linearity energy measurement up to 2500 pe. The power consumption is around 3.5 mW/channel for Petiroc and 3 mW/channel for Citiroc, excluding ASICs outing buffer

  11. Characterisation of a human acid-sensing ion channel (hASIC1a) endogenously expressed in HEK293 cells.

    Science.gov (United States)

    Gunthorpe, M J; Smith, G D; Davis, J B; Randall, A D

    2001-08-01

    Acid-sensing ion channels (ASICs) are a new and expanding family of proton-gated cation (Na+/Ca2+) channels that are widely expressed in sensory neurons and the central nervous system. Their distribution suggests that they may play a critical role in the sensation of the pain that accompanies tissue acidosis and may also be important in detecting the subtle pH variations that occur during neuronal signalling. Here, using whole-cell patch-clamp electrophysiology and reverse transcriptase-polymerase chain reaction (RT-PCR), we show that HEK293 cells, a commonly used cell line for the expression and characterisation of many ion channels, functionally express an endogenous proton-gated conductance attributable to the activity of human ASIC1a. These data therefore represent the first functional characterisation of hASIC1 and have many important implications for the use of HEK293 cells as a host cell system for the study of ASICs, vanilloid receptor-1 and any other proton-gated channel. With this latter point in mind we have devised a simple desensitisation strategy to selectively remove the contribution of hASIC1a from proton-gated currents recorded from HEK293 cells expressing vanilloid receptor-1.

  12. X-Y Converter Family

    DEFF Research Database (Denmark)

    Bhaskar, Mahajan Sagar; Sanjeevikumar, Padmanaban; Wheeler, Patrick

    2016-01-01

    A New breed of a buck boost converter, named as the XY converter family is proposed in this article. In the XY family, 16 topologies are presented which are highly suitable for renewable energy applications which require a high ratio of DC-DC converter; such as a photovoltaic multilevel inverter...... system, high voltage automotive applications and industrial drives. Compared to the traditional boost converter and existing recent converters, the proposed XY converter family has the ability to provide a higher output voltage by using less number of power devices and reactive components. Other distinct...... features of the XY converter family are i) Single control switch ii) Provide negative output voltage iii) Non-isolated topologies iv) High conversion ratio without making the use of high duty cycle and v) modular structure. XY family is compared with the recent high step-up converters and the detailed...

  13. Resonant power converters

    CERN Document Server

    Kazimierczuk, Marian K

    2012-01-01

    This book is devoted to resonant energy conversion in power electronics. It is a practical, systematic guide to the analysis and design of various dc-dc resonant inverters, high-frequency rectifiers, and dc-dc resonant converters that are building blocks of many of today's high-frequency energy processors. Designed to function as both a superior senior-to-graduate level textbook for electrical engineering courses and a valuable professional reference for practicing engineers, it provides students and engineers with a solid grasp of existing high-frequency technology, while acquainting them wit

  14. Cycloidal Wave Energy Converter

    Energy Technology Data Exchange (ETDEWEB)

    Stefan G. Siegel, Ph.D.

    2012-11-30

    This program allowed further advancing the development of a novel type of wave energy converter, a Cycloidal Wave Energy Converter or CycWEC. A CycWEC consists of one or more hydrofoils rotating around a central shaft, and operates fully submerged beneath the water surface. It operates under feedback control sensing the incoming waves, and converts wave power to shaft power directly without any intermediate power take off system. Previous research consisting of numerical simulations and two dimensional small 1:300 scale wave flume experiments had indicated wave cancellation efficiencies beyond 95%. The present work was centered on construction and testing of a 1:10 scale model and conducting two testing campaigns in a three dimensional wave basin. These experiments allowed for the first time for direct measurement of electrical power generated as well as the interaction of the CycWEC in a three dimensional environment. The Atargis team successfully conducted two testing campaigns at the Texas A&M Offshore Technology Research Center and was able to demonstrate electricity generation. In addition, three dimensional wave diffraction results show the ability to achieve wave focusing, thus increasing the amount of wave power that can be extracted beyond what was expected from earlier two dimensional investigations. Numerical results showed wave cancellation efficiencies for irregular waves to be on par with results for regular waves over a wide range of wave lengths. Using the results from previous simulations and experiments a full scale prototype was designed and its performance in a North Atlantic wave climate of average 30kW/m of wave crest was estimated. A full scale WEC with a blade span of 150m will deliver a design power of 5MW at an estimated levelized cost of energy (LCOE) in the range of 10-17 US cents per kWh. Based on the new results achieved in the 1:10 scale experiments these estimates appear conservative and the likely performance at full scale will

  15. A 58 nW ECG ASIC With Motion-Tolerant Heartbeat Timing Extraction for Wearable Cardiovascular Monitoring.

    Science.gov (United States)

    Da He, David; Sodini, Charles G

    2015-06-01

    An ASIC for wearable cardiovascular monitoring is implemented using a topology that takes advantage of the electrocardiogram's (ECG) waveform to replace the traditional ECG instrumentation amplifier, ADC, and signal processor with a single chip solution. The ASIC can extract heartbeat timings in the presence of baseline drift, muscle artifact, and signal clipping. The circuit can operate with ECGs ranging from the chest location to remote locations where the ECG magnitude is as low as 30 μV. Besides heartbeat detection, a midpoint estimation method can accurately extract the ECG R-wave timing, enabling the calculations of heart rate variability. With 58 nW of power consumption at 0.8 V supply voltage and 0.76 mm (2) of active die area in standard 0.18 μm CMOS technology, the ECG ASIC is sufficiently low power and compact to be suitable for long term and wearable cardiovascular monitoring applications under stringent battery and size constraints.

  16. ALTIROC0, a 20 pico-second time resolution ASIC for the ATLAS High Granularity Timing Detector (HGTD)

    CERN Document Server

    de la Taille, C.; Conforti, S.; Dinaucourt, P.; Martin-Chassard, G.; Seguin-Moreau, N.; Agapopoulou, C.; Makovec, N.; Serin, L.; Simion, S.

    2018-01-01

    ALTIROC0 is an 8-channel ASIC prototype designed to readout 1x1 or 2x2 mm^2 50 µm thick Low Gain Avalanche Diodes (LGAD) of the ATLAS High Granularity Timing Detector (HGTD). The targeted combined time resolution of the sensor and the readout electronics is 30 ps for one MIP. Each analog channel of the ASIC must exhibit an extremely low jitter to ensure this challenging time resolution, while keeping a low power consumption of 2 mW/channel. A “Time Over Threshold” and a “Constant Fraction Discriminator” architecture are integrated to correct for the time walk. Test bench measurements performed on the ASIC received in April 2017 are presented.

  17. A custom front-end ASIC for the readout and timing of 64 SiPM photosensors

    International Nuclear Information System (INIS)

    Bagliesi, M.G.; Avanzini, C.; Bigongiari, G.; Cecchi, R.; Kim, M.Y.; Maestro, P.; Marrocchesi, P.S.; Morsani, F.

    2011-01-01

    A new class of instruments - based on Silicon PhotoMultiplier (SiPM) photosensors - are currently under development for the next generation of Astroparticle Physics experiments in future space missions. A custom front-end ASIC (Application Specific Integrated Circuit) for the readout of 64 SiPM sensors was specified in collaboration with GM-IDEAS (Norway) that designed and manufactured the ASIC. Our group developed a custom readout board equipped with a 16 bit ADC for the digitization of both pulse height and time information. A time stamp, generated by the ASIC in correspondence of the threshold crossing time, is digitized and recorded for each channel. This allows to define a narrow time window around the physics event that reduces significantly the background due to the SiPM dark count rate. In this paper, we report on the preliminary test results obtained with the readout board prototype.

  18. Improved On-Chip Measurement of Delay in an FPGA or ASIC

    Science.gov (United States)

    Chen, Yuan; Burke, Gary; Sheldon, Douglas

    2007-01-01

    An improved design has been devised for on-chip-circuitry for measuring the delay through a chain of combinational logic elements in a field-programmable gate array (FPGA) or application-specific integrated circuit (ASIC). In the improved design, the delay chain does not include input and output buffers and is not configured as an oscillator. Instead, the delay chain is made part of the signal chain of an on-chip pulse generator. The duration of the pulse is measured on-chip and taken to equal the delay.

  19. TRP and ASIC channels mediate the antinociceptive effect of citronellyl acetate.

    Science.gov (United States)

    Rios, Emiliano Ricardo Vasconcelos; Rocha, Nayrton Flávio Moura; Carvalho, Alyne Mara Rodrigues; Vasconcelos, Leonardo Freire; Dias, Marília Leite; de Sousa, Damião Pergentino; de Sousa, Francisca Cléa Florenço; Fonteles, Marta Maria de França

    2013-05-25

    Citronellyl acetate (CAT), a monoterpene product of the secondary metabolism of plants, has been shown in the literature to possess several different biological activities. However, no antinociceptive abilities have yet been discussed. Here, we used acute pain animal models to describe the antinociceptive action of CAT. The acetic acid-induced writhing test and the paw-licking test, in which paw licking was induced by glutamate and formalin, were performed to evaluate the antinociceptive action of CAT and to determine the involvement of PKC, PKA, TRPV1, TRPA1, TRPM8 and ASIC in its antinociceptive mechanism. To do so, we induced paw-linking using agonists. CAT was administered intragastrically (25, 50, 75, 100 and 200 mg/kg), and the two higher doses caused antinociceptive effects in the acetic acid model; the highest dose reduced pain for 4h after it was administered (200 mg/kg). In the formalin test, two doses of CAT promoted antinociception in both the early and later phases of the test. The glutamate test showed that its receptors are involved in the antinociceptive mechanism of CAT. Pretreatment with CAT did not alter locomotor activity or motor coordination. In an investigation into the participation of TRP channels and ASICs in CAT's antinociceptive mechanism, we used capsaicin (2.2 μg/paw), cinnamaldehyde (10 mmol/paw), menthol (1.2 mmol/paw) and acidified saline (2% acetic acid, pH 1.98). The results showed that TRPV1, TRPM8 and ASIC, but not TRPA1, are involved in the antinociceptive mechanism. Finally, the involvement of PKC and PKA was also studied, and we showed that both play a role in the antinociceptive mechanism of CAT. The results of this work contribute information regarding the antinociceptive properties of CAT on acute pain and show that, at least in part, TRPV1, TRPM8, ASIC, glutamate receptors, PKC and PKA participate in CAT's antinociceptive mechanism. Copyright © 2013 Elsevier Ireland Ltd. All rights reserved.

  20. Transmitting Performance Evaluation of ASICs for CMUT-Based Portable Ultrasound Scanners

    DEFF Research Database (Denmark)

    Llimos Muntal, Pere; Diederichsen, Søren Elmin; Jørgensen, Ivan Harald Holger

    2017-01-01

    Portable ultrasound scanners (PUS) have, in recent years, raised a lot of attention, as they can potentially overcome some of the limitations of static scanners. However, PUS have a lot of design limitations including size and power consumption. These restrictions can compromise the image quality...... of the scanner. In order to overcome these restrictions, application specific integrated circuits (ASICs) are needed to implement the electronics. In this work, a comparative study of the transmitting performance of a capacitive micromachined ultrasonic transducer (CMUT) driven by a commercial generic ultrasound...

  1. The development of two ASIC's for a fast silicon strip detector readout system

    International Nuclear Information System (INIS)

    Christain, D.; Haldeman, M.; Yarema, R.; Zimmerman, T.; Newcomer, F.M.; VanBerg, R.

    1989-01-01

    A high speed, low noise readout system for silicon strip detectors is being developed for Fermilab E771, which will begin taking data in 1989. E771 is a fixed target experiment designed to study the production of B hadrons by an 800 GeV/c proton beam. The experimental apparatus consists of an open geometry magnetic spectrometer featuring good muon and electron identification and a 16000 channel silicon microstrip vertex detector. This paper reviews the design and prototyping of two application specific integrated circuits (ASIC's) an amplifier and a discriminator, which are being produced for the silicon strip detector readout system

  2. A 0.18 micrometer CMOS Thermopile Readout ASIC Immune to 50 MRAD Total Ionizing Dose (SI) and Single Event Latchup to 174MeV-cm(exp 2)/mg

    Science.gov (United States)

    Quilligan, Gerard T.; Aslam, Shahid; Lakew, Brook; DuMonthier, Jeffery J.; Katz, Richard B.; Kleyner, Igor

    2014-01-01

    Radiation hardened by design (RHBD) techniques allow commercial CMOS circuits to operate in high total ionizing dose and particle fluence environments. Our radiation hard multi-channel digitizer (MCD) ASIC (Figure 1) is a versatile analog system on a chip (SoC) fabricated in 180nm CMOS. It provides 18 chopper stabilized amplifier channels, a 16- bit sigma-delta analog-digital converter (SDADC) and an on-chip controller. The MCD was evaluated at Goddard Space Flight Center and Texas A&M University's radiation effects facilities and found to be immune to single event latchup (SEL) and total ionizing dose (TID) at 174 MeV-cm(exp 2)/mg and 50 Mrad (Si) respectively.

  3. High-density expression of Ca2+-permeable ASIC1a channels in NG2 glia of rat hippocampus.

    Directory of Open Access Journals (Sweden)

    Yen-Chu Lin

    Full Text Available NG2 cells, a fourth type of glial cell in the mammalian CNS, undergo reactive changes in response to a wide variety of brain insults. Recent studies have demonstrated that neuronally expressed acid-sensing ion channels (ASICs are implicated in various neurological disorders including brain ischemia and seizures. Acidosis is a common feature of acute neurological conditions. It is postulated that a drop in pH may be the link between the pathological process and activation of NG2 cells. Such postulate immediately prompts the following questions: Do NG2 cells express ASICs? If so, what are their functional properties and subunit composition? Here, using a combination of electrophysiology, Ca2+ imaging and immunocytochemistry, we present evidence to demonstrate that NG2 cells of the rat hippocampus express high density of Ca2+-permeable ASIC1a channels compared with several types of hippocampal neurons. First, nucleated patch recordings from NG2 cells revealed high density of proton-activated currents. The magnitude of proton-activated current was pH dependent, with a pH for half-maximal activation of 6.3. Second, the current-voltage relationship showed a reversal close to the equilibrium potential for Na+. Third, psalmotoxin 1, a blocker specific for the ASIC1a channel, largely inhibited proton-activated currents. Fourth, Ca2+ imaging showed that activation of proton-activated channels led to an increase of [Ca2+]i. Finally, immunocytochemistry showed co-localization of ASIC1a and NG2 proteins in the hippocampus. Thus the acid chemosensor, the ASIC1a channel, may serve for inducing membrane depolarization and Ca2+ influx, thereby playing a crucial role in the NG2 cell response to injury following ischemia.

  4. Specification of requirements for the implementation of ASICs and FPGA in instrumentation and control systems important to safety in German NPPs

    International Nuclear Information System (INIS)

    Schnurer, G.

    2007-01-01

    This paper gives an overview concerning the design as well as the verification and validation of Application Specific Integrated Circuits (ASICs) and Field Programmable Gate Arrays (FPGA) in German NPPs which are applied to carry out I and C functions. The qualification procedures dealt with restricted on ASICs without any microcontroller core. Dependent on the different safety categories, recommendations concerning the qualification level and procedures are elaborated which have to be achieved for ASICs and FPGA. Important aspects within the framework of the expert judgement for upgrading of safety relevant I and C by ASICs and FPGA are dealt with. These aspects are of general character and are mainly focused on suitability test procedures and robustness requirements of ASICs and FPGA

  5. Gas converter. Gaswandler

    Energy Technology Data Exchange (ETDEWEB)

    Eisenmann, A

    1984-09-27

    A gas converter is proposed for carbonisation gas containing hydrocarbons, consisting of a bricked shaft, which has a free combustion chamber and a solid bed of bulk grainy material with partly burnt hot carbonisation gases flowing through it as the lower boundary of this combustion chamber, in the upper part of which a hot reaction zone at about 1000 to 1200/sup 0/C is formed and which has a cracked gas extraction below the solid bed and an ash outlet. The solid bed is arranged at an angle to the vertical. The shaft has a solid material outlet for the bed material no longer capable of taking part in the reaction on the wall going obliquely downwards and a solid material inlet for new bulk bed material on the opposite wall going obliquely upwards.

  6. Electromagnetic wave energy converter

    Science.gov (United States)

    Bailey, R. L. (Inventor)

    1973-01-01

    Electromagnetic wave energy is converted into electric power with an array of mutually insulated electromagnetic wave absorber elements each responsive to an electric field component of the wave as it impinges thereon. Each element includes a portion tapered in the direction of wave propagation to provide a relatively wideband response spectrum. Each element includes an output for deriving a voltage replica of the electric field variations intercepted by it. Adjacent elements are positioned relative to each other so that an electric field subsists between adjacent elements in response to the impinging wave. The electric field results in a voltage difference between adjacent elements that is fed to a rectifier to derive dc output power.

  7. Power converters for ITER

    CERN Document Server

    Benfatto, I

    2006-01-01

    The International Thermonuclear Experimental Reactor (ITER) is a thermonuclear fusion experiment designed to provide long deuterium– tritium burning plasma operation. After a short description of ITER objectives, the main design parameters and the construction schedule, the paper describes the electrical characteristics of the French 400 kV grid at Cadarache: the European site proposed for ITER. Moreover, the paper describes the main requirements and features of the power converters designed for the ITER coil and additional heating power supplies, characterized by a total installed power of about 1.8 GVA, modular design with basic units up to 90 MVA continuous duty, dc currents up to 68 kA, and voltages from 1 kV to 1 MV dc.

  8. The interaction between the first transmembrane domain and the thumb of ASIC1a is critical for its N-glycosylation and trafficking.

    Directory of Open Access Journals (Sweden)

    Lan Jing

    Full Text Available Acid-sensing ion channel-1a (ASIC1a, the primary proton receptor in the brain, contributes to multiple diseases including stroke, epilepsy and multiple sclerosis. Thus, a better understanding of its biogenesis will provide important insights into the regulation of ASIC1a in diseases. Interestingly, ASIC1a contains a large, yet well organized ectodomain, which suggests the hypothesis that correct formation of domain-domain interactions at the extracellular side is a key regulatory step for ASIC1a maturation and trafficking. We tested this hypothesis here by focusing on the interaction between the first transmembrane domain (TM1 and the thumb of ASIC1a, an interaction known to be critical in channel gating. We mutated Tyr71 and Trp287, two key residues involved in the TM1-thumb interaction in mouse ASIC1a, and found that both Y71G and W287G decreased synaptic targeting and surface expression of ASIC1a. These defects were likely due to altered folding; both mutants showed increased resistance to tryptic cleavage, suggesting a change in conformation. Moreover, both mutants lacked the maturation of N-linked glycans through mid to late Golgi. These data suggest that disrupting the interaction between TM1 and thumb alters ASIC1a folding, impedes its glycosylation and reduces its trafficking. Moreover, reducing the culture temperature, an approach commonly used to facilitate protein folding, increased ASIC1a glycosylation, surface expression, current density and slowed the rate of desensitization. These results suggest that correct folding of extracellular ectodomain plays a critical role in ASIC1a biogenesis and function.

  9. Integrated power electronic converters and digital control

    CERN Document Server

    Emadi, Ali; Nie, Zhong

    2009-01-01

    Non-isolated DC-DC ConvertersBuck ConverterBoost ConverterBuck-Boost ConverterIsolated DC-DC ConvertersFlyback ConverterForward ConverterPush-Pull ConverterFull-Bridge ConverterHalf-Bridge ConverterPower Factor CorrectionConcept of PFCGeneral Classification of PFC CircuitsHigh Switching Frequency Topologies for PFCApplication of PFC in Advanced Motor DrivesIntegrated Switched-Mode Power ConvertersSwitched-Mode Power SuppliesThe Concept of Integrated ConverterDefinition of Integrated Switched-Mode Power Supplies (ISMPS)Boost-Type Integrated TopologiesGeneral Structure of Boost-Type Integrated T

  10. The TDCpix Readout ASIC: A 75 ps Resolution Timing Front-End for the Gigatrackerof theNA62 Experiment

    Science.gov (United States)

    Rinella, G. Aglieri; Fiorini, M.; Jarron, P.; Kaplon, J.; Kluge, A.; Martin, E.; Morel, M.; Noy, M.; Perktold, L.; Poltorak, K.

    NA62 is an experiment under development at the CERN Super Proton Synchrotron, aiming at measuring ultra rare kaon decays. The Gigatracker (GTK) detector shall combine on-beam tracking of individual particles with a time resolution of 150 ps rms. The peak flow of particles crossing the detector modules reaches 1.27 MHz/mm2 fora total rateof about 0.75 GHz.Ahybrid siliconpixel detectoris beingdevelopedto meet these requirements. The pixel chip for the Gigatracker (TDCpix) is under design. The TDCpix chip will feature 1800 square pixels of 300×300 μm2 arranged in a matrix of 45 rows × 40 columns. Bump-bonded to a silicon pixel sensor it shall perform time stamping of particle hits with a timing accuracybetter than 200 ps rms and a detection efficiencyabove 99%. The chosen architecture provides full separation of the sensitive analog amplifiers of the pixel matrix from the noisy digital circuits of the TDCs and of the readout blocks. Discriminated hit signals from each pixel are transmitted to the end of column region. An array ofTime to Digital Converters (TDC) is implemented at the bottom of the pixel array. The TDCs are based on time tagging the events with the fine time codes generated by Delay Locked Loops (DLL) and have a nominal time bin of ˜100 ps. Time stamps and time-over-threshold are recorded for each discriminated hit and the correction of the discriminator's time-walk is performed off-detector. Data are continuously transmitted on four 2.4 Gb/s serial output links. Adescription of the on-going design of the final TDCpix is given in this paper. Design choices and some technical implementation details are presented. Aprototype ASIC including thekeycomponents of this architecture has been manufactured. The achievement of specification figures such as a time resolution of the processing chain of 75 ps rms as well as charged particle time stampingwitha resolutionbetterthan200psrmswere demonstratedexperimentally.Asummaryoftheseresultsisalso presented in

  11. The H1 SPACAL time-to-digital converter system

    International Nuclear Information System (INIS)

    Eisenhandler, E.; Landon, M.; Thompson, G.

    1995-01-01

    This paper describes a pipelined 1,400-channel Time-to-Digital Converter (TDC) system for the H1 Scintillating Fiber Calorimeter, which will soon be installed in the H1 experiment at DESY. The main task of the TDC system is to determine the time of arrival of energy depositions, and send this information from bunch crossings that satisfy the event trigger into the H1 data acquisition system. In addition, the TDC system must monitor the timing trigger, which vetoes bunch crossings that contain too much background energy. Products of the interaction are separated from background on the basis of their different times of arrival with respect to the bunch crossing clock. For this monitoring the TDC system uses automatic on-board histogramming hardware that produces a family of histograms for each of 1,400 channels. The TDC function is performed by the TMC1004 ASIC. The system digitizes over a range of 32ns per bunch crossing with 1ns bins and a precision of 1ns. Because of the way the TMC1004 is designed, it is possible to vary the size of the bins between 0.6ns and 3ns by trading off measurement range for bin size. The system occupies two 9U VME crates

  12. Conformational dynamics and role of the acidic pocket in ASIC pH-dependent gating.

    Science.gov (United States)

    Vullo, Sabrina; Bonifacio, Gaetano; Roy, Sophie; Johner, Niklaus; Bernèche, Simon; Kellenberger, Stephan

    2017-04-04

    Acid-sensing ion channels (ASICs) are proton-activated Na + channels expressed in the nervous system, where they are involved in learning, fear behaviors, neurodegeneration, and pain sensation. In this work, we study the role in pH sensing of two regions of the ectodomain enriched in acidic residues: the acidic pocket, which faces the outside of the protein and is the binding site of several animal toxins, and the palm, a central channel domain. Using voltage clamp fluorometry, we find that the acidic pocket undergoes conformational changes during both activation and desensitization. Concurrently, we find that, although proton sensing in the acidic pocket is not required for channel function, it does contribute to both activation and desensitization. Furthermore, protonation-mimicking mutations of acidic residues in the palm induce a dramatic acceleration of desensitization followed by the appearance of a sustained current. In summary, this work describes the roles of potential pH sensors in two extracellular domains, and it proposes a model of acidification-induced conformational changes occurring in the acidic pocket of ASIC1a.

  13. Multiplexed detection of cardiac biomarkers in serum with nanowire arrays using readout ASIC.

    Science.gov (United States)

    Zhang, Guo-Jun; Chai, Kevin Tshun Chuan; Luo, Henry Zhan Hong; Huang, Joon Min; Tay, Ignatius Guang Kai; Lim, Andy Eu-Jin; Je, Minkyu

    2012-05-15

    Early detection of cardiac biomarkers for diagnosis of heart attack is the key to saving lives. Conventional method of detection like the enzyme-linked immunosorbent assay (ELISA) is time consuming and low in sensitivity. Here, we present a label-free detection system consisting of an array of silicon nanowire sensors and an interface readout application specific integrated circuit (ASIC). This system provides a rapid solution that is highly sensitive and is able to perform direct simultaneous-multiplexed detection of cardiac biomarkers in serum. Nanowire sensor arrays were demonstrated to have the required selectivity and sensitivity to perform multiplexed detection of 100 fg/ml troponin T, creatine kinase MM, and creatine kinase MB in serum. A good correlation between measurements from a probe station and the readout ASIC was obtained. Our detection system is expected to address the existing limitations in cardiac health management that are currently imposed by the conventional testing platform, and opens up possibilities in the development of a miniaturized device for point-of-care diagnostic applications. Copyright © 2012 Elsevier B.V. All rights reserved.

  14. A low power biomedical signal processor ASIC based on hardware software codesign.

    Science.gov (United States)

    Nie, Z D; Wang, L; Chen, W G; Zhang, T; Zhang, Y T

    2009-01-01

    A low power biomedical digital signal processor ASIC based on hardware and software codesign methodology was presented in this paper. The codesign methodology was used to achieve higher system performance and design flexibility. The hardware implementation included a low power 32bit RISC CPU ARM7TDMI, a low power AHB-compatible bus, and a scalable digital co-processor that was optimized for low power Fast Fourier Transform (FFT) calculations. The co-processor could be scaled for 8-point, 16-point and 32-point FFTs, taking approximate 50, 100 and 150 clock circles, respectively. The complete design was intensively simulated using ARM DSM model and was emulated by ARM Versatile platform, before conducted to silicon. The multi-million-gate ASIC was fabricated using SMIC 0.18 microm mixed-signal CMOS 1P6M technology. The die area measures 5,000 microm x 2,350 microm. The power consumption was approximately 3.6 mW at 1.8 V power supply and 1 MHz clock rate. The power consumption for FFT calculations was less than 1.5 % comparing with the conventional embedded software-based solution.

  15. A 130 nm ASIC prototype for the NA62 Gigatracker readout

    CERN Document Server

    Dellacasa, G; Wheadon, R; Mazza, G; Rivetti, A; Marchetto, F; Garbolino, S

    2011-01-01

    One of the most challenging detectors of the NA62 experiment is the silicon tracker, called Gigatracker. It consists of three hybrid silicon pixel stations, each one covering an area of 27 mm x 60 mm. While the maximum pixel size is fairly large, 300 mu m x 300 mu m the system has to sustain a very high particle rate, 1.5 MHz/mm(2), which corresponds to 800 MHz for each station. To obtain an efficient tracking with such a high rate the required track timing resolution is 150 ps (rms). Therefore the front-end ASIC should provide for each pixel a 200 Ps time measurement capability, thus leading to the requirement of time walk compensation and very compact TDCs. Moreover, Single Event Upset protection has to be implemented in order to protect the digital circuitry. An ASIC prototype has been realized in CMOS 130 nm technology, containing three pixel columns. The chip performs the time walk compensation by a Constant Fraction Discriminator circuit, while the time measurement is performed by a Time to Amplitude Co...

  16. A low-power high dynamic range front-end ASIC for imaging calorimeters

    CERN Document Server

    Bagliesi, M G; Marrocchesi, P S; Meucci, M; Millucci, V; Morsani, F; Paoletti, R; Pilo, F; Scribano, A; Turini, N; Valle, G D

    2002-01-01

    High granularity calorimeters with shower imaging capabilities require dedicated front-end electronics. The ICON 4CH and VA4 PMT chip-set is suitable for very high dynamic range systems with strict noise requirements. The ICON 4CH is a 4 channel input, 12 channel output ASIC designed for use in a multi-anode photomultiplier system with very large dynamic range and low-noise requirements. Each of the four input signals to the ASIC is split equally into three branches by a current conveyor. Each of the three branches is scaled differently: 1:1, 1:8 and 1:80. The signal is read out by a 12 channel low noise/low power high dynamic range charge sensitive preamplifier-shaper circuit (VA4-PMT chip), with simultaneous sample- and-hold, multiplexed analog read-out, calibration facilities. Tests performed in our lab with a PMT are reported in terms of linearity, dynamic range and cross-talk of the system. (5 refs).

  17. Performance of the First Version of VMM Front-End ASIC with Resistive Micromegas Detectors

    CERN Document Server

    The ATLAS collaboration

    2014-01-01

    This note describes the performance of the first version of a front end ASIC, VMM1, being developed for the Micromegas and sTGC detectors of the ATLAS New Small Wheel (NSW) upgrade. The VMM1 ASIC was designed by the micro-electronics group of the Instrumentation Division of Brookhaven National Laboratory. It contains 64-channels of linear, low noise amplifiers with adaptive feedback, charge amplitude peak detectors with time stamp. It can accept inputs of both polarities, features selectable gain and shaping time and has a built-in calibration system. It is designed to operate with micro-pattern gas detectors providing both trigger and tracking information. The VMM1 was tested during August 2012 test beam campaign at SPS/H6 beam line at CERN using micromegas detectors of the Muon ATLAS MicroMega Activity R&D program. We present here the VMM1 configuration, the software that was developed to achieve its operation, as well as the calibration procedure. Furthermore, we present the analysis performed with the...

  18. Implementation of the ASDBLR straw tube readout ASIC in DMILL technology

    CERN Document Server

    Dressnandt, N; Newcomer, F M; Van Berg, R; Williams, H H

    2001-01-01

    The ASDBLR ASIC provides eight channels of low noise, low power, high rate on-detector readout suitable for the ATLAS Transition Radiation Tracker (TRT) at the LHC. The TRT's unprecedented wire chamber readout requirements of a maximum hit rate per wire of 20MHz and double pulse resolution of similar to 25ns with position resolution of better than 150mum in a high radiation environment have been addressed in the design of the ASDBLR. A carefully tuned ion tail cancellation stage followed by an output sensing baseline restorer implemented in differential structures provides robust signal processing combination compatible with the realities of ASIC design. Two comparators track the output of the signal processing stage to provide Tracking information from charged particles and evidence of higher energy Transition Radiation (TR) photons; their outputs are summed as current steps to form a differential ternary output. The ten year total dose requirement for neutrons of 10**1**4 n/cm**2 and 1.5 MRad of ionizing ra...

  19. Hydrogenated amorphous silicon sensors based on thin film on ASIC technology

    CERN Document Server

    Despeisse, M; Anelli, G; Jarron, P; Kaplon, J; Rusack, R; Saramad, S; Wyrsch, N

    2006-01-01

    The performance and limitations of a novel detector technology based on the deposition of a thin-film sensor on top of processed integrated circuits have been studied. Hydrogenated amorphous silicon (a-Si:H) films have been deposited on top of CMOS circuits developed for these studies and the resulting "thin-film on ASIC" (TFA) detectors are presented. The leakage current of the a-Si:H sensor at high reverse biases turns out to be an important parameter limiting the performance of a TFA detector. Its detailed study and the pixel segmentation of the detector are presented. High internal electric fields (in the order of 10/sup 4/-10/sup 5/ V/cm) can be built in the a-Si:H sensor and overcome the low mobility of electrons and holes in a-Si:H. Signal induction by generated carrier motion and speed in the a-Si:H sensor have been studied with a 660 nm pulsed laser on a TFA detector based on an ASIC integrating 5 ns peaking time pre- amplifiers. The measurement set-up also permits to study the depletion of the senso...

  20. A tripolar current-steering stimulator ASIC for field shaping in deep brain stimulation.

    Science.gov (United States)

    Valente, Virgilio; Demosthenous, Andreas; Bayford, Richard

    2012-06-01

    A significant problem with clinical deep brain stimulation (DBS) is the high variability of its efficacy and the frequency of side effects, related to the spreading of current beyond the anatomical target area. This is the result of the lack of control that current DBS systems offer on the shaping of the electric potential distribution around the electrode. This paper presents a stimulator ASIC with a tripolar current-steering output stage, aiming at achieving more selectivity and field shaping than current DBS systems. The ASIC was fabricated in a 0.35-μ m CMOS technology occupying a core area of 0.71 mm(2). It consists of three current sourcing/sinking channels. It is capable of generating square and exponential-decay biphasic current pulses with five different time constants up to 28 ms and delivering up to 1.85 mA of cathodic current, in steps of 4 μA, from a 12 V power supply. Field shaping was validated by mapping the potential distribution when injecting current pulses through a multicontact DBS electrode in saline.

  1. Upgrading FLIR NanoRaider with the next Generation of CdZnTe Detectors. Goal - Integrate VFG detectors into FLIR R200. Advanced Virtual Grid ASIC (AVG-ASIC).

    Energy Technology Data Exchange (ETDEWEB)

    Bolotnikov, Aleksey [Brookhaven National Lab. (BNL), Upton, NY (United States); Cui, Yonggang [Brookhaven National Lab. (BNL), Upton, NY (United States); Vernon, Emerson [Brookhaven National Lab. (BNL), Upton, NY (United States); De Geronimo, Gianluigi [Brookhaven National Lab. (BNL), Upton, NY (United States)

    2016-06-01

    This document presents motivations, goals and the current status of this project; development (fabrication, performance) of position-sensitive virtual Frisch-grid detectors proposed for nanoRaider, an instrument commonly used by nuclear inspectors; ASIC developments for CZT detectors; and the electronics development for the detector prototype..

  2. Impedance Source Power Electronic Converters

    DEFF Research Database (Denmark)

    Liu, Yushan; Abu-Rub, Haitham; Ge, Baoming

    Impedance Source Power Electronic Converters brings together state of the art knowledge and cutting edge techniques in various stages of research related to the ever more popular impedance source converters/inverters. Significant research efforts are underway to develop commercially viable...... and technically feasible, efficient and reliable power converters for renewable energy, electric transportation and for various industrial applications. This book provides a detailed understanding of the concepts, designs, controls, and application demonstrations of the impedance source converters/inverters. Key...... features: Comprehensive analysis of the impedance source converter/inverter topologies, including typical topologies and derived topologies. Fully explains the design and control techniques of impedance source converters/inverters, including hardware design and control parameter design for corresponding...

  3. Impedance source power electronic converters

    CERN Document Server

    Liu, Yushan; Ge, Baoming; Blaabjerg, Frede; Ellabban, Omar; Loh, Poh Chiang

    2016-01-01

    Impedance Source Power Electronic Converters brings together state of the art knowledge and cutting edge techniques in various stages of research related to the ever more popular impedance source converters/inverters. Significant research efforts are underway to develop commercially viable and technically feasible, efficient and reliable power converters for renewable energy, electric transportation and for various industrial applications. This book provides a detailed understanding of the concepts, designs, controls, and application demonstrations of the impedance source converters/inverters. Key features: Comprehensive analysis of the impedance source converter/inverter topologies, including typical topologies and derived topologies. Fully explains the design and control techniques of impedance source converters/inverters, including hardware design and control parameter design for corresponding control methods. Presents the latest power conversion solutions that aim to advance the role of pow...

  4. Pilot tests of a PET detector using the TOF-PET ASIC based on monolithic crystals and SiPMs

    International Nuclear Information System (INIS)

    Aguilar, A.; González-Montoro, A.; González, A.J.; Hernández, L.; Monzó, J.M.; Benlloch, J.M.; Bugalho, R.; Ferramacho, L.

    2016-01-01

    In this work we show pilot tests of PET detector blocks using the TOF-PET ASIC, coupled to SiPM detector arrays and different crystal configurations. We have characterized the main ASIC features running calibration processes to compensate the time dispersion among the different ASIC/SiPM paths as well as for the time walk on the arrival of optical photons. The aim of this work is to use of LYSO monolithic crystals and explore their photon Depth of Interaction (DOI) capabilities, keeping good energy and spatial resolutions. First tests have been carried out with crystal arrays. Here we made it possible to reach a coincidence resolving times (CRT) of 370 ps FWHM, with energy resolutions better than 20% and resolving well 2 mm sized crystal elements. When using monolithic crystals, a single-pixel LYSO reference crystal helped to explore the CRT performance. We studied different strategies to provide the best timestamp determination in the monolithic scintillator. Times around 1 ns FWHM have been achieved in these pilot studies. In terms of spatial and energy resolution, values of about 3 mm and better than 30% were found, respectively. We have also demonstrated the capability of this system (monolithic and ASIC) to return accurate DOI information.

  5. Design of low noise front-end ASIC and DAQ system for CdZnTe detector

    International Nuclear Information System (INIS)

    Luo Jie; Deng Zhi; Liu Yinong

    2012-01-01

    A low noise front-end ASIC has been designed for CdZnTe detector. This chip contains 16 channels and each channel consists of a dual-stage charge sensitive preamplifier, 4th order semi-Gaussian shaper, leakage current compensation (LCC) circuit, discriminator and output buffer. This chip has been fabricated in Chartered 0.35 μm CMOS process, the preliminary results show that it works well. The total channel charge gain can be adjusted from 100 mV/fC to 400 mV/fC and the peaking time can be adjusted from 1 μs to 4 μs. The minimum measured ENC at zero input capacitance is 70 e and minimum noise slope is 20 e/pF. The peak detector and derandomizer (PDD) ASIC developed by BNL and an associated USB DAQ board are also introduced in this paper. Two front-end ASICs can be connected to the PDD ASIC on the USB DAQ board and compose a 32 channels DAQ system for CdZnTe detector. (authors)

  6. A front end ASIC for the readout of the PMT in the KM3NeT detector

    International Nuclear Information System (INIS)

    Gajanana, D; Gromov, V; Timmer, P; Heine, E; Kluit, R

    2010-01-01

    In this work, we describe the front end ASIC to readout the Photo-Multiplier-Tube of the KM3NeT detector, in detail. Stringent power budgeting, area constraints and lowering cost motivate us to design a custom front-end ASIC for reading the PMT. The ASIC amplifies the PMT signal and discriminates it against a threshold level and delivers the information via low voltage differential signals (LVDS). These LVDS signals carry highly accurate timing information of the photons . The length of the LVDS signals or Time over Threshold (ToT) gives information on the number of detected photons. A one-time programmable read-only memory (PROM) block provides unique identification to the chip. The chip communicates with the data acquisition electronics via an I 2 C bus. The data is transmitted to shore via fiber optics, where processing is done. The ASIC was fabricated in 0.35u CMOS process from AustriaMicroSystems (AMS).

  7. FMRFamide-gated sodium channel and ASIC channels: a new class of ionotropic receptors for FMRFamide and related peptides.

    Science.gov (United States)

    Lingueglia, Eric; Deval, Emmanuel; Lazdunski, Michel

    2006-05-01

    FMRFamide and related peptides typically exert their action through G-protein coupled receptors. However, two ionotropic receptors for these peptides have recently been identified. They are both members of the epithelial amiloride-sensitive Na+ channel and degenerin (ENaC/DEG) family of ion channels. The invertebrate FMRFamide-gated Na+ channel (FaNaC) is a neuronal Na+-selective channel which is directly gated by micromolar concentrations of FMRFamide and related tetrapeptides. Its response is fast and partially desensitizing, and FaNaC has been proposed to participate in peptidergic neurotransmission. On the other hand, mammalian acid-sensing ion channels (ASICs) are not gated but are directly modulated by FMRFamide and related mammalian peptides like NPFF and NPSF. ASICs are activated by external protons and are therefore extracellular pH sensors. They are expressed both in the central and peripheral nervous system and appear to be involved in many physiological and pathophysiological processes such as hippocampal long-term potentiation and defects in learning and memory, acquired fear-related behavior, retinal function, brain ischemia, pain sensation in ischemia and inflammation, taste perception, hearing functions, and mechanoperception. The potentiation of ASIC activity by endogenous RFamide neuropeptides probably participates in the response to noxious acidosis in sensory and central neurons. Available data also raises the possibility of the existence of still unknown FMRFamide related endogenous peptides acting as direct agonists for ASICs.

  8. AIDA: A 16-channel amplifier ASIC to read out the advanced implantation detector array for experiments in nuclear decay spectroscopy

    Energy Technology Data Exchange (ETDEWEB)

    Braga, D. [STFC Rutherford Appleton Laboratory, Didcot, OX11 0QX (United Kingdom); Coleman-Smith, P. J. [STFC Daresbury Laboratory, Warrington WA4 4AD (United Kingdom); Davinson, T. [Dept. of Physics and Astronomy, Univ. of Edinburgh, Edinburgh EH9 3JZ (United Kingdom); Lazarus, I. H. [STFC Daresbury Laboratory, Warrington WA4 4AD (United Kingdom); Page, R. D. [Dept. of Physics, Univ. of Liverpool, Oliver Lodge Laboratory, Liverpool L69 7ZE (United Kingdom); Thomas, S. [STFC Rutherford Appleton Laboratory, Didcot, OX11 0QX (United Kingdom)

    2011-07-01

    We have designed a read-out ASIC for nuclear decay spectroscopy as part of the AIDA project - the Advanced Implantation Detector Array. AIDA will be installed in experiments at the Facility for Antiproton and Ion Research in GSI, Darmstadt. The AIDA ASIC will measure the signals when unstable nuclei are implanted into the detector, followed by the much smaller signals when the nuclei subsequently decay. Implant energies can be as high as 20 GeV; decay products need to be measured down to 25 keV within just a few microseconds of the initial implants. The ASIC uses two amplifiers per detector channel, one covering the 20 GeV dynamic range, the other selectable over a 20 MeV or 1 GeV range. The amplifiers are linked together by bypass transistors which are normally switched off. The arrival of a large signal causes saturation of the low-energy amplifier and a fluctuation of the input voltage, which activates the link to the high-energy amplifier. The bypass transistors switch on and the input charge is integrated by the high-energy amplifier. The signal is shaped and stored by a peak-hold, then read out on a multiplexed output. Control logic resets the amplifiers and bypass circuit, allowing the low-energy amplifier to measure the subsequent decay signal. We present simulations and test results, demonstrating the AIDA ASIC operation over a wide range of input signals. (authors)

  9. Design of front end electronics and a full scale 4k pixel readout ASIC for the DSSC X-ray detector at the European XFEL

    International Nuclear Information System (INIS)

    Erdinger, Florian

    2016-01-01

    The goal of this thesis was to design a large scale readout ASIC for the 1-Mega pixel DEPFET Sensor with Signal Compression (DSSC) detector system which is being developed by an international collaboration for the European XFEL (EuXFEL). Requirements for the DSSC detector include single photon detection down to 0.5 keV combined with a large dynamic range of up to 10000 photons at frame rates of up to 4.5 MHz. The detector core concepts include full parallel readout, signal compression on the sensor or ASIC level, filtering, immediate digitization and local storage within the pixel. The DSSC is a hybrid pixel detector, each sensor pixel mates to a dedicated ASIC pixel, which includes the entire specified signal processing chain along with auxiliary circuits. One ASIC comprises 4096 pixels and a full periphery including biasing and digital control. This thesis presents the design of the ASIC, its components and integration are described in detail. Emphasis is put on the design of the analog front-end. The first full format ASIC (F1) has been fabricated within the scope of this thesis along with numerous test chips. Furthermore, the EuXFEL and the DSSC detector system are presented to create the context for the ASIC, which is the core topic of this thesis.

  10. Design of front end electronics and a full scale 4k pixel readout ASIC for the DSSC X-ray detector at the European XFEL

    Energy Technology Data Exchange (ETDEWEB)

    Erdinger, Florian

    2016-11-22

    The goal of this thesis was to design a large scale readout ASIC for the 1-Mega pixel DEPFET Sensor with Signal Compression (DSSC) detector system which is being developed by an international collaboration for the European XFEL (EuXFEL). Requirements for the DSSC detector include single photon detection down to 0.5 keV combined with a large dynamic range of up to 10000 photons at frame rates of up to 4.5 MHz. The detector core concepts include full parallel readout, signal compression on the sensor or ASIC level, filtering, immediate digitization and local storage within the pixel. The DSSC is a hybrid pixel detector, each sensor pixel mates to a dedicated ASIC pixel, which includes the entire specified signal processing chain along with auxiliary circuits. One ASIC comprises 4096 pixels and a full periphery including biasing and digital control. This thesis presents the design of the ASIC, its components and integration are described in detail. Emphasis is put on the design of the analog front-end. The first full format ASIC (F1) has been fabricated within the scope of this thesis along with numerous test chips. Furthermore, the EuXFEL and the DSSC detector system are presented to create the context for the ASIC, which is the core topic of this thesis.

  11. Functional TRP and ASIC-like channels in cultured urothelial cells from the rat.

    Science.gov (United States)

    Kullmann, F Aura; Shah, M A; Birder, L A; de Groat, W C

    2009-04-01

    Transient receptor potential (TRP) and acid-sensing ion channels (ASIC) are molecular detectors of chemical, mechanical, thermal, and nociceptive stimuli in sensory neurons. They have been identified in the urothelium, a tissue considered part of bladder sensory pathways, where they might play a role in bladder function. This study investigated functional properties of TRP and ASIC channels in cultured urothelial cells from the rat using patch-clamp and fura 2 Ca(2+) imaging techniques. The TRPV4 agonist 4alpha-phorbol-12,13 didecanoate (4alpha-PDD; 1-5 microM) and the TRPA1/TRPM8 agonist icilin (50-100 microM) elicited transient currents in a high percentage of cells (>70%). 4alpha-PDD responses were suppressed by the TRPV4 antagonist HC-010961 (10 microM). The TRPV1 agonist capsaicin (1-100 microM) and the TRPA1/TRPM8 agonist menthol (5-200 microM) elicited transient currents in a moderate percentage of cells ( approximately 25%). All of these agonists increased intracellular calcium concentration ([Ca(2+)](i)). Most cells responded to more than one TRP agonist (e.g., capsaicin and 4alpha-PDD), indicating coexpression of different TRP channels. In the presence of the TRPV1 antagonist capsazepine (10 microM), changes in pH induced by HCl elicited ionic currents (pH 5.5) and increased [Ca(2+)](i) (pH 6.5) in approximately 50% of cells. Changes in pH using acetic acid (pH 5.5) elicited biphasic-like currents. Responses induced by acid were sensitive to amiloride (10 microM). In summary, urothelial cells express multiple TRP and ASIC channels, whose activation elicits ionic currents and Ca(2+) influx. These "neuron-like" properties might be involved in transmitter release, such as ATP, that can act on afferent nerves or smooth muscle to modulate their responses to different stimuli.

  12. Proposed electromagnetic wave energy converter

    Science.gov (United States)

    Bailey, R. L.

    1973-01-01

    Device converts wave energy into electric power through array of insulated absorber elements responsive to field of impinging electromagnetic radiation. Device could also serve as solar energy converter that is potentially less expensive and fragile than solar cells, yet substantially more efficient.

  13. Catalytic converters in the fireplace

    International Nuclear Information System (INIS)

    Kouki, J.

    1995-01-01

    In addition to selecting the appropriate means of heating and using dry fuel, the amount of harmful emissions contained by flue gases produced by fireplaces can be reduced by technical means. One such option is to use an oxidising catalytic converter. Tests at TTS Institute's Heating Studies Experimental Station have focused on two such converters (dense and coarse) mounted in light-weight iron heating stoves. The ability of the dense catalytic converter to oxidise carbon monoxide gases proved to be good. The concentration of carbon monoxide in the flue gases was reduced by as much as 90 %. Measurements conducted by VTT (Technical Research Centre of Finland) showed that the conversion of other gases, e.g. of methane, was good. The exhaust resistance caused by the dense converter was so great as to necessitate the mounting of a fluegas evacuation fan in the chimney for the purpose of creating sufficient draught. When relying on natural draught, the dense converter requires a chimney of at least 7 metres and a by-pass connection while the fire is being lit. In addition, the converter will have to be constructed to be less dense and this will mean that it's capability to oxidise non-combusted gases will be reduced. The coarse converter did not impair the draught but it's oxidising property was insufficient. With the tests over, the converter was not observed to have become blocked up by impurities

  14. Multilevel push pull power converter

    DEFF Research Database (Denmark)

    2007-01-01

    A power converter for converting an input voltage (Vin) into an output voltage (Vout), comprising a first supply potential and a second supply potential established by the input voltage, and at least one primary winding having two terminals, a center tap arranged between the two terminals and con...

  15. Very Low-Power Consumption Analog Pulse Processing ASIC for Semiconductor Radiation Detectors

    International Nuclear Information System (INIS)

    Wessendorf, K.O.; Lund, J.C.; Brunett, B.A.; Laguna, G.R.; Clements, J.W.

    1999-01-01

    We describe a very-low power consumption circuit for processing the pulses from a semiconductor radiation detector. The circuit was designed for use with a cadmium zinc telluride (CZT) detector for unattended monitoring of stored nuclear materials. The device is intended to be battery powered and operate at low duty-cycles over a long period of time. This system will provide adequate performance for medium resolution gamma-ray pulse-height spectroscopy applications. The circuit incorporates the functions of a charge sensitive preamplifier, shaping amplifier, and peak sample and hold circuit. An application specific integrated circuit (ASIC) version of the design has been designed, built and tested. With the exception of the input field effect transistor (FET), the circuit is constructed using bipolar components. In this paper the design philosophy and measured performance characteristics of the circuit are described

  16. Tarantula toxins use common surfaces for interacting with Kv and ASIC ion channels.

    Science.gov (United States)

    Gupta, Kanchan; Zamanian, Maryam; Bae, Chanhyung; Milescu, Mirela; Krepkiy, Dmitriy; Tilley, Drew C; Sack, Jon T; Yarov-Yarovoy, Vladimir; Kim, Jae Il; Swartz, Kenton J

    2015-05-07

    Tarantula toxins that bind to voltage-sensing domains of voltage-activated ion channels are thought to partition into the membrane and bind to the channel within the bilayer. While no structures of a voltage-sensor toxin bound to a channel have been solved, a structural homolog, psalmotoxin (PcTx1), was recently crystalized in complex with the extracellular domain of an acid sensing ion channel (ASIC). In the present study we use spectroscopic, biophysical and computational approaches to compare membrane interaction properties and channel binding surfaces of PcTx1 with the voltage-sensor toxin guangxitoxin (GxTx-1E). Our results show that both types of tarantula toxins interact with membranes, but that voltage-sensor toxins partition deeper into the bilayer. In addition, our results suggest that tarantula toxins have evolved a similar concave surface for clamping onto α-helices that is effective in aqueous or lipidic physical environments.

  17. ASIC design of a digital fuzzy system on chip for medical diagnostic applications.

    Science.gov (United States)

    Roy Chowdhury, Shubhajit; Roy, Aniruddha; Saha, Hiranmay

    2011-04-01

    The paper presents the ASIC design of a digital fuzzy logic circuit for medical diagnostic applications. The system on chip under consideration uses fuzzifier, memory and defuzzifier for fuzzifying the patient data, storing the membership function values and defuzzifying the membership function values to get the output decision. The proposed circuit uses triangular trapezoidal membership functions for fuzzification patients' data. For minimizing the transistor count, the proposed circuit uses 3T XOR gates and 8T adders for its design. The entire work has been carried out using TSMC 0.35 µm CMOS process. Post layout TSPICE simulation of the whole circuit indicates a delay of 31.27 ns and the average power dissipation of the system on chip is 123.49 mW which indicates a less delay and less power dissipation than the comparable embedded systems reported earlier.

  18. Radiation-induced effects on the XAA1.2 ASIC chip for space application

    Energy Technology Data Exchange (ETDEWEB)

    Del Monte, Ettore [Istituto di Astrofisica Spaziale e Fisica Cosmica, CNR, Roma, Via Fosso del Cavaliere 100, I-00133 Rome (Italy) and Dipartimento di Fisica, Universita di Roma ' Tor Vergata' , Via della Ricerca Scientifica 1, I-00133 Rome (Italy)]. E-mail: delmonte@rm.iasf.cnr.it; Pacciani, Luigi [Istituto di Astrofisica Spaziale e Fisica Cosmica, CNR, Roma, Via Fosso del Cavaliere 100, I-00133 Rome (Italy); Porrovecchio, Geiland [Istituto di Astrofisica Spaziale e Fisica Cosmica, CNR, Roma, Via Fosso del Cavaliere 100, I-00133 Rome (Italy); Soffitta, Paolo [Istituto di Astrofisica Spaziale e Fisica Cosmica, CNR, Roma, Via Fosso del Cavaliere 100, I-00133 Rome (Italy); Costa, Enrico [Istituto di Astrofisica Spaziale e Fisica Cosmica, CNR, Roma, Via Fosso del Cavaliere 100, I-00133 Rome (Italy); Di Persio, Giuseppe [Istituto di Astrofisica Spaziale e Fisica Cosmica, CNR, Roma, Via Fosso del Cavaliere 100, I-00133 Rome (Italy); Feroci, Marco [Istituto di Astrofisica Spaziale e Fisica Cosmica, CNR, Roma, Via Fosso del Cavaliere 100, I-00133 Rome (Italy); Mastropietro, Marcello [Istituto di Metodologie Inorganiche e dei Plasmi, CNR, Roma, Via Salaria km 29.300, I-00016 Monterotondo Scalo (RM) c.p. 10 (Italy); Morelli, Ennio [Istituto di Astrofisica Spaziale e Fisica Cosmica, CNR, Bologna, Via P. Gobetti 101, I-40129 Bologna (Italy); Rapisarda, Massimo [ENEA C.R. Frascati, Via Enrico Fermi 45, I-00044 Frascati, RM (Italy); Rubini, Alda [Istituto di Astrofisica Spaziale e Fisica Cosmica, CNR, Roma, Via Fosso del Cavaliere 100, I-00133 Rome (Italy); Bisello, Dario; Candelori, Andrea [Dipartimento di Fisica, Universita di Padova, INFN Sezione di Padova, Via Marzolo 8, I-35100 Padova (Italy); Kaminski, Alexandre [Dipartimento di Fisica, Universita di Padova, INFN Sezione di Padova, Via Marzolo 8, I-35100 Padova (Italy); Wyss, Jeffery [DIMSAT, Universita di Cassino, Via Di Biasio 43, I-03043 Cassino, FR (Italy)

    2005-02-11

    The XAA1.2 is a custom ASIC chip for space applications built using a 0.8{mu}m complementary metal oxide semiconductor technology on epitaxial layer. It has been selected as the front-end electronics chip of the SuperAGILE experiment on board the AGILE space mission, although it is not specifically designed as a radiation hard device. To study the XAA1.2 sensitivity to Single Event Effects and Total Dose Effects we irradiate this chip at the SIRAD facility of the Laboratori Nazionali INFN of Legnaro. In this paper we describe the experimental set-up and the measurements. We then discuss how the results can be scaled to the cosmic rays environment in a low-Earth orbit.

  19. The TDCPix ASIC: Tracking for the NA62 GigaTracker

    CERN Document Server

    Noy, Matthew; Bonacini, Sandro; Kaplon, Jan; Kluge, Alexander; Morel, Michel; Perktold, Lukas; Poltorak, Karolina

    2014-01-01

    The TDCPix is a hybrid pixel detector readout ASIC designed for the NA62 GigaTracker detec- tor. The asynchronously operating pixel array consists of 1800 pixels, each 300x300 m m 2 . The requirements are a single-hit timing resolution better than 200 ps RMS and a read-out efficiency of 99% or better in the presence of a beam rate between 800 MHz and 1 GHz . The discrimina- tor time walk effect is compensated by time-over-threshold discriminators connected to an array of 360 dual TDC channels. The TDCpix processes up to 210 Mhits = s and provides the hit data without the need of a trigger in a continuous data stream via four 3.2 Gb = s serialisers. Under test since January 2014, the TDCPix chip is fully functional and shows excellent performance.

  20. A high speed serializer ASIC for ATLAS Liquid Argon calorimeter upgrade

    CERN Document Server

    Liu, T; The ATLAS collaboration

    2014-01-01

    We have been developing a serializer application-specific integrated circuit (ASIC) based on a commercial 0.25-μm silicon-on-sapphire (SOS) CMOS technology for the ATLAS liquid argon calorimeter front-end electronics upgrade. The first prototype, a 5 Gbps 16:1 serializer has been designed, fabricated, and tested in lab environment and in 200 MeV proton beam. The test results indicate that the first prototype meets the design goals. The second prototype, a double-lane, 8 Gbps per lane serializer is under development. The post layout simulation indicates that 8 Gbps is achievable. In this paper we present the design and the test results of the first prototype and the design and status of the second prototype.

  1. Update on the high speed serializer ASIC development for ATLAS Liquid Argon calorimeter upgrade

    CERN Document Server

    Liu, T; The ATLAS collaboration

    2011-01-01

    We have been developing a serializer application-specific integrated circuit (ASIC) based on a commercial 0.25-μm silicon-on-sapphire (SOS) CMOS technology for the ATLAS liquid argon calorimeter front-end electronics upgrade. The first prototype, a 5 Gbps 16:1 serializer has been designed, fabricated, and tested in lab environment and in a 200 MeV proton beam. The test results indicate that the first prototype meets the design goals. The second prototype, a double-lane, 8 Gbps per lane serializer is under development. The post-layout simulation indicates that 8 Gbps is achievable. In this paper we present the design and the test results of the first prototype and the design and status of the second prototype.

  2. Radiation-induced effects on the XAA1.2 ASIC chip for space application

    International Nuclear Information System (INIS)

    Del Monte, Ettore; Pacciani, Luigi; Porrovecchio, Geiland; Soffitta, Paolo; Costa, Enrico; Di Persio, Giuseppe; Feroci, Marco; Mastropietro, Marcello; Morelli, Ennio; Rapisarda, Massimo; Rubini, Alda; Bisello, Dario; Candelori, Andrea; Kaminski, Alexandre; Wyss, Jeffery

    2005-01-01

    The XAA1.2 is a custom ASIC chip for space applications built using a 0.8μm complementary metal oxide semiconductor technology on epitaxial layer. It has been selected as the front-end electronics chip of the SuperAGILE experiment on board the AGILE space mission, although it is not specifically designed as a radiation hard device. To study the XAA1.2 sensitivity to Single Event Effects and Total Dose Effects we irradiate this chip at the SIRAD facility of the Laboratori Nazionali INFN of Legnaro. In this paper we describe the experimental set-up and the measurements. We then discuss how the results can be scaled to the cosmic rays environment in a low-Earth orbit

  3. SCOTT: A time and amplitude digitizer ASIC for PMT signal processing

    Science.gov (United States)

    Ferry, S.; Guilloux, F.; Anvar, S.; Chateau, F.; Delagnes, E.; Gautard, V.; Louis, F.; Monmarthe, E.; Le Provost, H.; Russo, S.; Schuller, J.-P.; Stolarczyk, Th.; Vallage, B.; Zonca, E.; KM3NeT Consortium

    2013-10-01

    SCOTT is an ASIC designed for the readout electronics of photomultiplier tubes developed for KM3NeT, the cubic-kilometer scale neutrino telescope in Mediterranean Sea. To digitize the PMT signals, the multi-time-over-threshold technique is used with up to 16 adjustable thresholds. Digital outputs of discriminators feed a circular sampling memory and a “first in first out” digital memory. A specific study has shown that five specifically chosen thresholds are suited to reach the required timing accuracy. A dedicated method based on the duration of the signal over a given threshold allows an equivalent timing precision at any charge. To verify that the KM3NeT requirements are fulfilled, this method is applied on PMT signals digitized by SCOTT.

  4. 4-channel rad-hard delay generation ASIC with 1ns timing resolution for LHC

    International Nuclear Information System (INIS)

    Toifl, T.; Moreira, P.; Marchioro, A.; Vari, R.

    1999-01-01

    An ASIC was developed to precisely delay digital signals within the range of 0--24ns in steps of 1ns. To obtain well defined delay values independent of variations in process, supply voltage and temperature, four independent delay channels are controlled by a common control voltage derived from a delay-locked loop (DLL), which is synchronized to an external 40 MHz clock signal. The delay values of the four signal channels and the clock channel can be individually programmed via an I 2 C interface. Due to an automatic reset logic the chip does not need an external reset signal. A first version of the chip was developed in a non-rad-hard 0.8 microm technology and the successful prototype was then transferred to a radiation hard process (DMILL). Measurement results for both chip variants will be presented

  5. Performance and future development of the ASDBLR ASIC for the ATLAS TRT

    CERN Document Server

    Bevensee, B E; Newcomer, F M; Tyrrell, B; Van Berg, R; Williams, H H; Romaniouk, A

    1998-01-01

    The ATLAS TRT straw tracker will consist of more than 420 K straw tubes filled with a Xenon-based fast gas located in a magnetic field of 2 T. Some tubes will operate at rates in excess of 20 MHz. Stringent signal processing goals $9 have been determined using both simulation tools and measurement standards set by hand tuned discrete component prototypes. These include the ability to detect the earliest clusters from ionizing tracks as well as energetic $9 transition radiation photons without baseline shifts in a low noise and low power design. We report on measurements of two ASIC's fabricated in different processes that appear to be capable of achieving these goals. (2 refs).

  6. Design of a readout ASIC for gas detectors with self-amplification

    International Nuclear Information System (INIS)

    Deng Zhi; Liu Yinong

    2009-01-01

    A readout ASIC has been designed for gas detectors with self-amplification such as GEM and RPC. It provides amplification and shaping of the detector signals and buffers them to the free running ADCs. The charge gain and the shaping time can be adjusted. The programmability of gain and shaping time is very convenient for studying detector performance under different gas gain and also expands the application range of the chip. The ENC increases as charge gain decreases below 10 mV/fC because the noise from the shaper becomes significant. The chip is designed in Chartered 0.35μm 2P4M CMOS process. Detailed design and simulation results are described in the paper. (authors)

  7. Highly Integrated MEMS-ASIC Sensing System for Intracorporeal Physiological Condition Monitoring.

    Science.gov (United States)

    Xue, Ning; Wang, Chao; Liu, Cunxiu; Sun, Jianhai

    2018-01-02

    In this paper, a highly monolithic-integrated multi-modality sensor is proposed for intracorporeal monitoring. The single-chip sensor consists of a solid-state based temperature sensor, a capacitive based pressure sensor, and an electrochemical oxygen sensor with their respective interface application-specific integrated circuits (ASICs). The solid-state-based temperature sensor and the interface ASICs were first designed and fabricated based on a 0.18-μm 1.8-V CMOS (complementary metal-oxide-semiconductor) process. The oxygen sensor and pressure sensor were fabricated by the standard CMOS process and subsequent CMOS-compatible MEMS (micro-electromechanical systems) post-processing. The multi-sensor single chip was completely sealed by the nafion, parylene, and PDMS (polydimethylsiloxane) layers for biocompatibility study. The size of the compact sensor chip is only 3.65 mm × 1.65 mm × 0.72 mm. The functionality, stability, and sensitivity of the multi-functional sensor was tested ex vivo. Cytotoxicity assessment was performed to verify that the bio-compatibility of the device is conforming to the ISO 10993-5:2009 standards. The measured sensitivities of the sensors for the temperature, pressure, and oxygen concentration are 10.2 mV/°C, 5.58 mV/kPa, and 20 mV·L/mg, respectively. The measurement results show that the proposed multi-sensor single chip is suitable to sense the temperature, pressure, and oxygen concentration of human tissues for intracorporeal physiological condition monitoring.

  8. NECTAr0, a new high speed digitizer ASIC for the Cherenkov telescope array

    International Nuclear Information System (INIS)

    Delagnes, E.; Glicenstein, J.F.; Guilloux, F.; Bolmont, J.; Corona, P.; Naumann, C.L.; Nayman, P.; Tavemet, J.P.; Toussenel, F.; Vincent, P.; Dzahini, D.; Rarbi, F.; Feinstein, F.; Vorobiov, S.; Gascon, D.; Sanuy, A.

    2011-01-01

    H.E.S.S. and MAGIC experiments have demonstrated the high level of maturity of Imaging Atmospheric Cherenkov Telescopes (IACTs) dedicated to very-high-energy gamma ray astronomy domain. The astro-particle physics community is preparing the next generation of instruments, with sensitivity improved by an order of magnitude in the 10 GeV to 100 TeV range. To reach this goal, the Cherenkov Telescope Array (CTA) will consist in an array of 50-100 dishes of various sizes and various spacing, each equipped with a camera, made of few thousands fast photo-detectors and its associated front-end electronics. The total number of electronics channels will be larger than 100,000 to be compared to the total of 6,000 channels of the 5-telescopes H.E.S.S.-I H.E.S.S.-II array. To decrease the overall CTA cost, a consequent effort should be done to lower the cost of the electronics while keeping performance at least as good as the one demonstrated on the current experiments and simplifying its maintenance. This will be allowed by mass production, use of standardized modules and integration of front-end functions in ASICs. The 3-year NECTAr program started in 2009 addresses these two topics. Its final aim is to develop and test a demonstrator module of a generic CTA camera. The paper is mainly focused on one of the main components of this module, the NECTAr ASIC which samples the photo-detector signal in a circular analog memory at several GSPS and digitizes it over 12 bits after having received an external trigger. (authors)

  9. Radiation tolerant power converter controls

    CERN Document Server

    Todd, B; King, Q; Uznanski, S

    2012-01-01

    The Large Hadron Collider (LHC) at the European Organisation for Nuclear Research (CERN) is the world's most powerful particle collider. The LHC has several thousand magnets, both warm and super-conducting, which are supplied with current by power converters. Each converter is controlled by a purpose-built electronic module called a Function Generator Controller (FGC). The FGC allows remote control of the power converter and forms the central part of a closed-loop control system where the power converter voltage is set, based on the converter output current and magnet-circuit characteristics. Some power converters and FGCs are located in areas which are exposed to beam-induced radiation. There are numerous radiation induced effects, some of which lead to a loss of control of the power converter, having a direct impact upon the accelerator's availability. Following the first long shut down (LS1), the LHC will be able to run with higher intensity beams and higher beam energy. This is expected to lead to signifi...

  10. Advanced DC/DC converters

    CERN Document Server

    Luo, Fang Lin

    2003-01-01

    DC/DC conversion techniques have undergone rapid development in recent decades. With the pioneering work of these authors, DC/DC converters have now moved into their sixth generation. This book offers a concise, practical presentation of DC/DC converters, summarizing the spectrum of conversion tecnologies and presentingmany new ideas and more than 100 new topologies. Nowhere else in the literature are DC/DC converters so logically sorted and systematically introduced, and nowhere else can readers find detailed information on prototype topologies that represent a major contribution to modern power engineering. More than 320 figures, 60 tables, and 500 formulae facilitate understand and provide precise data.

  11. A 1.0 V 78 mircoW reconfigurable ASIC embedded in an intelligent electrode for continuous remote ECG applications.

    Science.gov (United States)

    Yang, Geng; Chen, Jian; Jonsson, Fredrik; Tenhunen, Hannu; Zheng, Li-Rong

    2009-01-01

    In this paper, a reconfigurable, low-power Application Specific Integrated Circuit (ASIC) that extracts and transmits electrocardiograph (ECG) signals is presented. An Intelligent Electrode is introduced which consists of the proposed ASIC and a micro spike array, permitting onsite ECG signal acquisition, processing and transmission. Fabricated in a standard 0.18 microm CMOS process, the ASIC consumes 78 microW with 1.0 V core voltage at 6 MHz operating frequency and only occupies 2.25 mm(2). The tiny silicon size makes it possible and suitable to embed the proposed ASIC into an Intelligent Electrode, and the low power consumption makes it feasible for long term continuous ECG monitoring.

  12. A ±6 ms-Accuracy, 0.68 mm2, and 2.21 μW QRS Detection ASIC

    Directory of Open Access Journals (Sweden)

    Sheng-Chieh Huang

    2012-01-01

    Full Text Available Healthcare issues arose from population aging. Meanwhile, electrocardiogram (ECG is a powerful measurement tool. The first step of ECG is to detect QRS complexes. A state-of-the-art QRS detection algorithm was modified and implemented to an application-specific integrated circuit (ASIC. By the dedicated architecture design, the novel ASIC is proposed with 0.68 mm2 core area and 2.21 μW power consumption. It is the smallest QRS detection ASIC based on 0.18 μm technology. In addition, the sensitivity is 95.65% and the positive prediction of the ASIC is 99.36% based on the MIT/BIH arrhythmia database certification.

  13. Radiation Hardened Structured ASIC Platform with Compensation of Delay for Temperature and Voltage Variations for Multiple Redundant Temporal Voting Latch Technology

    Science.gov (United States)

    Ardalan, Sasan (Inventor)

    2018-01-01

    The invention relates to devices and methods of maintaining the current starved delay at a constant value across variations in voltage and temperature to increase the speed of operation of the sequential logic in the radiation hardened ASIC design.

  14. Time-to-digital converters

    CERN Document Server

    Henzler, Stephan

    2010-01-01

    This text covers the fundamentals of time-to-digital converters on analog and digital conversion principles. It includes a theoretical investigation into quantization, linearity, noise and variability, and it details a range of advanced TDC architectures.

  15. Transformerless dc-Isolated Converter

    Science.gov (United States)

    Rippel, Wally E.

    1987-01-01

    Efficient voltage converter employs capacitive instead of transformer coupling to provide dc isolation. Offers buck/boost operation, minimal filtering, and low parts count, with possible application in photovoltaic power inverters, power supplies and battery charges. In photovoltaic inverter circuit with transformerless converter, Q2, Q3, Q4, and Q5 form line-commutated inverter. Switching losses and stresses nil because switching performed when current is zero.

  16. Picosecond image-converter diagnostics

    International Nuclear Information System (INIS)

    Schelev, M.Ya.

    1975-01-01

    A brief review is presented of the improvements in picosecond image-converter diagnostics carried out since the previous Congress in 1972. The account is given under the following headings: picosecond image converter cameras for visible and x-ray radiation diagnostics; Nd:glass and ruby mode-locked laser measurements; x-ray plasma emission diagnostics; computer treatment of pictures produced by picosecond cameras. (U.K.)

  17. A 172 $\\mu$W Compressively Sampled Photoplethysmographic (PPG) Readout ASIC With Heart Rate Estimation Directly From Compressively Sampled Data.

    Science.gov (United States)

    Pamula, Venkata Rajesh; Valero-Sarmiento, Jose Manuel; Yan, Long; Bozkurt, Alper; Hoof, Chris Van; Helleputte, Nick Van; Yazicioglu, Refet Firat; Verhelst, Marian

    2017-06-01

    A compressive sampling (CS) photoplethysmographic (PPG) readout with embedded feature extraction to estimate heart rate (HR) directly from compressively sampled data is presented. It integrates a low-power analog front end together with a digital back end to perform feature extraction to estimate the average HR over a 4 s interval directly from compressively sampled PPG data. The application-specified integrated circuit (ASIC) supports uniform sampling mode (1x compression) as well as CS modes with compression ratios of 8x, 10x, and 30x. CS is performed through nonuniformly subsampling the PPG signal, while feature extraction is performed using least square spectral fitting through Lomb-Scargle periodogram. The ASIC consumes 172  μ W of power from a 1.2 V supply while reducing the relative LED driver power consumption by up to 30 times without significant loss of relevant information for accurate HR estimation.

  18. Characterization of the CBC2 readout ASIC for the CMS strip-tracker high-luminosity upgrade

    International Nuclear Information System (INIS)

    Braga, D; Hall, G; Pesaresi, M; Raymond, M; Jones, L; Murray, P; Prydderch, M

    2014-01-01

    The CMS Binary Chip 2 (CBC2) is a full-scale prototype ASIC developed for the front-end readout of the high-luminosity upgrade of the CMS silicon strip tracker. The 254-channel, 130 nm CMOS ASIC is designed for the binary readout of double-layer modules, and features cluster-width discrimination and coincidence logic for detecting high-P T track candidates. The chip was delivered in January 2013 and has since been bump-bonded to a dual-chip hybrid and extensively tested. The CBC2 is fully functional and working to specification: we present the result of electrical characterization of the chip, including gain, noise, threshold scan and power consumption, together with the performance of the stub finding logic. Finally we will outline the plan for future developments towards the production version

  19. The digital ASIC for the digital front end electronics of the SPI astrophysics gamma-ray experiment

    International Nuclear Information System (INIS)

    Lafond, E.; Mur, M.; Schanne, S.

    1998-01-01

    The SPI spectrometer is one of the gamma-ray astronomy instruments that will be installed on the ESA INTEGRAL satellite, intended to be launched in 2001 by the European Space Agency. The Digital Front-End Electronics sub-system (DFEE) is in charge of the real time data processing of the various measurements produced by the Germanium (Ge) detectors and the Bismuth Germanate (BGO) anti-coincidence shield. The central processing unit of the DFEE is implemented in a digital ASIC circuit, which provides the real time association of the various time signals, acquires the associated energy measurements, and classifies the various types of physics events. The paper gives the system constraints of the DFEE, the architecture of the ASIC circuit, the technology requirements, and the strategy for test and integration. Emphasis is given to the high level language development and simulation, the automatic circuit synthesis approach, and the performance estimation

  20. CBC3: a CMS microstrip readout ASIC with logic for track-trigger modules at HL-LHC

    CERN Document Server

    Prydderch, Mark Lyndon; Bell, Stephen Jean-marc; Key-Charriere, M; Jones, Lawrence; Auzinger, Georg; Borg, Johan; Hall, Geoffrey; Pesaresi, Mark Franco; Raymond, David Mark; Uchida, Kirika; Goldstein, Joel; Seif El Nasr, Sarah

    2018-01-01

    The CBC3 is the latest version of the CMS Binary Chip ASIC for readout of the outer radial region of the upgraded CMS Tracker at HL-LHC. This 254-channel, 130nm CMOS ASIC is designed to be bump-bonded to a substrate to which sensors will be wire-bonded. It will instrument double-layer 2S-modules, consisting of two overlaid silicon microstrip sensors with aligned microstrips. On-chip logic identifies first level trigger primitives from high transverse-momentum tracks by selecting correlated hits in the two sensors. Delivered in late 2016, the CBC3 has been under test for several months, including X-ray irradiations and SEU testing. Results and performance are reported.

  1. Two-inductor boost and buck converters

    Science.gov (United States)

    White, J. L.; Muldoon, W. J.

    The derivation, analysis and design of a coupled inductor boost converter is presented. Aspects of the qualitative ac behavior of coupled inductor converters are discussed. Considerations for the design of the magnetics for such converters are addressed.

  2. ASIC-like currents in freshly isolated cerebral artery smooth muscle cells are inhibited by endogenous oxidase activity.

    Science.gov (United States)

    Chung, Wen-Shuo; Farley, Jerry M; Drummond, Heather A

    2011-01-01

    The aim of this study was to determine if VSMC ASIC-like currents are regulated by oxidative state. We used whole-cell patch clamp of isolated mouse cerebral VSMCs to determine if 1) reducing agents, such as DTT and GSH, and 2) inhibition of endogenous oxidase activity from NADPH and Xanthine oxidases potentiate active currents and activate electrically silent currents. Pretreatment with 2 mM DTT or GSH, increased the mean peak amplitude of ASIC-like currents evoked by pH 6.0 from 0.4 ± 0.1 to 14.9 ± 3.6 pA/pF, and from 0.9 ± 0.3 to 11.3 ± 2.4 pA/pF, respectively. Pretreatment with apocynin, a NADPH oxidase inhibitor, mimics the effect of the reducing agents, with the mean peak current amplitude increased from 0.9 ± 0.5 to 7.0 ± 2.6 pA/pF and from 0.5 ± 0.2 to 26.4 ± 6.8 pA/pF by 50 and 200 μM apocynin, respectively. Pretreatment with allopurinol, a xanthine oxidase inhibitor, also potentiates the VSMC ASIC-like activity. These findings suggest that VSMC ASIC-like channels are regulated by oxidative state and may be inhibited by basal endogenous oxidative sources such as NADPH and xanthine oxidase. Copyright © 2011 S. Karger AG, Basel.

  3. 17β-Estradiol Enhances ASIC Activity in Primary Sensory Neurons to Produce Sex Difference in Acidosis-Induced Nociception.

    Science.gov (United States)

    Qu, Zu-Wei; Liu, Ting-Ting; Ren, Cuixia; Gan, Xiong; Qiu, Chun-Yu; Ren, Ping; Rao, Zhiguo; Hu, Wang-Ping

    2015-12-01

    Sex differences have been reported in a number of pain conditions. Women are more sensitive to most types of painful stimuli than men, and estrogen plays a key role in the sex differences in pain perception. However, it is unclear whether there is a sex difference in acidosis-evoked pain. We report here that both male and female rats exhibit nociceptive behaviors in response to acetic acid, with females being more sensitive than males. Local application of exogenous 17β-estradiol (E2) exacerbated acidosis-evoked nociceptive response in male rats. E2 and estrogen receptor (ER)-α agonist 1,3,5-Tris(4-hydroxyphenyl)-4-propyl-1H-pyrazole, but not ERβ agonist 2,3-bis(4-hydroxyphenyl)-propionitrile, replacement also reversed attenuation of the acetic acid-induced nociceptive response in ovariectomized females. Moreover, E2 can exert a rapid potentiating effect on the functional activity of acid-sensing ion channels (ASICs), which mediated the acidosis-induced events. E2 dose dependently increased the amplitude of ASIC currents with a 42.8 ± 1.6 nM of EC50. E2 shifted the concentration-response curve for proton upward with a 50.1% ± 6.2% increase of the maximal current response to proton. E2 potentiated ASIC currents via an ERα and ERK1/2 signaling pathway. E2 also altered acidosis-evoked membrane excitability of dorsal root ganglia neurons and caused a significant increase in the amplitude of the depolarization and the number of spikes induced by acidic stimuli. E2 potentiation of the functional activity of ASICs revealed a peripheral mechanism underlying this sex difference in acetic acid-induced nociception.

  4. Development and evaluation of an ultra-fast ASIC for future PET scanners using TOF-capable MPPC array detectors

    International Nuclear Information System (INIS)

    Ambe, T.; Ikeda, H.; Kataoka, J.; Matsuda, H.; Kato, T.

    2015-01-01

    We developed a front-end ASIC for future PET scanners with Time-Of-Flight (TOF) capability to be coupled with 4×4 Multi-Pixel Photon Counter (MPPC) arrays. The ASIC is designed based on the open-IP project proposed by JAXA and realized in TSMC 0.35 μm CMOS technology. The circuit comprises 16-channel, low impedance current conveyors for effectively acquiring fast MPPC signals. For precise measurement of the coincidence timing of 511-keV gamma rays, the leading-edge method was used to discriminate the signals. We first tested the time response of the ASIC by illuminating each channel of a MPPC array device 3×3 mm 2 in size with a Pico-second Light Pulsar with a light emission peak of 655 nm and pulse duration of 54 ps (FWHM). We obtained 105 ps (FWHM) on average for each channel in time jitter measurements. Moreover, we compensated for the time lag of each channel with inner delay circuits and succeeded in suppressing about a 700-ps lag to only 15 ps. This paper reports TOF measurements using back-to-back 511-keV signals, and suggests that the ASIC can be a promising device for future TOF-PET scanners based on the MPPC array. - Highlights: • We developed a newly designed large-area monolithic MPPC array. • We obtained fine gain uniformity, and good energy and time resolutions when coupled to the LYSO scintillator. • We fabricated gamma-ray camera consisting of the MPPC array and the submillimeter pixelized LYSO and GGAG scintillators. • In the flood images, each crystal of scintillator matrices was clearly resolved. • Good energy resolutions for 662 keV gamma-rays for each LYSO and GGAG scintillator matrices were obtained

  5. A Novel Front-End ASIC With Post Digital Filtering and Calibration for CZT-Based PET Detector

    International Nuclear Information System (INIS)

    Gao, W.; Yin, J.; Li, C.; Zeng, H.; Gao, D.; Hu, Y.

    2015-01-01

    This paper presents a novel front-end electronics based on a front-end ASIC with post digital filtering and calibration dedicated to CZT detectors for PET imaging. A cascade amplifier based on split-leg topology is selected to realize the charge-sensitive amplifier (CSA) for the sake of low noise performances and the simple scheme of the power supplies. The output of the CSA is connected to a variable-gain amplifier to generate the compatible signals for the A/D conversion. A multi-channel single-slope ADC is designed to sample multiple points for the digital filtering and shaping. The digital signal processing algorithms are implemented by a FPGA. To verify the proposed scheme, a front-end readout prototype ASIC is designed and implemented in 0.35 μm CMOS process. In a single readout channel, a CSA, a VGA, a 10-bit ADC and registers are integrated. Two dummy channels, bias circuits, and time controller are also integrated. The die size is 2.0 mm x 2.1 mm. The input range of the ASIC is from 2000 e - to 100000 e - , which is suitable for the detection of the X-and gamma ray from 11.2 keV to 550 keV. The linearity of the output voltage is less than 1 %. The gain of the readout channel is 40.2 V/pC. The static power dissipation is about 10 mW/channel. The above tested results show that the electrical performances of the ASIC can well satisfy PET imaging applications. (authors)

  6. Secure ASIC Architecture for Optimized Utilization of a Trusted Supply Chain for Common Architecture A and D Applications

    Science.gov (United States)

    2017-03-01

    Secure ASIC Architecture for Optimized Utilization of a Trusted Supply Chain for Common Architecture A&D Applications Ezra Hall, Ray Eberhard...use applications. Furthermore, a product roadmap must be comprehended as part of this platform, offering A&D programs a solution to their...existing solutions for adoption to occur. Additionally, a well-developed roadmap to future secure SoCs, leveraging the value add of future advanced

  7. Development of Charge Sensitive Preamplifier and Readout Integrate Circuit Board for High Resolution Detector using ASIC Process

    Energy Technology Data Exchange (ETDEWEB)

    Jeon, J. Y.; Kim, J. H.; Park, J. M.; Yang, J. Y.; Kim, K. Y.; Kim, Y. S. [RadTek Co., Daejeon (Korea, Republic of)

    2010-06-15

    - Design of discrete type charge sensitive amplifier for high resolution semi-conductor sensor - Design and develop the test board for the performance of charge sensitive amplifier with sensor - Performance of electrical test for the sensor and charge sensitive amplifier - Development of prototype 8 x 8 array type detector module - Noise equivalent charge test for the charge sensitive amplifier - Design and development of Micro SMD discrete type amplifier applying ASIC procedure - Development of Hybrid type charge sensitive amplifier including shape

  8. A Novel Front-End ASIC With Post Digital Filtering and Calibration for CZT-Based PET Detector

    Energy Technology Data Exchange (ETDEWEB)

    Gao, W.; Yin, J.; Li, C.; Zeng, H.; Gao, D. [Institute of Microelectronics, School of Computer Science and Techonology, Northwestern Polytechnical University, Xi' an (China); Hu, Y. [Institut Pluridiscipline Hubert Curien, CNRS/UDS/IN2P3, Strasbourg (France)

    2015-07-01

    This paper presents a novel front-end electronics based on a front-end ASIC with post digital filtering and calibration dedicated to CZT detectors for PET imaging. A cascade amplifier based on split-leg topology is selected to realize the charge-sensitive amplifier (CSA) for the sake of low noise performances and the simple scheme of the power supplies. The output of the CSA is connected to a variable-gain amplifier to generate the compatible signals for the A/D conversion. A multi-channel single-slope ADC is designed to sample multiple points for the digital filtering and shaping. The digital signal processing algorithms are implemented by a FPGA. To verify the proposed scheme, a front-end readout prototype ASIC is designed and implemented in 0.35 μm CMOS process. In a single readout channel, a CSA, a VGA, a 10-bit ADC and registers are integrated. Two dummy channels, bias circuits, and time controller are also integrated. The die size is 2.0 mm x 2.1 mm. The input range of the ASIC is from 2000 e{sup -} to 100000 e{sup -}, which is suitable for the detection of the X-and gamma ray from 11.2 keV to 550 keV. The linearity of the output voltage is less than 1 %. The gain of the readout channel is 40.2 V/pC. The static power dissipation is about 10 mW/channel. The above tested results show that the electrical performances of the ASIC can well satisfy PET imaging applications. (authors)

  9. A Radiation Hard Multi-Channel Digitizer ASIC for Operation in the Harsh Jovian Environment

    Science.gov (United States)

    Aslam, Shahid; Aslam, S.; Akturk, A.; Quilligan, G.

    2011-01-01

    ultimately impact the surface of Europa after the mission is completed. The current JEO mission concept includes a range of instruments on the payload, to monitor dynamic phenomena (such as Io's volcanoes and Jupiters atmosphere), map the Jovian magnetosphere and its interactions with the Galilean satellites, and characterize water oceans beneath the ice shells of Europa and Ganymede. The payload includes a low mass (3.7 Kg) and low power (ASIC that resides very close to the thermopile linear array outputs. Both the thermopile array and the MCD ASIC will need to show full functionality within the harsh Jovian radiation environment, operating at cryogenic temperatures, typically 150 K to 170 K. In the following, a radiation mitigation strategy together with a low risk Radiation-Hardened-By-Design (RHBD) methodology using commercial foundry processes is given for the design and manufacture of a MCD ASIC that will meet this challenge.

  10. Studies and development of a readout ASIC for pixelated CdTe detectors for space applications

    International Nuclear Information System (INIS)

    Michalowska, A.

    2013-01-01

    The work presented in this thesis is part of a project where a new instrument is developed: a camera for hard X-rays imaging spectroscopy. It is dedicated to fundamental research for observations in astrophysics, at wavelengths which can only be observed using space-borne instruments. In this domain the spectroscopic accuracy as well as the imaging details are of high importance. This work has been realized at CEA/IRFU (Institut de Recherche sur les lois Fondamentales de l'Univers), which has a long-standing and successful experience in instruments for high energy physics and space physics instrumentation. The objective of this thesis is the design of the readout electronics for a pixelated CdTe detector, suitable for a stacked assembly. The principal parameters of this integrated circuit are a very low noise for reaching a good accuracy in X-ray energy measurement, very low power consumption, a critical parameter in space-borne applications, and a small dead area for the full system combining the detector and the readout electronics. In this work I have studied the limits of these three parameters in order to optimize the circuit. In terms of the spectral resolution, two categories of noise had to be distinguished to determine the final performance. The first is the Fano noise limit, related to detector interaction statistics, which cannot be eliminated. The second is the electronic noise, also unavoidable; however it can be minimized through optimization of the detection chain. Within the detector, establishing a small pixel pitch of 300 μm reduces the input capacitance and the dark current. This limits the effects of the electronic noise. Also in order to limit the input capacitance the future camera is designed as a stacked assembly of the detector with the readout ASIC. This allows to reach extremely good input parameters seen by the readout electronics: a capacitance in range of 0.3 pF-1 pF and a dark current below 5 pA. In the frame of this thesis I have

  11. Regulation of ASIC channels by a stomatin/STOML3 complex located in a mobile vesicle pool in sensory neurons.

    Science.gov (United States)

    Lapatsina, Liudmila; Jira, Julia A; Smith, Ewan St J; Poole, Kate; Kozlenkov, Alexey; Bilbao, Daniel; Lewin, Gary R; Heppenstall, Paul A

    2012-06-01

    A complex of stomatin-family proteins and acid-sensing (proton-gated) ion channel (ASIC) family members participate in sensory transduction in invertebrates and vertebrates. Here, we have examined the role of the stomatin-family protein stomatin-like protein-3 (STOML3) in this process. We demonstrate that STOML3 interacts with stomatin and ASIC subunits and that this occurs in a highly mobile vesicle pool in dorsal root ganglia (DRG) neurons and Chinese hamster ovary cells. We identify a hydrophobic region in the N-terminus of STOML3 that is required for vesicular localization of STOML3 and regulates physical and functional interaction with ASICs. We further characterize STOML3-containing vesicles in DRG neurons and show that they are Rab11-positive, but not part of the early-endosomal, lysosomal or Rab14-dependent biosynthetic compartment. Moreover, uncoupling of vesicles from microtubules leads to incorporation of STOML3 into the plasma membrane and increased acid-gated currents. Thus, STOML3 defines a vesicle pool in which it associates with molecules that have critical roles in sensory transduction. We suggest that the molecular features of this vesicular pool may be characteristic of a 'transducosome' in sensory neurons.

  12. Involvement of Opioid System, TRPM8, and ASIC Receptors in Antinociceptive Effect of Arrabidaea brachypoda (DC Bureau

    Directory of Open Access Journals (Sweden)

    Vinícius Peixoto Rodrigues

    2017-11-01

    Full Text Available Arrabidaea brachypoda (DC Bureau is a medicinal plant found in Brazil. Known as “cipó-una”, it is popularly used as a natural therapeutic agent against pain and inflammation. This study evaluated the chemical composition and antinociceptive activity of the dichloromethane fraction from the roots of A. brachypoda (DEAB and its mechanism of action. The chemical composition was characterized by high-performance liquid chromatography, and this fraction is composed only of dimeric flavonoids. The antinociceptive effect was evaluated in formalin and hot plate tests after oral administration (10–100 mg/kg in male Swiss mice. We also investigated the involvement of TRPV1 (transient receptor potential vanilloid 1, TRPA1 (transient receptor potential ankyrin 1, TRPM8 (transient receptor potential melastatin 8, and ASIC (acid-sensing ion channel, as well as the opioidergic, glutamatergic, and supraspinal pathways. Moreover, the nociceptive response was reduced (30 mg/kg in the early and late phase of the formalin test. DEAB activity appears to involve the opioid system, TRPM8, and ASIC receptors, clearly showing that the DEAB alleviates acute pain in mice and suggesting the involvement of the TRPM8 and ASIC receptors and the opioid system in acute pain relief.

  13. Involvement of Opioid System, TRPM8, and ASIC Receptors in Antinociceptive Effect of Arrabidaea brachypoda (DC) Bureau.

    Science.gov (United States)

    Rodrigues, Vinícius Peixoto; Rocha, Cláudia Quintino da; Périco, Larissa Lucena; Santos, Raquel de Cássia Dos; Ohara, Rie; Nishijima, Catarine Massucato; Ferreira Queiroz, Emerson; Wolfender, Jean-Luc; Rocha, Lúcia Regina Machado da; Santos, Adair Roberto Soares; Vilegas, Wagner; Hiruma-Lima, Clélia Akiko

    2017-11-02

    Arrabidaea brachypoda (DC) Bureau is a medicinal plant found in Brazil. Known as "cipó-una", it is popularly used as a natural therapeutic agent against pain and inflammation. This study evaluated the chemical composition and antinociceptive activity of the dichloromethane fraction from the roots of A. brachypoda (DEAB) and its mechanism of action. The chemical composition was characterized by high-performance liquid chromatography, and this fraction is composed only of dimeric flavonoids. The antinociceptive effect was evaluated in formalin and hot plate tests after oral administration (10-100 mg/kg) in male Swiss mice. We also investigated the involvement of TRPV1 (transient receptor potential vanilloid 1), TRPA1 (transient receptor potential ankyrin 1), TRPM8 (transient receptor potential melastatin 8), and ASIC (acid-sensing ion channel), as well as the opioidergic, glutamatergic, and supraspinal pathways. Moreover, the nociceptive response was reduced (30 mg/kg) in the early and late phase of the formalin test. DEAB activity appears to involve the opioid system, TRPM8, and ASIC receptors, clearly showing that the DEAB alleviates acute pain in mice and suggesting the involvement of the TRPM8 and ASIC receptors and the opioid system in acute pain relief.

  14. The GBT-SCA, a radiation tolerant ASIC for detector control and monitoring applications in HEP experiments

    International Nuclear Information System (INIS)

    Caratelli, A.; Bonacini, S.; Kloukinas, K.; Marchioro, A.; Moreira, P.; Oliveira, R. De; Paillard, C.

    2015-01-01

    The future upgrades of the LHC experiments will increase the beam luminosity leading to a corresponding growth of the amounts of data to be treated by the data acquisition systems. To address these needs, the GBT (Giga-Bit Transceiver optical link [1,2]) architecture was developed to provide the simultaneous transfer of readout data, timing and trigger signals as well as slow control and monitoring data. The GBT-SCA ASIC, part of the GBT chip-set, has the purpose to distribute control and monitoring signals to the on-detector front-end electronics and perform monitoring operations of detector environmental parameters. In order to meet the requirements of different front-end ASICs used in the experiments, it provides various user-configurable interfaces capable to perform simultaneous operations. It is designed employing radiation tolerant design techniques to ensure robustness against SEUs and TID radiation effects and is implemented in a commercial 130 nm CMOS technology. This work presents the GBT-SCA architecture, the ASIC interfaces, the data transfer protocol, and its integration with the GBT optical link

  15. Triroc: A Multi-Channel SiPM Read-Out ASIC for PET/PET-ToF Application

    Science.gov (United States)

    Ahmad, Salleh; Fleury, Julien; de la Taille, Christophe; Seguin-Moreau, Nathalie; Dulucq, Frederic; Martin-Chassard, Gisele; Callier, Stephane; Thienpont, Damien; Raux, Ludovic

    2015-06-01

    Triroc is the latest addition to SiPM readout ASICs family developed at Weeroc, a start-up company from the Omega microelectronics group of IN2P3/CNRS. This chip is developed under the framework TRIMAGE European project which is aimed for building a cost effective tri-modal PET/MR/EEG brain scan. To ensure the flexibility and compatibility with any SiPM in the market, the ASIC is designed to be capable of accepting negative and positive polarity input signals. This 64-channel ASIC, is suitable for SiPM readout which requires high accuracy timing and charge measurements. Targeted applications would be PET prototyping with time-of-flight capability. Main features of Triroc includes high dynamic range ADC up to 2500 photoelectrons and TDC fine time binning of 40 ps. Triroc requires very minimal external components which means it is a good contender for compact multichannel PET prototyping. Triroc is designed by using AMS 0.35 μm SiGe technology and it was submitted in March 2014. The detail design of this chip will be presented.

  16. Increased Asics Expression via the Camkii-CREB Pathway in a Novel Mouse Model of Trigeminal Pain

    Directory of Open Access Journals (Sweden)

    Yan Wang

    2018-03-01

    Full Text Available Background/Aims: Migraine is a disabling condition that severely impacts socioeconomic function and quality of life. The focus of this study was to develop a mouse model of trigeminal pain that mimics migraine. Methods: After undergoing dural cannulation surgery, mice were treated with repeated dural doses of an acidic solution to induce trigeminal pain. Results: The method elicited intermittent, head-directed wiping and scratching as well as the expression of both the c-FOS gene in the spinal trigeminal nucleus caudalis and calcitonin gene related peptide (CGRP in the periaqueductal grey matter. Interestingly, the acid-induced trigeminal pain behaviour was inhibited by amiloride, an antagonist of acid-sensing ion channels (ASICs, but not by AMG-9810, an inhibitor of transient receptor potential cation channel V1(TRPV1. In addition, the relative mRNA and protein expression levels of ASIC1a and ASIC3 were increased in the acid-induced trigeminal nociceptive pathways. Furthermore, blocking CaMKII with KN-93 significantly reduced the acid-induced trigeminal pain behaviour and c-FOS gene expression. Conclusion: The data suggested that chronic intermittent administration of an acidic solution to mice resulted in trigeminal hypersensitivity and that dural acid-induced trigeminal pain behaviour in mice may mechanistically mimic migraine. The observations here identify an entirely novel treatment strategy for migraine.

  17. Modeling of asymmetrical boost converters

    Directory of Open Access Journals (Sweden)

    Eliana Isabel Arango Zuluaga

    2014-01-01

    Full Text Available The asymmetrical interleaved dual boost (AIDB is a fifth-order DC/DC converter designed to interface photovoltaic (PV panels. The AIDB produces small current harmonics to the PV panels, reducing the power losses caused by the converter operation. Moreover, the AIDB provides a large voltage conversion ratio, which is required to step-up the PV voltage to the large dc-link voltage used in grid-connected inverters. To reject irradiance and load disturbances, the AIDB must be operated in a closed-loop and a dynamic model is required. Given that the AIDB converter operates in Discontinuous Conduction Mode (DCM, classical modeling approaches based on Continuous Conduction Mode (CCM are not valid. Moreover, classical DCM modeling techniques are not suitable for the AIDB converter. Therefore, this paper develops a novel mathematical model for the AIDB converter, which is suitable for control-pur-poses. The proposed model is based on the calculation of a diode current that is typically disregarded. Moreover, because the traditional correction to the second duty cycle reported in literature is not effective, a new equation is designed. The model accuracy is contrasted with circuital simulations in time and frequency domains, obtaining satisfactory results. Finally, the usefulness of the model in control applications is illustrated with an application example.

  18. High-Performance Data Converters

    DEFF Research Database (Denmark)

    Steensgaard-Madsen, Jesper

    -resolution internal D/A converters are required. Unit-element mismatch-shaping D/A converters are analyzed, and the concept of mismatch-shaping is generalized to include scaled-element D/A converters. Several types of scaled-element mismatch-shaping D/A converters are proposed. Simulations show that, when implemented...... in a standard CMOS technology, they can be designed to yield 100 dB performance at 10 times oversampling. The proposed scaled-element mismatch-shaping D/A converters are well suited for use as the feedback stage in oversampled delta-sigma quantizers. It is, however, not easy to make full use of their potential......-order difference of the output signal from the loop filter's first integrator stage. This technique avoids the need for accurate matching of analog and digital filters that characterizes the MASH topology, and it preserves the signal-band suppression of quantization errors. Simulations show that quantizers...

  19. Entanglement in a parametric converter

    Energy Technology Data Exchange (ETDEWEB)

    Lee, Su-Yong; Qamar, Shahid; Lee, Hai-Woong; Zubairy, M Suhail [Center for Quantum Physics, COMSATS Institute of Information Technology, Islamabad (Pakistan)], E-mail: shahid_qamar@pieas.edu.pk, E-mail: zubairy@physics.tamu.edu

    2008-07-28

    In this paper, we consider a parametric converter as a source of entangled radiation. We examine recently derived conditions (Hillery and Zubairy 2006 Phys. Rev. Lett. 96 050503, Duan et al 2000 Phys. Rev. Lett. 84 2722) for determining when the two output modes in a parametric converter are entangled. We show that for different initial field states, the two criteria give different conditions that ensure that the output states are entangled. We also present an input-output calculation for the entanglement of the output field.

  20. Differential effects of temperature on acid-activated currents mediated by TRPV1 and ASIC channels in rat dorsal root ganglion neurons.

    Science.gov (United States)

    Neelands, Torben R; Zhang, Xu-Feng; McDonald, Heath; Puttfarcken, Pamela

    2010-05-06

    Elevated temperature and decreased extracellular pH are hallmarks of inflammatory pain states. Dorsal root ganglia (DRG) neurons are integral in transferring painful stimuli from the periphery to central sites. This study investigated the effect of elevated temperatures on the response of DRG neurons to acute application of acidic solutions. At room temperature (22 degrees C), in response to pH 5.5, there were a variety of kinetic responses consistent with differential expression of TRPV1 and ASIC channels. Increasing the temperature resulted in a significant increase in the peak and total current mediated by TRPV1 in response to an acidic solution. In contrast, the amplitude of a fast activating, rapidly inactivating ASIC1-like current was not affected by increasing the temperature but did result in an increased rate of desensitization that reduced the total current level. This effect on the rate of desensitization was temperature-dependent and could be reversed by returning to 22 degrees C. Likewise, cells exhibiting slowly inactivating ASIC2-like responses also had temperature-dependent increase in the rate of desensitization. The ASIC2-like responses and the TRPV1 responses tended to decrease in amplitude with repetitive application of pH 5.5 even at 22 degrees C. The rate of desensitization of ASIC-like currents activated by less acidic solutions (pH 6.8) was also increased in a temperature-dependent manner. Finally, acidic pH reduced threshold to trigger action potentials, however, the pattern of action potential firing was shaped by the distribution of ASIC and TRPV1 channels. These results indicate that the ambient temperature at which acidosis occurs has a profound effect on the contribution of ASIC and TRPV1 channels, therefore, altering the neuronal excitability. Copyright 2010 Elsevier B.V. All rights reserved.

  1. PAR-2 activation enhances weak acid-induced ATP release through TRPV1 and ASIC sensitization in human esophageal epithelial cells.

    Science.gov (United States)

    Wu, Liping; Oshima, Tadayuki; Shan, Jing; Sei, Hiroo; Tomita, Toshihiko; Ohda, Yoshio; Fukui, Hirokazu; Watari, Jiro; Miwa, Hiroto

    2015-10-15

    Esophageal visceral hypersensitivity has been proposed to be the pathogenesis of heartburn sensation in nonerosive reflux disease. Protease-activated receptor-2 (PAR-2) is expressed in human esophageal epithelial cells and is believed to play a role in inflammation and sensation. PAR-2 activation may modulate these responses through adenosine triphosphate (ATP) release, which is involved in transduction of sensation and pain. The transient receptor potential vanilloid receptor 1 (TRPV1) and acid-sensing ion channels (ASICs) are both acid-sensitive nociceptors. However, the interaction among these molecules and the mechanisms of heartburn sensation are still not clear. We therefore examined whether ATP release in human esophageal epithelial cells in response to acid is modulated by TRPV1 and ASICs and whether PAR-2 activation influences the sensitivity of TRPV1 and ASICs. Weak acid (pH 5) stimulated the release of ATP from primary human esophageal epithelial cells (HEECs). This effect was significantly reduced after pretreatment with 5-iodoresiniferatoxin (IRTX), a TRPV1-specific antagonist, or with amiloride, a nonselective ASIC blocker. TRPV1 and ASIC3 small interfering RNA (siRNA) transfection also decreased weak acid-induced ATP release. Pretreatment of HEECs with trypsin, tryptase, or a PAR-2 agonist enhanced weak acid-induced ATP release. Trypsin treatment led to the phosphorylation of TRPV1. Acid-induced ATP release enhancement by trypsin was partially blocked by IRTX, amiloride, or a PAR-2 antagonist. Conversely, acid-induced ATP release was augmented by PAR-2 activation through TRPV1 and ASICs. These findings suggested that the pathophysiology of heartburn sensation or esophageal hypersensitivity may be associated with the activation of PAR-2, TRPV1, and ASICs. Copyright © 2015 the American Physiological Society.

  2. ABSTRACTS OF THE “GIORNATE DI CONIGLICOLTURA ASIC 2011”

    Directory of Open Access Journals (Sweden)

    ABSTRACTS OF THE “GIORNATE DI CONIG Forlì, Italy,

    2012-10-01

    Full Text Available The fourth edition of the Italian Rabbit Days was held in Forlì (Italy on April 8-9, 2011, organized by ASIC (Italian Rabbit Scientific Association in collaboration with Dipartimento di Scienze degli Alimenti (Università di Bologna, Dipartimento di Scienze Animali (Università di Padova, Fondazione Iniziative Zooprofilattiche e Zootecniche (Brescia, ASPA (Animal Production Scientific Association and the Forli Fair. The first day included three invited lectures: “Feed restriction strategies, implications on physiology, growth and health of the growing rabbit”, presented by T. Gidenne, L. Fortun-Lamothe, S. Combes; “Ovulation induction in rabbit does: a review”, presented by A. Dal Bosco; “Factors affecting efficacy of intravaginal administration of GnRH analogues for ovulation induction in rabbit does” presented by P.G. Rebollar. In addition, three sessions of oral communications on Reproduction and Genetics, Nutrition and Physiology, Welfare, Management, and Pathology were held. During the second day it was presented a round table focused on “Management and use of drugs and vaccines in rabbit production”. Finally a Poster Session was through the two days. The meeting was attended by more than 100 participants, including researchers and technicians from France, Spain, Hungary, Belgium and Switzerland. A total of 3 invited papers, 14 oral communications and 16 posters were presented during the congress. Following the abstracts of all contributions are reported.

  3. Circuit design and simulation of a transmit beamforming ASIC for high-frequency ultrasonic imaging systems.

    Science.gov (United States)

    Athanasopoulos, Georgios I; Carey, Stephen J; Hatfield, John V

    2011-07-01

    This paper describes the design of a programmable transmit beamformer application-specific integrated circuit (ASIC) with 8 channels for ultrasound imaging systems. The system uses a 20-MHz reference clock. A digital delay-locked loop (DLL) was designed with 50 variable delay elements, each of which provides a clock with different phase from a single reference. Two phase detectors compare the phase difference of the reference clock with the feedback clock, adjusting the delay of the delay elements to bring the feedback clock signal in phase with the reference clock signal. Two independent control voltages for the delay elements ensure that the mark space ratio of the pulses remain at 50%. By combining a 10- bit asynchronous counter with the delays from the DLL, each channel can be programmed to give a maximum time delay of 51 μs with 1 ns resolution. It can also give bursts of up to 64 pulses. Finally, for a single pulse, it can adjust the pulse width between 9 ns and 100 ns by controlling the current flowing through a capacitor in a one-shot circuit, for use with 40-MHz and 5-MHz transducers, respectively.

  4. Integration of SPICE with TEK LV500 ASIC Design Verification System

    Directory of Open Access Journals (Sweden)

    A. Srivastava

    1996-01-01

    Full Text Available The present work involves integration of the simulation stage of design of a VLSI circuit and its testing stage. The SPICE simulator, TEK LV500 ASIC Design Verification System, and TekWaves, a test program generator for LV500, were integrated. A software interface in ‘C’ language in UNIX ‘solaris 1.x’ environment has been developed between SPICE and the testing tools (TekWAVES and LV500. The function of the software interface developed is multifold. It takes input from either SPICE2G.6 or SPICE 3e.1. The output generated by the interface software can be given as an input to either TekWAVES or LV500. A graphical user interface has also been developed with OPENWlNDOWS using Xview tool kit on SUN workstation. As an example, a two phase clock generator circuit has been considered and usefulness of the software demonstrated. The interface software could be easily linked with VLSI design such as MAGIC layout editor.

  5. Receiver ASIC for timing, trigger and control distribution in LHC experiments

    International Nuclear Information System (INIS)

    Christiansen, J.; Marchioro, A.; Moreira, P.; Sancho, A.

    1996-01-01

    An ASIC receiver has been developed for the optical timing, trigger and control distribution system for LHC detectors. It is capable of recovering the LHC reference clock and the first-level trigger decisions and making them available to the front-end electronics properly deskewed in time. The timing receiver is also capable of recognizing individually addressed commands to provide some slow control capability. Its main functions include post-amplification of the signal received from a photodetector-preamplifier, automatic gain control, data/clock separation, demultiplexing of the trigger and data channels and programmable coarse/fine deskewing functions. The design has been mapped into a standard 1microm CMOS process with all the analogue and timing critical functions implemented in full custom. The jitter measured on the recovered clock is less than 100 ps for input optical powers down to -25 dBm. The time deskewing functions allow the commands and the first level trigger accept signal to be phase shifted up to a maximum of sixteen clock cycles in steps of 0.1 ns

  6. Spectral response characterization of CdTe sensors of different pixel size with the IBEX ASIC

    Science.gov (United States)

    Zambon, P.; Radicci, V.; Trueb, P.; Disch, C.; Rissi, M.; Sakhelashvili, T.; Schneebeli, M.; Broennimann, C.

    2018-06-01

    We characterized the spectral response of CdTe sensors with different pixel sizes - namely 75, 150 and 300 μm - bonded to the latest generation IBEX single photon counting ASIC developed at DECTRIS, to detect monochromatic X-ray energy in the range 10-60 keV. We present a comparison of pulse height spectra recorded for several energies, showing the dependence on the pixel size of the non-trivial atomic fluorescence and charge sharing effects that affect the detector response. The extracted energy resolution, in terms of full width at half maximum or FWHM, ranges from 1.5 to 4 keV according to the pixel size and chip configuration. We devoted a careful analysis to the Quantum Efficiency and to the Spectral Efficiency - a newly-introduced measure that quantifies the impact of fluorescence and escape phenomena on the spectrum integrity in high- Z material based detectors. We then investigated the influence of the photon flux on the aforementioned quantities up to 180 ṡ 106 cts/s/mm2 and 50 ṡ 106 cts/s/mm2 for the 150 μm and 300 μm pixel case, respectively. Finally, we complemented the experimental data with analytical and with Monte Carlo simulations - taking into account the stochastic nature of atomic fluorescence - with an excellent agreement.

  7. An important step forward in continuous spectroscopic imaging of ionising radiations using ASICs

    Energy Technology Data Exchange (ETDEWEB)

    Fessler, P. [11 rue Rabelais, 92170 Vanves (France); Coffin, J. [Institut de Recherches Subatomiques, B.P. 28, 67037 Strasbourg (France); Eberle, H. [Institut de Recherches Subatomiques, B.P. 28, 67037 Strasbourg (France); Raad Iseli, C. de [Smart Silicon Systems SA, Ch. de la Graviere 6, CH-1007 Lausanne (Switzerland); Hilt, B. [Universite de Haute-Alsace, GRPHE, 61, rue Albert Camus, 68093 Mulhouse (France); Huss, D. [Universite de Haute-Alsace, GRPHE, 61, rue Albert Camus, 68093 Mulhouse (France); Krummenacher, F. [Smart Silicon Systems SA, Ch. de la Graviere 6, CH-1007 Lausanne (Switzerland); Lutz, J.R. [Institut de Recherches Subatomiques, B.P. 28, 67037 Strasbourg (France); Prevot, G. [Institut de Recherches Subatomiques, B.P. 28, 67037 Strasbourg (France); Renouprez, A. [Institut de Recherche sur la Catalyse, 2 Avenue Albert Einstein, 69626 Villeurbanne (France); Sigward, M.H. [Institut de Recherches Subatomiques, B.P. 28, 67037 Strasbourg (France); Schwaller, B. [Universite de Haute-Alsace, GRPHE, 61, rue Albert Camus, 68093 Mulhouse (France); Voltolini, C. [Institut de Recherches Subatomiques, B.P. 28, 67037 Strasbourg (France)

    1999-01-21

    Characterization results are given for an original ASIC allowing continuous acquisition of ionising radiation images in spectroscopic mode. Ionising radiation imaging in general and spectroscopic imaging in particular must primarily be guided by the attempt to decrease statistical noise, which requires detection systems designed to allow very high counting rates. Any source of dead time must therefore be avoided. Thus, the use of on-line corrections of the inevitable dispersion of characteristics between the large number of electronic channels of the detection system, shall be precluded. Without claiming to achieve ultimate noise levels, the work described is focused on how to prevent good individual acquisition channel noise performance from being totally destroyed by the dispersion between channels without introducing dead times. With this goal, we developed an automatic charge amplifier output voltage offset compensation system which operates regardless of the cause of the offset (detector or electronic). The main performances of the system are the following: the input equivalent noise charge is 190 e rms (input non connected, peaking time 500 ns), the highest gain is 255 mV/fC, the peaking time is adjustable between 200 ns and 2 {mu}s and the power consumption is 10 mW per channel. The agreement between experimental data and theoretical simulation results is excellent.

  8. An important step forward in continuous spectroscopic imaging of ionising radiations using ASICs

    International Nuclear Information System (INIS)

    Fessler, P.; Coffin, J.; Eberle, H.; Raad Iseli, C. de; Hilt, B.; Huss, D.; Krummenacher, F.; Lutz, J.R.; Prevot, G.; Renouprez, A.; Sigward, M.H.; Schwaller, B.; Voltolini, C.

    1999-01-01

    Characterization results are given for an original ASIC allowing continuous acquisition of ionising radiation images in spectroscopic mode. Ionising radiation imaging in general and spectroscopic imaging in particular must primarily be guided by the attempt to decrease statistical noise, which requires detection systems designed to allow very high counting rates. Any source of dead time must therefore be avoided. Thus, the use of on-line corrections of the inevitable dispersion of characteristics between the large number of electronic channels of the detection system, shall be precluded. Without claiming to achieve ultimate noise levels, the work described is focused on how to prevent good individual acquisition channel noise performance from being totally destroyed by the dispersion between channels without introducing dead times. With this goal, we developed an automatic charge amplifier output voltage offset compensation system which operates regardless of the cause of the offset (detector or electronic). The main performances of the system are the following: the input equivalent noise charge is 190 e rms (input non connected, peaking time 500 ns), the highest gain is 255 mV/fC, the peaking time is adjustable between 200 ns and 2 μs and the power consumption is 10 mW per channel. The agreement between experimental data and theoretical simulation results is excellent

  9. Single event effect hardness for the front-end ASICs in the DAMPE satellite BGO calorimeter

    Science.gov (United States)

    Gao, Shan-Shan; Jiang, Di; Feng, Chang-Qing; Xi, Kai; Liu, Shu-Bin; An, Qi

    2016-01-01

    The Dark Matter Particle Explorer (DAMPE) is a Chinese scientific satellite designed for cosmic ray studies with a primary scientific goal of indirect detection of dark matter particles. As a crucial sub-detector, the BGO calorimeter measures the energy spectrum of cosmic rays in the energy range from 5 GeV to 10 TeV. In order to implement high-density front-end electronics (FEE) with the ability to measure 1848 signals from 616 photomultiplier tubes on the strictly constrained satellite platform, two kinds of 32-channel front-end ASICs, VA160 and VATA160, are customized. However, a space mission period of more than 3 years makes single event effects (SEEs) become threats to reliability. In order to evaluate SEE sensitivities of these chips and verify the effectiveness of mitigation methods, a series of laser-induced and heavy ion-induced SEE tests were performed. Benefiting from the single event latch-up (SEL) protection circuit for power supply, the triple module redundancy (TMR) technology for the configuration registers and the optimized sequential design for the data acquisition process, 52 VA160 chips and 32 VATA160 chips have been applied in the flight model of the BGO calorimeter with radiation hardness assurance. Supported by Strategic Priority Research Program on Space Science of the Chinese Academy of Sciences (XDA04040202-4) and Fundamental Research Funds for the Central Universities (WK2030040048)

  10. A Serializer ASIC at 5 Gbps for Detector Front-end Electronics Readout

    CERN Document Server

    Gong, D; The ATLAS collaboration; Liu, T; Xiang, A; Ye, J

    2010-01-01

    High speed and ultra low power serial data transmission over fiber optics plays an essential roll in detector front-end electronics readout for experiments at the LHC. The ATLAS Liquid Argon Calorimeter front-end readout upgrade for the sLHC calls for an optical link system with a data bandwidth of 100 Gbps per each front-end board (FEB), a factor of 62 increase compared with the present optical link system. The transmitter of this optical link will have to withstand the radiation environment where the front-end crates are situated, and stay within the current power dissipation budget limited by the present FEB cooling capacity. To meet these challenges, we developed a 16:1 serializer based on a commercial 0.25 μm silicon-on-sapphire (SOS) CMOS technology. This serializer, designed to work at 5 Gbps, is a key component in an optical link system. Test results of this ASIC will be reported. A system design for the 100 Gbps optical link system will also be presented, with discussions about key components identi...

  11. Automatic Testing of the Trigger Data Serializer ASIC for the Upgrade of the ATLAS Muon Spectrometer

    CERN Document Server

    Pinkham, Reid; Schwarz, Thomas

    The Trigger Data Serializer (TDS) is a custom designed Application Specific Integrated Circuit (ASIC) designed at the University of Michigan to be used on the ATLAS New Small Wheel (NSW) detector. The TDS is a central hub of the NSW trigger system. It prepares the trigger data for both pad and strip detectors, performs pad-strip matching, and serializes the matched strip data to other circuits on the rim of the NSW. In total, 6000 TDS chips will be produced. As part of the TDS’ initial production run, a test platform was developed to verify the functionality of each chip before being sent to users. The test platform consisted of multiple FPGA evaluation boards with custom designed mezzanine boards to hold the TDS chip during testing and control software running on a local computer. Of the initial run of 200 chips, 161 chips were tested with the automatic setup of which 158 passed. Detailed description of the TDS and automatic test fixture can be found in this thesis.

  12. The PASTA chip - A free-running readout ASIC for silicon strip sensors in PANDA

    Energy Technology Data Exchange (ETDEWEB)

    Goerres, Andre; Stockmanns, Tobias; Ritman, James [Institut fuer Kernphysik, Forschungszentrum Juelich, Juelich (Germany); Rivetti, Angelo [INFN Sezione di Torino, Torino (Italy); Collaboration: PANDA-Collaboration

    2014-07-01

    The PANDA experiment is a multi purpose detector, investigating hadron physics in the charm quark mass regime. It is one of the main experiments at the future FAIR accelerator facility, using pp annihilations from a 1.5-15 GeV/c anti-proton beam. Because of the broad physics spectrum and the similarity of event and background signals, PANDA does not rely on a hardware-level trigger decision. The innermost of PANDA's sub-systems is the Micro Vertex Detector (MVD), consisting of silicon pixel and strip sensors. The latter will be read out by a specialized, free-running readout front-end called PANDA Strip ASIC (PASTA). It has to face a high event rate of up to 40 kHz/ch in an radiation-intense environment. To fulfill the MVD's requirements, it has to give accurate timing information to incoming events (<10 ns) and determine the collected charge with an 8-bit precision. The design has to meet cooling and placing restrictions, leading to a very low power consumption (<4 mW/ch) and limited dimensions. Therefore, a simple, time-based readout approach is chosen. In this talk, the conceptual design of the front-end is presented.

  13. The PASTA chip. A free-running readout ASIC for silicon strip sensors in PANDA

    Energy Technology Data Exchange (ETDEWEB)

    Goerres, Andre; Stockmanns, Tobias; Ritman, James [Forschungszentrum Juelich GmbH, Juelich (Germany); Rivetti, Angelo [INFN Sezione di Torino, Torino (Italy); Collaboration: PANDA-Collaboration

    2015-07-01

    The PANDA experiment is a multi purpose detector, investigating hadron physics in the charm quark mass regime. It is one of the main experiments at the future FAIR accelerator facility, using anti pp annihilations from a 1.5-15 GeV/c anti-proton beam. Because of the broad physics spectrum and the similarity of event and background signals, PANDA does an event selection based on the complete raw data of the detector. The innermost of PANDA's sub-systems is the Micro Vertex Detector (MVD), consisting of silicon pixel and strip sensors. The latter will be read out by a specialized, free-running readout front-end called PANDA Strip ASIC (PASTA). It has to face a high event rate of up to 40 kHz/ch in an radiation-intense environment. To fulfill the MVD's requirements, it has to give accurate timing information to incoming events (<10 ns) and determine the collected charge with an 8-bit precision. All this has to be done with a very low power design (<4 mW/ch) on a small footprint with less than 21 mm{sup 2} and 60 μm input pitch for 64 channels per chip. Therefore, a simple, time-based readout approach with two independent thresholds is chosen. In this talk, the conceptual design of the full front-end and some aspects of the digital part are presented.

  14. Systematic study of new types of Hamamatsu MPPCs read out with the NINO ASIC

    CERN Document Server

    Doroud, K; Williams, M C S; Yamamoto, K; Zichichi, A; Zuyeuski, R

    2014-01-01

    Over the last decade there have been commercial TOF-PET scanners constructed using Photo-Multiplier Tubes (PMT) that have achieved View the MathML source~500ps FWHM Coincidence Time Resolution (CTR). A new device known as the Silicon PhotoMultiplier (SiPM) has the potential to overcome some of the limitations of the PMT. Therefore implementing a SiPM based TOF-PET scanner is of high interest. Recently Philips has introduced a TOF-PET scanner that uses digital Silicon PhotoMultipliers (d-SiPMs) which has a CTR of 350 ps. Here we will report on the timing performance of two Hamamatsu 3×3 mm2 analogue-SiPMs read out with the NINO ASIC: this is an ultra-fast amplifier/discriminator with a differential architecture. The differential architecture is very important since the single-ended readout uses the ground as the signal return; as the ground is also the reference level for the discriminators, the result is high crosstalk and degraded time resolution. However differential readout allows the scaling up from a si...

  15. Sensor-based whole-arm obstacle avoidance utilizing ASIC technology

    International Nuclear Information System (INIS)

    Wintenberg, A.L.; Ericson, M.N.; Babcock, S.M.; Armstrong, G.A.; Britton, C.L. Jr.; Butler, P.L.; Hamel, W.R.; Newport, D.F.

    1993-01-01

    Operation of manipulator systems in poorly defined work environments often presents a significant hazard to both the robotic assembly and the environment. In applications relating to the Environmental Restoration and Waste Management (ER ampersand WM) Program, many of the environments are considered hazardous, both, in the structure and composition of the environment Use of a sensing system that provides information to the manipulator control unit regarding obstacles in close proximity will provide protection against collisions. In this paper, a hierarchical design and implementation of a whole-arm obstacle avoidance system is presented. The system is based on capacitive sensors configured as bracelets for proximity sensing. Each bracelet contains a number of sensor nodes and a processor for sensor node control and readout, and communications with a higher level host, common to all bracelets. The host controls the entire sensing network and communicates proximity information to the manipulator controller. The overall architecture of this system is discussed with detail on the individual system modules. Details of an application specific integrated circuit (ASIC) designed to implement the sensor node electronics are presented. Justifications for the general measurement methods and associated implementation are discussed. Additionally, the current state of development including measured dam is presented

  16. Cosmic non-TEM radiation and synthetic feed array sensor system in ASIC mixed signal technology

    Science.gov (United States)

    Centureli, F.; Scotti, G.; Tommasino, P.; Trifiletti, A.; Romano, F.; Cimmino, R.; Saitto, A.

    2014-08-01

    The paper deals with the opportunity to introduce "Not strictly TEM waves" Synthetic detection Method (NTSM), consisting in a Three Axis Digital Beam Processing (3ADBP), to enhance the performances of radio telescope and sensor systems. Current Radio Telescopes generally use the classic 3D "TEM waves" approximation Detection Method, which consists in a linear tomography process (Single or Dual axis beam forming processing) neglecting the small z component. The Synthetic FEED ARRAY three axis Sensor SYSTEM is an innovative technique using a synthetic detection of the generic "NOT strictly TEM Waves radiation coming from the Cosmo, which processes longitudinal component of Angular Momentum too. Than the simultaneous extraction from radiation of both the linear and quadratic information component, may reduce the complexity to reconstruct the Early Universe in the different requested scales. This next order approximation detection of the observed cosmologic processes, may improve the efficacy of the statistical numerical model used to elaborate the same information acquired. The present work focuses on detection of such waves at carrier frequencies in the bands ranging from LF to MMW. The work shows in further detail the new generation of on line programmable and reconfigurable Mixed Signal ASIC technology that made possible the innovative Synthetic Sensor. Furthermore the paper shows the ability of such technique to increase the Radio Telescope Array Antenna performances.

  17. Single channel analog pulse processor Asic for gas proportional counters and SI detector

    International Nuclear Information System (INIS)

    Chandratre, V.B.; Sarkar, Soumen; Kataria, S.K.; Viyogi, Y.P.

    2005-01-01

    The paper presents the design and development of a single channel pulse processor in short Singleplex ASIC targeted for gas proportional counters/Si detectors. The design is optimized for the dynamic range of +500 fC to -500 fC with provision for externally adjusted pole-zero cancellation. A dedicated filter based on the de-convolution principle is used for the cancellation of the long hyperbolic signal tail produced by the slow drift of ions, typical in gas proportional with the filter time constants derived from the actual detector input signal shape. The pole-zero adjustment can be done by external dc voltage to achieve perfect base-line recovery to 1% after 5 μs. The simulated 0 pf noise is 500 e - rms for the peaking time of 1.2 μs with noise slope of 7e - -. The gain is 3.4 mv/fC over the entire linear dynamic range with power dissipation of 13 mW. This design is a modified version of Indiplex chip with features dynamic range equal gain on both polarities with nearly same noise and serves as diagnostic chip for Indiplex. The chip can be used for radiation monitoring instruments. (author)

  18. Latest results of SEE measurements obtained by the STRURED demonstrator ASIC

    Energy Technology Data Exchange (ETDEWEB)

    Candelori, A. [INFN, Section of Padova, Via Marzolo 8, c.a.p. 35131, Padova (Italy); De Robertis, G. [INFN Section of Bari, Via Orabona 4, c.a.p. 70126, Bari (Italy); Gabrielli, A. [Physics Department, University of Bologna, Viale Berti Pichat 6/2, c.a.p. 40127, Bologna (Italy); Mattiazzo, S.; Pantano, D. [INFN, Section of Padova, Via Marzolo 8, c.a.p. 35131, Padova (Italy); Ranieri, A., E-mail: antonio.ranieri@ba.infn.i [INFN Section of Bari, Via Orabona 4, c.a.p. 70126, Bari (Italy); Tessaro, M. [INFN, Section of Padova, Via Marzolo 8, c.a.p. 35131, Padova (Italy)

    2011-01-21

    With the perspective to develop a radiation-tolerant circuit for High Energy Physics (HEP) applications, a test digital ASIC VLSI chip, called STRURED, has been designed and fabricated using a standard-cell library of commercial 130 nm CMOS technology by implementing three different radiation-tolerant architectures (Hamming, Triple Modular Redundancy and Triple Time Redundancy) in order to correct circuit malfunctions induced by the occurrence of Soft Errors (SEs). SEs are one of the main reasons of failures affecting electronic digital circuits operating in harsh radiation environments, such as in experiments performed at HEP colliders or in apparatus to be operated in space. In this paper we present and discuss the latest results of SE cross-section measurements performed using the STRURED digital device, exposed to high energy heavy ions at the SIRAD irradiation facility of the INFN National Laboratories of Legnaro (Padova, Italy). In particular the different behaviors of the input part and the core of the three radiation-tolerant architectures are analyzed in detail.

  19. Development of high performance readout ASICs for silicon photomultipliers (SiPMs)

    International Nuclear Information System (INIS)

    Shen, Wei

    2012-01-01

    Silicon Photomultipliers (SiPMs) are novel kind of solid state photon detectors with extremely high photon detection resolution. They are composed of hundreds or thousands of avalanche photon diode pixels connected in parallel. These avalanche photon diodes are operated in Geiger Mode. SiPMs have the same magnitude of multiplication gain compared to the conventional photomultipliers (PMTs). Moreover, they have a lot of advantages such as compactness, relatively low bias voltage and magnetic field immunity etc. Special readout electronics are required to preserve the high performance of the detector. KLauS and STiC are two CMOS ASIC chips designed in particular for SiPMs. KLauS is used for SiPM charge readout applications. Since SiPMs have a much larger detector capacitance compared to other solid state photon detectors such as PIN diodes and APDs, a few special techniques are used inside the chip to make sure a descent signal to noise ratio for pixel charge signal can be obtained. STiC is a chip dedicated to SiPM time-of-flight applications. High bandwidth and low jitter design schemes are mandatory for such applications where time jitter less than tens of picoseconds is required. Design schemes and error analysis as well as measurement results are presented in the thesis.

  20. Double-differential recording and AGC using microcontrolled variable gain ASIC.

    Science.gov (United States)

    Rieger, Robert; Deng, Shin-Liang

    2013-01-01

    Low-power wearable recording of biopotentials requires acquisition front-ends with high common-mode rejection for interference suppression and adjustable gain to provide an optimum signal range to a cascading analogue-to-digital stage. A microcontroller operated double-differential (DD) recording setup and automatic gain control circuit (AGC) are discussed which reject common-mode interference and provide tunable gain, thus compensating for imbalance and variation in electrode interface impedance. Custom-designed variable gain amplifiers (ASIC) are used as part of the recording setup. The circuit gain and balance is set by the timing of microcontroller generated clock signals. Measured results are presented which confirm that improved common-mode rejection is achieved compared to a single differential amplifier in the presence of input network imbalance. Practical measured examples further validate gain control suitable for biopotential recording and power-line rejection for wearable ECG and EMG recording. The prototype front-end consumes 318 μW including amplifiers and microcontroller.

  1. ASIC Wafer Test System for the ATLAS Semiconductor Tracker Front-End Chip

    International Nuclear Information System (INIS)

    Anghinolfi, F.; Bialas, W.; Busek, N.; Ciocio, A.; Cosgrove, D.; Fadeyev, V.; Flacco, C.; Gilchriese, M.; Grillo, A.A.; Haber, C.; Kaplon, J.; Lacasta, C.; Murray, W.; Niggli, H.; Pritchard, T.; Rosenbaum, F.; Spieler, H.; Stezelberger, T.; Vu, C.; Wilder, M.; Yaver, H.; Zetti, F.

    2002-01-01

    An ASIC wafer test system has been developed to provide comprehensive production screening of the ATLAS Semiconductor Tracker front-end chip (ABCD3T). The ABCD3T[1] features a 128-channel analog front-end, a digital pipeline, and communication circuitry, clocked at 40 MHz, which is the bunch crossing frequency at the LHC (Large Hadron Collider). The tester measures values and tolerance ranges of all critical IC parameters, including DC parameters, electronic noise, time resolution, clock levels and clock timing. The tester is controlled by an FPGA (ORCA3T) programmed to issue the input commands to the IC and to interpret the output data. This allows the high-speed wafer-level IC testing necessary to meet the production schedule. To characterize signal amplitudes and phase margins, the tester utilizes pin-driver, delay, and DAC chips, which control the amplitudes and delays of signals sent to the IC under test. Output signals from the IC under test go through window comparator chips to measure their levels. A probe card has been designed specifically to reduce pick-up noise that can affect the measurements. The system can operate at frequencies up to 100 MHz to study the speed limits of the digital circuitry before and after radiation damage. Testing requirements and design solutions are presented

  2. AC-DC PFC Converter Using Combination of Flyback Converter and Full-bridge DC-DC Converter

    Directory of Open Access Journals (Sweden)

    Moh. Zaenal Efendi

    2014-06-01

    Full Text Available This paper presents a combination of power factor correction converter using Flyback converter and Full-bridge dc-dc converter in series connection. Flyback converter is operated in discontinuous conduction mode so that it can serve as a power factor correction converter and meanwhile Full-bridge dc-dc converter is used for dc regulator. This converter system is designed to produce a 86 Volt of output voltage and 2 A of output current. Both simulation and experiment results show that the power factor of this converter achieves up to 0.99 and meets harmonic standard of IEC61000-3-2. Keywords: Flyback Converter, Full-bridge DC-DC Converter, Power Factor Correction.

  3. Current-to-frequency converter

    Energy Technology Data Exchange (ETDEWEB)

    Glowacki, S W [Institute of Nuclear Research, Warsaw (Poland)

    1981-07-15

    A current-to-frequency converter covering the range from 3 x 10/sup -10/ A up to 3 x 10/sup -5/ A of the input current is described. The circuit operates with nuclear detectors featuring a high internal resistance.

  4. Materials for thermionic energy converters

    NARCIS (Netherlands)

    Wolff, L.R.; Hermans, J.M.; Adriaansen, J.K.M.; Gubbels, G.H.M.; Vincenzini, P.

    1987-01-01

    This paper deals with the design and construction of a combustion heated Thermionic Energy Converter (TEC). Main components of this TEC are: 1. A ''Hot Shell'' protecting the TEC from the combustion environment 2. A ''Ceramic Seal'' electrically insulating the emitter from the collector 3. A

  5. Smart AD and DA Converters

    NARCIS (Netherlands)

    Roermund, van A.H.M.; Hegt, J.A.; Harpe, P.J.A.; Radulov, G.I.; Zanikopoulos, A.; Doris, K.; Quinn, P.J.

    2005-01-01

    In this paper, a concept is proposed to solve the problems related to the embedding of AD and DA converters in system-on-chips, FPGAs or other VLSI solutions. Problems like embedded testing, yield, reliability and reduced design space become crucial bottlenecks in the integration of high-performance

  6. Charge-pump voltage converter

    Science.gov (United States)

    Brainard, John P [Albuquerque, NM; Christenson, Todd R [Albuquerque, NM

    2009-11-03

    A charge-pump voltage converter for converting a low voltage provided by a low-voltage source to a higher voltage. Charge is inductively generated on a transfer rotor electrode during its transit past an inductor stator electrode and subsequently transferred by the rotating rotor to a collector stator electrode for storage or use. Repetition of the charge transfer process leads to a build-up of voltage on a charge-receiving device. Connection of multiple charge-pump voltage converters in series can generate higher voltages, and connection of multiple charge-pump voltage converters in parallel can generate higher currents. Microelectromechanical (MEMS) embodiments of this invention provide a small and compact high-voltage (several hundred V) voltage source starting with a few-V initial voltage source. The microscale size of many embodiments of this invention make it ideally suited for MEMS- and other micro-applications where integration of the voltage or charge source in a small package is highly desirable.

  7. Impedance interactions in bidirectional cascaded converter

    DEFF Research Database (Denmark)

    Tian, Yanjun; Loh, Poh Chiang; Chen, Zhe

    2016-01-01

    A cascaded converter is built by connecting one elementary converter to another. Output impedance of one converter will therefore interact with input impedance of the other converter. This interaction will change when power flow reverses. To compare this difference, an investigation is performed...

  8. Converter Monitoring Unit for Retrofit of Wind Power Converters

    DEFF Research Database (Denmark)

    Rannestad, Bjorn; Maarbjerg, Anders Eggert; Frederiksen, Kristian

    2018-01-01

    A Converter Monitoring Unit (CMU), which will enable condition monitoring of wind turbine converters is presented in this paper. Reducing the cost of corrective maintenance by means of condition monitoring is a way of lowering Operation & Maintenance (O&M) costs for wind turbine systems....... The CMU must be able to detect a broad range of failure modes related to Insulated Gate Bipolar Transistor (IGBT) power modules and associated gate drives. IGBT collector-emitter on-state voltage (vceon) and current (ic) is sampled in the CMU and used for detection of emerging failures. A new method...... for compensation of unwanted inductive voltage drop in the vceon measurement path is presented, enabling retrofitting of CMUs in existing wind turbines. Finally, experimental results obtained on a prototype CMU are presented. Experimentally the vceon dependency to IGBT junction temperature and deterioration...

  9. A 75 ps rms time resolution BiCMOS time to digital converter optimized for high rate imaging detectors

    CERN Document Server

    Hervé, C

    2002-01-01

    This paper presents an integrated time to digital converter (TDC) with a bin size adjustable in the range of 125 to 175 ps and a differential nonlinearity of +-0.3%. The TDC has four channels. Its architecture has been optimized for the readout of imaging detectors in use at Synchrotron Radiation facilities. In particular, a built-in logic flags piled-up events. Multi-hit patterns are also supported for other applications. Time measurements are extracted off chip at the maximum throughput of 40 MHz. The dynamic range is 14 bits. It has been fabricated in 0.8 mu m BiCMOS technology. Time critical inputs are PECL compatible whereas other signals are CMOS compatible. A second application specific integrated circuit (ASIC) has been developed which translates NIM electrical levels to PECL ones. Both circuits are used to assemble board level TDCs complying with industry standards like VME, NIM and PCI.

  10. Parametric study of laser photovoltaic energy converters

    Science.gov (United States)

    Walker, G. H.; Heinbockel, J. H.

    1987-01-01

    Photovoltaic converters are of interest for converting laser power to electrical power in a space-based laser power system. This paper describes a model for photovoltaic laser converters and the application of this model to a neodymium laser silicon photovoltaic converter system. A parametric study which defines the sensitivity of the photovoltaic parameters is described. An optimized silicon photovoltaic converter has an efficiency greater than 50 percent for 1000 W/sq cm of neodymium laser radiation.

  11. Bidirectional dc-to-dc Power Converter

    Science.gov (United States)

    Griesbach, C. R.

    1986-01-01

    Solid-state, series-resonant converter uses high-voltage thyristors. Converter used either to convert high-voltage, low-current dc power to lowvoltage, high current power or reverse. Taking advantage of newly-available high-voltage thyristors to provide better reliability and efficiency than traditional converters that use vacuum tubes as power switches. New converter essentially maintenance free and provides greatly increased mean time between failures. Attractive in industrial applications whether or not bidirectional capability is required.

  12. Radiated EMI from power converters

    Directory of Open Access Journals (Sweden)

    Arnautovski-Toševa Vesna

    2005-01-01

    Full Text Available With the continuous increase of switching frequency together with the ongoing trend to higher complexity and functionality, power converters as a part of electronic systems have raised more and more electromagnetic energy pollution to the local system environment. In the same time, stringent demands are imposed on the designers of new circuits that electromagnetic interference (EMI has to be suppressed at its source before it is allowed to propagate into other circuits and systems. In this paper, the authors present a full-wave numerical method for calculation and simulation of electromagnetic field radiated by power converter circuitry. The main objective is to analyze the layout geometry in order to obtain competitive PCB layout that will enable suitably attenuated level of the radiated electric field to safe level. By this it would be possible to ensure reliable operation of the sensitive electronic components in the proximity.

  13. Vibration converter with magnetic levitation

    Science.gov (United States)

    Gladilin, A. V.; Pirogov, V. A.; Golyamina, I. P.; Kulaev, U. V.; Kurbatov, P. A.; Kurbatova, E. P.

    2015-05-01

    The paper presents a mathematical model, the results of computational and theoretical research, and the feasibility of creating a vibration converter with full magnetic levitation in the suspension of a high-temperature superconductor (HTSC). The axial and radial stability of the active part of the converter is provided by the interaction of the magnetic field of ring-shaped permanent magnets and a hollow cylinder made of the ceramic HTSC material. The force is created by a system of current-carrying coils whose magnetic field is polarized by permanent magnets and interacts with induced currents in the superconducting cylinder. The case of transition to the superconducting state of HTSC material in the field of the permanent magnets (FC mode) is considered. The data confirm the outlook for the proposed technical solutions.

  14. Status of advanced bremsstrahlung converters

    International Nuclear Information System (INIS)

    Halbleib, J.A.

    1980-01-01

    This paper is an attempt to review the somewhat ill-defined area of advanced converter research in a more or less chronological fashion. Section 2 reviews the early B/sub z/ work that was motivated by the CASINO project. More recent work makes liberal use of technology from ICF research using REBs is discussed in Sec. 3. Section 4 discusses possible directions for future research, some of which are being actively pursued at Sandia National Laboratories (SNL) and elsewhere

  15. Computerized simulation of converter process

    Energy Technology Data Exchange (ETDEWEB)

    Jalkanen, H; Suomi, M L; Wallgren, M [Helsinki Univ. of Technology, Otaniemi (Finland). Lab. of Metallurgy

    1997-12-31

    Converter process is essentially an oxidising refining process aiming in addition to (1) the primary refining action, decarburisation of high carbon iron melt, also to (2) maximal elimination of impurity elements, especially silicon, phosphorus and sulphur, (3) melting of substantial amounts of scrap using the extra heat released in oxidation reactions and (4) to exact final steel temperature control, optimal for further treatments. `Quantitative modelling of such a complex non-stationary chemical process as oxygen converting necessitates extensive formulation of chemical and thermal evolution of the process in connection with the technological properties of the reactor and the process control measures. A comprehensive converter simulation program like CONSIM-3. 1 and its preceding versions that is based on the theoretical and practical knowledge on the process can be used for (1) educating specialists and smelter personnel, (2) planning of the blowing programs, (3) developing and testing of process control systems and after some elaboration and restructuring (4) it can be integrated to static or dynamic process control systems. (orig.) SULA 2 Research Programme; 10 refs.

  16. Computerized simulation of converter process

    Energy Technology Data Exchange (ETDEWEB)

    Jalkanen, H.; Suomi, M.L.; Wallgren, M. [Helsinki Univ. of Technology, Otaniemi (Finland). Lab. of Metallurgy

    1996-12-31

    Converter process is essentially an oxidising refining process aiming in addition to (1) the primary refining action, decarburisation of high carbon iron melt, also to (2) maximal elimination of impurity elements, especially silicon, phosphorus and sulphur, (3) melting of substantial amounts of scrap using the extra heat released in oxidation reactions and (4) to exact final steel temperature control, optimal for further treatments. `Quantitative modelling of such a complex non-stationary chemical process as oxygen converting necessitates extensive formulation of chemical and thermal evolution of the process in connection with the technological properties of the reactor and the process control measures. A comprehensive converter simulation program like CONSIM-3. 1 and its preceding versions that is based on the theoretical and practical knowledge on the process can be used for (1) educating specialists and smelter personnel, (2) planning of the blowing programs, (3) developing and testing of process control systems and after some elaboration and restructuring (4) it can be integrated to static or dynamic process control systems. (orig.) SULA 2 Research Programme; 10 refs.

  17. Systematic study of new types of Hamamatsu MPPCs read out with the NINO ASIC

    Energy Technology Data Exchange (ETDEWEB)

    Doroud, K. [Museo Storico della Fisica e Centro Studi e Ricerche E. Fermi, Roma (Italy); Rodriguez, A. [CERN, Geneva (Switzerland); ICSC World Laboratory, Geneva (Switzerland); Williams, M.C.S., E-mail: crispin.williams@cern.ch [CERN, Geneva (Switzerland); INFN and Dipartimento di Fisica e Astronomia, Università di Bologna (Italy); Yamamoto, K. [Solid State Division, Hamamatsu Photonics K.K., Hamamatsu (Japan); Zichichi, A. [Museo Storico della Fisica e Centro Studi e Ricerche E. Fermi, Roma (Italy); CERN, Geneva (Switzerland); INFN and Dipartimento di Fisica e Astronomia, Università di Bologna (Italy); Zuyeuski, R. [CERN, Geneva (Switzerland); ICSC World Laboratory, Geneva (Switzerland)

    2014-07-01

    Over the last decade there have been commercial TOF-PET scanners constructed using Photo-Multiplier Tubes (PMT) that have achieved ∼500ps FWHM Coincidence Time Resolution (CTR). A new device known as the Silicon PhotoMultiplier (SiPM) has the potential to overcome some of the limitations of the PMT. Therefore implementing a SiPM based TOF-PET scanner is of high interest. Recently Philips has introduced a TOF-PET scanner that uses digital Silicon PhotoMultipliers (d-SiPMs) which has a CTR of 350 ps. Here we will report on the timing performance of two Hamamatsu 3×3 mm{sup 2} analogue-SiPMs read out with the NINO ASIC: this is an ultra-fast amplifier/discriminator with a differential architecture. The differential architecture is very important since the single-ended readout uses the ground as the signal return; as the ground is also the reference level for the discriminators, the result is high crosstalk and degraded time resolution. However differential readout allows the scaling up from a single cell to a multi-cell device with no loss of time resolution; this becomes increasingly important for the highly segmented detectors that are being built today, both for particle and for medical instrumentation. We obtained excellent results for both the Single Photon Time Resolution (SPTR) and for the CTR using a LYSO crystal of 15 mm length. Such a crystal length has sufficient detection efficiency for 511 keV gammas to make an excellent PET device. The results presented here are proof that a TOF-PET detector with a CTR of 175 ps is indeed possible. This is the first step that defines the starting point of our SuperNINO project.

  18. Systematic study of new types of Hamamatsu MPPCs read out with the NINO ASIC

    International Nuclear Information System (INIS)

    Doroud, K.; Rodriguez, A.; Williams, M.C.S.; Yamamoto, K.; Zichichi, A.; Zuyeuski, R.

    2014-01-01

    Over the last decade there have been commercial TOF-PET scanners constructed using Photo-Multiplier Tubes (PMT) that have achieved ∼500ps FWHM Coincidence Time Resolution (CTR). A new device known as the Silicon PhotoMultiplier (SiPM) has the potential to overcome some of the limitations of the PMT. Therefore implementing a SiPM based TOF-PET scanner is of high interest. Recently Philips has introduced a TOF-PET scanner that uses digital Silicon PhotoMultipliers (d-SiPMs) which has a CTR of 350 ps. Here we will report on the timing performance of two Hamamatsu 3×3 mm 2 analogue-SiPMs read out with the NINO ASIC: this is an ultra-fast amplifier/discriminator with a differential architecture. The differential architecture is very important since the single-ended readout uses the ground as the signal return; as the ground is also the reference level for the discriminators, the result is high crosstalk and degraded time resolution. However differential readout allows the scaling up from a single cell to a multi-cell device with no loss of time resolution; this becomes increasingly important for the highly segmented detectors that are being built today, both for particle and for medical instrumentation. We obtained excellent results for both the Single Photon Time Resolution (SPTR) and for the CTR using a LYSO crystal of 15 mm length. Such a crystal length has sufficient detection efficiency for 511 keV gammas to make an excellent PET device. The results presented here are proof that a TOF-PET detector with a CTR of 175 ps is indeed possible. This is the first step that defines the starting point of our SuperNINO project

  19. MUSIC: An 8 channel readout ASIC for SiPM arrays

    Science.gov (United States)

    Gómez, Sergio; Gascón, David; Fernández, Gerard; Sanuy, Andreu; Mauricio, Joan; Graciani, Ricardo; Sanchez, David

    2016-04-01

    This paper presents an 8 channel ASIC for SiPM anode readout based on a novel low input impedance current conveyor (under patent1). This Multiple Use SiPM Integrated Circuit (MUSIC) has been designed to serve several purposes, including, for instance, the readout of SiPM arrays for some of the Cherenkov Telescope Array (CTA) cameras. The current division scheme at the very front end part of the circuit splits the input current into differently scaled copies which are connected to independent current mirrors. The circuit contains a tunable pole zero cancellation of the SiPM recovery time constant to deal with sensors from different manufacturers. Decay times up to 100 ns are supported covering most of the available SiPM devices in the market. MUSIC offers three main features: (1) differential output of the sum of the individual input channels; (2) 8 individual single ended analog outputs and; (3) 8 individual binary outputs. The digital outputs encode the amount of collected charge in the duration of the digital signal using a time over threshold technique. For each individual channel, the user must select the analog or digital output. Each functionality, the signal sum and the 8 A/D outputs, include a selectable dual-gain configuration. Moreover, the signal sum implements dual-gain output providing a 15 bit dynamic range. Full die simulation results of the MUSIC designed using AMS 0.35 µm SiGe technology are presented: total die size of 9 mm2, 500 MHz bandwidth for channel sum and 150 MHz bandwidth for A/D channels, low input impedance (≍32 Ω), single photon output pulse width at half maximum (FWHM) between 5 and 10 ns and with a power consumption of ≍ 30 mW/ch plus ≍ 200 mW for the 8 ch sum. Encapsulated prototype samples of the MUSIC are expected by March 2016.

  20. Revisiting the Role of TRP, Orai, and ASIC Channels in the Pulmonary Arterial Response to Hypoxia

    Directory of Open Access Journals (Sweden)

    Roberto V. Reyes

    2018-05-01

    Full Text Available The pulmonary arteries are exquisitely responsive to oxygen changes. They rapidly and proportionally contract as arterial PO2 decrease, and they relax as arterial PO2 is re-established. The hypoxic pulmonary vasoconstriction (HPV is intrinsic since it does not require neural or endocrine factors, as evidenced in isolated vessels. On the other hand, pulmonary arteries also respond to sustained hypoxia with structural and functional remodeling, involving growth of smooth muscle medial layer and later recruitment of adventitial fibroblasts, secreted mitogens from endothelium and changes in the response to vasoconstrictor and vasodilator stimuli. Hypoxic pulmonary arterial vasoconstriction and remodeling are relevant biological responses both under physiological and pathological conditions, to explain matching between ventilation and perfusion, fetal to neonatal transition of pulmonary circulation and pulmonary artery over-constriction and thickening in pulmonary hypertension. Store operated channels (SOC and receptor operated channels (ROC are plasma membrane cationic channels that mediate calcium influx in response to depletion of internal calcium stores or receptor activation, respectively. They are involved in both HPV and pathological remodeling since their pharmacological blockade or genetic suppression of several of the Stim, Orai, TRP, or ASIC proteins in SOC or ROC complexes attenuate the calcium increase, the tension development, the pulmonary artery smooth muscle proliferation, and pulmonary arterial hypertension. In this Mini Review, we discussed the evidence obtained in in vivo animal models, at the level of isolated organ or cells of pulmonary arteries, and we identified and discussed the questions for future research needed to validate these signaling complexes as targets against pulmonary hypertension.

  1. Development of a Compact Matrix Converter

    Directory of Open Access Journals (Sweden)

    J. Bauer

    2009-01-01

    Full Text Available This paper deals with the development of a matrix converter. Matrix converters belong to the category of direct frequency converters. A converter does not contain DC-link and the output voltage is provided by direct switching of voltage from the input phases. This is enabled by 9 bidirectional switches, which are provided by anti-serial connection of 18 IGBT transistors. The absence of a DC-link is great advantage of the matrix converter, but it also increases the requirements on the converter control. For this reason a new prototype of a matrix converter is being developed with sophisticated modern components (FPGA, Power PC equipped in the control part of the converter. The converter will be used for testing new control algorithms and commutation methods. 

  2. Detector Control and Data Acquisition for the Wide-Field Infrared Survey Telescope (WFIRST) with a Custom ASIC

    Science.gov (United States)

    Smith, Brian S.; Loose, Markus; Alkire, Greg; Joshi, Atul; Kelly, Daniel; Siskind, Eric; Rossetti, Dino; Mah, Jonathan; Cheng, Edward; Miko, Laddawan; hide

    2016-01-01

    The Wide-Field Infrared Survey Telescope (WFIRST) will have the largest near-IR focal plane ever flown by NASA, a total of 18 4K x 4K devices. The project has adopted a system-level approach to detector control and data acquisition where 1) control and processing intelligence is pushed into components closer to the detector to maximize signal integrity, 2) functions are performed at the highest allowable temperatures, and 3) the electronics are designed to ensure that the intrinsic detector noise is the limiting factor for system performance. For WFIRST, the detector arrays operate at 90 to 100 K, the detector control and data acquisition functions are performed by a custom ASIC at 150 to 180 K, and the main data processing electronics are at the ambient temperature of the spacecraft, notionally approx.300 K. The new ASIC is the main interface between the cryogenic detectors and the warm instrument electronics. Its single-chip design provides basic clocking for most types of hybrid detectors with CMOS ROICs. It includes a flexible but simple-to-program sequencer, with the option of microprocessor control for more elaborate readout schemes that may be data-dependent. All analog biases, digital clocks, and analog-to-digital conversion functions are incorporated and are connected to the nearby detectors with a short cable that can provide thermal isolation. The interface to the warm electronics is simple and robust through multiple LVDS channels. It also includes features that support parallel operation of multiple ASICs to control detectors that may have more capability or requirements than can be supported by a single chip.

  3. Development and characterisation of a front-end ASIC for macro array of photo-detectors of large dimensions

    International Nuclear Information System (INIS)

    Conforti Di Lorenzo, S.

    2010-10-01

    The coverage of large areas of photo-detection is a crucial element of experiments studying high energy atmospheric cosmic showers and neutrinos from different sources. The objective of this project is to realize big detectors using thousands of photomultipliers (PMT). The project proposes to segment the large surface of photo-detection into macro pixels consisting of an array of 16 PMT of 12 inches (2*2 m 2 ), connected to an autonomous front-end electronics which works in without-trigger data acquisition mode placed near the array. This is possible thanks to the microelectronics progress that allows to integrate the readout and the signal processing, of all the multipliers, in the same circuit (ASIC) named PARISROC (Photomultiplier Array Integrated ins SiGe Read Out Chip). The ASIC must only send out the digital data by network to the surface central data storage. The PARISROC chip made in AM's Silicon Germanium (SiGe) 0.35 μm technology, integrates 16 independent channels for each PMT of the array, providing charge and time measurements. The first prototype of PARISROC chip has a total surface of 19 mm 2 . The ASIC measurements have led to the realization of a second prototype. Important measurements were performed in terms of noise, dynamic range, readout frequency (from 10 MHz to 40 MHz), time measurements (TDC improvements) and charge measurements (Slow shaper improvements). This new prototype of PARISROC-2 has been tested and the characterisation has shown a good overall behavior and the verification of the improvements. (author)

  4. Characterization and performance of monolithic detector blocks with a dedicated ASIC front-end readout for PET imaging of the human brain

    International Nuclear Information System (INIS)

    Rato Mendes, Pedro; Sarasola Martin, Iciar; Canadas, Mario; Garcia de Acilu, Paz; Cuypers, Robin; Perez, Jose Manuel; Willmott, Carlos

    2011-01-01

    We are developing a human brain PET scanner prototype compatible with MRI based on monolithic scintillator crystals, APD matrices and a dedicated ASIC front-end readout. In this work we report on the performance of individual detector modules and on the operation of such modules in PET coincidence. Results will be presented on the individual characterization of detector blocks and its ASIC front-end readout, with measured energy resolutions of 13% full-width half-maximum (FWHM) at 511 keV and spatial resolutions of the order of 2 mm FWHM. First results on PET coincidence performance indicate spatial resolutions as good as 2.1 mm FWHM for SSRB/FBP reconstruction of tomographic data obtained using a simple PET demonstrator based on a pair of monolithic detector blocks with ASIC readout.

  5. Threshold equalization algorithm for the XAA1.2 ASICs and its application to SuperAGILE X-ray imager

    Energy Technology Data Exchange (ETDEWEB)

    Pacciani, Luigi [Istituto di Fisica Spaziale e Fisica Cosmica, INAF, Roma, via Fosso del Cavaliere, 100-I-00133 Roma (Italy)], E-mail: luigi.pacciani@iasf-roma.inaf.it; Uberti, Olga; Del Monte, Ettore; Argan, Andrea; Feroci, Marco; Soffitta, Paolo; Trois, Alessio; Costa, Enrico; Donnarumma, Immacolata; Evangelista, Yuri; Lazzarotto, Francesco [Istituto di Fisica Spaziale e Fisica Cosmica, INAF, Roma, via Fosso del Cavaliere, 100-I-00133 Roma (Italy); Rapisarda, Massimo [ENEA C.R. Frascati, via Enrico Fermi, 45, I-00044 Frascati (RM) (Italy); Morelli, Ennio [Istituto di Fisica Spaziale e Fisica Cosmica, INAF, Bologna, via P. Gobetti, 101-I-40129 Bologna (Italy); Mastropietro, Marcello [Istituto dei Sistemi Complessi, CNR, Roma, via Salaria, km 29300, I-00016 Monterotondo Scalo (RM) c.p. 10 (Italy); Rubini, Alda [Istituto di Fisica Spaziale e Fisica Cosmica, INAF, Roma, via Fosso del Cavaliere, 100-I-00133 Roma (Italy)

    2008-08-11

    In this paper we report the procedure developed and the results achieved for the equalization of threshold levels for the 6144 discriminator units of XAA1.2 ASICs chosen for the SuperAGILE X-ray imager onboard the AGILE satellite. For these kinds of imager, we will show that the threshold equalization is a critical issue. For each XAA1.2 we reduced the threshold dispersion by a factor of 3-4, and a factor of {approx}2 for daisy chains of ASICs. Despite the method being developed for XAA1.2, the discriminator units and threshold fine-adjustment circuits are common to other chips of XA and VA-TA family, so that the algorithm and results can be extended to these two families of ASICs. This work may be useful for the design of electronic boards where the threshold equalization is a crucial issue.

  6. Threshold equalization algorithm for the XAA1.2 ASICs and its application to SuperAGILE X-ray imager

    International Nuclear Information System (INIS)

    Pacciani, Luigi; Uberti, Olga; Del Monte, Ettore; Argan, Andrea; Feroci, Marco; Soffitta, Paolo; Trois, Alessio; Costa, Enrico; Donnarumma, Immacolata; Evangelista, Yuri; Lazzarotto, Francesco; Rapisarda, Massimo; Morelli, Ennio; Mastropietro, Marcello; Rubini, Alda

    2008-01-01

    In this paper we report the procedure developed and the results achieved for the equalization of threshold levels for the 6144 discriminator units of XAA1.2 ASICs chosen for the SuperAGILE X-ray imager onboard the AGILE satellite. For these kinds of imager, we will show that the threshold equalization is a critical issue. For each XAA1.2 we reduced the threshold dispersion by a factor of 3-4, and a factor of ∼2 for daisy chains of ASICs. Despite the method being developed for XAA1.2, the discriminator units and threshold fine-adjustment circuits are common to other chips of XA and VA-TA family, so that the algorithm and results can be extended to these two families of ASICs. This work may be useful for the design of electronic boards where the threshold equalization is a crucial issue

  7. Role of peripheral sigma-1 receptors in ischaemic pain: Potential interactions with ASIC and P2X receptors.

    Science.gov (United States)

    Kwon, S G; Roh, D H; Yoon, S Y; Choi, S R; Choi, H S; Moon, J Y; Kang, S Y; Kim, H W; Han, H J; Beitz, A J; Oh, S B; Lee, J H

    2016-04-01

    The role of peripheral sigma-1 receptors (Sig-1Rs) in normal nociception and in pathologically induced pain conditions has not been thoroughly investigated. Since there is mounting evidence that Sig-1Rs modulate ischaemia-induced pathological conditions, we investigated the role of Sig-1Rs in ischaemia-induced mechanical allodynia (MA) and addressed their possible interaction with acid-sensing ion channels (ASICs) and P2X receptors at the ischaemic site. We used a rodent model of hindlimb thrombus-induced ischaemic pain (TIIP) to investigate their role. Western blot was performed to observe changes in Sig-1R expression in peripheral nervous tissues. MA was measured after intraplantar (i.pl.) injections of antagonists for the Sig-1, ASIC and P2X receptors in TIIP rats or agonists of each receptor in naïve rats. Sig-1R expression significantly increased in skin, sciatic nerve and dorsal root ganglia at 3 days post-TIIP surgery. I.pl. injections of the Sig-1R antagonist, BD-1047 on post-operative days 0-3 significantly attenuated the development of MA during the induction phase, but had no effect on MA when given during the maintenance phase (days 3-6 post-surgery). BD-1047 synergistically increased amiloride (an ASICs blocker)- and TNP-ATP (a P2X antagonist)-induced analgesic effects in TIIP rats. In naïve rats, i.pl. injection of Sig-1R agonist PRE-084 alone did not produce MA; but it did induce MA when co-administered with either an acidic pH solution or a sub-effective dose of αβmeATP. Peripheral Sig-1Rs contribute to the induction of ischaemia-induced MA via facilitation of ASICs and P2X receptors. Thus, peripheral Sig-1Rs represent a novel therapeutic target for the treatment of ischaemic pain. © 2015 European Pain Federation - EFIC®

  8. Conceptual design of the TRACE detector readout using a compact, dead time-less analog memory ASIC

    OpenAIRE

    Aliaga Varea, Ramón José; Herrero Bosch, Vicente; Capra, S.; Pullia, A.; Dueñas, J. A.; Grassi, L.; Triossi, A.; Domingo Pardo, C.; Gadea Gironés, Rafael; González, V.; Hüyük, T.; Sanchís, E.; Gadea, A.; Mengoni, D.

    2015-01-01

    The new TRacking Array for light Charged particle Ejectiles (TRACE) detector system requires monitorization and sampling of all pulses in a large number of channels with very strict space and power consumption restrictions for the front-end electronics and cabling. Its readout system is to be based on analog memory ASICs with 64 channels each that sample a View the MathML source window of the waveform of any valid pulses at 200 MHz while discarding any other signals and are read out at 50 MHz...

  9. Simulation Results of Double Forward Converter

    Directory of Open Access Journals (Sweden)

    P. Vijaya KUMAR

    2009-12-01

    Full Text Available This work aims to find a better forward converter for DC to DC conversion.Simulation of double forward converter in SMPS system is discussed in this paper. Aforward converter with RCD snubber to synchronous rectifier and/or to current doubleris also discussed. The evolution of the forward converter is first reviewed in a tutorialfashion. Performance parameters are discussed including operating principle, voltageconversion ratio, efficiency, device stress, small-signal dynamics, noise and EMI. Itscircuit operation and its performance characteristics of the forward converter with RCDsnubber and double forward converter are described and the simulation results arepresented.

  10. FF-EMU: a radiation tolerant ASIC for the distribution of timing, trigger and control signals in the CMS End-Cap Muon detector

    International Nuclear Information System (INIS)

    Campagnari, C; Costantino, N; Magazzù, G; Tongiani, Claudio

    2012-01-01

    A radiation tolerant integrated circuit for the distribution of clock, trigger and control signals in the Front-End electronics of the CMS End-Cap Muon detector has been developed in the IBM CMOS 130nm technology. The circuit houses transmitter and receiver interfaces to serial links implementing the FF-LYNX protocol that allows the integrated transmission of triggers and data frames with different latency constraints. Encoder and decoder modules associate signal transitions to FF-LYNX frames. The system and the ASIC architecture and behavior and the results of test and characterization of the ASIC prototypes will be presented.

  11. Conception and test of an integrated circuit (ASIC): application to multiwire chambers and photomultipliers of the GRAAL experience; Conception et test d`un circuit integre (ASIC): application aux chambres multifils et aux photomultiplicateurs de l`experience GRAAL

    Energy Technology Data Exchange (ETDEWEB)

    Bugnet, H.

    1995-11-21

    The nuclear physics project GRAAL (GRenoble Anneau Accelerateur Laser) located at the European Synchrotron Radiation Facility (ESRF) in Grenoble produces a high energy photon beam with a maximum energy of 1.5 GeV. This gamma beam is obtained by Compton backscattering and can be polarized easily. It permits to probe, in an original way, the structure of the nucleon. The associated detector system includes multiwire proportional chambers and scintillator hodoscopes. A kit of six ASICs (Application Specific Integrated Circuit) has been developed and used for the signal processing and data conditioning up to the level of the data acquisition. This integrated electronics can be mounted right on the detectors. Obvious advantages, due to the reduction of the length of the wires and the number of connections, are an improvement of the signal quality and an increase of the reliability. The Wire Processor (WP), ASIC designed and tested during this thesis, treats the signals from the chamber wires and the photomultipliers. In one chip, there are two identical channels permitting the amplification, the amplitude discrimination, the generation of a programmable delay and the writing in a two state memory in case of coincidence with an external strobe signal. The measurement of the multiwire chamber efficiency demonstrates the functioning of the WP, the data conditioning electronics, the data acquisition and the chamber itself. (author). 62 refs., 111 figs., 13 tabs.

  12. Auxiliary resonant DC tank converter

    Science.gov (United States)

    Peng, Fang Z.

    2000-01-01

    An auxiliary resonant dc tank (ARDCT) converter is provided for achieving soft-switching in a power converter. An ARDCT circuit is coupled directly across a dc bus to the inverter to generate a resonant dc bus voltage, including upper and lower resonant capacitors connected in series as a resonant leg, first and second dc tank capacitors connected in series as a tank leg, and an auxiliary resonant circuit comprising a series combination of a resonant inductor and a pair of auxiliary switching devices. The ARDCT circuit further includes first clamping means for holding the resonant dc bus voltage to the dc tank voltage of the tank leg, and second clamping means for clamping the resonant dc bus voltage to zero during a resonant period. The ARDCT circuit resonantly brings the dc bus voltage to zero in order to provide a zero-voltage switching opportunity for the inverter, then quickly rebounds the dc bus voltage back to the dc tank voltage after the inverter changes state. The auxiliary switching devices are turned on and off under zero-current conditions. The ARDCT circuit only absorbs ripples of the inverter dc bus current, thus having less current stress. In addition, since the ARDCT circuit is coupled in parallel with the dc power supply and the inverter for merely assisting soft-switching of the inverter without participating in real dc power transmission and power conversion, malfunction and failure of the tank circuit will not affect the functional operation of the inverter; thus a highly reliable converter system is expected.

  13. Electromechanical converters for electric vehicles

    Science.gov (United States)

    Ambros, T.; Burduniuc, M.; Deaconu, S. I.; Rujanschi, N.

    2018-01-01

    The paper presents the analysis of various constructive schemes of synchronous electromechanical converters with permanent magnets fixed on the rotor and asynchronous with the short-circuit rotor. Various electrical stator winding schemes have also been compared, demonstrating the efficiency of copper utilization in toroidal windings. The electromagnetic calculus of the axial machine has particularities compared to the cylindrical machine, in the paper is presented the method of correlating the geometry of the cylindrical and axial machines. In this case the method and recommendations used in the design of such machines may be used.

  14. Power electronics converters and regulators

    CERN Document Server

    Dokić, Branko L

    2015-01-01

    This book is the result of the extensive experience the authors gained through their year-long occupation at the Faculty of Electrical Engineering at the University of Banja Luka. Starting at the fundamental basics of electrical engineering, the book guides the reader into this field and covers all the relevant types of converters and regulators. Understanding is enhanced by the given examples, exercises and solutions. Thus this book can be used as a textbook for students, for self-study or as a reference book for professionals.

  15. OAM mode converter in twisted fibers

    DEFF Research Database (Denmark)

    Usuga Castaneda, Mario A.; Beltran-Mejia, Felipe; Cordeiro, Cristiano

    2014-01-01

    We analyze the case of an OAM mode converter based on a twisted fiber, through finite element simulations where we exploit an equivalence between geometric and material transformations. The obtained converter has potential applications in MDM. © 2014 OSA.......We analyze the case of an OAM mode converter based on a twisted fiber, through finite element simulations where we exploit an equivalence between geometric and material transformations. The obtained converter has potential applications in MDM. © 2014 OSA....

  16. A new concept of thermionic converter

    International Nuclear Information System (INIS)

    Musa, G.

    1978-10-01

    The parameters of a new type of thermionic converter which has a number of concentric electrodes, is computed. The obtained theoretical efficiency of this new type of converter is nearly the efficiency of the ideal thermionic converter. The obtained results are explained by the reduction of the radiation loss from the emitter due to the electrode configuration. Efficiencies as high as 20% are expected from this type of converter now in construction. (author)

  17. Spectrometric analog-to-digital converter

    International Nuclear Information System (INIS)

    Ormandzhiev, S.I.; Jordanov, V.T.

    1988-01-01

    Converter of digit-by-digit counterbalancing with slipping dial with number of channels equal to total number of states of the main digital-to-analog converter of digit-by-digit counterbalancing systems is presented. Algorithm for selection of digital-to-analog converters, which must be used by means of computer is suggested

  18. A novel series-resonant converter topology

    NARCIS (Netherlands)

    Tilgenkamp, N.V.; Haan, de S.W.H.; Huisman, H.

    1987-01-01

    A converter topology based on the principles of seriesresonant (SR) power conversion is described in which the input and output of this converter have one terminal in common, and the transformer is omitted. Both the underlying theory and associated waveforms are presented. The converter is suitable

  19. An efficient ASIC implementation of 16-channel on-line recursive ICA processor for real-time EEG system.

    Science.gov (United States)

    Fang, Wai-Chi; Huang, Kuan-Ju; Chou, Chia-Ching; Chang, Jui-Chung; Cauwenberghs, Gert; Jung, Tzyy-Ping

    2014-01-01

    This is a proposal for an efficient very-large-scale integration (VLSI) design, 16-channel on-line recursive independent component analysis (ORICA) processor ASIC for real-time EEG system, implemented with TSMC 40 nm CMOS technology. ORICA is appropriate to be used in real-time EEG system to separate artifacts because of its highly efficient and real-time process features. The proposed ORICA processor is composed of an ORICA processing unit and a singular value decomposition (SVD) processing unit. Compared with previous work [1], this proposed ORICA processor has enhanced effectiveness and reduced hardware complexity by utilizing a deeper pipeline architecture, shared arithmetic processing unit, and shared registers. The 16-channel random signals which contain 8-channel super-Gaussian and 8-channel sub-Gaussian components are used to analyze the dependence of the source components, and the average correlation coefficient is 0.95452 between the original source signals and extracted ORICA signals. Finally, the proposed ORICA processor ASIC is implemented with TSMC 40 nm CMOS technology, and it consumes 15.72 mW at 100 MHz operating frequency.

  20. Conception and test of an integrated circuit (ASIC): application to multiwire chambers and photomultipliers of the GRAAL experience

    International Nuclear Information System (INIS)

    Bugnet, H.

    1995-01-01

    The nuclear physics project GRAAL (GRenoble Anneau Accelerateur Laser) located at the European Synchrotron Radiation Facility (ESRF) in Grenoble produces a high energy photon beam with a maximum energy of 1.5 GeV. This gamma beam is obtained by Compton backscattering and can be polarized easily. It permits to probe, in an original way, the structure of the nucleon. The associated detector system includes multiwire proportional chambers and scintillator hodoscopes. A kit of six ASICs (Application Specific Integrated Circuit) has been developed and used for the signal processing and data conditioning up to the level of the data acquisition. This integrated electronics can be mounted right on the detectors. Obvious advantages, due to the reduction of the length of the wires and the number of connections, are an improvement of the signal quality and an increase of the reliability. The Wire Processor (WP), ASIC designed and tested during this thesis, treats the signals from the chamber wires and the photomultipliers. In one chip, there are two identical channels permitting the amplification, the amplitude discrimination, the generation of a programmable delay and the writing in a two state memory in case of coincidence with an external strobe signal. The measurement of the multiwire chamber efficiency demonstrates the functioning of the WP, the data conditioning electronics, the data acquisition and the chamber itself. (author). 62 refs., 111 figs., 13 tabs

  1. Multi-time-over-threshold technique for photomultiplier signal processing: Description and characterization of the SCOTT ASIC

    International Nuclear Information System (INIS)

    Ferry, S.; Guilloux, F.; Anvar, S.; Chateau, F.; Delagnes, E.; Gautard, V.; Louis, F.; Monmarthe, E.; Le Provost, H.; Russo, S.; Schuller, J.-P.; Stolarczyk, Th.; Vallage, B.; Zonca, E.

    2012-01-01

    KM3NeT aims to build a cubic-kilometer scale neutrino telescope in the Mediterranean Sea based on a 3D array of photomultiplier tubes. A dedicated ASIC, named SCOTT, has been developed for the readout electronics of the PMTs: it uses up to 16 adjustable thresholds to digitize the signals with the multi-time-over-threshold technique. Digital outputs of discriminators feed a circular sampling memory and a “first in first out” digital memory for derandomization. At the end of the data processing, the ASIC produces a digital waveform sampled at 800 MHz. A specific study was carried out to process PMT data and has showed that five specifically chosen thresholds are suited to reach the required timing precision. A dedicated method based on the duration of the signal over a given threshold allows an equivalent timing precision at any charge. A charge estimator using the information from the thresholds allows a charge determination within less than 20% up to 60 pe.

  2. Multi-time-over-threshold technique for photomultiplier signal processing: Description and characterization of the SCOTT ASIC

    Science.gov (United States)

    Ferry, S.; Guilloux, F.; Anvar, S.; Chateau, F.; Delagnes, E.; Gautard, V.; Louis, F.; Monmarthe, E.; Le Provost, H.; Russo, S.; Schuller, J.-P.; Stolarczyk, Th.; Vallage, B.; Zonca, E.; Representing the KM3NeT Consortium

    2012-12-01

    KM3NeT aims to build a cubic-kilometer scale neutrino telescope in the Mediterranean Sea based on a 3D array of photomultiplier tubes. A dedicated ASIC, named SCOTT, has been developed for the readout electronics of the PMTs: it uses up to 16 adjustable thresholds to digitize the signals with the multi-time-over-threshold technique. Digital outputs of discriminators feed a circular sampling memory and a “first in first out” digital memory for derandomization. At the end of the data processing, the ASIC produces a digital waveform sampled at 800 MHz. A specific study was carried out to process PMT data and has showed that five specifically chosen thresholds are suited to reach the required timing precision. A dedicated method based on the duration of the signal over a given threshold allows an equivalent timing precision at any charge. A charge estimator using the information from the thresholds allows a charge determination within less than 20% up to 60 pe.

  3. Prototype board development for the validation of the VMM ASICs for the New Small Wheel ATLAS upgrade project

    CERN Document Server

    Gkountoumis, Panagiotis; The ATLAS collaboration

    2018-01-01

    The VMM is a custom Application Specific Integrated Circuit (ASIC) which was designed to be used in the front-end readout electronics of both micromegas (MM) and small Thin Gap Chambers (sTGC) detectors of the New Small Wheel (NSW) Phase-I upgrade project of the ATLAS experiment. A new version of the VMM was recently fabricated and for that reason various prototype boards, the micromegas Front-End (MMFE1) and the General Purpose VMM (GPVMM), have been fabricated and extensively tested in order to validate the functionality of the ASIC. These boards use commercial Field Programmable Gate Arrays (FPGAs) for direct communication with computers which is achieved through 10/100/1000 Mbps Ethernet and UDP/IP protocols. The low noise performance of these boards gave the opportunity to be used in various test beams with micromegas detectors for validating the VMM and for performance studies of the sTGC detectors. A detailed description of the boards along with the results of the test beam and the detector studies wi...

  4. Prototype board development for the validation of the VMM ASICs for the New Small Wheel ATLAS upgrade project

    CERN Document Server

    Gkountoumis, Panagiotis; The ATLAS collaboration

    2018-01-01

    The VMM is a custom Application Specific Integrated Circuit (ASIC) which was designed to be used in the frontend readout electronics of both micromegas (MM) and small Thin Gap Chambers (sTGC) detectors of the New Small Wheel (NSW) Phase-I upgrade project of the ATLAS experiment. A new version of the VMM was recently fabricated and for that reason various prototype boards, the micromegas Front-End (MMFE1) and the General Purpose VMM (GPVMM), have been fabricated and extensively tested in order to validate the functionality of the ASIC. These boards use commercial Field Programmable Gate Arrays (FPGAs) for direct communication with computers which is achieved through 10=100=1000 Mbps Ethernet and UDP/IP protocols. The low noise performance of these boards gave the opportunity to be used in various test beams with micormegas detectors for validating the VMM and for performance studies of the sTGC detectors. A detailed description of the boards along with the results of the test beam and the detector studies will...

  5. Pixel readout ASIC for an APD based 2D X-ray hybrid pixel detector with sub-nanosecond resolution

    Energy Technology Data Exchange (ETDEWEB)

    Thil, Ch., E-mail: christophe.thil@ziti.uni-heidelberg.d [Heidelberg University, Institute of Computer Engineering, B6, 26, 68161 Mannheim (Germany); Baron, A.Q.R. [RIKEN SPring-8 Center, 1-1-1 Kouto, Sayo-cho, Sayo-gun, Hyogo 679-5148 (Japan); Fajardo, P. [ESRF, Polygone Scientifique Louis Neel, 6, rue Jules Horowitz, 38000 Grenoble (France); Fischer, P. [Heidelberg University, Institute of Computer Engineering, B6, 26, 68161 Mannheim (Germany); Graafsma, H. [DESY, Notkestrasse 85, 22607 Hamburg (Germany); Rueffer, R. [ESRF, Polygone Scientifique Louis Neel, 6, rue Jules Horowitz, 38000 Grenoble (France)

    2011-02-01

    The fast response and the short recovery time of avalanche photodiodes (APDs) in linear mode make those devices ideal for direct X-ray detection in applications requiring high time resolution or counting rate. In order to provide position sensitivity, the XNAP project aims at creating a hybrid pixel detector with nanosecond time resolution based on a monolithic APD sensor array with 32 x32 pixels covering about 1 cm{sup 2} active area. The readout is implemented in a pixelated front-end ASIC suited for the readout of such arrays, matched to pixels of 280{mu}mx280{mu}m size. Every single channel features a fast transimpedance amplifier, a discriminator with locally adjustable threshold and two counters with high dynamic range and counting speed able to accumulate X-ray hits with no readout dead time. Additionally, the detector can be operated in list mode by time-stamping every single event with sub-nanosecond resolution. In a first phase of the project, a 4x4 pixel test module is built to validate the conceptual design of the detector. The XNAP project is briefly presented and the performance of the readout ASIC is discussed.

  6. Pixel readout ASIC for an APD based 2D X-ray hybrid pixel detector with sub-nanosecond resolution

    International Nuclear Information System (INIS)

    Thil, Ch.; Baron, A.Q.R.; Fajardo, P.; Fischer, P.; Graafsma, H.; Rueffer, R.

    2011-01-01

    The fast response and the short recovery time of avalanche photodiodes (APDs) in linear mode make those devices ideal for direct X-ray detection in applications requiring high time resolution or counting rate. In order to provide position sensitivity, the XNAP project aims at creating a hybrid pixel detector with nanosecond time resolution based on a monolithic APD sensor array with 32 x32 pixels covering about 1 cm 2 active area. The readout is implemented in a pixelated front-end ASIC suited for the readout of such arrays, matched to pixels of 280μmx280μm size. Every single channel features a fast transimpedance amplifier, a discriminator with locally adjustable threshold and two counters with high dynamic range and counting speed able to accumulate X-ray hits with no readout dead time. Additionally, the detector can be operated in list mode by time-stamping every single event with sub-nanosecond resolution. In a first phase of the project, a 4x4 pixel test module is built to validate the conceptual design of the detector. The XNAP project is briefly presented and the performance of the readout ASIC is discussed.

  7. Molten-salt converter reactors

    International Nuclear Information System (INIS)

    Perry, A.M.

    1975-01-01

    Molten-salt reactors appear to have substantial promise as advanced converters. Conversion ratios of 0.85 to 0.9 should be attainable with favourable fuel cycle costs, with 235 U valued at $12/g. An increase in 235 U value by a factor of two or three ($10 to $30/lb. U 3 O 8 , $75/SWU) would be expected to increase the optimum conversion ratio, but this has not been analyzed in detail. The processing necessary to recover uranium from the fuel salt has been partially demonstrated in the MSRE. The equipment for doing this would be located at the reactor, and there would be no reliance on an established recycle industry. Processing costs are expected to be quite low, and fuel cycle optimization depends primarily on inventory and burnup or replacement costs for the fuel and for the carrier salt. Significant development problems remain to be resolved for molten-salt reactors, notably the control of tritium and the elimination of intergranular cracking of Hastelloy-N in contact with tellurium. However, these problems appear to be amenable to solution. It is appropriate to consider separating the development schedule for molten-salt reactors from that for the processing technology required for breeding. The Molten-Salt Converter Reactor should be a useful reactor in its own right and would be an advance towards the achievement of true breeding in thermal reactors. (author)

  8. Hybrid thermionic-photovoltaic converter

    Energy Technology Data Exchange (ETDEWEB)

    Datas, A. [Instituto de Energía Solar, Universidad Politécnica de Madrid, 28040 Madrid (Spain)

    2016-04-04

    A conceptual device for the direct conversion of heat into electricity is presented. This concept hybridizes thermionic (TI) and thermophotovoltaic (TPV) energy conversion in a single thermionic-photovoltaic (TIPV) solid-state device. This device transforms into electricity both the electron and photon fluxes emitted by an incandescent surface. This letter presents an idealized analysis of this device in order to determine its theoretical potential. According to this analysis, the key advantage of this converter, with respect to either TPV or TI, is the higher power density in an extended temperature range. For low temperatures, TIPV performs like TPV due to the negligible electron flux. On the contrary, for high temperatures, TIPV performs like TI due to the great enhancement of the electron flux, which overshadows the photon flux contribution. At the intermediate temperatures, ∼1650 K in the case of this particular study, I show that the power density potential of TIPV converter is twice as great as that of TPV and TI. The greatest impact concerns applications in which the temperature varies in a relatively wide range, for which averaged power density enhancement above 500% is attainable.

  9. Valuing Convertible Bonds Based on LSRQM Method

    Directory of Open Access Journals (Sweden)

    Jian Liu

    2014-01-01

    Full Text Available Convertible bonds are one of the essential financial products for corporate finance, while the pricing theory is the key problem to the theoretical research of convertible bonds. This paper demonstrates how to price convertible bonds with call and put provisions using Least-Squares Randomized Quasi-Monte Carlo (LSRQM method. We consider the financial market with stochastic interest rates and credit risk and present a detailed description on calculating steps of convertible bonds value. The empirical results show that the model fits well the market prices of convertible bonds in China’s market and the LSRQM method is effective.

  10. Converting pest insects into food

    DEFF Research Database (Denmark)

    Offenberg, Hans Joachim; Wiwatwittaya, Decha

    2010-01-01

    Canopy dwelling weaver ants (Oecophylla spp.) are used to control a variety of pests in a number of tropical tree crops. What is less familiar is the existence of commercial markets where these ants and their brood are sold for (i) human consumption, (ii) pet food or (iii) traditional medicine...... on management, 32-115 kg ant brood (mainly new queens) was harvested per ha per year without detrimental effect on colony survival and worker ant densities. This suggest that ant biocontrol and ant harvest can be sustainable integrated in plantations and double benefits derived. As ant production is fuelled...... by pest insects, problematic pests are converted into food and additional earnings. To assess the profitability of providing additional food for the ants, O. smaragdina food conversion efficiency (ECI) was estimated in the laboratory. This estimate suggests the feeding of weaver ants in ant farms...

  11. Efficiency of Capacitively Loaded Converters

    DEFF Research Database (Denmark)

    Andersen, Thomas; Huang, Lina; Andersen, Michael A. E.

    2012-01-01

    This paper explores the characteristic of capacitance versus voltage for dielectric electro active polymer (DEAP) actuator, 2kV polypropylene film capacitor as well as 3kV X7R multi layer ceramic capacitor (MLCC) at the beginning. An energy efficiency for capacitively loaded converters...... is introduced as a definition of efficiency. The calculated and measured efficiency curves for charging DEAP actuator, polypropylene film capacitor and X7R MLCC are provided and compared. The attention has to be paid for the voltage dependent capacitive load, like X7R MLCC, when evaluating the charging...... polypropylene film capacitor can be the equivalent capacitive load. Because of the voltage dependent characteristic, X7R MLCC cannot be used to replace the DEAP actuator. However, this type of capacitor can be used to substitute the capacitive actuator with voltage dependent property at the development phase....

  12. Dorsal root ganglion neurons innervating skeletal muscle respond to physiological combinations of protons, ATP, and lactate mediated by ASIC, P2X, and TRPV1.

    Science.gov (United States)

    Light, Alan R; Hughen, Ronald W; Zhang, Jie; Rainier, Jon; Liu, Zhuqing; Lee, Jeewoo

    2008-09-01

    The adequate stimuli and molecular receptors for muscle metaboreceptors and nociceptors are still under investigation. We used calcium imaging of cultured primary sensory dorsal root ganglion (DRG) neurons from C57Bl/6 mice to determine candidates for metabolites that could be the adequate stimuli and receptors that could detect these stimuli. Retrograde DiI labeling determined that some of these neurons innervated skeletal muscle. We found that combinations of protons, ATP, and lactate were much more effective than individually applied compounds for activating rapid calcium increases in muscle-innervating dorsal root ganglion neurons. Antagonists for P2X, ASIC, and TRPV1 receptors suggested that these three receptors act together to detect protons, ATP, and lactate when presented together in physiologically relevant concentrations. Two populations of muscle-innervating DRG neurons were found. One responded to low metabolite levels (likely nonnoxious) and used ASIC3, P2X5, and TRPV1 as molecular receptors to detect these metabolites. The other responded to high levels of metabolites (likely noxious) and used ASIC3, P2X4, and TRPV1 as their molecular receptors. We conclude that a combination of ASIC, P2X5 and/or P2X4, and TRPV1 are the molecular receptors used to detect metabolites by muscle-innervating sensory neurons. We further conclude that the adequate stimuli for muscle metaboreceptors and nociceptors are combinations of protons, ATP, and lactate.

  13. The VFAT3-Comm-Port: a complete communication port for front-end ASICs intended for use within the high luminosity radiation environments of the LHC

    International Nuclear Information System (INIS)

    Dabrowski, M.; Aspell, P.; Bonacini, S.; Ciaglia, D.; Kloukinas, K.; Lentdecker, G. De; Robertis, G. De; Kupiainen, M.; Talvitie, J.; Tuuva, T.; Leroux, P.; Tavernier, F.

    2015-01-01

    This paper presents the VFAT3 Comm-Port (V3CP), which offers a single port for all communication to and from a front-end ASIC within the HL-LHC environment. This includes synchronization to the LHC clock, slow control communication, the execution of fast control commands and the readout of data

  14. A Front-End ASIC with Receive Sub-array Beamforming Integrated with a 32 × 32 PZT Matrix Transducer for 3-D Transesophageal Echocardiography

    NARCIS (Netherlands)

    Chen, C.; Chen, Z.; Bera, Deep; Raghunathan, S.B.; ShabaniMotlagh, M.; Noothout, E.C.; Chang, Z.Y.; Ponte, Jacco; Prins, Christian; Vos, H.J.; Bosch, Johan G.; Verweij, M.D.; de Jong, N.; Pertijs, M.A.P.

    2017-01-01

    This paper presents a power-and area-efficient front-end application-specific integrated circuit (ASIC) that is directly integrated with an array of 32 × 32 piezoelectric transducer elements to enable next-generation miniature ultrasound probes for real-time 3-D transesophageal echocardiography.

  15. Acid and stretch, but not capsaicin, are effective stimuli for ATP release in the porcine bladder mucosa: Are ASIC and TRPV1 receptors involved?

    Science.gov (United States)

    Sadananda, Prajni; Kao, Felicity C L; Liu, Lu; Mansfield, Kylie J; Burcher, Elizabeth

    2012-05-15

    Stretch-evoked ATP release from the bladder mucosa is a key event in signaling bladder fullness. Our aim was to examine whether acid and capsaicin can also release ATP and to determine the receptors involved, using agonists and antagonists at TRPV1 and acid-sensing ion channels (ASICs). Strips of porcine bladder mucosa were exposed to acid, capsaicin or stretch. Strip tension was monitored. Bath fluid was collected for ATP measurement. Gene expression of ASICs and TRPV1 in porcine bladders was quantified using quantitative real-time PCR (qRT-PCR). Stretch stimulus (150% of original length) repeatedly and significantly increased ATP release to approximately 45 times basal release. Acid (pH 6.5, 6.0, 5.6) contracted mucosal strips and also increased ATP release up to 30-fold, without evidence of desensitization. Amiloride (0.3 μM) reduced the acid-evoked ATP release by approximately 70%, while capsazepine (10 μM) reduced acid-evoked ATP release at pH 6.0 and pH 5.6 (by 68% and 61%, respectively). Capsaicin (0.1-10 μM) was ineffective in causing ATP release, and also failed to contract porcine mucosal or detrusor strips. Gene expression for ASIC1, ASIC2, ASIC3 and TRPV1 was seen in the lateral wall, dome, trigone and neck of both detrusor and mucosa. In conclusion, stretch and acid induce ATP release in the porcine bladder mucosa, but capsaicin is ineffective. The pig bladder is a well-known model for the human bladder, however these data suggest that it should be used with caution, particularly for TRPV1 related studies. Copyright © 2012 Elsevier B.V. All rights reserved.

  16. The TDCpix readout ASIC: A 75 ps resolution timing front-end for the NA62 Gigatracker hybrid pixel detector

    Energy Technology Data Exchange (ETDEWEB)

    Kluge, A., E-mail: alexander.kluge@cern.ch; Aglieri Rinella, G.; Bonacini, S.; Jarron, P.; Kaplon, J.; Morel, M.; Noy, M.; Perktold, L.; Poltorak, K.

    2013-12-21

    The TDCpix is a novel pixel readout ASIC for the NA62 Gigatracker detector. NA62 is a new experiment being installed at the CERN Super Proton Synchrotron. Its Gigatracker detector shall provide on-beam tracking and time stamping of individual particles with a time resolution of 150 ps rms. It will consist of three tracking stations, each with one hybrid pixel sensor. The peak flow of particles crossing the detector modules reaches 1.27 MHz/mm{sup 2} for a total rate of about 0.75 GHz. Ten TDCpix chips will be bump-bonded to every silicon pixel sensor. Each chip shall perform time stamping of 100 M particle hits per second with a detection efficiency above 99% and a timing accuracy better than 200 ps rms for an overall three-station-setup time resolution of better than 150 ps. The TDCpix chip has been designed in a 130 nm CMOS technology. It will feature 45×40 square pixels of 300×300μm{sup 2} and a complex End of Column peripheral region including an array of TDCs based on DLLs, four high speed serializers, a low-jitter PLL, readout and control circuits. This contribution will describe the complete design of the final TDCpix ASIC. It will discuss design choices, the challenges faced and some of the lessons learned. Furthermore, experimental results from the testing of circuit prototypes will be presented. These demonstrate the achievement of key performance figures such as a time resolution of the processing chain of 75 ps rms with a laser sent to the center of the pixel and the capability of time stamping charged particles with an overall resolution below 200 ps rms. -- Highlights: • Feasibility demonstration of a silicon pixel detector with sub-ns time tagging capability. • Demonstrator detector assembly with a time resolution of 75 ps RMS with laser charge injection; 170 ps RMS with particle beam. • Design of trigger-less TDCpix ASIC with 1800 pixels, 720 TDC channels and 4 3.2 Gbit/s serializers.

  17. Simulation of the High Performance Time to Digital Converter for the ATLAS Muon Spectrometer trigger upgrade

    International Nuclear Information System (INIS)

    Meng, X.T.; Levin, D.S.; Chapman, J.W.; Zhou, B.

    2016-01-01

    The ATLAS Muon Spectrometer endcap thin-Resistive Plate Chamber trigger project compliments the New Small Wheel endcap Phase-1 upgrade for higher luminosity LHC operation. These new trigger chambers, located in a high rate region of ATLAS, will improve overall trigger acceptance and reduce the fake muon trigger incidence. These chambers must generate a low level muon trigger to be delivered to a remote high level processor within a stringent latency requirement of 43 bunch crossings (1075 ns). To help meet this requirement the High Performance Time to Digital Converter (HPTDC), a multi-channel ASIC designed by CERN Microelectronics group, has been proposed for the digitization of the fast front end detector signals. This paper investigates the HPTDC performance in the context of the overall muon trigger latency, employing detailed behavioral Verilog simulations in which the latency in triggerless mode is measured for a range of configurations and under realistic hit rate conditions. The simulation results show that various HPTDC operational configurations, including leading edge and pair measurement modes can provide high efficiency (>98%) to capture and digitize hits within a time interval satisfying the Phase-1 latency tolerance.

  18. Circular waveguide mode converters at 140 GHz

    International Nuclear Information System (INIS)

    Trulsen, J.; Woskoboinikow, P.; Temkin, R.J.

    1986-01-01

    A unified derivation of the coupled mode equations for circular waveguide is presented. Also, approximate design criteria for TE/sub 0n/ to TE/sub 0n'/ axisymmetric, TE 01 to TE 11 wriggle, and TE 01 to TM 11 bend converters are reviewed. Numerically solving the coupled mode equations, an optimized set of mode converters has been designed for conversion of a 2 millimeter wave TE 03 mode into TE 11 . This set consists of axisymmetric TE 03 to TE 02 and TE 02 to TE 01 converters followed by a wriggle TE 01 to TE 11 converter. This mode converter set was fabricated and tested using a 3 kW, 137 GHz gyrotron. A TE 11 mode purity of better than 97% was achieved. The TE 01 to TE 11 wriggle converter was experimentally optimized for a measured conversion efficiency of better than 99% not including ohmic losses

  19. Ocean floor mounting of wave energy converters

    Science.gov (United States)

    Siegel, Stefan G

    2015-01-20

    A system for mounting a set of wave energy converters in the ocean includes a pole attached to a floor of an ocean and a slider mounted on the pole in a manner that permits the slider to move vertically along the pole and rotate about the pole. The wave energy converters can then be mounted on the slider to allow adjustment of the depth and orientation of the wave energy converters.

  20. A 290 mV Sub-V(T) ASIC for Real-Time Atrial Fibrillation Detection.

    Science.gov (United States)

    Andersson, Oskar; Chon, Ki H; Sornmo, Leif; Rodrigues, Joachim Neves

    2015-06-01

    A real-time detector for episodes of atrial fibrillation is fabricated as an application specific integrated circuit (ASIC). The basis for detection is a set of three parameters for characterizing the RR interval series, i.e., turning point ratio, root mean square of successive differences, and Shannon entropy. The developed hardware architecture targets ultra-low voltage operation, suitable for implantable loop recorders with ultra-low energy requirements. Algorithmic and architectural optimizations are performed to minimize area and energy dissipation, with a total area footprint reduction of 44%. The design is fabricated in 65-nm CMOS low-leakage high-threshold technology. Measurements with aggressively scaled supply voltage (VDD) in the subthreshold (sub-VT) region show energy savings of up to 41 X when operating at 1 kHz with a VDD of 300 mV compared to a nominal VDD of 1.2 V.

  1. Development of a multi-channel front-end electronics module based on ASIC for silicon strip array detectors

    International Nuclear Information System (INIS)

    Zhao Xingwen; Yan Duo; Su Hong; Qian Yi; Kong Jie; Zhang Xueheng; Li Zhankui; Li Haixia

    2014-01-01

    The silicon strip array detector is one of external target facility subsystems in the Cooling Storage Ring on the Heavy Ion Research Facility at Lanzhou (HIRFL-CSR). Using the ASICs, the front-end electronics module has been developed for the silicon strip array detectors and can implement measurement of energy of 96 channels. The performance of the front-end electronics module has been tested. The energy linearity of the front-end electronics module is better than 0.3% for the dynamic range of 0.1∼0.7 V. The energy resolution is better than 0.45%. The maximum channel crosstalk is better than 10%. The channel consistency is better than 1.3%. After continuously working for 24 h at room temperature, the maximum drift of the zero-peak is 1.48 mV. (authors)

  2. Characterization of a wide dynamic-range, radiation-tolerant charge-digitizer asic for monitoring of Beam losses

    CERN Document Server

    Guido Venturini, G G; Dehning, B; Kayal, M

    2012-01-01

    An Application Specific Integrated Circuit (ASIC) has been designed and fabricated to provide a compact solution to digitize current signals from ionization chambers and diamond detectors, employed as beam loss monitors at CERN and several other high energy physics facilities. The circuit topology has been devised to accept positive and negative currents, to have a wide dynamic range (above 120 dB), withstand radiation levels over 10 Mrad and offer different modes of operation, covering a broad range of applications. Furthermore, an internal conversion reference is employed in the digitization, to provide an accurate absolute measurement. This paper discusses the detailed characterization of the first prototype: linearity, radiation tolerance and temperature dependence of the conversion, as well as implications and system-level considerations regarding its use for beam instrumentation applications in a high energy physics facility.

  3. CBC2: A CMS microstrip readout ASIC with logic for track-trigger modules at HL-LHC

    Energy Technology Data Exchange (ETDEWEB)

    Hall, G., E-mail: g.hall@imperial.ac.uk [Blackett Laboratory, Imperial College, London SW7 2AZ (United Kingdom); Pesaresi, M.; Raymond, M. [Blackett Laboratory, Imperial College, London SW7 2AZ (United Kingdom); Braga, D.; Jones, L.; Murray, P.; Prydderch, M. [Rutherford Appleton Laboratory, Chilton, Didcot, Oxon OX11 OQX (United Kingdom); Abbaneo, D.; Blanchot, G.; Honma, A.; Kovacs, M.; Vasey, F. [CERN, CH-1211, Geneva (Switzerland)

    2014-11-21

    The CBC2 is the latest version of the CMS Binary Chip ASIC for readout of the upgraded CMS Tracker at the High Luminosity LHC. It is designed in 130 nm CMOS with 254 input channels and will be bump-bonded to a substrate to which sensors will be wire-bonded. The CBC2 is designed to instrument double layer modules, consisting of two overlaid silicon microstrip sensors with aligned microstrips, in the outer tracker. It incorporates logic to identify L1 trigger primitives in the form of “stubs”: high transverse-momentum track candidates which are identified within the low momentum background by selecting correlated hits between two closely separated microstrip sensors. The first prototype modules have been assembled. The performance of the chip in recent laboratory tests is briefly reported and the status of module construction described.

  4. Vacuum-insulated catalytic converter

    Science.gov (United States)

    Benson, David K.

    2001-01-01

    A catalytic converter has an inner canister that contains catalyst-coated substrates and an outer canister that encloses an annular, variable vacuum insulation chamber surrounding the inner canister. An annular tank containing phase-change material for heat storage and release is positioned in the variable vacuum insulation chamber a distance spaced part from the inner canister. A reversible hydrogen getter in the variable vacuum insulation chamber, preferably on a surface of the heat storage tank, releases hydrogen into the variable vacuum insulation chamber to conduct heat when the phase-change material is hot and absorbs the hydrogen to limit heat transfer to radiation when the phase-change material is cool. A porous zeolite trap in the inner canister absorbs and retains hydrocarbons from the exhaust gases when the catalyst-coated substrates and zeolite trap are cold and releases the hydrocarbons for reaction on the catalyst-coated substrate when the zeolite trap and catalyst-coated substrate get hot.

  5. Semi-automatic logarithmic converter of logs

    International Nuclear Information System (INIS)

    Gol'dman, Z.A.; Bondar's, V.V.

    1974-01-01

    Semi-automatic logarithmic converter of logging charts. An original semi-automatic converter was developed for use in converting BK resistance logging charts and the time interval, ΔT, of acoustic logs from a linear to a logarithmic scale with a specific ratio for subsequent combining of them with neutron-gamma logging charts in operative interpretation of logging materials by a normalization method. The converter can be used to increase productivity by giving curves different from those obtained in manual, pointwise processing. The equipment operates reliably and is simple in use. (author)

  6. Multilevel converters for 10 MW Wind Turbines

    DEFF Research Database (Denmark)

    Ma, Ke; Blaabjerg, Frede

    2011-01-01

    Several promising multi-level converter configurations for 10 MW Wind Turbines both with direct drive and one-stage gear box drive using Permanent Magnet Synchronous Generator (PMSG) are proposed, designed and compared. Reliability is a crucial indicator for large scale wind power converters...... that the three-level and five-level H-bridge converter topologies both have potential to achieve improved thermal performances compared to the three-level Neutral-Point-Clamped converter topology in the wind power application....

  7. Commutation Processes in Multiresonant ZVS Bridge Converter

    Directory of Open Access Journals (Sweden)

    Miroslaw Luft

    2008-01-01

    Full Text Available The analysis of the multiresonant ZVS DC/DC bridge converter is presented. The control system of the converter is basedon the method of frequency control at the constant time of transistor turn-off with a phase shift. The operation of the circuit is givenand the operating range of the converter is defined where ZVS switching operation is assured. Control characteristics are given andthe converter’s efficiency is defined. The circuit’s operation is analysed on the basis of results of the converter simulation tests using Simplorer programme.

  8. Cyclophosphamide-induced cystitis reduces ASIC channel but enhances TRPV1 receptor function in rat bladder sensory neurons.

    Science.gov (United States)

    Dang, Khoa; Bielefeldt, Klaus; Gebhart, G F

    2013-07-01

    Using patch-clamp techniques, we studied the plasticity of acid-sensing ion channels (ASIC) and transient receptor potential V1 (TRPV1) channel function in dorsal root ganglia (DRG) neurons retrogradely labeled from the bladder. Saline (control) or cyclophosphamide (CYP) was given intraperitoneally on days 1, 3, and 5. On day 6, lumbosacral (LS, L6-S2) or thoracolumbar (TL, T13-L2) DRG were removed and dissociated. Bladders and bladder DRG neurons from CYP-treated rats showed signs of inflammation (greater myeloperoxidase activity; lower intramuscular wall pH) and increased size (whole cell capacitance), respectively, compared with controls. Most bladder neurons (>90%) responded to protons and capsaicin. Protons produced multiphasic currents with distinct kinetics, whereas capsaicin always triggered a sustained response. The TRPV1 receptor antagonist A-425619 abolished capsaicin-triggered currents and raised the threshold of heat-activated currents. Prolonged exposure to an acidic environment (pH range: 7.2 to 6.6) inhibited proton-evoked currents, potentiated the capsaicin-evoked current, and reduced the threshold of heat-activated currents in LS and TL bladder neurons. CYP treatment reduced density but not kinetics of all current components triggered by pH 5. In contrast, CYP-treatment was associated with an increased current density in response to capsaicin in LS and TL bladder neurons. Correspondingly, heat triggered current at a significantly lower temperature in bladder neurons from CYP-treated rats compared with controls. These results reveal that cystitis differentially affects TRPV1- and ASIC-mediated currents in both bladder sensory pathways. Acidification of the bladder wall during inflammation may contribute to changes in nociceptive transmission mediated through the TRPV1 receptor, suggesting a role for TRPV1 in hypersensitivity associated with cystitis.

  9. SENSROC4: An Multichannel Low-Noise Front-End Readout ASIC Dedicated to CZT Detectors for PET Imaging

    International Nuclear Information System (INIS)

    Gao, W.; Liu, H.; Gao, D.; Gan, B.; Wei, T.; Hu, Y.

    2013-06-01

    In this paper, we present the design of a novel low-noise front-end readout application-specific integrated circuit (ASIC) for our small animal PET systems which objective is to achieve the following performances, the spatial resolution of 1 mm 3 , the detection efficiency of 15 % and the time resolution of 1 ns. A cascade amplifier based on the PMOS input transistor is selected to realize the charge-sensitive amplifier (CSA) for the sake of good noise performances. The output of the CSA is split into two branches. One is connected to a slow shaper for energy measurements. The other is connected to a fast shaper for time acquisition. A novel monostable circuit is designed to adjust the time delay of the trigger signals so that the peak value of the shaped voltages can be sampled and stored. Based on the above techniques, an eight-channel front-end readout prototype chip is designed and implemented in 0.35 μm CMOS process. The die size is 2.286 mm x 2.282 mm. The input range of the ASIC is from 2000 e- to 180000 e-, reflecting to the energy of the gamma ray from 11.2 keV to 1 MeV. The gain of the readout channel is 65 V/pC. The best test result of ENC is 86.5 e- at zero farad plus 9.3 e- per pico-farad. The nonlinearity is less than 3 %. The crosstalk is less than 2 %. The power dissipation is about 9 mW/channel (authors)

  10. ASIC or PIC? Implantable stimulators based on semi-custom CMOS technology or low-power microcontroller architecture.

    Science.gov (United States)

    Salmons, S; Gunning, G T; Taylor, I; Grainger, S R; Hitchings, D J; Blackhurst, J; Jarvis, J C

    2001-01-01

    To gain a better understanding of the effects of chronic stimulation on mammalian muscles we needed to generate patterns of greater variety and complexity than simple constant-frequency or burst patterns. We describe here two approaches to the design of implantable neuromuscular stimulators that can satisfy these requirements. Devices of both types were developed and used in long-term experiments. The first device was based on a semi-custom Application Specific Integrated Circuit (ASIC). This approach has the advantage that the circuit can be completely tested at every stage of development and production, assuring a high degree of reliability. It has the drawback of inflexibility: the patterns are produced by state machines implemented in silicon, so each new set of patterns requires a fresh production run, which is costly and time-consuming. The second device was based on a commercial microcontroller (Microchip PIC16C84). The functionality of this type of circuit is specified in software rather than in silicon hardware, allowing a single device to be programmed for different functions. With the use of features designed to improve fault-tolerance we found this approach to be as reliable as that based on ASICs. The encapsulated devices can easily be accommodated subcutaneously on the flank of a rabbit and a recent version is small enough to implant into the peritoneal cavity of rats. The current devices are programmed with a predetermined set of 12 patterns before assembly; the desired pattern is selected after implantation with an electronic flash gun. The operating current drain is less than 40 microA.

  11. Step-Up DC-DC converters

    DEFF Research Database (Denmark)

    Forouzesh, Mojtaba; Siwakoti, Yam P.; Gorji, Saman A.

    2017-01-01

    on the general law and framework of the development of next-generation step-up dc-dc converters, this paper aims to comprehensively review and classify various step-up dc-dc converters based on their characteristics and voltage-boosting techniques. In addition, the advantages and disadvantages of these voltage...

  12. Present trends in HVDC converter station design

    Energy Technology Data Exchange (ETDEWEB)

    Carlsson, Lennart; Asplund, Gunnar; Bjorklund, Hans; Flisberg, Gunnar [ABB Power Systems AB, Ludvika (Sweden)

    1994-12-31

    HVDC converter station technology has developed rapidly to satisfy increasing requirements during past 10 - 15 years, but there has not been any dramatic changes since thyristor valves were introduced in the mid 70s. This paper describes some recent and expected future developments, that will substantiality change and simplify future converter stations. (author) 4 refs., 7 figs.

  13. Luminescent converter of neodymium laser radiation

    International Nuclear Information System (INIS)

    Ryba-Romanowski, W.; Golab, S.

    1992-01-01

    The new luminescent converter of neodymium laser radiation has been worked out. Activated inorganic compounds of ytterbium and erbium ions has been used as luminescent agent. The multi-component inorganic glass containing tellurium oxide as well as boron, sodium, magnesium and zinc oxides has been applied as a converter matrix

  14. Time-Interleaved Analog to Digital Converters

    NARCIS (Netherlands)

    Louwsma, S.M.; van Tuijl, Adrianus Johannes Maria; Nauta, Bram

    2010-01-01

    This book describes the research carried out by our PhD student Simon Louwsma at the University of Twente, The Netherlands in the field of high-speed Analogto- Digital (AD) converters. AD converters are crucial circuits for modern systems where information is stored or processed in digital form. Due

  15. Switched-mode converters (one quadrant)

    CERN Document Server

    Barrade, P

    2006-01-01

    Switched-mode converters are DC/DC converters that supply DC loads with a regulated output voltage, and protection against overcurrents and short circuits. These converters are generally fed from an AC network via a transformer and a conventional diode rectifier. Switched-mode converters (one quadrant) are non-reversible converters that allow the feeding of a DC load with unipolar voltage and current. The switched-mode converters presented in this contribution are classified into two families. The first is dedicated to the basic topologies of DC/DC converters, generally used for low- to mid-power applications. As such structures enable only hard commutation processes, the main drawback of such topologies is high commutation losses. A typical multichannel evolution is presented that allows an interesting decrease in these losses. Deduced from this direct DC/DC converter, an evolution is also presented that allows the integration of a transformer into the buck and the buck–boost structure. This enables an int...

  16. Controller for a wave energy converter

    Science.gov (United States)

    Wilson, David G.; Bull, Diana L.; Robinett, III, Rush D.

    2015-09-22

    A wave energy converter (WEC) is described, the WEC including a power take off (PTO) that converts relative motion of bodies of the WEC into electrical energy. A controller controls operation of the PTO, causing the PTO to act as a motor to widen a wave frequency spectrum that is usable to generate electrical energy.

  17. Full range ZVS DC-DC converter

    International Nuclear Information System (INIS)

    Upadhyay, Rinki; Badapanda, M.K.; Hannurkar, P.R.

    2011-01-01

    A 500 V, 24 Amp DC-DC converter with digital signal processor (DSP) based control and protection has been designed, fabricated and tested. Its power circuit consists of IGBT based single phase inverter bridge, ferrite transformer and diode rectifier. All IGBTs in the inverter bridge are operated in zero voltage switching (ZVS) mode to minimize switching losses thereby increasing the efficiency of the converter significantly. The efficiency of this converter is measured to be greater than 97% at full load. In a conventional full bridge inverter, typically ZVS is achieved under full load condition while at light load ZVS is lost. An auxiliary LC circuit has been intentionally incorporated in this converter to achieve ZVS even at light loaded conditions. Detailed simulation of the converter circuit is carried out and crucial waveforms have been presented in this paper. Microchip make dsPIC30F2020 DSP is employed to provide phase shifted PWMs to IGBTs in the inverter bridge. All the crucial parameters are also monitored by this DSP and in case of any unfavorable conditions, the converter is tripped off. Suitable experiments were carried out in this DC-DC converter under different loaded conditions and a close match between the simulated and experimental results were obtained. Such DC-DC converters can be connected in series or parallel for the development of solid state modular power supplies for various applications. (author)

  18. Passive Resonant Bidirectional Converter with Galvanic Barrier

    Science.gov (United States)

    Rosenblad, Nathan S. (Inventor)

    2014-01-01

    A passive resonant bidirectional converter system that transports energy across a galvanic barrier includes a converter using at least first and second converter sections, each section including a pair of transfer terminals, a center tapped winding; a chopper circuit interconnected between the center tapped winding and one of the transfer terminals; an inductance feed winding interconnected between the other of the transfer terminals and the center tap and a resonant tank circuit including at least the inductance of the center tap winding and the parasitic capacitance of the chopper circuit for operating the converter section at resonance; the center tapped windings of the first and second converter sections being disposed on a first common winding core and the inductance feed windings of the first and second converter sections being disposed on a second common winding core for automatically synchronizing the resonant oscillation of the first and second converter sections and transferring energy between the converter sections until the voltage across the pairs of transfer terminals achieves the turns ratio of the center tapped windings.

  19. Modeling and Simulation of Matrix Converter

    DEFF Research Database (Denmark)

    Liu, Fu-rong; Klumpner, Christian; Blaabjerg, Frede

    2005-01-01

    This paper discusses the modeling and simulation of matrix converter. Two models of matrix converter are presented: one is based on indirect space vector modulation and the other is based on power balance equation. The basis of these two models is• given and the process on modeling is introduced...

  20. A novel power converter for photovoltaic applications

    Science.gov (United States)

    Yuvarajan, S.; Yu, Dachuan; Xu, Shanguang

    A simple and economical power conditioner to convert the power available from solar panels into 60 Hz ac voltage is described. The raw dc voltage from the solar panels is converted to a regulated dc voltage using a boost converter and a large capacitor and the dc output is then converted to 60 Hz ac using a bridge inverter. The ratio between the load current and the short-circuit current of a PV panel at maximum power point is nearly constant for different insolation (light) levels and this property is utilized in designing a simple maximum power point tracking (MPPT) controller. The controller includes a novel arrangement for sensing the short-circuit current without disturbing the operation of the PV panel and implementing MPPT. The switching losses in the inverter are reduced by using snubbers. The results obtained on an experimental converter are presented.

  1. Step-Up DC-DC converters

    DEFF Research Database (Denmark)

    Forouzesh, Mojtaba; Siwakoti, Yam P.; Gorji, Saman A.

    2017-01-01

    on the general law and framework of the development of next-generation step-up dc-dc converters, this paper aims to comprehensively review and classify various step-up dc-dc converters based on their characteristics and voltage-boosting techniques. In addition, the advantages and disadvantages of these voltage......DC-DC converters with voltage boost capability are widely used in a large number of power conversion applications, from fraction-of-volt to tens of thousands of volts at power levels from milliwatts to megawatts. The literature has reported on various voltage-boosting techniques, in which......-boosting techniques and associated converters are discussed in detail. Finally, broad applications of dc-dc converters are presented and summarized with comparative study of different voltage-boosting techniques....

  2. A review of Indirect Matrix Converter Topologies

    Directory of Open Access Journals (Sweden)

    Salem Rahmani

    2015-08-01

    Full Text Available Abstract—Matrix Converter (MC is a modern direct AC/AC electrical power converter without dc-link capacitor. MC is operated in four quadrant, assuring a control of the output voltage, amplitude and frequency. The matrix converter has recently attracted significant attention among researchers and it has become increasing attractive for applications of wind energy conversion, military power supplies, induction motor drives, etc. Recently, different MC topologies have been proposed and developed which have their own advantages and disadvantages. Matrix converter can be classified as direct and indirect structures. The direct one has been elaborated in previous work. In this paper the indirect MCs are reviewed. Different characteristics of the indirect MC topologies are mentioned to show the strengths and weaknesses of such converter topologies.

  3. Reaching a few picosecond timing precision with the 16-channel digitizer and timestamper SAMPIC ASIC

    Energy Technology Data Exchange (ETDEWEB)

    Delagnes, E., E-mail: eric.delagnes@cea.fr [CEA/IRFU/SEDI, Saclay (France); Breton, D. [Laboratoire de L’accélérateur Linéaire from CNRS/IN2P3, Centre scientifique d’Orsay, Bâtiment 200, 91898, Orsay, Cedex (France); Grabas, H. [CEA/IRFU/SEDI, Saclay (France); Maalmi, J.; Rusquart, P. [Laboratoire de L’accélérateur Linéaire from CNRS/IN2P3, Centre scientifique d’Orsay, Bâtiment 200, 91898, Orsay, Cedex (France)

    2015-07-01

    SAMPIC is a Time and Waveform to Digital Converter (TWDC) multichannel chip. It integrates 16 channels each including DLL-based TDC providing a raw time associated with an ultra-fast analog memory sampling the signal used for precise timing measurements as well as other parameters of the pulse. Every channel also integrates a discriminator that can trigger it independently or participate to a more complex trigger. After triggering, the analog samples are digitized by on-chip ADCs and are sent serially to the acquisition. The paper describes the architecture of SAMPIC and reports the main performance measured on the first prototype chip with a focus on timing resolution in the range of 15 ps RMS using raw data improved to less than 5 ps RMS after a simple calibration.

  4. A Spacecraft Housekeeping System-on-Chip in a Radiation Hardened Structured ASIC

    Science.gov (United States)

    Suarez, George; DuMonthier, Jeffrey J.; Sheikh, Salman S.; Powell, Wesley A.; King, Robyn L.

    2012-01-01

    Housekeeping systems are essential to health monitoring of spacecraft and instruments. Typically, sensors are distributed across various sub-systems and data is collected using components such as analog-to-digital converters, analog multiplexers and amplifiers. In most cases programmable devices are used to implement the data acquisition control and storage, and the interface to higher level systems. Such discrete implementations require additional size, weight, power and interconnect complexity versus an integrated circuit solution, as well as the qualification of multiple parts. Although commercial devices are readily available, they are not suitable for space applications due the radiation tolerance and qualification requirements. The Housekeeping System-o n-A-Chip (HKSOC) is a low power, radiation hardened integrated solution suitable for spacecraft and instrument control and data collection. A prototype has been designed and includes a wide variety of functions including a 16-channel analog front-end for driving and reading sensors, analog-to-digital and digital-to-analog converters, on-chip temperature sensor, power supply current sense circuits, general purpose comparators and amplifiers, a 32-bit processor, digital I/O, pulse-width modulation (PWM) generators, timers and I2C master and slave serial interfaces. In addition, the device can operate in a bypass mode where the processor is disabled and external logic is used to control the analog and mixed signal functions. The device is suitable for stand-alone or distributed systems where multiple chips can be deployed across different sub-systems as intelligent nodes with computing and processing capabilities.

  5. Development of Formulations for a-SiC and Manganese CMP and Post-CMP Cleaning of Cobalt

    Science.gov (United States)

    Lagudu, Uma Rames Krishna

    We have investigated the chemical mechanical polishing (CMP) of amorphous SiC (a-SiC) and Mn and Post CMP cleaning of cobalt for various device applications. During the manufacture of copper interconnects using the damascene process the polishing of copper is followed by the polishing of the barrier material (Co, Mn, Ru and their alloys) and its post CMP cleaning. This is followed by the a-SiC hard mask CMP. Silicon carbide thin films, though of widespread use in microelectronic engineering, are difficult to process by CMP because of their hardness and chemical inertness. The earlier part of the SiC work discusses the development of slurries based on silica abrasives that resulted in high a-SiC removal rates (RRs). The ionic strength of the silica dispersion was found to play a significant role in enhancing material removal rate, while also providing very good post-polish surface-smoothness. For example, the addition of 50 mM potassium nitrate to a pH 8 aqueous slurry consisting of 10 wt % of silica abrasives and 1.47 M hydrogen peroxide increased the RR from about 150 nm/h to about 2100 nm/h. The role of ionic strength in obtaining such high RRs was investigated using surface zeta-potentials measurements and X-ray photoelectron spectroscopy (XPS). Evidently, hydrogen peroxide promoted the oxidation of Si and C to form weakly adhered species that were subsequently removed by the abrasive action of the silica particles. The effect of potassium nitrate in increasing material removal is attributed to the reduction in the electrostatic repulsion between the abrasive particles and the SiC surface because of screening of surface charges by the added electrolyte. We also show that transition metal compounds when used as additives to silica dispersions enhance a-SiC removal rates (RRs). Silica slurries containing potassium permanganate gave RRs as high as 2000 nm/h at pH 4. Addition of copper sulfate to this slurry further enhanced the RRs to ˜3500 nm/h at pH 6

  6. NINO An ultra-fast and low-power front-end amplifier/discriminator ASIC designed for the multigap resistive plate chamber

    CERN Document Server

    Anghinolfi, F; Martemyanov, A N; Usenko, E; Wenninger, Horst; Williams, M C S; Zichichi, A

    2004-01-01

    For the full exploitation of the excellent timing properties of the Multigap Resistive Plate Chamber (MRPC), front-end electronics with special characteristics are needed. These are (a) differential input, to profit from the differential signal from the MRPC (b) a fast amplifier with less than 1 ns peaking time and (c) input charge measurement by Time-Over-Threshold for slewing correction. An 8- channel amplifier and discriminator chip has been developed to match these requirements. This is the NINO ASIC, fabricated with 0.25 omegam CMOS technology. The power requirement at 40mW/channel is low. Results on the performance of the MRPCs using the NINO ASIC are presented. Typical time resolution a of the MRPC system is in the 50 ps range, with an efficiency of 99.9%.

  7. Development of a low-noise, 4th-order readout ASIC for CdZnTe detectors in gamma spectrometer applications

    Energy Technology Data Exchange (ETDEWEB)

    Wang, Jia, E-mail: jwang@nwpu.edu.cn [School of Computer Science and Engineering, Northwestern Polytechnical University, 127 West Youyixi Road, 710072 Xi' an (China); Su, Lin; Wei, Xiaomin; Zheng, Ran [School of Computer Science and Engineering, Northwestern Polytechnical University, 127 West Youyixi Road, 710072 Xi' an (China); Hu, Yann [IPHC, University of Strasbourg, 23 rue du loess, 67037 Strasbourg Cedex 02 (France)

    2016-09-21

    This paper presents an ASIC readout circuit development, which aims to achieve low noise. In order to compensate the leakage current and improve gain, a dual-stage CSA has been utilized. A 4th-order high-linearity shaper is proposed to obtain a Semi-Gaussian wave and further decrease the noise induced by the leakage current. The ASIC has been designed and fabricated in a standard commercial 2P4M 0.35 μm CMOS process. Die area of one channel is about 1190 μm×147 μm. The input charge range is 1.8 fC. The peaking time can be adjusted from 1 μs to 3 μs. Measured ENC is about 55e{sup −} (rms) at input capacitor of 0 F. The gain is 271 mV/fC at the peaking time of 1 μs.

  8. Electromagnetic Compatibility of Matrix Converter System

    Directory of Open Access Journals (Sweden)

    S. Fligl

    2006-12-01

    Full Text Available The presented paper deals with matrix converters pulse width modulation strategies design with emphasis on the electromagnetic compatibility. Matrix converters provide an all-silicon solution to the problem of converting AC power from one frequency to another, offering almost all the features required of an ideal static frequency changer. They possess many advantages compared to the conventional voltage or current source inverters. A matrix converter does not require energy storage components as a bulky capacitor or an inductance in the DC-link, and enables the bi-directional power flow between the power supply and load. The most of the contemporary modulation strategies are able to provide practically sinusoidal waveforms of the input and output currents with negligible low order harmonics, and to control the input displacement factor. The perspective of matrix converters regarding EMC in comparison with other types of converters is brightly evident because it is no need to use any equipment for power factor correction and current and voltage harmonics reduction. Such converter with proper control is properly compatible both with the supply mains and with the supplied load. A special digital control system was developed for the realized experimental test bed which makes it possible to achieve greater throughput of the digital control system and its variability.

  9. Underwater noise from a wave energy converter

    DEFF Research Database (Denmark)

    Tougaard, Jakob

    A recent addition to the anthropogenic sources of underwater noise is offshore wave energy converters. Underwater noise was recorded from the Wavestar wave energy converter located at Hastholm, Denmark (57°7.73´N, 8°37.23´E). The Wavestar is a full-scale test and demonstration converter...... in full operation and start and stop of the converter. Median broad band (10 Hz – 20 kHz) sound pressure level (Leq) was 123 dB re. 1 Pa, irrespective of status of the wave energy converter (stopped, running or starting/stopping). The most pronounced peak in the third-octave spectrum was in the 160 Hz...... significant noise above ambient could be detected above the 250 Hz band. The absolute increase in noise above ambient was very small. L50 third-octave levels in the four bands with the converter running were thus only 1-2 dB above ambient L50 levels. The noise recorded 25 m from the wave energy converter...

  10. Linearity enhancement design of a 16-channel low-noise front-end readout ASIC for CdZnTe detectors

    International Nuclear Information System (INIS)

    Zeng, Huiming; Wei, Tingcun; Wang, Jia

    2017-01-01

    A 16-channel front-end readout application-specific integrated circuit (ASIC) with linearity enhancement design for cadmium zinc telluride (CdZnTe) detectors is presented in this paper. The resistors in the slow shaper are realized using a high-Z circuit to obtain constant resistance value instead of using only a metal–oxide–semiconductor (MOS) transistor, thus the shaping time of the slow shaper can be kept constant for different amounts of input energies. As a result, the linearity of conversion gain is improved significantly. The ASIC was designed and fabricated in a 0.35 µm CMOS process with a die size of 2.60 mm×3.53 mm. The tested results show that a typical channel provides an equivalent noise charge (ENC) of 109.7e − +16.3e − /pF with a power consumption of 4 mW and achieves a conversion gain of 87 mV/fC with a nonlinearity of <0.4%. The linearity of conversion gain is improved by at least 86.6% as compared with the traditional approaches using the same front-end readout architecture and manufacture process. Moreover, the inconsistency among channels is <0.3%. An energy resolution of 2.975 keV (FWHM) for gamma rays of 59.5 keV was measured by connecting the ASIC to a 5 mm×5 mm ×2 mm CdZnTe detector at room temperature. The front-end readout ASIC presented in this paper achieves an outstanding linearity performance without compromising the noise, power consumption, and chip size performances.

  11. VEGA: A low-power front-end ASIC for large area multi-linear X-ray silicon drift detectors: Design and experimental characterization

    Energy Technology Data Exchange (ETDEWEB)

    Ahangarianabhari, Mahdi; Macera, Daniele [Politecnico di Milano, Department of Electronics Engineering, Information Science and Bioengineering, P.za L. da Vinci 32, 20133 Milano (Italy); National Institute of Nuclear Physics, INFN sez. Milano (Italy); Bertuccio, Giuseppe, E-mail: Giuseppe.Bertuccio@polimi.it [Politecnico di Milano, Department of Electronics Engineering, Information Science and Bioengineering, P.za L. da Vinci 32, 20133 Milano (Italy); National Institute of Nuclear Physics, INFN sez. Milano (Italy); Malcovati, Piero; Grassi, Marco [University of Pavia, Department of Electrical Engineering, and National Institute of Nuclear Physics, INFN sez. Pavia, Pavia (Italy)

    2015-01-11

    We present the design and the first experimental characterization of VEGA, an Application Specific Integrated Circuit (ASIC) designed to read out large area monolithic linear Silicon Drift Detectors (SDD’s). VEGA consists of an analog and a digital/mixed-signal section to accomplish all the functionalities and specifications required for high resolution X-ray spectroscopy in the energy range between 500 eV and 50 keV. The analog section includes a charge sensitive preamplifier, a shaper with 3-bit digitally selectable shaping times from 1.6 µs to 6.6 µs and a peak stretcher/sample-and-hold stage. The digital/mixed-signal section includes an amplitude discriminator with coarse and fine threshold level setting, a peak discriminator and a logic circuit to fulfill pile-up rejection, signal sampling, trigger generation, channel reset and the preamplifier and discriminators disabling functionalities. A Serial Peripherical Interface (SPI) is integrated in VEGA for loading and storing all configuration parameters in an internal register within few microseconds. The VEGA ASIC has been designed and manufactured in 0.35 µm CMOS mixed-signal technology in single and 32 channel versions with dimensions of 200 µm×500 µm per channel. A minimum intrinsic Equivalent Noise Charge (ENC) of 12 electrons r.m.s. at 3.6 µs peaking time and room temperature is measured and the linearity error is between −0.9% and +0.6% in the whole input energy range. The total power consumption is 481 µW and 420 µW per channel for the single and 32 channels version, respectively. A comparison with other ASICs for X-ray SDD’s shows that VEGA has a suitable low noise and offers high functionality as ADC-ready signal processing but at a power consumption that is a factor of four lower than other similar existing ASICs.

  12. Sour ageusia in two individuals implicates ion channels of the ASIC and PKD families in human sour taste perception at the anterior tongue.

    Directory of Open Access Journals (Sweden)

    Taufiqul Huque

    2009-10-01

    Full Text Available The perception of sour taste in humans is incompletely understood at the receptor cell level. We report here on two patients with an acquired sour ageusia. Each patient was unresponsive to sour stimuli, but both showed normal responses to bitter, sweet, and salty stimuli.Lingual fungiform papillae, containing taste cells, were obtained by biopsy from the two patients, and from three sour-normal individuals, and analyzed by RT-PCR. The following transcripts were undetectable in the patients, even after 50 cycles of amplification, but readily detectable in the sour-normal subjects: acid sensing ion channels (ASICs 1a, 1beta, 2a, 2b, and 3; and polycystic kidney disease (PKD channels PKD1L3 and PKD2L1. Patients and sour-normals expressed the taste-related phospholipase C-beta2, the delta-subunit of epithelial sodium channel (ENaC and the bitter receptor T2R14, as well as beta-actin. Genomic analysis of one patient, using buccal tissue, did not show absence of the genes for ASIC1a and PKD2L1. Immunohistochemistry of fungiform papillae from sour-normal subjects revealed labeling of taste bud cells by antibodies to ASICs 1a and 1beta, PKD2L1, phospholipase C-beta2, and delta-ENaC. An antibody to PKD1L3 labeled tissue outside taste bud cells.These data suggest a role for ASICs and PKDs in human sour perception. This is the first report of sour ageusia in humans, and the very existence of such individuals ("natural knockouts" suggests a cell lineage for sour that is independent of the other taste modalities.

  13. Linearity enhancement design of a 16-channel low-noise front-end readout ASIC for CdZnTe detectors

    Energy Technology Data Exchange (ETDEWEB)

    Zeng, Huiming; Wei, Tingcun, E-mail: weitc@nwpu.edu.cn; Wang, Jia

    2017-03-01

    A 16-channel front-end readout application-specific integrated circuit (ASIC) with linearity enhancement design for cadmium zinc telluride (CdZnTe) detectors is presented in this paper. The resistors in the slow shaper are realized using a high-Z circuit to obtain constant resistance value instead of using only a metal–oxide–semiconductor (MOS) transistor, thus the shaping time of the slow shaper can be kept constant for different amounts of input energies. As a result, the linearity of conversion gain is improved significantly. The ASIC was designed and fabricated in a 0.35 µm CMOS process with a die size of 2.60 mm×3.53 mm. The tested results show that a typical channel provides an equivalent noise charge (ENC) of 109.7e{sup −}+16.3e{sup −}/pF with a power consumption of 4 mW and achieves a conversion gain of 87 mV/fC with a nonlinearity of <0.4%. The linearity of conversion gain is improved by at least 86.6% as compared with the traditional approaches using the same front-end readout architecture and manufacture process. Moreover, the inconsistency among channels is <0.3%. An energy resolution of 2.975 keV (FWHM) for gamma rays of 59.5 keV was measured by connecting the ASIC to a 5 mm×5 mm ×2 mm CdZnTe detector at room temperature. The front-end readout ASIC presented in this paper achieves an outstanding linearity performance without compromising the noise, power consumption, and chip size performances.

  14. CAS - CERN Accelerator School: Power Converters

    CERN Document Server

    2015-01-01

    These proceedings collate lectures given at the twenty-eighth specialized course organised by the CERN Accelerator School (CAS). The course was held at the Hotel du Parc, Baden, Switzerland from 7 - 14 May 2014, in collaboration with the Paul Scherrer Institute. Following introductory lectures on accelerators and the requirements on power converters, the course covered components and topologies of the different types of power converters needed for particle accelerators. Issues of design, control and exploitation in a sometimes-hostile environment were addressed. Site visits to ABB and PSI provided an insight into state-of-the-art power converter production and operation, while topical seminars completed the programme.

  15. High-power converters and AC drives

    CERN Document Server

    Wu, Bin

    2017-01-01

    This new edition reflects the recent technological advancements in the MV drive industry, such as advanced multilevel converters and drive configurations. It includes three new chapters, Control of Synchronous Motor Drives, Transformerless MV Drives, and Matrix Converter Fed Drives. In addition, there are extensively revised chapters on Multilevel Voltage Source Inverters and Voltage Source Inverter-Fed Drives. This book includes a systematic analysis on a variety of high-power multilevel converters, illustrates important concepts with simulations and experiments, introduces various megawatt drives produced by world leading drive manufacturers, and addresses practical problems and their mitigations methods.

  16. Field Data Logger Prototype for Power Converters

    DEFF Research Database (Denmark)

    Chaudhary, Sanjay; Ghimire, Pramod; Thøgersen, Paul Bach

    2014-01-01

    and subsequent analysis of the data. This paper presents the development of a low cost prototype field data logger prototype using Raspberry PI and industrial sensors. The functionalities of the data logger prototype are described. An online rainflow count algorithm has been implemented as well.......Mission profile data is very important for the cost effective and reliable design of power converters. The converter design can be improved on the basis of actual field data. Actual mission profile data can be collected for the power converters using field data loggers over a long period of time...

  17. Synchronous Control of Modular Multilevel Converters

    DEFF Research Database (Denmark)

    Oleschuk, Valentin; Blaabjerg, Frede; Bose, Bimal K.

    2002-01-01

    A novel method of direct synchronous pulsewidth modulation (PWM) is applied for control of modular multilevel converters consisting from three standard triphase inverter modules along with an 0.33 p.u. output transformer. The proposed method provides synchronisation of the voltage waveforms...... for each module and the composed voltage at the output of the converter. Multilevel output voltage of the converter has quarter-wave symmetry during the whole range including the zone of overmodulation. Both continuous and discontinuous versions of synchronous PWM, based on vector approach...

  18. A 4×8-Gbps VCSEL array driver ASIC and integration with a custom array transmitter module for the LHC front-end transmission

    International Nuclear Information System (INIS)

    Guo, Di; Liu, Chonghan; Chen, Jinghong; Chramowicz, John; Gong, Datao; He, Huiqin; Hou, Suen; Liu, Tiankuan; Prosser, Alan; Teng, Ping-Kun; Xiang, Annie C.; Xiao, Le; Ye, Jingbo

    2016-01-01

    This paper describes the design, fabrication and experiment results of a 4×8-Gbps Vertical-Cavity Surface-Emitting Laser (VCSEL) array driver ASIC with the adjustable active-shunt peaking technique and the novel balanced output structure under the Silicon-on-Sapphire (SOS) process, and a custom array optical transmitter module, featuring a compact size of 10 mm×15 mm×5.3 mm. Both the array driver ASIC and the module have been fully tested after integration as a complete parallel transmitter. Optical eye diagram of each channel passes the eye mask at 8 Gbps/ch with adjacent channel working simultaneously with a power consumption of 150 mW/ch. The optical transmission of Bit-Error Rate (BER) less than 10E-12 is achieved at an aggregated data rate of 4×8-Gbps. - Highlights: • An anode-driven VCSEL Array driver ASIC with the configurable active-shunt peaking technique in pre-driving stages. • A novel full-differential balanced output structure is used to minimize the noise and crosstalk from the power. • A custom array optical transmitter module with custom low-cost reliable alignment method.

  19. A 4×8-Gbps VCSEL array driver ASIC and integration with a custom array transmitter module for the LHC front-end transmission

    Energy Technology Data Exchange (ETDEWEB)

    Guo, Di [Department of Physics, Southern Methodist University, Dallas, TX 75275 (United States); State Key Laboratory of Particle Detection and Electronics, University of Science and Technology of China, Hefei Anhui 230026 (China); Liu, Chonghan [Department of Physics, Southern Methodist University, Dallas, TX 75275 (United States); Chen, Jinghong [Department of Electrical and Computer Engineering, University of Houston, Houston, TX 77004 (United States); Chramowicz, John [Real-Time Systems Engineering Department, Fermi National Laboratory, Batavia, IL 60510 (United States); Gong, Datao [Department of Physics, Southern Methodist University, Dallas, TX 75275 (United States); He, Huiqin [Department of Physics, Southern Methodist University, Dallas, TX 75275 (United States); Shenzhen Polytechnic, Shenzhen 518055 (China); Hou, Suen [Institute of Physics, Academia Sinica, Nangang 11529, Taipei, Taiwan (China); Liu, Tiankuan [Department of Physics, Southern Methodist University, Dallas, TX 75275 (United States); Prosser, Alan [Real-Time Systems Engineering Department, Fermi National Laboratory, Batavia, IL 60510 (United States); Teng, Ping-Kun [Institute of Physics, Academia Sinica, Nangang 11529, Taipei, Taiwan (China); Xiang, Annie C. [Department of Physics, Southern Methodist University, Dallas, TX 75275 (United States); Xiao, Le [Department of Physics, Southern Methodist University, Dallas, TX 75275 (United States); Department of Physics, Central China Normal University, Wuhan, Hubei 430079 (China); Ye, Jingbo [Department of Physics, Southern Methodist University, Dallas, TX 75275 (United States)

    2016-09-21

    This paper describes the design, fabrication and experiment results of a 4×8-Gbps Vertical-Cavity Surface-Emitting Laser (VCSEL) array driver ASIC with the adjustable active-shunt peaking technique and the novel balanced output structure under the Silicon-on-Sapphire (SOS) process, and a custom array optical transmitter module, featuring a compact size of 10 mm×15 mm×5.3 mm. Both the array driver ASIC and the module have been fully tested after integration as a complete parallel transmitter. Optical eye diagram of each channel passes the eye mask at 8 Gbps/ch with adjacent channel working simultaneously with a power consumption of 150 mW/ch. The optical transmission of Bit-Error Rate (BER) less than 10E-12 is achieved at an aggregated data rate of 4×8-Gbps. - Highlights: • An anode-driven VCSEL Array driver ASIC with the configurable active-shunt peaking technique in pre-driving stages. • A novel full-differential balanced output structure is used to minimize the noise and crosstalk from the power. • A custom array optical transmitter module with custom low-cost reliable alignment method.

  20. Development of slew-rate-limited time-over-threshold (ToT) ASIC for a multi-channel silicon-based ion detector

    Science.gov (United States)

    Uenomachi, M.; Orita, T.; Shimazoe, K.; Takahashi, H.; Ikeda, H.; Tsujita, K.; Sekiba, D.

    2018-01-01

    High-resolution Elastic Recoil Detection Analysis (HERDA), which consists of a 90o sector magnetic spectrometer and a position-sensitive detector (PSD), is a method of quantitative hydrogen analysis. In order to increase sensitivity, a HERDA system using a multi-channel silicon-based ion detector has been developed. Here, as a parallel and fast readout circuit from a multi-channel silicon-based ion detector, a slew-rate-limited time-over-threshold (ToT) application-specific integrated circuit (ASIC) was designed, and a new slew-rate-limited ToT method is proposed. The designed ASIC has 48 channels and each channel consists of a preamplifier, a slew-rate-limited shaping amplifier, which makes ToT response linear, and a comparator. The measured equivalent noise charges (ENCs) of the preamplifier, the shaper, and the ToT on no detector capacitance were 253±21, 343±46, and 560±56 electrons RMS, respectively. The spectra from a 241Am source measured using a slew-rate-limited ToT ASIC are also reported.