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Sample records for charge-to-time converter asic

  1. A four channel time-to-digital converter ASIC with in-built calibration and SPI interface

    Energy Technology Data Exchange (ETDEWEB)

    Hari Prasad, K.; Sukhwani, Menka [Electronics Division, Bhabha Atomic Research Center, Mumbai 400085 (India); Saxena, Pooja [Homi Bhabha National Institute, Mumbai 400094 (India); Chandratre, V.B., E-mail: vbc@barc.gov.in [Electronics Division, Bhabha Atomic Research Center, Mumbai 400085 (India); Pithawa, C.K. [Electronics Division, Bhabha Atomic Research Center, Mumbai 400085 (India)

    2014-02-11

    A design of high resolution, wide dynamic range Time-to-Digital Converter (TDC) ASIC, implemented in 0.35 µm commercial CMOS technology is presented. The ASIC features four channel TDC with an in-built calibration and Serial Peripheral Interconnect (SPI) slave interface. The TDC is based on the vernier ring oscillator method in order to achieve both high resolution and wide dynamic range. This TDC ASIC is tested and found to have resolution of 127 ps (LSB), dynamic range of 1.8 µs and precision (σ) of 74 ps. The measured values of differential non-linearity (DNL) and integral non-linearity (INL) are 350 ps and 300 ps respectively.

  2. ASIC and FPGA based DPWM architectures for single-phase and single-output DC-DC converter: a review

    Science.gov (United States)

    Chander, Subhash; Agarwal, Pramod; Gupta, Indra

    2013-12-01

    Pulse width modulation (PWM) has been widely used in power converter control. This paper presents a review of architectures of the Digital Pulse Width Modulators (DPWM) targeting digital control of switching DC-DC converters. An attempt is made to review the reported architectures with emphasis on the ASIC and FPGA implementations in single phase and single-output DC-DC converters. Recent architectures using FPGA's advanced resources for achieving the resolution higher than classical methods have also been discussed. The merits and demerits of different architectures, and their relative comparative performance, are also presented. The Authors intention is to uncover the groundwork and the related references through this review for the benefit of readers and researchers targeting different DPWM architectures for the DC-DC converters.

  3. Switched capacitor DC-DC converter ASICs for the upgraded LHC trackers

    Energy Technology Data Exchange (ETDEWEB)

    Bochenek, M; Faccio, F; Michelis, S [CERN, CH-1211 Geneve 23 (Switzerland); Dabrowski, W, E-mail: Michal.Bochenek@cern.ch [AGH University of Science and Technology, Faculty of Physics and Applied Computer Science, Al. Mickiewicza 30 30-059 Krakow (Poland)

    2010-12-15

    The High Luminosity Upgrade of the ATLAS Inner Tracker puts demanding requirements on the powering system of the silicon strip detector modules due to 10-fold increase of the channel count compared to the existing SemiConductor Tracker. Therefore, new solutions for the powering scheme must be elaborated. Currently two possible approaches, the serial powering and the parallel powering scheme using the DC-DC conversion technique, are under development. This paper describes two switched capacitor DC-DC converters designed in a 130 nm technology. For the optimized step-down converter, foreseen for the parallel powering scheme, power efficiency of 97% has been achieved, while for the charge pump, designed for the serial powering scheme, power efficiency of 85% has been achieved.

  4. Switched capacitor DC-DC converter ASICs for the upgraded LHC trackers

    CERN Document Server

    Bochenek, M; Faccio, F; Michelis, S

    2010-01-01

    The High Luminosity Upgrade of the ATLAS Inner Tracker puts demanding requirements on the powering system of the silicon strip detector modules due to 10-fold increase of the channel count compared to the existing SemiConductor Tracker. Therefore, new solutions for the powering scheme must be elaborated. Currently two possible approaches, the serial powering and the parallel powering scheme using the DC-DC conversion technique, are under development. This paper describes two switched capacitor DC-DC converters designed in a 130 nm technology. For the optimized step-down converter, foreseen for the parallel powering scheme, power efficiency of 97% has been achieved, while for the charge pump, designed for the serial powering scheme, power efficiency of 85% has been achieved

  5. A flexible multi-channel high-resolution time-to-digital converter ASIC

    CERN Document Server

    Mota, M; Debieux, S; Ryzhov, V; Moreira, P; Marchioro, A

    2000-01-01

    A data driven multi-channel Time-to-Digital Converter (TDC) circuit with programmable resolution ( similar to 25ps - 8OOps binning) and a dynamic range of 102.4mus has been implemented in a 0.25mum CMOS technology. An on-chip PLL is used for clock multiplication up to 320MHz from an external 40MHz reference. A 32 element Delay Locked Loop (DLL) performs time interpolation down to 97.5ps. Finally, finer time interpolation is obtained using four samples of the DLL separated by 24.5ps generated by an adjustable on-chip RC delay line. In the lower resolution modes of operation, 32 TDC channels are available. In the highest resolution mode eight channels are available, since four low-resolution channels are used to perform a single fine time interpolation. The TDC is capable of measuring both leading and trailing edges of the input signal. Measurements are initially stored as time stamps in individual four-location deep asynchronous channel buffers. After proper encoding, measurements are written into four 256-dee...

  6. Memory, microprocessor, and ASIC

    CERN Document Server

    Chen, Wai-Kai

    2003-01-01

    System Timing. ROM/PROM/EPROM. SRAM. Embedded Memory. Flash Memories. Dynamic Random Access Memory. Low-Power Memory Circuits. Timing and Signal Integrity Analysis. Microprocessor Design Verification. Microprocessor Layout Method. Architecture. ASIC Design. Logic Synthesis for Field Programmable Gate Array (EPGA) Technology. Testability Concepts and DFT. ATPG and BIST. CAD Tools for BIST/DFT and Delay Faults.

  7. A Readout ASIC for CZT Detectors

    CERN Document Server

    Jones, L

    2008-01-01

    Spectrometers that can identify the energy of gamma radiation and determine the source isotope have until recently used low temperature semiconductors. These require cooling which makes their portability difficult. The material Cadmium Zinc Telluride (CZT) is now available which operates at room temperature and can be used to measure the energy of gamma radiation. In a compton camera configuration the direction of the radiation can also be determined. A read-out ASIC has been developed for such a system and features 100 channels of electronics, each with a charge amplifier, CR-RC shaper, and peak-hold. A 12 bit ADC converts the data which is sparsified before being read out. The energy, signal rise time, and timestamp of any hit channel is read out together with the data from all of its neighbours. The ASIC has a selectable lower dynamic range which could be used for lower energy interactions.

  8. Simultaneous disruption of mouse ASIC1a, ASIC2 and ASIC3 genes enhances cutaneous mechanosensitivity.

    Directory of Open Access Journals (Sweden)

    Sinyoung Kang

    Full Text Available Three observations have suggested that acid-sensing ion channels (ASICs might be mammalian cutaneous mechanoreceptors; they are structurally related to Caenorhabditis elegans mechanoreceptors, they are localized in specialized cutaneous mechanosensory structures, and mechanical displacement generates an ASIC-dependent depolarization in some neurons. However, previous studies of mice bearing a single disrupted ASIC gene showed only subtle or no alterations in cutaneous mechanosensitivity. Because functional redundancy of ASIC subunits might explain limited phenotypic alterations, we hypothesized that disrupting multiple ASIC genes would markedly impair cutaneous mechanosensation. We found the opposite. In behavioral studies, mice with simultaneous disruptions of ASIC1a, -2 and -3 genes (triple-knockouts, TKOs showed increased paw withdrawal frequencies when mechanically stimulated with von Frey filaments. Moreover, in single-fiber nerve recordings of cutaneous afferents, mechanical stimulation generated enhanced activity in A-mechanonociceptors of ASIC TKOs compared to wild-type mice. Responses of all other fiber types did not differ between the two genotypes. These data indicate that ASIC subunits influence cutaneous mechanosensitivity. However, it is unlikely that ASICs directly transduce mechanical stimuli. We speculate that physical and/or functional association of ASICs with other components of the mechanosensory transduction apparatus contributes to normal cutaneous mechanosensation.

  9. Evaluation of a front-end ASIC for the readout of PMTs in large dynamic range

    CERN Document Server

    Wu, Weihao; Liang, Yu; Yu, Li; Liu, Jianfeng; Liu, Shubin; An, Qi

    2015-01-01

    The Large High Altitude Air Shower Observatory (LHAASO) project has been proposed for the survey and study of cosmic rays. In the LHAASO project, the Water Cherenkov Detector Array (WCDA) is one of major detectors for searching gamma ray sources. A Charge-to-Time Convertor (QTC) ASIC (Application Specification Integrated Circuit) fabricated in Global Foundry 0.35 {\\mu}m CMOS technology, has been developed for readout of Photomultiplier Tubes (PMTs) in the WCDA. This paper focuses on the evaluation of this front-end readout ASIC performance. Test results indicate that the time resolution is better than 400 ps and the charge resolution is better than 1% with large input signals and remains better than 15% @ 1 Photo Electron (P.E.), both beyond the application requirement. Moreover, this ASIC has a weak ambient temperature dependence, low input rate dependence and high channel-to-channel isolation.

  10. A Radiation Hardened by Design CMOS ASIC for Thermopile Readouts

    Science.gov (United States)

    Quilligan, G.; Aslam, S.; DuMonthier, J.

    2012-01-01

    A radiation hardened by design (RHBD) mixed-signal application specific integrated circuit (ASIC) has been designed for a thermopile readout for operation in the harsh Jovian orbital environment. The multi-channel digitizer (MCD) ASIC includes 18 low noise amplifier channels which have tunable gain/filtering coefficients, a 16-bit sigma-delta analog-digital converter (SDADC) and an on-chip controller. The 18 channels, SDADC and controller were designed to operate with immunity to single event latchup (SEL) and to at least 10 Mrad total ionizing dose (TID). The ASIC also contains a radiation tolerant 16-bit 20 MHz Nyquist ADC for general purpose instrumentation digitizer needs. The ASIC is currently undergoing fabrication in a commercial 180 nm CMOS process. Although this ASIC was designed specifically for the harsh radiation environment of the NASA led JEO mission it is suitable for integration into instrumentation payloads 011 the ESA JUICE mission where the radiation hardness requirements are slightly less stringent.

  11. Mongoose ASIC microcontroller programming guide

    Science.gov (United States)

    Smith, Brian S.

    1993-01-01

    The 'Mongoose' ASIC microcontroller is a radiation-hard implementation of the R3000 microprocessor. This document describes the internals of the microcontroller in a level of detail necessary for someone implementing a software design.

  12. ASIC-enabled High Resolution Optical Time Domain Reflectometer

    Science.gov (United States)

    Skendzic, Sandra

    Fiber optics has become the preferred technology in communication systems because of what it has to offer: high data transmission rates, immunity to electromagnetic interference, and lightweight, flexible cables. An optical time domain reflectometer (OTDR) provides a convenient method of locating and diagnosing faults (e.g. break in a fiber) along a fiber that can obstruct crucial optical pathways. Both the ability to resolve the precise location of the fault and distinguish between two discrete, closely spaced faults are figures of merit. This thesis presents an implementation of a high resolution OTDR through the use of a compact and programmable ASIC (application specific integrated circuit). The integration of many essential OTDR functions on a single chip is advantageous over existing commercial instruments because it enables small, lightweight packaging, and offers low power and cost efficiency. Furthermore, its compactness presents the option of placing multiple ASICs in parallel, which can conceivably ease the characterization of densely populated fiber optic networks. The OTDR ASIC consists of a tunable clock, pattern generator, precise timer, electrical receiver, and signal sampling circuit. During OTDR operation, the chip generates narrow electrical pulse, which can then be converted to optical format when coupled with an external laser diode driver. The ASIC also works with an external photodetector to measure the timing and amplitude of optical reflections in a fiber. It has a 1 cm sampling resolution, which allows for a 2 cm spatial resolution. While this OTDR ASIC has been previously demonstrated for multimode fiber fault diagnostics, this thesis focuses on extending its functionality to single mode fiber. To validate this novel approach to OTDR, this thesis is divided into five chapters: (1) introduction, (2) implementation, (3), performance of ASIC-based OTDR, (4) exploration in optical pre-amplification with a semiconductor optical amplifier, and

  13. Characterisation of the NA62 GigaTracker end of column readout ASIC

    CERN Document Server

    Noy, M; Perktold, L; Rinella, G A; Riedler, P; Morel, M; Kluge, A; Kaplon, J; Martin, E; Jarron, P

    2011-01-01

    The architecture and characterisation of the End Of Column demonstrator readout ASIC for the NA62 GigaTracker hybrid pixel detector is presented. This ASIC serves as a proof of principle for a pixel chip with 1800 pixels which must perform time stamping to better than 200 ps (RMS), provide 300 mu m pitch position information and operate with a dead-time of 1\\% or less for 800 MHz-1 GHz beam rate. The demonstrator ASIC comprises a full test column with 45 pixels alongside other test structures. The timewalk correction mechanism employed is measurement of the time-over-threshold, coupled with an off-detector look-up table. The time to digital converter is a delay locked loop with 32 contributing delay cells fed with a 320 MHz to yield a nominal bin size of 97 ps. Recently, P-in-N sensors have been bump-bonded to the ASIC and characterisation of these assemblies has begun.

  14. SPIDR, a general-purpose readout system for pixel ASICs

    Science.gov (United States)

    van der Heijden, B.; Visser, J.; van Beuzekom, M.; Boterenbrood, H.; Kulis, S.; Munneke, B.; Schreuder, F.

    2017-02-01

    The SPIDR (Speedy PIxel Detector Readout) system is a flexible general-purpose readout platform that can be easily adapted to test and characterize new and existing detector readout ASICs. It is originally designed for the readout of pixel ASICs from the Medipix/Timepix family, but other types of ASICs or front-end circuits can be read out as well. The SPIDR system consists of an FPGA board with memory and various communication interfaces, FPGA firmware, CPU subsystem and an API library on the PC . The FPGA firmware can be adapted to read out other ASICs by re-using IP blocks. The available IP blocks include a UDP packet builder, 1 and 10 Gigabit Ethernet MAC's and a "soft core" CPU . Currently the firmware is targeted at the Xilinx VC707 development board and at a custom board called Compact-SPIDR . The firmware can easily be ported to other Xilinx 7 series and ultra scale FPGAs. The gap between an ASIC and the data acquisition back-end is bridged by the SPIDR system. Using the high pin count VITA 57 FPGA Mezzanine Card (FMC) connector only a simple chip carrier PCB is required. A 1 and a 10 Gigabit Ethernet interface handle the connection to the back-end. These can be used simultaneously for high-speed data and configuration over separate channels. In addition to the FMC connector, configurable inputs and outputs are available for synchronization with other detectors. A high resolution (≈ 27 ps bin size) Time to Digital converter is provided for time stamping events in the detector. The SPIDR system is frequently used as readout for the Medipix3 and Timepix3 ASICs. Using the 10 Gigabit Ethernet interface it is possible to read out a single chip at full bandwidth or up to 12 chips at a reduced rate. Another recent application is the test-bed for the VeloPix ASIC, which is developed for the Vertex Detector of the LHCb experiment. In this case the SPIDR system processes the 20 Gbps scrambled data stream from the VeloPix and distributes it over four 10 Gigabit

  15. Rad-Hard Structured ASIC Body of Knowledge

    Science.gov (United States)

    Heidecker, Jason

    2013-01-01

    Structured Application-Specific Integrated Circuit (ASIC) technology is a platform between traditional ASICs and Field-Programmable Gate Arrays (FPGA). The motivation behind structured ASICs is to combine the low nonrecurring engineering costs (NRE) costs of FPGAs with the high performance of ASICs. This report provides an overview of the structured ASIC platforms that are radiation-hardened and intended for space application

  16. A silicon pixel readout ASIC with 100 ps time resolution for the NA62 experiment

    Energy Technology Data Exchange (ETDEWEB)

    Dellacasa, G; Garbolino, S; Marchetto, F; Martoiu, S; Mazza, G; Rivetti, A; Wheadon, R, E-mail: mazza@to.infn.it [INFN sez. di Torino, Via P. Giuria 1, 10125 Torino (Italy)

    2011-01-15

    The silicon tracker of the NA62 experiment requires the measurement of the particles arrival time with a resolution better than 200 ps rms and a spatial resolution of 300 {mu}m. A time measurement technique based on a Time to Amplitude Converter has been implemented in an ASIC in order to prove the possibility to integrate a TDC with resolution better than 200 ps in a pixel cell. Time-walk problem has been addressed with the use of the Constant Fraction Discriminator technique. The ASIC has been designed in a CMOS 0.13 {mu}m technology with single event upset protection of the digital logic.

  17. Front-end ASICs for high-energy astrophysics in space

    Science.gov (United States)

    Gevin, O.; Limousin, O.; Meuris, A.

    2016-07-01

    In most of embedded imaging systems for space applications, high granularity and increasing size of focal planes justify an almost systematic use of integrated circuits. . To fulfill challenging requirements for excellent spatial and energy resolution, integrated circuits must fit the sensors perfectly and interface the system such a way to optimize simultaneously noise, geometry and architecture. Moreover, very low power consumption and radiation tolerance are mandatory to envision a use onboard a payload in space. Consequently, being part of an optimized detection system for space, the integrated circuit is specifically designed for each application and becomes an Application Specific Integrated Circuits (ASIC). The paper focuses on mixed analog and digital signal ASICs for spectro-imaging systems in the keVMeV energy band. The first part of the paper summarizes the main advantages conferred by the use of front-end ASICs for highenergy astrophysics instruments in space mission. Space qualification of ASICs requires the chip to be radiation hard. The paper will shortly describe some of the typical hardening techniques and give some guidelines that an ASIC designer should follow to choose the most efficient technology for his project. The first task of the front-end electronics is to convert the charge coming from the detector into a voltage. For most of the Silicon detectors (CCD, DEPFET, SDD) this is conversion happens in the detector itself. For other sensor materials, charge preamplifiers operate the conversion. The paper shortly describes the different key parameters of charge preamplifiers and the binding parameters for the design. Filtering is generally mandatory in order to increase the signal to noise ratio or to reduce the duration of the signal. After a brief review on the main noise sources, the paper reviews noise-filtering techniques that are commonly used in Integrated circuits designs. The way sensors and ASICs are interconnected together plays a

  18. Front End Spectroscopy ASIC for Germanium Detectors

    Science.gov (United States)

    Wulf, Eric

    Large-area, tracking, semiconductor detectors with excellent spatial and spectral resolution enable exciting new access to soft (0.2-5 MeV) gamma-ray astrophysics. The improvements from semiconductor tracking detectors come with the burden of high density of strips and/or pixels that require high-density, low-power, spectroscopy quality readout electronics. CMOS ASIC technologies are a natural fit to this requirement and have led to high-quality readout systems for all current semiconducting tracking detectors except for germanium detectors. The Compton Spectrometer and Imager (COSI), formerly NCT, at University of California Berkeley and the Gamma-Ray Imager/Polarimeter for Solar flares (GRIPS) at Goddard Space Flight Center utilize germanium cross-strip detectors and are on the forefront of NASA's Compton telescope research with funded missions of long duration balloon flights. The development of a readout ASIC for germanium detectors would allow COSI to replace their discrete electronics readout and would enable the proposed Gamma-Ray Explorer (GRX) mission utilizing germanium strip-detectors. We propose a 3-year program to develop and test a germanium readout ASIC to TRL 5 and to integrate the ASIC readout onto a COSI detector allowing a TRL 6 demonstration for the following COSI balloon flight. Our group at NRL led a program, sponsored by another government agency, to produce and integrate a cross-strip silicon detector ASIC, designed and fabricated by Dr. De Geronimo at Brookhaven National Laboratory. The ASIC was designed to handle the large (>30 pF) capacitance of three 10 cm^2 detectors daisy-chained together. The front-end preamplifier, selectable inverter, shaping times, and gains make this ASIC compatible with a germanium cross-strip detector as well. We therefore have the opportunity and expertise to leverage the previous investment in the silicon ASIC for a new mission. A germanium strip detector ASIC will also require precise timing of the signals at

  19. Driver ASICs for Advanced Deformable Mirrors Project

    Data.gov (United States)

    National Aeronautics and Space Administration — The program leverages on our extensive expertise in developing high-performance driver ASICs for deformable mirror systems and seeks to expand the capacities of the...

  20. Driver ASICs for Advanced Deformable Mirrors Project

    Data.gov (United States)

    National Aeronautics and Space Administration — The overall goal of the SBIR program is to develop a new Application Specified Integrated Circuit (ASIC) driver to be used in driver electronics of a deformable...

  1. VMM - An ASIC for Micropattern Detectors

    CERN Document Server

    Iakovidis, Georgios; The ATLAS collaboration; De Geronimo, Gianluigi

    2015-01-01

    The VMM is an ASIC that can be used in a variety of tracking detectors. It is designed to be used with resistive Micromegas and sTGC detectors in the New Small Wheel upgrade of the ATLAS Muon spectrometer. The ASIC is fabricated in the 130nm 1.2V 8‐metal CMOS technology from IBM. The ASIC integrates 64 channels, each providing charge amplification, discrimination, neighbour logic, amplitude and timing measurements, analog-to-digital conversions, and either direct output for trigger or multiplexed readout. The front-end amplifier can operate with a wide range of input capacitances, has adjustable polarity, gain and peaking time. The VMM2 is the second version of the VMM ASIC family fabricated in 2014. It was tested with resistive Micromegas prototypes in the 2015 test beam campaigns at CERN. The specification and performance of the VMM2 will be presented as well as the Micromegas detector performance with the VMM2.

  2. Genetic mapping of ASIC4 and contrasting phenotype to ASIC1a in modulating innate fear and anxiety.

    Science.gov (United States)

    Lin, Shing-Hong; Chien, Ya-Chih; Chiang, Wei-Wei; Liu, Yan-Zhen; Lien, Cheng-Chang; Chen, Chih-Cheng

    2015-06-01

    Although ASIC4 is a member of the acid-sensing ion channel (ASIC) family, we have limited knowledge of its expression and physiological function in vivo. To trace the expression of this ion channel, we generated the ASIC4-knockout/CreERT(2)-knockin (Asic4(Cre) (ERT) (2)) mouse line. After tamoxifen induction in the Asic4(Cre) (ERT)(2)::CAG-STOP(floxed)-Td-tomato double transgenic mice, we mapped the expression of ASIC4 at the cellular level in the central nervous system (CNS). ASIC4 was expressed in many brain regions, including the olfactory bulb, cerebral cortex, striatum, hippocampus, amygdala, thalamus, hypothalamus, brain stem, cerebellum, spinal cord and pituitary gland. Colocalisation studies further revealed that ASIC4 was expressed mainly in three types of cells in the CNS: (i) calretinin (CR)-positive and/or vasoactive intestine peptide (VIP)-positive interneurons; (ii) neural/glial antigen 2 (NG2)-positive glia, also known as oligodendrocyte precursor cells; and (iii) cerebellar granule cells. To probe the possible role of ASIC4, we hypothesised that ASIC4 could modulate the membrane expression of ASIC1a and thus ASIC1a signaling in vivo. We conducted behavioral phenotyping of Asic4(Cre) (ERT)(2) mice by screening many of the known behavioral phenotypes found in Asic1a knockouts and found ASIC4 not involved in shock-evoked fear learning and memory, seizure termination or psychostimulant-induced locomotion/rewarding effects. In contrast, ASIC4 might play an important role in modulating the innate fear response to predator odor and anxious state because ASIC4-mutant mice showed increased freezing response to 2,4,5-trimethylthiazoline and elevated anxiety-like behavior in both the open-field and elevated-plus maze. ASIC4 may modulate fear and anxiety by counteracting ASIC1a activity in the brain.

  3. NIRCA ASIC for the readout of focal plane arrays

    Science.gov (United States)

    Pâhlsson, Philip; Steenari, David; Øya, Petter; Otnes Berge, Hans Kristian; Meier, Dirk; Olsen, Alf; Hasanbegovic, Amir; Altan, Mehmet A.; Najafiuchevler, Bahram; Talebi, Jahanzad; Azman, Suleyman; Gheorghe, Codin; Ackermann, Jörg; Mæhlum, Gunnar; Johansen, Tor Magnus; Stein, Timo

    2016-05-01

    This work is a continuation of our preliminary tests on NIRCA - the Near Infrared Readout and Controller ASIC [1]. The primary application for NIRCA is future astronomical science and Earth observation missions where NIRCA will be used with mercury cadmium telluride image sensors (HgCdTe, or MCT) [2], [3]. Recently we have completed the ASIC tests in the cryogenic environment down to 77 K. We have verified that NIRCA provides to the readout integrated circuit (ROIC) regulated power, bias voltages, and fully programmable digital sequences with sample control of the analogue to digital converters (ADC). Both analog and digital output from the ROIC can be acquired and image data is 8b/10bencoded and delivered via serial interface. The NIRCA also provides temperature measurement, and monitors several analog and digital input channels. The preliminary work confirms that NIRCA is latch-up immune and able to operate down to 77 K. We have tested the performance of the 12-bit ADC with pre-amplifier to have 10.8 equivalent number of bits (ENOB) at 1.4 Msps and maximum sampling speed at 2 Msps. The 1.8-V and 3.3-V output regulators and the 10-bit DACs show good linearity and work as expected. A programmable sequencer is implemented as a micro-controller with a custom instruction set. Here we describe the special operations of the sequencer with regards to the applications and a novel approach to parallel real-time hardware outputs. The test results of the working prototype ASIC show good functionality and performance from room temperature down to 77 K. The versatility of the chip makes the architecture a possible candidate for other research areas, defense or industrial applications that require analog and digital acquisition, voltage regulation, and digital signal generation.

  4. Preliminary validation results of an ASIC for the readout and control of near-infrared large array detectors

    Science.gov (United States)

    Pâhlsson, Philip; Meier, Dirk; Otnes Berge, Hans Kristian; Øya, Petter; Steenari, David; Olsen, Alf; Hasanbegovic, Amir; Altan, Mehmet A.; Najafiuchevler, Bahram; Talebi, Jahanzad; Azman, Suleyman; Gheorghe, Codin; Ackermann, Jörg; Mæhlum, Gunnar

    2015-06-01

    In this paper we present initial test results of the Near Infrared Readout and Controller ASIC (NIRCA), designed for large area image sensors under contract from the European Space Agency (ESA) and the Norwegian Space Center. The ASIC is designed to read out image sensors based on mercury cadmium telluride (HgCdTe, or MCT) operating down to 77 K. IDEAS has developed, designed and initiated testing of NIRCA with promising results, showing complete functionality of all ASIC sub-components. The ASIC generates programmable digital signals to clock out the contents of an image array and to amplify, digitize and transfer the resulting pixel charge. The digital signals can be programmed into the ASIC during run-time and allows for windowing and custom readout schemes. The clocked out voltages are amplified by programmable gain amplifiers and digitized by 12-bit, 3-Msps successive approximation register (SAR) analogue-to-digital converters (ADC). Digitized data is encoded using 8-bit to 10-bit encoding and transferred over LVDS to the readout system. The ASIC will give European researchers access to high spectral sensitivity, very low noise and radiation hardened readout electronics for astronomy and Earth observation missions operating at 77 K and room temperature. The versatility of the chip makes the architecture a possible candidate for other research areas, or defense or industrial applications that require analog and digital acquisition, voltage regulation, and digital signal generation.

  5. Optical Link ASICs for the LHC Upgrade

    CERN Document Server

    Gan, K K; Kass, R D; Moore, J R; Smith, D S

    2009-01-01

    We have designed three ASICs for possible applications in the optical links of a new layer of pixel detector in the ATLAS experiment for the first phase of the LHC luminosity upgrade. The ASICs include a high-speed driver for the VCSEL, a receiver/decoder to decode the signal received at the PIN diode to extract the data and clock, and a clock multiplier to produce a higher frequency clock to serialize the data for transmission. These ASICs were designed using a 130 nm CMOS process to enhance the radiation-hardness. We have characterized the fabricated ASICs and the submission has been mostly successful. We irradiated the ASICs with 24 GeV/c protons at CERN to a dosage of 70 Mrad. We observed no significant degradation except the driver circuit in the VCSEL driver fabricated using the thick oxide process in order to provide sufficient voltage to drive a VCSEL. The degradation is due to a large threshold shifts in the PMOS transistors used.

  6. XAMPS Detectors Readout ASIC for LCLS

    Energy Technology Data Exchange (ETDEWEB)

    Dragone, A; /SLAC; Pratte, J.F.; Rehak, P.; /Brookhaven; Carini, G.A.; /BNL, NSLS; Herbst, R.; /SLAC; O' Connor, P.; /Brookhaven; Siddons, D.P.; /BNL, NSLS

    2008-12-18

    An ASIC for the readout of signals from X-ray Active Matrix Pixel Sensor (XAMPS) detectors to be used at the Linac Coherent Light Source (LCLS) is presented. The X-ray Pump Probe (XPP) instrument, for which the ASIC has been designed, requires a large input dynamic range on the order of 104 photons at 8 keV with a resolution of half a photon FWHM. Due to the size of the pixel and the length of the readout line, large input capacitance is expected, leading to stringent requirement on the noise optimization. Furthermore, the large number of pixels needed for a good position resolution and the fixed LCLS beam period impose limitations on the time available for the single pixel readout. Considering the periodic nature of the LCLS beam, the ASIC developed for this application is a time-variant system providing low-noise charge integration, filtering and correlated double sampling. In order to cope with the large input dynamic range a charge pump scheme implementing a zero-balance measurement method has been introduced. It provides an on chip 3-bit coarse digital conversion of the integrated charge. The residual charge is sampled using correlated double sampling into analog memory and measured with the required resolution. The first 64 channel prototype of the ASIC has been fabricated in TSMC CMOS 0.25 {micro}m technology. In this paper, the ASIC architecture and performances are presented.

  7. SIDECAR ASIC firmware for astronomy applications

    Science.gov (United States)

    Chen, Jing; Loose, Markus; Ricardo, Raphael; Beletic, James; Farris, Mark; Xu, Min; Wong, Andre; Cabelli, Craig

    2014-07-01

    The SIDECAR ASIC is a fully integrated system-on-a-chip focal plane array controller that offers low power and low noise, small size and low weight. It has been widely used to operate different image sensors for ground-based and flightbased astronomy applications. A key mechanism to operating analog detectors is the SIDECAR ASIC's high level of programmability. This paper gives an overview of the SIDECAR ASIC architecture, including its optimized microcontroller featuring a customized instruction set. It describes the firmware components, including timing generation, biasing, commanding, housekeeping and synchronization of multiple detectors. The firmware development tools including compiler and supporting development environment and hardware setup are presented. The firmware capability for ground-based HxRG applications and for flight-based applications like the James Webb Space Telescope (JWST), the repair of the Advanced Camera for Surveys (ACS), and others are also discussed.

  8. Timing and control requirements for a 32-channel AMU-ADC ASIC for the PHENIX detector

    Energy Technology Data Exchange (ETDEWEB)

    Emery, M.S.; Ericson, M.N.; Britton, C.L. Jr. [and others

    1998-02-01

    A custom CMOS Application Specific Integrated Circuit (ASIC) has been developed consisting of an analog memory unit (AMU) has been developed consisting of an analog memory unit (AMU) and analog to digital converter (ADC), both of which have been designed for applications in the PHENIX experiment. This IC consists of 32 pipes of analog memory with 64 cells per pipe. Each pipe also has its own ADC channel. Timing and control signal requirements for optimum performance are discussed in this paper.

  9. Characterisation of the NA62 GigaTracker end of column readout ASIC

    Science.gov (United States)

    Noy, M.; Aglieri Rinella, G.; Fiorini, M.; Jarron, P.; Kaplon, J.; Kluge, A.; Martin, E.; Morel, M.; Perktold, L.; Riedler, P.

    2011-01-01

    The architecture and characterisation of the End Of Column demonstrator readout ASIC for the NA62 GigaTracker hybrid pixel detector is presented. This ASIC serves as a proof of principle for a pixel chip with 1800 pixels which must perform time stamping to better than 200 ps (RMS), provide 300 μm pitch position information and operate with a dead-time of 1% or less for 800 MHz-1 GHz beam rate. The demonstrator ASIC comprises a full test column with 45 pixels alongside other test structures. The timewalk correction mechanism employed is measurement of the time-over-threshold, coupled with an off-detector look-up table. The time to digital converter is a delay locked loop with 32 contributing delay cells fed with a 320 MHz to yield a nominal bin size of 97 ps. Recently, P-in-N sensors have been bump-bonded to the ASIC and characterisation of these assemblies has begun.

  10. A wireless capsule system with ASIC for monitoring the physiological signals of the human gastrointestinal tract.

    Science.gov (United States)

    Xu, Fei; Yan, Guozheng; Zhao, Kai; Lu, Li; Gao, Jinyang; Liu, Gang

    2014-12-01

    This paper presents the design of a wireless capsule system for monitoring the physiological signals of the human gastrointestinal (GI) tract. The primary components of the system include a wireless capsule, a portable data recorder, and a workstation. Temperature, pH, and pressure sensors; an RF transceiver; a controlling and processing application specific integrated circuit (ASIC); and batteries were applied in a wireless capsule. Decreasing capsule size, improving sensor precision, and reducing power needs were the primary challenges; these were resolved by employing micro sensors, optimized architecture, and an ASIC design that include power management, clock management, a programmable gain amplifier (PGA), an A/D converter (ADC), and a serial peripheral interface (SPI) communication unit. The ASIC has been fabricated in 0.18- μm CMOS technology with a die area of 5.0 mm × 5.0 mm. The wireless capsule integrating the ASIC controller measures Φ 11 mm × 26 mm. A data recorder and a workstation were developed, and 20 cases of human experiments were conducted in hospitals. Preprocessing in the workstation can significantly improve the quality of the data, and 76 original features were determined by mathematical statistics. Based on the 13 optimal features achieved in the evaluation of the features, the clustering algorithm can identify the patients who lack GI motility with a recognition rate reaching 83.3%.

  11. An analogue front-end ASIC prototype designed for PMT signal readout

    Science.gov (United States)

    Liu, Jian-Feng; Zhao, Lei; Yu, Li; Liang, Yu; Qin, Jia-Jun; Yang, Yun-Fan; Wu, Wei-Hao; Liu, Shu-Bin; An, Qi

    2016-06-01

    The Water Cherenkov Detector Array (WCDA) is one of the core detectors in the Large High Altitude Air Shower Observatory (LHAASO), and it consists of 3600 photomultiplier tubes (PMTs). Both high resolution time and charge measurement are required over a large dynamic range from 1 photoelectron (P.E.) to 4000 P.E. The prototype of an analogue front-end Application Specific Integrated Circuit (ASIC) fabricated using Global Foundry 0.35 μm CMOS technology is designed to read out the PMT signal in the WCDA. This ASIC employs leading edge discrimination and an (RC)4 shaping structure. Combined with the following Time-to-Digital Converter (TDC) and Analog-to-Digital Converter (ADC), both the arrival time and charge of the PMT signal can be measured. Initial test results indicate that time resolution is better than 350 ps and charge resolution is better than 10% at 1 P.E. and better than 1% with large input signals (300 P.E. to 4000 P.E.). Besides, this ASIC has a good channel-to-channel isolation of more than 84 dB and the temperature dependency of charge measurement is less than 5% in the range 0-50°C. Supported by Knowledge Innovation Program of Chinese Academy of Sciences (KJCX2-YW-N27), National Natural Science Foundation of China (11175174) and CAS Center for Excellence in Particle Physics (CCEPP)

  12. Abnormal Cardiac Autonomic Regulation in Mice Lacking ASIC3

    Directory of Open Access Journals (Sweden)

    Ching-Feng Cheng

    2014-01-01

    Full Text Available Integration of sympathetic and parasympathetic outflow is essential in maintaining normal cardiac autonomic function. Recent studies demonstrate that acid-sensing ion channel 3 (ASIC3 is a sensitive acid sensor for cardiac ischemia and prolonged mild acidification can open ASIC3 and evoke a sustained inward current that fires action potentials in cardiac sensory neurons. However, the physiological role of ASIC3 in cardiac autonomic regulation is not known. In this study, we elucidate the role of ASIC3 in cardiac autonomic function using Asic3−/− mice. Asic3−/− mice showed normal baseline heart rate and lower blood pressure as compared with their wild-type littermates. Heart rate variability analyses revealed imbalanced autonomic regulation, with decreased sympathetic function. Furthermore, Asic3−/− mice demonstrated a blunted response to isoproterenol-induced cardiac tachycardia and prolonged duration to recover to baseline heart rate. Moreover, quantitative RT-PCR analysis of gene expression in sensory ganglia and heart revealed that no gene compensation for muscarinic acetylcholines receptors and beta-adrenalin receptors were found in Asic3−/− mice. In summary, we unraveled an important role of ASIC3 in regulating cardiac autonomic function, whereby loss of ASIC3 alters the normal physiological response to ischemic stimuli, which reveals new implications for therapy in autonomic nervous system-related cardiovascular diseases.

  13. Large dynamic range 64-channel ASIC for CZT or CdTe detectors

    Energy Technology Data Exchange (ETDEWEB)

    Glasser, F. E-mail: francis.glasser@cea.fr; Villard, P.; Rostaing, J.P.; Accensi, M.; Baffert, N.; Girard, J.L

    2003-08-21

    We present a customized 64-channel ASIC, named ALIX, developed in a 0.8 {mu}m CMOS technology. This circuit is dedicated to measure charges from semi-conductor X-ray detectors like Cadmium Zinc Telluride (CZT) or Cadmium Telluride CdTe. The specificity of ALIX is to be able to measure charges over a very large dynamic range (from 10 fC to 3 nC), and to store eight measurements in a very short time (from every 250 ns to a few ms). Up to eight images are stored inside the ASIC and each image can be read out in 64 {mu}s. A new acquisition sequence can then be started. Two analog readouts are available, one for the X-ray signal and one for the offset and afterglow measurement in case of pulsed X-rays. The outputs are converted into digital values by two off-chip 14 bits Analog-to-Digital Converters (ADC). A first version of ALIX has been tested with CZT and CdTe detectors under high-energy pulsed X-ray photons (20 MeV, 60 ns pulses every 250 ns). We will present the different results of linearity and signal-to-noise ratio. A second version of ALIX has been designed with some corrections. Electrical tests performed on 85 ASICS showed that the corrections were successful. We are now able to integrate them behind a 64x32 pixels 1 mm pitch CZT detector. Such an ASIC could also be used for strip detectors where a large dynamic range and a fast response are necessary.

  14. Large dynamic range 64-channel ASIC for CZT or CdTe detectors

    Science.gov (United States)

    Glasser, F.; Villard, P.; Rostaing, J. P.; Accensi, M.; Baffert, N.; Girard, J. L.

    2003-08-01

    We present a customized 64-channel ASIC, named ALIX, developed in a 0.8 μm CMOS technology. This circuit is dedicated to measure charges from semi-conductor X-ray detectors like Cadmium Zinc Telluride (CZT) or Cadmium Telluride CdTe. The specificity of ALIX is to be able to measure charges over a very large dynamic range (from 10 fC to 3 nC), and to store eight measurements in a very short time (from every 250 ns to a few ms). Up to eight images are stored inside the ASIC and each image can be read out in 64 μs. A new acquisition sequence can then be started. Two analog readouts are available, one for the X-ray signal and one for the offset and afterglow measurement in case of pulsed X-rays. The outputs are converted into digital values by two off-chip 14 bits Analog-to-Digital Converters (ADC). A first version of ALIX has been tested with CZT and CdTe detectors under high-energy pulsed X-ray photons (20 MeV, 60 ns pulses every 250 ns). We will present the different results of linearity and signal-to-noise ratio. A second version of ALIX has been designed with some corrections. Electrical tests performed on 85 ASICS showed that the corrections were successful. We are now able to integrate them behind a 64×32 pixels 1 mm pitch CZT detector. Such an ASIC could also be used for strip detectors where a large dynamic range and a fast response are necessary.

  15. VMM - An ASIC for Micropattern Detectors

    CERN Document Server

    Iakovidis, Georgios; The ATLAS collaboration; De Geronimo, Gianluigi

    2015-01-01

    The VMM is a custom Application Specific Integrated Circuit (ASIC) that can be used in a va- riety of charge interpolated tracking detectors. It is designed to be used with the resistive Micromegas and sTGC detectors in the New Small Wheel upgrade of the ATLAS Muon spectrometer. The ASIC is designed at Brookhaven National Laboratory and fabricated in the 130 nm Global Foundries 8RF-DM process. The devices will be packaged in a Ball Grid Array with outline dimensions of 21 × 21 mm2 . It integrates 64 channels, each providing charge amplification, discrimination, neighbour logic, amplitude and timing measurements, analog- to-digital conversions, and either direct output for trigger or multiplexed readout. The front-end amplifier can operate with a wide range of input capacitances, has adjustable polarity, gain and peaking time. The VMM2 is the second version of the VMM ASIC family fabricated in 2014. The design, tests and qualification of the VMM1, VMM2 and roadmap to VMM3 is described.

  16. Configurable Radiation Hardened High Speed Isolated Interface ASIC Project

    Data.gov (United States)

    National Aeronautics and Space Administration — NVE Corporation will design and build an innovative, low cost, flexible, configurable, radiation hardened, galvanically isolated, interface ASIC chip set that will...

  17. A 130 nm ASIC prototype for the NA62 Gigatracker readout

    Energy Technology Data Exchange (ETDEWEB)

    Dellacasa, G., E-mail: gdellaca@to.infn.it [I.N.F.N. sez. Torino, via Giuria 1, 10125 Torino (Italy); Garbolino, S. [Universita degli Studi di Torino, Dip. Fisica Sperimentale, via Giuria 1, 10125 Torino (Italy); Marchetto, F. [I.N.F.N. sez. Torino, via Giuria 1, 10125 Torino (Italy); Martoiu, S. [I.N.F.N. sez. Torino, via Giuria 1, 10125 Torino (Italy); CERN CH-1211, Geneve 23 (Switzerland); Mazza, G.; Rivetti, A.; Wheadon, R. [I.N.F.N. sez. Torino, via Giuria 1, 10125 Torino (Italy)

    2011-09-11

    One of the most challenging detectors of the NA62 experiment is the silicon tracker, called Gigatracker. It consists of three hybrid silicon pixel stations, each one covering an area of 27 mmx60 mm. While the maximum pixel size is fairly large, 300{mu}mx300{mu}m the system has to sustain a very high particle rate, 1.5 MHz/mm{sup 2}, which corresponds to 800 MHz for each station. To obtain an efficient tracking with such a high rate the required track timing resolution is 150 ps (rms). Therefore the front-end ASIC should provide for each pixel a 200 ps time measurement capability, thus leading to the requirement of time walk compensation and very compact TDCs. Moreover, Single Event Upset protection has to be implemented in order to protect the digital circuitry. An ASIC prototype has been realized in CMOS 130 nm technology, containing three pixel columns. The chip performs the time walk compensation by a Constant Fraction Discriminator circuit, while the time measurement is performed by a Time to Amplitude Converter based TDC, both of them implemented on each pixel cell. The End of Column circuit containing only digital logic is responsible for the data readout from the pixel cell. The whole chip works with a system clock of 160 MHz and the digital logic is SEU protected by the use of Hamming codes. The detailed architecture of the ASIC prototype and test results are presented.

  18. ERICA: an energy resolving photon counting readout ASIC for X-ray in-line cameras

    Science.gov (United States)

    Macias-Montero, J.-G.; Sarraj, M.; Chmeissani, M.; Moore, T.; Casanova, R.; Martinez, R.; Puigdengoles, C.; Prats, X.; Kolstein, M.

    2016-12-01

    We present ERICA (Energy Resolving Inline X-ray Camera) a photon-counting readout ASIC, with 6 energy bins. The ASIC is composed of a matrix of 8 × 20 pixels controlled by a global digital controller and biased with 7 independent digital to analog converters (DACs) and a band-gap current reference. The pixel analog front-end includes a charge sensitive amplifier with 16 mV/ke- gain and dynamic range of 45 ke-. ERICA has programmable pulse width, an adjustable constant current feedback resistor, a linear test pulse generator, and six discriminators with 6-bit local threshold adjustment. The pixel digital back-end includes the digital controller, 8 counters of 8-bit depth, half-full buffer flag for any of the 8 counters, a 74-bit shadow/shift register, a 74-bit configuration latch, and charge sharing compensation processing to perform the energy classification and counting operations of every detected photon in 1 μ s. The pixel size is 330 μm × 330 μm and its average consumption is 150 μW. Implemented in TSMC 0.25 μm CMOS process, the ASIC pixel's equivalent noise charge (ENC) is 90 e- RMS connected to a 1 mm thickness matching CdTe detector biased at -300 V with a total leakage current of 20 nA.

  19. A 64ch readout module for PPD/MPPC/SiPM using EASIROC ASIC

    Energy Technology Data Exchange (ETDEWEB)

    Nakamura, Isamu, E-mail: isamu.nakamura@kek.jp [KEK, 1-1 Oho Tsukuba 305-0801 (Japan); Ishijima, N.; Hanagaki, K. [Osaka University, 1-1 Machikaneyama, Toyonaka, Osaka 560-0043 (Japan); Yoshimura, K. [Okayama University, 1-1 Tsushimanaka, Kita-ku, Okayama 700-8530 (Japan); Nakai, Y. [Kyushu University, 6-10-1 Hakozaki, Higashi-ku, Fukuoka 812-8581 (Japan); Ueno, K. [KEK, 1-1 Oho Tsukuba 305-0801 (Japan)

    2015-07-01

    A readout module for PPD/MPPC/GAPD/SiPM is developed using EASIROC ASIC. The module can handle 64 PPDs and has on-board bias power supply, ADC for energy measurement, 1 ns TDC on FPGA as well as 64ch Logic output for external trigger. Controls and data transfer are through SiTCP technology implemented in FPGA. The module has NIM format for convenience, but can be operated without crate with 5 V AC/DC converter. Basic performance of production module was tested and the results are presented in the poster.

  20. Expression and functions of ASIC1 in the zebrafish retina.

    Science.gov (United States)

    Liu, Sha; Wang, Mei-Xia; Mao, Cheng-Jie; Cheng, Xiao-Yu; Wang, Chen-Tao; Huang, Jian; Zhong, Zhao-Min; Hu, Wei-Dong; Wang, Fen; Hu, Li-Fang; Wang, Han; Liu, Chun-Feng

    2014-12-12

    It has been demonstrated that acid sensing ionic channels (ASICs) are present in the central and peripheral nervous system of mammals, including the retina. However, it remains unclear whether the zebrafish retina also expresses ASICs. In the present study, the expression and distribution of zasic1 were examined in the retina of zebrafish. Both zasic1 mRNA and protein expressions were detected in the adult zebrafish retina. A wide distribution of ASIC1 in zebrafish retina was confirmed using whole mount in situ hybridization and immunohistochemistry study. Acidosis-induced currents in the isolated retinal ganglion cells (RGCs) were also recorded using whole cell patch clamping. Moreover, blockade of ASICs channel significantly reduced the locomotion of larval zebrafish in response to light exposure. In sum, our data demonstrate the presence of ASIC1 and its possible functional relevance in the retina of zebrafish.

  1. ASIC Design and Implementation for Digital Pulse Compression Chip

    Institute of Scientific and Technical Information of China (English)

    高俊峰; 韩月秋; 王巍

    2004-01-01

    A novel ASIC design of changeable-point digital pulse compression (DPC) chip is presented. System hardware resource is reduced to one third of the traditional design method through operations sharing hardware, i.e. let FFT, complex multiplication and IFFT be fulfilled with the same hardware structure. Block-floating-point scaling is used to enhance the dynamic range and computation accuracy. This design applies parallel pipeline structure and the radix-4 butterfly operation to improve the processing speed. In addition, a triple-memory-space(TMS) configuration is used that allows input, computation and output operations to be overlapped, so that the dual-butterfly unit is never left in an idle state waiting for I/O operation. The whole design is implemented with only one chip of XC2V500-5 FPGA. It can implement 1 024-point DPC within 91.6 μs.The output data is converted to floating-point formation to achieve seamless interface with TMS320C6701. The validity of the design is verified by simulation and measurement results.

  2. Small Microprocessor for ASIC or FPGA Implementation

    Science.gov (United States)

    Kleyner, Igor; Katz, Richard; Blair-Smith, Hugh

    2011-01-01

    A small microprocessor, suitable for use in applications in which high reliability is required, was designed to be implemented in either an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA). The design is based on commercial microprocessor architecture, making it possible to use available software development tools and thereby to implement the microprocessor at relatively low cost. The design features enhancements, including trapping during execution of illegal instructions. The internal structure of the design yields relatively high performance, with a significant decrease, relative to other microprocessors that perform the same functions, in the number of microcycles needed to execute macroinstructions. The problem meant to be solved in designing this microprocessor was to provide a modest level of computational capability in a general-purpose processor while adding as little as possible to the power demand, size, and weight of a system into which the microprocessor would be incorporated. As designed, this microprocessor consumes very little power and occupies only a small portion of a typical modern ASIC or FPGA. The microprocessor operates at a rate of about 4 million instructions per second with clock frequency of 20 MHz.

  3. Status Report on the LOC ASIC

    CERN Document Server

    Ye, J

    2008-01-01

    Based on a commercially available 0.25 μm Silicon on Sapphire CMOS technology, we are developing the LOC ASIC for high speed serial data transmission in the front-end electronics systems of the ATLAS upgrade for the SLHC1. Evaluation of this technology for applications in the SLHC, based on a dedicated test chip, has been performed with irradiation tests in gamma (Co-60) and in 230 MeV proton beams. Test results indicate that this may be a candidate technology of ASIC developments for the SLHC. More thorough evaluation tests will be carried out under another R&D program supported through the Advanced Detector Research (ADR) from the Department of Energy. Characterization tests on the first prototype serializer, LOC1, have been carried out in lab. Based on the lessons learned from this chip, we propose a new architecture design of the second prototype, LOC2, aiming for a serial data rate in the range of 5 Gbps. Simulation on key components of LOC2 are being carried out and the results we have so far are p...

  4. An Analogue Front-End ASIC Prototype Designed For PMT Signal Readout

    CERN Document Server

    Liu, Jianfeng; Yu, Li; Liang, Yu; Qin, Jiajun; Yang, Yunfang; Wu, Weihao; Liu, Shubin; An, Qi

    2015-01-01

    The Large High Altitude Air Shower Observatory (LHAASO) is designed for high energy gamma ray and cosmic ray detection. A Water Cherenkov Detector Array which is sensitive to gamma ray showers above a few hundred GeV is proposed to survey gamma ray sources. The WCDA consists of 3600 PhotoMultiplier Tubes (PMT) which collect the Cherenkov light produced by the shower particles in water. Both high precision time and charge measurement are required over a large dynamic range from 1 photo electron (P.E.) to 4000 P.E. Prototype of an analogue front-end Application Specific Integrated Circuit (ASIC) fabricated in Chartered 0.35 {\\mu}m CMOS technology is designed to read out PMT signal in the WCDA. This ASIC employs leading edge discrimination and RC4 shaping structure; combined with the following Time-to-Digital Converter (TDC) and Analog-to-Digital Converter (ADC), both the arrival time and charge of the PMT signal can be measured. Initial test results indicate that time resolution is better than 350 ps and charge...

  5. Extreme Temperature, Rad-Hard Power Management ASIC Project

    Data.gov (United States)

    National Aeronautics and Space Administration — Ridgetop Group will design a rad-hard Application Specific Integrated Circuit (ASIC) for spacecraft power management that is functional over a temperature range of...

  6. Low-power Cross-Correlator ASIC Project

    Data.gov (United States)

    National Aeronautics and Space Administration — Pacific MicroCHIP Corporation offers to design an ASIC that includes a cross-correlation unit together with the interfaces to be connected to the output of the...

  7. Multipurpose Test Structures and Process Characterization using 0.13 μm CMOS: The CHAMP ASIC

    Science.gov (United States)

    Cooney, Michael; Andrew, Matt; Nishimura, Kurtis; Ruckman, Larry; Varner, Gary; Grabas, Hervé; Oberla, Eric; Genat, Jean-Francois; Large Area Picosecond Photodetector Collaboration

    The University of Hawaii (UH) in collaboration with the University of Chicago (UC) submitted a test Application Specific Integrated Circuit (ASIC), the Chicago-Hawaii ASIC MultiPurpose (CHAMP), composed of a number of discrete test elements in a 0.13 μm CMOS process. This paper describes the structures submitted by UH and UC. Hawaii designs include high speed flip-flops, voltage controlled ring oscillators and delay lines, an Low Voltage Differential Signal (LVDS) receiver, a set of four 64-cell waveform samplers with shared input, an analog storage and comparator structure, as well as a 12-bit Digital to Analog Converter (DAC). The Chicago designs include voltage controlled delay lines, delay locked loops, voltage controlled ring oscillators, transmission lines, and resistors. Each of the structures will be described, with simulation and test results presented.

  8. A 32-channel, 025 mum CMOS ASIC for the readout of the silicon drift detectors of the ALICE experiment

    CERN Document Server

    Mazza, G; Anghinolfi, F; Martínez, M I; Rivetti, A; Rotondo, F

    2004-01-01

    In this paper we present a 32 channel ASIC prototype for the readout of the silicon drift detectors (SDDs) of the ALICE experiment. The ASIC integrates on the same substrate 32 transimpedance amplifiers, a 32 x 256 cell analogue memory and 16 successive approximation 10 bit A/D converters. The circuit amplifies and samples at 40 MS/s the input signal in a continuous way. When an external trigger signal validates the acquisition, the sampling is stopped and the data are digitized at lower speed (0.5 MS/s). The chip has been designed and fabricated in a commercial 0.25 mum CMOS technology. It has been extensively tested both on a bench and connected with a detector in several beam tests. In this paper both design issues and test results are presented. The radiation tolerance of the design has been increased by special layout techniques. Total dose irradiation tests are also presented.

  9. Monolithic Active Pixel Matrix with Binary Counters (MAMBO) ASIC

    Energy Technology Data Exchange (ETDEWEB)

    Khalid, Farah F.; Deptuch, Grzegorz; Shenai, Alpana; Yarema, Raymond J.; /Fermilab

    2010-11-01

    Monolithic Active Matrix with Binary Counters (MAMBO) is a counting ASIC designed for detecting and measuring low energy X-rays from 6-12 keV. Each pixel contains analogue functionality implemented with a charge preamplifier, CR-RC{sup 2} shaper and a baseline restorer. It also contains a window comparator which can be trimmed by 4 bit DACs to remove systematic offsets. The hits are registered by a 12 bit ripple counter which is reconfigured as a shift register to serially output the data from the entire ASIC. Each pixel can be tested individually. Two diverse approaches have been used to prevent coupling between the detector and electronics in MAMBO III and MAMBO IV. MAMBO III is a 3D ASIC, the bottom ASIC consists of diodes which are connected to the top ASIC using {mu}-bump bonds. The detector is decoupled from the electronics by physically separating them on two tiers and using several metal layers as a shield. MAMBO IV is a monolithic structure which uses a nested well approach to isolate the detector from the electronics. The ASICs are being fabricated using the SOI 0.2 {micro}m OKI process, MAMBO III is 3D bonded at T-Micro and MAMBO IV nested well structure was developed in collaboration between OKI and Fermilab.

  10. ASIC1基因敲除小鼠的繁殖及基因鉴定%Reproduction and genotype identification of ASIC1 knockout mice

    Institute of Scientific and Technical Information of China (English)

    周仁鹏; 吴小山; 王志森; 葛金芳; 陈飞虎

    2015-01-01

    To breed and identify acid sensing ion channel 1(ASIC1) gene knockout mice, so as to lay the founda-tion for studying ASIC1 protein. The heterozygote mice were bred and reproduced. Genome DNA extracted from the murine tail was subjected to PCR test for genotype identification. Breeding and reproducing of ASIC1 knockout mice were both successful,and the genotypes of the offspring mice were heterozygous( ASIC1+/ -) ,homozygous( ASIC1-/ -) ,and wild-type( ASIC1+/ +) . Appropriate methods of breeding,reproducing and identifying can effective-ly obtain ASIC1-/ - mice.%饲养并繁殖酸敏感离子通道1(ASIC1)基因敲除杂合子小鼠,提取小鼠尾部组织DNA,采用聚合酶链反应( PCR)方法鉴定子代小鼠基因型. ASIC1 基因敲除小鼠的繁育和鉴定均获得成功,子代小鼠基因型分别为杂合子( ASIC1+/-)、纯合子( ASIC1-/ -)和野生型( ASIC1+/ +).

  11. An efficient real time superresolution ASIC system

    Science.gov (United States)

    Reddy, Dikpal; Yue, Zhanfeng; Topiwala, Pankaj

    2008-04-01

    Superresolution of images is an important step in many applications like target recognition where the input images are often grainy and of low quality due to bandwidth constraints. In this paper, we present a real-time superresolution application implemented in ASIC/FPGA hardware, and capable of 30 fps of superresolution by 16X in total pixels. Consecutive frames from the video sequence are grouped and the registered values between them are used to fill the pixels in the higher resolution image. The registration between consecutive frames is evaluated using the algorithm proposed by Schaum et al. The pixels are filled by averaging a fixed number of frames associated with the smallest error distances. The number of frames (the number of nearest neighbors) is a user defined parameter whereas the weights in the averaging process are decided by inverting the corresponding smallest error distances. Wiener filter is used to post process the image. Different input parameters, such as size of input image, enlarging factor and the number of nearest neighbors, can be tuned conveniently by the user. We use a maximum word size of 32 bits to implement the algorithm in Matlab Simulink as well as the hardware, which gives us a fine balance between the number of bits and performance. The algorithm performs with real time speed with very impressive superresolution results.

  12. Charged Particle Tracking with the Timepix ASIC

    CERN Document Server

    Akiba, Kazuyoshi; Collins, P; Crossley, M; Dumps, R; Gersabeck, M; Gligorov, Vladimir V; Llopart, X; Nicol, M; Poikela, T; Cabruja, Enric; Fleta, C; Lozano, M; Pellegrini, G; Bates, R; Eklund, L; Hynds, D; Ferre Llin, L; Maneuski, D; Parkes, C; Plackett, R; Rodrigues, E; Stewart, G; Akiba, K; van Beuzekom, M; Heijne, V; Heijne, E H M; Gordon, H; John, M; Gandelman, M; Esperante, D; Gallas, A; Vazquez Regueiro, P; Bayer, F; Michel, T; Needham, M; Artuso, M; Badman, R; Borgia, A; Garofoli, J; Wang, J; Xing, Z; Buytaert, Jan; Leflat, Alexander

    2012-01-01

    A prototype particle tracking telescope has been constructed using Timepix and Medipix ASIC hybrid pixel assemblies as the six sensing planes. Each telescope plane consisted of one 1.4 cm2 assembly, providing a 256x256 array of 55 micron square pixels. The telescope achieved a pointing resolution of 2.3 micron at the position of the device under test. During a beam test in 2009 the telescope was used to evaluate in detail the performance of two Timepix hybrid pixel assemblies; a standard planar 300 micron thick sensor, and 285 micron thick double sided 3D sensor. This paper describes a detailed charge calibration study of the pixel devices, which allows the true charge to be extracted, and reports on measurements of the charge collection characteristics and Landau distributions. The planar sensor achieved a best resolution of 4.0 micron for angled tracks, and resolutions of between 4.4 and 11 micron for perpendicular tracks, depending on the applied bias voltage. The double sided 3D sensor, which has signific...

  13. Development of an ASIC for Si/CdTe detectors in a radioactive substance visualizing system

    Science.gov (United States)

    Harayama, Atsushi; Takeda, Shin`ichiro; Sato, Goro; Ikeda, Hirokazu; Watanabe, Shin; Takahashi, Tadayuki

    2014-11-01

    We report on the recent development of a 64-channel analog front-end ASIC for a new gamma-ray imaging system designed to visualize radioactive substances. The imaging system employs a novel Compton camera which consists of silicon (Si) and cadmium telluride (CdTe) detectors. The ASIC is intended for the readout of pixel/pad detectors utilizing Si/CdTe as detector materials, and covers a dynamic range up to 1.4 MeV. The readout chip consists of 64 identical signal channels and was implemented with X-FAB 0.35 μm CMOS technology. Each channel contains a charge-sensitive amplifier, a pole-zero cancellation circuit, a low-pass filter, a comparator, and a sample-hold circuit, along with a Wilkinson-type A-to-D converter. We observed an equivalent noise charge of 500 e- and a noise slope of 5 e-/pF (r.m.s.) with a power consumption of 2.1 mW per channel. The chip works well when connected to Schottky CdTe diodes, and delivers spectra with good energy resolution, such as 12 keV (FWHM) at 662 keV and 24 keV (FWHM) at 1.33 MeV.

  14. Development of an ASIC for Si/CdTe detectors in a radioactive substance visualizing system

    Energy Technology Data Exchange (ETDEWEB)

    Harayama, Atsushi, E-mail: harayama@astro.isas.jaxa.jp [Institute of Space and Astronautical Science, Japan Aerospace Exploration Agency, Sagamihara, Kanagawa 229-8510 (Japan); Takeda, Shin' ichiro [Institute of Space and Astronautical Science, Japan Aerospace Exploration Agency, Sagamihara, Kanagawa 229-8510 (Japan); Sato, Goro [RIKEN Nishina Center, 2-1 Hirosawa, Wako, Saitama 351-0198 (Japan); Institute of Space and Astronautical Science, Japan Aerospace Exploration Agency, Sagamihara, Kanagawa 229-8510 (Japan); Ikeda, Hirokazu; Watanabe, Shin; Takahashi, Tadayuki [Institute of Space and Astronautical Science, Japan Aerospace Exploration Agency, Sagamihara, Kanagawa 229-8510 (Japan)

    2014-11-21

    We report on the recent development of a 64-channel analog front-end ASIC for a new gamma-ray imaging system designed to visualize radioactive substances. The imaging system employs a novel Compton camera which consists of silicon (Si) and cadmium telluride (CdTe) detectors. The ASIC is intended for the readout of pixel/pad detectors utilizing Si/CdTe as detector materials, and covers a dynamic range up to 1.4 MeV. The readout chip consists of 64 identical signal channels and was implemented with X-FAB 0.35μm CMOS technology. Each channel contains a charge-sensitive amplifier, a pole-zero cancellation circuit, a low-pass filter, a comparator, and a sample-hold circuit, along with a Wilkinson-type A-to-D converter. We observed an equivalent noise charge of ∼500 e{sup −} and a noise slope of ∼5 e{sup −}/pF (r.m.s.) with a power consumption of 2.1 mW per channel. The chip works well when connected to Schottky CdTe diodes, and delivers spectra with good energy resolution, such as ∼12 keV (FWHM) at 662 keV and ∼24 keV (FWHM) at 1.33 MeV.

  15. CWICOM: A Highly Integrated & Innovative CCSDS Image Compression ASIC

    Science.gov (United States)

    Poupat, Jean-Luc; Vitulli, Raffaele

    2013-08-01

    The space market is more and more demanding in terms of on image compression performances. The earth observation satellites instrument resolution, the agility and the swath are continuously increasing. It multiplies by 10 the volume of picture acquired on one orbit. In parallel, the satellites size and mass are decreasing, requiring innovative electronic technologies reducing size, mass and power consumption. Astrium, leader on the market of the combined solutions for compression and memory for space application, has developed a new image compression ASIC which is presented in this paper. CWICOM is a high performance and innovative image compression ASIC developed by Astrium in the frame of the ESA contract n°22011/08/NLL/LvH. The objective of this ESA contract is to develop a radiation hardened ASIC that implements the CCSDS 122.0-B-1 Standard for Image Data Compression, that has a SpaceWire interface for configuring and controlling the device, and that is compatible with Sentinel-2 interface and with similar Earth Observation missions. CWICOM stands for CCSDS Wavelet Image COMpression ASIC. It is a large dynamic, large image and very high speed image compression ASIC potentially relevant for compression of any 2D image with bi-dimensional data correlation such as Earth observation, scientific data compression… The paper presents some of the main aspects of the CWICOM development, such as the algorithm and specification, the innovative memory organization, the validation approach and the status of the project.

  16. Performance of VATA64HDR16 ASIC for medical physics applications based on continuous crystals and SiPMs

    Science.gov (United States)

    Barrio, J.; Etxebeste, A.; Lacasta, C.; Muñoz, E.; Oliver, J. F.; Solaz, C.; Llosá, G.

    2015-12-01

    Detectors based on Silicon Photomultipliers (SiPMs) coupled to continuous crystals are being tested in medical physics applications due to their potential high resolution and sensitivity. To cope with the high granularity required for a very good spatial resolution, SiPM matrices with a large amount of elements are needed. To be able to read the information coming from each individual channel, dedicated ASICs are employed. The VATA64HDR16 ASIC is a 64-channel, charge-sensitive amplifier that converts the collected charge into a proportional current or voltage signal. A complete assessment of the suitability of that ASIC for medical physics applications based on continuous crystals and SiPMs has been carried out. The input charge range is linear from 0-2 pC up to 55 pC. The energy resolution obtained at 511 keV is 10% FWHM with a LaBr3 crystal and 16% FWHM with a LYSO crystal. A coincidence timing resolution of 24 ns FWHM is obtained with two LYSO crystals.

  17. A 45 nm Low Cost, Radiation Hardened, Platform Based Structured ASIC Project

    Data.gov (United States)

    National Aeronautics and Space Administration — The proposed 45 nm radiation hardened platform based structured ASIC architecture offers the performance and density expected of a custom ASIC with the low...

  18. HEXITEC ASIC-a pixellated readout chip for CZT detectors

    Energy Technology Data Exchange (ETDEWEB)

    Jones, Lawrence [STFC Rutherford Appleton Laboratory, Didcot OX11 0QX (United Kingdom)], E-mail: l.l.jones@stfc.ac.uk; Seller, Paul; Wilson, Matthew; Hardie, Alec [STFC Rutherford Appleton Laboratory, Didcot OX11 0QX (United Kingdom)

    2009-06-01

    HEXITEC is a collaborative project with the aim of developing a new range of detectors for high-energy X-ray imaging. High-energy X-ray imaging has major advantages over current lower energy imaging for the life and physical sciences, including improved phase-contrast images on larger, higher density samples and with lower accumulated doses. However, at these energies conventional silicon-based devices cannot be used, hence, the requirement for a new range of high Z-detector materials. Underpinning the HEXITEC programme are the development of a pixellated Cadmium Zinc Telluride (CZT) detectors and a pixellated readout ASIC which will be bump-bonded to the detector. The HEXITEC ASIC is required to have low noise (20 electrons rms) and tolerate detector leakage currents. A prototype 20x20 pixel ASIC has been developed and manufactured on a standard 0.35 {mu}m CMOS process.

  19. The read-out ASIC for the Space NUCLEON project

    Science.gov (United States)

    Atkin, E.; Voronin, A.; Karmanov, D.; Kudryashov, I.; Podorozhniy, D.; Shumikhin, V.

    2015-04-01

    This paper summarizes the design results for the read-out ASIC for the space NUCLEON project of the Russian Federal Space Agency ROSCOSMOS. The ASIC with a unique high dynamic range (1-40 000 mip) at low power consumption ( 50, generated by silicon detectors, having capacitances up to 100 pF. The chip structure includes 32 analog channels, each consisting of a charge sensitive amplifier (CSA) with a p-MOS input transistor (W = 8 mm, L = 0.5 μ m), a shaper (peaking time of 2 us) and a T&H circuit. The ASIC showed a 120 pC dynamic range at a SNR of 2.5 for the particles with minimal ionization energy (1 mip). The chip was fabricated by the 0.35 um CMOS process via Europractice and tested both at lab conditions and in the SPS beam at CERN.

  20. IMOTEPAD: A mixed-signal 64-channel front-end ASIC for small-animal PET imaging

    Science.gov (United States)

    Fang, Xiaochao; Ollivier-Henry, Nicolas; Gao, Wu; Hu-Guo, Christine; Colledani, Claude; Humbert, Bernard; Brasse, David; Hu, Yann

    2011-04-01

    This paper presents the design and characteristics of a mixed-signal 64-channel front-end readout ASIC called IMOTEPAD dedicated to multi-channel plate (MCP) photodetector coupled to LYSO scintillating crystals for small-animal PET imaging. In our configuration, the crystals are oriented in the axial direction readout on both sides by individual photodetector channels allowing the spatial resolution and the detection efficiency to be independent of each other. As a result, both energy signals and timing triggers from the photodetectors are required to be read out by the front-end ASIC. This dedicated ASIC IMOTEPAD comprises two parts: the analog part IMOTEPA and the digital part IMOTEPD. The IMOTEPA is dedicated to energy measurement. And the timing information is digitized by the IMOTEPD in which the key principal element is a time-to-digital converter (TDC) based on a delay-locked loop (DLL) with 32 delay cells. The chip is designed and fabricated in 0.35 μm CMOS process. The measurements show that for the analog part IMOTEPA, the energy gain is 13.1 mV/pC while the peak time of a CR-RC pulse shaper is 280 ns. The SNR is 39 dB and the RMS noise is 300 μV. The nonlinearity is less than 3%. The crosstalk is less than 0.2%. For the IMOTEPD, the bin size of the TDC is 625 ps with a reference clock of 50 MHz. The RMS jitter of the DLL is less than 42 ps. The DNL of the TDC is equal to about 0.17 LSB and the INL is equal to 0.31 LSB. The power dissipation of each channel is less than 16.8 mW. The design of the ASIC, especially for TDC and the measurement results of the IMOTEPAD will be presented and discussed in this paper.

  1. A novel simulation and verification approach in an ASIC design process

    CERN Document Server

    Husmann, D; Mahboubi, K; Pfeiffer, U; Schumacher, C

    2000-01-01

    We have built a fast signal-processing and readout ASIC (PPrAsic) for the Pre-Processor system of the ATLAS Level-1 Calorimeter Trigger. Our novel ASIC design environment incorporates algorithm development with digital hardware synthesis and verification. The purely digital ASIC was designed in Verilog HDL (hardware description language) and embedded in a system wide analog and digital simulation or implemented algorithms. We present here our design environment and experience that we gained from the design process. (10 refs).

  2. Development of a selftriggered high counting rate ASIC for readout of 2D gas microstrip neutron detectors

    CERN Document Server

    Brogna, AS; Dabrowski, W; Fiutowski, T; Gebauer, B; Mindur, B; Schmidt, Ch J; Schulz, Ch; Soltveit, H K; Szczygiel, R; Trunk, U; Wiacek, P

    2007-01-01

    In the frame of the DETNI project a 32-channel ASIC suitable for readout of a novel 2D thermal neutron detector based on a hybrid low-pressure Micro-Strip Gas Chamber with solid 157Gd converter has been developed. Each channel delivers position information, a fast time stamp of 2 ns resolution and the signal amplitude (called energy below). The time stamp is used for correlating the signals from X and Y strips while the amplitude is used for finding the center of gravity of a cluster of strips. The timing and energy information are stored in derandomizing buffers and read out via token ring architecture.

  3. A 2D 4×4 Channel Readout ASIC for Pixelated CdTe Detectors for Medical Imaging Applications

    OpenAIRE

    Macias-Montero, Jose-Gabriel; Sarraj, Maher; Chmeissani, Mokhtar; Martínez, Ricardo; Puigdengoles, Carles

    2015-01-01

    We present a 16-channel readout integrated circuit (ROIC) with nanosecond-resolution time to digital converter (TDC) for pixelated Cadmium Telluride (CdTe) gamma-ray detectors. The 4 × 4 pixel array ROIC is the proof of concept of the 10 × 10 pixel array readout ASIC for positron-emission tomography (PET) scanner, positron-emission mammography (PEM) scanner, and Compton gamma camera. The electronics of each individual pixel integrates an analog front-end with switchable gain, an analog to dig...

  4. Beam test performance of the SKIROC2 ASIC

    CERN Document Server

    Frisson, T; Anduze, M; Augustin, J.E; Bonis, J; Boudry, V; Bourgeois, C; Brient, J.C; Callier, S; Cerutti, M; Chen, S; Cornat, R; Cornebise, P; Cuisy, D; David, J; De la Taille, C; Dulucq, F; Frotin, M; Gastaldi, F; Ghislain, P; Giraud, J; Gonnin, A; Grondin, D; Guliyev, E; Hostachy, J.Y; Jeans, D; Kamiya, Y; Kawagoe, K; Kozakai, C; Lacour, D; Lavergne, L; Lee, S.H; Magniette, F; Ono, H; Poeschl, R; Rouëné, J; Seguin-Moreau, N; Song, H.S; Sudo, Y; Thiebault, A; Tran, H; Ueno, H; Van der Kolk, N; Yoshioka, T

    2015-01-01

    Beam tests of the first layers of CALICE silicon tungsten ECAL technological prototype were performed in April and July 2012 using 1–6 GeV electron beam at DESY. This paper presents an analysis of the SKIROC2 readout ASIC performance under test beam conditions.

  5. Three-dimensional stacked structured ASIC devices and methods of fabrication thereof

    Energy Technology Data Exchange (ETDEWEB)

    Shinde, Subhash L.; Teifel, John; Flores, Richard S.; Jarecki Jr., Robert L.; Bauer, Todd

    2015-11-19

    A 3D stacked sASIC is provided that includes a plurality of 2D reconfigurable structured structured ASIC (sASIC) levels interconnected through hard-wired arrays of 3D vias. The 2D sASIC levels may contain logic, memory, analog functions, and device input/output pad circuitry. During fabrication, these 2D sASIC levels are stacked on top of each other and fused together with 3D metal vias. Such 3D vias may be fabricated as through-silicon vias (TSVs). They may connect to the back-side of the 2D sASIC level, or they may be connected to top metal pads on the front-side of the 2D sASIC level.

  6. FROST: an ASIC for digital mammography with synchrotron radiation

    Energy Technology Data Exchange (ETDEWEB)

    Bergamaschi, A. E-mail: bergamaschi@ts.infn.it; Prest, M.; Vallazza, E.; Arfelli, F.; Dreossi, D.; Longo, R.; Olivo, A.; Pani, S.; Castelli, E

    2003-09-01

    The FRONTier RADiography (FRONTRAD) collaboration is developing a digital system for mammography at the Elettra Synchrotron Light Source in Trieste. The system is based on a silicon microstrip detector array. The ASIC FROST (FRONTRAD Read Out sySTem) was developed as a collaboration between INFN Trieste and Aurelia Microelettronica and is designed to operate in single photon counting mode. FROST provides low-noise and high-gain performances and is able to work at incident photon rates higher than 100 kHz with almost 100% efficiency. The ASIC has been tested and the first images of mammographic test objects will be shown. The acquisition time per breast image should be of about 10 s.

  7. Implementation of the Timepix ASIC in the Scalable Readout System

    Science.gov (United States)

    Lupberger, M.; Desch, K.; Kaminski, J.

    2016-09-01

    We report on the development of electronics hardware, FPGA firmware and software to provide a flexible multi-chip readout of the Timepix ASIC within the framework of the Scalable Readout System (SRS). The system features FPGA-based zero-suppression and the possibility to read out up to 4×8 chips with a single Front End Concentrator (FEC). By operating several FECs in parallel, in principle an arbitrary number of chips can be read out, exploiting the scaling features of SRS. Specifically, we tested the system with a setup consisting of 160 Timepix ASICs, operated as GridPix devices in a large TPC field cage in a 1 T magnetic field at a DESY test beam facility providing an electron beam of up to 6 GeV. We discuss the design choices, the dedicated hardware components, the FPGA firmware as well as the performance of the system in the test beam.

  8. Data encryption standard ASIC design and development report.

    Energy Technology Data Exchange (ETDEWEB)

    Robertson, Perry J.; Pierson, Lyndon George; Witzke, Edward L.

    2003-10-01

    This document describes the design, fabrication, and testing of the SNL Data Encryption Standard (DES) ASIC. This device was fabricated in Sandia's Microelectronics Development Laboratory using 0.6 {micro}m CMOS technology. The SNL DES ASIC was modeled using VHDL, then simulated, and synthesized using Synopsys, Inc. software and finally IC layout was performed using Compass Design Automation's CAE tools. IC testing was performed by Sandia's Microelectronic Validation Department using a HP 82000 computer aided test system. The device is a single integrated circuit, pipelined realization of DES encryption and decryption capable of throughputs greater than 6.5 Gb/s. Several enhancements accommodate ATM or IP network operation and performance scaling. This design is the latest step in the evolution of DES modules.

  9. Development of the read-out ASIC for muon chambers

    Science.gov (United States)

    Atkin, E.; Bulbakov, I.; Gusev, A.; Malankin, E.; Normanov, D.; Sagdiev, I.; Shumikhin, V.; Shumkin, O.; Ivanov, P.; Vinogradov, S.; Voronin, A.; Samsonov, V.; Ivanov, V.

    2016-02-01

    A front-end prototype ASIC for muon chambers is presented. ASIC was designed and prototyped in the CMOS UMC MMRF 180 nm process via Europractice. The chip includes 8 analog processing channels, each consisting of a preamplifier, two shapers (fast and slow), differential comparator and an area efficient 6 bit SAR ADC with 1.2 mW power consumption at 50 Msps. The chip also includes the threshold DAC and digital serializer. The design has the following features: dynamic range of 100 fC, channel hit rate of 2 MHz, ENC of 1000 e- at 50 pF, power consumption of 10 mW per channel, 6 bit SAR ADC.

  10. Implementation of the Timepix ASIC in the Scalable Readout System

    Energy Technology Data Exchange (ETDEWEB)

    Lupberger, M., E-mail: lupberger@physik.uni-bonn.de; Desch, K.; Kaminski, J.

    2016-09-11

    We report on the development of electronics hardware, FPGA firmware and software to provide a flexible multi-chip readout of the Timepix ASIC within the framework of the Scalable Readout System (SRS). The system features FPGA-based zero-suppression and the possibility to read out up to 4×8 chips with a single Front End Concentrator (FEC). By operating several FECs in parallel, in principle an arbitrary number of chips can be read out, exploiting the scaling features of SRS. Specifically, we tested the system with a setup consisting of 160 Timepix ASICs, operated as GridPix devices in a large TPC field cage in a 1 T magnetic field at a DESY test beam facility providing an electron beam of up to 6 GeV. We discuss the design choices, the dedicated hardware components, the FPGA firmware as well as the performance of the system in the test beam.

  11. VeloPix ASIC for the LHCb VELO Upgrade

    CERN Multimedia

    Cid Vidal, Xabier

    2015-01-01

    The LHCb Vertex Detector (VELO) will be upgraded in 2018 along with the other subsystems of LHCb in order to enable full detector readout at 40 MHz. LHCb will run without a hardware trigger and all data will be fed directly to the software triggering algorithms in the CPU farm. The upgraded VELO is a lightweight silicon hybrid pixel detector with 55 um square pixels, operating in vacuum in close proximity to the LHC beams. The readout will be provided by a dedicated front end ASIC, dubbed VeloPix, matched to the LHCb luminosity requirements. VeloPix is a binary pixel chip with a matrix of 256 x 256 pixels, covering an area of 2 cm^2. It is designed in a 130 nm CMOS technology, and is closely related to the Timepix3, from the Medipix family of ASICs. The principal challenge that the chip has to meet is a hit rate of up to 900 Mhits/s/ASIC, resulting in a data rate of more than 16 Gbit/s. Combining pixels into groups of 2x4 super-pixels enables the use of shared logic and a reduction of bandwidth due to combine...

  12. ASIC for High Rate 3D Position Sensitive Detectors

    Energy Technology Data Exchange (ETDEWEB)

    Vernon, E.; De Geronimo, G.; Ackley, K.; Fried, J.; He, Z.; Herman, C.; Zhang, F.

    2010-06-16

    We report on the development of an application specific integrated circuit (ASIC) for 3D position sensitive detectors (3D PSD). The ASIC is designed to operate with pixelated wide bandgap sensors like Cadmium-Zinc-Telluride (CZT), Mercuric Iodide (Hgl2) and Thallium Bromide (TIBr). It measures the amplitudes and timings associated with an ionizing event on 128 anodes, the anode grid, and the cathode. Each channel provides low-noise charge amplification, high-order shaping with peaking time adjustable from 250 ns to 12 {micro}s, gain adjustable to 20 mV/fC or 120 mV/fC (for a dynamic range of 3.2 MeV and 530 keV in CZT), amplitude discrimination with 5-bit trimming, and positive and negative peak and timing detections. The readout can be full or sparse, based on a flag and single- or multi-cycle token passing. All channels, triggered channels only, or triggered with neighbors can be read out thus increasing the rate capability of the system to more than 10 kcps. The ASIC dissipates 330 mW which corresponds to about 2.5 mW per channel.

  13. Front-end ASIC for pixilated wide bandgap detectors

    Science.gov (United States)

    Vernon, Emerson; de Geronimo, Gianluigi; Fried, Jack; Herman, Cedric; Zhang, Feng; He, Zhong

    2009-08-01

    A CMOS application specific integrated circuit (ASIC) was developed for 3D Position Sensitive Detectors (PSD). The preamplifiers were optimized for pixellated Cadmium-Zinc-Telluride (CZT) Mercuric-Iodide (HgI2) and Thallium Bromide (TlBr) sensors. The ASIC responds to an ionizing event in the sensor by measuring both amplitude and timing in the pertinent anode and cathode channels. Each channel is sensitive to events and transients of positive or negative polarity and performs low-noise charge amplification, high-order shaping, peak and timing detection along with analog storage and multiplexing. Three methodologies are implemented to perform timing measurement in the cathode channel. Multiple sparse modes are available for the readout of channel data. The ASIC integrates 130 channels in an area of 12 x 9 mm2 and dissipates ~330 mW. With a CZT detector connected and biased, an electronic resolution of ~200 e- rms for charges up to 100 fC was measured. Spectral data from the University of Michigan revealed a cumulative single-pixel resolution of ~0.55 % FWHM at 662 KeV.

  14. JPIC-Rad-Hard JPEG2000 Image Compression ASIC

    Science.gov (United States)

    Zervas, Nikos; Ginosar, Ran; Broyde, Amitai; Alon, Dov

    2010-08-01

    JPIC is a rad-hard high-performance image compression ASIC for the aerospace market. JPIC implements tier 1 of the ISO/IEC 15444-1 JPEG2000 (a.k.a. J2K) image compression standard [1] as well as the post compression rate-distortion algorithm, which is part of tier 2 coding. A modular architecture enables employing a single JPIC or multiple coordinated JPIC units. JPIC is designed to support wide data sources of imager in optical, panchromatic and multi-spectral space and airborne sensors. JPIC has been developed as a collaboration of Alma Technologies S.A. (Greece), MBT/IAI Ltd (Israel) and Ramon Chips Ltd (Israel). MBT IAI defined the system architecture requirements and interfaces, The JPEG2K-E IP core from Alma implements the compression algorithm [2]. Ramon Chips adds SERDES interfaces and host interfaces and integrates the ASIC. MBT has demonstrated the full chip on an FPGA board and created system boards employing multiple JPIC units. The ASIC implementation, based on Ramon Chips' 180nm CMOS RadSafe[TM] RH cell library enables superior radiation hardness.

  15. Low power Analog Digital Converter for a silicon photomultiplier readout ASIC

    Science.gov (United States)

    Briggl, K.; Chen, H.; Shen, W.; Schultz-Coulon, H. C.

    2015-04-01

    We present an ADC designed in the UMC 0.18um CMOS technology. It will be used in the SiPM analog front-end ``KLauS" developed for the analog hadronic calorimeter at ILD. Key parameter in this application is an extremely low power consumption of the front-end electronics. For quantization of the energy depositions, a 10-bit ADC resolution is required. For calibration purposes, a 12-bit quantization is used. A successive approximation register split capacitor array structure is chosen to minimize the DC power consumption. A peak sensing block is used to minimize the required sampling rate. We present design details and simulation results of the ADC, as well as the peak sensing track & hold circuit.

  16. ASIC Based Galvanically Isolated Driver Circuit for the Use in Power Converters for Photovoltaic Applications

    OpenAIRE

    Niedermeier, Markus

    2014-01-01

    The generation of electricity by photovoltaic sources plays a great role in the transition from fossil energy sources to renewable energy sources. It gained momentum especially since the introduction of affordable photovoltaic systems for private customers is accompanied by public subsidies. This leads to the application of photovoltaic systems in urban areas where conventional string topologies of photovoltaic arrays that are applied in solar parks are less efficient due to the effects of pa...

  17. The SIRIUS Mixed analog-digital ASIC developed for the LOFT LAD and WFM instruments

    CERN Document Server

    Cros, A; Moutaye, E; Ravera, L; Barret, D; Caïs, P; Clédassou, R; Bodin, P; Seyler, JY; Bonzo, A; Feroci, M; Labanti, C; Evangelista, Y; Favre, Y

    2014-01-01

    We report on the development and characterization of the low-noise, low power, mixed analog-digital SIRIUS ASICs for both the LAD and WFM X-ray instruments of LOFT. The ASICs we developed are reading out large area silicon drift detectors (SDD). Stringent requirements in terms of noise (ENC of 17 e- to achieve an energy resolution on the LAD of 200 eV FWHM at 6 keV) and power consumption (650 {\\mu}W per channel) were basis for the ASICs design. These SIRIUS ASICs are developed to match SDD detectors characteristics: 16 channels ASICs adapted for the LAD (970 microns pitch) and 64 channels for the WFM (145 microns pitch) will be fabricated. The ASICs were developed with the 180nm mixed technology of TSMC.

  18. A Low Power Application-Specific Integrated Circuit (ASIC) Implementation of Wavelet Transform/Inverse Transform

    Science.gov (United States)

    2001-03-01

    A unique ASIC was designed implementing the Haar Wavelet transform for image compression/decompression. ASIC operations include performing the Haar... wavelet transform on a 512 by 512 square pixel image, preparing the image for transmission by quantizing and thresholding the transformed data, and...performing the inverse Haar wavelet transform , returning the original image with only minor degradation. The ASIC is based on an existing four-chip FPGA

  19. Wavelength Converters

    DEFF Research Database (Denmark)

    Kloch, Allan; Hansen, Peter Bukhave; Wolfson, David;

    1999-01-01

    at 2.5 Gbit/s, the regeneration causes a reduction of the required input power to an in-line EDFA of ~6 dB for a power penalty of 1 dB at a bit error rate of 10-9. If two converters are concatenated the power requirement is reduced ~8 dB. Obviously, the power reduction allows for longer spans between....... It is predicted that jitter accumulation can be minimised by using a 9-10 dB ratio between the signal and CW power also assuring a high extinction ratio. Using this guideline simulations show that 20 cross-gain modulation converters can be cascaded at 10 Gbit/s with only ~20 ps of accumulated jitter...... and an extinction ratio of ~10 dB.The regenerative capabilities of the cross-phase converters are described and verified experimentally at 20 Gbit/s, where the noise redistribution and improvement of the signal-to-noise ratio clearly is demonstrated by controlling the input power to an EDFA. In a similar experiment...

  20. HDL Design for 1 Zetta Bits Per Second (1 Zbps Multichannel 64:1 LVDS Data Serializer & De-Serializer ASIC Array Card Design for 6th Sense and Future Ultra High Wireless and Mobile Communication Protocol Cards

    Directory of Open Access Journals (Sweden)

    P. N. V. M SASTRY

    2015-01-01

    Full Text Available The Aim is to HDL Design & Implementation for Exa Bit Rate Multichannel 64:1 LVDS Data Serializer & De-Serializer ASIC Array Card for Ultra High Speed Wireless Communication Products like Network On Chip Routers, Data Bus Communication Interface Applications, Cloud Computing Networks , Zetta bit Ethernet at Zetta Bit Rate Of Data Transfer Speed. Basically This Serializer Array Converts 64 bit parallel Data Array in to Serial Array Form on Transmitter Side and Transmission Done through High Speed Wireless Serial Communication Link and also Converts this Same Serial Array Data into Parallel Data Array on the Receiver Side by De-Serializer Array ASIC without any noise, also measure Very High Compressed Jitter Tolerance & Eye Diagram, Bit Error Rate through Analyzer. This LVDS Data SER-De-SER mainly used in High Speed Bus Communication Protocol Transceivers, Interface FPGA Add On Cards. The Process Of Design is Implemented through Verilog HDL / VHDL, Programming & Debugging Done Latest FPGA Board.

  1. Performance of 2nd generation CALICE/EUDET ASICs

    Science.gov (United States)

    de La Taille, C.; CALICE Collaboration; EUDET Collaboration

    2011-04-01

    The paper reviews the performance of the three ASICs : HARDROC2, SPIROC2 and SKIROC2 developed to readout the ILC calorimeter prototypes. The chips integrate 36 to 64 channels of front-end, digitization and backend electronics in SiGe 0.35 μm technology. This second version was found mature enough to be produced in several hundreds to equip large scale technological prototypes and establish the feasibility of these highly granular "imaging" calorimeters as required for particle flow algorithms at the ILC. The low noise and low power sequential readout as well as power-pulsing operation at detector level and in magnetic field are proven.

  2. A prototype hybrid pixel detector ASIC for the CLIC experiment

    CERN Document Server

    Valerio, P; Arfaoui, S; Ballabriga, R; Benoit, M; Bonacini, S; Campbell, M; Dannheim, D; De Gaspari, M; Felici, D; Kulis, S; Llopart, X; Nascetti, A; Poikela, T; Wong, W S

    2014-01-01

    A prototype hybrid pixel detector ASIC specifically designed to the requirements of the vertex detector for CLIC is described and first electrical measurements are presented. The chip has been designed using a commercial 65 nm CMOS technology and comprises a matrix of 64x64 square pixels with 25 μm pitch. The main features include simultaneous 4-bit measure- ment of Time-over-Threshold (ToT) and Time-of-Arrival (ToA) with 10 ns accuracy, on-chip data compression and power pulsing capability.

  3. Multichannel readout ASIC design flow for high energy physics and cosmic rays experiments

    Science.gov (United States)

    Voronin, A.; Malankin, E.

    2016-02-01

    In the large-scale high energy physics and astrophysics experiments multi-channel readout application specific integrated circuits (ASICs) are widely used. The ASICs for such experiments are complicated systems, which usually include both analog and digital building blocks. The complexity and large number of channels in such ASICs require the proper methodological approach to their design. The paper represents the mixed-signal design flow of the ASICs for high energy physics and cosmic rays experiments. This flow was successfully embedded to the development of the read-out ASIC prototype for the muon chambers of the CBM experiment. The approach was approved in UMC CMOS MMRF 180 nm process. The design flow enable to analyse the mixed-signal system operation on the different levels: functional, behavioural, schematic and post layout including parasitic elements. The proposed design flow allows reducing the simulation period and eliminating the functionality mismatches on the very early stage of the design.

  4. A prototype of pixel readout ASIC in 65 nm CMOS technology for extreme hit rate detectors at HL-LHC

    Science.gov (United States)

    Paternò, A.; Pacher, L.; Monteil, E.; Loddo, F.; Demaria, N.; Gaioni, L.; De Canio, F.; Traversi, G.; Re, V.; Ratti, L.; Rivetti, A.; Da Rocha Rolo, M.; Dellacasa, G.; Mazza, G.; Marzocca, C.; Licciulli, F.; Ciciriello, F.; Marconi, S.; Placidi, P.; Magazzù, G.; Stabile, A.; Mattiazzo, S.; Veri, C.

    2017-02-01

    This paper describes a readout ASIC prototype designed by the CHIPIX65 project, part of RD53, for a pixel detector at HL-LHC . A 64×64 matrix of 50×50μm2 pixels is realised. A digital architecture has been developed, with particle efficiency above 99.5% at 3 GHz/cm2 pixel rate, trigger frequency of 1 MHz and 12.5μsec latency. Two analog front end designs, one synchronous and one asynchronous, are implemented. Charge is measured with 5-bit precision, analog dead-time below 1%. The chip integrates for the first time many of the components developed by the collaboration in the past, including the Digital-to-Analog converters, Bandgap reference, Serializer, sLVS drivers, and analog Front Ends. Irradiation tests on these components proved their reliability up to 600 Mrad.

  5. READOUT ASIC FOR 3D POSITION-SENSITIVE DETECTORS.

    Energy Technology Data Exchange (ETDEWEB)

    DE GERONIMO,G.; VERNON, E.; ACKLEY, K.; DRAGONE, A.; FRIED, J.; OCONNOR, P.; HE, Z.; HERMAN, C.; ZHANG, F.

    2007-10-27

    We describe an application specific integrated circuit (ASIC) for 3D position-sensitive detectors. It was optimized for pixelated CZT sensors, and it measures, corresponding to an ionizing event, the energy and timing of signals from 121 anodes and one cathode. Each channel provides low-noise charge amplification, high-order shaping, along with peak- and timing-detection. The cathode's timing can be measured in three different ways: the first is based on multiple thresholds on the charge amplifier's voltage output; the second uses the threshold crossing of a fast-shaped signal; and the third measures the peak amplitude and timing from a bipolar shaper. With its power of 2 mW per channel the ASIC measures, on a CZT sensor Connected and biased, charges up to 100 fC with an electronic resolution better than 200 e{sup -} rms. Our preliminary spectral measurements applying a simple cathode/mode ratio correction demonstrated a single-pixel resolution of 4.8 keV (0.72 %) at 662 keV, with the electronics and leakage current contributing in total with 2.1 keV.

  6. A CMOS ASIC Design for SiPM Arrays.

    Science.gov (United States)

    Dey, Samrat; Banks, Lushon; Chen, Shaw-Pin; Xu, Wenbin; Lewellen, Thomas K; Miyaoka, Robert S; Rudell, Jacques C

    2011-12-01

    Our lab has previously reported on novel board-level readout electronics for an 8×8 silicon photomultiplier (SiPM) array featuring row/column summation technique to reduce the hardware requirements for signal processing. We are taking the next step by implementing a monolithic CMOS chip which is based on the row-column architecture. In addition, this paper explores the option of using diagonal summation as well as calibration to compensate for temperature and process variations. Further description of a timing pickoff signal which aligns all of the positioning (spatial channels) pulses in the array is described. The ASIC design is targeted to be scalable with the detector size and flexible to accommodate detectors from different vendors. This paper focuses on circuit implementation issues associated with the design of the ASIC to interface our Phase II MiCES FPGA board with a SiPM array. Moreover, a discussion is provided for strategies to eventually integrate all the analog and mixed-signal electronics with the SiPM, on either a single-silicon substrate or multi-chip module (MCM).

  7. Replication of Space-Shuttle Computers in FPGAs and ASICs

    Science.gov (United States)

    Ferguson, Roscoe C.

    2008-01-01

    A document discusses the replication of the functionality of the onboard space-shuttle general-purpose computers (GPCs) in field-programmable gate arrays (FPGAs) and application-specific integrated circuits (ASICs). The purpose of the replication effort is to enable utilization of proven space-shuttle flight software and software-development facilities to the extent possible during development of software for flight computers for a new generation of launch vehicles derived from the space shuttles. The replication involves specifying the instruction set of the central processing unit and the input/output processor (IOP) of the space-shuttle GPC in a hardware description language (HDL). The HDL is synthesized to form a "core" processor in an FPGA or, less preferably, in an ASIC. The core processor can be used to create a flight-control card to be inserted into a new avionics computer. The IOP of the GPC as implemented in the core processor could be designed to support data-bus protocols other than that of a multiplexer interface adapter (MIA) used in the space shuttle. Hence, a computer containing the core processor could be tailored to communicate via the space-shuttle GPC bus and/or one or more other buses.

  8. Exploring Many-Core Design Templates for FPGAs and ASICs

    Directory of Open Access Journals (Sweden)

    Ilia Lebedev

    2012-01-01

    Full Text Available We present a highly productive approach to hardware design based on a many-core microarchitectural template used to implement compute-bound applications expressed in a high-level data-parallel language such as OpenCL. The template is customized on a per-application basis via a range of high-level parameters such as the interconnect topology or processing element architecture. The key benefits of this approach are that it (i allows programmers to express parallelism through an API defined in a high-level programming language, (ii supports coarse-grained multithreading and fine-grained threading while permitting bit-level resource control, and (iii reduces the effort required to repurpose the system for different algorithms or different applications. We compare template-driven design to both full-custom and programmable approaches by studying implementations of a compute-bound data-parallel Bayesian graph inference algorithm across several candidate platforms. Specifically, we examine a range of template-based implementations on both FPGA and ASIC platforms and compare each against full custom designs. Throughout this study, we use a general-purpose graphics processing unit (GPGPU implementation as a performance and area baseline. We show that our approach, similar in productivity to programmable approaches such as GPGPU applications, yields implementations with performance approaching that of full-custom designs on both FPGA and ASIC platforms.

  9. DIRAC v2 a DIgital Readout Asic for hadronic Calorimeter

    CERN Document Server

    Gaglione, R; Chefdeville, M; Drancourt, C; Vouters, G

    2009-01-01

    DIRAC is a 64 channel mixed-signal readout integrated circuit designed for Micro-Pattern Gaseous Detectors (MICROMEGAS, Gas Electron Multiplier) or Resistive Plate Chambers. These detectors are foreseen as the active part of a digital hadronic calorimeter for a high energy physics experiment at the International Linear Collider. Physic requirements lead to a highly granular hadronic calorimeter with up to thirty million channels with probably only hit information (digital calorimeter). The DIRAC ASIC has been especially designed for these constraints. Each channel of the DIRAC chip is made of a 4 gains charge preamplifier, a DC-servo loop, 3 switched comparators and a digital memory, thus providing additional energy information for a hit. A bulk MICROMEGAS detector with embedded DIRAC v1 ASIC has been built. The tests of this assembly, both in laboratory with X-Rays and in a beam at CERN are presented, demonstrating the feasibility of a bulk MICROMEGAS detector with embedded electronics. The second version of...

  10. Radiation-hard ASICs for optical data transmission in the first phase of the LHC upgrade

    CERN Document Server

    Gan, K K; Kagan, H P; Kass, R D; Moore, J R; Smith, D S; Wiese, A; Ziolkowskic, M; 10.1088/1748-0221/5/12/C12006

    2010-01-01

    We have designed two ASICs for possible applications in the optical links of a new layer of the pixel detector to be install inside the ATLAS Pixel detector for the first phase of the LHC luminosity upgrade. The ASICs include a high-speed driver for the VCSEL and a receiver/decoder to decode the signal received at the PIN diode to extract the data and clock. Both ASICs contain 4 channels for operation with a VCSEL or PIN array. The ASICs were designed using a 130 nm CMOS process to enhance the radiation-hardness. We have characterized the fabricated ASICs and the performance of the ASICs is satisfactory. The receiver/decoder can properly decode the bi-phase marked input stream with low PIN current and the driver can operate a VCSEL up to ~ 5 Gb/s. The added functionalities are also successful, including redundancy to bypass a broken VCSEL or PIN channel, individual control of VCSEL current, and power-on reset circuit to set all VCSEL currents to a nominal value. The ASICs were irradiated to a dose of 46 Mrad ...

  11. Reconfigurable ASIC for a Low Level Trigger System in Cherenkov Telescope Cameras

    CERN Document Server

    Gascon, David; Blanch, Oscar; Boix, Joan; Delagnes, Eric; Delgado, Carlos; Freixas, Lluís; Guilloux, Fabrice; López-Coto, Rubén; Griffiths, Scott; Martínez, Gustavo; Martínez, Oscar; Sanuy, Andreu; Tejedor, Luis Ángel

    2016-01-01

    A versatile and reconfigurable ASIC is presented, which implements two different concepts of low level trigger (L0) for Cherenkov telescopes: the Majority trigger (sum of discriminated inputs) and the Sum trigger concept (analogue clipped sum of inputs). Up to 7 input signals can be processed following one or both of the previous trigger concepts. Each differential pair output of the discriminator is also available as a LVDS output. Differential circuitry using local feedback allows the ASIC to achieve high speed (500 MHz) while maintaining good linearity in a 1 Vpp range. Experimental results are presented. A number of prototype camera designs of the Cherenkov Telescope Array (CTA) project will use this ASIC.

  12. Characterization of the VEGA ASIC coupled to large area position-sensitive Silicon Drift Detectors

    CERN Document Server

    Campana, R; Fuschino, F; Ahangarianabhari, M; Macera, D; Bertuccio, G; Grassi, M; Labanti, C; Marisaldi, M; Malcovati, P; Rachevski, A; Zampa, G; Zampa, N; Andreani, L; Baldazzi, G; Del Monte, E; Favre, Y; Feroci, M; Muleri, F; Rashevskaya, I; Vacchi, A; Ficorella, F; Giacomini, G; Picciotto, A; Zuffa, M

    2014-01-01

    Low-noise, position-sensitive Silicon Drift Detectors (SDDs) are particularly useful for experiments in which a good energy resolution combined with a large sensitive area is required, as in the case of X-ray astronomy space missions and medical applications. This paper presents the experimental characterization of VEGA, a custom Application Specific Integrated Circuit (ASIC) used as the front-end electronics for XDXL-2, a large-area (30.5 cm^2) SDD prototype. The ASICs were integrated on a specifically developed PCB hosting also the detector. Results on the ASIC noise performances, both stand-alone and bonded to the large area SDD, are presented and discussed.

  13. ASIC Design of Floating-Point FFT Processor

    Institute of Scientific and Technical Information of China (English)

    陈禾; 赵忠武

    2004-01-01

    An application specific integrated circuit (ASIC) design of a 1024 points floating-point fast Fourier transform(FFT) processor is presented. It can satisfy the requirement of high accuracy FFT result in related fields. Several novel design techniques for floating-point adder and multiplier are introduced in detail to enhance the speed of the system. At the same time, the power consumption is decreased. The hardware area is effectively reduced as an improved butterfly processor is developed. There is a substantial increase in the performance of the design since a pipelined architecture is adopted, and very large scale integrated (VLSI) is easy to realize due to the regularity. A result of validation using field programmable gate array (FPGA) is shown at the end. When the system clock is set to 50 MHz, 204.8 μs is needed to complete the operation of FFT computation.

  14. Design of versatile ASIC and protocol tester for CBM readout system

    Science.gov (United States)

    Zabołotny, W. M.; Byszuk, A. P.; Emschermann, D.; Gumiński, M.; Juszczyk, B.; Kasiński, K.; Kasprowicz, G.; Lehnert, J.; Müller, W. F. J.; Poźniak, K.; Romaniuk, R.; Szczygieł, R.

    2017-02-01

    Silicon Tracking System (STS), Muon Chamber (MUCH) and Transition Radiation Detector (TRD) subdetectors in the Compressed Baryonic Matter (CBM) detector system at Facility for Antiproton and Ion Research (FAIR) use the same innovative protocol ensuring reliable synchronization of the communication link between the controller and the front-end ASIC, transmission of time-deterministic commands to the ASIC and efficient readout of data. The paper describes the FPGA-based tester platform which can be used both for the verification of the protocol implementation in a front-end ASIC at the design stage, and for testing of the produced ASICs. Due to its modularity, the platform can be easily adapted for different integrated circuits and readout systems.

  15. Structure and erosion resistance ofNi60A/SiC coatting by laser cladding

    Institute of Scientific and Technical Information of China (English)

    LOU Bai-yang; CHEN Zhen; BAI Wan-jin; DONG Gang

    2006-01-01

    The Ni60A and Ni60A/SiC coatings were obtained by laser cladding on 0.45% C steel. The microstructure and hardness of the coatings were studied by SEM and XRD. The erosion resistances of Ni60A and Ni60A/SiC coatings were also investigated. The results show that the structure of different coatings is up to the temperature gradient and solidifying velocity in metal-melting region during laser cladding process. The coatings consist of a cladding layer, in which dendritic crystal and bulky cell-like crystal exist mainly, and a thermo-affected layer. Ni60A/SiC coating has higher microhardness than that of Ni60A coating, which is mainly caused by SiC and complicated phases formed by Ni, Cr, Fe, C and Si. It is obvious from the erosion test that the Ni60A/SiC coating has high erosion resistance.

  16. High-Speed, Low Power 256 Channel Gamma Radiation Array Detector ASIC Project

    Data.gov (United States)

    National Aeronautics and Space Administration — Building on prior success in detector electronics, we propose to design and fabricate a 256 channel readout ASIC for solid state gamma radiation array detectors...

  17. Wide Temperature Rad-Hard ASIC for Process Control of a Fuel Cell System Project

    Data.gov (United States)

    National Aeronautics and Space Administration — Ridgetop Group developed a top-level design of a rad-hard application-specific integrated circuit (ASIC) for spacecraft power management that is functional over a...

  18. ASIC2 is present in human mechanosensory neurons of the dorsal root ganglia and in mechanoreceptors of the glabrous skin.

    Science.gov (United States)

    Cabo, R; Alonso, P; Viña, E; Vázquez, G; Gago, A; Feito, J; Pérez-Moltó, F J; García-Suárez, O; Vega, J A

    2015-03-01

    Mechanosensory neurons lead to the central nervous system touch, vibration and pressure sensation. They project to the periphery and form different kinds of mechanoreceptors. The manner in which they sense mechanical signals is still not fully understood, but electrophysiological experiments have suggested that this may occur through the activation of ion channels that gate in response to mechanical stimuli. The acid-sensing ion channels (ASICs), especially ASIC2, may function as mechanosensors or are required for mechanosensation, and they are expressed in both mechanosensory neurons and mechanoreceptors. Here, we have used double immunohistochemistry for ASIC2 together with neuronal and glial markers associated with laser confocal microscopy and image analysis, to investigate the distribution of ASIC2 in human lumbar dorsal root ganglia, as well as in mechanoreceptors of the hand and foot glabrous skin. In lumbar dorsal root ganglia, ASIC2 immunoreactive neurons were almost all intermediate or large sized (mean diameter ≥20-70 µm), and no ASIC2 was detected in the satellite glial. ASIC2-positive axons were observed in Merkel cell-neurite complexes, Meissner and Pacinian corpuscles, all of them regarded as low-threshold mechanoreceptors. Moreover, a variable percent of Meissner (8 %) and Pacinian corpuscles (27 %) also displayed ASIC2 immunoreactivity in the Schwann-related cells. These results demonstrate the distribution of ASIC2 in the human cutaneous mechanosensory system and suggest the involvement of ASIC2 in mechanosensation.

  19. Knockdown of acid-sensing ion channel 1a (ASIC1a) suppresses disease phenotype in SCA1 mouse model.

    Science.gov (United States)

    Vig, Parminder J S; Hearst, Scoty M; Shao, Qingmei; Lopez, Maripar E

    2014-08-01

    The mutated ataxin-1 protein in spinocerebellar ataxia 1 (SCA1) targets Purkinje cells (PCs) of the cerebellum and causes progressive ataxia due to loss of PCs and neurons of the brainstem. The exact mechanism of this cellular loss is still not clear. Currently, there are no treatments for SCA1; however, understanding of the mechanisms that regulate SCA1 pathology is essential for devising new therapies for SCA1 patients. We previously established a connection between the loss of intracellular calcium-buffering and calcium-signalling proteins with initiation of neurodegeneration in SCA1 transgenic (Tg) mice. Recently, acid-sensing ion channel 1a (ASIC1a) have been implicated in calcium-mediated toxicity in many brain disorders. Here, we report generating SCA1 Tg mice in the ASIC1a knockout (KO) background and demonstrate that the deletion of ASIC1a gene expression causes suppression of the SCA1 disease phenotype. Loss of the ASIC1a channel in SCA1/ASIC1a KO mice resulted in the improvement of motor deficit and decreased PC degeneration. Interestingly, the expression of the ASIC1 variant, ASIC1b, was upregulated in the cerebellum of both SCA1/ASIC1a KO and ASIC1a KO animals as compared to the wild-type (WT) and SCA1 Tg mice. Further, these SCA1/ASIC1a KO mice exhibited translocation of PC calcium-binding protein calbindin-D28k from the nucleus to the cytosol in young animals, which otherwise have both cytosolic and nuclear localization. Furthermore, in addition to higher expression of calcium-buffering protein parvalbumin, PCs of the older SCA1/ASIC1a KO mice showed a decrease in morphologic abnormalities as compared to the age-matched SCA1 animals. Our data suggest that ASIC1a may be a mediator of SCA1 pathogenesis and targeting ASIC1a could be a novel approach to treat SCA1.

  20. Local ASIC3 modulates pain and disease progression in a rat model of osteoarthritis

    Directory of Open Access Journals (Sweden)

    Izumi Masashi

    2012-08-01

    Full Text Available Abstract Background Recent data have suggested a relationship between acute arthritic pain and acid sensing ion channel 3 (ASIC3 on primary afferent fibers innervating joints. The purpose of this study was to clarify the role of ASIC3 in a rat model of osteoarthritis (OA which is considered a degenerative rather than an inflammatory disease. Methods We induced OA via intra-articular mono-iodoacetate (MIA injection, and evaluated pain-related behaviors including weight bearing measured with an incapacitance tester and paw withdrawal threshold in a von Frey hair test, histology of affected knee joint, and immunohistochemistry of knee joint afferents. We also assessed the effect of ASIC3 selective peptide blocker (APETx2 on pain behavior, disease progression, and ASIC3 expression in knee joint afferents. Results OA rats showed not only weight-bearing pain but also mechanical hyperalgesia outside the knee joint (secondary hyperalgesia. ASIC3 expression in knee joint afferents was significantly upregulated approximately twofold at Day 14. Continuous intra-articular injections of APETx2 inhibited weight distribution asymmetry and secondary hyperalgesia by attenuating ASIC3 upregulation in knee joint afferents. Histology of ipsilateral knee joint showed APETx2 worked chondroprotectively if administered in the early, but not late phase. Conclusions Local ASIC3 immunoreactive nerve is strongly associated with weight-bearing pain and secondary hyperalgesia in MIA-induced OA model. APETx2 inhibited ASIC3 upregulation in knee joint afferents regardless of the time-point of administration. Furthermore, early administration of APETx2 prevented cartilage damage. APETx2 is a novel, promising drug for OA by relieving pain and inhibiting disease progression.

  1. ASIC3, an acid-sensing ion channel, is expressed in metaboreceptive sensory neurons

    Directory of Open Access Journals (Sweden)

    Fierro Leonardo

    2005-11-01

    Full Text Available Abstract Background ASIC3, the most sensitive of the acid-sensing ion channels, depolarizes certain rat sensory neurons when lactic acid appears in the extracellular medium. Two functions have been proposed for it: 1 ASIC3 might trigger ischemic pain in heart and muscle; 2 it might contribute to some forms of touch mechanosensation. Here, we used immunocytochemistry, retrograde labelling, and electrophysiology to ask whether the distribution of ASIC3 in rat sensory neurons is consistent with either of these hypotheses. Results Less than half (40% of dorsal root ganglion sensory neurons react with anti-ASIC3, and the population is heterogeneous. They vary widely in cell diameter and express different growth factor receptors: 68% express TrkA, the receptor for nerve growth factor, and 25% express TrkC, the NT3 growth factor receptor. Consistent with a role in muscle nociception, small ( Conclusion Our data indicates that: 1 ASIC3 is expressed in a restricted population of nociceptors and probably in some non-nociceptors; 2 co-expression of ASIC3 and CGRP, and the absence of P2X3, are distinguishing properties of a class of sensory neurons, some of which innervate blood vessels. We suggest that these latter afferents may be muscle metaboreceptors, neurons that sense the metabolic state of muscle and can trigger pain when there is insufficient oxygen.

  2. Design and performance of a custom ASIC digitizer for wire chamber readout in 65 nm CMOS technology

    Science.gov (United States)

    Lee, M. J.; Brown, D. N.; Chang, J. K.; Ding, D.; Gnani, D.; Grace, C. R.; Jones, J. A.; Kolomensky, Y. G.; von der Lippe, H.; Mcvittie, P. J.; Stettler, M. W.; Walder, J.-P.

    2015-06-01

    We present the design and performance of a prototype ASIC digitizer for integrated wire chamber readout, implemented in 65 nm commercial CMOS technology. Each channel of the 4-channel prototype is composed of two 16-bit Time-to-Digital Converters (TDCs), one 8-bit Analog-to-Digital Converter (ADC), a front-end preamplifier and shaper, plus digital and analog buffers that support a variety of digitization chains. The prototype has a multiplexed digital backend that executes a state machine, distributes control and timing signals, and buffers data for serial output. Laboratory bench tests measure the absolute TDC resolution between 74 ps and 480 ps, growing with the absolute delay, and a relative time resolution of 19 ps. Resolution outliers due to cross-talk between clock signals and supply or reference voltages are seen. After calibration, the ADC displays good linearity and noise performance, with an effective number of bits of 6.9. Under normal operating conditions the circuit consumes 32 mW per channel. Potential design improvements to address the resolution drift and tails are discussed.

  3. Design and Performance of a Custom ASIC Digitizer for Wire Chamber Readout in 65 nm CMOS Technology

    CERN Document Server

    Lee, MyeongJae; Chang, Jessica K; Ding, Dawei; Gnani, Dario; Grace, Carl R; Jones, John A; Kolomensky, Yury G; von der Lippe, Henrik; Mcvittie, Patrick J; Stettler, Matthew W; Walder, Jean-Pierre

    2015-01-01

    We present the design and performance of a prototype ASIC digitizer for integrated wire chamber readout, implemented in 65 nm commercial CMOS technology. Each channel of the 4-channel prototype is composed of two 16-bit Time-to-Digital Converters (TDCs), one 8-bit Analog-to-Digital Converter (ADC), a front-end preamplifier and shaper, plus digital and analog buffers that support a variety of digitization chains. The prototype has a multiplexed digital backend that executes a state machine, distributes control and timing signals, and buffers data for serial output. Laboratory bench tests measure the absolute TDC resolution between 74 ps and 480 ps, growing with the absolute delay, and a relative time resolution of 19 ps. Resolution outliers due to cross-talk between clock signals and supply or reference voltages are seen. After calibration, the ADC displays good linearity and noise performance, with an effective number of bits of 6.9. Under normal operating conditions the circuit consumes 32 mW per channel. Po...

  4. Development of low-noise high-speed analog ASIC for X-ray CCD cameras and wide-band X-ray imaging sensors

    Science.gov (United States)

    Nakajima, Hiroshi; Hirose, Shin-nosuke; Imatani, Ritsuko; Nagino, Ryo; Anabuki, Naohisa; Hayashida, Kiyoshi; Tsunemi, Hiroshi; Doty, John P.; Ikeda, Hirokazu; Kitamura, Hisashi; Uchihori, Yukio

    2016-09-01

    We report on the development and performance evaluation of the mixed-signal Application Specific Integrated Circuit (ASIC) developed for the signal processing of onboard X-ray CCD cameras and various types of X-ray imaging sensors in astrophysics. The quick and low-noise readout is essential for the pile-up free imaging spectroscopy with a future X-ray telescope. Our goal is the readout noise of 5e- r . m . s . at the pixel rate of 1 Mpix/s that is about 10 times faster than those of the currently working detectors. We successfully developed a low-noise ASIC as the front-end electronics of the Soft X-ray Imager onboard Hitomi that was launched on February 17, 2016. However, it has two analog-to-digital converters per chain due to the limited processing speed and hence we need to correct the difference of gain to obtain the X-ray spectra. Furthermore, its input equivalent noise performance is not satisfactory (> 100 μV) at the pixel rate higher than 500 kpix/s. Then we upgrade the design of the ASIC with the fourth-order ΔΣ modulators to enhance its inherent noise-shaping performance. Its performance is measured using pseudo CCD signals with variable processing speed. Although its input equivalent noise is comparable with the conventional one, the integrated non-linearity (0.1%) improves to about the half of that of the conventional one. The radiation tolerance is also measured with regard to the total ionizing dose effect and the single event latch-up using protons and Xenon, respectively. The former experiment shows that all of the performances does not change after imposing the dose corresponding to 590 years in a low earth orbit. We also put the upper limit on the frequency of the latch-up to be once per 48 years.

  5. Radiation hardness studies of the front-end ASICs for the optical links of the ATLAS semiconductor tracker

    CERN Document Server

    White, D J; Mahout, G; Jovanovic, P; Mandic, I; Weidberg, A R

    2001-01-01

    Studies have been performed on the effects of radiation on ASICs incorporating bipolar npn transistors in the AMS 0.8 mu m BiCMOS process. Radiation effects are reviewed and the approach used to achieve radiation tolerant ASICs is described. The radiation tests required to validate the ASICs for use in the ATLAS detector at the CERN Large Hadron Collider are discussed. The results demonstrate that they are sufficiently radiation tolerant for use in the ATLAS semiconductor tracker. (20 refs).

  6. FRONT-END ASIC FOR A SILICON COMPTON TELESCOPE.

    Energy Technology Data Exchange (ETDEWEB)

    DE GERONIMO,G.; FRIED, J.; FROST, E.; PHLIPS, B.; VERNON, E.; WULF, E.A.

    2007-10-27

    We describe a front-end application specific integrated circuit (ASIC) developed for a silicon Compton telescope. Composed of 32 channels, it reads out signals in both polarities from each side of a Silicon strip sensor, 2 mm thick 27 cm long, characterized by a strip capacitance of 30 pF. Each front-end channel provides low-noise charge amplification, shaping with a stabilized baseline, discrimination, and peak detection with an analog memory. The channels can process events simultaneously, and the read out is sparsified. The charge amplifier makes uses a dual-cascode configuration and dual-polarity adaptive reset, The low-hysteresis discriminator and the multi-phase peak detector process signals with a dynamic range in excess of four hundred. An equivalent noise charge (ENC) below 200 electrons was measured at 30 pF, with a slope of about 4.5 electrons/pF at a peaking time of 4 {micro}s. With a total dissipated power of 5 mW the channel covers an energy range up to 3.2 MeV.

  7. VeloPix ASIC development for LHCb VELO upgrade

    CERN Document Server

    van Beuzekom, M; Campbell, M; Collins, P; Gromov, V; Kluit, R; Llopart, X; Poikela, T; Wyllie, K; Zivkovic, V

    2013-01-01

    The upgrade of the LHCb experiment, planned for 2018, will transform the readout of the entire experiment to a triggerless system operating at 40 MHz. All data reduction algorithms will be run in a high level software farm, and will have access to event information from all subdetectors. This approach will give great power and fl exibility in accessing the physics channels of interest in the future, in particular the identi fi cation of fl avour tagged events with displaced vertices. The data acquisition and front end electronics systems require signi fi cant modi fi cation to cope with the enormous throughput of data. For the silicon vertex locator (VELO) a dedicated development is underway for a new ASIC, VeloPix, which will be a derivative of the Timepix/Medipix family of chips. The chip will be radiation hard and be able to cope with pixel hit rates of above 500 MHz, highly non-uniformly distributed over the 2 cm 2 chip area. The chip will incorporate local intelligence in the pixels for time-over-thresho...

  8. ASIC Readout Circuit Architecture for Large Geiger Photodiode Arrays

    Science.gov (United States)

    Vasile, Stefan; Lipson, Jerold

    2012-01-01

    The objective of this work was to develop a new class of readout integrated circuit (ROIC) arrays to be operated with Geiger avalanche photodiode (GPD) arrays, by integrating multiple functions at the pixel level (smart-pixel or active pixel technology) in 250-nm CMOS (complementary metal oxide semiconductor) processes. In order to pack a maximum of functions within a minimum pixel size, the ROIC array is a full, custom application-specific integrated circuit (ASIC) design using a mixed-signal CMOS process with compact primitive layout cells. The ROIC array was processed to allow assembly in bump-bonding technology with photon-counting infrared detector arrays into 3-D imaging cameras (LADAR). The ROIC architecture was designed to work with either common- anode Si GPD arrays or common-cathode InGaAs GPD arrays. The current ROIC pixel design is hardwired prior to processing one of the two GPD array configurations, and it has the provision to allow soft reconfiguration to either array (to be implemented into the next ROIC array generation). The ROIC pixel architecture implements the Geiger avalanche quenching, bias, reset, and time to digital conversion (TDC) functions in full-digital design, and uses time domain over-sampling (vernier) to allow high temporal resolution at low clock rates, increased data yield, and improved utilization of the laser beam.

  9. A time-based front-end ASIC for the silicon micro strip sensors of the bar PANDA Micro Vertex Detector

    Science.gov (United States)

    Di Pietro, V.; Brinkmann, K.-Th.; Riccardi, A.; Ritman, J.; Rivetti, A.; Rolo, M. D.; Stockmanns, T.; Zambanini, A.

    2016-03-01

    The bar PANDA (Antiproton Annihilation at Darmstadt) experiment foresees many detectors for tracking, particle identification and calorimetry. Among them, the innermost is the MVD (Micro Vertex Detector) responsible for a precise tracking and the reconstruction of secondary vertices. This detector will be built from both hybrid pixel (two inner barrels and six forward disks) and double-sided micro strip (two outer barrels and outer rim of the last two disks) silicon sensors. A time-based approach has been chosen for the readout ASIC of the strip sensors. The PASTA (bar PANDA Strip ASIC) chip aims at high resolution time-stamping and charge information through the Time over Threshold (ToT) technique. It benefits from a Time to Digital Converter (TDC) allowing a time bin width down to 50 ps. The analog front-end was designed to serve both n-type and p-type strips and the performed simulations show remarkable performances in terms of linearity and electronic noise. The TDC consists of an analog interpolator, a digital local controller, and a digital global controller as the common back-end for all of the 64 channels.

  10. Acid-sensing ion channels (ASICs: therapeutic targets for neurological diseases and their regulation

    Directory of Open Access Journals (Sweden)

    Hae-Jin Kweon

    2013-06-01

    Full Text Available Extracellular acidification occurs not only in pathologicalconditions such as inflammation and brain ischemia, but alsoin normal physiological conditions such as synaptic transmission.Acid-sensing ion channels (ASICs can detect a broadrange of physiological pH changes during pathological andsynaptic cellular activities. ASICs are voltage-independent,proton-gated cation channels widely expressed throughout thecentral and peripheral nervous system. Activation of ASICs isinvolved in pain perception, synaptic plasticity, learning andmemory, fear, ischemic neuronal injury, seizure termination,neuronal degeneration, and mechanosensation. Therefore,ASICs emerge as potential therapeutic targets for manipulatingpain and neurological diseases. The activity of these channelscan be regulated by many factors such as lactate, Zn2+, andPhe-Met-Arg-Phe amide (FMRFamide-like neuropeptides byinteracting with the channel’s large extracellular loop. ASICsare also modulated by G protein-coupled receptors such asCB1 cannabinoid receptors and 5-HT2. This review focuses onthe physiological roles of ASICs and the molecularmechanisms by which these channels are regulated. [BMBReports 2013; 46(6: 295-304

  11. ASIC3 Mediates Itch Sensation in Response to Coincident Stimulation by Acid and Nonproton Ligand

    Directory of Open Access Journals (Sweden)

    Zhong Peng

    2015-10-01

    Full Text Available The regulation and mechanisms underlying itch sensation are complex. Here, we report a role for acid-sensing ion channel 3 (ASIC3 in mediating itch evoked by certain pruritogens during tissue acidosis. Co-administration of acid with Ser-Leu-Ile-Gly-Arg-Leu-NH2 (SL-NH2 increased scratching behavior in wild-type, but not ASIC3-null, mice, implicating the channel in coincident detection of acidosis and pruritogens. Mechanistically, SL-NH2 slowed desensitization of proton-evoked currents by targeting the previously identified nonproton ligand-sensing domain located in the extracellular region of ASIC3 channels in primary sensory neurons. Ablation of the ASIC3 gene reduced dry-skin-induced scratching behavior and pathological changes under conditions with concomitant inflammation. Taken together, our data suggest that ASIC3 mediates itch sensation via coincident detection of acidosis and nonproton ligands that act at the nonproton ligand-sensing domain of the channel.

  12. Test beam analysis of ultra-thin hybrid pixel detector assemblies with Timepix readout ASICs

    CERN Document Server

    Alipour Tehrani, Niloufar; Dannheim, Dominik; Firu, Elena; Kulis, Szymon; Redford, Sophie; Sicking, Eva

    2016-01-01

    The requirements for the vertex detector at the proposed Compact Linear Collider imply a very small material budget: less than 0.2% of a radiation length per detection layer including services and mechanical supports. We present here a study using Timepix readout ASICs hybridised to pixel sensors of 50 − 500 μm thickness, including assemblies with 100 μm thick sensors bonded to thinned 100μm thick ASICs. Sensors from three producers (Advacam, Micron Semiconductor Ltd, Canberra) with different edge termination technologies (active edge, slim edge) were bonded to Timepix ASICs. These devices were characterised with the EUDET telescope at the DESY II test beam using 5.6 GeV electrons. Their performance for the detection and tracking of minimum ionising particles was evaluated in terms of charge sharing, detection efficiency, single-point resolution and energy deposition.

  13. A Low-Power ASIC Signal Processor for a Vestibular Prosthesis.

    Science.gov (United States)

    Töreyin, Hakan; Bhatti, Pamela T

    2016-06-01

    A low-power ASIC signal processor for a vestibular prosthesis (VP) is reported. Fabricated with TI 0.35 μm CMOS technology and designed to interface with implanted inertial sensors, the digitally assisted analog signal processor operates extensively in the CMOS subthreshold region. During its operation the ASIC encodes head motion signals captured by the inertial sensors as electrical pulses ultimately targeted for in-vivo stimulation of vestibular nerve fibers. To achieve this, the ASIC implements a coordinate system transformation to correct for misalignment between natural sensors and implanted inertial sensors. It also mimics the frequency response characteristics and frequency encoding mappings of angular and linear head motions observed at the peripheral sense organs, semicircular canals and otolith. Overall the design occupies an area of 6.22 mm (2) and consumes 1.24 mW when supplied with ± 1.6 V.

  14. Application specific integrated circuit (ASIC) readout technologies for future ion beam analytical instruments

    Energy Technology Data Exchange (ETDEWEB)

    Whitlow, Harry J. E-mail: harry_j.whitlow@nuclear.lu.se

    2000-03-01

    New possibilities for ion beam analysis (IBA) are afforded by recent developments in detector technology which facilitate the parallel collection of data from a large number of channels. Application specific integrated circuit (ASIC) technologies, which have been widely employed for multi-channel readout systems in nuclear and particle physics, are more net-cost effective (160/channel for 1000 channels) and a more rational solution for readout of a large number of channels than afforded by conventional electronics. Based on results from existing and on-going chip designs, the possibilities and issues of ASIC readout technology are considered from the IBA viewpoint. Consideration is given to readout chip architecture and how the stringent resolution, linearity and stability requirements for IBA may be met. In addition the implications of the restrictions imposed by ASIC technology are discussed.

  15. Atomic force microscopy imaging reveals the formation of ASIC/ENaC cross-clade ion channels

    Energy Technology Data Exchange (ETDEWEB)

    Jeggle, Pia; Smith, Ewan St. J.; Stewart, Andrew P. [Department of Pharmacology, University of Cambridge, Tennis Court Road, Cambridge CB2 1PD (United Kingdom); Haerteis, Silke; Korbmacher, Christoph [Institut für Zelluläre und Molekulare Physiologie, Friedrich-Alexander-Universität Erlangen-Nürnberg, Waldstrasse 6, 91054 Erlangen (Germany); Edwardson, J. Michael, E-mail: jme1000@cam.ac.uk [Department of Pharmacology, University of Cambridge, Tennis Court Road, Cambridge CB2 1PD (United Kingdom)

    2015-08-14

    ASIC and ENaC are co-expressed in various cell types, and there is evidence for a close association between them. Here, we used atomic force microscopy (AFM) to determine whether ASIC1a and ENaC subunits are able to form cross-clade hybrid ion channels. ASIC1a and ENaC could be co-isolated from detergent extracts of tsA 201 cells co-expressing the two subunits. Isolated proteins were incubated with antibodies against ENaC and Fab fragments against ASIC1a. AFM imaging revealed proteins that were decorated by both an antibody and a Fab fragment with an angle of ∼120° between them, indicating the formation of ASIC1a/ENaC heterotrimers. - Highlights: • There is evidence for a close association between ASIC and ENaC. • We used AFM to test whether ASIC1a and ENaC subunits form cross-clade ion channels. • Isolated proteins were incubated with subunit-specific antibodies and Fab fragments. • Some proteins were doubly decorated at ∼120° by an antibody and a Fab fragment. • Our results indicate the formation of ASIC1a/ENaC heterotrimers.

  16. Wavelength converter technology

    DEFF Research Database (Denmark)

    Kloch, Allan; Hansen, Peter Bukhave; Poulsen, Henrik Nørskov;

    1999-01-01

    Wavelength conversion is important since it ensures full flexibility of the WDM network layer. Progress in optical wavelength converter technology is reviewed with emphasis on all-optical wavelength converter types based on semiconductor optical amplifiers....

  17. Wavelength converter technology

    DEFF Research Database (Denmark)

    Kloch, Allan; Hansen, Peter Bukhave; Poulsen, Henrik Nørskov;

    1999-01-01

    Wavelength conversion is important since it ensures full flexibility of the WDM network layer. Progress in optical wavelength converter technology is reviewed with emphasis on air-optical wavelength converter types based on semiconductor optical amplifiers....

  18. Power Converters for Accelerators

    CERN Document Server

    Visintini, R

    2015-01-01

    Particle accelerators use a great variety of power converters for energizing their sub-systems; while the total number of power converters usually depends on the size of the accelerator or combination of accelerators (including the experimental setup), the characteristics of power converters depend on their loads and on the particle physics requirements: this paper aims to provide an overview of the magnet power converters in use in several facilities worldwide.

  19. Technologies for converter topologies

    Energy Technology Data Exchange (ETDEWEB)

    Zhou, Yan; Zhang, Haiyu

    2017-02-28

    In some embodiments of the disclosed inverter topologies, an inverter may include a full bridge LLC resonant converter, a first boost converter, and a second boost converter. In such embodiments, the first and second boost converters operate in an interleaved manner. In other disclosed embodiments, the inverter may include a half-bridge inverter circuit, a resonant circuit, a capacitor divider circuit, and a transformer.

  20. A front-end ASIC design for non-uniformity correction

    Science.gov (United States)

    Shen, X.; Ding, R. J.; Lin, J. M.; Liu, F.

    2008-12-01

    A front-end design of an ASIC that implements calibration and correction for IRFPA non-uniformity is presented. An algorithm suitable for ASIC implementation is introduced, and one kind of architecture that implements this algorithm has been designed. We map the architecture to TSMC 0.25um process. After evaluating the chip area and operation speed, we confirm that this architect will also be effective when the FPA scale in enlarged to 1Kby1K. Finally the flow of circuit implementation and method of verification are introduced briefly.

  1. Integrated input protection against discharges for Micro Pattern Gas Detectors readout ASICs

    Science.gov (United States)

    Fiutowski, T.; Dąbrowski, W.; Koperny, S.; Wiącek, P.

    2017-02-01

    Immunity against possible random discharges inside active detector volume of MPGDs is one of the key aspects that should be addressed in the design of the front-end electronics. This issue becomes particularly critical for systems with high channel counts and high density readout employing the front-end electronics built as multichannel ASICs implemented in modern CMOS technologies, for which the breakdown voltages are in the range of a few Volts. The paper presents the design of various input protection structures integrated in the ASIC manufactured in a 350 nm CMOS process and test results using an electrical circuit to mimic discharges in the detectors.

  2. Development and experimental study of the readout ASIC for muon chambers of the CBM experiment

    Science.gov (United States)

    Atkin, E.; Ivanov, V.; Ivanov, P.; Khanzadeev, A.; Malankin, E.; Normanov, D.; Roshchin, E.; Samsonov, V.; Shumikhin, V.; Voronin, A.

    2016-01-01

    The measurement results of the front-end ASIC for the GEM detector read-out are presented. The MUCH ASIC v2 was designed and prototyped via Europractice by means of the 0.18 um CMOS MMRF process of UMC (Taiwan). The parameters of the analog channels, including the CSA, fast and slow shapers, discriminators, were measured. The channels provide a sufficient dynamic range of 100 fC, low power consumption of 10 mW per channel and ENC of 1550 el at a 50 pF detector capacitance.

  3. The GBT-SCA, a radiation tolerant ASIC for detector control applications in SLHC experiments

    CERN Document Server

    Gabrielli, A; Kloukinas, K; Marchioro, A; Moreira, P; Ranieri, A; De Robertis, D

    2009-01-01

    This work describes the architecture of the GigaBit Transceiver – Slow Control Adapter (GBT–SCA) ASIC suitable for the control and monitoring applications of the embedded front-end electronics in the future SLHC experiments. The GBT–SCA is part the GBT chipset currently under development for the SLHC detector upgrades. It is designed for radiation tolerance and it will be fabricated in a commercial 130 nm CMOS technology. The paper discusses the GBT-SCA architecture, the data transfer protocol, the ASIC interfaces, and its integration with the GBT optical link. The GBT–SCA is one the components of the GBT system chipset. It is proposed for the future SLHC experiments and is designed to be configurable matching different front-end system requirements. The GBT-SCA is intended for the slow control and monitoring of the embedded front end electronics and implements a point-to-multi point connection between one GBT optical link ASIC and several front end ASICs. The GBT-SCA connects to a dedicated electrica...

  4. MULTICHANNEL ENERGY AND TIMING MEASUREMENTS WITH THE PEAK DETECTOR/DERANDOMIZER ASIC.

    Energy Technology Data Exchange (ETDEWEB)

    O' CONNOR,P.; DE GERONIMO,G.; GROSHOLZ,J.; KANDASAMY,A.; JUNNARKAR,S.; FRIED,J.

    2004-10-16

    The Peak Detector/Derandomizer ASIC (PDD) provides threshold discrimination, peak detection, time-to-amplitude conversion, analog memory, sparsification, and multiplexing for 32 channels of analog pulse data. In this work the spectroscopic capabilities of the chip (high resolution and high rate) are demonstrated along with correlated measurements of pulse risetime. Imaging and coincidence detection using the PDD chip will also be illustrated.

  5. A DES ASIC Suitable for Network Encryption at 10 Gbps and Beyond

    Energy Technology Data Exchange (ETDEWEB)

    Gass, Karl; Pierson, Lyndon G.; Robertson, Perry J.; Wilcox, D. Craig; Witzke, Edward L.

    1999-04-30

    The Sandia National Laboratories (SNL) Data Encryption Standard (DES) Application Specific Integrated Circuit (ASIC) is the fastest known implementation of the DES algorithm as defined in the Federal Information Processing Standards (FIPS) Publication 46-2. DES is used for protecting data by cryptographic means. The SNL DES ASIC, over 10 times faster than other currently available DES chips, is a high-speed, filly pipelined implementation offering encryption, decryption, unique key input, or algorithm bypassing on each clock cycle. Operating beyond 105 MHz on 64 bit words, this device is capable of data throughputs greater than 6.7 Billion bits per second (tester limited). Simulations predict proper operation up to 9.28 Billion bits per second. In low frequency, low data rate applications, the ASIC consumes less that one milliwatt of power. The device has features for passing control signals synchronized to throughput data. Three SNL DES ASICS may be easily cascaded to provide the much greater security of triple-key, triple-DES.

  6. FRONT-END ASIC FOR HIGH RESOLUTION X-RAY SPECTROMETERS.

    Energy Technology Data Exchange (ETDEWEB)

    DE GERONIMO,G.; CHEN, W.; FRIED, J.; LI, Z.; PINELLI, D.A.; REHAK, P.; VERNON, E.; GASKIN, J.A.; RAMSEY, B.D.; ANELLI, G.

    2007-10-27

    We present an application specific integrated circuit (ASIC) for high-resolution x-ray spectrometers. The ASIC is designed to read out signals from a pixelated silicon drift detector (SDD). Each hexagonal pixel has an area of 15 mmz and an anode capacitance of less than 100 fF. There is no integrated Field Effect transistor (FET) in the pixel, rather, the readout is done by wirebonding the anodes to the inputs of the ASIC. The ASIC provides 14 channels of low-noise charge amplification, high-order shaping with baseline stabilization, and peak detection with analog memory. The readout is sparse and based on low voltage differential signaling. An interposer provides all the interconnections required to bias and operate the system. The channel dissipates 1.6 mW. The complete 14-pixel unit covers an area of 210 mm{sup 2}, dissipates 12 mW cm{sup -2}, and can be tiled to cover an arbitrarily large detection area. We measured a preliminary resolution of 172 eV at -35 C on the 6 keV peak of a {sup 55}Fe source.

  7. A Prototype PZT Matrix Transducer With Low-Power Integrated Receive ASIC for 3-D Transesophageal Echocardiography.

    Science.gov (United States)

    Chen, Chao; Raghunathan, Shreyas B; Yu, Zili; Shabanimotlagh, Maysam; Chen, Zhao; Chang, Zu-yao; Blaak, Sandra; Prins, Christian; Ponte, Jacco; Noothout, Emile; Vos, Hendrik J; Bosch, Johan G; Verweij, Martin D; de Jong, Nico; Pertijs, Michiel A P

    2016-01-01

    This paper presents the design, fabrication, and experimental evaluation of a prototype lead zirconium titanate (PZT) matrix transducer with an integrated receive ASIC, as a proof of concept for a miniature three-dimensional (3-D) transesophageal echocardiography (TEE) probe. It consists of an array of 9 ×12 piezoelectric elements mounted on the ASIC via an integration scheme that involves direct electrical connections between a bond-pad array on the ASIC and the transducer elements. The ASIC addresses the critical challenge of reducing cable count, and includes front-end amplifiers with adjustable gains and micro-beamformer circuits that locally process and combine echo signals received by the elements of each 3 ×3 subarray. Thus, an order-of-magnitude reduction in the number of receive channels is achieved. Dedicated circuit techniques are employed to meet the strict space and power constraints of TEE probes. The ASIC has been fabricated in a standard 0.18-μm CMOS process and consumes only 0.44 mW/channel. The prototype has been acoustically characterized in a water tank. The ASIC allows the array to be presteered across ±37° while achieving an overall dynamic range of 77 dB. Both the measured characteristics of the individual transducer elements and the performance of the ASIC are in good agreement with expectations, demonstrating the effectiveness of the proposed techniques.

  8. Design of a video capsule endoscopy system with low-power ASIC for monitoring gastrointestinal tract.

    Science.gov (United States)

    Liu, Gang; Yan, Guozheng; Zhu, Bingquan; Lu, Li

    2016-11-01

    In recent years, wireless capsule endoscopy (WCE) has been a state-of-the-art tool to examine disorders of the human gastrointestinal tract painlessly. However, system miniaturization, enhancement of the image-data transfer rate and power consumption reduction for the capsule are still key challenges. In this paper, a video capsule endoscopy system with a low-power controlling and processing application-specific integrated circuit (ASIC) is designed and fabricated. In the design, these challenges are resolved by employing a microimage sensor, a novel radio frequency transmitter with an on-off keying modulation rate of 20 Mbps, and an ASIC structure that includes a clock management module, a power-efficient image compression module and a power management unit. An ASIC-based prototype capsule, which measures Φ11 mm × 25 mm, has been developed here. Test results show that the designed ASIC consumes much less power than most of the other WCE systems and that its total power consumption per frame is the least. The image compression module can realize high near-lossless compression rate (3.69) and high image quality (46.2 dB). The proposed system supports multi-spectral imaging, including white light imaging and autofluorescence imaging, at a maximum frame rate of 24 fps and with a resolution of 400 × 400. Tests and in vivo trials in pigs have proved the feasibility of the entire system, but further improvements in capsule control and compression performance inside the ASIC are needed in the future.

  9. The photoelectric displacement converter

    Science.gov (United States)

    Dragoner, Valeriu V.

    2005-02-01

    In the article are examined questions of constructing photoelectric displacement converter satisfying demands that are stated above. Converter has channels of approximate and precise readings. The approximate reading may be accomplished either by the method of reading from a code mask or by the method of the consecutive calculation of optical scale gaps number. Phase interpolator of mouar strips" gaps is determined as a precise measuring. It is shown mathematical model of converter that allow evaluating errors and operating speed of conversion.

  10. Low-power digital ASIC for on-chip spectral analysis of low-frequency physiological signals

    Institute of Scientific and Technical Information of China (English)

    Nie Zedong; Zhang Fengjuan; Li Jie; Wang Lei

    2012-01-01

    A digital ASIC chip customized for battery-operated body sensing devices is presented.The ASIC incorporates a novel hybrid-architecture fast Fourier transform (FFT) unit that is capable of scalable spectral analysis,a licensed ARM7TDMI IP hardcore and several peripheral IP blocks.Extensive experimental results suggest that the complete chip works as intended.The power consumption of the FFT unit is 0.69 mW @ 1 MHz with 1.8 V power supply.The low-power and programmable features of the ASIC make it suitable for ‘on-the-fly' low-frequency physiological signal processing.

  11. Development and validation of a 64 channel front end ASIC for 3D directional detection with MIMAC

    CERN Document Server

    Richer, J P; Bosson, G; Guillaudin, O; Mayet, F; Santos, D

    2011-01-01

    A front end ASIC has been designed to equip the {\\mu}TPC prototype developed for the MIMAC project, which requires 3D reconstruction of low energy particle tracks in order to perform directional detection of galactic Dark Matter. Each ASIC is able to monitor 64 strips of pixels and provides the "Time Over Threshold" information for each of those. These 64 digital informations, sampled at a rate of 50 MHz, can be transferred at 400MHz by eight LVDS serial links. Eight ASIC were validated on a 2x256 strips of pixels prototype.

  12. Plasmon-assisted optical vias for photonic ASICS

    Energy Technology Data Exchange (ETDEWEB)

    Skogen, Erik J.; Vawter, Gregory A.; Tauke-Pedretti, Anna

    2017-03-21

    The present invention relates to optical vias to optically connect multilevel optical circuits. In one example, the optical via includes a surface plasmon polariton waveguide, and a first optical waveguide formed on a first substrate is coupled to a second optical waveguide formed on a second substrate by the surface plasmon polariton waveguide. In some embodiments, the first optical waveguide includes a transition region configured to convert light from an optical mode to a surface plasmon polariton mode or from a surface plasmon polariton mode to an optical mode.

  13. High speed data converters

    CERN Document Server

    Ali, Ahmed MA

    2016-01-01

    This book covers high speed data converters from the perspective of a leading high speed ADC designer and architect, with a strong emphasis on high speed Nyquist A/D converters. For our purposes, the term 'high speed' is defined as sampling rates that are greater than 10 MS/s.

  14. Electrical Power Converter

    NARCIS (Netherlands)

    Ferreira, J.A.

    2014-01-01

    Electrical power converter for converting electrical power of a power source connected or connectable at an input to electrical DC-power at an output, wherein between the input and the output a first circuit of submodules is provided, wherein said first circuit of submodules and the power source for

  15. Cascaded resonant bridge converters

    Science.gov (United States)

    Stuart, Thomas A. (Inventor)

    1989-01-01

    A converter for converting a low voltage direct current power source to a higher voltage, high frequency alternating current output for use in an electrical system where it is desired to use low weight cables and other circuit elements. The converter has a first stage series resonant (Schwarz) converter which converts the direct current power source to an alternating current by means of switching elements that are operated by a variable frequency voltage regulator, a transformer to step up the voltage of the alternating current, and a rectifier bridge to convert the alternating current to a direct current first stage output. The converter further has a second stage series resonant (Schwarz) converter which is connected in series to the first stage converter to receive its direct current output and convert it to a second stage high frequency alternating current output by means of switching elements that are operated by a fixed frequency oscillator. The voltage of the second stage output is controlled at a relatively constant value by controlling the first stage output voltage, which is accomplished by controlling the frequency of the first stage variable frequency voltage controller in response to second stage voltage. Fault tolerance in the event of a load short circuit is provided by making the operation of the first stage variable frequency voltage controller responsive to first and second stage current limiting devices. The second stage output is connected to a rectifier bridge whose output is connected to the input of the second stage to provide good regulation of output voltage wave form at low system loads.

  16. Targeting ASIC1 in primary progressive multiple sclerosis: evidence of neuroprotection with amiloride.

    Science.gov (United States)

    Arun, Tarunya; Tomassini, Valentina; Sbardella, Emilia; de Ruiter, Michiel B; Matthews, Lucy; Leite, Maria Isabel; Gelineau-Morel, Rose; Cavey, Ana; Vergo, Sandra; Craner, Matt; Fugger, Lars; Rovira, Alex; Jenkinson, Mark; Palace, Jacqueline

    2013-01-01

    Neurodegeneration is the main cause for permanent disability in multiple sclerosis. The effect of current immunomodulatory treatments on neurodegeneration is insufficient. Therefore, direct neuroprotection and myeloprotection remain an important therapeutic goal. Targeting acid-sensing ion channel 1 (encoded by the ASIC1 gene), which contributes to the excessive intracellular accumulation of injurious Na(+) and Ca(2+) and is over-expressed in acute multiple sclerosis lesions, appears to be a viable strategy to limit cellular injury that is the substrate of neurodegeneration. While blockade of ASIC1 through amiloride, a potassium sparing diuretic that is currently licensed for hypertension and congestive cardiac failure, showed neuroprotective and myeloprotective effects in experimental models of multiple sclerosis, this strategy remains untested in patients with multiple sclerosis. In this translational study, we tested the neuroprotective effects of amiloride in patients with primary progressive multiple sclerosis. First, we assessed ASIC1 expression in chronic brain lesions from post-mortem of patients with progressive multiple sclerosis to identify the target process for neuroprotection. Second, we tested the neuroprotective effect of amiloride in a cohort of 14 patients with primary progressive multiple sclerosis using magnetic resonance imaging markers of neurodegeneration as outcome measures of neuroprotection. Patients with primary progressive multiple sclerosis underwent serial magnetic resonance imaging scans before (pretreatment phase) and during (treatment phase) amiloride treatment for a period of 3 years. Whole-brain volume and tissue integrity were measured with high-resolution T(1)-weighted and diffusion tensor imaging. In chronic brain lesions of patients with progressive multiple sclerosis, we demonstrate an increased expression of ASIC1 in axons and an association with injury markers within chronic inactive lesions. In patients with primary

  17. Development of a flight qualified 100 x 100 mm MCP UV detector using advanced cross strip anodes and associated ASIC electronics

    Science.gov (United States)

    Vallerga, John; McPhate, Jason; Tremsin, Anton; Siegmund, Oswald; Raffanti, Rick; Cumming, Harley; Seljak, Andrej; Virta, Vihtori; Varner, Gary

    2016-07-01

    Photon counting microchannel plate (MCP) imagers have been the detector of choice for most UV astronomical missions over the last three decades (e.g. EUVE, FUSE, COS on Hubble etc.) and been mentioned for instruments on future large telescopes in space such as LUVOIR14. Using cross strip anodes, improvements in the MCP laboratory readout technology have resulted in better spatial resolution (x10), temporal resolution (x 1000) and output event rate (x100), all the while operating at lower gain (x10) resulting in lower high voltage requirements and longer MCP lifetimes. A crossed strip anode MCP readout starts with a set of orthogonal conducting strips (e.g. 80 x 80), typically spaced at a 635 micron pitch onto which charge clouds from MCP amplified events land. Each strip has its own charge sensitive amplifier that is sampled continuously by a dedicated analog to digital converter (ADC). All of the ADC digital output lines are fed into a field programmable gate array (FGPA) which can detect charge events landing on the strips, measure the peak amplitudes of those charge events and calculate their spatial centroid along with their time of arrival (X,Y,T) and pass this information to a downstream computer. Laboratory versions of these electronics have demonstrated < 20 microns FWHM spatial resolution, count rates on the order of 2 MHz, and temporal resolution of 1ns. In 2012 our group at U.C. Berkeley, along with our partners at the U. Hawaii, received a NASA Strategic Astrophysics Technology (SAT) grant to raise the TRL of a cross strip detector from 4 to 6 by replacing most of the 19" rack mounted, high powered electronics with application specific integrated circuits (ASICs) which will lower the power, mass, and volume requirements of the detector electronics. We were also tasked to design and fabricate a "standard" 50mm square active area MCP detector incorporating these electronics that can be environmentally qualified for flight (temperature, vacuum, vibration

  18. Differential regulation of proton-sensitive ion channels by phospholipids: a comparative study between ASICs and TRPV1.

    Directory of Open Access Journals (Sweden)

    Hae-Jin Kweon

    Full Text Available Protons are released in pain-generating pathological conditions such as inflammation, ischemic stroke, infection, and cancer. During normal synaptic activities, protons are thought to play a role in neurotransmission processes. Acid-sensing ion channels (ASICs are typical proton sensors in the central nervous system (CNS and the peripheral nervous system (PNS. In addition to ASICs, capsaicin- and heat-activated transient receptor potential vanilloid 1 (TRPV1 channels can also mediate proton-mediated pain signaling. In spite of their importance in perception of pH fluctuations, the regulatory mechanisms of these proton-sensitive ion channels still need to be further investigated. Here, we compared regulation of ASICs and TRPV1 by membrane phosphoinositides, which are general cofactors of many receptors and ion channels. We observed that ASICs do not require membrane phosphatidylinositol 4-phosphate (PI(4P or phosphatidylinositol 4,5-bisphosphate (PI(4,5P2 for their function. However, TRPV1 currents were inhibited by simultaneous breakdown of PI(4P and PI(4,5P2. By using a novel chimeric protein, CF-PTEN, that can specifically dephosphorylate at the D3 position of phosphatidylinositol 3,4,5-trisphosphate (PI(3,4,5P3, we also observed that neither ASICs nor TRPV1 activities were altered by depletion of PI(3,4,5P3 in intact cells. Finally, we compared the effects of arachidonic acid (AA on two proton-sensitive ion channels. We observed that AA potentiates the currents of both ASICs and TRPV1, but that they have different recovery aspects. In conclusion, ASICs and TRPV1 have different sensitivities toward membrane phospholipids, such as PI(4P, PI(4,5P2, and AA, although they have common roles as proton sensors. Further investigation about the complementary roles and respective contributions of ASICs and TRPV1 in proton-mediated signaling is necessary.

  19. FROST: a low-noise high-rate photon counting ASIC for X-ray applications

    Energy Technology Data Exchange (ETDEWEB)

    Prest, M. E-mail: prest@ts.infn.it; Vallazza, E.; Chiavacci, M.; Mariani, R.; Motto, S.; Neri, M.; Scantamburlo, N.; Arfelli, F.; Conighi, A.; Longo, R.; Olivo, A.; Pani, S.; Poropat, P.; Rashevsky, A.; Rigon, L.; Tromba, G.; Castelli, E

    2001-04-01

    FRONTier RADiography is an R and D project to assess the feasibility of digital mammography with Synchrotron Radiation at the ELETTRA Light Source in Trieste. In order to reach an acceptable time duration of the exam, a fast- and low-noise photon counting ASIC has been developed in collaboration with Aurelia Microelettronica, called Frontrad ReadOut SysTem. It is a multichannel counting system, each channel being made of a low-noise charge-sensitive preamplifier optimized for X-ray energy range (10-100 keV), a CR-RC{sup 2} shaper, a discriminator and a 16-bit counter. In order to set the discriminator threshold, a set of a global 6-bit DAC and a local (per channel) 3-bit DAC has been implemented within the ASIC. We report on the measurements done with the 8-channel prototype chip and the comparison with the simulation results.

  20. ENC Measurement for ASIC Preamp Board as a Detector Module for PET System

    Directory of Open Access Journals (Sweden)

    N. Nagara

    2016-08-01

    Full Text Available We developed a gamma ray detector with an LuAG:Pr scintillator and an avalanche photodiode as a detector for a positron emission tomography (PET system. Studies have been performed on the influences of gamma irradiation on application-specific integrated circuit (ASIC preamp boards used as a detector module. As a device used in nuclear environments for substantial durations, the ASIC has to have a lifetime long enough to ensure that there will be a negligible failure rate during this period. These front-end systems must meet the requirements for standard positron emission tomography (PET systems. Therefore, an equivalent noise charge (ENC experiment is needed to measure the front-end system's characteristics. This study showed that minimum ENC conditions can be achieved if a shorter shaping time could be applied.

  1. Comparative Analysis of ALU Implementation with RCA and Sklansky Adders In ASIC Design Flow

    Directory of Open Access Journals (Sweden)

    Abdul Rehman Buzdar

    2016-07-01

    Full Text Available An Arithmetic Logic Unit (ALU is the heart of every central processing unit (CPU which performs basic operations like addition, subtraction, multiplication, division and bitwise logic operations on binary numbers. This paper deals with implementation of a basic ALU unit using two different types of adder circuits, a ripple carry adder and a sklansky type adder. The ALU is designed using application specific integrated circuit (ASIC platform where VHDL hardware description language and standard cells are used. The target process technology is 130nm CMOS from the foundry ST Microelectronics. The Cadence EDA tools are used for the ASIC implementation. A comparative analysis is provided for the two ALU circuits designed in terms of area, power and timing requirements.

  2. Irradiation of the CLARO-CMOS chip, a fast ASIC for single-photon counting

    Energy Technology Data Exchange (ETDEWEB)

    Andreotti, M.; Baldini, W.; Calabrese, R. [Università degli Studi di Ferrara and INFN Sezione di Ferrara (Italy); Carniti, P.; Cassina, L. [Università degli Studi di Milano Bicocca and INFN Sezione di Milano Bicocca (Italy); Cotta Ramusino, A. [Università degli Studi di Ferrara and INFN Sezione di Ferrara (Italy); Fiorini, M., E-mail: fiorini@fe.infn.it [Università degli Studi di Ferrara and INFN Sezione di Ferrara (Italy); Giachero, A.; Gotti, C. [Università degli Studi di Milano Bicocca and INFN Sezione di Milano Bicocca (Italy); Luppi, E. [Università degli Studi di Ferrara and INFN Sezione di Ferrara (Italy); Maino, M. [Università degli Studi di Milano Bicocca and INFN Sezione di Milano Bicocca (Italy); Malaguti, R. [Università degli Studi di Ferrara and INFN Sezione di Ferrara (Italy); Pessina, G. [Università degli Studi di Milano Bicocca and INFN Sezione di Milano Bicocca (Italy); Tomassetti, L. [Università degli Studi di Ferrara and INFN Sezione di Ferrara (Italy)

    2015-07-01

    The CLARO-CMOS is a prototype ASIC that allows fast photon counting with low power consumption, built in AMS 0.35 μm CMOS technology. It is intended to be used as a front-end readout for the upgraded LHCb RICH detectors. In this environment, assuming 10 years of operation at the nominal luminosity expected after the upgrade, the ASIC must withstand a total fluence of about 6×10{sup 12} 1 MeV n{sub eq}/cm{sup 2} and a total ionising dose of 400 krad. Long term stability of the electronics front-end is essential and the effects of radiation damage on the CLARO-CMOS performance must be carefully studied. This paper describes results of multi-step irradiation tests with protons up to the dose of ~8 Mrad, including measurement of single event effects during irradiation and chip performance evaluation before and after each irradiation step.

  3. ASICs in nanometer and 3D technologies for readout of hybrid pixel detectors

    Science.gov (United States)

    Maj, Piotr; Grybos, Pawel; Kmon, Piotr; Szczygiel, Robert

    2013-07-01

    Hybrid pixel detectors working in a single photon counting mode are very attractive solutions for material science and medical X-ray imaging applications. Readout electronics of these detectors has to match the geometry of pixel detectors with an area of readout channel of 100 μm × 100 μm (or even less) and very small power consumption (a few tens of μW). New solutions of readout ASICs are going into directions of better spatial resolutions, higher data throughput and more advanced functionality. We report on the design and measurement results of two pixel prototype ASICs in nanometer technology and 3D technology which offer fast signal processing, low noise performance and advanced functionality per single readout pixel cell.

  4. Irradiation of the CLARO-CMOS chip, a fast ASIC for single-photon counting

    Science.gov (United States)

    Andreotti, M.; Baldini, W.; Calabrese, R.; Carniti, P.; Cassina, L.; Cotta Ramusino, A.; Fiorini, M.; Giachero, A.; Gotti, C.; Luppi, E.; Maino, M.; Malaguti, R.; Pessina, G.; Tomassetti, L.

    2015-07-01

    The CLARO-CMOS is a prototype ASIC that allows fast photon counting with low power consumption, built in AMS 0.35 μm CMOS technology. It is intended to be used as a front-end readout for the upgraded LHCb RICH detectors. In this environment, assuming 10 years of operation at the nominal luminosity expected after the upgrade, the ASIC must withstand a total fluence of about 6×1012 1 MeV neq/cm2 and a total ionising dose of 400 krad. Long term stability of the electronics front-end is essential and the effects of radiation damage on the CLARO-CMOS performance must be carefully studied. This paper describes results of multi-step irradiation tests with protons up to the dose of ~8 Mrad, including measurement of single event effects during irradiation and chip performance evaluation before and after each irradiation step.

  5. System-level considerations for the front-end readout ASIC in the CBM experiment from the power supply perspective

    Science.gov (United States)

    Kasinski, K.; Koczon, P.; Ayet, S.; Löchner, S.; Schmidt, C. J.

    2017-03-01

    New fixed target experiments using high intensity beams with energy up to 10 AGeV from the SIS100 synchrotron presently being constructed at FAIR/GSI are under preparation. Most of the readout electronics and power supplies are expected to be exposed to a very high flux of nuclear reaction products and have to be radiation tolerant up to 3 MRad (TID) and sustain up to 1014/cm2 of 1 MeV neutron equivalent in their life time. Moreover, the mostly minimum ionising particles under investigation leave very little signal in the sensors. Therefore very low noise level amplitude measurements are required by the front-end electronics for effective tracking. Sensor and interconnecting micro-cable capacitance and series resistance in conjunction with intrinsic noise of the charge sensitive amplifier are dominant noise sources in the system. However, the single-ended architecture of the amplifiers employed for the charge processing channels implies a potential problem with noise contributions from power supply sources. Strict system-level constraints leave very little freedom in selecting a power supply structure optimal with respect to: power efficiency, cooling capabilities and power density on modules, but also noise injection to the front-end via the power supply lines. Design of the power supply and distribution system of the Silicon Tracking System in the CBM experiment together with details on the front-end ASICs (STS -XYTER2) and measurement results of power supply and conditioning electronics (selected DC/DC converter and LDO regulators) are presented.

  6. MATRIX: a 15 ps resistive interpolation TDC ASIC based on a novel regular structure

    Science.gov (United States)

    Mauricio, J.; Gascón, D.; Ciaglia, D.; Gómez, S.; Fernández, G.; Sanuy, A.

    2016-12-01

    This paper presents a 4-channel TDC ASIC with the following features: 15-ps LSB (9.34 ps after calibration), 10-ps jitter, commercial 180 nm technology. The main contribution of this work is the novel design of the clock interpolation circuitry based on a resistive interpolation mesh circuit (patented), a two-dimensional regular structure with very good properties in terms of power consumption, area and low process variability.

  7. Low noise DC to DC converters for the sLHC experiments

    Energy Technology Data Exchange (ETDEWEB)

    Allongue, B; Blanchot, G; Faccio, F; Fuentes, C; Michelis, S; Orlandi, S, E-mail: georges.blanchot@cern.c [CERN, Route de Meyrin, CH-1211 Geneva 23 (Switzerland)

    2010-11-15

    The development of front-end systems for the ATLAS tracker at the sLHC is now in progress and the availability of radiation tolerant buck converter ASICs enables the implementation of DC to DC converter based powering schemes. The front-end systems powered in this manner will be exposed to the radiated and conducted noise emitted by the converters. The electromagnetic compatibility between DC to DC converters and ATLAS short strip tracker hybrid prototypes has been studied with specific susceptibility tests. Different DC to DC converter prototypes have been designed following a noise optimization methodology to match the noise requirements of these front-end systems. The DC to DC converter developed in this manner presents a negligible emission of noise that was confirmed by system tests on an ATLAS tracker front-end module prototype. As a result of this, power converters can now be integrated in close vicinity of front-end chips without compromising their overall noise performance.

  8. Converting Nonclassicality into Entanglement

    Science.gov (United States)

    Killoran, N.; Steinhoff, F. E. S.; Plenio, M. B.

    2016-02-01

    Quantum mechanics exhibits a wide range of nonclassical features, of which entanglement in multipartite systems takes a central place. In several specific settings, it is well known that nonclassicality (e.g., squeezing, spin squeezing, coherence) can be converted into entanglement. In this work, we present a general framework, based on superposition, for structurally connecting and converting nonclassicality to entanglement. In addition to capturing the previously known results, this framework also allows us to uncover new entanglement convertibility theorems in two broad scenarios, one which is discrete and one which is continuous. In the discrete setting, the classical states can be any finite linearly independent set. For the continuous setting, the pertinent classical states are "symmetric coherent states," connected with symmetric representations of the group S U (K ). These results generalize and link convertibility properties from the resource theory of coherence, spin coherent states, and optical coherent states, while also revealing important connections between local and nonlocal pictures of nonclassicality.

  9. Converting Nonclassicality into Entanglement.

    Science.gov (United States)

    Killoran, N; Steinhoff, F E S; Plenio, M B

    2016-02-26

    Quantum mechanics exhibits a wide range of nonclassical features, of which entanglement in multipartite systems takes a central place. In several specific settings, it is well known that nonclassicality (e.g., squeezing, spin squeezing, coherence) can be converted into entanglement. In this work, we present a general framework, based on superposition, for structurally connecting and converting nonclassicality to entanglement. In addition to capturing the previously known results, this framework also allows us to uncover new entanglement convertibility theorems in two broad scenarios, one which is discrete and one which is continuous. In the discrete setting, the classical states can be any finite linearly independent set. For the continuous setting, the pertinent classical states are "symmetric coherent states," connected with symmetric representations of the group SU(K). These results generalize and link convertibility properties from the resource theory of coherence, spin coherent states, and optical coherent states, while also revealing important connections between local and nonlocal pictures of nonclassicality.

  10. Improving Power Converter Reliability

    DEFF Research Database (Denmark)

    Ghimire, Pramod; de Vega, Angel Ruiz; Beczkowski, Szymon

    2014-01-01

    The real-time junction temperature monitoring of a high-power insulated-gate bipolar transistor (IGBT) module is important to increase the overall reliability of power converters for industrial applications. This article proposes a new method to measure the on-state collector?emitter voltage...... of a high-power IGBT module during converter operation, which may play a vital role in improving the reliability of the power converters. The measured voltage is used to estimate the module average junction temperature of the high and low-voltage side of a half-bridge IGBT separately in every fundamental...... is measured in a wind power converter at a low fundamental frequency. To illustrate more, the test method as well as the performance of the measurement circuit are also presented. This measurement is also useful to indicate failure mechanisms such as bond wire lift-off and solder layer degradation...

  11. 4 pi direction sensitive gamma imager with RENA-3 readout ASIC

    Science.gov (United States)

    Du, Yanfeng; Li, Wen; Yanoff, Brian; Gordon, Jeffrey; Castleberry, Donald

    2007-09-01

    A 4π direction-sensitive gamma imager is presented, using a 1 cm 3 3D CZT detector from Yinnel Tech and the RENA-3 readout ASIC from NOVA R&D. The measured readout system electronic noise is around 4-5 keV FWHM for all anode channels. The measured timing resolution between two channels within a single ASIC is around 10 ns and the resolution is 30 ns between two separate ASIC chips. After 3D material non-uniformity and charge trapping corrections, the measured single-pixel-event energy resolution is around 1% for Cs-137 at 662 keV using a 1 cm 3 CZT detector from Yinnel Tech with an 8 x 8 anode pixel array at 1.15 mm pitch. The energy resolution for two pixel events is 2.9%. A 10 uCi Cs-137 point source was moved around the detector to test the image reconstruction algorithms and demonstrate the source direction detection capability. Accurate source locations were reconstructed with around 200 two-pixel events within a total energy window +/-10 keV around the 662 keV full energy peak. The angular resolution FWHM at four of the five positions tested was between 0.05-0.07 steradians.

  12. A new front-end ASIC for GEM detectors with time and charge measurement capabilities

    Science.gov (United States)

    Ciciriello, F.; Corsi, F.; De Robertis, G.; Felici, G.; Loddo, F.; Marzocca, C.; Matarrese, G.; Ranieri, A.

    2016-07-01

    A 32 channel CMOS front-end ASIC has been designed to read out the GEM detectors intended to be used for beam monitoring in a new proton-therapy facility currently under construction. In order to improve the spatial resolution by exploiting charge centroid algorithms, the analog channels, based on the classic CSA+shaper architecture, are equipped with a peak detector (PD) which works as an analog memory during the read-out phase. The outputs of the PDs are multiplexed towards an integrated 8-bit subranging ADC. An accurate trigger signal marks the arrival of a valid event and is generated by fast-ORing the outputs of 32 voltage discriminators which compare the shaper outputs with a programmable threshold. The digital part of the ASIC manages the read-out of the channels, the A/D conversion and the configuration of the ASIC. A 100 Mbit/s LVDS serial link is used for data communication. The sensitivity of the analog channel is 15 mV/fC and the dynamic range is 80 fC. The simulated ENC is about 650 e- for a detector capacitance of 10 pF. © 2001 Elsevier Science. All rights reserved

  13. Development of a front end ASIC for Dark Matter directional detection with MIMAC

    CERN Document Server

    Richer, J P; Bourrion, O; Grignon, C; Guillaudin, O; Mayet, F; Santos, D

    2009-01-01

    A front end ASIC (BiCMOS-SiGe 0.35 um) has been developed within the framework of the MIMAC detector project, which aims at directional detection of non-baryonic Dark Matter. This search strategy requires 3D reconstruction of low energy (keV) tracks with a gazeous uTPC. The development of this front end ASIC is a key point in this project, allowing the 3D track reconstruction. Each ASIC monitors 16 strips of pixels with charge preamplifiers and their time over threshold is provided in real time by current discriminators via two serializing LVDS links working at 320 MHz. The charge is summed over the 16 strips and provided via a shaper. These specifications have been chosen in order to build an auto triggered electronic. An acquisition board and the related software were developed in order to validate this methodology on a prototype chamber. The prototype detector presents an anode where 2x96 strips are monitored.

  14. Development of a front end ASIC for Dark Matter directional detection with MIMAC

    Energy Technology Data Exchange (ETDEWEB)

    Richer, J.P.; Bosson, G. [Laboratoire de Physique Subatomique et de Cosmologie, Universite Joseph Fourier Grenoble 1, CNRS/IN2P3, Institut Polytechnique de Grenoble, 53, rue des Martyrs, Grenoble (France); Bourrion, O., E-mail: olivier.bourrion@lpsc.in2p3.f [Laboratoire de Physique Subatomique et de Cosmologie, Universite Joseph Fourier Grenoble 1, CNRS/IN2P3, Institut Polytechnique de Grenoble, 53, rue des Martyrs, Grenoble (France); Grignon, C.; Guillaudin, O.; Mayet, F.; Santos, D. [Laboratoire de Physique Subatomique et de Cosmologie, Universite Joseph Fourier Grenoble 1, CNRS/IN2P3, Institut Polytechnique de Grenoble, 53, rue des Martyrs, Grenoble (France)

    2010-08-21

    A front end ASIC (BiCMOS-SiGe 0.35{mu}m) has been developed within the framework of the MIMAC detector project, which aims at directional detection of non-baryonic Dark Matter. This search strategy requires 3D reconstruction of low energy (a few keV) tracks with a gaseous {mu}TPC. The development of this front end ASIC is a key point of the project, allowing the 3D track reconstruction. Each ASIC monitors 16 strips of pixels with charge preamplifiers and their time over threshold is provided in real time by current discriminators via two serializing LVDS links working at 320 MHz. The charge is summed over the 16 strips and provided via a shaper. These specifications have been chosen in order to build an auto triggered electronics. An acquisition board and the related software were developed in order to validate this methodology on a prototype chamber. The prototype detector presents an anode where 2x96 strips of pixels are monitored.

  15. A new front-end ASIC for GEM detectors with time and charge measurement capabilities

    Energy Technology Data Exchange (ETDEWEB)

    Ciciriello, F., E-mail: fabio.ciciriello@poliba.it [DEI-Politecnico di Bari, Via Orabona 4, I-70125 Bari (Italy); INFN, Sezione di Bari, Via Orabona 4, I-70125 Bari (Italy); Corsi, F. [DEI-Politecnico di Bari, Via Orabona 4, I-70125 Bari (Italy); INFN, Sezione di Bari, Via Orabona 4, I-70125 Bari (Italy); De Robertis, G. [INFN, Sezione di Bari, Via Orabona 4, I-70125 Bari (Italy); Felici, G. [INFN, Laboratori Nazionali di Frascati, Via E. Fermi 40, I-00044 Frascati (Italy); Loddo, F. [INFN, Sezione di Bari, Via Orabona 4, I-70125 Bari (Italy); Marzocca, C.; Matarrese, G. [DEI-Politecnico di Bari, Via Orabona 4, I-70125 Bari (Italy); INFN, Sezione di Bari, Via Orabona 4, I-70125 Bari (Italy); Ranieri, A. [INFN, Sezione di Bari, Via Orabona 4, I-70125 Bari (Italy)

    2016-07-11

    A 32 channel CMOS front-end ASIC has been designed to read out the GEM detectors intended to be used for beam monitoring in a new proton-therapy facility currently under construction. In order to improve the spatial resolution by exploiting charge centroid algorithms, the analog channels, based on the classic CSA+shaper architecture, are equipped with a peak detector (PD) which works as an analog memory during the read-out phase. The outputs of the PDs are multiplexed towards an integrated 8-bit subranging ADC. An accurate trigger signal marks the arrival of a valid event and is generated by fast-ORing the outputs of 32 voltage discriminators which compare the shaper outputs with a programmable threshold. The digital part of the ASIC manages the read-out of the channels, the A/D conversion and the configuration of the ASIC. A 100 Mbit/s LVDS serial link is used for data communication. The sensitivity of the analog channel is 15 mV/fC and the dynamic range is 80 fC. The simulated ENC is about 650 e{sup −} for a detector capacitance of 10 pF. © 2001 Elsevier Science. All rights reserved.

  16. RF-DC converter for HF RFID sensing applications powered by a near-field loop antenna

    Science.gov (United States)

    Colella, R.; Pasca, M.; Catarinucci, L.; Tarricone, L.; D'Amico, S.

    2016-07-01

    In this paper, an RF-DC converter operating at 13.56 MHz (HF radio frequency identification (RFID) frequency band) is presented. Its architecture provides RF to load isolation, reducing the losses due to the reverse saturation current and improving the sensitivity. Fed by a loop antenna, the RF-DC converter is made by a Dickson's RF-DC rectifier and an additional Pelliconi's charge pump driven by a fully integrated 50 kHz ring oscillator realized using an application-specific integrated circuit (ASIC). The input RF signal from the reader is converted to DC supply voltage and stored on a 1 μF capacitor. Mathematical model of the converter is developed and verified through measurements. Silicon prototypes of the ASIC have been realized in 350 nm complementary metal-oxide semiconductor technology. Measurements have been done on 10 different samples showing an output voltage in the range of 0.5 V-3.11 V in correspondence of an RF input signal power in the range of -19 dBm-0 dBm. These output voltage levels are suitable to power HF RFID sensing platforms and sensor nodes of body sensor networks.

  17. Radiation Hardened Structured ASIC Platform for Rapid Chip Development for Very High Speed System on a Chip (SoC) and Complex Digital Logic Systems Project

    Data.gov (United States)

    National Aeronautics and Space Administration — Radiation Hardened Application Specific Integrated Circuits (ASICs) provide for the highest performance, lowest power and size for Space Missions. In order to...

  18. SSG Wave Energy Converter

    DEFF Research Database (Denmark)

    Margheritini, Lucia; Vicinanza, Diego; Frigaard, Peter

    2008-01-01

    head hydroturbines are converting the potential energy of the stored water into power. A key to success for the SSG will be the low cost of the structure and its robustness. The construction of the pilot plant is scheduled and this paper aims to describe the concept of the SSG wave energy converter...... and the studies behind the process that leads to its construction. The pilot plant is an on-shore full scale module in 3 levels with an expected power production of 320 MWh/y in the North Sea. Location, wave climate and laboratory tests results will be used here to describe the pilot plant and its characteristics....

  19. Angiotensin-converting enzyme

    DEFF Research Database (Denmark)

    Sørensen, P G; Rømer, F K; Cortes, D

    1984-01-01

    In order to evaluate bleomycin-associated lung damage in humans, lung function parameters and serum levels of the endothelial-bound angiotensin-converting enzyme (ACE) were determined by serial measurements in 11 patients who were treated for testicular cancer. None developed clinical or radiolog......In order to evaluate bleomycin-associated lung damage in humans, lung function parameters and serum levels of the endothelial-bound angiotensin-converting enzyme (ACE) were determined by serial measurements in 11 patients who were treated for testicular cancer. None developed clinical...

  20. Front-end readout ASIC for charged particle counting with the RADEM instrument on the ESA JUICE mission

    Science.gov (United States)

    Stein, Timo A.; Pâhlsson, Philip; Meier, Dirk; Hasanbegovic, Amir; Otnes Berge, Hans Kristian; Altan, Mehmet Akif; Ackermann, Jörg; Najafiuchevler, Bahram; Azman, Suleyman; Talebi, Jahanzad; Olsen, Alf; Gheorghe, Codin; Steenari, David; Øya, Petter; Johansen, Tor Magnus; Maehlum, Gunnar

    2016-07-01

    The detector readout for the Radiation-hard Electron Monitor (RADEM) aboard the JUpiter ICy moons Explorer (JUICE) uses a custom-made application-specific integrated circuit (ASIC, model: IDE3466) for the charge signal readout from silicon radiation sensors. RADEM measures the total ionizing dose and dose rate for protons (5 MeV to 250 MeV), electrons (0.3 MeV to 40 MeV) and ions. RADEM has in total three chips of the same design: one chip for the proton and ion detector, one for the electron detector, and one for the directional detector. The ASIC has 36 chargesensitive pre-amplifiers (CSA), 36 counters of 22-bits each, and one analogue output for multiplexing the pulse heights from all channels. The counters count pulses from charged particles in the silicon sensors depending on the charge magnitude and the coincidence trigger pattern from the 36 channels. We have designed the ASIC in 0.35-μm CMOS process and an ASIC wafer lot has been manufactured at AMS. This article presents the ASIC design specifications and design validation results. The preliminary results from tests with bare chips indicate that the design meets the technical requirements.

  1. DC-DC converters in 0.35μm CMOS technology

    Science.gov (United States)

    Michelis, S.; Allongue, B.; Blanchot, G.; Faccio, F.; Fuentes, C.; Orlandi, S.; Saggini, S.; Cengarle, S.; Ongaro, F.

    2012-01-01

    In view of the upgrade of the LHC experiments, we are developing custom DC/DC converters for a more efficient power distribution scheme. A new prototype have been integrated in ASICs in the selected 0.35μm commercial high voltage technology that has been successfully tested for all radiation effects: TID, displacement damage and Single Event Burnout. This converter has been optimized for high efficiency and improved radiation tolerance. Amongst the new features the most relevant are the presence of internal linear regulators, protection circuits with a state-machine and a new pinout for a modified assembly in package in order to reduce conductive losses. This paper illustrates the design of the prototype followed by functional and radiation tests.

  2. The Convertible Arbitrage Strategy Analyzed

    NARCIS (Netherlands)

    Loncarski, I.; Ter Horst, J.R.; Veld, C.H.

    2006-01-01

    This paper analyzes convertible bond arbitrage on the Canadian market for the period 1998 to 2004.Convertible bond arbitrage is the combination of a long position in convertible bonds and a short position in the underlying stocks. Convertible arbitrage has been one of the most successful strategies

  3. Convertible Proxy Signcryption Scheme

    Institute of Scientific and Technical Information of China (English)

    李继国; 李建中; 曹珍富; 张亦辰

    2004-01-01

    In 1996, Mambo et al introduced the concept of proxy signature. However, proxy signature can only provide the delegated authenticity and cannot provide confidentiality. Recently, Gamage et al and Chan and Wei proposed different proxy signcryption schemes respectively, which extended the concept of proxy signature.However, only the specified receiver can decrypt and verify the validity of proxy signcryption in their schemes.To protect the receiver' s benefit in case of a later dispute, Wu and Hsu proposed a convertible authenticated encryption scheme, which carn enable the receiver to convert signature into an ordinary one that can be verified by anyone. Based on Wu and Hsu' s scheme and improved Kim' s scheme, we propose a convertible proxy signcryption scheme. The security of the proposed scheme is based on the intractability of reversing the one-way hash function and solving the discrete logarithm problem. The proposed scheme can satisfy all properties of strong proxy signature and withstand the public key substitution attack and does not use secure channel. In addition, the proposed scheme can be extended to convertible threshold proxy signcryption scheme.

  4. Converting the reset

    NARCIS (Netherlands)

    Hoogland, J.K.; Neumann, C.D.D.; Bloch, D.

    2001-01-01

    We give a simple algorithm to incorporate the effects of resets in convertible bond prices, without having to add an extra factor to take into account the value of the reset. Furthermore we show that the effect of a notice period, and additional make-whole features, can be treated in a straightforwa

  5. An Electromagnetic Beam Converter

    DEFF Research Database (Denmark)

    2009-01-01

    The present invention relates to an electromagnetic beam converter and a method for conversion of an input beam of electromagnetic radiation having a bell shaped intensity profile a(x,y) into an output beam having a prescribed target intensity profile l(x',y') based on a further development...

  6. Advanced DC/DC converters

    CERN Document Server

    Luo, Fang Lin

    2003-01-01

    INTRODUCTIONHistorical ReviewMultiple Quadrant ChoppersPump CircuitsDevelopment of DC/DC Conversion TechniqueCategorize Prototypes and DC/DC Converters Family TreeVOLTAGE-LIFT CONVERTERSIntroductionSeven Self-Lift ConvertersPositive Output Luo-ConvertersNegative Output Luo-ConvertersModified Positive Output Luo-Converters Double Output Luo-ConvertersPOSITIVE OUTPUT SUPER-LIFT LUO-CONVERTERS IntroductionMain SeriesAdditional SeriesEnhanced Series Re-Enhanced Series Multiple-Enhanced Series Summary of Positive Output

  7. X-ray imaging with a silicon microstrip detector coupled to the RX64 ASIC

    Energy Technology Data Exchange (ETDEWEB)

    Baldazzi, G.; Bollini, D.; Cabal Rodriguez, A.E.; Dabrowski, W.; Diaz Garcia, A.; Gambaccini, M.; Giubellino, P.; Gombia, M.; Grybos, P.; Idzik, M.; Marzari-Chiesa, A.; Montano Zetina, L.M.; Prino, F.; Ramello, L. E-mail: ramello@to.infn.it; Sitta, M.; Swientek, K.; Taibi, A.; Tuffanelli, A.; Wheadon, R.; Wiacek, P

    2003-08-21

    A single photon counting X-ray imaging system, with possible applications to dual energy mammography and angiography, is presented. A silicon microstrip detector with 100 {mu}m pitch strips is coupled to RX64 ASICs, each of them including 64 channels of preamplifier, shaper, discriminator and scaler. The system has low noise, good spatial resolution and high counting rate capability. Results on energy resolution have been obtained with a fluorescence source and quasi-monochromatic X-rays beams. Preliminary images obtained with an angiographic phantom are presented.

  8. QIE12: A New High-Performance ASIC for the ATLAS TileCal Upgrade

    CERN Document Server

    Drake, Gary; The ATLAS collaboration; Proudfoot, James; Stanek, Robert; Chekanov, Sergei

    2015-01-01

    We present results on the QIE12, a custom ASIC, being developed for the ATLAS TileCal Phase 2 Upgrade. The design features 1.5 fC sensitivity, more than 17 bits of dynamic range with logarithmic response, and an on-chip TDC with one nanosecond resolution. It has a programmable shunt output for monitoring the integrated current. The device operates with no dead-time at 40 MHz, making it ideal for calorimetry at the LHC. We present bench measurements and integration studies that characterize the performance, radiation tolerance measurements, and the design for the ATLAS TileCal detector for the Phase 2 Upgrade.

  9. An introduction to future truly wearable medical devices--from application to ASIC.

    Science.gov (United States)

    Casson, Alexander J; Logesparan, Lojini; Rodriguez-Villegas, Esther

    2010-01-01

    This talk will provide an introduction to the "Towards future truly wearable medical devices: from application to ASIC" mini-symposium. For user comfort and acceptance long term physiological sensors must be discrete, comfortable and easy to use. These requirements place stringent limits on all aspects of the system design: from the overall application aim, to power generation issues, to low power electronic design techniques. For successful devices design issues in all of these areas must be solved simultaneously. The work here presents an overview and introduction to these topics.

  10. Operational Studies of Cadmium Zinc Telluride Microstrip Detectors using SVX ASIC Electronics

    Science.gov (United States)

    Krizmanic, John; Barbier, L. M.; Barthelmy, S.; Bartlett, L.; Birsa, F.; Gehrels, N.; Hanchak, C.; Kurczynski, P.; Odom, J.; Parsons, A.; Palmer, D.; Sheppard, D.; Snodgrass, S.; Stahle, C. M.; Teegarden, B.; Tueller, J.

    1997-04-01

    We have been investigating the operational properties of cadmium zinc telluride (CZT) microstrip detectors by using SVX ASIC readout electronics. This research is in conjunction with the development of a CZT-based, next generation gamma-ray telescope for use in the gamma-ray Burst ArcSecond Imaging and Spectroscopy (BASIS) experiment. CZT microstrip detectors with 128 channels and 100 micron strip pitch have been fabricated and were interfaced to SVX electronics at Goddard Space Flight Center. Experimental results involving position sensing, spectroscopy, and CZT operational properties will be presented.

  11. Recent progress in front end ASICs for high-energy physics

    CERN Document Server

    Hall, G

    2005-01-01

    Developments of Application Specific Integrated Circuits (ASICs) for applications in the CMS experiment are briefly described, along with the motivations for the choice of technology, focussing especially on silicon strip readout of the CMS tracker. The major change in the last few years has been the widespread adoption in CMS of a commercial deep sub-micron CMOS technology in preference to specific radiation-hardened processes which seemed to be the only solution meeting the LHC requirements only a few years ago. The reasons for this are described and the performance of representative chips and the technology presented. The implications for future developments are outlined.

  12. Low-noise multichannel ASIC for high count rate X-ray diffractometry applications

    Energy Technology Data Exchange (ETDEWEB)

    Szczygiel, R. [AGH University of Science and Technology, Department of Measurement and Instrumentation, al. Mickiewicza 30, Krakow (Poland)], E-mail: robert.szczygiel@agh.edu.pl; Grybos, P.; Maj, P. [AGH University of Science and Technology, Department of Measurement and Instrumentation, al. Mickiewicza 30, Krakow (Poland); Tsukiyama, A.; Matsushita, K.; Taguchi, T. [Rigaku Corporation, 3-9-12 Matsubara-cho, Akishima-shi, Tokyo (Japan)

    2009-08-01

    RG64 is a 64-channel ASIC designed for the silicon strip detector readout and optimized for high count rate X-ray imaging applications. In this paper we report on the test results referring to the RG64 noise level, channel uniformity and the operation with a high rate of input signals. The parameters of the RG64-based diffractometry system are compared with the ones based on the scintillation counter. Diffractometry measurement results with silicon strip detectors of different strip lengths and strip pitch are also presented.

  13. Racing of ASIC Versus FPGA%论ASIC与FPGA之争

    Institute of Scientific and Technical Information of China (English)

    韩俊刚

    2004-01-01

    论述现场可编程门阵列(FPGA)产品的发展情况和对于专用集成电路(ASIC)的影响.介绍了目前国际上对FPGA和ASIC的竞争问题的讨论,同时对ASIC和FPGA进行了简单的比较,并对FPGA的新的应用领域作了介绍.最后提出发展我国FPGA产业的建议.

  14. Performance and Calibration of H2RG Detectors and SIDECAR ASICs for the RATIR Camera

    Science.gov (United States)

    Fox, Ori D.; Kutyrev, Alexander S.; Rapchun, David A.; Klein, Christopher R.; Butler, Nathaniel R.; Bloom, Josh; de Diego, Jos A.; Simn Farah, Alejandro D.; Gehrels, Neil A.; Georgiev, Leonid; Gonzlez-Hernandez, J. Jess; Lee, William H.; Loose, Markus; Lotkin, Gennadiy; Moseley, Samuel H.; Prochaska, J. Xavier; Ramirez-Ruiz, Enrico; Richer, Michael G.; Robinson, Frederick D.; Romn-Zuniga, Carols; Samuel, Mathew V.; Sparr, Leroy M.; Watson, Alan M.

    2012-01-01

    The Reionization And Transient Infra,.Red (RATIR) camera has been built for rapid Gamma,.Ray Burst (GRE) followup and will provide simultaneous optical and infrared photometric capabilities. The infrared portion of this camera incorporates two Teledyne HgCdTe HAWAII-2RG detectors, controlled by Teledyne's SIDECAR ASICs. While other ground-based systems have used the SIDECAR before, this system also utilizes Teledyne's JADE2 interface card and IDE development environment. Together, this setup comprises Teledyne's Development Kit, which is a bundled solution that can be efficiently integrated into future ground-based systems. In this presentation, we characterize the system's read noise, dark current, and conversion gain.

  15. A custom front-end ASIC for the readout and timing of 64 SiPM photosensors

    Energy Technology Data Exchange (ETDEWEB)

    Bagliesi, M.G., E-mail: mg.bagliesi@pi.infn.it [Department of Physics, University of Siena and INFN, Via Roma 56, 53100 Siena (Italy); Avanzini, C. [INFN Sezione di Pisa, Edificio C-Polo Fibonacci Largo Bruno Pontecorvo 3, 56127 Pisa (Italy); Bigongiari, G.; Cecchi, R.; Kim, M.Y.; Maestro, P.; Marrocchesi, P.S. [Department of Physics, University of Siena and INFN, Via Roma 56, 53100 Siena (Italy); Morsani, F. [INFN Sezione di Pisa, Edificio C-Polo Fibonacci Largo Bruno Pontecorvo 3, 56127 Pisa (Italy)

    2011-06-15

    A new class of instruments - based on Silicon PhotoMultiplier (SiPM) photosensors - are currently under development for the next generation of Astroparticle Physics experiments in future space missions. A custom front-end ASIC (Application Specific Integrated Circuit) for the readout of 64 SiPM sensors was specified in collaboration with GM-IDEAS (Norway) that designed and manufactured the ASIC. Our group developed a custom readout board equipped with a 16 bit ADC for the digitization of both pulse height and time information. A time stamp, generated by the ASIC in correspondence of the threshold crossing time, is digitized and recorded for each channel. This allows to define a narrow time window around the physics event that reduces significantly the background due to the SiPM dark count rate. In this paper, we report on the preliminary test results obtained with the readout board prototype.

  16. CLARO-CMOS, an ASIC for single photon counting with Ma-PMTs, MCPs and SiPMs

    Science.gov (United States)

    Carniti, P.; Cibinetto, G.; Cotta Ramusino, A.; Giachero, A.; Gotti, C.; Maino, M.; Malaguti, R.; Pessina, G.

    2013-01-01

    An ASIC named CLARO-CMOS was designed for fast photon counting with MaPMTs, MCPs and SiPMs. The prototype was realized in a .35 μm CMOS technology and has four channels, each with a fast amplifier and a discriminator. The main features of the design are the high speed of operation and the low power dissipation, below 1 mW per channel. This paper focuses on the use of the CLARO for SiPM readout. The ASIC was tested with several SiPMs of various sizes, connected to the input of the chip both directly and through a coaxial cable about one meter long. In the latter case the ASIC is still fully functional although the speed of response is affected by the cable capacitance. The threshold could be set just above the single photoelectron level, and with 1 ×1 mm2 SiPMs the discrete photoelectron peaks could be well resolved.

  17. High-density expression of Ca2+-permeable ASIC1a channels in NG2 glia of rat hippocampus.

    Directory of Open Access Journals (Sweden)

    Yen-Chu Lin

    Full Text Available NG2 cells, a fourth type of glial cell in the mammalian CNS, undergo reactive changes in response to a wide variety of brain insults. Recent studies have demonstrated that neuronally expressed acid-sensing ion channels (ASICs are implicated in various neurological disorders including brain ischemia and seizures. Acidosis is a common feature of acute neurological conditions. It is postulated that a drop in pH may be the link between the pathological process and activation of NG2 cells. Such postulate immediately prompts the following questions: Do NG2 cells express ASICs? If so, what are their functional properties and subunit composition? Here, using a combination of electrophysiology, Ca2+ imaging and immunocytochemistry, we present evidence to demonstrate that NG2 cells of the rat hippocampus express high density of Ca2+-permeable ASIC1a channels compared with several types of hippocampal neurons. First, nucleated patch recordings from NG2 cells revealed high density of proton-activated currents. The magnitude of proton-activated current was pH dependent, with a pH for half-maximal activation of 6.3. Second, the current-voltage relationship showed a reversal close to the equilibrium potential for Na+. Third, psalmotoxin 1, a blocker specific for the ASIC1a channel, largely inhibited proton-activated currents. Fourth, Ca2+ imaging showed that activation of proton-activated channels led to an increase of [Ca2+]i. Finally, immunocytochemistry showed co-localization of ASIC1a and NG2 proteins in the hippocampus. Thus the acid chemosensor, the ASIC1a channel, may serve for inducing membrane depolarization and Ca2+ influx, thereby playing a crucial role in the NG2 cell response to injury following ischemia.

  18. A multi-channel 24.4 ps bin size Time-to-Digital Converter for HEP applications

    CERN Document Server

    Mester, C; Morira, P

    2008-01-01

    A multi-channel time-tagging Time-to-Digital Converter (TDC) ASIC with a resolution of 24.4 ps (bin size) has been implemented and fabricated in a 130 nm CMOS technology. An on-chip PLL is used to generate an internal timing reference from an external 40 MHz clock source. The circuit is based on a 32 element Delay Locked Loop (DLL) which performs the time interpolation. The 32 channel architecture of the TDC is suitable for both triggered and non-triggered applications. The prototype contains test structures such as a substrate noise generator. The paper describes the circuit architecture and its principles of operation.

  19. A 0.18 micrometer CMOS Thermopile Readout ASIC Immune to 50 MRAD Total Ionizing Dose (SI) and Single Event Latchup to 174MeV-cm(exp 2)/mg

    Science.gov (United States)

    Quilligan, Gerard T.; Aslam, Shahid; Lakew, Brook; DuMonthier, Jeffery J.; Katz, Richard B.; Kleyner, Igor

    2014-01-01

    Radiation hardened by design (RHBD) techniques allow commercial CMOS circuits to operate in high total ionizing dose and particle fluence environments. Our radiation hard multi-channel digitizer (MCD) ASIC (Figure 1) is a versatile analog system on a chip (SoC) fabricated in 180nm CMOS. It provides 18 chopper stabilized amplifier channels, a 16- bit sigma-delta analog-digital converter (SDADC) and an on-chip controller. The MCD was evaluated at Goddard Space Flight Center and Texas A&M University's radiation effects facilities and found to be immune to single event latchup (SEL) and total ionizing dose (TID) at 174 MeV-cm(exp 2)/mg and 50 Mrad (Si) respectively.

  20. DSP controlled power converter

    OpenAIRE

    Chan, CH; Pong, MH

    1995-01-01

    A digital controller is designed and implemented by a Digital Signal Processor (DSP) to replace the Pulse Width Modulator (PWM) and error amplifier compensation network in a two wheeler forward converter. The DSP controller is designed in three approaches: a) Discretization of analog controller - the design is based on the transfer function of the error amplifier compensation network. b) Digital PID controller design - the design is based on the general form of the pulse transfer function of ...

  1. The interaction between the first transmembrane domain and the thumb of ASIC1a is critical for its N-glycosylation and trafficking.

    Directory of Open Access Journals (Sweden)

    Lan Jing

    Full Text Available Acid-sensing ion channel-1a (ASIC1a, the primary proton receptor in the brain, contributes to multiple diseases including stroke, epilepsy and multiple sclerosis. Thus, a better understanding of its biogenesis will provide important insights into the regulation of ASIC1a in diseases. Interestingly, ASIC1a contains a large, yet well organized ectodomain, which suggests the hypothesis that correct formation of domain-domain interactions at the extracellular side is a key regulatory step for ASIC1a maturation and trafficking. We tested this hypothesis here by focusing on the interaction between the first transmembrane domain (TM1 and the thumb of ASIC1a, an interaction known to be critical in channel gating. We mutated Tyr71 and Trp287, two key residues involved in the TM1-thumb interaction in mouse ASIC1a, and found that both Y71G and W287G decreased synaptic targeting and surface expression of ASIC1a. These defects were likely due to altered folding; both mutants showed increased resistance to tryptic cleavage, suggesting a change in conformation. Moreover, both mutants lacked the maturation of N-linked glycans through mid to late Golgi. These data suggest that disrupting the interaction between TM1 and thumb alters ASIC1a folding, impedes its glycosylation and reduces its trafficking. Moreover, reducing the culture temperature, an approach commonly used to facilitate protein folding, increased ASIC1a glycosylation, surface expression, current density and slowed the rate of desensitization. These results suggest that correct folding of extracellular ectodomain plays a critical role in ASIC1a biogenesis and function.

  2. Performance of CATIROC: ASIC for smart readout of large photomultiplier arrays

    Science.gov (United States)

    Blin, S.; Callier, S.; Conforti Di Lorenzo, S.; Dulucq, F.; De La Taille, C.; Martin-Chassard, G.; Seguin-Moreau, N.

    2017-03-01

    CATIROC (Charge And Time Integrated Read Out Chip) is a complete read-out chip manufactured in AustriaMicroSystem (AMS) SiGe 0.35 μm technology, designed to read arrays of 16 photomultipliers (PMTs). It is an upgraded version of PARISROC2 [1] designed in 2010 in the context of the PMm2 (square meter PhotoMultiplier) project [2]. CATIROC is a SoC (System on Chip) that processes analog signals up to the digitization and sparsification to reduce the cost and cable number. The ASIC is composed of 16 independent channels that work in triggerless mode, auto-triggering on the single photo-electron. It provides a charge measurement up to 400 photoelectrons (70 pC) on two scales of 10 bits and a timing information with an accuracy of 200 ps rms. The ASIC was sent for fabrication in February 2015 and then received in September 2015. It is a good candidate for two Chinese projects (LHAASO and JUNO). The architecture and the measurements will be detailed in the paper.

  3. Low-Power, 8-Channel EEG Recorder and Seizure Detector ASIC for a Subdermal Implantable System.

    Science.gov (United States)

    Do Valle, Bruno G; Cash, Sydney S; Sodini, Charles G

    2016-12-01

    EEG remains the mainstay test for the diagnosis and treatment of patients with epilepsy. Unfortunately, ambulatory EEG systems are far from ideal for patients who have infrequent seizures. These systems only last up to 3 days and if a seizure is not captured during the recordings, a definite diagnosis of the patient's condition cannot be given. This work aims to address this need by proposing a subdermal implantable, eight-channel EEG recorder and seizure detector that has two modes of operation: diagnosis and seizure counting. In the diagnosis mode, EEG is continuously recorded until a number of seizures are recorded. In the seizure counting mode, the system uses a low-power algorithm to track the number of seizures a patient has, providing doctors with a reliable count to help determine medication efficacy or other clinical endpoint. An ASIC that implements the EEG recording and seizure detection algorithm was designed and fabricated in a 0.18 μm CMOS process. The ASIC includes eight EEG channels and is designed to minimize the system's power and size. The result is a power-efficient analog front end that requires 2.75 μW per channel in diagnosis mode and 0.84 μW per channel in seizure counting mode. Both modes have an input referred noise of approximately 1.1 μVrms.

  4. A low power biomedical signal processor ASIC based on hardware software codesign.

    Science.gov (United States)

    Nie, Z D; Wang, L; Chen, W G; Zhang, T; Zhang, Y T

    2009-01-01

    A low power biomedical digital signal processor ASIC based on hardware and software codesign methodology was presented in this paper. The codesign methodology was used to achieve higher system performance and design flexibility. The hardware implementation included a low power 32bit RISC CPU ARM7TDMI, a low power AHB-compatible bus, and a scalable digital co-processor that was optimized for low power Fast Fourier Transform (FFT) calculations. The co-processor could be scaled for 8-point, 16-point and 32-point FFTs, taking approximate 50, 100 and 150 clock circles, respectively. The complete design was intensively simulated using ARM DSM model and was emulated by ARM Versatile platform, before conducted to silicon. The multi-million-gate ASIC was fabricated using SMIC 0.18 microm mixed-signal CMOS 1P6M technology. The die area measures 5,000 microm x 2,350 microm. The power consumption was approximately 3.6 mW at 1.8 V power supply and 1 MHz clock rate. The power consumption for FFT calculations was less than 1.5 % comparing with the conventional embedded software-based solution.

  5. Radiation-hard ASICs for optical data transmission in the ATLAS pixel detector

    CERN Document Server

    Ziolkowski, M; Buchholz, P; Ciliox, A; Gan, K K; Holder, M; Johnson, M; Kagan, H; Kass, R; Nderitu, S; Rahimi, A; Rush, C J; Smith, S; Ter-Antonian, R; Zoeller, M M

    2004-01-01

    We have developed two radiation-hard ASICs for optical data transmission in the ATLAS pixel detector at the CERN Large Hadron Collider (LHC). The first circuit is a driver chip for a Vertical Cavity Surface Emitting Laser (VCSEL) diode to be used for 80 Mbit/s data transmission from the detector. The second circuit is a Bi-Phase Mark, decoder chip to recover the control data and 40 MHz clock received optically by a PIN diode on the detector side. During ten years of operation at the LHC, the ATLAS optical link circuitry will be exposed to a maximum total fluence of 10/sup 15/ 1-MeV-equivalent neutrons per cm/sup 2/. We have successfully implemented both ASICs in a commercial 0.25 mu m CMOS technology using standard layout techniques to enhance the radiation tolerance. Both chips are four- channel devices compatible with common cathode PIN and VCSEL arrays. We present results from final prototype circuits and from irradiation studies of both circuits with 24 GeV protons up to a total dose of 57 Mrad. (3 refs).

  6. A 130 nm ASIC prototype for the NA62 Gigatracker readout

    CERN Document Server

    Dellacasa, G; Wheadon, R; Mazza, G; Rivetti, A; Marchetto, F; Garbolino, S

    2011-01-01

    One of the most challenging detectors of the NA62 experiment is the silicon tracker, called Gigatracker. It consists of three hybrid silicon pixel stations, each one covering an area of 27 mm x 60 mm. While the maximum pixel size is fairly large, 300 mu m x 300 mu m the system has to sustain a very high particle rate, 1.5 MHz/mm(2), which corresponds to 800 MHz for each station. To obtain an efficient tracking with such a high rate the required track timing resolution is 150 ps (rms). Therefore the front-end ASIC should provide for each pixel a 200 Ps time measurement capability, thus leading to the requirement of time walk compensation and very compact TDCs. Moreover, Single Event Upset protection has to be implemented in order to protect the digital circuitry. An ASIC prototype has been realized in CMOS 130 nm technology, containing three pixel columns. The chip performs the time walk compensation by a Constant Fraction Discriminator circuit, while the time measurement is performed by a Time to Amplitude Co...

  7. Development of arrays of Silicon Drift Detectors and readout ASIC for the SIDDHARTA experiment

    Science.gov (United States)

    Quaglia, R.; Schembari, F.; Bellotti, G.; Butt, A. D.; Fiorini, C.; Bombelli, L.; Giacomini, G.; Ficorella, F.; Piemonte, C.; Zorzi, N.

    2016-07-01

    This work deals with the development of new Silicon Drift Detectors (SDDs) and readout electronics for the upgrade of the SIDDHARTA experiment. The detector is based on a SDDs array organized in a 4×2 format with each SDD square shaped with 64 mm2 (8×8) active area. The total active area of the array is therefore 32×16 mm2 while the total area of the detector (including 1 mm border dead area) is 34 × 18mm2. The SIDDHARTA apparatus requires 48 of these modules that are designed and manufactured by Fondazione Bruno Kessler (FBK). The readout electronics is composed by CMOS preamplifiers (CUBEs) and by the new SFERA (SDDs Front-End Readout ASIC) circuit. SFERA is a 16-channels readout ASIC designed in a 0.35 μm CMOS technology, which features in each single readout channel a high order shaping amplifier (9th order Semi-Gaussian complex-conjugate poles) and a high efficiency pile-up rejection logic. The outputs of the channels are connected to an analog multiplexer for the external analog to digital conversion. An on-chip 12-bit SAR ADC is also included. Preliminary measurements of the detectors in the single SDD format are reported. Also measurements of low X-ray energies are reported in order to prove the possible extension to the soft X-ray range.

  8. TARGET: A Digitizing And Trigger ASIC For The Cherenkov Telescope Array

    CERN Document Server

    Funk, S; Katagiri, H; Kraus, M; Okumura, A; Schoorlemmer, H; Shigenaka, A; Tajima, H; Tibaldo, L; Varner, G; Zink, A; Zorn, J

    2016-01-01

    The future ground-based gamma-ray observatory Cherenkov Telescope Array (CTA) will feature multiple types of imaging atmospheric Cherenkov telescopes, each with thousands of pixels. To be affordable, camera concepts for these telescopes have to feature low cost per channel and at the same time meet the requirements for CTA in order to achieve the desired scientific goals. We present the concept of the TeV Array Readout Electronics with GSa/s sampling and Event Trigger (TARGET) Application Specific Circuit (ASIC), envisaged to be used in the cameras of various CTA telescopes, e.g. the Gamma-ray Cherenkov Telescope (GCT), a proposed 2-Mirror Small-Sized Telescope, and the Schwarzschild-Couder Telescope (SCT), a proposed Medium-Sized Telescope. In the latest version of this readout concept the sampling and trigger parts are split into dedicated ASICs, TARGET C and T5TEA, both providing 16 parallel input channels. TARGET C features a tunable sampling rate (usually 1 GSa/s), a 16k sample deep buffer for each chann...

  9. An extremely low power voltage reference with high PSRR for power-aware ASICs

    Science.gov (United States)

    Jihai, Duan; Dongyu, Deng; Weilin, Xu; Baolin, Wei

    2015-09-01

    An extremely low power voltage reference without resistors is presented for power-aware ASICs. In order to reduce the power dissipation, an Oguey current reference source is used to reduce the static current; a cascode current mirror is used to increase the power supply rejection ratio (PSRR) and reduce the line sensitivity of the circuit. The voltage reference is fabricated in SMIC 0.18-μm CMOS process. The measured results for the voltage reference demonstrate that the temperature coefficient of the voltage is 66 ppm/°C in a range from 25 to 100 °C. The line sensitivity is 0.9% in a supply voltage range of 1.8 to 3.3 V, and PSRR is -49 dB at 100 Hz. The power dissipation is 200 nW. The chip area is 0.01 mm2. The circuit can be used as an elementary circuit block for power-aware ASICs. Project supported by the National Natural Science Foundation of China (Nos. 61161003, 61264001, 61166004) and the Guangxi Natural Science Foundation (No. 2013GXNSFAA019333).

  10. The TDCpix Readout ASIC: A 75 ps Resolution Timing Front-End for the Gigatrackerof theNA62 Experiment

    Science.gov (United States)

    Rinella, G. Aglieri; Fiorini, M.; Jarron, P.; Kaplon, J.; Kluge, A.; Martin, E.; Morel, M.; Noy, M.; Perktold, L.; Poltorak, K.

    NA62 is an experiment under development at the CERN Super Proton Synchrotron, aiming at measuring ultra rare kaon decays. The Gigatracker (GTK) detector shall combine on-beam tracking of individual particles with a time resolution of 150 ps rms. The peak flow of particles crossing the detector modules reaches 1.27 MHz/mm2 fora total rateof about 0.75 GHz.Ahybrid siliconpixel detectoris beingdevelopedto meet these requirements. The pixel chip for the Gigatracker (TDCpix) is under design. The TDCpix chip will feature 1800 square pixels of 300×300 μm2 arranged in a matrix of 45 rows × 40 columns. Bump-bonded to a silicon pixel sensor it shall perform time stamping of particle hits with a timing accuracybetter than 200 ps rms and a detection efficiencyabove 99%. The chosen architecture provides full separation of the sensitive analog amplifiers of the pixel matrix from the noisy digital circuits of the TDCs and of the readout blocks. Discriminated hit signals from each pixel are transmitted to the end of column region. An array ofTime to Digital Converters (TDC) is implemented at the bottom of the pixel array. The TDCs are based on time tagging the events with the fine time codes generated by Delay Locked Loops (DLL) and have a nominal time bin of ˜100 ps. Time stamps and time-over-threshold are recorded for each discriminated hit and the correction of the discriminator's time-walk is performed off-detector. Data are continuously transmitted on four 2.4 Gb/s serial output links. Adescription of the on-going design of the final TDCpix is given in this paper. Design choices and some technical implementation details are presented. Aprototype ASIC including thekeycomponents of this architecture has been manufactured. The achievement of specification figures such as a time resolution of the processing chain of 75 ps rms as well as charged particle time stampingwitha resolutionbetterthan200psrmswere demonstratedexperimentally.Asummaryoftheseresultsisalso presented in

  11. X-Y Converter Family

    DEFF Research Database (Denmark)

    Bhaskar, Mahajan Sagar; Sanjeevikumar, Padmanaban; Wheeler, Patrick

    2016-01-01

    A New breed of a buck boost converter, named as the XY converter family is proposed in this article. In the XY family, 16 topologies are presented which are highly suitable for renewable energy applications which require a high ratio of DC-DC converter; such as a photovoltaic multilevel inverter...... system, high voltage automotive applications and industrial drives. Compared to the traditional boost converter and existing recent converters, the proposed XY converter family has the ability to provide a higher output voltage by using less number of power devices and reactive components. Other distinct...... features of the XY converter family are i) Single control switch ii) Provide negative output voltage iii) Non-isolated topologies iv) High conversion ratio without making the use of high duty cycle and v) modular structure. XY family is compared with the recent high step-up converters and the detailed...

  12. Cycloidal Wave Energy Converter

    Energy Technology Data Exchange (ETDEWEB)

    Stefan G. Siegel, Ph.D.

    2012-11-30

    This program allowed further advancing the development of a novel type of wave energy converter, a Cycloidal Wave Energy Converter or CycWEC. A CycWEC consists of one or more hydrofoils rotating around a central shaft, and operates fully submerged beneath the water surface. It operates under feedback control sensing the incoming waves, and converts wave power to shaft power directly without any intermediate power take off system. Previous research consisting of numerical simulations and two dimensional small 1:300 scale wave flume experiments had indicated wave cancellation efficiencies beyond 95%. The present work was centered on construction and testing of a 1:10 scale model and conducting two testing campaigns in a three dimensional wave basin. These experiments allowed for the first time for direct measurement of electrical power generated as well as the interaction of the CycWEC in a three dimensional environment. The Atargis team successfully conducted two testing campaigns at the Texas A&M Offshore Technology Research Center and was able to demonstrate electricity generation. In addition, three dimensional wave diffraction results show the ability to achieve wave focusing, thus increasing the amount of wave power that can be extracted beyond what was expected from earlier two dimensional investigations. Numerical results showed wave cancellation efficiencies for irregular waves to be on par with results for regular waves over a wide range of wave lengths. Using the results from previous simulations and experiments a full scale prototype was designed and its performance in a North Atlantic wave climate of average 30kW/m of wave crest was estimated. A full scale WEC with a blade span of 150m will deliver a design power of 5MW at an estimated levelized cost of energy (LCOE) in the range of 10-17 US cents per kWh. Based on the new results achieved in the 1:10 scale experiments these estimates appear conservative and the likely performance at full scale will

  13. Resonant power converters

    CERN Document Server

    Kazimierczuk, Marian K

    2012-01-01

    This book is devoted to resonant energy conversion in power electronics. It is a practical, systematic guide to the analysis and design of various dc-dc resonant inverters, high-frequency rectifiers, and dc-dc resonant converters that are building blocks of many of today's high-frequency energy processors. Designed to function as both a superior senior-to-graduate level textbook for electrical engineering courses and a valuable professional reference for practicing engineers, it provides students and engineers with a solid grasp of existing high-frequency technology, while acquainting them wit

  14. A low-power CMOS ASIC for X-ray Silicon Drift Detectors low-noise pulse processing

    Science.gov (United States)

    Ahangarianabhari, M.; Bertuccio, G.; Macera, D.; Malcovati, P.; Grassi, M.; Rashevsky, A.; Rashevskaya, I.; Vacchi, A.; Zampa, G.; Zampa, N.; Fuschino, F.; Evangelista, Y.; Campana, R.; Labanti, C.; Feroci, M.

    2014-03-01

    We present an Application Specific Integrated Circuit (ASIC), named VEGA-1, designed and manufactured for low-power analog pulse processing of signals from Silicon Drift Detectors (SDDs). The VEGA-1 ASIC consists of an analog and a digital/mixed-signal section to achieve all the functionalities and specifications required for high-resolution X-ray spectroscopy in the energy range from 500 eV to 60 keV with low power consumption. The VEGA-1 ASIC has been designed and manufactured in 0.35-μm CMOS mixed-signal technology in single and 32-channel version with dimensions of 200 μm × 500 μm per channel. A minimum intrinsic ENC of 12 electrons r.m.s. at 3.6 μs shaping time and room temperature is measured for the ASIC without detector. The VEGA-1 has been tested with Q10-SDD designed in Trieste and fabricated at FBK, with an active area of 10 mm2 and a thickness of 450 μm. The aforementioned detector has an anode current of about 180 pA at +22°C. A minimum Equivalent Noise Charge (ENC) of 16 electrons r.m.s. at 3.0 μs shaping time and -30°C has been demonstrated with a total measured power consumption of 482 μW.

  15. Pilot tests of a PET detector using the TOF-PET ASIC based on monolithic crystals and SiPMs

    Science.gov (United States)

    Aguilar, A.; González-Montoro, A.; González, A. J.; Hernández, L.; Monzó, J. M.; Bugalho, R.; Ferramacho, L.; Benlloch, J. M.

    2016-12-01

    In this work we show pilot tests of PET detector blocks using the TOF-PET ASIC, coupled to SiPM detector arrays and different crystal configurations. We have characterized the main ASIC features running calibration processes to compensate the time dispersion among the different ASIC/SiPM paths as well as for the time walk on the arrival of optical photons. The aim of this work is to use of LYSO monolithic crystals and explore their photon Depth of Interaction (DOI) capabilities, keeping good energy and spatial resolutions. First tests have been carried out with crystal arrays. Here we made it possible to reach a coincidence resolving times (CRT) of 370 ps FWHM, with energy resolutions better than 20% and resolving well 2 mm sized crystal elements. When using monolithic crystals, a single-pixel LYSO reference crystal helped to explore the CRT performance. We studied different strategies to provide the best timestamp determination in the monolithic scintillator. Times around 1 ns FWHM have been achieved in these pilot studies. In terms of spatial and energy resolution, values of about 3 mm and better than 30% were found, respectively. We have also demonstrated the capability of this system (monolithic and ASIC) to return accurate DOI information.

  16. Ionizing radiation effects on a 64-channel charge measurement ASIC designed in CMOS 0.35 {mu}m technology

    Energy Technology Data Exchange (ETDEWEB)

    La Rosa, A. [INFN, Via P. Giuria 1, Torino 10125 (Italy); Dipartimento di Fisica Sperimentale, Universita di Torino, Via P. Giuria 1, Torino 10125 (Italy)], E-mail: alessandro.larosa@cern.ch; Marchetto, F.; Pardo, J. [INFN, Via P. Giuria 1, Torino 10125 (Italy); Donetti, M. [INFN, Via P. Giuria 1, Torino 10125 (Italy); Fondazione CNAO, Via Caminadella 16, Milano 20123 (Italy); Attili, A. [INFN, Via P. Giuria 1, Torino 10125 (Italy); Bourhaleb, F. [Dipartimento di Fisica Sperimentale, Universita di Torino, Via P. Giuria 1, Torino 10125 (Italy); Cirio, R. [INFN, Via P. Giuria 1, Torino 10125 (Italy); Dipartimento di Fisica Sperimentale, Universita di Torino, Via P. Giuria 1, Torino 10125 (Italy); Garella, M.A.; Giordanengo, S. [INFN, Via P. Giuria 1, Torino 10125 (Italy); Givehchi, N. [INFN, Via P. Giuria 1, Torino 10125 (Italy); Dipartimento di Fisica Sperimentale, Universita di Torino, Via P. Giuria 1, Torino 10125 (Italy); Iliescu, S.; Mazza, G. [INFN, Via P. Giuria 1, Torino 10125 (Italy); Pecka, A.; Peroni, C. [INFN, Via P. Giuria 1, Torino 10125 (Italy); Dipartimento di Fisica Sperimentale, Universita di Torino, Via P. Giuria 1, Torino 10125 (Italy); Pitta, G. [Fondazione TERA, Via Puccini 11, Novara 28100 (Italy)

    2008-08-11

    A 64-channel circuit Application Specific Integrated Circuit (ASIC) for charge measurement has been designed in CMOS 0.35 {mu}m technology and characterized with electrical tests. The ASIC has been conceived to be used as a front-end for dosimetry and beam monitoring detector read-out. For that application, the circuitry is housed at a few centimeters from the irradiated area of the detectors and therefore radiation damages can affect the chip performances. The ASIC has been tested on an X-ray beam. In this paper, the results of the test and an estimate of the expected lifetime of the ASIC in a standard radio-therapeutical treatment environment are presented. An increase of the background current of 2 fA/Gy has been observed at low doses, whilst the gain changes by less than 3% when irradiated up to 15 kGy. Furthermore it has been assessed that, when used as an on-line beam monitor and the annealing effect has been taken into account, the background current increase is {approx}440 fA/year.

  17. Ionizing radiation effects on a 64-channel charge measurement ASIC designed in CMOS 0.35 μm technology

    Science.gov (United States)

    La Rosa, A.; Marchetto, F.; Pardo, J.; Donetti, M.; Attili, A.; Bourhaleb, F.; Cirio, R.; Garella, M. A.; Giordanengo, S.; Givehchi, N.; Iliescu, S.; Mazza, G.; Pecka, A.; Peroni, C.; Pittà, G.

    2008-08-01

    A 64-channel circuit Application Specific Integrated Circuit (ASIC) for charge measurement has been designed in CMOS 0.35 μm technology and characterized with electrical tests. The ASIC has been conceived to be used as a front-end for dosimetry and beam monitoring detector read-out. For that application, the circuitry is housed at a few centimeters from the irradiated area of the detectors and therefore radiation damages can affect the chip performances. The ASIC has been tested on an X-ray beam. In this paper, the results of the test and an estimate of the expected lifetime of the ASIC in a standard radio-therapeutical treatment environment are presented. An increase of the background current of 2 fA/Gy has been observed at low doses, whilst the gain changes by less than 3% when irradiated up to 15 kGy. Furthermore it has been assessed that, when used as an on-line beam monitor and the annealing effect has been taken into account, the background current increase is ˜440 fA/year.

  18. AIDA: A 16-channel amplifier ASIC to read out the advanced implantation detector array for experiments in nuclear decay spectroscopy

    Energy Technology Data Exchange (ETDEWEB)

    Braga, D. [STFC Rutherford Appleton Laboratory, Didcot, OX11 0QX (United Kingdom); Coleman-Smith, P. J. [STFC Daresbury Laboratory, Warrington WA4 4AD (United Kingdom); Davinson, T. [Dept. of Physics and Astronomy, Univ. of Edinburgh, Edinburgh EH9 3JZ (United Kingdom); Lazarus, I. H. [STFC Daresbury Laboratory, Warrington WA4 4AD (United Kingdom); Page, R. D. [Dept. of Physics, Univ. of Liverpool, Oliver Lodge Laboratory, Liverpool L69 7ZE (United Kingdom); Thomas, S. [STFC Rutherford Appleton Laboratory, Didcot, OX11 0QX (United Kingdom)

    2011-07-01

    We have designed a read-out ASIC for nuclear decay spectroscopy as part of the AIDA project - the Advanced Implantation Detector Array. AIDA will be installed in experiments at the Facility for Antiproton and Ion Research in GSI, Darmstadt. The AIDA ASIC will measure the signals when unstable nuclei are implanted into the detector, followed by the much smaller signals when the nuclei subsequently decay. Implant energies can be as high as 20 GeV; decay products need to be measured down to 25 keV within just a few microseconds of the initial implants. The ASIC uses two amplifiers per detector channel, one covering the 20 GeV dynamic range, the other selectable over a 20 MeV or 1 GeV range. The amplifiers are linked together by bypass transistors which are normally switched off. The arrival of a large signal causes saturation of the low-energy amplifier and a fluctuation of the input voltage, which activates the link to the high-energy amplifier. The bypass transistors switch on and the input charge is integrated by the high-energy amplifier. The signal is shaped and stored by a peak-hold, then read out on a multiplexed output. Control logic resets the amplifiers and bypass circuit, allowing the low-energy amplifier to measure the subsequent decay signal. We present simulations and test results, demonstrating the AIDA ASIC operation over a wide range of input signals. (authors)

  19. Temperature modeling and emulation of an ASIC temperature monitor system for Tightly-Coupled Processor Arrays (TCPAs)

    OpenAIRE

    E. Glocker; S. Boppu; Chen, Q; Schlichtmann, U.; Teich, J.; D. Schmitt-Landsiedel

    2014-01-01

    This contribution provides an approach for emulating the behaviour of an ASIC temperature monitoring system (TMon) during run-time for a tightly-coupled processor array (TCPA) of a heterogeneous invasive multi-tile architecture to be used for FPGA prototyping. It is based on a thermal RC modeling approach. Also different usage scenarios of TCPA are analyzed and compared.

  20. Gallium phosphide energy converters

    Energy Technology Data Exchange (ETDEWEB)

    Sims, P.E.; Dinetta, L.C.; Goetz, M.A.

    1995-10-01

    Gallium phosphide (GaP) energy converters may be successfully deployed to provide new mission capabilities for spacecraft. Betavoltaic power supplies based on the conversion of tritium beta decay to electricity using GaP energy converters can supply long term low-level power with high reliability. High temperature solar cells, also based on GaP, can be used in inward-bound missions greatly reducing the need for thermal dissipation. Results are presented for GaP direct conversion devices powered by Ni-63 and compared to the conversion of light emitted by tritiarated phosphors. Leakage currents as low as 1.2 x 10(exp {minus}17) A/sq cm have been measured and the temperature dependence of the reverse saturation current is found to have ideal behavior. Temperature dependent IV, QE, R(sub sh), and V(sub oc) results are also presented. These data are used to predict the high-temperature solar cell and betacell performance of GaP devices and suggest appropriate applications for the deployment of this technology.

  1. Manufacturing method of photoelectric converter

    Energy Technology Data Exchange (ETDEWEB)

    Yamazaki, Shunpei; Suzuki, Kunio; Fukada, Takeshi; Kanehana, Mikio

    1987-06-25

    This is a photoelectric converter wherein a photoelectromotive force is generated by utilizing the shorter wavelength side by the 1st converter and by utilizing the longer wavelength side by the 2nd converter; as a whole, wider wavelength range of light can be converted into electricity. In the 1st. converter, an electrode on the side of semi-incident surface is made transparent as well as an electrode equipped on the back of a non-mono-crystalline semiconductor. Light which passed this is introduced into the 2nd converter to generate an electromotive force. This invention especially relates with a method of forming this 2nd converter. In preparing I-type non-mono-crystalline semiconductor among the semiconductors having PIN junction, PCVD method is used by means of ECR (Electron Cyclotron Resonance) by using a hydrogen- or halogen- added Si-semiconductor instead of using expensive Ge, etc, which are common in the conventional method. (3 figs)

  2. Unity power factor converter

    Science.gov (United States)

    Wester, Gene W. (Inventor)

    1980-01-01

    A unity power factor converter capable of effecting either inversion (dc-to-dc) or rectification (ac-to-dc), and capable of providing bilateral power control from a DC source (or load) through an AC transmission line to a DC load (or source) for power flow in either direction, is comprised of comparators for comparing the AC current i with an AC signal i.sub.ref (or its phase inversion) derived from the AC ports to generate control signals to operate a switch control circuit for high speed switching to shape the AC current waveform to a sine waveform, and synchronize it in phase and frequency with the AC voltage at the AC ports, by selectively switching the connections to a series inductor as required to increase or decrease the current i.

  3. Electromagnetic wave energy converter

    Science.gov (United States)

    Bailey, R. L. (Inventor)

    1973-01-01

    Electromagnetic wave energy is converted into electric power with an array of mutually insulated electromagnetic wave absorber elements each responsive to an electric field component of the wave as it impinges thereon. Each element includes a portion tapered in the direction of wave propagation to provide a relatively wideband response spectrum. Each element includes an output for deriving a voltage replica of the electric field variations intercepted by it. Adjacent elements are positioned relative to each other so that an electric field subsists between adjacent elements in response to the impinging wave. The electric field results in a voltage difference between adjacent elements that is fed to a rectifier to derive dc output power.

  4. The TDCPix ASIC: Tracking for the NA62 GigaTracker

    CERN Document Server

    Noy, Matthew; Bonacini, Sandro; Kaplon, Jan; Kluge, Alexander; Morel, Michel; Perktold, Lukas; Poltorak, Karolina

    2014-01-01

    The TDCPix is a hybrid pixel detector readout ASIC designed for the NA62 GigaTracker detec- tor. The asynchronously operating pixel array consists of 1800 pixels, each 300x300 m m 2 . The requirements are a single-hit timing resolution better than 200 ps RMS and a read-out efficiency of 99% or better in the presence of a beam rate between 800 MHz and 1 GHz . The discrimina- tor time walk effect is compensated by time-over-threshold discriminators connected to an array of 360 dual TDC channels. The TDCpix processes up to 210 Mhits = s and provides the hit data without the need of a trigger in a continuous data stream via four 3.2 Gb = s serialisers. Under test since January 2014, the TDCPix chip is fully functional and shows excellent performance.

  5. Analogue Sum ASIC for L1 Trigger Decision in Cherenkov Telescope Cameras

    CERN Document Server

    Barrio, Joan Abel; Boix, Joan; Delagnes, Eric; Delgado, Carlos; Coromina, Lluis Freixas; Gascon, David; Guilloux, Fabrice; Coto, Ruben Lopez; Martinez, Gustavo; Sanuy, Andreu; Tejedor, Luis Angel

    2014-01-01

    The Cherenkov Telescope Array (CTA) project aims to build the largest ground-based gamma-ray observatory based on an array of Imaging Atmospheric Cherenkov Telescopes (IACTs). The CTA will implement a multi-level trigger system to distinguish between gamma ray-like induced showers and background images induced by night sky background (NSB) light. The trigger system is based on coincident detections among pixels (level 0 trigger), clusters of pixels (level 1) or telescopes. In this article, the first version of the application specific integrated circuit (ASIC) for Level 1 trigger system is presented, capable of working with different Level 0 strategies and different trigger region sizes. In addition, it complies with all the requirements specified by the CTA project, specially the most critical ones as regards noise, bandwidth, dynamic range and power consumption. All these features make the presented system very suitable for use in the CTA cameras and improve the features of discrete components prototypes of...

  6. Performance and future development of the ASDBLR ASIC for the ATLAS TRT

    CERN Document Server

    Bevensee, B E; Newcomer, F M; Tyrrell, B; Van Berg, R; Williams, H H; Romaniouk, A

    1998-01-01

    The ATLAS TRT straw tracker will consist of more than 420 K straw tubes filled with a Xenon-based fast gas located in a magnetic field of 2 T. Some tubes will operate at rates in excess of 20 MHz. Stringent signal processing goals $9 have been determined using both simulation tools and measurement standards set by hand tuned discrete component prototypes. These include the ability to detect the earliest clusters from ionizing tracks as well as energetic $9 transition radiation photons without baseline shifts in a low noise and low power design. We report on measurements of two ASIC's fabricated in different processes that appear to be capable of achieving these goals. (2 refs).

  7. Investigation of a Superscalar Operand Stack Using FO4 and ASIC Wire-Delay Metrics

    Directory of Open Access Journals (Sweden)

    Christopher Bailey

    2014-01-01

    Full Text Available Complexity in processor microarchitecture and the related issues of power density, hot spots and wire delay, are seen to be a major concern for design migration into low nanometer technologies of the future. This paper evaluates the hardware cost of an alternative to register-file organization, the superscalar stack issue array (SSIA. We believe this is the first such reported study using discrete stack elements. Several possible implementations are evaluated, using a 90 nm standard cell library as a reference model, yielding delay data and FO4 metrics. The evaluation, including reference to ASIC layout, RC extraction, and timing simulation, suggests a 4-wide issue rate of at least four Giga-ops/sec at 90 nm and opportunities for twofold future improvement by using more advanced design approaches.

  8. SCOTT: A time and amplitude digitizer ASIC for PMT signal processing

    Energy Technology Data Exchange (ETDEWEB)

    Ferry, S., E-mail: sophie.ferry@cea.fr [CEA/ Irfu/ SPP, Gif-sur-Yvette (France); Guilloux, F.; Anvar, S.; Chateau, F.; Delagnes, E.; Gautard, V.; Louis, F.; Monmarthe, E.; Le Provost, H. [CEA/ Irfu/ SEDI, Gif-sur-Yvette (France); Russo, S. [Dipartimento di Scienze Fisiche Università di Napoli, Napoli (Italy); Schuller, J-P.; Stolarczyk, Th.; Vallage, B. [CEA/ Irfu/ SPP, Gif-sur-Yvette (France); Zonca, E. [CEA/ Irfu/ SEDI, Gif-sur-Yvette (France)

    2013-10-11

    SCOTT is an ASIC designed for the readout electronics of photomultiplier tubes developed for KM3NeT, the cubic-kilometer scale neutrino telescope in Mediterranean Sea. To digitize the PMT signals, the multi-time-over-threshold technique is used with up to 16 adjustable thresholds. Digital outputs of discriminators feed a circular sampling memory and a “first in first out” digital memory. A specific study has shown that five specifically chosen thresholds are suited to reach the required timing accuracy. A dedicated method based on the duration of the signal over a given threshold allows an equivalent timing precision at any charge. To verify that the KM3NeT requirements are fulfilled, this method is applied on PMT signals digitized by SCOTT.

  9. The eight-channel ASIC bipolar transresistance amplifier D0M AMPL-8.3

    CERN Document Server

    Alexeev, G D; Dvornikov, O V; Khokhlov, A I; Mikhailov, V A; Odnokloubov, I A; Tokmenin, V V

    2001-01-01

    The eight-channel ASIC low-noise bipolar transresistance amplifier D0M Ampl-8.3 has been designed on the basis of BJT-JFET technology for gaseous wire detectors used in high-energy physics experiments. The amplifier has differential gain 130 mV/mu A at 1 k OMEGA, input noise 35 and 60 nA r.m.s. at 0 and 60 pF input capacitance, respectively, leading/trailing edge 7 ns, input resistance approx 50 OMEGA, crosstalks -47 dB, dissipated power 160 triple bond 640 mW/chip for +-3 triple bond 5 V supply. The Ampl-8.3 has been accepted for upgrading the Forward Angle Muon System of the D0 experiment (Fermilab, Batavia, USA), the total number of channels is about 50,000.

  10. ASIC design of a digital fuzzy system on chip for medical diagnostic applications.

    Science.gov (United States)

    Roy Chowdhury, Shubhajit; Roy, Aniruddha; Saha, Hiranmay

    2011-04-01

    The paper presents the ASIC design of a digital fuzzy logic circuit for medical diagnostic applications. The system on chip under consideration uses fuzzifier, memory and defuzzifier for fuzzifying the patient data, storing the membership function values and defuzzifying the membership function values to get the output decision. The proposed circuit uses triangular trapezoidal membership functions for fuzzification patients' data. For minimizing the transistor count, the proposed circuit uses 3T XOR gates and 8T adders for its design. The entire work has been carried out using TSMC 0.35 µm CMOS process. Post layout TSPICE simulation of the whole circuit indicates a delay of 31.27 ns and the average power dissipation of the system on chip is 123.49 mW which indicates a less delay and less power dissipation than the comparable embedded systems reported earlier.

  11. An important step forward in continuous spectroscopic imaging of ionising radiations using ASICs

    CERN Document Server

    Fessler, P; Eberle, H; Raad-Iseli, C D; Hilt, B; Huss, D; Krummenacher, F; Lutz, Jean Robert; Prevot, G; Renouprez, Albert Jean; Sigward, M H; Schwaller, B; Voltolini, C

    1999-01-01

    Characterization results are given for an original ASIC allowing continuous acquisition of ionising radiation images in spectroscopic mode. Ionising radiation imaging in general and spectroscopic imaging in particular must primarily be guided by the attempt to decrease statistical noise, which requires detection systems designed to allow very high counting rates. Any source of dead time must therefore be avoided. Thus, the use of on-line corrections of the inevitable dispersion of characteristics between the large number of electronic channels of the detection system, shall be precluded. Without claiming to achieve ultimate noise levels, the work described is focused on how to prevent good individual acquisition channel noise performance from being totally destroyed by the dispersion between channels without introducing dead times. With this goal, we developed an automatic charge amplifier output voltage offset compensation system which operates regardless of the cause of the offset (detector or electronic). ...

  12. Very Low-Power Consumption Analog Pulse Processing ASIC for Semiconductor Radiation Detectors

    Energy Technology Data Exchange (ETDEWEB)

    Wessendorf, K.O.; Lund, J.C.; Brunett, B.A.; Laguna, G.R.; Clements, J.W.

    1999-08-23

    We describe a very-low power consumption circuit for processing the pulses from a semiconductor radiation detector. The circuit was designed for use with a cadmium zinc telluride (CZT) detector for unattended monitoring of stored nuclear materials. The device is intended to be battery powered and operate at low duty-cycles over a long period of time. This system will provide adequate performance for medium resolution gamma-ray pulse-height spectroscopy applications. The circuit incorporates the functions of a charge sensitive preamplifier, shaping amplifier, and peak sample and hold circuit. An application specific integrated circuit (ASIC) version of the design has been designed, built and tested. With the exception of the input field effect transistor (FET), the circuit is constructed using bipolar components. In this paper the design philosophy and measured performance characteristics of the circuit are described.

  13. CZT strip detectors for imaging and spectroscopy: Collimated beam and ASIC readout experiments

    Energy Technology Data Exchange (ETDEWEB)

    Kurczynski, P. [Univ. of Maryland, College Park, MD (United States); Krizmanic, J.F.; Parsons, A. [Goddard Space Flight Center, Greenbelt, MD (United States)

    1996-12-31

    We report the status of ongoing investigations into Cadmium Zinc Telluride (CZT) strip detectors for application in hard x-ray astronomy. We have instrumented a nine strip by nine strip region of a two sided strip detector made in our detector fabrication facility. In order to measure the position resolution of our detectors, we have implemented a collimated beam that concentrates radiation to a spot size less than the strip width of our detector. We have also performed charge collection studies as a function of incident photon energy and bias voltage with a single sided, 100{mu}m pitch CZT strip detector wire bonded to an SVX ASIC charge amplifier. The detectors exhibited excellent strip uniformity in terms of photon count rate and spectroscopic information.

  14. Design Methodology: ASICs with complex in-pixel processing for Pixel Detectors

    Energy Technology Data Exchange (ETDEWEB)

    Fahim, Farah [Fermilab

    2014-10-31

    The development of Application Specific Integrated Circuits (ASIC) for pixel detectors with complex in-pixel processing using Computer Aided Design (CAD) tools that are, themselves, mainly developed for the design of conventional digital circuits requires a specialized approach. Mixed signal pixels often require parasitically aware detailed analog front-ends and extremely compact digital back-ends with more than 1000 transistors in small areas below 100μm x 100μm. These pixels are tiled to create large arrays, which have the same clock distribution and data readout speed constraints as in, for example, micro-processors. The methodology uses a modified mixed-mode on-top digital implementation flow to not only harness the tool efficiency for timing and floor-planning but also to maintain designer control over compact parasitically aware layout.

  15. Update on the high speed serializer ASIC development for ATLAS Liquid Argon calorimeter upgrade

    CERN Document Server

    Liu, T; The ATLAS collaboration

    2011-01-01

    We have been developing a serializer application-specific integrated circuit (ASIC) based on a commercial 0.25-μm silicon-on-sapphire (SOS) CMOS technology for the ATLAS liquid argon calorimeter front-end electronics upgrade. The first prototype, a 5 Gbps 16:1 serializer has been designed, fabricated, and tested in lab environment and in a 200 MeV proton beam. The test results indicate that the first prototype meets the design goals. The second prototype, a double-lane, 8 Gbps per lane serializer is under development. The post-layout simulation indicates that 8 Gbps is achievable. In this paper we present the design and the test results of the first prototype and the design and status of the second prototype.

  16. A high speed serializer ASIC for ATLAS Liquid Argon calorimeter upgrade

    CERN Document Server

    Liu, T; The ATLAS collaboration

    2014-01-01

    We have been developing a serializer application-specific integrated circuit (ASIC) based on a commercial 0.25-μm silicon-on-sapphire (SOS) CMOS technology for the ATLAS liquid argon calorimeter front-end electronics upgrade. The first prototype, a 5 Gbps 16:1 serializer has been designed, fabricated, and tested in lab environment and in 200 MeV proton beam. The test results indicate that the first prototype meets the design goals. The second prototype, a double-lane, 8 Gbps per lane serializer is under development. The post layout simulation indicates that 8 Gbps is achievable. In this paper we present the design and the test results of the first prototype and the design and status of the second prototype.

  17. Integrated power electronic converters and digital control

    CERN Document Server

    Emadi, Ali; Nie, Zhong

    2009-01-01

    Non-isolated DC-DC ConvertersBuck ConverterBoost ConverterBuck-Boost ConverterIsolated DC-DC ConvertersFlyback ConverterForward ConverterPush-Pull ConverterFull-Bridge ConverterHalf-Bridge ConverterPower Factor CorrectionConcept of PFCGeneral Classification of PFC CircuitsHigh Switching Frequency Topologies for PFCApplication of PFC in Advanced Motor DrivesIntegrated Switched-Mode Power ConvertersSwitched-Mode Power SuppliesThe Concept of Integrated ConverterDefinition of Integrated Switched-Mode Power Supplies (ISMPS)Boost-Type Integrated TopologiesGeneral Structure of Boost-Type Integrated T

  18. Science Enabling ASICs and FEEs for the JUICE and JEO Missions

    Science.gov (United States)

    Paschalidis, Nicholas; Sittler, Ed; Cooper, John; Christian, Eric; Moore, Tom

    2011-01-01

    A family of science enabling radiation hard Application Specific Integrated Circuits (ASICs), Front End Electronics (FEEs) and Event Processing Systems, with flight heritage on many NASA missions, is presented. These technologies play an important role in the miniaturization of instruments -and spacecraft systems- at the same time increasing performance and reducing power. The technologies target time of flight, position sensing, and energy measurements as well as standard housekeeping and telemetry functions for particle and fields instruments, but find applications in other instrument categories too. More specifically the technologies include: the TOF chip, 1D and 2D Delay Lines with MCP detectors, for high precision fast and low power time of flight and position sensing; the Energy chip for multichannel SSD readout with time over threshold and standard voltage read out for TDC and ADC digitization; Fast multi channel read out chip with commandable thresholds; the TRIO chip for multiplexed ADC and housekeeping etc. It should be mentioned that the ASICs include basic trigger capabilities to enable random event processing in a heavy background of penetrators and UV foreground. Typical instruments include time of flight versus energy and look angle particle analyzers such as: plasma composition, energetic particle, neutral atom imaging as well as fast plasma and deltaE/E ion/electron telescopes. Flight missions include: Cassini/LEMMS, IMAGE/HENA, MESSENGER/EPPS/MLA/X-ray/MLA, STEREO, PLUTO-NH/PEPSSI/LORI, IBEX-Lo, JUNO/JEDI, RBSP/RBSPICE, MMS/HPCA/EPD, SO/SIS. Given the proven capability on heavy radiation missions such as JUNO, MMS and RBSB, as well diverse long duration missions such as MESSENGER, PLUTO and Cassini, it is expected that these technologies will play an important role in the particle and fields (at least) instruments on the upcoming JUICE and JEO missions.

  19. Design methodology: edgeless 3D ASICs with complex in-pixel processing for pixel detectors

    Energy Technology Data Exchange (ETDEWEB)

    Fahim Farah, Fahim Farah [Northwestern U. (main); Deptuch, Grzegorz W. [Fermilab; Hoff, James R. [Fermilab; Mohseni, Hooman [Northwestern U. (main)

    2015-08-28

    The design methodology for the development of 3D integrated edgeless pixel detectors with in-pixel processing using Electronic Design Automation (EDA) tools is presented. A large area 3 tier 3D detector with one sensor layer and two ASIC layers containing one analog and one digital tier, is built for x-ray photon time of arrival measurement and imaging. A full custom analog pixel is 65μm x 65μm. It is connected to a sensor pixel of the same size on one side, and on the other side it has approximately 40 connections to the digital pixel. A 32 x 32 edgeless array without any peripheral functional blocks constitutes a sub-chip. The sub-chip is an indivisible unit, which is further arranged in a 6 x 6 array to create the entire 1.248cm x 1.248cm ASIC. Each chip has 720 bump-bond I/O connections, on the back of the digital tier to the ceramic PCB. All the analog tier power and biasing is conveyed through the digital tier from the PCB. The assembly has no peripheral functional blocks, and hence the active area extends to the edge of the detector. This was achieved by using a few flavors of almost identical analog pixels (minimal variation in layout) to allow for peripheral biasing blocks to be placed within pixels. The 1024 pixels within a digital sub-chip array have a variety of full custom, semi-custom and automated timing driven functional blocks placed together. The methodology uses a modified mixed-mode on-top digital implementation flow to not only harness the tool efficiency for timing and floor-planning but also to maintain designer control over compact parasitically aware layout. The methodology uses the Cadence design platform, however it is not limited to this tool.

  20. Wireless miniature implantable devices and ASICs for monitoring, treatment, and study of glaucoma and cardiac disease

    Science.gov (United States)

    Chow, Eric Y.

    Glaucoma affects about 65 million people and is the second leading cause of blindness in the world. Although the condition is irreversible and incurable, early detection is vital to slowing and even stopping the progression of the disease. Our work focuses on the design, fabrication, and assembly of a continuous active glaucoma intraocular pressure (IOP) monitor that provides clinicians with the necessary data to more accurately diagnose and treat patients. Major benefits of an active monitoring device include the potential to develop a closed-loop treatment system and to operate independently for extended periods of time. The fully wireless operation uses gigahertzfrequency electromagnetic wave propagation, which allows for an orientation independent transfer of power and data over reasonable distances. Our system is comprised of a MEMS capacitive sensor, capacitive power storage array, ASIC, and monopole antenna assembled into a biocompatible liquid crystal polymer (LCP) package. We have performed in vivo trials on rabbits, both chronic and acute, to validate system functionality, fully wireless feasibility, and biocompatibility. Heart failure (HF) affects approximately 2% of the adult population in developed countries and 6-10% of people over the age of 65. Continuous monitoring of blood pressure, flow, and chemistry from a minimally invasive device can serve as a diagnostic and early-warning system for cardiac health. We developed a miniaturized system attached to the outer surface of an FDA approved stent, used as both the antenna for wireless telemetry/powering and structural support. The system comprises of a MEMS pressure sensor, ASIC for the sensor interface and wireless capabilities, LCP substrate, and FDA approved stent. In vivo studies on pigs validated functionality and fully wireless operation and demonstrate the feasibility of a stent-based wireless implant for continuous monitoring of blood pressure as well as other parameters including oxygen, flow

  1. Advanced power electronics converters PWM converters processing AC voltages

    CERN Document Server

    dos Santos, Euzeli

    2014-01-01

    This book covers power electronics, in depth, by presenting the basic principles and application details, which can be used both as a textbook and reference book.  Introduces a new method to present power electronics converters called Power Blocks Geometry. Applicable for courses focusing on power electronics, power electronics converters, and advanced power converters. Offers a comprehensive set of simulation results to help understand the circuits presented throughout the book

  2. Nanostructure Neutron Converter Layer Development

    Science.gov (United States)

    Park, Cheol (Inventor); Sauti, Godfrey (Inventor); Kang, Jin Ho (Inventor); Lowther, Sharon E. (Inventor); Thibeault, Sheila A. (Inventor); Bryant, Robert G. (Inventor)

    2016-01-01

    Methods for making a neutron converter layer are provided. The various embodiment methods enable the formation of a single layer neutron converter material. The single layer neutron converter material formed according to the various embodiments may have a high neutron absorption cross section, tailored resistivity providing a good electric field penetration with submicron particles, and a high secondary electron emission coefficient. In an embodiment method a neutron converter layer may be formed by sequential supercritical fluid metallization of a porous nanostructure aerogel or polyimide film. In another embodiment method a neutron converter layer may be formed by simultaneous supercritical fluid metallization of a porous nanostructure aerogel or polyimide film. In a further embodiment method a neutron converter layer may be formed by in-situ metalized aerogel nanostructure development.

  3. Impedance source power electronic converters

    CERN Document Server

    Liu, Yushan; Ge, Baoming; Blaabjerg, Frede; Ellabban, Omar; Loh, Poh Chiang

    2016-01-01

    Impedance Source Power Electronic Converters brings together state of the art knowledge and cutting edge techniques in various stages of research related to the ever more popular impedance source converters/inverters. Significant research efforts are underway to develop commercially viable and technically feasible, efficient and reliable power converters for renewable energy, electric transportation and for various industrial applications. This book provides a detailed understanding of the concepts, designs, controls, and application demonstrations of the impedance source converters/inverters. Key features: Comprehensive analysis of the impedance source converter/inverter topologies, including typical topologies and derived topologies. Fully explains the design and control techniques of impedance source converters/inverters, including hardware design and control parameter design for corresponding control methods. Presents the latest power conversion solutions that aim to advance the role of pow...

  4. DC to DC converters: operation; Hacheurs: fonctionnement

    Energy Technology Data Exchange (ETDEWEB)

    Bernot, F. [Ecole d' Ingenieurs de Tours, 37 (France)

    2002-05-01

    This article deals with pulse width modulation (PWM) and pulse position modulation (PPM) DC to DC converters. A tri-phase PWM converter is made of 6 simple DC/DC converters grouped together into 3 reversible converters of the same type: 1 - single-quadrant voltage lowering converters (hydraulic analogy, study with ideal elements, full scheme with input and output filters); 2 - single-quadrant voltage raising converters (hydraulic analogy, operation); 3 - two quadrants reversible converters (structure construction, quadrants of operation, reversible converter connected to a DC motor); 4 - four-quadrants reversible converters; 5 - other converters structure (current converters and converters with intermediate storage, asymmetrical converters, converters with capacitive storage, insulated converters, resonating converters, status); 6 - conclusion. (J.S.)

  5. A thermochemical energy converter

    Energy Technology Data Exchange (ETDEWEB)

    Toyeguti, K.; Indzima, T.

    1982-08-09

    Mercury is used as the active mass of the anode in the converter and 0/sub 2/ is used as the active cathode material. The reaction of Mercury + 1/2 0/sub 2/-Hg0 occurs with a discharge. With heating to 500/sup 0/C the regeneration of the Mercury, Hg0 yields Mercury + 1/2 0/sub 2/, occurs. The device for performing the thermochenical conversion of energy contains an element body, an oxygen chamber, an oxygen electrode, a chamber with an alkaline liquid electrolyte, a separator, an auxiliary separator, an electrode and a chamber with the Mercury. The thermochemical reaction occurs in the reactor to which the Hg0 is transported along a pipe which has a refrigerator and a valve. The Mercury is fed into the element from a reservoir. The Mercury reduced in the reactor and in a reaction tower is fed into it through a closed cycle. The bellows is connected with the reactor by a pipe with a refrigerator. Through it the 0/sub 2/ goes in a closed cycle to the chamber. The current forming reactions are Hg + 20H-anion yields Hg0 + H/sub 2/0 + 2e and 1/2 0/sub 2/ + H/sub 2/0 + 2e yields 20H-anion. The voltage on the outleads of the element is approximately 0.3 volts.

  6. Design and test of a 64-channel charge measurement ASIC developed in CMOS 0.35 {mu}m technology

    Energy Technology Data Exchange (ETDEWEB)

    La Rosa, A. [Dipartimento di Fisica Sperimentale, Universita di Torino, Via P. Giuria 1, Turin 10125 (Italy); INFN, Via P. Giuria 1, Turin 10125 (Italy)], E-mail: larosa@to.infn.it; Mazza, G. [INFN, Via P. Giuria 1, Turin 10125 (Italy); Donetti, M. [INFN, Via P. Giuria 1, Turin 10125 (Italy); Fondazione CNAO, Via Caminadella 16, Milano 20123 (Italy); Marchetto, F. [INFN, Via P. Giuria 1, Turin 10125 (Italy); Luetto, L. [Dipartimento di Fisica Sperimentale, Universita di Torino, Via P. Giuria 1, Turin 10125 (Italy); Attili, A. [INFN, Via P. Giuria 1, Turin 10125 (Italy); Bourhaleb, F. [Dipartimento di Fisica Sperimentale, Universita di Torino, Via P. Giuria 1, Turin 10125 (Italy); Cirio, R.; Garella, M.A.; Giordanengo, S. [INFN, Via P. Giuria 1, Turin 10125 (Italy); Givehchi, N. [Dipartimento di Fisica Sperimentale, Universita di Torino, Via P. Giuria 1, Turin 10125 (Italy); INFN, Via P. Giuria 1, Turin 10125 (Italy); Iliescu, S.; Pardo, J. [INFN, Via P. Giuria 1, Turin 10125 (Italy); Pecka, A.; Peroni, C. [Dipartimento di Fisica Sperimentale, Universita di Torino, Via P. Giuria 1, Turin 10125 (Italy); INFN, Via P. Giuria 1, Turin 10125 (Italy); Pitta, G. [Fondazione TERA, Via Puccini 11, Novara 28100 (Italy)

    2007-12-21

    A 64-channel charge measurement (Application-Specific Integrated Circuit) ASIC has been designed and tested: it is intended to serve as a front-end electronic read-out for detectors to monitor and measure radiotherapeutical beams. The ASIC has been designed in a CMOS 0.35 {mu}m technology with particular attention to the linearity over a wide input range and can accept currents of both polarities. The linearity is better than 1.5% for a dynamic range of the input current between 500 pA and 3 {mu}A. For a charge resolution of 350 fC, the spread (r.m.s.) of the gain is less than 1%.

  7. Design and test of a 64-channel charge measurement ASIC developed in CMOS 0.35 μm technology

    Science.gov (United States)

    La Rosa, A.; Mazza, G.; Donetti, M.; Marchetto, F.; Luetto, L.; Attili, A.; Bourhaleb, F.; Cirio, R.; Garella, M. A.; Giordanengo, S.; Givehchi, N.; Iliescu, S.; Pardo, J.; Pecka, A.; Peroni, C.; Pittà, G.

    2007-12-01

    A 64-channel charge measurement (Application-Specific Integrated Circuit) ASIC has been designed and tested: it is intended to serve as a front-end electronic read-out for detectors to monitor and measure radiotherapeutical beams. The ASIC has been designed in a CMOS 0.35 μm technology with particular attention to the linearity over a wide input range and can accept currents of both polarities. The linearity is better than 1.5% for a dynamic range of the input current between 500 pA and 3 μA. For a charge resolution of 350 fC, the spread (r.m.s.) of the gain is less than 1%.

  8. Proposed electromagnetic wave energy converter

    Science.gov (United States)

    Bailey, R. L.

    1973-01-01

    Device converts wave energy into electric power through array of insulated absorber elements responsive to field of impinging electromagnetic radiation. Device could also serve as solar energy converter that is potentially less expensive and fragile than solar cells, yet substantially more efficient.

  9. A Radiation Hard Multi-Channel Digitizer ASIC for Operation in the Harsh Jovian Environment

    Science.gov (United States)

    Aslam, Shahid; Aslam, S.; Akturk, A.; Quilligan, G.

    2011-01-01

    ultimately impact the surface of Europa after the mission is completed. The current JEO mission concept includes a range of instruments on the payload, to monitor dynamic phenomena (such as Io's volcanoes and Jupiters atmosphere), map the Jovian magnetosphere and its interactions with the Galilean satellites, and characterize water oceans beneath the ice shells of Europa and Ganymede. The payload includes a low mass (3.7 Kg) and low power (< 5 W) Thermal Instrument (TI) concept for measuring possible warm thermal anomalies on Europa s cold surface caused by recent (< 10,000 years) eruptive activity. Regions of anomalously high heat flow will be identified by thermal mapping using a nadir pointing, push-broom filter radiometer that provides far-IR imagery in two broad band spectral wavelength regions, 8-20 m and 20-100 m, for surface temperature measurements with better than a 2 K accuracy and a spatial resolution of 250 m/pixel obtained from a 100 Km orbit. The temperature accuracy permits a search for elevated temperatures when combined with albedo information. The spatial resolution is sufficient to resolve Europa's larger cracks and ridge axial valleys. In order to accomplish the thermal mapping, the TI uses sensitive thermopile arrays that are readout by a custom designed low-noise Multi-Channel Digitizer (MCD) ASIC that resides very close to the thermopile linear array outputs. Both the thermopile array and the MCD ASIC will need to show full functionality within the harsh Jovian radiation environment, operating at cryogenic temperatures, typically 150 K to 170 K. In the following, a radiation mitigation strategy together with a low risk Radiation-Hardened-By-Design (RHBD) methodology using commercial foundry processes is given for the design and manufacture of a MCD ASIC that will meet this challenge.

  10. Impedance Source Power Electronic Converters

    DEFF Research Database (Denmark)

    Liu, Yushan; Abu-Rub, Haitham; Ge, Baoming

    Impedance Source Power Electronic Converters brings together state of the art knowledge and cutting edge techniques in various stages of research related to the ever more popular impedance source converters/inverters. Significant research efforts are underway to develop commercially viable...... control methods. Presents the latest power conversion solutions that aim to advance the role of power electronics into industries and sustainable energy conversion systems. Compares impedance source converter/inverter applications in renewable energy power generation and electric vehicles as well...... and technically feasible, efficient and reliable power converters for renewable energy, electric transportation and for various industrial applications. This book provides a detailed understanding of the concepts, designs, controls, and application demonstrations of the impedance source converters/inverters. Key...

  11. A Novel Front-End ASIC With Post Digital Filtering and Calibration for CZT-Based PET Detector

    Energy Technology Data Exchange (ETDEWEB)

    Gao, W.; Yin, J.; Li, C.; Zeng, H.; Gao, D. [Institute of Microelectronics, School of Computer Science and Techonology, Northwestern Polytechnical University, Xi' an (China); Hu, Y. [Institut Pluridiscipline Hubert Curien, CNRS/UDS/IN2P3, Strasbourg (France)

    2015-07-01

    This paper presents a novel front-end electronics based on a front-end ASIC with post digital filtering and calibration dedicated to CZT detectors for PET imaging. A cascade amplifier based on split-leg topology is selected to realize the charge-sensitive amplifier (CSA) for the sake of low noise performances and the simple scheme of the power supplies. The output of the CSA is connected to a variable-gain amplifier to generate the compatible signals for the A/D conversion. A multi-channel single-slope ADC is designed to sample multiple points for the digital filtering and shaping. The digital signal processing algorithms are implemented by a FPGA. To verify the proposed scheme, a front-end readout prototype ASIC is designed and implemented in 0.35 μm CMOS process. In a single readout channel, a CSA, a VGA, a 10-bit ADC and registers are integrated. Two dummy channels, bias circuits, and time controller are also integrated. The die size is 2.0 mm x 2.1 mm. The input range of the ASIC is from 2000 e{sup -} to 100000 e{sup -}, which is suitable for the detection of the X-and gamma ray from 11.2 keV to 550 keV. The linearity of the output voltage is less than 1 %. The gain of the readout channel is 40.2 V/pC. The static power dissipation is about 10 mW/channel. The above tested results show that the electrical performances of the ASIC can well satisfy PET imaging applications. (authors)

  12. Design and performances of a low-noise and radiation-hardened readout ASIC for CdZnTe detectors

    Science.gov (United States)

    Bo, Gan; Tingcun, Wei; Wu, Gao; Yongcai, Hu

    2016-06-01

    In this paper, we present the design and performances of a low-noise and radiation-hardened front-end readout application specific integrated circuit (ASIC) dedicated to CdZnTe detectors for a hard X-ray imager in space applications. The readout channel is comprised of a charge sensitive amplifier, a CR-RC shaping amplifier, an analog output buffer, a fast shaper, and a discriminator. An 8-channel prototype ASIC is designed and fabricated in TSMC 0.35-μm mixed-signal CMOS technology, the die size of the prototype chip is 2.2 × 2.2 mm2. The input energy range is from 5 to 350 keV. For this 8-channel prototype ASIC, the measured electrical characteristics are as follows: the overall gain of the readout channel is 210 V/pC, the linearity error is less than 2%, the crosstalk is less than 0.36%, The equivalent noise charge of a typical channel is 52.9 e- at zero farad plus 8.2 e- per picofarad, and the power consumption is less than 2.4 mW/channel. Through the measurement together with a CdZnTe detector, the energy resolution is 5.9% at the 59.5-keV line under the irradiation of the radioactive source 241Am. The radiation effect experiments show that the proposed ASIC can resist the total ionization dose (TID) irradiation of higher than 200 krad(Si). Project supported by the National Key Scientific Instrument and Equipment Development Project (No. 2011YQ040082), the National Natural Science Foundation of China (Nos. 11475136, 11575144, 61176094), and the Shaanxi Natural Science Foundation of China (No. 2015JM1016).

  13. Development and evaluation of an ultra-fast ASIC for future PET scanners using TOF-capable MPPC array detectors

    Energy Technology Data Exchange (ETDEWEB)

    Ambe, T., E-mail: hiro-a-be.n@akane.waseda.jp [Research Institute for Science and Engineering, Waseda University, 3-4-1, Okubo, Shinjuku, Tokyo (Japan); Ikeda, H. [ISAS/JAXA, 3-1-1, Yoshinodai, Chuo-ku, Sagamihara-shi, Kanagawa (Japan); Kataoka, J.; Matsuda, H.; Kato, T. [Research Institute for Science and Engineering, Waseda University, 3-4-1, Okubo, Shinjuku, Tokyo (Japan)

    2015-01-21

    We developed a front-end ASIC for future PET scanners with Time-Of-Flight (TOF) capability to be coupled with 4×4 Multi-Pixel Photon Counter (MPPC) arrays. The ASIC is designed based on the open-IP project proposed by JAXA and realized in TSMC 0.35 μm CMOS technology. The circuit comprises 16-channel, low impedance current conveyors for effectively acquiring fast MPPC signals. For precise measurement of the coincidence timing of 511-keV gamma rays, the leading-edge method was used to discriminate the signals. We first tested the time response of the ASIC by illuminating each channel of a MPPC array device 3×3 mm{sup 2} in size with a Pico-second Light Pulsar with a light emission peak of 655 nm and pulse duration of 54 ps (FWHM). We obtained 105 ps (FWHM) on average for each channel in time jitter measurements. Moreover, we compensated for the time lag of each channel with inner delay circuits and succeeded in suppressing about a 700-ps lag to only 15 ps. This paper reports TOF measurements using back-to-back 511-keV signals, and suggests that the ASIC can be a promising device for future TOF-PET scanners based on the MPPC array. - Highlights: • We developed a newly designed large-area monolithic MPPC array. • We obtained fine gain uniformity, and good energy and time resolutions when coupled to the LYSO scintillator. • We fabricated gamma-ray camera consisting of the MPPC array and the submillimeter pixelized LYSO and GGAG scintillators. • In the flood images, each crystal of scintillator matrices was clearly resolved. • Good energy resolutions for 662 keV gamma-rays for each LYSO and GGAG scintillator matrices were obtained.

  14. Test systems of the STS-XYTER2 ASIC: from wafer-level to in-system verification

    Science.gov (United States)

    Kasinski, Krzysztof; Zubrzycka, Weronika

    2016-09-01

    The STS/MUCH-XYTER2 ASIC is a full-size prototype chip for the Silicon Tracking System (STS) and Muon Chamber (MUCH) detectors in the new fixed-target experiment Compressed Baryonic Matter (CBM) at FAIR-center, Darmstadt, Germany. The STS assembly includes more than 14000 ASICs. The complicated, time-consuming, multi-step assembly process of the detector building blocks and tight quality assurance requirements impose several intermediate testing to be performed for verifying crucial assembly steps (e.g. custom microcable tab-bonding before wire-bonding to the PCB) and - if necessary - identifying channels or modules for rework. The chip supports the multi-level testing with different probing / contact methods (wafer probe-card, pogo-probes, in-system tests). A huge number of ASICs to be tested restricts the number and kind of tests possible to be performed within a reasonable time. The proposed architectures of test stand equipment and a brief summary of methodologies are presented in this paper.

  15. Inhibition of acid-induced apoptosis by targeting ASIC1a mRNA with short hairpin RNA

    Institute of Scientific and Technical Information of China (English)

    Xie-chuan WENG; Jian-quan ZHENG; Qing-e JIN; Xiao-yun MA

    2007-01-01

    Aim: To study the role of acid-sensing ion channel (ASIC) la in the cell death and apoptosis induced by extracellular acid in C6 glioma cells. Methods: The stable ASICla-silenced C6 cell line, built with RNA interference technology, were con-firmed by RT-PCR and Western blot analysis. The cell viability following acid exposure was analyzed with lactate dehydrogenase (LDH) and 3-(4,5-dimethylthiazol-2-yl)-2, 5-diphenyltetrazolium bromide (MTT) assay. The apoptotic cells dyed with Annexin-V and propidium iodide were measured with a flow cytometer, while the changes of cell cycle were also assayed. Results: The downregulation of ASIC 1 a proteins by stable transfection of short hairpin RNA decreased the cell death percentage and increased cell viability following acid exposure with LDH and the MTT assay. The rate of apoptosis was lower in the ASIC la-silenced cell line than that in the wild-type C6 cell line. The percentage of sub-G0 cells was lower in the ASICla-silenced C6 cells than that in the wild-type cells. Conclusion: Extracellular acid induced cell death and apoptosis viaASICla mechanisms in the C6 glioma cells.

  16. Radiation tolerant power converter controls

    CERN Document Server

    Todd, B; King, Q; Uznanski, S

    2012-01-01

    The Large Hadron Collider (LHC) at the European Organisation for Nuclear Research (CERN) is the world's most powerful particle collider. The LHC has several thousand magnets, both warm and super-conducting, which are supplied with current by power converters. Each converter is controlled by a purpose-built electronic module called a Function Generator Controller (FGC). The FGC allows remote control of the power converter and forms the central part of a closed-loop control system where the power converter voltage is set, based on the converter output current and magnet-circuit characteristics. Some power converters and FGCs are located in areas which are exposed to beam-induced radiation. There are numerous radiation induced effects, some of which lead to a loss of control of the power converter, having a direct impact upon the accelerator's availability. Following the first long shut down (LS1), the LHC will be able to run with higher intensity beams and higher beam energy. This is expected to lead to signifi...

  17. Power converter simulation and analysis

    Energy Technology Data Exchange (ETDEWEB)

    Ghazy, M.A.

    1989-01-01

    There has been a great deal of progress made in computer aided design and analysis in the power electronic field. Many of the simulation packages are inefficient and time consuming in simulating switching converters. This thesis proposes an efficient, simple, general simulation approach to simulate any power converter with less computation time and space requirements on computer. In this approach the equations of power converters are formulated using network topology. In this thesis several procedures have been explained for the steady-state computation of power electronic circuits. Also, the steady-state analyses have been accomplished by a new technique called Fourier series method. For a complete system consisting of converters, filters, and electric machines, the simulation is complicated if a frequency domain technique is used. This thesis introduces a better technique which decouples the system into subsystems and simulates it in the time domain. The design of power converters using optimization techniques is presented in this thesis. Finally, the theory of Variable Structured Systems has been applied to power converters. Sliding mode control for DC-DC and DC-AC power converters is introduced as a tool to accomplish desired characteristics.

  18. PWM DC/DC Converter

    OpenAIRE

    Chen, Juan

    2008-01-01

    This report is the result of a Master Thesis work done at Seaward Electronics Inc. in Beijing, China from June to December in 2007. The main goal for this thesis is to verify and improve the performance of Honey-PWM DC-DC converter, which has been fabricated by a standard 0.6um CMOS processes. The project was started with studying of Buck converter structure. After the understanding of the converter structure, the project goes in to the analyses phase for each sub-cells, including the theory,...

  19. Reading a GEM with a VLSI pixel ASIC used as a direct charge collecting anode

    CERN Document Server

    Bellazzini, R; Baldini, L; Bitti, F; Brez, A; Latronico, L; Massai, M M; Minuti, M; Omodei, N; Razzano, M; Sgro, C; Spandre, G; Costa, E; Soffitta, P

    2004-01-01

    In MicroPattern Gas Detectors (MPGD) when the pixel size is below 100 micron and the number of pixels is large (above 1000) it is virtually impossible to use the conventional PCB read-out approach to bring the signal charge from the individual pixel to the external electronics chain. For this reason a custom CMOS array of 2101 active pixels with 80 micron pitch, directly used as the charge collecting anode of a GEM amplifying structure, has been developed and built. Each charge collecting pad, hexagonally shaped, realized using the top metal layer of a deep submicron VLSI technology is individually connected to a full electronics chain (pre-amplifier, shaping-amplifier, sample and hold, multiplexer) which is built immediately below it by using the remaining five active layers. The GEM and the drift electrode window are assembled directly over the chip so the ASIC itself becomes the pixelized anode of a MicroPattern Gas Detector. With this approach, for the first time, gas detectors have reached the level of i...

  20. A 15 GSa/s, 1.5 GHz Bandwidth Waveform Digitizing ASIC

    CERN Document Server

    Oberla, E; Grabas, H; Frisch, H; Nishimura, K; Varner, G

    2013-01-01

    The PSEC4 custom integrated circuit was designed for the recording of fast waveforms for use in large-area time-of-flight detector systems. The ASIC has been fabricated using the IBM-8RF 0.13 micron CMOS process. On each of 6 analog channels, PSEC4 employs a switched capacitor array (SCA) 256 samples deep, a ramp-compare ADC with 10.5 bits of DC dynamic range, and a serial data readout with the capability of region-of-interest windowing to reduce dead time. The sampling rate can be adjusted between 4 and 15 Gigasamples/second [GSa/s] on all channels and is servo-controlled on-chip with a low-jitter delay-locked loop (DLL). The input signals are passively coupled on-chip with a -3 dB analog bandwidth of 1.5 GHz. The power consumption in quiescent sampling mode is less than 50 mW/chip; at a sustained trigger and readout rate of 50 kHz the chip draws 100 mW. After fixed-pattern pedestal subtraction, the uncorrected integral non-linearity is 0.15% over an 750 mV dynamic range. With a linearity correction, a full ...

  1. Double-differential recording and AGC using microcontrolled variable gain ASIC.

    Science.gov (United States)

    Rieger, Robert; Deng, Shin-Liang

    2013-01-01

    Low-power wearable recording of biopotentials requires acquisition front-ends with high common-mode rejection for interference suppression and adjustable gain to provide an optimum signal range to a cascading analogue-to-digital stage. A microcontroller operated double-differential (DD) recording setup and automatic gain control circuit (AGC) are discussed which reject common-mode interference and provide tunable gain, thus compensating for imbalance and variation in electrode interface impedance. Custom-designed variable gain amplifiers (ASIC) are used as part of the recording setup. The circuit gain and balance is set by the timing of microcontroller generated clock signals. Measured results are presented which confirm that improved common-mode rejection is achieved compared to a single differential amplifier in the presence of input network imbalance. Practical measured examples further validate gain control suitable for biopotential recording and power-line rejection for wearable ECG and EMG recording. The prototype front-end consumes 318 μW including amplifiers and microcontroller.

  2. Circuit design and simulation of a transmit beamforming ASIC for high-frequency ultrasonic imaging systems.

    Science.gov (United States)

    Athanasopoulos, Georgios I; Carey, Stephen J; Hatfield, John V

    2011-07-01

    This paper describes the design of a programmable transmit beamformer application-specific integrated circuit (ASIC) with 8 channels for ultrasound imaging systems. The system uses a 20-MHz reference clock. A digital delay-locked loop (DLL) was designed with 50 variable delay elements, each of which provides a clock with different phase from a single reference. Two phase detectors compare the phase difference of the reference clock with the feedback clock, adjusting the delay of the delay elements to bring the feedback clock signal in phase with the reference clock signal. Two independent control voltages for the delay elements ensure that the mark space ratio of the pulses remain at 50%. By combining a 10- bit asynchronous counter with the delays from the DLL, each channel can be programmed to give a maximum time delay of 51 μs with 1 ns resolution. It can also give bursts of up to 64 pulses. Finally, for a single pulse, it can adjust the pulse width between 9 ns and 100 ns by controlling the current flowing through a capacitor in a one-shot circuit, for use with 40-MHz and 5-MHz transducers, respectively.

  3. A silicon strip detector coupled to the RX64 ASIC for X-ray diagnostic imaging

    Energy Technology Data Exchange (ETDEWEB)

    Baldazzi, G.; Bollini, D.; Cabal Rodriguez, A.E.; Dabrowski, W.; Diaz Garcia, A.; Gambaccini, M.; Giubellino, P.; Gombia, M.; Grybos, P.; Idzik, M.; Marzari-Chiesa, A.; Montano, L.M.; Prino, F. E-mail: prino@to.infn.it; Ramello, L.; Sitta, M.; Swientek, K.; Taibi, A.; Tuffanelli, A.; Wheadon, R.; Wiacek, P

    2003-11-21

    First results from a silicon microstrip detector with 100 {mu}m pitch coupled to the RX64 ASIC are presented. The system is capable of single photon counting in digital X-ray imaging, with possible applications to dual energy mammography and angiography. The main features of the detecting system are low noise, good spatial resolution and high counting rate capability. The energy resolution and the conversion efficiency of the system are discussed, based on results obtained with fluorescence X-ray sources and quasi-monochromatic X-ray beams in the 8-36 keV energy range, with strips being either orthogonal or parallel to the incoming X-rays. We present also preliminary imaging results obtained with a plexiglass phantom with tiny cylindrical cavities filled with iodate solution, simulating patient vessels; in this case the X-ray beam has two components, respectively below and above the iodine K-edge at 33.17 keV.

  4. An ASIC for fast single photon counting in the LHCb RICH upgrade

    Science.gov (United States)

    Gotti, C.

    2017-03-01

    The LHCb experiment will be upgraded during the second LHC long shutdown (years 2019–2020) to operate at higher luminosity. The new triggerless architecture of LHCb requires data from the entire detector to be read out at 40 MHz. The basic element of the front-end electronics of the Ring Imaging Cherenkov (RICH) detector upgrade is the "Elementary Cell" (EC), a readout system for multianode photomultiplier tubes designed to minimise parasitic capacitance at the anodes, to obtain a fast readout with low noise and low crosstalk. At the heart of the EC is the CLARO, an 8 channel, low power and radiation hard front-end ASIC designed in 0.35 μm CMOS technology. Each channel compares the charge signals from the photomultiplier anodes with a programmable threshold, and gives a digital pulse at the output when the threshold is exceeded. Baseline recovery occurs in less than 25 ns for typical single photon signals. In the LHCb RICH upgrade environment, the chips will have to withstand radiation up to a total ionising dose of 2 kGy (200 krad) and neutron and hadron fluences up to 03×112 cm‑2 and following irradiation, the chips have been shown to tolerate such doses with a margin of safety.

  5. A 15 GSa/s, 1.5 GHz bandwidth waveform digitizing ASIC

    Energy Technology Data Exchange (ETDEWEB)

    Oberla, Eric, E-mail: ejo@uchicago.edu [Enrico Fermi Institute, University of Chicago, 5640 S. Ellis Avenue, Chicago, IL 60637 (United States); Genat, Jean-Francois; Grabas, Hervé; Frisch, Henry [Enrico Fermi Institute, University of Chicago, 5640 S. Ellis Avenue, Chicago, IL 60637 (United States); Nishimura, Kurtis; Varner, Gary [University of Hawai' i at Manoa, Watanabe Hall, 2505 Correa Road, Honolulu, HI (United States)

    2014-01-21

    The PSEC4 custom integrated circuit was designed for the recording of fast waveforms for use in large-area time-of-flight detector systems. The ASIC has been fabricated using the IBM-8RF 0.13μm CMOS process. On each of the six analog channels, PSEC4 employs a switched capacitor array (SCA) of 256 samples deep, a ramp-compare ADC with 10.5 bits of DC dynamic range, and a serial data readout with the capability of region-of-interest windowing to reduce dead time. The sampling rate can be adjusted between 4 and 15 Gigasamples/second (GSa/s) on all channels and is servo-controlled on-chip with a low-jitter delay-locked loop (DLL). The input signals are passively coupled on-chip with a −3 dB analog bandwidth of 1.5 GHz. The power consumption in quiescent sampling mode is less than 50 mW/chip; at a sustained trigger and a readout rate of 50 kHz the chip draws 100 mW. After fixed-pattern pedestal subtraction, the uncorrected integral non-linearity is 0.15% over a 750 mV dynamic range. With a linearity correction, a full 1 V signal voltage range is available. The sampling timebase has a fixed-pattern non-linearity with an RMS of 13%, which can be corrected for precision waveform feature extraction and timing.

  6. Systematic study of new types of Hamamatsu MPPCs read out with the NINO ASIC

    CERN Document Server

    Doroud, K; Williams, M C S; Yamamoto, K; Zichichi, A; Zuyeuski, R

    2014-01-01

    Over the last decade there have been commercial TOF-PET scanners constructed using Photo-Multiplier Tubes (PMT) that have achieved View the MathML source~500ps FWHM Coincidence Time Resolution (CTR). A new device known as the Silicon PhotoMultiplier (SiPM) has the potential to overcome some of the limitations of the PMT. Therefore implementing a SiPM based TOF-PET scanner is of high interest. Recently Philips has introduced a TOF-PET scanner that uses digital Silicon PhotoMultipliers (d-SiPMs) which has a CTR of 350 ps. Here we will report on the timing performance of two Hamamatsu 3×3 mm2 analogue-SiPMs read out with the NINO ASIC: this is an ultra-fast amplifier/discriminator with a differential architecture. The differential architecture is very important since the single-ended readout uses the ground as the signal return; as the ground is also the reference level for the discriminators, the result is high crosstalk and degraded time resolution. However differential readout allows the scaling up from a si...

  7. Development of the analog ASIC for multi-channel readout X-ray CCD camera

    CERN Document Server

    Nakajima, Hiroshi; Idehara, Toshihiro; Anabuki, Naohisa; Tsunemi, Hiroshi; Doty, John P; Ikeda, Hirokazu; Katayama, Haruyoshi; Kitamura, Hisashi; Uchihori, Yukio; 10.1016/j.nima.2010.12.174

    2011-01-01

    We report on the performance of an analog application-specific integrated circuit (ASIC) developed aiming for the front-end electronics of the X-ray CCDcamera system onboard the next X-ray astronomical satellite, ASTRO-H. It has four identical channels that simultaneously process the CCD signals. Distinctive capability of analog-to-digital conversion enables us to construct a CCD camera body that outputs only digital signals. As the result of the front-end electronics test, it works properly with low input noise of =<30 uV at the pixel rate below 100 kHz. The power consumption is sufficiently low of about 150 mW/chip. The input signal range of 720 mV covers the effective energy range of the typical X-ray photon counting CCD (up to 20 keV). The integrated non-linearity is 0.2% that is similar as those of the conventional CCDs in orbit. We also performed a radiation tolerance test against the total ionizing dose (TID) effect and the single event effect. The irradiation test using 60Co and proton beam showed ...

  8. Abstracts of the “GIORNATE DI CONIGLICOLTURA ASIC 2013”

    Directory of Open Access Journals (Sweden)

    GIORNATE DI CONIGLICOLTURA ASIC Forlì, Italy

    2013-06-01

    Full Text Available Onthe 10 and 11 of April, in Forlì (Italy it was held the 5th edition of the Italian Rabbit Days, product of the collaboration among ASIC (Italian Rabbit Scientific Association, ASPA (Animal Production Scientific Association and the Forlì Fair. The 1st day included a round table focused on “Which future for italian rabbit faming?”. During the 2nd day, there were presented 2 main lectures “Resources allocation in reproductive rabbit does: genetic strategies for a suitable performance”, by Pascual J.J., Savietto D., Cervera C., Baselga M. and “Controlling the rabbit digestive ecosystem to improve digestive health and efficacy”, by Combes S., Fortun-Lamothe L, Cauquil L., Gidenne T. which were previously presented at the last World Rabbit Congress. Moreover, 2 sessions of oral communications on Pathology and Zootechnics were held. Finally a Poster Session was through the 2 days. The meeting was attended by more than 80 participants, including researchers from France, Spain, and Hungary. A total of 2 main lectures, 10 oral communications and 6 posters were presented during the congress. Following are reported the abstracts of all contributions presented.

  9. A 15 GSa/s, 1.5 GHz bandwidth waveform digitizing ASIC

    Science.gov (United States)

    Oberla, Eric; Genat, Jean-Francois; Grabas, Hervé; Frisch, Henry; Nishimura, Kurtis; Varner, Gary

    2014-01-01

    The PSEC4 custom integrated circuit was designed for the recording of fast waveforms for use in large-area time-of-flight detector systems. The ASIC has been fabricated using the IBM-8RF 0.13 μm CMOS process. On each of the six analog channels, PSEC4 employs a switched capacitor array (SCA) of 256 samples deep, a ramp-compare ADC with 10.5 bits of DC dynamic range, and a serial data readout with the capability of region-of-interest windowing to reduce dead time. The sampling rate can be adjusted between 4 and 15 Gigasamples/second (GSa/s) on all channels and is servo-controlled on-chip with a low-jitter delay-locked loop (DLL). The input signals are passively coupled on-chip with a -3 dB analog bandwidth of 1.5 GHz. The power consumption in quiescent sampling mode is less than 50 mW/chip; at a sustained trigger and a readout rate of 50 kHz the chip draws 100 mW. After fixed-pattern pedestal subtraction, the uncorrected integral non-linearity is 0.15% over a 750 mV dynamic range. With a linearity correction, a full 1 V signal voltage range is available. The sampling timebase has a fixed-pattern non-linearity with an RMS of 13%, which can be corrected for precision waveform feature extraction and timing.

  10. The PASTA chip - A free-running readout ASIC for silicon strip sensors in PANDA

    Energy Technology Data Exchange (ETDEWEB)

    Goerres, Andre; Stockmanns, Tobias; Ritman, James [Institut fuer Kernphysik, Forschungszentrum Juelich, Juelich (Germany); Rivetti, Angelo [INFN Sezione di Torino, Torino (Italy); Collaboration: PANDA-Collaboration

    2014-07-01

    The PANDA experiment is a multi purpose detector, investigating hadron physics in the charm quark mass regime. It is one of the main experiments at the future FAIR accelerator facility, using pp annihilations from a 1.5-15 GeV/c anti-proton beam. Because of the broad physics spectrum and the similarity of event and background signals, PANDA does not rely on a hardware-level trigger decision. The innermost of PANDA's sub-systems is the Micro Vertex Detector (MVD), consisting of silicon pixel and strip sensors. The latter will be read out by a specialized, free-running readout front-end called PANDA Strip ASIC (PASTA). It has to face a high event rate of up to 40 kHz/ch in an radiation-intense environment. To fulfill the MVD's requirements, it has to give accurate timing information to incoming events (<10 ns) and determine the collected charge with an 8-bit precision. The design has to meet cooling and placing restrictions, leading to a very low power consumption (<4 mW/ch) and limited dimensions. Therefore, a simple, time-based readout approach is chosen. In this talk, the conceptual design of the front-end is presented.

  11. The PASTA chip. A free-running readout ASIC for silicon strip sensors in PANDA

    Energy Technology Data Exchange (ETDEWEB)

    Goerres, Andre; Stockmanns, Tobias; Ritman, James [Forschungszentrum Juelich GmbH, Juelich (Germany); Rivetti, Angelo [INFN Sezione di Torino, Torino (Italy); Collaboration: PANDA-Collaboration

    2015-07-01

    The PANDA experiment is a multi purpose detector, investigating hadron physics in the charm quark mass regime. It is one of the main experiments at the future FAIR accelerator facility, using anti pp annihilations from a 1.5-15 GeV/c anti-proton beam. Because of the broad physics spectrum and the similarity of event and background signals, PANDA does an event selection based on the complete raw data of the detector. The innermost of PANDA's sub-systems is the Micro Vertex Detector (MVD), consisting of silicon pixel and strip sensors. The latter will be read out by a specialized, free-running readout front-end called PANDA Strip ASIC (PASTA). It has to face a high event rate of up to 40 kHz/ch in an radiation-intense environment. To fulfill the MVD's requirements, it has to give accurate timing information to incoming events (<10 ns) and determine the collected charge with an 8-bit precision. All this has to be done with a very low power design (<4 mW/ch) on a small footprint with less than 21 mm{sup 2} and 60 μm input pitch for 64 channels per chip. Therefore, a simple, time-based readout approach with two independent thresholds is chosen. In this talk, the conceptual design of the full front-end and some aspects of the digital part are presented.

  12. Sensor-based whole-arm obstacle avoidance utilizing ASIC technology

    Science.gov (United States)

    Wintenberg, A. L.; Ericson, M. N.; Babcock, S. M.; Armstrong, G. A.; Britton, C. L., Jr.; Butler, P. L.; Hamel, W. R.; Newport, D. F.

    Operation of manipulator systems in poorly defined work environments often presents a significant hazard to both the robotic assembly and the environment. In applications relating to the Environmental Restoration and Waste Management (ER&WM) Program, many of the environments are considered hazardous, both, in the structure and composition of the environment. Use of a sensing system that provides information to the manipulator control unit regarding obstacles in close proximity will provide protection against collisions. A hierarchical design and implementation of a whole-arm obstacle avoidance system is presented. The system is based on capacitive sensors configured as bracelets for proximity sensing. Each bracelet contains a number of sensor nodes and a processor for sensor node control and readout, and communications with a higher level host, common to all bracelets. The host controls the entire sensing network and communicates proximity information to the manipulator controller. The overall architecture of this system is discussed with detail on the individual system modules. Details of an application specific integrated circuit (ASIC) designed to implement the sensor node electronics are presented. Justifications for the general measurement methods and associated implementation are discussed. Additionally, the current state of development including measured data is presented.

  13. An important step forward in continuous spectroscopic imaging of ionising radiations using ASICs

    Energy Technology Data Exchange (ETDEWEB)

    Fessler, P. [11 rue Rabelais, 92170 Vanves (France); Coffin, J. [Institut de Recherches Subatomiques, B.P. 28, 67037 Strasbourg (France); Eberle, H. [Institut de Recherches Subatomiques, B.P. 28, 67037 Strasbourg (France); Raad Iseli, C. de [Smart Silicon Systems SA, Ch. de la Graviere 6, CH-1007 Lausanne (Switzerland); Hilt, B. [Universite de Haute-Alsace, GRPHE, 61, rue Albert Camus, 68093 Mulhouse (France); Huss, D. [Universite de Haute-Alsace, GRPHE, 61, rue Albert Camus, 68093 Mulhouse (France); Krummenacher, F. [Smart Silicon Systems SA, Ch. de la Graviere 6, CH-1007 Lausanne (Switzerland); Lutz, J.R. [Institut de Recherches Subatomiques, B.P. 28, 67037 Strasbourg (France); Prevot, G. [Institut de Recherches Subatomiques, B.P. 28, 67037 Strasbourg (France); Renouprez, A. [Institut de Recherche sur la Catalyse, 2 Avenue Albert Einstein, 69626 Villeurbanne (France); Sigward, M.H. [Institut de Recherches Subatomiques, B.P. 28, 67037 Strasbourg (France); Schwaller, B. [Universite de Haute-Alsace, GRPHE, 61, rue Albert Camus, 68093 Mulhouse (France); Voltolini, C. [Institut de Recherches Subatomiques, B.P. 28, 67037 Strasbourg (France)

    1999-01-21

    Characterization results are given for an original ASIC allowing continuous acquisition of ionising radiation images in spectroscopic mode. Ionising radiation imaging in general and spectroscopic imaging in particular must primarily be guided by the attempt to decrease statistical noise, which requires detection systems designed to allow very high counting rates. Any source of dead time must therefore be avoided. Thus, the use of on-line corrections of the inevitable dispersion of characteristics between the large number of electronic channels of the detection system, shall be precluded. Without claiming to achieve ultimate noise levels, the work described is focused on how to prevent good individual acquisition channel noise performance from being totally destroyed by the dispersion between channels without introducing dead times. With this goal, we developed an automatic charge amplifier output voltage offset compensation system which operates regardless of the cause of the offset (detector or electronic). The main performances of the system are the following: the input equivalent noise charge is 190 e rms (input non connected, peaking time 500 ns), the highest gain is 255 mV/fC, the peaking time is adjustable between 200 ns and 2 {mu}s and the power consumption is 10 mW per channel. The agreement between experimental data and theoretical simulation results is excellent.

  14. CLARO-CMOS, a very low power ASIC for fast photon counting with pixellated photodetectors

    Science.gov (United States)

    Carniti, P.; De Matteis, M.; Giachero, A.; Gotti, C.; Maino, M.; Pessina, G.

    2012-11-01

    The CLARO-CMOS is an application specific integrated circuit (ASIC) designed for fast photon counting with pixellated photodetectors such as multi-anode photomultiplier tubes (Ma-PMT), micro-channel plates (MCP), and silicon photomultipliers (SiPM). The first prototype has four channels, each with a charge sensitive amplifier with settable gain and a discriminator with settable threshold, providing fast hit information for each channel independently. The design was realized in a long-established, stable and inexpensive 0.35 μm CMOS technology, and provides outstanding performance in terms of speed and power dissipation. The prototype consumes less than 1 mW per channel at low rate, and less than 2 mW at an event rate of 10 MHz per channel. The recovery time after each pulse is less than 25 ns for input signals within a factor of 10 above threshold. Input referred RMS noise is about 7.7 ke- (1.2 fC) with an input capacitance of 3.3 pF. With this value of input capacitance a timing resolution down to 10 ps RMS was measured for pulser signals of a few million electrons, corresponding to the single photon response for these detectors.

  15. CLARO-CMOS, a very low power ASIC for fast photon counting with pixellated photodetectors

    CERN Document Server

    Carniti, Paolo

    2012-01-01

    The CLARO-CMOS is an application specific integrated circuit (ASIC) designed for fast photon counting with pixellated photodetectors such as multi-anode photomultiplier tubes (Ma-PMT), micro-channel plates (MCP), and silicon photomultipliers (SiPM). The first prototype has four channels, each with a charge sensitive amplifier with settable gain and a discriminator with settable threshold, providing fast hit information for each channel independently. The design was realized in a long-established, stable and inexpensive 0.35 um CMOS technology, and provides outstanding performance in terms of speed and power dissipation. The prototype consumes less than 1 mW per channel at low rate, and less than 2 mW at an event rate of 10 MHz per channel. The recovery time after each pulse is less than 25 ns for input signals within a factor of 10 above threshold. Input referred RMS noise is about 7.7 ke^- (1.2 fC) with an input capacitance of 3.3 pF. Thanks to the low noise and high speed, a timing resolution down to 10 ps ...

  16. A pixel detector asic for dosimetry using time-over-threshold energy measurements

    CERN Document Server

    Wong, W S; Ballabriga, R; Bohnel, M; Campbell, M; Heijne, E; Llopart, X; Michel, T; Munster, I; Plackett, R; Sievers, P; Takoukam, P; Tlustos, L; Valerio, P

    2011-01-01

    In this work we present the design of a chip which provides the readout of a highly segmented diode array, in which signals induced by individual X-ray photons are processed discretely. There are several benefits to this approach, including the ability to achieve a high signal to noise ratio due to the inherently low sensor capacitance, and the suppression of background noise (e.g. dark current) using an analogue threshold. The segmentation also ensures a linear behaviour even at very high dose rates. A time over threshold (ToT) energy measurement technique provides an immediate digital value corresponding to the energy deposited onto the diode by each individual photon. Deadtime-free operation is achieved by reading out a subset of the detector segments at a time while the rest of the detector continues to process signals. This paper describes the application-specific integrated circuit (ASIC) chip which was designed to provide pre-processing of photo-induced signals in the detector and readout of the proces...

  17. Fatalic, a very-front-end Asic for the ATLAS Tile Calorimeter

    CERN Document Server

    Manen, Samuel Pierre; The ATLAS collaboration

    2016-01-01

    Abstract—The ATLAS Collaboration has started a vast program of upgrades in the context of high-luminosity LHC (HLLHC) forseen in 2024. The current readout electronics of every subdetector, including the Tile Calorimeter (TileCal), must be upgraded to comply with the new specifications aiming for the future operating conditions. The ASIC described in this document, named Front-end ATlAs tiLe Integrated Circuit (FATALIC), has been developed to fulfil the requirements of the TileCal upgrade. FATALIC is based on a 130 nm CMOS technology and performs the complete processing of the signal, including amplification, shaping and digitization. The first stage is a current conveyor which splits the input signal into three ranges, allowing to deal with a large dynamic range (from 25 fC up to 1.2 nC). Each current conveyor output is followed by a shaper and a dedicated pipeline 12 bit ADC operating at 40 MHz. Measurements show a non-linearity at the percent level for a typical input charge of interest. The noise of the ...

  18. Results of a combined monolithic crystal and an array of ASICs controlled SiPMs

    Energy Technology Data Exchange (ETDEWEB)

    Conde, P.; González, A.J., E-mail: agonzalez@i3m.upv.es; Hernández, L.; Bellido, P.; Iborra, A.; Crespo, E.; Moliner, L.; Rigla, J.P.; Rodríguez-Álvarez, M.J.; Sánchez, F.; Seimetz, M.; Soriano, A.; Vidal, L.F.; Benlloch, J.M.

    2014-01-11

    In this work we present the energy and spatial resolutions we have obtained for a γ-ray detector based on a monolithic LYSO crystal coupled to an array of 256 SiPMs. Two crystal configurations of the same trapezoidal shape have been tried. In one approach all surfaces were black painted but the exit one facing the photosensor array which was polished. The other approach included a retroreflector (RR) layer coupled to the entrance face of the crystal powering the amount of transmitted light to the photosensors. Two coupling media between the scintillator and the SiPM array were used, namely direct coupling by means of optical grease and coupling through an array of light guides. Since the same operational voltage was supplied to the entire array, it was needed to equalize their gains before feeding their signals to the Data Acquisition system. Such a job was performed by means of 4 scalable Application Specific Circuits (ASICs). An energy resolution of about 24.4% has been achieved for the direct coupling with the RR layer together with a spatial resolution of approximately 2.9 mm at the detector center. With the light guides coupling the effects of image compression at the edges are significantly minimized, but worsening the energy resolution to about 33.1% with a spatial resolution nearing 4 mm at the detector center.

  19. Time-to-digital converters

    CERN Document Server

    Henzler, Stephan

    2010-01-01

    This text covers the fundamentals of time-to-digital converters on analog and digital conversion principles. It includes a theoretical investigation into quantization, linearity, noise and variability, and it details a range of advanced TDC architectures.

  20. Laser system with wavelength converter

    DEFF Research Database (Denmark)

    2012-01-01

    The present invention relates to an apparatus comprising a diode laser (10) providing radiation in a first wavelength interval, a radiation conversion unit (12) having an input and an output, the radiation converter configured to receive the radiation in the first wavelength interval from the diode...... laser at the input, the radiation conversion unit configured to convert the radiation in the first wavelength interval to radiation in a second wavelength interval and the output configured to output the converted radiation, the second wavelength interval having one end point outside the first...... wavelength interval. Further, the invention relates to a method of optically pumping a target laser (14) in a laser system, the laser system comprising a laser source providing radiation at a first frequency, the laser source being optically connected to an input of a frequency converter, the frequency...

  1. The charge pump PLL clock generator designed for the 1.56 ns bin size time-to-digital converter pixel array of the Timepix3 readout ASIC

    CERN Document Server

    Fu, Y et al.

    2014-01-01

    Timepix3 is a newly developed pixel readout chip which is expected to be operated in a wide range of gaseous and silicon detectors. It is made of 256×256 pixels organized in a square pixel-array with 55 µm pitch. Oscillators running at 640 MHz are distributed across the pixel-array and allow for a highly accurate measurement of the arrival time of a hit. This paper concentrates on a low-jitter phase locked loop (PLL) that is located in the chip periphery. This PLL provides a control voltage which regulates the actual frequency of the individual oscillators, allowing for compensation of process, voltage, and temperature variations.

  2. Radiation tolerant power converter controls

    Science.gov (United States)

    Todd, B.; Dinius, A.; King, Q.; Uznanski, S.

    2012-11-01

    The Large Hadron Collider (LHC) at the European Organisation for Nuclear Research (CERN) is the world's most powerful particle collider. The LHC has several thousand magnets, both warm and super-conducting, which are supplied with current by power converters. Each converter is controlled by a purpose-built electronic module called a Function Generator Controller (FGC). The FGC allows remote control of the power converter and forms the central part of a closed-loop control system where the power converter voltage is set, based on the converter output current and magnet-circuit characteristics. Some power converters and FGCs are located in areas which are exposed to beam-induced radiation. There are numerous radiation induced effects, some of which lead to a loss of control of the power converter, having a direct impact upon the accelerator's availability. Following the first long shut down (LS1), the LHC will be able to run with higher intensity beams and higher beam energy. This is expected to lead to significantly increased radiation induced effects in materials close to the accelerator, including the FGC. Recent radiation tests indicate that the current FGC would not be sufficiently reliable. A so-called FGClite is being designed to work reliably in the radiation environment in the post-LS1 era. This paper outlines the concepts of power converter controls for machines such as the LHC, introduces the risks related to radiation and a radiation tolerant project flow. The FGClite is then described, with its key concepts and challenges: aiming for high reliability in a radiation field.

  3. Wave energy converter test application

    OpenAIRE

    Hottola, Niko

    2016-01-01

    This thesis was made for wave energy company Wello Oy. Given assignment was to find the suitable generator and frequency converter for a wave energy converter test application. The primary objective was to find a suitable generator for direct drive, in order to avoid the weight of the test application rising too high. In this thesis the possible machine types for test application are presented and what are their advenatages and disadvantages. In addition, the operation of the frequency co...

  4. Boron nitride converted carbon fiber

    Science.gov (United States)

    Rousseas, Michael; Mickelson, William; Zettl, Alexander K.

    2016-04-05

    This disclosure provides systems, methods, and apparatus related to boron nitride converted carbon fiber. In one aspect, a method may include the operations of providing boron oxide and carbon fiber, heating the boron oxide to melt the boron oxide and heating the carbon fiber, mixing a nitrogen-containing gas with boron oxide vapor from molten boron oxide, and converting at least a portion of the carbon fiber to boron nitride.

  5. Photoelectric converters with quantum coherence

    OpenAIRE

    Su, Shan-He; Sun, Chang-Pu; Li, Sheng-Wen; Chen, Jin-Can

    2016-01-01

    Photon impingement is capable of liberating electrons in electronic devices and driving the electron flux from the lower chemical potential to higher chemical potential. Previous studies hinted that the thermodynamic efficiency of a nano-sized photoelectric converter at maximum power is bounded by the Curzon-Ahlborn efficiency. In this study, we apply quantum effects to design a photoelectric converter based on a three-level quantum dot (QD) interacting with fermionic baths and photons. We sh...

  6. Transformerless dc-Isolated Converter

    Science.gov (United States)

    Rippel, Wally E.

    1987-01-01

    Efficient voltage converter employs capacitive instead of transformer coupling to provide dc isolation. Offers buck/boost operation, minimal filtering, and low parts count, with possible application in photovoltaic power inverters, power supplies and battery charges. In photovoltaic inverter circuit with transformerless converter, Q2, Q3, Q4, and Q5 form line-commutated inverter. Switching losses and stresses nil because switching performed when current is zero.

  7. Radiation effects on DC-DC Converters

    Science.gov (United States)

    Zhang, Dexin; Attia, John O.; Kankam, Mark D. (Technical Monitor)

    2000-01-01

    DC-DC switching converters are circuits that can be used to convert a DC voltage of one value to another by switching action. They are increasing being used in space systems. Most of the popular DC-DC switching converters utilize power MOSFETs. However power MOSFETs, when subjected to radiation, are susceptible to degradation of device characteristics or catastrophic failure. This work focuses on the effects of total ionizing dose on converter performance. Four fundamental switching converters (buck converter, buck-boost converter, cuk converter, and flyback converter) were built using Harris IRF250 power MOSFETs. These converters were designed for converting an input of 60 volts to an output of about 12 volts with a switching frequency of 100 kHz. The four converters were irradiated with a Co-60 gamma source at dose rate of 217 rad/min. The performances of the four converters were examined during the exposure to the radiation. The experimental results show that the output voltage of the converters increases as total dose increases. However, the increases of the output voltage were different for the four different converters, with the buck converter and cuk converter the highest and the flyback converter the lowest. We observed significant increases in output voltage for cuk converter at a total dose of 24 krad (si).

  8. Binary/BCD-to-ASCII data converter

    Science.gov (United States)

    Miller, A. J.

    1977-01-01

    Converter inputs multiple precision binary words, converts data to multiple precision binary-coded decimal, and routes data back to computer. Converter base can be readily changed without need for new gate structure for each base changeover.

  9. Development of a low noise readout ASIC for CZT detectors for gamma-ray spectroscopy applications

    Science.gov (United States)

    Luo, J.; Deng, Z.; Wang, G.; Li, H.; Liu, Y.

    2012-08-01

    A multi-channel readout ASIC for pixelated CZT detectors has been developed for gamma-ray spectroscopy applications. Each channel consists of a low noise dual-stage charge sensitive amplifier (CSA), a CR-(RC)4 semi-Gaussian shaper and a class-AB output buffer. The equivalent noise charge (ENC) of input PMOS transistor is optimized for 5 pF input capacitance and 1 μs peaking time using gm/ID design methodology. The gain can be adjusted from 100 mV/fC to 400 mV/fC and the peaking time can be adjusted from 1 μs to 4 μs. A 16-channel chip has been designed and fabricated in 0.35 μm 2P4M CMOS technology. The test results show that the chip works well and fully satisfies the design specifications. The ENC was measured to be 72 e + 26 e/pF at 1 μs peaking time and 86 e + 20 e/pF at 4 μs peaking time. The non-uniformity of the channel gain and ENC was less than ±12% and ±11% respectively for 16 channels in one chip. The chip was also tested with a pixelated CZT detector at room temperature. The measured energy resolution at 59.5 keV photopeak of 241Am and 122 keV photopeak of 57Co were 4.5% FWHM and 2.8% FWHM for the central area pixels, respectively.

  10. Systematic study of new types of Hamamatsu MPPCs read out with the NINO ASIC

    Energy Technology Data Exchange (ETDEWEB)

    Doroud, K. [Museo Storico della Fisica e Centro Studi e Ricerche E. Fermi, Roma (Italy); Rodriguez, A. [CERN, Geneva (Switzerland); ICSC World Laboratory, Geneva (Switzerland); Williams, M.C.S., E-mail: crispin.williams@cern.ch [CERN, Geneva (Switzerland); INFN and Dipartimento di Fisica e Astronomia, Università di Bologna (Italy); Yamamoto, K. [Solid State Division, Hamamatsu Photonics K.K., Hamamatsu (Japan); Zichichi, A. [Museo Storico della Fisica e Centro Studi e Ricerche E. Fermi, Roma (Italy); CERN, Geneva (Switzerland); INFN and Dipartimento di Fisica e Astronomia, Università di Bologna (Italy); Zuyeuski, R. [CERN, Geneva (Switzerland); ICSC World Laboratory, Geneva (Switzerland)

    2014-07-01

    Over the last decade there have been commercial TOF-PET scanners constructed using Photo-Multiplier Tubes (PMT) that have achieved ∼500ps FWHM Coincidence Time Resolution (CTR). A new device known as the Silicon PhotoMultiplier (SiPM) has the potential to overcome some of the limitations of the PMT. Therefore implementing a SiPM based TOF-PET scanner is of high interest. Recently Philips has introduced a TOF-PET scanner that uses digital Silicon PhotoMultipliers (d-SiPMs) which has a CTR of 350 ps. Here we will report on the timing performance of two Hamamatsu 3×3 mm{sup 2} analogue-SiPMs read out with the NINO ASIC: this is an ultra-fast amplifier/discriminator with a differential architecture. The differential architecture is very important since the single-ended readout uses the ground as the signal return; as the ground is also the reference level for the discriminators, the result is high crosstalk and degraded time resolution. However differential readout allows the scaling up from a single cell to a multi-cell device with no loss of time resolution; this becomes increasingly important for the highly segmented detectors that are being built today, both for particle and for medical instrumentation. We obtained excellent results for both the Single Photon Time Resolution (SPTR) and for the CTR using a LYSO crystal of 15 mm length. Such a crystal length has sufficient detection efficiency for 511 keV gammas to make an excellent PET device. The results presented here are proof that a TOF-PET detector with a CTR of 175 ps is indeed possible. This is the first step that defines the starting point of our SuperNINO project.

  11. MUSIC: An 8 channel readout ASIC for SiPM arrays

    Science.gov (United States)

    Gómez, Sergio; Gascón, David; Fernández, Gerard; Sanuy, Andreu; Mauricio, Joan; Graciani, Ricardo; Sanchez, David

    2016-04-01

    This paper presents an 8 channel ASIC for SiPM anode readout based on a novel low input impedance current conveyor (under patent1). This Multiple Use SiPM Integrated Circuit (MUSIC) has been designed to serve several purposes, including, for instance, the readout of SiPM arrays for some of the Cherenkov Telescope Array (CTA) cameras. The current division scheme at the very front end part of the circuit splits the input current into differently scaled copies which are connected to independent current mirrors. The circuit contains a tunable pole zero cancellation of the SiPM recovery time constant to deal with sensors from different manufacturers. Decay times up to 100 ns are supported covering most of the available SiPM devices in the market. MUSIC offers three main features: (1) differential output of the sum of the individual input channels; (2) 8 individual single ended analog outputs and; (3) 8 individual binary outputs. The digital outputs encode the amount of collected charge in the duration of the digital signal using a time over threshold technique. For each individual channel, the user must select the analog or digital output. Each functionality, the signal sum and the 8 A/D outputs, include a selectable dual-gain configuration. Moreover, the signal sum implements dual-gain output providing a 15 bit dynamic range. Full die simulation results of the MUSIC designed using AMS 0.35 µm SiGe technology are presented: total die size of 9 mm2, 500 MHz bandwidth for channel sum and 150 MHz bandwidth for A/D channels, low input impedance (≍32 Ω), single photon output pulse width at half maximum (FWHM) between 5 and 10 ns and with a power consumption of ≍ 30 mW/ch plus ≍ 200 mW for the 8 ch sum. Encapsulated prototype samples of the MUSIC are expected by March 2016.

  12. PWM Converter Power Density Barriers

    Science.gov (United States)

    Kolar, Johann W.; Drofenik, Uwe; Biela, Juergen; Heldwein, Marcelo; Ertl, Hans; Friedli, Thomas; Round, Simon

    Power density of power electronic converters has roughly doubled every 10 years since 1970. Behind this trajectory is the continuous advancement of power semiconductor devices, which has increased the converter switching frequencies by a factor of 10 every decade. However, today's cooling concepts and passive components are major barriers for a continuation of this trend. To identify such technological barriers, this paper investigates the volume of the cooling system and passive components as a function of the switching frequency for power electronic converters and determines the switching frequency that minimizes the total volume. A power density limit of 28kW/dm3 at 300kHz is calculated for an isolated DC-DC converter, 44kW/dm3 at 820kHz for a three-phase unity power factor PWM rectifier, and 26kW/dm3 at 21kHz for a sparse matrix converter. For single-phase AC-DC conversion a general limit of 35kW/dm3 results from the DC link capacitor. These power density limits highlight the need to broaden the scope of power electronics research to include cooling systems, high frequency electromagnetics, interconnection and packaging technology, and multi-domain modelling and simulation to ensure further advancement along the power density trajectory.

  13. Detector control and data acquisition for the wide field infrared survey telescope (WFIRST) with a custom ASIC

    Science.gov (United States)

    Smith, Brian; Loose, Markus; Alkire, Greg; Joshi, Atul; Kelly, Daniel; Siskind, Eric; Rossetti, Dino; Mah, Jonathan; Cheng, Edward; Miko, Laddawan; Luppino, Gerard; Culver, Harry; Wollack, Edward; Content, David

    2016-07-01

    The Wide-Field Infrared Survey Telescope (WFIRST) will have the largest near-IR focal plane ever flown by NASA, a total of 18 4K x 4K devices. The project has adopted a system-level approach to detector control and data acquisition where 1) control and processing intelligence is pushed into components closer to the detector to maximize signal integrity, 2) functions are performed at the highest allowable temperatures, and 3) the electronics are designed to ensure that the intrinsic detector noise is the limiting factor for system performance. For WFIRST, the detector arrays operate at 90 to 100 K, the detector control and data acquisition functions are performed by a custom ASIC at 150 to 180 K, and the main data processing electronics are at the ambient temperature of the spacecraft, notionally 300 K. The new ASIC is the main interface between the cryogenic detectors and the warm instrument electronics. Its single-chip design provides basic clocking for most types of hybrid detectors with CMOS ROICs. It includes a flexible but simple-to-program sequencer, with the option of microprocessor control for more elaborate readout schemes that may be data-dependent. All analog biases, digital clocks, and analog-to-digital conversion functions are incorporated and are connected to the nearby detectors with a short cable that can provide thermal isolation. The interface to the warm electronics is simple and robust through multiple LVDS channels. It also includes features that support parallel operation of multiple ASICs to control detectors that may have more capability or requirements than can be supported by a single chip.

  14. Post combustion in converter steelmaking

    Energy Technology Data Exchange (ETDEWEB)

    Oghbasilasie, H.; Holappa, L.

    1997-12-31

    The purpose of this work is to study the fundamentals of post combustion and the effect of different process parameters on the post combustion ratio (PCR) and heat transfer efficiency (HTE) in converter steelmaking process. The PCR and HTE have been determined under normal operating conditions. Trials assessed the effect of lance height, vessel volume, foaming slag and pellet additions on PCR and HTE. Based on enthalpy considerations, post combustion of CO gas is regarded as one of the most effective means of increasing the heat supply to the BOP. The thermodynamic study of gas-metal-slag reactions gives the limiting conditions for post combustion inside the converter reactor. Different process parameters influencing both thermodynamic equilibria and kinetic conditions can greatly affect the post combustion ratio. Different features of converter processes as well smelting reduction processes utilizing post combustion have been reviewed. (orig.) SULA 2 Research Programme; 26 refs.

  15. KLauS: a low power Silicon Photomultiplier charge readout ASIC in 0.18 UMC CMOS

    Science.gov (United States)

    Briggl, K.; Chen, H.; Schimansky, D.; Shen, W.; Stankova, V.; Schultz-Coulon, H. C.

    2016-03-01

    We present the development of a low power Silicon Photomultiplier charge readout ASIC for an imaging calorimeter at a future linear collider. The analog front-end is designed to achieve sufficient signal-to-noise ratio for single pixel signals using low gain SiPMs, while allowing charge measurements over the full dynamic range of the sensors. The front-end consists of an input stage, two charge measurement branches and a fast comparator. A SAR ADC with a resolution of 10 bit digitizes the pulse height information. An additional pipelined SAR stage allows to increase the quantization resolution to 12 bit for calibration measurements.

  16. Simplified design of data converters

    CERN Document Server

    Lenk, John

    1997-01-01

    Simplified Design of Data Converters shows how to design and experiment with data converters, both analog-to-digital and digital to analog. The design approach here is the same one used in all of John Lenk's best-selling books on simplified and practical design. Throughout the book, design problems start with guidelines for selecting all components on a trial-value basis, assuming a specific design goal and set of conditions. Then, using the guideline values in experimental circuits, the desired results are produced by varying the experimental component values, if needed.If you are a w

  17. An ASIC design for versatile receive front-end electronics of an ultrasonic medical imaging system--16 channel analog inputs and 4 dynamically focused beam outputs.

    Science.gov (United States)

    Park, Song B; Kwak, Jaeyoung; Lee, Kwyro

    2003-04-01

    An ultra large-scale ASIC is designed for the receive front-end electronics of an ultrasonic medical imaging system. The chip receives 16 channel analog rf signals and outputs 4 sets of sample-point-wise dynamically focused partial beam data. Four complete beam data sets are obtained in parallel by simply cascading as many chips as needed in an array system. High resolution of the focusing delay is obtained by nonuniformly selecting each channel data from a quadruply-interpolated rf data stream. The proposed ASIC can be applied to most practical array transducers in the frequency range of 2 to 10 MHz. The digital part of the designed ASIC can be implemented on a chip area of 17.9 microm2 with 0.18 mm CMOS technology, leaving sufficient room for 16 ADCs of 8 bits, 50 MHz on the 5.7 mm x 5.7 mm chip with a 208 pin package.

  18. Irradiation tests of ROHM 0.35um ASIC and Actel Anti-fuse FPGA for the ATLAS Muon Endcap Level-1 Trigger System

    CERN Document Server

    Ichimiya, R; Arai, Y; Ikeno, M; Sasaki, O; Ohshita, H; Takada, N; Hane, Y; Hasuko, K; Nomoto, H; Sakamoto, H; Shibuya, K; Takemoto, T; Fukunaga, C; Toshima, K; Sakuma, T; 10th Workshop on Electronics for LHC and Future Experiments

    2004-01-01

    In order to implement a level-1 trigger logic in an efficient manner from timing and space consumption point of view, application specific IC chips (ASIC) as well as FPGA ones are vitally used in the ATLAS muon end-cap level-1 trigger system. Various subsidiary logics are implemented in FPGAs while the core trigger logic is implemented in ASICs. These components will suffer for ten years the radiation of approximately 100Gy of total ionizing dose (TID) and a hadron fluence of 2x10^10hadrons/cm^2, which will cause single event upset (SEU) or single event latch up (SEL). We intend to use Rohm 0.35um gate width CMOS technology for ASIC and Actel anti-fuse based FPGA. In this presentation we report the result of irradiation test of devices made with these technologies and discuss validity of them to use in the system.

  19. Design and Control for the Buck-Boost Converter Combining 1-Plus-D Converter and Synchronous Rectified Buck Converters

    OpenAIRE

    2015-01-01

    In this paper, a design and control for the buck-boost converter, i.e., 1-plus-D converter with a positive output voltage, is presented, which combines the 1-plus-D converter and the synchronous rectified (SR) buck converter. By doing so, the problem in voltage bucking of the 1-plus-D converter can be solved, thereby increasing the application capability of the 1-plus-D converter. Since such a converter operates in continuous conduction mode inherently, it possesses the nonpulsating output cu...

  20. AC-DC PFC Converter Using Combination of Flyback Converter and Full-bridge DC-DC Converter

    Directory of Open Access Journals (Sweden)

    Moh. Zaenal Efendi

    2014-06-01

    Full Text Available This paper presents a combination of power factor correction converter using Flyback converter and Full-bridge dc-dc converter in series connection. Flyback converter is operated in discontinuous conduction mode so that it can serve as a power factor correction converter and meanwhile Full-bridge dc-dc converter is used for dc regulator. This converter system is designed to produce a 86 Volt of output voltage and 2 A of output current. Both simulation and experiment results show that the power factor of this converter achieves up to 0.99 and meets harmonic standard of IEC61000-3-2. Keywords: Flyback Converter, Full-bridge DC-DC Converter, Power Factor Correction.

  1. Leu85 in the beta1-beta2 linker of ASIC1 slows activation and decreases the apparent proton affinity by stabilizing a closed conformation.

    Science.gov (United States)

    Li, Tianbo; Yang, Youshan; Canessa, Cecilia M

    2010-07-16

    Acid-sensing ion channels (ASICs) are proton-activated channels expressed in neurons of the central and peripheral nervous systems where they modulate neuronal activity in response to external increases in proton concentration. The size of ASIC1 currents evoked by a given local acidification is determined by the number of channels in the plasma membrane and by the apparent proton affinities for activation and steady-state desensitization of the channel. Thus, the magnitude of the pH drop and the value of the baseline pH both are functionally important. Recent characterization of ASIC1s from an increasing number of species has made evident that proton affinities of these channels vary across vertebrates. We found that in species with high baseline plasma pH, e.g. frog, shark, and fish, ASIC1 has high proton affinity compared with the mammalian channel. The beta1-beta2 linker in the extracellular domain, specifically by the substitution M85L, determines the interspecies differences in proton affinities and also the time course of ASIC1 macroscopic currents. The mechanism underlying these observations is a delay in channel opening after application of protons, most likely by stabilizing a closed conformation that decreases the apparent affinity to protons and also slows the rise and decay phases of the current. Together, the results suggest evolutionary adaptation of ASIC1 to match the value of the species-specific plasma pH. At the molecular level, adaptation is achieved by substitutions of nonionizable residues rather than by modification of the channel proton sensor.

  2. Conception and test of an integrated circuit (ASIC): application to multiwire chambers and photomultipliers of the GRAAL experience; Conception et test d`un circuit integre (ASIC): application aux chambres multifils et aux photomultiplicateurs de l`experience GRAAL

    Energy Technology Data Exchange (ETDEWEB)

    Bugnet, H.

    1995-11-21

    The nuclear physics project GRAAL (GRenoble Anneau Accelerateur Laser) located at the European Synchrotron Radiation Facility (ESRF) in Grenoble produces a high energy photon beam with a maximum energy of 1.5 GeV. This gamma beam is obtained by Compton backscattering and can be polarized easily. It permits to probe, in an original way, the structure of the nucleon. The associated detector system includes multiwire proportional chambers and scintillator hodoscopes. A kit of six ASICs (Application Specific Integrated Circuit) has been developed and used for the signal processing and data conditioning up to the level of the data acquisition. This integrated electronics can be mounted right on the detectors. Obvious advantages, due to the reduction of the length of the wires and the number of connections, are an improvement of the signal quality and an increase of the reliability. The Wire Processor (WP), ASIC designed and tested during this thesis, treats the signals from the chamber wires and the photomultipliers. In one chip, there are two identical channels permitting the amplification, the amplitude discrimination, the generation of a programmable delay and the writing in a two state memory in case of coincidence with an external strobe signal. The measurement of the multiwire chamber efficiency demonstrates the functioning of the WP, the data conditioning electronics, the data acquisition and the chamber itself. (author). 62 refs., 111 figs., 13 tabs.

  3. Charge-pump voltage converter

    Science.gov (United States)

    Brainard, John P.; Christenson, Todd R.

    2009-11-03

    A charge-pump voltage converter for converting a low voltage provided by a low-voltage source to a higher voltage. Charge is inductively generated on a transfer rotor electrode during its transit past an inductor stator electrode and subsequently transferred by the rotating rotor to a collector stator electrode for storage or use. Repetition of the charge transfer process leads to a build-up of voltage on a charge-receiving device. Connection of multiple charge-pump voltage converters in series can generate higher voltages, and connection of multiple charge-pump voltage converters in parallel can generate higher currents. Microelectromechanical (MEMS) embodiments of this invention provide a small and compact high-voltage (several hundred V) voltage source starting with a few-V initial voltage source. The microscale size of many embodiments of this invention make it ideally suited for MEMS- and other micro-applications where integration of the voltage or charge source in a small package is highly desirable.

  4. High-Performance Data Converters

    DEFF Research Database (Denmark)

    Steensgaard-Madsen, Jesper

    Novel techniques for multi-bit oversampled data conversion are described. State-of-the-art oversampled data converters are analyzed, leading to the conclusion that their performance is limited mainly by low-resolution signal representation. To increase the resolution, high-performance, high...

  5. XML Docbook to Mediawiki Converter

    Directory of Open Access Journals (Sweden)

    Maria Chiara Pievatolo

    2013-05-01

    Full Text Available A Perl script, based on the work of Stefano Selleri, to migrate XML-Docbook 4.X documents to Wiki markup. I added some lines to meet my need to convert my Kant translations from Docbook to MediaWiki. A sample of the output can be...

  6. ChromAIX: Fast photon-counting ASIC for Spectral Computed Tomography

    Energy Technology Data Exchange (ETDEWEB)

    Steadman, Roger, E-mail: roger.steadman@philips.com [Philips Research Europe, Weisshausstrasse 2, 52066 Aachen (Germany); Herrmann, Christoph; Muelhens, Oliver [Philips Research Europe, Weisshausstrasse 2, 52066 Aachen (Germany); Maeding, Dale G. [Innovative Design, under contract with Aeroflex Colorado Springs (United States)

    2011-08-21

    X-ray attenuation properties of matter (i.e. human body in medical Computed Tomography) are energy and material dependent. This dependency is largely neglected in conventional CT techniques, which require the introduction of correction algorithms in order to prevent image artefacts. The exploitation of the inherent energy information contained in the X-ray spectrum allows distinguishing the two main physical causes of energy-dependent attenuation (photo-electric effect and Compton effect). Currently a number of methods exist that allow assessing the energy-dependent attenuation in conventional systems. These methods consist of using two distinct spectra (kVp switching or dual source) or of discriminating low and high energy photons by means of stacking two detectors. Further improvements can be achieved by transitioning to direct-conversion technologies and counting-mode detection, which inherently exhibits a better signal-to-noise ratio. Further including energy discrimination enables new applications, which are not feasible with dual-energy techniques, e.g. the possibility to discriminate K-edge features (contrast agents, e.g. gadolinium) from other contributions to the X-ray attenuation of a human body. The capability of providing energy-resolved information with two or more independent measurements is referred to as Spectral CT. A new proprietary photon-counting ASIC (ChromAIX) has been developed to provide high count-rate capabilities while offering energy discrimination. ChromAIX consists of a pixel array with an isotropic pitch of 300 {mu}m. Each pixel contains independent discriminators that enable the possibility to discretize the incoming photons into a number of energy levels. Extensive electrical characterization has been carried out to assess the performance in terms of count-rate performance and noise. Observed rates exceed 10 Mcps/pixel (Poissonian, mean incoming rates >27 Mcps). The energy resolution is better than 4.1 keV FWHM and has been shown to

  7. ChromAIX: Fast photon-counting ASIC for Spectral Computed Tomography

    Science.gov (United States)

    Steadman, Roger; Herrmann, Christoph; Mülhens, Oliver; Maeding, Dale G.

    2011-08-01

    X-ray attenuation properties of matter (i.e. human body in medical Computed Tomography) are energy and material dependent. This dependency is largely neglected in conventional CT techniques, which require the introduction of correction algorithms in order to prevent image artefacts. The exploitation of the inherent energy information contained in the X-ray spectrum allows distinguishing the two main physical causes of energy-dependent attenuation (photo-electric effect and Compton effect). Currently a number of methods exist that allow assessing the energy-dependent attenuation in conventional systems. These methods consist of using two distinct spectra (kVp switching or dual source) or of discriminating low and high energy photons by means of stacking two detectors. Further improvements can be achieved by transitioning to direct-conversion technologies and counting-mode detection, which inherently exhibits a better signal-to-noise ratio. Further including energy discrimination enables new applications, which are not feasible with dual-energy techniques, e.g. the possibility to discriminate K-edge features (contrast agents, e.g. gadolinium) from other contributions to the X-ray attenuation of a human body. The capability of providing energy-resolved information with two or more independent measurements is referred to as Spectral CT.A new proprietary photon-counting ASIC (ChromAIX) has been developed to provide high count-rate capabilities while offering energy discrimination. ChromAIX consists of a pixel array with an isotropic pitch of 300 μm. Each pixel contains independent discriminators that enable the possibility to discretize the incoming photons into a number of energy levels. Extensive electrical characterization has been carried out to assess the performance in terms of count-rate performance and noise. Observed rates exceed 10 Mcps/pixel (Poissonian, mean incoming rates >27 Mcps). The energy resolution is better than 4.1 keV FWHM and has been shown to be

  8. Bidirectional dc-to-dc Power Converter

    Science.gov (United States)

    Griesbach, C. R.

    1986-01-01

    Solid-state, series-resonant converter uses high-voltage thyristors. Converter used either to convert high-voltage, low-current dc power to lowvoltage, high current power or reverse. Taking advantage of newly-available high-voltage thyristors to provide better reliability and efficiency than traditional converters that use vacuum tubes as power switches. New converter essentially maintenance free and provides greatly increased mean time between failures. Attractive in industrial applications whether or not bidirectional capability is required.

  9. Respiratory virus infection up-regulates TRPV1, TRPA1 and ASICS3 receptors on airway cells

    Science.gov (United States)

    Omar, Shadia; Clarke, Rebecca; Abdullah, Haniah; Brady, Clare; Corry, John; Winter, Hanagh; Touzelet, Olivier; Power, Ultan F.; Lundy, Fionnuala; McGarvey, Lorcan P. A.

    2017-01-01

    Receptors implicated in cough hypersensitivity are transient receptor potential vanilloid 1 (TRPV1), transient receptor potential cation channel, Subfamily A, Member 1 (TRPA1) and acid sensing ion channel receptor 3 (ASIC3). Respiratory viruses, such as respiratory syncytial virus (RSV) and measles virus (MV) may interact directly and/or indirectly with these receptors on sensory nerves and epithelial cells in the airways. We used in vitro models of sensory neurones (SHSY5Y or differentiated IMR-32 cells) and human bronchial epithelium (BEAS-2B cells) as well as primary human bronchial epithelial cells (PBEC) to study the effect of MV and RSV infection on receptor expression. Receptor mRNA and protein levels were examined by qPCR and flow cytometry, respectively, following infection or treatment with UV inactivated virus, virus-induced soluble factors or pelleted virus. Concentrations of a range of cytokines in resultant BEAS-2B and PBEC supernatants were determined by ELISA. Up-regulation of TRPV1, TRPA1 and ASICS3 expression occurred by 12 hours post-infection in each cell type. This was independent of replicating virus, within the same cell, as virus-induced soluble factors alone were sufficient to increase channel expression. IL-8 and IL-6 increased in infected cell supernatants. Antibodies against these factors inhibited TRP receptor up-regulation. Capsazepine treatment inhibited virus induced up-regulation of TRPV1 indicating that these receptors are targets for treating virus-induced cough. PMID:28187208

  10. Multi-time-over-threshold technique for photomultiplier signal processing: Description and characterization of the SCOTT ASIC

    Energy Technology Data Exchange (ETDEWEB)

    Ferry, S. [CEA/Irfu/SPP, Gif-sur-Yvette (France); Guilloux, F., E-mail: fabrice.guilloux@cea.fr [CEA/Irfu/SEDI, Gif-sur-Yvette (France); Anvar, S.; Chateau, F.; Delagnes, E.; Gautard, V.; Louis, F.; Monmarthe, E.; Le Provost, H. [CEA/Irfu/SEDI, Gif-sur-Yvette (France); Russo, S. [Dipartimento di Scienze Fisiche Universita di Napoli, Napoli (Italy); Schuller, J.-P.; Stolarczyk, Th.; Vallage, B. [CEA/Irfu/SPP, Gif-sur-Yvette (France); Zonca, E. [CEA/Irfu/SEDI, Gif-sur-Yvette (France)

    2012-12-11

    KM3NeT aims to build a cubic-kilometer scale neutrino telescope in the Mediterranean Sea based on a 3D array of photomultiplier tubes. A dedicated ASIC, named SCOTT, has been developed for the readout electronics of the PMTs: it uses up to 16 adjustable thresholds to digitize the signals with the multi-time-over-threshold technique. Digital outputs of discriminators feed a circular sampling memory and a 'first in first out' digital memory for derandomization. At the end of the data processing, the ASIC produces a digital waveform sampled at 800 MHz. A specific study was carried out to process PMT data and has showed that five specifically chosen thresholds are suited to reach the required timing precision. A dedicated method based on the duration of the signal over a given threshold allows an equivalent timing precision at any charge. A charge estimator using the information from the thresholds allows a charge determination within less than 20% up to 60 pe.

  11. Pixel readout ASIC for an APD based 2D X-ray hybrid pixel detector with sub-nanosecond resolution

    Energy Technology Data Exchange (ETDEWEB)

    Thil, Ch., E-mail: christophe.thil@ziti.uni-heidelberg.d [Heidelberg University, Institute of Computer Engineering, B6, 26, 68161 Mannheim (Germany); Baron, A.Q.R. [RIKEN SPring-8 Center, 1-1-1 Kouto, Sayo-cho, Sayo-gun, Hyogo 679-5148 (Japan); Fajardo, P. [ESRF, Polygone Scientifique Louis Neel, 6, rue Jules Horowitz, 38000 Grenoble (France); Fischer, P. [Heidelberg University, Institute of Computer Engineering, B6, 26, 68161 Mannheim (Germany); Graafsma, H. [DESY, Notkestrasse 85, 22607 Hamburg (Germany); Rueffer, R. [ESRF, Polygone Scientifique Louis Neel, 6, rue Jules Horowitz, 38000 Grenoble (France)

    2011-02-01

    The fast response and the short recovery time of avalanche photodiodes (APDs) in linear mode make those devices ideal for direct X-ray detection in applications requiring high time resolution or counting rate. In order to provide position sensitivity, the XNAP project aims at creating a hybrid pixel detector with nanosecond time resolution based on a monolithic APD sensor array with 32 x32 pixels covering about 1 cm{sup 2} active area. The readout is implemented in a pixelated front-end ASIC suited for the readout of such arrays, matched to pixels of 280{mu}mx280{mu}m size. Every single channel features a fast transimpedance amplifier, a discriminator with locally adjustable threshold and two counters with high dynamic range and counting speed able to accumulate X-ray hits with no readout dead time. Additionally, the detector can be operated in list mode by time-stamping every single event with sub-nanosecond resolution. In a first phase of the project, a 4x4 pixel test module is built to validate the conceptual design of the detector. The XNAP project is briefly presented and the performance of the readout ASIC is discussed.

  12. Underlying mechanism of ASIC1a involved in acidosis-induced cytotoxicity in rat C6 glioma cells

    Institute of Scientific and Technical Information of China (English)

    Xie-chuan WENG; Jian-quan ZHENG; Jin LI; Wen-bin XIAO

    2007-01-01

    Aim:To investigate the underlying mechanism of acid-sensing ion channel (ASIC) la involved in the acidosis-induced cytotoxicity of rat C6 glioma cells. Methods:The stable ASICla-silenced C6 cells built with the RNA interference technology were confirmed by RT-PCR and Western blot analysis. Intracellular calcium ([Ca2+]i) in both the wild-type rat C6 glioma cells and the ASIC I a-silenced C6 cells were analyzed before and after acid application/exposure with the calcium imaging experiment. Results:The rapid extracellular pH drop induced the increase of [Ca2+]i in the wild-type C6 cells,but not in the ASICla-silenced C6 cells. During the prolonged acid exposure,[Ca2+]i was lower in the ASICla-silenced C6 cells than that in the control cells. Conclusion:The resultant toxicity of [Ca2+]i might contribute to the acidosis-induced cytotoxicity.

  13. An efficient ASIC implementation of 16-channel on-line recursive ICA processor for real-time EEG system.

    Science.gov (United States)

    Fang, Wai-Chi; Huang, Kuan-Ju; Chou, Chia-Ching; Chang, Jui-Chung; Cauwenberghs, Gert; Jung, Tzyy-Ping

    2014-01-01

    This is a proposal for an efficient very-large-scale integration (VLSI) design, 16-channel on-line recursive independent component analysis (ORICA) processor ASIC for real-time EEG system, implemented with TSMC 40 nm CMOS technology. ORICA is appropriate to be used in real-time EEG system to separate artifacts because of its highly efficient and real-time process features. The proposed ORICA processor is composed of an ORICA processing unit and a singular value decomposition (SVD) processing unit. Compared with previous work [1], this proposed ORICA processor has enhanced effectiveness and reduced hardware complexity by utilizing a deeper pipeline architecture, shared arithmetic processing unit, and shared registers. The 16-channel random signals which contain 8-channel super-Gaussian and 8-channel sub-Gaussian components are used to analyze the dependence of the source components, and the average correlation coefficient is 0.95452 between the original source signals and extracted ORICA signals. Finally, the proposed ORICA processor ASIC is implemented with TSMC 40 nm CMOS technology, and it consumes 15.72 mW at 100 MHz operating frequency.

  14. Development of CdTe pixel detectors combined with an aluminum Schottky diode sensor and photon-counting ASICs

    Science.gov (United States)

    Toyokawa, H.; Saji, C.; Kawase, M.; Wu, S.; Furukawa, Y.; Kajiwara, K.; Sato, M.; Hirono, T.; Shiro, A.; Shobu, T.; Suenaga, A.; Ikeda, H.

    2017-01-01

    We have been developing CdTe pixel detectors combined with a Schottky diode sensor and photon-counting ASICs. The hybrid pixel detector was designed with a pixel size of 200 μ m by 200 μm and an area of 19 mm by 20 mm or 38.2 mm by 40.2 mm. The photon-counting ASIC, SP8-04F10K, has a preamplifier, a shaper, 3-level window-type discriminators and a 24-bits counter in each pixel. The single-chip detector with 100 by 95 pixels successfully operated with a photon-counting mode selecting X-ray energy with the window comparator and stable operation was realized at 20 degrees C. We have performed a feasibility study for a white X-ray microbeam experiment. Laue diffraction patterns were measured during the scan of the irradiated position in a silicon steel sample. The grain boundaries were identified by using the differentials between adjacent images at each position.

  15. Photoelectric converter; Koden henkan soshi

    Energy Technology Data Exchange (ETDEWEB)

    Sawayama, I.

    1995-04-07

    The conventional solar cell module wherein plural photovoltaic elements formed on a metal substrate are connected and coated by weatherproof and translucent resin has defects such as pinholes, and separation because moisture infiltrating from the outside causes dissolution of such conductive matrix as silver in the collecting electrode. This invention relates to a photoelectric converter which has little decrease in the output under the environment of light irradiation, wherein a photoelectric converting semiconductor, a transparent conductive layer on the above-mentioned semiconductor, and conductive member containing water repellent fine powder grains on this transparent conductive layer are laminated successively. Polytetrafluoroethylene, polydimethyl siloxane, polyethylene, and nylon are desirable to be employed as the water repellent fine powder grains. The fine powder grains are mixed with conductive filler and binder to produce conductive paste, pattern-applied by a screen printing machine, and subjected to thermal treatment to form a conductive member. 3 figs., 1 tab.

  16. Photoelectric converters with quantum coherence.

    Science.gov (United States)

    Su, Shan-He; Sun, Chang-Pu; Li, Sheng-Wen; Chen, Jin-Can

    2016-05-01

    Photon impingement is capable of liberating electrons in electronic devices and driving the electron flux from the lower chemical potential to higher chemical potential. Previous studies hinted that the thermodynamic efficiency of a nanosized photoelectric converter at maximum power is bounded by the Curzon-Ahlborn efficiency η_{CA}. In this study, we apply quantum effects to design a photoelectric converter based on a three-level quantum dot (QD) interacting with fermionic baths and photons. We show that, by adopting a pair of suitable degenerate states, quantum coherences induced by the couplings of QDs to sunlight and fermion baths can coexist steadily in nanoelectronic systems. Our analysis indicates that the efficiency at maximum power is no longer limited to η_{CA} through manipulation of carefully controlled quantum coherences.

  17. Photoelectric converters with quantum coherence

    Science.gov (United States)

    Su, Shan-He; Sun, Chang-Pu; Li, Sheng-Wen; Chen, Jin-Can

    2016-05-01

    Photon impingement is capable of liberating electrons in electronic devices and driving the electron flux from the lower chemical potential to higher chemical potential. Previous studies hinted that the thermodynamic efficiency of a nanosized photoelectric converter at maximum power is bounded by the Curzon-Ahlborn efficiency ηCA. In this study, we apply quantum effects to design a photoelectric converter based on a three-level quantum dot (QD) interacting with fermionic baths and photons. We show that, by adopting a pair of suitable degenerate states, quantum coherences induced by the couplings of QDs to sunlight and fermion baths can coexist steadily in nanoelectronic systems. Our analysis indicates that the efficiency at maximum power is no longer limited to ηCA through manipulation of carefully controlled quantum coherences.

  18. Biomass compounds converted to gasoline

    Energy Technology Data Exchange (ETDEWEB)

    1979-10-08

    It is claimed that corn, castor, and jojoba oils as well as Hevea latex can be converted in high yields to gasoline by passage over zeolite catalysts at 450 degrees to 500 degrees centigrade. Gasoline yields are 60% from corn oil (essentially tristearin), compared with 50% yields from methanol. Latex depolymerizes before conversion. Fat and oil molecules adopt conformations that enable them to enter zeolite interstices, resulting in high yields of C6 to C9 aromatics.

  19. Workshop 4 Converter cooling & recuperation

    Science.gov (United States)

    Iles, Peter; Hindman, Don

    1995-01-01

    Cooling the PV converter increases the overall TPV system efficiency, and more than offsets the losses incurred in providing cooling systems. Convective air flow methods may be sufficient, and several standard water cooling systems, including thermo-syphon radiators, capillary pumps or microchannel plates, are available. Recuperation is used to increase system efficiency, rather than to increase the emitter temperature. Recuperators operating at comparable high temperatures, such as in high temperature turbines have worked effectively.

  20. Simplified dc to dc converter

    Science.gov (United States)

    Gruber, R. P. (Inventor)

    1984-01-01

    A dc to dc converter which can start with a shorted output and which regulates output voltage and current is described. Voltage controlled switches directed current through the primary of a transformer the secondary of which includes virtual reactance. The switching frequency of the switches is appropriately varied to increase the voltage drop across the virtual reactance in the secondary winding to which there is connected a low impedance load. A starting circuit suitable for voltage switching devices is provided.

  1. Design and Control for the Buck-Boost Converter Combining 1-Plus-D Converter and Synchronous Rectified Buck Converters

    Directory of Open Access Journals (Sweden)

    Jeevan Naik

    2015-06-01

    Full Text Available In this paper, a design and control for the buck-boost converter, i.e., 1-plus-D converter with a positive output voltage, is presented, which combines the 1-plus-D converter and the synchronous rectified (SR buck converter. By doing so, the problem in voltage bucking of the 1-plus-D converter can be solved, thereby increasing the application capability of the 1-plus-D converter. Since such a converter operates in continuous conduction mode inherently, it possesses the nonpulsating output current, thereby not only decreasing the current stress on the output capacitor but also reducing the output voltage ripple. Above all, both the 1-plus-D converter and the SR buck converter, combined into a buck–boost converter with no right-half plane zero, use the same power switches, thereby causing the required circuit to be compact and the corresponding cost to be down. Furthermore, during the magnetization period, the input voltage of the 1-plus-D converter comes from the input voltage source, whereas during the demagnetization period, the input voltage of the 1-plus-D converter comes from the output voltage of the SR buck converter.

  2. Computerized simulation of converter process

    Energy Technology Data Exchange (ETDEWEB)

    Jalkanen, H.; Suomi, M.L.; Wallgren, M. [Helsinki Univ. of Technology, Otaniemi (Finland). Lab. of Metallurgy

    1996-12-31

    Converter process is essentially an oxidising refining process aiming in addition to (1) the primary refining action, decarburisation of high carbon iron melt, also to (2) maximal elimination of impurity elements, especially silicon, phosphorus and sulphur, (3) melting of substantial amounts of scrap using the extra heat released in oxidation reactions and (4) to exact final steel temperature control, optimal for further treatments. `Quantitative modelling of such a complex non-stationary chemical process as oxygen converting necessitates extensive formulation of chemical and thermal evolution of the process in connection with the technological properties of the reactor and the process control measures. A comprehensive converter simulation program like CONSIM-3. 1 and its preceding versions that is based on the theoretical and practical knowledge on the process can be used for (1) educating specialists and smelter personnel, (2) planning of the blowing programs, (3) developing and testing of process control systems and after some elaboration and restructuring (4) it can be integrated to static or dynamic process control systems. (orig.) SULA 2 Research Programme; 10 refs.

  3. Development of a compact radiation-hardened low-noise front-end readout ASIC for CZT-based hard X-ray imager

    Energy Technology Data Exchange (ETDEWEB)

    Gao, W., E-mail: gaowu@nwpu.edu.cn; Gan, B.; Li, X.; Wei, T.; Gao, D.; Hu, Y.

    2015-04-21

    In this paper, we present the development and performances of a radiation-hardened front-end readout application-specific integrated circuit (ASIC) dedicated to CZT detectors for a hard X-ray imager in space applications. The readout channel consists of a charge sensitive amplifier (CSA), a CR-RC shaper, a fast shaper, a discriminator and a driving buffer. With the additional digital filtering, the readout channel can achieve very low noise performances and low power dissipation. An eight-channel prototype ASIC is designed and fabricated in 0.35 μm CMOS process. The energy range of the detected X-rays is evaluated as 1.45 keV to 281 keV. The gain is larger than 100 mV/fC. The equivalent noise charge (ENC) of the ASIC is 53 e{sup −} at zero farad plus 10 e{sup −} per picofarad. The power dissipation is less than 4.4 mW/channel. Through the measurement with a CZT detector, the energy resolution is less than 3.45 keV (FWHM) under the irradiation of the radioactive source {sup 241}Am. The radiation effect experiments indicate that the proposed ASIC can resist the total ionization dose (TID) irradiation of higher than 200 krad (Si)

  4. Development of a compact radiation-hardened low-noise front-end readout ASIC for CZT-based hard X-ray imager

    Science.gov (United States)

    Gao, W.; Gan, B.; Li, X.; Wei, T.; Gao, D.; Hu, Y.

    2015-04-01

    In this paper, we present the development and performances of a radiation-hardened front-end readout application-specific integrated circuit (ASIC) dedicated to CZT detectors for a hard X-ray imager in space applications. The readout channel consists of a charge sensitive amplifier (CSA), a CR-RC shaper, a fast shaper, a discriminator and a driving buffer. With the additional digital filtering, the readout channel can achieve very low noise performances and low power dissipation. An eight-channel prototype ASIC is designed and fabricated in 0.35 μm CMOS process. The energy range of the detected X-rays is evaluated as 1.45 keV to 281 keV. The gain is larger than 100 mV/fC. The equivalent noise charge (ENC) of the ASIC is 53 e- at zero farad plus 10 e- per picofarad. The power dissipation is less than 4.4 mW/channel. Through the measurement with a CZT detector, the energy resolution is less than 3.45 keV (FWHM) under the irradiation of the radioactive source 241Am. The radiation effect experiments indicate that the proposed ASIC can resist the total ionization dose (TID) irradiation of higher than 200 krad (Si).

  5. The TDCpix readout ASIC: A 75 ps resolution timing front-end for the NA62 Gigatracker hybrid pixel detector

    Energy Technology Data Exchange (ETDEWEB)

    Kluge, A., E-mail: alexander.kluge@cern.ch; Aglieri Rinella, G.; Bonacini, S.; Jarron, P.; Kaplon, J.; Morel, M.; Noy, M.; Perktold, L.; Poltorak, K.

    2013-12-21

    The TDCpix is a novel pixel readout ASIC for the NA62 Gigatracker detector. NA62 is a new experiment being installed at the CERN Super Proton Synchrotron. Its Gigatracker detector shall provide on-beam tracking and time stamping of individual particles with a time resolution of 150 ps rms. It will consist of three tracking stations, each with one hybrid pixel sensor. The peak flow of particles crossing the detector modules reaches 1.27 MHz/mm{sup 2} for a total rate of about 0.75 GHz. Ten TDCpix chips will be bump-bonded to every silicon pixel sensor. Each chip shall perform time stamping of 100 M particle hits per second with a detection efficiency above 99% and a timing accuracy better than 200 ps rms for an overall three-station-setup time resolution of better than 150 ps. The TDCpix chip has been designed in a 130 nm CMOS technology. It will feature 45×40 square pixels of 300×300μm{sup 2} and a complex End of Column peripheral region including an array of TDCs based on DLLs, four high speed serializers, a low-jitter PLL, readout and control circuits. This contribution will describe the complete design of the final TDCpix ASIC. It will discuss design choices, the challenges faced and some of the lessons learned. Furthermore, experimental results from the testing of circuit prototypes will be presented. These demonstrate the achievement of key performance figures such as a time resolution of the processing chain of 75 ps rms with a laser sent to the center of the pixel and the capability of time stamping charged particles with an overall resolution below 200 ps rms. -- Highlights: • Feasibility demonstration of a silicon pixel detector with sub-ns time tagging capability. • Demonstrator detector assembly with a time resolution of 75 ps RMS with laser charge injection; 170 ps RMS with particle beam. • Design of trigger-less TDCpix ASIC with 1800 pixels, 720 TDC channels and 4 3.2 Gbit/s serializers.

  6. OAM mode converter in twisted fibers

    DEFF Research Database (Denmark)

    Usuga Castaneda, Mario A.; Beltran-Mejia, Felipe; Cordeiro, Cristiano

    2014-01-01

    We analyze the case of an OAM mode converter based on a twisted fiber, through finite element simulations where we exploit an equivalence between geometric and material transformations. The obtained converter has potential applications in MDM. © 2014 OSA.......We analyze the case of an OAM mode converter based on a twisted fiber, through finite element simulations where we exploit an equivalence between geometric and material transformations. The obtained converter has potential applications in MDM. © 2014 OSA....

  7. Analysis and design of converters in Matlab

    OpenAIRE

    Lorente Sanjurjo, Rodrigo

    2010-01-01

    This project will try to provide better understanding of data converters, more specifically in the mathematical representation and coding of non idealities of the converter. As programming tool it will be used the MATLAB environment, with which will carry out the coding and the analysis of the behavior of the converters by adding diverse nonlinearities, taking advantage of the simplicity, clarity, and extensibility that provides this environment. Summarizing, it is going to study the converte...

  8. Power electronics converters and regulators

    CERN Document Server

    Dokić, Branko L

    2015-01-01

    This book is the result of the extensive experience the authors gained through their year-long occupation at the Faculty of Electrical Engineering at the University of Banja Luka. Starting at the fundamental basics of electrical engineering, the book guides the reader into this field and covers all the relevant types of converters and regulators. Understanding is enhanced by the given examples, exercises and solutions. Thus this book can be used as a textbook for students, for self-study or as a reference book for professionals.

  9. Converting pest insects into food

    DEFF Research Database (Denmark)

    Offenberg, Hans Joachim; Wiwatwittaya, Decha

    2010-01-01

    on management, 32-115 kg ant brood (mainly new queens) was harvested per ha per year without detrimental effect on colony survival and worker ant densities. This suggest that ant biocontrol and ant harvest can be sustainable integrated in plantations and double benefits derived. As ant production is fuelled...... by pest insects, problematic pests are converted into food and additional earnings. To assess the profitability of providing additional food for the ants, O. smaragdina food conversion efficiency (ECI) was estimated in the laboratory. This estimate suggests the feeding of weaver ants in ant farms...

  10. Energy resolution of a silicon detector with the RX64 ASIC designed for X-ray imaging

    Energy Technology Data Exchange (ETDEWEB)

    Bollini, D.; Cabal Rodriguez, A.E.; Dabrowski, W.; Diaz Garcia, A.; Gambaccini, M.; Giubellino, P.; Grybos, P.; Idzik, M.; Marzari-Chiesa, A.; Montano, L.M.; Prino, F.; Ramello, L. E-mail: ramello@to.infn.it; Sitta, M.; Swientek, K.; Wheadon, R.; Wiacek, P

    2003-12-11

    Results from a silicon microstrip detector coupled to the RX64 ASIC are presented. The system is capable of single photon counting in digital X-ray imaging, with foreseen applications to dual energy mammography and angiography. The main features of the detecting system are low noise (operation with threshold as low as {approx}4 keV is possible), good spatial resolution (a pixel of 100 {mu}mx300 {mu}m when oriented edge-on) and good counting rate capability (up to one million counts per channel with a maximum rate of about 200 kHz per channel). The energy resolution of the system, as obtained with several fluorescence X-ray lines, is described.

  11. A prototype of a new generation readout ASIC in 65nm CMOS for pixel detectors at HL-LHC

    Science.gov (United States)

    Monteil, E.; Pacher, L.; Paternò, A.; Loddo, F.; Demaria, N.; Gaioni, L.; De Canio, F.; Traversi, G.; Re, V.; Ratti, L.; Rivetti, A.; Da Rocha Rolo, M.; Dellacasa, G.; Mazza, G.; Marzocca, C.; Licciulli, F.; Ciciriello, F.; Marconi, S.; Placidi, P.; Magazzù, G.; Stabile, A.; Mattiazzo, S.; Veri, C.

    2016-12-01

    This paper describes a readout ASIC prototype designed by CHIPIX65 project, part of RD53, for a pixel detector at HL-LHC . A 64 × 64 matrix of 50 × 50 μ m2 pixels is realised. A digital architecture has been developed, with particle efficiency above 99.9% at 3 GHz/cm2 pixel rate, 1 MHz trigger rate with 12.5 μ s latency. Two analog front end designs, one synchronous and one asynchronous, are implemented. Charge is measured with 5-bit precision and the analog dead-time is below 1%. IP-blocks (DAC, ADC, BandGap, SER, sLVS-TX/RX) and very front ends are silicon proven, irradiated to 600-800Mrad.

  12. The bile acid-sensitive ion channel (BASIC), the ignored cousin of ASICs and ENaC.

    Science.gov (United States)

    Wiemuth, Dominik; Assmann, Marc; Gründer, Stefan

    2014-01-01

    The DEG/ENaC gene family of ion channels is characterized by a high degree of structural similarity and an equally high degree of diversity concerning the physiological function. In humans and rodents, the DEG/ENaC family comprises 2 main subgroups: the subunits of the epithelial Na(+) channel (ENaC) and the subunits of the acid sensing ion channels (ASICs). The bile acid-sensitive channel (BASIC), previously known as BLINaC or INaC, represents a third subgroup within the DEG/ENaC family. Although BASIC was identified more than a decade ago, very little is known about its physiological function. Recent progress in the characterization of this neglected member of the DEG/ENaC family, which is summarized in this focused review, includes the discovery of surprising species differences, its pharmacological characterization, and the identification of bile acids as putative natural activators.

  13. Characterization of a wide dynamic-range, radiation-tolerant charge-digitizer asic for monitoring of Beam losses

    CERN Document Server

    Guido Venturini, G G; Dehning, B; Kayal, M

    2012-01-01

    An Application Specific Integrated Circuit (ASIC) has been designed and fabricated to provide a compact solution to digitize current signals from ionization chambers and diamond detectors, employed as beam loss monitors at CERN and several other high energy physics facilities. The circuit topology has been devised to accept positive and negative currents, to have a wide dynamic range (above 120 dB), withstand radiation levels over 10 Mrad and offer different modes of operation, covering a broad range of applications. Furthermore, an internal conversion reference is employed in the digitization, to provide an accurate absolute measurement. This paper discusses the detailed characterization of the first prototype: linearity, radiation tolerance and temperature dependence of the conversion, as well as implications and system-level considerations regarding its use for beam instrumentation applications in a high energy physics facility.

  14. Ecologically Optimal Solution of Power Semiconductors Converters

    Directory of Open Access Journals (Sweden)

    Ivan Lokseninec

    2003-01-01

    Full Text Available One of the relevant scientific programs of Department of Power Electrical Systems is research of ecologically optimal topologies main circuits of power converters. This paper presents some methods how to reduce unfavourable influences of power converters on the grid. The achieved results were applieed in praxis, especially in the power converters produced by Electrotechnical Research and Projecting Institute in Nova Dubnica.

  15. ASIC or PIC? Implantable stimulators based on semi-custom CMOS technology or low-power microcontroller architecture.

    Science.gov (United States)

    Salmons, S; Gunning, G T; Taylor, I; Grainger, S R; Hitchings, D J; Blackhurst, J; Jarvis, J C

    2001-01-01

    To gain a better understanding of the effects of chronic stimulation on mammalian muscles we needed to generate patterns of greater variety and complexity than simple constant-frequency or burst patterns. We describe here two approaches to the design of implantable neuromuscular stimulators that can satisfy these requirements. Devices of both types were developed and used in long-term experiments. The first device was based on a semi-custom Application Specific Integrated Circuit (ASIC). This approach has the advantage that the circuit can be completely tested at every stage of development and production, assuring a high degree of reliability. It has the drawback of inflexibility: the patterns are produced by state machines implemented in silicon, so each new set of patterns requires a fresh production run, which is costly and time-consuming. The second device was based on a commercial microcontroller (Microchip PIC16C84). The functionality of this type of circuit is specified in software rather than in silicon hardware, allowing a single device to be programmed for different functions. With the use of features designed to improve fault-tolerance we found this approach to be as reliable as that based on ASICs. The encapsulated devices can easily be accommodated subcutaneously on the flank of a rabbit and a recent version is small enough to implant into the peritoneal cavity of rats. The current devices are programmed with a predetermined set of 12 patterns before assembly; the desired pattern is selected after implantation with an electronic flash gun. The operating current drain is less than 40 microA.

  16. A dc to dc converter

    Science.gov (United States)

    Willis, A. E.; Gould, J. M.; Matheney, J. L.; Garrett, H. (Inventor)

    1984-01-01

    The object of the invention is to provide an improved converter for converting one direct current voltage to another. A plurality of phased square wave voltages are provided from a ring counter through amplifiers to a like plurality of output transformers. Each of these transformers has two windings, and S(1) winding and an S(2) winding. The S(1) windings are connected in series, then the S(2) windings are connected in series, and finally, the two sets of windings are connected in series. One of six SCRs is connected between each two series connected windings to a positive output terminal and one of diodes is connected between each set of two windings of a zero output terminal. By virtue of this configuration, a quite high average direct current voltage is obtained, which varies between full voltage and two-thirds full voltage rather than from full voltage to zero. Further, its variation, ripple frequency, is reduced to one-sixth of that present in a single phase system. Application to raising battery voltage for an ion propulsion system is mentioned.

  17. Reliability of Wave Energy Converters

    DEFF Research Database (Denmark)

    Ambühl, Simon

    . Structural reliability considerations and optimizations impact operation and maintenance (O&M) costs as well as the initial investment costs. Furthermore, there is a control system for WEC applications which defines the harvested energy but also the loads onto the structure. Therefore, extreme loads but also...... WEPTOS. Calibration of safety factors are performed for welded structures at theWavestar device including different control systems for harvesting energy from waves. In addition, a case study of different O&M strategies for WECs is discussed, and an example of reliability-based structural optimization......There are many different working principles for wave energy converters (WECs) which are used to produce electricity from waves. In order for WECs to become successful and more competitive to other renewable electricity sources, the consideration of the structural reliability of WECs is essential...

  18. Reliability of Wave Energy Converters

    DEFF Research Database (Denmark)

    Ambühl, Simon

    for welded structures at the Wavestar device includingdifferent control systems for harvesting energy from waves. In addition, a casestudy of different O&M strategies for WECs is discussed, and an example ofreliability-based structural optimization of the Wavestar foundation ispresented. The work performed......There are many different working principles for wave energy converters (WECs) which are used to produce electricity from waves. In order for WECs tobecome successful and more competitive to other renewable electricity sources,the consideration of the structural reliability of WECs is essential.......Structural reliability considerations and optimizations impact operation andmaintenance (O&M) costs as well as the initial investment costs.Furthermore, there is a control system for WEC applications which defines theharvested energy but also the loads onto the structure. Therefore, extremeloads but also fatigue loads...

  19. Manufacturing method of photoelectric converter

    Energy Technology Data Exchange (ETDEWEB)

    Toda, Koji; Niwa, Yasuo

    1987-06-24

    In a method of making a thin film for a photoelectric converter by a method to form an electroconductive layer by burning a mixture of lead oxide and chromic oxide, thickness of the film was limited and the poreless uniform film was not obtainable. The intransparency of the film gave low conversion efficiency only. This invention enabled to obtain a transparent film wherein an oxide (containing lead and chrome) is used as a target to form, in vacuum, a thin film of the oxide, and then this thin film is heat-treated in an atmosphere at least containing lead. Thin transparent film was obtained enhancing the conversion efficiency. High quality and high reliability are ensured because a poreless uniform film can be obtained. Cost was reduced because mass-production was made possible by the use of a vacuum technique. (5 figs)

  20. Efficiency of Capacitively Loaded Converters

    DEFF Research Database (Denmark)

    Andersen, Thomas; Huang, Lina; Andersen, Michael A. E.;

    2012-01-01

    This paper explores the characteristic of capacitance versus voltage for dielectric electro active polymer (DEAP) actuator, 2kV polypropylene film capacitor as well as 3kV X7R multi layer ceramic capacitor (MLCC) at the beginning. An energy efficiency for capacitively loaded converters...... is introduced as a definition of efficiency. The calculated and measured efficiency curves for charging DEAP actuator, polypropylene film capacitor and X7R MLCC are provided and compared. The attention has to be paid for the voltage dependent capacitive load, like X7R MLCC, when evaluating the charging...... polypropylene film capacitor can be the equivalent capacitive load. Because of the voltage dependent characteristic, X7R MLCC cannot be used to replace the DEAP actuator. However, this type of capacitor can be used to substitute the capacitive actuator with voltage dependent property at the development phase....

  1. Simulation of the High Performance Time to Digital Converter for the ATLAS Muon Spectrometer trigger upgrade

    Science.gov (United States)

    Meng, X. T.; Levin, D. S.; Chapman, J. W.; Zhou, B.

    2016-09-01

    The ATLAS Muon Spectrometer endcap thin-Resistive Plate Chamber trigger project compliments the New Small Wheel endcap Phase-1 upgrade for higher luminosity LHC operation. These new trigger chambers, located in a high rate region of ATLAS, will improve overall trigger acceptance and reduce the fake muon trigger incidence. These chambers must generate a low level muon trigger to be delivered to a remote high level processor within a stringent latency requirement of 43 bunch crossings (1075 ns). To help meet this requirement the High Performance Time to Digital Converter (HPTDC), a multi-channel ASIC designed by CERN Microelectronics group, has been proposed for the digitization of the fast front end detector signals. This paper investigates the HPTDC performance in the context of the overall muon trigger latency, employing detailed behavioral Verilog simulations in which the latency in triggerless mode is measured for a range of configurations and under realistic hit rate conditions. The simulation results show that various HPTDC operational configurations, including leading edge and pair measurement modes can provide high efficiency (>98%) to capture and digitize hits within a time interval satisfying the Phase-1 latency tolerance.

  2. Development of Formulations for a-SiC and Manganese CMP and Post-CMP Cleaning of Cobalt

    Science.gov (United States)

    Lagudu, Uma Rames Krishna

    We have investigated the chemical mechanical polishing (CMP) of amorphous SiC (a-SiC) and Mn and Post CMP cleaning of cobalt for various device applications. During the manufacture of copper interconnects using the damascene process the polishing of copper is followed by the polishing of the barrier material (Co, Mn, Ru and their alloys) and its post CMP cleaning. This is followed by the a-SiC hard mask CMP. Silicon carbide thin films, though of widespread use in microelectronic engineering, are difficult to process by CMP because of their hardness and chemical inertness. The earlier part of the SiC work discusses the development of slurries based on silica abrasives that resulted in high a-SiC removal rates (RRs). The ionic strength of the silica dispersion was found to play a significant role in enhancing material removal rate, while also providing very good post-polish surface-smoothness. For example, the addition of 50 mM potassium nitrate to a pH 8 aqueous slurry consisting of 10 wt % of silica abrasives and 1.47 M hydrogen peroxide increased the RR from about 150 nm/h to about 2100 nm/h. The role of ionic strength in obtaining such high RRs was investigated using surface zeta-potentials measurements and X-ray photoelectron spectroscopy (XPS). Evidently, hydrogen peroxide promoted the oxidation of Si and C to form weakly adhered species that were subsequently removed by the abrasive action of the silica particles. The effect of potassium nitrate in increasing material removal is attributed to the reduction in the electrostatic repulsion between the abrasive particles and the SiC surface because of screening of surface charges by the added electrolyte. We also show that transition metal compounds when used as additives to silica dispersions enhance a-SiC removal rates (RRs). Silica slurries containing potassium permanganate gave RRs as high as 2000 nm/h at pH 4. Addition of copper sulfate to this slurry further enhanced the RRs to ˜3500 nm/h at pH 6

  3. Three-phase AC-AC power converters based on matrix converter topology matrix-reactance frequency converters concept

    CERN Document Server

    Szczesniak, Pawel

    2013-01-01

    AC voltage frequency changes is one of the most important functions of solid state power converters. The most desirable features in frequency converters are the ability to generate load voltages with arbitrary amplitude and frequency, sinusoidal currents and voltages waveforms; the possibility of providing unity power factor for any load; and, finally, a simple and compact power circuit. Over the past decades, a number of different frequency converter topologies have appeared in the literature, but only the converters with either a voltage or current DC link are commonly used in industrial app

  4. A Novel Low Noise Interface ASIC of Vacuum Microelectronic Accelerometer%一种新型低噪声真空微电子加速度计的接口ASIC

    Institute of Scientific and Technical Information of China (English)

    刘海涛; 温志渝; 陈李; 温中泉; 贺学峰

    2012-01-01

    真空微电子加速度计基于隧道效应而工作,其内部固有的低频噪声(如1/f噪声)大大降低其信噪比,而且也是影响精度和线性度的主要因素.采用混频技术和相关检测算法,本文研制和设计了一种新型低噪声接口ASIC(专用集成电路).最后测试了加速度计的噪声和线性度,在0~200 Hz范围内输出信号平均噪声密度为69μV·Hz-1/2,线性度相关系数为99.99%,最大的非线性度为0.41%.通过实验结果可以看出该电路能大大改善加速度计的噪声特性和线性度,而且该电路设计思想能用于其它隧道效应加速度计.%Abstract:The vacuum microelectronic accelerometer works based on tunneling effect,the inherent low frequency noise such as 1/f noise decreases the signal-to-noise ratio greatly,and it is the main influencing factors to precision and linearity of accelerometer.In order to eliminate the noise and improved the linearity characteristic, in this paper a novel low noise interface ASIC ( Application Specific Integrated Circuit) was bring forward and designed according to the frequency mixing technique and coherent detection technology.Finally the noise and linearity of the accelerometer was tested,the mean noise spectrum density of output signal is 69μV · Hz-1/2 from 0 Hz to 200 Hz.the correlation coefficient of the least-square linear fitting curve is 99.99%,the maxim nonlinearity is 0.41%.Through the results and compare with the previous results of circuit,we can draw conclusion that the noise and linear performs have been improved through interface circuit,and furthermore,the idea of circuit design can also be used to the other tunneling accelerometer.

  5. KLauS: an ASIC for silicon photomultiplier readout and its application in a setup for production testing of scintillating tiles

    CERN Document Server

    Briggl, K; Hagdorn, R; Harion, T; Schultz-Coulon, H.C; Shen, W

    2014-01-01

    signals from silicon photomultipliers. Developed as an analog front-end for future calorimeters with high granularity as pursued by the AHCAL concept in the CALICE collaboration, the ASIC is designed to measure the charge signal of the sensors in a large dynamic range and with low electronic noise contributions. In order to tune the operation voltage of each sensor individually, an 8-bit DAC to tune the voltage at the input terminal within a range of 2V is implemented. Using an integrated fast comparator with low jitter, the time information can be measured with subnanosecond resolution. The low power consumption of the ASIC can be further decreased using power gating techniques. Future versions of KLauS are under development and will incorporate an ADC with a resolution of up to 12-bits and blocks for digital data transmission. The chip is used in a setup for mass testing and characterization of scintillator tiles for the AHCAL ...

  6. Development of a low-noise, 4th-order readout ASIC for CdZnTe detectors in gamma spectrometer applications

    Science.gov (United States)

    Wang, Jia; Su, Lin; Wei, Xiaomin; Zheng, Ran; Hu, Yann

    2016-09-01

    This paper presents an ASIC readout circuit development, which aims to achieve low noise. In order to compensate the leakage current and improve gain, a dual-stage CSA has been utilized. A 4th-order high-linearity shaper is proposed to obtain a Semi-Gaussian wave and further decrease the noise induced by the leakage current. The ASIC has been designed and fabricated in a standard commercial 2P4M 0.35 μm CMOS process. Die area of one channel is about 1190 μm×147 μm. The input charge range is 1.8 fC. The peaking time can be adjusted from 1 μs to 3 μs. Measured ENC is about 55e- (rms) at input capacitor of 0 F. The gain is 271 mV/fC at the peaking time of 1 μs.

  7. Converting Relational Database Into Xml Document

    Directory of Open Access Journals (Sweden)

    Kanagaraj.S

    2012-03-01

    Full Text Available XML (Extensible Markup Language is emerging and gradually accepted as the standard for data interchange in the Internet world. Interoperation of relational database and XML database involves schema and data translations. Through EER (extended entity relationship model can convert the schema of relational database into XML. The semantics of the relational database, captured in EER diagram, are mapped to XML schema using stepwise procedures and mapped to XML document under the definitions of the XML schema. Converting Relational Database into XML Document is a process of converting the existing databases into XML file format. Existing conversion techniques convert a single database into xml. The proposed approach performs the conversion of databases like Ms-Access, MS-SQL to XML file format. Read the tables information from the corresponding database and generate code for the appropriate databases and convert the tables into XML flat file format. This converted XML file is been presented to the user.

  8. Radiation-Tolerant DC-DC Converters

    Science.gov (United States)

    Skutt, Glenn; Sable, Dan; Leslie, Leonard; Graham, Shawn

    2012-01-01

    A document discusses power converters suitable for space use that meet the DSCC MIL-PRF-38534 Appendix G radiation hardness level P classification. A method for qualifying commercially produced electronic parts for DC-DC converters per the Defense Supply Center Columbus (DSCC) radiation hardened assurance requirements was developed. Development and compliance testing of standard hybrid converters suitable for space use were completed for missions with total dose radiation requirements of up to 30 kRad. This innovation provides the same overall performance as standard hybrid converters, but includes assurance of radiation- tolerant design through components and design compliance testing. This availability of design-certified radiation-tolerant converters can significantly reduce total cost and delivery time for power converters for space applications that fit the appropriate DSCC classification (30 kRad).

  9. Linearity enhancement design of a 16-channel low-noise front-end readout ASIC for CdZnTe detectors

    Science.gov (United States)

    Zeng, Huiming; Wei, Tingcun; Wang, Jia

    2017-03-01

    A 16-channel front-end readout application-specific integrated circuit (ASIC) with linearity enhancement design for cadmium zinc telluride (CdZnTe) detectors is presented in this paper. The resistors in the slow shaper are realized using a high-Z circuit to obtain constant resistance value instead of using only a metal-oxide-semiconductor (MOS) transistor, thus the shaping time of the slow shaper can be kept constant for different amounts of input energies. As a result, the linearity of conversion gain is improved significantly. The ASIC was designed and fabricated in a 0.35 μm CMOS process with a die size of 2.60 mm×3.53 mm. The tested results show that a typical channel provides an equivalent noise charge (ENC) of 109.7e-+16.3e-/pF with a power consumption of 4 mW and achieves a conversion gain of 87 mV/fC with a nonlinearity of <0.4%. The linearity of conversion gain is improved by at least 86.6% as compared with the traditional approaches using the same front-end readout architecture and manufacture process. Moreover, the inconsistency among channels is <0.3%. An energy resolution of 2.975 keV (FWHM) for gamma rays of 59.5 keV was measured by connecting the ASIC to a 5 mm×5 mm ×2 mm CdZnTe detector at room temperature. The front-end readout ASIC presented in this paper achieves an outstanding linearity performance without compromising the noise, power consumption, and chip size performances.

  10. VEGA: A low-power front-end ASIC for large area multi-linear X-ray silicon drift detectors: Design and experimental characterization

    Science.gov (United States)

    Ahangarianabhari, Mahdi; Macera, Daniele; Bertuccio, Giuseppe; Malcovati, Piero; Grassi, Marco

    2015-01-01

    We present the design and the first experimental characterization of VEGA, an Application Specific Integrated Circuit (ASIC) designed to read out large area monolithic linear Silicon Drift Detectors (SDD's). VEGA consists of an analog and a digital/mixed-signal section to accomplish all the functionalities and specifications required for high resolution X-ray spectroscopy in the energy range between 500 eV and 50 keV. The analog section includes a charge sensitive preamplifier, a shaper with 3-bit digitally selectable shaping times from 1.6 μs to 6.6 μs and a peak stretcher/sample-and-hold stage. The digital/mixed-signal section includes an amplitude discriminator with coarse and fine threshold level setting, a peak discriminator and a logic circuit to fulfill pile-up rejection, signal sampling, trigger generation, channel reset and the preamplifier and discriminators disabling functionalities. A Serial Peripherical Interface (SPI) is integrated in VEGA for loading and storing all configuration parameters in an internal register within few microseconds. The VEGA ASIC has been designed and manufactured in 0.35 μm CMOS mixed-signal technology in single and 32 channel versions with dimensions of 200 μm×500 μm per channel. A minimum intrinsic Equivalent Noise Charge (ENC) of 12 electrons r.m.s. at 3.6 μs peaking time and room temperature is measured and the linearity error is between -0.9% and +0.6% in the whole input energy range. The total power consumption is 481 μW and 420 μW per channel for the single and 32 channels version, respectively. A comparison with other ASICs for X-ray SDD's shows that VEGA has a suitable low noise and offers high functionality as ADC-ready signal processing but at a power consumption that is a factor of four lower than other similar existing ASICs.

  11. VEGA: A low-power front-end ASIC for large area multi-linear X-ray silicon drift detectors: Design and experimental characterization

    Energy Technology Data Exchange (ETDEWEB)

    Ahangarianabhari, Mahdi; Macera, Daniele [Politecnico di Milano, Department of Electronics Engineering, Information Science and Bioengineering, P.za L. da Vinci 32, 20133 Milano (Italy); National Institute of Nuclear Physics, INFN sez. Milano (Italy); Bertuccio, Giuseppe, E-mail: Giuseppe.Bertuccio@polimi.it [Politecnico di Milano, Department of Electronics Engineering, Information Science and Bioengineering, P.za L. da Vinci 32, 20133 Milano (Italy); National Institute of Nuclear Physics, INFN sez. Milano (Italy); Malcovati, Piero; Grassi, Marco [University of Pavia, Department of Electrical Engineering, and National Institute of Nuclear Physics, INFN sez. Pavia, Pavia (Italy)

    2015-01-11

    We present the design and the first experimental characterization of VEGA, an Application Specific Integrated Circuit (ASIC) designed to read out large area monolithic linear Silicon Drift Detectors (SDD’s). VEGA consists of an analog and a digital/mixed-signal section to accomplish all the functionalities and specifications required for high resolution X-ray spectroscopy in the energy range between 500 eV and 50 keV. The analog section includes a charge sensitive preamplifier, a shaper with 3-bit digitally selectable shaping times from 1.6 µs to 6.6 µs and a peak stretcher/sample-and-hold stage. The digital/mixed-signal section includes an amplitude discriminator with coarse and fine threshold level setting, a peak discriminator and a logic circuit to fulfill pile-up rejection, signal sampling, trigger generation, channel reset and the preamplifier and discriminators disabling functionalities. A Serial Peripherical Interface (SPI) is integrated in VEGA for loading and storing all configuration parameters in an internal register within few microseconds. The VEGA ASIC has been designed and manufactured in 0.35 µm CMOS mixed-signal technology in single and 32 channel versions with dimensions of 200 µm×500 µm per channel. A minimum intrinsic Equivalent Noise Charge (ENC) of 12 electrons r.m.s. at 3.6 µs peaking time and room temperature is measured and the linearity error is between −0.9% and +0.6% in the whole input energy range. The total power consumption is 481 µW and 420 µW per channel for the single and 32 channels version, respectively. A comparison with other ASICs for X-ray SDD’s shows that VEGA has a suitable low noise and offers high functionality as ADC-ready signal processing but at a power consumption that is a factor of four lower than other similar existing ASICs.

  12. Regeneration of ZVS converter with Resonant inductor

    Directory of Open Access Journals (Sweden)

    J.Sivavara Prasad

    2011-09-01

    Full Text Available This paper presents an analysis of the regeneration of zero-voltage-switching converter with resonant inductor, quasi-resonant converters, and full-bridge zero-voltage-switched PWM Converter. The design of a clamping circuit considering a saturable resonant inductor is presented and compared with the design of a clamping circuit with a linear resonant inductor. A diode model with reverse recovery is employed to simulate the effects.

  13. Ocean floor mounting of wave energy converters

    Science.gov (United States)

    Siegel, Stefan G

    2015-01-20

    A system for mounting a set of wave energy converters in the ocean includes a pole attached to a floor of an ocean and a slider mounted on the pole in a manner that permits the slider to move vertically along the pole and rotate about the pole. The wave energy converters can then be mounted on the slider to allow adjustment of the depth and orientation of the wave energy converters.

  14. Commutation Processes in Multiresonant ZVS Bridge Converter

    Directory of Open Access Journals (Sweden)

    Miroslaw Luft

    2008-01-01

    Full Text Available The analysis of the multiresonant ZVS DC/DC bridge converter is presented. The control system of the converter is basedon the method of frequency control at the constant time of transistor turn-off with a phase shift. The operation of the circuit is givenand the operating range of the converter is defined where ZVS switching operation is assured. Control characteristics are given andthe converter’s efficiency is defined. The circuit’s operation is analysed on the basis of results of the converter simulation tests using Simplorer programme.

  15. DC/DC Converter Stability Testing Study

    Science.gov (United States)

    Wang, Bright L.

    2008-01-01

    This report presents study results on hybrid DC/DC converter stability testing methods. An input impedance measurement method and a gain/phase margin measurement method were evaluated to be effective to determine front-end oscillation and feedback loop oscillation. In particular, certain channel power levels of converter input noises have been found to have high degree correlation with the gain/phase margins. It becomes a potential new method to evaluate stability levels of all type of DC/DC converters by utilizing the spectral analysis on converter input noises.

  16. Reliability of Power Electronic Converter Systems

    DEFF Research Database (Denmark)

    -link capacitance in power electronic converter systems; wind turbine systems; smart control strategies for improved reliability of power electronics system; lifetime modelling; power module lifetime test and state monitoring; tools for performance and reliability analysis of power electronics systems; fault......-tolerant adjustable speed drive systems; mission profile oriented reliability design in wind turbine and photovoltaic systems; reliability of power conversion systems in photovoltaic applications; power supplies for computers; and high-power converters. Reliability of Power Electronic Converter Systems is essential...... reading for researchers, professionals and students working with power electronics and their applications, particularly those specializing in the development and application of power electronic converters and systems....

  17. High-speed low-power analog ASICs for a 3D neuroprocessor

    Science.gov (United States)

    Duong, Tuan A.; Kemeny, Sabrina E.; Tran, Mua D.; Daud, Taher; Thakoor, Anilkumar P.

    1995-03-01

    A particularly challenging neural network application requiring high-speed and intensive image processing capability is target acquisition and discrimination. It requires spatio-temporal recognition of point and resolved targets at high speeds. A reconfigurable neural architecture may discriminate targets from clutter or classify targets once resolved. By mating a 64 X 64 pixel array infrared (IR) image sensor to a 3-D stack (cube) of 64 neural-net ICs along respective edges, every pixel would directly input to a neural network, thereby processing the information with full parallelism. However, the `cube' has to operate at 90 degree(s)K with processing speed and approximately 2 watts of power dissipation. Analog circuitry, where the spatially parallel input to the neural networks is also analog, would make this possible. Digital neural processing would require analog-to-digital converters on each IC, impractical with the power constraint. A versatile reconfigurable circuit is presented that offers a variety of neural architectures: multilayer perceptron, cascade backpropagation, and template matching with winner-take-all (WTA) circuitry. Special designs of analog neuron and synapse implemented in VLSI are presented which bear out high speed response both at room and low temperatures with synapse-neuron signal propagation times of approximately 100 ns.

  18. Dedicated multichannel readout ASIC coupled with single crystal diamond for dosimeter application

    Science.gov (United States)

    Fabbri, A.; Falco, M. D.; De Notaristefani, F.; Galasso, M.; Marinelli, M.; Orsolini Cencelli, V.; Tortora, L.; Verona, C.; Verona Rinati, G.

    2013-02-01

    This paper reports on the tests of a low-noise, multi-channel readout integrated circuit used as a readout electronic front-end for a diamond multi-pixel dosimeter. The system is developed for dose distribution measurement in radiotherapy applications. The first 10-channel prototype chip was designed and fabricated in a 0.18 um CMOS process. Every channel includes a charge integrator with a 10 pF capacitor and a double slope A/D converter. The diamond multi-pixel detector, based on CVD synthetic single crystal diamond Schottky diodes, is made by a 3 × 3 sensor matrix. The overall device has been tested under irradiation with 6 MeV radio therapeutic photon beams at the Policlinico ``Tor Vergata'' (PTV) hospital. Measurements show a 20 fA RMS leakage current from the front-end input stage and a negligible dark current from the diamond detector, a stable temporal response and a good linear behaviour as a function of both dose and dose rate. These characteristics were common to each tested channel.

  19. Conceptual design of the TRACE detector readout using a compact, dead time-less analog memory ASIC

    Science.gov (United States)

    Aliaga, R. J.; Herrero-Bosch, V.; Capra, S.; Pullia, A.; Dueñas, J. A.; Grassi, L.; Triossi, A.; Domingo-Pardo, C.; Gadea, R.; González, V.; Hüyük, T.; Sanchís, E.; Gadea, A.; Mengoni, D.

    2015-11-01

    The new TRacking Array for light Charged particle Ejectiles (TRACE) detector system requires monitorization and sampling of all pulses in a large number of channels with very strict space and power consumption restrictions for the front-end electronics and cabling. Its readout system is to be based on analog memory ASICs with 64 channels each that sample a 1 μs window of the waveform of any valid pulses at 200 MHz while discarding any other signals and are read out at 50 MHz with external ADC digitization. For this purpose, a new, compact analog memory architecture is described that allows pulse capture with zero dead time in any channel while vastly reducing the total number of storage cells, particularly for large amounts of input channels. This is accomplished by partitioning the typical Switched Capacitor Array structure into two pipelined, asymmetric stages and introducing FIFO queue-like control circuitry for captured data, achieving total independence between the capture and readout operations.

  20. Characteristics of a multichannel low-noise front-end ASIC for CZT-based small animal PET imaging

    Science.gov (United States)

    Gao, W.; Liu, H.; Gan, B.; Hu, Y.

    2014-05-01

    In this paper, we present the design and characteristics of a novel low-noise front-end readout application-specific integrated circuit dedicated to CdZnTe (CZT) detectors for a small animal PET imaging system. A low-noise readout method based on the charge integration and the delayed peak detection is proposed. An eight-channel front-end readout prototype chip is designed and implemented in a 0.35 μm CMOS process. The die size is 2.3 mm ×2.3 mm. The prototype chip is tested in different methods including electronic test, energy spectrum test and irradiation test. The input range of the ASIC is from 2000e- to 180,000e-, reflecting the energy of the gamma ray from 11.2 keV to 1 MeV. The gain of the readout channel is 65 mV/fC at the shaping time of 1 μs. The best test result of the equivalent noise charge (ENC) is 58.9 e- at zero farad plus 5.4 e- per picofarad. The nonlinearity and the crosstalk are less than 3% and less than 2%, respectively, at the room temperature. The static power dissipation is about 3 mW/channel.

  1. Characteristics of a multichannel low-noise front-end ASIC for CZT-based small animal PET imaging

    Energy Technology Data Exchange (ETDEWEB)

    Gao, W., E-mail: gaowu@nwpu.edu.cn [Institute of Microelectronics, School of Computer S and T, Northwestern Polytechnical University, Xi’an (China); Liu, H., E-mail: newhui.cn@gmail.com [Institute of Microelectronics, School of Computer S and T, Northwestern Polytechnical University, Xi’an (China); Gan, B., E-mail: shadow524@163.com [Institute of Microelectronics, School of Computer S and T, Northwestern Polytechnical University, Xi’an (China); Hu, Y., E-mail: Yann.Hu@ires.in2p3.fr [Institut Pluridisciplinaire Hubert Curien, IN2P3/CNRS/UDS, Strasbourg (France)

    2014-05-01

    In this paper, we present the design and characteristics of a novel low-noise front-end readout application-specific integrated circuit dedicated to CdZnTe (CZT) detectors for a small animal PET imaging system. A low-noise readout method based on the charge integration and the delayed peak detection is proposed. An eight-channel front-end readout prototype chip is designed and implemented in a 0.35 μm CMOS process. The die size is 2.3 mm ×2.3 mm. The prototype chip is tested in different methods including electronic test, energy spectrum test and irradiation test. The input range of the ASIC is from 2000e{sup −} to 180,000e{sup −}, reflecting the energy of the gamma ray from 11.2 keV to 1 MeV. The gain of the readout channel is 65 mV/fC at the shaping time of 1 μs. The best test result of the equivalent noise charge (ENC) is 58.9 e{sup −} at zero farad plus 5.4 e{sup −} per picofarad. The nonlinearity and the crosstalk are less than 3% and less than 2%, respectively, at the room temperature. The static power dissipation is about 3 mW/channel.

  2. A 65 nm pixel readout ASIC with quick transverse momentum discrimination capabilities for the CMS Tracker at HL-LHC

    Science.gov (United States)

    Ceresa, D.; Kaplon, J.; Francisco, R.; Caratelli, A.; Kloukinas, K.; Marchioro, A.

    2016-01-01

    A readout ASIC for the hybrid pixel detector with the capability of performing quick recognition of particles with high transverse momentum has been designed for the requirements of the CMS Outer Tracker at the High Luminosity LHC . The particle momentum dicrimination capability represents the main challenge for this design together with the low power requirement: the constraint of low mass for the new tracker dictates a total power budget of less than 100 mW/cm2. The choice of a 65 nm CMOS technology has made it possible to satisfy this power requirement despite the fairly large amount of logic necessary to perform the momentum discrimination and the continuous operation at 40 MHz. Several techniques for low power have been used to implement this logic that performs cluster reduction, position offset correction and coordinate encoding. A prototype chip including a large part of the final functionality and the full front-end has been realized and comprises a matrix of 16 by 3 rectangular pixels of 100 μm × 1446 μm, providing 7.65 mm2 of segmented active area. Measurements of the analog front-end characteristics closely match the simulations and confirm the consumption of < 30 μA per pixel. Front-end characterization and irradiation results up to 150 MRad are also reported.

  3. Single Event Effect Hardness for the Front-end ASICs Applied in BGO Calorimeter of DAMPE Satellite

    CERN Document Server

    Gao, Shan-Shan; Feng, Chang-Qing; Xi, Kai; Liu, Shu-Bin; An, Qi

    2016-01-01

    Dark Matter Particle Explorer (DAMPE) is a Chinese scientific satellite designed for cosmic ray study with a primary scientific goal of indirect search of dark matter particles. As a crucial sub-detector, BGO calorimeter measures the energy spectrum of cosmic rays in the energy range from 5 GeV to 10 TeV. In order to implement high-density front-end electronics (FEE) with the ability to measure 1848 signals from 616 photomultiplier tubes on the strictly constrained satellite platform, two kinds of 32-channel front-end ASICs, VA160 and VATA160, are customized. However, a space mission period of more than 3 years makes single event effect (SEE) a probable threat to reliability. In order to evaluate the SEE sensitivity of the chips and verify the effectiveness of mitigation methods, a series of laser-induced and heavy ion-induced SEE tests were performed. Benefiting from the single event latch-up (SEL) protection circuit for power supply, the triple module redundancy (TMR) technology for the configuration regist...

  4. Back-end and interface implementation of the STS-XYTER2 prototype ASIC for the CBM experiment

    Science.gov (United States)

    Kasinski, K.; Szczygiel, R.; Zabolotny, W.

    2016-11-01

    Each front-end readout ASIC for the High-Energy Physics experiments requires robust and effective hit data streaming and control mechanism. A new STS-XYTER2 full-size prototype chip for the Silicon Tracking System and Muon Chamber detectors in the Compressed Baryonic Matter experiment at Facility for Antiproton and Ion Research (FAIR, Germany) is a 128-channel time and amplitude measuring solution for silicon microstrip and gas detectors. It operates at 250 kHit/s/channel hit rate, each hit producing 27 bits of information (5-bit amplitude, 14-bit timestamp, position and diagnostics data). The chip back-end implements fast front-end channel read-out, timestamp-wise hit sorting, and data streaming via a scalable interface implementing the dedicated protocol (STS-HCTSP) for chip control and hit transfer with data bandwidth from 9.7 MHit/s up to 47 MHit/s. It also includes multiple options for link diagnostics, failure detection, and throttling features. The back-end is designed to operate with the data acquisition architecture based on the CERN GBTx transceivers. This paper presents the details of the back-end and interface design and its implementation in the UMC 180 nm CMOS process.

  5. A 65 nm pixel readout ASIC with quick transverse momentum discrimination capabilities for the CMS Tracker at HL-LHC

    CERN Document Server

    AUTHOR|(CDS)2084503; Kaplon, J; Francisco, R; Caratelli, Alessandro; Kloukinas, Konstantinos; Marchioro, Alessandro

    2016-01-01

    A readout ASIC for the hybrid pixel detector with the capability of performing quick recognition of particles with high transverse momentum has been designed for the requirements of the CMS Outer Tracker at the High Luminosity LHC. The particle momentum dicrimination capability represents the main challenge for this design together with the low power requirement: the constraint of low mass for the new tracker dictates a total power budget of less than 100\\,mW/cm$^2$. The choice of a 65\\,nm CMOS technology has made it possible to satisfy this power requirement despite the fairly large amount of logic necessary to perform the momentum discrimination and the continuous operation at 40\\,MHz. Several techniques for low power have been used to implement this logic that performs cluster reduction, position offset correction and coordinate encoding. A prototype chip including a large part of the final functionality and the full front-end has been realized and comprises a matrix of 16 by 3 rectangular pixels of 100\\,$...

  6. Power Converters Secure Electronics in Harsh Environments

    Science.gov (United States)

    2013-01-01

    In order to harden power converters for the rigors of space, NASA awarded multiple SBIR contracts to Blacksburg, Virginia-based VPT Inc. The resulting hybrid DC-DC converters have proven valuable in aerospace applications, and as a result the company has generated millions in revenue from the product line and created four high-tech jobs to handle production.

  7. Input-output rearrangement of isolated converters

    DEFF Research Database (Denmark)

    Madsen, Mickey Pierre; Kovacevic, Milovan; Mønster, Jakob Døllner;

    2015-01-01

    is not a requirement. The proposed technique is particularly valuable in power conversion at very high frequencies, and may be combined with other stress reduction methods. Finally, the new arrangements are experimentally verified both on off the shelf converters and on a VHF resonant SEPIC converter. All results...

  8. High Precision Current Measurement for Power Converters

    CERN Document Server

    Cerqueira Bastos, M

    2015-01-01

    The accurate measurement of power converter currents is essential to controlling and delivering stable and repeatable currents to magnets in particle accelerators. This paper reviews the most commonly used devices for the measurement of power converter currents and discusses test and calibration methods.

  9. High-Efficiency dc/dc Converter

    Science.gov (United States)

    Sturman, J.

    1982-01-01

    High-efficiency dc/dc converter has been developed that provides commonly used voltages of plus or minus 12 Volts from an unregulated dc source of from 14 to 40 Volts. Unique features of converter are its high efficiency at low power level and ability to provide output either larger or smaller than input voltage.

  10. Present trends in HVDC converter station design

    Energy Technology Data Exchange (ETDEWEB)

    Carlsson, Lennart; Asplund, Gunnar; Bjorklund, Hans; Flisberg, Gunnar [ABB Power Systems AB, Ludvika (Sweden)

    1994-12-31

    HVDC converter station technology has developed rapidly to satisfy increasing requirements during past 10 - 15 years, but there has not been any dramatic changes since thyristor valves were introduced in the mid 70s. This paper describes some recent and expected future developments, that will substantiality change and simplify future converter stations. (author) 4 refs., 7 figs.

  11. Multilevel converters for 10 MW Wind Turbines

    DEFF Research Database (Denmark)

    Ma, Ke; Blaabjerg, Frede

    2011-01-01

    Several promising multi-level converter configurations for 10 MW Wind Turbines both with direct drive and one-stage gear box drive using Permanent Magnet Synchronous Generator (PMSG) are proposed, designed and compared. Reliability is a crucial indicator for large scale wind power converters...

  12. Modeling and Simulation of Matrix Converter

    DEFF Research Database (Denmark)

    Liu, Fu-rong; Klumpner, Christian; Blaabjerg, Frede

    2005-01-01

    This paper discusses the modeling and simulation of matrix converter. Two models of matrix converter are presented: one is based on indirect space vector modulation and the other is based on power balance equation. The basis of these two models is• given and the process on modeling is introduced...

  13. Radiation Effects on DC-DC Converters

    Science.gov (United States)

    Zhang, De-Xin; AbdulMazid, M. D.; Attia, John O.; Kankam, Mark D. (Technical Monitor)

    2001-01-01

    In this work, several DC-DC converters were designed and built. The converters are Buck Buck-Boost, Cuk, Flyback, and full-bridge zero-voltage switched. The total ionizing dose radiation and single event effects on the converters were investigated. The experimental results for the TID effects tests show that the voltages of the Buck Buck-Boost, Cuk, and Flyback converters increase as total dose increased when using power MOSFET IRF250 as a switching transistor. The change in output voltage with total dose is highest for the Buck converter and the lowest for Flyback converter. The trend of increase in output voltages with total dose in the present work agrees with those of the literature. The trends of the experimental results also agree with those obtained from PSPICE simulation. For the full-bridge zero-voltage switch converter, it was observed that the dc-dc converter with IRF250 power MOSFET did not show a significant change of output voltage with total dose. In addition, for the dc-dc converter with FSF254R4 radiation-hardened power MOSFET, the output voltage did not change significantly with total dose. The experimental results were confirmed by PSPICE simulation that showed that FB-ZVS converter with IRF250 power MOSFET's was not affected with the increase in total ionizing dose. Single Event Effects (SEE) radiation tests were performed on FB-ZVS converters. It was observed that the FB-ZVS converter with the IRF250 power MOSFET, when the device was irradiated with Krypton ion with ion-energy of 150 MeV and LET of 41.3 MeV-square cm/mg, the output voltage increased with the increase in fluence. However, for Krypton with ion-energy of 600 MeV and LET of 33.65 MeV-square cm/mg, and two out of four transistors of the converter were permanently damaged. The dc-dc converter with FSF254R4 radiation hardened power MOSFET's did not show significant change at the output voltage with fluence while being irradiated by Krypton with ion energy of 1.20 GeV and LET of 25

  14. SPECTRAL ANALYSIS OF BUCK AND SEPIC CONVERTERS

    Directory of Open Access Journals (Sweden)

    CHAKIB ALAOUI

    2011-02-01

    Full Text Available Switched mode power converters generate harmonic currents, which will be injected into the utility grid, causing distortion of the utility waveform. They also become a source for the generation of EMI, which may affect the communication systems. This work is about the design and evaluation of the two most frequently used SMPS used in step down mode of operation: the Buck converter and the Sepic converter working in step-down mode of operation. These converters were designed using optimized equations for their components ratings. Simulation results show that although the Buck output voltage is low in harmonics, it has high harmonic contents in currents circulating in its inductor and diode, and hence requires strong filtering. The Sepic converterhas lower harmonic contents than the Buck converter.

  15. Periodic Control of Power Electronic Converters

    DEFF Research Database (Denmark)

    Zhou, Keliang; Danwei, Wang; Yang, Yongheng

    Advanced power electronic converters convert, control and condition electricity. Power converters require control strategies for periodic signal compensation to assure good power quality and stable power system operation. This comprehensive text presents the most recent internal model principle...... based periodic control technology, which offers the perfect periodic control solution for power electronic conversion. It also provides complete analysis and synthesis methods for periodic control systems, and plenty of practical examples to demonstrate the validity of proposed periodic control...... technology for power converters. It proposes a unified framework for housing periodic control schemes for power converters, and provides a general proportional-integral-derivative control solution to periodic signal compensation in extensive engineering applications. Periodic Control of Power Electronic...

  16. Qualitative model of a plasma photoelectric converter

    Science.gov (United States)

    Gorbunov, N. A.; Flamant, G.

    2009-01-01

    A converter of focused optical radiation into electric current is considered on the basis of the photovoltaic effect in plasmas. The converter model is based on analysis of asymmetric spatial distributions of charge particle number density and ambipolar potential in the photoplasma produced by external optical radiation focused in a heat pipe filled with a mixture of alkali vapor and a heavy inert gas. Energy balance in the plasma photoelectric converter is analyzed. The conditions in which the external radiation energy is effectively absorbed in the converter are indicated. The plasma parameters for which the energy of absorbed optical radiation is mainly spent on sustaining the ambipolar field in the plasma are determined. It is shown that the plasma photoelectric converter makes it possible to attain a high conversion efficiency for focused solar radiation.

  17. Modelling, analyses and design of switching converters

    Science.gov (United States)

    Cuk, S. M.; Middlebrook, R. D.

    1978-01-01

    A state-space averaging method for modelling switching dc-to-dc converters for both continuous and discontinuous conduction mode is developed. In each case the starting point is the unified state-space representation, and the end result is a complete linear circuit model, for each conduction mode, which correctly represents all essential features, namely, the input, output, and transfer properties (static dc as well as dynamic ac small-signal). While the method is generally applicable to any switching converter, it is extensively illustrated for the three common power stages (buck, boost, and buck-boost). The results for these converters are then easily tabulated owing to the fixed equivalent circuit topology of their canonical circuit model. The insights that emerge from the general state-space modelling approach lead to the design of new converter topologies through the study of generic properties of the cascade connection of basic buck and boost converters.

  18. A novel power converter for photovoltaic applications

    Science.gov (United States)

    Yuvarajan, S.; Yu, Dachuan; Xu, Shanguang

    A simple and economical power conditioner to convert the power available from solar panels into 60 Hz ac voltage is described. The raw dc voltage from the solar panels is converted to a regulated dc voltage using a boost converter and a large capacitor and the dc output is then converted to 60 Hz ac using a bridge inverter. The ratio between the load current and the short-circuit current of a PV panel at maximum power point is nearly constant for different insolation (light) levels and this property is utilized in designing a simple maximum power point tracking (MPPT) controller. The controller includes a novel arrangement for sensing the short-circuit current without disturbing the operation of the PV panel and implementing MPPT. The switching losses in the inverter are reduced by using snubbers. The results obtained on an experimental converter are presented.

  19. PERFORMANCE ANALYSIS OF 2D CONVERTER BY COMBINING SR & KY CONVERTERS

    Directory of Open Access Journals (Sweden)

    V. Manoj Kumar

    2014-03-01

    Full Text Available Most of the portable equipments use battery as power source. The increasing use of low voltage portable devices and growing requirements of functionalities embedded into such devices. Thus an efficient power management technique is needed for longer battery life for them. Highly variable nature of batteries systems often require supply voltages to be both higher and lower than the battery. This is most efficiently generated by a buck-boost switching converter. But here the converter efficiency is decreased since the power loss occurs in the storage devices. Step by step, process of designing, feedback control and simulation of a novel voltage-buck boost converter, combining KY and synchronous Rectifier buck converter for battery power applications. Unlike the traditional buck–boost converter, this converter has the positive output voltage and system is stable, different from the negative output voltage and low stable of the traditional inverting buck–boost converters. Since such a converter operates in continuous conduction mode. Also it possesses the non-pulsating output current, thereby not only decreasing the current stress on the output capacitor but also reducing the output voltage ripple. Both the KY converter and the synchronous buck converter, combined into a positive buck– boost converter, uses the same power switches. Here it makes the circuit to be compact and the corresponding cost to be down. Voltage conversion ratio is 2D,so it is also called 2D converter.

  20. Underwater noise from a wave energy converter

    DEFF Research Database (Denmark)

    Tougaard, Jakob

    A recent addition to the anthropogenic sources of underwater noise is offshore wave energy converters. Underwater noise was recorded from the Wavestar wave energy converter located at Hastholm, Denmark (57°7.73´N, 8°37.23´E). The Wavestar is a full-scale test and demonstration converter...... in full operation and start and stop of the converter. Median broad band (10 Hz – 20 kHz) sound pressure level (Leq) was 123 dB re. 1 Pa, irrespective of status of the wave energy converter (stopped, running or starting/stopping). The most pronounced peak in the third-octave spectrum was in the 160 Hz...... significant noise above ambient could be detected above the 250 Hz band. The absolute increase in noise above ambient was very small. L50 third-octave levels in the four bands with the converter running were thus only 1-2 dB above ambient L50 levels. The noise recorded 25 m from the wave energy converter...

  1. Electromagnetic Compatibility of Matrix Converter System

    Directory of Open Access Journals (Sweden)

    S. Fligl

    2006-12-01

    Full Text Available The presented paper deals with matrix converters pulse width modulation strategies design with emphasis on the electromagnetic compatibility. Matrix converters provide an all-silicon solution to the problem of converting AC power from one frequency to another, offering almost all the features required of an ideal static frequency changer. They possess many advantages compared to the conventional voltage or current source inverters. A matrix converter does not require energy storage components as a bulky capacitor or an inductance in the DC-link, and enables the bi-directional power flow between the power supply and load. The most of the contemporary modulation strategies are able to provide practically sinusoidal waveforms of the input and output currents with negligible low order harmonics, and to control the input displacement factor. The perspective of matrix converters regarding EMC in comparison with other types of converters is brightly evident because it is no need to use any equipment for power factor correction and current and voltage harmonics reduction. Such converter with proper control is properly compatible both with the supply mains and with the supplied load. A special digital control system was developed for the realized experimental test bed which makes it possible to achieve greater throughput of the digital control system and its variability.

  2. Propagation characteristics of converted refracted wave and its application in static correction of converted wave

    Institute of Scientific and Technical Information of China (English)

    2008-01-01

    Three-component seismic exploration through P-wave source and three-component geophone is an effective technique used in complicated reservoir exploration. In three-component seismic exploration data processing,one of the difficulties is static correction of converted wave. This paper analyzes propagation characteristics of non-converted and converted refracted waves,and discovers a favor-able condition for the formation of converted refracted wave,i.e. the velocity of overlaying medium S wave is much lower than that of underlying medium S wave. In addition,the paper proposes the static correction method of converted wave based on PPS converted refracted wave,and processes the real three-component seismic data with better results of static correction of converted wave.

  3. Time interleaved counter analog to digital converters

    OpenAIRE

    Danesh, Seyed Amir Ali

    2011-01-01

    The work explores extending time interleaving in A/D converters, by applying a high-level of parallelism to one of the slowest and simplest types of data-converters, the counter ADC. The motivation for the work is to realise high-performance re-configurable A/D converters for use in multi-standard and multi-PHY communication receivers with signal bandwidths in the 10s to 100s of MHz. The counter ADC requires only a comparator, a ramp signal, and a digital counter, where the ...

  4. Data Converter for Multistandard Mobile Phones

    DEFF Research Database (Denmark)

    Yurttas, Aziz; Bruun, Erik; Jensen, Rasmus Glarborg

    2004-01-01

    This paper describes an analog to digital converter (ADC) for mobile communication systems using a direct down conversion architecture. The ADC can be programmed to meet the requirements of different communication standards, including GSM (Global System for Mobile communication) and WCDMA (Wideband...... Code Division Multiple Access). The ADC is realized with a pipeline ADC architecture for WCDMA and a Sigma-Delta architecture for GSM. In order to have an optimized area and power consumption, the basic building blocks (opamps) of the converters are shared between the two converter architectures...

  5. Selective harmonic control for power converters

    DEFF Research Database (Denmark)

    Zhou, Keliang; Yang, Yongheng; Blaabjerg, Frede;

    2014-01-01

    This paper proposes an Internal Model Principle (IMP) based Selective Harmonic Controller (SHC) for power converters. The proposed SHC offers an optimal control solution for power converters to mitigate power harmonics. It makes a good trade-off among cost, complexity and performance. It has high...... accuracy and fast transient response, and it is cost-effective, easy for real-time implementation, and compatible for design rules-of-thumb. An application on a three-phase PWM converter has confirmed the effectiveness of the proposed control scheme in terms of harmonic mitigation....

  6. High-power converters and AC drives

    CERN Document Server

    Wu, Bin

    2017-01-01

    This new edition reflects the recent technological advancements in the MV drive industry, such as advanced multilevel converters and drive configurations. It includes three new chapters, Control of Synchronous Motor Drives, Transformerless MV Drives, and Matrix Converter Fed Drives. In addition, there are extensively revised chapters on Multilevel Voltage Source Inverters and Voltage Source Inverter-Fed Drives. This book includes a systematic analysis on a variety of high-power multilevel converters, illustrates important concepts with simulations and experiments, introduces various megawatt drives produced by world leading drive manufacturers, and addresses practical problems and their mitigations methods.

  7. Reliability of power electronic converter systems

    CERN Document Server

    Chung, Henry Shu-hung; Blaabjerg, Frede; Pecht, Michael

    2016-01-01

    This book outlines current research into the scientific modeling, experimentation, and remedial measures for advancing the reliability, availability, system robustness, and maintainability of Power Electronic Converter Systems (PECS) at different levels of complexity.

  8. A three-port direct current converter

    DEFF Research Database (Denmark)

    2016-01-01

    The three-port direct current converter comprising: at least one input direct current source; at least one storage battery; a primary side circuit; a secondary side circuit; a first single magnetic component shared by the primary side circuit and the secondary side circuit, wherein the primary side...... circuit comprises a connection between the at least one input direct current source and the at least one storage battery, the primary side circuit configured for operating as a buck converter; a second magnetic component serially coupled to the first single magnetic component, wherein the first and second...... magnetic components are configured to perform a voltage step-up, wherein the secondary side circuit comprises a connection between the at least one storage battery and at least one load, the secondary side configured for operating as a tapped boost converter; wherein the three-port direct current converter...

  9. Catalytic converters as a source of platinum

    Directory of Open Access Journals (Sweden)

    A. Fornalczyk

    2011-10-01

    Full Text Available The increase of Platinum Group Metals demand in automotive industry is connected with growing amount of cars equipped with the catalytic converters. The paper presents the review of available technologies during recycling process. The possibility of removing platinum from the used catalytic converters applying pyrometallurgical and hyrdometallurgical methods were also investigated. Metals such as Cu, Pb, Ca, Mg, Cd were used in the pyrometallurgical research (catalytic converter was melted with Cu, Pb and Ca or Mg and Cd vapours were blown through the whole carrier. In hydrometallurgical research catalytic converters was dissolved in aqua regia. Analysis of Pt contents in the carrier before and after the process was performed by means of atomic absorption spectroscopy. Obtained result were discussed.

  10. Interface of magnetoresistive converter of active power

    Directory of Open Access Journals (Sweden)

    A. I. Vytiaganets

    2009-10-01

    Full Text Available The vehicle and programmatic interfaces of magnetoresistive converter of active power are considered, the results of statistical treatment of the multiple measuring of active-power are analysed.

  11. "Forback" Dc-To-Dc Converters

    Science.gov (United States)

    Lukemire, Alan T.

    1992-01-01

    Dc-to-dc power-converter circuits called "forback" resemble circuits of standard configurations called "forward", "flyback", and "Cuk". Circuit employs minor modifications to existing topologies, combines advantages, while eliminating disadvantages, of older circuits.

  12. New PWM switched-mode converter topologies

    Science.gov (United States)

    Hua, Gui-Chao; Huang, Shi-Peng

    Two augmented switching cells are proposed from which four novel topologies can be derived: an augmented buck converter, an augmented boost converter, a novel switching power amplifier, and a novel switching controlled rectifier. The augmented buck and the augmented boost converters realize higher step-down and step-up ratios, respectively, under a given switch duty ratio by proper design of the turn ratios of the transformer and coupled inductor. The switching power amplifier achieves four-quadrant output by the use of two bidirectional current switches and a single power supply, while the inverse converter can be used as a switching controlled rectifier. The experimental verification of the power amplifier is presented.

  13. Switching power converters medium and high power

    CERN Document Server

    Neacsu, Dorin O

    2013-01-01

    An examination of all of the multidisciplinary aspects of medium- and high-power converter systems, including basic power electronics, digital control and hardware, sensors, analog preprocessing of signals, protection devices and fault management, and pulse-width-modulation (PWM) algorithms, Switching Power Converters: Medium and High Power, Second Edition discusses the actual use of industrial technology and its related subassemblies and components, covering facets of implementation otherwise overlooked by theoretical textbooks. The updated Second Edition contains many new figures, as well as

  14. Local Bifurcations in DC-DC Converters

    OpenAIRE

    2012-01-01

    Three local bifurcations in DC-DC converters are reviewed. They are period-doubling bifurcation, saddle-node bifurcation, and Neimark bifurcation. A general sampled-data model is employed to study the types of loss of stability of the nominal (periodic) solution and their connection with local bifurcations. More accurate prediction of instability and bifurcation than using the averaging approach is obtained. Examples of bifurcations associated with instabilities in DC-DC converters are given.

  15. Industrial application, 1MHz, quasi resonant converter

    OpenAIRE

    Carrasco Solís, Juan Manuel; Pérez Ridao, Francisco; Quero Reboul, José Manuel; Janer Jiménez, Carlos; García Franquelo, Leopoldo

    1993-01-01

    An industrial multi-output QRC converter is presented. Its main designing constraints are low cost, small in size, reduced EMI and EMC, high efficiency and severe dynamic behaviour in all outputs. Accomplishing this last restriction proved to be a difficult task. This has been done by means of a classical controller and cross regulation. The actual performance was tested on a 1MHz prototype rated at 50W. The low cost developed converter is characterized by its simplicity of design and operati...

  16. AC – AC Converters for UPS

    Directory of Open Access Journals (Sweden)

    Rusalin Lucian R. Păun

    2008-05-01

    Full Text Available This paper propose a new control technique forsingle – phase AC – AC converters used for a on-line UPSwith a good dynamic response, a reduced-partscomponents, a good output characteristic, a good powerfactorcorrection(PFC. This converter no needs anisolation transformer. A power factor correction rectifierand an inverter with the proposed control scheme has beendesigned and simulated using Caspoc2007, validating theconcept.

  17. LHC Power Converters: A Precision Game

    CERN Multimedia

    2001-01-01

    The LHC test-bed, String 2, is close to commissioning and one important element to get a first chance to prove what it can do is the power converter system. In String 2 there are 16 converters, in the full LHC there will be almost 1800. This article takes a look at what is so special about the power converters for the LHC. The 13 000 Amps power converters with the watercooled cables going to the String 2 feedboxes. The LHC's superconducting magnets will be the pinnacle of high technology. But to work, they'll need the help of high-precision power converters to supply them with extremely stable DC current. Perfection will be the name of the game, with an accuracy of just 1-2 parts per million (ppm) required. LEP, for the sake of comparison, could live with 10-20 ppm. The LHC's power converters will be very different from those of LEP or the SPS since the new accelerator's magnets are mostly superconducting. That means that they require much higher currents at a lower voltage since superconductors have no re...

  18. The FPGA Prototyping Verification of ASIC Based on TotalRecall Technology%基于TotalRecall技术ASIC的FPGA原型验证

    Institute of Scientific and Technical Information of China (English)

    郭安华; 黄世震

    2012-01-01

    Verification is a very important part in IG design. With the rapid development of FPGA, the FPGA prototype verification has been used widely in the ASIC. FPGA prototyping verification is an effective verification way of ASIC, but the visibility of traditional FPGA prototyping verification is poor. In order to solve the visibility problem of traditional FPGA prototyping verification, verification engineer uses a combination of TotalRecall technology FPGA prototyping verification method to verify a mouse chip. The result shows this method provides complete visibility and ensures FPGA prototyping verification at the real speed. This method has innovated ASIC verification methodology.%芯片设计中一个非常重要的环节是验证.随着FPGA技术的迅速发展使基于FPGA的原型验证被广泛的用于ASIC的开发过程,FPGA原型验证是ASIC有效的验证途径,但传统FPGA原型验证的可视性非常差.为了解决传统FPGA原型验证可视性的问题,验证工程师采用了结合TotalRecall技术的FPGA原型验证方法对一款鼠标芯片进行验证.获得该方法不仅能提供100%的可视性,还确保FPGA原型验证以实时硬件速度运行.该方法创新了ASIC的验证方法学.

  19. Simulation of Multi output Fly back Converter with Integrated Auxiliary Buck Converter with reduced components

    Directory of Open Access Journals (Sweden)

    J.KOMATHI

    2015-04-01

    Full Text Available The fly back converter has been widely used for multi outputs due to the simple structure and low cost in low-power applications. This paper presents a new multi output converter. It consists of a half-bridge inverter with boost converter in primary side and a fly back rectifier that is integrated with an auxiliary buck converter in secondary side. The boost converter is used to generate high voltage dc from Low voltage PV cells. The primary switches control the main output voltage and the secondary synchronous switches control the auxiliary output voltage. The main advantages of the proposed converter are that the transformer size can be reduced due to the less magnetizing offset current, all the power switches including synchronous ones can achieve the zero-voltage switching (ZVS and it has no output cross regulation problems. The circuit is simulated using MATLAB. The performance is verified with simulation results.

  20. Dual Converter Fed Open-End Transformer Topology with Parallel Converters and Integrated Magnetics

    DEFF Research Database (Denmark)

    Gohil, Ghanshyamsinh Vijaysinh; Bede, Lorand; Teodorescu, Remus;

    2016-01-01

    converter group comprises of two parallel Voltage Source Converters (VSCs), whose carrier signals are interleaved to improve the harmonic quality of the resultant switched output voltage of that converter group. However, an additional inductive component is required to suppress the circulating current...... procedure is also described. The volume and the losses of the proposed solution are compared with that of the state-of-art solution. The control of the proposed converter system is also discussed. The analysis has been verified by the simulation and experimental results....

  1. Materials technology for Stirling space power converters

    Science.gov (United States)

    Baggenstoss, William; Mittendorf, Donald

    1992-01-01

    This program was conducted in support of the NASA LeRC development of the Stirling power converter (SPC) for space power applications. The objectives of this contract were: (1) to perform a technology review and analyses to support the evaluation of materials issues for the SPC; (2) to evaluate liquid metal compatibility issues of the SPC; (3) to evaluate and define a transient liquid phase diffusion bonding (TLPDB) process for the SPC joints to the Udimet 720 heater head; and (4) to evaluate alternative (to the TLPDB) joining techniques. In the technology review, several aspects of the current Stirling design were examined including the power converter assembly process, materials joining, gas bearings, and heat exchangers. The supporting analyses included GLIMPS power converter simulation in support of the materials studies, and system level analysis in support of the technology review. The liquid metal compatibility study evaluated process parameters for use in the Stirling power converter. The alternative joining techniques study looked at the applicability of various joining techniques to the Stirling power converter requirements.

  2. Efficiency of Thermionic and Thermoelectric Converters

    Science.gov (United States)

    Gerstenmaier, York Christian; Wachutka, Gerhard

    2007-02-01

    Thermoelectric and thermionic converters — also in micro- and nano-meter design — are considered for power generation and cooling applications. The potential of thermionic vacuum gap converters is investigated precisely by a new advanced theory with inclusion of backward currents from the 2nd electrode, losses due to thermal radiation and ohmic resistance in the electrodes, tunneling through the gap, image forces, and space charge effects. The efficiency of nano-meter gap thermionic converters is by far higher than for thermoelectric devices (including nano-structured superlattices) for operating temperatures above 800°K, however, there is no chance of realization with today's technology. For a vacuum gap width of about 1 μm the performance is higher than for hypothetical bulk- thermoelectric generators (TEGs) with ZT = 1 for T > 1000°K and also higher than for hypothetical nano-structured superlattices (ZT = 2.4) for T > 1200°K. A thermionic converter with gap width of 5μm has lower performance than a TEG with ZT = 1, however, also operates at T > 1200°K. Reasonable performance of thermionic converters at T ⩽ 500°K necessitates materials with workfunctions ⩽ 0.5 eV.

  3. Analog front-end design of the STS/MUCH-XYTER2—full size prototype ASIC for the CBM experiment

    Science.gov (United States)

    Kleczek, Rafal

    2017-01-01

    The design of the analog front-end of the STS/MUCH-XYTER2 ASIC, a full-size prototype chip for the Silicon Tracking System (STS, based on double-sided silicon strip sensors) and Muon Chamber (MUCH, based on gas sensors) detectors is presented. The ASIC contains 128 charge processing channels, each built of a charge sensitive amplifier, a polarity selection circuit and two pulse shaping amplifiers forming two parallel signal paths. The first path is used for timing measurement with a fast discriminator. The second path allows low-noise amplitude measurement with a 5-bit continuous-time flash ADC. Different operating conditions and constraints posed by two target detectors' applications require front-end electronics flexibility to meet extended system-wise requirements. The presented circuit implements switchable shaper peaking time, gain switching and trimming, input amplifier pulsed reset circuit, fail-safe measures. The power consumption is scalable (for the STS and the MUCH modes), but limited to 10 mW/channel.

  4. Radiation hardness tests and characterization of the CLARO-CMOS, a low power and fast single-photon counting ASIC in 0.35 micron CMOS technology

    Science.gov (United States)

    Fiorini, M.; Andreotti, M.; Baldini, W.; Calabrese, R.; Carniti, P.; Cassina, L.; Cotta Ramusino, A.; Giachero, A.; Gotti, C.; Luppi, E.; Maino, M.; Malaguti, R.; Pessina, G.; Tomassetti, L.

    2014-12-01

    The CLARO-CMOS is a prototype ASIC that allows fast photon counting with 5 ns peaking time, a recovery time to baseline smaller than 25 ns, and a power consumption of less than 1 mW per channel. This chip is capable of single-photon counting with multi-anode photomultipliers and finds applications also in the read-out of silicon photomultipliers and microchannel plates. The prototype is realized in AMS 0.35 micron CMOS technology. In the LHCb RICH environment, assuming 10 years of operation at the nominal luminosity expected after the upgrade in Long Shutdown 2 (LS2), the ASIC must withstand a total fluence of about 6×1012 1 MeV neq /cm2 and a total ionizing dose of 400 krad. A systematic evaluation of the radiation effects on the CLARO-CMOS performance is therefore crucial to ensure long term stability of the electronics front-end. The results of multi-step irradiation tests with neutrons and X-rays up to the fluence of 1014 cm-2 and a dose of 4 Mrad, respectively, are presented, including measurement of single event effects during irradiation and chip performance evaluation before and after each irradiation step.

  5. Converters for Distributed Power Generation Systems

    DEFF Research Database (Denmark)

    Blaabjerg, Frede; Yang, Yongheng

    2015-01-01

    Power electronics technology has become the enabling technology for the integration of distributed power generation systems (DPGS) such as offshore wind turbine power systems and commercial photovoltaic power plants. Depending on the applications, a vast array of DPGS-based power converter...... presents an overview of the power converters for the DPGS, mainly based on wind turbine systems and photovoltaic systems, covering a wide range of applications. Moreover, the modulation schemes and interfacing power filters for the power converters are also exemplified. Finally, the general control...... topologies has been developed and more are coming into the market in order to achieve an efficient and reliable power conversion from the renewables. In addition, stringent demands from both the distribution system operators and the consumers have been imposed on the renewable-based DPGS. This article...

  6. CMOS Integrated Capacitive DC-DC Converters

    CERN Document Server

    Van Breussegem, Tom

    2013-01-01

    This book provides a detailed analysis of all aspects of capacitive DC-DC converter design: topology selection, control loop design and noise mitigation. Readers will benefit from the authors’ systematic overview that starts from the ground up, in-depth circuit analysis and a thorough review of recently proposed techniques and design methodologies.  Not only design techniques are discussed, but also implementation in CMOS is shown, by pinpointing the technological opportunities of CMOS and demonstrating the implementation based on four state-of-the-art prototypes.  Provides a detailed analysis of all aspects of capacitive DC-DC converter design;  Analyzes the potential of this type of DC-DC converter and introduces a number of techniques to unleash their full potential; Combines system theory with practical implementation techniques; Includes unique analysis of CMOS technology for this application; Provides in-depth analysis of four fabricated prototypes.

  7. A linear temperature-to-frequency converter

    DEFF Research Database (Denmark)

    Løvborg, Leif

    1965-01-01

    The possibility of converting temperature into a frequency signal by means of a thermistor which is part of the frequency-determining network of an RC oscillator is investigated. It is shown that a temperature - frequency characteristic which has a point of inflection may be realized, and that th......The possibility of converting temperature into a frequency signal by means of a thermistor which is part of the frequency-determining network of an RC oscillator is investigated. It is shown that a temperature - frequency characteristic which has a point of inflection may be realized......, and that the maximum value of the temperature-frequency coefficient beta in this point is-1/3 alpha, where a is the temperature coefficient of the thermistor at the corresponding temperature. Curves showing the range in which the converter is expected to be linear to within plusmn0.1 degC are given. A laboratory...

  8. Power system applications for PASC converter systems

    Energy Technology Data Exchange (ETDEWEB)

    Donnelly, M.K. [Pacific Northwest Lab., Richland, WA (United States); Johnson, R.M. [Montana State Univ., Bozeman, MT (United States)

    1994-04-01

    This paper shows, using computer EMTP simulations, some preliminary results of applying pulse amplitude synthesis and control (PASC) technology to single-source level voltage converter system. The method can be applied to any single terminal pair source with appropriate modifications in power extraction interface and computer control program to match source and load impedance characteristics. The PASC realization as discussed here employs banks of transformers, one bank per phase, in which the primaries are connected in parallel through a switch matrix to the dc source. Two opposite polarity primaries per transformer are pulsed alternatively in time to produce an oscillatory sinusoidal output waveform. PASC conversion system capabilities to produce both leading and lagging power factor power output in single-phase and three-phase {Delta} or Y configurations are illustrated. EMTP simulations are used to demonstrate the converter capabilities. Also included are discussions regarding harmonics and potential control strategies to adapt the converter to an application or to minimize harmonics.

  9. External ionization mechanisms for advanced thermionic converters

    Science.gov (United States)

    Hatziprokopiou, M. E.

    Ion generation and recombination mechanisms in the cesium plasma were investigated as they pertain to the advanced mode thermionic energy converters. The changes in plasma density and temperature within the converter were studied under the influence of several promising auxiliary ionization candidate sources. Three novel approaches of external cesium ion generation were investigated in some detail, namely vibrationally excited N2 as an energy source of ionization of Cs ions in a DC discharge, microwave power as a means of resonant sustenance of the cesium plasma, and ion generation in a pulse N2-Cs mixture. The experimental data obtained and discussed in this work show that all three techniques--i.e. the non-LTE high-voltage pulsing, the energy transfer from vibrationally excited diatomic gases, and the external pumping with a microwave power--have considerable promise as schemes in auxiliary ion generation applicable to the advanced thermionic energy converter.

  10. High Efficiency Reversible Fuel Cell Power Converter

    DEFF Research Database (Denmark)

    Pittini, Riccardo

    The large scale integration of renewable energy sources requires suitable energy storage systems to balance energy production and demand in the electrical grid. Bidirectional fuel cells are an attractive technology for energy storage systems due to the high energy density of fuel. Compared...... entitled "High Efficiency Reversible Fuel Cell Power Converter" and it presents the design of a high efficiency dc-dc converter developed and optimized for bidirectional fuel cell applications. First, a brief overview of fuel cell and energy storage technologies is presented. Different system topologies...... to traditional unidirectional fuel cell, bidirectional fuel cells have increased operating voltage and current ranges. These characteristics increase the stresses on dc-dc and dc-ac converters in the electrical system, which require proper design and advanced optimization. This work is part of the PhD project...

  11. Self-oscillating resonant power converter

    DEFF Research Database (Denmark)

    2014-01-01

    The present invention relates to resonant power converters and inverters comprising a self-oscillating feedback loop coupled from a switch output to a control input of a switching network comprising one or more semiconductor switches. The self-oscillating feedback loop sets a switching frequency...... of the power converter and comprises a first intrinsic switch capacitance coupled between a switch output and a control input of the switching network and a first inductor. The first inductor is coupled in-between a first bias voltage source and the control input of the switching network and has...... a substantially fixed inductance. The first bias voltage source is configured to generate an adjustable bias voltage applied to the first inductor. The output voltage of the power converter is controlled in a flexible and rapid manner by controlling the adjustable bias voltage....

  12. Single phase AC-DC power factor corrected converter with high frequency isolation using buck converter

    Directory of Open Access Journals (Sweden)

    R. Ramesh,

    2014-03-01

    Full Text Available Single phase ac-dc converters having high frequency isolation are implemented in buck, boost, buck-boost configuration with improving the power quality in terms of reducing the harmonics of input current. The paperpropose the circuit configuration, control mechanism, and simulation result for the single phase ac-dc converter.

  13. Solar energy converter using surface plasma waves

    Science.gov (United States)

    Anderson, L. M. (Inventor)

    1984-01-01

    Sunlight is dispersed over a diffraction grating formed on the surface of a conducting film on a substrate. The angular dispersion controls the effective grating period so that a matching spectrum of surface plasmons is excited for parallel processing on the conducting film. The resulting surface plasmons carry energy to an array of inelastic tunnel diodes. This solar energy converter does not require different materials for each frequency band, and sunlight is directly converted to electricity in an efficient manner by extracting more energy from the more energetic photons.

  14. Metamaterial polarization converter analysis: limits of performance

    DEFF Research Database (Denmark)

    Markovich, Dmitry L.; Andryieuski, Andrei; Zalkovskij, Maksim;

    2013-01-01

    In this paper, we analyze the theoretical limits of a metamaterial-based converter with orthogonal linear eigenpolarizations that allow linear-to-elliptical polarization transformation with any desired ellipticity and ellipse orientation. We employ the transmission line approach providing a needed...... and a single layer with a ground plane can have 100 % polarization conversion efficiency. We tested our conclusions numerically reaching the designated limits of efficiency using a simple metamaterial design. Our general analysis provides useful guidelines for the metamaterial polarization converter design...

  15. Generalized modular multilevel converter and modulation

    DEFF Research Database (Denmark)

    Liu, Hui; Loh, Poh Chiang; Blaabjerg, Frede

    2014-01-01

    Modular multilevel converter (MMC) has gained popularity recently with its modulation, capacitor voltage balancing and circulating current issues widely discussed. Contributing to this effort, a study is presented here to show how the MMC topology can be derived from the viewpoint of two series...... converters regulating a power grid. The generalized topology derived and notated as GMMC can then be altered to create various types of MMC, including the traditional topology that is presently well-known. This effort has not been previously discussed, and may smoothen the understanding of MMC operation...

  16. Is China Ready for Full Yuan Convertibility?

    Institute of Scientific and Technical Information of China (English)

    2011-01-01

    Although China has made headway in reforming the exchange rate regime of its currency,the yuan,and expanding the use of it in cross-border trade during the past year,the yuan is far from fully convertible.Huang Yiping,a professor at the National School of Development of Peking University,said in an article for Beijing Review that China has the conditions for capital account liberalization and should strive for basic convertibility within five years. Edited excerpts follow

  17. A novel PWM control for a bi-directional full-bridge DC-DC converter with smooth conversion mode transitions

    Science.gov (United States)

    Lorentz, V. R. H.; Schwarzmann, H.; März, M.; Bauer, A. J.; Ryssel, H.; Frey, L.; Poure, P.; Braun, F.

    2011-08-01

    A novel CMOS integrated pulse-width modulation (PWM) control circuit allowing smooth transitions between conversion modes in full-bridge based bi-directional DC-DC converters operating at high switching frequencies is presented. The novel PWM control circuit is able to drive full-bridge based DC-DC converters performing step-down (i.e. buck) and step-up (i.e. boost) voltage conversion in both directions, thus allowing charging and discharging of the batteries in mobile systems. It provides smooth transitions between buck, buck-boost and boost modes. Additionally, the novel PWM control loop circuit uses a symmetrical triangular carrier, which overcomes the necessity of using an output phasing circuit previously required in PWM controllers based on sawtooth oscillators. The novel PWM control also enables to build bi-directional DC-DC converters operating at high switching frequencies (i.e. up to 10 MHz and above). Finally, the proposed PWM control circuit also allows the use of an average lossless inductor-current sensor for sensing the average load current even at very high switching frequencies. In this article, the proposed PWM control circuit is modelled and the integrated CMOS schematic is given. The corresponding theory is analysed and presented in detail. The circuit simulations realised in the Cadence Spectre software with a commercially available 0.18 µm mixed-signal CMOS technology from UMC are shown. The PWM control circuit was implemented in a monolithic integrated bi-directional CMOS DC-DC converter ASIC prototype. The fabricated prototype was tested experimentally and has shown performances in accordance with the theory.

  18. Low-power variable frequency PFC converters

    Energy Technology Data Exchange (ETDEWEB)

    Li Yani; Yang Yintang; Zhu Zhangming, E-mail: yanili@mail.xidian.edu.c [Key Laboratory of Wide Band-Gap Semiconductor Materials and Devices of the Ministry of Education, Institute of Microelectronics, Xidian University, Xi' an 710071 (China)

    2010-01-15

    Based on the SinoMOS 1 {mu}m 40 V CMOS process, a novel power factor contention (PFC) converter with a low-power variable frequency function is presented. The circuit introduces a multi-vector error amplifier and a programmable oscillator to achieve frequency modulation, which provides a rapid dynamic response and precise output voltage clamping with low power in the entire load. According to the external load variation, the system can modulate the circuit operating frequency linearly, thereby ensuring that the PFC converter can work in frequency conversion-mode. Measured results show that the normal operating frequency of the PFC converter is 5-6 kHz, the start-up current is 36 {mu}A, the stable operating current is only 2.43 mA, the efficiency is 97.3%, the power factor (PF) is 0.988, THD is 3.8%, the load adjust rate is 3%, and the linear adjust rate is less than 1%. Both theoretical and practical results reveal that the power consumption of the whole supply system is reduced efficiently, especially when the load varies. The active die area of the PFC converter chip is 1.61 x 1.52 mm{sup 2}. (semiconductor integrated circuits)

  19. Mathematical modeling of the flash converting process

    Energy Technology Data Exchange (ETDEWEB)

    Sohn, H.Y.; Perez-Tello, M.; Riihilahti, K.M. [Utah Univ., Salt Lake City, UT (United States)

    1996-12-31

    An axisymmetric mathematical model for the Kennecott-Outokumpu flash converting process for converting solid copper matte to copper is presented. The model is an adaptation of the comprehensive mathematical model formerly developed at the University of Utah for the flash smelting of copper concentrates. The model incorporates the transport of momentum, heat, mass, and reaction kinetics between gas and particles in a particle-laden turbulent gas jet. The standard k-{epsilon} model is used to describe gas-phase turbulence in an Eulerian framework. The particle-phase is treated from a Lagrangian viewpoint which is coupled to the gas-phase via the source terms in the Eulerian gas-phase governing equations. Matte particles were represented as Cu{sub 2}S yFeS, and assumed to undergo homogeneous oxidation to Cu{sub 2}O, Fe{sub 3}O{sub 4}, and SO{sub 2}. A reaction kinetics mechanism involving both external mass transfer of oxygen gas to the particle surface and diffusion of oxygen through the porous oxide layer is proposed to estimate the particle oxidation rate Predictions of the mathematical model were compared with the experimental data collected in a bench-scale flash converting facility. Good agreement between the model predictions and the measurements was obtained. The model was used to study the effect of different gas-injection configurations on the overall fluid dynamics in a commercial size flash converting shaft. (author)

  20. Converting Student Support Services to Online Delivery.

    Science.gov (United States)

    Brigham, David E.

    2001-01-01

    Uses a systems framework to analyze the creation of student support services for distance education at Regents College: electronic advising, electronic peer network, online course database, online bookstore, virtual library, and alumni services website. Addresses the issues involved in converting distance education programs from print-based and…

  1. Development of the Wave Energy Converter

    DEFF Research Database (Denmark)

    Kofoed, Jens Peter; Frigaard, Peter; Sørensen, Hans Christian

    2000-01-01

    The development of the wave energy converter Wave Dragon (WD) is presented. The WD is based on the overtopping principle. Initially a description of the WD is given. Then the development over time in terms of the various research and development projects working with the concept is described...

  2. Aquabuoy Wave Energy Converter

    DEFF Research Database (Denmark)

    Vicinanza, Diego; Margheritini, Lucia; Frigaard, Peter

    The work reported here is part of the contract agreement between the Finavera Renewables Ocean Energy Ltd. and the Department of Civil Engineering Hydraulics and Coastal Engineering Laboratory to instrument a model in scale 1:10 to prototype of the AquaBuOY (AB) wave energy converter and to analyse...

  3. Near-Shore Floating Wave Energy Converters

    DEFF Research Database (Denmark)

    Ruol, Piero; Zanuttigh, Barbara; Martinelli, Luca

    2011-01-01

    Aim of this note is to analyse the possible application of a Wave Energy Converter (WEC) as a combined tool to protect the coast and harvest energy. Physical model tests are used to evaluate wave transmission past a near-shore floating WEC of the wave activated body type, named DEXA. Efficiency...

  4. Online Scheduling in Distributed Message Converter Systems

    NARCIS (Netherlands)

    Risse, Thomas; Wombacher, Andreas; Surridge, Mike; Taylor, Steve; Aberer, Karl

    2001-01-01

    The optimal distribution of jobs among hosts in distributed environments is an important factor to achieve high performance. The optimal strategy depends on the application. In this paper we present a new online scheduling strategy for distributed EDI converter system. The strategy is based on the B

  5. Fast Constant Weight Codeword to Index Converter

    Science.gov (United States)

    2011-08-01

    is achievable; a 64-out- of-128 bit converter uses only 9% of the available ALMs. The large values of n required special Verilog programming. For...n r ) in a MATLAB program and wrote it to a header file that was included in the Verilog code. III. COMPLEX DISJOINT DECOMPOSITION SOLUTION It can

  6. Efficient, lightweight dc/dc switching converter

    Science.gov (United States)

    Cuk, S.; Middlebrook, R. D.

    1981-01-01

    Converters have input properties of boost power stage and output properties of buck power stage, yet they perform general conversion function with high efficiency. Other features include non-pulsating input/output currents, use of capacitive energy transfer, low output voltage ripple, reduced EMI, and small size.

  7. Power electronics converters for wind turbine systems

    DEFF Research Database (Denmark)

    Blaabjerg, Frede; Liserre, Marco; Ma, Ke

    2011-01-01

    The steady growth of installed wind power which reached 200 GW capacity in 2010, together with the up-scaling of the single wind turbine power capability - 7 MW’s has been announced by manufacturers - has pushed the research and development of power converters towards full scale power conversion,...

  8. Power Electronics Converters for Wind Turbine Systems

    DEFF Research Database (Denmark)

    Blaabjerg, Frede; Liserre, Marco; Ma, Ke

    2012-01-01

    The steady growth of installed wind power together with the upscaling of the single wind turbine power capability has pushed the research and development of power converters toward full-scale power conversion, lowered cost pr kW, increased power density, and also the need for higher reliability. ...

  9. China to Gradually Make Capital Account Convertible

    Institute of Scientific and Technical Information of China (English)

    2006-01-01

    @@ China is pushing forward its currency Renminbi (RMB)'s capital account convertibility gradually and in a stable manner, said an official with the State Administration of Foreign Exchange (SAFE), ruling out both an adventurous leap and conservative cautiousness, according to a report of Xinhua on April 12.

  10. China to Gradually Make Capital Account Convertible

    Institute of Scientific and Technical Information of China (English)

    2006-01-01

      China is pushing forward its currency Renminbi (RMB)'s capital account convertibility gradually and in a stable manner, said an official with the State Administration of Foreign Exchange (SAFE), ruling out both an adventurous leap and conservative cautiousness, according to a report of Xinhua on April 12.……

  11. Hybrid switch for resonant power converters

    Science.gov (United States)

    Lai, Jih-Sheng; Yu, Wensong

    2014-09-09

    A hybrid switch comprising two semiconductor switches connected in parallel but having different voltage drop characteristics as a function of current facilitates attainment of zero voltage switching and reduces conduction losses to complement reduction of switching losses achieved through zero voltage switching in power converters such as high-current inverters.

  12. Bidirectional converter interface for a battery energy storage test bench

    DEFF Research Database (Denmark)

    Trintis, Ionut; Thomas, Stephan; Blank, Tobias;

    2011-01-01

    This paper presents the bidirectional converter interface for a 6 kV battery energy storage test bench. The power electronic interface consists a two stage converter topology having a low voltage dc-ac grid connected converter and a new dual active bridge dc-dc converter with high transformation...... ratio. The dc-dc converter controls the battery charge/discharge current while the grid converter controls the common dc-link voltage and the grid current. The applied control structures and the hardware implementation of both converters are presented, together with their interaction. Experimental...

  13. A New Hard Switching Bidirectional Converter With High Power Density

    Directory of Open Access Journals (Sweden)

    Bahador Fani

    2010-01-01

    Full Text Available In this paper, a new isolated dc-dc bidirectional converter is proposed. This converter consists of two transformers (flyback and forward and only one switch in primary side and one switch in secondary side of transformers. In this converter energy transfers to the output in both on and off switch states so power density of this converter is high This converter controlled by PWM signal. Also this converter operates over a wide input voltage range. Theoretical analysis is presented and computer simulation and experimental results verify the converter analysis.

  14. Coordinated Control of Wave Energy Converters Subject to Motion Constraints

    OpenAIRE

    2016-01-01

    In this paper, a generic coordinated control method for wave energy converters is proposed, and the constraints on motion amplitudes and the hydrodynamic interaction between converters are considered. The objective of the control problem is to maximize the energy converted from ocean waves, and this is achieved by coordinating the power take-off (PTO) damping of each wave energy converter in the frequency domain in each sea state. In a case study, a wave energy farm consisting of four convert...

  15. Emissions Tests Of Two Dc-To-Dc Converters

    Science.gov (United States)

    Mclyman, W. T.

    1992-01-01

    Report describes tests to characterize unwanted electric and magnetic fields, at frequencies up to few megahertz, radiated by two dc-to-dc converters, one 20-kHz square-wave converter; the other, a 33-kHz sine-wave converter. Part of effort to develop "quiet" power converter for use aboard spacecraft. Converter required to interfere minimally with delicate instruments measuring electric and magnetic fields.

  16. Multi-output DC-DC converters based on diode-clamped converters configuration

    DEFF Research Database (Denmark)

    Nami, A.; Zare, F.; Ghosh, A.;

    2010-01-01

    for a diode-clamed inverter in the grid connection systems, where boosting low rectified output-voltage and series DC link capacitors is required. To verify the proposed topology, steady-state and dynamic analyses of a MOB converter are examined. A simple control strategy has been proposed to demonstrate...... the performance of the proposed topology for a double-output boost converter. The topology and its control strategy can easily be extended to offer multiple outputs. Simulation and experimental results are presented to show the validity of the control strategy for the proposed converter....

  17. Research on Converter Valve Overvoltage Mechanism and Calculation Conditions of ± 800 kV Converter Station

    Institute of Scientific and Technical Information of China (English)

    WANG Dongju; DENG Xu; ZHOU Hao; CHEN Xilei; XU Anwen; SHEN Yang

    2012-01-01

    The thyristor converter valve is the key equipment of commutation in ultra high voltage direct current (UHVDC) transmission systems. Owing to the limited voltage and current overload capacity, any transient overvoltage may cause permanent damage to the thyristor converter valve. In order to specify the converter valves' overvoltage levels of the ±800 kV UHVDC transmission system, the mechanisms of its generation and development are discussed in detail, from which the calculation conditions for the highest stresses of the converter valves are given. Finally, the converter valve's overvoltage of Xiluodu UHV converter station is simulated. The research results show that the overvoltages of the converter valves in the upper 3-pulse group of the high voltage(HV) and low voltage(LV) 12-pulse converter are generated jointly by the DC line voltage and the converter transformer's voltage at its valve side. Calculation conditions for this overvoltage are: DC system in bipolar operation mode, converter station operating as rectifier, maximum DC system operating voltage, minimum DC current, minimum AC system voltage of the converter station. Furthermore, the other converter valves' overvoltage is caused by the phase-to-phase switching surge generated at the converter station's AC side, penetrating into the valve hall. Overall, the maximum overvoltages of Xiluodu converter station in the upper 3-pulse group of the HV and LV 12-pulse converter are 379.1 kV and 384.9 kV, for other converter valves the maximum overvoltage is 375.3 kV.

  18. Imbalance between pulmonary angiotensin-converting enzyme and angiotensin-converting enzyme 2 activity in acute respiratory distress syndrome

    NARCIS (Netherlands)

    Wosten-van Asperen, Roelie M.; Bos, Albert; Bem, Reinout A.; Dierdorp, Barbara S.; Dekker, Tamara; van Goor, Harry; Kamilic, Jelena; van der Loos, Chris M.; van den Berg, Elske; Bruijn, Martijn; van Woensel, Job B.; Lutter, Rene

    2013-01-01

    Objective: Angiotensin-converting enzyme and its effector peptide angiotensin II have been implicated in the pathogenesis of acute respiratory distress syndrome. Recently, angiotensin-converting enzyme 2 was identified as the counter-regulatory enzyme of angiotensin-converting enzyme that converts a

  19. Efficient Wide Range Converters (EWiRaC): A new family of high efficient AC-DC Converters

    DEFF Research Database (Denmark)

    Petersen, Lars; Andersen, Michael Andreas E.

    2006-01-01

    The performance in terms of efficiency of the existing power supplies used for PFC is very dependent on the input voltage range. The boost converter is the most commonly used PFC converter because of its simplicity and high efficiency. But, the boost converter as well as other known converters...... the converter topology according to the input voltage. This new converter type has been named: efficient wide range converter (EWiRaC). The performance of the EWiRaC is experimental verified in a universal input range (90-270VAC) application with an output voltage of 185VDC capable of 500W output power. The EWi...

  20. TiConverter: A training image converting tool for multiple-point geostatistics

    Science.gov (United States)

    Fadlelmula F., Mohamed M.; Killough, John; Fraim, Michael

    2016-11-01

    TiConverter is a tool developed to ease the application of multiple-point geostatistics whether by the open source Stanford Geostatistical Modeling Software (SGeMS) or other available commercial software. TiConverter has a user-friendly interface and it allows the conversion of 2D training images into numerical representations in four different file formats without the need for additional code writing. These are the ASCII (.txt), the geostatistical software library (GSLIB) (.txt), the Isatis (.dat), and the VTK formats. It performs the conversion based on the RGB color system. In addition, TiConverter offers several useful tools including image resizing, smoothing, and segmenting tools. The purpose of this study is to introduce the TiConverter, and to demonstrate its application and advantages with several examples from the literature.

  1. Analog-digital converters for industrial applications including an introduction to digital-analog converters

    CERN Document Server

    Ohnhäuser, Frank

    2015-01-01

    This book offers students and those new to the topic of analog-to-digital converters (ADCs) a broad introduction, before going into details of the state-of-the-art design techniques for SAR and DS converters, including the latest research topics, which are valuable for IC design engineers as well as users of ADCs in applications. The book then addresses important topics, such as correct connectivity of ADCs in an application, the verification, characterization and testing of ADCs that ensure high-quality end products. Analog-to-digital converters are the central element in any data processing system and regulation loops such as modems or electrical motor drives. They significantly affect the performance and resolution of a system or end product. System development engineers need to be familiar with the performance parameters of the converters and understand the advantages and disadvantages of the various architectures. Integrated circuit development engineers have to overcome the problem of achieving high per...

  2. Radiation effects in power converters: Design of a radiation hardened integrated switching DC/DC converter

    Science.gov (United States)

    Adell, Philippe

    When electronic devices are used in space and military systems, they may be exposed to various types of radiation, including photons, electrons, protons, neutrons, and heavy ions. The effects of radiation on the semiconductor devices within the systems range from gradual degradation to catastrophic failure. In order to design and produce reliable systems for space or military applications, it is necessary to understand the device-level effects of radiation and develop appropriate strategies for reducing system susceptibility. This research focuses on understanding radiation effects in power converters for space and military applications. We show that power converters are very sensitive to radiation (total-dose, single event effects and displacement damage) and that their radiation response is dependent on input bias conditions and load conditions. We compared the radiation hardness of various power converter topologies using experiments and simulations. Evaluation of these designs under different modes of operation is demonstrated to be critical for determining radiation hardness. We emphasize the correlation between radiation effects and the role of the dynamic response of these topologies. For instance, total dose exposure has been found to degrade loop gain and affect regulation in some converters. We propose several radiation-hardening solutions to improve the radiation response of these designs. For instance, we demonstrate the design of a digitally controlled boost converter suitable for space applications based on an SRAM FPGA. A design hardening solution has been developed and successfully applied through VHDL simulations and experiments to assure the continuous operation of the converter in the presence of SEES (more precisely SEFIs). This research led to the design of a digitally controlled radiation hardened integrated switching buck converter. The proposed design is suitable for micro-satellite applications and is based on a high-voltage/CMOS process

  3. Parametric study of minimum converter loss in an energy-storage dc-to-dc converter

    Science.gov (United States)

    Wong, R. C.; Owen, H. A., Jr.; Wilson, T. G.

    1982-01-01

    Through a combination of analytical and numerical minimization procedures, a converter design that results in the minimum total converter loss (including core loss, winding loss, capacitor and energy-storage-reactor loss, and various losses in the semiconductor switches) is obtained. Because the initial phase involves analytical minimization, the computation time required by the subsequent phase of numerical minimization is considerably reduced in this combination approach. The effects of various loss parameters on the optimum values of the design variables are also examined.

  4. Faults and Diagnosis Systems in Power Converters

    DEFF Research Database (Denmark)

    Lee, Kyo-Beum; Choi, Uimin

    2014-01-01

    efforts have been put into making these systems better in terms of reliability in order to achieve high power source availability, reduce the cost of energy and also increase the reliability of overall systems. Among the components used in power converters, a power device and a capacitor fault occurs most......A power converter is needed in almost all kinds of renewable energy systems and drive systems. It is used both for controlling the renewable source and for interfacing with the load, which can be grid-connected or working in standalone mode. Further, it drives the motors efficiently. Increasing...... frequently. Therefore, it is important to monitor the power device and capacitor fault to increase the reliability of power electronics. In this chapter, the diagnosis methods for power device fault will be discussed by dividing into open- and short-circuit faults. Then, the condition monitoring methods...

  5. Strained quantum well photovoltaic energy converter

    Science.gov (United States)

    Freundlich, Alexandre (Inventor); Renaud, Philippe (Inventor); Vilela, Mauro Francisco (Inventor); Bensaoula, Abdelhak (Inventor)

    1998-01-01

    An indium phosphide photovoltaic cell is provided where one or more quantum wells are introduced between the conventional p-conductivity and n-conductivity indium phosphide layer. The approach allows the cell to convert the light over a wider range of wavelengths than a conventional single junction cell and in particular convert efficiently transparency losses of the indium phosphide conventional cell. The approach hence may be used to increase the cell current output. A method of fabrication of photovoltaic devices is provided where ternary InAsP and InGaAs alloys are used as well material in the quantum well region and results in an increase of the cell current output.

  6. Study on a Novel High-Efficiency Bridgeless PFC Converter

    Directory of Open Access Journals (Sweden)

    Cao Taiqiang

    2014-01-01

    Full Text Available In order to implement a high-efficiency bridgeless power factor correction converter, a new topology and operation principles of continuous conduction mode (CCM and DC steady-state character of the converter are analyzed, which show that the converter not only has bipolar-gain characteristic but also has the same characteristic as the traditional Boost converter, while the voltage transfer ratio is not related with the resonant branch parameters and switching frequency. Based on the above topology, a novel bridgeless Bipolar-Gain Pseudo-Boost PFC converter is proposed. With this converter, the diode rectifier bridge of traditional AC-DC converter is eliminated, and zero-current switching of fast recovery diode is achieved. Thus, the efficiency is improved. Next, we also propose the one-cycle control policy of this converter. Finally, experiments are provided to verify the accuracy and feasibility of the proposed converter.

  7. Fracture imaging with converted elastic waves

    Energy Technology Data Exchange (ETDEWEB)

    Nihei, K.T.; Nakagawa, S.; Myer, L.R.

    2001-05-29

    This paper examines the seismic signatures of discrete, finite-length fractures, and outlines an approach for elastic, prestack reverse-time imaging of discrete fractures. The results of this study highlight the importance of incorporating fracture-generated P-S converted waves into the imaging method, and presents an alternate imaging condition that can be used in elastic reverse-time imaging when a direct wave is recorded (e.g., for crosswell and VSP acquisition geometries).

  8. Reversible thyristor converters of brushless synchronous compensators

    Directory of Open Access Journals (Sweden)

    А.М.Galynovskiy

    2013-12-01

    Full Text Available Behavior of models of three-phase-to-single-phase rotary reversible thyristor converters of brushless synchronous compensators in a circuit simulation system is analyzed. It is shown that combined control mode of opposite-connected thyristors may result in the exciter armature winding short circuits both at the thyristor feed-forward and lagging current delay angles. It must be taken into consideration when developing brushless compensator excitation systems.

  9. Converting Student Support Services to Online Delivery

    OpenAIRE

    David E. Brigham

    2001-01-01

    This case study describes how Regents College (soon to be Excelsior College), an accredited, private, distance education institution with administrative offices in Albany, New York addressed the structural, management, and resource issues that came into play when converting distance education programs from print-based and telephone delivery to online delivery. The study uses a systems framework to describe and analyze the circumstances and issues surrounding the creation of six student suppor...

  10. (Convertible) Undeniable Signatures Without Random Oracles

    Science.gov (United States)

    Yuen, Tsz Hon; Au, Man Ho; Liu, Joseph K.; Susilo, Willy

    We propose a convertible undeniable signature scheme without random oracles. Our construction is based on Waters' and Kurosawa and Heng's schemes that were proposed in Eurocrypt 2005. The security of our scheme is based on the CDH and the decision linear assumption. Comparing only the part of undeniable signatures, our scheme uses more standard assumptions than the existing undeniable signatures without random oracles due to Laguillamie and Vergnaud.

  11. Multiport Resonant DC-DC Converter

    OpenAIRE

    Tran, Yan-Kim; Dujic, Drazen; Barrade, Philippe

    2015-01-01

    his paper presents a multiport galvanically isolated LLC resonant DC-DC converter suitable for DC applications. A three-port structure is analyzed, with full bidirectional power flow capabilities, simple control and behavior similar to that expected from a DC transformer. Each port is equipped with half-bridge modules accompanied with tuned resonant tank, partly realized with elements of a multi- winding high frequency transformer. With some restrictions that are explained in the paper, each ...

  12. The CERN Control Protocol for power converters

    Energy Technology Data Exchange (ETDEWEB)

    Barnett, I.; Benincasa, G.; Berrig, O.; Brun, R.; Burla, P.; Coudert, G.; Pett, J.G.; Pittin, R.; Royer, J.P.; Trofimov, N. (CERN, Geneva (Switzerland))

    1993-08-01

    The Control Protocols provide, for a class of similar devices, a unique and standard access procedure from the control system. Behavioral models have been proposed for the different kinds of Power Converters and the corresponding functionalities, with their parameters, variables and attributes have been identified. The resulting data structures have been presented using the ISO ASN.1 metalanguage, that permits universal representation independent of any computer environment. Implementations in the UNIX-based CERN accelerator control systems are under development.

  13. Studies of the high rate coincidence timing response of the STiC and TOFPET ASICs for the SAFIR PET scanner

    Science.gov (United States)

    Becker, R.; Casella, C.; Corrodi, S.; Dissertori, G.; Fischer, J.; Howard, A.; Ito, M.; Lustermann, W.

    2016-12-01

    The proposed SAFIR PET detector will measure positron electron annihilations at injected activities up to 500 MBq in a mouse or rat. The system is required to have the best possible timing resolution in order to remove accidental coincidences (randoms) and maximise the image quality for short time frames allowing the possibility of 4-D kinetic modelling of simultaneous PET and MRI for the first time. Two different ASICs, TOFPET and STiC, have been investigated with LYSO crystal scintillators coupled to SiPM detectors and using 18F sources up to 480 MBq. Timing responses are very encouraging with a coincidence time resolution of ~100 ps measured at low activities, degrading to 130 ps at the foreseen scanner maximum event rate. Sensitivities for single event rates and coincidences are measured and compared with Geant4 Monte Carlo simulations.

  14. Optimizing Design of UHVDC Converter Stations

    Institute of Scientific and Technical Information of China (English)

    MA Weimin; NIE Dingzhen; CAO Yanming

    2012-01-01

    Based on the consultation and study for Xiangjiaba-Shanghai ±800 kV UHVDC(ultra high voltage direct current) project, this paper presents an optimal design for key technique solutions. In this paper, the DC system electrical scheme design, the DC filter design, the DC harmonic component suppression, the over voltage and insulation coordination, the requirements for converter station equipment, the main equipment technical parameters of equipment (including thyristor valve, converter transformer, smoothing reactor, DC breaker), the configuration of measuring device and DC control protection system, and the de-icing operation design are investigated. According to the UHVDC technology researched conclusions and the development of the project construction, the UHVDC system design for converter stations becomes an optimal combination. The optimized design solves numbers of technical problems of the world's first UHVDC project, and it is applied to the project's construction. Under the actual operating condition, the optimized design is proved to be correct and superior. These optimal design conclusions are impartment for developing UHVDC technique and equipment, and provide reference for future UHVDC projects.

  15. Radiation hardness tests and characterization of the CLARO-CMOS, a low power and fast single-photon counting ASIC in 0.35 micron CMOS technology

    Energy Technology Data Exchange (ETDEWEB)

    Fiorini, M., E-mail: fiorini@fe.infn.it [Università degli Studi di Ferrara and INFN Sezione di Ferrara (Italy); Andreotti, M.; Baldini, W.; Calabrese, R. [Università degli Studi di Ferrara and INFN Sezione di Ferrara (Italy); Carniti, P.; Cassina, L. [Università degli Studi di Milano Bicocca and INFN Sezione di Milano Bicocca (Italy); Cotta Ramusino, A. [Università degli Studi di Ferrara and INFN Sezione di Ferrara (Italy); Giachero, A.; Gotti, C. [Università degli Studi di Milano Bicocca and INFN Sezione di Milano Bicocca (Italy); Luppi, E. [Università degli Studi di Ferrara and INFN Sezione di Ferrara (Italy); Maino, M. [Università degli Studi di Milano Bicocca and INFN Sezione di Milano Bicocca (Italy); Malaguti, R. [Università degli Studi di Ferrara and INFN Sezione di Ferrara (Italy); Pessina, G. [Università degli Studi di Milano Bicocca and INFN Sezione di Milano Bicocca (Italy); Tomassetti, L. [Università degli Studi di Ferrara and INFN Sezione di Ferrara (Italy)

    2014-12-01

    The CLARO-CMOS is a prototype ASIC that allows fast photon counting with 5 ns peaking time, a recovery time to baseline smaller than 25 ns, and a power consumption of less than 1 mW per channel. This chip is capable of single-photon counting with multi-anode photomultipliers and finds applications also in the read-out of silicon photomultipliers and microchannel plates. The prototype is realized in AMS 0.35 micron CMOS technology. In the LHCb RICH environment, assuming 10 years of operation at the nominal luminosity expected after the upgrade in Long Shutdown 2 (LS2), the ASIC must withstand a total fluence of about 6×10{sup 12} 1 MeV n{sub eq}/cm{sup 2} and a total ionizing dose of 400 krad. A systematic evaluation of the radiation effects on the CLARO-CMOS performance is therefore crucial to ensure long term stability of the electronics front-end. The results of multi-step irradiation tests with neutrons and X-rays up to the fluence of 10{sup 14} cm{sup −2} and a dose of 4 Mrad, respectively, are presented, including measurement of single event effects during irradiation and chip performance evaluation before and after each irradiation step. - Highlights: • CLARO chip capable of single-photon counting with 5 ns peaking time. • Chip irradiated up to very high neutron, proton and X-rays fluences, as expected for upgraded LHCb RICH detectors. • No significant performance degradation is observed after irradiation.

  16. Accelerated commutation for passive clamp isolated boost converters

    OpenAIRE

    2002-01-01

    An efficient and cost effective bidirectional DC/DC converter reduces switch voltage stress via accelerated commutation allowing use of a low-cost passive clamp circuit in boost mode. The converter includes a primary circuit, transformer and secondary circuit. The primary circuit takes the form of a “full bridge converter,” a “push-pull converter,” or an “L-type converter.”. The primary circuit may include a dissipator such as a snubber circuit or small buck converter. A secondary side of the...

  17. One-Quadrant Switched-Mode Power Converters

    CERN Document Server

    Petrocelli, R

    2015-01-01

    This article presents the main topics related to one-quadrant power convert- ers. The basic topologies are analysed and a simple methodology to obtain the steady-state output–input voltage ratio is set out. A short discussion of dif- ferent methods to control one-quadrant power converters is presented. Some of the reported derived topologies of one-quadrant power converters are also considered. Some topics related to one-quadrant power converters such as syn- chronous rectification, hard and soft commutation, and interleaved converters are discussed. Finally, a brief introduction to resonant converters is given.

  18. Comparison between the Performance of Basic SEPIC Converter and modified SEPIC Converter with PI Controller

    Directory of Open Access Journals (Sweden)

    Satyendra Kumar Gupta

    2014-08-01

    Full Text Available There are multiple solutions in which line current is sinusoidal. In addition, in the recent years, a great number of circuits have been proposed with non sinusoidal line current. In this paper, a review of the most interesting solutions for single phase and low power applications is carried out. They are classified attending to the line current waveform, energy processing, number of switches, control loops, etc. The major advantages and disadvantages are highlighted and the field of application is found. The paper presents performance analysis of modified SEPIC dc-dc converter with low input voltage and wide output voltage range. The operational analysis and the design is done for the 380W power output of the modified converter. The simulation results of modified SEPIC converter are obtained with PI controller for the output voltage. The results obtained with the modified converter are compared with the basic SEPIC converter topology for the rise time, peak time, settling time and steady state error of the output response for open loop. Voltage tracking curve is also shown for wide output voltage range.

  19. High power density dc/dc converter: Selection of converter topology

    Science.gov (United States)

    Divan, Deepakraj M.

    1990-01-01

    The work involved in the identification and selection of a suitable converter topology is described. Three new dc/dc converter topologies are proposed: Phase-Shifted Single Active Bridge DC/DC Converter; Single Phase Dual Active Bridges DC/DC Converter; and Three Phase Dual Active Bridges DC/DC Converter (Topology C). The salient features of these topologies are: (1) All are minimal in structure, i.e., each consists of an input and output bridge, input and output filter and a transformer, all components essential for a high power dc/dc conversion process; (2) All devices of both the bridges can operate under near zero-voltage conditions, making possible a reduction of device switching losses and hence, an increase in switching frequency; (3) All circuits operate at a constant frequency, thus simplifying the task of the magnetic and filter elements; (4) Since, the leakage inductance of the transformer is used as the main current transfer element, problems associated with the diode reverse recovery are eliminated. Also, this mode of operation allows easy paralleling of multiple modules for extending the power capacity of the system; (5) All circuits are least sensitive to parasitic impedances, infact the parasitics are efficently utilized; and (6) The soft switching transitions, result in low electromagnetic interference. A detailed analysis of each topology was carried out. Based on the analysis, the various device and component ratings for each topology operating at an optimum point, and under the given specifications, are tabulated and discussed.

  20. A resonant dc-dc power converter assembly

    DEFF Research Database (Denmark)

    2015-01-01

    The present invention relates to a resonant DC-DC power converter assembly comprising a first resonant DC-DC power converter and a second resonant DC-DC power converter having identical circuit topologies. A first inductor of the first resonant DC-DC power converter and a second inductor...... of the second resonant DC-DC power converter are configured for magnetically coupling the first and second resonant DC-DC power converters to each other to forcing substantially 180 degrees phase shift, or forcing substantially 0 degree phase shift, between corresponding resonant voltage waveforms of the first...... and second resonant DC-DC power converters. The first and second inductors are corresponding components of the first and second resonant DC-DC power converters....

  1. An Efficient DC- DC Converter with Bidirectional Power Flow

    Directory of Open Access Journals (Sweden)

    N.RAJARAJESWARI

    2008-07-01

    Full Text Available This paper introduces a Bi-directional DC-DC converter with adaptive fuzzy logic controller. Bidirectional power flow is obtained by same power components and provides a simple, efficient, and galvanically isolated converter. In the presence of DC mains the converter operates as buck converter and charges the battery. When the DC mains fails, the converter operates as boost converter and the down stream converter is fed by the battery. The power switches are controlled by Pulse Width Modulation technique and the pulses are generated by the application of fuzzy logic with an adoption algorithm. The proposed converter is simulated using MATLAB and laboratory prototype was developed to validate the simulation results.

  2. A Three-Phase Interleaved Floating Output Boost Converter

    Directory of Open Access Journals (Sweden)

    Ajmal Farooq

    2015-01-01

    Full Text Available High step-up dc-dc converter is an essential part in several renewable energy systems. In this paper, a new topology of step-up dc-dc converter based on interleaved structure is proposed. The proposed converter uses three energy storing capacitors to achieve a high voltage gain. Besides the high voltage gain feature, the proposed converter also reduces the voltage stress across the semiconductor switches. This helps in using low rating switching devices which can reduce the overall size and cost of the converter. The operating principle of the proposed converter is discussed in detail and its principle waveforms are analyzed. An experiment is carried out on a 20 V input, 130 V output, and 21 W power prototype of the proposed converter in the laboratory to verify the performance of the proposed converter. An efficiency of 91.3% is achieved at the rated load.

  3. Optical analog-to-digital converter

    Science.gov (United States)

    Evanchuk, Vincent L. (Inventor)

    1984-01-01

    A method and apparatus for converting the intensity of an unknown optical signal (B) into an electrical signal in digital form utilizes two elongated optical attenuators (11, 13), one for the unknown optical signal from a source (10) and one for a known optical signal (A) from a variable source (12), a plurality of photodetectors (e.g., 17, 18) along each attenuator for detecting the intensity of the optical signals, and a plurality of comparators (e.g., 21) connected to the photodetectors in pairs to determine at what points being compared the attenuated known signal equals the attenuated unknown signal. The intensity of the unknown relative to the known is thus determined by the output of a particular comparator. That output is automatically encoded to a relative intensity value in digital form through a balancing feedback control (24) and encoder (23). The digital value may be converted to analog form in a D-to-A converter (27) and used to vary the source of the known signal so that the attenuated intensity of the known signal at a predetermined point (comparator 16) equals the attenuated intensity of the unknown signal at the predetermined point of comparison. If the known signal is then equal to the unknown, there is verification of the analog-to-digital conversion being complete. Otherwise the output of the comparator indicating equality at some other point along the attenuators will provide an output which is encoded and added, through an accumulator comprised of a register (25) and an adder (26), to a previous relative intensity value thereby to further vary the intensity of the known signal source. The steps are repeated until full conversion is verified.

  4. Simulation of New Switched Capacitance Power Converter for Srm

    Directory of Open Access Journals (Sweden)

    S. M. Mohamed Saleem

    2014-06-01

    Full Text Available In this paper, design and simulation of switched capacitance power converter are proposed for 6/4 switched reluctance motor (SRM drive. The operating principle and design consideration of the proposed converter is explained. The proposed converter performance is better in reduction of torque ripple and constant speed can be achieved quickly with reduced power loss when compared with asymmetric converter. The proposed system is simulated by using MATLAB Simulink and their results are clearly presented.

  5. A New Modular Multilevel Converter with Integrated Energy Storage

    DEFF Research Database (Denmark)

    Trintis, Ionut; Munk-Nielsen, Stig; Teodorescu, Remus

    2011-01-01

    This paper introduces a new modular converter with integrated energy storage based on the cascaded half-bridge modular multilevel converter with common DC bus. It represents a complete modular solution with power electronics and energy storage building blocks, for medium and high voltage...... in the future HVDC meshed grids. Its functionality and flexibility makes the converter independent on the energy storage unit characteristic. The converter concept with its basic functions and control schemes are described and evaluated in this paper....

  6. Converting Student Support Services to Online Delivery

    Directory of Open Access Journals (Sweden)

    David E. Brigham

    2001-01-01

    Full Text Available This case study describes how Regents College (soon to be Excelsior College, an accredited, private, distance education institution with administrative offices in Albany, New York addressed the structural, management, and resource issues that came into play when converting distance education programs from print-based and telephone delivery to online delivery. The study uses a systems framework to describe and analyze the circumstances and issues surrounding the creation of six student support services: electronic advising, an electronic peer network, an online database of distance courses, an online bookstore, a virtual library, and an alumni services website.

  7. Dead time optimization method for power converter

    Science.gov (United States)

    Deselaers, C.; Bergmann, U.; Gronwald, F.

    2013-07-01

    This paper introduces a method for dead time optimization in variable speed motor drive systems. The aim of this method is to reduce the conduction time of the freewheeling diode to a minimum without generation of cross conduction. This results in lower losses, improved EMC, and less overshooting of the phase voltage. The principle of the method is to detect beginning cross currents without adding additional components in the half bridge like resistors or inductances. Only the wave shape of the phase voltage needs to be monitored during switching. This is illustrated by an application of the method to a real power converter.

  8. Design, modeling and testing of data converters

    CERN Document Server

    Kiaei, Sayfe; Xu, Fang

    2014-01-01

    This book presents the a scientific discussion of the state-of-the-art techniques and designs for modeling, testing and for the performance analysis of data converters. The focus is put on sustainable data conversion. Sustainability has become a public issue that industries and users can not ignore. Devising environmentally friendly solutions for data conversion designing, modeling and testing is nowadays a requirement that researchers and practitioners must consider in their activities. This book presents the outcome of the IWADC workshop 2011, held in Orvieto, Italy.

  9. Power converters for medium voltage networks

    CERN Document Server

    Islam, Md Rabiul; Zhu, Jianguo

    2014-01-01

    This book examines a number of topics, mainly in connection with advances in semiconductor devices and magnetic materials and developments in medium and large-scale renewable power plant technologies, grid integration techniques and new converter topologies, including advanced digital control systems for medium-voltage networks. The book's individual chapters provide an extensive compilation of fundamental theories and in-depth information on current research and development trends, while also exploring new approaches to overcoming some critical limitations of conventional grid integration te

  10. Waste Plastic Converting into Hydrocarbon Fuel Materials

    Energy Technology Data Exchange (ETDEWEB)

    Sarker, Moinuddin; Mamunor Rashid, Mohammad; Molla, Mohammad

    2010-09-15

    The increased demand and high prices for energy sources are driving efforts to convert organic compounds into useful hydrocarbon fuels. Although much of this work has focused on biomass, there are strong benefits to deriving fuels from waste plastic material. Natural State Research Inc. (NSR) has invented a simple and economically viable process to decompose the hydrocarbon polymers of waste plastic into the shorter chain hydrocarbon of liquid fuel (patent pending). The method and principle of the production / process will be discussed. Initial tests with several widely used polymers indicate a high potential for commercialization.

  11. Converting VSAM in COBOL to embedded SQL

    Energy Technology Data Exchange (ETDEWEB)

    Huang, Hai; Wang, Yamin; Tsai, Wei-Tek [Univ. of Minnesota, Minneapolis, MN (United States)

    1996-12-31

    VSAM databases we widely used on IBM mainframe systems. As new technology, such as relational database and client-server computing, becomes popular, there is a need to reengineer the VSAM databases to relational databases. This paper addresses the issues on converting COBOL programs that access VSAM database to COBOL programs that access relational databases with embedded SQL. It proposed a semi-automatic approach to the conversion of VSAM data sets to SQL tables and VSAM operations in COBOL program to embedded SQL queries. The proposed approach has been experimented on several industrial COBOL programs and a tool implementing the approach is under development.

  12. EMI filter techniques in power electronic converters

    Directory of Open Access Journals (Sweden)

    Fredy Edimer Hoyos Velasco

    2012-04-01

    Full Text Available This paper presents the results of EMI reduction techniques applied to power electronic converters. The techniques applied included shielding control and power signals, separating power system references regarding reference for instrumentation and measurement signals, implementing analog filters and configuring an appropriate switch trigger system for electronic power to decrease shifting EMI emissions to the maximum. This paper presents the results before and after applying the techniques to reduce interference. The results were also veryfied by using two real time control strategies rapid control prototyping (RCP.

  13. Multi Port Single Stage Power Electronics Converter and Wind PFC Converter for DC Micro Grid Applications

    Directory of Open Access Journals (Sweden)

    M. Hemachandran

    2014-08-01

    Full Text Available In this study multi port AC/DC-DC single stage power electronics converter proposed for grid power supply. The topology includes reduced number of active element and passive element. Passive element is used to provide to achieve improved voltage gain and to reduce the voltage stress of input side switches. The active-clamp circuits are used to recycle the energy stored in the leakage inductors and to improve the system performances. Here two input port (wind and battery unit and output port connected to dc grid, battery act as charge unit and source. Efficient wind power conversion is achieved by PFC boost dc-dc converter. Controlled and high step up voltage is supplied to multi-port converter from wind source.

  14. Novel screening techniques for wind turbine power converters

    DEFF Research Database (Denmark)

    Jørgensen, Asger Bjørn; Sønderskov, Simon Dyhr; Christensen, Nicklas;

    2016-01-01

    Power converters represent one of the highest failure rates in the wind turbine. Therefore converter manufacturers perform burn-in tests to prevent shipping of faulty converters. Recent developments in junction temperature estimation, based on accurate online IGBT collector-emitter voltage...

  15. Convertible Arbitrage Price Pressure and Short-Sale Constraints

    NARCIS (Netherlands)

    de Jong, Abe; Dutordoir, Marie; van Genuchten, Nathalie; Verwijmeren, Patrick

    2012-01-01

    Using a sample of 4,148 convertibles issued over 1990-2009 by companies listed in 35 countries, the authors exploited worldwide differences in short-sale constraints to examine whether short selling by convertible arbitrageurs creates downward pressure on convertible issuers' stock prices. They foun

  16. New active load voltage clamp for HF-link converters

    DEFF Research Database (Denmark)

    Ljusev, Petar; Andersen, Michael Andreas E.

    2005-01-01

    This paper proposes a new active clamp for HF-link converters, which features very high efficiency by returning the clamped energy back to the primary side through a small auxiliary converter. It also increases the reliability of HF-link converters by providing an alternative load current path du...

  17. 7 CFR 12.32 - Converted wetland identification criteria.

    Science.gov (United States)

    2010-01-01

    ... 7 Agriculture 1 2010-01-01 2010-01-01 false Converted wetland identification criteria. 12.32 Section 12.32 Agriculture Office of the Secretary of Agriculture HIGHLY ERODIBLE LAND AND WETLAND CONSERVATION Wetland Conservation § 12.32 Converted wetland identification criteria. (a) Converted...

  18. Fuzzy control of power converters based on quasilinear modelling

    Science.gov (United States)

    Li, C. K.; Lee, W. L.; Chou, Y. W.

    1995-03-01

    Unlike feedback control by the fuzzy PID method, a new fuzzy control algorithm based on quasilinear modelling of the DC-DC converter is proposed. Investigation is carried out using a buck-boost converter. Simulation results demonstrated that the converter can be regulated with improved performance even when subjected to input disturbance and load variation.

  19. Fault isolation in parallel coupled wind turbine converters

    DEFF Research Database (Denmark)

    Odgaard, Peter Fogh; Thøgersen, Paul Bach; Stoustrup, Jakob

    2010-01-01

    Parallel converters in wind turbine give a number advantages, such as fault tolerance due to the redundant converters. However, it might be difficult to isolate gain faults in one of the converters if only a combined power measurement is available. In this paper a scheme using orthogonal power re...

  20. Data Converters Performance at Extreme Temperatures

    Science.gov (United States)

    Rejeshuni, Rarnesham; Kumar, Nikil; Mao, James; Keymeulen, Didier; Zebulum, Ricardo S.; Stoica, Adrian

    2006-01-01

    Space missions often require radiation and extreme-temperature hardened electronics to survive the harsh environments beyond earth's atmosphere. Traditional approaches to preserve electronics incorporate shielding, insulation and redundancy at the expense of power and weight. However, a novel way of bypassing these problems is the concept of evolutionary hardware. A reconfgurable device, consisting of several switches interconnected with analog/digital parts, is controlled by an evolutionary processor (EP). When the EP detects degradation in the circuit it sends signals to reconfgure the switches, thus forming a new circuit with the desired output. This concept has been developed since the mid-90s, but one problem remains - the EP cannot degrade substantially. For this reason, extensive testing at extreme temperatures (-180' to 120(deg)C) has been done on devices found on FPGA boards (taking the role of the EP) such as the Analog to Digital and the Digital to Analog Converter. Analysis of the results has shown that FPGA boards implementing EP with some compensation may be a practical solution to evolving circuits. This paper describes results on the tests of data converters at extreme temperatures.

  1. Serial Pixel Analog-to-Digital Converter

    Energy Technology Data Exchange (ETDEWEB)

    Larson, E D

    2010-02-01

    This method reduces the data path from the counter to the pixel register of the analog-to-digital converter (ADC) from as many as 10 bits to a single bit. The reduction in data path width is accomplished by using a coded serial data stream similar to a pseudo random number (PRN) generator. The resulting encoded pixel data is then decoded into a standard hexadecimal format before storage. The high-speed serial pixel ADC concept is based on the single-slope integrating pixel ADC architecture. Previous work has described a massively parallel pixel readout of a similar architecture. The serial ADC connection is similar to the state-of-the art method with the exception that the pixel ADC register is a shift register and the data path is a single bit. A state-of-the-art individual-pixel ADC uses a single-slope charge integration converter architecture with integral registers and “one-hot” counters. This implies that parallel data bits are routed among the counter and the individual on-chip pixel ADC registers. The data path bit-width to the pixel is therefore equivalent to the pixel ADC bit resolution.

  2. Converting DYNAMO simulations to Powersim Studio simulations

    Energy Technology Data Exchange (ETDEWEB)

    Walker, La Tonya Nicole; Malczynski, Leonard A.

    2014-02-01

    DYNAMO is a computer program for building and running 'continuous' simulation models. It was developed by the Industrial Dynamics Group at the Massachusetts Institute of Technology for simulating dynamic feedback models of business, economic, and social systems. The history of the system dynamics method since 1957 includes many classic models built in DYANMO. It was not until the late 1980s that software was built to take advantage of the rise of personal computers and graphical user interfaces that DYNAMO was supplanted. There is much learning and insight to be gained from examining the DYANMO models and their accompanying research papers. We believe that it is a worthwhile exercise to convert DYNAMO models to more recent software packages. We have made an attempt to make it easier to turn these models into a more current system dynamics software language, Powersim © Studio produced by Powersim AS2 of Bergen, Norway. This guide shows how to convert DYNAMO syntax into Studio syntax.

  3. Wind Energy Conversion Based on Matrix Converter

    Directory of Open Access Journals (Sweden)

    Mutharasan Anburaj

    2014-07-01

    Full Text Available In recent years renewable sources such as solar, wave and wind are used for the generation of electricity. Wind is one of the major renewable sources. The amount of energy from a Wind Energy Conversion System (WECS depends not only on the wind at the site, but also on the control strategy used for the WECS. In assistance to get the appropriate wind energy from the conversion system, wind turbine generator will be run in variable speed mode. The variable speed capability is achieved through the use of an advanced power electronic converter. Fixed speed wind turbines and induction generators are often used in wind farms. But the limitations of such generators are low efficiency and poor power quality which necessitates the variable speed wind turbine generators such as Doubly Fed Induction Generator (DFIG and Permanent Magnet Synchronous Generator (PMSG. A high-performance configuration can be obtained by using Scherbius drive composed of a DFIG and a converter in combination AC-DC-AC connect between stator & rotor points for providing the required variable speed operation

  4. A novel converter topology for TEM applications

    Indian Academy of Sciences (India)

    S Kedarnath; Krishna Vasudevan

    2008-10-01

    Time-domain Electro Magnetic (TEM) systems, are used for remote sensing of conductive mineral deposits buried under the surface of the earth. A low frequency trapezoidal current excitation set-up in an exciter coil loop causes a flux that penetrates deep into the earth. When the excitation is cut off sharply, conductive deposits in the earth carrying flux react by causing eddy current flows within them. The flux produced by such eddy currents is picked up by a sensor coil. By comparing the emf induced in the sensor coil with a priori known emf patterns for mineral deposits, the presence of mineral deposits can be ascertained. The voltage, current and energy levels of the TEM system, require special type of excitation technique. Power converters for such non-standard requirements are not reported in the literature, particularly for TEM applications. This paper introduces TEM systems to the reader and presents the requirements for excitation. A converter topology to meet the requirements, it’s analysis, control and performance are presented. Among other alternatives that the authors have attempted, the topology presented features reduced number of passive elements, high voltage gain and low losses. These features enable the sensor head to be operated from the normal low level battery.

  5. Forback DC-to-DC converter

    Science.gov (United States)

    Lukemire, Alan T.

    1995-05-01

    A pulse-width modulated DC-to-DC power converter including a first inductor, i.e. a transformer or an equivalent fixed inductor equal to the inductance of the secondary winding of the transformer, coupled across a source of DC input voltage via a transistor switch which is rendered alternately conductive (ON) and nonconductive (OFF) in accordance with a signal from a feedback control circuit is described. A first capacitor capacitively couples one side of the first inductor to a second inductor which is connected to a second capacitor which is coupled to the other side of the first inductor. A circuit load shunts the second capacitor. A semiconductor diode is additionally coupled from a common circuit connection between the first capacitor and the second inductor to the other side of the first inductor. A current sense transformer generating a current feedback signal for the switch control circuit is directly coupled in series with the other side of the first inductor so that the first capacitor, the second inductor and the current sense transformer are connected in series through the first inductor. The inductance values of the first and second inductors, moreover, are made identical. Such a converter topology results in a simultaneous voltsecond balance in the first inductance and ampere-second balance in the current sense transformer.

  6. Forback DC-to-DC converter

    Science.gov (United States)

    Lukemire, Alan T. (Inventor)

    1993-01-01

    A pulse-width modulated DC-to-DC power converter including a first inductor, i.e. a transformer or an equivalent fixed inductor equal to the inductance of the secondary winding of the transformer, coupled across a source of DC input voltage via a transistor switch which is rendered alternately conductive (ON) and nonconductive (OFF) in accordance with a signal from a feedback control circuit is described. A first capacitor capacitively couples one side of the first inductor to a second inductor which is connected to a second capacitor which is coupled to the other side of the first inductor. A circuit load shunts the second capacitor. A semiconductor diode is additionally coupled from a common circuit connection between the first capacitor and the second inductor to the other side of the first inductor. A current sense transformer generating a current feedback signal for the switch control circuit is directly coupled in series with the other side of the first inductor so that the first capacitor, the second inductor and the current sense transformer are connected in series through the first inductor. The inductance values of the first and second inductors, moreover, are made identical. Such a converter topology results in a simultaneous voltsecond balance in the first inductance and ampere-second balance in the current sense transformer.

  7. Angiotensin converting enzyme 2 and atherosclerosis.

    Science.gov (United States)

    Wang, Yutang; Tikellis, Chris; Thomas, Merlin C; Golledge, Jonathan

    2013-01-01

    Angiotensin converting enzyme 2 (ACE2) is a homolog of angiotensin converting enzyme (ACE) which generates angiotensin II from angiotensin I. ACE, its product angiotensin II and the downstream angiotensin type I receptor are important components of the renin-angiotensin system (RAS). Angiotensin II, the most important component of the RAS, promotes the development of atherosclerosis. The identification of ACE2 in 2000 opened a new chapter of research on the regulation of the RAS. ACE2 degrades pro-atherosclerotic angiotensin II and generates anti-atherosclerotic angiotensin 1-7. In this review, we explored the importance of ACE2 in protecting experimental animals from developing atherosclerosis and its involvement in human atherosclerosis. We also examined the published evidence assessing the importance of ACE2 in different cell types relevant to atherosclerosis and putative underlying cellular and molecular mechanisms linking ACE2 with protection from atherosclerosis. ACE2 shifts the balance from angiotensin II to angiotensin 1-7 inhibiting the progression of atherosclerosis in animal models.

  8. CCLIBS: The CERN Power Converter Control Libraries

    CERN Document Server

    AUTHOR|(SzGeCERN)404953; Lebioda, Krzysztof Tomasz; Magrans De Abril, Marc; Martino, Michele; Murillo Garcia, Raul; Nicoletti, Achille

    2015-01-01

    Accurate control of power converters is a vital activity in large physics projects. Several different control scenarios may coexist, including regulation of a circuit’s voltage, current, or field strength within a magnet. Depending on the type of facility, a circuit’s reference value may be changed asynchronously or synchronously with other circuits. Synchronous changes may be on demand or under the control of a cyclic timing system. In other cases, the reference may be calculated in real-time by an outer regulation loop of some other quantity, such as the tune of the beam in a synchrotron. The power stage may be unipolar or bipolar in voltage and current. If it is unipolar in current, it may be used with a polarity switch. Depending on the design, the power stage may be controlled by a firing angle or PWM duty-cycle reference, or a voltage or current reference. All these cases are supported by the CERN Converter Control Libraries (CCLIBS). These open-source C libraries include advanced reference generati...

  9. Buck-boost converter feedback controller design via evolutionary search

    Science.gov (United States)

    Sundareswaran, K.; Devi, V.; Nadeem, S. K.; Sreedevi, V. T.; Palani, S.

    2010-11-01

    Buck-boost converters are switched power converters. The model of the converter system varies from the ON state to the OFF state and hence traditional methods of controller design based on approximate transfer function models do not yield good dynamic response at different operating points of the converter system. This article attempts to design a feedback controller for a buck-boost type dc-dc converter using a genetic algorithm. The feedback controller design is perceived as an optimisation problem and a robust controller is estimated through an evolutionary search. Extensive simulation and experimental results provided in the article show the effectiveness of the new approach.

  10. A nanoscale linear-to-linear motion converter of graphene.

    Science.gov (United States)

    Dai, Chunchun; Guo, Zhengrong; Zhang, Hongwei; Chang, Tienchong

    2016-08-14

    Motion conversion plays an irreplaceable role in a variety of machinery. Although many macroscopic motion converters have been widely used, it remains a challenge to convert motion at the nanoscale. Here we propose a nanoscale linear-to-linear motion converter, made of a flake-substrate system of graphene, which can convert the out-of-plane motion of the substrate into the in-plane motion of the flake. The curvature gradient induced van der Waals potential gradient between the flake and the substrate provides the driving force to achieve motion conversion. The proposed motion converter may have general implications for the design of nanomachinery and nanosensors.

  11. Affecting Factors and Improving Measures for Converter Gas Recovery

    Institute of Scientific and Technical Information of China (English)

    2007-01-01

    To change the undesirable present situation of recovering and using converter gas in steel plants in China,the basic approaches to improving the converter gas recovery rate were analyzed theoretically along with the change curves of the converter gas component content, based on the converter gas recovery system of Baosteel No. 2 steelmaking plant. The effects of converter device, raw material, air imbibed quantity, recovery restricted condition, and intensity of oxygen blowing on the converter gas recovery rate were studied. Among these, the effects of the air imbibed quantity, recovery restricted condition, and intensity of oxygen blowing are remarkable. Comprehensive measures were put forward for improving the converter gas recovery from the point of devices, etc. , and good results were achieved.

  12. Bifurcation behaviours of peak current controlled PFC boost converter

    Institute of Scientific and Technical Information of China (English)

    Ren Hai-Peng; Liu Ding

    2005-01-01

    Bifurcation behaviours of the peak current controlled power-factor-correction (PFC) boost converter, including fast-scale instability and low-frequency bifurcation, are investigated in this paper. Conventionally, the PFC converter is analysed in continuous conduction mode (CCM). This prevents us from recognizing the overall dynamics of the converter. It has been pointed out that the discontinuous conduction mode (DCM) can occur in the PFC boost converter, especially in the light load condition. Therefore, the DCM model is employed to analyse the PFC converter to cover the possible DCM operation. By this way, the low-frequency bifurcation diagram is derived, which makes the route from period-double bifurcation to chaos clear. The bifurcation diagrams versus the load resistance and the output capacitance also indicate the stable operation boundary of the converter, which is useful for converter design.

  13. Pricing Chinese Convertible Bonds with Dynamic Credit Risk

    Directory of Open Access Journals (Sweden)

    Ping Li

    2014-01-01

    Full Text Available To price convertible bonds more precisely, least squares Monte Carlo (LSM method is used in this paper for its advantage in handling the dependence of derivatives on the path, and dynamic credit risk is used to replace the fixed one to make the value of convertible bonds reflect the real credit risk. In the empirical study, we price convertible bonds based on static credit risk and dynamic credit risk, respectively. Empirical results indicate that the ICBC convertible bond has been overpriced, resulting from the underestimation of credit risk. In addition, when there is an issue of dividend, the conversion price will change in China's convertible bonds, while it does not change in the international convertible bonds. So we also empirically study the difference between the convertible bond's prices by assuming whether the conversion price changes or not.

  14. Converter applications and their influence on large electrical machines

    CERN Document Server

    Drubel, Oliver

    2013-01-01

    Converter driven applications are applied in more and more processes. Almost any installed wind-farm, ship drives, steel mills, several boiler feed water pumps, extruder and many other applications operate much more efficient and economic in case of variable speed solutions. The boundary conditions for a motor or generator will change, if it is supplied by a converter. An electrical machine, which is operated by a converter, can no longer be regarded as an independent component, but is embedded in a system consisting of converter and machine. This book gives an overview of existing converter designs for large electrical machines. Methods for the appropriate calculation of machine phenomena, which are implied by converters are derived in the power range above 500kVA. It is shown how due to the converter inherent higher voltage harmonics and pulse frequencies special phenomena are caused inside the machine which can be the reason for malfunction. It is demonstrated that additional losses create additional tempe...

  15. Three-phase Resonant DC-link Converter

    DEFF Research Database (Denmark)

    Munk-Nielsen, Stig

    no additional power electric components is eliminating the high voltage peaks associated with the resonant circuit. The resonant link voltage peaks are limited below 2.1 times the DC link voltages. A new principle eliminating former resonant converter stability problems are proposed, implemented and tested......The purpose of the project is to develop a three-phase resonant converter suitable for standard speed drives. The motivation for working with resonant converters is found in the problem of the standard converter type used today. In standard converter type Pulse Width Modulated-Voltage Source....... The high speed of the switches cannot be fully utilizied. By using a parallel resonant converter the switching happens at low or zero voltage which reduses switch losses. The dv/dt is controlled by the resonant circuit, and it is therefore reduced significantly. The perspective using a resonant converter...

  16. Generators for gearless wind energy converters

    Energy Technology Data Exchange (ETDEWEB)

    Grauers, A. [Chalmers Univ. of Technology, Goeteborg (Sweden). Dept. of Electric Power Engineering

    1996-12-01

    This paper discusses some design alternatives for directly driven generators, and one specific generator type is investigated for a wide range of rated power. First, the specification for a directly driven generator is presented, then different design alternatives are discussed. A radial-flux permanent magnet generator for frequency converter connection has been chosen for a more detailed investigation. The design, optimization and performance of that generator type are presented. Generators from 30 kW to 3 MW are designed and compared with conventional four-pole generators with gear. It is found that a directly driven generator can be more efficient than a conventional generator and gear and have a rather small diameter and a low active weight. 8 refs, 7 figs, 2 tabs

  17. Converting energy from fusion into useful forms

    CERN Document Server

    Kovari, M; Jenkins, I; Kiely, C

    2014-01-01

    If fusion power reactors are to be feasible, it will still be necessary to convert the energy of the nuclear reaction into usable form. The heat produced will be removed from the reactor core by a primary coolant, which might be water, helium, molten lithium-lead, molten lithium-containing salt, or CO2. The heat could then be transferred to a conventional Rankine cycle or Brayton (gas turbine) cycle. Alternatively it could be used for thermochemical processes such as producing hydrogen or other transport fuels. Fusion presents new problems because of the high energy neutrons released. These affect the selection of materials and the operating temperature, ultimately determining the choice of coolant and working cycle. The limited temperature ranges allowed by present day irradiated structural materials, combined with the large internal power demand of the plant, will limit the overall thermal efficiency. The operating conditions of the fusion power source, the materials, coolant, and energy conversion system w...

  18. Converting environmental documentation to management information

    Energy Technology Data Exchange (ETDEWEB)

    Larsen, M.J.; Frentz, H.J. [Tracor Technology Resources, Inc., Rockville, MD (United States)

    1996-12-01

    The growth of environmental, health, and safety regulations and their reporting requirements has been extraordinary. Penalties for missteps in environmental documentation also grow more serious. Every major piece of environmental legislation requires facilities to collect data and maintain records, in many cases detailed records for long periods of time, on raw materials, processes, emissions, events, personnel, and many other facets of business operations. Unfortunately, for some organizations, the collection of data that satisfies regulatory requirements is an end in itself. Data acquired in this manner may result in little useful information that managers can use to foster their business goals. For organizations of any appreciable size, the volume of environmental data, in manual form, makes analysis difficult to impossible. Too often, data resides in disparate databases, in different locations, and within incompatible information management systems. This paper discusses converting these disparate databases into a useful system.

  19. Clustering of cycloidal wave energy converters

    Science.gov (United States)

    Siegel, Stefan G.

    2016-03-29

    A wave energy conversion system uses a pair of wave energy converters (WECs) on respective active mountings on a floating platform, so that the separation of the WECs from each other or from a central WEC can be actively adjusted according to the wavelength of incident waves. The adjustable separation facilitates operation of the system to cancel reactive forces, which may be generated during wave energy conversion. Modules on which such pairs of WECs are mounted can be assembled with one or more central WECs to form large clusters in which reactive forces and torques can be made to cancel. WECs of different sizes can be employed to facilitate cancelation of reactive forces and torques.

  20. Intermittency in Switching Power Converters: Theoretical Analysis

    Institute of Scientific and Technical Information of China (English)

    ZHOU Yu-fei; CHEN Jun-ning; TSE Chi K.; QIU Shui-sheng; KE Dao-ming; SHI Long-xing; SUN Wei-feng

    2006-01-01

    In view of reasonable explanation of intermittent subharmonics and chaos that can be gained from coupling filter between circuits,this paper discusses a method that maps time bifurcation with parameter bifurcation.Based on this mapping method,the general analysis method of characteristic multiplier,which is originally aimed at parameter bifurcation,can be used for the study of intermittency,i.e.,time bifurcation.In this paper,all researches coming from characteristic multipliers,parameter-bifurcation diagrams,and the largest Lyapunov exponent indicate the same results as those produced by simulation and experiment.Thus,it is proved theoretically that the intermittency in switching power converter can be explained in terms of coupling of spurious interference.

  1. Will oscillating wave surge converters survive tsunamis?

    Directory of Open Access Journals (Sweden)

    L. O’Brien

    2015-07-01

    Full Text Available With an increasing emphasis on renewable energy resources, wave power technology is becoming one of the realistic solutions. However, the 2011 tsunami in Japan was a harsh reminder of the ferocity of the ocean. It is known that tsunamis are nearly undetectable in the open ocean but as the wave approaches the shore its energy is compressed, creating large destructive waves. The question posed here is whether an oscillating wave surge converter (OWSC could withstand the force of an incoming tsunami. Several tools are used to provide an answer: an analytical 3D model developed within the framework of linear theory, a numerical model based on the non-linear shallow water equations and empirical formulas. Numerical results show that run-up and draw-down can be amplified under some circumstances, leading to an OWSC lying on dry ground!

  2. Transcutaneous optical power converter for implantable devices

    Science.gov (United States)

    Tamura, Toshiyo; Shamsuddin, A. K. M.; Kawarada, Atsushi; Togawa, Tatsuo; Oberg, P. Ake

    1994-02-01

    An optical transcutaneous power converter has been developed for the power supply of implanted devices. It consists of a light source, optical fiber system and a photo detector. The light source is either a halogen lamp or continuous high-power laser diode which illuminated skin surface. The light penetrates through the skin to the solar cells. The preliminary experiments with a slice of tissue in between the light source and the solar cells showed that the power transfer efficiency was 40% in comparison to direct illumination of the solar cells. The maximum electric power obtained with a slice of tissue simulating the skin was about 8 mW at a laser diode run at a power of 100 mW. The electric power transferred is enough to supply low power consuming CMOS circuits.

  3. Performance Evaluation of Wave Energy Converters

    DEFF Research Database (Denmark)

    Pecher, Arthur

    Ocean waves provide a sustainable, power-dense, predictable and widely available source of energy that could provide about 10 % of worlds energy needs. While research into waveenergy has been undertaken for decades, a significant increase in related activities has been seen in the recent years......, with more than 150 concepts currently being developed worldwide. Wave energy conversion concepts can be of many kinds, as the energy in the waves can be absorbed in many different ways. However, each concept is expected to require a thorough development process, involving different phases and prototypes....... Guidelines for the development of wave energy converters recommend the use of different prototypes, having different sizes, which have to perform tank tests or sea trials. Thisimplicates the need of different testing environment, which shifts from being controllable to uncontrollable with the development...

  4. Performance Evaluation of Wave Energy Converters

    DEFF Research Database (Denmark)

    Pecher, Arthur

    Ocean waves provide a sustainable, power-dense, predictable and widely available source of energy that could provide about 10 % of worlds energy needs. While research into wave energy has been undertaken for decades, a significant increase in related activities has been seen in the recent years......, with more than 150 concepts currently being developed worldwide. Wave energy conversion concepts can be of many kinds, as the energy in the waves can be absorbed in many different ways. However, each concept is expected to require a thorough development process, involving different phases and prototypes....... Guidelines for the development of wave energy converters recommend the use of different prototypes, having different sizes, which have to perform tank tests or sea trials. This implicates the need of different testing environment, which shifts from being controllable to uncontrollable with the development...

  5. Mechanical vibration to electrical energy converter

    Science.gov (United States)

    Kellogg, Rick Allen; Brotz, Jay Kristoffer

    2009-03-03

    Electromechanical devices that generate an electrical signal in response to an external source of mechanical vibrations can operate as a sensor of vibrations and as an energy harvester for converting mechanical vibration to electrical energy. The devices incorporate a magnet that is movable through a gap in a ferromagnetic circuit, wherein a coil is wound around a portion of the ferromagnetic circuit. A flexible coupling is used to attach the magnet to a frame for providing alignment of the magnet as it moves or oscillates through the gap in the ferromagnetic circuit. The motion of the magnet can be constrained to occur within a substantially linear range of magnetostatic force that develops due to the motion of the magnet. The devices can have ferromagnetic circuits with multiple arms, an array of magnets having alternating polarity and, encompass micro-electromechanical (MEM) devices.

  6. Passive components used in power converters

    CERN Document Server

    Rufer, A; Barrade, P

    2006-01-01

    In power converters, passive components play an important role, and have in general specific nature and properties. The goal of this tutorial is to give an overview, first on inductive components for power conversion, and second on dedicated power capacitors. In a third part, new components— supercapacitors—will be presented. Generally, inductors for power applications must be custom designed. In this tutorial, the most important effects encountered when realising inductive components will be presented in the first part, without entering into the detailed design of such components. For that purpose, the referenced documents that have served as a base for this tutorial must be consulted [1], [2], and mainly [3]. The second part of this tutorial (Capacitors used in power electronics) is dedicated to power capacitors. Unlike inductors, capacitors cannot be specifically designed, but must be selected from a manufacturer’s list of components. Here, the documentation corresponds to a subset of Ref. [4] that h...

  7. Modular Power Converters for PV Applications

    Energy Technology Data Exchange (ETDEWEB)

    Ozpineci, Burak [ORNL; Tolbert, Leon M [ORNL

    2012-05-01

    This report describes technical opportunities to serve as parts of a technological roadmap for Shoals Technologies Group in power electronics for PV applications. There are many different power converter circuits that can be used for solar inverter applications. The present applications do not take advantage of the potential for using common modules. We envision that the development of a power electronics module could enable higher reliability by being durable and flexible. Modules would have fault current limiting features and detection circuits such that they can limit the current through the module from external faults and can identify and isolate internal faults such that the remaining modules can continue to operate with only minimal disturbance to the utility or customer. Development of a reliable, efficient, low-cost, power electronics module will be a key enabling technology for harnessing more power from solar panels and enable plug and play operation. Power electronics for computer power supplies, communication equipment, and transportation have all targeted reliability and modularity as key requirements and have begun concerted efforts to replace monolithic components with collections of common smart modules. This is happening on several levels including (1) device level with intelligent control, (2) functional module level, and (3) system module. This same effort is needed in power electronics for solar applications. Development of modular units will result in standard power electronic converters that will have a lower installed and operating cost for the overall system. These units will lead to increased adaptability and flexibility of solar inverters. Incorporating autonomous fault current limiting and reconfiguration capabilities into the modules and having redundant modules will lead to a durable converter that can withstand the rigors of solar power generation for more than 30 years. Our vision for the technology roadmap is that there is no need

  8. A system for converting print into braille.

    Science.gov (United States)

    Blenkhorn, P

    1997-06-01

    This paper describes a method for converting text into braille, in the form in which it is stored as in a computer. The system has been designed to be configurable for a wide range of languages and character sets, and uses a predominantly table driven method to achieve this. The algorithm is explained in the context of the conversion of text into Standard English Braille (British), and the tables for this transformation are given. Particular importance has been attached to enabling braille specialists, who are not experts in computer algorithms, to be able to modify the system for either slight modifications to an existing braille code translator, or for producing a braille code translator for a new language.

  9. Simplifying the circuit of Josephson parametric converters

    Science.gov (United States)

    Abdo, Baleegh; Brink, Markus; Chavez-Garcia, Jose; Keefe, George

    Josephson parametric converters (JPCs) are quantum-limited three-wave mixing devices that can play various important roles in quantum information processing in the microwave domain, including amplification of quantum signals, transduction of quantum information, remote entanglement of qubits, nonreciprocal amplification, and circulation of signals. However, the input-output and biasing circuit of a state-of-the-art JPC consists of bulky components, i.e. two commercial off-chip broadband 180-degree hybrids, four phase-matched short coax cables, and one superconducting magnetic coil. Such bulky hardware significantly hinders the integration of JPCs in scalable quantum computing architectures. In my talk, I will present ideas on how to simplify the JPC circuit and show preliminary experimental results

  10. Hybrid-free Josephson Parametric Converter

    Science.gov (United States)

    Frattini, N. E.; Narla, A.; Sliwa, K. M.; Shankar, S.; Hatridge, M.; Devoret, M. H.

    A necessary component for any quantum computation architecture is the ability to perform efficient quantum operations. In the microwave regime of superconducting qubits, these quantum-limited operations can be realized with a non-degenerate Josephson junction based three-wave mixer, the Josephson Parametric Converter (JPC). Currently, the quantum signal of interest must pass through a lossy 180 degree hybrid to be presented as a differential drive to the JPC. This hybrid therefore places a limit on the quantum efficiency of the system and also increases the device footprint. We present a new design for the JPC eliminating the need for any external hybrid. We also show that this design has nominally identical performance to the conventional JPC. Work supported by ARO, AFOSR and YINQE.

  11. Radiant energy to electric energy converter

    Science.gov (United States)

    Sher, Arden (Inventor)

    1980-01-01

    Radiant energy is converted into electric energy by irradiating a capacitor including an ionic dielectric. The dielectric is a sintered crystal superionic conductor, e.g., lanthanum trifluoride, lanthanum trichloride, or silver bromide, so that a multiplicity of crystallites exist between electrodes of the capacitor. The radiant energy cyclically irradiates the dielectric so that the dielectric exhibits a cyclic photocapacitive like effect. Adjacent crystallites have abutting surfaces that enable the crystallites to effectively form a multiplicity of series capacitor elements between the electrodes. Each of the capacitor elements has a dipole layer only on or near its surface. The capacitor is initially charged to a voltage just below the dielectric breakdown voltage by connecting it across a DC source causing a current to flow through a charging resistor to the dielectric. The device can be utilized as a radiant energy detector or as a solar energy cell.

  12. A 4-Channel Waveform Sampling ASIC in 0.13 μm CMOS for front-end Readout of Large-Area Micro-Channel Plate Detectors

    Science.gov (United States)

    Oberla, E.; Grabas, H.; Bogdan, M.; Frisch, H.; Genat, J. F.; Nishimura, K.; Varner, G.; Wong, A.

    We describe here the development of PSEC-3, a custom integrated circuit designed in the IBM-8RF 0.13 μm CMOS process and intended for fast, low-power waveform sampling. As part of the Large-Area Picosecond Photo-Detector (LAPPD) collaboration, this chip has been designed as a prototype application-specific integrated circuit (ASIC) for the front-end transmission line readout of large-area micro-channel plate photomultiplier tubes (MCP-PMTs). With 4 channels, PSEC-3 has a buffer depth of 256 samples on each channel, a chip-parallel ramp-compare ADC, and a serial data readout that includes the capability for region-of-interest windowing to reduce dead time. Chip calibrations and performance results, including achieved sampling rates of 2.5-17 GSa/s, are reported. Some design issues are identified, in particular the dependence of analog bandwidth on location in the sampling array. The causes have been found and addressed in a subsequent PSEC-4 submission.

  13. CLARO-CMOS: a fast, low power and radiation-hard front-end ASIC for single-photon counting in 0.35 micron CMOS technology

    Science.gov (United States)

    Andreotti, M.; Baldini, W.; Calabrese, R.; Carniti, P.; Cassina, L.; Cotta Ramusino, A.; Fiorini, M.; Giachero, A.; Gotti, C.; Luppi, E.; Maino, M.; Malaguti, R.; Pessina, G.; Tomassetti, L.

    2015-01-01

    The CLARO-CMOS is a prototype ASIC designed for fast photon counting with multi-anode photomultiplier tubes (MaPMT). The CLARO features a 5 ns peaking time, a recovery time to baseline smaller than 25 ns, and a power consumption of less than 1 mW per channel. The chip was designed in 0.35 μm CMOS technology, and was tested for radiation hardness with neutrons up to 1014 1 MeV neq/cm2, X-rays up to 40 kGy and protons up to 76 kGy. Its capability to read out single photons at high rate from a Hamamatsu R11265 MaPMT, the baseline photon detector for the LHCb RICH upgrade, was demonstrated both with test bench measurements and with actual signals from a R11265 MaPMT. The presented results allowed CLARO to be chosen as the front-end readout chip in the upgraded LHCb RICH detector.

  14. Chromatic X-Ray imaging with a fine pitch CdTe sensor coupled to a large area photon counting pixel ASIC

    CERN Document Server

    Bellazzini, R; Brez, A; Minuti, M; Pinchera, M; Mozzo, P

    2012-01-01

    An innovative X-ray imaging sensor with intrinsic digital characteristics is presented. It is based on Chromatic Photon Counting technology. The detector is able to count individually the incident X-ray photons and to separate them according to their energy (two 'color' images per exposure). The energy selection occurs in real time and at radiographic imaging speed (GHz global counting rate). Photon counting, color mode and a very high spatial resolution (more than 10 l.p./mm at MTF50) allow to obtain an optimal ratio between image quality and absorbed dose. The individual block of the imaging system is a two-side buttable semiconductor radiation detector made of a thin pixellated CdTe crystal (the sensor) coupled to a large area VLSI CMOS pixel ASIC. 1, 2, 4, 8 tile units have been built. The 8 tiles unit has 25cm x 2.5cm sensitive area. Results and images obtained from in depth testing of several configurations of the system are presented. The X-Ray imaging system is the technological platform of PIXIRAD Im...

  15. Integrated Solar Power Converters: Wafer-Level Sub-Module Integrated DC/DC Converter

    Energy Technology Data Exchange (ETDEWEB)

    None

    2012-02-09

    Solar ADEPT Project: CU-Boulder is developing advanced power conversion components that can be integrated into individual solar panels to improve energy yields. The solar energy that is absorbed and collected by a solar panel is converted into useable energy for the grid through an electronic component called an inverter. Many large, conventional solar energy systems use one, central inverter to convert energy. CU-Boulder is integrating smaller, microinverters into individual solar panels to improve the efficiency of energy collection. The University’s microinverters rely on electrical components that direct energy at high speeds and ensure that minimal energy is lost during the conversion process—improving the overall efficiency of the power conversion process. CU-Boulder is designing its power conversion devices for use on any type of solar panel.

  16. Synchronously Driven Power Converter Controller Solution for MedAustron

    CERN Document Server

    Šepetavc, Luka; Tavčar, Rok; Moser, Roland; Gutleber, Johannes

    2011-01-01

    MedAustron is an ion beam cancer therapy and research centre currently under construction in Wiener Neustadt, Austria. This facility features a synchrotron particle accelerator for light ions. Cosylab is closely working together with MedAustron on the development of a power converter controller (PCC) for the 260 deployed power converters – power supplies. Power converters deliver power to magnets used for focusing and steering particle beams. We have designed and developed software and hardware which allows integration of different types of power converters into MedAustron's control system (MACS). PCC's role is to synchronously control and monitor connected power converters. Custom real-time fibre optics link and modular front end devices have been designed for this purpose. Modular front end devices make it possible to interface with almost any type of power converter – with or without built in regulation logic. We implemented realtime mechanisms and a dedicated real-time fibre link to ...

  17. High Voltage Bi-directional Flyback Converter for Capacitive Actuator

    DEFF Research Database (Denmark)

    Thummala, Prasanth; Zhang, Zhe; Andersen, Michael A. E.

    2013-01-01

    This paper presents a high voltage DC-DC converter topology for bi-directional energy transfer between a low voltage DC source and a high voltage capacitive load. The topology is a bi-directional flyback converter with variable switching frequency control during the charge mode, and constant...... switching frequency control during the discharge mode. The converter is capable of charging the capacitive load from 24 V DC source to 2.5 kV, and discharges it to 0 V. The flyback converter has been analyzed in detail during both charge and discharge modes, by considering all the parasitic elements...... in the converter, including the most dominating parameters of the high voltage transformer viz., self-capacitance and leakage inductance. The specific capacitive load for this converter is a dielectric electro active polymer (DEAP) actuator, which can be used as an effective replacement for conventional actuators...

  18. Design & Implementation of Zero Voltage Switching Buck Converter

    Directory of Open Access Journals (Sweden)

    A.Suresh Kumar

    2014-09-01

    Full Text Available Zero voltage switching (ZVS buck converter is more preferable over hard switched buck converter for low power, high frequency DC-DC conversion applications. In Zero voltage switching converter, turn on & turn off of a switch occurs at zero voltage that results in lower switching losses. In this converter soft switching is achieved by using resonant components. The optimal values of resonant components are determined by using electric functions derived from circuit configuration. This type of soft switched resonant converter offers very low electromagnetic interference (EMI.This study presents the circuit configuration with least components to realize highly efficient zero voltage switching resonant converter. It’s feasibility is confirmed with the developed proto type model and experimental results are verified.

  19. Closed Loop Control of Soft Switched Interleaved Buck Converter

    Directory of Open Access Journals (Sweden)

    R. Shenbagalakshmi

    2012-06-01

    Full Text Available Design, Modeling and Simulation of a closed loop control is presented for Interleaved Buck Converter with Soft Switching. The features of the closed loop system are to reduce the switching losses and load current sharing among the parallel connected converters. The control system of the converter is designed using PWM technique. In order to improve the transient response and dynamic stability of the converters, the controller parameters are designed based on current mode control. Resonant components thus designed enable the application of zero current switching for both the converters connected in parallel thereby maintaining greater efficiency and minimizing voltage and current oscillations. The system analysis, design and performance are verified through simulation using MATLAB/Simulink environment. The simulation approach reveals the high speed dynamic performance of the closed loop system designed using robust PID controller. The laboratory prototype of the Buck converter is developed to verify the controller platform using PIC16F877A microcontroller.

  20. Symmetry Analysis of Thermoelectric Energy Converters with Inhomogeneous Legs

    Science.gov (United States)

    Korzhuev, M. A.

    2010-09-01

    Symmetry analysis has been applied to thermoelectric energy converters [thermoelectric generators (TEG), coolers (TEC), and heaters (TEH)] with inhomogeneous legs. The features of the crystallographic symmetry of thermoelectric materials and the symmetry of legs, thermocouples, and modules are studied. The effect of symmetry on the figure of merit Z of thermoelectric energy converters is considered. A general rule for proper placement of legs in thermoelectric converters is developed. A modified tetratomic classification for thermoelectric energy converters with inhomogeneous legs (TEGa, TEGb, TEC, and TEH) is proposed. An increase in Z for thermoelectric energy converters with inhomogeneous legs is due to the bulk thermoelectric effect. An increase in Z gives the reduction of irreversible processes in the modules (Joule heating and thermal conductivity), accompanying breaking of the symmetry of the legs. It is found that violations of the symmetry requirements can lead to significant energy losses in converters.