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Sample records for charge-to-time converter asic

  1. High-speed charge-to-time converter ASIC for the Super-Kamiokande detector

    CERN Document Server

    Nishino, H; Hayato, Y; Nakayama, S; Okumura, K; Shiozawa, M; Takeda, A; Ishikawa, K; Minegishi, A; Arai, Y; 10.1016/j.nima.2009.09.026

    2009-01-01

    A new application-specific integrated circuit (ASIC), the high-speed charge-to-time converter (QTC) IWATSU CLC101, provides three channels, each consisting of preamplifier, discriminator, low-pass filter, and charge integration circuitry, optimized for the waveform of a photomultiplier tube (PMT). This ASIC detects PMT signals using individual built-in discriminators and drives output timing signals whose width represents the integrated charge of the PMT signal. Combined with external input circuits composed of passive elements, the QTC provides full analog signal processing for the detector's PMTs, ready for further processing by time-to-digital converters (TDCs). High-rate (>1MHz) signal processing is achieved by short-charge-conversion-time and baseline-restoration circuits. Wide-range charge measurements are enabled by offering three gain ranges while maintaining a short cycle time. QTC chip test results show good analog performance, with efficient detection for a single photoelectron signal, four orders ...

  2. A multichannel time-to-digital converter ASIC with better than 3 ps RMS time resolution

    International Nuclear Information System (INIS)

    The development of a new multichannel, fine-time resolution time-to-digital converter (TDC) ASIC is currently under development at CERN. A prototype TDC has been designed, fabricated and successfully verified with demonstrated time resolutions of better than 3 ps-rms. Least-significant-bit (LSB) sizes as small as 5 ps with a differential-non-linearity (DNL) of better than ±0.9 LSB and integral-non-linearity (INL) of better than ±1.3 LSB respectively have been achieved. The contribution describes the implemented architecture and presents measurement results of a prototype ASIC implemented in a commercial 130 nm technology

  3. A four channel time-to-digital converter ASIC with in-built calibration and SPI interface

    International Nuclear Information System (INIS)

    A design of high resolution, wide dynamic range Time-to-Digital Converter (TDC) ASIC, implemented in 0.35 µm commercial CMOS technology is presented. The ASIC features four channel TDC with an in-built calibration and Serial Peripheral Interconnect (SPI) slave interface. The TDC is based on the vernier ring oscillator method in order to achieve both high resolution and wide dynamic range. This TDC ASIC is tested and found to have resolution of 127 ps (LSB), dynamic range of 1.8 µs and precision (σ) of 74 ps. The measured values of differential non-linearity (DNL) and integral non-linearity (INL) are 350 ps and 300 ps respectively

  4. A four channel time-to-digital converter ASIC with in-built calibration and SPI interface

    Energy Technology Data Exchange (ETDEWEB)

    Hari Prasad, K.; Sukhwani, Menka [Electronics Division, Bhabha Atomic Research Center, Mumbai 400085 (India); Saxena, Pooja [Homi Bhabha National Institute, Mumbai 400094 (India); Chandratre, V.B., E-mail: vbc@barc.gov.in [Electronics Division, Bhabha Atomic Research Center, Mumbai 400085 (India); Pithawa, C.K. [Electronics Division, Bhabha Atomic Research Center, Mumbai 400085 (India)

    2014-02-11

    A design of high resolution, wide dynamic range Time-to-Digital Converter (TDC) ASIC, implemented in 0.35 µm commercial CMOS technology is presented. The ASIC features four channel TDC with an in-built calibration and Serial Peripheral Interconnect (SPI) slave interface. The TDC is based on the vernier ring oscillator method in order to achieve both high resolution and wide dynamic range. This TDC ASIC is tested and found to have resolution of 127 ps (LSB), dynamic range of 1.8 µs and precision (σ) of 74 ps. The measured values of differential non-linearity (DNL) and integral non-linearity (INL) are 350 ps and 300 ps respectively.

  5. The Design of an Asic Control Chip for a Forward Active Clamp Converter and the Investigation of Integratable Lateral Power Devices

    OpenAIRE

    Dong, Wei

    1997-01-01

    In Part I, the design of an ASIC control chip for a forward active clamp converter is presented. Integration of the control and drive circuit into one IC chip results in higher power density, higher reliability for the converter module. The designed ASIC control chip uses a 2.0 um N well Analog CMOS process, and is fabricated at MOSIS. The design procedures of the ASIC chip are explained, and experimental results are presented. Part II of the thesis focuses on the numerical investigat...

  6. ASIC and FPGA based DPWM architectures for single-phase and single-output DC-DC converter: a review

    Science.gov (United States)

    Chander, Subhash; Agarwal, Pramod; Gupta, Indra

    2013-12-01

    Pulse width modulation (PWM) has been widely used in power converter control. This paper presents a review of architectures of the Digital Pulse Width Modulators (DPWM) targeting digital control of switching DC-DC converters. An attempt is made to review the reported architectures with emphasis on the ASIC and FPGA implementations in single phase and single-output DC-DC converters. Recent architectures using FPGA's advanced resources for achieving the resolution higher than classical methods have also been discussed. The merits and demerits of different architectures, and their relative comparative performance, are also presented. The Authors intention is to uncover the groundwork and the related references through this review for the benefit of readers and researchers targeting different DPWM architectures for the DC-DC converters.

  7. A flexible multi-channel high-resolution time-to-digital converter ASIC

    CERN Document Server

    Mota, M; Debieux, S; Ryzhov, V; Moreira, P; Marchioro, A

    2000-01-01

    A data driven multi-channel Time-to-Digital Converter (TDC) circuit with programmable resolution ( similar to 25ps - 8OOps binning) and a dynamic range of 102.4mus has been implemented in a 0.25mum CMOS technology. An on-chip PLL is used for clock multiplication up to 320MHz from an external 40MHz reference. A 32 element Delay Locked Loop (DLL) performs time interpolation down to 97.5ps. Finally, finer time interpolation is obtained using four samples of the DLL separated by 24.5ps generated by an adjustable on-chip RC delay line. In the lower resolution modes of operation, 32 TDC channels are available. In the highest resolution mode eight channels are available, since four low-resolution channels are used to perform a single fine time interpolation. The TDC is capable of measuring both leading and trailing edges of the input signal. Measurements are initially stored as time stamps in individual four-location deep asynchronous channel buffers. After proper encoding, measurements are written into four 256-dee...

  8. Evaluation of a front-end ASIC for the readout of PMTs over a large dynamic range

    Science.gov (United States)

    Wu, Wei-Hao; Zhao, Lei; Liang, Yu; Yu, Li; Liu, Jian-Feng; Liu, Shu-Bin; An, Qi

    2015-12-01

    The Large High Altitude Air Shower Observatory (LHAASO) project has been proposed for the survey and study of cosmic rays. In the LHAASO project, the Water Cherenkov Detector Array (WCDA) is one of the major detectors for searching for gamma ray sources. A Charge-to-Time Convertor (QTC) ASIC (Application Specification Integrated Circuit), fabricated with Global Foundry 0.35 μm CMOS technology, has been developed for readout of photomultiplier tubes (PMTs) in the WCDA. This ASIC provides both time and charge measurement of PMT signals. The input charge is converted to a pulse width based on the Time-Over-Threshold (TOT) technique and linear discharge method; as for time measurement, leading edge discrimination is employed. This paper focuses on the evaluation of this front-end readout ASIC performance. Test results indicate that the time resolution is better than 400 ps and the charge resolution is better than 1% with large input signals and remains better than 15% @1 photoelectron (P.E.), both beyond the application requirement. Moreover, this ASIC has a weak ambient temperature dependence, low input rate dependence and high channel-to-channel isolation.

  9. ASIC design at Fermilab

    International Nuclear Information System (INIS)

    In the past few years, ASIC (Application Specific Integrated Circuit) design has become important at Fermilab. The purpose of this paper is to present an overview of the in-house ASIC design activity which has taken place. This design effort has added much value to the high energy physics program and physics capability at Fermilab. The two approaches to ASIC development being pursued at Fermilab are examined by looking at some of the types of projects where ASICs are being used or contemplated. To help estimate the cost of future designs, a cost comparison is given to show the relative development and production expenses for these two ASIC approaches. 5 refs., 14 figs., 7 tabs

  10. Sidecar Asic at ESO

    Science.gov (United States)

    Dorn, Reinhold J.; Eschbaumer, Siegfried; Finger, Gert; Ives, Derek; Meyer, Manfred; Stegmeier, Joerg

    2010-07-01

    Teledyne Imaging Sensors (TIS) has developed a CMOS device known as the SIDECAR application-specific integrated circuit (ASIC). This single chip provides all the functionality of FPA drive electronics to operate visible and infrared imaging detectors with a fully digital interface. A Teledyne 2K ×2K silicon PIN diode array hybridized to a Hawaii-2RG multiplexer, the Hybrid Visible Silicon Imager (HyViSI) was read out with the ESO standard IR detector controller IRACE, which delivers detector limited performance. We have tested the H2RG HyViSI detector with the TIS SIDECAR ASIC in 32 channel readout mode at cryogenic temperatures. The SIDECAR has been evaluated down to 105 Kelvin operating temperature and performance results have been compared to those obtained with external electronics. Furthermore ESO has developed its own interface card to replace the JADE USB card provided by Teledyne. The ASIC controller is now being embedded in the ESO standard VLT hard and software environment. This paper provides an update on the recent development of the new ESO ASIC interface card. We find that the SIDECAR ASIC provides performance equal to external electronics.

  11. Memory, microprocessor, and ASIC

    CERN Document Server

    Chen, Wai-Kai

    2003-01-01

    System Timing. ROM/PROM/EPROM. SRAM. Embedded Memory. Flash Memories. Dynamic Random Access Memory. Low-Power Memory Circuits. Timing and Signal Integrity Analysis. Microprocessor Design Verification. Microprocessor Layout Method. Architecture. ASIC Design. Logic Synthesis for Field Programmable Gate Array (EPGA) Technology. Testability Concepts and DFT. ATPG and BIST. CAD Tools for BIST/DFT and Delay Faults.

  12. A Readout ASIC for CZT Detectors

    CERN Document Server

    Jones, L

    2008-01-01

    Spectrometers that can identify the energy of gamma radiation and determine the source isotope have until recently used low temperature semiconductors. These require cooling which makes their portability difficult. The material Cadmium Zinc Telluride (CZT) is now available which operates at room temperature and can be used to measure the energy of gamma radiation. In a compton camera configuration the direction of the radiation can also be determined. A read-out ASIC has been developed for such a system and features 100 channels of electronics, each with a charge amplifier, CR-RC shaper, and peak-hold. A 12 bit ADC converts the data which is sparsified before being read out. The energy, signal rise time, and timestamp of any hit channel is read out together with the data from all of its neighbours. The ASIC has a selectable lower dynamic range which could be used for lower energy interactions.

  13. Evaluation of a front-end ASIC for the readout of PMTs in large dynamic range

    OpenAIRE

    Wu, Weihao; ZHAO Lei; Liang, Yu; Yu, Li; Liu, Jianfeng; Liu, Shubin; An, Qi

    2015-01-01

    The Large High Altitude Air Shower Observatory (LHAASO) project has been proposed for the survey and study of cosmic rays. In the LHAASO project, the Water Cherenkov Detector Array (WCDA) is one of major detectors for searching gamma ray sources. A Charge-to-Time Convertor (QTC) ASIC (Application Specification Integrated Circuit) fabricated in Global Foundry 0.35 {\\mu}m CMOS technology, has been developed for readout of Photomultiplier Tubes (PMTs) in the WCDA. This paper focuses on the evalu...

  14. Prototype of a front-end readout ASIC designed for the Water Cherenkov Detector Array in LHAASO

    International Nuclear Information System (INIS)

    The Large High Altitude Air Shower Observatory is in the R and D phase, in which the Water Cherenkov Detector Array is an important part. The signals of Photo-Multiplier Tubes would vary from single photo electron to 4000 photo electrons, and both high precision charge and time measurement is required. To simplify the signal processing chain, the charge-to-time conversion method is employed. A prototype of the front-end readout ASIC is designed and fabricated in Chartered 0.35 μ m CMOS technology, which integrates time disctrimination and converts the input charge information to pulse widths. With Time-to-Digital Converters, both time and charge can be digitized at the same time. We have conducted initial tests on this chip, and the results indicate that a time resolution better than 0.5 ns is achieved over the full dynamic range (1 ∼ 4000 photo electrons, corresponding to 0.75 ∼ 3000 pC with the threshold of 0.188 pC); the charge resolution is better than 1% with large input amplitudes (500 ∼ 4000 photo electrons), and remains better than 15% with a 1 photo electron input amplitude, which is beyond the application requirement

  15. Evaluation of a front-end ASIC for the readout of PMTs in large dynamic range

    CERN Document Server

    Wu, Weihao; Liang, Yu; Yu, Li; Liu, Jianfeng; Liu, Shubin; An, Qi

    2015-01-01

    The Large High Altitude Air Shower Observatory (LHAASO) project has been proposed for the survey and study of cosmic rays. In the LHAASO project, the Water Cherenkov Detector Array (WCDA) is one of major detectors for searching gamma ray sources. A Charge-to-Time Convertor (QTC) ASIC (Application Specification Integrated Circuit) fabricated in Global Foundry 0.35 {\\mu}m CMOS technology, has been developed for readout of Photomultiplier Tubes (PMTs) in the WCDA. This paper focuses on the evaluation of this front-end readout ASIC performance. Test results indicate that the time resolution is better than 400 ps and the charge resolution is better than 1% with large input signals and remains better than 15% @ 1 Photo Electron (P.E.), both beyond the application requirement. Moreover, this ASIC has a weak ambient temperature dependence, low input rate dependence and high channel-to-channel isolation.

  16. ASIC-enabled High Resolution Optical Time Domain Reflectometer

    Science.gov (United States)

    Skendzic, Sandra

    Fiber optics has become the preferred technology in communication systems because of what it has to offer: high data transmission rates, immunity to electromagnetic interference, and lightweight, flexible cables. An optical time domain reflectometer (OTDR) provides a convenient method of locating and diagnosing faults (e.g. break in a fiber) along a fiber that can obstruct crucial optical pathways. Both the ability to resolve the precise location of the fault and distinguish between two discrete, closely spaced faults are figures of merit. This thesis presents an implementation of a high resolution OTDR through the use of a compact and programmable ASIC (application specific integrated circuit). The integration of many essential OTDR functions on a single chip is advantageous over existing commercial instruments because it enables small, lightweight packaging, and offers low power and cost efficiency. Furthermore, its compactness presents the option of placing multiple ASICs in parallel, which can conceivably ease the characterization of densely populated fiber optic networks. The OTDR ASIC consists of a tunable clock, pattern generator, precise timer, electrical receiver, and signal sampling circuit. During OTDR operation, the chip generates narrow electrical pulse, which can then be converted to optical format when coupled with an external laser diode driver. The ASIC also works with an external photodetector to measure the timing and amplitude of optical reflections in a fiber. It has a 1 cm sampling resolution, which allows for a 2 cm spatial resolution. While this OTDR ASIC has been previously demonstrated for multimode fiber fault diagnostics, this thesis focuses on extending its functionality to single mode fiber. To validate this novel approach to OTDR, this thesis is divided into five chapters: (1) introduction, (2) implementation, (3), performance of ASIC-based OTDR, (4) exploration in optical pre-amplification with a semiconductor optical amplifier, and

  17. The multichannel amplifier/discriminator CMOS ASIC for visual light photon counters

    International Nuclear Information System (INIS)

    The 18-channel CMOS custom monolithic amplifier/discriminator ASIC was designed as a front-end electronics chip for Visual Light Photon Counters which convert photons from scintillation fibre/strip detectors to electrical signals. One ASICs channel contains a charge-sensitive preamplifier, a discriminator to mark the arrival time of signals, and a charge divider to provide analog outputs for analog-to-digital conversion being performed by SVX2. The ASIC is proposed as one of the variants for possible future front-end electronics upgrading the D0 Central Fibre Tracker, Central and Forward Pre-Showers (Fermilab, Batavia, USA)

  18. ASIC design in the KM3NeT detector

    International Nuclear Information System (INIS)

    In the KM3NeT project [1], Cherenkov light from the muon interactions with transparent matter around the detector, is used to detect neutrinos. Photo multiplier tubes (PMT) used as photon sensor, are housed in a glass sphere (aka Optical Module) to detect single photons from the Cherenkov light. The PMT needs high operational voltage ( ∼ 1.5 kV) and is generated by a Cockroft-Walton (CW) multiplier circuit. The electronics required to control the PMT's and collect the signals is integrated in two ASIC's namely: 1) a front-end mixed signal ASIC (PROMiS) for the readout of the PMT and 2) an analog ASIC (CoCo) to generate pulses for charging the CW circuit and to control the feedback of the CW circuit. In this article, we discuss the two integrated circuits and test results of the complete setup. PROMiS amplifies the input charge, converts it to a pulse width and delivers the information via LVDS signals. These LVDS signals carry accurate information on the Time of arrival ( 2C bus. This unique combination of the ASIC's results in a very cost and power efficient PMT base design.

  19. Characterisation of the NA62 GigaTracker end of column readout ASIC

    CERN Document Server

    Noy, M; Perktold, L; Rinella, G A; Riedler, P; Morel, M; Kluge, A; Kaplon, J; Martin, E; Jarron, P

    2011-01-01

    The architecture and characterisation of the End Of Column demonstrator readout ASIC for the NA62 GigaTracker hybrid pixel detector is presented. This ASIC serves as a proof of principle for a pixel chip with 1800 pixels which must perform time stamping to better than 200 ps (RMS), provide 300 mu m pitch position information and operate with a dead-time of 1\\% or less for 800 MHz-1 GHz beam rate. The demonstrator ASIC comprises a full test column with 45 pixels alongside other test structures. The timewalk correction mechanism employed is measurement of the time-over-threshold, coupled with an off-detector look-up table. The time to digital converter is a delay locked loop with 32 contributing delay cells fed with a 320 MHz to yield a nominal bin size of 97 ps. Recently, P-in-N sensors have been bump-bonded to the ASIC and characterisation of these assemblies has begun.

  20. Noise evaluation of a MOSFET for an ASIC (Contract research)

    International Nuclear Information System (INIS)

    In two-dimensional position sensitive (2-D) neutron detectors used for neutron scattering experiments in the J-PARC, it is required that very small pulse signals consisted of several hundred channels should be measured with discriminating form noises and gamma ray signals and converted from analogue to digital signals in real time. To establish performances of neutron detectors such as fast response and a very small spatial resolution, multi-channel small signals should be measured and the signal processing should be carried out with high S/N ratios. For development of multi-channel electronics with fast response and very low noise, manufacture of an application specific integrated circuits (ASICs) with high performances is indispensable for the 2-D neutron detectors. Therefore, MOSFETs with high gm and low noise required for the ASIC were designed and the noise performances were studied and estimated. (author)

  1. Rad-Hard Structured ASIC Body of Knowledge

    Science.gov (United States)

    Heidecker, Jason

    2013-01-01

    Structured Application-Specific Integrated Circuit (ASIC) technology is a platform between traditional ASICs and Field-Programmable Gate Arrays (FPGA). The motivation behind structured ASICs is to combine the low nonrecurring engineering costs (NRE) costs of FPGAs with the high performance of ASICs. This report provides an overview of the structured ASIC platforms that are radiation-hardened and intended for space application

  2. Acid-Sensing Ion Channel 2a (ASIC2a) Promotes Surface Trafficking of ASIC2b via Heteromeric Assembly.

    Science.gov (United States)

    Kweon, Hae-Jin; Kim, Dong-Il; Bae, Yeonju; Park, Jae-Yong; Suh, Byung-Chang

    2016-01-01

    Acid-sensing ion channels (ASICs) are proton-activated cation channels that play important roles as typical proton sensors during pathophysiological conditions and normal synaptic activities. Among the ASIC subunits, ASIC2a and ASIC2b are alternative splicing products from the same gene, ACCN1. It has been shown that ASIC2 isoforms have differential subcellular distribution: ASIC2a targets the cell surface by itself, while ASIC2b resides in the ER. However, the underlying mechanism for this differential subcellular localization remained to be further elucidated. By constructing ASIC2 chimeras, we found that the first transmembrane (TM1) domain and the proximal post-TM1 domain (17 amino acids) of ASIC2a are critical for membrane targeting of the proteins. We also observed that replacement of corresponding residues in ASIC2b by those of ASIC2a conferred proton-sensitivity as well as surface expression to ASIC2b. We finally confirmed that ASIC2b is delivered to the cell surface from the ER by forming heteromers with ASIC2a, and that the N-terminal region of ASIC2a is additionally required for the ASIC2a-dependent membrane targeting of ASIC2b. Together, our study supports an important role of ASIC2a in membrane targeting of ASIC2b. PMID:27477936

  3. Development of a low-noise analog front-end ASIC for APD-PET detectors

    International Nuclear Information System (INIS)

    We report on the development of a front-end ASIC for high spatial resolution PET detectors with time-of-flight capability based on LYSO scintillator arrays coupled with position-sensitive avalanche photodiode (APD) arrays. The ASIC is designed based on the open-IP LSI project led by JAXA and realized in TSMC 0.35-μm CMOS technology. It consists of an 8-channel charge-sensitive amplifier, band-pass filters, differentiators, pulse-height and timing discriminators, and two-channel time-to-amplitude converters. As a result, energy resolution of 9.7% (FWHM) is obtained at 511 keV, with a time resolution below 970 ps (σ). We will also report on the current status of developing a second-version ASIC designed to have 32-channel analog circuits with improved time resolution.

  4. Driver ASICs for Advanced Deformable Mirrors Project

    Data.gov (United States)

    National Aeronautics and Space Administration — The program leverages on our extensive expertise in developing high-performance driver ASICs for deformable mirror systems and seeks to expand the capacities of the...

  5. VMM - An ASIC for Micropattern Detectors

    CERN Document Server

    Iakovidis, Georgios; The ATLAS collaboration; De Geronimo, Gianluigi

    2015-01-01

    The VMM is an ASIC that can be used in a variety of tracking detectors. It is designed to be used with resistive Micromegas and sTGC detectors in the New Small Wheel upgrade of the ATLAS Muon spectrometer. The ASIC is fabricated in the 130nm 1.2V 8‐metal CMOS technology from IBM. The ASIC integrates 64 channels, each providing charge amplification, discrimination, neighbour logic, amplitude and timing measurements, analog-to-digital conversions, and either direct output for trigger or multiplexed readout. The front-end amplifier can operate with a wide range of input capacitances, has adjustable polarity, gain and peaking time. The VMM2 is the second version of the VMM ASIC family fabricated in 2014. It was tested with resistive Micromegas prototypes in the 2015 test beam campaigns at CERN. The specification and performance of the VMM2 will be presented as well as the Micromegas detector performance with the VMM2.

  6. Driver ASICs for Advanced Deformable Mirrors Project

    Data.gov (United States)

    National Aeronautics and Space Administration — The overall goal of the SBIR program is to develop a new Application Specified Integrated Circuit (ASIC) driver to be used in driver electronics of a deformable...

  7. ASIC life extension through hardware patch interfaces

    OpenAIRE

    Bryksin, Vladyslav Sergeevich

    2009-01-01

    Specialized processor designs and ASICs offer lower power consumption and greater efficiency compared to general purpose processors. However, the drawback of specialized hardware designs is the reduction in the generality of workloads that they are able to handle. An important characteristic of specialized hardware designs is the inability to manage changes in the underlying applications. This thesis describes and analyzes the concept of ASIC patching in the Arsenal design: a mechanism to mit...

  8. NIRCA ASIC for the readout of focal plane arrays

    Science.gov (United States)

    Pâhlsson, Philip; Steenari, David; Øya, Petter; Otnes Berge, Hans Kristian; Meier, Dirk; Olsen, Alf; Hasanbegovic, Amir; Altan, Mehmet A.; Najafiuchevler, Bahram; Talebi, Jahanzad; Azman, Suleyman; Gheorghe, Codin; Ackermann, Jörg; Mæhlum, Gunnar; Johansen, Tor Magnus; Stein, Timo

    2016-05-01

    This work is a continuation of our preliminary tests on NIRCA - the Near Infrared Readout and Controller ASIC [1]. The primary application for NIRCA is future astronomical science and Earth observation missions where NIRCA will be used with mercury cadmium telluride image sensors (HgCdTe, or MCT) [2], [3]. Recently we have completed the ASIC tests in the cryogenic environment down to 77 K. We have verified that NIRCA provides to the readout integrated circuit (ROIC) regulated power, bias voltages, and fully programmable digital sequences with sample control of the analogue to digital converters (ADC). Both analog and digital output from the ROIC can be acquired and image data is 8b/10bencoded and delivered via serial interface. The NIRCA also provides temperature measurement, and monitors several analog and digital input channels. The preliminary work confirms that NIRCA is latch-up immune and able to operate down to 77 K. We have tested the performance of the 12-bit ADC with pre-amplifier to have 10.8 equivalent number of bits (ENOB) at 1.4 Msps and maximum sampling speed at 2 Msps. The 1.8-V and 3.3-V output regulators and the 10-bit DACs show good linearity and work as expected. A programmable sequencer is implemented as a micro-controller with a custom instruction set. Here we describe the special operations of the sequencer with regards to the applications and a novel approach to parallel real-time hardware outputs. The test results of the working prototype ASIC show good functionality and performance from room temperature down to 77 K. The versatility of the chip makes the architecture a possible candidate for other research areas, defense or industrial applications that require analog and digital acquisition, voltage regulation, and digital signal generation.

  9. Preliminary validation results of an ASIC for the readout and control of near-infrared large array detectors

    Science.gov (United States)

    Pâhlsson, Philip; Meier, Dirk; Otnes Berge, Hans Kristian; Øya, Petter; Steenari, David; Olsen, Alf; Hasanbegovic, Amir; Altan, Mehmet A.; Najafiuchevler, Bahram; Talebi, Jahanzad; Azman, Suleyman; Gheorghe, Codin; Ackermann, Jörg; Mæhlum, Gunnar

    2015-06-01

    In this paper we present initial test results of the Near Infrared Readout and Controller ASIC (NIRCA), designed for large area image sensors under contract from the European Space Agency (ESA) and the Norwegian Space Center. The ASIC is designed to read out image sensors based on mercury cadmium telluride (HgCdTe, or MCT) operating down to 77 K. IDEAS has developed, designed and initiated testing of NIRCA with promising results, showing complete functionality of all ASIC sub-components. The ASIC generates programmable digital signals to clock out the contents of an image array and to amplify, digitize and transfer the resulting pixel charge. The digital signals can be programmed into the ASIC during run-time and allows for windowing and custom readout schemes. The clocked out voltages are amplified by programmable gain amplifiers and digitized by 12-bit, 3-Msps successive approximation register (SAR) analogue-to-digital converters (ADC). Digitized data is encoded using 8-bit to 10-bit encoding and transferred over LVDS to the readout system. The ASIC will give European researchers access to high spectral sensitivity, very low noise and radiation hardened readout electronics for astronomy and Earth observation missions operating at 77 K and room temperature. The versatility of the chip makes the architecture a possible candidate for other research areas, or defense or industrial applications that require analog and digital acquisition, voltage regulation, and digital signal generation.

  10. Development of an ASIC for the readout and control of near-infrared large array detectors

    Science.gov (United States)

    Meier, Dirk; Berge, Hans Kristian Otnes; Hasanbegovic, Amir; Altan, Mehmet A.; Najafiuchevler, Bahram; Azman, Suleyman; Talebi, Jahanzad; Olsen, Alf; Øya, Petter; Paahlsson, Philip; Gheorghe, Codin; Maehlum, Gunnar

    2014-07-01

    The article describes the near infrared readout and controller ASIC (NIRCA) developed by Integrated Detector Electronics AS (IDEAS). The project aims at future astronomical science and Earth observation missions, where the ASIC will be used with image sensors based on mercury cadmium telluride (HgCdTe, or MCT). NIRCA is designed to operate from cryogenic temperatures (77 K) to higher than room temperature (328 K) and in a high radiation environment (LET > 60 MeVcm2/mg). The ASIC connects to the readout integrated circuit (ROIC) and delivers fully digitized data via serial digital output. The ASIC contains an analogue front-end (AFE) with 4 analogue-to-digital converters (ADCs) and programmable gain amplifiers with offset adjustment. The ADCs have a differential input swing of +/-2 V, 12-bit resolution, and a maximum sample rate of 3 MSps. The ASIC contains a programmable sequencer (microcontroller) to generate up to 40 digital signals for the ROIC and to control the analogue front-end and DACs on the chip. The ASIC has two power supply voltage regulators that provide the ROIC with 1.8 V and 3.3 V, and programmable 10-bit DACs to generate 16 independent reference and bias voltages from 0.3 V to 3 V. In addition NIRCA allows one to read 8 external digital signals, and monitor external and internal analogue signals including onchip temperature. NIRCA can be programmed and controlled via SPI interface for all internal functions and allows data forwarding from and to the ROIC SPI interface.

  11. A wireless capsule system with ASIC for monitoring the physiological signals of the human gastrointestinal tract.

    Science.gov (United States)

    Xu, Fei; Yan, Guozheng; Zhao, Kai; Lu, Li; Gao, Jinyang; Liu, Gang

    2014-12-01

    This paper presents the design of a wireless capsule system for monitoring the physiological signals of the human gastrointestinal (GI) tract. The primary components of the system include a wireless capsule, a portable data recorder, and a workstation. Temperature, pH, and pressure sensors; an RF transceiver; a controlling and processing application specific integrated circuit (ASIC); and batteries were applied in a wireless capsule. Decreasing capsule size, improving sensor precision, and reducing power needs were the primary challenges; these were resolved by employing micro sensors, optimized architecture, and an ASIC design that include power management, clock management, a programmable gain amplifier (PGA), an A/D converter (ADC), and a serial peripheral interface (SPI) communication unit. The ASIC has been fabricated in 0.18- μm CMOS technology with a die area of 5.0 mm × 5.0 mm. The wireless capsule integrating the ASIC controller measures Φ 11 mm × 26 mm. A data recorder and a workstation were developed, and 20 cases of human experiments were conducted in hospitals. Preprocessing in the workstation can significantly improve the quality of the data, and 76 original features were determined by mathematical statistics. Based on the 13 optimal features achieved in the evaluation of the features, the clustering algorithm can identify the patients who lack GI motility with a recognition rate reaching 83.3%. PMID:25608285

  12. ASIC For Complex Fixed-Point Arithmetic

    Science.gov (United States)

    Petilli, Stephen G.; Grimm, Michael J.; Olson, Erlend M.

    1995-01-01

    Application-specific integrated circuit (ASIC) performs 24-bit, fixed-point arithmetic operations on arrays of complex-valued input data. High-performance, wide-band arithmetic logic unit (ALU) designed for use in computing fast Fourier transforms (FFTs) and for performing ditigal filtering functions. Other applications include general computations involved in analysis of spectra and digital signal processing.

  13. An analogue front-end ASIC prototype designed for PMT signal readout

    Science.gov (United States)

    Liu, Jian-Feng; Zhao, Lei; Yu, Li; Liang, Yu; Qin, Jia-Jun; Yang, Yun-Fan; Wu, Wei-Hao; Liu, Shu-Bin; An, Qi

    2016-06-01

    The Water Cherenkov Detector Array (WCDA) is one of the core detectors in the Large High Altitude Air Shower Observatory (LHAASO), and it consists of 3600 photomultiplier tubes (PMTs). Both high resolution time and charge measurement are required over a large dynamic range from 1 photoelectron (P.E.) to 4000 P.E. The prototype of an analogue front-end Application Specific Integrated Circuit (ASIC) fabricated using Global Foundry 0.35 μm CMOS technology is designed to read out the PMT signal in the WCDA. This ASIC employs leading edge discrimination and an (RC)4 shaping structure. Combined with the following Time-to-Digital Converter (TDC) and Analog-to-Digital Converter (ADC), both the arrival time and charge of the PMT signal can be measured. Initial test results indicate that time resolution is better than 350 ps and charge resolution is better than 10% at 1 P.E. and better than 1% with large input signals (300 P.E. to 4000 P.E.). Besides, this ASIC has a good channel-to-channel isolation of more than 84 dB and the temperature dependency of charge measurement is less than 5% in the range 0–50°C. Supported by Knowledge Innovation Program of Chinese Academy of Sciences (KJCX2-YW-N27), National Natural Science Foundation of China (11175174) and CAS Center for Excellence in Particle Physics (CCEPP)

  14. Abnormal cardiac autonomic regulation in mice lacking ASIC3.

    Science.gov (United States)

    Cheng, Ching-Feng; Kuo, Terry B J; Chen, Wei-Nan; Lin, Chao-Chieh; Chen, Chih-Cheng

    2014-01-01

    Integration of sympathetic and parasympathetic outflow is essential in maintaining normal cardiac autonomic function. Recent studies demonstrate that acid-sensing ion channel 3 (ASIC3) is a sensitive acid sensor for cardiac ischemia and prolonged mild acidification can open ASIC3 and evoke a sustained inward current that fires action potentials in cardiac sensory neurons. However, the physiological role of ASIC3 in cardiac autonomic regulation is not known. In this study, we elucidate the role of ASIC3 in cardiac autonomic function using Asic3(-/-) mice. Asic3(-/-) mice showed normal baseline heart rate and lower blood pressure as compared with their wild-type littermates. Heart rate variability analyses revealed imbalanced autonomic regulation, with decreased sympathetic function. Furthermore, Asic3(-/-) mice demonstrated a blunted response to isoproterenol-induced cardiac tachycardia and prolonged duration to recover to baseline heart rate. Moreover, quantitative RT-PCR analysis of gene expression in sensory ganglia and heart revealed that no gene compensation for muscarinic acetylcholines receptors and beta-adrenalin receptors were found in Asic3(-/-) mice. In summary, we unraveled an important role of ASIC3 in regulating cardiac autonomic function, whereby loss of ASIC3 alters the normal physiological response to ischemic stimuli, which reveals new implications for therapy in autonomic nervous system-related cardiovascular diseases. PMID:24804235

  15. Abnormal Cardiac Autonomic Regulation in Mice Lacking ASIC3

    Directory of Open Access Journals (Sweden)

    Ching-Feng Cheng

    2014-01-01

    Full Text Available Integration of sympathetic and parasympathetic outflow is essential in maintaining normal cardiac autonomic function. Recent studies demonstrate that acid-sensing ion channel 3 (ASIC3 is a sensitive acid sensor for cardiac ischemia and prolonged mild acidification can open ASIC3 and evoke a sustained inward current that fires action potentials in cardiac sensory neurons. However, the physiological role of ASIC3 in cardiac autonomic regulation is not known. In this study, we elucidate the role of ASIC3 in cardiac autonomic function using Asic3−/− mice. Asic3−/− mice showed normal baseline heart rate and lower blood pressure as compared with their wild-type littermates. Heart rate variability analyses revealed imbalanced autonomic regulation, with decreased sympathetic function. Furthermore, Asic3−/− mice demonstrated a blunted response to isoproterenol-induced cardiac tachycardia and prolonged duration to recover to baseline heart rate. Moreover, quantitative RT-PCR analysis of gene expression in sensory ganglia and heart revealed that no gene compensation for muscarinic acetylcholines receptors and beta-adrenalin receptors were found in Asic3−/− mice. In summary, we unraveled an important role of ASIC3 in regulating cardiac autonomic function, whereby loss of ASIC3 alters the normal physiological response to ischemic stimuli, which reveals new implications for therapy in autonomic nervous system-related cardiovascular diseases.

  16. Latest generation of ASICs for photodetector readout

    Energy Technology Data Exchange (ETDEWEB)

    Seguin-Moreau, N., E-mail: seguin@lal.in2p3.fr [Laboratoire de l’Accélérateur Linéaire, IN2P3-CNRS, Université Paris-Sud, Bâtiment 200, 91898 Orsay Cedex (France)

    2013-08-01

    The OMEGA microelectronics group has designed a new generation of multichannel integrated circuits, the “ROC” family, in AustrianMicroSystem (AMS) SiGe 0.35 μm technology to read out signals from various families of photodetectors. The chip named MAROC (standing for Multi Anode ReadOut Chip) has been designed to read out MultiAnode Photomultipliers (MAPMT), Photomultiplier ARray In SiGe ReadOut Chip (PARISROC) to read out Photomultipliers (PMTs) and SiPM Integrated ReadOut Chip (SPIROC) to readout Silicon PhotoMultiplier (SiPM) detectors and which was the first ASIC to do so. The three of them fulfill the stringent requirements of the future photodetectors, in particular in terms of low noise, radiation hardness, large dynamic range, high density and high speed while keeping low power thanks to the SiGe technology. These multi-channel ASICs are real System on Chip (SoC) as they provide charge, time and photon-counting information which are digitized internally. Their complexity and versatility enable innovative frontier detectors and also cover spin off of these detectors in adjacent fields such as medical or material imaging as well as smart detectors. In this presentation, the three ASIC architectures and test results will be described to give a general panorama of the “ROC” chips.

  17. Latest generation of ASICs for photodetector readout

    Science.gov (United States)

    Seguin-Moreau, N.

    2013-08-01

    The OMEGA microelectronics group has designed a new generation of multichannel integrated circuits, the "ROC" family, in AustrianMicroSystem (AMS) SiGe 0.35 μm technology to read out signals from various families of photodetectors. The chip named MAROC (standing for Multi Anode ReadOut Chip) has been designed to read out MultiAnode Photomultipliers (MAPMT), Photomultiplier ARray In SiGe ReadOut Chip (PARISROC) to read out Photomultipliers (PMTs) and SiPM Integrated ReadOut Chip (SPIROC) to readout Silicon PhotoMultiplier (SiPM) detectors and which was the first ASIC to do so. The three of them fulfill the stringent requirements of the future photodetectors, in particular in terms of low noise, radiation hardness, large dynamic range, high density and high speed while keeping low power thanks to the SiGe technology. These multi-channel ASICs are real System on Chip (SoC) as they provide charge, time and photon-counting information which are digitized internally. Their complexity and versatility enable innovative frontier detectors and also cover spin off of these detectors in adjacent fields such as medical or material imaging as well as smart detectors. In this presentation, the three ASIC architectures and test results will be described to give a general panorama of the "ROC" chips.

  18. VMM - An ASIC for Micropattern Detectors

    CERN Document Server

    Iakovidis, Georgios; The ATLAS collaboration; De Geronimo, Gianluigi

    2015-01-01

    The VMM is a custom Application Specific Integrated Circuit (ASIC) that can be used in a va- riety of charge interpolated tracking detectors. It is designed to be used with the resistive Micromegas and sTGC detectors in the New Small Wheel upgrade of the ATLAS Muon spectrometer. The ASIC is designed at Brookhaven National Laboratory and fabricated in the 130 nm Global Foundries 8RF-DM process. The devices will be packaged in a Ball Grid Array with outline dimensions of 21 × 21 mm2 . It integrates 64 channels, each providing charge amplification, discrimination, neighbour logic, amplitude and timing measurements, analog- to-digital conversions, and either direct output for trigger or multiplexed readout. The front-end amplifier can operate with a wide range of input capacitances, has adjustable polarity, gain and peaking time. The VMM2 is the second version of the VMM ASIC family fabricated in 2014. The design, tests and qualification of the VMM1, VMM2 and roadmap to VMM3 is described.

  19. Latest generation of ASICs for photodetector readout

    International Nuclear Information System (INIS)

    The OMEGA microelectronics group has designed a new generation of multichannel integrated circuits, the “ROC” family, in AustrianMicroSystem (AMS) SiGe 0.35 μm technology to read out signals from various families of photodetectors. The chip named MAROC (standing for Multi Anode ReadOut Chip) has been designed to read out MultiAnode Photomultipliers (MAPMT), Photomultiplier ARray In SiGe ReadOut Chip (PARISROC) to read out Photomultipliers (PMTs) and SiPM Integrated ReadOut Chip (SPIROC) to readout Silicon PhotoMultiplier (SiPM) detectors and which was the first ASIC to do so. The three of them fulfill the stringent requirements of the future photodetectors, in particular in terms of low noise, radiation hardness, large dynamic range, high density and high speed while keeping low power thanks to the SiGe technology. These multi-channel ASICs are real System on Chip (SoC) as they provide charge, time and photon-counting information which are digitized internally. Their complexity and versatility enable innovative frontier detectors and also cover spin off of these detectors in adjacent fields such as medical or material imaging as well as smart detectors. In this presentation, the three ASIC architectures and test results will be described to give a general panorama of the “ROC” chips

  20. Configurable Radiation Hardened High Speed Isolated Interface ASIC Project

    Data.gov (United States)

    National Aeronautics and Space Administration — NVE Corporation will design and build an innovative, low cost, flexible, configurable, radiation hardened, galvanically isolated, interface ASIC chip set that will...

  1. PARISROC, an autonomous front-end ASIC for triggerless acquisition in next generation neutrino experiments

    International Nuclear Information System (INIS)

    PARISROC (Photomultiplier ARray Integrated in SiGe ReadOut Chip) is a complete readout chip in AustriaMicroSystems (AMS) SiGe 0.35 μm technology designed to read array of 16 Photomultipliers (PMTs). The ASIC is realized in the context of the PMm2 (square meter PhotoMultiplier) project that has proposed a new system of “smart photo-detectors” composed by sensor and read-out electronics dedicated to next generation neutrino experiments. The future water Cherenkov detectors will take place in megaton size water tanks then with a large surface of photo-detection. We propose to segment the large surface in arrays with a single front-end electronics and only the useful data send in surface to be stocked and analyzed. This paper describes the second version of the ASIC and illustrates the chip principle of operation and the main characteristics thank to a series of measurements. It is a 16-channel ASIC with channels that work independently, in triggerless mode and all managed by a common digital part. Then main innovation is that all the channels are handled independently by the digital part so that only channels that have triggered are digitized. Then the data are transferred to the internal memory and sent out in a data driven way. The ASIC allows charge and time measurement. We measured a charge measurement range starting from 160 fC (1 photoelectron-p.e., at PMT gain of 106) to 100 pC (around 600 p.e.) at 1% of linearity; time tagging at 1 ns thanks to a 24-bit counter at 10 MHz and a Time to Digital Converter (TDC) on a 100 ns ramp.

  2. Smart Sensor ASIC for Nuclear Power Monitoring

    International Nuclear Information System (INIS)

    Mixed-signal integrated circuits are used in a variety of applications where ionizing radiation is present, including satellites, space vehicles, nuclear reactor monitoring, medical imaging, and cancer therapy. While total ionizing radiation is present in each of these environments, the type of radiation (e.g. heavy ions vs. high-energy x-rays) and other environmental factors present unique challenges to the mixed-signal designer. This paper discusses a Smart Sensor radiation hardened, mixed-signal, application specific integrated circuit (ASIC) specifically designed for sensor monitoring in a nuclear reactor environment. Results after exposure to gamma rays, neutrons, and temperatures up to 200 deg. C are reported. (authors)

  3. A 64ch readout module for PPD/MPPC/SiPM using EASIROC ASIC

    Energy Technology Data Exchange (ETDEWEB)

    Nakamura, Isamu, E-mail: isamu.nakamura@kek.jp [KEK, 1-1 Oho Tsukuba 305-0801 (Japan); Ishijima, N.; Hanagaki, K. [Osaka University, 1-1 Machikaneyama, Toyonaka, Osaka 560-0043 (Japan); Yoshimura, K. [Okayama University, 1-1 Tsushimanaka, Kita-ku, Okayama 700-8530 (Japan); Nakai, Y. [Kyushu University, 6-10-1 Hakozaki, Higashi-ku, Fukuoka 812-8581 (Japan); Ueno, K. [KEK, 1-1 Oho Tsukuba 305-0801 (Japan)

    2015-07-01

    A readout module for PPD/MPPC/GAPD/SiPM is developed using EASIROC ASIC. The module can handle 64 PPDs and has on-board bias power supply, ADC for energy measurement, 1 ns TDC on FPGA as well as 64ch Logic output for external trigger. Controls and data transfer are through SiTCP technology implemented in FPGA. The module has NIM format for convenience, but can be operated without crate with 5 V AC/DC converter. Basic performance of production module was tested and the results are presented in the poster.

  4. ASIC Design and Implementation for Digital Pulse Compression Chip

    Institute of Scientific and Technical Information of China (English)

    高俊峰; 韩月秋; 王巍

    2004-01-01

    A novel ASIC design of changeable-point digital pulse compression (DPC) chip is presented. System hardware resource is reduced to one third of the traditional design method through operations sharing hardware, i.e. let FFT, complex multiplication and IFFT be fulfilled with the same hardware structure. Block-floating-point scaling is used to enhance the dynamic range and computation accuracy. This design applies parallel pipeline structure and the radix-4 butterfly operation to improve the processing speed. In addition, a triple-memory-space(TMS) configuration is used that allows input, computation and output operations to be overlapped, so that the dual-butterfly unit is never left in an idle state waiting for I/O operation. The whole design is implemented with only one chip of XC2V500-5 FPGA. It can implement 1 024-point DPC within 91.6 μs.The output data is converted to floating-point formation to achieve seamless interface with TMS320C6701. The validity of the design is verified by simulation and measurement results.

  5. Indigenous design and development of digital ASICs

    International Nuclear Information System (INIS)

    FPGAs and CPLDs were extensively used for the design and development of Instrumentation and Control systems including safety systems of Prototype Fast Breeder Reactor (PFBR). The developed I and C systems have been tested extensively for their functionality and also undergone various qualification tests. Some of these I and C systems have also been deployed in Fast Breeder Test Reactor. The performance of these designs is found to be satisfactory. However FPGAs/CPLDs are rapidly evolving and the devices become obsolete in a short span of time (typically about 5 to 8 years), whereas reactor's life time is typically about 40 years. This obsolescence problem can be handled in different ways. This paper discusses design and fabrication of digital ASICs as one of the alternate for handling obsolescence problems. Aim of this development work is to establish complete digital ASIC design, fabrication and testing flow, so that the same can be used in some of the critical/strategic requirements. (author)

  6. READ - Remote Analog ASIC Design System

    Directory of Open Access Journals (Sweden)

    Michael E. Auer

    2006-11-01

    Full Text Available The scope of this work is to present a solution to implement a remote electronic laboratory for testing and designing analog ASICs (ispPAC10. The application allows users to create circuit schematics, upload the design to the device and perform measurements. The software used for designing circuits is the PAC-Designer and it runs on a Citrix server. The signals are generated and the responses are acquired by a data acquisition board controlled by LabView. The virtual instruments interact with some ActiveX controls specially designed to look like real oscilloscope and function generator devices and represent the user interface of the lab. These ActiveX give users the control over the LabView VIs and the access to its facilities in order to perform electronic exercises.

  7. VHiSSI: Experimental Spacefibre Asic

    Science.gov (United States)

    Gonzalez Villafranca, Alberto; Ferrer, Albert; McLaren, David; McClements, Chris; Parkes, Steve

    2015-09-01

    SpaceFibreis the next generation data link and network technology being developed by University of Dundee for the European Space Agency. This high-speed technology runs over both copper and fibre optic cables and is backwards compatible with the ubiquitous SpaceWire technology. SpaceFibre provides 12 times the throughput of a SpW link (2.5 Gbps) with current flight qualified technology together with inbuilt QoS and FDIR capabilities. This paper details the first implementation of SpaceFibre in a radiation tolerant device in the frame of the VHiSSI project. The functionality of this ASIC chip is explained and the results of the functional and Total Ionising Dose and Single Event Effect radiation testing are detailed.

  8. An Analogue Front-End ASIC Prototype Designed For PMT Signal Readout

    CERN Document Server

    Liu, Jianfeng; Yu, Li; Liang, Yu; Qin, Jiajun; Yang, Yunfang; Wu, Weihao; Liu, Shubin; An, Qi

    2015-01-01

    The Large High Altitude Air Shower Observatory (LHAASO) is designed for high energy gamma ray and cosmic ray detection. A Water Cherenkov Detector Array which is sensitive to gamma ray showers above a few hundred GeV is proposed to survey gamma ray sources. The WCDA consists of 3600 PhotoMultiplier Tubes (PMT) which collect the Cherenkov light produced by the shower particles in water. Both high precision time and charge measurement are required over a large dynamic range from 1 photo electron (P.E.) to 4000 P.E. Prototype of an analogue front-end Application Specific Integrated Circuit (ASIC) fabricated in Chartered 0.35 {\\mu}m CMOS technology is designed to read out PMT signal in the WCDA. This ASIC employs leading edge discrimination and RC4 shaping structure; combined with the following Time-to-Digital Converter (TDC) and Analog-to-Digital Converter (ADC), both the arrival time and charge of the PMT signal can be measured. Initial test results indicate that time resolution is better than 350 ps and charge...

  9. The 'KATOD-1' strip readout ASIC for cathode strip chamber

    International Nuclear Information System (INIS)

    The 'KATOD-1', a 16-channels readout ASIC, has been designed to perform tests of P3 and P4 full-scale prototypes of the cathode strip chamber for the ME1/1 forward muon station of the Compact Muon Solenoid (CMS) experiment. The ASIC channel consists of two charge-sensitive preamplifiers, a three-stage shaper with cancellation, and an output driver. The ASIC is instrumented with control of gain, in the range of (-4.2 : +5.0) mV/fC, and control of output pulse-shape. The equivalent input noise is equal to 2400 e with the slope of 12 e/pF for detector capacity up to 200 pF. The peaking time is 100 ns for the chamber signal. The ASIC has been produced by a microwave Bi-jFET technology

  10. Low-power Cross-Correlator ASIC Project

    Data.gov (United States)

    National Aeronautics and Space Administration — Pacific MicroCHIP Corporation offers to design an ASIC that includes a cross-correlation unit together with the interfaces to be connected to the output of the...

  11. Extreme Temperature, Rad-Hard Power Management ASIC Project

    Data.gov (United States)

    National Aeronautics and Space Administration — Ridgetop Group will design a rad-hard Application Specific Integrated Circuit (ASIC) for spacecraft power management that is functional over a temperature range of...

  12. Automated Solution for Data Monitoring (Dashboard) of ASIC Design Flow

    OpenAIRE

    Kariyappa B S1 , Aravind2 , Dhananjaya A3 , Vineet Puri

    2013-01-01

    Application Specific Integrated Circuit (ASIC) design flow consists of several steps involved with Electronic Design Automation (EDA) tools. For an ASIC designer it is very important to know the status of design development. Finding the status of the actual design is currently a manual work. It is difficult to track the status and error information using log/report files generated by the tool at different stages of design flow. Therefore it is necessary to develop an automated tool to solve t...

  13. Monolithic Active Pixel Matrix with Binary Counters (MAMBO) ASIC

    Energy Technology Data Exchange (ETDEWEB)

    Khalid, Farah F.; Deptuch, Grzegorz; Shenai, Alpana; Yarema, Raymond J.; /Fermilab

    2010-11-01

    Monolithic Active Matrix with Binary Counters (MAMBO) is a counting ASIC designed for detecting and measuring low energy X-rays from 6-12 keV. Each pixel contains analogue functionality implemented with a charge preamplifier, CR-RC{sup 2} shaper and a baseline restorer. It also contains a window comparator which can be trimmed by 4 bit DACs to remove systematic offsets. The hits are registered by a 12 bit ripple counter which is reconfigured as a shift register to serially output the data from the entire ASIC. Each pixel can be tested individually. Two diverse approaches have been used to prevent coupling between the detector and electronics in MAMBO III and MAMBO IV. MAMBO III is a 3D ASIC, the bottom ASIC consists of diodes which are connected to the top ASIC using {mu}-bump bonds. The detector is decoupled from the electronics by physically separating them on two tiers and using several metal layers as a shield. MAMBO IV is a monolithic structure which uses a nested well approach to isolate the detector from the electronics. The ASICs are being fabricated using the SOI 0.2 {micro}m OKI process, MAMBO III is 3D bonded at T-Micro and MAMBO IV nested well structure was developed in collaboration between OKI and Fermilab.

  14. Development of an ASIC for Si/CdTe detectors in a radioactive substance visualizing system

    International Nuclear Information System (INIS)

    We report on the recent development of a 64-channel analog front-end ASIC for a new gamma-ray imaging system designed to visualize radioactive substances. The imaging system employs a novel Compton camera which consists of silicon (Si) and cadmium telluride (CdTe) detectors. The ASIC is intended for the readout of pixel/pad detectors utilizing Si/CdTe as detector materials, and covers a dynamic range up to 1.4 MeV. The readout chip consists of 64 identical signal channels and was implemented with X-FAB 0.35μm CMOS technology. Each channel contains a charge-sensitive amplifier, a pole-zero cancellation circuit, a low-pass filter, a comparator, and a sample-hold circuit, along with a Wilkinson-type A-to-D converter. We observed an equivalent noise charge of ∼500 e− and a noise slope of ∼5 e−/pF (r.m.s.) with a power consumption of 2.1 mW per channel. The chip works well when connected to Schottky CdTe diodes, and delivers spectra with good energy resolution, such as ∼12 keV (FWHM) at 662 keV and ∼24 keV (FWHM) at 1.33 MeV

  15. Design and characterization of the ePix10k: a high dynamic range integrating pixel ASIC for LCLS detectors

    Science.gov (United States)

    Caragiulo, P.; Dragone, A.; Markovic, B.; Herbst, R.; Nishimura, K.; Reese, B.; Herrmann, S.; Hart, P.; Blaj, G.; Segal, J.; Tomada, A.; Hasi, J.; Carini, G.; Kenney, C.; Haller, G.

    2015-05-01

    ePix10k is a variant of a novel class of integrating pixel ASICs architectures optimized for the processing of signals in second generation LINAC Coherent Light Source (LCLS) X-Ray cameras. The ASIC is optimized for high dynamic range application requiring high spatial resolution and fast frame rates. ePix ASICs are based on a common platform composed of a random access analog matrix of pixel with global shutter, fast parallel column readout, and dedicated sigma-delta analog to digital converters per column. The ePix10k variant has 100um×100um pixels arranged in a 176×192 matrix, a resolution of 140e- r.m.s. and a signal range of 3.5pC (10k photons at 8keV). In its final version it will be able to sustain a frame rate of 2kHz. A first prototype has been fabricated and characterized. Performance in terms of noise, linearity, uniformity, cross-talk, together with preliminary measurements with bump bonded sensors are reported here.

  16. Performance of VATA64HDR16 ASIC for medical physics applications based on continuous crystals and SiPMs

    International Nuclear Information System (INIS)

    Detectors based on Silicon Photomultipliers (SiPMs) coupled to continuous crystals are being tested in medical physics applications due to their potential high resolution and sensitivity. To cope with the high granularity required for a very good spatial resolution, SiPM matrices with a large amount of elements are needed. To be able to read the information coming from each individual channel, dedicated ASICs are employed. The VATA64HDR16 ASIC is a 64-channel, charge-sensitive amplifier that converts the collected charge into a proportional current or voltage signal. A complete assessment of the suitability of that ASIC for medical physics applications based on continuous crystals and SiPMs has been carried out. The input charge range is linear from 0−2 pC up to 55 pC. The energy resolution obtained at 511 keV is 10% FWHM with a LaBr3 crystal and 16% FWHM with a LYSO crystal. A coincidence timing resolution of 24 ns FWHM is obtained with two LYSO crystals

  17. Implementation of an ASIC for Detector Instrumentation in Nuclear Physics Applications

    OpenAIRE

    McIntosh, James Alexander

    1996-01-01

    A prototype ASIC (EFT1) for silicon strip detector instrumentation has been designed and tested. The ASIC design contains the electronics necessary for preamplification, shaping, hit detection, and data readout control.The specific­ ation of the ASIC makes it suitable for charged particle spectroscopy applications with the implementation of multiple channels on a single chip reducing the cost compared to expensive discrete instrumentation. The ASIC contains features wh...

  18. Four-channel readout ASIC for silicon pad detectors

    International Nuclear Information System (INIS)

    A custom front-end readout ASIC has been designed for silicon calorimeters supposed to be used in high-energy physics experiments. The ASIC was produced using BJT-JFET technology. It contains four channels of a fast low-noise charge-sensitive preamplifier (CSP) with inverting outputs summed by a linear adder (LA) followed by an RC-CR shaping amplifier (SA) with 30 ns peaking time. Availability of separate outputs of the CSPs and the LA makes it possible to join any number of silicon detector layers to obtain the longitudinal and transversal resolution required using only this ASIC in any silicon calorimeter minitower configuration. Noise performance is ENC=1800e-+18e-/pF at 30 ns peaking time for detector capacitance up to Cd=400 pF. Rise time is 8 ns at input capacitance Cd=100 pF. Power dissipation is less than 50 mW/ chip at voltage supply 5 V

  19. A 2D 4×4 Channel Readout ASIC for Pixelated CdTe Detectors for Medical Imaging Applications

    OpenAIRE

    Macias-Montero, Jose-Gabriel; Sarraj, Maher; Chmeissani, Mokhtar; Martínez, Ricardo; Puigdengoles, Carles

    2015-01-01

    We present a 16-channel readout integrated circuit (ROIC) with nanosecond-resolution time to digital converter (TDC) for pixelated Cadmium Telluride (CdTe) gamma-ray detectors. The 4 × 4 pixel array ROIC is the proof of concept of the 10 × 10 pixel array readout ASIC for positron-emission tomography (PET) scanner, positron-emission mammography (PEM) scanner, and Compton gamma camera. The electronics of each individual pixel integrates an analog front-end with switchable gain, an analog to dig...

  20. Octal channel amplifier-discriminator based on ASD-8 (ASIC) for timing measurements with drift chambers

    International Nuclear Information System (INIS)

    The 8-channel amplifier-discriminator AD8-H/1 based on ASIC ASD-8 is described. The IC, aimed at timing measurements with wire gaseous detectors, contains 8 identical channels consisting of the preamplifier, the shaper and the discriminator. Spark protection diode chains are installed at the inputs of the device; output current can either directly drive a cable or be converted into a voltage pulse of a required standard. The main parameters of the device are the following: power consumption is not more than 30 mW per channel, noise, σ, is ∼ 1500 e- for Cin = 10 pF, minimum threshold voltage is ∼ 1 fC, signal rise time is about 8 ns, double pulse resolution using detector signals is expected to be better than 100 ns. This amplifier-discriminator is proposed for data readout from drift chambers with a high spatial resolution

  1. Beam test performance of the SKIROC2 ASIC

    CERN Document Server

    Frisson, T; Anduze, M; Augustin, J.E; Bonis, J; Boudry, V; Bourgeois, C; Brient, J.C; Callier, S; Cerutti, M; Chen, S; Cornat, R; Cornebise, P; Cuisy, D; David, J; De la Taille, C; Dulucq, F; Frotin, M; Gastaldi, F; Ghislain, P; Giraud, J; Gonnin, A; Grondin, D; Guliyev, E; Hostachy, J.Y; Jeans, D; Kamiya, Y; Kawagoe, K; Kozakai, C; Lacour, D; Lavergne, L; Lee, S.H; Magniette, F; Ono, H; Poeschl, R; Rouëné, J; Seguin-Moreau, N; Song, H.S; Sudo, Y; Thiebault, A; Tran, H; Ueno, H; Van der Kolk, N; Yoshioka, T

    2015-01-01

    Beam tests of the first layers of CALICE silicon tungsten ECAL technological prototype were performed in April and July 2012 using 1–6 GeV electron beam at DESY. This paper presents an analysis of the SKIROC2 readout ASIC performance under test beam conditions.

  2. Evidence for the involvement of ASIC3 in sensory mechanotransduction in proprioceptors.

    Science.gov (United States)

    Lin, Shing-Hong; Cheng, Yuan-Ren; Banks, Robert W; Min, Ming-Yuan; Bewick, Guy S; Chen, Chih-Cheng

    2016-01-01

    Acid-sensing ion channel 3 (ASIC3) is involved in acid nociception, but its possible role in neurosensory mechanotransduction is disputed. We report here the generation of Asic3-knockout/eGFPf-knockin mice and subsequent characterization of heterogeneous expression of ASIC3 in the dorsal root ganglion (DRG). ASIC3 is expressed in parvalbumin (Pv+) proprioceptor axons innervating muscle spindles. We further generate a floxed allele of Asic3 (Asic3(f/f)) and probe the role of ASIC3 in mechanotransduction in neurite-bearing Pv+ DRG neurons through localized elastic matrix movements and electrophysiology. Targeted knockout of Asic3 disrupts spindle afferent sensitivity to dynamic stimuli and impairs mechanotransduction in Pv+ DRG neurons because of substrate deformation-induced neurite stretching, but not to direct neurite indentation. In behavioural tasks, global knockout (Asic3(-/-)) and Pv-Cre::Asic3(f/f) mice produce similar deficits in grid and balance beam walking tasks. We conclude that, at least in mouse, ASIC3 is a molecular determinant contributing to dynamic mechanosensitivity in proprioceptors. PMID:27161260

  3. Three-dimensional stacked structured ASIC devices and methods of fabrication thereof

    Energy Technology Data Exchange (ETDEWEB)

    Shinde, Subhash L.; Teifel, John; Flores, Richard S.; Jarecki Jr., Robert L.; Bauer, Todd

    2015-11-19

    A 3D stacked sASIC is provided that includes a plurality of 2D reconfigurable structured structured ASIC (sASIC) levels interconnected through hard-wired arrays of 3D vias. The 2D sASIC levels may contain logic, memory, analog functions, and device input/output pad circuitry. During fabrication, these 2D sASIC levels are stacked on top of each other and fused together with 3D metal vias. Such 3D vias may be fabricated as through-silicon vias (TSVs). They may connect to the back-side of the 2D sASIC level, or they may be connected to top metal pads on the front-side of the 2D sASIC level.

  4. Precision BiCMOS successive approximation analog-to-digital converter with low power consumption

    International Nuclear Information System (INIS)

    An IP block of a successive approximation analog-to-digital converter (ADC) with low power consumption has been developed as a part of an application-specific integrated circuit (ASIC) for an intellectual flow meter. The advantages of the application of the modified “top-down” design method to the design of the chip have been demonstrated. The results of the simulation, verification, and test of the analog-to-digital converter are presented

  5. I and C functional test facility with ASICS and ADIOS

    International Nuclear Information System (INIS)

    Recently, digital technology is introduced to instrumentation and control systems in nuclear power plants. It is actively proceeded in the nuclear industry that the intelligent technologies apply to operation and operator support system. In this paper, The Automatic Startup Intelligent Control System (ASICS) that automatically controls the PWR plant from cold shutdown to 5 percent of reactor power and Alarm and Diagnosis-Integrated Operator Support System (ADIOS) that is integrated with alarms, process values, and diagnostic information to an expert system focused on alarm processing are described. The performance and the function of ASICS and ADIOS are evaluated with the real-time functional test facility and the results are shown that the developed systems are efficient and useful for operation and operator support (author) (ml)

  6. ENaCs and ASICs as therapeutic targets

    OpenAIRE

    Qadri, Yawar J.; Rooj, Arun K.; Fuller, Catherine M.

    2012-01-01

    The epithelial Na+ channel (ENaC) and acid-sensitive ion channel (ASIC) branches of the ENaC/degenerin superfamily of cation channels have drawn increasing attention as potential therapeutic targets in a variety of diseases and conditions. Originally thought to be solely expressed in fluid absorptive epithelia and in neurons, it has become apparent that members of this family exhibit nearly ubiquitous expression. Therapeutic opportunities range from hypertension, due to the role of ENaC in ma...

  7. An SEU analysis approach for error propagation in digital VLSI CMOS ASICs

    International Nuclear Information System (INIS)

    A critical issue in the development of ASIC designs is the ability to achieve first pass fabrication success. Unsuccessful fabrication runs have serious impact on ASIC costs and schedules. The ability to predict an ASICs radiation response prior to fabrication is therefore a key issue when designing ASICs for military and aerospace systems. This paper describes an analysis approach for calculating static bit error propagation in synchronous VLSI CMOS circuits developed as an aid for predicting the SEU response of ASIC's. The technique is intended for eventual application as an ASIC development simulation tool which can be used by circuit design engineers for performance evaluation during the pre-fabrication design process in much the same way that logic and timing simulators are used

  8. The SIRIUS Mixed analog-digital ASIC developed for the LOFT LAD and WFM instruments

    CERN Document Server

    Cros, A; Moutaye, E; Ravera, L; Barret, D; Caïs, P; Clédassou, R; Bodin, P; Seyler, JY; Bonzo, A; Feroci, M; Labanti, C; Evangelista, Y; Favre, Y

    2014-01-01

    We report on the development and characterization of the low-noise, low power, mixed analog-digital SIRIUS ASICs for both the LAD and WFM X-ray instruments of LOFT. The ASICs we developed are reading out large area silicon drift detectors (SDD). Stringent requirements in terms of noise (ENC of 17 e- to achieve an energy resolution on the LAD of 200 eV FWHM at 6 keV) and power consumption (650 {\\mu}W per channel) were basis for the ASICs design. These SIRIUS ASICs are developed to match SDD detectors characteristics: 16 channels ASICs adapted for the LAD (970 microns pitch) and 64 channels for the WFM (145 microns pitch) will be fabricated. The ASICs were developed with the 180nm mixed technology of TSMC.

  9. Automated Solution for Data Monitoring (Dashboard of ASIC Design Flow

    Directory of Open Access Journals (Sweden)

    Kariyappa B S1 , Aravind2 , Dhananjaya A3 , Vineet Puri

    2013-07-01

    Full Text Available Application Specific Integrated Circuit (ASIC design flow consists of several steps involved with Electronic Design Automation (EDA tools. For an ASIC designer it is very important to know the status of design development. Finding the status of the actual design is currently a manual work. It is difficult to track the status and error information using log/report files generated by the tool at different stages of design flow. Therefore it is necessary to develop an automated tool to solve these issues and hence to reduce the designer effort significantly. In this paper smart data monitoring (dashboard system is developed as an automated solution using PERL scripting language. The 8-bit Arithmetic Logic Unit (ALU is designed for the verification of developed dashboard system. The log/report files are generated at each stages of the design. The information like errors, warnings, time of execution and report parameters are extracted from the design runs and stored in to database using the dashboard system. The stored design status information and report results are visualized in a single window dashboard view at each stages of the design flow. The developed dashboard system is generic and can be used for any kind of ASIC design. Thus monitoring multiple design products using dashboard, the time and effort required for checking design status is reducedsignificantly.

  10. The read-out ASIC for the Space NUCLEON project

    International Nuclear Information System (INIS)

    This paper summarizes the design results for the read-out ASIC for the space NUCLEON project of the Russian Federal Space Agency ROSCOSMOS. The ASIC with a unique high dynamic range (1–40 000 mip) at low power consumption (< 1.5 mW per channel) has been developed. It allows to record signals of relativistic particles and nuclei with charges from Z = 1 up to Z > 50, generated by silicon detectors, having capacitances up to 100 pF. The chip structure includes 32 analog channels, each consisting of a charge sensitive amplifier (CSA) with a p-MOS input transistor (W = 8 mm, L = 0.5 μ m), a shaper (peaking time of 2 us) and a T and H circuit. The ASIC showed a 120 pC dynamic range at a SNR of 2.5 for the particles with minimal ionization energy (1 mip). The chip was fabricated by the 0.35 um CMOS process via Europractice and tested both at lab conditions and in the SPS beam at CERN

  11. An ASIC Low Power Primer Analysis, Techniques and Specification

    CERN Document Server

    Chadha, Rakesh

    2013-01-01

    This book provides an invaluable primer on the techniques utilized in the design of low power digital semiconductor devices.  Readers will benefit from the hands-on approach which starts form the ground-up, explaining with basic examples what power is, how it is measured and how it impacts on the design process of application-specific integrated circuits (ASICs).  The authors use both the Unified Power Format (UPF) and Common Power Format (CPF) to describe in detail the power intent for an ASIC and then guide readers through a variety of architectural and implementation techniques that will help meet the power intent.  From analyzing system power consumption, to techniques that can employed in a low power design, to a detailed description of two alternate standards for capturing the power directives at various phases of the design, this book is filled with information that will give ASIC designers a competitive edge in low-power design. Starts from the ground-up and explains what power is, how it is measur...

  12. VeloPix ASIC for the LHCb VELO Upgrade

    CERN Multimedia

    Cid Vidal, Xabier

    2015-01-01

    The LHCb Vertex Detector (VELO) will be upgraded in 2018 along with the other subsystems of LHCb in order to enable full detector readout at 40 MHz. LHCb will run without a hardware trigger and all data will be fed directly to the software triggering algorithms in the CPU farm. The upgraded VELO is a lightweight silicon hybrid pixel detector with 55 um square pixels, operating in vacuum in close proximity to the LHC beams. The readout will be provided by a dedicated front end ASIC, dubbed VeloPix, matched to the LHCb luminosity requirements. VeloPix is a binary pixel chip with a matrix of 256 x 256 pixels, covering an area of 2 cm^2. It is designed in a 130 nm CMOS technology, and is closely related to the Timepix3, from the Medipix family of ASICs. The principal challenge that the chip has to meet is a hit rate of up to 900 Mhits/s/ASIC, resulting in a data rate of more than 16 Gbit/s. Combining pixels into groups of 2x4 super-pixels enables the use of shared logic and a reduction of bandwidth due to combine...

  13. Four-channel readout ASIC for silicon pad detectors

    CERN Document Server

    Baturitsky, M A

    2000-01-01

    A custom front-end readout ASIC has been designed for silicon calorimeters supposed to be used in high-energy physics experiments. The ASIC was produced using BJT-JFET technology. It contains four channels of a fast low-noise charge-sensitive preamplifier (CSP) with inverting outputs summed by a linear adder (LA) followed by an RC-CR shaping amplifier (SA) with 30 ns peaking time. Availability of separate outputs of the CSPs and the LA makes it possible to join any number of silicon detector layers to obtain the longitudinal and transversal resolution required using only this ASIC in any silicon calorimeter minitower configuration. Noise performance is ENC=1800e sup - +18e sup - /pF at 30 ns peaking time for detector capacitance up to C sub d =400 pF. Rise time is 8 ns at input capacitance C sub d =100 pF. Power dissipation is less than 50 mW/ chip at voltage supply 5 V.

  14. ASIC Design and Data Communications for the Boston Retinal Prosthesis

    Science.gov (United States)

    Shire, Douglas B.; Ellersick, William; Kelly, Shawn K.; Doyle, Patrick; Priplata, Attila; Drohan, William; Mendoza, Oscar; Gingerich, Marcus; McKee, Bruce; Wyatt, John L.; Rizzo, Joseph F.

    2016-01-01

    We report on the design and testing of a custom application-specific integrated circuit (ASIC) that has been developed as a key component of the Boston retinal prosthesis. This device has been designed for patients who are blind due to age-related macular degeneration or retinitis pigmentosa. Key safety and communication features of the low-power ASIC are described, as are the highly configurable neural stimulation current waveforms that are delivered to its greater than 256 output electrodes. The ASIC was created using an 0.18 micron Si fabrication process utilizing standard 1.8 volt CMOS transistors as well as 20 volt lightly doped drain FETs. The communication system receives frequency-shift keyed inputs at 6.78 MHz from an implanted secondary coil, and transmits data back to the control unit through a lower-bandwidth channel that employs load-shift keying. The design’s safety is ensured by on-board electrode voltage monitoring, stimulus charge limits, error checking of data transmitted to the implant, and comprehensive self-test and performance monitoring features. Each stimulus cycle is initiated by a transmitted word with a full 32-bit error check code. Taken together, these features allow researchers to safely and wirelessly tailor retinal stimulation and vision recovery for each patient. PMID:23365888

  15. Low power Analog Digital Converter for a silicon photomultiplier readout ASIC

    International Nuclear Information System (INIS)

    We present an ADC designed in the UMC 0.18um CMOS technology. It will be used in the SiPM analog front-end ''KLauS' developed for the analog hadronic calorimeter at ILD. Key parameter in this application is an extremely low power consumption of the front-end electronics. For quantization of the energy depositions, a 10-bit ADC resolution is required. For calibration purposes, a 12-bit quantization is used. A successive approximation register split capacitor array structure is chosen to minimize the DC power consumption. A peak sensing block is used to minimize the required sampling rate. We present design details and simulation results of the ADC, as well as the peak sensing track and hold circuit

  16. Low power Analog Digital Converter for a silicon photomultiplier readout ASIC

    Science.gov (United States)

    Briggl, K.; Chen, H.; Shen, W.; Schultz-Coulon, H. C.

    2015-04-01

    We present an ADC designed in the UMC 0.18um CMOS technology. It will be used in the SiPM analog front-end ``KLauS" developed for the analog hadronic calorimeter at ILD. Key parameter in this application is an extremely low power consumption of the front-end electronics. For quantization of the energy depositions, a 10-bit ADC resolution is required. For calibration purposes, a 12-bit quantization is used. A successive approximation register split capacitor array structure is chosen to minimize the DC power consumption. A peak sensing block is used to minimize the required sampling rate. We present design details and simulation results of the ADC, as well as the peak sensing track & hold circuit.

  17. ASIC3 Channels Integrate Agmatine and Multiple Inflammatory Signals through the Nonproton Ligand Sensing Domain

    Directory of Open Access Journals (Sweden)

    Cao Hui

    2010-12-01

    Full Text Available Abstract Background Acid-sensing ion channels (ASICs have long been known to sense extracellular protons and contribute to sensory perception. Peripheral ASIC3 channels represent natural sensors of acidic and inflammatory pain. We recently reported the use of a synthetic compound, 2-guanidine-4-methylquinazoline (GMQ, to identify a novel nonproton sensing domain in the ASIC3 channel, and proposed that, based on its structural similarity with GMQ, the arginine metabolite agmatine (AGM may be an endogenous nonproton ligand for ASIC3 channels. Results Here, we present further evidence for the physiological correlation between AGM and ASIC3. Among arginine metabolites, only AGM and its analog arcaine (ARC activated ASIC3 channels at neutral pH in a sustained manner similar to GMQ. In addition to the homomeric ASIC3 channels, AGM also activated heteromeric ASIC3 plus ASIC1b channels, extending its potential physiological relevance. Importantly, the process of activation by AGM was highly sensitive to mild acidosis, hyperosmolarity, arachidonic acid (AA, lactic acid and reduced extracellular Ca2+. AGM-induced ASIC3 channel activation was not through the chelation of extracellular Ca2+ as occurs with increased lactate, but rather through a direct interaction with the newly identified nonproton ligand sensing domain. Finally, AGM cooperated with the multiple inflammatory signals to cause pain-related behaviors in an ASIC3-dependent manner. Conclusions Nonproton ligand sensing domain might represent a novel mechanism for activation or sensitization of ASIC3 channels underlying inflammatory pain-sensing under in vivo conditions.

  18. Hydrogen converters

    International Nuclear Information System (INIS)

    The National Atomic Energy Commission of Argentina developed a process of 99Mo production from fission, based on irradiation of uranium aluminide targets with thermal neutrons in the RA-3 reactor of the Ezeiza Atomic Centre. These targets are afterwards dissolved in an alkaline solution, with the consequent liberation of hydrogen as the main gaseous residue. This work deals with the use of a first model of metallic converter and a later prototype of glass converter at laboratory scale, adjusted to the requirements and conditions of the specific redox process. Oxidized copper wires were used, which were reduced to elementary copper at 400 C degrees and then regenerated by oxidation with hot air. Details of the bed structure and the operation conditions are also provided. The equipment required for the assembling in cells is minimal and, taking into account the operation final temperature and the purge with nitrogen, the procedure is totally safe. Finally, the results are extrapolated for the design of a converter to be used in a hot cell. (author)

  19. Wavelength Converters

    DEFF Research Database (Denmark)

    Kloch, Allan; Hansen, Peter Bukhave; Wolfson, David;

    1999-01-01

    After a short introduction to the different requirements to and techniques for wavelength conversion, focus is on cross-gain and cross-phase modulation in SOAs and SOA based interferometers. Aspects like jitter accumulation, regeneration and conversion to the same wavelength is discussed. It is...... extinction ratio of ~10 dB.The regenerative capabilities of the cross-phase converters are described and verified experimentally at 20 Gbit/s, where the noise redistribution and improvement of the signal-to-noise ratio clearly is demonstrated by controlling the input power to an EDFA. In a similar experiment...

  20. ASIC3 Is Required for Development of Fatigue-Induced Hyperalgesia.

    Science.gov (United States)

    Gregory, Nicholas S; Brito, Renan G; Fusaro, Maria Cláudia G Oliveira; Sluka, Kathleen A

    2016-03-01

    An acute bout of exercise can exacerbate pain, hindering participation in regular exercise and daily activities. The mechanisms underlying pain in response to acute exercise are poorly understood. We hypothesized that proton accumulation during muscle fatigue activates acid-sensing ion channel 3 (ASIC3) on muscle nociceptors to produce hyperalgesia. We investigated the role of ASIC3 using genetic and pharmacological approaches in a model of fatigue-enhanced hyperalgesia. This model uses two injections of pH 5.0 saline into muscle in combination with an electrically induced fatigue of the same muscle just prior to the second injection of acid to induce mechanical hyperalgesia. We show a significant decrease in muscle force and decrease in muscle pH after 6 min of electrical stimulation. Genetic deletion of ASIC3 using knockout mice and pharmacological blockade of ASIC3 with APETx2 in muscle prevents the fatigue-enhanced hyperalgesia. However, ASIC3(-/-) mice and APETx2 have no effect on the fatigue response. Genetic deletion of ASIC3 in primary afferents innervating muscle using an HSV-1 expressing microRNA (miRNA) to ASIC3 surprisingly had no effect on the development of the hyperalgesia. Muscle fatigue increased the number of macrophages in muscle, and removal of macrophages from muscle with clodronate liposomes prevented the development of fatigue-enhanced hyperalgesia. Thus, these data suggest that fatigue reduces pH in muscle that subsequently activates ASIC3 on macrophages to enhance hyperalgesia to muscle insult. PMID:25577172

  1. 4-Channel readout ASIC for MaPMT

    International Nuclear Information System (INIS)

    MaPMTs is widely used, but conventional PCB circuits can not satisfy their demands because of the defects of large volume, high power dissipation and noise. The 4-channel readout ASIC for MaPMT is designed for solving these problems with 0.35 μm CMOS technology. The circuit is composed of Pre-Amp, gain adjusting, and CR-RC shaper with Pole-zero cancling. The test results show power dissipation is 66 mW; gain 62.2 mV/pC; dynamic range 13 pC, INL=1.5%; SNR=9.1. The performances meet design requires. (authors)

  2. A prototype hybrid pixel detector ASIC for the CLIC experiment

    CERN Document Server

    Valerio, P; Arfaoui, S; Ballabriga, R; Benoit, M; Bonacini, S; Campbell, M; Dannheim, D; De Gaspari, M; Felici, D; Kulis, S; Llopart, X; Nascetti, A; Poikela, T; Wong, W S

    2014-01-01

    A prototype hybrid pixel detector ASIC specifically designed to the requirements of the vertex detector for CLIC is described and first electrical measurements are presented. The chip has been designed using a commercial 65 nm CMOS technology and comprises a matrix of 64x64 square pixels with 25 μm pitch. The main features include simultaneous 4-bit measure- ment of Time-over-Threshold (ToT) and Time-of-Arrival (ToA) with 10 ns accuracy, on-chip data compression and power pulsing capability.

  3. 0.18μm CMOS, MONOLITHIC MSTP ASIC

    Institute of Scientific and Technical Information of China (English)

    Wang Peng; Jin Depeng; Zeng Lieguang

    2006-01-01

    A highly integrated monolithic Multi-Service Transport Platform (MSTP) Application Specified Integrated Circuit (ASIC) MSEOSX8-6 has been fabricated with 0.18μm CMOS technology incorporating 26×106 transistors. The chip is designed to provide standard framing and mapping of 10/100/1000Mbit/s Ethernet, Resilient Packet Ring (RPR) and E1 traffics into protected Synchronous Digital Hierarchy (SDH) STM-1 transport payloads using hitless rate adaptation for optimum bandwidth utilization. It consumes 4W of power on average and utilizes 756 pin enhanced BGA package.

  4. An ASIC design for PMT front-end readout

    International Nuclear Information System (INIS)

    An ASIC of 5 channels is designed for PMT front-end readout, in Chartered 0.35 μm 2P4M COMS technology. Each channel integrates preamplifier, slow shaper, fast shaper and discriminator. The gain of pre-amp is adjustable and the time constant of slow shaper can be set to be 25 ns, 50 ns and 100 ns. The chip is used for experiments of dark mAtter detecting (HEGARD)[1]. The results of simulation show it has good dynamic range (14 bits), good linearity (1%) and good noise performAnce (<1/10 p.e.). (authors)

  5. HDL code analysis for ASICs in mobile systems

    OpenAIRE

    Wickberg, Fredrik

    2007-01-01

    The complex work of designing new ASICs today and the increasing costs of time to market (TTM) delays are putting high responsibility on the research and development teams to make fault free designs. The main purpose of implementing a static rule checking tool in the design flow today is to find errors and bugs in the hardware definition language (HDL) code as fast and soon as possible. The sooner you find a bug in the design, the shorter the turnaround time becomes, and thereby both time and...

  6. The Human Acid-Sensing Ion Channel ASIC1a: Evidence for a Homotetrameric Assembly State at the Cell Surface.

    Science.gov (United States)

    van Bemmelen, Miguel Xavier; Huser, Delphine; Gautschi, Ivan; Schild, Laurent

    2015-01-01

    The chicken acid-sensing ion channel ASIC1 has been crystallized as a homotrimer. We address here the oligomeric state of the functional ASIC1 in situ at the cell surface. The oligomeric states of functional ASIC1a and mutants with additional cysteines introduced in the extracellular pore vestibule were resolved on SDS-PAGE. The functional ASIC1 complexes were stabilized at the cell surface of Xenopus laevis oocytes or CHO cells either using the sulfhydryl crosslinker BMOE, or sodium tetrathionate (NaTT). Under these different crosslinking conditions ASIC1a migrates as four distinct oligomeric states that correspond by mass to multiples of a single ASIC1a subunit. The relative importance of each of the four ASIC1a oligomers was critically dependent on the availability of cysteines in the transmembrane domain for crosslinking, consistent with the presence of ASIC1a homo-oligomers. The expression of ASIC1a monomers, trimeric or tetrameric concatemeric cDNA constructs resulted in functional channels. The resulting ASIC1a complexes are resolved as a predominant tetramer over the other oligomeric forms, after stabilization with BMOE or NaTT and SDS-PAGE/western blot analysis. Our data identify a major ASIC1a homotetramer at the surface membrane of the cell expressing functional ASIC1a channel. PMID:26252376

  7. Multichannel readout ASIC design flow for high energy physics and cosmic rays experiments

    Science.gov (United States)

    Voronin, A.; Malankin, E.

    2016-02-01

    In the large-scale high energy physics and astrophysics experiments multi-channel readout application specific integrated circuits (ASICs) are widely used. The ASICs for such experiments are complicated systems, which usually include both analog and digital building blocks. The complexity and large number of channels in such ASICs require the proper methodological approach to their design. The paper represents the mixed-signal design flow of the ASICs for high energy physics and cosmic rays experiments. This flow was successfully embedded to the development of the read-out ASIC prototype for the muon chambers of the CBM experiment. The approach was approved in UMC CMOS MMRF 180 nm process. The design flow enable to analyse the mixed-signal system operation on the different levels: functional, behavioural, schematic and post layout including parasitic elements. The proposed design flow allows reducing the simulation period and eliminating the functionality mismatches on the very early stage of the design.

  8. A CMOS ASIC Design for SiPM Arrays.

    Science.gov (United States)

    Dey, Samrat; Banks, Lushon; Chen, Shaw-Pin; Xu, Wenbin; Lewellen, Thomas K; Miyaoka, Robert S; Rudell, Jacques C

    2011-12-01

    Our lab has previously reported on novel board-level readout electronics for an 8×8 silicon photomultiplier (SiPM) array featuring row/column summation technique to reduce the hardware requirements for signal processing. We are taking the next step by implementing a monolithic CMOS chip which is based on the row-column architecture. In addition, this paper explores the option of using diagonal summation as well as calibration to compensate for temperature and process variations. Further description of a timing pickoff signal which aligns all of the positioning (spatial channels) pulses in the array is described. The ASIC design is targeted to be scalable with the detector size and flexible to accommodate detectors from different vendors. This paper focuses on circuit implementation issues associated with the design of the ASIC to interface our Phase II MiCES FPGA board with a SiPM array. Moreover, a discussion is provided for strategies to eventually integrate all the analog and mixed-signal electronics with the SiPM, on either a single-silicon substrate or multi-chip module (MCM). PMID:24825923

  9. Exploring Many-Core Design Templates for FPGAs and ASICs

    Directory of Open Access Journals (Sweden)

    Ilia Lebedev

    2012-01-01

    Full Text Available We present a highly productive approach to hardware design based on a many-core microarchitectural template used to implement compute-bound applications expressed in a high-level data-parallel language such as OpenCL. The template is customized on a per-application basis via a range of high-level parameters such as the interconnect topology or processing element architecture. The key benefits of this approach are that it (i allows programmers to express parallelism through an API defined in a high-level programming language, (ii supports coarse-grained multithreading and fine-grained threading while permitting bit-level resource control, and (iii reduces the effort required to repurpose the system for different algorithms or different applications. We compare template-driven design to both full-custom and programmable approaches by studying implementations of a compute-bound data-parallel Bayesian graph inference algorithm across several candidate platforms. Specifically, we examine a range of template-based implementations on both FPGA and ASIC platforms and compare each against full custom designs. Throughout this study, we use a general-purpose graphics processing unit (GPGPU implementation as a performance and area baseline. We show that our approach, similar in productivity to programmable approaches such as GPGPU applications, yields implementations with performance approaching that of full-custom designs on both FPGA and ASIC platforms.

  10. Replication of Space-Shuttle Computers in FPGAs and ASICs

    Science.gov (United States)

    Ferguson, Roscoe C.

    2008-01-01

    A document discusses the replication of the functionality of the onboard space-shuttle general-purpose computers (GPCs) in field-programmable gate arrays (FPGAs) and application-specific integrated circuits (ASICs). The purpose of the replication effort is to enable utilization of proven space-shuttle flight software and software-development facilities to the extent possible during development of software for flight computers for a new generation of launch vehicles derived from the space shuttles. The replication involves specifying the instruction set of the central processing unit and the input/output processor (IOP) of the space-shuttle GPC in a hardware description language (HDL). The HDL is synthesized to form a "core" processor in an FPGA or, less preferably, in an ASIC. The core processor can be used to create a flight-control card to be inserted into a new avionics computer. The IOP of the GPC as implemented in the core processor could be designed to support data-bus protocols other than that of a multiplexer interface adapter (MIA) used in the space shuttle. Hence, a computer containing the core processor could be tailored to communicate via the space-shuttle GPC bus and/or one or more other buses.

  11. A miniaturized ASIC-based multichannel scaler instrument

    International Nuclear Information System (INIS)

    A miniaturized multichannel scaler instrument has been developed to address size and operational constraints for data acquisition in a portable laser-induced luminescence system. The multichannel scaling (MCS) function is implemented as a programmable application specific integrated circuit (ASIC) with standard interfaces for control and data acquisition. The instrument is microcontroller-based with sufficient computing power for data manipulation and algorithmic processing. The unit includes electronics for laser control and amplification and pulse height discrimination of PMT pulses. Modification of the instrument should allow use in nuclear, chemical, and spectroscopy-related applications including Mossbauer experiments. Interfaces are incorporated allowing both computer-controlled and stand-alone operational. Implementation of the MCS function as an ASIC and comparison with conventional implementations are discussed. Full characterization of the MCS is presented including differential non-linearity (DNL), bin dead time, and bandwidth measurements. The instrument was specifically designed for determining environmental uranium concentration levels in ground water monitoring applications, with sufficient sensitivity to analyzed low-level process streams and effluent. The analysis method employed is based on phosphorescence decay techniques thoroughly covered in published literature

  12. Characterization results of the JUNGFRAU full scale readout ASIC

    Science.gov (United States)

    Mozzanica, A.; Bergamaschi, A.; Brueckner, M.; Cartier, S.; Dinapoli, R.; Greiffenberg, D.; Jungmann-Smith, J.; Maliakal, D.; Mezza, D.; Ramilli, M.; Ruder, C.; Schaedler, L.; Schmitt, B.; Shi, X.; Tinti, G.

    2016-02-01

    The two-dimensional pixel detector JUNGFRAU is designed for high performance photon science applications at free electron lasers and synchrotron light sources. It is developed for the SwissFEL currently under construction at the Paul Scherrer Institut, Switzerland. The detector is a hybrid pixel detector with a charge integration readout ASIC characterized by single photon sensitivity and a low noise performance over a dynamic range of 104 12 keV photons. Geometrically, a JUNGFRAU readout chip consists of 256×256 pixels of 75×75 μm2. The chips are bump bonded to 320 μm thick silicon sensors. Arrays of 2×4 chips are tiled to form modules of 4×8 cm2 area. Several multi-module systems with up to 16 Mpixels per system will be delivered to the two end stations at SwissFEL. The JUNGFRAU full scale readout ASIC and module design are presented along with characterization results of the first systems. Experiments from fluorescence X-ray, visible light illumination, and synchrotron irradiation are shown. The results include an electronic noise of ~50 electrons r.m.s., which enables single photon detection energies below 2 keV and a noise well below the Poisson statistical limit over the entire dynamic range. First imaging experiments are also shown.

  13. DIRAC v2 a DIgital Readout Asic for hadronic Calorimeter

    CERN Document Server

    Gaglione, R; Chefdeville, M; Drancourt, C; Vouters, G

    2009-01-01

    DIRAC is a 64 channel mixed-signal readout integrated circuit designed for Micro-Pattern Gaseous Detectors (MICROMEGAS, Gas Electron Multiplier) or Resistive Plate Chambers. These detectors are foreseen as the active part of a digital hadronic calorimeter for a high energy physics experiment at the International Linear Collider. Physic requirements lead to a highly granular hadronic calorimeter with up to thirty million channels with probably only hit information (digital calorimeter). The DIRAC ASIC has been especially designed for these constraints. Each channel of the DIRAC chip is made of a 4 gains charge preamplifier, a DC-servo loop, 3 switched comparators and a digital memory, thus providing additional energy information for a hit. A bulk MICROMEGAS detector with embedded DIRAC v1 ASIC has been built. The tests of this assembly, both in laboratory with X-Rays and in a beam at CERN are presented, demonstrating the feasibility of a bulk MICROMEGAS detector with embedded electronics. The second version of...

  14. Interaction of Acid-sensing Ion Channel (ASIC) 1 with the Tarantula Toxin Psalmotoxin 1 is State Dependent

    OpenAIRE

    Chen, Xuanmao; Kalbacher, Hubert; Gründer, Stefan

    2006-01-01

    Acid-sensing ion channels (ASICs) are Na+ channels gated by extracellular H+. Six ASIC subunits that are expressed in neurons have been characterized. The tarantula toxin psalmotoxin 1 has been reported to potently and specifically inhibit homomeric ASIC1a and has been useful to characterize ASICs in neurons. Recently we have shown that psalmotoxin 1 inhibits ASIC1a by increasing its apparent affinity for H+. However, the mechanism by which PcTx1 increases the apparent H+ affinity remained un...

  15. A 256 channel 8-Bit current digitizer ASIC for the Belle-II PXD

    International Nuclear Information System (INIS)

    The international DEPFET collaboration is developing a silicon pixel vertex detector (PXD), based on monolithic arrays of DEPFET transistors, for the future physics experiment Belle-II at the SuperKEKB particle accelerator in Japan. The matrix elements are read out in a 'rolling shutter mode', i.e. rows are selected consecutively and all columns are read out in each cycle of < 100 ns. One of the major parts in the front-end electronics chain is the DEPFET Current Digitizer ASIC (DCDB). It is now in a close-to-final state. The chip provides 256 channels of analog-to-digital converters with a resolution of six to eight bits. Each converter features an individual dynamic offset correction circuit as well as programmable gain and bandwidth. Several operation modes using single sampling or double correlated sampling are possible. A large synthesized digital block is used for decoding and derandomization of the conversion results. The data is put out on eight 8-bit links, operating at a speed of 400 MHz. Additionally, a JTAG compatible interface is implemented for configuration and debugging purpose. Significant effort was made to reduce the power consumption of the DCDB, since both, voltage drop on the internal power buses and heat sources in the Belle-II experiment are a concern. The chip was realized on a 3.2mm x 5mm die using the UMC 180nm CMOS technology in a multi-project wafer run, provided by EuroPractice. An extra redistribution metal layer with bump bond pads is used, allowing for flipping the chip onto the final all-silicon DEPFET sensor module. Several tests have been performed in order to prove the chip's operation and its quality in terms of noise. The results are presented.

  16. A 256 channel 8-Bit current digitizer ASIC for the Belle-II PXD

    Science.gov (United States)

    Knopf, J.; Fischer, P.; Kreidl, C.; Peric, I.

    2011-01-01

    The international DEPFET collaboration is developing a silicon pixel vertex detector (PXD), based on monolithic arrays of DEPFET transistors, for the future physics experiment Belle-II at the SuperKEKB particle accelerator in Japan. The matrix elements are read out in a 'rolling shutter mode', i.e. rows are selected consecutively and all columns are read out in each cycle of chain is the DEPFET Current Digitizer ASIC (DCDB). It is now in a close-to-final state. The chip provides 256 channels of analog-to-digital converters with a resolution of six to eight bits. Each converter features an individual dynamic offset correction circuit as well as programmable gain and bandwidth. Several operation modes using single sampling or double correlated sampling are possible. A large synthesized digital block is used for decoding and derandomization of the conversion results. The data is put out on eight 8-bit links, operating at a speed of 400 MHz. Additionally, a JTAG compatible interface is implemented for configuration and debugging purpose. Significant effort was made to reduce the power consumption of the DCDB, since both, voltage drop on the internal power buses and heat sources in the Belle-II experiment are a concern. The chip was realized on a 3.2mm × 5mm die using the UMC 180nm CMOS technology in a multi-project wafer run, provided by EuroPractice. An extra redistribution metal layer with bump bond pads is used, allowing for flipping the chip onto the final all-silicon DEPFET sensor module. Several tests have been performed in order to prove the chip's operation and its quality in terms of noise. The results are presented.

  17. Radiation-hard ASICs for optical data transmission in the first phase of the LHC upgrade

    CERN Document Server

    Gan, K K; Kagan, H P; Kass, R D; Moore, J R; Smith, D S; Wiese, A; Ziolkowskic, M; 10.1088/1748-0221/5/12/C12006

    2010-01-01

    We have designed two ASICs for possible applications in the optical links of a new layer of the pixel detector to be install inside the ATLAS Pixel detector for the first phase of the LHC luminosity upgrade. The ASICs include a high-speed driver for the VCSEL and a receiver/decoder to decode the signal received at the PIN diode to extract the data and clock. Both ASICs contain 4 channels for operation with a VCSEL or PIN array. The ASICs were designed using a 130 nm CMOS process to enhance the radiation-hardness. We have characterized the fabricated ASICs and the performance of the ASICs is satisfactory. The receiver/decoder can properly decode the bi-phase marked input stream with low PIN current and the driver can operate a VCSEL up to ~ 5 Gb/s. The added functionalities are also successful, including redundancy to bypass a broken VCSEL or PIN channel, individual control of VCSEL current, and power-on reset circuit to set all VCSEL currents to a nominal value. The ASICs were irradiated to a dose of 46 Mrad ...

  18. Direct visualization of the trimeric structure of the ASIC1a channel, using AFM imaging.

    Science.gov (United States)

    Carnally, Stewart M; Dev, Harveer S; Stewart, Andrew P; Barrera, Nelson P; Van Bemmelen, Miguel X; Schild, Laurent; Henderson, Robert M; Edwardson, J Michael

    2008-08-01

    There has been confusion about the subunit stoichiometry of the degenerin family of ion channels. Recently, a crystal structure of acid-sensing ion channel (ASIC) 1a revealed that it assembles as a trimer. Here, we used atomic force microscopy (AFM) to image unprocessed ASIC1a bound to mica. We detected a mixture of subunit monomers, dimers and trimers. In some cases, triple-subunit clusters were clearly visible, confirming the trimeric structure of the channel, and indicating that the trimer sometimes disaggregated after adhesion to the mica surface. This AFM-based technique will now enable us to determine the subunit arrangement within heteromeric ASICs. PMID:18514062

  19. Direct visualization of the trimeric structure of the ASIC1a channel, using AFM imaging

    International Nuclear Information System (INIS)

    There has been confusion about the subunit stoichiometry of the degenerin family of ion channels. Recently, a crystal structure of acid-sensing ion channel (ASIC) 1a revealed that it assembles as a trimer. Here, we used atomic force microscopy (AFM) to image unprocessed ASIC1a bound to mica. We detected a mixture of subunit monomers, dimers and trimers. In some cases, triple-subunit clusters were clearly visible, confirming the trimeric structure of the channel, and indicating that the trimer sometimes disaggregated after adhesion to the mica surface. This AFM-based technique will now enable us to determine the subunit arrangement within heteromeric ASICs

  20. Distance and Speed Measurements using FPGA and ASIC on a high data rate system

    Directory of Open Access Journals (Sweden)

    Abdul Rehman Buzdar

    2015-10-01

    Full Text Available This paper deals with the implementation of FPGA and ASIC designs to calculate the distance and speed of a moving remote object using laser source and echo pulses reflected from that remote object. The project proceeded in three phases for the FPGA implementation: All-in-C design using Xilinx Microblaze soft core processor system, an accelerated design with custom co-processor and Microblaze soft core processor system, and full custom hardware design implemented using VHDL on Xilinx FPGA. Later the complete system was implemented on ASIC. The ASIC implementation optimized the modules for area and timing for a 130nm process technology.

  1. Enhanced muscle fatigue occurs in male but not female ASIC3-/- mice

    OpenAIRE

    Burnes, Lynn A.; Kolker, Sandra J.; Danielson, Jessica F.; Walder, Roxanne Y.; Sluka, Kathleen A.

    2008-01-01

    Muscle fatigue is associated with a number of clinical diseases, including chronic pain conditions. Decreases in extracellular pH activates acid-sensing ion channel 3 (ASIC3), depolarizes muscle, protects against fatigue, and produces pain. We examined whether ASIC3-/- mice were more fatigable than ASIC3+/+ mice in a task-dependent manner. We developed two exercise protocols to measure exercise-induced muscle fatigue: ( fatigue task 1, three 1-h runs; fatigue task 2, three 30-min runs). In fa...

  2. ASIC Design of Floating-Point FFT Processor

    Institute of Scientific and Technical Information of China (English)

    陈禾; 赵忠武

    2004-01-01

    An application specific integrated circuit (ASIC) design of a 1024 points floating-point fast Fourier transform(FFT) processor is presented. It can satisfy the requirement of high accuracy FFT result in related fields. Several novel design techniques for floating-point adder and multiplier are introduced in detail to enhance the speed of the system. At the same time, the power consumption is decreased. The hardware area is effectively reduced as an improved butterfly processor is developed. There is a substantial increase in the performance of the design since a pipelined architecture is adopted, and very large scale integrated (VLSI) is easy to realize due to the regularity. A result of validation using field programmable gate array (FPGA) is shown at the end. When the system clock is set to 50 MHz, 204.8 μs is needed to complete the operation of FFT computation.

  3. Macro Pixel ASIC (MPA): The readout ASIC for the pixel-strip (PS) module of the CMS outer tracker at HL-LHC

    CERN Document Server

    Ceresa, Davide; Kloukinas, Konstantinos; Jan Kaplon; Bialas, Wojciech; Re, Valerio; Traversi, Gianluca; Gaioni, Luigi; Ratti, Lodovico

    2014-01-01

    The CMS tracker at HL-LHC is required to provide prompt information on particles with high transverse momentum to the central Level\\,1 trigger. For this purpose, the innermost part of the outer tracker is based on a combination of a pixelated sensor with a short strip sensor, the so-called Pixel-Strip module (PS). The readout of these sensors is carried out by distinct ASICs, the Strip Sensor ASIC (SSA), for the strip layer, and the Macro Pixel ASIC (MPA) for the pixel layer. The processing of the data directly on the front-end module represents a design challenge due to the large data volume (30720\\,pixels and 1920\\,strips per module) and the limited power budget. This is the reason why several studies have been carried out to find the best compromise between ASICs performance and power consumption. This paper describes the current status of the MPA ASIC development where the logic for generating prompt information on particles with high transverse momentum is implemented. An overview of the readout method i...

  4. Wide Temperature Rad-Hard ASIC for Process Control of a Fuel Cell System Project

    Data.gov (United States)

    National Aeronautics and Space Administration — Ridgetop Group developed a top-level design of a rad-hard application-specific integrated circuit (ASIC) for spacecraft power management that is functional over a...

  5. High-Speed, Low Power 256 Channel Gamma Radiation Array Detector ASIC Project

    Data.gov (United States)

    National Aeronautics and Space Administration — Building on prior success in detector electronics, we propose to design and fabricate a 256 channel readout ASIC for solid state gamma radiation array detectors...

  6. ASIC3, an acid-sensing ion channel, is expressed in metaboreceptive sensory neurons

    Directory of Open Access Journals (Sweden)

    Fierro Leonardo

    2005-11-01

    Full Text Available Abstract Background ASIC3, the most sensitive of the acid-sensing ion channels, depolarizes certain rat sensory neurons when lactic acid appears in the extracellular medium. Two functions have been proposed for it: 1 ASIC3 might trigger ischemic pain in heart and muscle; 2 it might contribute to some forms of touch mechanosensation. Here, we used immunocytochemistry, retrograde labelling, and electrophysiology to ask whether the distribution of ASIC3 in rat sensory neurons is consistent with either of these hypotheses. Results Less than half (40% of dorsal root ganglion sensory neurons react with anti-ASIC3, and the population is heterogeneous. They vary widely in cell diameter and express different growth factor receptors: 68% express TrkA, the receptor for nerve growth factor, and 25% express TrkC, the NT3 growth factor receptor. Consistent with a role in muscle nociception, small ( Conclusion Our data indicates that: 1 ASIC3 is expressed in a restricted population of nociceptors and probably in some non-nociceptors; 2 co-expression of ASIC3 and CGRP, and the absence of P2X3, are distinguishing properties of a class of sensory neurons, some of which innervate blood vessels. We suggest that these latter afferents may be muscle metaboreceptors, neurons that sense the metabolic state of muscle and can trigger pain when there is insufficient oxygen.

  7. ASICs Do Not Play a Role in Maintaining Hyperalgesia Induced by Repeated Intramuscular Acid Injections

    Directory of Open Access Journals (Sweden)

    Mamta Gautam

    2012-01-01

    Full Text Available Repeated intramuscular acid injections produce long-lasting mechanical hyperalgesia that depends on activation of ASICs. The present study investigated if pH-activated currents in sensory neurons innervating muscle were altered in response to repeated acid injections, and if blockade of ASICs reverses existing hyperalgesia. In muscle sensory neurons, the mean acid-evoked current amplitudes and the biophysical properties of the ASIC-like currents were unchanged following acidic saline injections when compared to neutral pH saline injections or uninjected controls. Moreover, increased mechanical sensitivity of the muscle and paw after the second acid injection was unaffected by local blockade of ASICs (A-317567 in the muscle. As a control, electron microscopic analysis showed that the tibial nerve was undamaged after acid injections. Our previous studies demonstrated that ASICs are important in the development of hyperalgesia to repeated acid injections. However, the current data suggest that ASICs are not involved in maintaining hyperalgesia to repeated intramuscular acid injections.

  8. Non-ideal effects of MOS capacitor in a switched capacitor waveform recorder ASIC

    Science.gov (United States)

    Zhang, Hong-Yan; Deng, Zhi; Liu, Yi-Nong

    2016-07-01

    SCAs (Switched Capacitor Arrays) have a wide range of uses, especially in high energy physics, nuclear science and astrophysics experiments. This paper presents a method of using a MOS capacitor as a sampling capacitor to gain larger capacitance with small capacitor area in SCA design. It studies the non-ideal effects of the MOS capacitor and comes up with ways to reduce these adverse effects. A prototype SCA ASIC which uses a MOS capacitor to store the samples has been designed and tested to verify this method. The SCA integrates 32 channels and each has 64 cells and a readout amplifier. The stored voltage is converted to a pair of differential currents (±4 mA max) and multiplexed to the output. All the functionalities have been verified. The power consumption is less than 2 mW/ch. The INL of all the cells in one channel are better than 0.39%. The equivalent input noise of the SCA has been tested to be 2.2 mV with 625 kHz full-scale sine wave as input, sampling at 40 MSPS (Mega-samples per Second) and reading out at 5 MHz. The effective resolution is 8.8 bits considering 1 V dynamic range. The maximum sampling rate reaches up to 50 MSPS and readout rate of 15 MHz to keep noise smaller than 2.5 mV. The test results validate the feasibility of the MOS capacitor. Supported by National Natural Science Foundation of China (11375100), Strategic Pioneer Program on Space Sciences, Chinese Academy of Sciences (XDA04060606-06) and State Key Laboratory of Particle Detection and Electronics

  9. PETA4: a multi-channel TDC/ADC ASIC for SiPM readout

    Science.gov (United States)

    Sacco, I.; Fischer, P.; Ritzert, M.

    2013-12-01

    The PETA4 ASIC is the latest member of a family of chips targeted mainly at the readout of Silicon Photomultipliers in PET, with possible use in other detector applications. PETA4 houses 36 channels on a 5 × 5mm2 die and is fabricated in the UMC 180nm technology. It uses bump bonds with a convenient pitch of ≈ 270μm to allow the construction of very compact modules at moderate substrate cost. The chip requires nearly no external components by integrating everything (PLL loop filter, bandgap reference, bias DACs,...) on chip. Power consumption is <= 40mW per channel, depending on digital speed and bias settings. Every channel has two independent frontends: an established differential amplifier which has shown to be insensitive to pickup in the target application of PET/MRI, and a single-ended frontend with very low input impedance (Zin ≈ 7Ω) for high channel count operation. A fast discriminator with tunable threshold and a noise of <= 300μV self-triggers time stamping with a bin width of 50ps as well as an integrator with programmable integration time. The amplitude signal is converted by a ≈ 9-bit SAR ADC. After conversion, events with sufficient amplitude are queued for serial readout. The previous chip version PETA3 has achieved a CRT time resolution of ≈ 200ps when reading out scintillation light from a 3 × 3×5mm3 LYSO crystal coupled at room temperature to a 3 × 3mm2 SiPM from FBK. Energy resolution for LYSO is ≈ 12.5%FWHM. LYSO crystals of 1.3mm size could be clearly identified with SiPMs of 4 × 4mm2 when using a light spreader. The architecture of PETA4 and its performance in the lab and with SiPMs will be presented.

  10. PETA4: a multi-channel TDC/ADC ASIC for SiPM readout

    International Nuclear Information System (INIS)

    The PETA4 ASIC is the latest member of a family of chips targeted mainly at the readout of Silicon Photomultipliers in PET, with possible use in other detector applications. PETA4 houses 36 channels on a 5 × 5mm2 die and is fabricated in the UMC 180nm technology. It uses bump bonds with a convenient pitch of ≈ 270μm to allow the construction of very compact modules at moderate substrate cost. The chip requires nearly no external components by integrating everything (PLL loop filter, bandgap reference, bias DACs,...) on chip. Power consumption is ≤ 40mW per channel, depending on digital speed and bias settings. Every channel has two independent frontends: an established differential amplifier which has shown to be insensitive to pickup in the target application of PET/MRI, and a single-ended frontend with very low input impedance (Zin ≈ 7Ω) for high channel count operation. A fast discriminator with tunable threshold and a noise of ≤ 300μV self-triggers time stamping with a bin width of 50ps as well as an integrator with programmable integration time. The amplitude signal is converted by a ≈ 9-bit SAR ADC. After conversion, events with sufficient amplitude are queued for serial readout. The previous chip version PETA3 has achieved a CRT time resolution of ≈ 200ps when reading out scintillation light from a 3 × 3×5mm3 LYSO crystal coupled at room temperature to a 3 × 3mm2 SiPM from FBK. Energy resolution for LYSO is ≈ 12.5%FWHM. LYSO crystals of 1.3mm size could be clearly identified with SiPMs of 4 × 4mm2 when using a light spreader. The architecture of PETA4 and its performance in the lab and with SiPMs will be presented

  11. Design and performance of a custom ASIC digitizer for wire chamber readout in 65 nm CMOS technology

    International Nuclear Information System (INIS)

    We present the design and performance of a prototype ASIC digitizer for integrated wire chamber readout, implemented in 65 nm commercial CMOS technology. Each channel of the 4-channel prototype is composed of two 16-bit Time-to-Digital Converters (TDCs), one 8-bit Analog-to-Digital Converter (ADC), a front-end preamplifier and shaper, plus digital and analog buffers that support a variety of digitization chains. The prototype has a multiplexed digital backend that executes a state machine, distributes control and timing signals, and buffers data for serial output. Laboratory bench tests measure the absolute TDC resolution between 74 ps and 480 ps, growing with the absolute delay, and a relative time resolution of 19 ps. Resolution outliers due to cross-talk between clock signals and supply or reference voltages are seen. After calibration, the ADC displays good linearity and noise performance, with an effective number of bits of 6.9. Under normal operating conditions the circuit consumes 32 mW per channel. Potential design improvements to address the resolution drift and tails are discussed

  12. Design and Performance of a Custom ASIC Digitizer for Wire Chamber Readout in 65 nm CMOS Technology

    CERN Document Server

    Lee, MyeongJae; Chang, Jessica K; Ding, Dawei; Gnani, Dario; Grace, Carl R; Jones, John A; Kolomensky, Yury G; von der Lippe, Henrik; Mcvittie, Patrick J; Stettler, Matthew W; Walder, Jean-Pierre

    2015-01-01

    We present the design and performance of a prototype ASIC digitizer for integrated wire chamber readout, implemented in 65 nm commercial CMOS technology. Each channel of the 4-channel prototype is composed of two 16-bit Time-to-Digital Converters (TDCs), one 8-bit Analog-to-Digital Converter (ADC), a front-end preamplifier and shaper, plus digital and analog buffers that support a variety of digitization chains. The prototype has a multiplexed digital backend that executes a state machine, distributes control and timing signals, and buffers data for serial output. Laboratory bench tests measure the absolute TDC resolution between 74 ps and 480 ps, growing with the absolute delay, and a relative time resolution of 19 ps. Resolution outliers due to cross-talk between clock signals and supply or reference voltages are seen. After calibration, the ADC displays good linearity and noise performance, with an effective number of bits of 6.9. Under normal operating conditions the circuit consumes 32 mW per channel. Po...

  13. The Human Acid-Sensing Ion Channel ASIC1a: Evidence for a Homotetrameric Assembly State at the Cell Surface

    OpenAIRE

    van Bemmelen, Miguel Xavier; Huser, Delphine; Gautschi, Ivan; Schild, Laurent

    2015-01-01

    The chicken acid-sensing ion channel ASIC1 has been crystallized as a homotrimer. We address here the oligomeric state of the functional ASIC1 in situ at the cell surface. The oligomeric states of functional ASIC1a and mutants with additional cysteines introduced in the extracellular pore vestibule were resolved on SDS-PAGE. The functional ASIC1 complexes were stabilized at the cell surface of Xenopus laevis oocytes or CHO cells either using the sulfhydryl crosslinker BMOE, or sodium tetrathi...

  14. ANUSANSKAR: a 16 channel frontend electronics (FEE) ASIC targeted for silicon pixel array detector based prototype Alice FOCAL

    International Nuclear Information System (INIS)

    ANUSANSKAR is a 16 channel pulse processing ASIC with analog multiplexed output designed in 0.7 um standard CMOS technology with each channel consisting of CSA, Semi Gaussian pulse shaper, DC cancellation and pedestal control, track and hold, output buffer blocks. The ASIC's analog multiplexed output can be read serially in daisy-chain topology. Testing, characterization and validation of ANUSANSKAR ASIC as readout for prototype ALICE forward calorimeter (FOCAL) has been carried out in PS beam line at CERN with up to 6 GeV of pion and electron beam. This paper describes the ANUSANSKAR ASIC along with the experimental results. (author)

  15. Design Specifications for a Radiation Tolerant Beam Loss Measurement ASIC

    CERN Document Server

    Venturini, G G; Effinger, E; Zamantzas, C

    2009-01-01

    A novel radiation-hardened current digitizer ASIC is in planning stage, aimed at the acquisition of the current signals from the ionization chambers employed in the Beam Loss Monitoring system at CERN. The purpose is to match and exceed the performance of the existing discrete component design, currently in operation in the Large Hadron Collider (LHC). The specifications include: a dynamic range of nine decades, defaulting to the 1 pA-1mA range but adjustable by the user, ability to withstand a total integrated dose of 10 kGy at least in 20 years of operation and user selectable integrating windows, as low as 500 ns. Moreover, the integrated circuit should be able to digitize currents of both polarity with a minimum number of external components and without needing any configuration. The target technology is the IBM 130nm CMOS process. The specifications, the architecture choices and the reasons on which they are based upon are discussed in this paper.

  16. ASIC Readout Circuit Architecture for Large Geiger Photodiode Arrays

    Science.gov (United States)

    Vasile, Stefan; Lipson, Jerold

    2012-01-01

    The objective of this work was to develop a new class of readout integrated circuit (ROIC) arrays to be operated with Geiger avalanche photodiode (GPD) arrays, by integrating multiple functions at the pixel level (smart-pixel or active pixel technology) in 250-nm CMOS (complementary metal oxide semiconductor) processes. In order to pack a maximum of functions within a minimum pixel size, the ROIC array is a full, custom application-specific integrated circuit (ASIC) design using a mixed-signal CMOS process with compact primitive layout cells. The ROIC array was processed to allow assembly in bump-bonding technology with photon-counting infrared detector arrays into 3-D imaging cameras (LADAR). The ROIC architecture was designed to work with either common- anode Si GPD arrays or common-cathode InGaAs GPD arrays. The current ROIC pixel design is hardwired prior to processing one of the two GPD array configurations, and it has the provision to allow soft reconfiguration to either array (to be implemented into the next ROIC array generation). The ROIC pixel architecture implements the Geiger avalanche quenching, bias, reset, and time to digital conversion (TDC) functions in full-digital design, and uses time domain over-sampling (vernier) to allow high temporal resolution at low clock rates, increased data yield, and improved utilization of the laser beam.

  17. VeloPix ASIC development for LHCb VELO upgrade

    CERN Document Server

    van Beuzekom, M; Campbell, M; Collins, P; Gromov, V; Kluit, R; Llopart, X; Poikela, T; Wyllie, K; Zivkovic, V

    2013-01-01

    The upgrade of the LHCb experiment, planned for 2018, will transform the readout of the entire experiment to a triggerless system operating at 40 MHz. All data reduction algorithms will be run in a high level software farm, and will have access to event information from all subdetectors. This approach will give great power and fl exibility in accessing the physics channels of interest in the future, in particular the identi fi cation of fl avour tagged events with displaced vertices. The data acquisition and front end electronics systems require signi fi cant modi fi cation to cope with the enormous throughput of data. For the silicon vertex locator (VELO) a dedicated development is underway for a new ASIC, VeloPix, which will be a derivative of the Timepix/Medipix family of chips. The chip will be radiation hard and be able to cope with pixel hit rates of above 500 MHz, highly non-uniformly distributed over the 2 cm 2 chip area. The chip will incorporate local intelligence in the pixels for time-over-thresho...

  18. FRONT-END ASIC FOR A SILICON COMPTON TELESCOPE.

    Energy Technology Data Exchange (ETDEWEB)

    DE GERONIMO,G.; FRIED, J.; FROST, E.; PHLIPS, B.; VERNON, E.; WULF, E.A.

    2007-10-27

    We describe a front-end application specific integrated circuit (ASIC) developed for a silicon Compton telescope. Composed of 32 channels, it reads out signals in both polarities from each side of a Silicon strip sensor, 2 mm thick 27 cm long, characterized by a strip capacitance of 30 pF. Each front-end channel provides low-noise charge amplification, shaping with a stabilized baseline, discrimination, and peak detection with an analog memory. The channels can process events simultaneously, and the read out is sparsified. The charge amplifier makes uses a dual-cascode configuration and dual-polarity adaptive reset, The low-hysteresis discriminator and the multi-phase peak detector process signals with a dynamic range in excess of four hundred. An equivalent noise charge (ENC) below 200 electrons was measured at 30 pF, with a slope of about 4.5 electrons/pF at a peaking time of 4 {micro}s. With a total dissipated power of 5 mW the channel covers an energy range up to 3.2 MeV.

  19. VeloPix ASIC development for LHCb VELO upgrade

    Energy Technology Data Exchange (ETDEWEB)

    Beuzekom, M. van, E-mail: martinb@nikhef.nl [Nikhef, Science Park 105, 1098 XG Amsterdam (Netherlands); Buytaert, J.; Campbell, M.; Collins, P. [CERN, 1211 Geneva 23 (Switzerland); Gromov, V.; Kluit, R. [Nikhef, Science Park 105, 1098 XG Amsterdam (Netherlands); Llopart, X. [CERN, 1211 Geneva 23 (Switzerland); Poikela, T. [University of Turku, Department of Information Technology, FI-20014 Turun yliopisto (Finland); CERN, 1211 Geneva 23 (Switzerland); Wyllie, K. [CERN, 1211 Geneva 23 (Switzerland); Zivkovic, V. [Nikhef, Science Park 105, 1098 XG Amsterdam (Netherlands)

    2013-12-11

    The upgrade of the LHCb experiment, planned for 2018, will transform the readout of the entire experiment to a triggerless system operating at 40 MHz. All data reduction algorithms will be run in a high level software farm, and will have access to event information from all subdetectors. This approach will give great power and flexibility in accessing the physics channels of interest in the future, in particular the identification of flavour tagged events with displaced vertices. The data acquisition and front end electronics systems require significant modification to cope with the enormous throughput of data. For the silicon vertex locator (VELO) a dedicated development is underway for a new ASIC, VeloPix, which will be a derivative of the Timepix/Medipix family of chips. The chip will be radiation hard and be able to cope with pixel hit rates of above 500 MHz, highly non-uniformly distributed over the 2 cm{sup 2} chip area. The chip will incorporate local intelligence in the pixels for time-over-threshold measurements, time-stamping and sparse readout. It must in addition be low power, radiation hard, and immune to single event upsets. In order to cope with the datarates and use the pixel area most effectively, an on-chip data compression scheme will integrated. This paper will describe the requirements of the LHCb VELO upgrade, and give an overview of the digital architecture being developed specifically for the readout chip.

  20. Functional and pharmacological characterization of two different ASIC1a/2a heteromers reveals their sensitivity to the spider toxin PcTx1.

    Science.gov (United States)

    Joeres, Niko; Augustinowski, Katrin; Neuhof, Andreas; Assmann, Marc; Gründer, Stefan

    2016-01-01

    Acid Sensing Ion Channels (ASICs) detect extracellular proton signals and are involved in synaptic transmission and pain sensation. ASIC subunits assemble into homo- and heteromeric channels composed of three subunits. Single molecule imaging revealed that heteromers composed of ASIC1a and ASIC2a, which are widely expressed in the central nervous system, have a flexible 2:1/1:2 stoichiometry. It was hitherto not possible, however, to functionally differentiate these two heteromers. To have a homogenous population of ASIC1a/2a heteromers with either 2:1 or 1:2 stoichiometry, we covalently linked subunits in the desired configuration and characterized their functional properties in Xenopus oocytes. We show that the two heteromers have slightly different proton affinity, with an additional ASIC1a subunit increasing apparent affinity. Moreover, we found that zinc, which potentiates ASIC2a-containing ASICs but not homomeric ASIC1a, potentiates both heteromers. Finally, we show that PcTx1, which binds at subunit-subunit interfaces of homomeric ASIC1a, inhibits both heteromers suggesting that ASIC2a can also contribute to a PcTx1 binding site. Using this functional fingerprint, we show that rat cortical neurons predominantly express the ASIC1a/2a heteromer with a 2:1 stoichiometry. Collectively, our results reveal the contribution of individual subunits to the functional properties of ASIC1a/2a heteromers. PMID:27277303

  1. Macro Pixel ASIC (MPA): the readout ASIC for the pixel-strip (PS) module of the CMS outer tracker at HL-LHC

    Science.gov (United States)

    Ceresa, D.; Marchioro, A.; Kloukinas, K.; Kaplon, J.; Bialas, W.; Re, V.; Traversi, G.; Gaioni, L.; Ratti, L.

    2014-11-01

    The CMS tracker at HL-LHC is required to provide prompt information on particles with high transverse momentum to the central Level 1 trigger. For this purpose, the innermost part of the outer tracker is based on a combination of a pixelated sensor with a short strip sensor, the so-called Pixel-Strip module (PS). The readout of these sensors is carried out by distinct ASICs, the Strip Sensor ASIC (SSA), for the strip layer, and the Macro Pixel ASIC (MPA) for the pixel layer. The processing of the data directly on the front-end module represents a design challenge due to the large data volume (30720 pixels and 1920 strips per module) and the limited power budget. This is the reason why several studies have been carried out to find the best compromise between ASICs performance and power consumption. This paper describes the current status of the MPA ASIC development where the logic for generating prompt information on particles with high transverse momentum is implemented. An overview of the readout method is presented with particular attention on the cluster reduction, position encoding and momentum discrimination logic. Concerning the architectural studies, a software test bench capable of reading physics Monte-Carlo generated events has been developed and used to validate the MPA design and to evaluate the MPA performance. The MPA-Light is scheduled to be submitted for fabrication this year and will include the full analog functions and a part of the digital logic of the final version in order to qualify the chosen VLSI technology for the analog front-end, the module assembly and the low voltage digital supply.

  2. A time-based front-end ASIC for the silicon micro strip sensors of the bar PANDA Micro Vertex Detector

    Science.gov (United States)

    Di Pietro, V.; Brinkmann, K.-Th.; Riccardi, A.; Ritman, J.; Rivetti, A.; Rolo, M. D.; Stockmanns, T.; Zambanini, A.

    2016-03-01

    The bar PANDA (Antiproton Annihilation at Darmstadt) experiment foresees many detectors for tracking, particle identification and calorimetry. Among them, the innermost is the MVD (Micro Vertex Detector) responsible for a precise tracking and the reconstruction of secondary vertices. This detector will be built from both hybrid pixel (two inner barrels and six forward disks) and double-sided micro strip (two outer barrels and outer rim of the last two disks) silicon sensors. A time-based approach has been chosen for the readout ASIC of the strip sensors. The PASTA (bar PANDA Strip ASIC) chip aims at high resolution time-stamping and charge information through the Time over Threshold (ToT) technique. It benefits from a Time to Digital Converter (TDC) allowing a time bin width down to 50 ps. The analog front-end was designed to serve both n-type and p-type strips and the performed simulations show remarkable performances in terms of linearity and electronic noise. The TDC consists of an analog interpolator, a digital local controller, and a digital global controller as the common back-end for all of the 64 channels.

  3. Characterization of the ePix100 prototype: a front-end ASIC for second-generation LCLS integrating hybrid pixel detectors

    Science.gov (United States)

    Caragiulo, P.; Dragone, A.; Markovic, B.; Herbst, R.; Nishimura, K.; Reese, B.; Herrmann, S.; Hart, P.; Blaj, G.; Segal, J.; Tomada, A.; Hasi, J.; Carini, G.; Kenney, C.; Haller, G.

    2014-09-01

    ePix100 is the first variant of a novel class of integrating pixel ASICs architectures optimized for the processing of signals in second generation LINAC Coherent Light Source (LCLS) X-Ray cameras. ePix100 is optimized for ultra-low noise application requiring high spatial resolution. ePix ASICs are based on a common platform composed of a random access analog matrix of pixel with global shutter, fast parallel column readout, and dedicated sigma-delta analog to digital converters per column. The ePix100 variant has 50μmx50μm pixels arranged in a 352x384 matrix, a resolution of 50e- r.m.s. and a signal range of 35fC (100 photons at 8keV). In its final version it will be able to sustain a frame rate of 1kHz. A first prototype has been fabricated and characterized and the measurement results are reported here.

  4. A time-based front-end ASIC for the silicon micro strip sensors of the P-bar ANDA Micro Vertex Detector

    International Nuclear Information System (INIS)

    The P-bar ANDA (Antiproton Annihilation at Darmstadt) experiment foresees many detectors for tracking, particle identification and calorimetry. Among them, the innermost is the MVD (Micro Vertex Detector) responsible for a precise tracking and the reconstruction of secondary vertices. This detector will be built from both hybrid pixel (two inner barrels and six forward disks) and double-sided micro strip (two outer barrels and outer rim of the last two disks) silicon sensors. A time-based approach has been chosen for the readout ASIC of the strip sensors. The PASTA ( P-bar ANDA Strip ASIC) chip aims at high resolution time-stamping and charge information through the Time over Threshold (ToT) technique. It benefits from a Time to Digital Converter (TDC) allowing a time bin width down to 50 ps. The analog front-end was designed to serve both n-type and p-type strips and the performed simulations show remarkable performances in terms of linearity and electronic noise. The TDC consists of an analog interpolator, a digital local controller, and a digital global controller as the common back-end for all of the 64 channels

  5. The RD27 muon trigger co-incidence array demonstrator ASIC

    International Nuclear Information System (INIS)

    One aim of the RD27 project is to perform design and R and D work leading to a first level muon trigger for an experiment at the Large Hadron Collider (LHC) at CERN. This paper describes the design, implementation and testing of an ASIC for a trigger demonstrator system. The trigger system is implemented using a set of seven chambers. The low momentum trigger requires hits in three out of the four inner chambers. The high momentum trigger requires a low momentum trigger and hits in two of three outer chambers. This scheme allows for chamber inefficiencies for real muons and reduces the trigger rate from neutron and photon-induced background in the detectors. The core of the ASIC is an eight by twenty-four input double co-incidence array allowing two momentum cuts to be applied. The ASIC has multiple inputs per axis and includes the multiplicity logic. The design of the ASIC is flexible enough to demonstrate fully combinatorial operation, fully pipelined operation, or any combination of the two. The ASIC has been fabricated using a 34K gate, 0.5microm CMOS gate array from Fujitsu. Testing confirms it can be pipelined at above 100MHz or fully combinatorial with a measured maximum propagation delay of 7.4ns, varying by up to 2ns depending on input pattern

  6. ASIC Implementation of I2C Master Bus Controller Firm IP Core

    Directory of Open Access Journals (Sweden)

    S Sindhu

    2015-08-01

    Full Text Available ASIC Implementation of I2C Master bus controller with design of Firm IP core has been proposed in this paper. I2C is one the most prominent protocol used in on chip communication among sub-systems. The generic design of I2C master controller has ample of features to incorporate vast varieties of application and I2C standards. The generic design is slow, congested and require high power. It’s rare to utilize all the features of generic design fully in a single particular application or system. Hence, a modified ASIC design with specific less features but with better timing, low power requirement and less area overhead, has been proposed in this paper. This design is specifically apt for digital systems which have serial bus interface requirement for on board communication. Moreover, the Firm IP core of I2C Master Controller has been designed for ASIC, which makes the design highly portable on any ASIC chips or SOC designs. The firm IPs is best in terms of flexibility and more predictable than commonly found soft IPs. The entire custom ASIC implementation of proposed design has been done in Cadence Tool chain with 45nm technology using standard cell library. A thorough comparison has been done between generic open sourced RTL design of I2C Controller obtained from Opencores.org and our proposed design.

  7. Atomic force microscopy imaging reveals the formation of ASIC/ENaC cross-clade ion channels

    Energy Technology Data Exchange (ETDEWEB)

    Jeggle, Pia; Smith, Ewan St. J.; Stewart, Andrew P. [Department of Pharmacology, University of Cambridge, Tennis Court Road, Cambridge CB2 1PD (United Kingdom); Haerteis, Silke; Korbmacher, Christoph [Institut für Zelluläre und Molekulare Physiologie, Friedrich-Alexander-Universität Erlangen-Nürnberg, Waldstrasse 6, 91054 Erlangen (Germany); Edwardson, J. Michael, E-mail: jme1000@cam.ac.uk [Department of Pharmacology, University of Cambridge, Tennis Court Road, Cambridge CB2 1PD (United Kingdom)

    2015-08-14

    ASIC and ENaC are co-expressed in various cell types, and there is evidence for a close association between them. Here, we used atomic force microscopy (AFM) to determine whether ASIC1a and ENaC subunits are able to form cross-clade hybrid ion channels. ASIC1a and ENaC could be co-isolated from detergent extracts of tsA 201 cells co-expressing the two subunits. Isolated proteins were incubated with antibodies against ENaC and Fab fragments against ASIC1a. AFM imaging revealed proteins that were decorated by both an antibody and a Fab fragment with an angle of ∼120° between them, indicating the formation of ASIC1a/ENaC heterotrimers. - Highlights: • There is evidence for a close association between ASIC and ENaC. • We used AFM to test whether ASIC1a and ENaC subunits form cross-clade ion channels. • Isolated proteins were incubated with subunit-specific antibodies and Fab fragments. • Some proteins were doubly decorated at ∼120° by an antibody and a Fab fragment. • Our results indicate the formation of ASIC1a/ENaC heterotrimers.

  8. A Trigger Data Serialize ASIC for the ATLAS Forward Muon Detector Upgrade

    CERN Document Server

    Wang, Jinhong; The ATLAS collaboration

    2016-01-01

    The small-strip Thin-Gap Chambers (sTGC) will be used as both trigger and precision tracking muon detectors for the Phase-I upgrade of the ATLAS New Small Wheel (NSW) muon detector. A Trigger data serializer (TDS) ASIC is required to prepare trigger data for both sTGC pad and strip detectors, perform pad-strip matching, and serializer trigger data to the circuits on the rim the rim of the NSW detector. The large number of input channels (128 differential input channels), short time available to prepare and transmit trigger data (<100 ns), high speed output data rate (4.8 Gbps), harsh radiation environment (about 300 kRad), and low power consumption (<1 W) all impose great challenges for the design of this ASIC using the IBM 130 nm CMOS process. We present our design and consderation of the TDS ASIC and the first prototype we built

  9. Test beam analysis of ultra-thin hybrid pixel detector assemblies with Timepix readout ASICs

    CERN Document Server

    Alipour Tehrani, Niloufar; Dannheim, Dominik; Firu, Elena; Kulis, Szymon; Redford, Sophie; Sicking, Eva

    2016-01-01

    The requirements for the vertex detector at the proposed Compact Linear Collider imply a very small material budget: less than 0.2% of a radiation length per detection layer including services and mechanical supports. We present here a study using Timepix readout ASICs hybridised to pixel sensors of 50 − 500 μm thickness, including assemblies with 100 μm thick sensors bonded to thinned 100μm thick ASICs. Sensors from three producers (Advacam, Micron Semiconductor Ltd, Canberra) with different edge termination technologies (active edge, slim edge) were bonded to Timepix ASICs. These devices were characterised with the EUDET telescope at the DESY II test beam using 5.6 GeV electrons. Their performance for the detection and tracking of minimum ionising particles was evaluated in terms of charge sharing, detection efficiency, single-point resolution and energy deposition.

  10. Development of an SOI analog front-end ASIC for X-ray charge coupled devices

    International Nuclear Information System (INIS)

    The FD-SOI technology is a fascinating LSI fabrication process as a possible radiation-tolerant device. In order to confirm benefits of the FD-SOI and expand application ranges in front-end electronics, we experimentally designed an analog front-end ASIC for X-ray CCD readout with the FD-SOI process. The circuit design was submitted to OKI Semiconductor Co., Ltd. via the multi-chip project as a part of the SOI pixel-detector R and D program in KEK. The ASIC contains seven readout channels using the correlated double sampling technique, and includes key circuit elements for a low-noise LSI. This paper describes the circuit design and the performance of the ASIC together with the radiation tolerance.

  11. A Low-Power ASIC Signal Processor for a Vestibular Prosthesis.

    Science.gov (United States)

    Töreyin, Hakan; Bhatti, Pamela T

    2016-06-01

    A low-power ASIC signal processor for a vestibular prosthesis (VP) is reported. Fabricated with TI 0.35 μm CMOS technology and designed to interface with implanted inertial sensors, the digitally assisted analog signal processor operates extensively in the CMOS subthreshold region. During its operation the ASIC encodes head motion signals captured by the inertial sensors as electrical pulses ultimately targeted for in-vivo stimulation of vestibular nerve fibers. To achieve this, the ASIC implements a coordinate system transformation to correct for misalignment between natural sensors and implanted inertial sensors. It also mimics the frequency response characteristics and frequency encoding mappings of angular and linear head motions observed at the peripheral sense organs, semicircular canals and otolith. Overall the design occupies an area of 6.22 mm (2) and consumes 1.24 mW when supplied with ± 1.6 V. PMID:26800546

  12. Wavelength converter technology

    DEFF Research Database (Denmark)

    Kloch, Allan; Hansen, Peter Bukhave; Poulsen, Henrik Nørskov;

    1999-01-01

    Wavelength conversion is important since it ensures full flexibility of the WDM network layer. Progress in optical wavelength converter technology is reviewed with emphasis on air-optical wavelength converter types based on semiconductor optical amplifiers....

  13. A low noise ASIC for two dimensional neutron gas detector with performance of high spatial resolution (Contract research)

    International Nuclear Information System (INIS)

    An ASD-ASIC (Amplifier-Shaper-Discriminator ASIC) with fast response and low noise performances has been designed for two-dimensional position sensitive neutron gas detectors (InSPaD). The InSPaD is a 2D neutron detector system with 3He gas and provides a high spatial resolution by making distinction between proton and triton particles generated in the gas chamber. The new ASD-ASIC is required to have very low noise, a wide dynamic range, good output linearity and high counting rate. The new ASD-ASIC has been designed by using CMOS and consisted of 64-channel ASDs, a 16-channel multiplexer with LVTTL drivers and sum amplifier system for summing all analog signals. The performances were evaluated by the Spice simulation. It was confirmed that the new ASD-ASIC had very low noise performance, wide dynamic range and fast signal processing functions. (author)

  14. Development and experimental study of the readout ASIC for muon chambers of the CBM experiment

    International Nuclear Information System (INIS)

    The measurement results of the front-end ASIC for the GEM detector read-out are presented. The MUCH ASIC v2 was designed and prototyped via Europractice by means of the 0.18 um CMOS MMRF process of UMC (Taiwan). The parameters of the analog channels, including the CSA, fast and slow shapers, discriminators, were measured. The channels provide a sufficient dynamic range of 100 fC, low power consumption of 10 mW per channel and ENC of 1550 el at a 50 pF detector capacitance

  15. Channel control ASIC for the CMS hadron calorimeter front end readout module

    International Nuclear Information System (INIS)

    The Channel Control ASIC (CCA) is used along with a custom Charge Integrator and Encoder (QIE) ASIC to digitize signals from the hybrid photo diodes (HPDs) and photomultiplier tubes (PMTs) in the CMS hadron calorimeter. The CCA sits between the QIE and the data acquisition system. All digital signals to and from the QIE pass through the CCA chip. One CCA chip interfaces with two QIE channels. The CCA provides individually delayed clocks to each of the QIE chips in addition to various control signals. The QIE sends digitized PMT or HPD signals and time slice information to the CCA, which sends the data to the data acquisition system through an optical link

  16. Wavelength converter technology

    DEFF Research Database (Denmark)

    Kloch, Allan; Hansen, Peter Bukhave; Poulsen, Henrik Nørskov; Wolfson, David; Jepsen, Kim Stokholm; Clausen, Anders; Limal, Emmanuel; Buxens, Alvaro A.

    Wavelength conversion is important since it ensures full flexibility of the WDM network layer. Progress in optical wavelength converter technology is reviewed with emphasis on air-optical wavelength converter types based on semiconductor optical amplifiers.......Wavelength conversion is important since it ensures full flexibility of the WDM network layer. Progress in optical wavelength converter technology is reviewed with emphasis on air-optical wavelength converter types based on semiconductor optical amplifiers....

  17. The GBT-SCA, a radiation tolerant ASIC for detector control applications in SLHC experiments

    CERN Document Server

    Gabrielli, A; Kloukinas, K; Marchioro, A; Moreira, P; Ranieri, A; De Robertis, D

    2009-01-01

    This work describes the architecture of the GigaBit Transceiver – Slow Control Adapter (GBT–SCA) ASIC suitable for the control and monitoring applications of the embedded front-end electronics in the future SLHC experiments. The GBT–SCA is part the GBT chipset currently under development for the SLHC detector upgrades. It is designed for radiation tolerance and it will be fabricated in a commercial 130 nm CMOS technology. The paper discusses the GBT-SCA architecture, the data transfer protocol, the ASIC interfaces, and its integration with the GBT optical link. The GBT–SCA is one the components of the GBT system chipset. It is proposed for the future SLHC experiments and is designed to be configurable matching different front-end system requirements. The GBT-SCA is intended for the slow control and monitoring of the embedded front end electronics and implements a point-to-multi point connection between one GBT optical link ASIC and several front end ASICs. The GBT-SCA connects to a dedicated electrica...

  18. Development of advanced I and C in nuclear power plants: ADIOS and ASICS

    International Nuclear Information System (INIS)

    In this paper Automatic Startup Intelligent Control System (ASICS) that automatically controls the PWR plant from cold shutdown to 5% of reactor power and Alarm and Diagnosis-Integrated Operator Support System (ADIOS) that is integrated with alarms, process values, and diagnostic information to an expert system focused on alarm processing are described. Nuclear Power Plant is manually controlled from cold shutdown to 5% according to the general operation procedures for startup operation of nuclear power plant. Alarm information is the primary sources to detect abnormalities in nuclear power plants or other process plants. The conventional hardwired alarm systems, characterized by one sensor-one indicator may lead the control room operators to be confused with avalanching alarms during plant transients. ASICS and ADIOS are designed to reduce the operator burden. The advances in computer software and hardware technology and also in information processing provide a good opportunity to improve the control systems and the annunciator systems of nuclear power plants or other similar process plants. It is very important to test and evaluate the performance and the function of the computer- or software-based systems like ASICS and ADIOS. The performance and the function of ASICS and ADIOS are evaluated with the real-time functional test facility and the results have shown that the developed systems are efficient and useful for operation and operator support

  19. Development of advanced I and C in nuclear power plants: ADIOS and ASICS

    Energy Technology Data Exchange (ETDEWEB)

    Kim, Jung-Taek E-mail: jtkim@nanum.kaeri.re.kr; Kwon, Kee-Choon; Hwang, In-Koo; Lee, Dong-Young; Park, Won-Man; Kim, Jung-Soo; Lee, Sang-Jeong

    2001-07-01

    In this paper Automatic Startup Intelligent Control System (ASICS) that automatically controls the PWR plant from cold shutdown to 5% of reactor power and Alarm and Diagnosis-Integrated Operator Support System (ADIOS) that is integrated with alarms, process values, and diagnostic information to an expert system focused on alarm processing are described. Nuclear Power Plant is manually controlled from cold shutdown to 5% according to the general operation procedures for startup operation of nuclear power plant. Alarm information is the primary sources to detect abnormalities in nuclear power plants or other process plants. The conventional hardwired alarm systems, characterized by one sensor-one indicator may lead the control room operators to be confused with avalanching alarms during plant transients. ASICS and ADIOS are designed to reduce the operator burden. The advances in computer software and hardware technology and also in information processing provide a good opportunity to improve the control systems and the annunciator systems of nuclear power plants or other similar process plants. It is very important to test and evaluate the performance and the function of the computer- or software-based systems like ASICS and ADIOS. The performance and the function of ASICS and ADIOS are evaluated with the real-time functional test facility and the results have shown that the developed systems are efficient and useful for operation and operator support.

  20. A Wireless Capsule Endoscope System With Low-Power Controlling and Processing ASIC.

    Science.gov (United States)

    Xinkai Chen; Xiaoyu Zhang; Linwei Zhang; Xiaowen Li; Nan Qi; Hanjun Jiang; Zhihua Wang

    2009-02-01

    This paper presents the design of a wireless capsule endoscope system. The proposed system is mainly composed of a CMOS image sensor, a RF transceiver and a low-power controlling and processing application specific integrated circuit (ASIC). Several design challenges involving system power reduction, system miniaturization and wireless wake-up method are resolved by employing optimized system architecture, integration of an area and power efficient image compression module, a power management unit (PMU) and a novel wireless wake-up subsystem with zero standby current in the ASIC design. The ASIC has been fabricated in 0.18-mum CMOS technology with a die area of 3.4 mm * 3.3 mm. The digital baseband can work under a power supply down to 0.95 V with a power dissipation of 1.3 mW. The prototype capsule based on the ASIC and a data recorder has been developed. Test result shows that proposed system architecture with local image compression lead to an average of 45% energy reduction for transmitting an image frame. PMID:23853159

  1. FRONT-END ASIC FOR HIGH RESOLUTION X-RAY SPECTROMETERS

    International Nuclear Information System (INIS)

    We present an application specific integrated circuit (ASIC) for high-resolution x-ray spectrometers. The ASIC is designed to read out signals from a pixelated silicon drift detector (SDD). Each hexagonal pixel has an area of 15 mmz and an anode capacitance of less than 100 fF. There is no integrated Field Effect transistor (FET) in the pixel, rather, the readout is done by wirebonding the anodes to the inputs of the ASIC. The ASIC provides 14 channels of low-noise charge amplification, high-order shaping with baseline stabilization, and peak detection with analog memory. The readout is sparse and based on low voltage differential signaling. An interposer provides all the interconnections required to bias and operate the system. The channel dissipates 1.6 mW. The complete 14-pixel unit covers an area of 210 mm2, dissipates 12 mW cm-2, and can be tiled to cover an arbitrarily large detection area. We measured a preliminary resolution of 172 eV at -35 C on the 6 keV peak of a 55Fe source

  2. Controller and data acquisition system for SIDECAR ASIC driven HAWAII detectors

    Science.gov (United States)

    Ramaprakash, Anamparambu; Burse, Mahesh; Chordia, Pravin; Chillal, Kalpesh; Kohok, Abhay; Mestry, Vilas; Punnadi, Sujit; Sinha, Sakya

    2010-07-01

    SIDECAR is an Application Specific Integrated Circuit (ASIC), which can be used for control and data acquisition from near-IR HAWAII detectors offered by Teledyne Imaging Sensors (TIS), USA. The standard interfaces provided by Teledyne are COM API and socket servers running under MS Windows platform. These interfaces communicate to the ASIC (and the detector) through an intermediate card called JWST ASIC Drive Electronics (JADE2). As part of an ongoing programme of several years, for developing astronomical focal plane array (CCDs, CMOS and Hybrid) controllers and data acquisition systems (CDAQs), IUCAA is currently developing the next generation controllers employing Virtex-5 family FPGA devices. We present here the capabilities which are built into these new CDAQs for handling HAWAII detectors. In our system, the computer which hosts the application programme, user interface and device drivers runs on a Linux platform. It communicates through a hot-pluggable USB interface (with an optional optical fibre extender) to the FPGA-based card which replaces the JADE2. The FPGA board in turn, controls the SIDECAR ASIC and through it a HAWAII-2RG detector, both of which are located in a cryogenic test Dewar set up which is liquid nitrogen cooled. The system can acquire data over 1, 4, or 32 readout channels, with or without binning, at different speeds, can define sub-regions for readout, offers various readout schemes like Fowler sampling, up-theramp etc. In this paper, we present the performance results obtained from a prototype system.

  3. FRONT-END ASIC FOR HIGH RESOLUTION X-RAY SPECTROMETERS.

    Energy Technology Data Exchange (ETDEWEB)

    DE GERONIMO,G.; CHEN, W.; FRIED, J.; LI, Z.; PINELLI, D.A.; REHAK, P.; VERNON, E.; GASKIN, J.A.; RAMSEY, B.D.; ANELLI, G.

    2007-10-27

    We present an application specific integrated circuit (ASIC) for high-resolution x-ray spectrometers. The ASIC is designed to read out signals from a pixelated silicon drift detector (SDD). Each hexagonal pixel has an area of 15 mmz and an anode capacitance of less than 100 fF. There is no integrated Field Effect transistor (FET) in the pixel, rather, the readout is done by wirebonding the anodes to the inputs of the ASIC. The ASIC provides 14 channels of low-noise charge amplification, high-order shaping with baseline stabilization, and peak detection with analog memory. The readout is sparse and based on low voltage differential signaling. An interposer provides all the interconnections required to bias and operate the system. The channel dissipates 1.6 mW. The complete 14-pixel unit covers an area of 210 mm{sup 2}, dissipates 12 mW cm{sup -2}, and can be tiled to cover an arbitrarily large detection area. We measured a preliminary resolution of 172 eV at -35 C on the 6 keV peak of a {sup 55}Fe source.

  4. A high speed Sorting Processor ASIC for the RPC Trigger system of the CMS experiment

    CERN Document Server

    De Robertis, G; Ranieri, A

    1999-01-01

    The design of a high speed Sorting Processor ASIC is presented. It was designed in BiCMOS 0.8 mu m technology and its aim is to reorder and provide the four highest words among eight input words, in decreasing order. This chip is the main component of the sorting tree of the Trigger Muon System of the CMS experiment.

  5. A high speed Sorting Processor ASIC for the RPC Trigger system of the CMS experiment

    Energy Technology Data Exchange (ETDEWEB)

    De Robertis, G.; Loddo, F. E-mail: flavio.loddo@ba.infn.it; Ranieri, A

    1999-11-01

    The design of a high speed Sorting Processor ASIC is presented. It was designed in BiCMOS 0.8 {mu}m technology and its aim is to reorder and provide the four highest words among eight input words, in decreasing order. This chip is the main component of the sorting tree of the Trigger Muon System of the CMS experiment.

  6. A high speed Sorting Processor ASIC for the RPC Trigger system of the CMS experiment

    International Nuclear Information System (INIS)

    The design of a high speed Sorting Processor ASIC is presented. It was designed in BiCMOS 0.8 μm technology and its aim is to reorder and provide the four highest words among eight input words, in decreasing order. This chip is the main component of the sorting tree of the Trigger Muon System of the CMS experiment

  7. A DES ASIC Suitable for Network Encryption at 10 Gbps and Beyond

    International Nuclear Information System (INIS)

    The Sandia National Laboratories (SNL) Data Encryption Standard (DES) Application Specific Integrated Circuit (ASIC) is the fastest known implementation of the DES algorithm as defined in the Federal Information Processing Standards (FIPS) Publication 46-2. DES is used for protecting data by cryptographic means. The SNL DES ASIC, over 10 times faster than other currently available DES chips, is a high-speed, filly pipelined implementation offering encryption, decryption, unique key input, or algorithm bypassing on each clock cycle. Operating beyond 105 MHz on 64 bit words, this device is capable of data throughputs greater than 6.7 Billion bits per second (tester limited). Simulations predict proper operation up to 9.28 Billion bits per second. In low frequency, low data rate applications, the ASIC consumes less that one milliwatt of power. The device has features for passing control signals synchronized to throughput data. Three SNL DES ASICS may be easily cascaded to provide the much greater security of triple-key, triple-DES

  8. ITER convertible blanket evaluation

    International Nuclear Information System (INIS)

    Proposed International Thermonuclear Experimental Reactor (ITER) convertible blankets were reviewed. Key design difficulties were identified. A new particle filter concept is introduced and key performance parameters estimated. Results show that this particle filter concept can satisfy all of the convertible blanket design requirements except the generic issue of Be blanket lifetime. If the convertible blanket is an acceptable approach for ITER operation, this particle filter option should be a strong candidate

  9. The photoelectric displacement converter

    Science.gov (United States)

    Dragoner, Valeriu V.

    2005-02-01

    In the article are examined questions of constructing photoelectric displacement converter satisfying demands that are stated above. Converter has channels of approximate and precise readings. The approximate reading may be accomplished either by the method of reading from a code mask or by the method of the consecutive calculation of optical scale gaps number. Phase interpolator of mouar strips" gaps is determined as a precise measuring. It is shown mathematical model of converter that allow evaluating errors and operating speed of conversion.

  10. Low-power digital ASIC for on-chip spectral analysis of low-frequency physiological signals

    Institute of Scientific and Technical Information of China (English)

    Nie Zedong; Zhang Fengjuan; Li Jie; Wang Lei

    2012-01-01

    A digital ASIC chip customized for battery-operated body sensing devices is presented.The ASIC incorporates a novel hybrid-architecture fast Fourier transform (FFT) unit that is capable of scalable spectral analysis,a licensed ARM7TDMI IP hardcore and several peripheral IP blocks.Extensive experimental results suggest that the complete chip works as intended.The power consumption of the FFT unit is 0.69 mW @ 1 MHz with 1.8 V power supply.The low-power and programmable features of the ASIC make it suitable for ‘on-the-fly' low-frequency physiological signal processing.

  11. ASIC1-mediated calcium entry stimulates NFATc3 nuclear translocation via PICK1 coupling in pulmonary arterial smooth muscle cells.

    Science.gov (United States)

    Gonzalez Bosc, Laura V; Plomaritas, Danielle R; Herbert, Lindsay M; Giermakowska, Wieslawa; Browning, Carly; Jernigan, Nikki L

    2016-07-01

    The development of chronic hypoxia (CH)-induced pulmonary hypertension is associated with increased pulmonary arterial smooth muscle cell (PASMC) Ca(2+) influx through acid-sensing ion channel-1 (ASIC1) and activation of the Ca(2+)/calcineurin-dependent transcription factor known as nuclear factor of activated T-cells isoform c3 (NFATc3). Whether Ca(2+) influx through ASIC1 contributes to NFATc3 activation in the pulmonary vasculature is unknown. Furthermore, both ASIC1 and calcineurin have been shown to interact with the scaffolding protein known as protein interacting with C kinase-1 (PICK1). In the present study, we tested the hypothesis that ASIC1 contributes to NFATc3 nuclear translocation in PASMC in a PICK1-dependent manner. Using both ASIC1 knockout (ASIC1(-/-)) mice and pharmacological inhibition of ASIC1, we demonstrate that ASIC1 contributes to CH-induced (1 wk at 380 mmHg) and endothelin-1 (ET-1)-induced (10(-7) M) Ca(2+) responses and NFATc3 nuclear import in PASMC. The interaction between ASIC1/PICK1/calcineurin was shown using a Duolink in situ Proximity Ligation Assay. Inhibition of PICK1 by using FSC231 abolished ET-1-induced and ionomycin-induced NFATc3 nuclear import, but it did not alter ET-1-mediated Ca(2+) responses, suggesting that PICK1 acts downstream of Ca(2+) influx. The key findings of the present work are that 1) Ca(2+) influx through ASIC1 mediates CH- and ET-1-induced NFATc3 nuclear import and 2) the scaffolding protein PICK1 is necessary for NFATc3 nuclear import. Together, these data provide an essential link between CH-induced ASIC1-mediated Ca(2+) influx and activation of the NFATc3 transcription factor. Identification of this ASIC1/PICK1/NFATc3 signaling complex increases our understanding of the mechanisms contributing to the vascular remodeling and increased vascular contractility that are associated with CH-induced pulmonary hypertension. PMID:27190058

  12. Differential regulation of proton-sensitive ion channels by phospholipids: a comparative study between ASICs and TRPV1.

    Directory of Open Access Journals (Sweden)

    Hae-Jin Kweon

    Full Text Available Protons are released in pain-generating pathological conditions such as inflammation, ischemic stroke, infection, and cancer. During normal synaptic activities, protons are thought to play a role in neurotransmission processes. Acid-sensing ion channels (ASICs are typical proton sensors in the central nervous system (CNS and the peripheral nervous system (PNS. In addition to ASICs, capsaicin- and heat-activated transient receptor potential vanilloid 1 (TRPV1 channels can also mediate proton-mediated pain signaling. In spite of their importance in perception of pH fluctuations, the regulatory mechanisms of these proton-sensitive ion channels still need to be further investigated. Here, we compared regulation of ASICs and TRPV1 by membrane phosphoinositides, which are general cofactors of many receptors and ion channels. We observed that ASICs do not require membrane phosphatidylinositol 4-phosphate (PI(4P or phosphatidylinositol 4,5-bisphosphate (PI(4,5P2 for their function. However, TRPV1 currents were inhibited by simultaneous breakdown of PI(4P and PI(4,5P2. By using a novel chimeric protein, CF-PTEN, that can specifically dephosphorylate at the D3 position of phosphatidylinositol 3,4,5-trisphosphate (PI(3,4,5P3, we also observed that neither ASICs nor TRPV1 activities were altered by depletion of PI(3,4,5P3 in intact cells. Finally, we compared the effects of arachidonic acid (AA on two proton-sensitive ion channels. We observed that AA potentiates the currents of both ASICs and TRPV1, but that they have different recovery aspects. In conclusion, ASICs and TRPV1 have different sensitivities toward membrane phospholipids, such as PI(4P, PI(4,5P2, and AA, although they have common roles as proton sensors. Further investigation about the complementary roles and respective contributions of ASICs and TRPV1 in proton-mediated signaling is necessary.

  13. Coupled FPGA/ASIC Implementation of Elliptic Curve Crypto-Processor

    OpenAIRE

    Mohsen Machhout; Zied Guitouni; Kholdoun Torki; Lazhar Khriji; Rached Tourki

    2010-01-01

    In this paper, we propose an elliptic curve key generation processor over GF(2163) scheme based on the Montgomery scalar multiplication algorithm. The new architecture is performed using polynomial basis.The Finite Field operations use a cellular automata multiplier and Fermat algorithm for inversion. For real time implementation, the architecture has been tested on an ISE 9.1 Software using Xilinx Virtex II Pro FPGA and on an ASIC CMOS 45 nm technology as well. The proposed implementation pr...

  14. CLARO-CMOS, a very low power ASIC for fast photon counting with pixellated photodetectors

    OpenAIRE

    Carniti, Paolo; De Matteis, Marcello; Giachero, Andrea; Gotti, Claudio; Maino, Matteo; Pessina, Gianluigi

    2012-01-01

    The CLARO-CMOS is an application specific integrated circuit (ASIC) designed for fast photon counting with pixellated photodetectors such as multi-anode photomultiplier tubes (Ma-PMT), micro-channel plates (MCP), and silicon photomultipliers (SiPM). The first prototype has four channels, each with a charge sensitive amplifier with settable gain and a discriminator with settable threshold, providing fast hit information for each channel independently. The design was realized in a long-establis...

  15. Improving Power Converter Reliability

    DEFF Research Database (Denmark)

    Ghimire, Pramod; de Vega, Angel Ruiz; Beczkowski, Szymon;

    2014-01-01

    is measured in a wind power converter at a low fundamental frequency. To illustrate more, the test method as well as the performance of the measurement circuit are also presented. This measurement is also useful to indicate failure mechanisms such as bond wire lift-off and solder layer degradation......The real-time junction temperature monitoring of a high-power insulated-gate bipolar transistor (IGBT) module is important to increase the overall reliability of power converters for industrial applications. This article proposes a new method to measure the on-state collector?emitter voltage of a...... high-power IGBT module during converter operation, which may play a vital role in improving the reliability of the power converters. The measured voltage is used to estimate the module average junction temperature of the high and low-voltage side of a half-bridge IGBT separately in every fundamental...

  16. Converting Nonclassicality into Entanglement.

    Science.gov (United States)

    Killoran, N; Steinhoff, F E S; Plenio, M B

    2016-02-26

    Quantum mechanics exhibits a wide range of nonclassical features, of which entanglement in multipartite systems takes a central place. In several specific settings, it is well known that nonclassicality (e.g., squeezing, spin squeezing, coherence) can be converted into entanglement. In this work, we present a general framework, based on superposition, for structurally connecting and converting nonclassicality to entanglement. In addition to capturing the previously known results, this framework also allows us to uncover new entanglement convertibility theorems in two broad scenarios, one which is discrete and one which is continuous. In the discrete setting, the classical states can be any finite linearly independent set. For the continuous setting, the pertinent classical states are "symmetric coherent states," connected with symmetric representations of the group SU(K). These results generalize and link convertibility properties from the resource theory of coherence, spin coherent states, and optical coherent states, while also revealing important connections between local and nonlocal pictures of nonclassicality. PMID:26967398

  17. Radio-isotope converter

    International Nuclear Information System (INIS)

    Due to the surface power density required for thermoelectric and thermionic converters, available radioactive sources are surveyed and listed. Curves of specific minimum diameter versus thermal flux density are given. 210Po and 242Cm appear to be suitable for direct thermionic when alpha emitters such as 238Pu and 244Cm are still suitable for thermoelectric conversion. This mode will also work with beta emitters 170Tm, 90Sr, 144Ce and 137Cs. Some thermoelectric radioisotope heated converters are suggested. (authors)

  18. Thermionic photovoltaic energy converter

    Science.gov (United States)

    Chubb, D. L. (Inventor)

    1985-01-01

    A thermionic photovoltaic energy conversion device comprises a thermionic diode mounted within a hollow tubular photovoltaic converter. The thermionic diode maintains a cesium discharge for producing excited atoms that emit line radiation in the wavelength region of 850 nm to 890 nm. The photovoltaic converter is a silicon or gallium arsenide photovoltaic cell having bandgap energies in this same wavelength region for optimum cell efficiency.

  19. A New Design Reuse Approach for Voip Implementation into Fpsocs and ASICS

    Directory of Open Access Journals (Sweden)

    Fatiha Louiz

    2013-11-01

    Full Text Available The aim of this paper is to present a newdesignreuse approachforautomatic generation ofVoice overInternet protocol (VOIPhardware description andimplementation intoFPSOCs and ASICs.Ourmotivation behind this work is justified by the following arguments:first,VOIP based System on chip(SOC implementation is an emergingresearch and development area, whereinnovativeapplications canbe implemented. Second,these systems are very complex and due to time to market pressure, there is a needto built platforms that help the designer to explore with different architectural possibilities and choose thecircuit that best correspond to the specifications. Third,we aim to develop in hardware,design,methodsand tools that are used in softwarelike the MATLAB tool for VOIP implementation.To achieve our goal,the proposed design approach is basedon a modular design of the VOIP architecture. The originality ofour approach is the application of the design for reuse (DFR and the design with reuse (DWR concepts.To validate the approach, a case study of a SOC based on the OR1K processor is studied.Wedemonstratethat theproposedSoCarchitecture isreconfigurable, scalable and the final RTL code can be reused forany FPSOCor ASIC technology.As an example,Performances measures, in the VIRTEX-5 FPGA devicefamily,and ASIC 65nm technology are shown through this paper

  20. A new front-end ASIC for GEM detectors with time and charge measurement capabilities

    Science.gov (United States)

    Ciciriello, F.; Corsi, F.; De Robertis, G.; Felici, G.; Loddo, F.; Marzocca, C.; Matarrese, G.; Ranieri, A.

    2016-07-01

    A 32 channel CMOS front-end ASIC has been designed to read out the GEM detectors intended to be used for beam monitoring in a new proton-therapy facility currently under construction. In order to improve the spatial resolution by exploiting charge centroid algorithms, the analog channels, based on the classic CSA+shaper architecture, are equipped with a peak detector (PD) which works as an analog memory during the read-out phase. The outputs of the PDs are multiplexed towards an integrated 8-bit subranging ADC. An accurate trigger signal marks the arrival of a valid event and is generated by fast-ORing the outputs of 32 voltage discriminators which compare the shaper outputs with a programmable threshold. The digital part of the ASIC manages the read-out of the channels, the A/D conversion and the configuration of the ASIC. A 100 Mbit/s LVDS serial link is used for data communication. The sensitivity of the analog channel is 15 mV/fC and the dynamic range is 80 fC. The simulated ENC is about 650 e- for a detector capacitance of 10 pF. © 2001 Elsevier Science. All rights reserved

  1. Hierarchical Test Development and Design-For for (a)synchronous Semi-Custom Asics.

    Science.gov (United States)

    Leenstra, Jentje

    The research, described in this thesis, deals in particular with several problems, which arise when trying to automate the process of testing low-volume semi-custom ASICs. For low-volume ASICs one of the major problems is the reduction of the test application costs. To reduce the costs of testing low-volume ASICs, the use of a semi -custom test method with associated design-for-testability techniques is proposed. To be able to start the detection and removal of testability problems during the design, a novel automated hierarchical test program development procedure is presented. It is shown how, by generating a test specification for each hierarchical module, the test program can be developed incrementally. As a result, the testability of each module becomes known and it circumvents the need to generate a complete new test program after changes. To reduce the ASIC test time, the hierarchical test development approach supports the synthesis of a reconfigurable scan path. Thereby, our novel scan path architecture circumvents the need to introduce explicit test controllers by simply loading the reconfiguration information through the scan path itself. Since the hierarchical ASIC test development method as well as the semi-custom test method requires that all test vectors can be applied through a synchronous (reconfigurable) scan path, it is also investigate how asynchronous control circuits can be designed in such a way that they are synchronously scan testable. An implementation model is presented, that uses an explicit stale register composed of SR flip-flops. It is shown that these controllers are synchronously testable and can be derived directly from a state diagram description. Finally, the possibility of using a dedicated test generation procedure is illustrated by showing how the test program for modules composed of a data path and a finite state machine controller can be derived by the use of a novel symbolic test assembly procedure. The automated

  2. Radiation Hardened Structured ASIC Platform for Rapid Chip Development for Very High Speed System on a Chip (SoC) and Complex Digital Logic Systems Project

    Data.gov (United States)

    National Aeronautics and Space Administration — Radiation Hardened Application Specific Integrated Circuits (ASICs) provide for the highest performance, lowest power and size for Space Missions. In order to...

  3. σ-1 Receptor Inhibition of ASIC1a Channels is Dependent on a Pertussis Toxin-Sensitive G-Protein and an AKAP150/Calcineurin Complex.

    Science.gov (United States)

    Mari, Yelenis; Katnik, Christopher; Cuevas, Javier

    2015-10-01

    ASIC1a channels play a major role in various pathophysiological conditions including depression, anxiety, epilepsy, and neurodegeneration following ischemic stroke. Sigma-1 (σ-1) receptor stimulation depresses the activity of ASIC1a channels in cortical neurons, but the mechanism(s) by which σ-1 receptors exert their influence on ASIC1a remains unknown. Experiments were undertaken to elucidate the signaling cascade linking σ-1 receptors to ASIC1a channels. Immunohistochemical studies showed that σ-1 receptors, ASIC1a and A-kinase anchoring peptide 150 colocalize in the plasma membrane of the cell body and processes of cortical neurons. Fluorometric Ca(2+) imaging experiments showed that disruption of the macromolecular complexes containing AKAP150 diminished the effects of the σ-1 on ASIC1a, as did application of the calcineurin inhibitors, cyclosporin A and FK-506. Moreover, whole-cell patch clamp experiments showed that σ-1 receptors were less effective at decreasing ASIC1a-mediated currents in the presence of the VIVIT peptide, which binds to calcineurin and prevents cellular effects dependent on AKAP150/calcineurin interaction. The coupling of σ-1 to ASIC1a was also disrupted by preincubation of the neurons in the G-protein inhibitor, pertussis toxin (PTX). Taken together, our data reveal that σ-1 receptor block of ASIC1a function is dependent on activation of a PTX-sensitive G-protein and stimulation of AKAP150 bound calcineurin. PMID:24925261

  4. SSG Wave Energy Converter

    DEFF Research Database (Denmark)

    Margheritini, Lucia; Vicinanza, Diego; Frigaard, Peter

    2008-01-01

    The SSG (Sea Slot-cone Generator) is a wave energy converter of the overtopping type. The structure consists of a number of reservoirs one on the top of each others above the mean water level, in which the water of incoming waves is stored temporary. In each reservoir, expressively designed low...... head hydroturbines are converting the potential energy of the stored water into power. A key to success for the SSG will be the low cost of the structure and its robustness. The construction of the pilot plant is scheduled and this paper aims to describe the concept of the SSG wave energy converter and...... the studies behind the process that leads to its construction. The pilot plant is an on-shore full scale module in 3 levels with an expected power production of 320 MWh/y in the North Sea. Location, wave climate and laboratory tests results will be used here to describe the pilot plant and its...

  5. Angiotensin-converting enzyme

    DEFF Research Database (Denmark)

    Sørensen, P G; Rømer, F K; Cortes, D

    1984-01-01

    In order to evaluate bleomycin-associated lung damage in humans, lung function parameters and serum levels of the endothelial-bound angiotensin-converting enzyme (ACE) were determined by serial measurements in 11 patients who were treated for testicular cancer. None developed clinical or radiolog......In order to evaluate bleomycin-associated lung damage in humans, lung function parameters and serum levels of the endothelial-bound angiotensin-converting enzyme (ACE) were determined by serial measurements in 11 patients who were treated for testicular cancer. None developed clinical or...

  6. Conformational changes in the lower palm domain of ASIC1a contribute to desensitization and RFamide modulation.

    Directory of Open Access Journals (Sweden)

    Erin N Frey

    Full Text Available Acid-sensing ion channel 1a (ASIC1a is a proton-gated cation channel that contributes to fear and pain as well as neuronal damage following persistent cerebral acidosis. Neuropeptides can affect acid-induced neuronal injury by altering ASIC1a inactivation and/or steady-state desensitization. Yet, exactly how ASIC1a inactivation and desensitization occur or are modulated by peptides is not completely understood. We found that regions of the extracellular palm domain and the β(11-12 linker are important for inactivation and steady-state desensitization of ASIC1a. The single amino acid substitutions L280C and L415C dramatically enhanced the rate of inactivation and altered the pH-dependence of steady-state desensitization. Further, the use of methanethiosulfonate (MTS reagents suggests that the lower palm region (L280C undergoes a conformational change when ASIC1a transitions from closed to desensitized. We determined that L280C also displays an altered response to the RFamide peptide, FRRFamide. Further, the presence of FRRFamide limited MTS modification of L280C. Together, these results indicate a potential role of the lower palm domain in peptide modulation and suggest RFamide-related peptides promote conformational changes within this region. These data provide empirical support for the idea that L280, and likely this region of the central vestibule, is intimately involved in channel inactivation and desensitization.

  7. Petiroc and Citiroc: front-end ASICs for SiPM read-out and ToF applications

    International Nuclear Information System (INIS)

    Petiroc and Citiroc are the two latest ASIC from Weeroc dedicated to SiPM read-out. Petiroc is a 16-channel front-end ASIC designed to readout silicon photomultipliers (SiPMs) for particle time-of-flight measurement applications. It combines a very fast and low-jitter trigger with an accurate charge measurement. Citiroc is a 32-channel front-end ASIC designed to readout silicon photo-multipliers (SiPM). It allows triggering down to 1/3 pe and provides the charge measurement with a good noise rejection. Moreover, Citiroc outputs the 32-channel triggers with a high accuracy (100 ps). Each channel of both ASICs combines a trigger path with an accurate charge measurement path. An adjustment of the SiPM high voltage is possible using a channel-by-channel input DAC. That allows a fine SiPM gain and dark noise adjustment at the system level to correct for the non-uniformity of SiPMs. Timing measurement down to 16 ps RMS jitter for Petiroc and 100 ps RMS for Citiroc is possible along with 1% linearity energy measurement up to 2500 pe. The power consumption is around 3.5 mW/channel for Petiroc and 3 mW/channel for Citiroc, excluding ASICs outing buffer

  8. An Electromagnetic Beam Converter

    DEFF Research Database (Denmark)

    2009-01-01

    The present invention relates to an electromagnetic beam converter and a method for conversion of an input beam of electromagnetic radiation having a bell shaped intensity profile a(x,y) into an output beam having a prescribed target intensity profile l(x',y') based on a further development of the...

  9. Definition of Power Converters

    CERN Document Server

    Bordry, F

    2015-01-01

    The paper is intended to introduce power conversion principles and to define common terms in the domain. The concept s of sources and switches are defined and classified. From the basic laws of source interconnections, a generic method of power converter synthesis is presented. Some examples illustrate this systematic method. Finally, the commutation cell and soft commuta tion are introduced and discussedd.

  10. Convertible Proxy Signcryption Scheme

    Institute of Scientific and Technical Information of China (English)

    李继国; 李建中; 曹珍富; 张亦辰

    2004-01-01

    In 1996, Mambo et al introduced the concept of proxy signature. However, proxy signature can only provide the delegated authenticity and cannot provide confidentiality. Recently, Gamage et al and Chan and Wei proposed different proxy signcryption schemes respectively, which extended the concept of proxy signature.However, only the specified receiver can decrypt and verify the validity of proxy signcryption in their schemes.To protect the receiver' s benefit in case of a later dispute, Wu and Hsu proposed a convertible authenticated encryption scheme, which carn enable the receiver to convert signature into an ordinary one that can be verified by anyone. Based on Wu and Hsu' s scheme and improved Kim' s scheme, we propose a convertible proxy signcryption scheme. The security of the proposed scheme is based on the intractability of reversing the one-way hash function and solving the discrete logarithm problem. The proposed scheme can satisfy all properties of strong proxy signature and withstand the public key substitution attack and does not use secure channel. In addition, the proposed scheme can be extended to convertible threshold proxy signcryption scheme.

  11. Fractional Watt AMTEC Converter

    Science.gov (United States)

    Hunt, T. K.; Rasmussen, J. R.

    2006-01-01

    We report here the long term performance of a small, multi-tube AMTEC converter. This converter was designed to operate and produce approximately 12 watt of electrical output from a small, 4 to 6 watt radioisotope heat source for remote power applications. It was built and put on test in 1999 using electrical heaters as stand-ins for the radioisotope capsule. Since that time it has accumulated more than 5 years of run time at an input heater temperature of 700 °C, with numerous thermal cycles to ambient that were generally related to grid power failures or physical moves of the test apparatus. The power output has remained, with variations due to orientation changes and minor variations due to small temperature changes, essentially constant at 0.40 W to 0.60 W over the test period and operation is ongoing. The converter casing and mechanical structure was fabricated from 316 SS and the electrodes are sputtered titanium nitride films. Separate static tests of a multilayer insulation package suitable for use with the converter showed the capability to reach 700 °C with a thermal input of < 4 watts.

  12. Advanced DC/DC converters

    CERN Document Server

    Luo, Fang Lin

    2003-01-01

    INTRODUCTIONHistorical ReviewMultiple Quadrant ChoppersPump CircuitsDevelopment of DC/DC Conversion TechniqueCategorize Prototypes and DC/DC Converters Family TreeVOLTAGE-LIFT CONVERTERSIntroductionSeven Self-Lift ConvertersPositive Output Luo-ConvertersNegative Output Luo-ConvertersModified Positive Output Luo-Converters Double Output Luo-ConvertersPOSITIVE OUTPUT SUPER-LIFT LUO-CONVERTERS IntroductionMain SeriesAdditional SeriesEnhanced Series Re-Enhanced Series Multiple-Enhanced Series Summary of Positive Output

  13. Review of hybrid pixel detector readout ASICs for spectroscopic X-ray imaging

    International Nuclear Information System (INIS)

    Semiconductor detector readout chips with pulse processing electronics have made possible spectroscopic X-ray imaging, bringing an improvement in the overall image quality and, in the case of medical imaging, a reduction in the X-ray dose delivered to the patient. In this contribution we review the state of the art in semiconductor-detector readout ASICs for spectroscopic X-ray imaging with emphasis on hybrid pixel detector technology. We discuss how some of the key challenges of the technology (such as dealing with high fluxes, maintaining spectral fidelity, power consumption density) are addressed by the various ASICs. In order to understand the fundamental limits of the technology, the physics of the interaction of radiation with the semiconductor detector and the process of signal induction in the input electrodes of the readout circuit are described. Simulations of the process of signal induction are presented that reveal the importance of making use of the small pixel effect to minimize the impact of the slow motion of holes and hole trapping in the induced signal in high-Z sensor materials. This can contribute to preserve fidelity in the measured spectrum with relatively short values of the shaper peaking time. Simulations also show, on the other hand, the distortion in the energy spectrum due to charge sharing and fluorescence photons when the pixel pitch is decreased. However, using recent measurements from the Medipix3 ASIC, we demonstrate that the spectroscopic information contained in the incoming photon beam can be recovered by the implementation in hardware of an algorithm whereby the signal from a single photon is reconstructed and allocated to the pixel with the largest deposition

  14. Development of ultra-fast ASIC for future PET scanners using TOF-capable MPPC detectors

    Energy Technology Data Exchange (ETDEWEB)

    Matsuda, H., E-mail: aken.matsu@gmail.com [Faculty of Advanced Science and Engineering, Waseda University, 3-4-1 Okubo, Shinjuku, Tokyo (Japan); Kataoka, J. [Faculty of Advanced Science and Engineering, Waseda University, 3-4-1 Okubo, Shinjuku, Tokyo (Japan); Ikeda, H. [Institute of Space and Astronautical Science, JAXA, Sagamihara, Kanagawa (Japan); Kato, T.; Anbe, T. [Faculty of Advanced Science and Engineering, Waseda University, 3-4-1 Okubo, Shinjuku, Tokyo (Japan); Nakamura, S.; Ishikawa, Y.; Sato, K.; Yamamura, K. [Solid State Division, Hamamatsu Photonics K.K., 1126-1 Ichino-cho, Hamamatsu, Shizuoka (Japan)

    2013-01-21

    We have developed a front-end ASIC (MPPC32) intended for future PET scanners that offers time-of-flight (TOF) capability in conjunction with a multi-pixel photon counter (MPPC) array. The ASIC design is based on the open-IP project proposed by JAXA and was realized in TSMC 0.35-μm CMOS technology. The circuit comprises 32-channel, low impedance CMOS current conveyors (CCs) to effectively acquire fast MPPC signals. In order to precisely measure the coincidence timing of 511 keV gamma rays, the leading-edge method was employed instead of conventional zero-crossing measurement to discriminate signals. As a result, we obtained time jitter and walk measurement of 67 ps (FWHM) and 98 ps (within 511 keV±20%), respectively. Moreover, excellent energy resolutions of 9.8% (662 keV; FWHM) and 10.5% (511 keV; FWHM) were obtained by utilizing a 3×3 mm{sup 2} MPPC (of 50μm pitch) coupled with a Ce-doped LYSO (Ce:LYSO) crystal 3×3×10 mm{sup 3} in size. We finally report on the TOF measurements, and demonstrate that the MPPC32 developed here can be a promising device for future TOF-PET scanners using the MPPC array. -- Highlights: ► We developed an analog front-end ASIC for fast MPPC readout that offers TOF capability. ► We employed CMOS current conveyors with low impedance to acquire fast MPPC signals. ► The excellent coincidence timing resolution between two MPPCs was obtained when coupled to LYSO crystals.

  15. PACIFIC: the readout ASIC for the SciFi Tracker of the upgraded LHCb detector

    Science.gov (United States)

    Mazorra, J.; Chanal, H.; Comerma, A.; Gascón, D.; Gómez, S.; Han, X.; Pillet, N.; Vandaele, R.

    2016-02-01

    The LHCb detector will be upgraded during the Long Shutdown 2 (LS2) of the LHC in order to cope with higher instantaneous luminosities and will switch to a 40 MHz readout rate using a trigger-less software based system. All front-end electronics will be replaced and several sub-detectors must be redesigned to cope with the higher detector occupancy and radiation damage. The current tracking detectors downstream of the LHCb dipole magnet will be replaced by the Scintillating Fibre (SciFi) Tracker. The SciFi Tracker will use scintillating fibres read out by Silicon Photomultipliers (SiPMs). State-of-the-art multi-channel SiPM arrays are being developed and a custom ASIC, called the low-Power ASIC for the sCIntillating FIbres traCker (PACIFIC), will be used to digitise the signals from the SiPMs. This article presents an overview of the R&D for the PACIFIC. It is a 64-channel ASIC implemented in 130 nm CMOS technology, aiming at a radiation tolerant design with a power consumption below 10 mW per channel. It interfaces directly with the SiPM anode through a current mode input, and provides a configurable non-linear 2-bit per channel digital output. The SiPM signal is acquired by a current conveyor and processed with a fast shaper and a gated integrator. The digitization is performed using a three threshold non-linear flash ADC operating at 40 MHz. Simulation and test results show the PACIFIC chip prototypes functioning well.

  16. Review of hybrid pixel detector readout ASICs for spectroscopic X-ray imaging

    Science.gov (United States)

    Ballabriga, R.; Alozy, J.; Campbell, M.; Frojdh, E.; Heijne, E. H. M.; Koenig, T.; Llopart, X.; Marchal, J.; Pennicard, D.; Poikela, T.; Tlustos, L.; Valerio, P.; Wong, W.; Zuber, M.

    2016-01-01

    Semiconductor detector readout chips with pulse processing electronics have made possible spectroscopic X-ray imaging, bringing an improvement in the overall image quality and, in the case of medical imaging, a reduction in the X-ray dose delivered to the patient. In this contribution we review the state of the art in semiconductor-detector readout ASICs for spectroscopic X-ray imaging with emphasis on hybrid pixel detector technology. We discuss how some of the key challenges of the technology (such as dealing with high fluxes, maintaining spectral fidelity, power consumption density) are addressed by the various ASICs. In order to understand the fundamental limits of the technology, the physics of the interaction of radiation with the semiconductor detector and the process of signal induction in the input electrodes of the readout circuit are described. Simulations of the process of signal induction are presented that reveal the importance of making use of the small pixel effect to minimize the impact of the slow motion of holes and hole trapping in the induced signal in high-Z sensor materials. This can contribute to preserve fidelity in the measured spectrum with relatively short values of the shaper peaking time. Simulations also show, on the other hand, the distortion in the energy spectrum due to charge sharing and fluorescence photons when the pixel pitch is decreased. However, using recent measurements from the Medipix3 ASIC, we demonstrate that the spectroscopic information contained in the incoming photon beam can be recovered by the implementation in hardware of an algorithm whereby the signal from a single photon is reconstructed and allocated to the pixel with the largest deposition.

  17. A custom front-end ASIC for the readout and timing of 64 SiPM photosensors

    International Nuclear Information System (INIS)

    A new class of instruments - based on Silicon PhotoMultiplier (SiPM) photosensors - are currently under development for the next generation of Astroparticle Physics experiments in future space missions. A custom front-end ASIC (Application Specific Integrated Circuit) for the readout of 64 SiPM sensors was specified in collaboration with GM-IDEAS (Norway) that designed and manufactured the ASIC. Our group developed a custom readout board equipped with a 16 bit ADC for the digitization of both pulse height and time information. A time stamp, generated by the ASIC in correspondence of the threshold crossing time, is digitized and recorded for each channel. This allows to define a narrow time window around the physics event that reduces significantly the background due to the SiPM dark count rate. In this paper, we report on the preliminary test results obtained with the readout board prototype.

  18. A custom front-end ASIC for the readout and timing of 64 SiPM photosensors

    Energy Technology Data Exchange (ETDEWEB)

    Bagliesi, M.G., E-mail: mg.bagliesi@pi.infn.it [Department of Physics, University of Siena and INFN, Via Roma 56, 53100 Siena (Italy); Avanzini, C. [INFN Sezione di Pisa, Edificio C-Polo Fibonacci Largo Bruno Pontecorvo 3, 56127 Pisa (Italy); Bigongiari, G.; Cecchi, R.; Kim, M.Y.; Maestro, P.; Marrocchesi, P.S. [Department of Physics, University of Siena and INFN, Via Roma 56, 53100 Siena (Italy); Morsani, F. [INFN Sezione di Pisa, Edificio C-Polo Fibonacci Largo Bruno Pontecorvo 3, 56127 Pisa (Italy)

    2011-06-15

    A new class of instruments - based on Silicon PhotoMultiplier (SiPM) photosensors - are currently under development for the next generation of Astroparticle Physics experiments in future space missions. A custom front-end ASIC (Application Specific Integrated Circuit) for the readout of 64 SiPM sensors was specified in collaboration with GM-IDEAS (Norway) that designed and manufactured the ASIC. Our group developed a custom readout board equipped with a 16 bit ADC for the digitization of both pulse height and time information. A time stamp, generated by the ASIC in correspondence of the threshold crossing time, is digitized and recorded for each channel. This allows to define a narrow time window around the physics event that reduces significantly the background due to the SiPM dark count rate. In this paper, we report on the preliminary test results obtained with the readout board prototype.

  19. A multi-channel 24.4 ps bin size Time-to-Digital Converter for HEP applications

    CERN Document Server

    Mester, C; Morira, P

    2008-01-01

    A multi-channel time-tagging Time-to-Digital Converter (TDC) ASIC with a resolution of 24.4 ps (bin size) has been implemented and fabricated in a 130 nm CMOS technology. An on-chip PLL is used to generate an internal timing reference from an external 40 MHz clock source. The circuit is based on a 32 element Delay Locked Loop (DLL) which performs the time interpolation. The 32 channel architecture of the TDC is suitable for both triggered and non-triggered applications. The prototype contains test structures such as a substrate noise generator. The paper describes the circuit architecture and its principles of operation.

  20. Development of an ASIC for CCD readout at the vertex detectors of the intrenational linear collider

    CERN Document Server

    Murray, P; Stefanov, K D; Woolliscroft, T

    2007-01-01

    The Linear Collider Flavour Identification Collaboration is developing sensors and readout electronics suitable for the International Linear Collider vertex detector. In order to achieve high data rates the proposed detector utilises column parallel CCDs, each read out by a custom designed ASIC. The prototype chip (CPR2) has 250 channels of electronics, each with a preamplifier, 5-bit flash ADC, data sparsification logic for identification of significant data clusters, and local memory for storage of data awaiting readout. CPR2 also has hierarchical 2-level data multiplexing and intermediate data memory, enabling readout of the sparsified data via the 5-bit data output bus.

  1. Coupled FPGA/ASIC Implementation of Elliptic Curve Crypto-Processor

    Directory of Open Access Journals (Sweden)

    Mohsen Machhout

    2010-04-01

    Full Text Available In this paper, we propose an elliptic curve key generation processor over GF(2163 scheme based on the Montgomery scalar multiplication algorithm. The new architecture is performed using polynomial basis.The Finite Field operations use a cellular automata multiplier and Fermat algorithm for inversion. For real time implementation, the architecture has been tested on an ISE 9.1 Software using Xilinx Virtex II Pro FPGA and on an ASIC CMOS 45 nm technology as well. The proposed implementation provides a time of 2.07 ms and 38 percent of Slices in Xilinx Virtex II Pro FPGA. Such features reveal the highefficiently of this implementation design

  2. ASIC implementation of a data-push architecture for silicon pixel readout

    International Nuclear Information System (INIS)

    A digital circuit for reading out a silicon pixel array consisting of 64 x 256 elements has been designed. The readout architecture has a data-push sequencing with a throughput of about 200ns/hit. The critical elements of this design have been fabricated through MOSIS using the HP 1.2μm double-metal-single-polysilicon process. Design details of the ASIC and test results are presented. Measurements of interface effects (metastability) between the analog and digital circuit are also presented

  3. Performance and Calibration of H2RG Detectors and SIDECAR ASICs for the RATIR Camera

    Science.gov (United States)

    Fox, Ori D.; Kutyrev, Alexander S.; Rapchun, David A.; Klein, Christopher R.; Butler, Nathaniel R.; Bloom, Josh; de Diego, Jos A.; Simn Farah, Alejandro D.; Gehrels, Neil A.; Georgiev, Leonid; Gonzlez-Hernandez, J. Jess; Lee, William H.; Loose, Markus; Lotkin, Gennadiy; Moseley, Samuel H.; Prochaska, J. Xavier; Ramirez-Ruiz, Enrico; Richer, Michael G.; Robinson, Frederick D.; Romn-Zuniga, Carols; Samuel, Mathew V.; Sparr, Leroy M.; Watson, Alan M.

    2012-01-01

    The Reionization And Transient Infra,.Red (RATIR) camera has been built for rapid Gamma,.Ray Burst (GRE) followup and will provide simultaneous optical and infrared photometric capabilities. The infrared portion of this camera incorporates two Teledyne HgCdTe HAWAII-2RG detectors, controlled by Teledyne's SIDECAR ASICs. While other ground-based systems have used the SIDECAR before, this system also utilizes Teledyne's JADE2 interface card and IDE development environment. Together, this setup comprises Teledyne's Development Kit, which is a bundled solution that can be efficiently integrated into future ground-based systems. In this presentation, we characterize the system's read noise, dark current, and conversion gain.

  4. Development of a Position Decoding ASIC for SPECT using Silicon Photomultiplier

    Science.gov (United States)

    Cho, M.; Kim, H.; Lim, K. T.; Cho, G.

    2016-01-01

    Single Photon Emission Computed Tomography(SPECT) is a widely used diagnosis modality for detecting metabolic diseases. In general, SPECT system is consisted of a sensor, a pre-amplifier, position decoding circuits(PDC) and a data acquisition(DAQ) system. Due to such complexity, it is quite costly to assemble SPECT system by putting discrete components together. Moreover, using discrete components would make the system rather bulky. In this work, we designed a channel module ASIC for SPECT system. This system was composed of a transimpedance amplifier(TIA), comparators and digital logics. In this particular module, a TIA was selected as a preamplifier because the decay time and the rise time are shorter than that of other preamplifier topologies. In the proposed module, the amplified pulse from the TIA was split into two separate signals and each signal was then fed into two comparators with different reference levels, e.g., a low and high level. Then an XOR gate combined the comparator outputs and the output of XOR gate was sent to the suceeding digital logic. Furthermore, the output of each component in the module is composed of a signal packet. The packet includes the information on the energy, the time and the position of the incident photon. The energy and position information of a detected radiation can be derived from the output of the D-flipflop(DFF) in the module via time-over-threshold(TOT). The timing information was measured using a delayed rising edge from the low-level referenced comparator. There are several advantages in developing the channel module ASIC. First of all, the ASIC has only digital outputs and thus a correction circuit for analog signal distortion can be neglected. In addition, it is possible to cut down the system production cost because the volume of the system can be reduced due to the compactness of ASIC. The benefits of channel module is not only limited to SPECT but also beneficial to many other radiation detecting systems.

  5. Towards Automation of ASIC TSMC 0.18 um Standard Cell Library Development

    OpenAIRE

    Djigbenou, Jeannette Donan

    2008-01-01

    Cell-based design is a widely adopted design approach in current Application Specific Integrated Circuits (ASIC) and System-on-Chip (SOC) designs. A standard cell library is a collection of basic building blocks that can be used in cell-based design. The use of a standard cell library offers shorter design time, induces fewer errors in the design process, and is easier to maintain. Development of a cell library is laborious, prone to errors and even a small error on a library cell can poss...

  6. FATALIC: A Dedicated Front-End ASIC for the ATLAS TileCal Upgrade

    CERN Document Server

    Royer, Laurent; The ATLAS collaboration

    2015-01-01

    A front-end ASIC (FATALIC) has been developed to fulfil the requirements of the Phase 2 upgrade of the ATLAS Tile Calorimeter. This electronics performs the complete processing of the signal delivered by each PM tube. The first stage is a current conveyor which splits the 17-bit dynamic range of the input signal into three ranges. Each channel is followed by a shaper and a dedicated pipeline 12-bit ADC operating at 40MHz. The chip is developed using a 130nm CMOS technology. Measurements show a linearity better than 0.5% for low energy particles, and an ENC limited to 10 fC.

  7. X-ray imaging with a silicon microstrip detector coupled to the RX64 ASIC

    International Nuclear Information System (INIS)

    A single photon counting X-ray imaging system, with possible applications to dual energy mammography and angiography, is presented. A silicon microstrip detector with 100 μm pitch strips is coupled to RX64 ASICs, each of them including 64 channels of preamplifier, shaper, discriminator and scaler. The system has low noise, good spatial resolution and high counting rate capability. Results on energy resolution have been obtained with a fluorescence source and quasi-monochromatic X-rays beams. Preliminary images obtained with an angiographic phantom are presented

  8. Front end ASIC for AGIPD, a high dynamic range fast detector for the European XFEL

    International Nuclear Information System (INIS)

    The Adaptive Gain Integrating Pixel Detector (AGIPD) is a hybrid pixel X-ray detector for the European-XFEL. One of the detector's important parts is the radiation tolerant front end ASIC fulfilling the European-XFEL requirements: high dynamic range—from sensitivity to single 12.5keV-photons up to 104 photons. It is implemented using the dynamic gain switching technique with three possible gains of the charge sensitive preamplifier. Each pixel can store up to 352 images in memory operated in random-access mode at ≥4.5 MHz frame rate. An external vetoing may be applied to overwrite unwanted frames

  9. QIE12: A New High-Performance ASIC for the ATLAS TileCal Upgrade

    CERN Document Server

    Drake, Gary; The ATLAS collaboration; Proudfoot, James; Stanek, Robert; Chekanov, Sergei

    2015-01-01

    We present results on the QIE12, a custom ASIC, being developed for the ATLAS TileCal Phase 2 Upgrade. The design features 1.5 fC sensitivity, more than 17 bits of dynamic range with logarithmic response, and an on-chip TDC with one nanosecond resolution. It has a programmable shunt output for monitoring the integrated current. The device operates with no dead-time at 40 MHz, making it ideal for calorimetry at the LHC. We present bench measurements and integration studies that characterize the performance, radiation tolerance measurements, and the design for the ATLAS TileCal detector for the Phase 2 Upgrade.

  10. Galvanically Isolated Modular Converter

    OpenAIRE

    Christe, Alexandre; Dujic, Drazen

    2016-01-01

    Direct current (DC) electrical grids are already a reality in low voltage (LV) telecom distribution systems and point-to-point high voltage DC transmission. Medium voltage (MV) domain, despite its big potential, still suffers from a lack of suitable conversion and protection technologies. This study presents a bidirectional, galvanically isolated, high power converter for interface of emerging MVDC grids with readily available LVAC grids. To achieve high conversion efficiency, the integration...

  11. DSP controlled power converter

    OpenAIRE

    Chan, CH; Pong, MH

    1995-01-01

    A digital controller is designed and implemented by a Digital Signal Processor (DSP) to replace the Pulse Width Modulator (PWM) and error amplifier compensation network in a two wheeler forward converter. The DSP controller is designed in three approaches: a) Discretization of analog controller - the design is based on the transfer function of the error amplifier compensation network. b) Digital PID controller design - the design is based on the general form of the pulse transfer function of ...

  12. A Conformation Change in the Extracellular Domain that Accompanies Desensitization of Acid-sensing Ion Channel (ASIC) 3

    OpenAIRE

    Cushman, Kenneth A.; Marsh-Haffner, Josephine; Adelman, John P.; McCleskey, Edwin W.

    2007-01-01

    Acid-sensing ion channels (ASICs) are thought to trigger some forms of acid-induced pain and taste, and to contribute to stroke-induced neural damage. After activation by low extracellular pH, different ASICs undergo desensitization on time scales from 0.1 to 10 s. Consistent with a substantial conformation change, desensitization slows dramatically when temperature drops (Askwith, C.C., C.J. Benson, M.J. Welsh, and P.M. Snyder. 2001. PNAS. 98:6459–6463). The nature of this conformation chang...

  13. The interaction between the first transmembrane domain and the thumb of ASIC1a is critical for its N-glycosylation and trafficking.

    Directory of Open Access Journals (Sweden)

    Lan Jing

    Full Text Available Acid-sensing ion channel-1a (ASIC1a, the primary proton receptor in the brain, contributes to multiple diseases including stroke, epilepsy and multiple sclerosis. Thus, a better understanding of its biogenesis will provide important insights into the regulation of ASIC1a in diseases. Interestingly, ASIC1a contains a large, yet well organized ectodomain, which suggests the hypothesis that correct formation of domain-domain interactions at the extracellular side is a key regulatory step for ASIC1a maturation and trafficking. We tested this hypothesis here by focusing on the interaction between the first transmembrane domain (TM1 and the thumb of ASIC1a, an interaction known to be critical in channel gating. We mutated Tyr71 and Trp287, two key residues involved in the TM1-thumb interaction in mouse ASIC1a, and found that both Y71G and W287G decreased synaptic targeting and surface expression of ASIC1a. These defects were likely due to altered folding; both mutants showed increased resistance to tryptic cleavage, suggesting a change in conformation. Moreover, both mutants lacked the maturation of N-linked glycans through mid to late Golgi. These data suggest that disrupting the interaction between TM1 and thumb alters ASIC1a folding, impedes its glycosylation and reduces its trafficking. Moreover, reducing the culture temperature, an approach commonly used to facilitate protein folding, increased ASIC1a glycosylation, surface expression, current density and slowed the rate of desensitization. These results suggest that correct folding of extracellular ectodomain plays a critical role in ASIC1a biogenesis and function.

  14. Hydrogenated amorphous silicon sensors based on thin film on ASIC technology

    CERN Document Server

    Despeisse, M; Anelli, G; Jarron, P; Kaplon, J; Rusack, R; Saramad, S; Wyrsch, N

    2006-01-01

    The performance and limitations of a novel detector technology based on the deposition of a thin-film sensor on top of processed integrated circuits have been studied. Hydrogenated amorphous silicon (a-Si:H) films have been deposited on top of CMOS circuits developed for these studies and the resulting "thin-film on ASIC" (TFA) detectors are presented. The leakage current of the a-Si:H sensor at high reverse biases turns out to be an important parameter limiting the performance of a TFA detector. Its detailed study and the pixel segmentation of the detector are presented. High internal electric fields (in the order of 10/sup 4/-10/sup 5/ V/cm) can be built in the a-Si:H sensor and overcome the low mobility of electrons and holes in a-Si:H. Signal induction by generated carrier motion and speed in the a-Si:H sensor have been studied with a 660 nm pulsed laser on a TFA detector based on an ASIC integrating 5 ns peaking time pre- amplifiers. The measurement set-up also permits to study the depletion of the senso...

  15. Implementation of the ASDBLR straw tube readout ASIC in DMILL technology

    CERN Document Server

    Dressnandt, N; Newcomer, F M; Van Berg, R; Williams, H H

    2001-01-01

    The ASDBLR ASIC provides eight channels of low noise, low power, high rate on-detector readout suitable for the ATLAS Transition Radiation Tracker (TRT) at the LHC. The TRT's unprecedented wire chamber readout requirements of a maximum hit rate per wire of 20MHz and double pulse resolution of similar to 25ns with position resolution of better than 150mum in a high radiation environment have been addressed in the design of the ASDBLR. A carefully tuned ion tail cancellation stage followed by an output sensing baseline restorer implemented in differential structures provides robust signal processing combination compatible with the realities of ASIC design. Two comparators track the output of the signal processing stage to provide Tracking information from charged particles and evidence of higher energy Transition Radiation (TR) photons; their outputs are summed as current steps to form a differential ternary output. The ten year total dose requirement for neutrons of 10**1**4 n/cm**2 and 1.5 MRad of ionizing ra...

  16. PACIFIC: A 64-channel ASIC for scintillating fiber tracking in LHCb upgrade

    International Nuclear Information System (INIS)

    The LHCb detector will be upgraded during the next LHC shutdown in 2018/19 [1]. The tracker system will have a major overhaul. Its components will be replaced with new technologies in order to cope with the increased hit occupancy and radiation environment. Here we describe a detector made of scintillating fibers read out by silicon photomultipliers (SiPM), with a view to its application for this upgrade. This technology has been shown to achieve high efficiency and spatial resolution, but its integration within a LHCb experiment presents new challenges. This article gives an overview of the R and D status of the low-Power ASIC for the sCIntillating FIbres traCker (PACIFIC) chip implemented in a 130 nm CMOS technology. The PACIFIC chip is a 64-channel ASIC which can be connected to a SiPM without the need of any external component. It includes analog signal processing and digitization. The first stage is a current conveyor followed by a tunable fast shaper (≈10 ns) and a gated integrator. The digitization is performed using a 3 threshold non-linear flash ADC operating at 40 MHz. The PACIFIC chip has the ability to cope with different SiPM suppliers with a power consumption below 8 mW per channel and it is radiation-tolerant. Lastly, simulation and test results show the proper read out of the SiPMs with the PACIFIC chip

  17. 3D probe array integrated with a front-end 100-channel neural recording ASIC

    International Nuclear Information System (INIS)

    Brain–machine interface technology can improve the lives of spinal cord injury victims and amputees. A neural interface system, consisting of a 3D probe array and a custom low-power (1 mW) 100-channel (100-ch) neural recording application-specific integrated circuit (ASIC), was designed and implemented to monitor neural activity. In this study, a microassembly 3D probe array method using a novel lead transfer technique was proposed to overcome the bonding plane mismatch encountered during orthogonal assembly. The proposed lead transfer technique can be completed using standard micromachining and packaging processes. The ASIC can be stacking-integrated with the probe array, minimizing the form factor of the assembled module. To minimize trauma to brain cells, the profile of the integrated probe array was controlled within 730 μm. The average impedance of the assembled probe was approximately 0.55 MΩ at 1 kHz. To verify the functionality of the integrated neural probe array, bench-top signal acquisitions were performed and discussed. (paper)

  18. PACIFIC: A 64-channel ASIC for scintillating fiber tracking in LHCb upgrade

    Science.gov (United States)

    Gascon, D.; Chanal, H.; Comerma, A.; Gomez, S.; Han, X.; Mazorra, J.; Mauricio, J.; Pillet, N.; Yengui, F.; Vandaele, R.

    2015-04-01

    The LHCb detector will be upgraded during the next LHC shutdown in 2018/19 [1]. The tracker system will have a major overhaul. Its components will be replaced with new technologies in order to cope with the increased hit occupancy and radiation environment. Here we describe a detector made of scintillating fibers read out by silicon photomultipliers (SiPM), with a view to its application for this upgrade. This technology has been shown to achieve high efficiency and spatial resolution, but its integration within a LHCb experiment presents new challenges. This article gives an overview of the R&D status of the low-Power ASIC for the sCIntillating FIbres traCker (PACIFIC) chip implemented in a 130 nm CMOS technology. The PACIFIC chip is a 64-channel ASIC which can be connected to a SiPM without the need of any external component. It includes analog signal processing and digitization. The first stage is a current conveyor followed by a tunable fast shaper (≈10 ns) and a gated integrator. The digitization is performed using a 3 threshold non-linear flash ADC operating at 40 MHz. The PACIFIC chip has the ability to cope with different SiPM suppliers with a power consumption below 8 mW per channel and it is radiation-tolerant. Lastly, simulation and test results show the proper read out of the SiPMs with the PACIFIC chip.

  19. Performance of the First Version of VMM Front-End ASIC with Resistive Micromegas Detectors

    CERN Document Server

    The ATLAS collaboration

    2014-01-01

    This note describes the performance of the first version of a front end ASIC, VMM1, being developed for the Micromegas and sTGC detectors of the ATLAS New Small Wheel (NSW) upgrade. The VMM1 ASIC was designed by the micro-electronics group of the Instrumentation Division of Brookhaven National Laboratory. It contains 64-channels of linear, low noise amplifiers with adaptive feedback, charge amplitude peak detectors with time stamp. It can accept inputs of both polarities, features selectable gain and shaping time and has a built-in calibration system. It is designed to operate with micro-pattern gas detectors providing both trigger and tracking information. The VMM1 was tested during August 2012 test beam campaign at SPS/H6 beam line at CERN using micromegas detectors of the Muon ATLAS MicroMega Activity R&D program. We present here the VMM1 configuration, the software that was developed to achieve its operation, as well as the calibration procedure. Furthermore, we present the analysis performed with the...

  20. Convertible bond valuation focusing on Chinese convertible bond market

    OpenAIRE

    Yang, Ke

    2010-01-01

    This paper mainly discusses the methods of valuation of convertible bonds in Chinese market. Different from common convertible bonds in European market, considering the complicate features of Chinese convertible bond, this paper represents specific pricing approaches for pricing convertible bonds with different provisions along with the increment of complexity of these provisions. More specifically, this paper represents the decomposing method and binomial tree method for pricing both of Non-...

  1. The TDCpix Readout ASIC: A 75 ps Resolution Timing Front-End for the Gigatrackerof theNA62 Experiment

    Science.gov (United States)

    Rinella, G. Aglieri; Fiorini, M.; Jarron, P.; Kaplon, J.; Kluge, A.; Martin, E.; Morel, M.; Noy, M.; Perktold, L.; Poltorak, K.

    NA62 is an experiment under development at the CERN Super Proton Synchrotron, aiming at measuring ultra rare kaon decays. The Gigatracker (GTK) detector shall combine on-beam tracking of individual particles with a time resolution of 150 ps rms. The peak flow of particles crossing the detector modules reaches 1.27 MHz/mm2 fora total rateof about 0.75 GHz.Ahybrid siliconpixel detectoris beingdevelopedto meet these requirements. The pixel chip for the Gigatracker (TDCpix) is under design. The TDCpix chip will feature 1800 square pixels of 300×300 μm2 arranged in a matrix of 45 rows × 40 columns. Bump-bonded to a silicon pixel sensor it shall perform time stamping of particle hits with a timing accuracybetter than 200 ps rms and a detection efficiencyabove 99%. The chosen architecture provides full separation of the sensitive analog amplifiers of the pixel matrix from the noisy digital circuits of the TDCs and of the readout blocks. Discriminated hit signals from each pixel are transmitted to the end of column region. An array ofTime to Digital Converters (TDC) is implemented at the bottom of the pixel array. The TDCs are based on time tagging the events with the fine time codes generated by Delay Locked Loops (DLL) and have a nominal time bin of ˜100 ps. Time stamps and time-over-threshold are recorded for each discriminated hit and the correction of the discriminator's time-walk is performed off-detector. Data are continuously transmitted on four 2.4 Gb/s serial output links. Adescription of the on-going design of the final TDCpix is given in this paper. Design choices and some technical implementation details are presented. Aprototype ASIC including thekeycomponents of this architecture has been manufactured. The achievement of specification figures such as a time resolution of the processing chain of 75 ps rms as well as charged particle time stampingwitha resolutionbetterthan200psrmswere demonstratedexperimentally.Asummaryoftheseresultsisalso presented in

  2. 面向 ASIC 实现的 CPA 研究平台及其应用%Design and application of CPA research platform for ASIC

    Institute of Scientific and Technical Information of China (English)

    王晨旭; 张凯峰; 喻明艳; 王进祥

    2013-01-01

    Differential Power Analysis(DPA), a technology of non-invasive side-channel attack, has posed a serious threat for the safety of cipher integrated circuits. In order to evaluate the effectiveness of power analysis attack countermeasure conveniently, following the gate-level power analysis method, a Correlation Power Analysis(CPA)research platform based on PrimeTime PX and MATLAB is built. The auxiliary platform has a strong universality, and only by reworking cipher-specific power model, the algorithm level countermeasures for different ciphers can be evaluated easily. As an application, standard AES algorithm and the improved AES algorithm with threshold countermeasure method is attacked, showing the platform effectiveness.%  差分功耗分析(DPA)是一种非侵入式边信道攻击技术,对各种密码芯片的安全构成了极大威胁。为了能够快速地评估密码算法 ASIC 实现方式的算法级抗功耗分析攻击措施的实际效果,将门级功耗分析方法应用于功耗分析攻击评估技术中,搭建了基于 PrimeTime PX 和 MATLAB 的相关性功耗分析(CPA)研究平台。该平台具有较强的通用性,只需修改算法攻击功耗模型部分,即可快速完成对不同密码算法 ASIC 实现中算法级防护措施的评估。作为应用,利用该平台分别对普通 AES 算法实现和基于 Threshold 技术的 AES 算法实现进行了相关性攻击实验,证明了该平台的有效性和便捷性。

  3. SIGN LANGUAGE CONVERTER

    OpenAIRE

    Taner Arsan; Oğuz Ülgen

    2015-01-01

    The aim of this paper is to design a convenient system that is helpful for the people who have hearing difficulties and in general who use very simple and effective method; sign language. This system can be used for converting sign language to voice and also voice to sign language. A motion capture system is used for sign language conversion and a voice recognition system for voice conversion. It captures the signs and dictates on the screen as writing. It also captures the voice ...

  4. Cycloidal Wave Energy Converter

    Energy Technology Data Exchange (ETDEWEB)

    Stefan G. Siegel, Ph.D.

    2012-11-30

    This program allowed further advancing the development of a novel type of wave energy converter, a Cycloidal Wave Energy Converter or CycWEC. A CycWEC consists of one or more hydrofoils rotating around a central shaft, and operates fully submerged beneath the water surface. It operates under feedback control sensing the incoming waves, and converts wave power to shaft power directly without any intermediate power take off system. Previous research consisting of numerical simulations and two dimensional small 1:300 scale wave flume experiments had indicated wave cancellation efficiencies beyond 95%. The present work was centered on construction and testing of a 1:10 scale model and conducting two testing campaigns in a three dimensional wave basin. These experiments allowed for the first time for direct measurement of electrical power generated as well as the interaction of the CycWEC in a three dimensional environment. The Atargis team successfully conducted two testing campaigns at the Texas A&M Offshore Technology Research Center and was able to demonstrate electricity generation. In addition, three dimensional wave diffraction results show the ability to achieve wave focusing, thus increasing the amount of wave power that can be extracted beyond what was expected from earlier two dimensional investigations. Numerical results showed wave cancellation efficiencies for irregular waves to be on par with results for regular waves over a wide range of wave lengths. Using the results from previous simulations and experiments a full scale prototype was designed and its performance in a North Atlantic wave climate of average 30kW/m of wave crest was estimated. A full scale WEC with a blade span of 150m will deliver a design power of 5MW at an estimated levelized cost of energy (LCOE) in the range of 10-17 US cents per kWh. Based on the new results achieved in the 1:10 scale experiments these estimates appear conservative and the likely performance at full scale will

  5. Resonant power converters

    CERN Document Server

    Kazimierczuk, Marian K

    2012-01-01

    This book is devoted to resonant energy conversion in power electronics. It is a practical, systematic guide to the analysis and design of various dc-dc resonant inverters, high-frequency rectifiers, and dc-dc resonant converters that are building blocks of many of today's high-frequency energy processors. Designed to function as both a superior senior-to-graduate level textbook for electrical engineering courses and a valuable professional reference for practicing engineers, it provides students and engineers with a solid grasp of existing high-frequency technology, while acquainting them wit

  6. A front end ASIC for the readout of the PMT in the KM3NeT detector

    International Nuclear Information System (INIS)

    In this work, we describe the front end ASIC to readout the Photo-Multiplier-Tube of the KM3NeT detector, in detail. Stringent power budgeting, area constraints and lowering cost motivate us to design a custom front-end ASIC for reading the PMT. The ASIC amplifies the PMT signal and discriminates it against a threshold level and delivers the information via low voltage differential signals (LVDS). These LVDS signals carry highly accurate timing information of the photons . The length of the LVDS signals or Time over Threshold (ToT) gives information on the number of detected photons. A one-time programmable read-only memory (PROM) block provides unique identification to the chip. The chip communicates with the data acquisition electronics via an I2C bus. The data is transmitted to shore via fiber optics, where processing is done. The ASIC was fabricated in 0.35u CMOS process from AustriaMicroSystems (AMS).

  7. Development and evaluation of an ultra-fast ASIC for future PET scanners using TOF-capable MPPC array detectors

    Science.gov (United States)

    Ambe, T.; Ikeda, H.; Kataoka, J.; Matsuda, H.; Kato, T.

    2015-01-01

    We developed a front-end ASIC for future PET scanners with Time-Of-Flight (TOF) capability to be coupled with 4×4 Multi-Pixel Photon Counter (MPPC) arrays. The ASIC is designed based on the open-IP project proposed by JAXA and realized in TSMC 0.35 μm CMOS technology. The circuit comprises 16-channel, low impedance current conveyors for effectively acquiring fast MPPC signals. For precise measurement of the coincidence timing of 511-keV gamma rays, the leading-edge method was used to discriminate the signals. We first tested the time response of the ASIC by illuminating each channel of a MPPC array device 3×3 mm2 in size with a Pico-second Light Pulsar with a light emission peak of 655 nm and pulse duration of 54 ps (FWHM). We obtained 105 ps (FWHM) on average for each channel in time jitter measurements. Moreover, we compensated for the time lag of each channel with inner delay circuits and succeeded in suppressing about a 700-ps lag to only 15 ps. This paper reports TOF measurements using back-to-back 511-keV signals, and suggests that the ASIC can be a promising device for future TOF-PET scanners based on the MPPC array.

  8. A ±6 ms-Accuracy, 0.68 mm2, and 2.21 μW QRS Detection ASIC

    OpenAIRE

    Sheng-Chieh Huang; Hui-Min Wang; Wei-Yu Chen

    2012-01-01

    Healthcare issues arose from population aging. Meanwhile, electrocardiogram (ECG) is a powerful measurement tool. The first step of ECG is to detect QRS complexes. A state-of-the-art QRS detection algorithm was modified and implemented to an application-specific integrated circuit (ASIC). By the dedicated architecture design, the novel ASIC is proposed with 0.68 mm2 core area and 2.21 μW power consumption. It is the smallest QRS detection ASIC based on 0.18 μm technology. In addition, the sen...

  9. Power converters for ITER

    CERN Document Server

    Benfatto, I

    2006-01-01

    The International Thermonuclear Experimental Reactor (ITER) is a thermonuclear fusion experiment designed to provide long deuterium– tritium burning plasma operation. After a short description of ITER objectives, the main design parameters and the construction schedule, the paper describes the electrical characteristics of the French 400 kV grid at Cadarache: the European site proposed for ITER. Moreover, the paper describes the main requirements and features of the power converters designed for the ITER coil and additional heating power supplies, characterized by a total installed power of about 1.8 GVA, modular design with basic units up to 90 MVA continuous duty, dc currents up to 68 kA, and voltages from 1 kV to 1 MV dc.

  10. Heated catalytic converter

    Energy Technology Data Exchange (ETDEWEB)

    1994-09-01

    This article describes how the use of an auxiliary burner to heat the converter promptly can provide substantially decreased emission levels. While, in principle, there may well be solutions to decreasing warm-up phase hydrocarbon emissions, their production-level implementation is hindered by conflicting requirements, insufficiently mature technologies, and significant technical and financial restraints. The US, California, and the European Community are tightening emission standards for the transitional-low-, low-, and ultra-low-emission vehicles throughout the coming decade. The lead figure shows the fundamental possibilities for reducing harmful substances in exhaust emissions. While one can distinguish between measures taken within the engine (internal), and others outside it (external), it currently seems that only a combination of both will provide a suitable overall concept.

  11. Electromagnetic wave energy converter

    Science.gov (United States)

    Bailey, R. L. (Inventor)

    1973-01-01

    Electromagnetic wave energy is converted into electric power with an array of mutually insulated electromagnetic wave absorber elements each responsive to an electric field component of the wave as it impinges thereon. Each element includes a portion tapered in the direction of wave propagation to provide a relatively wideband response spectrum. Each element includes an output for deriving a voltage replica of the electric field variations intercepted by it. Adjacent elements are positioned relative to each other so that an electric field subsists between adjacent elements in response to the impinging wave. The electric field results in a voltage difference between adjacent elements that is fed to a rectifier to derive dc output power.

  12. Capturing a failure of an ASIC in-situ, using infrared radiometry and image processing software

    Science.gov (United States)

    Ruiz, Ronald P.

    2003-01-01

    Failures in electronic devices can sometimes be tricky to locate-especially if they are buried inside radiation-shielded containers designed to work in outer space. Such was the case with a malfunctioning ASIC (Application Specific Integrated Circuit) that was drawing excessive power at a specific temperature during temperature cycle testing. To analyze the failure, infrared radiometry (thermography) was used in combination with image processing software to locate precisely where the power was being dissipated at the moment the failure took place. The IR imaging software was used to make the image of the target and background, appear as unity. As testing proceeded and the failure mode was reached, temperature changes revealed the precise location of the fault. The results gave the design engineers the information they needed to fix the problem. This paper describes the techniques and equipment used to accomplish this failure analysis.

  13. Low noise front end ICECAL ASIC for the upgrade of the LHCb calorimeter

    International Nuclear Information System (INIS)

    A fully differential ASIC with cooled input termination is presented as a solution for the Upgrade of the Calorimeter front end electronics. The LHCb experiment needs to increase about ten times the integrated luminosity in order to study new physics. The increase in signal has to be compensated reducing the gain of the photomultipliers which implies stringent noise requirements. The proposed solution offers an active termination at the input and avoids the noise originated by the use of a resistor. The circuit is based on a two interleaved channel with a first amplifier stage, a switched integrator, and a Track-and-Hold. Two prototypes have been implemented and tested in SiGe BiCMOS 0.35um technology.

  14. SCOTT: A time and amplitude digitizer ASIC for PMT signal processing

    Energy Technology Data Exchange (ETDEWEB)

    Ferry, S., E-mail: sophie.ferry@cea.fr [CEA/ Irfu/ SPP, Gif-sur-Yvette (France); Guilloux, F.; Anvar, S.; Chateau, F.; Delagnes, E.; Gautard, V.; Louis, F.; Monmarthe, E.; Le Provost, H. [CEA/ Irfu/ SEDI, Gif-sur-Yvette (France); Russo, S. [Dipartimento di Scienze Fisiche Università di Napoli, Napoli (Italy); Schuller, J-P.; Stolarczyk, Th.; Vallage, B. [CEA/ Irfu/ SPP, Gif-sur-Yvette (France); Zonca, E. [CEA/ Irfu/ SEDI, Gif-sur-Yvette (France)

    2013-10-11

    SCOTT is an ASIC designed for the readout electronics of photomultiplier tubes developed for KM3NeT, the cubic-kilometer scale neutrino telescope in Mediterranean Sea. To digitize the PMT signals, the multi-time-over-threshold technique is used with up to 16 adjustable thresholds. Digital outputs of discriminators feed a circular sampling memory and a “first in first out” digital memory. A specific study has shown that five specifically chosen thresholds are suited to reach the required timing accuracy. A dedicated method based on the duration of the signal over a given threshold allows an equivalent timing precision at any charge. To verify that the KM3NeT requirements are fulfilled, this method is applied on PMT signals digitized by SCOTT.

  15. Performance and future development of the ASDBLR ASIC for the ATLAS TRT

    CERN Document Server

    Bevensee, B E; Newcomer, F M; Tyrrell, B; Van Berg, R; Williams, H H; Romaniouk, A

    1998-01-01

    The ATLAS TRT straw tracker will consist of more than 420 K straw tubes filled with a Xenon-based fast gas located in a magnetic field of 2 T. Some tubes will operate at rates in excess of 20 MHz. Stringent signal processing goals $9 have been determined using both simulation tools and measurement standards set by hand tuned discrete component prototypes. These include the ability to detect the earliest clusters from ionizing tracks as well as energetic $9 transition radiation photons without baseline shifts in a low noise and low power design. We report on measurements of two ASIC's fabricated in different processes that appear to be capable of achieving these goals. (2 refs).

  16. Very Low-Power Consumption Analog Pulse Processing ASIC for Semiconductor Radiation Detectors

    Energy Technology Data Exchange (ETDEWEB)

    Wessendorf, K.O.; Lund, J.C.; Brunett, B.A.; Laguna, G.R.; Clements, J.W.

    1999-08-23

    We describe a very-low power consumption circuit for processing the pulses from a semiconductor radiation detector. The circuit was designed for use with a cadmium zinc telluride (CZT) detector for unattended monitoring of stored nuclear materials. The device is intended to be battery powered and operate at low duty-cycles over a long period of time. This system will provide adequate performance for medium resolution gamma-ray pulse-height spectroscopy applications. The circuit incorporates the functions of a charge sensitive preamplifier, shaping amplifier, and peak sample and hold circuit. An application specific integrated circuit (ASIC) version of the design has been designed, built and tested. With the exception of the input field effect transistor (FET), the circuit is constructed using bipolar components. In this paper the design philosophy and measured performance characteristics of the circuit are described.

  17. The eight-channel ASIC bipolar transresistance amplifier D0M AMPL-8.3

    CERN Document Server

    Alexeev, G D; Dvornikov, O V; Khokhlov, A I; Mikhailov, V A; Odnokloubov, I A; Tokmenin, V V

    2001-01-01

    The eight-channel ASIC low-noise bipolar transresistance amplifier D0M Ampl-8.3 has been designed on the basis of BJT-JFET technology for gaseous wire detectors used in high-energy physics experiments. The amplifier has differential gain 130 mV/mu A at 1 k OMEGA, input noise 35 and 60 nA r.m.s. at 0 and 60 pF input capacitance, respectively, leading/trailing edge 7 ns, input resistance approx 50 OMEGA, crosstalks -47 dB, dissipated power 160 triple bond 640 mW/chip for +-3 triple bond 5 V supply. The Ampl-8.3 has been accepted for upgrading the Forward Angle Muon System of the D0 experiment (Fermilab, Batavia, USA), the total number of channels is about 50,000.

  18. GASTONE: A new ASIC for the cylindrical GEM inner tracker of KLOE experiment at DAFNE

    International Nuclear Information System (INIS)

    GEM Amplifier Shaper Tracking ON Events (GASTONE) is a low-noise low-power mixed analog-digital ASIC designed to host 64 channels to readout the GEM inner tracker (IT) detector foreseen in the upgrade of the KLOE apparatus at the LNF e+e- DAFNE collider. Each channel is made of a charge sensitive preamplifier, a shaper, a discriminator and a monostable. Digital output data are transmitted via serial interface at 100 Mbit/s data rate. The chip has been developed by using the AMS CMOS 0.35 process. A 16 channels prototype has been produced and used to instrument the single layer IT prototype that has been tested with cosmic muons and a proton beam test at CERN.

  19. GASTONE: A new ASIC for the cylindrical GEM inner tracker of KLOE experiment at DAFNE

    Energy Technology Data Exchange (ETDEWEB)

    Balla, A.; Bencivenni, G.; Beretta, M.; Cerioni, S.; Ciambrone, P.; De Lucia, E. [INFN Laboratori Nazionali Frascati, Via Fermi 40, 00044 Frascati (RM) (Italy); De Robertis, G. [INFN Sezione di Bari, Via Orabona 4, 70125 Bari (Italy); Domenici, D.; Felici, G.; Flammia, M.; Gatta, M.; Jacewicz, M. [INFN Laboratori Nazionali Frascati, Via Fermi 40, 00044 Frascati (Italy); Liuzzi, R. [INFN Sezione di Bari, Via Orabona 4, 70125 Bari (Italy); Loddo, F. [INFN Sezione di Bari, Via Orabona 4, 70125 Bari (Italy)], E-mail: flavio.loddo@ba.infn.it; Monno, L. [INFN Sezione di Bari, Via Orabona 4, 70125 Bari (Italy); Pistilli, M. [INFN Laboratori Nazionali Frascati, Via Fermi 40, 00044 Frascati (Italy); Ranieri, A. [INFN Sezione di Bari, Via Orabona 4, 70125 Bari (Italy); Rizzi, A. [INFN Laboratori Nazionali Frascati, Via Fermi 40, 00044 Frascati (Italy)

    2009-06-01

    GEM Amplifier Shaper Tracking ON Events (GASTONE) is a low-noise low-power mixed analog-digital ASIC designed to host 64 channels to readout the GEM inner tracker (IT) detector foreseen in the upgrade of the KLOE apparatus at the LNF e{sup +}e{sup -} DAFNE collider. Each channel is made of a charge sensitive preamplifier, a shaper, a discriminator and a monostable. Digital output data are transmitted via serial interface at 100 Mbit/s data rate. The chip has been developed by using the AMS CMOS 0.35 process. A 16 channels prototype has been produced and used to instrument the single layer IT prototype that has been tested with cosmic muons and a proton beam test at CERN.

  20. A VLSI ASIC front end for the optical module of the NEMO underwater neutrino detector

    International Nuclear Information System (INIS)

    The work described here has been developed in the context of the NEMO Collaboration with the aim of studying and designing a front-end electronics for the Optical Modules, which contains the telescope optical sensors, as a full-custom Very Large Scale Integration (VLSI) Application Specific Integrated Circuit (ASIC). The solution has a multitude of advantages. The most important are low power consumption and the pre-analysis and suitable reduction of data to be transferred to the shore station for acquisition. A detailed description of the chosen architecture and the design principles of the blocks, that carry out the specialized function required by this architecture, will be given. The chips produced will be described and the test measurements performed will be shown

  1. Very Low-Power Consumption Analog Pulse Processing ASIC for Semiconductor Radiation Detectors

    International Nuclear Information System (INIS)

    We describe a very-low power consumption circuit for processing the pulses from a semiconductor radiation detector. The circuit was designed for use with a cadmium zinc telluride (CZT) detector for unattended monitoring of stored nuclear materials. The device is intended to be battery powered and operate at low duty-cycles over a long period of time. This system will provide adequate performance for medium resolution gamma-ray pulse-height spectroscopy applications. The circuit incorporates the functions of a charge sensitive preamplifier, shaping amplifier, and peak sample and hold circuit. An application specific integrated circuit (ASIC) version of the design has been designed, built and tested. With the exception of the input field effect transistor (FET), the circuit is constructed using bipolar components. In this paper the design philosophy and measured performance characteristics of the circuit are described

  2. Design Methodology: ASICs with complex in-pixel processing for Pixel Detectors

    Energy Technology Data Exchange (ETDEWEB)

    Fahim, Farah [Fermilab

    2014-10-31

    The development of Application Specific Integrated Circuits (ASIC) for pixel detectors with complex in-pixel processing using Computer Aided Design (CAD) tools that are, themselves, mainly developed for the design of conventional digital circuits requires a specialized approach. Mixed signal pixels often require parasitically aware detailed analog front-ends and extremely compact digital back-ends with more than 1000 transistors in small areas below 100μm x 100μm. These pixels are tiled to create large arrays, which have the same clock distribution and data readout speed constraints as in, for example, micro-processors. The methodology uses a modified mixed-mode on-top digital implementation flow to not only harness the tool efficiency for timing and floor-planning but also to maintain designer control over compact parasitically aware layout.

  3. A 2.5 gb/s GaAs ATM Mux Demux ASIC

    DEFF Research Database (Denmark)

    Madsen, Jens Kargaard; Lassen, Peter Stuhr

    1995-01-01

    This paper describes the design and implementation of a high speed GaAs ATM Mux Demur ASIC (AMDA) which is the key element in a high speed ATM Add-Drop unit. This unit is used in a new distributed ATM multiplexing-demultiplexing architecture for broadband switching systems. The Add-Drop unit...... provides a cell based interface between networks/systems operating at different data rates, the high speed interface being 2.5 Gb/s and the low speed interface being 155/622 Mb/s. Self-timed FIFOs are used for handling the speed gaps between domains operating at different clock rates, and a Self-Timed At...... Receiver's Input (STARI) interface is used at all high speed chip-to-chip links to eliminate timing skews The AMDA demonstrated operation above 4 Gb/s (500 MHz clock frequency) with an associated power dissipation of 5 W...

  4. Integrated power electronic converters and digital control

    CERN Document Server

    Emadi, Ali; Nie, Zhong

    2009-01-01

    Non-isolated DC-DC ConvertersBuck ConverterBoost ConverterBuck-Boost ConverterIsolated DC-DC ConvertersFlyback ConverterForward ConverterPush-Pull ConverterFull-Bridge ConverterHalf-Bridge ConverterPower Factor CorrectionConcept of PFCGeneral Classification of PFC CircuitsHigh Switching Frequency Topologies for PFCApplication of PFC in Advanced Motor DrivesIntegrated Switched-Mode Power ConvertersSwitched-Mode Power SuppliesThe Concept of Integrated ConverterDefinition of Integrated Switched-Mode Power Supplies (ISMPS)Boost-Type Integrated TopologiesGeneral Structure of Boost-Type Integrated T

  5. Design methodology: edgeless 3D ASICs with complex in-pixel processing for pixel detectors

    Energy Technology Data Exchange (ETDEWEB)

    Fahim Farah, Fahim Farah [Northwestern U. (main); Deptuch, Grzegorz W. [Fermilab; Hoff, James R. [Fermilab; Mohseni, Hooman [Northwestern U. (main)

    2015-08-28

    The design methodology for the development of 3D integrated edgeless pixel detectors with in-pixel processing using Electronic Design Automation (EDA) tools is presented. A large area 3 tier 3D detector with one sensor layer and two ASIC layers containing one analog and one digital tier, is built for x-ray photon time of arrival measurement and imaging. A full custom analog pixel is 65μm x 65μm. It is connected to a sensor pixel of the same size on one side, and on the other side it has approximately 40 connections to the digital pixel. A 32 x 32 edgeless array without any peripheral functional blocks constitutes a sub-chip. The sub-chip is an indivisible unit, which is further arranged in a 6 x 6 array to create the entire 1.248cm x 1.248cm ASIC. Each chip has 720 bump-bond I/O connections, on the back of the digital tier to the ceramic PCB. All the analog tier power and biasing is conveyed through the digital tier from the PCB. The assembly has no peripheral functional blocks, and hence the active area extends to the edge of the detector. This was achieved by using a few flavors of almost identical analog pixels (minimal variation in layout) to allow for peripheral biasing blocks to be placed within pixels. The 1024 pixels within a digital sub-chip array have a variety of full custom, semi-custom and automated timing driven functional blocks placed together. The methodology uses a modified mixed-mode on-top digital implementation flow to not only harness the tool efficiency for timing and floor-planning but also to maintain designer control over compact parasitically aware layout. The methodology uses the Cadence design platform, however it is not limited to this tool.

  6. Advanced power electronics converters PWM converters processing AC voltages

    CERN Document Server

    dos Santos, Euzeli

    2014-01-01

    This book covers power electronics, in depth, by presenting the basic principles and application details, which can be used both as a textbook and reference book.  Introduces a new method to present power electronics converters called Power Blocks Geometry. Applicable for courses focusing on power electronics, power electronics converters, and advanced power converters. Offers a comprehensive set of simulation results to help understand the circuits presented throughout the book

  7. High-Performance Data Converters

    DEFF Research Database (Denmark)

    Steensgaard-Madsen, Jesper

    in a standard CMOS technology, they can be designed to yield 100 dB performance at 10 times oversampling. The proposed scaled-element mismatch-shaping D/A converters are well suited for use as the feedback stage in oversampled delta-sigma quantizers. It is, however, not easy to make full use of their......Novel techniques for multi-bit oversampled data conversion are described. State-of-the-art oversampled data converters are analyzed, leading to the conclusion that their performance is limited mainly by low-resolution signal representation. To increase the resolution, high-performance, high......-resolution internal D/A converters are required. Unit-element mismatch-shaping D/A converters are analyzed, and the concept of mismatch-shaping is generalized to include scaled-element D/A converters. Several types of scaled-element mismatch-shaping D/A converters are proposed. Simulations show that, when implemented...

  8. Low pressure solar thermal converter

    OpenAIRE

    Muller, Gerald

    2010-01-01

    The current development of solar power converters with air as working fluid focuses mostly on concentrating collectors combined with hot-air engines, and on very low temperature solar tower concepts. Whilst concentrating collectors and Stirling engines need complex technology, solar tower converters have very low efficiencies and require large installations. Pressurized containers as energy converters offer the advantage of simplicity, but appear not to have been investigated in detail. ...

  9. A ±6 ms-Accuracy, 0.68 mm2, and 2.21 μW QRS Detection ASIC

    Directory of Open Access Journals (Sweden)

    Sheng-Chieh Huang

    2012-01-01

    Full Text Available Healthcare issues arose from population aging. Meanwhile, electrocardiogram (ECG is a powerful measurement tool. The first step of ECG is to detect QRS complexes. A state-of-the-art QRS detection algorithm was modified and implemented to an application-specific integrated circuit (ASIC. By the dedicated architecture design, the novel ASIC is proposed with 0.68 mm2 core area and 2.21 μW power consumption. It is the smallest QRS detection ASIC based on 0.18 μm technology. In addition, the sensitivity is 95.65% and the positive prediction of the ASIC is 99.36% based on the MIT/BIH arrhythmia database certification.

  10. Venturini Method Based Matrix Converter

    Directory of Open Access Journals (Sweden)

    Derick Mathew

    2015-03-01

    Full Text Available Recently, matrix converter has received considerable interest as a viable alternative to the conventional ac-dc-ac converter. This direct ac-ac converter provides some attractive characteristics such as: four quadrant operation, absence of bulky dc-link electrolyte capacitors, clean input power characteristics. Due to the absence of dc link energy storage elements any disturbance in the input voltage will be immediately reflected to the output voltages. In this paper venturini method for matrix converter has been presented. Three phase sinusoidal symmetrical voltage or current can obtained .

  11. The function and regulation of acid-sensing ion channels (ASICs) and the epithelial Na(+) channel (ENaC): IUPHAR Review 19.

    Science.gov (United States)

    Boscardin, Emilie; Alijevic, Omar; Hummler, Edith; Frateschi, Simona; Kellenberger, Stephan

    2016-09-01

    Acid-sensing ion channels (ASICs) and the epithelial Na(+) channel (ENaC) are both members of the ENaC/degenerin family of amiloride-sensitive Na(+) channels. ASICs act as proton sensors in the nervous system where they contribute, besides other roles, to fear behaviour, learning and pain sensation. ENaC mediates Na(+) reabsorption across epithelia of the distal kidney and colon and of the airways. ENaC is a clinically used drug target in the context of hypertension and cystic fibrosis, while ASIC is an interesting potential target. Following a brief introduction, here we will review selected aspects of ASIC and ENaC function. We discuss the origin and nature of pH changes in the brain and the involvement of ASICs in synaptic signalling. We expose how in the peripheral nervous system, ASICs cover together with other ion channels a wide pH range as proton sensors. We introduce the mechanisms of aldosterone-dependent ENaC regulation and the evidence for an aldosterone-independent control of ENaC activity, such as regulation by dietary K(+) . We then provide an overview of the regulation of ENaC by proteases, a topic of increasing interest over the past few years. In spite of the profound differences in the physiological and pathological roles of ASICs and ENaC, these channels share many basic functional and structural properties. It is likely that further research will identify physiological contexts in which ASICs and ENaC have similar or overlapping roles. PMID:27278329

  12. PcTx1 affords neuroprotection in a conscious model of stroke in hypertensive rats via selective inhibition of ASIC1a.

    Science.gov (United States)

    McCarthy, Claudia A; Rash, Lachlan D; Chassagnon, Irène R; King, Glenn F; Widdop, Robert E

    2015-12-01

    Acid-sensing ion channel 1a (ASIC1a) is the primary acid sensor in mammalian brain and plays a major role in neuronal injury following cerebral ischemia. Evidence that inhibition of ASIC1a might be neuroprotective following stroke was previously obtained using "PcTx1 venom" from the tarantula Psalmopeous cambridgei. We show here that the ASIC1a-selective blocker PcTx1 is present at only 0.4% abundance in this venom, leading to uncertainty as to whether the observed neuroprotective effects were due to PcTx1 blockade of ASIC1a or inhibition of other ion channels and receptors by the hundreds of peptides and small molecules present in the venom. We therefore examined whether pure PcTx1 is neuroprotective in a conscious model of stroke via direct inhibition of ASIC1a. A focal reperfusion model of stroke was induced in conscious spontaneously hypertensive rats (SHR) by administering endothelin-1 to the middle cerebral artery via a surgically implanted cannula. Two hours later, SHR were treated with a single intracerebroventricular (i.c.v.) dose of PcTx1 (1 ng/kg), an ASIC1a-inactive mutant of PcTx1 (1 ng/kg), or saline, and ledged beam and neurological tests were used to assess the severity of symptomatic changes. PcTx1 markedly reduced cortical and striatal infarct volumes measured 72 h post-stroke, which correlated with improvements in neurological score, motor function and preservation of neuronal architecture. In contrast, the inactive PcTx1 analogue had no effect on stroke outcome. This is the first demonstration that selective pharmacological inhibition of ASIC1a is neuroprotective in conscious SHRs, thus validating inhibition of ASIC1a as a potential treatment for stroke. PMID:26320544

  13. Development of New European VLIW Space DSP ASICS, IP Cores and Related Software via ESA Contracts in 2015 and Beyond

    Science.gov (United States)

    Trautner, R.

    2015-09-01

    European space industry needs a new generation of payload data processors in order to cope with in-creasing payload data processing requirements. ESA has defined a roadmap for the development of future payload processor hardware which is being implemented. A key part of this roadmap addresses the development of VLIW Digital Signal Processor (DSP) ASICs, IP cores and associated software. In this paper, we first present an overview of the ESA roadmap and the key development routes. We recapitulate the activities that have created the technology base for the ongoing DSP development, and present the ASIC development and several accompanying activities that will lead to the availability of a new space qualified DSP - the Scalable Sensor Data Processor (SSDP) - in the near future. We then present the expected future evolution of this technology area, and summarize the corresponding ESA roadmap part on VLIW DSPs and related IP and software.

  14. The eCDR-PLL, a radiation-tolerant ASIC for clock and data recovery and deterministic phase clock synthesis

    International Nuclear Information System (INIS)

    A radiation-tolerant CDR/PLL ASIC has been developed for the upcoming LHC upgrades, featuring clock Frequency Multiplication (FM) and Clock and Data Recovery (CDR), showing deterministic phase and low jitter. Two FM modes have been implemented: either generating 40, 60, 120 and 240 MHz clock outputs for GBT-FPGA applications or providing 40, 80, 160 and 320 MHz clocks for TTC and e-link applications. The CDR operates with 40, 80, 160 or 320 Mbit/s data rates while always generating clocks at 40, 80, 160 and 320 MHz, regardless of the data rate. All the outputs are phase programmable with a resolution of 195 ps or 260 ps, depending on the selected mode. The ASIC has been designed using radiation-tolerant techniques in a 130 nm CMOS technology and operates at a 1.2 V supply voltage

  15. Multilevel push pull power converter

    DEFF Research Database (Denmark)

    2007-01-01

    A power converter for converting an input voltage (Vin) into an output voltage (Vout), comprising a first supply potential and a second supply potential established by the input voltage, and at least one primary winding having two terminals, a center tap arranged between the two terminals and...

  16. Catalytic converters in the fireplace

    International Nuclear Information System (INIS)

    In addition to selecting the appropriate means of heating and using dry fuel, the amount of harmful emissions contained by flue gases produced by fireplaces can be reduced by technical means. One such option is to use an oxidising catalytic converter. Tests at TTS Institute's Heating Studies Experimental Station have focused on two such converters (dense and coarse) mounted in light-weight iron heating stoves. The ability of the dense catalytic converter to oxidise carbon monoxide gases proved to be good. The concentration of carbon monoxide in the flue gases was reduced by as much as 90 %. Measurements conducted by VTT (Technical Research Centre of Finland) showed that the conversion of other gases, e.g. of methane, was good. The exhaust resistance caused by the dense converter was so great as to necessitate the mounting of a fluegas evacuation fan in the chimney for the purpose of creating sufficient draught. When relying on natural draught, the dense converter requires a chimney of at least 7 metres and a by-pass connection while the fire is being lit. In addition, the converter will have to be constructed to be less dense and this will mean that it's capability to oxidise non-combusted gases will be reduced. The coarse converter did not impair the draught but it's oxidising property was insufficient. With the tests over, the converter was not observed to have become blocked up by impurities

  17. Proposed electromagnetic wave energy converter

    Science.gov (United States)

    Bailey, R. L.

    1973-01-01

    Device converts wave energy into electric power through array of insulated absorber elements responsive to field of impinging electromagnetic radiation. Device could also serve as solar energy converter that is potentially less expensive and fragile than solar cells, yet substantially more efficient.

  18. Design and performances of a low-noise and radiation-hardened readout ASIC for CdZnTe detectors

    Science.gov (United States)

    Bo, Gan; Tingcun, Wei; Wu, Gao; Yongcai, Hu

    2016-06-01

    In this paper, we present the design and performances of a low-noise and radiation-hardened front-end readout application specific integrated circuit (ASIC) dedicated to CdZnTe detectors for a hard X-ray imager in space applications. The readout channel is comprised of a charge sensitive amplifier, a CR-RC shaping amplifier, an analog output buffer, a fast shaper, and a discriminator. An 8-channel prototype ASIC is designed and fabricated in TSMC 0.35-μm mixed-signal CMOS technology, the die size of the prototype chip is 2.2 × 2.2 mm2. The input energy range is from 5 to 350 keV. For this 8-channel prototype ASIC, the measured electrical characteristics are as follows: the overall gain of the readout channel is 210 V/pC, the linearity error is less than 2%, the crosstalk is less than 0.36%, The equivalent noise charge of a typical channel is 52.9 e‑ at zero farad plus 8.2 e‑ per picofarad, and the power consumption is less than 2.4 mW/channel. Through the measurement together with a CdZnTe detector, the energy resolution is 5.9% at the 59.5-keV line under the irradiation of the radioactive source 241Am. The radiation effect experiments show that the proposed ASIC can resist the total ionization dose (TID) irradiation of higher than 200 krad(Si). Project supported by the National Key Scientific Instrument and Equipment Development Project (No. 2011YQ040082), the National Natural Science Foundation of China (Nos. 11475136, 11575144, 61176094), and the Shaanxi Natural Science Foundation of China (No. 2015JM1016).

  19. Development and evaluation of an ultra-fast ASIC for future PET scanners using TOF-capable MPPC array detectors

    Energy Technology Data Exchange (ETDEWEB)

    Ambe, T., E-mail: hiro-a-be.n@akane.waseda.jp [Research Institute for Science and Engineering, Waseda University, 3-4-1, Okubo, Shinjuku, Tokyo (Japan); Ikeda, H. [ISAS/JAXA, 3-1-1, Yoshinodai, Chuo-ku, Sagamihara-shi, Kanagawa (Japan); Kataoka, J.; Matsuda, H.; Kato, T. [Research Institute for Science and Engineering, Waseda University, 3-4-1, Okubo, Shinjuku, Tokyo (Japan)

    2015-01-21

    We developed a front-end ASIC for future PET scanners with Time-Of-Flight (TOF) capability to be coupled with 4×4 Multi-Pixel Photon Counter (MPPC) arrays. The ASIC is designed based on the open-IP project proposed by JAXA and realized in TSMC 0.35 μm CMOS technology. The circuit comprises 16-channel, low impedance current conveyors for effectively acquiring fast MPPC signals. For precise measurement of the coincidence timing of 511-keV gamma rays, the leading-edge method was used to discriminate the signals. We first tested the time response of the ASIC by illuminating each channel of a MPPC array device 3×3 mm{sup 2} in size with a Pico-second Light Pulsar with a light emission peak of 655 nm and pulse duration of 54 ps (FWHM). We obtained 105 ps (FWHM) on average for each channel in time jitter measurements. Moreover, we compensated for the time lag of each channel with inner delay circuits and succeeded in suppressing about a 700-ps lag to only 15 ps. This paper reports TOF measurements using back-to-back 511-keV signals, and suggests that the ASIC can be a promising device for future TOF-PET scanners based on the MPPC array. - Highlights: • We developed a newly designed large-area monolithic MPPC array. • We obtained fine gain uniformity, and good energy and time resolutions when coupled to the LYSO scintillator. • We fabricated gamma-ray camera consisting of the MPPC array and the submillimeter pixelized LYSO and GGAG scintillators. • In the flood images, each crystal of scintillator matrices was clearly resolved. • Good energy resolutions for 662 keV gamma-rays for each LYSO and GGAG scintillator matrices were obtained.

  20. Test results of the ASIC front-end trigger prototypes for the muon barrel detector of CMS at LHC

    International Nuclear Information System (INIS)

    A sample of ASIC prototypes of the first-level trigger front-end device for the muon barrel drift chambers of CMS was tested on a full size chamber prototype. Tests were performed at several incident angles on cosmic rays and at normal incidence using a muon beam. The chamber was irradiated using a 137Cs gamma source to simulate the LHC radiation environment. The performance of the tested prototypes with respect to efficiency, resolution and noise issues is reported

  1. Development and evaluation of an ultra-fast ASIC for future PET scanners using TOF-capable MPPC array detectors

    International Nuclear Information System (INIS)

    We developed a front-end ASIC for future PET scanners with Time-Of-Flight (TOF) capability to be coupled with 4×4 Multi-Pixel Photon Counter (MPPC) arrays. The ASIC is designed based on the open-IP project proposed by JAXA and realized in TSMC 0.35 μm CMOS technology. The circuit comprises 16-channel, low impedance current conveyors for effectively acquiring fast MPPC signals. For precise measurement of the coincidence timing of 511-keV gamma rays, the leading-edge method was used to discriminate the signals. We first tested the time response of the ASIC by illuminating each channel of a MPPC array device 3×3 mm2 in size with a Pico-second Light Pulsar with a light emission peak of 655 nm and pulse duration of 54 ps (FWHM). We obtained 105 ps (FWHM) on average for each channel in time jitter measurements. Moreover, we compensated for the time lag of each channel with inner delay circuits and succeeded in suppressing about a 700-ps lag to only 15 ps. This paper reports TOF measurements using back-to-back 511-keV signals, and suggests that the ASIC can be a promising device for future TOF-PET scanners based on the MPPC array. - Highlights: • We developed a newly designed large-area monolithic MPPC array. • We obtained fine gain uniformity, and good energy and time resolutions when coupled to the LYSO scintillator. • We fabricated gamma-ray camera consisting of the MPPC array and the submillimeter pixelized LYSO and GGAG scintillators. • In the flood images, each crystal of scintillator matrices was clearly resolved. • Good energy resolutions for 662 keV gamma-rays for each LYSO and GGAG scintillator matrices were obtained

  2. Development of Charge Sensitive Preamplifier and Readout Integrate Circuit Board for High Resolution Detector using ASIC Process

    International Nuclear Information System (INIS)

    - Design of discrete type charge sensitive amplifier for high resolution semi-conductor sensor - Design and develop the test board for the performance of charge sensitive amplifier with sensor - Performance of electrical test for the sensor and charge sensitive amplifier - Development of prototype 8 x 8 array type detector module - Noise equivalent charge test for the charge sensitive amplifier - Design and development of Micro SMD discrete type amplifier applying ASIC procedure - Development of Hybrid type charge sensitive amplifier including shape

  3. Studies and development of a readout ASIC for pixelated CdTe detectors for space applications

    International Nuclear Information System (INIS)

    The work presented in this thesis is part of a project where a new instrument is developed: a camera for hard X-rays imaging spectroscopy. It is dedicated to fundamental research for observations in astrophysics, at wavelengths which can only be observed using space-borne instruments. In this domain the spectroscopic accuracy as well as the imaging details are of high importance. This work has been realized at CEA/IRFU (Institut de Recherche sur les lois Fondamentales de l'Univers), which has a long-standing and successful experience in instruments for high energy physics and space physics instrumentation. The objective of this thesis is the design of the readout electronics for a pixelated CdTe detector, suitable for a stacked assembly. The principal parameters of this integrated circuit are a very low noise for reaching a good accuracy in X-ray energy measurement, very low power consumption, a critical parameter in space-borne applications, and a small dead area for the full system combining the detector and the readout electronics. In this work I have studied the limits of these three parameters in order to optimize the circuit. In terms of the spectral resolution, two categories of noise had to be distinguished to determine the final performance. The first is the Fano noise limit, related to detector interaction statistics, which cannot be eliminated. The second is the electronic noise, also unavoidable; however it can be minimized through optimization of the detection chain. Within the detector, establishing a small pixel pitch of 300 μm reduces the input capacitance and the dark current. This limits the effects of the electronic noise. Also in order to limit the input capacitance the future camera is designed as a stacked assembly of the detector with the readout ASIC. This allows to reach extremely good input parameters seen by the readout electronics: a capacitance in range of 0.3 pF-1 pF and a dark current below 5 pA. In the frame of this thesis I have

  4. Development of a CdTe pixel detector with a window comparator ASIC for high energy X-ray applications

    Science.gov (United States)

    Hirono, T.; Toyokawa, H.; Furukawa, Y.; Honma, T.; Ikeda, H.; Kawase, M.; Koganezawa, T.; Ohata, T.; Sato, M.; Sato, G.; Takagaki, M.; Takahashi, T.; Watanabe, S.

    2011-09-01

    We have developed a photon-counting-type CdTe pixel detector (SP8-01). SP8-01 was designed as a prototype of a high-energy X-ray imaging detector for experiments using synchrotron radiation. SP8-01 has a CdTe sensor of 500 μm thickness, which has an absorption efficiency of almost 100% up to 50 keV and 45% even at 100 keV. A full-custom application specific integrated circuit (ASIC) was designed as a readout circuit of SP8-01, which is equipped with a window-type discriminator. The upper discriminator realizes a low-background measurement, because X-ray beams from the monochromator contain higher-order components beside the fundamental X-rays in general. ASIC chips were fabricated with a TSMC 0.25 μm CMOS process, and CdTe sensors were bump-bonded to the ASIC chips by a gold-stud bonding technique. Beam tests were performed at SPring-8. SP8-01 detected X-rays up to 120 keV. The capability of SP8-01 as an imaging detector for high-energy X-ray synchrotron radiation was evaluated with its performance characteristics.

  5. Inhibition of acid-induced apoptosis by targeting ASIC1a mRNA with short hairpin RNA

    Institute of Scientific and Technical Information of China (English)

    Xie-chuan WENG; Jian-quan ZHENG; Qing-e JIN; Xiao-yun MA

    2007-01-01

    Aim: To study the role of acid-sensing ion channel (ASIC) la in the cell death and apoptosis induced by extracellular acid in C6 glioma cells. Methods: The stable ASICla-silenced C6 cell line, built with RNA interference technology, were con-firmed by RT-PCR and Western blot analysis. The cell viability following acid exposure was analyzed with lactate dehydrogenase (LDH) and 3-(4,5-dimethylthiazol-2-yl)-2, 5-diphenyltetrazolium bromide (MTT) assay. The apoptotic cells dyed with Annexin-V and propidium iodide were measured with a flow cytometer, while the changes of cell cycle were also assayed. Results: The downregulation of ASIC 1 a proteins by stable transfection of short hairpin RNA decreased the cell death percentage and increased cell viability following acid exposure with LDH and the MTT assay. The rate of apoptosis was lower in the ASIC la-silenced cell line than that in the wild-type C6 cell line. The percentage of sub-G0 cells was lower in the ASICla-silenced C6 cells than that in the wild-type cells. Conclusion: Extracellular acid induced cell death and apoptosis viaASICla mechanisms in the C6 glioma cells.

  6. A 58 nW ECG ASIC With Motion-Tolerant Heartbeat Timing Extraction for Wearable Cardiovascular Monitoring.

    Science.gov (United States)

    Da He, David; Sodini, Charles G

    2015-06-01

    An ASIC for wearable cardiovascular monitoring is implemented using a topology that takes advantage of the electrocardiogram's (ECG) waveform to replace the traditional ECG instrumentation amplifier, ADC, and signal processor with a single chip solution. The ASIC can extract heartbeat timings in the presence of baseline drift, muscle artifact, and signal clipping. The circuit can operate with ECGs ranging from the chest location to remote locations where the ECG magnitude is as low as 30 μV. Besides heartbeat detection, a midpoint estimation method can accurately extract the ECG R-wave timing, enabling the calculations of heart rate variability. With 58 nW of power consumption at 0.8 V supply voltage and 0.76 mm (2) of active die area in standard 0.18 μm CMOS technology, the ECG ASIC is sufficiently low power and compact to be suitable for long term and wearable cardiovascular monitoring applications under stringent battery and size constraints. PMID:25252285

  7. Design and ASIC Implemenatation of DUC/DDC for Communication Systems

    Directory of Open Access Journals (Sweden)

    Naagesh S. Bhat

    2012-01-01

    Full Text Available Communication systems use the concept of transmitting information using the electrical distribution network as a communication channel. To enable the transmission data signal modulated on a carrier signal is superimposed on the electrical wires. Typical power lines are designed to handle 50/60 Hz of AC power signal; however they can carry the signals up to 500 KHz frequency. This work aims to aid transmission/reception of an audio signal in the spectrum from 300 Hz to 4000 Hz using PLCC on a tunable carrier frequency in the spectrum from 200 KHz to 500 KHz. For digital amplitude modulation the sampling rate of the carrier and the audio signal has to be matched. Tunable carrier generation can be achieved with Direct Digital Synthesizers at a desired sampling rate. DSP Sample rate conversion techniques are very useful to make the sampling circuits to work on their own sampling rates which are fine for the data/modulated-carrier signal’s bandwidth. This also simplifies the complexity of the samplingcircuits. Digital Up Conversion (DUC and Digital Down Conversion (DDC are DSP sample rate conversion techniques which refer to increasing and decreasing the sampling rate of a signal respectively. The objective was to design and implement low power ASIC of DUC and DDC designs at 65nm for PLCC. Low power implementation was carried out using Multi-VDD technique. MATLAB software models were used to understand the DUC and DDC designs. RTL to GDS flow was executed using Synopsys tools such as VCS, Design Compiler, IC Compiler and PrimeTime. Key milestones of this activity are RTL verification, synthesis, gate-level simulations, low power architecture definitions, physical implementation, ASIC signoff checks and postroute delay based simulations. Multi-VDD technique deployed on DUC and DDC helped to reduce the power consumption from 280.9uW to 198.07uW and from 176.26uW to 124.47uW respectively. DUC and DUC designs have met functionality at 64MHz clock

  8. Design and ASIC Implemenatation of DUC/DDC for Communication Systems

    Directory of Open Access Journals (Sweden)

    Naagesh S. Bhat

    2011-12-01

    Full Text Available Communication systems use the concept of transmitting information using the electrical distribution network as a communication channel. To enable the transmission data signal modulated on a carrier signal is superimposed on the electrical wires. Typical power lines are designed to handle 50/60 Hz of AC power signal; however they can carry the signals up to 500 KHz frequency. This work aims to aid transmission/reception of an audio signal in the spectrum from 300 Hz to 4000 Hz using PLCC on a t unable carrier frequency in the spectrum from 200 KHz to 500 KHz. For digital amplitude modulation the sampling rate of the carrier and the audio signal has to be matched. T unable carrier generation can be achieved with Direct Digital Synthesizers at a desired sampling rate. DSP Sample rate conversion techniques are very useful to make the sampling circuits to work on their own sampling rates which are fine for the data/modulated-carrier signal’s bandwidth. This also simplifies the complexity of the sampling circuits. Digital Up Conversion (DUC and Digital Down Conversion (DDC are DSP sample rate conversion techniques which refer to increasing and decreasing the sampling rate of a signal respectively. The objective was to design and implement low power ASIC of DUC and DDC designs at 65nm for PLCC. Low power implementation was carried out using Multi-VDD technique. MATLAB software models were used to understand the DUC and DDC designs. RTL to GDS flow was executed using Synopsys tools such as VCS, Design Compiler, IC Compiler and Prime Time. Key milestones of this activity are RTL verification, synthesis, gate-level simulations, low power architecture definitions, physical implementation, ASIC signoff checks and post route delay based simulations. Multi-VDD technique deployed on DUC and DDC helped to reduce the power consumption from 280.9uW to 198.07uW and from 176.26uW to 124.47uW respectively. DUC and DUC designs have met functionality at 64MHz clock

  9. Radiation tolerant power converter controls

    CERN Document Server

    Todd, B; King, Q; Uznanski, S

    2012-01-01

    The Large Hadron Collider (LHC) at the European Organisation for Nuclear Research (CERN) is the world's most powerful particle collider. The LHC has several thousand magnets, both warm and super-conducting, which are supplied with current by power converters. Each converter is controlled by a purpose-built electronic module called a Function Generator Controller (FGC). The FGC allows remote control of the power converter and forms the central part of a closed-loop control system where the power converter voltage is set, based on the converter output current and magnet-circuit characteristics. Some power converters and FGCs are located in areas which are exposed to beam-induced radiation. There are numerous radiation induced effects, some of which lead to a loss of control of the power converter, having a direct impact upon the accelerator's availability. Following the first long shut down (LS1), the LHC will be able to run with higher intensity beams and higher beam energy. This is expected to lead to signifi...

  10. ASIC Wafer Test System for the ATLAS Semiconductor Tracker Front-End Chip

    International Nuclear Information System (INIS)

    An ASIC wafer test system has been developed to provide comprehensive production screening of the ATLAS Semiconductor Tracker front-end chip (ABCD3T). The ABCD3T[1] features a 128-channel analog front-end, a digital pipeline, and communication circuitry, clocked at 40 MHz, which is the bunch crossing frequency at the LHC (Large Hadron Collider). The tester measures values and tolerance ranges of all critical IC parameters, including DC parameters, electronic noise, time resolution, clock levels and clock timing. The tester is controlled by an FPGA (ORCA3T) programmed to issue the input commands to the IC and to interpret the output data. This allows the high-speed wafer-level IC testing necessary to meet the production schedule. To characterize signal amplitudes and phase margins, the tester utilizes pin-driver, delay, and DAC chips, which control the amplitudes and delays of signals sent to the IC under test. Output signals from the IC under test go through window comparator chips to measure their levels. A probe card has been designed specifically to reduce pick-up noise that can affect the measurements. The system can operate at frequencies up to 100 MHz to study the speed limits of the digital circuitry before and after radiation damage. Testing requirements and design solutions are presented

  11. Analogue sum ASIC for L1 trigger decision in Cherenkov Telescope cameras

    International Nuclear Information System (INIS)

    The Cherenkov Telescope Array (CTA) project [1] aims to build the largest ground-based gamma-ray observatory based on an array of Imaging Atmospheric Cherenkov Telescopes (IACTs). The CTA will implement a multi-level trigger system to distinguish between gamma ray-like induced showers and background images induced by night sky background (NSB) light [2]. The trigger system is based on coincident detections among pixels (level 0 trigger), clusters of pixels (level 1) or telescopes. In this article, the first version of the application specific integrated circuit (ASIC) for Level 1 trigger system is presented, capable of working with different Level 0 strategies and different trigger region sizes. In addition, it complies with all the requirements specified by the CTA project, specially the most critical ones as regards noise, bandwidth, dynamic range and power consumption. All these features make the presented system very suitable for use in the CTA cameras and improve the features of discrete components prototypes of the L1 trigger circuit in terms of compactness, noise, performance and power consumption

  12. The PASTA chip - A free-running readout ASIC for silicon strip sensors in PANDA

    International Nuclear Information System (INIS)

    The PANDA experiment is a multi purpose detector, investigating hadron physics in the charm quark mass regime. It is one of the main experiments at the future FAIR accelerator facility, using pp annihilations from a 1.5-15 GeV/c anti-proton beam. Because of the broad physics spectrum and the similarity of event and background signals, PANDA does not rely on a hardware-level trigger decision. The innermost of PANDA's sub-systems is the Micro Vertex Detector (MVD), consisting of silicon pixel and strip sensors. The latter will be read out by a specialized, free-running readout front-end called PANDA Strip ASIC (PASTA). It has to face a high event rate of up to 40 kHz/ch in an radiation-intense environment. To fulfill the MVD's requirements, it has to give accurate timing information to incoming events (<10 ns) and determine the collected charge with an 8-bit precision. The design has to meet cooling and placing restrictions, leading to a very low power consumption (<4 mW/ch) and limited dimensions. Therefore, a simple, time-based readout approach is chosen. In this talk, the conceptual design of the front-end is presented.

  13. Sensor-based whole-arm obstacle avoidance utilizing ASIC technology

    International Nuclear Information System (INIS)

    Operation of manipulator systems in poorly defined work environments often presents a significant hazard to both the robotic assembly and the environment. In applications relating to the Environmental Restoration and Waste Management (ER ampersand WM) Program, many of the environments are considered hazardous, both, in the structure and composition of the environment Use of a sensing system that provides information to the manipulator control unit regarding obstacles in close proximity will provide protection against collisions. In this paper, a hierarchical design and implementation of a whole-arm obstacle avoidance system is presented. The system is based on capacitive sensors configured as bracelets for proximity sensing. Each bracelet contains a number of sensor nodes and a processor for sensor node control and readout, and communications with a higher level host, common to all bracelets. The host controls the entire sensing network and communicates proximity information to the manipulator controller. The overall architecture of this system is discussed with detail on the individual system modules. Details of an application specific integrated circuit (ASIC) designed to implement the sensor node electronics are presented. Justifications for the general measurement methods and associated implementation are discussed. Additionally, the current state of development including measured dam is presented

  14. Single event effect hardness for the front-end ASICs in the DAMPE satellite BGO calorimeter

    Science.gov (United States)

    Shan-Shan, Gao; Di, Jiang; Chang-Qing, Feng; Kai, Xi; Shu-Bin, Liu; Qi, An

    2016-01-01

    The Dark Matter Particle Explorer (DAMPE) is a Chinese scientific satellite designed for cosmic ray studies with a primary scientific goal of indirect detection of dark matter particles. As a crucial sub-detector, the BGO calorimeter measures the energy spectrum of cosmic rays in the energy range from 5 GeV to 10 TeV. In order to implement high-density front-end electronics (FEE) with the ability to measure 1848 signals from 616 photomultiplier tubes on the strictly constrained satellite platform, two kinds of 32-channel front-end ASICs, VA160 and VATA160, are customized. However, a space mission period of more than 3 years makes single event effects (SEEs) become threats to reliability. In order to evaluate SEE sensitivities of these chips and verify the effectiveness of mitigation methods, a series of laser-induced and heavy ion-induced SEE tests were performed. Benefiting from the single event latch-up (SEL) protection circuit for power supply, the triple module redundancy (TMR) technology for the configuration registers and the optimized sequential design for the data acquisition process, 52 VA160 chips and 32 VATA160 chips have been applied in the flight model of the BGO calorimeter with radiation hardness assurance. Supported by Strategic Priority Research Program on Space Science of the Chinese Academy of Sciences (XDA04040202-4) and Fundamental Research Funds for the Central Universities (WK2030040048)

  15. Calibration of ultra-thin hybrid pixel detector assemblies with Timepix readout ASICs

    CERN Document Server

    AUTHOR|(SzGeCERN)734627; Arfaoui, Samir; Benoit, Mathieu; Celeste, Damiano; Dannheim, Dominik; Pfleger, Florentina; Redford, Sophie

    2015-01-01

    In the framework of vertex detector R&D for a future Compact Linear Collider, the charac- terisation of ultra-thin hybrid pixel detector assemblies comprising 50 − 300 μm thick silicon sensors and Timepix readout ASICs is underway through beam tests at DESY and CERN. The work presented here supports the beam test data analysis by providing an energy calibra- tion of certain assemblies, so giving access to energy measurements in addition to recorded Time Over Threshold counts. Photons from a variety of radioactive sources and X-ray fluorescence are used to measure the response of the assemblies in the region of 3 − 60 keV. Threshold measurements are also performed. Global and pixel-by-pixel calibrations of the assemblies are parametrised and the uniformity of the response of the pixel matrices are discussed. Data samples recorded in beam tests are calibrated and the resulting energy spectra presented. For the first time calibration parameters are estimated for two 50 μm thick sensors which are forese...

  16. The coincidence matrix ASIC of the level-1 muon barrel trigger of the ATLAS experiment

    CERN Document Server

    Bocci, V; Salamon, A; Vari, R; Veneziano, Stefano

    2003-01-01

    The ATLAS barrel level-1 muon trigger processes hit information from the resistive plate chamber detector, identifying candidate muon tracks and assigning them to a programmable p/sub T/ range and to a unique bunch crossing number. The trigger system uses up to seven detector layers and seeks hit patterns compatible with muon tracks in the bending and nonbending projection. The basic principle of the algorithm is to demand a coincidence of hits in the different chamber layers within a path. The width of the road is related to the p/sub T / threshold to be applied. The system is split into an on-detector and an off-detector part. The on-detector electronics reduces the information from about 350 k channels to about 400 32-bit data words sent via optical fiber to the so-called sector logic (SL). The off- detector SL electronics collects muon candidates and associates them to detector regions-of-interest of Delta eta * Delta Phi of 0.1*0.1. The core of the on-detector electronics is the coincidence matrix ASIC (...

  17. Front-end ASICs development for W Si calorimeter at ILC (CALICE collaboration)

    Science.gov (United States)

    Fleury, Julien; de La Taille, Christophe; Martin-Chassard, Gisèle

    2007-03-01

    An ASIC (FLC_PHY3) has been developed to read out the test-beam prototype of the future international linear collider (ILC) tungsten-silicon calorimeter. It consists of 18 channels low-noise charge preamplifiers, bi-gain CRRC2 180 ns shapers, 12-bit track-and-hold, and a 5 MHz output multiplexer. It covers a dynamic range of 14 bits with a noise of 3500 e - with the 70 pF detector and a linearity at the per-mil level. The chip dissipates 6 mW/channel and 1000 chips have been produced in AMS 0.8 μm BiCMOS technology in 2003. One channel has recently been migrated into 0.35 μm, improving the series noise by 20% and the 1/ f noise by two. Besides, a power pulsing feature has been added in order to exploit the 1% duty cycle of the accelerator. This feature is a key parameter for ILC, as it is mandatory to embed the front-end inside the detector, without spoiling the Moliere radius with cooling pipes. Preliminary results indicate a good behavior in pulsing mode and several hundred channels have been produced of the recent version including this feature (FLC_PHY4), to be tested extensively in test beam at CERN in autumn 2006. FLC_PHY4 also includes a 12-bit ADC in order to take a step to the final version, which will send digital data out.

  18. A pixel detector asic for dosimetry using time-over-threshold energy measurements

    CERN Document Server

    Wong, W S; Ballabriga, R; Bohnel, M; Campbell, M; Heijne, E; Llopart, X; Michel, T; Munster, I; Plackett, R; Sievers, P; Takoukam, P; Tlustos, L; Valerio, P

    2011-01-01

    In this work we present the design of a chip which provides the readout of a highly segmented diode array, in which signals induced by individual X-ray photons are processed discretely. There are several benefits to this approach, including the ability to achieve a high signal to noise ratio due to the inherently low sensor capacitance, and the suppression of background noise (e.g. dark current) using an analogue threshold. The segmentation also ensures a linear behaviour even at very high dose rates. A time over threshold (ToT) energy measurement technique provides an immediate digital value corresponding to the energy deposited onto the diode by each individual photon. Deadtime-free operation is achieved by reading out a subset of the detector segments at a time while the rest of the detector continues to process signals. This paper describes the application-specific integrated circuit (ASIC) chip which was designed to provide pre-processing of photo-induced signals in the detector and readout of the proces...

  19. A 15 GSa/s, 1.5 GHz bandwidth waveform digitizing ASIC

    International Nuclear Information System (INIS)

    The PSEC4 custom integrated circuit was designed for the recording of fast waveforms for use in large-area time-of-flight detector systems. The ASIC has been fabricated using the IBM-8RF 0.13μm CMOS process. On each of the six analog channels, PSEC4 employs a switched capacitor array (SCA) of 256 samples deep, a ramp-compare ADC with 10.5 bits of DC dynamic range, and a serial data readout with the capability of region-of-interest windowing to reduce dead time. The sampling rate can be adjusted between 4 and 15 Gigasamples/second (GSa/s) on all channels and is servo-controlled on-chip with a low-jitter delay-locked loop (DLL). The input signals are passively coupled on-chip with a −3 dB analog bandwidth of 1.5 GHz. The power consumption in quiescent sampling mode is less than 50 mW/chip; at a sustained trigger and a readout rate of 50 kHz the chip draws 100 mW. After fixed-pattern pedestal subtraction, the uncorrected integral non-linearity is 0.15% over a 750 mV dynamic range. With a linearity correction, a full 1 V signal voltage range is available. The sampling timebase has a fixed-pattern non-linearity with an RMS of 13%, which can be corrected for precision waveform feature extraction and timing

  20. CLARO-CMOS, a very low power ASIC for fast photon counting with pixellated photodetectors

    CERN Document Server

    Carniti, Paolo

    2012-01-01

    The CLARO-CMOS is an application specific integrated circuit (ASIC) designed for fast photon counting with pixellated photodetectors such as multi-anode photomultiplier tubes (Ma-PMT), micro-channel plates (MCP), and silicon photomultipliers (SiPM). The first prototype has four channels, each with a charge sensitive amplifier with settable gain and a discriminator with settable threshold, providing fast hit information for each channel independently. The design was realized in a long-established, stable and inexpensive 0.35 um CMOS technology, and provides outstanding performance in terms of speed and power dissipation. The prototype consumes less than 1 mW per channel at low rate, and less than 2 mW at an event rate of 10 MHz per channel. The recovery time after each pulse is less than 25 ns for input signals within a factor of 10 above threshold. Input referred RMS noise is about 7.7 ke^- (1.2 fC) with an input capacitance of 3.3 pF. Thanks to the low noise and high speed, a timing resolution down to 10 ps ...

  1. Development of the analog ASIC for multi-channel readout X-ray CCD camera

    CERN Document Server

    Nakajima, Hiroshi; Idehara, Toshihiro; Anabuki, Naohisa; Tsunemi, Hiroshi; Doty, John P; Ikeda, Hirokazu; Katayama, Haruyoshi; Kitamura, Hisashi; Uchihori, Yukio; 10.1016/j.nima.2010.12.174

    2011-01-01

    We report on the performance of an analog application-specific integrated circuit (ASIC) developed aiming for the front-end electronics of the X-ray CCDcamera system onboard the next X-ray astronomical satellite, ASTRO-H. It has four identical channels that simultaneously process the CCD signals. Distinctive capability of analog-to-digital conversion enables us to construct a CCD camera body that outputs only digital signals. As the result of the front-end electronics test, it works properly with low input noise of =<30 uV at the pixel rate below 100 kHz. The power consumption is sufficiently low of about 150 mW/chip. The input signal range of 720 mV covers the effective energy range of the typical X-ray photon counting CCD (up to 20 keV). The integrated non-linearity is 0.2% that is similar as those of the conventional CCDs in orbit. We also performed a radiation tolerance test against the total ionizing dose (TID) effect and the single event effect. The irradiation test using 60Co and proton beam showed ...

  2. A pixel detector asic for dosimetry using time-over-threshold energy measurements

    International Nuclear Information System (INIS)

    In this work we present the design of a chip which provides the readout of a highly segmented diode array, in which signals induced by individual X-ray photons are processed discretely. There are several benefits to this approach, including the ability to achieve a high signal to noise ratio due to the inherently low sensor capacitance, and the suppression of background noise (e.g. dark current) using an analogue threshold. The segmentation also ensures a linear behaviour even at very high dose rates. A time over threshold (ToT) energy measurement technique provides an immediate digital value corresponding to the energy deposited onto the diode by each individual photon. Deadtime-free operation is achieved by reading out a subset of the detector segments at a time while the rest of the detector continues to process signals. This paper describes the application-specific integrated circuit (ASIC) chip which was designed to provide pre-processing of photo-induced signals in the detector and readout of the processed digital data.

  3. A 15 GSa/s, 1.5 GHz Bandwidth Waveform Digitizing ASIC

    CERN Document Server

    Oberla, E; Grabas, H; Frisch, H; Nishimura, K; Varner, G

    2013-01-01

    The PSEC4 custom integrated circuit was designed for the recording of fast waveforms for use in large-area time-of-flight detector systems. The ASIC has been fabricated using the IBM-8RF 0.13 micron CMOS process. On each of 6 analog channels, PSEC4 employs a switched capacitor array (SCA) 256 samples deep, a ramp-compare ADC with 10.5 bits of DC dynamic range, and a serial data readout with the capability of region-of-interest windowing to reduce dead time. The sampling rate can be adjusted between 4 and 15 Gigasamples/second [GSa/s] on all channels and is servo-controlled on-chip with a low-jitter delay-locked loop (DLL). The input signals are passively coupled on-chip with a -3 dB analog bandwidth of 1.5 GHz. The power consumption in quiescent sampling mode is less than 50 mW/chip; at a sustained trigger and readout rate of 50 kHz the chip draws 100 mW. After fixed-pattern pedestal subtraction, the uncorrected integral non-linearity is 0.15% over an 750 mV dynamic range. With a linearity correction, a full ...

  4. Systematic study of new types of Hamamatsu MPPCs read out with the NINO ASIC

    CERN Document Server

    Doroud, K; Williams, M C S; Yamamoto, K; Zichichi, A; Zuyeuski, R

    2014-01-01

    Over the last decade there have been commercial TOF-PET scanners constructed using Photo-Multiplier Tubes (PMT) that have achieved View the MathML source~500ps FWHM Coincidence Time Resolution (CTR). A new device known as the Silicon PhotoMultiplier (SiPM) has the potential to overcome some of the limitations of the PMT. Therefore implementing a SiPM based TOF-PET scanner is of high interest. Recently Philips has introduced a TOF-PET scanner that uses digital Silicon PhotoMultipliers (d-SiPMs) which has a CTR of 350 ps. Here we will report on the timing performance of two Hamamatsu 3×3 mm2 analogue-SiPMs read out with the NINO ASIC: this is an ultra-fast amplifier/discriminator with a differential architecture. The differential architecture is very important since the single-ended readout uses the ground as the signal return; as the ground is also the reference level for the discriminators, the result is high crosstalk and degraded time resolution. However differential readout allows the scaling up from a si...

  5. AFTER, the front end ASIC of the T2K Time Projection Chambers

    CERN Document Server

    Baron, P; Calvet, D; de la Broise, X; Delagnes, E; Delbart, A; Druillole, F; Le Coguie, A; Mazzucato, E; Monmarthe, E; Zito, M

    2009-01-01

    The T2K (Tokai-to-Kamioka) experiment is a long baseline neutrino oscillation experiment in Japan. A near detector, located at 280m of the production target, is used to characterize the beam. One of its key elements is a tracker, made of three Time Projection Chambers (TPC) read by Micromegas endplates. A new readout system has been developed to collect, amplify, condition and acquire the data produced by the 124,000 detector channels of these detectors. The front-end element of this system is a a new 72-channel application specific integrated circuit. Each channel includes a low noise charge preamplifier, a pole zero compensation stage, a second order Sallen-Key low pass filter and a 511-cell Switched Capacitor Array. This electronics offers a large flexibility in sampling frequency, shaping time, gain, while taking advantage of the low physics events rate of 0.3 Hz. We detail the design and the performance of this ASIC and report on the deployment of the frond-end electronics on-site.

  6. Latest results of SEE measurements obtained by the STRURED demonstrator ASIC

    Energy Technology Data Exchange (ETDEWEB)

    Candelori, A. [INFN, Section of Padova, Via Marzolo 8, c.a.p. 35131, Padova (Italy); De Robertis, G. [INFN Section of Bari, Via Orabona 4, c.a.p. 70126, Bari (Italy); Gabrielli, A. [Physics Department, University of Bologna, Viale Berti Pichat 6/2, c.a.p. 40127, Bologna (Italy); Mattiazzo, S.; Pantano, D. [INFN, Section of Padova, Via Marzolo 8, c.a.p. 35131, Padova (Italy); Ranieri, A., E-mail: antonio.ranieri@ba.infn.i [INFN Section of Bari, Via Orabona 4, c.a.p. 70126, Bari (Italy); Tessaro, M. [INFN, Section of Padova, Via Marzolo 8, c.a.p. 35131, Padova (Italy)

    2011-01-21

    With the perspective to develop a radiation-tolerant circuit for High Energy Physics (HEP) applications, a test digital ASIC VLSI chip, called STRURED, has been designed and fabricated using a standard-cell library of commercial 130 nm CMOS technology by implementing three different radiation-tolerant architectures (Hamming, Triple Modular Redundancy and Triple Time Redundancy) in order to correct circuit malfunctions induced by the occurrence of Soft Errors (SEs). SEs are one of the main reasons of failures affecting electronic digital circuits operating in harsh radiation environments, such as in experiments performed at HEP colliders or in apparatus to be operated in space. In this paper we present and discuss the latest results of SE cross-section measurements performed using the STRURED digital device, exposed to high energy heavy ions at the SIRAD irradiation facility of the INFN National Laboratories of Legnaro (Padova, Italy). In particular the different behaviors of the input part and the core of the three radiation-tolerant architectures are analyzed in detail.

  7. Latest results of SEE measurements obtained by the STRURED demonstrator ASIC

    International Nuclear Information System (INIS)

    With the perspective to develop a radiation-tolerant circuit for High Energy Physics (HEP) applications, a test digital ASIC VLSI chip, called STRURED, has been designed and fabricated using a standard-cell library of commercial 130 nm CMOS technology by implementing three different radiation-tolerant architectures (Hamming, Triple Modular Redundancy and Triple Time Redundancy) in order to correct circuit malfunctions induced by the occurrence of Soft Errors (SEs). SEs are one of the main reasons of failures affecting electronic digital circuits operating in harsh radiation environments, such as in experiments performed at HEP colliders or in apparatus to be operated in space. In this paper we present and discuss the latest results of SE cross-section measurements performed using the STRURED digital device, exposed to high energy heavy ions at the SIRAD irradiation facility of the INFN National Laboratories of Legnaro (Padova, Italy). In particular the different behaviors of the input part and the core of the three radiation-tolerant architectures are analyzed in detail.

  8. Front-end ASICs development for W-Si calorimeter at ILC

    International Nuclear Information System (INIS)

    An ASIC (FLCPHY3) has been developed to read out the test-beam prototype of the future international linear collider (ILC) tungsten-silicon calorimeter. It consists of 18 channels low-noise charge preamplifiers, bi-gain CRRC2 180 ns shapers, 12-bit track-and-hold, and a 5 MHz output multiplexer. It covers a dynamic range of 14 bits with a noise of 3500 e- with the 70 pF detector and a linearity at the per-mil level. The chip dissipates 6 mW/channel and 1000 chips have been produced in AMS 0.8 μm BiCMOS technology in 2003. One channel has recently been migrated into 0.35 μm, improving the series noise by 20% and the 1/f noise by two. Besides, a power pulsing feature has been added in order to exploit the 1% duty cycle of the accelerator. This feature is a key parameter for ILC, as it is mandatory to embed the front-end inside the detector, without spoiling the Moliere radius with cooling pipes. Preliminary results indicate a good behavior in pulsing mode and several hundred channels have been produced of the recent version including this feature (FLCPHY4), to be tested extensively in test beam at CERN in autumn 2006. FLCPHY4 also includes a 12-bit ADC in order to take a step to the final version, which will send digital data out

  9. Reading a GEM with a VLSI pixel ASIC used as a direct charge collecting anode

    CERN Document Server

    Bellazzini, R; Baldini, L; Bitti, F; Brez, A; Latronico, L; Massai, M M; Minuti, M; Omodei, N; Razzano, M; Sgro, C; Spandre, G; Costa, E; Soffitta, P

    2004-01-01

    In MicroPattern Gas Detectors (MPGD) when the pixel size is below 100 micron and the number of pixels is large (above 1000) it is virtually impossible to use the conventional PCB read-out approach to bring the signal charge from the individual pixel to the external electronics chain. For this reason a custom CMOS array of 2101 active pixels with 80 micron pitch, directly used as the charge collecting anode of a GEM amplifying structure, has been developed and built. Each charge collecting pad, hexagonally shaped, realized using the top metal layer of a deep submicron VLSI technology is individually connected to a full electronics chain (pre-amplifier, shaping-amplifier, sample and hold, multiplexer) which is built immediately below it by using the remaining five active layers. The GEM and the drift electrode window are assembled directly over the chip so the ASIC itself becomes the pixelized anode of a MicroPattern Gas Detector. With this approach, for the first time, gas detectors have reached the level of i...

  10. ABSTRACTS OF THE “GIORNATE DI CONIGLICOLTURA ASIC 2011”

    Directory of Open Access Journals (Sweden)

    ABSTRACTS OF THE “GIORNATE DI CONIG Forlì, Italy,

    2012-10-01

    Full Text Available The fourth edition of the Italian Rabbit Days was held in Forlì (Italy on April 8-9, 2011, organized by ASIC (Italian Rabbit Scientific Association in collaboration with Dipartimento di Scienze degli Alimenti (Università di Bologna, Dipartimento di Scienze Animali (Università di Padova, Fondazione Iniziative Zooprofilattiche e Zootecniche (Brescia, ASPA (Animal Production Scientific Association and the Forli Fair. The first day included three invited lectures: “Feed restriction strategies, implications on physiology, growth and health of the growing rabbit”, presented by T. Gidenne, L. Fortun-Lamothe, S. Combes; “Ovulation induction in rabbit does: a review”, presented by A. Dal Bosco; “Factors affecting efficacy of intravaginal administration of GnRH analogues for ovulation induction in rabbit does” presented by P.G. Rebollar. In addition, three sessions of oral communications on Reproduction and Genetics, Nutrition and Physiology, Welfare, Management, and Pathology were held. During the second day it was presented a round table focused on “Management and use of drugs and vaccines in rabbit production”. Finally a Poster Session was through the two days. The meeting was attended by more than 100 participants, including researchers and technicians from France, Spain, Hungary, Belgium and Switzerland. A total of 3 invited papers, 14 oral communications and 16 posters were presented during the congress. Following the abstracts of all contributions are reported.

  11. The PASTA chip - A free-running readout ASIC for silicon strip sensors in PANDA

    Energy Technology Data Exchange (ETDEWEB)

    Goerres, Andre; Stockmanns, Tobias; Ritman, James [Institut fuer Kernphysik, Forschungszentrum Juelich, Juelich (Germany); Rivetti, Angelo [INFN Sezione di Torino, Torino (Italy); Collaboration: PANDA-Collaboration

    2014-07-01

    The PANDA experiment is a multi purpose detector, investigating hadron physics in the charm quark mass regime. It is one of the main experiments at the future FAIR accelerator facility, using pp annihilations from a 1.5-15 GeV/c anti-proton beam. Because of the broad physics spectrum and the similarity of event and background signals, PANDA does not rely on a hardware-level trigger decision. The innermost of PANDA's sub-systems is the Micro Vertex Detector (MVD), consisting of silicon pixel and strip sensors. The latter will be read out by a specialized, free-running readout front-end called PANDA Strip ASIC (PASTA). It has to face a high event rate of up to 40 kHz/ch in an radiation-intense environment. To fulfill the MVD's requirements, it has to give accurate timing information to incoming events (<10 ns) and determine the collected charge with an 8-bit precision. The design has to meet cooling and placing restrictions, leading to a very low power consumption (<4 mW/ch) and limited dimensions. Therefore, a simple, time-based readout approach is chosen. In this talk, the conceptual design of the front-end is presented.

  12. Laser system with wavelength converter

    DEFF Research Database (Denmark)

    2012-01-01

    The present invention relates to an apparatus comprising a diode laser (10) providing radiation in a first wavelength interval, a radiation conversion unit (12) having an input and an output, the radiation converter configured to receive the radiation in the first wavelength interval from the diode...... laser at the input, the radiation conversion unit configured to convert the radiation in the first wavelength interval to radiation in a second wavelength interval and the output configured to output the converted radiation, the second wavelength interval having one end point outside the first...... wavelength interval. Further, the invention relates to a method of optically pumping a target laser (14) in a laser system, the laser system comprising a laser source providing radiation at a first frequency, the laser source being optically connected to an input of a frequency converter, the frequency...

  13. Time-to-digital converters

    CERN Document Server

    Henzler, Stephan

    2010-01-01

    This text covers the fundamentals of time-to-digital converters on analog and digital conversion principles. It includes a theoretical investigation into quantization, linearity, noise and variability, and it details a range of advanced TDC architectures.

  14. Boron nitride converted carbon fiber

    Energy Technology Data Exchange (ETDEWEB)

    Rousseas, Michael; Mickelson, William; Zettl, Alexander K.

    2016-04-05

    This disclosure provides systems, methods, and apparatus related to boron nitride converted carbon fiber. In one aspect, a method may include the operations of providing boron oxide and carbon fiber, heating the boron oxide to melt the boron oxide and heating the carbon fiber, mixing a nitrogen-containing gas with boron oxide vapor from molten boron oxide, and converting at least a portion of the carbon fiber to boron nitride.

  15. PHASE CONVERTER OF COMPOSING DISPLACEMENT

    OpenAIRE

    SMIRNOV YU.S.; Lysov, A. N.; E.V. Yurasova; SAFRONOV V.V.; VSTAVSKAYA E.V.

    2016-01-01

    Minimax strategy of mechatronic converters efficiency improving relative to error decrease with velocity increase at the same time provides common dataware level rise. The analysis of usage possibilities of different type position transducers (PT) gives the advantages of resolvers. The subsequent processing of their output signals is performed by “Resolver-to-Digit” Converter (RDC) which provides displacement digital equivalent and digital or analog signals specifying its velocity and acceler...

  16. The charge pump PLL clock generator designed for the 1.56 ns bin size time-to-digital converter pixel array of the Timepix3 readout ASIC

    CERN Document Server

    Fu, Y et al.

    2014-01-01

    Timepix3 is a newly developed pixel readout chip which is expected to be operated in a wide range of gaseous and silicon detectors. It is made of 256×256 pixels organized in a square pixel-array with 55 µm pitch. Oscillators running at 640 MHz are distributed across the pixel-array and allow for a highly accurate measurement of the arrival time of a hit. This paper concentrates on a low-jitter phase locked loop (PLL) that is located in the chip periphery. This PLL provides a control voltage which regulates the actual frequency of the individual oscillators, allowing for compensation of process, voltage, and temperature variations.

  17. FREQUENCY CONVERTERS WITH IMPROVED PERFORMANCE

    Directory of Open Access Journals (Sweden)

    Grigorash O. V.

    2016-01-01

    Full Text Available In the autonomous power supply systems there are widely used frequency converters that are able to simultaneously increase or decrease the frequency of the current and voltage stabilizing power supply. These positive properties of frequency converters can improve the operational and technical characteristics of the autonomous power supply system in the complex. The article suggests a functional diagram of a frequency converter performed on reversible rectifiers. We have presented timing diagrams illustrating the principle of its operation. The article also deals with two functional scheme of direct frequency converters executed on single-phase, threephase transformer with a rotating magnetic field. The principle of operation of these schemes has been also discussed in the timing diagrams. The proposed technical solutions for frequency converters contain a smaller amount of power electronic devices that make it possible, thereby reducing the level of electromagnetic interference, increase the efficiency and reliability of performance inverters. The considered scheme of frequency converters, can improve the technical characteristics of the autonomous power supply systems in the complex. We can significantly improve the performance of power systems through the use of modular aggregating principle of the basic functional units of an autonomous system

  18. Current status of converter steelmaking

    Energy Technology Data Exchange (ETDEWEB)

    Oghbasialasie, H.; Holappa, L.

    1995-12-31

    This literature work is mainly focusing on the mechanisms of modern converter steelmaking and related with the evaluation of converter technology applied during the last decades and further to the future. The history of steelmaking has been briefly reviewed from bloomeries and early-steelmaking processes to the progress of modern converter process. The pneumatic converter processes were developed in the 1850`s and thereafter the basis for the rapid growth of steel industries was established for the next 100 years. The world production of steel has not continuously grown but fluctuating quite much. It reached 723 Mt in 1994. The production is believed to grow the forecast for the year 2003 being approximately 800 Mt. Electric arc furnace production is estimated to reach 280 Mt by 2003, and BOFIOH will reach 520 Mt by 2003. The current status of the converter steelmaking process is briefly described both on its theoretical bases and practical technological progresses. Developments which significantly improve the process are briefly discussed. Several more recent developments such as combined oxygen blowing process, increased scrap melting, post combustion and hot metal pretreatment are discussed. The future progress will be in further development of these process characteristics as well as in eventual emerging of the continuous converter process. (author)

  19. Development of a low noise readout ASIC for CZT detectors for gamma-ray spectroscopy applications

    International Nuclear Information System (INIS)

    A multi-channel readout ASIC for pixelated CZT detectors has been developed for gamma-ray spectroscopy applications. Each channel consists of a low noise dual-stage charge sensitive amplifier (CSA), a CR-(RC)4 semi-Gaussian shaper and a class-AB output buffer. The equivalent noise charge (ENC) of input PMOS transistor is optimized for 5 pF input capacitance and 1 μs peaking time using gm/ID design methodology. The gain can be adjusted from 100 mV/fC to 400 mV/fC and the peaking time can be adjusted from 1 μs to 4 μs. A 16-channel chip has been designed and fabricated in 0.35 μm 2P4M CMOS technology. The test results show that the chip works well and fully satisfies the design specifications. The ENC was measured to be 72 e + 26 e/pF at 1 μs peaking time and 86 e + 20 e/pF at 4 μs peaking time. The non-uniformity of the channel gain and ENC was less than ±12% and ±11% respectively for 16 channels in one chip. The chip was also tested with a pixelated CZT detector at room temperature. The measured energy resolution at 59.5 keV photopeak of 241Am and 122 keV photopeak of 57Co were 4.5% FWHM and 2.8% FWHM for the central area pixels, respectively.

  20. Systematic study of new types of Hamamatsu MPPCs read out with the NINO ASIC

    Science.gov (United States)

    Doroud, K.; Rodriguez, A.; Williams, M. C. S.; Yamamoto, K.; Zichichi, A.; Zuyeuski, R.

    2014-07-01

    Over the last decade there have been commercial TOF-PET scanners constructed using Photo-Multiplier Tubes (PMT) that have achieved ~ 500 ps FWHM Coincidence Time Resolution (CTR). A new device known as the Silicon PhotoMultiplier (SiPM) has the potential to overcome some of the limitations of the PMT. Therefore implementing a SiPM based TOF-PET scanner is of high interest. Recently Philips has introduced a TOF-PET scanner that uses digital Silicon PhotoMultipliers (d-SiPMs) which has a CTR of 350 ps. Here we will report on the timing performance of two Hamamatsu 3×3 mm2 analogue-SiPMs read out with the NINO ASIC: this is an ultra-fast amplifier/discriminator with a differential architecture. The differential architecture is very important since the single-ended readout uses the ground as the signal return; as the ground is also the reference level for the discriminators, the result is high crosstalk and degraded time resolution. However differential readout allows the scaling up from a single cell to a multi-cell device with no loss of time resolution; this becomes increasingly important for the highly segmented detectors that are being built today, both for particle and for medical instrumentation. We obtained excellent results for both the Single Photon Time Resolution (SPTR) and for the CTR using a LYSO crystal of 15 mm length. Such a crystal length has sufficient detection efficiency for 511 keV gammas to make an excellent PET device. The results presented here are proof that a TOF-PET detector with a CTR of 175 ps is indeed possible. This is the first step that defines the starting point of our SuperNINO project.

  1. Systematic study of new types of Hamamatsu MPPCs read out with the NINO ASIC

    Energy Technology Data Exchange (ETDEWEB)

    Doroud, K. [Museo Storico della Fisica e Centro Studi e Ricerche E. Fermi, Roma (Italy); Rodriguez, A. [CERN, Geneva (Switzerland); ICSC World Laboratory, Geneva (Switzerland); Williams, M.C.S., E-mail: crispin.williams@cern.ch [CERN, Geneva (Switzerland); INFN and Dipartimento di Fisica e Astronomia, Università di Bologna (Italy); Yamamoto, K. [Solid State Division, Hamamatsu Photonics K.K., Hamamatsu (Japan); Zichichi, A. [Museo Storico della Fisica e Centro Studi e Ricerche E. Fermi, Roma (Italy); CERN, Geneva (Switzerland); INFN and Dipartimento di Fisica e Astronomia, Università di Bologna (Italy); Zuyeuski, R. [CERN, Geneva (Switzerland); ICSC World Laboratory, Geneva (Switzerland)

    2014-07-01

    Over the last decade there have been commercial TOF-PET scanners constructed using Photo-Multiplier Tubes (PMT) that have achieved ∼500ps FWHM Coincidence Time Resolution (CTR). A new device known as the Silicon PhotoMultiplier (SiPM) has the potential to overcome some of the limitations of the PMT. Therefore implementing a SiPM based TOF-PET scanner is of high interest. Recently Philips has introduced a TOF-PET scanner that uses digital Silicon PhotoMultipliers (d-SiPMs) which has a CTR of 350 ps. Here we will report on the timing performance of two Hamamatsu 3×3 mm{sup 2} analogue-SiPMs read out with the NINO ASIC: this is an ultra-fast amplifier/discriminator with a differential architecture. The differential architecture is very important since the single-ended readout uses the ground as the signal return; as the ground is also the reference level for the discriminators, the result is high crosstalk and degraded time resolution. However differential readout allows the scaling up from a single cell to a multi-cell device with no loss of time resolution; this becomes increasingly important for the highly segmented detectors that are being built today, both for particle and for medical instrumentation. We obtained excellent results for both the Single Photon Time Resolution (SPTR) and for the CTR using a LYSO crystal of 15 mm length. Such a crystal length has sufficient detection efficiency for 511 keV gammas to make an excellent PET device. The results presented here are proof that a TOF-PET detector with a CTR of 175 ps is indeed possible. This is the first step that defines the starting point of our SuperNINO project.

  2. Post combustion in converter steelmaking

    Energy Technology Data Exchange (ETDEWEB)

    Oghbasilasie, H.; Holappa, L.

    1997-12-31

    The purpose of this work is to study the fundamentals of post combustion and the effect of different process parameters on the post combustion ratio (PCR) and heat transfer efficiency (HTE) in converter steelmaking process. The PCR and HTE have been determined under normal operating conditions. Trials assessed the effect of lance height, vessel volume, foaming slag and pellet additions on PCR and HTE. Based on enthalpy considerations, post combustion of CO gas is regarded as one of the most effective means of increasing the heat supply to the BOP. The thermodynamic study of gas-metal-slag reactions gives the limiting conditions for post combustion inside the converter reactor. Different process parameters influencing both thermodynamic equilibria and kinetic conditions can greatly affect the post combustion ratio. Different features of converter processes as well smelting reduction processes utilizing post combustion have been reviewed. (orig.) SULA 2 Research Programme; 26 refs.

  3. Increasing of Reliability of Converter

    Directory of Open Access Journals (Sweden)

    Trebuňa, F.

    2006-01-01

    Full Text Available The innovative activities in steel production invoke exploitation of new machines with the higher production capacity and productivity of labor. The paper deals with deformation and stress analysis of carrying parts of converter pedestal on the base of which the proposals and supporting measures were made that had the aim to increase reliability of the converter during steel production. This was achieved by lifespan prolongation of anchor and connecting bolts of converter pedestal, by change of stiffness of connected elements as well as by correction of nuts of bolted connections. The realization of structural changes decreased loading amplitudes and consequently the vibrations of pedestal. Solution was verified by numerical and experimental procedures of mechanics.

  4. A conformation change in the extracellular domain that accompanies desensitization of acid-sensing ion channel (ASIC) 3.

    Science.gov (United States)

    Cushman, Kenneth A; Marsh-Haffner, Josephine; Adelman, John P; McCleskey, Edwin W

    2007-04-01

    Acid-sensing ion channels (ASICs) are thought to trigger some forms of acid-induced pain and taste, and to contribute to stroke-induced neural damage. After activation by low extracellular pH, different ASICs undergo desensitization on time scales from 0.1 to 10 s. Consistent with a substantial conformation change, desensitization slows dramatically when temperature drops (Askwith, C.C., C.J. Benson, M.J. Welsh, and P.M. Snyder. 2001. PNAS. 98:6459-6463). The nature of this conformation change is unknown, but two studies showed that desensitization rate is altered by mutations on or near the first transmembrane domain (TM1) (Coric, T., P. Zhang, N. Todorovic, and C.M. Canessa. 2003. J. Biol. Chem. 278:45240-45247; Pfister, Y., I. Gautschi, A.-N. Takeda, M. van Bemmelen, S. Kellenberger, and L. Schild. 2006. J. Biol. Chem. 281:11787-11791). Here we show evidence of a specific conformation change associated with desensitization. When mutated from glutamate to cysteine, residue 79, which is some 20 amino acids extracellular to TM1, can be altered by cysteine-modifying reagents when the channel is closed, but not when it is desensitized; thus, desensitization appears to conceal the residue from the extracellular medium. D78 and E79 are a pair of adjacent acidic amino acids that are highly conserved in ASICs yet absent from epithelial Na(+) channels, their acid-insensitive relatives. Despite large effects on desensitization by mutations at positions 78 and 79-including a shift to 10-fold lower proton concentration with the E79A mutant-there are not significant effects on activation. PMID:17389250

  5. Development and characterisation of a front-end ASIC for macro array of photo-detectors of large dimensions

    International Nuclear Information System (INIS)

    The coverage of large areas of photo-detection is a crucial element of experiments studying high energy atmospheric cosmic showers and neutrinos from different sources. The objective of this project is to realize big detectors using thousands of photomultipliers (PMT). The project proposes to segment the large surface of photo-detection into macro pixels consisting of an array of 16 PMT of 12 inches (2*2 m2), connected to an autonomous front-end electronics which works in without-trigger data acquisition mode placed near the array. This is possible thanks to the microelectronics progress that allows to integrate the readout and the signal processing, of all the multipliers, in the same circuit (ASIC) named PARISROC (Photomultiplier Array Integrated ins SiGe Read Out Chip). The ASIC must only send out the digital data by network to the surface central data storage. The PARISROC chip made in AM's Silicon Germanium (SiGe) 0.35 μm technology, integrates 16 independent channels for each PMT of the array, providing charge and time measurements. The first prototype of PARISROC chip has a total surface of 19 mm2. The ASIC measurements have led to the realization of a second prototype. Important measurements were performed in terms of noise, dynamic range, readout frequency (from 10 MHz to 40 MHz), time measurements (TDC improvements) and charge measurements (Slow shaper improvements). This new prototype of PARISROC-2 has been tested and the characterisation has shown a good overall behavior and the verification of the improvements. (author)

  6. KLauS: a low power Silicon Photomultiplier charge readout ASIC in 0.18 UMC CMOS

    Science.gov (United States)

    Briggl, K.; Chen, H.; Schimansky, D.; Shen, W.; Stankova, V.; Schultz-Coulon, H. C.

    2016-03-01

    We present the development of a low power Silicon Photomultiplier charge readout ASIC for an imaging calorimeter at a future linear collider. The analog front-end is designed to achieve sufficient signal-to-noise ratio for single pixel signals using low gain SiPMs, while allowing charge measurements over the full dynamic range of the sensors. The front-end consists of an input stage, two charge measurement branches and a fast comparator. A SAR ADC with a resolution of 10 bit digitizes the pulse height information. An additional pipelined SAR stage allows to increase the quantization resolution to 12 bit for calibration measurements.

  7. Test results of the ASIC front-end trigger prototypes for the muon barrel detector of CMS at LHC

    CERN Document Server

    De Giorgi, M; Dosselli, U; Gasparini, F; Gasparini, U; Gonella, F; Guaita, P; Lippi, I; Meneguzzo, Anna Teresa; Passaseo, M; Pegoraro, M; Ronchese, P; Ponte-Sancho, A J; Martinelli, R; Torassa, E; Ventura, L; Zotto, P L; Zumerle, G

    1999-01-01

    A sample of ASIC prototypes of the first-level trigger front-end device for the muon barrel drift chambers of CMS was tested on a full size chamber prototype. Tests were performed at several incident angles on cosmic rays and at normal incidence using a muon beam. The chamber was irradiated using a /sup 137/Cs gamma source to simulate the LHC radiation environment. The performance of the tested prototypes with respect to efficiency, resolution and noise issues is reported. (9 refs).

  8. ASTEROID: A 64 channel ASIC for source follower readout of DEPFET arrays for X-ray astronomy

    International Nuclear Information System (INIS)

    The 64 channel ASTEROID ASIC has been developed to readout DEPFET Macro-Pixel Arrays operated in source follower mode. In particular ASTEROID will be coupled with the DEPFET Macro-Pixel sensors designed for the X-ray astronomy application BepiColombo. This is a satellite-based mission that requires a detector system with high speed readout, high energy resolution and radiation hardness properties. In the source follower operating mode of the DEPFETs, the front-end electronics is AC-coupled. This allows easy coping with non homogeneity of the pixel matrix and an easy compensation of threshold voltage shifts of the DEPFET devices due to radiation damage. In order to achieve the low noise value required at short processing time, ASTEROID implements a trapezoidal weighting function. This is the time-limited optimum filter for white series noise, which is dominant at the foreseen readout speed. The ASIC is realized in the 0.35μm3.3V AMS CMOS technology. The outputs of the 64 analog channels are multiplexed to one serial output with a speed up to 20 MHz. Thanks to the new multiplexer architecture adopted, ASTEROID is the only ASIC that allows window-mode readout of the pixel matrices, i.e. that allows to address selectively arbitrary sub-areas of the pixel array or even to readout different sub-areas at different speeds. In order to fully operate the 64 channels in parallel, the ASIC contains a digital section that generates the timing signals for the analog circuits. This digital section is based on SEU-immune dual port memory cells. ASTEROID has been tested for the first time with a demonstrator 64x64 macro-pixel Matrix of the size of 3.2x3.2cm2. The energy resolution measured on the Mn-kα peak of 55Fe is of 124 eV with a pixel processing time of 4.8μs at -800C. This excellent result, never achieved before with source follower DEPFET at this readout speed, perfectly matches the requirements of BepiColombo Mission.

  9. A 75 ps rms time resolution BiCMOS time to digital converter optimized for high rate imaging detectors

    CERN Document Server

    Hervé, C

    2002-01-01

    This paper presents an integrated time to digital converter (TDC) with a bin size adjustable in the range of 125 to 175 ps and a differential nonlinearity of +-0.3%. The TDC has four channels. Its architecture has been optimized for the readout of imaging detectors in use at Synchrotron Radiation facilities. In particular, a built-in logic flags piled-up events. Multi-hit patterns are also supported for other applications. Time measurements are extracted off chip at the maximum throughput of 40 MHz. The dynamic range is 14 bits. It has been fabricated in 0.8 mu m BiCMOS technology. Time critical inputs are PECL compatible whereas other signals are CMOS compatible. A second application specific integrated circuit (ASIC) has been developed which translates NIM electrical levels to PECL ones. Both circuits are used to assemble board level TDCs complying with industry standards like VME, NIM and PCI.

  10. Conception and test of an integrated circuit (ASIC): application to multiwire chambers and photomultipliers of the GRAAL experience; Conception et test d`un circuit integre (ASIC): application aux chambres multifils et aux photomultiplicateurs de l`experience GRAAL

    Energy Technology Data Exchange (ETDEWEB)

    Bugnet, H.

    1995-11-21

    The nuclear physics project GRAAL (GRenoble Anneau Accelerateur Laser) located at the European Synchrotron Radiation Facility (ESRF) in Grenoble produces a high energy photon beam with a maximum energy of 1.5 GeV. This gamma beam is obtained by Compton backscattering and can be polarized easily. It permits to probe, in an original way, the structure of the nucleon. The associated detector system includes multiwire proportional chambers and scintillator hodoscopes. A kit of six ASICs (Application Specific Integrated Circuit) has been developed and used for the signal processing and data conditioning up to the level of the data acquisition. This integrated electronics can be mounted right on the detectors. Obvious advantages, due to the reduction of the length of the wires and the number of connections, are an improvement of the signal quality and an increase of the reliability. The Wire Processor (WP), ASIC designed and tested during this thesis, treats the signals from the chamber wires and the photomultipliers. In one chip, there are two identical channels permitting the amplification, the amplitude discrimination, the generation of a programmable delay and the writing in a two state memory in case of coincidence with an external strobe signal. The measurement of the multiwire chamber efficiency demonstrates the functioning of the WP, the data conditioning electronics, the data acquisition and the chamber itself. (author). 62 refs., 111 figs., 13 tabs.

  11. Converting accounts receivable into cash.

    Science.gov (United States)

    Folk, M D; Roest, P R

    1995-09-01

    In recent years, increasing numbers of healthcare providers have converted their accounts receivable into cash through a process called securitization. This practice has gained popularity because it provides a means to raise capital necessary to healthcare organizations. Although securitization transactions can be complex, they may provide increased financial flexibility to providers as they prepare for continuing change in the healthcare industry. PMID:10145096

  12. Charge-pump voltage converter

    Science.gov (United States)

    Brainard, John P.; Christenson, Todd R.

    2009-11-03

    A charge-pump voltage converter for converting a low voltage provided by a low-voltage source to a higher voltage. Charge is inductively generated on a transfer rotor electrode during its transit past an inductor stator electrode and subsequently transferred by the rotating rotor to a collector stator electrode for storage or use. Repetition of the charge transfer process leads to a build-up of voltage on a charge-receiving device. Connection of multiple charge-pump voltage converters in series can generate higher voltages, and connection of multiple charge-pump voltage converters in parallel can generate higher currents. Microelectromechanical (MEMS) embodiments of this invention provide a small and compact high-voltage (several hundred V) voltage source starting with a few-V initial voltage source. The microscale size of many embodiments of this invention make it ideally suited for MEMS- and other micro-applications where integration of the voltage or charge source in a small package is highly desirable.

  13. Parametric study of laser photovoltaic energy converters

    Science.gov (United States)

    Walker, G. H.; Heinbockel, J. H.

    1987-01-01

    Photovoltaic converters are of interest for converting laser power to electrical power in a space-based laser power system. This paper describes a model for photovoltaic laser converters and the application of this model to a neodymium laser silicon photovoltaic converter system. A parametric study which defines the sensitivity of the photovoltaic parameters is described. An optimized silicon photovoltaic converter has an efficiency greater than 50 percent for 1000 W/sq cm of neodymium laser radiation.

  14. Multi-time-over-threshold technique for photomultiplier signal processing: Description and characterization of the SCOTT ASIC

    Energy Technology Data Exchange (ETDEWEB)

    Ferry, S. [CEA/Irfu/SPP, Gif-sur-Yvette (France); Guilloux, F., E-mail: fabrice.guilloux@cea.fr [CEA/Irfu/SEDI, Gif-sur-Yvette (France); Anvar, S.; Chateau, F.; Delagnes, E.; Gautard, V.; Louis, F.; Monmarthe, E.; Le Provost, H. [CEA/Irfu/SEDI, Gif-sur-Yvette (France); Russo, S. [Dipartimento di Scienze Fisiche Universita di Napoli, Napoli (Italy); Schuller, J.-P.; Stolarczyk, Th.; Vallage, B. [CEA/Irfu/SPP, Gif-sur-Yvette (France); Zonca, E. [CEA/Irfu/SEDI, Gif-sur-Yvette (France)

    2012-12-11

    KM3NeT aims to build a cubic-kilometer scale neutrino telescope in the Mediterranean Sea based on a 3D array of photomultiplier tubes. A dedicated ASIC, named SCOTT, has been developed for the readout electronics of the PMTs: it uses up to 16 adjustable thresholds to digitize the signals with the multi-time-over-threshold technique. Digital outputs of discriminators feed a circular sampling memory and a 'first in first out' digital memory for derandomization. At the end of the data processing, the ASIC produces a digital waveform sampled at 800 MHz. A specific study was carried out to process PMT data and has showed that five specifically chosen thresholds are suited to reach the required timing precision. A dedicated method based on the duration of the signal over a given threshold allows an equivalent timing precision at any charge. A charge estimator using the information from the thresholds allows a charge determination within less than 20% up to 60 pe.

  15. ASIC-based architecture for the real-time computation of 2D convolution with large kernel size

    Science.gov (United States)

    Shao, Rui; Zhong, Sheng; Yan, Luxin

    2015-12-01

    Bidimensional convolution is a low-level processing algorithm of interest in many areas, but its high computational cost constrains the size of the kernels, especially in real-time embedded systems. This paper presents a hardware architecture for the ASIC-based implementation of 2-D convolution with medium-large kernels. Aiming to improve the efficiency of storage resources on-chip, reducing off-chip bandwidth of these two issues, proposed construction of a data cache reuse. Multi-block SPRAM to cross cached images and the on-chip ping-pong operation takes full advantage of the data convolution calculation reuse, design a new ASIC data scheduling scheme and overall architecture. Experimental results show that the structure can achieve 40× 32 size of template real-time convolution operations, and improve the utilization of on-chip memory bandwidth and on-chip memory resources, the experimental results show that the structure satisfies the conditions to maximize data throughput output , reducing the need for off-chip memory bandwidth.

  16. Conception and test of an integrated circuit (ASIC): application to multiwire chambers and photomultipliers of the GRAAL experience

    International Nuclear Information System (INIS)

    The nuclear physics project GRAAL (GRenoble Anneau Accelerateur Laser) located at the European Synchrotron Radiation Facility (ESRF) in Grenoble produces a high energy photon beam with a maximum energy of 1.5 GeV. This gamma beam is obtained by Compton backscattering and can be polarized easily. It permits to probe, in an original way, the structure of the nucleon. The associated detector system includes multiwire proportional chambers and scintillator hodoscopes. A kit of six ASICs (Application Specific Integrated Circuit) has been developed and used for the signal processing and data conditioning up to the level of the data acquisition. This integrated electronics can be mounted right on the detectors. Obvious advantages, due to the reduction of the length of the wires and the number of connections, are an improvement of the signal quality and an increase of the reliability. The Wire Processor (WP), ASIC designed and tested during this thesis, treats the signals from the chamber wires and the photomultipliers. In one chip, there are two identical channels permitting the amplification, the amplitude discrimination, the generation of a programmable delay and the writing in a two state memory in case of coincidence with an external strobe signal. The measurement of the multiwire chamber efficiency demonstrates the functioning of the WP, the data conditioning electronics, the data acquisition and the chamber itself. (author). 62 refs., 111 figs., 13 tabs

  17. Histone Modifications in a Mouse Model of Early Adversities and Panic Disorder: Role for Asic1 and Neurodevelopmental Genes.

    Science.gov (United States)

    Cittaro, Davide; Lampis, Valentina; Luchetti, Alessandra; Coccurello, Roberto; Guffanti, Alessandro; Felsani, Armando; Moles, Anna; Stupka, Elia; D' Amato, Francesca R; Battaglia, Marco

    2016-01-01

    Hyperventilation following transient, CO2-induced acidosis is ubiquitous in mammals and heritable. In humans, respiratory and emotional hypersensitivity to CO2 marks separation anxiety and panic disorders, and is enhanced by early-life adversities. Mice exposed to the repeated cross-fostering paradigm (RCF) of interference with maternal environment show heightened separation anxiety and hyperventilation to 6% CO2-enriched air. Gene-environment interactions affect CO2 hypersensitivity in both humans and mice. We therefore hypothesised that epigenetic modifications and increased expression of genes involved in pH-detection could explain these relationships. Medullae oblongata of RCF- and normally-reared female outbred mice were assessed by ChIP-seq for H3Ac, H3K4me3, H3K27me3 histone modifications, and by SAGE for differential gene expression. Integration of multiple experiments by network analysis revealed an active component of 148 genes pointing to the mTOR signalling pathway and nociception. Among these genes, Asic1 showed heightened mRNA expression, coherent with RCF-mice's respiratory hypersensitivity to CO2 and altered nociception. Functional enrichment and mRNA transcript analyses yielded a consistent picture of enhancement for several genes affecting chemoception, neurodevelopment, and emotionality. Particularly, results with Asic1 support recent human findings with panic and CO2 responses, and provide new perspectives on how early adversities and genes interplay to affect key components of panic and related disorders. PMID:27121911

  18. Radiated EMI from power converters

    Directory of Open Access Journals (Sweden)

    Arnautovski-Toševa Vesna

    2005-01-01

    Full Text Available With the continuous increase of switching frequency together with the ongoing trend to higher complexity and functionality, power converters as a part of electronic systems have raised more and more electromagnetic energy pollution to the local system environment. In the same time, stringent demands are imposed on the designers of new circuits that electromagnetic interference (EMI has to be suppressed at its source before it is allowed to propagate into other circuits and systems. In this paper, the authors present a full-wave numerical method for calculation and simulation of electromagnetic field radiated by power converter circuitry. The main objective is to analyze the layout geometry in order to obtain competitive PCB layout that will enable suitably attenuated level of the radiated electric field to safe level. By this it would be possible to ensure reliable operation of the sensitive electronic components in the proximity.

  19. Vibration converter with magnetic levitation

    Science.gov (United States)

    Gladilin, A. V.; Pirogov, V. A.; Golyamina, I. P.; Kulaev, U. V.; Kurbatov, P. A.; Kurbatova, E. P.

    2015-05-01

    The paper presents a mathematical model, the results of computational and theoretical research, and the feasibility of creating a vibration converter with full magnetic levitation in the suspension of a high-temperature superconductor (HTSC). The axial and radial stability of the active part of the converter is provided by the interaction of the magnetic field of ring-shaped permanent magnets and a hollow cylinder made of the ceramic HTSC material. The force is created by a system of current-carrying coils whose magnetic field is polarized by permanent magnets and interacts with induced currents in the superconducting cylinder. The case of transition to the superconducting state of HTSC material in the field of the permanent magnets (FC mode) is considered. The data confirm the outlook for the proposed technical solutions.

  20. Photoelectric converters with quantum coherence

    Science.gov (United States)

    Su, Shan-He; Sun, Chang-Pu; Li, Sheng-Wen; Chen, Jin-Can

    2016-05-01

    Photon impingement is capable of liberating electrons in electronic devices and driving the electron flux from the lower chemical potential to higher chemical potential. Previous studies hinted that the thermodynamic efficiency of a nanosized photoelectric converter at maximum power is bounded by the Curzon-Ahlborn efficiency ηCA. In this study, we apply quantum effects to design a photoelectric converter based on a three-level quantum dot (QD) interacting with fermionic baths and photons. We show that, by adopting a pair of suitable degenerate states, quantum coherences induced by the couplings of QDs to sunlight and fermion baths can coexist steadily in nanoelectronic systems. Our analysis indicates that the efficiency at maximum power is no longer limited to ηCA through manipulation of carefully controlled quantum coherences.

  1. Reducing catalytic converter pressure loss

    Energy Technology Data Exchange (ETDEWEB)

    NONE

    1996-06-01

    This article examines why approximately 30--40% of total exhaust-system pressure loss occurs in the catalytic converter and what can be done to reduce pressure loss. High exhaust-system backpressure is of concern in the design of power trains for passenger cars and trucks because it penalizes fuel economy and limits peak power. Pressure losses occur due to fluid shear and turning during turbulent flow in the converter headers and in entry separation and developing laminar-flow boundary layers within the substrate flow passages. Some of the loss mechanisms are coupled. For example, losses in the inlet header are influenced by the presence of the flow resistance of a downstream substrate. Conversely, the flow maldistribution and pressure loss of the substrate(s) depend on the design of the inlet header.

  2. Collector for thermionic energy converter

    International Nuclear Information System (INIS)

    An improved collector is provided for a thermionic energy converter. The collector comprises a p-type layer of a semiconductor material formed on an n-type layer of a semiconductor material. The p-n junction is maintained in a forward biased condition. The electron affinity of the exposed surface of the p-type layer is effectively lowered to a low level near zero by the presence of a work function lowering activator. The dissipation of energy during collection is reduced by the passage of electrons through the p-type layer in the metastable conduction band state. A significant portion of the electron current remains at the potential of the fermi level of the n-type layer rather than dropping to the fermi level of the p-type layer. Less energy is therefore dissipated as heat and a higher net power output is delivered from a thermionic energy converter incorporating the collector

  3. Combined catalytic converter and afterburner

    Energy Technology Data Exchange (ETDEWEB)

    Ma, T.T.-H.

    1994-11-30

    This patent describes the combined use of a catalytic converter and afterburner. An afterburner chamber and a catalyst matrix are disposed in series within a casing. A combustible premixed charge is ignited in the afterburner chamber before it enters the catalyst matrix. This invention overcomes the problem encountered in previous designs of some of the premixed charge passing unreacted through the device unless a very long afterburner chamber is used. (UK)

  4. Radiated EMI from power converters

    OpenAIRE

    Arnautovski-Toševa Vesna; Rousset Yanis; Drissi El Khamlichi Khalil; Grčev Leonid

    2005-01-01

    With the continuous increase of switching frequency together with the ongoing trend to higher complexity and functionality, power converters as a part of electronic systems have raised more and more electromagnetic energy pollution to the local system environment. In the same time, stringent demands are imposed on the designers of new circuits that electromagnetic interference (EMI) has to be suppressed at its source before it is allowed to propagate into other circuits and systems. In this p...

  5. Resonant Demagnetization PWM Forward Converter

    OpenAIRE

    BİLGİN, Bülent

    2003-01-01

    In this paper, a new approach to demagnetization process of a PWM forward converter (FC) is proposed. According to this approach, the demagnetization winding and diode of a conventional FC are removed, and an external capacitor is added in parallel with the secondary diode. This replacement changes the linear demagnetization process of a conventional FC into a resonant demagnetization process. The theoretical performance results of the proposed resonant demagnetization forward conve...

  6. EMI Prediction of Switching Converters

    OpenAIRE

    Trinchero, Riccardo; Stievano, Igor Simone; Canavero, Flavio

    2015-01-01

    This paper addresses the simulation of the conducted electromagnetic interference produced by circuits with periodically switching elements. The proposed method allows for the computation of their steady-state responses by means of augmented linear time-invariant equivalents built from circuit inspection only, and standard tools for circuit analysis. The approach is demonstrated on a real dc-dc boost converter by comparing simulation results with real measurements

  7. Development of a Compact Matrix Converter

    Directory of Open Access Journals (Sweden)

    J. Bauer

    2009-01-01

    Full Text Available This paper deals with the development of a matrix converter. Matrix converters belong to the category of direct frequency converters. A converter does not contain DC-link and the output voltage is provided by direct switching of voltage from the input phases. This is enabled by 9 bidirectional switches, which are provided by anti-serial connection of 18 IGBT transistors. The absence of a DC-link is great advantage of the matrix converter, but it also increases the requirements on the converter control. For this reason a new prototype of a matrix converter is being developed with sophisticated modern components (FPGA, Power PC equipped in the control part of the converter. The converter will be used for testing new control algorithms and commutation methods. 

  8. Computerized simulation of converter process

    Energy Technology Data Exchange (ETDEWEB)

    Jalkanen, H.; Suomi, M.L.; Wallgren, M. [Helsinki Univ. of Technology, Otaniemi (Finland). Lab. of Metallurgy

    1996-12-31

    Converter process is essentially an oxidising refining process aiming in addition to (1) the primary refining action, decarburisation of high carbon iron melt, also to (2) maximal elimination of impurity elements, especially silicon, phosphorus and sulphur, (3) melting of substantial amounts of scrap using the extra heat released in oxidation reactions and (4) to exact final steel temperature control, optimal for further treatments. `Quantitative modelling of such a complex non-stationary chemical process as oxygen converting necessitates extensive formulation of chemical and thermal evolution of the process in connection with the technological properties of the reactor and the process control measures. A comprehensive converter simulation program like CONSIM-3. 1 and its preceding versions that is based on the theoretical and practical knowledge on the process can be used for (1) educating specialists and smelter personnel, (2) planning of the blowing programs, (3) developing and testing of process control systems and after some elaboration and restructuring (4) it can be integrated to static or dynamic process control systems. (orig.) SULA 2 Research Programme; 10 refs.

  9. The VFAT3-Comm-Port: a complete communication port for front-end ASICs intended for use within the high luminosity radiation environments of the LHC

    International Nuclear Information System (INIS)

    This paper presents the VFAT3 Comm-Port (V3CP), which offers a single port for all communication to and from a front-end ASIC within the HL-LHC environment. This includes synchronization to the LHC clock, slow control communication, the execution of fast control commands and the readout of data

  10. Development of a compact radiation-hardened low-noise front-end readout ASIC for CZT-based hard X-ray imager

    International Nuclear Information System (INIS)

    In this paper, we present the development and performances of a radiation-hardened front-end readout application-specific integrated circuit (ASIC) dedicated to CZT detectors for a hard X-ray imager in space applications. The readout channel consists of a charge sensitive amplifier (CSA), a CR-RC shaper, a fast shaper, a discriminator and a driving buffer. With the additional digital filtering, the readout channel can achieve very low noise performances and low power dissipation. An eight-channel prototype ASIC is designed and fabricated in 0.35 μm CMOS process. The energy range of the detected X-rays is evaluated as 1.45 keV to 281 keV. The gain is larger than 100 mV/fC. The equivalent noise charge (ENC) of the ASIC is 53 e− at zero farad plus 10 e− per picofarad. The power dissipation is less than 4.4 mW/channel. Through the measurement with a CZT detector, the energy resolution is less than 3.45 keV (FWHM) under the irradiation of the radioactive source 241Am. The radiation effect experiments indicate that the proposed ASIC can resist the total ionization dose (TID) irradiation of higher than 200 krad (Si)

  11. Development of a compact radiation-hardened low-noise front-end readout ASIC for CZT-based hard X-ray imager

    Energy Technology Data Exchange (ETDEWEB)

    Gao, W., E-mail: gaowu@nwpu.edu.cn; Gan, B.; Li, X.; Wei, T.; Gao, D.; Hu, Y.

    2015-04-21

    In this paper, we present the development and performances of a radiation-hardened front-end readout application-specific integrated circuit (ASIC) dedicated to CZT detectors for a hard X-ray imager in space applications. The readout channel consists of a charge sensitive amplifier (CSA), a CR-RC shaper, a fast shaper, a discriminator and a driving buffer. With the additional digital filtering, the readout channel can achieve very low noise performances and low power dissipation. An eight-channel prototype ASIC is designed and fabricated in 0.35 μm CMOS process. The energy range of the detected X-rays is evaluated as 1.45 keV to 281 keV. The gain is larger than 100 mV/fC. The equivalent noise charge (ENC) of the ASIC is 53 e{sup −} at zero farad plus 10 e{sup −} per picofarad. The power dissipation is less than 4.4 mW/channel. Through the measurement with a CZT detector, the energy resolution is less than 3.45 keV (FWHM) under the irradiation of the radioactive source {sup 241}Am. The radiation effect experiments indicate that the proposed ASIC can resist the total ionization dose (TID) irradiation of higher than 200 krad (Si)

  12. Simulation Results of Double Forward Converter

    Directory of Open Access Journals (Sweden)

    P. Vijaya KUMAR

    2009-12-01

    Full Text Available This work aims to find a better forward converter for DC to DC conversion.Simulation of double forward converter in SMPS system is discussed in this paper. Aforward converter with RCD snubber to synchronous rectifier and/or to current doubleris also discussed. The evolution of the forward converter is first reviewed in a tutorialfashion. Performance parameters are discussed including operating principle, voltageconversion ratio, efficiency, device stress, small-signal dynamics, noise and EMI. Itscircuit operation and its performance characteristics of the forward converter with RCDsnubber and double forward converter are described and the simulation results arepresented.

  13. A 10 cm × 10 cm CdTe Spectroscopic Imaging Detector based on the HEXITEC ASIC

    International Nuclear Information System (INIS)

    The 250 μ m pitch 80x80 pixel HEXITEC detector systems have shown that spectroscopic imaging with an energy resolution of <1 keV FWHM per pixel can be readily achieved in the range of 5–200 keV with Al-pixel CdTe biased to −500 V. This level of spectroscopic imaging has a variety of applications but the ability to produce large area detectors remains a barrier to the adoption of this technology. The limited size of ASICs and defect free CdTe wafers dictates that building large area monolithic detectors is not presently a viable option. A 3-side buttable detector module has been developed to cover large areas with arrays of smaller detectors. The detector modules are 20.35 × 20.45 mm with CdTe bump bonded to the HEXITEC ASIC with coverage up to the edge of the module on three sides. The fourth side has a space of 3 mm to allow I/O wire bonds to be made between the ASIC and the edge of a PCB that routes the signals to a connector underneath the active area of the module. The detector modules have been assembled in rows of five modules with a dead space of 170 μ m between each module. Five rows of modules have been assembled in a staggered height array where the wire bonds of one row of modules are covered by the active detector area of a neighboring row. A data acquisition system has been developed to digitise, store and output the 24 Gbit/s data that is generated by the array. The maximum bias magnitude that could be applied to the CdTe detectors from the common voltage source was limited by the worst performing detector module. In this array of detectors a bias of −400 V was used and the detector modules had 93 % of pixels with better than 1.2 keV FWHM at 59.5 keV. An example of K-edge enhanced imaging for mammography was demonstrated. Subtracting images from the events directly above and below the K-edge of the Iodine contrast agent was able to extract the Iodine information from the image of a breast phantom and improve the contrast of the images

  14. The TDCpix readout ASIC: A 75 ps resolution timing front-end for the NA62 Gigatracker hybrid pixel detector

    Energy Technology Data Exchange (ETDEWEB)

    Kluge, A., E-mail: alexander.kluge@cern.ch; Aglieri Rinella, G.; Bonacini, S.; Jarron, P.; Kaplon, J.; Morel, M.; Noy, M.; Perktold, L.; Poltorak, K.

    2013-12-21

    The TDCpix is a novel pixel readout ASIC for the NA62 Gigatracker detector. NA62 is a new experiment being installed at the CERN Super Proton Synchrotron. Its Gigatracker detector shall provide on-beam tracking and time stamping of individual particles with a time resolution of 150 ps rms. It will consist of three tracking stations, each with one hybrid pixel sensor. The peak flow of particles crossing the detector modules reaches 1.27 MHz/mm{sup 2} for a total rate of about 0.75 GHz. Ten TDCpix chips will be bump-bonded to every silicon pixel sensor. Each chip shall perform time stamping of 100 M particle hits per second with a detection efficiency above 99% and a timing accuracy better than 200 ps rms for an overall three-station-setup time resolution of better than 150 ps. The TDCpix chip has been designed in a 130 nm CMOS technology. It will feature 45×40 square pixels of 300×300μm{sup 2} and a complex End of Column peripheral region including an array of TDCs based on DLLs, four high speed serializers, a low-jitter PLL, readout and control circuits. This contribution will describe the complete design of the final TDCpix ASIC. It will discuss design choices, the challenges faced and some of the lessons learned. Furthermore, experimental results from the testing of circuit prototypes will be presented. These demonstrate the achievement of key performance figures such as a time resolution of the processing chain of 75 ps rms with a laser sent to the center of the pixel and the capability of time stamping charged particles with an overall resolution below 200 ps rms. -- Highlights: • Feasibility demonstration of a silicon pixel detector with sub-ns time tagging capability. • Demonstrator detector assembly with a time resolution of 75 ps RMS with laser charge injection; 170 ps RMS with particle beam. • Design of trigger-less TDCpix ASIC with 1800 pixels, 720 TDC channels and 4 3.2 Gbit/s serializers.

  15. The TDCpix readout ASIC: A 75 ps resolution timing front-end for the NA62 Gigatracker hybrid pixel detector

    International Nuclear Information System (INIS)

    The TDCpix is a novel pixel readout ASIC for the NA62 Gigatracker detector. NA62 is a new experiment being installed at the CERN Super Proton Synchrotron. Its Gigatracker detector shall provide on-beam tracking and time stamping of individual particles with a time resolution of 150 ps rms. It will consist of three tracking stations, each with one hybrid pixel sensor. The peak flow of particles crossing the detector modules reaches 1.27 MHz/mm2 for a total rate of about 0.75 GHz. Ten TDCpix chips will be bump-bonded to every silicon pixel sensor. Each chip shall perform time stamping of 100 M particle hits per second with a detection efficiency above 99% and a timing accuracy better than 200 ps rms for an overall three-station-setup time resolution of better than 150 ps. The TDCpix chip has been designed in a 130 nm CMOS technology. It will feature 45×40 square pixels of 300×300μm2 and a complex End of Column peripheral region including an array of TDCs based on DLLs, four high speed serializers, a low-jitter PLL, readout and control circuits. This contribution will describe the complete design of the final TDCpix ASIC. It will discuss design choices, the challenges faced and some of the lessons learned. Furthermore, experimental results from the testing of circuit prototypes will be presented. These demonstrate the achievement of key performance figures such as a time resolution of the processing chain of 75 ps rms with a laser sent to the center of the pixel and the capability of time stamping charged particles with an overall resolution below 200 ps rms. -- Highlights: • Feasibility demonstration of a silicon pixel detector with sub-ns time tagging capability. • Demonstrator detector assembly with a time resolution of 75 ps RMS with laser charge injection; 170 ps RMS with particle beam. • Design of trigger-less TDCpix ASIC with 1800 pixels, 720 TDC channels and 4 3.2 Gbit/s serializers

  16. Power electronics converters and regulators

    CERN Document Server

    Dokić, Branko L

    2015-01-01

    This book is the result of the extensive experience the authors gained through their year-long occupation at the Faculty of Electrical Engineering at the University of Banja Luka. Starting at the fundamental basics of electrical engineering, the book guides the reader into this field and covers all the relevant types of converters and regulators. Understanding is enhanced by the given examples, exercises and solutions. Thus this book can be used as a textbook for students, for self-study or as a reference book for professionals.

  17. Power Converters and Power Quality

    CERN Document Server

    Kahle, K

    2015-01-01

    This paper discusses the subject of power quality for power converters. The first part gives an overview of most of the common disturbances and power quality issues in electrical networks for particle accelerators, and explains their consequences for accelerator operation. The propagation of asymmetrical network disturbances into a network is analysed. Quantitative parameters for network disturbances in a typical network are presented, and immunity levels for users’ electrical equipment are proposed. The second part of this paper discusses the technologies and strategies used in particle accelerator networks for power quality improvement . Particular focus is given to networks supplying loads with cycling active and reactive power

  18. Converting pest insects into food

    DEFF Research Database (Denmark)

    Offenberg, Hans Joachim; Wiwatwittaya, Decha

    2010-01-01

    pest insects, problematic pests are converted into food and additional earnings. To assess the profitability of providing additional food for the ants, O. smaragdina food conversion efficiency (ECI) was estimated in the laboratory. This estimate suggests the feeding of weaver ants in ant farms to be......Canopy dwelling weaver ants (Oecophylla spp.) are used to control a variety of pests in a number of tropical tree crops. What is less familiar is the existence of commercial markets where these ants and their brood are sold for (i) human consumption, (ii) pet food or (iii) traditional medicine. In...

  19. Digital to Analog Converter Description

    OpenAIRE

    Tuijl, van, B.A.J.

    2003-01-01

    A circuit for analogue to digital or digital to analogue conversion comprising at least 2n matched current sources (40-1, 40-2, 40-n), where n is the resolution required of the conversion. Preferably more than 2n current sources (40-1, 40-2, 40-n) are used. The order in which the sources (40-1, 40-2, 40-n) are used may be changed in different samples. The current sources (40-1, 40-2, 40-n) may be replaced by one bit switched capacitor converters or by inverters connected to one end of a set o...

  20. Analysis Of Single Phase Matrix Converter

    OpenAIRE

    Divya Ahirrao; Bhagyashri Gaware

    2014-01-01

    This paper presents concept of single phase matrix converter. Single phase matrix converter (SPMC) performs a function such as frequency changer, rectifier, inverter; chopper. This reduces the need for new converter hardware. Pulse width modulation (SPWM) techniques are used to calculate the switch duty ratio to synthesis the output. The simulation of converter is carried out in MATLAB/SIMULINK. Hardware design is obtained using readily available IC‟s and other components. Thi...

  1. Valuing Convertible Bonds Based on LSRQM Method

    OpenAIRE

    Jian Liu; Lizhao Yan; Chaoqun Ma

    2014-01-01

    Convertible bonds are one of the essential financial products for corporate finance, while the pricing theory is the key problem to the theoretical research of convertible bonds. This paper demonstrates how to price convertible bonds with call and put provisions using Least-Squares Randomized Quasi-Monte Carlo (LSRQM) method. We consider the financial market with stochastic interest rates and credit risk and present a detailed description on calculating steps of convertible bonds value. The e...

  2. OAM mode converter in twisted fibers

    DEFF Research Database (Denmark)

    Usuga Castaneda, Mario A.; Beltran-Mejia, Felipe; Cordeiro, Cristiano;

    2014-01-01

    We analyze the case of an OAM mode converter based on a twisted fiber, through finite element simulations where we exploit an equivalence between geometric and material transformations. The obtained converter has potential applications in MDM. © 2014 OSA.......We analyze the case of an OAM mode converter based on a twisted fiber, through finite element simulations where we exploit an equivalence between geometric and material transformations. The obtained converter has potential applications in MDM. © 2014 OSA....

  3. Simulation Results of Double Forward Converter

    OpenAIRE

    P. Vijaya Kumar; S. Rama Reddy

    2009-01-01

    This work aims to find a better forward converter for DC to DC conversion.Simulation of double forward converter in SMPS system is discussed in this paper. Aforward converter with RCD snubber to synchronous rectifier and/or to current doubleris also discussed. The evolution of the forward converter is first reviewed in a tutorialfashion. Performance parameters are discussed including operating principle, voltageconversion ratio, efficiency, device stress, small-signal dynamics, noise and EMI....

  4. Developments of gamma-ray imagers using CdTe semiconductors based on the analog ASIC technology

    International Nuclear Information System (INIS)

    Cadmium Telluride (CdTe) is one of the most promising semiconductor materials for hard X-ray and gamma-ray detection because of the high detection efficiency, and of the good energy resolution. Moreover, CdTe detectors with Schottky junction work as diode detectors, and show superior energy resolution. Based on the CdTe diode devices, we have developed CdTe pixel/strip imagers, and also realized a Si/CdTe Compton camera. These devices will be used for the Hard X-ray Imager (HXI) and the Soft Gamma-ray Detector (SGD) onboard ASTRO-H X-ray satellite to be launched in 2015. These developments are briefly reported in this article. We also describe our recent development of low-noise analog readout ASICs to be used for future development of CdTe gamma-ray imagers. (author)

  5. A wide dynamic range multi-channel preamplifier/shaper ASIC family for universal low power applications

    CERN Document Server

    Baturitsky, M A; Tchekhovski, V A; Zamiatin, N I

    2003-01-01

    A universal ASIC family for intermediate energy physics detectors has been designed using a bipolar/JFET technology. The family consists of two 8-channel charge-sensitive preamplifiers (CSP) ZENIT-A2, ZENIT-A3 and a shaper ZENIT-B. The values of switched gain of both CSPs are 80 and 240 mV/pC for ZENIT-A2 and 500 and 1000 mV/pC for ZENIT-A3 with channel-to-channel non-identity not more than +-5%. The CSPs can operate with input capacitance up to 300 pF for low gain and 150 pF for high gain mode. The input signal dynamic range of the shaper is matched to the outputs of both CSPs. The shaper has fast and slow outputs. The CSPs have a power consumption of 13 mW/channel; the shaper of 44 mW/channel.

  6. Energy resolution of a silicon detector with the RX64 ASIC designed for X-ray imaging

    International Nuclear Information System (INIS)

    Results from a silicon microstrip detector coupled to the RX64 ASIC are presented. The system is capable of single photon counting in digital X-ray imaging, with foreseen applications to dual energy mammography and angiography. The main features of the detecting system are low noise (operation with threshold as low as ∼4 keV is possible), good spatial resolution (a pixel of 100 μmx300 μm when oriented edge-on) and good counting rate capability (up to one million counts per channel with a maximum rate of about 200 kHz per channel). The energy resolution of the system, as obtained with several fluorescence X-ray lines, is described

  7. Tunable astigmatic π/2 mode converter

    International Nuclear Information System (INIS)

    The scheme of a tunable astigmatic π/2 mode converter is described. The converter provides the use of input beams with the twofold variable Rayleigh length, while variations in the optical length of the converter itself do not exceed 1/6. (laser beams)

  8. Ecologically Optimal Solution of Power Semiconductors Converters

    Directory of Open Access Journals (Sweden)

    Ivan Lokseninec

    2003-01-01

    Full Text Available One of the relevant scientific programs of Department of Power Electrical Systems is research of ecologically optimal topologies main circuits of power converters. This paper presents some methods how to reduce unfavourable influences of power converters on the grid. The achieved results were applieed in praxis, especially in the power converters produced by Electrotechnical Research and Projecting Institute in Nova Dubnica.

  9. Single event effect characterization of the mixed-signal ASIC developed for CCD camera in space use

    Energy Technology Data Exchange (ETDEWEB)

    Nakajima, Hiroshi, E-mail: nakajima@ess.sci.osaka-u.ac.jp [Department of Earth and Space Science, Graduate School of Science, Osaka University, 1-1 Machikaneyama, Toyonaka, Osaka 560-0043 (Japan); Fujikawa, Mari; Mori, Hideki; Kan, Hiroaki; Ueda, Shutaro; Kosugi, Hiroko; Anabuki, Naohisa; Hayashida, Kiyoshi; Tsunemi, Hiroshi [Department of Earth and Space Science, Graduate School of Science, Osaka University, 1-1 Machikaneyama, Toyonaka, Osaka 560-0043 (Japan); Doty, John P. [Noqsi Aerospace Ltd., 2822 South Nova Road, Pine, CO 80470 (United States); Ikeda, Hirokazu [The Institute of Space and Astronautical Science, Japan Aerospace Exploration Agency, 3-1-1 Yoshinodai, Chuo-ku, Sagamihara, Kanagawa 252-5210 (Japan); Kitamura, Hisashi; Uchihori, Yukio [National Institute for Radiological Sciences (NIRS), Anagawa 4-9-1, Inage-ku, Chiba-shi, Chiba 263-8555 (Japan)

    2013-12-11

    We present the single event effect (SEE) tolerance of a mixed-signal application-specific integrated circuit (ASIC) developed for a charge-coupled device camera onboard a future X-ray astronomical mission. We adopted proton and heavy ion beams at HIMAC/NIRS in Japan. The particles with high linear energy transfer (LET) of 57.9MeVcm{sup 2}/mg is used to measure the single event latch-up (SEL) tolerance, which results in a sufficiently low cross-section of σ{sub SEL}<4.2×10{sup −11}cm{sup 2}/(Ion×ASIC). The single event upset (SEU) tolerance is estimated with various kinds of species with wide range of energy. Taking into account that a part of the protons creates recoiled heavy ions that have higher LET than that of the incident protons, we derived the probability of SEU event as a function of LET. Then the SEE event rate in a low-earth orbit is estimated considering a simulation result of LET spectrum. SEL rate is below once per 49 years, which satisfies the required latch-up tolerance. The upper limit of the SEU rate is derived to be 1.3×10{sup −3} events/s. Although the SEU events cannot be distinguished from the signals of X-ray photons from astronomical objects, the derived SEU rate is below 1.3% of expected non-X-ray background rate of the detector and hence these events should not be a major component of the instrumental background.

  10. SENSROC4: An Multichannel Low-Noise Front-End Readout ASIC Dedicated to CZT Detectors for PET Imaging

    International Nuclear Information System (INIS)

    In this paper, we present the design of a novel low-noise front-end readout application-specific integrated circuit (ASIC) for our small animal PET systems which objective is to achieve the following performances, the spatial resolution of 1 mm3, the detection efficiency of 15 % and the time resolution of 1 ns. A cascade amplifier based on the PMOS input transistor is selected to realize the charge-sensitive amplifier (CSA) for the sake of good noise performances. The output of the CSA is split into two branches. One is connected to a slow shaper for energy measurements. The other is connected to a fast shaper for time acquisition. A novel monostable circuit is designed to adjust the time delay of the trigger signals so that the peak value of the shaped voltages can be sampled and stored. Based on the above techniques, an eight-channel front-end readout prototype chip is designed and implemented in 0.35 μm CMOS process. The die size is 2.286 mm x 2.282 mm. The input range of the ASIC is from 2000 e- to 180000 e-, reflecting to the energy of the gamma ray from 11.2 keV to 1 MeV. The gain of the readout channel is 65 V/pC. The best test result of ENC is 86.5 e- at zero farad plus 9.3 e- per pico-farad. The nonlinearity is less than 3 %. The crosstalk is less than 2 %. The power dissipation is about 9 mW/channel (authors)

  11. Hybrid thermionic-photovoltaic converter

    Science.gov (United States)

    Datas, A.

    2016-04-01

    A conceptual device for the direct conversion of heat into electricity is presented. This concept hybridizes thermionic (TI) and thermophotovoltaic (TPV) energy conversion in a single thermionic-photovoltaic (TIPV) solid-state device. This device transforms into electricity both the electron and photon fluxes emitted by an incandescent surface. This letter presents an idealized analysis of this device in order to determine its theoretical potential. According to this analysis, the key advantage of this converter, with respect to either TPV or TI, is the higher power density in an extended temperature range. For low temperatures, TIPV performs like TPV due to the negligible electron flux. On the contrary, for high temperatures, TIPV performs like TI due to the great enhancement of the electron flux, which overshadows the photon flux contribution. At the intermediate temperatures, ˜1650 K in the case of this particular study, I show that the power density potential of TIPV converter is twice as great as that of TPV and TI. The greatest impact concerns applications in which the temperature varies in a relatively wide range, for which averaged power density enhancement above 500% is attainable.

  12. Reactive Power Compensation using a Matrix Converter

    OpenAIRE

    Holtsmark, Nathalie Marie-Anna

    2010-01-01

    This Master's thesis investigates a new application for the matrix converter: Shunt reactive power compensation. The suggested Matrix Converter-based Reactive power Compensation (MCRC) device is composed of a matrix converter, which input is connected to the grid and an electric machine at the output of the converter. The reactive power flowing in or out of the grid can be regulated with the matrix converter by controlling the magnitude and/or phase angle of the current at the input of the co...

  13. Valuing Convertible Bonds Based on LSRQM Method

    Directory of Open Access Journals (Sweden)

    Jian Liu

    2014-01-01

    Full Text Available Convertible bonds are one of the essential financial products for corporate finance, while the pricing theory is the key problem to the theoretical research of convertible bonds. This paper demonstrates how to price convertible bonds with call and put provisions using Least-Squares Randomized Quasi-Monte Carlo (LSRQM method. We consider the financial market with stochastic interest rates and credit risk and present a detailed description on calculating steps of convertible bonds value. The empirical results show that the model fits well the market prices of convertible bonds in China’s market and the LSRQM method is effective.

  14. Analysis Of Single Phase Matrix Converter

    Directory of Open Access Journals (Sweden)

    Divya Ahirrao

    2014-03-01

    Full Text Available This paper presents concept of single phase matrix converter. Single phase matrix converter (SPMC performs a function such as frequency changer, rectifier, inverter; chopper. This reduces the need for new converter hardware. Pulse width modulation (SPWM techniques are used to calculate the switch duty ratio to synthesis the output. The simulation of converter is carried out in MATLAB/SIMULINK. Hardware design is obtained using readily available IC‟s and other components. This paper discusses the new multiple converter for single phase input using matrix topology using just a single control logic.

  15. Efficiency of Capacitively Loaded Converters

    DEFF Research Database (Denmark)

    Andersen, Thomas; Huang, Lina; Andersen, Michael A. E.;

    2012-01-01

    introduced as a definition of efficiency. The calculated and measured efficiency curves for charging DEAP actuator, polypropylene film capacitor and X7R MLCC are provided and compared. The attention has to be paid for the voltage dependent capacitive load, like X7R MLCC, when evaluating the charging......This paper explores the characteristic of capacitance versus voltage for dielectric electro active polymer (DEAP) actuator, 2kV polypropylene film capacitor as well as 3kV X7R multi layer ceramic capacitor (MLCC) at the beginning. An energy efficiency for capacitively loaded converters is...... polypropylene film capacitor can be the equivalent capacitive load. Because of the voltage dependent characteristic, X7R MLCC cannot be used to replace the DEAP actuator. However, this type of capacitor can be used to substitute the capacitive actuator with voltage dependent property at the development phase....

  16. Reaching a few picosecond timing precision with the 16-channel digitizer and timestamper SAMPIC ASIC

    Energy Technology Data Exchange (ETDEWEB)

    Delagnes, E., E-mail: eric.delagnes@cea.fr [CEA/IRFU/SEDI, Saclay (France); Breton, D. [Laboratoire de L’accélérateur Linéaire from CNRS/IN2P3, Centre scientifique d’Orsay, Bâtiment 200, 91898, Orsay, Cedex (France); Grabas, H. [CEA/IRFU/SEDI, Saclay (France); Maalmi, J.; Rusquart, P. [Laboratoire de L’accélérateur Linéaire from CNRS/IN2P3, Centre scientifique d’Orsay, Bâtiment 200, 91898, Orsay, Cedex (France)

    2015-07-01

    SAMPIC is a Time and Waveform to Digital Converter (TWDC) multichannel chip. It integrates 16 channels each including DLL-based TDC providing a raw time associated with an ultra-fast analog memory sampling the signal used for precise timing measurements as well as other parameters of the pulse. Every channel also integrates a discriminator that can trigger it independently or participate to a more complex trigger. After triggering, the analog samples are digitized by on-chip ADCs and are sent serially to the acquisition. The paper describes the architecture of SAMPIC and reports the main performance measured on the first prototype chip with a focus on timing resolution in the range of 15 ps RMS using raw data improved to less than 5 ps RMS after a simple calibration.

  17. A Spacecraft Housekeeping System-on-Chip in a Radiation Hardened Structured ASIC

    Science.gov (United States)

    Suarez, George; DuMonthier, Jeffrey J.; Sheikh, Salman S.; Powell, Wesley A.; King, Robyn L.

    2012-01-01

    Housekeeping systems are essential to health monitoring of spacecraft and instruments. Typically, sensors are distributed across various sub-systems and data is collected using components such as analog-to-digital converters, analog multiplexers and amplifiers. In most cases programmable devices are used to implement the data acquisition control and storage, and the interface to higher level systems. Such discrete implementations require additional size, weight, power and interconnect complexity versus an integrated circuit solution, as well as the qualification of multiple parts. Although commercial devices are readily available, they are not suitable for space applications due the radiation tolerance and qualification requirements. The Housekeeping System-o n-A-Chip (HKSOC) is a low power, radiation hardened integrated solution suitable for spacecraft and instrument control and data collection. A prototype has been designed and includes a wide variety of functions including a 16-channel analog front-end for driving and reading sensors, analog-to-digital and digital-to-analog converters, on-chip temperature sensor, power supply current sense circuits, general purpose comparators and amplifiers, a 32-bit processor, digital I/O, pulse-width modulation (PWM) generators, timers and I2C master and slave serial interfaces. In addition, the device can operate in a bypass mode where the processor is disabled and external logic is used to control the analog and mixed signal functions. The device is suitable for stand-alone or distributed systems where multiple chips can be deployed across different sub-systems as intelligent nodes with computing and processing capabilities.

  18. Development of Formulations for a-SiC and Manganese CMP and Post-CMP Cleaning of Cobalt

    Science.gov (United States)

    Lagudu, Uma Rames Krishna

    We have investigated the chemical mechanical polishing (CMP) of amorphous SiC (a-SiC) and Mn and Post CMP cleaning of cobalt for various device applications. During the manufacture of copper interconnects using the damascene process the polishing of copper is followed by the polishing of the barrier material (Co, Mn, Ru and their alloys) and its post CMP cleaning. This is followed by the a-SiC hard mask CMP. Silicon carbide thin films, though of widespread use in microelectronic engineering, are difficult to process by CMP because of their hardness and chemical inertness. The earlier part of the SiC work discusses the development of slurries based on silica abrasives that resulted in high a-SiC removal rates (RRs). The ionic strength of the silica dispersion was found to play a significant role in enhancing material removal rate, while also providing very good post-polish surface-smoothness. For example, the addition of 50 mM potassium nitrate to a pH 8 aqueous slurry consisting of 10 wt % of silica abrasives and 1.47 M hydrogen peroxide increased the RR from about 150 nm/h to about 2100 nm/h. The role of ionic strength in obtaining such high RRs was investigated using surface zeta-potentials measurements and X-ray photoelectron spectroscopy (XPS). Evidently, hydrogen peroxide promoted the oxidation of Si and C to form weakly adhered species that were subsequently removed by the abrasive action of the silica particles. The effect of potassium nitrate in increasing material removal is attributed to the reduction in the electrostatic repulsion between the abrasive particles and the SiC surface because of screening of surface charges by the added electrolyte. We also show that transition metal compounds when used as additives to silica dispersions enhance a-SiC removal rates (RRs). Silica slurries containing potassium permanganate gave RRs as high as 2000 nm/h at pH 4. Addition of copper sulfate to this slurry further enhanced the RRs to ˜3500 nm/h at pH 6

  19. Three-phase AC-AC power converters based on matrix converter topology matrix-reactance frequency converters concept

    CERN Document Server

    Szczesniak, Pawel

    2013-01-01

    AC voltage frequency changes is one of the most important functions of solid state power converters. The most desirable features in frequency converters are the ability to generate load voltages with arbitrary amplitude and frequency, sinusoidal currents and voltages waveforms; the possibility of providing unity power factor for any load; and, finally, a simple and compact power circuit. Over the past decades, a number of different frequency converter topologies have appeared in the literature, but only the converters with either a voltage or current DC link are commonly used in industrial app

  20. Design and performance of a low noise, 128-channel ASIC preamplifier for readout of active matrix flat-panel imaging arrays

    CERN Document Server

    Maolinbay, M; Yarema, R J; Antonuk, L E; El-Mohri, Y; Yeakey, M

    2002-01-01

    Design architecture and performance measurements of a low noise, 128-channel application-specific-integrated-circuit (ASIC) preamplifier are reported. The ASIC was designed for readout of active matrix flat-panel imager (AMFPI) arrays. Such arrays, which presently can be made as large as 41 cmx41 cm and with pixel-to-pixel pitches down to approx 70 mu m, require large numbers of low noise, high density, custom integrated readout circuits. The design of this new chip is specifically tailored for research and development of active matrix flat-panel arrays for various medical imaging applications. The design architecture includes the following features: (1) Programmable signal gain which allows acquisition of a wide range of signal sizes from various array designs so as to optimize the signal-to-noise ratio; (2) Correlated double sampling (CDS) which significantly reduces certain noise components; (3) Pipelined readout (simultaneously sampling and multiplexing signals) which reduces image acquisition time; (4) P...

  1. KLauS: an ASIC for silicon photomultiplier readout and its application in a setup for production testing of scintillating tiles

    CERN Document Server

    Briggl, K; Hagdorn, R; Harion, T; Schultz-Coulon, H.C; Shen, W

    2014-01-01

    signals from silicon photomultipliers. Developed as an analog front-end for future calorimeters with high granularity as pursued by the AHCAL concept in the CALICE collaboration, the ASIC is designed to measure the charge signal of the sensors in a large dynamic range and with low electronic noise contributions. In order to tune the operation voltage of each sensor individually, an 8-bit DAC to tune the voltage at the input terminal within a range of 2V is implemented. Using an integrated fast comparator with low jitter, the time information can be measured with subnanosecond resolution. The low power consumption of the ASIC can be further decreased using power gating techniques. Future versions of KLauS are under development and will incorporate an ADC with a resolution of up to 12-bits and blocks for digital data transmission. The chip is used in a setup for mass testing and characterization of scintillator tiles for the AHCAL ...

  2. Converting Relational Database Into Xml Document

    Directory of Open Access Journals (Sweden)

    Kanagaraj.S

    2012-03-01

    Full Text Available XML (Extensible Markup Language is emerging and gradually accepted as the standard for data interchange in the Internet world. Interoperation of relational database and XML database involves schema and data translations. Through EER (extended entity relationship model can convert the schema of relational database into XML. The semantics of the relational database, captured in EER diagram, are mapped to XML schema using stepwise procedures and mapped to XML document under the definitions of the XML schema. Converting Relational Database into XML Document is a process of converting the existing databases into XML file format. Existing conversion techniques convert a single database into xml. The proposed approach performs the conversion of databases like Ms-Access, MS-SQL to XML file format. Read the tables information from the corresponding database and generate code for the appropriate databases and convert the tables into XML flat file format. This converted XML file is been presented to the user.

  3. Radiation-Tolerant DC-DC Converters

    Science.gov (United States)

    Skutt, Glenn; Sable, Dan; Leslie, Leonard; Graham, Shawn

    2012-01-01

    A document discusses power converters suitable for space use that meet the DSCC MIL-PRF-38534 Appendix G radiation hardness level P classification. A method for qualifying commercially produced electronic parts for DC-DC converters per the Defense Supply Center Columbus (DSCC) radiation hardened assurance requirements was developed. Development and compliance testing of standard hybrid converters suitable for space use were completed for missions with total dose radiation requirements of up to 30 kRad. This innovation provides the same overall performance as standard hybrid converters, but includes assurance of radiation- tolerant design through components and design compliance testing. This availability of design-certified radiation-tolerant converters can significantly reduce total cost and delivery time for power converters for space applications that fit the appropriate DSCC classification (30 kRad).

  4. Multilevel converters for 10 MW Wind Turbines

    DEFF Research Database (Denmark)

    Ma, Ke; Blaabjerg, Frede

    2011-01-01

    Several promising multi-level converter configurations for 10 MW Wind Turbines both with direct drive and one-stage gear box drive using Permanent Magnet Synchronous Generator (PMSG) are proposed, designed and compared. Reliability is a crucial indicator for large scale wind power converters......, therefore the evaluations are mainly focused on the power device thermal performances, which are closely related to the life time and cost of the converter. Simulation results of different converter candidates regarding the loss and junction temperature are presented and analyzed. It is concluded that the...... three-level and five-level H-bridge converter topologies both have potential to achieve improved thermal performances compared to the three-level Neutral-Point-Clamped converter topology in the wind power application....

  5. Sour ageusia in two individuals implicates ion channels of the ASIC and PKD families in human sour taste perception at the anterior tongue.

    Directory of Open Access Journals (Sweden)

    Taufiqul Huque

    Full Text Available BACKGROUND: The perception of sour taste in humans is incompletely understood at the receptor cell level. We report here on two patients with an acquired sour ageusia. Each patient was unresponsive to sour stimuli, but both showed normal responses to bitter, sweet, and salty stimuli. METHODS AND FINDINGS: Lingual fungiform papillae, containing taste cells, were obtained by biopsy from the two patients, and from three sour-normal individuals, and analyzed by RT-PCR. The following transcripts were undetectable in the patients, even after 50 cycles of amplification, but readily detectable in the sour-normal subjects: acid sensing ion channels (ASICs 1a, 1beta, 2a, 2b, and 3; and polycystic kidney disease (PKD channels PKD1L3 and PKD2L1. Patients and sour-normals expressed the taste-related phospholipase C-beta2, the delta-subunit of epithelial sodium channel (ENaC and the bitter receptor T2R14, as well as beta-actin. Genomic analysis of one patient, using buccal tissue, did not show absence of the genes for ASIC1a and PKD2L1. Immunohistochemistry of fungiform papillae from sour-normal subjects revealed labeling of taste bud cells by antibodies to ASICs 1a and 1beta, PKD2L1, phospholipase C-beta2, and delta-ENaC. An antibody to PKD1L3 labeled tissue outside taste bud cells. CONCLUSIONS: These data suggest a role for ASICs and PKDs in human sour perception. This is the first report of sour ageusia in humans, and the very existence of such individuals ("natural knockouts" suggests a cell lineage for sour that is independent of the other taste modalities.

  6. VEGA: A low-power front-end ASIC for large area multi-linear X-ray silicon drift detectors: Design and experimental characterization

    International Nuclear Information System (INIS)

    We present the design and the first experimental characterization of VEGA, an Application Specific Integrated Circuit (ASIC) designed to read out large area monolithic linear Silicon Drift Detectors (SDD’s). VEGA consists of an analog and a digital/mixed-signal section to accomplish all the functionalities and specifications required for high resolution X-ray spectroscopy in the energy range between 500 eV and 50 keV. The analog section includes a charge sensitive preamplifier, a shaper with 3-bit digitally selectable shaping times from 1.6 µs to 6.6 µs and a peak stretcher/sample-and-hold stage. The digital/mixed-signal section includes an amplitude discriminator with coarse and fine threshold level setting, a peak discriminator and a logic circuit to fulfill pile-up rejection, signal sampling, trigger generation, channel reset and the preamplifier and discriminators disabling functionalities. A Serial Peripherical Interface (SPI) is integrated in VEGA for loading and storing all configuration parameters in an internal register within few microseconds. The VEGA ASIC has been designed and manufactured in 0.35 µm CMOS mixed-signal technology in single and 32 channel versions with dimensions of 200 µm×500 µm per channel. A minimum intrinsic Equivalent Noise Charge (ENC) of 12 electrons r.m.s. at 3.6 µs peaking time and room temperature is measured and the linearity error is between −0.9% and +0.6% in the whole input energy range. The total power consumption is 481 µW and 420 µW per channel for the single and 32 channels version, respectively. A comparison with other ASICs for X-ray SDD’s shows that VEGA has a suitable low noise and offers high functionality as ADC-ready signal processing but at a power consumption that is a factor of four lower than other similar existing ASICs

  7. Silicon waveguide based TE mode converter.

    Science.gov (United States)

    Zhang, Jing; Liow, Tsung-Yang; Yu, Mingbin; Lo, Guo-Qiang; Kwong, Dim-Lee

    2010-11-22

    A silicon waveguide based TE mode converter was designed for the mode conversion between a horizontal waveguide and vertical waveguide in the two-layer structure waveguide based polarization diversity circuit. The TE mode converter's performance was studied. The polarization mode converter with minimum length of 5 μm was demonstrated to provide the TE mode conversion while maintaining the polarization status. The insertion loss at the transition region was less than 2 dB. PMID:21164874

  8. Estimating the temperature of a catalytic converter

    Energy Technology Data Exchange (ETDEWEB)

    Ma, T.T.-H.

    1994-11-02

    A method is described for estimating the temperature in a catalytic converter used in the exhaust system of an internal combustion engine. Pressure sensors monitor the flow resistance across the catalytic converter to provide an indication of the temperature inside. This feedback system allows heating devices to be switched off and thus avoid overheating, while maintaining the catalytic converter's efficiency by assuring that it does not operate below its light off temperature. (UK)

  9. Estimating the temperature of a catalytic converter

    Energy Technology Data Exchange (ETDEWEB)

    Ma, T.T.-H.

    1994-11-02

    A method of estimating the temperature of a catalytic converter used in the exhaust system of an internal combustion engine is described. Heated exhaust gas oxygen (HEGO) sensors are placed upstream and downstream of the catalytic converter. The temperature of the catalytic converter shortly after start-up is measured by monitoring the resistance of the HEGO sensor's heating element. The downstream sensor is used for mixture control and to double check results of the upstream sensor. (UK)

  10. Timing of Convertible Debt Financing and Investment

    OpenAIRE

    Kyoko Yagi; Ryuta Takashima; Hiroshi Takamori; Katsushige Sawaki

    2008-01-01

    In this paper, we examine the optimal investment policy of the firm which is financed by issuing equity, straight debt and convertible debt. We extend the model in Mauer and Sarkar (2005) over financing with convertible debt. We examine two different investment policies that maximize the equity value and the firm value and show the agency cost as the difference between each policy value. Furthermore, we investigate how the issuance of convertible debt affects investment.

  11. Efficient Implementation of Sample Rate Converter

    OpenAIRE

    Charanjit singh; Manjeet Singh patterh; Sanjay Sharma

    2011-01-01

    Within wireless base station system design, manufacturers continue to seek ways to add value and performance while increasing differentiation. Transmit/receive functionality has become an area of focus as designers attempt to address the need to move data from very high frequency sample rates to chip processing rates. Digital Up Converter (DUC) and Digital Down Converter (DDC) are used as sample rate converters. These are the important block in every digital communication system; hence there ...

  12. Regeneration of ZVS converter with Resonant inductor

    Directory of Open Access Journals (Sweden)

    J.Sivavara Prasad

    2011-09-01

    Full Text Available This paper presents an analysis of the regeneration of zero-voltage-switching converter with resonant inductor, quasi-resonant converters, and full-bridge zero-voltage-switched PWM Converter. The design of a clamping circuit considering a saturable resonant inductor is presented and compared with the design of a clamping circuit with a linear resonant inductor. A diode model with reverse recovery is employed to simulate the effects.

  13. Vacuum-insulated catalytic converter

    Energy Technology Data Exchange (ETDEWEB)

    Benson, David K. (Golden, CO)

    2001-01-01

    A catalytic converter has an inner canister that contains catalyst-coated substrates and an outer canister that encloses an annular, variable vacuum insulation chamber surrounding the inner canister. An annular tank containing phase-change material for heat storage and release is positioned in the variable vacuum insulation chamber a distance spaced part from the inner canister. A reversible hydrogen getter in the variable vacuum insulation chamber, preferably on a surface of the heat storage tank, releases hydrogen into the variable vacuum insulation chamber to conduct heat when the phase-change material is hot and absorbs the hydrogen to limit heat transfer to radiation when the phase-change material is cool. A porous zeolite trap in the inner canister absorbs and retains hydrocarbons from the exhaust gases when the catalyst-coated substrates and zeolite trap are cold and releases the hydrocarbons for reaction on the catalyst-coated substrate when the zeolite trap and catalyst-coated substrate get hot.

  14. Commutation Processes in Multiresonant ZVS Bridge Converter

    Directory of Open Access Journals (Sweden)

    Miroslaw Luft

    2008-01-01

    Full Text Available The analysis of the multiresonant ZVS DC/DC bridge converter is presented. The control system of the converter is basedon the method of frequency control at the constant time of transistor turn-off with a phase shift. The operation of the circuit is givenand the operating range of the converter is defined where ZVS switching operation is assured. Control characteristics are given andthe converter’s efficiency is defined. The circuit’s operation is analysed on the basis of results of the converter simulation tests using Simplorer programme.

  15. Design and performance of a low noise, 128-channel ASIC preamplifier for readout of active matrix flat-panel imaging arrays

    International Nuclear Information System (INIS)

    Design architecture and performance measurements of a low noise, 128-channel application-specific-integrated-circuit (ASIC) preamplifier are reported. The ASIC was designed for readout of active matrix flat-panel imager (AMFPI) arrays. Such arrays, which presently can be made as large as 41 cmx41 cm and with pixel-to-pixel pitches down to ∼70 μm, require large numbers of low noise, high density, custom integrated readout circuits. The design of this new chip is specifically tailored for research and development of active matrix flat-panel arrays for various medical imaging applications. The design architecture includes the following features: (1) Programmable signal gain which allows acquisition of a wide range of signal sizes from various array designs so as to optimize the signal-to-noise ratio; (2) Correlated double sampling (CDS) which significantly reduces certain noise components; (3) Pipelined readout (simultaneously sampling and multiplexing signals) which reduces image acquisition time; (4) Programmable bandwidth controls which balance noise and acquisition speed; and (5) Two selectable modes of output multiplexing (64:1, 16:1) for slow or fast readout. In this paper, detailed measurements of various performance parameters are presented. These measurements include noise characteristics, the relationship between bandwidth and noise, signal response linearity, channel-to-channel and pipeline cross-talk, signal gain and gain variation across channels, and the effect of sampling methods on noise. These characterizations indicate that the performance of the ASIC has achieved the original design goals

  16. Dedicated multichannel readout ASIC coupled with single crystal diamond for dosimeter application

    Science.gov (United States)

    Fabbri, A.; Falco, M. D.; De Notaristefani, F.; Galasso, M.; Marinelli, M.; Orsolini Cencelli, V.; Tortora, L.; Verona, C.; Verona Rinati, G.

    2013-02-01

    This paper reports on the tests of a low-noise, multi-channel readout integrated circuit used as a readout electronic front-end for a diamond multi-pixel dosimeter. The system is developed for dose distribution measurement in radiotherapy applications. The first 10-channel prototype chip was designed and fabricated in a 0.18 um CMOS process. Every channel includes a charge integrator with a 10 pF capacitor and a double slope A/D converter. The diamond multi-pixel detector, based on CVD synthetic single crystal diamond Schottky diodes, is made by a 3 × 3 sensor matrix. The overall device has been tested under irradiation with 6 MeV radio therapeutic photon beams at the Policlinico ``Tor Vergata'' (PTV) hospital. Measurements show a 20 fA RMS leakage current from the front-end input stage and a negligible dark current from the diamond detector, a stable temporal response and a good linear behaviour as a function of both dose and dose rate. These characteristics were common to each tested channel.

  17. Catalytic converter with thermoelectric generator

    Energy Technology Data Exchange (ETDEWEB)

    Parise, R.J.

    1998-07-01

    The unique design of an electrically heated catalyst (EHC) and the inclusion of an ECO valve in the exhaust of an internal combustion engine will meet the strict new emission requirements, especially at vehicle cold start, adopted by several states in this country as well as in Europe and Japan. The catalytic converter (CC) has been a most useful tool in pollution abatement for the automobile. But the emission requirements are becoming more stringent and, along with other improvements, the CC must be improved to meet these new standards. Coupled with the ECO valve, the EHC can meet these new emission limits. In an internal combustion engine vehicle (ICEV), approximately 80% of the energy consumed leaves the vehicle as waste heat: out the tail pipe, through the radiator, or convected/radiated off the engine. Included with the waste heat out the tail pipe are the products of combustion which must meet strict emission requirements. The design of a new CC is presented here. This is an automobile CC that has the capability of producing electrical power and reducing the quantity of emissions at vehicle cold start, the Thermoelectric Catalytic Power Generator. The CC utilizes the energy of the exothermic reactions that take place in the catalysis substrate to produce electrical energy with a thermoelectric generator. On vehicle cold start, the thermoelectric generator is used as a heat pump to heat the catalyst substrate to reduce the time to catalyst light-off. Thus an electrically heated catalyst (EHC) will be used to augment the abatement of tail pipe emissions. Included with the EHC in the exhaust stream of the automobile is the ECO valve. This valve restricts the flow of pollutants out the tail pipe of the vehicle for a specified amount of time until the EHC comes up to operating temperature. Then the ECO valve opens and allows the full exhaust, now treated by the EHC, to leave the vehicle.

  18. Power Electronics Converters for Wind Turbine Systems

    DEFF Research Database (Denmark)

    Blaabjerg, Frede; Liserre, Marco; Ma, Ke

    2012-01-01

    . In this paper, power converter technologies are reviewed with focus on existing ones and on those that have potential for higher power but which have not been yet adopted due to the important risk associated with the high-power industry. The power converters are classified into single- and multicell topologies......, but continuously cost and reliability are important issues to be addressed....

  19. Passive Resonant Bidirectional Converter with Galvanic Barrier

    Science.gov (United States)

    Rosenblad, Nathan S. (Inventor)

    2014-01-01

    A passive resonant bidirectional converter system that transports energy across a galvanic barrier includes a converter using at least first and second converter sections, each section including a pair of transfer terminals, a center tapped winding; a chopper circuit interconnected between the center tapped winding and one of the transfer terminals; an inductance feed winding interconnected between the other of the transfer terminals and the center tap and a resonant tank circuit including at least the inductance of the center tap winding and the parasitic capacitance of the chopper circuit for operating the converter section at resonance; the center tapped windings of the first and second converter sections being disposed on a first common winding core and the inductance feed windings of the first and second converter sections being disposed on a second common winding core for automatically synchronizing the resonant oscillation of the first and second converter sections and transferring energy between the converter sections until the voltage across the pairs of transfer terminals achieves the turns ratio of the center tapped windings.

  20. Modeling and Simulation of Matrix Converter

    DEFF Research Database (Denmark)

    Liu, Fu-rong; Klumpner, Christian; Blaabjerg, Frede

    2005-01-01

    This paper discusses the modeling and simulation of matrix converter. Two models of matrix converter are presented: one is based on indirect space vector modulation and the other is based on power balance equation. The basis of these two models is• given and the process on modeling is introduced in...

  1. High Precision Current Measurement for Power Converters

    OpenAIRE

    Bastos, M. Cerqueira

    2016-01-01

    The accurate measurement of power converter currents is essential to controlling and delivering stable and repeatable currents to magnets in particle accelerators. This paper reviews the most commonly used devices for the measurement of power converter currents and discusses test and calibration methods.

  2. Power Converters Secure Electronics in Harsh Environments

    Science.gov (United States)

    2013-01-01

    In order to harden power converters for the rigors of space, NASA awarded multiple SBIR contracts to Blacksburg, Virginia-based VPT Inc. The resulting hybrid DC-DC converters have proven valuable in aerospace applications, and as a result the company has generated millions in revenue from the product line and created four high-tech jobs to handle production.

  3. Switched-mode converters (one quadrant)

    CERN Document Server

    Barrade, P

    2006-01-01

    Switched-mode converters are DC/DC converters that supply DC loads with a regulated output voltage, and protection against overcurrents and short circuits. These converters are generally fed from an AC network via a transformer and a conventional diode rectifier. Switched-mode converters (one quadrant) are non-reversible converters that allow the feeding of a DC load with unipolar voltage and current. The switched-mode converters presented in this contribution are classified into two families. The first is dedicated to the basic topologies of DC/DC converters, generally used for low- to mid-power applications. As such structures enable only hard commutation processes, the main drawback of such topologies is high commutation losses. A typical multichannel evolution is presented that allows an interesting decrease in these losses. Deduced from this direct DC/DC converter, an evolution is also presented that allows the integration of a transformer into the buck and the buck–boost structure. This enables an int...

  4. Convertible Bonds: Default Risk and Uncertain Volatility

    OpenAIRE

    Huang, Haishi

    2009-01-01

    Within a default intensity approach we discuss the optimal exercise of the callable and convertible bonds. Pricing bounds for convertible bonds are derived in an uncertain volatility model, i.e. when the volatility of the stock price process lies between two extreme values.

  5. Present trends in HVDC converter station design

    Energy Technology Data Exchange (ETDEWEB)

    Carlsson, Lennart; Asplund, Gunnar; Bjorklund, Hans; Flisberg, Gunnar [ABB Power Systems AB, Ludvika (Sweden)

    1994-12-31

    HVDC converter station technology has developed rapidly to satisfy increasing requirements during past 10 - 15 years, but there has not been any dramatic changes since thyristor valves were introduced in the mid 70s. This paper describes some recent and expected future developments, that will substantiality change and simplify future converter stations. (author) 4 refs., 7 figs.

  6. Underwater noise from a wave energy converter

    DEFF Research Database (Denmark)

    Tougaard, Jakob

    A recent addition to the anthropogenic sources of underwater noise is offshore wave energy converters. Underwater noise was recorded from the Wavestar wave energy converter located at Hastholm, Denmark (57°7.73´N, 8°37.23´E). The Wavestar is a full-scale test and demonstration converter of the ab...... to affect seals and porpoises cannot be generalised. Nevertheless, the results clearly demonstrate that it is possible to harvest wave energy in a way which does not add substantially to the increasing levels of anthropogenic noise in the ocean.......A recent addition to the anthropogenic sources of underwater noise is offshore wave energy converters. Underwater noise was recorded from the Wavestar wave energy converter located at Hastholm, Denmark (57°7.73´N, 8°37.23´E). The Wavestar is a full-scale test and demonstration converter...... of the absorber type. During recordings the converter was operating close to maximum power output (nominal capacity of 110 kW). During operation the independently operating absorbers float semi-submerged in the water and wave-generated up-and-down motion is converted into hydraulic pressure by means of pistons...

  7. Spatial resolution of plastic scintillation converter

    International Nuclear Information System (INIS)

    The authors obtain point- and line-scattering functions and a modulation-transfer function for scintillation plates on a polystyrene base used as converters of x-ray images by optical transfer by means of an objective. For x-ray energies of 1-8 MeV, the spatial resolution of the converter is 2.5-1.0 mm-1

  8. Utilization of Nonlinear Converters for Audio Amplification

    DEFF Research Database (Denmark)

    Iversen, Niels; Birch, Thomas; Knott, Arnold

    2012-01-01

    introduction of non-linear converters for audio amplication defeats this limitation. A Cuk converter, designed to deliver an AC peak output voltage twice the supply voltage, is presented in this paper. A 3V prototype has been developed to prove the concept. The prototype shows that it is possible to achieve an...

  9. 3 SC for grid connected converters

    Energy Technology Data Exchange (ETDEWEB)

    Balogh, A.; Varga, E.; Varjasi, I. [Budapest Univ. of Technology and Economics, Budapest (Hungary). Dept. of Automation and Applied Informatics

    2008-07-01

    There are several grid connected converters in the modern grid system. They are usually converters for renewable energy sources, industrial 4 quadrant drives and other converters with direct current link. These converters are connected to the grid using a 3 phase bridge. Standards dictate the maximal harmonic emission and the maximal reactive current for the grid connected converters. For a converter working at nominal power, this means close to unity power factor. The harmonic emission could be limited with high switching frequency and/or with large harmonic filters. Additional financial issues are the efficiency, the small size and weight. Hardware solutions for increasing efficiency are being sought, although the energy required, especially the renewable energy, is expensive. Efficiency is one of the most important parameters of a grid connected system. The paper discussed the structure of the converter, standard control strategies, the three state control (3SC) method, and power factor correction with 3SC. Experimental results were also presented. It was concluded that with the new developed discontinuous current control, a high efficiency and reliable grid connected converter could be created, which satisfies the prescriptions and limitations of the standards. The auxiliary RPC control could make both inductive and capacitive reactive power and is able to inject current harmonics into the grid compensating the distortion of the grid voltage. 12 refs., 2 tabs.

  10. Characteristics of a multichannel low-noise front-end ASIC for CZT-based small animal PET imaging

    Energy Technology Data Exchange (ETDEWEB)

    Gao, W., E-mail: gaowu@nwpu.edu.cn [Institute of Microelectronics, School of Computer S and T, Northwestern Polytechnical University, Xi’an (China); Liu, H., E-mail: newhui.cn@gmail.com [Institute of Microelectronics, School of Computer S and T, Northwestern Polytechnical University, Xi’an (China); Gan, B., E-mail: shadow524@163.com [Institute of Microelectronics, School of Computer S and T, Northwestern Polytechnical University, Xi’an (China); Hu, Y., E-mail: Yann.Hu@ires.in2p3.fr [Institut Pluridisciplinaire Hubert Curien, IN2P3/CNRS/UDS, Strasbourg (France)

    2014-05-01

    In this paper, we present the design and characteristics of a novel low-noise front-end readout application-specific integrated circuit dedicated to CdZnTe (CZT) detectors for a small animal PET imaging system. A low-noise readout method based on the charge integration and the delayed peak detection is proposed. An eight-channel front-end readout prototype chip is designed and implemented in a 0.35 μm CMOS process. The die size is 2.3 mm ×2.3 mm. The prototype chip is tested in different methods including electronic test, energy spectrum test and irradiation test. The input range of the ASIC is from 2000e{sup −} to 180,000e{sup −}, reflecting the energy of the gamma ray from 11.2 keV to 1 MeV. The gain of the readout channel is 65 mV/fC at the shaping time of 1 μs. The best test result of the equivalent noise charge (ENC) is 58.9 e{sup −} at zero farad plus 5.4 e{sup −} per picofarad. The nonlinearity and the crosstalk are less than 3% and less than 2%, respectively, at the room temperature. The static power dissipation is about 3 mW/channel.

  11. STiC — a mixed mode silicon photomultiplier readout ASIC for time-of-flight applications

    International Nuclear Information System (INIS)

    STiC is an application specific integrated circuit (ASIC) for the readout of silicon photomultipliers. The chip has been designed to provide a very high timing resolution for time-of-flight applications in medical imaging and particle physics. It is dedicated in particular to the EndoToFPET-US project, which is developing an endoscopic PET detector combined with ultrasound imaging for early pancreas and prostate cancer detection. This PET system aims to provide a spatial resolution of 1 mm and a time-of-flight resolution of 200 ps FWHM. The analog frontend of STiC can use either a differential or single ended connection to the SiPM. The time and energy information of the detector signal is encoded into two time stamps. A special linearized time-over-threshold method is used to obtain a linear relation between the signal charge and the measured signal width, improving the energy resolution. The trigger signals are digitized by an integrated TDC module with a resolution of less than 20 ps. The TDC data is stored in an internal memory and transfered over a 160 MBit/s serial link using 8/10 bit encoding. First coincidence measurements using a 3.1 × 3.1 × 15 mm3 LYSO crystal and a S10362-33-50 Hamamtsu MPPC show a coincidence time resolution of less than 285 ps. We present details on the chip design as well as first characterization measurements

  12. STiC — a mixed mode silicon photomultiplier readout ASIC for time-of-flight applications

    Science.gov (United States)

    Harion, T.; Briggl, K.; Chen, H.; Fischer, P.; Gil, A.; Kiworra, V.; Ritzert, M.; Schultz-Coulon, H.-C.; Shen, W.; Stankova, V.

    2014-02-01

    STiC is an application specific integrated circuit (ASIC) for the readout of silicon photomultipliers. The chip has been designed to provide a very high timing resolution for time-of-flight applications in medical imaging and particle physics. It is dedicated in particular to the EndoToFPET-US project, which is developing an endoscopic PET detector combined with ultrasound imaging for early pancreas and prostate cancer detection. This PET system aims to provide a spatial resolution of 1 mm and a time-of-flight resolution of 200 ps FWHM. The analog frontend of STiC can use either a differential or single ended connection to the SiPM. The time and energy information of the detector signal is encoded into two time stamps. A special linearized time-over-threshold method is used to obtain a linear relation between the signal charge and the measured signal width, improving the energy resolution. The trigger signals are digitized by an integrated TDC module with a resolution of less than 20 ps. The TDC data is stored in an internal memory and transfered over a 160 MBit/s serial link using 8/10 bit encoding. First coincidence measurements using a 3.1 × 3.1 × 15 mm3 LYSO crystal and a S10362-33-50 Hamamtsu MPPC show a coincidence time resolution of less than 285 ps. We present details on the chip design as well as first characterization measurements.

  13. Single Event Effect Hardness for the Front-end ASICs Applied in BGO Calorimeter of DAMPE Satellite

    CERN Document Server

    Gao, Shan-Shan; Feng, Chang-Qing; Xi, Kai; Liu, Shu-Bin; An, Qi

    2015-01-01

    Dark Matter Particle Explorer (DAMPE) is a Chinese scientific satellite designed for cosmic ray study with a primary scientific goal of indirect search of dark matter particles. As a crucial sub-detector, BGO calorimeter measures the energy spectrum of cosmic rays in the energy range from 5 GeV to 10 TeV. In order to implement high-density front-end electronics (FEE) with the ability to measure 1848 signals from 616 photomultiplier tubes on the strictly constrained satellite platform, two kinds of 32-channel front-end ASICs, VA160 and VATA160, are customized. However, a space mission period of more than 3 years makes single event effect (SEE) a probable threat to reliability. In order to evaluate the SEE sensitivity of the chips and verify the effectiveness of mitigation methods, a series of laser-induced and heavy ion-induced SEE tests were performed. Benefiting from the single event latch-up (SEL) protection circuit for power supply, the triple module redundancy (TMR) technology for the configuration regist...

  14. The TDCpix readout ASIC: A 75ps resolution timing front-end for the NA62 Gigatracker hybrid pixel detector

    CERN Document Server

    Kluge, A; Bonacini, S; Jarron, P; Kaplon, J; Morel, M; Noy, M; Perktold, L; Poltorak, K

    2013-01-01

    The TDCpix is a novel pixel readout ASIC for the NA62 Gigatracker detector. NA62 is a new experiment being installed at the CERN Super Proton Synchrotron. Its Gigatracker detector shall provide on-beam tracking and time stamping of individual particles with a time resolution of 150 ps rms. It will consist of three tracking stations, each with one hybrid pixel sensor. The peak fl ow of particles crossing the detector modules reaches 1.27 MHz/mm 2 for a total rate of about 0.75 GHz. Ten TDCpix chips will be bump-bonded to every silicon pixel sensor. Each chip shall perform time stamping of 100 M particle hits per second with a detection ef fi ciency above 99% and a timing accuracy better than 200 ps rms for an overall three-station-setup time resolution of better than 150 ps. The TDCpix chip has been designed in a 130 nm CMOS technology. It will feature 45 40 square pixels of 300 300 μ m 2 and a complex End of Column peripheral region including an array of TDCs based on DLLs, four high speed serializers, a low...

  15. Characteristics of a multichannel low-noise front-end ASIC for CZT-based small animal PET imaging

    Science.gov (United States)

    Gao, W.; Liu, H.; Gan, B.; Hu, Y.

    2014-05-01

    In this paper, we present the design and characteristics of a novel low-noise front-end readout application-specific integrated circuit dedicated to CdZnTe (CZT) detectors for a small animal PET imaging system. A low-noise readout method based on the charge integration and the delayed peak detection is proposed. An eight-channel front-end readout prototype chip is designed and implemented in a 0.35 μm CMOS process. The die size is 2.3 mm ×2.3 mm. The prototype chip is tested in different methods including electronic test, energy spectrum test and irradiation test. The input range of the ASIC is from 2000e- to 180,000e-, reflecting the energy of the gamma ray from 11.2 keV to 1 MeV. The gain of the readout channel is 65 mV/fC at the shaping time of 1 μs. The best test result of the equivalent noise charge (ENC) is 58.9 e- at zero farad plus 5.4 e- per picofarad. The nonlinearity and the crosstalk are less than 3% and less than 2%, respectively, at the room temperature. The static power dissipation is about 3 mW/channel.

  16. Architecture of a general purpose embedded Slow-Control Adapter ASIC for future high-energy physics experiments

    Energy Technology Data Exchange (ETDEWEB)

    Gabrielli, Alessandro [INFN and Physics Department, University of Bologna, Viale Berti Pichat 6/2, 40127 Bologna (Italy)], E-mail: alessandro.gabrielli@bo.infn.it; Loddo, Flavio; Ranieri, Antonio; De Robertis, Giuseppe [INFN and Physics Department, University of Bari, Via E. Orabona 4, 70126 Bari (Italy)

    2008-10-21

    This work is aimed at defining the architecture of a new digital ASIC, namely Slow-Control Adapter (SCA), which will be designed in a commercial 130-nm CMOS technology. This chip will be embedded within a high-speed data acquisition optical link (GBT) to control and monitor the front-end electronics in future high-energy physics experiments. The GBT link provides a transparent transport layer between the SCA and control electronics in the counting room. The proposed SCA supports a variety of common bus protocols to interface with end-user general-purpose electronics. Between the GBT and the SCA a standard 100 Mb/s IEEE-802.3 compatible protocol will be implemented. This standard protocol allows off-line tests of the prototypes using commercial components that support the same standard. The project is justified because embedded applications in modern large HEP experiments require particular care to assure the lowest possible power consumption, still offering the highest reliability demanded by very large particle detectors.

  17. Architecture of a general purpose embedded Slow-Control Adapter ASIC for future high-energy physics experiments

    International Nuclear Information System (INIS)

    This work is aimed at defining the architecture of a new digital ASIC, namely Slow-Control Adapter (SCA), which will be designed in a commercial 130-nm CMOS technology. This chip will be embedded within a high-speed data acquisition optical link (GBT) to control and monitor the front-end electronics in future high-energy physics experiments. The GBT link provides a transparent transport layer between the SCA and control electronics in the counting room. The proposed SCA supports a variety of common bus protocols to interface with end-user general-purpose electronics. Between the GBT and the SCA a standard 100 Mb/s IEEE-802.3 compatible protocol will be implemented. This standard protocol allows off-line tests of the prototypes using commercial components that support the same standard. The project is justified because embedded applications in modern large HEP experiments require particular care to assure the lowest possible power consumption, still offering the highest reliability demanded by very large particle detectors.

  18. Characteristics of a multichannel low-noise front-end ASIC for CZT-based small animal PET imaging

    International Nuclear Information System (INIS)

    In this paper, we present the design and characteristics of a novel low-noise front-end readout application-specific integrated circuit dedicated to CdZnTe (CZT) detectors for a small animal PET imaging system. A low-noise readout method based on the charge integration and the delayed peak detection is proposed. An eight-channel front-end readout prototype chip is designed and implemented in a 0.35 μm CMOS process. The die size is 2.3 mm ×2.3 mm. The prototype chip is tested in different methods including electronic test, energy spectrum test and irradiation test. The input range of the ASIC is from 2000e− to 180,000e−, reflecting the energy of the gamma ray from 11.2 keV to 1 MeV. The gain of the readout channel is 65 mV/fC at the shaping time of 1 μs. The best test result of the equivalent noise charge (ENC) is 58.9 e− at zero farad plus 5.4 e− per picofarad. The nonlinearity and the crosstalk are less than 3% and less than 2%, respectively, at the room temperature. The static power dissipation is about 3 mW/channel

  19. DS Sentry: an acquisition ASIC for smart, micro-power sensing applications

    Science.gov (United States)

    Liobe, John; Fiscella, Mark; Moule, Eric; Balon, Mark; Bocko, Mark; Ignjatovic, Zeljko

    2011-06-01

    Unattended ground monitoring that combines seismic and acoustic information can be a highly valuable tool in intelligence gathering; however there are several prerequisites for this approach to be viable. The first is high sensitivity as well as the ability to discriminate real threats from noise and other spurious signals. By combining ground sensing with acoustic and image monitoring this requirement may be achieved. Moreover, the DS Sentry®provides innate spurious signal rejection by the "active-filtering" technique employed as well as embedding some basic statistical analysis. Another primary requirement is spatial and temporal coverage. The ideal is uninterrupted, long-term monitoring of an area. Therefore, sensors should be densely deployed and consume very little power. Furthermore, sensors must be inexpensive and easily deployed to allow dense placements in critical areas. The ADVIS DS Sentry®, which is a fully-custom integrated circuit that enables smart, micro-power monitoring of dynamic signals, is the foundation of the proposed system. The core premise behind this technology is the use of an ultra-low power front-end for active monitoring of dynamic signals in conjunction with a highresolution, Σ Δ-based analog-to-digital converter, which utilizes a novel noise rejection technique and is only employed when a potential threat has been detected. The DS Sentry® can be integrated with seismic accelerometers and microphones and user-programmed to continuously monitor for signals with specific signatures such as impacts, footsteps, excavation noise, vehicle-induced ground vibrations, or speech, while consuming only microwatts of power. This will enable up to several years of continuous monitoring on a single small battery while concurrently mitigating false threats.

  20. SPECTRAL ANALYSIS OF BUCK AND SEPIC CONVERTERS

    Directory of Open Access Journals (Sweden)

    CHAKIB ALAOUI

    2011-02-01

    Full Text Available Switched mode power converters generate harmonic currents, which will be injected into the utility grid, causing distortion of the utility waveform. They also become a source for the generation of EMI, which may affect the communication systems. This work is about the design and evaluation of the two most frequently used SMPS used in step down mode of operation: the Buck converter and the Sepic converter working in step-down mode of operation. These converters were designed using optimized equations for their components ratings. Simulation results show that although the Buck output voltage is low in harmonics, it has high harmonic contents in currents circulating in its inductor and diode, and hence requires strong filtering. The Sepic converterhas lower harmonic contents than the Buck converter.

  1. Switched Mode Four-Quadrant Converters

    CERN Document Server

    Thurel, Y

    2015-01-01

    This paper was originally presented at CAS-2004, and was slightly modified for CAS-2014. It presents a review of the key parameters that impact the design choices for a true four-quadrant power converter, in the range 1-10 kW, mainly based on switching mode converter topology. This paper will first describe the state-of-the-art for this power converter family, giving the drawbacks and advantages of different possible solutions. It will also present practical results obtained from the CERN-designed converter. It will finally give some important tips regarding critical phases like test one, when conducting a project dealing with this type of power converter.

  2. Qualitative model of a plasma photoelectric converter

    Science.gov (United States)

    Gorbunov, N. A.; Flamant, G.

    2009-01-01

    A converter of focused optical radiation into electric current is considered on the basis of the photovoltaic effect in plasmas. The converter model is based on analysis of asymmetric spatial distributions of charge particle number density and ambipolar potential in the photoplasma produced by external optical radiation focused in a heat pipe filled with a mixture of alkali vapor and a heavy inert gas. Energy balance in the plasma photoelectric converter is analyzed. The conditions in which the external radiation energy is effectively absorbed in the converter are indicated. The plasma parameters for which the energy of absorbed optical radiation is mainly spent on sustaining the ambipolar field in the plasma are determined. It is shown that the plasma photoelectric converter makes it possible to attain a high conversion efficiency for focused solar radiation.

  3. Flow parameters of IC engine catalytic converters

    Energy Technology Data Exchange (ETDEWEB)

    Zmudka, Z.; Postrzednik, S. [Silesian Univ. of Tech., Gliwice (Poland)

    2007-07-01

    Conversion rate of harmful substances is the principal parameter of catalyst work in respect of ecology. However, resistance of exhaust gas flow through the catalytic converter is also essential problem, apart from its chemical efficiency because fitting the catalyst in exhaust system alters flow characteristic of this system significantly. Catalytic converter can be treated as local or linear resistance element of exhaust system. The first model, in which flow resistance generated by a catalyst is treated as local resistance, is more simplified. Resistance number of the converter was calculated using Darcy model. In the second case, exhaust gas flow resistance through catalyst is treated as linear resistance with energy dissipation (linear frictional resistance) distributed linearly along way of exhaust gas flow. Friction number for the tested converter was calculated and analysed. The problem has been illustrated by results of experimental researches of three-way catalytic converter installed in exhaust system of spark ignition engine and its basic analysis. (orig.)

  4. PERFORMANCE ANALYSIS OF 2D CONVERTER BY COMBINING SR & KY CONVERTERS

    Directory of Open Access Journals (Sweden)

    V. Manoj Kumar

    2014-03-01

    Full Text Available Most of the portable equipments use battery as power source. The increasing use of low voltage portable devices and growing requirements of functionalities embedded into such devices. Thus an efficient power management technique is needed for longer battery life for them. Highly variable nature of batteries systems often require supply voltages to be both higher and lower than the battery. This is most efficiently generated by a buck-boost switching converter. But here the converter efficiency is decreased since the power loss occurs in the storage devices. Step by step, process of designing, feedback control and simulation of a novel voltage-buck boost converter, combining KY and synchronous Rectifier buck converter for battery power applications. Unlike the traditional buck–boost converter, this converter has the positive output voltage and system is stable, different from the negative output voltage and low stable of the traditional inverting buck–boost converters. Since such a converter operates in continuous conduction mode. Also it possesses the non-pulsating output current, thereby not only decreasing the current stress on the output capacitor but also reducing the output voltage ripple. Both the KY converter and the synchronous buck converter, combined into a positive buck– boost converter, uses the same power switches. Here it makes the circuit to be compact and the corresponding cost to be down. Voltage conversion ratio is 2D,so it is also called 2D converter.

  5. Boost matrix converters in clean energy systems

    Science.gov (United States)

    Karaman, Ekrem

    This dissertation describes an investigation of novel power electronic converters, based on the ultra-sparse matrix topology and characterized by the minimum number of semiconductor switches. The Z-source, Quasi Z-source, Series Z-source and Switched-inductor Z-source networks were originally proposed for boosting the output voltage of power electronic inverters. These ideas were extended here on three-phase to three-phase and three-phase to single-phase indirect matrix converters. For the three-phase to three-phase matrix converters, the Z-source networks are placed between the three-switch input rectifier stage and the output six-switch inverter stage. A brief shoot-through state produces the voltage boost. An optimal pulse width modulation technique was developed to achieve high boosting capability and minimum switching losses in the converter. For the three-phase to single-phase matrix converters, those networks are placed similarly. For control purposes, a new modulation technique has been developed. As an example application, the proposed converters constitute a viable alternative to the existing solutions in residential wind-energy systems, where a low-voltage variable-speed generator feeds power to the higher-voltage fixed-frequency grid. Comprehensive analytical derivations and simulation results were carried out to investigate the operation of the proposed converters. Performance of the proposed converters was then compared between each other as well as with conventional converters. The operation of the converters was experimentally validated using a laboratory prototype.

  6. Radiation-hard ASICS for sLHC optical data transmission

    International Nuclear Information System (INIS)

    High-speed data transmission in a high radiation environment poses an immense challenge in the detector design. We investigate the feasibility of using optical links for the silicon trackers of the ATLAS experiment for the planned upgrade of the LHC. The planned upgrade with ten times higher collision rate will produce a similar increase in the radiation. One possibility for the optical transmission is to use VCSEL arrays operating at 850 nm to transmit optical signals while using PIN arrays to convert the optical signals into electrical signals. We have designed a prototype chip containing building blocks for future SLHC optical links using a 130 nm CMOS 8RF process. The chip contains four main blocks; a VCSEL driver optimized for operation at 640 Mb/s, a VCSEL driver optimized for 3.2 Gb/s, a PIN receiver with a clock/data recovery circuit for operation at 40, 160, and 320 Mb/s, and two clock multipliers designed to operate at 640 Mb/s. The clock multiplier is designed to produce the high speed clock to serialize the data for transmission. All circuitry was designed following test results and guidelines from CERN on radiation tolerant design for the process. We have irradiated the chips with 24 GeV protons at CERN. For the VDC, the duty cycle of the output signal and the current consumption of the LVDS receiver remained constant during the irradiation. However, we observed significant decreases in the current consumption of the VCSEL driver circuit and the output drive current. This indicated that the think oxide layout used in the VCSEL driver portion of the chip might not be as radiation-hard and the circuit had been redesigned to minimize this sensitivity. For the PIN receiver, we found that the radiation produced no significant degradation, including the single event upset rate. The upset rate decreased with larger PIN current and was higher for a chip coupled to a PIN diode as expected. For the clock multipliers, we observed that the clocks of some chips

  7. Electromagnetic Compatibility of Matrix Converter System

    Directory of Open Access Journals (Sweden)

    S. Fligl

    2006-12-01

    Full Text Available The presented paper deals with matrix converters pulse width modulation strategies design with emphasis on the electromagnetic compatibility. Matrix converters provide an all-silicon solution to the problem of converting AC power from one frequency to another, offering almost all the features required of an ideal static frequency changer. They possess many advantages compared to the conventional voltage or current source inverters. A matrix converter does not require energy storage components as a bulky capacitor or an inductance in the DC-link, and enables the bi-directional power flow between the power supply and load. The most of the contemporary modulation strategies are able to provide practically sinusoidal waveforms of the input and output currents with negligible low order harmonics, and to control the input displacement factor. The perspective of matrix converters regarding EMC in comparison with other types of converters is brightly evident because it is no need to use any equipment for power factor correction and current and voltage harmonics reduction. Such converter with proper control is properly compatible both with the supply mains and with the supplied load. A special digital control system was developed for the realized experimental test bed which makes it possible to achieve greater throughput of the digital control system and its variability.

  8. Acoustics of automotive catalytic converter assemblies

    Science.gov (United States)

    Dickey, Nolan S.; Selamet, Ahmet; Parks, Steve J.; Tallio, Kevin V.; Miazgowicz, Keith D.; Radavich, Paul M.

    2003-10-01

    In an automotive exhaust system, the purpose of the catalytic converter is to reduce pollutant emissions. However, catalytic converters also affect the engine and exhaust system breathing characteristics; they increase backpressure, affect exhaust system acoustic characteristics, and contribute to exhaust manifold tuning. Thus, radiated sound models should include catalytic converters since they can affect both the source characteristics and the exhaust system acoustic behavior. A typical catalytic converter assembly employs a ceramic substrate to carry the catalytically active noble metals. The substrate has numerous parallel tubes and is mounted in a housing with swelling mat or wire mesh around its periphery. Seals at the ends of the substrate can be used to help force flow through the substrate and/or protect the mat material. Typically, catalytic converter studies only consider sound propagation in the small capillary tubes of the substrate. Investigations of the acoustic characteristics of entire catalytic converter assemblies (housing, substrate, seals, and mat) do not appear to be available. This work experimentally investigates the acoustic behavior of catalytic converter assemblies and the contributions of the separate components to sound attenuation. Experimental findings are interpreted with respect to available techniques for modeling sound propagation in ceramic substrates.

  9. Propagation characteristics of converted refracted wave and its application in static correction of converted wave

    Institute of Scientific and Technical Information of China (English)

    2008-01-01

    Three-component seismic exploration through P-wave source and three-component geophone is an effective technique used in complicated reservoir exploration. In three-component seismic exploration data processing,one of the difficulties is static correction of converted wave. This paper analyzes propagation characteristics of non-converted and converted refracted waves,and discovers a favor-able condition for the formation of converted refracted wave,i.e. the velocity of overlaying medium S wave is much lower than that of underlying medium S wave. In addition,the paper proposes the static correction method of converted wave based on PPS converted refracted wave,and processes the real three-component seismic data with better results of static correction of converted wave.

  10. Application of AGPU for Matrix Converters

    Directory of Open Access Journals (Sweden)

    Nithin T Abraham

    2014-07-01

    Full Text Available A simple PI control loop for the matrix converter system is designed in the simulation to maintain a constant output voltage inspite of any disturbance in the source. The single phase matrix converter employs a modified safe-commutation strategy, which results in the elimination of voltage spikes on switches, without the need of a snubber circuit when there is an inductive load being utilized. This is facilitated through the proper switching control algorithm. The sine PWM pulses are generated as switching pulses to the converter to reduce the THD.

  11. Matrix laser IR-visible image converter

    International Nuclear Information System (INIS)

    A new type of a focal matrix IR-visible image converter is proposed. The pixel IR detectors of the matrix are tunable microcavities of VCSEL (vertical-cavity surface emitting laser) semiconductor microstructures. The image conversion is performed due to the displacements of highly reflecting cavity mirrors caused by thermoelastic stresses in their microsuspensions appearing upon absorption of IR radiation. Analysis of the possibilities of the converter shows that its sensitivity is 10-3-10-2 K and the time response is 10-4-10-3 s. These characteristics determine the practical application of the converter. (laser applications and other topics in quantum electronics)

  12. Selective harmonic control for power converters

    DEFF Research Database (Denmark)

    Zhou, Keliang; Yang, Yongheng; Blaabjerg, Frede; Lu, Wenzhou; Danwei, Wang

    This paper proposes an Internal Model Principle (IMP) based Selective Harmonic Controller (SHC) for power converters. The proposed SHC offers an optimal control solution for power converters to mitigate power harmonics. It makes a good trade-off among cost, complexity and performance. It has high...... accuracy and fast transient response, and it is cost-effective, easy for real-time implementation, and compatible for design rules-of-thumb. An application on a three-phase PWM converter has confirmed the effectiveness of the proposed control scheme in terms of harmonic mitigation....

  13. Field Data Logger Prototype for Power Converters

    DEFF Research Database (Denmark)

    Chaudhary, Sanjay; Ghimire, Pramod; Thøgersen, Paul Bach; de Place Rimmen, Peter

    2014-01-01

    Mission profile data is very important for the cost effective and reliable design of power converters. The converter design can be improved on the basis of actual field data. Actual mission profile data can be collected for the power converters using field data loggers over a long period of time...... and subsequent analysis of the data. This paper presents the development of a low cost prototype field data logger prototype using Raspberry PI and industrial sensors. The functionalities of the data logger prototype are described. An online rainflow count algorithm has been implemented as well....

  14. Energy saving dc-dc converter circuit

    International Nuclear Information System (INIS)

    An energy saving dc-dc converter circuit is disclosed having two energy efficient means which operate in tandem, an energy conserving means and a voltage doubling means. These energy efficient means are applied in combination with elements commonly found in dc-dc converter circuits, namely an ac voltage generator, a transformer for stepping up the generated ac voltage, and means for storing the converted dc voltage. The energy conserving means is connected to the dc voltage storage means. It comprises a resettable inhibit circuit which cuts off the provision of dc voltage for conversion for a predetermined interval when the output of the converter exceeds a predetermined level. The voltage doubling means is reponsive to outputs of the inhibit circuit of the energy conserving means and the ac voltage generator. It provides a phase inverted waveform of the generated ac voltage on one of two leads to the ac voltage step-up transformer

  15. Reliability of power electronic converter systems

    CERN Document Server

    Chung, Henry Shu-hung; Blaabjerg, Frede; Pecht, Michael

    2016-01-01

    This book outlines current research into the scientific modeling, experimentation, and remedial measures for advancing the reliability, availability, system robustness, and maintainability of Power Electronic Converter Systems (PECS) at different levels of complexity.

  16. Catalytic converters as a source of platinum

    Directory of Open Access Journals (Sweden)

    A. Fornalczyk

    2011-10-01

    Full Text Available The increase of Platinum Group Metals demand in automotive industry is connected with growing amount of cars equipped with the catalytic converters. The paper presents the review of available technologies during recycling process. The possibility of removing platinum from the used catalytic converters applying pyrometallurgical and hyrdometallurgical methods were also investigated. Metals such as Cu, Pb, Ca, Mg, Cd were used in the pyrometallurgical research (catalytic converter was melted with Cu, Pb and Ca or Mg and Cd vapours were blown through the whole carrier. In hydrometallurgical research catalytic converters was dissolved in aqua regia. Analysis of Pt contents in the carrier before and after the process was performed by means of atomic absorption spectroscopy. Obtained result were discussed.

  17. Switching power converters medium and high power

    CERN Document Server

    Neacsu, Dorin O

    2013-01-01

    An examination of all of the multidisciplinary aspects of medium- and high-power converter systems, including basic power electronics, digital control and hardware, sensors, analog preprocessing of signals, protection devices and fault management, and pulse-width-modulation (PWM) algorithms, Switching Power Converters: Medium and High Power, Second Edition discusses the actual use of industrial technology and its related subassemblies and components, covering facets of implementation otherwise overlooked by theoretical textbooks. The updated Second Edition contains many new figures, as well as

  18. Convertible Bonds: Risks and Optimal Strategies

    OpenAIRE

    Huang, Haishi

    2009-01-01

    Within the structural approach for credit risk models we discuss the optimal exercise of the callable and convertible bonds. The Vasi˘cek–model is applied to incorporate interest rate risk into the firm’s value process which follows a geometric Brownian motion. Finally, we derive pricing bounds for convertible bonds in an uncertain volatility model, i.e. when the volatility of the firm value process lies between two extreme values.

  19. Spatial resolution of plastic scintillation converter

    Energy Technology Data Exchange (ETDEWEB)

    Gladchenko, V.L.; Gorbunov, V.V.

    1986-05-01

    The authors obtain point- and line-scattering functions and a modulation-transfer function for scintillation plates on a polystyrene base used as converters of x-ray images by optical transfer by means of an objective. For x-ray energies of 1-8 MeV, the spatial resolution of the converter is 2.5-1.0 mm/sup -1/.

  20. Optimal control of wave energy converters

    OpenAIRE

    Bacelli, Giorgio

    2014-01-01

    Wave Energy Converters (WECs) are devices designed to absorb energy from ocean waves. The particular type of Wave Energy Converter (WEC) considered in this thesis is an oscillating body; energy conversion is carried out by means of a structure immersed in water which oscillates under forces exerted by waves. This thesis addresses the control of oscillating body WECs and the objective of the control system is to optimise the motion of the devices that maximises the energy absorp...

  1. Mathematical efficiency modeling of static power converters

    OpenAIRE

    Hoff Dupont, Fabrício; Zaragoza Bertomeu, Jordi; Rech, Cassiano; Pinheiro, José Renes

    2015-01-01

    This paper presents a review and a comparative analysis between mathematical models for the efficiency of power converters. Two different types of models are considered, being one for converters subject solely for output power variations, and a second one also considering input voltage variations. Both cases are particularly important for systems fed by renewable sources as photovoltaic panels or wind turbines. Knowledge of the appropriate models is of interest in the dev...

  2. Resonant Wave Energy Converters: Concept development

    International Nuclear Information System (INIS)

    The Resonant Wave Energy Converter (REWEC) is a device for converting sea wave energy to electrical energy. It belongs to the family of Oscillating Water Columns and is composed by an absorbing chamber connected to the open sea via a vertical duct. The paper gives a holistic view on the concept development of the device, starting from its implementation in the context of submerged breakwaters to the recently developed vertical breakwaters.

  3. AC – AC Converters for UPS

    Directory of Open Access Journals (Sweden)

    Rusalin Lucian R. Păun

    2008-05-01

    Full Text Available This paper propose a new control technique forsingle – phase AC – AC converters used for a on-line UPSwith a good dynamic response, a reduced-partscomponents, a good output characteristic, a good powerfactorcorrection(PFC. This converter no needs anisolation transformer. A power factor correction rectifierand an inverter with the proposed control scheme has beendesigned and simulated using Caspoc2007, validating theconcept.

  4. A Multiport Isolated DC-DC Converter

    OpenAIRE

    Tran, Yan-Kim; Dujic, Drazen

    2016-01-01

    This paper presents a multi-port isolated DC-DC converter for DC applications. A three-port structure is presented, characterized with full bidirectional power flow and simple control. Galvanic isolation is achieved by means of a multi-winding medium frequency transformer which is a part of a resonant LLC converter. To provide controllable power exchange with external DC ports, two out of three ports are equipped with additional bidirectional buck/boost stages. They serve to provide active po...

  5. Three-phase Resonant DC-link Converter

    DEFF Research Database (Denmark)

    Munk-Nielsen, Stig

    The purpose of the project is to develop a three-phase resonant converter suitable for standard speed drives. The motivation for working with resonant converters is found in the problem of the standard converter type used today. In standard converter type Pulse Width Modulated-Voltage Source...... frequency three phase parallel resonant converter is realized....

  6. LHC Power Converters: A Precision Game

    CERN Multimedia

    2001-01-01

    The LHC test-bed, String 2, is close to commissioning and one important element to get a first chance to prove what it can do is the power converter system. In String 2 there are 16 converters, in the full LHC there will be almost 1800. This article takes a look at what is so special about the power converters for the LHC. The 13 000 Amps power converters with the watercooled cables going to the String 2 feedboxes. The LHC's superconducting magnets will be the pinnacle of high technology. But to work, they'll need the help of high-precision power converters to supply them with extremely stable DC current. Perfection will be the name of the game, with an accuracy of just 1-2 parts per million (ppm) required. LEP, for the sake of comparison, could live with 10-20 ppm. The LHC's power converters will be very different from those of LEP or the SPS since the new accelerator's magnets are mostly superconducting. That means that they require much higher currents at a lower voltage since superconductors have no re...

  7. Design of fission neutron converter in HFETR

    International Nuclear Information System (INIS)

    In order to increase local fast neutron fluence rate in High Flux Engineering Test Reactor (HFETR), the fission neutron converter adopted the crisscross fuel rod whose fuel pellet was made of high fission density alloy UMo with 7% Mo. 62 fuel rods in the converter were arranged with triangle dot-matrix between outer tube with diameter of 6.3 mm and inner tube with diameter of 24 mm. And the converter has an irradiation hole with diameter of 20 mm in the center. The calculation result with MCNP shows that fast neutron (E>1 MeV) fluence rate of irradiated samples in the converter can achieve up to 3.34 × 1014 cm-2·s-1, which is about 40% higher than that in the HFETR core at the same position without converter. On the other hand, under the condition of design flow velocity and pressure, the analysis results with ANSYS/CFX show that the maximum permission power can reach 2.4 MW and the maximum power density of fuel pellet is S. 007 kW/cm3. Here, the cladding temperature of the fuel rod is 193.6 ℃, and the converter can fulfill the requirement of thermal-hydraulic design criteria of HFETR and flow instability will not occur. (authors)

  8. Performance and Analysis of Modular Multilevel Converter

    Directory of Open Access Journals (Sweden)

    T.Yuvaraja

    2016-07-01

    Full Text Available The Modular Multilevel Converter (MMC represents an emerging topology with a scalable technology making high voltage and power capability possible. The MMC is built up by identical, but individually controllable sub modules. The Modular Multilevel Converter (MMC is a new topology for multilevel converters with potential for medium voltage and high voltage applications. Equivalent Circuit models and dynamic models for the MMC that provide a faithful representation of system behavior are quite complex given the large number of energy states and control variables. They are not particularly useful in studying the terminal behavior of the converter and for the development of an intuitive control approach to regulate power transfer. A control scheme with a new sub module capacitor voltage balancing method is also proposed in this paper. Modular multilevel converters, based on cascading of half bridge converter cells, can combine low switching frequency with low harmonic interference. They can be designed for high operating voltages without direct series connection of semiconductor element

  9. A photon-counting silicon-strip detector for digital mammography with an ultrafast 0.18-μm CMOS ASIC

    Energy Technology Data Exchange (ETDEWEB)

    Chen, Han, E-mail: hanchen@kth.se [Department of Physics, Royal Institute of Technology (KTH), AlbaNova University Center, 106 91 Stockholm (Sweden); Cederström, Björn [Department of Physics, Royal Institute of Technology (KTH), AlbaNova University Center, 106 91 Stockholm (Sweden); Philips Healthcare, Smidesvägen 5, 171 41 Solna (Sweden); Xu, Cheng; Persson, Mats; Karlsson, Staffan; Danielsson, Mats [Department of Physics, Royal Institute of Technology (KTH), AlbaNova University Center, 106 91 Stockholm (Sweden)

    2014-06-01

    We have evaluated a silicon-strip detector with a 0.18-μm CMOS application specific integrated circuits (ASIC) containing 160 channels for use in photon-counting digital mammography. Measurements were performed at the Elettra light source using monochromatic X-ray beams with different energies and intensities. Energy resolution, ΔE/E{sub in}, was measured to vary between 0.10 and 0.23 in the energy range of 15–40 keV. Pulse pileup has shown little effect on energy resolution.

  10. VALENCY ELECTRON CONTROL IN A GLOW DISCHARGE PRODUCED a-SiC : H AND ITS APPLICATION TO a-Si SOLAR CELL

    OpenAIRE

    Tawada, Y.; Kondo, M; Okamoto, H.; Hamakawa, Y.

    1981-01-01

    A clear valency electron controlability has been found in hydrogenated amorphous silicon carbide produced by the plasma deposition of [SiH4 (1-x) + CH4 (x)] gas mixture. A series of experimental investigation on electrical, optical and optoelectronic properties in the amorphous silicon carbide has been made. Emplying a-SiC : H as a wide gap window material in p-i-n a-Si solar cell, more than 7.5% conversion efficiency has been obtained with Jsc=13.45mA/ cm2, Voc=0.909volts and FF=0.617.

  11. A New Hard Switching Bidirectional Converter With High Power Density

    OpenAIRE

    Bahador Fani; Majid Delshad; Daryoosh Nazarpour

    2010-01-01

    In this paper, a new isolated dc-dc bidirectional converter is proposed. This converter consists of two transformers (flyback and forward) and only one switch in primary side and one switch in secondary side of transformers. In this converter energy transfers to the output in both on and off switch states so power density of this converter is high This converter controlled by PWM signal. Also this converter operates over a wide input voltage range. Theoretical analysis is presented and compu...

  12. Ac-dc converter firing error detection

    International Nuclear Information System (INIS)

    Each of the twelve Booster Main Magnet Power Supply modules consist of two three-phase, full-wave rectifier bridges in series to provide a 560 VDC maximum output. The harmonic contents of the twelve-pulse ac-dc converter output are multiples of the 60 Hz ac power input, with a predominant 720 Hz signal greater than 14 dB in magnitude above the closest harmonic components at maximum output. The 720 Hz harmonic is typically greater than 20 dB below the 500 VDC output signal under normal operation. Extracting specific harmonics from the rectifier output signal of a 6, 12, or 24 pulse ac-dc converter allows the detection of SCR firing angle errors or complete misfires. A bandpass filter provides the input signal to a frequency-to-voltage converter. Comparing the output of the frequency-to-voltage converter to a reference voltage level provides an indication of the magnitude of the harmonics in the ac-dc converter output signal

  13. High Efficiency Reversible Fuel Cell Power Converter

    DEFF Research Database (Denmark)

    Pittini, Riccardo

    traditional unidirectional fuel cell, bidirectional fuel cells have increased operating voltage and current ranges. These characteristics increase the stresses on dc-dc and dc-ac converters in the electrical system, which require proper design and advanced optimization. This work is part of the PhD project......The large scale integration of renewable energy sources requires suitable energy storage systems to balance energy production and demand in the electrical grid. Bidirectional fuel cells are an attractive technology for energy storage systems due to the high energy density of fuel. Compared to...... entitled "High Efficiency Reversible Fuel Cell Power Converter" and it presents the design of a high efficiency dc-dc converter developed and optimized for bidirectional fuel cell applications. First, a brief overview of fuel cell and energy storage technologies is presented. Different system topologies as...

  14. Metamaterial polarization converter analysis: limits of performance

    DEFF Research Database (Denmark)

    Markovich, Dmitry L.; Andryieuski, Andrei; Zalkovskij, Maksim;

    2013-01-01

    In this paper, we analyze the theoretical limits of a metamaterial-based converter with orthogonal linear eigenpolarizations that allow linear-to-elliptical polarization transformation with any desired ellipticity and ellipse orientation. We employ the transmission line approach providing a needed...... a single layer with a ground plane can have 100 % polarization conversion efficiency. We tested our conclusions numerically reaching the designated limits of efficiency using a simple metamaterial design. Our general analysis provides useful guidelines for the metamaterial polarization converter...... level of the design generalization. Our analysis reveals that the maximal conversion efficiency for transmission through a single metamaterial layer is 50 %, while the realistic reflection configuration can give the conversion efficiency up to 90 %. We show that a double layer transmission converter and...

  15. Self-oscillating resonant power converter

    DEFF Research Database (Denmark)

    2014-01-01

    The present invention relates to resonant power converters and inverters comprising a self-oscillating feedback loop coupled from a switch output to a control input of a switching network comprising one or more semiconductor switches. The self-oscillating feedback loop sets a switching frequency of...... the power converter and comprises a first intrinsic switch capacitance coupled between a switch output and a control input of the switching network and a first inductor. The first inductor is coupled in-between a first bias voltage source and the control input of the switching network and has a...... substantially fixed inductance. The first bias voltage source is configured to generate an adjustable bias voltage applied to the first inductor. The output voltage of the power converter is controlled in a flexible and rapid manner by controlling the adjustable bias voltage....

  16. Reliability of Power Electronic Converter Systems

    DEFF Research Database (Denmark)

    The main aims of power electronic converter systems (PECS) are to control, convert, and condition electrical power flow from one form to another through the use of solid-state electronics. This book outlines current research into the scientific modeling, experimentation, and remedial measures...... for advancing the reliability, availability, system robustness, and maintainability of PECS at different levels of complexity. Drawing on the experience of an international team of experts, this book explores the reliability of PECS covering topics including an introduction to reliability engineering in power......-link capacitance in power electronic converter systems; wind turbine systems; smart control strategies for improved reliability of power electronics system; lifetime modelling; power module lifetime test and state monitoring; tools for performance and reliability analysis of power electronics systems; fault...

  17. SIG Galileo final converter technical summary report

    International Nuclear Information System (INIS)

    The report is primarily concerned with the work performed for DOE on converter development and fabrication for the NASA Galileo Jupiter mission as a DOE prime contractor with interface primarily with Teledyne Energy Systems. The activities reported on were directed toward design, analysis and testing of modules and converters SN-1 thru SN-7 and attendant Quality Control and Reliability effort. Although assembly and testing of SN-1 was not accomplished due to the stop work order, the design was virtually completed and a significant amount of subcontracting and manufacturing of both module and converter components was underway. These subcontracting and manufacturing activities were selectively closed down depending upon degree of completion and material or hardware potential usage in the Technology Program

  18. The RS685012 Polymorphism of ACCN2, the Human Ortholog of Murine Acid-Sensing Ion Channel (ASIC1) Gene, is Highly Represented in Patients with Panic Disorder.

    Science.gov (United States)

    Gugliandolo, Agnese; Gangemi, Chiara; Caccamo, Daniela; Currò, Monica; Pandolfo, Gianluca; Quattrone, Diego; Crucitti, Manuela; Zoccali, Rocco Antonio; Bruno, Antonio; Muscatello, Maria Rosaria Anna

    2016-03-01

    Panic disorder (PD) is a disabling anxiety disorder that is characterized by unexpected, recurrent panic attacks, associated with fear of dying and worrying about possible future attacks or other behavioral changes as a consequence of the attacks. The acid-sensing ion channels (ASICs) are a family of proton-sensing channels expressed throughout the nervous system. Their activity is linked to a variety of behaviors including fear, anxiety, pain, depression, learning, and memory. The human analog of ASIC1a is the amiloride-sensitive cation channel 2 (ACCN2). Adenosine A2A receptors are suggested to play an important role in different brain circuits and pathways involved in anxiety reactions. In this work we aimed to evaluate the distribution of ACCN2 rs685012 and ADORA2A rs2298383 polymorphisms in PD patients compared with healthy subjects. We found no association between ADORA2A polymorphism and PD. Instead, the C mutated allele for ACCN2 rs685012 polymorphism was significantly more frequent in patients than in controls. On the contrary, the TT homozygous wild-type genotype and also the ACCN2 TT/ADORA2A CT diplotype were significantly more represented in controls. These results are suggestive for a role of ACCN2 rs685012 polymorphism in PD development in Caucasian people. PMID:26589317

  19. Single phase AC-DC power factor corrected converter with high frequency isolation using buck converter

    Directory of Open Access Journals (Sweden)

    R. Ramesh,

    2014-03-01

    Full Text Available Single phase ac-dc converters having high frequency isolation are implemented in buck, boost, buck-boost configuration with improving the power quality in terms of reducing the harmonics of input current. The paperpropose the circuit configuration, control mechanism, and simulation result for the single phase ac-dc converter.

  20. Dual Converter Fed Open-End Transformer Topology with Parallel Converters and Integrated Magnetics

    DEFF Research Database (Denmark)

    Gohil, Ghanshyamsinh Vijaysinh; Bede, Lorand; Teodorescu, Remus;

    2016-01-01

    A converter system for high power applications, connected to a medium-voltage network using a stepup transformer, is presented in this paper. The converterside winding of the transformer is configured as an openend and both the ends of the windings are fed from two different converter groups. Each...

  1. Solar energy converter using surface plasma waves

    Science.gov (United States)

    Anderson, L. M. (Inventor)

    1984-01-01

    Sunlight is dispersed over a diffraction grating formed on the surface of a conducting film on a substrate. The angular dispersion controls the effective grating period so that a matching spectrum of surface plasmons is excited for parallel processing on the conducting film. The resulting surface plasmons carry energy to an array of inelastic tunnel diodes. This solar energy converter does not require different materials for each frequency band, and sunlight is directly converted to electricity in an efficient manner by extracting more energy from the more energetic photons.

  2. SP-100 converter multicouple thermoelectric cell

    International Nuclear Information System (INIS)

    The General Electric Company is under contract to DOE to design, fabricate, and test an SP-100 Ground Engineering System. This paper provides a description of the SP-100 space reactor power system configuration, and a more detailed description of the power conversion subsystem (PCSS) and the key building block of the power converter, the thermoelectric cell. The functions of the various elements of the PCSS and the cells are also presented. These cells convert the thermal energy from the reactor into electrical power at the desired voltage while being conductively coupled to the hot and cold side heat exchangers to maximize the power output and system specific power

  3. Efficient polarization converter for projection displays.

    Science.gov (United States)

    Yip, W C; Huang, H C; Kwok, H S

    1997-09-01

    In the waveguiding limit, a twisted nematic liquid crystal cell behaves as an achromatic polarization rotator. We propose and demonstrate the application of such a polarization rotator to convert unpolarized light into linearly polarized light with almost 100% efficiency. This polarization converter has a 2:1 aspect ratio, which is close to the 16:9 ratio for modern televisions. It can be used therefore in a projection display with polarization-dependent light valves such as a liquid crystal light valve. Both transmittive and reflective light valves can be used. The temperature dependence of the achromatic polarization rotator is also studied. PMID:18259503

  4. Magneto-hydrodynamic converter with liquid metal

    International Nuclear Information System (INIS)

    The magneto-hydrodynamic converter with liquid metal contains a source of heat, a two phase nozzle, a separator, a liquid diffuser, a liquid metal cooler, a magneto-hydrodynamic generator and means for heating and compressing a liquid coming from the cooler, which are hydraulically connected and in sequence, and which form a closed circuit. A diffuser and a condenser which are hydraulically connected together, are connected between the separator and the means for heating and compressing the liquid metal coming from the cooler. The magneto-hydrodynamic converter with liquid metal can be used to genrate electricity in thermal and nuclear powerstations. (orig.)

  5. All linear optical devices are mode converters

    OpenAIRE

    Miller, David A. B.

    2012-01-01

    We show that every linear optical component can be completely described as a device that converts one set of orthogonal input modes, one by one, to a matching set of orthogonal output modes. This result holds for any linear optical structure with any specific variation in space and/or time of its structure. There are therefore preferred orthogonal "mode converter" basis sets of input and output functions for describing any linear optical device, in terms of which the device can be described b...

  6. Combination solar photovoltaic heat engine energy converter

    Science.gov (United States)

    Chubb, Donald L.

    1987-01-01

    A combination solar photovoltaic heat engine converter is proposed. Such a system is suitable for either terrestrial or space power applications. The combination system has a higher efficiency than either the photovoltaic array or the heat engine alone can attain. Advantages in concentrator and radiator area and receiver mass of the photovoltaic heat engine system over a heat-engine-only system are estimated. A mass and area comparison between the proposed space station organic Rankine power system and a combination PV-heat engine system is made. The critical problem for the proposed converter is the necessity for high temperature photovoltaic array operation. Estimates of the required photovoltaic temperature are presented.

  7. Efficient modelling of a modular multilevel converter

    DEFF Research Database (Denmark)

    El-Khatib, Walid Ziad; Holbøll, Joachim; Rasmussen, Tonny Wederberg

    2013-01-01

    Looking at the near future, we see that offshore wind penetration into the electrical grid will continue increasing rapidly. Until very recently, the trend has been to place the offshore wind farms close to shore within the reach for transmission using HVAC cables but for larger distances HVDC...... calculated for the converter. Time-domain simulations on a MMC HVDC test system are performed in the PSCAD/EMTDC software environment based on the new model. The results demonstrate that the modeled MMC-HVDC system with or without converter transformer is able to operate under specific fault conditions....

  8. Performance Evaluation of Wave Energy Converters

    DEFF Research Database (Denmark)

    Pecher, Arthur

    prototypes. Guidelines for the development of wave energy converters recommend the use of different prototypes, having different sizes, which have to perform tank tests or sea trials. Thisimplicates the need of different testing environment, which shifts from being controllable to uncontrollable with the...... development stages, and results thereby in a need for specific testobjectives and procedures for each development stage. This PhD thesis has looked into the different development stages and more specifically in the performance assessment of wave energy converters based on tank testing and sea trials. The...

  9. Performance Evaluation of Wave Energy Converters

    DEFF Research Database (Denmark)

    Pecher, Arthur

    prototypes. Guidelines for the development of wave energy converters recommend the use of different prototypes, having different sizes, which have to perform tank tests or sea trials. This implicates the need of different testing environment, which shifts from being controllable to uncontrollable with the...... development stages, and results thereby in a need for specific test objectives and procedures for each development stage. This PhD thesis has looked into the different development stages and more specifically in the performance assessment of wave energy converters based on tank testing and sea trials. The...

  10. Microgrid Control Techniques at Power Converter Level

    Czech Academy of Sciences Publication Activity Database

    Valouch, Viktor; Šimek, Petr; Škramlík, Jiří; Tlustý, J.

    Ostrava: VŠB - TU Ostrava, 2013, s. 611-616. ISBN 978-80-248-2988-3. [Electric Power Engineering - EPE 2013. Kouty nad Desnou (CZ), 28.05.2013-30.05.2013] Institutional support: RVO:61388998 Keywords : microgrid * power converter * droop control Subject RIV: JA - Electronics ; Optoelectronics, Electrical Engineering

  11. Integrated multilevel converter and battery management

    OpenAIRE

    K. Wilkie; Stone, D.; Bingham, C.; Foster, M.

    2008-01-01

    A cascaded H-bridge multilevel converter is proposed as a BLDC drive incorporating real-time battery management. Intelligent H-bridges are used to monitor battery cells whilst simultaneously increasing their performance by reducing the variation between cells and controlling their discharge profiles.

  12. Generalized modular multilevel converter and modulation

    DEFF Research Database (Denmark)

    Liu, Hui; Loh, Poh Chiang; Blaabjerg, Frede

    2014-01-01

    Modular multilevel converter (MMC) has gained popularity recently with its modulation, capacitor voltage balancing and circulating current issues widely discussed. Contributing to this effort, a study is presented here to show how the MMC topology can be derived from the viewpoint of two series c...

  13. Faults and Diagnosis Systems in Power Converters

    DEFF Research Database (Denmark)

    Lee, Kyo-Beum; Choi, Uimin

    2014-01-01

    efforts have been put into making these systems better in terms of reliability in order to achieve high power source availability, reduce the cost of energy and also increase the reliability of overall systems. Among the components used in power converters, a power device and a capacitor fault occurs most...

  14. Angiotensin converting enzyme inhibitor induced hyperkalaemic paralysis

    OpenAIRE

    Dutta., D; Fischler, M; McClung, A

    2001-01-01

    Secondary hyperkalaemic paralysis is a rare condition often mimicking the Guillain-Barré syndrome. There have been a few case reports of hyperkalaemia caused by renal failure, trauma, and drugs where the presentation has been with muscle weakness. A case of hyperkalaemic paralysis caused by an angiotensin converting enzyme inhibitor is reported.


Keywords: hyperkalaemia; paralysis; ACE inhibitors

  15. Online Scheduling in Distributed Message Converter Systems

    NARCIS (Netherlands)

    Risse, Thomas; Wombacher, Andreas; Surridge, Mike; Taylor, Steve; Aberer, Karl

    2001-01-01

    The optimal distribution of jobs among hosts in distributed environments is an important factor to achieve high performance. The optimal strategy depends on the application. In this paper we present a new online scheduling strategy for distributed EDI converter system. The strategy is based on the B

  16. Data Converter for Multistandard Mobile Phones

    DEFF Research Database (Denmark)

    Yurttas, Aziz; Bruun, Erik; Jensen, Rasmus Glarborg

    2004-01-01

    This paper describes an analog to digital converter (ADC) for mobile communication systems using a direct down conversion architecture. The ADC can be programmed to meet the requirements of different communication standards, including GSM (Global System for Mobile communication) and WCDMA (Wideband...

  17. Development of the Wave Energy Converter

    DEFF Research Database (Denmark)

    Kofoed, Jens Peter; Frigaard, Peter; Sørensen, Hans Christian;

    2000-01-01

    The development of the wave energy converter Wave Dragon (WD) is presented. The WD is based on the overtopping principle. Initially a description of the WD is given. Then the development over time in terms of the various research and development projects working with the concept is described. This...

  18. Input-output rearrangement of isolated converters

    DEFF Research Database (Denmark)

    Madsen, Mickey Pierre; Kovacevic, Milovan; Mønster, Jakob Døllner;

    2015-01-01

    This paper presents a new way of rearranging the input and output of isolated converters. The new arrangement posses several advantages, as increased voltage range, higher power handling capabilities, reduced voltage stress and improved efficiency, for applications where galvanic isolation is not a...

  19. Catalytic Converters Maintain Air Quality in Mines

    Science.gov (United States)

    2014-01-01

    At Langley Research Center, engineers developed a tin-oxide based washcoat to prevent oxygen buildup in carbon dioxide lasers used to detect wind shears. Airflow Catalyst Systems Inc. of Rochester, New York, licensed the technology and then adapted the washcoat for use as a catalytic converter to treat the exhaust from diesel mining equipment.

  20. National Ignition Facility frequency converter development

    International Nuclear Information System (INIS)

    A preliminary error budget for the third harmonic converter for the National Ignition Facility (NIF) laser driver has been developed using a root-sum-square-accumulation of error sources. Such a budget sets an upper bound on the allowable magnitude of the various effects that reduce conversion efficiency. Development efforts on crystal mounting technology and crystal quality studies are discussed

  1. Aquabuoy Wave Energy Converter

    DEFF Research Database (Denmark)

    Vicinanza, Diego; Margheritini, Lucia; Frigaard, Peter

    The work reported here is part of the contract agreement between the Finavera Renewables Ocean Energy Ltd. and the Department of Civil Engineering Hydraulics and Coastal Engineering Laboratory to instrument a model in scale 1:10 to prototype of the AquaBuOY (AB) wave energy converter and to analyse...

  2. Convertible bonds and bank risk-taking

    NARCIS (Netherlands)

    N. Martynova; E. Perotti

    2015-01-01

    We study how contingent capital that converts in equity ahead of default affects bankrisk-shifting. Going concern conversion restores equity value in highly levered states,thus reducing heightened risk incentives. In contrast, conversion at default for traditionalbail-inable debt has no effect on en

  3. Mathematical modeling of the flash converting process

    Energy Technology Data Exchange (ETDEWEB)

    Sohn, H.Y.; Perez-Tello, M.; Riihilahti, K.M. [Utah Univ., Salt Lake City, UT (United States)

    1996-12-31

    An axisymmetric mathematical model for the Kennecott-Outokumpu flash converting process for converting solid copper matte to copper is presented. The model is an adaptation of the comprehensive mathematical model formerly developed at the University of Utah for the flash smelting of copper concentrates. The model incorporates the transport of momentum, heat, mass, and reaction kinetics between gas and particles in a particle-laden turbulent gas jet. The standard k-{epsilon} model is used to describe gas-phase turbulence in an Eulerian framework. The particle-phase is treated from a Lagrangian viewpoint which is coupled to the gas-phase via the source terms in the Eulerian gas-phase governing equations. Matte particles were represented as Cu{sub 2}S yFeS, and assumed to undergo homogeneous oxidation to Cu{sub 2}O, Fe{sub 3}O{sub 4}, and SO{sub 2}. A reaction kinetics mechanism involving both external mass transfer of oxygen gas to the particle surface and diffusion of oxygen through the porous oxide layer is proposed to estimate the particle oxidation rate Predictions of the mathematical model were compared with the experimental data collected in a bench-scale flash converting facility. Good agreement between the model predictions and the measurements was obtained. The model was used to study the effect of different gas-injection configurations on the overall fluid dynamics in a commercial size flash converting shaft. (author)

  4. Synthetic Applications of Nitrile-Converting Enzymes

    Czech Academy of Sciences Publication Activity Database

    Martínková, Ludmila; Mylerová, Veronika

    2003-01-01

    Roč. 7, - (2003), s. 1279-1295. ISSN 1385-2728 R&D Projects: GA AV ČR IAA4020213 Institutional research plan: CEZ:AV0Z5020903 Keywords : nitrile * converting * enzymes Subject RIV: EE - Microbiology, Virology Impact factor: 2.521, year: 2003

  5. 8-Bit superconducting A/D converter

    International Nuclear Information System (INIS)

    The design, fabrication and testing of a superconducting 8-bit converter are presented. Experimental results show essentially monotonic output code at conversion rates of a few megahertz. An algorithm for automatic adjustment and potential problems of higher speed operation are discussed

  6. Near-Shore Floating Wave Energy Converters

    DEFF Research Database (Denmark)

    Ruol, Piero; Zanuttigh, Barbara; Martinelli, Luca;

    2011-01-01

    Aim of this note is to analyse the possible application of a Wave Energy Converter (WEC) as a combined tool to protect the coast and harvest energy. Physical model tests are used to evaluate wave transmission past a near-shore floating WEC of the wave activated body type, named DEXA. Efficiency a...

  7. Hybrid switch for resonant power converters

    Science.gov (United States)

    Lai, Jih-Sheng; Yu, Wensong

    2014-09-09

    A hybrid switch comprising two semiconductor switches connected in parallel but having different voltage drop characteristics as a function of current facilitates attainment of zero voltage switching and reduces conduction losses to complement reduction of switching losses achieved through zero voltage switching in power converters such as high-current inverters.

  8. China to Gradually Make Capital Account Convertible

    Institute of Scientific and Technical Information of China (English)

    2006-01-01

    @@ China is pushing forward its currency Renminbi (RMB)'s capital account convertibility gradually and in a stable manner, said an official with the State Administration of Foreign Exchange (SAFE), ruling out both an adventurous leap and conservative cautiousness, according to a report of Xinhua on April 12.

  9. China to Gradually Make Capital Account Convertible

    Institute of Scientific and Technical Information of China (English)

    2006-01-01

      China is pushing forward its currency Renminbi (RMB)'s capital account convertibility gradually and in a stable manner, said an official with the State Administration of Foreign Exchange (SAFE), ruling out both an adventurous leap and conservative cautiousness, according to a report of Xinhua on April 12.……

  10. Power electronics converters for wind turbine systems

    DEFF Research Database (Denmark)

    Blaabjerg, Frede; Liserre, Marco; Ma, Ke

    2011-01-01

    The steady growth of installed wind power which reached 200 GW capacity in 2010, together with the up-scaling of the single wind turbine power capability - 7 MW’s has been announced by manufacturers - has pushed the research and development of power converters towards full scale power conversion,...

  11. A Fast Time-to-Pulse Height Converter

    International Nuclear Information System (INIS)

    A fast time-to-pulse height converter representing a development of Green and Bell's gated beam converter is described. The converter is compatible with 2 input pulses in the stop channel and exhibits excellent linearity and time resolution properties. High stability and large output pulses are obtained by using a large time constant in the converting network

  12. Bidirectional converter interface for a battery energy storage test bench

    DEFF Research Database (Denmark)

    Trintis, Ionut; Thomas, Stephan; Blank, Tobias;

    2011-01-01

    This paper presents the bidirectional converter interface for a 6 kV battery energy storage test bench. The power electronic interface consists a two stage converter topology having a low voltage dc-ac grid connected converter and a new dual active bridge dc-dc converter with high transformation...... ratio. The dc-dc converter controls the battery charge/discharge current while the grid converter controls the common dc-link voltage and the grid current. The applied control structures and the hardware implementation of both converters are presented, together with their interaction. Experimental...

  13. A New Hard Switching Bidirectional Converter With High Power Density

    Directory of Open Access Journals (Sweden)

    Bahador Fani

    2010-01-01

    Full Text Available In this paper, a new isolated dc-dc bidirectional converter is proposed. This converter consists of two transformers (flyback and forward and only one switch in primary side and one switch in secondary side of transformers. In this converter energy transfers to the output in both on and off switch states so power density of this converter is high This converter controlled by PWM signal. Also this converter operates over a wide input voltage range. Theoretical analysis is presented and computer simulation and experimental results verify the converter analysis.

  14. A low-voltage boost converter using a forward converter with integrated Meissner oscillator

    Science.gov (United States)

    Woias, P.; Islam, M.; Heller, S.; Roth, R.

    2013-12-01

    This paper describes a novel boost converter to be used with energy harvesters that provide only low output voltages. The device is self-supplied from electric power delivered to its input. With peak power conversion efficiencies above 30% at start-up voltages down to 10 mV this circuit sets best values in comparison with the state-of-the-art. This is achieved by the novel combination of a Meissner oscillator, used as stand-alone in most low-voltage step-up converters today, with a forward converter usually applied in high power systems.

  15. A low-voltage boost converter using a forward converter with integrated Meissner oscillator

    International Nuclear Information System (INIS)

    This paper describes a novel boost converter to be used with energy harvesters that provide only low output voltages. The device is self-supplied from electric power delivered to its input. With peak power conversion efficiencies above 30% at start-up voltages down to 10 mV this circuit sets best values in comparison with the state-of-the-art. This is achieved by the novel combination of a Meissner oscillator, used as stand-alone in most low-voltage step-up converters today, with a forward converter usually applied in high power systems

  16. Soft-switching techniques for pulse-width-modulated converters

    OpenAIRE

    Hua, Guichao

    1994-01-01

    The concept of soft-switching pulse-width-modulated (PWM) technique was proposed aimed at combining the advantages of both the conventional PWM technique and the resonant technique. This work presents four new families of soft-switching PWM converters: the zero-voltage-switched (ZVS) PWM converters, the zero-current-switched (ZCS) PWM converters, the zerovoltage- transition (ZVT) PWM converters, and the zero-current-transition (ZCT) PWM converters. The family of ZVS- and ...

  17. Research on Converter Valve Overvoltage Mechanism and Calculation Conditions of ± 800 kV Converter Station

    Institute of Scientific and Technical Information of China (English)

    WANG Dongju; DENG Xu; ZHOU Hao; CHEN Xilei; XU Anwen; SHEN Yang

    2012-01-01

    The thyristor converter valve is the key equipment of commutation in ultra high voltage direct current (UHVDC) transmission systems. Owing to the limited voltage and current overload capacity, any transient overvoltage may cause permanent damage to the thyristor converter valve. In order to specify the converter valves' overvoltage levels of the ±800 kV UHVDC transmission system, the mechanisms of its generation and development are discussed in detail, from which the calculation conditions for the highest stresses of the converter valves are given. Finally, the converter valve's overvoltage of Xiluodu UHV converter station is simulated. The research results show that the overvoltages of the converter valves in the upper 3-pulse group of the high voltage(HV) and low voltage(LV) 12-pulse converter are generated jointly by the DC line voltage and the converter transformer's voltage at its valve side. Calculation conditions for this overvoltage are: DC system in bipolar operation mode, converter station operating as rectifier, maximum DC system operating voltage, minimum DC current, minimum AC system voltage of the converter station. Furthermore, the other converter valves' overvoltage is caused by the phase-to-phase switching surge generated at the converter station's AC side, penetrating into the valve hall. Overall, the maximum overvoltages of Xiluodu converter station in the upper 3-pulse group of the HV and LV 12-pulse converter are 379.1 kV and 384.9 kV, for other converter valves the maximum overvoltage is 375.3 kV.

  18. Analog-digital converters for industrial applications including an introduction to digital-analog converters

    CERN Document Server

    Ohnhäuser, Frank

    2015-01-01

    This book offers students and those new to the topic of analog-to-digital converters (ADCs) a broad introduction, before going into details of the state-of-the-art design techniques for SAR and DS converters, including the latest research topics, which are valuable for IC design engineers as well as users of ADCs in applications. The book then addresses important topics, such as correct connectivity of ADCs in an application, the verification, characterization and testing of ADCs that ensure high-quality end products. Analog-to-digital converters are the central element in any data processing system and regulation loops such as modems or electrical motor drives. They significantly affect the performance and resolution of a system or end product. System development engineers need to be familiar with the performance parameters of the converters and understand the advantages and disadvantages of the various architectures. Integrated circuit development engineers have to overcome the problem of achieving high per...

  19. A Variational Inequality from Pricing Convertible Bond

    Directory of Open Access Journals (Sweden)

    Yan Huiwen

    2011-01-01

    Full Text Available The model of pricing American-style convertible bond is formulated as a zero-sum Dynkin game, which can be transformed into a parabolic variational inequality (PVI. The fundamental variable in this model is the stock price of the firm which issued the bond, and the differential operator in PVI is linear. The optimal call and conversion strategies correspond to the free boundaries of PVI. Some properties of the free boundaries are studied in this paper. We show that the bondholder should convert the bond if and only if the price of the stock is equal to a fixed value, and the firm should call the bond back if and only if the price is equal to a strictly decreasing function of time. Moreover, we prove that the free boundaries are smooth and bounded. Eventually we give some numerical results.

  20. Study on alkali metal thermoelectric converter

    International Nuclear Information System (INIS)

    The alkali metal thermoelectric converter (AMTEC) utilizing the sodium ion conducting β''-alumina solid electrolyte (BASE) is a device to convert heat energy to electric energy directly. It is characterized by high conversion efficiencies (20-40%), high power densities (1 W/cm2), no moving parts, low maintenance requirements, high durability, and efficiency independent of size. Because of these merits, AMTEC is one of the most promising candidate for dispersed small scale power station, remote power station and aerospace power systems. In this paper, the theoretical and experimental studies on the thin film electrodes characteristics, power generating characteristics, cell efficiency, integral electrode with large current lead, porous metal current lead, series connected cells power generation, potassium AMTEC, wick return AMTEC and system analysis for space and grand use are reported. (J.P.N.) 79 refs

  1. Integrated mode converter for mode division multiplexing

    Science.gov (United States)

    Perez-Galacho, Diego; Alonso-Ramos, Carlos Alberto; Marris-Morini, Delphine; Vakarin, Vladyslav; Le Roux, Xavier; Ortega-Moñux, Alejandro; Wangüemert-Perez, Juan Gonzalo; Vivien, Laurent

    2016-05-01

    The ever growing demands of bandwidth in optical communication systems are making traditional Wavelength Division Multiplexing (WDM) based systems to reach its limit. In order to cope with future bandwidth demand is necessary to use new levels of orthogonality, such as the waveguide mode or the polarization state. Mode Division Multiplexing (MDM) has recently attracted attention as a possible solution to increase aggregate bandwidth. In this work we discuss the proposition a of mode converter that can cover the whole C-Band of optical communications. The Mode Converter is based on two Multimode Interference (MMI) couplers and a phase shifter. Insertion loss (IL) below 0.2 dB and Extinction ratio (ER) higher than 20 dB in a broad bandwidth range of 1.5 μm to 1.6 μm have been estimated. The total length of the device is less than 30 μm.

  2. Enhancing the efficiency of silicon Raman converters

    Science.gov (United States)

    Vermeulen, Nathalie; Sipe, John E.; Thienpont, Hugo

    2010-05-01

    We propose a silicon ring Raman converter in which the spatial variation of the Raman gain along the ring for TE polarization is used to quasi-phase-match the CARS process. If in addition the pump, Stokes, and anti-Stokes waves involved in the CARS interaction are resonantly enhanced by the ring structure, the Stokes-to-anti-Stokes conversion efficiency can be increased by at least four orders of magnitude over that of one-dimensional perfectly phase-matched silicon Raman converters, and can reach values larger than unity with relatively low input pump intensities. These improvements in conversion performance could substantially expand the practical applicability of the CARS process for optical wavelength conversion.

  3. Control of Power Converters in AC Microgrids

    DEFF Research Database (Denmark)

    Rocabert, Joan; Luna, Alvaro; Blaabjerg, Frede; Rodriguez, Pedro

    2012-01-01

    electrical system. The high penetration of distributed generators, linked to the grid through highly controllable power processors based on power electronics, together with the incorporation of electrical energy storage systems, communication technologies, and controllable loads, opens new horizons to the...... effective expansion of microgrid applications integrated into electrical power systems. This paper carries out an overview about microgrid structures and control techniques at different hierarchical levels. At the power converter level, a detailed analysis of the main operation modes and control structures...... for power converters belonging to microgrids is carried out, focusing mainly on grid-forming, grid-feeding, and grid-supporting configurations. This analysis is extended as well toward the hierarchical control scheme of microgrids, which, based on the primary, secondary, and tertiary control layer...

  4. Real power measurement using a thermal converter

    International Nuclear Information System (INIS)

    In this paper, a new application of thermal converters is presented which allows energy, power and rms measurement without the need to substitute the measurement signal with a dc signal as performed in ac–dc transfer. Using a mathematical model of standard planar multijunction thermal converters (PMJTCs), the effective power acting inside the heater of the PMJTC is calculated from the output signal of its thermocouples. Due to the underlying physical principles, this method not only allows the calculation of the rms value of sinusoidal signals but also the average power and absolute energy contained in non-sinusoidal, non-periodic and even non-stationary signals, as appearing in the characterization of energy harvesters. (paper)

  5. Data Converter for Multistandard Mobile Phones

    DEFF Research Database (Denmark)

    Yurttas, Aziz; Bruun, Erik; Jensen, Rasmus Glarborg

    2004-01-01

    This paper describes an analog to digital converter (ADC) for mobile communication systems using a direct down conversion architecture. The ADC can be programmed to meet the requirements of different communication standards, including GSM (Global System for Mobile communication) and WCDMA (Wideba...... entire ADC consumes about 5.5 mW and occupies an active area of about 0.36 mm(2). A test circuit has been developed and fabricated and measurements show that both the required programmability and the required performance can be obtained using the proposed configurations.......This paper describes an analog to digital converter (ADC) for mobile communication systems using a direct down conversion architecture. The ADC can be programmed to meet the requirements of different communication standards, including GSM (Global System for Mobile communication) and WCDMA (Wideband...

  6. Strained quantum well photovoltaic energy converter

    Science.gov (United States)

    Freundlich, Alexandre (Inventor); Renaud, Philippe (Inventor); Vilela, Mauro Francisco (Inventor); Bensaoula, Abdelhak (Inventor)

    1998-01-01

    An indium phosphide photovoltaic cell is provided where one or more quantum wells are introduced between the conventional p-conductivity and n-conductivity indium phosphide layer. The approach allows the cell to convert the light over a wider range of wavelengths than a conventional single junction cell and in particular convert efficiently transparency losses of the indium phosphide conventional cell. The approach hence may be used to increase the cell current output. A method of fabrication of photovoltaic devices is provided where ternary InAsP and InGaAs alloys are used as well material in the quantum well region and results in an increase of the cell current output.

  7. Optical analog-to-digital converter

    Science.gov (United States)

    Vawter, G. Allen; Raring, James; Skogen, Erik J.

    2009-07-21

    An optical analog-to-digital converter (ADC) is disclosed which converts an input optical analog signal to an output optical digital signal at a sampling rate defined by a sampling optical signal. Each bit of the digital representation is separately determined using an optical waveguide interferometer and an optical thresholding element. The interferometer uses the optical analog signal and the sampling optical signal to generate a sinusoidally-varying output signal using cross-phase-modulation (XPM) or a photocurrent generated from the optical analog signal. The sinusoidally-varying output signal is then digitized by the thresholding element, which includes a saturable absorber or at least one semiconductor optical amplifier, to form the optical digital signal which can be output either in parallel or serially.

  8. A high efficiency photovoltaic module integrated converter with the asymmetrical half-bridge flyback converter

    Energy Technology Data Exchange (ETDEWEB)

    Kim, Heeje; Kim, Jongrak; Shin, Dongsul [Department of Electrical Engineering, Pusan National University, Jangjeon, Geumjeong, Busan 609-735 (Korea); Kim, Hosung; Lee, Kyungjun [Department of Electrical Engineering, Pusan National University, Jangjeon, Geumjeong, Busan 609-735 (Korea); New and Renewable Energy System Research Center, Korea Electro-technology Research Institute, 28-1, Sungju-dong Changwon-si, Kyungsannam-do, 641-120 (Korea); Kim, Jonghyun; Yoo, Dongwook [New and Renewable Energy System Research Center, Korea Electro-technology Research Institute, 28-1, Sungju-dong Changwon-si, Kyungsannam-do, 641-120 (Korea)

    2010-08-15

    A module integrated converter (MIC) for a photovoltaic (PV) cell is important part of power conditioning system (PCS). It performs maximum power point tracking of a PV cell to generate the power as much as possible from solar energy. There are several methods for connection between the PV modules and the MICs. In order to avoid partial shading effects, converter-per-module approach was proposed. The MIC that performs maximum power point tracking (MPPT), if it is low efficiency, is no use. The MIC whose output is connected to the output of PV module was proposed for high efficiency. However, there are some problems. In this study, an asymmetrical half-bridge flyback converter is proposed instead of the original flyback converter with same method to solve the problems. The proposed MIC was built to verify the performance. The new topology using soft switching technique showed good performance for the efficiency. At the higher power, the efficiency of the proposed converter is higher than existing converter. (author)

  9. Emergency braking for free piston energy converters

    OpenAIRE

    West, M.; Long, S.; Wang, J; Bingham, Chris; Howe, D.

    2005-01-01

    Free piston energy converters are a potential technology for future hybrid vehicles, as well as stationary power generation applications. A candidate 2-stroke system comprises of two opposing combustion chambers with a common piston rod, and integrated with a tubular permanent magnet electrical machine for the conversion of mechanical to electrical energy. A key issue for the ultimate adoption of such systems, however, is their robustness in the event of a fault to enable a safe shutdown, wit...

  10. Online Scheduling in Distributed Message Converter Systems

    OpenAIRE

    Risse, Thomas; Wombacher, Andreas; Surridge, Mike; Taylor, Steve; Aberer, Karl

    2001-01-01

    The optimal distribution of jobs among hosts in distributed environments is an important factor to achieve high performance. The optimal strategy depends on the application. In this paper we present a new online scheduling strategy for distributed EDI converter system. The strategy is based on the Bin-Stretching approach. The original algorithm has been enhanced to satisfy the business goals of meeting deadlines, priority processing, low response time and high throughput. The algorithm can be...

  11. Reversible thyristor converters of brushless synchronous compensators

    OpenAIRE

    А.М. Galynovskiy; E.М.Dubchak; E.А. Lenskaya

    2013-01-01

    Behavior of models of three-phase-to-single-phase rotary reversible thyristor converters of brushless synchronous compensators in a circuit simulation system is analyzed. It is shown that combined control mode of opposite-connected thyristors may result in the exciter armature winding short circuits both at the thyristor feed-forward and lagging current delay angles. It must be taken into consideration when developing brushless compensator excitation systems.

  12. Angiotensin Converting Enzyme Activity in Alopecia Areata

    OpenAIRE

    Mohammad Reza Namazi; Armaghan Ashraf; Farhad Handjani; Ebrahim Eftekhar; Amir Kalafi

    2014-01-01

    Background. Alopecia areata (AA) is a chronic inflammatory disease of the hair follicle. The exact pathogenesis of AA remains unknown, although recent studies support a T-cell mediated autoimmune process. On the other hand, some studies have proposed that the renin-angiotensin-aldosterone system (RAAS) may play a role in autoimmunity. Therefore, we assessed serum activity of angiotensin converting enzyme (ACE), a component of this system, in AA. Methods. ACE activity was measured in the sera ...

  13. Modeling the bremsstrahlung emission from converters

    CERN Document Server

    Mirea, M; Clapier, F; Hassaïne, M; Ibrahim, F; Müller, A C; Pauwels, N; Proust, J; Verney, D; Antoni, R; Bourgeois, L; Kandri-Rody, S

    2001-01-01

    The bremsstrahlung angular and energy theoretical distributions delivered from W and UCx thick converters are reported. This study is focussed on initial kinetic energies of the electron beam included in the range 30-60 MeV, suitable for the production of large radiative yields able to induce the $^{238}$U fission. These results offer the possibility to evaluate the required shielding for a neutron rich nuclei source.

  14. Metamaterial Polarization Converter Analysis: Limits of Performance

    OpenAIRE

    Markovich, Dmitry L.; Andryieuski, Andrei; Zalkovskij, Maksim; Malureanu, Radu; Lavrinenko, Andrei V.

    2012-01-01

    In this paper we analyze the theoretical limits of a metamaterial converter that allows for linear-to- elliptical polarization transformation with any desired ellipticity and ellipse orientation. We employ the transmission line approach providing a needed level of the design generalization. Our analysis reveals that the maximal conversion e?ciency for transmission through a single metamaterial layer is 50%, while the realistic re ection con?guration can give the conversion e?ciency up to 90%....

  15. New Perspectives on Wave Energy Converter Control

    OpenAIRE

    Price, Alexandra A E

    2009-01-01

    This work examines some of the fundamental problems behind the control of wave energy converters (WECs). Several new perspectives are presented to aid the understanding of the problem and the interpretation of the literature. The first of these is a group of methods for classifying control of WECs. One way to classify control is to consider the stage of power transfer from the wave to the final energy carrier. Consideration of power transfer can also be used to classify WECs in...

  16. Modelling Controlled Arrays of Wave Energy Converters

    OpenAIRE

    Balitsky, Philip

    2013-01-01

    Given the great potential resource, the utilization of wave energy for electricity production can make a signicant contribution to the renewable energy portfolio of coastal nations such as Ireland and the UK. There are, however, many challenges that must be overcome in order for wave energy to be commercially viable. One of the key objectives of the wave energy industry today is to produce commercially viable wave farms by placing multiple wave energy converters (WECs) toget...

  17. Spectral converters and luminescent solar concentrators

    Energy Technology Data Exchange (ETDEWEB)

    Scudo, Petra F.; Abbondanza, Luigi; Fusco, Roberto; Caccianotti, Luciano [Eni S.p.A, Research Center for Non-Conventional Energies - Istituto ENI Donegani, Via G.Fauser 4, 28100 Novara (Italy)

    2010-07-15

    In this paper we present a comprehensive theoretical description of molecular spectral converters in the specific context of luminescent solar concentrators (LSCs). The theoretical model is an extension to a three-level system interacting with a solar radiation bath of the standard quantum theory of atomic radiative processes. We derive the equilibrium equations of the conversion process and provide specific examples of application of this principle to the development of solar concentration devices. (author)

  18. Spectral converters and luminescent solar concentrators

    OpenAIRE

    Scudo, Petra F.; Abbondanza, Luigi; Fusco, Roberto

    2009-01-01

    In this paper we present a comprehensive theoretical description of molecular spectral converters in the specific context of Luminescent Solar Concentrators (LSCs). The theoretical model is an extension to a three-level system interacting with a solar radiation bath of the standard quantum theory of atomic radiative processes. We derive the equilibrium equations of the conversion process and provide specific examples of application of this principle to the development of solar concentration d...

  19. Spectral converters and luminescent solar concentrators

    CERN Document Server

    Scudo, Petra F; Fusco, Roberto

    2009-01-01

    In this paper we present a comprehensive theoretical description of molecular spectral converters in the specific context of Luminescent Solar Concentrators (LSCs). The theoretical model is an extension to a three-level system interacting with a solar radiation bath of the standard quantum theory of atomic radiative processes. We derive the equilibrium equations of the conversion process and provide specific examples of application of this principle to the development of solar concentration devices.

  20. Converting digital learning content into learning objects

    OpenAIRE

    Schreurs, Jeanne; Moreau, Rachel

    2006-01-01

    Our learning content can be structured as learning objects( LO) and as atomic learning objects (ALO). For both of them a set of metadata has been defined. The metadata follows the international standards on learning content. As a result the interoperability of the learning objects in different learning systems is being guaranteed. We are converting the digital learning content into LO's. A learning object is seen as a composition or a scenario model of a set of blocks. The blocks, presenting ...

  1. Reversible thyristor converters of brushless synchronous compensators

    Directory of Open Access Journals (Sweden)

    А.М.Galynovskiy

    2013-12-01

    Full Text Available Behavior of models of three-phase-to-single-phase rotary reversible thyristor converters of brushless synchronous compensators in a circuit simulation system is analyzed. It is shown that combined control mode of opposite-connected thyristors may result in the exciter armature winding short circuits both at the thyristor feed-forward and lagging current delay angles. It must be taken into consideration when developing brushless compensator excitation systems.

  2. Serum angiotensin converting enzyme in pneumonias.

    OpenAIRE

    Kerttula, Y; Weber, T H

    1986-01-01

    Serum concentrations of angiotensin converting enzyme (ACE) were studied in pneumonias caused by different pathogens and in cases in which the aetiology could not be defined. In all aetiological groups, except in viral pneumonia, there was a significant increase in ACE during recovery (p less than 0.001). In several patients the lowest values during the acute phase of disease and the highest values during recovery were outside the reference limits. In cases with known aetiology the highest AC...

  3. Impedance Interaction Modeling and Analysis for Bidirectional Cascaded Converters

    DEFF Research Database (Denmark)

    Tian, Yanjun; Deng, Fujin; Chen, Zhe;

    2015-01-01

    more uncertainty to the system stability. An investigation is performed here for showing that the forward and reverse interactions are prominently different in terms of dynamics and stability even though the cascaded converter control remains unchanged. An important guideline has been drawn for the......For the cascaded converter system, the output impedance of source converter interacts with the input impedance of load converter, and the interaction may cause the system instability. In bidirectional applications, when the power flow is reversed, the impedance interaction also varies, which brings...... control of the cascaded converter. That is when voltage mode converter working as the load converter; the constant power mode converter as the source converter, the system is more stable. The concluded findings have been verified by simulation and experimental results....

  4. Electron-positron high efficiency converter

    International Nuclear Information System (INIS)

    This work is concerned with new possible hardware to produce positrons in the upgraded CESR (Cornell University, USA) linac injector by the enhanced power capacity of the converter and improved focusing of the emerging positrons. The paper describes the design of the converter which can handle 200 MeV incident beams carrying 6 kW average power. In this work it is suggested to design the quarter wave transformer (QWT) from two Helmholtz coils. The electron-positron converter is placed in the median plane of the QWT which is located in the middle of the flat top of the magnetic field Bi (z) distribution. In addition it is suggested to increase Bi up to a level of ∼2.5 T and a solenoidal magnetic field Bf extending over the first e+-linac section up to the level of ∼0.5 T. Calculations have shown that the conversion efficiency about 1% can be achieved for an electron beam having r.m.s. diameter σr∼3 mm. An additional factor of about 2 may be obtained by decreasing σr to 1.5 mm. 15 refs., 6 figs., 4 tabs

  5. Optimizing Design of UHVDC Converter Stations

    Institute of Scientific and Technical Information of China (English)

    MA Weimin; NIE Dingzhen; CAO Yanming

    2012-01-01

    Based on the consultation and study for Xiangjiaba-Shanghai ±800 kV UHVDC(ultra high voltage direct current) project, this paper presents an optimal design for key technique solutions. In this paper, the DC system electrical scheme design, the DC filter design, the DC harmonic component suppression, the over voltage and insulation coordination, the requirements for converter station equipment, the main equipment technical parameters of equipment (including thyristor valve, converter transformer, smoothing reactor, DC breaker), the configuration of measuring device and DC control protection system, and the de-icing operation design are investigated. According to the UHVDC technology researched conclusions and the development of the project construction, the UHVDC system design for converter stations becomes an optimal combination. The optimized design solves numbers of technical problems of the world's first UHVDC project, and it is applied to the project's construction. Under the actual operating condition, the optimized design is proved to be correct and superior. These optimal design conclusions are impartment for developing UHVDC technique and equipment, and provide reference for future UHVDC projects.

  6. Chromatic X-ray imaging with a fine pitch CdTe sensor coupled to a large area photon counting pixel ASIC

    International Nuclear Information System (INIS)

    An innovative X-ray imaging sensor based on Chromatic Photon Counting technology with intrinsic digital characteristics is presented. The system counts individually the incident X-ray photons and selects them according to their energy to produce two color images per exposure. The energy selection occurs in real time and at radiographic imaging speed (GHz global counting rate). Photon counting, color mode and a very fine spatial resolution (more than 10 LP/mm at MTF50) allow to obtain a high ratio between image quality and absorbed dose. The individual building block of the imaging system is a two-side buttable semiconductor radiation detector made of a thin pixellated CdTe crystal coupled to a large area VLSI CMOS pixel ASIC. Modules with 1, 2, 4, and 8 block units have been built. The largest module has 25 × 2.5 cm2 sensitive area. Results and images obtained from testing different modules are presented.

  7. Cryogenic low noise and low dissipation multiplexing electronics, using HEMT+SiGe ASICs, for the readout of high impedance sensors: New version

    International Nuclear Information System (INIS)

    High Electron Mobility Transistors (HEMTs), optimized by CNRS/LPN laboratory for ultra-low noise at very low temperature, have demonstrated their capacity to be used in place of Si JFETs when working temperatures below 100 K are required. We associated them with specific SiGe ASICs that we developed, to implement a complete readout channel able to read highly segmented high impedance detectors within a framework of very low thermal dissipation. Our electronics is dimensioned to read 4096 detection channels, of typically 1 MΩ impedance, and performs 32:1 multiplexing and amplifying, dissipating only 6 mW at 2.5 K and 100 mW at 15 K thanks to high impedance commuting of input stage, with a typical noise of 1 nV/√Hz at 1 kHz

  8. Circuito integrado ASIC para el control vectorial-borroso de un motor de inducción destinado a accionamiento de tráfico vertical

    OpenAIRE

    Mora Jiménez, José Luis; Colodro Ruiz, Francisco; Barrero, Federico; Torralba Silgado, Antonio Jesús; Galván Díez, Eduardo; García Franquelo, Federico; Barranco, M.

    1995-01-01

    Con este trabajo se describe el diseño de un circuito integrado ASIC para el Control Vectorial-Borroso de un Motor de Inducción Des­tinado a Accionamiento de Tráfico Vertical. Se presentan, además, algunos resultados de simu­lación para la optimización del diseño desde el punto de vista del número de puertas. Estas si­mulaciones se han realizado mediante lenguaje de alto nivel utilizándose un modelo real del motor de inducción junto con el inversor trifásico encargado de su accionamiento y se...

  9. GASTONE64: A new front-end ASIC for the cylindrical GEM Inner Tracker of KLOE-2 experiment at DAΦNE

    Energy Technology Data Exchange (ETDEWEB)

    Balla, A.; Bencivenni, G. [INFN-LNF, Frascati (Italy); Branchini, P.; Budano, A. [Istituto di Fisica, Università degli Studi di Roma 3, Roma (Italy); Cerioni, S.; Ciambrone, P. [INFN-LNF, Frascati (Italy); Czerwinski, E. [Institute of Physics, Jagiellonian University, Krakow (Poland); De Lucia, E. [INFN-LNF, Frascati (Italy); De Robertis, G. [INFN-Bari, Bari (Italy); Di Domenico, A. [Dipartimento di Fisica, “Sapienza” Università di Roma (Italy); Domenici, D.; Jing, D. [INFN-LNF, Frascati (Italy); Erriquez, O.; Fanizzi, G. [INFN-Bari, Bari (Italy); Dipartimento di Fisica, Università degli Studi di Bari, Bari (Italy); Felici, G.; Gatta, M. [INFN-LNF, Frascati (Italy); Lacalamita, N.; Liuzzi, R. [INFN-Bari, Bari (Italy); Loddo, F., E-mail: flavio.loddo@ba.infn.it [INFN-Bari, Bari (Italy); Mongelli, M. [INFN-Bari, Bari (Italy); and others

    2013-12-21

    GASTONE64 (Gem Amplifier Shaper Tracking ON Events) is a novel 64-channel mixed analog-digital ASIC developed to readout the cylindrical GEM inner tracking detector of the KLOE-2 apparatus at the e{sup +}e{sup −}DAΦNE collider. It has been designed in the CMOS 0.35μm technology and each analog channel is made of preamplifier, shaper and discriminator. The expected input charge ranges between few fC up to 40 fC, the charge sensitivity is 16 mV/fC while the equivalent input noise charge (ENC) is 800 e{sup −}+40 e{sup −}/pF. The discriminated signals are read-out using a 100 MBit/s LVDS serial data link. The power consumption is about 6 mW/channel.

  10. Cryogenic low noise and low dissipation multiplexing electronics, using HEMT+SiGe ASICs, for the readout of high impedance sensors: New version

    Energy Technology Data Exchange (ETDEWEB)

    Broïse, Xavier de la, E-mail: labroise@cea.fr; Lugiez, Francis; Bounab, Ayoub; Le Coguie, Alain

    2015-07-01

    High Electron Mobility Transistors (HEMTs), optimized by CNRS/LPN laboratory for ultra-low noise at very low temperature, have demonstrated their capacity to be used in place of Si JFETs when working temperatures below 100 K are required. We associated them with specific SiGe ASICs that we developed, to implement a complete readout channel able to read highly segmented high impedance detectors within a framework of very low thermal dissipation. Our electronics is dimensioned to read 4096 detection channels, of typically 1 MΩ impedance, and performs 32:1 multiplexing and amplifying, dissipating only 6 mW at 2.5 K and 100 mW at 15 K thanks to high impedance commuting of input stage, with a typical noise of 1 nV/√Hz at 1 kHz.

  11. GASTONE64: A new front-end ASIC for the cylindrical GEM Inner Tracker of KLOE-2 experiment at DAΦNE

    International Nuclear Information System (INIS)

    GASTONE64 (Gem Amplifier Shaper Tracking ON Events) is a novel 64-channel mixed analog-digital ASIC developed to readout the cylindrical GEM inner tracking detector of the KLOE-2 apparatus at the e+e−DAΦNE collider. It has been designed in the CMOS 0.35μm technology and each analog channel is made of preamplifier, shaper and discriminator. The expected input charge ranges between few fC up to 40 fC, the charge sensitivity is 16 mV/fC while the equivalent input noise charge (ENC) is 800 e−+40 e−/pF. The discriminated signals are read-out using a 100 MBit/s LVDS serial data link. The power consumption is about 6 mW/channel

  12. 60 Gbit/s宽带电路交换ASIC芯片设计%Design of ASIC chips for 60 Gbit/s broadband circuit switching

    Institute of Scientific and Technical Information of China (English)

    孟李林

    2007-01-01

    文章提出了一种60 Gbit/s宽带电路交换专用集成电路(ASIC)芯片的设计实现方案.针对设计芯片速度快、规模大和功耗大等特点,给出了采用流水线设计思想和优化结构处理技术的电路设计解决方案.同时还给出了采用现场可编程门阵列(FPGA)芯片对设计电路进行功能验证的结果和ASIC流片的基本数据.

  13. Combined, but not individual, blockade of ASIC3, P2X, and EP4 receptors attenuates the exercise pressor reflex in rats with freely perfused hindlimb muscles.

    Science.gov (United States)

    Stone, Audrey J; Copp, Steven W; Kim, Joyce S; Kaufman, Marc P

    2015-12-01

    In healthy humans, tests of the hypothesis that lactic acid, PGE2, or ATP plays a role in evoking the exercise pressor reflex proved controversial. The findings in humans resembled ours in decerebrate rats that individual blockade of the receptors to lactic acid, PGE2, and ATP had only small effects on the exercise pressor reflex provided that the muscles were freely perfused. This similarity between humans and rats prompted us to test the hypothesis that in rats with freely perfused muscles combined receptor blockade is required to attenuate the exercise pressor reflex. We first compared the reflex before and after injecting either PPADS (10 mg/kg), a P2X receptor antagonist, APETx2 (100 μg/kg), an activating acid-sensing ion channel 3 (ASIC) channel antagonist, or L161982 (2 μg/kg), an EP4 receptor antagonist, into the arterial supply of the hindlimb of decerebrated rats. We then examined the effects of combined blockade of P2X receptors, ASIC3 channels, and EP4 receptors on the exercise pressor reflex using the same doses, intra-arterial route, and time course of antagonist injections as those used for individual blockade. We found that neither PPADS (n = 5), APETx2 (n = 6), nor L161982 (n = 6) attenuated the reflex. In contrast, combined blockade of these receptors (n = 7) attenuated the peak (↓27%, P EP4 receptors on the endings of thin fiber muscle afferents is required to attenuate the exercise pressor reflex in rats with freely perfused hindlimbs. PMID:26472871

  14. Fault isolation in parallel coupled wind turbine converters

    DEFF Research Database (Denmark)

    Odgaard, Peter Fogh; Thøgersen, Paul Bach; Stoustrup, Jakob

    2010-01-01

    Parallel converters in wind turbine give a number advantages, such as fault tolerance due to the redundant converters. However, it might be difficult to isolate gain faults in one of the converters if only a combined power measurement is available. In this paper a scheme using orthogonal power...... references to the converters is proposed. Simulations on a wind turbine with 5 parallel converters show a clear potential of this scheme for isolation of this gain fault to the correct converter in which the fault occurs....

  15. One-Quadrant Switched-Mode Power Converters

    CERN Document Server

    Petrocelli, R

    2015-01-01

    This article presents the main topics related to one-quadrant power convert- ers. The basic topologies are analysed and a simple methodology to obtain the steady-state output–input voltage ratio is set out. A short discussion of dif- ferent methods to control one-quadrant power converters is presented. Some of the reported derived topologies of one-quadrant power converters are also considered. Some topics related to one-quadrant power converters such as syn- chronous rectification, hard and soft commutation, and interleaved converters are discussed. Finally, a brief introduction to resonant converters is given.

  16. Comparison between the Performance of Basic SEPIC Converter and modified SEPIC Converter with PI Controller

    Directory of Open Access Journals (Sweden)

    Satyendra Kumar Gupta

    2014-08-01

    Full Text Available There are multiple solutions in which line current is sinusoidal. In addition, in the recent years, a great number of circuits have been proposed with non sinusoidal line current. In this paper, a review of the most interesting solutions for single phase and low power applications is carried out. They are classified attending to the line current waveform, energy processing, number of switches, control loops, etc. The major advantages and disadvantages are highlighted and the field of application is found. The paper presents performance analysis of modified SEPIC dc-dc converter with low input voltage and wide output voltage range. The operational analysis and the design is done for the 380W power output of the modified converter. The simulation results of modified SEPIC converter are obtained with PI controller for the output voltage. The results obtained with the modified converter are compared with the basic SEPIC converter topology for the rise time, peak time, settling time and steady state error of the output response for open loop. Voltage tracking curve is also shown for wide output voltage range.

  17. High power density dc/dc converter: Selection of converter topology

    Science.gov (United States)

    Divan, Deepakraj M.

    1990-01-01

    The work involved in the identification and selection of a suitable converter topology is described. Three new dc/dc converter topologies are proposed: Phase-Shifted Single Active Bridge DC/DC Converter; Single Phase Dual Active Bridges DC/DC Converter; and Three Phase Dual Active Bridges DC/DC Converter (Topology C). The salient features of these topologies are: (1) All are minimal in structure, i.e., each consists of an input and output bridge, input and output filter and a transformer, all components essential for a high power dc/dc conversion process; (2) All devices of both the bridges can operate under near zero-voltage conditions, making possible a reduction of device switching losses and hence, an increase in switching frequency; (3) All circuits operate at a constant frequency, thus simplifying the task of the magnetic and filter elements; (4) Since, the leakage inductance of the transformer is used as the main current transfer element, problems associated with the diode reverse recovery are eliminated. Also, this mode of operation allows easy paralleling of multiple modules for extending the power capacity of the system; (5) All circuits are least sensitive to parasitic impedances, infact the parasitics are efficently utilized; and (6) The soft switching transitions, result in low electromagnetic interference. A detailed analysis of each topology was carried out. Based on the analysis, the various device and component ratings for each topology operating at an optimum point, and under the given specifications, are tabulated and discussed.

  18. Dc to ac converter operates efficiently at low input voltages

    Science.gov (United States)

    1965-01-01

    Self-oscillating dc to ac converter with transistor switching to produce a square wave output is used for low and high voltage power sources. The converter has a high efficiency throughout a wide range of loads.

  19. A resonant dc-dc power converter assembly

    DEFF Research Database (Denmark)

    2015-01-01

    The present invention relates to a resonant DC-DC power converter assembly comprising a first resonant DC-DC power converter and a second resonant DC-DC power converter having identical circuit topologies. A first inductor of the first resonant DC-DC power converter and a second inductor of the...... second resonant DC-DC power converter are configured for magnetically coupling the first and second resonant DC-DC power converters to each other to forcing substantially 180 degrees phase shift, or forcing substantially 0 degree phase shift, between corresponding resonant voltage waveforms of the first...... and second resonant DC-DC power converters. The first and second inductors are corresponding components of the first and second resonant DC-DC power converters....

  20. Nonlinear control design for wave energy converter

    OpenAIRE

    Galván García, Bruno

    2013-01-01

    In this thesis, we study the optimization of a single-piston pump system for use in a new wave energy converter by using a feedback mechanism. The first part of the thesis is dedicated to the optimal determination of control variables using the dynamical model of the single-piston pump system, which is a switched system that is built on first principles and describes the dynamics of four main important elements of the system: the buoy, the rod, the piston and the pumped water. ...