WorldWideScience

Sample records for charge-based low-power high-snr

  1. Free-space optical communications with peak and average constraints: High SNR capacity approximation

    KAUST Repository

    Chaaban, Anas

    2015-09-07

    The capacity of the intensity-modulation direct-detection (IM-DD) free-space optical channel with both average and peak intensity constraints is studied. A new capacity lower bound is derived by using a truncated-Gaussian input distribution. Numerical evaluation shows that this capacity lower bound is nearly tight at high signal-to-noise ratio (SNR), while it is shown analytically that the gap to capacity upper bounds is a small constant at high SNR. In particular, the gap to the high-SNR asymptotic capacity of the channel under either a peak or an average constraint is small. This leads to a simple approximation of the high SNR capacity. Additionally, a new capacity upper bound is derived using sphere-packing arguments. This bound is tight at high SNR for a channel with a dominant peak constraint.

  2. Quasi Cyclic Low Density Parity Check Code for High SNR Data Transfer

    Directory of Open Access Journals (Sweden)

    M. R. Islam

    2010-06-01

    Full Text Available An improved Quasi Cyclic Low Density Parity Check code (QC-LDPC is proposed to reduce the complexity of the Low Density Parity Check code (LDPC while obtaining the similar performance. The proposed QC-LDPC presents an improved construction at high SNR with circulant sub-matrices. The proposed construction yields a performance gain of about 1 dB at a 0.0003 bit error rate (BER and it is tested on 4 different decoding algorithms. Proposed QC-LDPC is compared with the existing QC-LDPC and the simulation results show that the proposed approach outperforms the existing one at high SNR. Simulations are also performed varying the number of horizontal sub matrices and the results show that the parity check matrix with smaller horizontal concatenation shows better performance.

  3. HIGH SNR SUM CAPACITY ANALYSIS OF BD MIMO BC SYSTEMS WITH IMPERFECT CSI

    Institute of Scientific and Technical Information of China (English)

    Wang Jing; Liu Zhanli; Wang Yan; You Xiaohu

    2009-01-01

    We investigate the sum capacity of Block Diagonalization precoding Multiple Input Multiple Output Broadcast Channels (BD MIMO BC) with imperfect Channel State Information (CSI) at the base station. Since it is difficult to obtain the exact expression, a lower and an upper bounds of the sum capacity under Gaussian channel estimation errors are drived instead. Analyses show that the gap between two bounds is considerably tight at all Signal to Noise Ratio (SNR) region. From the lower bound of the sum capacity, we can see that the multiplexing gain tends to be zero at high SNR region, which indicates that the BD MIMO BC system with channel estimation errors is interference-limited at high SNR.

  4. High-speed and high-SNR photoacoustic microscopy based on a galvanometer mirror in non-conducting liquid

    Science.gov (United States)

    Kim, Jin Young; Lee, Changho; Park, Kyungjin; Han, Sangyeob; Kim, Chulhong

    2016-01-01

    Optical-resolution photoacoustic microscopy (OR-PAM), a promising microscopic imaging technique with high ultrasound resolution and superior optical sensitivity, can provide anatomical, functional, and molecular information at scales ranging from the microvasculature to single red blood cells. In particular, real-time OR-PAM imaging with a high signal-to-noise ratio (SNR) is a prerequisite for widespread use in preclinical and clinical applications. Although several technical approaches have been pursued to simultaneously improve the imaging speed and SNR of OR-PAM, they are bulky, complex, not sensitive, and/or not actually real-time. In this paper, we demonstrate a simple and novel OR-PAM technique which is based on a typical galvanometer immersed in non-conducting liquid. Using an opto-ultrasound combiner, this OR-PAM system achieves a high SNR and fast imaging speed. It takes only 2 seconds to acquire a volumetric image with a wide field of view (FOV) of 4 × 8 mm2 along the X and Y axes, respectively. The measured lateral and axial resolutions are 6.0 and 37.7 μm, respectively. Finally, as a demonstration of the system’s capability, we successfully imaged the microvasculature in a mouse ear in vivo. Our new method will contribute substantially to the popularization and commercialization of OR-PAM in various preclinical and clinical applications. PMID:27708379

  5. Low power digital signal processing

    DEFF Research Database (Denmark)

    Paker, Ozgun

    2003-01-01

    This thesis introduces a novel approach to programmable and low power platform design for audio signal processing, in particular hearing aids. The proposed programmable platform is a heterogeneous multiprocessor architecture consisting of small and simple instruction set processors called mini...... data addressing capabilities lead to the design of low power mini-cores. The algorithm suite also consisted of less demanding and/or irregular algorithms (LMS, compression) that required subsample rate signal processing justifying the use of a DSP/CPU-core. The thesis also contributes to the recent...... to be a viable alternative to conventional expensive test equipment. Finally, the work presented in this thesis has been published at several IEEE workshops and conferences, and in the Journal of VLSI Signal Processing....

  6. Low power unattended defense reactor

    International Nuclear Information System (INIS)

    A small, low power, passive, nuclear reactor electric power supply has been designed for unattended defense applications. Through innovative utilization of existing proven technologies and components, a highly reliable, walk-away safe design has been obtained. Operating at a thermal power level of 200 kWt, the reactor uses low enrichment uranium fuel in a graphite block core to generate heat that is transferred through heat pipes to a thermoelectric (TE) converter. Waste heat is removed from the TEs by circulation of ambient air. Because such a power supply offers the promise of minimal operation and maintenance (O and M) costs as well as no fuel logistics, it is particularly attractive for remote, unattended applications such as the North Warning System

  7. Ultra low power full adder topologies

    DEFF Research Database (Denmark)

    Moradi, Farshad; Wisland, Dag T.; Mahmoodi, Hamid;

    In this paper several low power full adder topologies are presented. The main idea of these circuits is based on the sense energy recovery full adder (SERF) design and the GDI (gate diffusion input) technique. These subthreshold circuits are employed for ultra low power applications. While the pr...

  8. Dual Mode Low Power Hall Thruster Project

    Data.gov (United States)

    National Aeronautics and Space Administration — Sample and return missions desire and missions like Saturn Observer require a low power Hall thruster that can operate at high thrust to power as well as high...

  9. Low Power Mass Spectrometer employing TOF Project

    Data.gov (United States)

    National Aeronautics and Space Administration — A low power Mass Spectrometer employing multiple time of flight circuits for parallel processing is possible with a new innovation in design of the Time of flight...

  10. Simultaneous Unbalanced Shared Local Oscillator Heterodyne Interferometry (SUSHI) for high SNR, minimally destructive dispersive detection of time-dependent atomic spins

    CERN Document Server

    Locke, Mary

    2013-01-01

    We demonstrate "Simultaneous Unbalanced Shared Local Oscillator Heterodyne Interferometry (SUSHI)," a new method for minimally destructive, high SNR dispersive detection of atomic spins. In SUSHI a dual-frequency probe laser interacts with atoms in one arm of a Mach-Zehnder interferometer, then beats against a bright local oscillator beam traversing the other arm, resulting in two simultaneous, independent heterodyne measurements of the atom-induced phase shift. Measurement noise due to mechanical disturbances of beam paths is strongly rejected by the technique of \\emph{active subtraction} in which anti-noise is actively written onto the local oscillator beam via an optical phase-locked-loop. In SUSHI, technical noise due to phase, amplitude, and frequency fluctuations of the various laser fields is strongly rejected (i) for any mean phase bias between the interferometer arms, (ii) without the use of piezo actuated mirrors, and (iii) without signal balancing. We experimentally demonstrate an ultra-low technic...

  11. Exercise efficiency of low power output cycling.

    Science.gov (United States)

    Reger, M; Peterman, J E; Kram, R; Byrnes, W C

    2013-12-01

    Exercise efficiency at low power outputs, energetically comparable to daily living activities, can be influenced by homeostatic perturbations (e.g., weight gain/loss). However, an appropriate efficiency calculation for low power outputs used in these studies has not been determined. Fifteen active subjects (seven females, eight males) performed 14, 5-min cycling trials: two types of seated rest (cranks vertical and horizontal), passive (motor-driven) cycling, no-chain cycling, no-load cycling, cycling at low (10, 20, 30, 40 W), and moderate (50, 60, 80, 100, 120 W) power outputs. Mean delta efficiency was 57% for low power outputs compared to 41.3% for moderate power outputs. Means for gross (3.6%) and net (5.7%) efficiencies were low at the lowest power output. At low power outputs, delta and work efficiency values exceeded theoretical values. In conclusion, at low power outputs, none of the common exercise efficiency calculations gave values comparable to theoretical muscle efficiency. However, gross efficiency and the slope and intercept of the metabolic power vs mechanical power output regression provide insights that are still valuable when studying homeostatic perturbations.

  12. Low power implementation of datapath using regularity

    Institute of Scientific and Technical Information of China (English)

    LAI Li-ya; LIU Peng

    2005-01-01

    Datapath accounts for a considerable part of power consumption in VLSI circuit design. This paper presents a method for physical implementation of datapath to achieve low power consumption. Regularity is a characteristic of datapath and the key of the proposed method, where synthesis is tightly combined with placement to make full use of regularity, so that low power consumption is achieved. In This paper, a new concept of Synthesis In Relative Placement (SIRP) is given to deal with the semi-regularity in some datapath. Experimental results of a sample circuit validated the proposed method.

  13. Low-Power Public Key Cryptography

    Energy Technology Data Exchange (ETDEWEB)

    BEAVER,CHERYL L.; DRAELOS,TIMOTHY J.; HAMILTON,VICTORIA A.; SCHROEPPEL,RICHARD C.; GONZALES,RITA A.; MILLER,RUSSELL D.; THOMAS,EDWARD V.

    2000-11-01

    This report presents research on public key, digital signature algorithms for cryptographic authentication in low-powered, low-computation environments. We assessed algorithms for suitability based on their signature size, and computation and storage requirements. We evaluated a variety of general purpose and special purpose computing platforms to address issues such as memory, voltage requirements, and special functionality for low-powered applications. In addition, we examined custom design platforms. We found that a custom design offers the most flexibility and can be optimized for specific algorithms. Furthermore, the entire platform can exist on a single Application Specific Integrated Circuit (ASIC) or can be integrated with commercially available components to produce the desired computing platform.

  14. Designing Low Power Circuits: A Review

    Directory of Open Access Journals (Sweden)

    Rohan M Joshi

    2012-09-01

    Full Text Available The growing market of battery-operated portable applications like laptop, mobile etc requires microelectronic devices with low power consumption. As transistor size continues to shrink and as need for more complex chips increases, power management of the chip is one of the key challenges in VLSI industry. The manufacturers are looking for low power designs because providing adequate cooling and packaging increases the cost and limits the functionality of the device. This paper surveys the optimization techniques used to reduce power consumption in CMOS at all the levels of the design flow. It includes the technology used to implement digital circuits, the circuit design style and topology, the architecture for implementing the circuits, and at the highest level the software and algorithms that are implemented.

  15. Versatile experimental low power 4 K cryocooler

    Science.gov (United States)

    Lambert, N.; Barbanera, S.; Zimmerman, J. E.

    The construction of a low power cryocooler consisting of a five-stage plastic Stirling cooler with an additional Joule-Thomson stage is described. Among its novel features are a contamination-free, pneumatic helium compressor and displacer drive. Valve timing is under computer control. Titanium foil embedded in the cylinder wall reduces helium diffusion through the plastic. The Joule-Thomson stage uses the same low pressure helium as the Stirling stages. The Stirling system cools down below 9 K. The Joule-Thomson stage delivers a few mW cooling at 4.2 K.

  16. Integrated low power digital gyro control electronics

    Science.gov (United States)

    M'Closkey, Robert (Inventor); Challoner, A. Dorian (Inventor); Grayver, Eugene (Inventor); Hayworth, Ken J. (Inventor)

    2005-01-01

    Embodiments of the invention generally encompass a digital, application specific integrated circuit (ASIC) has been designed to perform excitation of a selected mode within a vibratory rate gyroscope, damping, or force-rebalance, of other modes within the sensor, and signal demodulation of the in-phase and quadrature components of the signal containing the angular rate information. The ASIC filters dedicated to each channel may be individually programmed to accommodate different rate sensor designs/technology or variations within the same class of sensors. The ASIC architecture employs a low-power design, making the ASIC, particularly suitable for use in power-sensitive applications.

  17. Radiation Tolerant Low Power Precision Time Source Project

    Data.gov (United States)

    National Aeronautics and Space Administration — The availability of small, low power atomic clocks is now a reality for ground-based and airborne navigation systems. Kernco's Low Power Precision Time Source...

  18. Microprocessor system for low power feedwater control

    International Nuclear Information System (INIS)

    The results of an ongoing Combustion Engineering development program to improve steam generator level control during low power operation are presented. A discussion is presented on the analytical tools, the verification process and the simulation capabilities that are currently available for the design and evaluation of advanced steam generator control systems. A review is then presented on the dynamic processes internal to the steam generator that must be controlled, the conceptual approach used in arriving at a design, followed by the verification of the design using a detailed digital simulation of the process and the control system. Finally, a discussion is presented on the reasons for the selection of a microprocessor based systems over a conventional analog system and the potential improvements in reliability and flexibility

  19. Low-Power Wireless Sensor Network Infrastructures

    DEFF Research Database (Denmark)

    Hansen, Morten Tranberg

    Advancements in wireless communication and electronics improving form factor and hardware capabilities has expanded the applicability of wireless sensor networks. Despite these advancements, devices are still limited in terms of energy which creates the need for duty-cycling and low-power protocols...... in order to achieve the wanted lifetimes. Through more than a decade of wireless sensor network research, progress towards realizing wanted lifetimes have been made and wireless standards for packet formatting and routing have been proposed. With standards in place, the wide-span between programming...... environments and communication primitives in wireless sensor network and traditional network development are closing. However, fundamental differences in wireless technology and energy constraints are still to be considered at the lower levels of the software stack. To fulfill energy requirements hardware...

  20. Energy neutral and low power wireless communications

    Science.gov (United States)

    Orhan, Oner

    Wireless sensor nodes are typically designed to have low cost and small size. These design objectives impose restrictions on the capacity and efficiency of the transceiver components and energy storage units that can be used. As a result, energy becomes a bottleneck and continuous operation of the sensor network requires frequent battery replacements, increasing the maintenance cost. Energy harvesting and energy efficient transceiver architectures are able to overcome these challenges by collecting energy from the environment and utilizing the energy in an intelligent manner. However, due to the nature of the ambient energy sources, the amount of useful energy that can be harvested is limited and unreliable. Consequently, optimal management of the harvested energy and design of low power transceivers pose new challenges for wireless network design and operation. The first part of this dissertation is on energy neutral wireless networking, where optimal transmission schemes under different system setups and objectives are investigated. First, throughput maximization for energy harvesting two-hop networks with decode-and-forward half-duplex relays is studied. For a system with two parallel relays, various combinations of the following four transmission modes are considered: Broadcast from the source, multi-access from the relays, and successive relaying phases I and II. Next, the energy cost of the processing circuitry as well as the transmission energy are taken into account for communication over a broadband fading channel powered by an energy harvesting transmitter. Under this setup, throughput maximization, energy maximization, and transmission completion time minimization problems are studied. Finally, source and channel coding for an energy-limited wireless sensor node is investigated under various energy constraints including energy harvesting, processing and sampling costs. For each objective, optimal transmission policies are formulated as the solutions of a

  1. Low Power CMOS Digitally Controlled Oscillator

    Directory of Open Access Journals (Sweden)

    Sujata Pandey,

    2010-08-01

    Full Text Available Here, two new designs of CMOS digitally controlled oscillators (DCO for low power application have been proposed. First design has been implemented with one driving strength controlled delay cell and withtwo NAND gates used as inverters. The second design with one delay cell and by two NOR gates is presented. The proposed circuits have been simulated in spice with 0.35 μm (micrometer technology at supply voltage of 3.3V. The first design shows 35-40% reduction in power consumption and second design shows 37.5-41.8% power saving as compared to conventional DCO. The frequency range of first and second design varies [3.1316 - 3.1085] GHz and [3.8112 – 3.7867] GHz respectively with the variation in control word from ‘000000’ to ‘000001'. Power consumption of first and second design varies [640.3845 - 700.2977] μW and [617.6616 -6 77.3996] μW respectively.

  2. Design and Analysis of Sequential Elements for Low Power Clocking System with Low Power Techniques

    Directory of Open Access Journals (Sweden)

    S.Sasidhar Reddy

    2014-09-01

    Full Text Available This paper proposed the design of sequential elements for low power clocking system with low low power techniques for saving the power. Power consumption is a major bottleneck of system performance and is listed as one of the top three challenges in International Technology Roadmap for Semiconductor 2008. In practice, a large portion of the on chip power is consumed by the clock system which is made of the clock distribution network and flop-flops. In this paper, various design techniques for a low power clocking system are surveyed. Among them is an effective way to reduce capacity of the clock load by minimizing number of clocked transistors. To approach this, proposed a novel clocked pair shared flip-flop which reduces the number of local clocked transistors by approximately 40%. A 24% reduction of clock driving power is achieved. In addition, low swing and double edge clocking, can be easily incorporated into the new flip-flop to build clocking systems. As the feature size becomes smaller, shorter channel lengths result in increased sub-threshold leakage current through a transistor when it is off. Dual sleep and sleepy stack methods are proposed to avoid static power consumption; the flip flops are simulated using HSPICE.

  3. Power electronics for low power arcjets

    Science.gov (United States)

    Hamley, John A.; Hill, Gerald M.

    1991-01-01

    In anticipation of the needs of future light-weight, low-power spacecraft, arcjet power electronics in the 100 to 400 W operating range were developed. Limited spacecraft power and thermal control capacity of these small spacecraft emphasized the need for high efficiency. Power topologies similar to those in the higher 2 kW and 5 to 30 kW power range were implemented, including a four transistor bridge switching circuit, current mode pulse-width modulated control, and an output current averaging inductor with an integral pulse generation winding. Reduction of switching transients was accomplished using a low inductance power distribution network, and no passive snubber circuits were necessary for power switch protection. Phase shift control of the power bridge was accomplished using an improved pulse width modulation to phase shift converter circuit. These features, along with conservative magnetics designs allowed power conversion efficiencies of greater than 92.5 percent to be achieved into resistive loads over the entire operating range of the converter. Electromagnetic compatibility requirements were not considered in this work, and control power for the converter was derived from AC mains. Addition of input filters and control power converters would result in an efficiency of on the order of 90 percent for a flight unit. Due to the developmental nature of arcjet systems at this power level, the exact nature of the thruster/power processor interface was not quantified. Output regulation and current ripple requirements of 1 and 20 percent respectively, as well as starting techniques, were derived from the characteristics of the 2 kW system but an open circuit voltage in excess of 175 V was specified. Arcjet integration tests were performed, resulting in successful starts and stable arcjet operation at power levels as low as 240 W with simulated hydrazine propellants.

  4. Hacking and penetration testing with low power devices

    CERN Document Server

    Polstra, Philip

    2014-01-01

    Hacking and Penetration Testing with Low Power Devices shows you how to perform penetration tests using small, low-powered devices that are easily hidden and may be battery-powered. It shows how to use an army of devices, costing less than you might spend on a laptop, from distances of a mile or more. Hacking and Penetration Testing with Low Power Devices shows how to use devices running a version of The Deck, a full-featured penetration testing and forensics Linux distribution, and can run for days or weeks on batteries due to their low power consumption. Author Philip Polstra shows how to

  5. Low power wireless EEG headset for BCI applications

    NARCIS (Netherlands)

    Patki, S.; Grundlehner, B.; Nakada, T.; Penders, J.

    2011-01-01

    Miniaturized, low power and low noise circuits and systems are instrumental in bringing EEG monitoring to the home environment. In this paper, we present a miniaturized, low noise and low-power EEG wireless platform integrated into a wearable headset. The wireless EEG headset achieves remote and wea

  6. Low Power/Low Voltage Interface Circuitry for Capacitive Sensors

    DEFF Research Database (Denmark)

    Furst, Claus Efdmann

    This thesis focuses mainly on low power/low voltage interface circuits, implemented in CMOS, for capacitive sensors. A brief discussion of demands and possibilities for analog signal processing in the future is presented. Techniques for low power design is presented. This is done by analyzing power...... consumption of different amplifier topologies. Next, low power features of different amplifier types are analyzed on transistor level. A brief comparison of SI circuits for low power applications vs. SC circuits is presented. Methodologies for low voltage design is presented. This is followed by a collection...... power consumption. It is shown that the Sigma-Delta modulator is advantageous when embedded in a feedback loop with a mechanical sensor. Here a micro mechanical capacitive microphone. Feedback and detection circuitry for a capacitive microphone is presented. Practical implementations of low power...

  7. Compact Low-Power Driver for Deformable Mirror Systems Project

    Data.gov (United States)

    National Aeronautics and Space Administration — This proposal describes a new concept to drive MEMS DMs using low-power, high-voltage multiplexing. Compared to other reported approaches, the proposed architecture...

  8. Design of ultra-low power impulse radios

    CERN Document Server

    Apsel, Alyssa; Dokania, Rajeev

    2014-01-01

    This book covers the fundamental principles behind the design of ultra-low power radios and how they can form networks to facilitate a variety of applications within healthcare and environmental monitoring, since they may operate for years off a small battery or even harvest energy from the environment. These radios are distinct from conventional radios in that they must operate with very constrained resources and low overhead.  This book provides a thorough discussion of the challenges associated with designing radios with such constrained resources, as well as fundamental design concepts and practical approaches to implementing working designs.  Coverage includes integrated circuit design, timing and control considerations, fundamental theory behind low power and time domain operation, and network/communication protocol considerations.   • Enables detailed understanding of the design space for ultra-low power radio; • Provides detailed discussion and examples of the design of a practical low power ...

  9. Compact Low-Power Driver for Deformable Mirror Systems Project

    Data.gov (United States)

    National Aeronautics and Space Administration — Boston Micromachines Corporation (BMC), a leading developer of unique, high-resolution micromachined deformable mirrors (DMs), will develop a compact, low-power,...

  10. Ultra-Low-Power MEMS Selective Gas Sensors Project

    Data.gov (United States)

    National Aeronautics and Space Administration — KWJ offers this proposal for a very low power but very practical "nano-watt" MEMS sensor platform for NASA requirements. The proposed nano-sensor platform is ultra...

  11. Ultra-Low-Power MEMS Selective Gas Sensors

    Science.gov (United States)

    Stetter, Joseph

    2012-01-01

    This innovation is a system for gas sensing that includes an ultra-low-power MEMS (microelectromechanical system) gas sensor, combined with unique electronic circuitry and a proprietary algorithm for operating the sensor. The electronics were created from scratch, and represent a novel design capable of low-power operation of the proprietary MEMS gas sensor platform. The algorithm is used to identify a specific target gas in a gas mixture, making the sensor selective to that target gas.

  12. Wireless powering for low-power distributed sensors

    Directory of Open Access Journals (Sweden)

    Popović Zoya B.

    2006-01-01

    Full Text Available In this paper, an overview of the field of wireless powering is presented with an emphasis on low-power applications. Several rectenna elements and arrays are discussed in more detail: (1 a 10-GHz array for powering sensors in aircraft wings; (2 a single antenna in the 2.4-GHz ISM band for low-power assisted-living sensors; and (3 a broadband array for power harvesting in the 2-18GHz frequency range.

  13. Low-Power Circuits for Brain–Machine Interfaces

    OpenAIRE

    Sarpeshkar, Rahul; Wattanapanitch, Woradorn; Arfin, Scott K.; Rapoport, Benjamin I.; Mandal, Soumyajit; Baker, Michael W.; Fee, Michale S.; Musallam, Sam; Andersen, Richard A.

    2008-01-01

    This paper presents work on ultra-low-power circuits for brain–machine interfaces with applications for paralysis prosthetics, stroke, Parkinson’s disease, epilepsy, prosthetics for the blind, and experimental neuroscience systems. The circuits include a micropower neural amplifier with adaptive power biasing for use in multi-electrode arrays; an analog linear decoding and learning architecture for data compression; low-power radio-frequency (RF) impedance-modulation circ...

  14. 47 CFR 73.6019 - Digital Class A TV station protection of low power TV, TV translator, digital low power TV and...

    Science.gov (United States)

    2010-10-01

    ... power TV, TV translator, digital low power TV and digital TV translator stations. 73.6019 Section 73... low power TV, TV translator, digital low power TV and digital TV translator stations. An application... A TV station will not be accepted if it fails to protect authorized low power TV, TV...

  15. Authenticated Encryption for Low-Power Reconfigurable Wireless Devices

    DEFF Research Database (Denmark)

    Khajuria, Samant; Andersen, Birger

    2013-01-01

    this enabling technology, these radios have to propose cryptographic services such as con- fidentiality, integrity and authentication. Therefore, integration of security services to these low-power devices is very challenging and crucial as they have limited resources and computational capabilities....... In this paper, we present a crypto solution for reconfigurable devices. The solution is a single pass Authenticated Encryption (AE) scheme that is designed for protecting both message confidentiality and its authenticity. This makes AE very attractive for low-cost low-power hardware implementation. For test...

  16. Technology and use of low power research reactors

    International Nuclear Information System (INIS)

    The report contains a summary of discussions and 10 papers presented at the Consultants' Meeting on the Technology and Use of Low Power Research Reactors organized by the IAEA and held in Beijing (China) during 30 April - 3 May 1985. The following topics have been covered: reactor utilization in medicine and biology, in universities, for training, as a neutron source for radiography and some remarks on the safety of low power research reactors. A separate abstract was prepared for each paper presented at the meeting

  17. Low Power Systolic Array Based Digital Filter for DSP Applications

    Directory of Open Access Journals (Sweden)

    S. Karthick

    2015-01-01

    Full Text Available Main concepts in DSP include filtering, averaging, modulating, and correlating the signals in digital form to estimate characteristic parameter of a signal into a desirable form. This paper presents a brief concept of low power datapath impact for Digital Signal Processing (DSP based biomedical application. Systolic array based digital filter used in signal processing of electrocardiogram analysis is presented with datapath architectural innovations in low power consumption perspective. Implementation was done with ASIC design methodology using TSMC 65 nm technological library node. The proposed systolic array filter has reduced leakage power up to 8.5% than the existing filter architectures.

  18. Novel Low Power Comparator Design using Reversible Logic Gates

    Directory of Open Access Journals (Sweden)

    Nagamani A N

    2011-09-01

    Full Text Available Reversible logic has received great attention in the recent years due to its ability to reduce the power dissipation which is the main requirement in low power digital design. It has wide applications inadvanced computing, low power CMOS design, Optical information processing, DNA computing, bio information, quantum computation and nanotechnology. This paper presents a novel design of reversiblecomparator using the existing reversible gates and proposed new Reversible BJN gate. All the comparators have been modeled and verified using VHDL and ModelSim. A comparative result is presented in terms of number of gates, number of garbage outputs, number of constant inputs and Quantum cost.

  19. Designing Asynchronous Circuits for Low Power: An IFIR Filter

    DEFF Research Database (Denmark)

    Nielsen, Lars Skovby; Sparsø, Jens

    1999-01-01

    This paper addresses the design of asynchronous circuits for low power through an example: a filter bank for a digital hearing aid. The asynchronous design re-implements an existing synchronous circuit which is used in a commercial product. For comparison, both designs have been fabricated...... by numerically small samples). Apart from the improved RAM design, these measures are only viable in an asynchronous design. The principles and techniques explained in this paper are of a general nature, and they apply to the design of asynchronous low-power digital signal-processing circuits in a broader...

  20. Low-power wearable sensing for preventive healthcare

    NARCIS (Netherlands)

    Penders, Julien; Altini, Marco; Wijsman, Jacqueline; Vullers, Rudolf; Van Hoof, C.

    2013-01-01

    Low-power wearable sensing will soon allow the quantitative and continuous measurement of health parameters. In this paper we illustrate how wearable sensors can be used to track activity and energy expenditure, and measure stress. Soon such information may empower people in managing their own healt

  1. Low-power attitude determination for magnetometry planetary missions

    DEFF Research Database (Denmark)

    Christensen, Thorbjørn Helvig

    with emphasis on the limited budget onboard very small satellites. A true low-power attitude sensor using the Anisotropic Magneto Resistor effect have been designed to late prototype state. Two prototypes of the AMR magnetometer have been built. One of the prototypes has an analog output and the second...

  2. Ultra low power transceiver for wireless body area networks

    CERN Document Server

    Masuch, Jens

    2013-01-01

    This book describes the design of ultra low power transceivers for body area networks.  Since these applications have very limited energy resources, typically powered only by tiny batteries or through energy harvesting techniques, this book describes an architecture for a Bluetooth low energy transceiver to overcome these limitations. Coverage includes not only the main concepts for achieving low power consumption, but also the details of the circuit design and its implementation in a standard CMOS technology.     ·         Guides readers through the design of ultra low power transceivers for body area networks, from architecture to circuit-level implementation; ·         Describes 4 key strategies for ultra-low power transceiver design and specific, innovative techniques for circuit-level design; ·         Enables readers to design transceivers for body area networks that are 27% more energy efficient than those currently available; ·         Includes a review of the st...

  3. TOWARDS A VERSATILE WIRELESS PLATFORM FOR LOW-POWER APPLICATIONS

    Directory of Open Access Journals (Sweden)

    Sandor Szilvasi

    2011-01-01

    Full Text Available Traditional wireless sensor network architectures are based on low-power microcontrollers and highly integrated short range radio transceiver chips operating in one of the few ISM bands. This combination provides a convenient and proven approach to design and build inexpensive sensor nodes rapidly. However, the black box nature of these radio chips severely limit experimentation and research with novel and innovative technologies in the wireless infrastructure. Our team previously proposed a revolutionary architecture for wireless nodes based on Flash FPGA devices. This paper shows the initial results of our work through the implementation and evaluation of a simple baseband FSK modem in the SmartFusion FPGA fabric. We also demonstrate how we could leverage existing software radio projects to use the baseband modem in a wide range of radio frequency bands. Finally, the paper describes our approach and implementation of power management and instrumentation, a key building block in our modularized low-power software radio platform.

  4. Performance Analysis of Reconfigurable SRAM Cell for Low Power Applications

    Directory of Open Access Journals (Sweden)

    Dillibabu.Mannem

    2012-06-01

    Full Text Available The majority of space taken in an integrated circuit is the memory. SRAM design consists of key considerations, such as increased speed, low power and reduced layout area. A cell which is functional at the nominal supply voltage, can fail at a lower voltage. From a system perspective this leads to a higher bit-error rate with voltage scaling and limits the opportunity for power saving. While this is a serious bottleneck for SRAM arrays used for data storage. This paper presents a performance analysis of reconfigurable SRAM cell for low power application. Simulations using TSMC 0.35um technology show that the SRAM cell read & write access times are 1.53ns and 1.93ns. Mentor Graphics ELDO and EZ-wave are used for simulations.

  5. Low power RF circuit design in standard CMOS technology

    CERN Document Server

    Alvarado, Unai; Adín, Iñigo

    2012-01-01

    Low Power Consumption is one of the critical issues in the performance of small battery-powered handheld devices. Mobile terminals feature an ever increasing number of wireless communication alternatives including GPS, Bluetooth, GSM, 3G, WiFi or DVB-H. Considering that the total power available for each terminal is limited by the relatively slow increase in battery performance expected in the near future, the need for efficient circuits is now critical. This book presents the basic techniques available to design low power RF CMOS analogue circuits. It gives circuit designers a complete guide of alternatives to optimize power consumption and explains the application of these rules in the most common RF building blocks: LNA, mixers and PLLs. It is set out using practical examples and offers a unique perspective as it targets designers working within the standard CMOS process and all the limitations inherent in these technologies.

  6. Low Power Reduced Instruction Set Architecture Using Clock Gating Technique

    Directory of Open Access Journals (Sweden)

    M.Kamaraju

    2013-10-01

    Full Text Available Today, all the portable device’s in electronics nee ds to be realized with low power architectures beca use of power consumption is a main consideration along wit h other performance parameters. Low power consumption helps to reduce heat dissipation, incre ases battery life and also reliability. In this pap er a 16- bit Reduced Instruction set Architecture (RISA pre sented. This architecture can handle multiple inter rupts and performing serial communication effectively. It can supported RISC (Reduced Instruction Set Computer concepts. A popular technique of Clock ga ting is applied to the proposed architecture and th en reduces the power. This entire architecture capture d using VerilogHDL and implemented on FPGA using Xilinx tools .

  7. Numerical Analysis of Powder Properties in Low Power Plasma Torch

    Institute of Scientific and Technical Information of China (English)

    YAN Zhi-jun; GAO Yang; HEI Zhu-kun; AN Lian-tong

    2004-01-01

    A mathematical model was presented to describe the particle trajectory, velocity and temperature properties in the low power plasma spraying torch (3.6 kW)in which powder particles were directly injected into the region between the cathode and anode. The results show that the characteristics of the particles by low power plasma spraying are similar to that by traditional APS( Atmosphere plasma spraying) in 40 kW. The velocities of the particles increase with the increase of inlet gas flow rate, current and percentage of nitrogen and hydrogen, while the temperature of the powder increase with the decrease of the gas flow rate and with the increase of current and percentage of nitrogen and hydrogen.

  8. Degrading Precision Arithmetics for Low-power FIR Implementation

    DEFF Research Database (Denmark)

    Albicocco, Pietro; Cardarilli, Gian Carlo; Nannarelli, Alberto;

    2011-01-01

    In this paper a review of different techniques used to implement highly optimized DSP systems is presented. The case of study is the implementation of parallel FIR filters aimed to applications characterized by high speed and high selectivity in frequency where at the same time low power dissipat......In this paper a review of different techniques used to implement highly optimized DSP systems is presented. The case of study is the implementation of parallel FIR filters aimed to applications characterized by high speed and high selectivity in frequency where at the same time low power...... on selective bit freezing, DPA-II, based on VDD voltage scaling, and DPA-III, based on power gating. Some theoreticaVsimuiative analysis of the introduced arithmetic errors and some implementation results are shown. A discussion on the suitability of these methodologies on standard cell technologies and FPGAs...

  9. Address Counter Generators for Low Power Memory BIST

    Directory of Open Access Journals (Sweden)

    Balwinder Singh

    2011-07-01

    Full Text Available In today's Integrated Circuits (IC's designs Built-in Self Test (BIST is becoming important for the memory which is the most necessary part of the System on Chip. The March algorithm has been widely used to test memory core of System on chip (SOC. LFSRs and counters are mainly used to generate the memory addresses, which can be serially applied to the memory cores under test. In this paper Address counters and Data generators (i.e. parts of the MBIST are designed. These implemented in Hardware Description Language (HDL, and the area and power analyzed for each case . From the analyzed results the low power LFSRs and counters can be identify for the low power memory BIST design.

  10. Low Power Dual Edge - Triggered Static D Flip-Flop

    Directory of Open Access Journals (Sweden)

    Anurag

    2013-06-01

    Full Text Available This paper enumerates new architecture of low power dual-edge triggered Flip-Flop (DETFF designed at 180nm CMOS technology. In DETFF same data throughput can be achieved with half of the clock frequency as compared to single edge triggered Flip-Flop (SETFF. In this paper conventional and proposed DETFF are presented and compared at same simulation conditions. The post layout experimental results comparison shows that the average power dissipation is improved by 48.17%, 41.29% and 36.84% when compared with SCDFF, DEPFF and SEDNIFF respectively and improvement in PDP is 42.44%, 33.88% and 24.69% as compared to SCDFF, DEPFF and SEDNIFF respectively. Therefore the proposed DETFF design is suitable for low power and small area applications.

  11. [Low-power Wireless Micro Ambulatory Electrocardiogram Node].

    Science.gov (United States)

    Cai, Zhipeng; Luo, Kan; Li, Jianqing

    2016-02-01

    Ambulatory electrocardiogram (ECG) monitoring can effectively reduce the risk and death rate of patients with cardiovascular diseases (CVDs). The Body Sensor Network (BSN) based ECG monitoring is a new and efficien method to protect the CVDs patients. To meet the challenges of miniaturization, low power and high signal quality of the node, we proposed a novel 50 mmX 50 mmX 10 mm, 30 g wireless ECG node, which includes the single-chip an alog front-end AD8232, ultra-low power microprocessor MSP430F1611 and Bluetooth module HM-11. The ECG signal quality is guaranteed by the on-line digital filtering. The difference threshold algorithm results in accuracy of R-wave detection and heart rate. Experiments were carried out to test the node and the results showed that the pro posed node reached the design target, and it has great potential in application of wireless ECG monitoring. PMID:27382732

  12. Glitch Reduction in Low- Power Low- Frequency Multiplier

    Directory of Open Access Journals (Sweden)

    Bhethala Rajasekhar

    2014-01-01

    Full Text Available Multiplication is an essential arithmetic operation for common DSP applications, such as filtering and fast Fourier transform (FFT. To achieve high execution speed, parallel array multipliers are widely used. These multipliers tend to consume most of the power in DSP computations, and thus power-efficient multipliers are very important for the design of low-power DSP systems. A straightforward approach is to design a full adder (FA that consumes less power. Power reduction can also be achieved through structural modification. For example, rows of partial products can be ignored. In this project a 10 transistor full adder is designed for low power which is used in the implementation of different types of multipliers. All these multipliers are compared for different technologies. A power gating technique is used by placing an MTCMOS cell is used at fine grain level so as to minimize the leakage power.

  13. Low power DCVSL circuits employing AC power supply

    Institute of Scientific and Technical Information of China (English)

    2002-01-01

    In view of changing the type of energy conversion in CMOS circuits, this paper investigates low power CMOS circuit design, which adopts a gradually changing power clock. First, we discuss the algebraic expressions and the corresponding properties of clocked power signals. Then the design procedure is summed up for converting complementary CMOS logic gates employing DC power to the power-clocked CMOS gates employing AC power. On this basis, the design of differential cascode voltage switch logic (DCVSL) circuits employing AC power clocks is proposed. The PSPICE simulations using a sinusoidal power-clock demonstrate that the designed power-clocked DCVSL circuit has a correct logic function and low power characteristics. Finally, an interface circuit to convert clocked signals into the standard logic levels of a CMOS circuit is proposed, and its validity is verified by computer simulations.

  14. Low Power Shoe Integrated Intelligent Wireless Gait Measurement System

    Science.gov (United States)

    Wahab, Y.; Mazalan, M.; Bakar, N. A.; Anuar, A. F.; Zainol, M. Z.; Hamzah, F.

    2014-04-01

    Gait analysis measurement is a method to assess and identify gait events and the measurements of dynamic, motion and pressure parameters involving the lowest part of the body. This significant analysis is widely used in sports, rehabilitation as well as other health diagnostic towards improving the quality of life. This paper presents a new system empowered by Inertia Measurement Unit (IMU), ultrasonic sensors, piezoceramic sensors array, XBee wireless modules and Arduino processing unit. This research focuses on the design and development of a low power ultra-portable shoe integrated wireless intelligent gait measurement using MEMS and recent microelectronic devices for foot clearance, orientation, error correction, gait events and pressure measurement system. It is developed to be cheap, low power, wireless, real time and suitable for real life in-door and out-door environment.

  15. Low Power Photomultiplier Tube Circuit And Method Thereor

    Science.gov (United States)

    Bochenski, Edwin B.; Skinner, Jack L.; Dentinger, Paul M.; Lindblom, Scott C.

    2006-04-18

    An electrical circuit for a photomultiplier tube (PMT) is disclosed that reduces power consumption to a point where the PMT may be powered for extended periods with a battery. More specifically, the invention concerns a PMT circuit comprising a low leakage switch and a high voltage capacitor positioned between a resistive divider and each of the PMT dynodes, and a low power control scheme for recharging the capacitors.

  16. LOW VOLTAGE, LOW POWER CMOS OPERATIONAL AMPLIFIER INPUT STAGE

    OpenAIRE

    GUEN-BOUAZZA, A.; B. BOUAZZA; B. OMARI; CHABANE-SARI, N. E.; C. GONTRAND

    2003-01-01

    The lowering of the power supply and voltage has an enormous impact on the signal to noise ratio (SNR) of analog circuits. The SNR decreases because of the lower allowable signal voltages and also because of higher noise voltages due to low supply currents. To maximise SNR, we have to make the signal as large as possible ideally from rail to rail. Nowedays trend howards low voltage and low power design are mainly driven by the technological limitations of high pe...

  17. Capacity of Fading Channels in the Low Power Regime

    KAUST Repository

    Benkhelifa, Fatma

    2013-01-01

    The low power regime has attracted various researchers in the information theory and communication communities to understand the performance limits of wireless systems. Indeed, the energy consumption is becoming one of the major limiting factors in wireless systems. As such, energy-efficient wireless systems are of major importance to the next generation wireless systems designers. The capacity is a metric that measures the performance limit of a wireless system. The study of the ergodic capacity of some fading channels in the low power regime is the main subject of this thesis. In our study, we consider that the receiver has always a full knowledge of the channel state information. However, we assume that the transmitter has possibly imperfect knowledge of the channel state information, i.e. he knows either perfectly the channel or only an estimated version of the channel. Both radio frequency and free space optical communication channel models are considered. The main contribution of this work is the explicit characterization of how the capacity scales as function of the signal-to-noise ratio in the low power regime. This allows us to characterize the gain due to the perfect knowledge compared to no knowledge of the channel state information at the transmitter. In particular, we show that the gain increases logarithmically for radio frequency communication. However, the gain increases as log2(Pavg) or log4(Pavg) for free-space optical communication, where Pavg is the average power constraint imposed to the input. Furthermore, we characterize the capacity of cascaded fading channels and we applied the result to Rayleigh-product fading channel and to a free-space optical link over gamma-gamma atmospheric turbulence in the presence of pointing errors. Finally, we study the capacity of Nakagami-m fading channel under quality of service constraints, namely the effective capacity. We have shown that the effective capacity converges to Shannon capacity in the very low

  18. A Low Power Low Voltage High Performance CMOS Current Mirror

    OpenAIRE

    Sirish Rao,; Sampath Kumar V

    2015-01-01

    The current mirrors are one of the most important circuits in designing the analog and mixed-mode circuit. A low power and low voltage high-performance CMOS current mirror with optimized input and output resistance are presented in this paper. SPICE simulations confirm the high-performance CMOS current mirror with power supply close to the threshold voltage of the transistor. In this paper, for achieving the low input resistance and a very high output resistance, the combination o...

  19. New low power pulse compressed ionosonde at Gibilmanna Ionospheric Observatory

    OpenAIRE

    G. Tutone; C. Scotto; U. Sciacca; Romano, V.; Pezzopane, M.; Bianchi, C; Baskaradas, J. A.; E. Zuccheretti

    2005-01-01

    A digital low power pulse compressed ionosonde was developed at the Istituto Nazionale di Geofisica e Vulcanologia (INGV), Rome, Italy. The aim of this Advanced Ionospheric Sounder, AIS-INGV, is to reduce the transmitted power and, consequently, weight, size, power consumption and hardware complexity. To compensate the power reduction the most advanced HF radar techniques such as the pulse compression and a phase coherent integration are used. The ionosonde is completely p...

  20.  Ultra Low Power Receiver Frontend for WBAN Applications

    OpenAIRE

    Song, Ying

    2011-01-01

    As integrated circuit technology as well as intelligent computing technology advances, sensor networks which can monitor environments, systems, and complicated interactions in a range of applications are becoming widespread. Wireless Body Area Network(WBAN), which can provide medical, assisted living, sports and entertainment functions for human being, is now enabled and is gradually matching the needs of society. The realization of the WBAN sensor nodes requires ultra-low power wireless comm...

  1. Design of Low Power Successive Approximation Analog to Digital Converter

    OpenAIRE

    Mr. Jitendra A. Waghmare; Prof. P.M. Ghutke

    2014-01-01

    In Biomedical applications such as pacemaker it becomes mandatory to design the circuits with low power and low voltage to enhance the system by means of long sustainability and less power consumption with maintenance free operation, especially in the circuits like Analog to Digital Converters (ADCs). So here is the selection of right architecture is very crucial. Day by day more and more applications are built on the basis of power consumption so SAR ADC will be useful for me...

  2. Flash on disk for low-power multimedia computing

    Science.gov (United States)

    Singleton, Leo; Nathuji, Ripal; Schwan, Karsten

    2007-01-01

    Mobile multimedia computers require large amounts of data storage, yet must consume low power in order to prolong battery life. Solid-state storage offers low power consumption, but its capacity is an order of magnitude smaller than the hard disks needed for high-resolution photos and digital video. In order to create a device with the space of a hard drive, yet the low power consumption of solid-state storage, hardware manufacturers have proposed using flash memory as a write buffer on mobile systems. This paper evaluates the power savings of such an approach and also considers other possible flash allocation algorithms, using both hardware- and software-level flash management. Its contributions also include a set of typical multimedia-rich workloads for mobile systems and power models based upon current disk and flash technology. Based on these workloads, we demonstrate an average power savings of 267 mW (53% of disk power) using hardware-only approaches. Next, we propose another algorithm, termed Energy-efficient Virtual Storage using Application-Level Framing (EVS-ALF), which uses both hardware and software for power management. By collecting information from the applications and using this metadata to perform intelligent flash allocation and prefetching, EVS-ALF achieves an average power savings of 307 mW (61%), another 8% improvement over hardware-only techniques.

  3. Low-power wireless sensor networks for environmental monitoring

    Science.gov (United States)

    Musaloiu-Elefteri, Razvan

    Significant progress has been made in the field of Wireless Sensor Networks in the decade that passed since its inception. This thesis presents several advances intended to make these networks a suitable instrument for environmental monitoring. The thesis first describes Koala, a low-power data-retrieval system that can achieve duty cycles below 1% by using bulk transfers, and Low Power Probing, a novel mechanism to efficiently wake up a network. The second contribution is Serendipity, another data-retrieval system, which takes advantage of the random rendezvous inherent in the Low Power Probing mechanism to achieve a very low duty cycle for low data rate networks. The third part explores the problem of and presents a solution for the interference between WSNs using IEEE 802.15.4 radios and the ubiquitous WiFi networks in the 2.4 GHz spectrum bandwidth. The last contribution of this thesis is Latte, a restricted version of the JavaScript language, that not only can be compiled to C and dynamically loaded on a sensing node, but can also be simulated and debugged in a JavaScript-enabled browser.

  4. Next High Performance and Low Power Flash Memory Package Structure

    Institute of Scientific and Technical Information of China (English)

    Jung-Hoon Lee

    2007-01-01

    In general, SAND flash memory has advantages in low power consumption, storage capacity, and fast erase/write performance in contrast to NOR flash. But, main drawback of the SAND flash memory is the slow access time for random read operations. Therefore, we proposed the new SAND flash memory package for overcoming this major drawback. We present a high performance and low power SAND flash memory system with a dual cache memory. The proposed SAND flash package consists of two parts, i.e., an SAND flash memory module, and a dual cache module. The new SAND flash memory system can achieve dramatically higher performance and lower power consumption compared with any conventional NAND-type flash memory module. Our results show that the proposed system can reduce about 78% of write operations into the flash memory cell and about 70% of read operations from the flash memory cell by using only additional 3KB cache space. This value represents high potential to achieve low power consumption and high performance gain.

  5. An ASIC Low Power Primer Analysis, Techniques and Specification

    CERN Document Server

    Chadha, Rakesh

    2013-01-01

    This book provides an invaluable primer on the techniques utilized in the design of low power digital semiconductor devices.  Readers will benefit from the hands-on approach which starts form the ground-up, explaining with basic examples what power is, how it is measured and how it impacts on the design process of application-specific integrated circuits (ASICs).  The authors use both the Unified Power Format (UPF) and Common Power Format (CPF) to describe in detail the power intent for an ASIC and then guide readers through a variety of architectural and implementation techniques that will help meet the power intent.  From analyzing system power consumption, to techniques that can employed in a low power design, to a detailed description of two alternate standards for capturing the power directives at various phases of the design, this book is filled with information that will give ASIC designers a competitive edge in low-power design. Starts from the ground-up and explains what power is, how it is measur...

  6. Ultra-low power S-Boxes architecture for AES

    Institute of Scientific and Technical Information of China (English)

    XING Ji-peng; ZOU Xue-cheng; GUO Xu

    2008-01-01

    It is crucial to design energy-efficient advancedcncryption standard (AES) cryptography for low power embeddedsystems powered by limited battery. Since the S-Boxes consumemuch of the total AES circuit power, an efficient approach toreducing the AES power consumption consists in reducing theS-Boxes power consumption. Among various implementationsof S-Boxes, the most energy-efficient one is the decoder-switch-encoder (DSE) architecture. In this paper, we refine the DSEarchitecture and propose one faster, more compact S-Boxesarchitecture of lower power: an improved and full-balanced DSEarchitecture. This architecture achieves low power consumptionof 68 μW at 10 MHz using 0.25 μm 1.8V UMC CMOStechnology. Compared with the original DSE S-Boxes, it furtherreduces the delay, gate count and power consumption by 8%,14% and 10% respectively. At the sane time, simulation resultsshow that the improved DSE S-Boxes has the best performanceamong various S-Boxes architectures in terms of power-areaproduct and power-delay product, and it is optimal forimplementing low power AES cryptography.

  7. 47 CFR 74.710 - Digital low power TV and TV translator station protection.

    Science.gov (United States)

    2010-10-01

    ... 47 Telecommunication 4 2010-10-01 2010-10-01 false Digital low power TV and TV translator station... SERVICES Low Power TV, TV Translator, and TV Booster Stations § 74.710 Digital low power TV and TV translator station protection. (a) An application to construct a new low power TV, TV translator, or...

  8. 47 CFR 74.792 - Digital low power TV and TV translator station protected contour.

    Science.gov (United States)

    2010-10-01

    ... 47 Telecommunication 4 2010-10-01 2010-10-01 false Digital low power TV and TV translator station... SERVICES Low Power TV, TV Translator, and TV Booster Stations § 74.792 Digital low power TV and TV translator station protected contour. (a) A digital low power TV or TV translator will be protected...

  9. 47 CFR 74.707 - Low power TV and TV translator station protection.

    Science.gov (United States)

    2010-10-01

    ... 47 Telecommunication 4 2010-10-01 2010-10-01 false Low power TV and TV translator station... SERVICES Low Power TV, TV Translator, and TV Booster Stations § 74.707 Low power TV and TV translator station protection. (a)(1) A low power TV or TV translator will be protected from interference from...

  10. Circuits and Systems for Low-Power Miniaturized Wireless Sensors

    Science.gov (United States)

    Nagaraju, Manohar

    The field of electronic sensors has witnessed a tremendous growth over the last decade particularly with the proliferation of mobile devices. New applications in Internet of Things (IoT), wearable technology, are further expected to fuel the demand for sensors from current numbers in the range of billions to trillions in the next decade. The main challenges for a trillion sensors are continued miniaturization, low-cost and large-scale manufacturing process, and low power consumption. Traditional integration and circuit design techniques in sensor systems are not suitable for applications in smart dust, IoT etc. The first part of this thesis demonstrates an example sensor system for biosignal recording and illustrates the tradeoffs in the design of low-power miniaturized sensors. The different components of the sensor system are integrated at the board level. The second part of the thesis demonstrates fully integrated sensors that enable extreme miniaturization of a sensing system with the sensor element, processing circuitry, a frequency reference for communication and the communication circuitry in a single hermetically sealed die. Design techniques to reduce the power consumption of the sensor interface circuitry at the architecture and circuit level are demonstrated. The principles are used to design sensors for two of the most common physical variables, mass and pressure. A low-power wireless mass and pressure sensor suitable for a wide variety of biological/chemical sensing applications and Tire Pressure Monitoring Systems (TPMS) respectively are demonstrated. Further, the idea of using high-Q resonators for a Voltage Controlled Oscillator (VCO) is proposed and a low-noise, wide bandwidth FBAR-based VCO is presented.

  11. EXPERIMENTAL INVESTIGATION OF AN AIR CHARGED LOW POWERED STIRLING ENGINE

    Directory of Open Access Journals (Sweden)

    Can ÇINAR

    2004-01-01

    Full Text Available In this study, an air charged, low powered manufactured ? type Stirling engine was investigated experimentally. Tests were conducted at 800, 900 and 1000 °C hot source temperatures, 1, 1.5, 2, 2.5, 3, 3.5 bars air charge pressure. The variation of engine power depending on the charge pressure and hot source temperature for two different heat transfer area was investigated experimentally. Maximum output power was obtained at 1000 °C and 3 bars charge pressure as 58 W at 441 rpm. Engine speed was reached at 846 rpm without load.

  12. Low-power Analog VLSI Implementation of Wavelet Transform

    Institute of Scientific and Technical Information of China (English)

    ZHANG Jiang-hong

    2009-01-01

    For applications requiring low-power, low-voltage and real-time, a novel analog VLSI implementation of continuous Marr wavelet transform based on CMOS log-domain integrator is proposed.Mart wavelet is approximated by a parameterized class of function and with Levenbery-Marquardt nonlinear least square method,the optimum parameters of this function are obtained.The circuits of implementating Mart wavelet transform are composed of analog filter whose impulse response is the required wavelet.The filter design is based on IFLF structure with CMOS log-domain integrators as the main building blocks.SPICE simulations indicate an excellent approximations of ideal wavelet.

  13. Ultra-low-power short-range radios

    CERN Document Server

    Chandrakasan, Anantha

    2015-01-01

    This book explores the design of ultra-low-power radio-frequency integrated circuits (RFICs), with communication distances ranging from a few centimeters to a few meters. Such radios have unique challenges compared to longer-range, higher-powered systems. As a result, many different applications are covered, ranging from body-area networks to transcutaneous implant communications and Internet-of-Things devices. A mix of introductory and cutting-edge design techniques and architectures which facilitate each of these applications are discussed in detail. Specifically, this book covers:.

  14. High Speed, Low Power Current Comparators with Hysteresis

    Directory of Open Access Journals (Sweden)

    Neeraj K. Chasta

    2012-02-01

    Full Text Available This paper, presents a novel idea for analog current comparison which compares input signal current and reference currents with high speed, low power and well controlled hysteresis. Proposed circuit is based on current mirror and voltage latching techniques which produces rail to rail output voltage as a result of current comparison. The same design can be extended to a simple current comparator without hysteresis (or very less hysteresis, where comparator gives high accuracy (less than 50nA and speed at the cost of moderate power consumption. The comparators are designed optimally and studied at 180 nm CMOS process technology for a supply voltage of 3V.

  15. A Comparative Study on SOI MOSFETs for Low Power Applications

    Directory of Open Access Journals (Sweden)

    Khairul Affendi Rosli

    2013-03-01

    Full Text Available Silicon on Insulator (SOI technology has become one of the most promising technologies in semiconductor fabrication industry for its numerous advantages. This study presents merits and demerits of different SOIs presented in literatures and a comparative study is done based on several design and performance issues for low power applications. From the study it is found that Fully Depleted SOI MOSFET (FDSOI technology is preferred due to its thin size, reduced leakage current and improved power consumption characteristics etc. compared to those of PDSOI and bulk silicon technology.

  16. USING SUBTHRESHOLD SRAM TO DESIGN LOW-POWER CRYPTO HARDWARE

    Directory of Open Access Journals (Sweden)

    Adnan Abdul-Aziz Gutub

    2011-01-01

    Full Text Available Cryptography and Security hardware architecture designing is in essential need for efficient power utilization which is achieved earlier by giving a range of trade- off between speed and power consumption. This paper presents the initiative of considering subthreshold SRAM memory modules to gain ultra-low-power capable systems. The paper presents improving existing crypto security architectures to reconfigurable domain-specific SRAM memory designs. It is found that reliability is still a problem not solved; however, we start this paper idea to design flexible crypto hardware to gain the performance as well as the reduced power consumption.

  17. High Speed, Low Power Current Comparators with Hysteresis

    Directory of Open Access Journals (Sweden)

    Neeraj K. Chasta

    2012-03-01

    Full Text Available This paper, presents a novel idea for analog current comparison which compares input signal current and reference currents with high speed, low power and well controlled hysteresis. Proposed circuit is based on current mirror and voltage latching techniques which produces rail to rail output voltage as a result of current comparison. The same design can be extended to a simple current comparator without hysteresis (or very less hysteresis, where comparator gives high accuracy (less than 50nA and speed at the cost of moderate power consumption. The comparators are designed optimally and studied at 180nm CMOS process technology for a supply voltage of 3V.

  18. Low-power adaptive filter based on RNS components

    DEFF Research Database (Denmark)

    Bernocchi, Gian Luca; Cardarilli, Gian Carlo; Del Re, Andrea;

    2007-01-01

    least mean squares (LMS) algorithm, is allowed. Previous work showed that the use of the residue number system (RNS) for the variable FIR filter grants advantages both in area and power consumption. On the other hand, the use of a binary serial implementation of the adaptation algorithm eliminates the......In this paper a low-power implementation of an adaptive FIR filter is presented. The filter is designed to meet the constraints of channel equalization for fixed wireless communications that typically requires a large number of taps, but a serial updating of the filter coefficients, based on the...

  19. High Speed, Low Power Current Comparators with Hysteresis

    CERN Document Server

    Chasta, Neeraj K

    2012-01-01

    This paper, presents a novel idea for analog current comparison which compares input signal current and reference currents with high speed, low power and well controlled hysteresis. Proposed circuit is based on current mirror and voltage latching techniques which produces rail to rail output voltage as a result of current comparison. The same design can be extended to a simple current comparator without hysteresis (or very less hysteresis), where comparator gives high accuracy (less than 50nA) and speed at the cost of moderate power consumption. The comparators are designed optimally and studied at 180nm CMOS process technology for a supply voltage of 3V.

  20. Wake-up receiver based ultra-low-power WBAN

    CERN Document Server

    Lont, Maarten; Roermund, Arthur van

    2014-01-01

    This book presents the cross-layer design and optimization of wake-up receivers for wireless body area networks (WBAN), with an emphasis on low-power circuit design. This includes the analysis of medium access control (MAC) protocols, mixer-first receiver design, and implications of receiver impairments on wideband frequency-shift-keying (FSK) receivers. Readers will learn how the overall power consumption is reduced by exploiting the characteristics of body area networks. Theoretical models presented are validated with two different receiver implementations, in 90nm and 40nm CMOS technology.   • Provides an overview of wireless body area network design from the network layer to the circuit implementation, and an overview of the cross-layer design trade-offs; • Discusses design at both the network or MAC-layer and circuit-level, with an emphasis on circuit design; • Covers the design of low-power frequency shift keying (FSK) wake-up-receivers; • Validates theory presented with two different recei...

  1. Low-power portable scanning imaging ladar system

    Science.gov (United States)

    Pyburn, Dana; Leon, Roberto; Haji-Saeed, B.; Sengupta, Sandip K.; Testorf, Markus; Kierstead, John; Khoury, Jehad; Woods, Charles L.; Lorenzo, Joseph

    2003-08-01

    We propose and are in the process of progressively implementing an improved architecture for a laser based system to acquire intensity and range images of hard targets in real-time. The system design emphasizes the use of low power laser sources in conjunction with optical preamplification of target return signals to maintain eye safety without incurring the associated performance penalty. The design leverages advanced fiber optic component technology developed for the commercial market to achieve compactness and low power consumption without the high costs and long lead times associated with custom military devices. All important system parameters are designed to be configured in the field, by the user, in software, allowing for adaptive reconfiguration for different missions and targets. Recently we have started our transition from the initial test bed, using a laser in the visible wavelength, into the final system with a 1550nm diode laser. Currently we are able to acquire and display 3-D false-color and gray-scale images, in the laboratory, at moderate frame rates in real-time. Commercial off-the-shelf data acquisition and signal processing software on a desktop computer equipped with commercial acquisition hardware is utilized. Significant improvements in both range and spatial resolution are expected in the near future.

  2. Optimization of ultra-low-power CMOS transistors

    CERN Document Server

    Stockinger, M

    2000-01-01

    chosen suitable for ultra-low-power purposes. In a first optimization study the drive current of NMOS transistors is maximized while keeping the leakage current below a limit of 1 pA/mu m. This results in peaking channel doping devices (PCD) with narrow doping peaks placed asymmetrically in the channel. Drive current improvements of 45 % and 71 % for the 0.25 mu m and 0.1 mu m devices, respectively, are achieved compared to uniformly doped devices. The PCD device is studied in detail and explanations for its superior drive performance are given. It is compared to already known device structures and practical alternatives are suggested with respect to its manufacturability. In a second optimization study the gate delay times of complete CMOS inverters are minimized. Both the doping profiles of the NMOS and PMOS transistors are optimized at the same time which results again in PCD devices. The inverter speeds are improved by 54 % and 97 % for the 0.25 mu m and 0.1 mu m devices, respectively. Ultra-low-power CMO...

  3. Low power valve actuation using trans-permanent magnetics

    Science.gov (United States)

    Duval, Luis Denit

    The subject of magnetic actuators is very broad, and encompasses a wide range of technologies, magnetic circuit topologies, and performance characteristics for an ever-increasing spectrum of applications. As a consequence of recent advances in soft and hard magnetic materials and developments in power electronics, microprocessors and digital control strategies, and the continuing demand for higher performance motion control systems, there appears to be more research and development activity in magnetic actuators for applications spanning all market sectors than at any time. In this dissertation, a rational approach for switching the states of permanent magnets through an on-board magnetization process is presented. The resulting dynamic systems are referred to as trans-permanent magnetic systems (T-PM). The first part of this research focuses on the governing equations needed for the analysis of T-PM systems. Their feasibility is demonstrated experimentally. In doing so, a method that has the potential of leading to new ultra-low power designs for electromechanical devices is introduced. In the second part of this research, the aforementioned developments in T-PM are applied to the problem of low power valves. Whereas alternate approaches to low power valve control may utilize latching mechanisms to maintain valve position during inactive periods, an approach that eliminates latching mechanisms is presented. Instead, the principles of T-PM are employed to switch the states of permanent magnets; the used of permanent magnets instead of electromagnets eliminates power consumption during inactive periods, thereby reducing power consumption to ultra-low levels. The magnets in a T-PM actuator are configured in a stack. The relationships between the strength and number of magnets in the stack and the stroke and resolution of the actuator are developed. This dissertation reports on the design and testing of a prototype valve actuator that uses a stack pf T-PM with

  4. Low power RF amplifier circuit for ion trap applications

    Science.gov (United States)

    Noriega, J. R.; García-Delgado, L. A.; Gómez-Fuentes, R.; García-Juárez, A.

    2016-09-01

    A low power RF amplifier circuit for ion trap applications is presented and described. The amplifier is based on a class-D half-bridge amplifier with a voltage mirror driver. The RF amplifier is composed of an RF class-D amplifier, an envelope modulator to ramp up the RF voltage during the ion analysis stage, a detector or amplitude demodulation circuit for sensing the output signal amplitude, and a feedback amplifier that linearizes the steady state output of the amplifier. The RF frequency is set by a crystal oscillator and the series resonant circuit is tuned to the oscillator frequency. The resonant circuit components have been chosen, in this case, to operate at 1 MHz. In testings, the class-D stage operated at a maximum of 78 mW at 1.1356 MHz producing 225 V peak.

  5. Characteristics of the XHT-100 Low Power Hall Thruster Prototype

    Science.gov (United States)

    Andrenucci, M.; Berti, M.; Biagioni, L.; Cesari, U.; Saverdi, M.

    2004-10-01

    Several space applications indicate the possibility to adopt Mini Hall Thrusters, with discharge power in the range 50 to 200 W, among existing electric thruster propulsion technologies, to match mission propulsion requirements. A nominally 100W Hall Effect Thruster prototype (with an alumina acceleration chamber diameter slightly larger than 29 mm) has been recently designed and manufactured by Alta and Centrospazio, with the purpose of performing a wide range parametric exploration of the main engineering and physical aspects relevant to these devices at low power. During 2004 a preliminary experimental characterization has been performed in Alta's IV-4 test facility (in Pisa, Italy), a 2 m dia. 4 m length AISI 316 L vacuum chamber, equipped with a set of 6 tailored cryopumping surfaces with a total pumping speed on Xe in the order of 70000 l/s. Additional tests will be performed at ESA- ESTEC Electric Propulsion Laboratory (in the Netherlands).

  6. Pulse swallowing frequency divider with low power and compact structure

    Science.gov (United States)

    Haijun, Gao; Lingling, Sun; Chaobo, Cai; Haiting, Zhan

    2012-11-01

    A pulse swallowing frequency divider with low power and compact structure is presented. One of the DFFs in the divided by 2/3 prescaler is controlled by the modulus control signal, and automatically powered off when it has no contribution to the operation of the prescaler. The DFFs in the program counter and the swallow counter are shared to compose a compact structure, which reduces the power consumption further. The proposed multi-modulus frequency divider was implemented in a standard 65 nm CMOS process with an area of 28 × 22 μm2. The power consumption of the divider is 0.6 mW under 1.2 V supply voltage when operating at 988 MHz.

  7. Low power linear actuator for direct drive electrohydraulic valves

    Institute of Scientific and Technical Information of China (English)

    Yong LI; Fan DING; Jian CUI; Qi-peng LI

    2008-01-01

    This paper presents a bi-directional permanent-magnet linear actuator for directly driving electrohydraulic valves with low power consumption. Its static and dynamic performances were analyzed using the 2D finite element method, taking into account the nonlinear characterization and the eddy current loss of the magnetic material. The experiment and simulation results agree well and show that the prototype actuator can produce a force of+100 N with the maximum power being 7 W and has linear characteristics with a positive magnetic stiffness within a stroke of±1 mm. Its non-linearity is less than 1.5% and the hysteresis less than 1.5%. The actuator's frequency response (-3 dB) of the displacement reaches about 15 Hz, and the most significant factor affecting the dynamic performance is identified as the eddy current loss of the magnetic material.

  8. Low Power Low Voltage Bulk Driven Balanced OTA

    Directory of Open Access Journals (Sweden)

    Neha Gupta

    2012-01-01

    Full Text Available The last few decades, a great deal of attention has been paid to low-voltage (LV low-power (LP integrated circuits design since the power consumption has become a critical issue. Among many techniques used for the design of LV LP analog circuits, the Bulk-driven principle offers a promising route towards this design for many aspects mainly the simplicity and using the conventional MOS technology to implement these designs. This paper is devoted to the Bulk-driven (BD principle and utilizing this principle to design LV LP building block of Operational Transconductance Amplifier (OTA in standard CMOS processes and supply voltage 0.9V. The simulation results have been carried out by the Spice simulatorusing the 130nm CMOS technology from TSMC.

  9. DAC for High Speed and Low Power Applications Using Abacus

    Directory of Open Access Journals (Sweden)

    Shankarayya G. Kambalimath

    2014-02-01

    Full Text Available This paper proposes a Chinese Abacus Digital-to-Ana log Converter (DAC for high speed and low power applications like audio and video applica tions. This circuit of DAC uses resister strings to get a good analog output. The designed D AC uses the algorithm of abacus. Instead of using binary code, here we use abacus code to contr ol the switches. So the complexity and the area will be reduced automatically. The 8-bit D AC is comprised of 12 resistors and 24 NMOS switches. The 8-bit Abacus resistor DAC requires 12 resistors and 24 switches. The 8-bit resistor-string DAC requires 255 resistors and 256 switches. The most important advantages are that the numbers of both resistors and switches are all reduced effectively. The simulation environment uses 1 μ m process technology

  10. Towards Low-Power On-chip Auditory Processing

    Directory of Open Access Journals (Sweden)

    Paul Hasler

    2005-05-01

    Full Text Available Machine perception is a difficult problem both from a practical or implementation point of view as well as from a theoretical or algorithm point of view. Machine perception systems based on biological perception systems show great promise in many areas but they often have processing requirements and/or data flow requirements that are difficult to implement, especially in small or low-power systems. We propose a system design approach that makes it possible to implement complex functionality using cooperative analog-digital signal processing to lower-power requirements dramatically over digital-only systems, as well as provide an architecture facilitating the development of biologically motivated perception systems. We show the architecture and application development approach. We also present several reference systems for speech recognition, noise suppression, and audio classification.

  11. Low Power Low Voltage Bulk Driven Balanced OTA

    CERN Document Server

    Gupta, Neha; Suthar, Meenakshi; Soni, Priyanka

    2012-01-01

    The last few decades, a great deal of attention has been paid to low-voltage (LV) low-power (LP) integrated circuits design since the power consumption has become a critical issue. Among many techniques used for the design of LV LP analog circuits, the Bulk-driven principle offers a promising route towards this design for many aspects mainly the simplicity and using the conventional MOS technology to implement these designs. This paper is devoted to the Bulk-driven (BD) principle and utilizing this principle to design LV LP building block of Operational Transconductance Amplifier (OTA) in standard CMOS processes and supply voltage 0.9V. The simulation results have been carried out by the Spice simulator using the 130nm CMOS technology from TSMC.

  12. Low-Power Architecture for an Optical Life Gas Analyzer

    Science.gov (United States)

    Pilgrim, Jeffrey; Vakhtin, Andrei

    2012-01-01

    Analog and digital electronic control architecture has been combined with an operating methodology for an optical trace gas sensor platform that allows very low power consumption while providing four independent gas measurements in essentially real time, as well as a user interface and digital data storage and output. The implemented design eliminates the cross-talk between the measurement channels while maximizing the sensitivity, selectivity, and dynamic range for each measured gas. The combination provides for battery operation on a simple camcorder battery for as long as eight hours. The custom, compact, rugged, self-contained design specifically targets applications of optical major constituent and trace gas detection for multiple gases using multiple lasers and photodetectors in an integrated package.

  13. Low-Power Design of Ethernet Data Transmission

    Institute of Scientific and Technical Information of China (English)

    Wen-Ming Pan; Qin Zhang; Jia-Feng Chen; Hao-Yuan Wang; Jia-Chong Kan

    2014-01-01

    For the reliability and power consumption issues of Ethernet data transmission based on the field programmable gate array (FPGA), a low-power consumption design method is proposed, which is suitable for FPGA implementation. To reduce the dynamic power consumption of integrated circuit (IC) design, the proposed method adopts the dynamic control of the clock frequency. For most of the time, when the port is in the idle state or lower-rate state, users can reduce or even turn off the reading clock frequency and reduce the clock flip frequency in order to reduce the dynamic power consumption. When the receiving rate is high, the reading clock frequency will be improved timely to ensure that no data will lost. Simulated and verified by Modelsim, the proposed method can dynamically control the clock frequency, including the dynamic switching of high-speed and low-speed clock flip rates, or stop of the clock flip.

  14. AN ADIABATIC APPROACH FOR LOW POWER FULL ADDER DESIGN

    Directory of Open Access Journals (Sweden)

    Prof. Dinesh Chandra

    2011-09-01

    Full Text Available Over the past decade, several adiabatic logic styles have been reported. This paper deals with the design of a 1-bit full adder using several adiabatic logic styles, which are derived from static CMOS logic, without a large change. The full adders are designed using 180nm technology parameters provided by predictive technology and simulated using HSPICE. The full adders designed are compared in terms of average power consumption with different values of load capacitance, temperature and input frequency. The different designs of full adder are also compared on the basis of propagation delay exhibit by them. It is found that, full adders designed with adiabatic logic styles tends to consume very low power in comparison to full adder designed with static CMOS logic. Under certain operating conditions, one of adiabatic designs of full adder achieves upto 74% power saving in comparison to the full adder designedwith static CMOS logic.

  15. Recent advances in flexible low power cholesteric LCDs

    Science.gov (United States)

    Khan, Asad; Shiyanovskaya, Irina; Montbach, Erica; Schneider, Tod; Nicholson, Forrest; Miller, Nick; Marhefka, Duane; Ernst, Todd; Doane, J. W.

    2006-05-01

    Bistable reflective cholesteric displays are a liquid crystal display technology developed to fill a market need for very low power displays. Their unique look, high reflectivity, bistability, and simple structure make them an ideal flat panel display choice for handheld or other portable devices where small lightweight batteries with long lifetimes are important. Applications ranging from low resolution large signs to ultra high resolution electronic books can utilize cholesteric displays to not only benefit from the numerous features, but also create enabling features that other flat panel display technologies cannot. Flexible displays are the focus of attention of numerous research groups and corporations worldwide. Cholesteric displays have been demonstrated to be highly amenable to flexible substrates. This paper will review recent advances in flexible cholesteric displays including both phase separation and emulsification approaches to encapsulation. Both approaches provide unique benefits to various aspects of manufacturability, processes, flexibility, and conformability.

  16. Pulse swallowing frequency divider with low power and compact structure

    Institute of Scientific and Technical Information of China (English)

    Gao Haijun; Sun Lingling; Cai Chaobo; Zhan Haiting

    2012-01-01

    A pulse swallowing frequency divider with low power and compact structure is presented.One of the DFFs in the divided by 2/3 prescaler is controlled by the modulus control signal,and automatically powered off when it has no contribution to the operation of the prescaler.The DFFs in the program counter and the swallow counter are shared to compose a compact structure,which reduces the power consumption further.The proposed multi-modulus frequency divider was implemented in a standard 65 nm CMOS process with an area of 28 ×22 μm2.The power consumption of the divider is 0.6 mW under 1.2 V supply voltage when operating at 988 MHz.

  17. Ultra-Low-Power Hybrid Light-Matter Solitons

    CERN Document Server

    Tinkler, L; Skryabin, D V; Yulin, A; Royall, B; Farrer, I; Ritchie, D A; Krizhanovskii, D N; Skolnick, M S

    2014-01-01

    New functionalities in nonlinear optics will require systems with giant optical nonlinearity as well as compatibility with photonic circuit fabrication techniques. Here we introduce a new platform based on strong light-matter coupling between waveguide photons and quantum-well excitons. On a sub-millimeter length scale we generate sub-picosecond bright temporal solitons at a pulse energy of only 0.5 pico-Joules. From this we deduce an unprecedented nonlinear refractive index 3 orders of magnitude larger than in any other ultrafast system. We study both temporal and spatio-temporal nonlinear effects and for the first time observe dark-bright spatio-temporal solitons. Theoretical modelling of soliton formation in the strongly coupled system confirms the experimental observations. These results show the promise of our system as a high speed, low power, integrated platform for physics and devices based on strong interactions between photons.

  18. Low Power Reversible Parallel Binary Adder/Subtractor

    Directory of Open Access Journals (Sweden)

    Rangaraju H G

    2010-09-01

    Full Text Available In recent years, Reversible Logic is becoming more and more prominent technology having its applications in Low Power CMOS, Quantum Computing, Nanotechnology, and Optical Computing. Reversibility plays an important role when energy efficient computations are considered. In this paper, Reversible eight-bit Parallel Binary Adder/Subtractor with Design I, Design II and Design III are proposed. In all the three design approaches, the full Adder and Subtractors are realized in a single unit as compared to only full Subtractor in the existing design. The performance analysis is verified using number reversible gates, Garbage input/outputs and Quantum Cost. It is observed that Reversible eight-bit Parallel Binary Adder/Subtractor with Design III is efficient compared to Design I, Design II and existing design

  19. Low Power Reversible Parallel Binary Adder/Subtractor

    Directory of Open Access Journals (Sweden)

    Muralidhara K N

    2010-09-01

    Full Text Available In recent years, Reversible Logic is becoming more and more prominent technology having its applications inLow Power CMOS, Quantum Computing, Nanotechnology, and Optical Computing. Reversibility plays animportant role when energy efficient computations are considered. In this paper, Reversible eight-bit ParallelBinary Adder/Subtractor with Design I, Design II and Design III are proposed. In all the three designapproaches, the full Adder and Subtractors are realized in a single unit as compared to only full Subtractorin the existing design. The performance analysis is verified using number reversible gates, Garbageinput/outputs and Quantum Cost. It is observed that Reversible eight-bit Parallel Binary Adder/Subtractorwith Design III is efficient compared to Design I, Design II and existing design

  20. Low-power microfluidic electro-hydraulic pump (EHP).

    Science.gov (United States)

    Lui, Clarissa; Stelick, Scott; Cady, Nathaniel; Batt, Carl

    2010-01-01

    Low-power electrolysis-based microfluidic pumps utilizing the principle of hydraulics, integrated with microfluidic channels in polydimethylsiloxane (PDMS) substrates, are presented. The electro-hydraulic pumps (EHPs), consisting of electrolytic, hydraulic and fluidic chambers, were investigated using two types of electrodes: stainless steel for larger volumes and annealed gold electrodes for smaller-scale devices. Using a hydraulic fluid chamber and a thin flexible PDMS membrane, this novel prototype successfully separates the reagent fluid from the electrolytic fluid, which is particularly important for biological and chemical applications. The hydraulic advantage of the EHP device arises from the precise control of flow rate by changing the electrolytic pressure generated, independent of the volume of the reagent chamber, mimicking the function of a hydraulic press. Since the reservoirs are pre-filled with reagents and sealed prior to testing, external fluid coupling is minimized. The stainless steel electrode EHPs were manufactured with varying chamber volume ratios (1 : 1 to 1 : 3) as a proof-of-concept, and exhibited flow rates of 1.25 to 30 microl/min with electrolysis-based actuation at 2.5 to 10 V(DC). The miniaturized gold electrode EHPs were manufactured with 3 mm diameters and 1 : 1 chamber volume ratios, and produced flow rates of 1.24 to 7.00 microl/min at 2.5 to 10 V(AC), with a higher maximum sustained pressure of 343 KPa, suggesting greater device robustness using methods compatible with microfabrication. The proposed technology is low-cost, low-power and disposable, with a high level of reproducibility, allowing for ease of fabrication and integration into existing microfluidic lab-on-a-chip and analysis systems. PMID:20024053

  1. A low-power SAR ADC for IRFPA ROIC

    Science.gov (United States)

    Gao, Lei; Ding, Ruijun; Zhou, Jie; Wang, Pan; Chen, Guoqiang

    2012-12-01

    This paper presents a low power ADC for the 512*512 infrared focal plane arrays (IRFPA) readout integrated circuit(ROIC). The major structure, the working mode and the simulation result of the readout integrated circuit are shown in this paper. The power supply voltage of 0.35μm standard CMOS process is 3.3V in this design, and then the output range of the Direct Injection (DI) input circuit is reached 2V. Successive-approximation-register (SAR) ADC architecture is used in this readout integrated circuit. And each ADC is shared by one column of the IRFPA. This SAR ADC is made up of a 13-bit digital-analog converter (DAC), a high resolution comparator, and a digital control circuit. The most important part is the voltage-scaling and charge-scaling charge redistribution DAC. In this DAC, charge scaling with a capacitor ladder to determine the least significant bits is combined with voltage scaling with a resister ladder to determine the most significant bits. The comparator uses three-stage operational amplifier structure to get a 77dB differential gain. The Common-Mode input rang of the comparator is 1V to 3V, and minimum resolvable voltage difference is 0.3mV. This SAR ADC has some advantages, especially in low power and high speed. The simulation result shows that the resolution of the ADC is 12 bit and the conversion time of the ADC is 6.5μs, while the power of each ADC is as low as 300μW. Finally, this SAR ADC can satisfy the request of 512*512 IRFPAs ROIC with a 100Hz frame rate.

  2. Low power laser therapy — an introduction and a review of some biological effects

    OpenAIRE

    Thiel, Haymo

    1986-01-01

    This report gives a brief introduction to the characteristics of therapeutic low power laser devices. Absorption, tissue penetration and physiological mechanisms of laser irradiation are discussed. The biological effects of low power laser light are reviewed in the areas of collagen metabolism, woundhealing, inflammation and pain control. Contraindications, precautions and side effects of low power laser irradiation are discussed.

  3. Low power laser therapy in treatment of bronchial asthma

    Directory of Open Access Journals (Sweden)

    Milojević Momir

    2003-01-01

    Full Text Available Introduction Modern concept of acupuncture is based on the fact there are designated locations on the surface of human body, which are related to integrative systems of an organism by means of sensory nerves, correlating and synchronizing organ functioning, depending on external and internal conditions, by means of nervous and neurohumoral regulation of metabolic and regenerative processes, including also mobilization of immunological, protective and antistress reactions. Apart from standard needle acupuncture, other methods of stimulating acupuncture points are also applied. Due to invention of low power lasers, irradiation laser acupuncture has been introduced into routine medical practice, characterized by painless and aseptic technique and outstanding clinical results. Material and methods The investigation was aimed at defining therapeutic effects of low power laser irradiation by stimulating acupuncture points or local treatment of asthma. A prospective analysis included 50 patients treated at the Institute of Pulmonary Diseases in Sremska Kamenica during 2000, 2001 and 2002. Together with conservative treatment of present disease, these patients were treated with laser stimulation of acupuncture points in duration of ten days. During treatment changes of functional respiratory parameters were recorded. Results were compared with those in the control group. The control group consisted of the same number of patients and differed from the examination group only by not using laser stimulation. Results Patients with bronchial asthma presented with significant improvement (p<0,0005 of all estimated lung function parameters just 30 minutes after laser stimulation. Improvements achieved on the third and the tenth day of treatment were significantly higher (p<0,001 to p<0,00005 in the examination group in comparison with the control group. Further investigation confirmed that improvement of measured lung function parameters was significantly

  4. Low power RF measurements of travelling wave type linear accelerator

    International Nuclear Information System (INIS)

    RRCAT is engaged in the development of travelling wave (TW) type linear accelerator for irradiation of industrial and agricultural products. TW accelerator designed for 2π/3 mode to operate at frequency of 2856 MHz. It consists of input coupler, buncher cells, regular cells and output coupler. Low power measurement of this structure includes measurement of resonant frequency of the cells for different resonant modes and quality factor, tuning of input-output coupler and measurement of phase advance per cell and electric field in the structure. Steele's non-resonant perturbation technique has been used for measurement of phase advance per cell and electric field in the structure. Kyhl's method has been used for the tuning of input-output coupler. Computer based automated bead pull set-up has been developed for measurement of phase advance per cell and electric field profile in the structure. All the codes are written in Python for interfacing of Vector Network Analyzer (VNA) , stepper motor with computer. These codes also automate the measurement process. This paper describes the test set- up for measurement and results of measurement of travelling wave type linear accelerating structure. (author)

  5. Low-Power Embedded DSP Core for Communication Systems

    Directory of Open Access Journals (Sweden)

    Tsao Ya-Lan

    2003-01-01

    Full Text Available This paper proposes a parameterized digital signal processor (DSP core for an embedded digital signal processing system designed to achieve demodulation/synchronization with better performance and flexibility. The features of this DSP core include parameterized data path, dual MAC unit, subword MAC, and optional function-specific blocks for accelerating communication system modulation operations. This DSP core also has a low-power structure, which includes the gray-code addressing mode, pipeline sharing, and advanced hardware looping. Users can select the parameters and special functional blocks based on the character of their applications and then generating a DSP core. The DSP core has been implemented via a cell-based design method using a synthesizable Verilog code with TSMC 0.35 m SPQM and 0.25 m 1P5M library. The equivalent gate count of the core area without memory is approximately 50 k. Moreover, the maximum operating frequency of a version is 100 MHz (0.35 m and 140 MHz (0.25 m.

  6. A simplified, low power system for effective vessel sealing

    Science.gov (United States)

    Lyle, Allison B.; Kennedy, Jenifer S.; Schmaltz, Dale F.; Kennedy, Aaron S.

    2015-03-01

    The first bipolar vessel sealing system was developed nearly 15 years ago and has since become standard of care in surgery. These systems make use of radio frequency current that is delivered between bipolar graspers to permanently seal arteries, veins and tissue bundles. Conventional vessel sealing generators are based off traditional electrosurgery generator architecture and deliver high power (150-300 Watts) and high current using complex control and sense algorithms to adjust the output for vessel sealing applications. In recent years, a need for small-scale surgical vessel sealers has developed as surgeons strive to further reduce their footprint on patients. There are many technical challenges associated with miniaturization of vessel sealing devices including maintaining electrical isolation while delivering high current in a saline environment. Research into creating a small, 3mm diameter vessel sealer revealed that a highly simplified generator system could be used to achieve excellent results and subsequently a low power vessel sealing system was developed. This system delivers 25 Watts constant power while limiting voltage ( 360mmHg), but seal times (1.7 +/- 0.7s versus 4.1 +/- 0.7s), thermal spread (<1mm vs <=2mm) and total energy delivery are reduced, when compared to an existing high power system.

  7. ``Low Power Wireless Technologies: An Approach to Medical Applications''

    Science.gov (United States)

    Bellido O., Francisco J.; González R., Miguel; Moreno M., Antonio; de La Cruz F, José Luis

    Wireless communication supposed a great both -quantitative and qualitative, jump in the management of the information, allowing the access and interchange of it without the need of a physical cable connection. The wireless transmission of voice and information has remained in constant evolution, arising new standards like BluetoothTM, WibreeTM or ZigbeeTM developed under the IEEE 802.15 norm. These newest wireless technologies are oriented to systems of communication of short-medium distance and optimized for a low cost and minor consume, becoming recognized as a flexible and reliable medium for data communications across a broad range of applications due to the potential that the wireless networks presents to operate in demanding environments providing clear advantages in cost, size, power, flexibility, and distributed intelligence. About the medical applications, the remote health or telecare (also called eHealth) is getting a bigger place into the manufacturers and medical companies, in order to incorporate products for assisted living and remote monitoring of health parameteres. At this point, the IEEE 1073, Personal Health Devices Working Group, stablish the framework for these kind of applications. Particularly, the 1073.3.X describes the physical and transport layers, where the new ultra low power short range wireless technologies can play a big role, providing solutions that allow the design of products which are particularly appropriate for monitor people’s health with interoperability requirements.

  8. Nanoelectromechanical Switches for Low-Power Digital Computing

    Directory of Open Access Journals (Sweden)

    Alexis Peschot

    2015-08-01

    Full Text Available The need for more energy-efficient solid-state switches beyond complementary metal-oxide-semiconductor (CMOS transistors has become a major concern as the power consumption of electronic integrated circuits (ICs steadily increases with technology scaling. Nano-Electro-Mechanical (NEM relays control current flow by nanometer-scale motion to make or break physical contact between electrodes, and offer advantages over transistors for low-power digital logic applications: virtually zero leakage current for negligible static power consumption; the ability to operate with very small voltage signals for low dynamic power consumption; and robustness against harsh environments such as extreme temperatures. Therefore, NEM logic switches (relays have been investigated by several research groups during the past decade. Circuit simulations calibrated to experimental data indicate that scaled relay technology can overcome the energy-efficiency limit of CMOS technology. This paper reviews recent progress toward this goal, providing an overview of the different relay designs and experimental results achieved by various research groups, as well as of relay-based IC design principles. Remaining challenges for realizing the promise of nano-mechanical computing, and ongoing efforts to address these, are discussed.

  9. Aircraft gas turbine low-power emissions reduction technology program

    Science.gov (United States)

    Dodds, W. J.; Gleason, C. C.; Bahr, D. W.

    1978-01-01

    Advanced aircraft turbine engine combustor technology was used to reduce low-power emissions of carbon monoxide and unburned hydrocarbons to levels significantly lower than those which were achieved with current technology. Three combustor design concepts, which were designated as the hot-wall liner concept, the recuperative-cooled liner concept, and the catalyst converter concept, were evaluated in a series of CF6-50 engine size 40 degree-sector combustor rig tests. Twenty-one configurations were tested at operating conditions spanning the design condition which was an inlet temperature and pressure of 422 K and 304 kPa, a reference velocity of 23 m/s and a fuel-air-ration of 10.5 g/kg. At the design condition typical of aircraft turbine engine ground idle operation, the best configurations of all three concepts met the stringent emission goals which were 10, 1, and 4 g/kg for CO, HC, and Nox, respectively.

  10. High-Resolution Low Power, Intergrated Aftershock and Microzonation System

    Science.gov (United States)

    Zimakov, L.; Passmore, P.

    2012-04-01

    Refraction Technology, Inc. has developed a self-contained, fully integrated Aftershock System, model 160-03, providing the customer simple and quick deployment during aftershock emergency mobilization and microzonation studies. The 160-03 has no external cables or peripheral equipment for command/control and operation in the field. The 160-03 contains three major components integrated in one case: a) 24-bit resolution state-of-the art low power ADC with CPU and Lid interconnect boards; b) power source; and c) three component 2 Hz sensors (two horizontals and one vertical), and built-in ±4g accelerometer. Optionally, the 1 Hz sensors can be built-in the 160-03 system at the customer's request. The self-contained rechargeable battery pack provides power autonomy up to 7 days during data acquisition at 200 sps on continuous three weak motion and triggered three strong motion recording channels. For longer power autonomy, the 160-03 Aftershock System battery pack can be charged from an external source (solar power system). The data in the field is recorded to a built-in swappable USB flash drive. The 160-03 configuration is fixed based on a configuration file stored on the system. The detailed specifications and performance are presented and discussed

  11. Implementation of UART with BIST Technique Using Low Power LFSR

    Directory of Open Access Journals (Sweden)

    Vishalaxi Godi

    2014-07-01

    Full Text Available Asynchronous serial communication is usually implemented by Universal Asynchronous Receiver Transmitter (UART, mostly used for low expense, low speed, short distance data exchange between processor and peripherals. UART allows full duplex serial communication link, and is used in data communication and control system. There is a need for realizing the UART function in a single or a very few chips. Further, design systems without full testability are open to the increased possibility of product failures and missed market opportunities. Also, it is necessary to ensure the data transfer is error proof. This project targets the introduction of Built-in self test (BIST and Status register to UART. The basic idea is to reduce the switching activity among the test patterns at the most. In this approach, the single input change patterns generated by a counter and a gray code generator are Exclusive-ORed with the seed generated by the low power linear feedback shift register [LP-LFSR]. The 8-bit UART with status register and BIST module is coded in Verilog HDL and synthesized and simulated using Xilinx XST and ISim version 14.4 and realized on FPGA.

  12. Low power spatial light modulator with pharaonis phoborhodopsin

    International Nuclear Information System (INIS)

    Spatial light modulation (SLM) has been theoretically analysed in pharaonis phoborhodopsin (ppR) and its mutants based on nonlinear intensity induced excited-state absorption, to achieve large percentage modulation at low power. Amplitude modulation of probe laser read beam (I p') transmissions at 560, 512 and 390 nm, corresponding to the peak absorption of ppRO, ppRKL and ppRM intermediate states, respectively, of ppR photocycle, by write beam intensity (I m') at 498 nm, corresponding to the peak absorption of the initial ppR state, have been analysed using the rate equation approach, considering all six intermediate states in its photocycle. The SLM characteristics are shown to be sensitive to the normalized small signal absorption coefficient (β) and the rate constants of intermediates. For a given I m' range, there is an optimum value of β (β opt) for maximum percentage modulation. We can achieve 100% modulation of the read beam if the initial ppR state does not absorb the respective probe beams. The SLM characteristics of F86D ppR have also been used to design an all-optical XOR logic gate. High dynamic range and sensitivity can be achieved at low write beam intensities in ppR compared to wild-type bacteriorhodopsin (WT-bR)

  13. Low Power Compact Radio Galaxies at High Angular Resolution

    Energy Technology Data Exchange (ETDEWEB)

    Giroletti, Marcello; Giovannini, G.; /Bologna U. /Bologna, Ist. Radioastronomia; Taylor, G.B.; /KIPAC, Menlo Park /NRAO, Socorro

    2005-06-30

    We present sub-arcsecond resolution multi-frequency (8 and 22 GHz) VLA images of five low power compact (LPC) radio sources, and phase referenced VLBA images at 1.6 GHz of their nuclear regions. At the VLA resolution we resolve the structure and identify component positions and flux densities. The phase referenced VLBA data at 1.6 GHz reveals flat-spectrum, compact cores (down to a few milliJansky) in four of the five sources. The absolute astrometry provided by the phase referencing allows us to identify the center of activity on the VLA images. Moreover, these data reveal rich structures, including two-sided jets and secondary components. On the basis of the arcsecond scale structures and of the nuclear properties, we rule out the presence of strong relativistic effects in our LPCs, which must be intrinsically small (deprojected linear sizes {approx}< 10 kpc). Fits of continuous injection models reveal break frequencies in the GHz domain, and ages in the range 10{sup 5}-10{sup 7} yrs. In LPCs, the outermost edge may be advancing more slowly than in more powerful sources or could even be stationary; some LPCs might also have ceased their activity. In general, the properties of LPCs can be related to a number of reasons, including, but not limited to: youth, frustration, low kinematic power jets, and short-lived activity in the radio.

  14. Optimization of Passive Low Power Wireless Electromagnetic Energy Harvesters

    Directory of Open Access Journals (Sweden)

    Dario Grgić

    2012-10-01

    Full Text Available This work presents the optimization of antenna captured low power radio frequency (RF to direct current (DC power converters using Schottky diodes for powering remote wireless sensors. Linearized models using scattering parameters show that an antenna and a matched diode rectifier can be described as a form of coupled resonator with different individual resonator properties. The analytical models show that the maximum voltage gain of the coupled resonators is mainly related to the antenna, diode and load (remote sensor resistances at matched conditions or resonance. The analytical models were verified with experimental results. Different passive wireless RF power harvesters offering high selectivity, broadband response and high voltage sensitivity are presented. Measured results show that with an optimal resistance of antenna and diode, it is possible to achieve high RF to DC voltage sensitivity of 0.5 V and efficiency of 20% at −30 dBm antenna input power. Additionally, a wireless harvester (rectenna is built and tested for receiving range performance.

  15. Compact, Low-power and Precision Timing Photodetector Readout

    Energy Technology Data Exchange (ETDEWEB)

    Varner, Gary S.; Ruckman, Larry L.; /Hawaii U.; Schwiening, Jochen; Vavra, Jaroslav; /SLAC

    2011-06-14

    Photodetector readout for next generation high event rate particle identification and single-photon detection requires a digitizer capable of integrated recording of dense arrays of sensor elements with high analog bandwidth (precision timing) and large record depth, in a cost-effective, compact and low-power way. Simply stated, one cannot do better than having a high-fidelity 'oscilloscope on a chip' for every sensor channel. A firs version of the Buffered Large Analog Bandwidth (BLAB1) ASIC has been designed based upon the lessons learned from the development of the Large Analog Bandwidth Recorder and Digitizer with Ordered Readout (LABRADOR) ASIC. While this LABRADOR ASIC has been very successful and forms the readout basis of a generation of new, large-scale radio neutrino detectors, its limited sampling depth is a major drawback. To address this shortcoming, a prototype intended for photodetector readout has been designed and fabricated with 64k deep sampling at multi-GSa/s operation. An evaluation system has been constructed for instrumentation of Time-Of-Propagation (TOP) and focusing DIRC prototypes and test results will be reported.

  16. FPGA Based Low Power ROM Design Using Capacitance Scaling

    DEFF Research Database (Denmark)

    Bansal, Meenakshi; Bansal, Neha; Saini, Rishita;

    2015-01-01

    An ideal capacitor will not dissipate any power, but a real capacitor wil l have some power dissipation. In this work, we are going to design capacitance scaling based low power ROM design. In order to test the compatibility of this ROM design with latest i7 Processor, we are operating this ROM...... with frequencies (2.9GHz, 3.3GHz, 3.6GHz, 3.8GHz and 4.0GHz) supported by i7 processor.By using different capacitance there comes is reduction in I/O Power and Total power but not in other Powers like Clock, and Leakage (almost negligible). When capacitance goes from 30pF to 5pF, there is a saving of 28.12% occur...... in I/O Power, saving of 0.2% occur in Leakage Power, there will be a saving of 11.54% occur in Total Power. This design is implemented on Virtex-5 FPGA using Xilinx ISE and Verilog....

  17. Low power spatial light modulator with pharaonis phoborhodopsin

    Energy Technology Data Exchange (ETDEWEB)

    Sharma, Parag [Department of Physics and Computer Science, Dayalbagh Educational Institute (Deemed University), Agra 282005 (India); Roy, Sukhdev [Department of Physics and Computer Science, Dayalbagh Educational Institute (Deemed University), Agra 282005 (India)]. E-mail: sukhdevr@hotmail.com; Singh, C.P. [Department of Physics and Computer Science, Dayalbagh Educational Institute (Deemed University), Agra 282005 (India)

    2005-04-22

    Spatial light modulation (SLM) has been theoretically analysed in pharaonis phoborhodopsin (ppR) and its mutants based on nonlinear intensity induced excited-state absorption, to achieve large percentage modulation at low power. Amplitude modulation of probe laser read beam (I {sub p}') transmissions at 560, 512 and 390 nm, corresponding to the peak absorption of ppR{sub O}, ppR{sub KL} and ppR{sub M} intermediate states, respectively, of ppR photocycle, by write beam intensity (I {sub m}') at 498 nm, corresponding to the peak absorption of the initial ppR state, have been analysed using the rate equation approach, considering all six intermediate states in its photocycle. The SLM characteristics are shown to be sensitive to the normalized small signal absorption coefficient ({beta}) and the rate constants of intermediates. For a given I {sub m}' range, there is an optimum value of {beta} ({beta} {sub opt}) for maximum percentage modulation. We can achieve 100% modulation of the read beam if the initial ppR state does not absorb the respective probe beams. The SLM characteristics of F86D ppR have also been used to design an all-optical XOR logic gate. High dynamic range and sensitivity can be achieved at low write beam intensities in ppR compared to wild-type bacteriorhodopsin (WT-bR)

  18. VLSI scaling methods and low power CMOS buffer circuit

    International Nuclear Information System (INIS)

    Device scaling is an important part of the very large scale integration (VLSI) design to boost up the success path of VLSI industry, which results in denser and faster integration of the devices. As technology node moves towards the very deep submicron region, leakage current and circuit reliability become the key issues. Both are increasing with the new technology generation and affecting the performance of the overall logic circuit. The VLSI designers must keep the balance in power dissipation and the circuit's performance with scaling of the devices. In this paper, different scaling methods are studied first. These scaling methods are used to identify the effects of those scaling methods on the power dissipation and propagation delay of the CMOS buffer circuit. For mitigating the power dissipation in scaled devices, we have proposed a reliable leakage reduction low power transmission gate (LPTG) approach and tested it on complementary metal oxide semiconductor (CMOS) buffer circuit. All simulation results are taken on HSPICE tool with Berkeley predictive technology model (BPTM) BSIM4 bulk CMOS files. The LPTG CMOS buffer reduces 95.16% power dissipation with 84.20% improvement in figure of merit at 32 nm technology node. Various process, voltage and temperature variations are analyzed for proving the robustness of the proposed approach. Leakage current uncertainty decreases from 0.91 to 0.43 in the CMOS buffer circuit that causes large circuit reliability. (semiconductor integrated circuits)

  19. A low power pulsed arcjet thruster for spacecraft propulsion

    Science.gov (United States)

    Willmes, Gary Francis

    1997-11-01

    An electrothermal thruster that operates in a pulsed mode at low power (converging-diverging nozzle, and all the energy addition occurs in the subsonic region. Peak currents in the arc are 110 to 270 amps. Pulsed arcjet performance at thermal steady state is measured for two 20 degree half angle conical nozzles with area ratios of 20 and 230. Thrust levels from 10 to 30 mN are measured on an inverted pendulum-type thrust stand, and input power levels from 24 to 119 watts are determined from measurements of pulse rate and breakdown voltage. A maximum specific impulse of 305 seconds is achieved with 38% efficiency. A time-dependent, quasi-1D numerical model is developed to evaluate energy losses in the pulsed arcjet. The numerical model uses a time-marching procedure and the MacCormack predictor-corrector algorithm. Viscous and heat transfer effects are incorporated though a friction factor and an average heat transfer coefficient. A numerical study of nozzle parameters, capillary geometry, wall temperature, and pulse energy shows that the performance is insensitive to capillary and nozzle geometry and that thermal characteristics are the dominant factor affecting performance. The specific impulse and efficiency of the pulsed arcjet are found to be sensitive to wall temperature due to heat transfer losses in the subsonic region. A pulse-forming electrical circuit is developed to reduce energy losses in the storage capacitor, and greater than 85% of the initial stored energy is transferred to the arc in a unipolar pulse. A high current diode installed across the capacitor terminals is used to eliminate voltage reversals in the current. The experimental breakdown voltage of the helium gas between the electrodes is found to follow a Paschen relationship where the minimum electrode separation distance is used in evaluating the data.

  20. Delay-Limited Capacity in the Low Power Regime

    KAUST Repository

    Rezki, Zouheir

    2016-02-11

    Outage performance of the M-block fading with additive white Gaussian noise (BF-AWGN) is investigated in the low-power regime. We consider delay-constrained constant-rate communications with perfect channel state information (CSI) at both the transmitter and the receiver (CSI-TR), under a shortterm power constraint (STPC) and a long-term power constraint (LTPC). Subject to STPC, we show that selection diversity that allocates all the power to the strongest block is asymptotically optimal. Then, we provide a simple characterization of the outage probability in the regime of interest. We quantify the reward due to CSI-TR over the constant-rate constant-power scheme and show that this reward increases with the delay constraint. For instance, for Rayleigh fading, we find that a power gain up to 4.3 dB is achievable. Subject to LTPC, we show that the above guidelines still holds and that the outage performance improves due to the flexibility of the LTPC over the STPC. More interestingly, we prove that LTPC allows zero-outage communication even at low SNR and characterize the delaylimited capacity at low SNR in a simple form. More precisely, we establish that the delay-limited capacity scales linearly with the power constraint, for a given M < 1. Our framework highlights the benefit of fading at low SNR as the delay-limited capacity may outperform the AWGN capacity. For instance, for Rayleigh fading and with M = 3, the delay-limited capacity is 16% higher than the capacity of an AWGN channel.

  1. CMOS Low Power Cell Library for Digital Design

    Directory of Open Access Journals (Sweden)

    Kanika Kaur

    2013-06-01

    Full Text Available Historically, VLSI designers have focused on increasing the speed and reducing the area of digital systems. However, the evolution of portable systems and advanced Deep Sub-Micron fabrication technologies have brought power dissipation as another critical design factor. Low power design reduces cooling cost and increases reliability especially for high density systems. Moreover, it reduces the weight and size of portable devices. The power dissipation in CMOS circuits consists of static and dynamic components. Since dynamic power is proportional to V2 dd and static power is proportional to Vdd, lowering the supply voltage and device dimensions, the transistor threshold voltage also has to be scaled down to achieve the required performance. In case of static power, the power is consumed during the steady state condition i.e when there are no input/output transitions. Static power has two sources: DC power and Leakage power. Consecutively to facilitate voltage scaling without disturbing the performance, threshold voltage has to be minimized. Furthermore it leads to better noise margins and helps to avoid the hot carrier effects in short channel devices. In this paper we have been proposed the new CMOS library for the complex digital design using scaling the supply voltage and device dimensions and also suggest the methods to control the leakage current to obtain the minimum power dissipation at optimum value of supply voltage and transistor threshold. In this paper CMOS Cell library has been implemented using TSMC (0.18um and TSMC (90nm technology using HEP2 tool of IC designing from Mentor Graphics for various analysis and simulations.

  2. An ultra-low-power image compressor for capsule endoscope

    Directory of Open Access Journals (Sweden)

    Weng Ping-Kuo

    2006-02-01

    Full Text Available Abstract Background Gastrointestinal (GI endoscopy has been popularly applied for the diagnosis of diseases of the alimentary canal including Crohn's Disease, Celiac disease and other malabsorption disorders, benign and malignant tumors of the small intestine, vascular disorders and medication related small bowel injury. The wireless capsule endoscope has been successfully utilized to diagnose diseases of the small intestine and alleviate the discomfort and pain of patients. However, the resolution of demosaicked image is still low, and some interesting spots may be unintentionally omitted. Especially, the images will be severely distorted when physicians zoom images in for detailed diagnosis. Increasing resolution may cause significant power consumption in RF transmitter; hence, image compression is necessary for saving the power dissipation of RF transmitter. To overcome this drawback, we have been developing a new capsule endoscope, called GICam. Methods We developed an ultra-low-power image compression processor for capsule endoscope or swallowable imaging capsules. In applications of capsule endoscopy, it is imperative to consider battery life/performance trade-offs. Applying state-of-the-art video compression techniques may significantly reduce the image bit rate by their high compression ratio, but they all require intensive computation and consume much battery power. There are many fast compression algorithms for reducing computation load; however, they may result in distortion of the original image, which is not good for use in the medical care. Thus, this paper will first simplify traditional video compression algorithms and propose a scalable compression architecture. Conclusion As the result, the developed video compressor only costs 31 K gates at 2 frames per second, consumes 14.92 mW, and reduces the video size by 75% at least.

  3. Low Power Design for Future Wearable and Implantable Devices

    Directory of Open Access Journals (Sweden)

    Katrine Lundager

    2016-10-01

    Full Text Available With the fast progress in miniaturization of sensors and advances in micromachinery systems, a gate has been opened to the researchers to develop extremely small wearable/implantable microsystems for different applications. However, these devices are reaching not to a physical limit but a power limit, which is a critical limit for further miniaturization to develop smaller and smarter wearable/implantable devices (WIDs, especially for multi-task continuous computing purposes. Developing smaller and smarter devices with more functionality requires larger batteries, which are currently the main power provider for such devices. However, batteries have a fixed energy density, limited lifetime and chemical side effect plus the fact that the total size of the WID is dominated by the battery size. These issues make the design very challenging or even impossible. A promising solution is to design batteryless WIDs scavenging energy from human or environment including but not limited to temperature variations through thermoelectric generator (TEG devices, body movement through Piezoelectric devices, solar energy through miniature solar cells, radio-frequency (RF harvesting through antenna etc. However, the energy provided by each of these harvesting mechanisms is very limited and thus cannot be used for complex tasks. Therefore, a more comprehensive solution is the use of different harvesting mechanisms on a single platform providing enough energy for more complex tasks without the need of batteries. In addition to this, complex tasks can be done by designing Integrated Circuits (ICs, as the main core and the most power consuming component of any WID, in an extremely low power mode by lowering the supply voltage utilizing low-voltage design techniques. Having the ICs operational at very low voltages, will enable designing battery-less WIDs for complex tasks, which will be discussed in details throughout this paper. In this paper, a path towards battery

  4. Low power interface IC's for electrostatic energy harvesting applications

    Science.gov (United States)

    Kempitiya, Asantha

    interest where the storage capacitor can be optimized to produce almost 70% of the ideal power taken as the power harvested with synchronous converters when neglecting the power consumption associated with synchronizing control circuitry. Theoretical predictions are confirmed by measurements on an asynchronous EHC implemented with a macro-scale electrostatic converter prototype. Based on the preceding analysis, the design of a novel ultra low power electrostatic integrated energy harvesting circuit is proposed for efficient harvesting of mechanical energy. The fundamental challenges of designing reliable low power sensing circuits for charge constrained electrostatic energy harvesters with capacity to self power its controller and driver stages are addressed. Experimental results are presented for a controller design implemented in AMI 0.7muM high voltage CMOS process using a macro-scale electrostatic converter prototype. The EHC produces 1.126muW for a power investment of 417nW with combined conduction and controller losses of 450nW which is a 20-30% improvement compared to prior art on electrostatic EHCs operating under charge constrain. Inherently dual plate variable capacitors harvest energy only during half of the mechanical cycle with the other half unutilized for energy conversion. To harvest mechanical energy over the complete mechanical vibration cycle, a low power energy harvesting circuit (EHC) that performs charge constrained synchronous energy conversion on a tri-plate variable capacitor for maximizing energy conversion is proposed. The tri-plate macro electrostatic generator with capacitor variation of 405pF to 1.15nF and 405pF to 1.07nF on two complementary adjacent capacitors is fabricated and used in the characterization of the designed EHC. The integrated circuit fabricated in AMI 0.7muM high voltage CMOS process, produces a total output power of 497nW to a 10muF reservoir capacitor from a 98Hz vibration signal. In summary, the thesis lays out the

  5. Low power laser irradiation does not affect the generation of signals in a sensory receptor

    Energy Technology Data Exchange (ETDEWEB)

    Lundeberg, T.; Zhou, J.

    1989-01-01

    The effect of low power Helium-Neon (He-Ne) and Gallium-Arsenide (Ga-As) laser on the slowly adapting crustacean stretch receptor was studied. The results showed that low power laser irradiation did not affect the membrane potential of the stretch receptor. These results are discussed in relation to the use of low power laser irradiation on the skin overlaying acupuncture points in treatment of pain syndrome.

  6. Miniaturized Low-Power Piezo Microvalve for NanoSat and CubeSat Propulsion Project

    Data.gov (United States)

    National Aeronautics and Space Administration — In space propulsion applications, an increasingly unmet need is compact, low-power, precision flow regulating valves. Propulsion for increasingly small spacecraft...

  7. Ultra-low power integrated circuit design circuits, systems, and applications

    CERN Document Server

    Li, Dongmei; Wang, Zhihua

    2014-01-01

    This book describes the design of CMOS circuits for ultra-low power consumption including analog, radio frequency (RF), and digital signal processing circuits (DSP). The book addresses issues from circuit and system design to production design, and applies the ultra-low power circuits described to systems for digital hearing aids and capsule endoscope devices. Provides a valuable introduction to ultra-low power circuit design, aimed at practicing design engineers; Describes all key building blocks of ultra-low power circuits, from a systems perspective; Applies circuits and systems described to real product examples such as hearing aids and capsule endoscopes.

  8. 76 FR 81998 - Methodology for Low Power/Shutdown Fire PRA

    Science.gov (United States)

    2011-12-29

    ... COMMISSION Methodology for Low Power/Shutdown Fire PRA AGENCY: Nuclear Regulatory Commission. ACTION: Draft... public comment a draft NUREG/CR, NUREG/CR-7114, Revision 0, ``Methodology for Low Power/Shutdown Fire PRA... quantitative risk analyses of both internal events and fires. The NRC developed this LPSD fire...

  9. 47 CFR 74.785 - Low power TV digital data service pilot project.

    Science.gov (United States)

    2010-10-01

    ... 47 Telecommunication 4 2010-10-01 2010-10-01 false Low power TV digital data service pilot project. 74.785 Section 74.785 Telecommunication FEDERAL COMMUNICATIONS COMMISSION (CONTINUED) BROADCAST RADIO SERVICES EXPERIMENTAL RADIO, AUXILIARY, SPECIAL BROADCAST AND OTHER PROGRAM DISTRIBUTIONAL SERVICES Low Power TV, TV Translator, and TV...

  10. 77 FR 10576 - Methodology for Low Power/Shutdown Fire PRA

    Science.gov (United States)

    2012-02-22

    ... COMMISSION Methodology for Low Power/Shutdown Fire PRA AGENCY: Nuclear Regulatory Commission. ACTION: Draft NUREG/CR; extension for public comment period. SUMMARY: On December 29, 2011 (76 FR 81998), the U.S... Draft NUREG/CR-7114, Revision 0, ``Methodology for Low Power/Shutdown Fire PRA.'' In response to...

  11. 47 CFR 74.795 - Digital low power TV and TV translator transmission system facilities.

    Science.gov (United States)

    2010-10-01

    ... translator transmission system facilities. (a) A digital low power TV or TV translator station shall operate... 47 Telecommunication 4 2010-10-01 2010-10-01 false Digital low power TV and TV translator transmission system facilities. 74.795 Section 74.795 Telecommunication FEDERAL COMMUNICATIONS...

  12. High voltage generator circuit with low power and high efficiency applied in EEPROM

    Institute of Scientific and Technical Information of China (English)

    Liu Yan; Zhang Shilin; Zhao Yiqiang

    2012-01-01

    This paper presents a low power and high efficiency high voltage generator circuit embedded in electrically erasable programmable read-only memory (EEPROM).The low power is minimized by a capacitance divider circuit and a regulator circuit using the controlling clock switch technique.The high efficiency is dependent on the zero threshold voltage (Vth) MOSFET and the charge transfer switch (CTS) charge pump.The proposed high voltage generator circuit has been implemented in a 0.35μm EEPROM CMOS process.Measured results show that the proposed high voltage generator circuit has a low power consumption of about 150.48 μW and a higher pumping efficiency (83.3%) than previously reported circuits.This high voltage generator circuit can also be widely used in low-power flash devices due to its high efficiency and low power dissipation.

  13. High voltage generator circuit with low power and high efficiency applied in EEPROM

    International Nuclear Information System (INIS)

    This paper presents a low power and high efficiency high voltage generator circuit embedded in electrically erasable programmable read-only memory (EEPROM). The low power is minimized by a capacitance divider circuit and a regulator circuit using the controlling clock switch technique. The high efficiency is dependent on the zero threshold voltage (Vth) MOSFET and the charge transfer switch (CTS) charge pump. The proposed high voltage generator circuit has been implemented in a 0.35 μm EEPROM CMOS process. Measured results show that the proposed high voltage generator circuit has a low power consumption of about 150.48 μW and a higher pumping efficiency (83.3%) than previously reported circuits. This high voltage generator circuit can also be widely used in low-power flash devices due to its high efficiency and low power dissipation. (semiconductor integrated circuits)

  14. A Novel Vernier-based Time to Digital Converter for Low-power RFID Sensor Tags

    Directory of Open Access Journals (Sweden)

    Seyed Hossein Shahrokhi

    Full Text Available Power consumption is a key factor in analogue and digital design for portable devices. Radio Frequency Identification (RFID is widely used in industry, military and medical purposes. This technology operates with very low power consumption. Power consump ...

  15. High-Speed, Low-Power ADC for Digital Beam Forming (DBF) Systems Project

    Data.gov (United States)

    National Aeronautics and Space Administration — In Phase 1, Ridgetop Group designed a high-speed, yet low-power silicon germanium (SiGe)-based, analog-to-digital converter (ADC) to be a key element for digital...

  16. Low-Power Ultra-Wideband Radio and Radar Chip Project

    Data.gov (United States)

    National Aeronautics and Space Administration — Prime Research LC (PRLC), Virginia Tech (VT), and the University of Texas at Arlington (UTA) propose to develop an ultra-low power radio/radar based on a CMOS...

  17. Miniaturized, Low Power Cryogenic Inlet System with Sampling Probes for Titan Project

    Data.gov (United States)

    National Aeronautics and Space Administration — Thorleaf Research, Inc. proposes to develop a miniature, low power cryogenic inlet system with sampling probes for Titan. This addresses a key technology gap for...

  18. Miniaturized, Low Power Cryogenic Inlet System with Sampling Probes for Titan Project

    Data.gov (United States)

    National Aeronautics and Space Administration — Thorleaf Research, Inc. has demonstrated feasibility in Phase 1 and now proposes a Phase 2 effort to develop a miniature, low power cryogenic inlet system with...

  19. Ultra-Low Power Extreme Environment Capable Avionics System-on-a-Chip Project

    Data.gov (United States)

    National Aeronautics and Space Administration — Develop ultra-low-power, wide-temperature (-150° C to +250 ° C), digital System-on-a-Chip (SOC) ASIC technology in a high resolution, inherently rad-hard...

  20. Shutdown and low-power operation at commercial nuclear power plants in the United States

    International Nuclear Information System (INIS)

    The report contains the results of the NRC Staff's evaluation of shutdown and low-power operations at US commercial nuclear power plants. The report describes studies conducted by the staff in the following areas: Operating experience related to shutdown and low-power operations, probabilistic risk assessment of shutdown and low-power conditions and utility programs for planning and conducting activities during periods the plant is shut down. The report also documents evaluations of a number of technical issues regarding shutdown and low-power operations performed by the staff, including the principal findings and conclusions. Potential new regulatory requirements are discussed, as well as potential changes in NRC programs. A draft report was issued for comment in February 1992. This report is the final version and includes the responses to the comments along with the staff regulatory analysis of potential new requirements

  1. High-Speed, Low-Power ADC for Digital Beam Forming (DBF) Systems Project

    Data.gov (United States)

    National Aeronautics and Space Administration — Ridgetop Group will design a high-speed, low-power silicon germanium (SiGe)-based, analog-to-digital converter (ADC) to be a key element for digital beam forming...

  2. Low Power WiFi: a study on power consumption for Internet of Things

    OpenAIRE

    Amozarrain Perez, Ugaitz

    2015-01-01

    An analysis of a Low-Power WiFi devices and the feasibility of using such a device for Internet of Things applications, for wireless sensor networks more specifically. The device is analyzed in power consumption and performance.

  3. Design of Ultra-Low Power Wake-Up Receiver in 130nm CMOS Technology

    OpenAIRE

    Gebreyohannes, Fikre Tsigabu

    2012-01-01

    Wireless Sensor Networks have found diverse applications from health to agriculture and industry. They have a potential to profound social changes, however, there are also some challenges that have to be addressed. One of the problems is the limited power source available to energize a sensor node. Longevity of a node is tied to its low power design. One of the areas where great power savings could be made is in nodal communication. Different schemes have been proposed targeting low power com...

  4. Synthesis of mesoporous MCM-41 materials with low-power microwave heating

    OpenAIRE

    Ergün, Aslı; Ergun, Asli; Kocabaş, Özlem Züleyha; Kocabas, Ozlem Zuleyha; BAYSAL, Mustafa; Yürüm, Alp; Yurum, Alp; YÜRÜM, YUDA; Yurum, Yuda

    2013-01-01

    Crystalline, high-surface-area, hexagonal mesoporous MCM-41 having uniform pore sizes and good thermal stability was successfully synthesized at 90 degrees 120 degrees C in 30min using low-power microwave irradiation. This appears to be the first comprehensive and quantitative investigation of the comparatively rapid synthesis of mesoporous MCM-41 using low-power microwave heating of 80W (90 degrees C) and 120W (120 degrees C). The influence of reaction temperature and the duration of heating...

  5. Analog IC techniques for low-voltage low-power electronics

    OpenAIRE

    Serdijn, W. A.; Verhoeven, C.J.M.; Van Roermund, A.H.M.

    1995-01-01

    Analog IC Techniques lor Low-Voltage Low Power Electronics addresses many very important, but recent, techniques which enable electronics to operate at a low supply voltage and consume a minimum amount of power. Apart from investigations at the device, circuit and system levels, the book provides a wealth of practical implementations, many worked out in silicon realizations. The book is intended for both the professional designer of low-voltage low-power analog integrated circuits and the gra...

  6. Review of the status of low power research reactors and considerations for its development

    Energy Technology Data Exchange (ETDEWEB)

    Lim, In Cheol; Wu, Sang Ik; Lee, Byung Chul; Ha, Jae Joo [KAERI, Daejeon (Korea, Republic of)

    2012-10-15

    At present, 232 research reactors in the world are in operation and two thirds of them have a power less than 1 MW. Many countries have used research reactors as the tools for educating and training students or engineers and for scientific service such as neutron activation analysis. As the introduction of a research reactor is considered a stepping stone for a nuclear power development program, many newcomers are considering having a low power research reactor. The IAEA has continued to provide forums for the exchange of information and experiences regarding low power research reactors. Considering these, the Agency is recently working on the preparation of a guide for the preparation of technical specification possibly for a member state to use when wanting to purchase a low power research reactor. In addition, ANS has stated that special consideration should be given to the continued national support to maintain and expand research and test reactor programs and to the efforts in identifying and addressing the future needs by working toward the development and deployment of next generation nuclear research and training facilities. Thus, more interest will be given to low power research reactors and its role as a facility for education and training. Considering these, the status of low power research reactors was reviewed, and some aspects to be considered in developing a low power research reactor were studied.

  7. 47 CFR 74.793 - Digital low power TV and TV translator station protection of broadcast stations.

    Science.gov (United States)

    2010-10-01

    ... 47 Telecommunication 4 2010-10-01 2010-10-01 false Digital low power TV and TV translator station... DISTRIBUTIONAL SERVICES Low Power TV, TV Translator, and TV Booster Stations § 74.793 Digital low power TV and TV translator station protection of broadcast stations. (a) An application to construct a new digital low...

  8. Charge-based particle separation in microfluidic devices using combined hydrodynamic and electrokinetic effects

    NARCIS (Netherlands)

    Jellema, L. C.; Mey, T.; Koster, S.; Verpoorte, E.

    2009-01-01

    A new microfluidic approach for charge-based particle separation using combined hydrodynamic and electrokinetic effects is presented. A recirculating flow pattern is employed, generated through application of bi-directional flow in a narrow glass microchannel incorporating diverging or converging se

  9. Two-phase low-power analogue CMOS peak detector with high dynamic range

    Science.gov (United States)

    Malankin, E.

    2016-02-01

    A low-power two-phase peak detector with wide dynamic range was developed. The PD was designed on the basis ofthe CMOS UMC 180 nm process. This block is considered as a part of the read-out electronics of the CBM experiment at upcoming FAIR accelerator (Germany). Peak detector has the following advantages: wide dynamic range of 5 - 1000 mV, low power consumption of 500 µW. The designed PD meets the requirements to the muon chamber read-out electronics of the CBM experiment. Due to the area efficiency (100×90 μm2) and low power consumption it can be used in different applications for high-energy physics read-out electronics.

  10. Low Power Design with High-Level Power Estimation and Power-Aware Synthesis

    CERN Document Server

    Ahuja, Sumit; Shukla, Sandeep Kumar

    2012-01-01

    Low-power ASIC/FPGA based designs are important due to the need for extended battery life, reduced form factor, and lower packaging and cooling costs for electronic devices. These products require fast turnaround time because of the increasing demand for handheld electronic devices such as cell-phones, PDAs and high performance machines for data centers. To achieve short time to market, design flows must facilitate a much shortened time-to-product requirement. High-level modeling, architectural exploration and direct synthesis of design from high level description enable this design process. This book presents novel research techniques, algorithms,methodologies and experimental results for high level power estimation and power aware high-level synthesis. Readers will learn to apply such techniques to enable design flows resulting in shorter time to market and successful low power ASIC/FPGA design. Integrates power estimation and reduction for high level synthesis, with low-power, high-level design; Shows spec...

  11. Design of Low Power Multiplier with Energy Efficient Full Adder Using DPTAAL

    Directory of Open Access Journals (Sweden)

    A. Kishore Kumar

    2013-01-01

    Full Text Available Asynchronous adiabatic logic (AAL is a novel lowpower design technique which combines the energy saving benefits of asynchronous systems with adiabatic benefits. In this paper, energy efficient full adder using double pass transistor with asynchronous adiabatic logic (DPTAAL is used to design a low power multiplier. Asynchronous adiabatic circuits are very low power circuits to preserve energy for reuse, which reduces the amount of energy drawn directly from the power supply. In this work, an 8×8 multiplier using DPTAAL is designed and simulated, which exhibits low power and reliable logical operations. To improve the circuit performance at reduced voltage level, double pass transistor logic (DPL is introduced. The power results of the proposed multiplier design are compared with the conventional CMOS implementation. Simulation results show significant improvement in power for clock rates ranging from 100 MHz to 300 MHz.

  12. An ECG Compressed Sensing Method of Low Power Body Area Network

    Directory of Open Access Journals (Sweden)

    Jizhong Liu

    2013-07-01

    Full Text Available Aimed at low power problem in body area network, an ECG compressed sensing method of low power body area network based on the compressed sensing theory was proposed. Random binary matrices were used as the sensing matrix to measure ECG signals on the sensor nodes. After measured value is transmitted to remote monitoring center, ECG signal sparse representation under the discrete cosine transform and block sparse Bayesian learning reconstruction algorithm is used to reconstruct the ECG signals. The simulation results show that the 30% of overall signal can get reconstruction signal which’s SNR is more than 60dB, each numbers in each rank of sensing matrix can be controlled below 5, which reduces the power of sensor node sampling, calculation and transmission. The method has the advantages of low power, high accuracy of signal reconstruction and easy to hardware implementation.  

  13. Design and implementation of a DSP with multi-level low power strategies for cochlear implants

    Institute of Scientific and Technical Information of China (English)

    Mai Songping; Zhang Chun; Chao Jun; Wang Zhihua

    2009-01-01

    This paper presents the design and implementation of a low power digital signal processor (THUCIDSP-1) targeting at application for cochlear implants. Multi-level low power strategies including algorithm optimization, operand isolation, clock gating and memory partitioning are adopted in the processor design to reduce the power consumption. Experimental results show that the complexity of the Continuous Interleaved Sampling (CIS) algorithm is reduced by more than 80% and the power dissipation of the hardware alone is reduced by about 25% with the low power methods. The THUCIDSP-1 prototype, fabricated in 0.18-μm standard CMOS process, consumes only 1.91 mW when executing the CIS algorithm at 3 MHz.

  14. A Novel Photodiode for Reflectance Pulse Oximetry in low-power applications

    DEFF Research Database (Denmark)

    Haahr, Rasmus Grønbek; Duun, Sune; Birkelund, Karen;

    2007-01-01

    The amount of light collected is crucial for low-power applications of pulse oximetry. In this work a novel ring-shaped backside photodiode has been developed for a wearable reflectance pulse oximeter. The photodiode is proven to work with a dual LED with wavelengths of 660 nm and 940 nm. For the......The amount of light collected is crucial for low-power applications of pulse oximetry. In this work a novel ring-shaped backside photodiode has been developed for a wearable reflectance pulse oximeter. The photodiode is proven to work with a dual LED with wavelengths of 660 nm and 940 nm...

  15. Ultra-Low Power Input Driver for High-ResolutionDiscrete-Time Σ∆ Modulator

    OpenAIRE

    Zhang, Yumiao

    2013-01-01

    This thesis presents the design of an input driver for ultra-low power sigmadelta modulator. High resolution Σ∆ ADCs are becoming more and more usefulin ultra-low power medical applications. Therefore, reducing supply voltage andpower starts a new chanllenges both at architecture as well as circuit performancelevel. Three input drivers are presented in this thesis making use of operationalamplifiers with the class AB buffers as output stage.In the thesis, the building blocks of the input buffer ...

  16. Semidigital PLL Design for Low-Cost Low-Power Clock Generation

    Directory of Open Access Journals (Sweden)

    Ni Xu

    2011-01-01

    Full Text Available This paper describes recent semidigital architectures of the phase-locked loop (PLL systems for low-cost low-power clock generation. With the absence of the time-to-digital converter (TDC, the semi-digital PLL (SDPLL enables low-power linear phase detection and does not necessarily require advanced CMOS technology while maintaining a technology scalability feature. Two design examples in 0.18 μm CMOS and 65 nm CMOS are presented with hardware and simulation results, respectively.

  17. A Low Power down Conversion CMOS Gilbert Mixer for Wireless Communications

    Directory of Open Access Journals (Sweden)

    Manoj Kumar Pandram,

    2014-07-01

    Full Text Available In this paper a design of low power 2.4GHz (RF down conversion Gilbert Cell mixer, implemented in 0.18μm CMOS technology with 1.8V supply voltage is presented. The obtained result shows a conversion gain equal to 6.7dB and third order Input intercept point -1db, power consumption of 3.86mW at 1.8V supply voltage. The 50Ω matched impedance condition is applicable. Result shows a good potential of this CMOS mixer and justify its use for low-power wireless communications.

  18. A low power, on demand electrothermal valve for wireless drug delivery applications.

    Science.gov (United States)

    Li, Po-Ying; Givrad, Tina K; Sheybani, Roya; Holschneider, Daniel P; Maarek, Jean-Michel I; Meng, Ellis

    2010-01-01

    We present a low power, on demand Parylene MEMS electrothermal valve. A novel Omega-shaped thermal resistive element requires low power (approximately mW) and enables rapid valve opening (approximately ms). Using both finite element analysis and valve opening experiments, a robust resistive element design for improved valve opening performance in water was obtained. In addition, a thermistor, as an inrush current limiter, was added into the valve circuit to provide variable current ramping. Wireless activation of the valve using RF inductive power transfer was demonstrated.

  19. An ultra-low-power CMOS temperature sensor for RFID applications

    Institute of Scientific and Technical Information of China (English)

    Xu Conghui; Gao Peijun; Che Wenyi; Tan Xi; Yan Na; Min Hao

    2009-01-01

    An ultra-low-power CMOS temperature sensor with analog-to-digital readout circuitry for RFID applications was implemented in a 0.18-μm CMOS process.To achieve ultra-low power consumption,an error model is proposed and the corresponding novel temperature sensor front-end with a new double-measure method is presented.Analog-to-digital conversion is accomplished by a sigma-delta converter.The complete system consumes only 26μA@1.8 V for continuous operation and achieves an accuracy of±0.65℃ from-20 to 120℃ after calibration at one temperature.

  20. A High performance and low power hardware architecture for H.264 cavlc algorithm

    OpenAIRE

    Şahin, Esra; Esra SAHIN; Hamzaoğlu, İlker; Hamzaoglu, Ilker

    2005-01-01

    In this paper, we present a high performance and low power hard-ware architecture for real-time implementation of Context Adap-tive Variable Length Coding (CAVLC) algorithm used in H.264 / MPEG4 Part 10 video coding standard. This hardware is designed to be used as part of a complete low power H.264 video coding system for portable applications. The proposed architecture is im-plemented in Verilog HDL. The Verilog RTL code is verified to work at 76 MHz in a Xilinx Virtex II FPGA and it is ver...

  1. Optimizing efficiency on conventional transformer based low power AC/DC standby power supplies

    DEFF Research Database (Denmark)

    Nielsen, Nils

    2004-01-01

    This article describes the research results for simple and cheap methods to reduce the idle- and load-losses in very low power conventional transformer based power supplies intended for standby usage. In this case "very low power" means 50 Hz/230 V-AC to 5 V-DC@1 W. The efficiency is measured...... on two common power supply topologies designed for this power level. The two described topologies uses either a series (or linear) or a buck regulation approach. Common to the test power supplies is they either are using a standard cheap off-the-shelf transformer, or one, which are loss optimized by very...

  2. Low cost low power 24 GHz FMCW radar transceiver for indoor presence detection

    NARCIS (Netherlands)

    Suijker, E.M.; Bolt, R.J.; Wanum, M. van; Heijningen, M. van; Maas, A.P.M.; Vliet, F.E. van

    2014-01-01

    In this paper a first time right 24 GHz FMCW radar transceiver is presented. The MMIC has a low power consumption of 86 mW and an output power of -10 dBm. Due to the integrated IF amplifier, the conversion gain of the receiver is 51 dB and the base band signals are directly processed with an ADC. Th

  3. An ultra low-voltage, low-power baseband-processor for UHF RFID tag

    Institute of Scientific and Technical Information of China (English)

    Yan HE; Jianyun HU; Hao MIN

    2008-01-01

    A novel ultra low-voltage, low-power baseband-processor for UHF radio frequency identification (RFID) tag is presented here. The baseband-processor is compa-tible with the EPCTM class-1 generation-2 (C1G2) UHF RFID protocol, and fits the requirements of ultra low-power of passive tags. Based on the analysis of the special power consumption of the tag, a new architecture is proposed. A novel scheme for generating pseudo-random numbers as well as a new method of partial-decoding is developed. Besides, other low-power techniques are also adopted for the special baseband-processor which imple-ments complex functions, such as encoding/coding, anti-collision and authorization scheme, and reading/writing operation to EEPROM. The chip was fabricated in 0.35 μm 1P3M standard CMOS process. Experimental results show that it achieves low power operation of 3.15 μW @ 1.5 V with the core area of 1.1 mm× 0.8 mm.

  4. Thermal simulation of surface micromachined polysilicon hot plates of low power consumption

    NARCIS (Netherlands)

    Dumitrescu, Marius; Cobianu, Cornel; Lungu, Dan; Pascu, Adrian; Kolev, Spas; Berg, van den Albert

    1999-01-01

    A simple, IC compatible, surface micromachined polysilicon membrane was technologically designed and thermally simulated by 3D finite element ‘COSMOS' program in order to investigate its capability to work as a micro hot plate for a gas sensing test structure of low power consumption. For an optimiz

  5. Single-Phase Hybrid Switched Reluctance Motor for Low-Power Low-Cost Applications

    DEFF Research Database (Denmark)

    Lu, Kaiyuan; Rasmussen, Peter Omand; Jakobsen, Uffe

    2011-01-01

    This paper presents a new single-phase, Hybrid Switched Reluctance (HSR) motor for low-cost, low-power, pump or fan drive systems. Its single-phase configuration allows use of a simple converter to reduce the system cost. Cheap ferrite magnets are used and arranged in a special flux concentration...

  6. Achievable rate of spectrum sharing cognitive radio systems over fading channels at low-power regime

    KAUST Repository

    Sboui, Lokman

    2014-11-01

    We study the achievable rate of cognitive radio (CR) spectrum sharing systems at the low-power regime for general fading channels and then for Nakagami fading. We formally define the low-power regime and present the corresponding closed-form expressions of the achievable rate lower bound under various types of interference and/or power constraints, depending on the available channel state information of the cross link (CL) between the secondary-user transmitter and the primary-user receiver. We explicitly characterize two regimes where either the interference constraint or the power constraint dictates the optimal power profile. Our framework also highlights the effects of different fading parameters on the secondary link (SL) ergodic achievable rate. We also study more realistic scenarios when there is either 1-bit quantized channel feedback from the CL alone or 2-bit feedback from both the CL and the SL and propose simple power control schemes and show that these schemes achieve the previously achieved rate at the low-power regime. Interestingly, we show that the low-power regime analysis provides a specific insight into the maximum achievable rate behavior of CR that has not been reported by previous studies.

  7. A low-power asynchronous data-path for a FIR filter bank

    DEFF Research Database (Denmark)

    Nielsen, Lars Skovby; Sparsø, Jens

    1996-01-01

    This paper describes a number of design issues relating to the implementation of low-power asynchronous signal processing circuits. Specifically, the paper addresses the design of a dedicated processor structure that implements an audio FIR filter bank which is part of an industrial application...

  8. Ultra low-power biomedical signal processing: an analog wavelet filter approach for pacemakers

    NARCIS (Netherlands)

    Pavlík Haddad, S.A.

    2006-01-01

    The purpose of this thesis is to describe novel signal processing methodologies and analog integrated circuit techniques for low-power biomedical systems. Physiological signals, such as the electrocardiogram (ECG), the electroencephalogram (EEG) and the electromyogram (EMG) are mostly non-stationary

  9. CMOS instrumentation amplifier with offset cancellation circuitry and high PSRR for low power application

    International Nuclear Information System (INIS)

    This paper presents the design and development of a CMOS instrumentation amplifier for biomedical application. The instrumentation amplifier possesses a very high power-supply rejection ratio (PSRR) and is able to operate at single supply voltage for low power application with improved performance compared to existing work. It also has a full CMOS implementation of offset cancellation circuitry. (author)

  10. Low-power laser therapy for carpal tunnel syndrome: effective optical power.

    Science.gov (United States)

    Chen, Yan; Zhao, Cheng-Qiang; Ye, Gang; Liu, Can-Dong; Xu, Wen-Dong

    2016-07-01

    Low-power laser therapy has been used for the non-surgical treatment of mild to moderate carpal tunnel syndrome, although its efficacy has been a long-standing controversy. The laser parameters in low-power laser therapy are closely related to the laser effect on human tissue. To evaluate the efficacy of low-power laser therapy, laser parameters should be accurately measured and controlled, which has been ignored in previous clinical trials. Here, we report the measurement of the effective optical power of low-power laser therapy for carpal tunnel syndrome. By monitoring the backside reflection and scattering laser power from human skin at the wrist, the effective laser power can be inferred. Using clinical measurements from 30 cases, we found that the effective laser power differed significantly among cases, with the measured laser reflection coefficient ranging from 1.8% to 54%. The reflection coefficient for 36.7% of these 30 cases was in the range of 10-20%, but for 16.7% of cases, it was higher than 40%. Consequently, monitoring the effective optical power during laser irradiation is necessary for the laser therapy of carpal tunnel syndrome. PMID:27630706

  11. Loss optimizing low power 50 Hz transformers intended for AC/DC standby power supplies

    DEFF Research Database (Denmark)

    Nielsen, Nils

    2004-01-01

    This paper presents the measured efficiency on selected low power conventional 50 Hz/230 V-AC transformers. The small transformers are intended for use in 1 W@5 V-DC series- or buck-regulated power supplies for standby purposes. The measured efficiency is compared for cheap off-the-self transformer...

  12. Prophylaxis and treatment of acute radiation ulcers in rats with low-power infrared laser radiation

    Science.gov (United States)

    Kursova, Larisa V.; Kaplan, Michael A.; Nikitina, Rosa G.; Maligina, Antonina I.

    1999-12-01

    Exposure of radiation ulcers in rats to low-power infrared laser radiation (LPLR) (wavelength--890 nm, pulse power--6 W, frequency--150 and 300 Hz, irradiation time--10 min) noticeably accelerates their healing, reduces exudative processes, increases number of specialized cells in wound. Application of LPLR prior to radiation damage decreases ulcer dimensions.

  13. Design of nodes for embedded and ultra low-power wireless sensor networks

    Science.gov (United States)

    Xu, Jun; You, Bo; Cui, Juan; Ma, Jing; Li, Xin

    2008-10-01

    Sensor network integrates sensor technology, MEMS (Micro-Electro-Mechanical system) technology, embedded computing, wireless communication technology and distributed information management technology. It is of great value to use it where human is quite difficult to reach. Power consumption and size are the most important consideration when nodes are designed for distributed WSN (wireless sensor networks). Consequently, it is of great importance to decrease the size of a node, reduce its power consumption and extend its life in network. WSN nodes have been designed using JN5121-Z01-M01 module produced by jennic company and IEEE 802.15.4/ZigBee technology. Its new features include support for CPU sleep modes and a long-term ultra low power sleep mode for the entire node. In low power configuration the node resembles existing small low power nodes. An embedded temperature sensor node has been developed to verify and explore our architecture. The experiment results indicate that the WSN has the characteristic of high reliability, good stability and ultra low power consumption.

  14. 76 FR 72849 - Digital Low Power Television, Television Translator, and Television Booster Stations and To Amend...

    Science.gov (United States)

    2011-11-28

    ... amendments to 47 CFR 73.624(g), published at 76 FR 44821, July 27, 2011, are effective on November 28, 2011... FR 44821, July 27, 2011. Synopsis As required by the Paperwork Reduction Act of 1995, (44 U.S.C. 3507... COMMISSION 47 CFR Parts 73 and 74 Digital Low Power Television, Television Translator, and Television...

  15. 76 FR 11680 - Digital Low Power Television, Television Translator, and Television Booster Stations and Digital...

    Science.gov (United States)

    2011-03-03

    ... Docket No. 03-185, FCC 04-220, 69 FR 69325, November 29, 2004. Synopsis As required by the Paperwork... COMMISSION 47 CFR Parts 73 and 74 Digital Low Power Television, Television Translator, and Television Booster Stations and Digital Class A Television Stations AGENCY: Federal Communications Commission. ACTION:...

  16. 47 CFR 73.3521 - Mutually exclusive applications for low power television, television translators and television...

    Science.gov (United States)

    2010-10-01

    ... television, television translators and television booster stations. 73.3521 Section 73.3521 Telecommunication... Applicable to All Broadcast Stations § 73.3521 Mutually exclusive applications for low power television, television translators and television booster stations. When there is a pending application for a new...

  17. Analog IC techniques for low-voltage low-power electronics

    NARCIS (Netherlands)

    Serdijn, W.A.; Verhoeven, C.J.M.; Van Roermund, A.H.M.

    1995-01-01

    Analog IC Techniques lor Low-Voltage Low Power Electronics addresses many very important, but recent, techniques which enable electronics to operate at a low supply voltage and consume a minimum amount of power. Apart from investigations at the device, circuit and system levels, the book provides a

  18. Nano-Link Based Ultra Low Power Micro Electronic Hotplates for Sensors and Actuators

    NARCIS (Netherlands)

    Groenland, A.W.; Kovalgin, A.Y.; Schmitz, J.; Wolters, R.A.M.

    2011-01-01

    Ultra low-power electrical hotplates are presented based on Ohmic heating of a small conductive volume (link) sandwiched between two electrodes. The link is fabricated by etching a hole in the dielectric layer between the electrodes and subsequently filling it with TiN deposited via ALD. This result

  19. Low-power laser therapy for carpal tunnel syndrome:effective optical power

    Institute of Scientific and Technical Information of China (English)

    Yan Chen; Cheng-qiang Zhao; Gang Ye; Can-dong Liu; Wen-dong Xu

    2016-01-01

    Low-power laser therapy has been used for the non-surgical treatment of mild to moderate carpal tunnel syndrome, although its efifca-cy has been a long-standing controversy. The laser parameters in low-power laser therapy are closely related to the laser effect on human tissue. To evaluate the efifcacy of low-power laser therapy, laser parameters should be accurately measured and controlled, which has been ignored in previous clinical trials. Here, we report the measurement of the effective optical power of low-power laser therapy for carpal tunnel syndrome. By monitoring the backside relfection and scattering laser power from human skin at the wrist, the effective laser power can be inferred. Using clinical measurements from 30 cases, we found that the effective laser power differed signiifcantly among cases, with the measured laser relfection coefifcient ranging from 1.8%to 54%. The relfection coefifcient for 36.7%of these 30 cases was in the range of 10–20%, but for 16.7%of cases, it was higher than 40%. Consequently, monitoring the effective optical power during laser irradiation is necessary for the laser therapy of carpal tunnel syndrome.

  20. A low power biomedical signal processor ASIC based on hardware software codesign.

    Science.gov (United States)

    Nie, Z D; Wang, L; Chen, W G; Zhang, T; Zhang, Y T

    2009-01-01

    A low power biomedical digital signal processor ASIC based on hardware and software codesign methodology was presented in this paper. The codesign methodology was used to achieve higher system performance and design flexibility. The hardware implementation included a low power 32bit RISC CPU ARM7TDMI, a low power AHB-compatible bus, and a scalable digital co-processor that was optimized for low power Fast Fourier Transform (FFT) calculations. The co-processor could be scaled for 8-point, 16-point and 32-point FFTs, taking approximate 50, 100 and 150 clock circles, respectively. The complete design was intensively simulated using ARM DSM model and was emulated by ARM Versatile platform, before conducted to silicon. The multi-million-gate ASIC was fabricated using SMIC 0.18 microm mixed-signal CMOS 1P6M technology. The die area measures 5,000 microm x 2,350 microm. The power consumption was approximately 3.6 mW at 1.8 V power supply and 1 MHz clock rate. The power consumption for FFT calculations was less than 1.5 % comparing with the conventional embedded software-based solution.

  1. 76 FR 23795 - Low-Power Television and Translator Upgrade Program: Notice of Final Closing Date

    Science.gov (United States)

    2011-04-28

    ... set forth in the Notice of Availability of Funds and Program Guidelines (Upgrade Program NOFA), 74 FR... National Telecommunications and Information Administration Low-Power Television and Translator Upgrade... and Translator Upgrade Program (Upgrade Program) will be Monday, July 2, 2012. NTIA also...

  2. Low power and self-reconfigurable WBAN controller for continuous bio-signal monitoring system

    NARCIS (Netherlands)

    Lee, S.; Yoo, H.J.

    2013-01-01

    The WBAN controller with Branched Bus (BB) topology and Continuous Data Transmission (CDT) protocol with low power consumption and self- reconfigurability is proposed for wearable healthcare applications. The BB topology and CDT protocol is a combination of conventional Bus and Star topology and a v

  3. A heterogeneous multi-core platform for low power signal processing in systems-on-chip

    DEFF Research Database (Denmark)

    Paker, Ozgun; Sparsø, Jens; Haandbæk, Niels;

    2002-01-01

    This paper presents a low-power and programmable DSP architecture - a heterogeneous multiprocessor platform consisting of standard CPU/DSP cores, and a set of simple instruction set processors called mini-cores each optimized for a particular class of algorithm (FIR, IIR, LMS, etc.). Communication...

  4. A Case Study of Nanoscale FPGA Programmable Switches with Low Power

    Directory of Open Access Journals (Sweden)

    V.Elamaran

    2013-04-01

    Full Text Available The trend in VLSI and system design is moving away from high speed to low power due to the rapid growth in the portable consumer electronics market. The technology evolution of deep submicron (DSM will be able to manage the needs and demands of future computing world. A rapid growth of future computing have led to challenges of very deep submicron (DSM regime. Here, the leakage power plays a major contributor to the total power dissipation involved in the circuit as the threshold voltage becomes small while we reduce the operating supply voltage. We present some techniques to reduce the power dissipation involved while interconnecting logic blocks in the Field Programmable Gate Arrays (FPGAs. The interconnections or connectivity among logic blocks are done by routing switches. We use pass-transistor logic, transmission logic and multiplexers for the construction of these routing switches. We present a technique which has both sleep mode in which the leakage power is reduced and low-power mode in which the dynamic power is reduced. These models are built by using Electronic Design Automation (EDA tools like DSCH (Digital Schematic and Microwind layout tools using BSIM4 MOSFET model in 60 nm technology. Results show that the pass-transistor approach is having low power consumption . The leakage and dynamic power are also reduced by the circuit which has the programmability option to change sleep mode and low-power mode.

  5. Water energy resources of the United States with emphasis on low head/low power resources

    Energy Technology Data Exchange (ETDEWEB)

    Hall, Douglas G. [Idaho National Lab. (INL), Idaho Falls, ID (United States). Idaho National Engineering and Environmental Lab. (INEEL); Cherry, Shane J. [Idaho National Lab. (INL), Idaho Falls, ID (United States). Idaho National Engineering and Environmental Lab. (INEEL); Reeves, Kelly S. [Idaho National Lab. (INL), Idaho Falls, ID (United States). Idaho National Engineering and Environmental Lab. (INEEL); Lee, Randy D. [Idaho National Lab. (INL), Idaho Falls, ID (United States). Idaho National Engineering and Environmental Lab. (INEEL); Carroll, Gregory R. [Idaho National Lab. (INL), Idaho Falls, ID (United States). Idaho National Engineering and Environmental Lab. (INEEL); Sommers, Garold L. [Idaho National Lab. (INL), Idaho Falls, ID (United States). Idaho National Engineering and Environmental Lab. (INEEL); Verdin, Kristine L. [Idaho National Lab. (INL), Idaho Falls, ID (United States). Idaho National Engineering and Environmental Lab. (INEEL)

    2004-04-01

    Analytical assessments of the water energy resources in the 20 hydrologic regions of the United States were performed using state-of-the-art digital elevation models and geographic information system tools. The principal focus of the study was on low head (less than 30 ft)/low power (less than 1 MW) resources in each region. The assessments were made by estimating the power potential of all the stream segments in a region, which averaged 2 miles in length. These calculations were performed using hydrography and hydraulic heads that were obtained from the U.S. Geological Survey’s Elevation Derivatives for National Applications dataset and stream flow predictions from a regression equation or equations developed specifically for the region. Stream segments excluded from development and developed hydropower were accounted for to produce an estimate of total available power potential. The total available power potential was subdivided into high power (1 MW or more), high head (30 ft or more)/low power, and low head/low power total potentials. The low head/low power potential was further divided to obtain the fractions of this potential corresponding to the operating envelopes of three classes of hydropower technologies: conventional turbines, unconventional systems, and microhydro (less than 100 kW). Summing information for all the regions provided total power potential in various power classes for the entire United States. Distribution maps show the location and concentrations of the various classes of low power potential. No aspect of the feasibility of developing these potential resources was evaluated. Results for each of the 20 hydrologic regions are presented in Appendix A, and similar presentations for each of the 50 states are made in Appendix B.

  6. Low Power Designing of PLL with 0.125μm CMOS technology

    Directory of Open Access Journals (Sweden)

    Divya Patel Yash Kshirsagar

    2011-10-01

    Full Text Available This paper deals with the designing of Low Power PLL by reducing power consumtion of VCO to generate well-timed on chip clock signals for digital signals. Switching of digital system introduce power supply or substrate noise which perturb the more sensitive blocks in VCO and clock buffer. Since power dissipation in PLL is small fraction of total active power but it increase with increasing operating frequency of digital system. This paper is describing the design of a fully-integrated low-jitter PLL for low power application. To achieve the low jitter performance, our work is proposed on jitter reduction method on both system and circuit level. The results are verified for both circuit and system level. The PLL is implemented in 0.25μm CMOS technology and consumes 10mW from a 2.5V supply

  7. Design and characterisation of micro-diaphragm for low power drug delivery applications

    Science.gov (United States)

    Dissanayake, Don W.; Al-Sarawi, Said F.; Lu, Tien-Fu; Abbott, Derek

    2008-03-01

    Micro-fabricated diaphragms can be used to provide pumping action in microvalve and microfluidic applications. In this paper, a design for a micro-diaphragm that features low power and small area is presented. The diaphragm is actuated using a Surface Acoustic Wave (SAW) device that is interrogated from an RF signal to provide secure actuation operation. The micropump is targeted for in vivo nano-scale drug delivery and similar applications. For low power micropump operation, it is important to design the diaphragm with a higher flexibility while maintaining the stability. Analysis is carried out using ANSYS simulation tools with different design methods and materials. Results achieved from analytical and Finite Element Modeling (FEM) methods are compared and discussed to decide on optimal dimensions for the diaphragm.

  8. Delay-limited capacity of fading multiple access and broadcast channels in the low power regime

    KAUST Repository

    Rezki, Zouheir

    2015-09-11

    We study delay-limited (also called zero-outage) capacity region of the fading multi-access channel (MAC) with Gaussian noise and perfect channel state information (CSI) at the receiver and at the transmitters (CSI-TR), in the low-power regime. We show that for fading channels where the MAC capacity region is strictly positive, it has a multidimensional rectangle structure and thus is simply characterized by single user capacity points. More specifically, we show that at low power, the boundary surface of the capacity region shrinks to a single point corresponding to the sum-rate maximizer and that the coordinates of this point coincide with single user capacity bounds. Using the duality of the Gaussian MAC and broadcast channels (BC), we show that time-sharing (or time division multiple access (TDMA)) is asymptotically optimal. © 2015 IEEE.

  9. Designing BEE: A Hardware Emulation Engine for Signal Processing in Low-Power Wireless Applications

    Directory of Open Access Journals (Sweden)

    Chang Chen

    2003-01-01

    Full Text Available This paper describes the design of a large-scale emulation engine and an application example from the field of low-power wireless devices. The primary goal of the emulator is to support design space exploration of real-time algorithms. The emulator is customized for dataflow dominant architectures, especially focusing on telecommunication-related applications. Due to its novel routing architecture and application-specific nature, the emulator is capable of real-time execution of a class of algorithms in its application space. Moreover, the dataflow structure facilitates the development of a highly abstracted design flow for the emulator. Simulations and practical measurements on commercial development boards are used to verify that real-time emulation of a low-power TDMA receiver is feasible at a clock speed of 25 MHz.

  10. Design of an ultra-low-power digital processor for passive UHF RFID tags

    International Nuclear Information System (INIS)

    A new architecture of digital processors for passive UHF radio-frequency identification tags is proposed. This architecture is based on ISO/IEC 18000-6C and targeted at ultra-low power consumption. By applying methods like system-level power management, global clock gating and low voltage implementation, the total power of the design is reduced to a few microwatts. In addition, an innovative way for the design of a true RNG is presented, which contributes to both low power and secure data transaction. The digital processor is verified by an integrated FPGA platform and implemented by the Synopsys design kit for ASIC flows. The design fits different CMOS technologies and has been taped out using the 2P4M 0.35 μm process of Chartered Semiconductor.

  11. The analysis of pressurizer safety valve stuck open accident for low power and shutdown PSA

    International Nuclear Information System (INIS)

    The PSV (Pressurizer Safety Valve) popping test carried out practically in the early phase of a refueling outage has a little possibility of triggering a test-induced LOCA due to a PSV not fully closed or stuck open. According to a KSNP (Korea Standard Nuclear Power Plant) low power and shutdown PSA (Probabilistic Safety Assessment), the failure of a HPSI (High Pressure Safety Injection) following a PSV stuck open was identified as a dominant accident sequence with a significant contribution to low power and shutdown risks. In this study, we aim to investigate the consequences of the NPP for the various accident sequences following the PSV stuck open as an initiating event through the thermal-hydraulic system code calculations. Also, we search the accident mitigation method for the sequence of HPSI failure, then, the applicability of the method is verified by the simulations using T/H system code

  12. Low-Power Implantable Device for Onset Detection and Subsequent Treatment of Epileptic Seizures: A Review

    Directory of Open Access Journals (Sweden)

    Muhammad Tariqus Salam

    2010-01-01

    Full Text Available Over the past few years, there has been growing interest in neuro-responsive intracerebral local treatments of seizures, such as focal drug delivery, focal cooling, or electrical stimulation. This mode of treatment requires an effective intracerebral electroencephalographic acquisition system, seizure detector, brain stimulator, and wireless system that consume ultra-low power. This review focuses on alternative brain stimulation treatments for medically intractable epilepsy patients. We mainly discuss clinical studies of long-term responsive stimulation and suggest safer optimized therapeutic options for epilepsy. Finally, we conclude our study with the proposed low-power, implantable fully integrated device that automatically detects low-voltage fast activity ictal onsets and triggers focal treatment to disrupt seizure progression. The detection performance was verified using intracerebral electroencephalographic recordings from two patients with epilepsy. Further experimental validation of this prototype is underway.

  13. Low Power Consumption Lasers for Miniature Optical Spectrometers for Trace Gas Analysis

    Science.gov (United States)

    Forouhar, S.; Frez, C.; Franz, K. J.; Ksendzov, A.; Qiu, Y.; Soibel, K. A.; Chen, J.; Hosoda, T.; Kipshidze, G.; Shterengas, L.; Belenky, G.

    2011-01-01

    The air quality of any manned spacecraft needs to be continuously monitored in order to safeguard the health of the crew. Air quality monitoring grows in importance as mission duration increases. Due to the small size, low power draw, and performance reliability, semiconductor laser-based instruments are viable candidates for this purpose. Achieving a minimum instrument size requires lasers with emission wavelength coinciding with the absorption of the fundamental absorption lines of the target gases, which are mostly in the 3.0-5.0 micron wavelength range. In this paper we report on our progress developing high wall plug efficiency type-I quantum-well GaSb-based diode lasers operating at room temperatures in the spectral region near 3.0-3.5 micron and quantum cascade (QC) lasers in the 4.0-5.0 micron range. These lasers will enable the development of miniature, low-power laser spectrometers for environmental monitoring of the spacecraft.

  14. A proposed OEIC circuit with two metal layer silicon waveguide and low power photonic receiver circuit

    Directory of Open Access Journals (Sweden)

    Shiraz Afazal

    2012-09-01

    Full Text Available Recent development in the field of optical communication have increased the need for Opto Electronic Integrated circuit used for the high speed data transmission with low power consuming, high bandwidth and compact size. Presented is the OEIC chip with two metal layer waveguide and low power receiver circuit using standard CMOS technology. The silicon dioxide waveguide is composed of two metal layer reducing metal layer make OEIC cost effective , The silicon LED is fabricated using nwell/p-substrate with p+ octagonal rings, the p+/nwell forms the series pn junction to increase the light emitting area which operates in reverse bias mode. Photo detector is made of multiple PN junction to increase the depletion region width with n+ active implantation/n-well fabricated on the p substrate .the photocurrent receiver circuit is made of MOSFET to perform the function of photo detection and preamplification

  15. Low-power Mid-IR Supercontinuum and Rogue Wave Generation in Chalcogenide Waveguides

    CERN Document Server

    Hernandez, Santiago M; Bonetti, Juan; Grosz, Diego F

    2016-01-01

    We present numerical results of supercontinuum (SC) generation in the mid-IR spectral region, specifically addressing the molecular fingerprint window ranging from 2.5 to 25 um. By solving the Generalized Nonlinear Schr\\"odinger Equation (GNLSE) in a chalcogenide waveguide, we demonstrate low-power SC generation beyond 10 um from a pump at 5 um. Further, we investigate the short-pulse and CW regimes, and show that a simple linear dispersion profile, applicable to a broad range of chalcogenide media, is sufficient to account for the broad SC generation, and yield rich pulse dynamics leading to the frequent occurrence of rogue wave events. Results are encouraging as they point to the feasibility of producing bright and coherent light, by means of single low-power tabletop laser pumping schemes, in a spectral region that finds applications in such diverse areas as molecular spectroscopy, metrology and tomography, among others, and that is not easily addressable with other light sources

  16. Design of an ultra-low-power digital processor for passive UHF RFID tags

    Institute of Scientific and Technical Information of China (English)

    Shi Wanggen; Zhuang Yiqi; Li Xiaoming; Wang Xianghua; Jin Zhao; Wang Dan

    2009-01-01

    A new architecture of digital processors for passive UHF radio-frequency identification tags is proposed.This architecture is based on ISO/IEC 18000-6C and targeted at ultra-low power consumption.By applying methods like system-level power management,global clock gating and low voltage implementation,the total power of the design is reduced to a few microwatts.In addition,an innovative way for the design of a true RNG is presented,which contributes to both low power and secure data transaction.The digital processor is verified by an integrated FPGA platform and implemented by the Synopsys design kit for ASIC flows.The design fits different CMOS technologies and has been taped out using the 2P4M 0.35μm process of Chartered Semiconductor.

  17. A heterogeneous multiprocessor architecture for low-power audio signal processing applications

    DEFF Research Database (Denmark)

    Paker, Ozgun; Sparsø, Jens; Haandbæk, Niels;

    2001-01-01

    of the application at hand using a normal synthesis based ASIC design flow. To give an impression of the size of a processor we mention that one of the FIR processors in a prototype design has 16 instructions, a 32 word×16 bit program memory, a 64 word×16 bit data memory and a 25 word×16 bit coefficient memory....... Early results obtained from the design of a prototype chip containing filter processors for a hearing aid application, indicate a power consumption that is an order of magnitude better than current state of the art low-power audio DSPs implemented using full-custom techniques. This is due to: (1......This paper describes a low-power programmable DSP architecture that targets audio signal processing. The architecture can be characterized as a heterogeneous multiprocessor consisting of small and simple instruction set processors called mini-cores that communicate using message passing...

  18. An ultra low power ECG signal processor design for cardiovascular disease detection.

    Science.gov (United States)

    Jain, Sanjeev Kumar; Bhaumik, Basabi

    2015-08-01

    This paper presents an ultra low power ASIC design based on a new cardiovascular disease diagnostic algorithm. This new algorithm based on forward search is designed for real time ECG signal processing. The algorithm is evaluated for Physionet PTB database from the point of view of cardiovascular disease diagnosis. The failed detection rate of QRS complex peak detection of our algorithm ranges from 0.07% to 0.26% for multi lead ECG signal. The ASIC is designed using 130-nm CMOS low leakage process technology. The area of ASIC is 1.21 mm(2). This ASIC consumes only 96 nW at an operating frequency of 1 kHz with a supply voltage of 0.9 V. Due to ultra low power consumption, our proposed ASIC design is most suitable for energy efficient wearable ECG monitoring devices.

  19. DSTN (Distributed Sleep Transistor Network) for Low Power Programmable Logic array Design

    CERN Document Server

    Singla, Pradeep; Malik, Naveen Kr; 10.5120/7004-9563

    2012-01-01

    With the high demand of the portable electronic products, Low- power design of VLSI circuits & Power dissipation has been recognized as a challenging technology in the recent years. PLA (Programming logic array) is one of the important off shelf part in the industrial application. This paper describes the new design of PLA using power gating structure sleep transistor at circuit level implementation for the low power applications. The important part of the power gating design i.e. header and footer switch selection is also describes in the paper. The simulating results of the proposed architecture of the new PLA is shown and compared with the conventional PLA. This paper clearly shows the optimization in the reduction of power dissipation in the new design implementation of the PLA. The transient response of the power gates structure of PLA is also illustrate in the paper by using TINA-PRO software.

  20. A low-power 10-bit 250-KSPS cyclic ADC with offset and mismatch correction*

    Institute of Scientific and Technical Information of China (English)

    Zhao Hongliang; Zhao Yiqiang; Geng Junfeng; Li Peng; Zhang Zhisheng

    2011-01-01

    A low power 10-bit 250-k sample per second (KSPS) cyclic analog to digital converter (ADC) is presented. The ADC's offset errors are successfully cancelled out through the proper choice of a capacitor switching sequence. The improved redundant signed digit algorithm used in the ADC can tolerate high levels of the comparator's offset errors and switched capacitor mismatch errors. With this structure, it has the advantages of simple circuit configuration, small chip area and low power dissipation. The cyclic ADC manufactured with the Chartered 0.35 μm 2P4M process shows a 58.5 dB signal to noise and distortion ratio and a 9.4 bit effective number of bits at a 250 KSPS sample rate. It dissipates 0.72 mW with a 3.3 V power supply and occupies dimensions of 0.42 × 0.68 mm2.

  1. Novel vertical channel double gate structures for high density and low power flash memory applications

    Institute of Scientific and Technical Information of China (English)

    HUANG Ru; ZHOU FaLong; CAI YiMao; WU DaKe; ZHANG Xing

    2008-01-01

    The flash memory technology meets physical and technical obstacles in further caling. New structures and new materials are implemented as possible solutions. This paper focuses on two kinds of new flash cells for high density and low power memory applications based on the vertical channel double gate structure. The proposed VD-NROM with dual-nitride-trapping-layer and vertical structure can achieve four-bit-per-cell storage capability. And the proposed VSAS-FG cell bene-fits the high programming efficiency, low power and high density capability, which can be realized without any additional mask and can achieve the self-alignment of the split-gate channel and the floating-gate. The two novel flash cell structures can be considered as potential candidates for different flash memory applications.

  2. Low-Power and High Speed 128-Point Pipline FFT/IFFT Processor for OFDM Applications

    Directory of Open Access Journals (Sweden)

    D. Rajaveerappa

    2012-03-01

    Full Text Available This paper represents low power and high speed 128-point pipelined Fast Fourier Transform (FFT and its inverse Fast Fourier Transform (IFFT processor for OFDM. The Modified architecture also provides concept of ROM module and variable length support from 128~2048 point for FFT/IFFT for OFDM applications such as digital audio broadcasting (DAB, digital video broadcasting-terrestrial (DVB-T, asymmetric digital subscriber loop (ADSL and very-high-speed digital subscriber loop (VDSL. The 128-point architecture consists of an optimized pipeline implementation based on Radix-2 butterfly processor Element. To reduce power consumption and chip area, special current-mode SRAMs are adopted to replace shift registers in the delay lines. In low-power operation, when the supply voltage is scaled down to 2.3 V, the processor consumes 176mW when it runs at 17.8 MHz.

  3. Design of an ultra-low-power digital processor for passive UHF RFID tags

    Science.gov (United States)

    Wanggen, Shi; Yiqi, Zhuang; Xiaoming, Li; Xianghua, Wang; Zhao, Jin; Dan, Wang

    2009-04-01

    A new architecture of digital processors for passive UHF radio-frequency identification tags is proposed. This architecture is based on ISO/IEC 18000-6C and targeted at ultra-low power consumption. By applying methods like system-level power management, global clock gating and low voltage implementation, the total power of the design is reduced to a few microwatts. In addition, an innovative way for the design of a true RNG is presented, which contributes to both low power and secure data transaction. The digital processor is verified by an integrated FPGA platform and implemented by the Synopsys design kit for ASIC flows. The design fits different CMOS technologies and has been taped out using the 2P4M 0.35 μm process of Chartered Semiconductor.

  4. High-brightness low-power consumption microLED arrays

    Science.gov (United States)

    Bonar, James R.; Valentine, Gareth J.; Gong, Zheng; Small, James; Gorton, Steve

    2016-03-01

    microLED arrays are a route to providing emissive displays with high brightness and low power consumption performance. In this talk we will discuss results pertaining to sub 10 μm LED pixels, the challenges posed and performance achieved in forming microLED arrays. In particular, pixel pitch, backplane capabilities and colourisation. The applications which can benefit from this approach will also be discussed.

  5. HIGH SPEED LOW POWER CMOS DOMINO OR GATE DESIGN IN 16NM TECHNOLOGY

    Directory of Open Access Journals (Sweden)

    P. Koti Lakshmi

    2015-07-01

    Full Text Available Dynamic logic circuits provide more compact designs with faster switching speeds and low power consumption compared with the other CMOS design styles. This paper proposes a wide fan-in circuit with increased switching speed and noise immunity. Speed is achieved by quickly removing the charge on the dynamic node during evaluation phase, compared to the other circuits. The design also offers very less Power Delay Product (PDP. The design is exercised for 20% variation in supply voltage.

  6. The effect of low-power lasers on intraoral wound healing.

    Science.gov (United States)

    Neiburger, E J

    1995-03-01

    Two types of helium-neon lasers were examined for their effectiveness in increasing the rate of wound healing by biostimulation. The diode helium-neon laser (670 nm) was as effective as the gas helium-neon laser (632 nm) in significantly speeding the rate of healing in rats. Thermal properties of low-power lasers and a controlled clinical case of helium-neon laser treatment of human aphthous stomatitis lesions were reported.

  7. A Survey of Scratch-Pad Memory Management Techniques for low-power and -energy

    OpenAIRE

    Idrissi Aouad, Maha; Zendra, Olivier

    2007-01-01

    ICOOOLPS'2007 was co-located with the 21st European Conference on Object-Oriented Programming (ECOOP'2007). International audience Scratch-Pad Memories (SPMs) are considered to be effective in helping reduce memory energy consumption. However, the variety of SPM management techniques complicates the choice of the right one to implement. In this paper, we first give a synthesis on existing SPM management techniques for low-power and -energy outlining their comparative advantages, drawbac...

  8. The Design of a Low Power Floating Gate Based Phase Frequency Detector and Charge Pump Implementation

    OpenAIRE

    Md. Monirul Islam; Ankit Shivhare

    2013-01-01

    A simple new architecture of phase frequency detector with low power and low phase noise is presented in this paper. The proposed phase frequency detector is based on floating gate, consist of 4 transistors including one floating gate pMOS and one floating gate nMOS constructed with two GDI (gate diffusion input) cells and maintain main characteristics of conventional phase frequency detector in 180 nm technology. Floating gate based methodology reduced the power of phase frequenc...

  9. LOW POWER AND LOW JITTER PHASE FREQUENCY DETECTOR FOR PHASE LOCK LOOP

    OpenAIRE

    KRUTI P. THAKORE,; HARIKRISHNA C. PARMAR,; Dr.N.M. DEVASHRAYEE

    2011-01-01

    This paper presents three types of phase frequency detectors – traditional PFD, modified PFD and high speed PFD. With the comparison of Low power and low jitter phase frequency detector the high speedphase frequency detector is the best candidate for this. High speed phase frequency detector is operated at 1GHz input frequency with 1.8v power supply, power consumption of .39nwatt and jitter is only 2ps.The design is simulated with .35μm CMOS technology.

  10. Designing of Low Power CNTFET Based D Flip-Flop Using Forced Stack Technique

    OpenAIRE

    Vikas Sharma; Umesh Dutta

    2015-01-01

    Low Power devices in small packages is the need of present and future electronic devices. Electronics Industry is making devices which can be planted in human bodies. CMOS Technology won‟t be able to deliver such devices because it shows short channel effects in Nano scale. So, to overcome the problems of CMOS technology we use CNTs (Carbon Nano Tubes). In electronic devices, power is consumed by various elements like flip-flop, latches, clock sources. So in order to reduce power ...

  11. A low-power implantable event-based seizure detection algorithm

    OpenAIRE

    Raghunathan, Shriram; Ward, Matthew P.; Roy, Kaushik; Irazoqui, Pedro P.

    2009-01-01

    Closed-loop neurostimulation has shown great promise as an alternate therapy for over 30% of the epileptic patient population that remain non-responsive to other forms of treatment. We present an event-based seizure detection algorithm that can be implemented in real-time using low power digital CMOS circuits to form an implantable epilepsy prosthesis. Seizures are detected by classifying and marking out 'events' ...

  12. A Low-Power Scalable Stream Compute Accelerator for General Matrix Multiply (GEMM)

    OpenAIRE

    Antony Savich; Shawki Areibi

    2014-01-01

    Many applications ranging from machine learning, image processing, and machine vision to optimization utilize matrix multiplication as a fundamental block. Matrix operations play an important role in determining the performance of such applications. This paper proposes a novel efficient, highly scalable hardware accelerator that is of equivalent performance to a 2 GHz quad core PC but can be used in low-power applications targeting embedded systems requiring high performance computation. P...

  13. Loss optimizing low power 50 Hz transformers intended for AC/DC standby power supplies

    OpenAIRE

    Nielsen, Nils

    2004-01-01

    This paper presents the measured efficiency on selected low power conventional 50 Hz/230 V-AC transformers. The small transformers are intended for use in 1 W@5 V-DC series- or buck-regulated power supplies for standby purposes. The measured efficiency is compared for cheap off-the-self transformer and for some which are optimized for a lower no-load loss. The optimization is done by simple and low cost means.

  14. Low power wind energy conversion system based on variable speed permanent magnet synchronous generators

    OpenAIRE

    Carranza Castillo, Oscar; Garcerá Sanfeliú, Gabriel; Figueres Amorós, Emilio; GONZÁLEZ MORALES, LUIS GERARDO

    2014-01-01

    This paper presents a low power wind energy conversion system (WECS) based on a permanent magnet synchronous generator and a high power factor (PF) rectifier. To achieve a high PF at the generator side, a power processing scheme based on a diode rectifier and a boost DC-DC converter working in discontinuous conduction mode is proposed. The proposed generator control structure is based on three cascaded control loops that regulate the generator current, the turbine speed and the amount of powe...

  15. The PSA approach for the safety assessment of low-power and shutdown states

    International Nuclear Information System (INIS)

    By order of the Federal Ministry for the Environment, Nature Conservation and Nuclear Safety (BMU), GRS carried out an investigation into the safety relevance of low-power and shutdown operating conditions. The analyses were performed on the example of a reference plant (GKN-2) for a modern PWR-1300 of the Konvoi type. They are based on a typical two-week refuelling outage of the reference plant and concentrate on initiating events that are typical of low-power and shutdown operation and which are relevant with regard to their contribution to the system damage states. According to current knowledge, these are mainly those initiating events which are followed by a loss of residual-heat removal (transients and leaks), and here it is especially those which occur during 3/4-loop operation after plant shutdown. Generally, it was possible to apply the available PSA methods - with some specific adaptations - to the operating conditions during low-power and shutdown operation. The analyses led to new insights with regard to boron dilution in the primary system due to condensation processes with reflux-condenser-mode at passive residual-heat removal via a steam generator. For a modern plant with a high level of safety and correspondingly low frequencies of system damage states from power operation it is therefore possible that the contribution to the system damage states from low-power and shutdown operation may well lie at the same order of magnitude. Furthermore it was possible to derive technical findings that can also be of generic relevance for other PWR plants. (orig.)

  16. Multi-Functional Micro Projection Device as Screen Substitute for Low Power Consumption Computing

    OpenAIRE

    Zeev Zalevsky; Yuval Kapellner

    2012-01-01

    One of the major power consuming components in a computer is its display unit. On average the screen consumes ten times more power than the DSP processor itself. Thus, reducing the power consumption should be one of the most important tasks in the development of low power consumption computing systems. In this paper we present one possible solution involving micro projection device based upon lasers and a digital light processing (DLP) matrix which is a matrix of electrically controllable mir...

  17. Effects of low-power light therapy on wound healing: LASER x LED *

    OpenAIRE

    Chaves, Maria Emília de Abreu; de Araújo, Angélica Rodrigues; Piancastelli, André Costa Cruz; Pinotti, Marcos

    2014-01-01

    Several studies demonstrate the benefits of low-power light therapy on wound healing. However, the use of LED as a therapeutic resource remains controversial. There are questions regarding the equality or not of biological effects promoted by LED and LASER. One objective of this review was to determine the biological effects that support the use of LED on wound healing. Another objective was to identify LED´s parameters for the treatment of wounds. The biological effects and parameters of LED...

  18. Precision BiCMOS successive approximation analog-to-digital converter with low power consumption

    International Nuclear Information System (INIS)

    An IP block of a successive approximation analog-to-digital converter (ADC) with low power consumption has been developed as a part of an application-specific integrated circuit (ASIC) for an intellectual flow meter. The advantages of the application of the modified “top-down” design method to the design of the chip have been demonstrated. The results of the simulation, verification, and test of the analog-to-digital converter are presented

  19. Low Power Greenhouse Gas Sensors for Unmanned Aerial Vehicles

    OpenAIRE

    Lary, David J.; Bryan Roscoe; William A. Harrison; Lei Tao; Miller, David J.; Zondlo, Mark A.; Kang Sun; David Schaefer; Amir Khan

    2012-01-01

    We demonstrate compact, low power, lightweight laser-based sensors for measuring trace gas species in the atmosphere designed specifically for electronic unmanned aerial vehicle (UAV) platforms. The sensors utilize non-intrusive optical sensing techniques to measure atmospheric greenhouse gas concentrations with unprecedented vertical and horizontal resolution (~1 m) within the planetary boundary layer. The sensors are developed to measure greenhouse gas species including carbon dioxide, wate...

  20. Design and Optimization of a Low Power Pressure Sensor for Wireless Biomedical Applications

    Directory of Open Access Journals (Sweden)

    J. Sosa

    2015-01-01

    (ADC are designed, optimized, and integrated in the same substrate using a commercial 1 μm CMOS technology. As result of the optimization, we obtained a digital sensor with high sensitivity, low noise (0.002 μV/Hz, and low power consumption (358 μW. Finally, the piezoresistance noise does not affect the pressure sensor application since its value is lower than half least significant bit (LSB of the ADC.

  1. Overview and Evaluation of Bluetooth Low Energy: An Emerging Low-Power Wireless Technology

    OpenAIRE

    Josep Paradells; Joaquim Oller; Carles Gomez

    2012-01-01

    Bluetooth Low Energy (BLE) is an emerging low-power wireless technology developed for short-range control and monitoring applications that is expected to be incorporated into billions of devices in the next few years. This paper describes the main features of BLE, explores its potential applications, and investigates the impact of various critical parameters on its performance. BLE represents a trade-off between energy consumption, latency, piconet size, and throughput that mainly depends on ...

  2. Adiabatic Improved Efficient Charge Recovery Logic for Low Power CMOS Logic

    Directory of Open Access Journals (Sweden)

    Prof. Mukesh Tiwar

    2012-08-01

    Full Text Available Power dissipation becoming a limiting factor in VLSI circuits and systems. Due to relatively high complexity of VLSI systems used in various applications, the power dissipation in CMOS inverter, arises from its switching activity, which is mainly influenced by the supply voltage and effective capacitance. The low-power requirements of present electronic systems have challenged the scientific research towards the study of technological, architectural and circuital solutions that allow a reduction of the energy dissipated by an electronic circuit. One of the main causes of energy dissipation in CMOS circuits is due to the charging and discharging of the node capacitances of the circuits, present both as a load and as parasitic. Such part of the total power dissipated by a circuit is called dynamic power. In order to reduce the dynamic power, an alternative approach to the traditional techniques of power consumption reduction, named adiabatic switching technique is use. Adiabatic switching is an approach to low-power digital circuits that differs fundamentally from other practical low-power techniques. The term adiabatic comes from thermodynamics, used to describe a process in which there is no exchange of heat with the environment. When adiabatic switching is used, the signal energies stored on circuit capacitances may be recycled instead of dissipated as heat. The adiabatic switching technique can achieve very low power dissipation, but at the expense of circuit complexity. Adiabatic logic offers a way to reuse the energy stored in the load capacitors rather than the traditional way of discharging the load capacitors to the ground and wasting this energy. Power reduction is achieved by recovering the energy in the recover phase of the supply clock.

  3. Low-Power Photothermal Probing of Single Plasmonic Nanostructures with Nanomechanical String Resonators

    DEFF Research Database (Denmark)

    Schmid, Silvan; Wu, Kaiyu; Larsen, Peter Emil;

    2014-01-01

    We demonstrate the direct photothermal probing and mapping of single plasmonic nanostructures via the temperature-induced detuning of nanomechanical string resonators. Single Au nanoslits and nanorods are illuminated with a partially polarized focused laser beam (λ = 633 nm) with irradiances in t......). Our results show that nanomechanical resonators are a unique and robust analysis tool for the low-power investigation of thermoplasmonic effects in plasmonic hot spots....

  4. Information needs in nuclear power plants during low power operation modes

    Energy Technology Data Exchange (ETDEWEB)

    Tommila, Teemu; Fantoni, Paolo F.; Zander, Ralf M.

    1998-02-01

    During the past few years an increasing attention has been paid to the safety of shutdown and refuelling operations. It has turned out that the risks during shutdown may be comparable to the risks of power operation. The goal of this report is to identify information requirements related to low power operating modes of nuclear power plants. These include, for example, warm and cold shutdowns, refuelling and maintenance, as well as related state transitions such as start-up and shut-down. The focus of the report is on planned refuelling outages and the role of the control room in managing the outage activities. As a starting point, the basic terminology and characteristics of low power operation are discussed. The current situation at nuclear power plants and some recent developments in information technology are reviewed. End-users' requirements and enabling technologies are combined in order to identify the opportunities for new information technology tools in low power operation. The required features of process control systems and maintenance information systems are described. Common plant modelling techniques, open software architectures and functional structuring of the process control system are suggested to be the key issues in the long-term development of operator support systems. On a shorter time scale, new tools solving limited practical problems should be developed and evaluated. This would provide a basis for the features needed for low power operation, including for example, outage planning, on-line risk monitoring, management of outage tasks, adaptive alarm handling, computerised procedures and task-oriented human interfaces. (author)

  5. A low power MICS band phase-locked loop for high resolution retinal prosthesis.

    Science.gov (United States)

    Yang, Jiawei; Skafidas, Efstratios

    2013-08-01

    Ultra low power dissipation is essential in retinal prosthesis and many other biomedical implants. Extensive research has been undertaken in designing low power biomedical transceivers, however to date, most effort has been focused on low frequency inductive links. For higher frequency, more robust and more complex applications, such as Medical Implant Communication Service (MICS) band multichannel transceivers, power consumption remains high. This paper explores the design of micro-power data links at 400 MHz for a high resolution retinal prosthesis. By taking advantage of advanced small geometry CMOS technology and precise transistor-level modeling, we successfully utilized subthreshold FET operation, which has been historically limited to low frequency circuits due to the inadequate transistor operating speed in and near weak inversion; we have implemented a low power MICS transceiver. Particularly, a low power, MICS band multichannel phase-locked loop (PLL) that employs a subthreshold voltage controlled oscillator (VCO) and digital synchronous dividers has been implemented on a 65-nm CMOS. A design methodology is presented in detail with the demonstration of EKV model parameters extraction. This PLL provides 600- mVpp quadrature oscillations and exhibits a phase noise of -102 dBc/Hz at 200-kHz offset, while only consuming 430- μW from a 1-V supply. The VCO has a gain (KVCO) of 12 MHz/V and is designed to operate in the near-weak inversion region and consumes 220- μA DC current. The designed PLL has a core area of 0.54 mm(2). It satisfies all specifications of MICS band operation with the advantage of significant reduction in power which is crucial for high resolution retinal prosthesis.

  6. A digital filter optimization method for low power digital wireless communication system

    OpenAIRE

    Tarumi, Kousuke; Tsujimoto, Taizo; Yasuura, Hiroto

    2003-01-01

    In this paper, we introduce a design method for a low power digital baseband processing circuit. In particular, we focus on a digital FIR(Finite Impulse Response) filter that is a part of the digital baseband processing. Because the digital filter contains large power consuming components, such as adders and multipliers. We propose a design method to reduce power consumption of the digital FIR filter circuit by optimizing bitwidth of inputs of the mutipliers and the adders. We found that the ...

  7. Ultra low-power biomedical signal processing: an analog wavelet filter approach for pacemakers

    OpenAIRE

    Pavlík Haddad, S.A.

    2006-01-01

    The purpose of this thesis is to describe novel signal processing methodologies and analog integrated circuit techniques for low-power biomedical systems. Physiological signals, such as the electrocardiogram (ECG), the electroencephalogram (EEG) and the electromyogram (EMG) are mostly non-stationary. The main difficulty in dealing with biomedical signal processing is that the information of interest is often a combination of features that are well localized temporally (e.g., spikes) and other...

  8. A low-power photovoltaic system with energy storage for radio communications: Description and design methodology

    Science.gov (United States)

    Chapman, C. P.; Chapman, P. D.; Lewison, A. H.

    1982-01-01

    A low power photovoltaic system was constructed with approximately 500 amp hours of battery energy storage to provide power to an emergency amateur radio communications center. The system can power the communications center for about 72 hours of continuous nonsun operation. Complete construction details and a design methodology algorithm are given with abundant engineering data and adequate theory to allow similar systems to be constructed, scaled up or down, with minimum design effort.

  9. The vulnerability of laser warning systems against guided weapons based on low power lasers

    OpenAIRE

    Al-Jaberi, Mubarak

    2006-01-01

    Laser assisted weapons, such as laser guided bombs, laser guided missiles and laser beam-riding missiles pose a significant threat to military assets in the modern battlefield. Laser beam-riding missiles are particularly hard to detect because they use low power lasers. Most laser warning systems produced so far can not detect laser beam-riding missiles because of their weak emissions which have signals less than 1% of laser range finder power . They are even harder to defeat because current ...

  10. Hydrodynamic and performance of low power turbines: conception, modelling and experimental tests

    OpenAIRE

    Mariana. Simão, Helena M. Ramos

    2010-01-01

    The present work comprises a research about hydraulic machines with the aim of optimization and the selection of adequate turbines of low power for exploitation of an available energy still unexplored in water supply systems based on analyses of 3D hydrodynamic flows and on characteristic curves which lead to the best efficiency point. The analysis is carried out based on non-dimensional parameters (i.e., discharge, head, efficiency, runner speed and mechanical power) in order to be possible ...

  11. Design of Low-Power CMOS OTA Using Bulk-Drive Technique

    Directory of Open Access Journals (Sweden)

    Maryam Ghadiri Modarres

    2015-10-01

    Full Text Available This paper presents the design of low power CMOS- OTA (operational transconductance amplifier using bulk drive (BD technique with broad band. This technique is used for design of low power circuits with broad band for high frequency users, for example communication systems, mobile communication and communication forming of medical electronics. OTA is the base of amplifier .It is a fundamental building part of analog systems. Recently analog designer has been paid to low voltage (LV,low power (LP integrated circuits. Many techniques are used for the design of LV LP circuits, the bulk driven offers principle this designs. This paper suggests a bulk driven OTA in standard CMOS processes and supply voltage 0.8 volt DC. It used of improved wilson current mirror. The simulation results have been carried out by the HSPICE simulator in 180 nm CMOS technology. The open loop gain is enhanced to 17.4dB at unity gain band with (UGB of 26.1 MHZ with sufficient output swing. Power consumption of the OTA is in range of few hundreds of nanowatts (6%.

  12. On the capacity of multiaccess fading channels with full channel state information at low power regime

    KAUST Repository

    Rezki, Zouheir

    2013-06-01

    We study the throughput capacity region of the Gaussian multiaccess (MAC) fading channel with perfect channel state information (CSI) at the receiver (CSI-R) and at the transmitters (CSI-T), at low power regime. We show that it has a multidimensional rectangle structure and thus is simply characterized by single user capacity points. More specifically, we show that at low power regime, the boundary surface of the capacity region shrinks to a single point corresponding to the sum rate maximizer and that the coordinates of this point coincide with single user capacity bounds. Inspired from this result, we propose an on-off scheme, compute its achievable rate, and provide a necessary condition on the fading channels under which this scheme achieves single user capacity bounds of the MAC channel at asymptotically low power regime. We argue that this necessary condition characterizes a class of fading that encompasses all known wireless channels, where the capacity region of the MAC channel has a simple expression in terms of users\\' average power constraints only. © 2013 IEEE.

  13. Designing of Low Power CNTFET Based D Flip-Flop Using Forced Stack Technique

    Directory of Open Access Journals (Sweden)

    Vikas Sharma

    2015-04-01

    Full Text Available Low Power devices in small packages is the need of present and future electronic devices. Electronics Industry is making devices which can be planted in human bodies. CMOS Technology won‟t be able to deliver such devices because it shows short channel effects in Nano scale. So, to overcome the problems of CMOS technology we use CNTs (Carbon Nano Tubes. In electronic devices, power is consumed by various elements like flip-flop, latches, clock sources. So in order to reduce power of a system we used to reduce power consumed by flip-flops. In this paper we design an existing flip-flop “Low power clocked pass transistor flip-flop (LCPTFF” on CNTFET using Stanford CNTFET model for reference. We propose a design of CNTFET based Forced Stack Low Power Clocked Pass Transistor Flip-Flop (CN-FS-LCPTFF and observe 12% to 25% power reduction in various conditions like temperature change, CNTFET diameter change, and different voltage supply.

  14. Development of an ultra-low-power x-ray-photon-resolving imaging detector array

    Science.gov (United States)

    Sun, Shunming; Downey, Stephen; Gaalema, Stephen; Gates, James L.; Jernigan, J. Garrett; Kaaret, Philip; MacIntosh, Scott; Ramsey, Brian; Wall, Bruce

    2010-08-01

    We report on progress to develop and demonstrate CZT and Si hybrid detector arrays for future NASA missions in X-ray and Gamma-ray astronomy. The primary goal for these detectors is consistent with the design concept for the EXIST mission1 and will also be appropriate for other NASA applications and ground-based projects. In particular we target science instruments that have large aperture (multiple square meters) and therefore require a low power ROIC (readout integrated circuits) design (energy resolution for single photon detection for X rays in the range 5-600 keV with a CZT sense layer and 2-30 keV with a Si sense layer. The target CZT arrays are 2 cm × 2 cm with 600 micron square-shaped pixels. The low power smart pixel detects rare X-ray hits with an adjustable threshold setting. A test array of 7 × 5 pixels with a 5 mm thick CZT sense layer demonstrates that the low power pixel can successfully detect X-rays with {50 readout noise electrons RMS.

  15. Low Power Greenhouse Gas Sensors for Unmanned Aerial Vehicles

    Directory of Open Access Journals (Sweden)

    David J. Lary

    2012-05-01

    Full Text Available We demonstrate compact, low power, lightweight laser-based sensors for measuring trace gas species in the atmosphere designed specifically for electronic unmanned aerial vehicle (UAV platforms. The sensors utilize non-intrusive optical sensing techniques to measure atmospheric greenhouse gas concentrations with unprecedented vertical and horizontal resolution (~1 m within the planetary boundary layer. The sensors are developed to measure greenhouse gas species including carbon dioxide, water vapor and methane in the atmosphere. Key innovations are the coupling of very low power vertical cavity surface emitting lasers (VCSELs to low power drive electronics and sensitive multi-harmonic wavelength modulation spectroscopic techniques. The overall mass of each sensor is between 1–2 kg including batteries and each one consumes less than 2 W of electrical power. In the initial field testing, the sensors flew successfully onboard a T-Rex Align 700E robotic helicopter and showed a precision of 1% or less for all three trace gas species. The sensors are battery operated and capable of fully automated operation for long periods of time in diverse sensing environments. Laser-based trace gas sensors for UAVs allow for high spatial mapping of local greenhouse gas concentrations in the atmospheric boundary layer where land/atmosphere fluxes occur. The high-precision sensors, coupled to the ease-of-deployment and cost effectiveness of UAVs, provide unprecedented measurement capabilities that are not possible with existing satellite-based and suborbital aircraft platforms.

  16. 10-bit 20-Msample/s ADC for low-voltage low-power applications

    Science.gov (United States)

    Sou, Gerard; Lu, Guo N.; Klisnick, Geoffroy; Redon, Michel

    1998-09-01

    For the development of new low-voltage, low-power imaging microsystems, we have designed a 10-bit 20-Msample/s ADC. It is a 3-stage sub-ranging architecture and has a rail-to-rail dynamic input. To achieve low-voltage operation and low- power consumption, specific analog blocks such as op-amps and flash ADCs were required. Complementary CMOS comparators with no static consumption were used to build a new low- power 4-bit flash ADC structure with rail-to-rail input range. A new 1.7 volts, 120 dB op-amp structure was designed. To achieve 20 MHz sampling rate, the ADC makes use of time-interleaving, switched capacitor amplifiers, which perform dynamic frequency compensation to optimize speed and offset cancellation to meet resolution requirement. A 20- Msample/s rate has been obtained with supply voltages down to 2.4 volts to 2.4 volts and 60mW power consumption. This ADC has been fabricated and tested and will be integrated on the same chip with color image sensors in a BICMOS process.

  17. Low power gas discharge plasma mediated inactivation and removal of biofilms formed on biomaterials.

    Science.gov (United States)

    Traba, Christian; Chen, Long; Liang, Jun F

    2013-03-20

    The antibacterial activity of gas discharge plasma has been studied for quiet some time. However, high biofilm inactivation activity of plasma was only recently reported. Studies indicate that the etching effect associated with plasmas generated represent an undesired effect, which may cause live bacteria relocation and thus contamination spreading. Meanwhile, the strong etching effects from these high power plasmas may also alter the surface chemistry and affect the biocompatibility of biomaterials. In this study, we examined the efficiency and effectiveness of low power gas discharge plasma for biofilm inactivation and removal. Among the three tested gases, oxygen, nitrogen, and argon, discharge oxygen demonstrated the best anti-biofilm activity because of its excellent ability in killing bacteria in biofilms and mild etching effects. Low power discharge oxygen completely killed and then removed the dead bacteria from attached surface but had negligible effects on the biocompatibility of materials. DNA left on the regenerated surface after removal of biofilms did not have any negative impact on tissue cell growth. On the contrary, dramatically increased growth was found for these cells seeded on regenerated surfaces. These results demonstrate the potential applications of low power discharge oxygen in biofilm treatments of biomaterials and indwelling device decontaminations.

  18. Flexible low-power-consumption OLED displays for a universal communication device

    Science.gov (United States)

    Hack, Michael G.; Chwang, Anna B.; Lu, Min-Hao M.; Kwong, Raymond C.; Weaver, Michael S.; Tung, Yeh-Jiun; Brown, Julie J.

    2003-09-01

    In this paper we will outline the technical challenges and progress towards enabling a novel communication device based on a roll-out, low power consumption, OLED display. Advanced mobile communication devices require a bright, high information content display in a small, light-weight, low power consumption package. We believe that phosphorescent OLED (PHOLED) technology fabricated on a truly flexible substrate, enables a mobile Universal Communication Device (UCD) to offer a high information content display in an extendable form, while rolling up into a small form factor when not in use. This communication device is of great interest for a range of both consumer and military applications. From the display perspective, the key component is achieving a long-lived, low power consumption display. We believe the OLEDs are the preferred display media, and in this talk we will outline our flexible phosphorescent OLED technology. The key to reliable operation is to ensure that the organic materials are fully encapsulated in a package designed for repetitive flexing. UDC has been developing long-lived flexible OLED (FOLED) displays based on plastic substrates and multi-layer monolithic encapsulation. Recent progress in this area will also be reported. Finally, we will outline the backplane requirements for flexible OLED displays and compare the various technology options that can be used to fabricate the UCD.

  19. Method And System For Examining Biological Materials Using Low Power Cw Excitation Raman Spectroscopy.

    Energy Technology Data Exchange (ETDEWEB)

    Alfano, Robert R. (Bronx, NY); Wang, Wubao (Flushing, NY)

    2003-05-06

    A method and system for examining biological materials using low-power cw excitation Raman spectroscopy. A low-power continuous wave (cw) pump laser beam and a low-power cw Stokes (or anti-Stokes) probe laser beam simultaneously illuminate a biological material and traverse the biological material in collinearity. The pump beam, whose frequency is varied, is used to induce Raman emission from the biological material. The intensity of the probe beam, whose frequency is kept constant, is monitored as it leaves the biological material. When the difference between the pump and probe excitation frequencies is equal to a Raman vibrational mode frequency of the biological material, the weak probe signal becomes amplified by one or more orders of magnitude (typically up to about 10.sup.4 -10.sup.6) due to the Raman emission from the pump beam. In this manner, by monitoring the intensity of the probe beam emitted from the biological material as the pump beam is varied in frequency, one can obtain an excitation Raman spectrum for the biological material tested. The present invention may be applied to in the in vivo and/or in vitro diagnosis of diabetes, heart disease, hepatitis, cancers and other diseases by measuring the characteristic excitation Raman lines of blood glucose, cholesterol, serum glutamic oxalacetic transaminase (SGOT)/serum glutamic pyruvic transaminase (SGPT), tissues and other corresponding Raman-active body constituents, respectively.

  20. RELEVANCE OF GROOVED NMOSFETS IN ULTRA DEEP SUBMICRON REGION IN LOW POWER APPLICATIONS

    Directory of Open Access Journals (Sweden)

    Subhra Dhar

    2011-09-01

    Full Text Available To manage the increasing static leakage in low power applications, solutions for leakage reduction aresought at the device design and process technology levels. In this paper, 90nm, 70nm and 50 nm grooved gaten MOS devices are simulated using Silvaco device simulator. By changing the corner angle and adjusting few structural parameters, static leakage reduction is achieved in grooved n MOSFETS in ultra low power applications. The simulation results show that leakage contributing currents like the sub threshold current, punch through current and tunneling leakage current are reduced. The oxide thickness can be increased without increase in the gate induced drain leakage current, and ON-OFF current ratio is improved and maintained constant even in the deep sub micron region. This study can be helpful for low power applications as the static leakage is reduced drastically, as well as be applicable to high speed devices as the ON current is maintained at a constant value. The results are compared with those of corresponding conventional planar devices to bring out the achievements of this work.

  1. Uncertainty quantification of a corrosion-enabled energy harvester for low-power sensing applications

    Science.gov (United States)

    Ouellette, Scott A.; Todd, Michael D.

    2013-04-01

    New developments in novel energy harvesting schemes for structural health monitoring sensor networks have progressed in parallel with advancements in low-power electronic devices and components. Energy harvesting from galvanic corrosion is one such scheme that has shown to be a viable solution for powering sensing platforms for marine infrastructure. However, with this particular energy harvesting scheme, the power output is current limited as a result of a high terminal resistance that increases with time. In addition, the output voltage is non-stationary, and is a function of several environmental parameters and the applied resistive load. Variability in the power source requires a robust conditioning circuit design to produce a regulated power supply to the sensing and computing electronics. This paper experimentally investigates the non-stationary power characteristics of a galvanic corrosion energy harvester; and uncertainty quantification (UQ) is performed on the measured power characteristics for two experimental specimens subject to resistive load sweeps. The effects on designing a low-power sensor node are considered, and the uncertainty characteristics are applied to a low-power boost converter by means of a Monte Carlo simulation. Lastly, the total energy harvester capacity (measured in mA-Hr) is approximated from the data and is compared to a conventional battery.

  2. Low-power portable geophysical data acquisition system and its use in geomagnetic measurements

    Science.gov (United States)

    Medford, L. V.; Maclennan, C. G.; Rosenfeld, P. E.; Lanzerotti, L. J.; Acuna, M. H.

    1981-07-01

    A low-power portable data acquisition system presently in use for geomagnetic measurements is described. The system is composed of a data-processing system containing a low-power microprocessor, a 9-track digital tape recorder, and a rechargeable battery pack. The magnetometer is a low-power three axis fluxgate design. Under program control the data processing system keeps track of time of day and date, samples three analog magnetometer outputs at intervals of either 0.4 or 2 s, digitizes the data to 15-bit resolution, and, depending upon relative magnetic activity, decides upon data compression to increase the tape storage capacity. It also monitors and records internal voltages and provides self-checking functions which may be monitored through a visual readout on the control panel. The system is mounted in a rugged, weather-tight carrying case suitable for use outdoors with minimal protection. The system, including magnetometer, uses 1.6-W power and can store 5.7 Mbytes of data.

  3. A low power sub- μW chemical gilbert cell for ISFET differential reaction monitoring.

    Science.gov (United States)

    Kalofonou, Melpomeni; Toumazou, Christofer

    2014-08-01

    This paper presents a low power current-mode method for monitoring differentially derived changes in pH from ion-sensitive field-effect transistor (ISFET) sensors, by adopting the Chemical Gilbert Cell. The fabricated system, with only a few transistors, achieves differential measurements and therefore drift minimisation of continuously recorded pH signals obtained from biochemical reactions such as DNA amplification in addition to combined gain tunability using only a single current. Experimental results are presented, demonstrating the capabilities of the front-end at a microscopic level through integration in a lab-on-chip (LoC) setup combining a microfluidic assembly, suitable for applications that require differential monitoring in small volumes, such as DNA detection where more than one gene needs to be studied. The system was designed and fabricated in a typical 0.35 μ m CMOS process with the resulting topology achieving good differential pH sensitivity with a measured low power consumption of only 165 nW due to weak inversion operation. A tunable gain is demonstrated with results confirming 15.56 dB gain at 20 nA of ISFET bias current and drift reduction of up to 100 times compared to a single-ended measurement is also reported due to the differential current output, making it ideal for robust, low-power chemical measurement.

  4. Outcomes of an international initiative for harmonization of low power and shutdown probabilistic safety assessment

    Directory of Open Access Journals (Sweden)

    Manna Giustino

    2010-01-01

    Full Text Available Many probabilistic safety assessment studies completed to the date have demonstrated that the risk dealing with low power and shutdown operation of nuclear power plants is often comparable with the risk of at-power operation, and the main contributors to the low power and shutdown risk often deal with human factors. Since the beginning of the nuclear power generation, human performance has been a very important factor in all phases of the plant lifecycle: design, commissioning, operation, maintenance, surveillance, modification, decommissioning and dismantling. The importance of this aspect has been confirmed by recent operating experience. This paper provides the insights and conclusions of a workshop organized in 2007 by the IAEA and the Joint Research Centre of the European Commission, on Harmonization of low power and shutdown probabilistic safety assessment for WWER nuclear power plants. The major objective of the workshop was to provide a comparison of the approaches and the results of human reliability analyses and gain insights in the enhanced handling of human factors.

  5. 47 CFR 74.789 - Broadcast regulations applicable to digital low power television and television translator stations.

    Science.gov (United States)

    2010-10-01

    ... power television and television translator stations. 74.789 Section 74.789 Telecommunication FEDERAL... AND OTHER PROGRAM DISTRIBUTIONAL SERVICES Low Power TV, TV Translator, and TV Booster Stations § 74.789 Broadcast regulations applicable to digital low power television and television...

  6. A very low power MAC (VLPM) protocol for Wireless Body Area Networks.

    Science.gov (United States)

    Ullah, Niamat; Khan, Pervez; Kwak, Kyung Sup

    2011-01-01

    Wireless Body Area Networks (WBANs) consist of a limited number of battery operated nodes that are used to monitor the vital signs of a patient over long periods of time without restricting the patient's movements. They are an easy and fast way to diagnose the patient's status and to consult the doctor. Device as well as network lifetime are among the most important factors in a WBAN. Prolonging the lifetime of the WBAN strongly depends on controlling the energy consumption of sensor nodes. To achieve energy efficiency, low duty cycle MAC protocols are used, but for medical applications, especially in the case of pacemakers where data have time-limited relevance, these protocols increase latency which is highly undesirable and leads to system instability. In this paper, we propose a low power MAC protocol (VLPM) based on existing wakeup radio approaches which reduce energy consumption as well as improving the response time of a node. We categorize the traffic into uplink and downlink traffic. The nodes are equipped with both a low power wake-up transmitter and receiver. The low power wake-up receiver monitors the activity on channel all the time with a very low power and keeps the MCU (Micro Controller Unit) along with main radio in sleep mode. When a node [BN or BNC (BAN Coordinator)] wants to communicate with another node, it uses the low-power radio to send a wakeup packet, which will prompt the receiver to power up its primary radio to listen for the message that follows shortly. The wake-up packet contains the desired node's ID along with some other information to let the targeted node to wake-up and take part in communication and let all other nodes to go to sleep mode quickly. The VLPM protocol is proposed for applications having low traffic conditions. For high traffic rates, optimization is needed. Analytical results show that the proposed protocol outperforms both synchronized and unsynchronized MAC protocols like T-MAC, SCP-MAC, B-MAC and X-MAC in terms

  7. A Very Low Power MAC (VLPM Protocol for Wireless Body Area Networks

    Directory of Open Access Journals (Sweden)

    Kyung Sup Kwak

    2011-03-01

    Full Text Available Wireless Body Area Networks (WBANs consist of a limited number of battery operated nodes that are used to monitor the vital signs of a patient over long periods of time without restricting the patient’s movements. They are an easy and fast way to diagnose the patient’s status and to consult the doctor. Device as well as network lifetime are among the most important factors in a WBAN. Prolonging the lifetime of the WBAN strongly depends on controlling the energy consumption of sensor nodes. To achieve energy efficiency, low duty cycle MAC protocols are used, but for medical applications, especially in the case of pacemakers where data have time-limited relevance, these protocols increase latency which is highly undesirable and leads to system instability. In this paper, we propose a low power MAC protocol (VLPM based on existing wakeup radio approaches which reduce energy consumption as well as improving the response time of a node. We categorize the traffic into uplink and downlink traffic. The nodes are equipped with both a low power wake-up transmitter and receiver. The low power wake-up receiver monitors the activity on channel all the time with a very low power and keeps the MCU (Micro Controller Unit along with main radio in sleep mode. When a node [BN or BNC (BAN Coordinator] wants to communicate with another node, it uses the low-power radio to send a wakeup packet, which will prompt the receiver to power up its primary radio to listen for the message that follows shortly. The wake-up packet contains the desired node’s ID along with some other information to let the targeted node to wake-up and take part in communication and let all other nodes to go to sleep mode quickly. The VLPM protocol is proposed for applications having low traffic conditions. For high traffic rates, optimization is needed. Analytical results show that the proposed protocol outperforms both synchronized and unsynchronized MAC protocols like T-MAC, SCP-MAC, B

  8. MOSFET-like CNFET based logic gate library for low-power application: a comparative study

    Science.gov (United States)

    Gowri Sankar, P. A.; Udhayakumar, K.

    2014-07-01

    The next generation of logic gate devices are expected to depend upon radically new technologies mainly due to the increasing difficulties and limitations of existing CMOS technology. MOSFET like CNFETs should ideally be the best devices to work with for high-performance VLSI. This paper presents results of a comprehensive comparative study of MOSFET-like carbon nanotube field effect transistors (CNFETs) technology based logic gate library for high-speed, low-power operation than conventional bulk CMOS libraries. It focuses on comparing four promising logic families namely: complementary-CMOS (C-CMOS), transmission gate (TG), complementary pass logic (CPL) and Domino logic (DL) styles are presented. Based on these logic styles, the proposed library of static and dynamic NAND-NOR logic gates, XOR, multiplexer and full adder functions are implemented efficiently and carefully analyzed with a test bench to measure propagation delay and power dissipation as a function of supply voltage. This analysis provides the right choice of logic style for low-power, high-speed applications. Proposed logic gates libraries are simulated using Synopsys HSPICE based on the standard 32 nm CNFET model. The simulation results demonstrate that, it is best to use C-CMOS logic style gates that are implemented in CNFET technology which are superior in performance compared to other logic styles, because of their low average power-delay-product (PDP). The analysis also demonstrates how the optimum supply voltage varies with logic styles in ultra-low power systems. The robustness of the proposed logic gate library is also compared with conventional and state-art of CMOS logic gate libraries.

  9. Parallel design patterns for a low-power, software-defined compressed video encoder

    Science.gov (United States)

    Bruns, Michael W.; Hunt, Martin A.; Prasad, Durga; Gunupudi, Nageswara R.; Sonachalam, Sekar

    2011-06-01

    Video compression algorithms such as H.264 offer much potential for parallel processing that is not always exploited by the technology of a particular implementation. Consumer mobile encoding devices often achieve real-time performance and low power consumption through parallel processing in Application Specific Integrated Circuit (ASIC) technology, but many other applications require a software-defined encoder. High quality compression features needed for some applications such as 10-bit sample depth or 4:2:2 chroma format often go beyond the capability of a typical consumer electronics device. An application may also need to efficiently combine compression with other functions such as noise reduction, image stabilization, real time clocks, GPS data, mission/ESD/user data or software-defined radio in a low power, field upgradable implementation. Low power, software-defined encoders may be implemented using a massively parallel memory-network processor array with 100 or more cores and distributed memory. The large number of processor elements allow the silicon device to operate more efficiently than conventional DSP or CPU technology. A dataflow programming methodology may be used to express all of the encoding processes including motion compensation, transform and quantization, and entropy coding. This is a declarative programming model in which the parallelism of the compression algorithm is expressed as a hierarchical graph of tasks with message communication. Data parallel and task parallel design patterns are supported without the need for explicit global synchronization control. An example is described of an H.264 encoder developed for a commercially available, massively parallel memorynetwork processor device.

  10. MOSFET-like CNFET based logic gate library for low-power application: a comparative study

    International Nuclear Information System (INIS)

    The next generation of logic gate devices are expected to depend upon radically new technologies mainly due to the increasing difficulties and limitations of existing CMOS technology. MOSFET like CNFETs should ideally be the best devices to work with for high-performance VLSI. This paper presents results of a comprehensive comparative study of MOSFET-like carbon nanotube field effect transistors (CNFETs) technology based logic gate library for high-speed, low-power operation than conventional bulk CMOS libraries. It focuses on comparing four promising logic families namely: complementary-CMOS (C-CMOS), transmission gate (TG), complementary pass logic (CPL) and Domino logic (DL) styles are presented. Based on these logic styles, the proposed library of static and dynamic NAND-NOR logic gates, XOR, multiplexer and full adder functions are implemented efficiently and carefully analyzed with a test bench to measure propagation delay and power dissipation as a function of supply voltage. This analysis provides the right choice of logic style for low-power, high-speed applications. Proposed logic gates libraries are simulated using Synopsys HSPICE based on the standard 32 nm CNFET model. The simulation results demonstrate that, it is best to use C-CMOS logic style gates that are implemented in CNFET technology which are superior in performance compared to other logic styles, because of their low average power-delay-product (PDP). The analysis also demonstrates how the optimum supply voltage varies with logic styles in ultra-low power systems. The robustness of the proposed logic gate library is also compared with conventional and state-art of CMOS logic gate libraries. (semiconductor integrated circuits)

  11. A low-power, multichannel gated oscillator-based CDR for short-haul applications

    OpenAIRE

    Tajalli, Armin; Muller, Paul; Atarodi, Mojtaba; Leblebici, Yusuf

    2005-01-01

    We present a complete top-down design of a low-power multi-channel clock recovery circuit based on gated current-controlled oscillators. The flow includes several tools and methods used to specify block constraints, to design and verify the topology down to the transistor level, as well as to achieve a power consumption as low as 5mW/Gbit/s. Statistical simulation is used to estimate the achievable bit error rate in presence of phase and frequency errors and to prove the feasibility of the co...

  12. Low-power laser use in the treatment of alopecia and crural ulcers

    Science.gov (United States)

    Ciuchita, Tavi; Usurelu, Mircea; Antipa, Ciprian; Vlaiculescu, Mihaela; Ionescu, Elena

    1998-07-01

    The authors tried to verify the efficacy of Low Power Laser (LPL) in scalp alopecia and crural ulcers of different causes. Laser used was (red diode, continuous emission, 8 mW power, wave length 670 nm spot size about 5 mm diameter on some points 1 - 2 minutes per point. We also use as control classical therapy. Before, during and after treatment, histological samples were done for alopecia. For laser groups (alopecia and ulcers) the results were rather superior and in a three or twice time shorter than control group. We conclude that LPL therapy is a very useful complementary method for the treatment of scalp alopecia and crural ulcers.

  13. Shock-Tolerant Low-Power Generator Design for Landed Missions

    Science.gov (United States)

    Gelderloos, Carl J.; Decino, Jim; Lock, Jennifer; Miller, Dan D.; Taylor, Robert

    2004-02-01

    A shock-tolerant thermal enclosure has been designed for use in distributed landed missions. Missions such as Pascal and the Mars Long-Lived Landed Network require low power sources capable of surviving an omnidirectional load at impact and delivering reliable power for several Martian years. With the use of a radioisotope heat source and a thermoelectric converter, power can be generated reliably, but the challenge of developing an insulating canister that delivers sufficient power at end of life and is shock tolerant has been elusive. We describe a manufacturable design using conventional materials that meets mission requirements and show preliminary analysis of impact load response.

  14. A photovoltaic power system and a low-power satellite earth station for Indonesia

    Science.gov (United States)

    Delombard, Richard; Everson, Kent

    1985-01-01

    A photovoltaic power system and a low-power, two-way satellite earth station have been installed at Wawotobi, Sulawesi, Indonesia to provide university classroom communications for audio teleconferencing and video graphics. This project is a part of the Agency for International Development's Rural Satellite Program. The purpose of this program is to demonstrate the use of satellite communications for development assistance applications. The purpose of the photovoltaic power system is to demonstrate the suitability of a hybrid photovoltaic/engine-generator power system for a remote satellite earth station. This paper describes the design, installation and initial operation of the photovoltaic power system and the earth station.

  15. Competition at the Wireless Sensor Network MAC Layer: Low Power Probing interfering with X-MAC

    International Nuclear Information System (INIS)

    Wireless Sensor Networks (WSNs) combine sensors with computer networks and enable very dense, in-situ and live measurements of data over a large area. Since this emerging technology has the potential to be embedded almost everywhere for numberless applications, interference between different networks can become a serious issue. For most WSNs, it is assumed today that the network medium access is non-competitive. On the basis of X-MAC interfered by Low Power Probing, this paper shows the danger and the effects of different sensor networks communicating on a single wireless channel of the 2.4 GHz band, which is used by the IEEE 802.15.4 standard.

  16. Low-Power Optical Feeder for VDSL Over Twisted Pair for Last Mile Access Networks

    Science.gov (United States)

    Dudley, Sandra E. M.; Quinlan, Terence J.; Henning, Ian D.; Walker, Stuart D.; Davey, Russell P.; Wallace, Andrew D.; Boyd, Ivan; Payne, Dave B.

    2006-01-01

    In this paper, we describe an ultra-low-power optoelectronic very-high-data-rate digital subscriber line (VDSL) system, enabling broadband access to the home over 10 km of optical fiber and 1 km of twisted pair. The cabinet/distribution point interface has a footprint of just 3 × 3 × 1 cm, and consumes only 165 mW. A quadrature-amplitude-modulation (QAM) scheme was used for system tests with 10 Mb/s full duplex achieved, and up to 40-dB up/downstream channel isolation is obtained using hybrid transformers.

  17. A Novel Pulse-Based Modulation Technique for Wideband Low Power Communication with Neuroprosthetic Devices

    OpenAIRE

    Inanlou, Farzad; Kiani, Mehdi; Ghovanloo, Maysam

    2010-01-01

    Pulse Harmonic Modulation (PHM) is a novel pulse-based (carrierless) modulation method for wideband, low power data transmission across inductive telemetry links that operate in the near-field domain. PHM utilizes two or more unidentical pulses during each bit period to minimize intersymbol interference (ISI). In this paper, we describe the PHM concept and demonstrate its operation with a proof-of-concept prototype, which achieves a data rate of 5.2 Mbps at 1 cm coil separation with a bit err...

  18. Dry cleaning of fluorocarbon residues by low-power electron cyclotron resonance hydrogen plasma

    CERN Document Server

    Lim, S H; Yuh, H K; Yoon Eui Joon; Lee, S I

    1988-01-01

    A low-power ( 50 W) electron cyclotron resonance hydrogen plasma cleaning process was demonstrated for the removal of fluorocarbon residue layers formed by reactive ion etching of silicon dioxide. The absence of residue layers was confirmed by in-situ reflection high energy electron diffraction and cross-sectional high resolution transmission electron microscopy. The ECR hydrogen plasma cleaning was applied to contact cleaning of a contact string structure, resulting in comparable contact resistance arising during by a conventional contact cleaning procedure. Ion-assisted chemical reaction involving reactive atomic hydrogen species generated in the plasma is attributed for the removal of fluorocarbon residue layers.

  19. Low power laser generated ultrasound: Signal processing for time domain data acquisition

    Energy Technology Data Exchange (ETDEWEB)

    Cleary, A; Thursby, G; McKee, C; Armstrong, I; Culshaw, B [Centre for Microsystems and Photonics, Department of Electronic and Electrical Engineering, University of Strathclyde, Glasgow, G1 1XW (United Kingdom); Veres, I; Pierce, S G, E-mail: alison.cleary@eee.strath.ac.uk [Centre for Ultrasonic Engineering, Department of Electronic and Electrical Engineering, University of Strathclyde, Glasgow, G1 1XW (United Kingdom)

    2011-01-01

    The use of low power modulated laser diode systems has previously been established as a suitable method for non-destructive laser generation of ultrasound. Using a quasi-continuous optical excitation amplified by an erbium-doped fibre amplifier (EDFA) allows flexible generation of ultrasonic waves, offering control of further parameters such as the frequency content or signal shape. In addition, pseudo-random binary sequences (PRBS) can be used to improve the detected impulse response. Here we compare two sequences, the m-sequence and the Golay code, and discuss the advantages and practical limits of their application with laser diode based optical excitation of ultrasound.

  20. Use of low power EM radar sensors for speech articulator measurements

    Energy Technology Data Exchange (ETDEWEB)

    Holzrichter, J.F.; Burnett, G.C.

    1997-05-14

    Very low power electromagnetic (EM) wave sensors are being used to measure speech articulator motions such as the vocal fold oscillations, jaw, tongue, and the soft palate. Data on vocal fold motions, that correlate well with established laboratory techniques, as well as data on the jaw, tongue, and soft palate are shown. The vocal fold measurements together with a volume air flow model are being used to perform pitch synchronous estimates of the voiced transfer functions using ARMA (autoregressive moving average) techniques. 6 refs., 5 figs.

  1. Low Power and High Speed D-Latch Circuit Designs Based on Carbon Nanotube FET

    Directory of Open Access Journals (Sweden)

    Neda Talebipoor

    2012-11-01

    Full Text Available In this paper we propose low power and high speed D-latche circuits base on carbon nanotube field effect transistor. D-latches are the important state-holding elements and systems performance enhancement will be achieved by improving the flip-flop latches structure. The circuit designs are simulated by Hspice .In this paper the consumption result of the circuit parameters such as delay, power and PDP for our three different D-latch circuit design in various voltages and different temperatures.

  2. A Low Power High Bandwidth Four Quadrant Analog Multiplier in 32 NM CNFET Technology

    Directory of Open Access Journals (Sweden)

    Ishit Makwana

    2012-04-01

    Full Text Available Carbon Nano tube Field Effect Transistor (CNFET is a promising new technology that overcomes several limitations of traditional silicon integrated circuit technology. In recent years, the potential of CNFET for analog circuit applications has been explored. This paper proposes a novel four quadrant analog multiplier design using CNFETs. The simulation based on 32nm CNFET technology shows that the proposed multiplier has very low harmonic distortion (<0.45%, large input range (±400mV, large bandwidth (~50GHz and low power consumption (~247µW, while operating at a supply voltage of ±0.9V.

  3. A Comparative Study Of Low Power Consumption Techniques In A VLSI Circuit

    Directory of Open Access Journals (Sweden)

    Tripti Mehta

    2015-07-01

    Full Text Available Power optimization has become an important factor in designing a VLSI circuit. Earlier dynamic power was single largest concern but as transistor size decreases static power dominates the dynamic power. A comparable analysis of different low power, leakage current reduction techniques like sleep, stack, sleepy keeper and reverse body bias with sleep and stack has been done. Based on simulations performed on a XNOR circuit, the reverse body with sleep and stack achieves up to 60% less power consumption as compared to the base case which is better than other conventional techniques. Simulations to estimate power consumption are done on a TANNER EDA tool at 90 nm technology.

  4. Low power continuous wave laser induced optical nonlinearities in saffron ( Crocus Sativus L.)

    Science.gov (United States)

    Nasibov, H.; Mamedbeili, I.

    2010-12-01

    We report on the low power CW laser induced nonlinear optical responses of Saffron (stigmata of Crocus Savitus L.) ethanol and methanol extracts. The optical nonlinearities were investigated by performing Z-scan measurements at 470 and 535 nm wavelengths. At both wavelengths the material has a strong nonlinear refraction, mainly of thermal origin. However, only at 470 nm wavelength the material exhibit pronounced saturable nonlinear absorption. Long-term (70 days) stability measurements indicated that the nonlinearities in the Saffron extracts are due to their nonvolatile components. This study shows that there is great potential for Saffron extracts to be used in nonlinear photonic applications.

  5. A low power low noise amplifier for a 128 channel detector read-out integrated circuit

    International Nuclear Information System (INIS)

    This paper describes the design of a low power, low noise CMOS amplifier. The amplifier was designed using the folded cascade configuration and was implemented on a 3μm double polysilicon process. The amplifier is part of a 128 channel charge amplifier array chip for use in the read-out of radiation detectors with many channels. Aspects of the amplifier design such as band-width, pulse response, and noise are discussed and the effects of individual transistors are shown thereby relating circuit performance to process parameters; circuit test results are presented and radiation test results are included. (author)

  6. Wireless ultra-wide-band transmission prototype ASICs for low-power space and radiation applications

    Energy Technology Data Exchange (ETDEWEB)

    Gabrielli, A. [Istituto Nazionale di Fisica Nucleare (INFN), Bologna (Italy); Department of Physics and Astronomy, University of Bologna, Bologna (Italy); Crepaldi, M. [IIT@Polito Istituto Italiano Tecnologia, Politecnico di Torino, Torino (Italy); Demarchi, D. [IIT@Polito Istituto Italiano Tecnologia, Politecnico di Torino, Torino (Italy); Department of Electronics (DELEN), Politecnico di Torino, Torino (Italy); Motto Ros, P. [IIT@Polito Istituto Italiano Tecnologia, Politecnico di Torino, Torino (Italy); Villani, G. [Science Technology Facility Council (STFC), Rutherford Appleton Laboratory (RAL), Didcot (United Kingdom)

    2014-11-21

    The paper describes the design and the fabrication of a microelectronic circuit composed of a sensor, an oscillator, a modulator, a transmitter and an antenna. The chip embeds a custom radiation sensor, provided by the silicon foundry that has fabricated the prototypes, but in principle the entire system can read a general sensor, as long as a proper interface circuit is used. The natural application for this circuit is radiation monitoring but the low-power budget extends the applications to space where wireless readout circuits can be applied to any type of sensors, even if not radiation sensitive devices.

  7. Wireless ultra-wide-band transmission prototype ASICs for low-power space and radiation applications

    International Nuclear Information System (INIS)

    The paper describes the design and the fabrication of a microelectronic circuit composed of a sensor, an oscillator, a modulator, a transmitter and an antenna. The chip embeds a custom radiation sensor, provided by the silicon foundry that has fabricated the prototypes, but in principle the entire system can read a general sensor, as long as a proper interface circuit is used. The natural application for this circuit is radiation monitoring but the low-power budget extends the applications to space where wireless readout circuits can be applied to any type of sensors, even if not radiation sensitive devices

  8. A Low Power High Bandwidth Four Quadrant Analog Multiplier in 32 NM CNFET Technology

    Directory of Open Access Journals (Sweden)

    Vitrag Sheth

    2012-05-01

    Full Text Available Carbon Nanotube Field Effect Transistor (CNFET is a promising new technology that overcomes several limitations of traditional silicon integrated circuit technology. In recent years, the potential of CNFET for analog circuit applications has been explored. This paper proposes a novel four quadrant analog multiplier design using CNFETs. The simulation based on 32nm CNFET technology shows that the proposed multiplier has very low harmonic distortion (<0.45%, large input range (±400mV, large bandwidth (~50GHz and low power consumption (~247µW, while operating at a supply voltage of ±0.9V.

  9. Ultra-low-power wireless transmitter for neural prostheses with modified pulse position modulation

    OpenAIRE

    Goodarzy, Farhad; Skafidas, Stan E.

    2014-01-01

    An ultra-low-power wireless transmitter for embedded bionic systems is proposed, which achieves 40 pJ/b energy efficiency and delivers 500 kb/s data using the medical implant communication service frequency band (402–405 MHz). It consumes a measured peak power of 200 µW from a 1.2 V supply while occupying an active area of 0.0016 mm2 in a 130 nm technology. A modified pulse position modulation technique called saturated amplified signal is proposed and implemented, which can reduce the overal...

  10. Study of a low power dissipation, miniature laser-pumped rubidium frequency standard

    Institute of Scientific and Technical Information of China (English)

    Liu Guo-Bin; Zhao Feng; Gu Si-Hong

    2009-01-01

    This paper studies a miniature low power consumption laser-pumped atom vapour cell clock scheme. Pumping 87Rb with a vertical cavity surface emitting laser diode pump and locking the laser frequency on a Doppler-broadened spectral line,it records a 5×10-11τ-1/2 (τ<500 s) frequency stability with a table-top system in a primary experiment.The study reveals that the evaluated scheme is at the level of 2.7 watts power consumption,90 cm3 volume and 10-12τ- 1/2 short-term frequency stability.

  11. Survey and selection of Energy Storage System for Low Power Embedded System

    OpenAIRE

    Meenu Nair; Chandan Maity

    2012-01-01

    Energy storage for portable low power Embedded System is one of the biggest challenges for a long time operation in present research and application. These systems are designed to operate the lowest possible energy at micro-watt or Milli-Watt range and the power is supplied from a small primary or secondary cell. In this paper an extensive study and latest survey has been shown to estimate and select the right suitable energy storage device in theoretical aspects and also commercially availab...

  12. Ultra Low Power 14XM FinFET's Process-a Radical New Approach to Transistors

    Directory of Open Access Journals (Sweden)

    Suhas K. V.

    2013-05-01

    Full Text Available FinFET technology is a radical new technology that has been proposed by the industry to overcome large leakage power occurring in low power VLSI circuits. In this paper, the working of the basic MOSFET, condition of operations for any transistor and the FinFET along with its structure is described. This paper mainly covers how FinFET can be an advantage compared to basic MOSFET and how leakage can be reduced in FinFET is explained with the comparison of basic MOSFET. The fabrication steps are briefly discussed

  13. A low-power piecewise linear analog to digital converter for use in particle tracking

    Energy Technology Data Exchange (ETDEWEB)

    Valencic, V.; Deval, P. [MEAD Microelectronics S.A., St. Sulpice (Switzerland)]|[EPFL, Lausanne (Switzerland). Electronics Labs.; Anghinolfi, F. [CERN, Geneva (Switzerland); Bonino, R.; Marra, D. La; Kambara, Hisanori [Univ. of Geneva (Switzerland)

    1995-08-01

    This paper describes a low-power piecewise linear A/D converter. A 5MHz {at} 5V with 25mW power consumption prototype has been implemented in a 1.5{micro}m CMOS process. The die area excluding pads is 5mm{sup 2}. 11-bit absolute accuracy is obtained with a new DC offset plus charge injection compensation technique used in the comparators scheme. This ADC with large dynamic range and high resolution is developed for the readout of a tracker and/or preshower in the future LHC experiments.

  14. Low power and self-reconfigurable WBAN controller for continuous bio-signal monitoring system.

    Science.gov (United States)

    Lee, Seulki; Yoo, Hoi-Jun

    2013-04-01

    The WBAN controller with Branched Bus (BB) topology and Continuous Data Transmission (CDT) protocol with low power consumption and self-reconfigurability is proposed for wearable healthcare applications. The BB topology and CDT protocol is a combination of conventional Bus and Star topology and a variation from TDMA protocol, respectively, while they are able to compensate for the electrical fault in bio-signal monitoring system caused by the electrode deformation. Thanks to them, the proposed WBAN controller enables more reliable operation in continuous bio-signal monitoring applications such as sleep monitoring.

  15. Dynamic Floating Output Stage for Low Power Buffer Amplifier for LCD Application

    Directory of Open Access Journals (Sweden)

    Hari Shanker Srivastava

    2015-02-01

    Full Text Available This topic proposes low-power buffer means low quiescent current buffer amplifier. A dynamic floating current node is used at the output of two-stage amplifier to increase the charging and discharging of output capacitor as well as settling time of buffer. It is designed for 10 bit digital analog converter to support for LCD column driver it is implemented in 180 nm CMOS technology with the quiescent current of 5 µA for 30 pF capacitance, the settling time calculated as 4.5µs, the slew rate obtained as 5V/µs and area on chip is 30×72µ

  16. Design of High Speed Low Power Reversible Logic Adder Using HNG Gate

    Directory of Open Access Journals (Sweden)

    Manjeet Singh Sankhwar,

    2014-01-01

    Full Text Available Reversibility plays a fundamental role when computations with minimal energy dissipation are considered. In recent years, reversible logic has emerged as one of the most important approaches for power optimization with its application in low power CMOS, optical information processing, quantum computing and nanotechnology. This research proposes a new implementation of adder in reversible logic. The design reduces the number of gate operations compared to the existing adder reversible logic implementations. So, this design gives rise to an implementation with a reduced area and delay. We can use it to construct more complex systems in nanotechnology.

  17. Sodium magnetic resonance imaging. Development of a 3D radial acquisition technique with optimized k-space sampling density and high SNR-efficiency; Natrium-Magnetresonanztomographie. Entwicklung einer 3D radialen Messtechnik mit optimierter k-Raum-Abtastdichte und hoher SNR-Effizienz

    Energy Technology Data Exchange (ETDEWEB)

    Nagel, Armin Michael

    2009-04-01

    A 3D radial k-space acquisition technique with homogenous distribution of the sampling density (DA-3D-RAD) is presented. This technique enables short echo times (TE<0.5 ms), that are necessary for {sup 23}Na-MRI, and provides a high SNR-efficiency. The gradients of the DA-3D-RAD-sequence are designed such that the average sampling density in each spherical shell of k-space is constant. The DA-3D-RAD-sequence provides 34% more SNR than a conventional 3D radial sequence (3D-RAD) if T{sub 2}{sup *}-decay is neglected. This SNR-gain is enhanced if T{sub 2}{sup *}-decay is present, so a 1.5 to 1.8 fold higher SNR is measured in brain tissue with the DA-3D-RAD-sequence. Simulations and experimental measurements show that the DA-3D-RAD sequence yields a better resolution in the presence of T{sub 2}{sup *}-decay and less image artefacts when B{sub 0}-inhomogeneities exist. Using the developed sequence, T{sub 1}-, T{sub 2}{sup *}- and Inversion-Recovery-{sup 23}Na-image contrasts were acquired for several organs and {sup 23}Na-relaxation times were measured (brain tissue: T{sub 1}=29.0{+-}0.3 ms; T{sub 2s}{sup *}{approx}4 ms; T{sub 2l}{sup *}{approx}31 ms; cerebrospinal fluid: T{sub 1}=58.1{+-}0.6 ms; T{sub 2}{sup *}=55{+-}3 ms (B{sub 0}=3 T)). T{sub 1}- und T{sub 2}{sup *}-relaxation times of cerebrospinal fluid are independent of the selected magnetic field strength (B0 = 3T/7 T), whereas the relaxation times of brain tissue increase with field strength. Furthermore, {sup 23}Na-signals of oedemata were suppressed in patients and thus signals from different tissue compartments were selectively measured. (orig.)

  18. Design and Implementation of RF Energy Harvesting System for Low-Power Electronic Devices

    Science.gov (United States)

    Uzun, Yunus

    2016-08-01

    Radio frequency (RF) energy harvester systems are a good alternative for energizing of low-power electronics devices. In this work, an RF energy harvester is presented to obtain energy from Global System for Mobile Communications (GSM) 900 MHz signals. The energy harvester, consisting of a two-stage Dickson voltage multiplier circuit and L-type impedance matching circuits, was designed, simulated, fabricated and tested experimentally in terms of its performance. Simulation and experimental works were carried out for various input power levels, load resistances and input frequencies. Both simulation and experimental works have been carried out for this frequency band. An efficiency of 45% is obtained from the system at 0 dBm input power level using the impedance matching circuit. This corresponds to the power of 450 μW and this value is sufficient for many low-power devices. The most important parameters affecting the efficiency of the RF energy harvester are the input power level, frequency band, impedance matching and voltage multiplier circuits, load resistance and the selection of diodes. RF energy harvester designs should be optimized in terms of these parameters.

  19. A Low-Power Digitally Controlled Oscillator for All Digital Phase-Locked Loops

    Directory of Open Access Journals (Sweden)

    Jun Zhao

    2010-01-01

    Full Text Available A low-power and low-jitter 12-bit CMOS digitally controlled oscillator (DCO design is presented. The Low-Power CMOS DCO is designed based on the ring oscillator implemented with Schmitt trigger inverters. The proposed DCO circuit uses control codes of thermometer type to reduce jitters. Performance of the DCO is verified through a novel All Digital Phase-Locked Loop (ADPLL designed with a unique lock-in process by employing a time-to-digital converter, where both the frequency of the reference clock and the delay between DCO_output and DCO_clock is measured. A carefully designed reset process reduces the phase acquisition process to two cycles. The ADPLL was implemented using the 32 nm Predictive Technology Model (PTM at 0.9 V supply voltage, and the simulation results show that the proposed ADPLL achieves 10 and 2 reference cycles of frequency and phase acquisitions, respectively, at 700 MHz with less than 67 ps peak-to-peak jitter. The DCO consumes 2.2 mW at 650 MHz with 0.9 V power supply.

  20. IEEE-802.15.4-based low-power body sensor node with RF energy harvester.

    Science.gov (United States)

    Tran, Thang Viet; Chung, Wan-Young

    2014-01-01

    This paper proposes the design and implementation of a low-voltage and low-power body sensor node based on the IEEE 802.15.4 standard to collect electrocardiography (ECG) and photoplethysmography (PPG) signals. To achieve compact size, low supply voltage, and low power consumption, the proposed platform is integrated into a ZigBee mote, which contains a DC-DC booster, a PPG sensor interface module, and an ECG front-end circuit that has ultra-low current consumption. The input voltage of the proposed node is very low and has a wide range, from 0.65 V to 3.3 V. An RF energy harvester is also designed to charge the battery during the working mode or standby mode of the node. The power consumption of the proposed node reaches 14 mW in working mode to prolong the battery lifetime. The software is supported by the nesC language under the TinyOS environment, which enables the proposed node to be easily configured to function as an individual health monitoring node or a node in a wireless body sensor network (BSN). The proposed node is used to set up a wireless BSN that can simultaneously collect ECG and PPG signals and monitor the results on the personal computer.

  1. Low-power wireless ECG acquisition and classification system for body sensor networks.

    Science.gov (United States)

    Lee, Shuenn-Yuh; Hong, Jia-Hua; Hsieh, Cheng-Han; Liang, Ming-Chun; Chang Chien, Shih-Yu; Lin, Kuang-Hao

    2015-01-01

    A low-power biosignal acquisition and classification system for body sensor networks is proposed. The proposed system consists of three main parts: 1) a high-pass sigma delta modulator-based biosignal processor (BSP) for signal acquisition and digitization, 2) a low-power, super-regenerative on-off keying transceiver for short-range wireless transmission, and 3) a digital signal processor (DSP) for electrocardiogram (ECG) classification. The BSP and transmitter circuits, which are the body-end circuits, can be operated for over 80 days using two 605 mAH zinc-air batteries as the power supply; the power consumption is 586.5 μW. As for the radio frequency receiver and DSP, which are the receiving-end circuits that can be integrated in smartphones or personal computers, power consumption is less than 1 mW. With a wavelet transform-based digital signal processing circuit and a diagnosis control by cardiologists, the accuracy of beat detection and ECG classification are close to 99.44% and 97.25%, respectively. All chips are fabricated in TSMC 0.18-μm standard CMOS process. PMID:25561446

  2. MOCA: A Low-Power, Low-Cost Motion Capture System Based on Integrated Accelerometers

    Directory of Open Access Journals (Sweden)

    Elisabetta Farella

    2007-01-01

    Full Text Available Human-computer interaction (HCI and virtual reality applications pose the challenge of enabling real-time interfaces for natural interaction. Gesture recognition based on body-mounted accelerometers has been proposed as a viable solution to translate patterns of movements that are associated with user commands, thus substituting point-and-click methods or other cumbersome input devices. On the other hand, cost and power constraints make the implementation of a natural and efficient interface suitable for consumer applications a critical task. Even though several gesture recognition solutions exist, their use in HCI context has been poorly characterized. For this reason, in this paper, we consider a low-cost/low-power wearable motion tracking system based on integrated accelerometers called motion capture with accelerometers (MOCA that we evaluated for navigation in virtual spaces. Recognition is based on a geometric algorithm that enables efficient and robust detection of rotational movements. Our objective is to demonstrate that such a low-cost and a low-power implementation is suitable for HCI applications. To this purpose, we characterized the system from both a quantitative point of view and a qualitative point of view. First, we performed static and dynamic assessment of movement recognition accuracy. Second, we evaluated the effectiveness of user experience using a 3D game application as a test bed.

  3. Ultra low power CMOS-based sensor for on-body radiation dose measurements

    KAUST Repository

    Arsalan, Muhammad

    2012-03-01

    For the first time, a dosimeter employing two floating gate radiation field effect transistors (FGRADFET) and operating at mere 0.1 V is presented. The novel dosimeter requires no power during irradiation and consumes only 1 μ Wduring readout. Besides the low power operation, structural changes at the device level have enhanced the sensitivity of the dosimeter considerably as compared to previous designs. The dosimeter is integrated with a wireless transmitter chip, thus eliminating all unwanted communication and power cables. It has been realized monolithically in DALSA\\'s 0.8 μ m complementary metal-oxide-semiconductor process and characterized with X-ray and γ-ray sources. A maximum sensitivity of 5 mV/rad for X-rays and 1.1 mV/rad for gamma;-rays have been achieved in measurements. Due to its small size, low-power, and wireless operation, the design is highly suitable for miniaturized, wearable, and battery operated dosimeters intended for radiotherapy and space applications. © 2012 IEEE.

  4. A low power dual-band multi-mode RF front-end for GNSS applications

    Energy Technology Data Exchange (ETDEWEB)

    Zhang Hao; Li Zhiqun; Wang Zhigong, E-mail: zhhseu@gmail.com [Institute of RF- and OE- ICs, Southeast University, Nanjing 210096 (China)

    2010-11-15

    A CMOS dual-band multi-mode RF front-end for the global navigation satellite system receivers of all GPS, Bei-Dou, Galileo and Glonass systems is presented. It consists of a reconfigurable low noise amplifier (LNA), a broadband active balun, a high linearity mixer and a bandgap reference (BGR) circuit. The effect of the input parasitic capacitance on the input impedance of the inductively degenerated common source LNA is analyzed in detail. By using two different LC networks at the input port and the switched capacitor at the output port, the LNA can work at two different frequency bands (1.2 GHz and 1.5 GHz) under low power consumption. The active balun uses a hybrid-connection structure to achieve high bandwidth. The mixer uses the multiple gated transistors technique to acquire a high linearity under low power consumption but does not deteriorate other performances. The measurement results of the proposed front-end achieve a noise figure of 2.1/2.0 dB, again of 33.9/33.8 dB and an input 1-dB compression point of 0/1 dBm at 1227.6/1575.42 MHz. The power consumption is about 16 mW under a 1.8 V power supply.

  5. Controlling the phase locking of stochastic magnetic bits for ultra-low power computation

    Science.gov (United States)

    Mizrahi, Alice; Locatelli, Nicolas; Lebrun, Romain; Cros, Vincent; Fukushima, Akio; Kubota, Hitoshi; Yuasa, Shinji; Querlioz, Damien; Grollier, Julie

    2016-07-01

    When fabricating magnetic memories, one of the main challenges is to maintain the bit stability while downscaling. Indeed, for magnetic volumes of a few thousand nm3, the energy barrier between magnetic configurations becomes comparable to the thermal energy at room temperature. Then, switches of the magnetization spontaneously occur. These volatile, superparamagnetic nanomagnets are generally considered useless. But what if we could use them as low power computational building blocks? Remarkably, they can oscillate without the need of any external dc drive, and despite their stochastic nature, they can beat in unison with an external periodic signal. Here we show that the phase locking of superparamagnetic tunnel junctions can be induced and suppressed by electrical noise injection. We develop a comprehensive model giving the conditions for synchronization, and predict that it can be achieved with a total energy cost lower than 10‑13 J. Our results open the path to ultra-low power computation based on the controlled synchronization of oscillators.

  6. Strategies for the commercial introduction of modular low power fuel cells

    Energy Technology Data Exchange (ETDEWEB)

    Miranda, H.V.; Laufer, A. [EnergiaH, Rio de Janeiro (Brazil); Miranda, P.E.V. [Coppe-Federal Univ., Rio de Janeiro (Brazil). Hydrogen Lab.

    2010-07-01

    The reality of the infrastructure in emerging economies brings the opportunity to build up a hydrogen compatible economy. For the Brazilian case, the fast development in many fields coexists with a considerable amount of potential renewable fuels available. Costs of energy distribution and of power grid maintenance throughout a continental size country may lead to a distributed generation system based in a diversified fuels matrix. This pathway drives attention to simpler low power fuel cell devices, with easier maintenance procedures, friendly integration with small power demands, and the capability of being applied separately or integrated to deliver higher power demands. Big cities and small distant agriculture based locations, such as Rio de Janeiro or rain forest extractive communities, could be able to produce fuel and energy in their own infrastructure projects. This article presents a market roadmap for the commercial introduction of direct oxidation type solid oxide fuel cells in Brazil, specifying fuel cell technological features and the specificities for each type of application, either in grid connected or in stand alone low power electric energy generation. (orig.)

  7. IEEE-802.15.4-based low-power body sensor node with RF energy harvester.

    Science.gov (United States)

    Tran, Thang Viet; Chung, Wan-Young

    2014-01-01

    This paper proposes the design and implementation of a low-voltage and low-power body sensor node based on the IEEE 802.15.4 standard to collect electrocardiography (ECG) and photoplethysmography (PPG) signals. To achieve compact size, low supply voltage, and low power consumption, the proposed platform is integrated into a ZigBee mote, which contains a DC-DC booster, a PPG sensor interface module, and an ECG front-end circuit that has ultra-low current consumption. The input voltage of the proposed node is very low and has a wide range, from 0.65 V to 3.3 V. An RF energy harvester is also designed to charge the battery during the working mode or standby mode of the node. The power consumption of the proposed node reaches 14 mW in working mode to prolong the battery lifetime. The software is supported by the nesC language under the TinyOS environment, which enables the proposed node to be easily configured to function as an individual health monitoring node or a node in a wireless body sensor network (BSN). The proposed node is used to set up a wireless BSN that can simultaneously collect ECG and PPG signals and monitor the results on the personal computer. PMID:25227063

  8. Hardware-efficient low-power image processing system for wireless capsule endoscopy.

    Science.gov (United States)

    Turcza, Pawel; Duplaga, Mariusz

    2013-11-01

    This paper presents the design of a hardware-efficient, low-power image processing system for next-generation wireless endoscopy. The presented system is composed of a custom CMOS image sensor, a dedicated image compressor, a forward error correction (FEC) encoder protecting radio transmitted data against random and burst errors, a radio data transmitter, and a controller supervising all operations of the system. The most significant part of the system is the image compressor. It is based on an integer version of a discrete cosine transform and a novel, low complexity yet efficient, entropy encoder making use of an adaptive Golomb-Rice algorithm instead of Huffman tables. The novel hardware-efficient architecture designed for the presented system enables on-the-fly compression of the acquired image. Instant compression, together with elimination of the necessity of retransmitting erroneously received data by their prior FEC encoding, significantly reduces the size of the required memory in comparison to previous systems. The presented system was prototyped in a single, low-power, 65-nm field programmable gate arrays (FPGA) chip. Its power consumption is low and comparable to other application-specific-integrated-circuits-based systems, despite FPGA-based implementation.

  9. Role of PKC isozymes in low-power light-stimulated proliferation of cultured skin cells

    Science.gov (United States)

    Grossman, Nili; Kleitman, Vered; Meller, Julia; Kaufmann, Roland; Akgun, Nermin; Ruck, Angelika; Livneh, Etta; Lubart, Rachel

    2000-11-01

    Exposure of cultured skin cells to low power visible light leads to a transiently stimulated proliferation. Facilitation of this response requires the presence of active PKC, elevation of intracellular calcium, and involves reactive oxygen species. In the present study, the role of PKC(alpha) and PCK(eta) was examined using paired murine fibroblasts, differing in the level of these isozymes expression. The ability of the cells to respond to low power UVA light or HeNe laser by stimulated proliferation was correlated with an active state or overexpression of PKC(alpha) , but not PKC(eta) . A parallel response was obtained in cells that were loaded with A1PcS4 before photosensitization. Whenever this latter treatment caused a light-stimulated inhibition, it was accompanied by the intracellular calcium and photosensitizer dynamics typical of the effect of PDT on rate epithelial cells. Accordingly, added antioxidants that suppressed light-stimulated proliferation also suppressed this light-stimulated inhibition. The model systems employed in this study are the first to demonstrate the specific effect of PKC isozymes on light-stimulated proliferation, in relation to oxidative stress, and indicate their dual role in light-tissue interaction.

  10. Ultra-low-power carbon nanotube FET-based quaternary logic gates

    Science.gov (United States)

    Sharifi, Fazel; Moaiyeri, Mohammad Hossein; Navi, Keivan; Bagherzadeh, Nader

    2016-09-01

    This paper presents low-power carbon nanotube field-effect transistor (CNTFET)-based quaternary logic circuits. The proposed quaternary circuits are designed based on the CNTFET unique properties, such as the same carrier mobility for N- and P-type devices and also providing desirable threshold voltages by adopting proper diameters for the nanotubes. In addition, no paths exist between supply and ground rails in the steady states of the proposed designs, which eliminates the ON state static current and also the stacking technique is utilised in order to significantly reduce the leakage currents. The results of the simulations, conducted using Synopsys HSPICE with the standard 32 nm CNTFET technology, confirm the significantly lower power consumption, higher energy efficiency and lower sensitivity to process variation of the proposed designs compared to the state-of-the-art quaternary logic circuits. The proposed quaternary logic circuits have on average 92, 99 and 91% less total power, static power and PDP, respectively, compared with the most low-power and energy-efficient CNTFET-based quaternary logic circuits, recently presented in the literature.

  11. Operation Characteristics Optimization of Low Power Three-Phase Asynchronous Motors

    Directory of Open Access Journals (Sweden)

    VLAD, I.

    2014-02-01

    Full Text Available Most published papers on low power asynchronous motors were aimed to achieve better operational performances in different operating conditions. The optimal design of the general-purpose motors requires searching and selecting an electric machine to meet minimum operating costs criterion and certain customer imposed restrictive conditions. In this paper, there are many significant simulations providing qualitative and quantitative information on reducing active and reactive energy losses in motors, and on parameters and constructive solution. The optimization study applied the minimal operating costs criterion, and it took into account the starting restrictive conditions. Thirteen variables regarding electromagnetic stresses and main constructive dimensions were considered. The operating costs of the optimized motor decreased with 25.6%, as compared to the existing solution. This paper can be a practical and theoretical support for the development and implementation of modern design methods, based on theoretical and experimental study of stationary and transient processes in low power motors, to increase efficiency and power factor.

  12. An Efficient Adiabatic CMOS Circuit Design Approach for Low Power Applications

    Directory of Open Access Journals (Sweden)

    Ashish Raghuwanshi

    2013-09-01

    Full Text Available One of the key issues in CMOS circuit design is the large amount of power being dissipated in the circuits. Energy recovering circuitry based on adiabatic principles is a relatively new technique used to implement low power dissipating circuits. By recycling the charge at capacitive nodes in the circuit, adiabatic logic families can achieve very low power dissipation. In this paper we had design and simulate the Inverter, Two-Input Nand gate, Two-Input Nor gate, Two-Input Xor gate, 2:1 Multiplexer on the basis of CMOS Logic and Adiabatic Switching logic using 180nm CMOS technology in Cadence design environment. Two adiabatic families are used in this work, Oneis the Positive Feedback Adiabatic Logic (PFAL and the other is the Efficient Charge Recovery Logic (ECRL Finally, the analysis of the average dynamic power dissipation with respect to the frequency and the load capacitance was done to show the amount of power dissipated by the CMOS, PFAL and ECRL family. The results shows that power saving of adiabatic circuit can reach more than 90% as compare to conventional static CMOS logic

  13. A Sub Threshold Source Coupled Logic Based Design of Low Power CMOS Analog Multiplexer

    Directory of Open Access Journals (Sweden)

    G.Deepika

    2014-08-01

    Full Text Available A novel approach for designing Ultra Low Power and wide dynamic range circuit for multiplexing analog signals is presented. The design operates in weak i nversion (Sub threshold region and uses Source - Coupled Logic ( SCL circuit. The bias current of t he SCL gates is varied to scale down linearly the p ower consumption and the operating frequency. The multip lexer design employs CMOS transistors as transmission gate with dynamic threshold voltage. T he design exhibits low power dissipation, high dynamic range and good linearity. The design was im plemented in 180 nm technology and was operated at a supply voltage of 400 mV with a bias current rang ing in the order of few Pico-amperes. The ON and OFF resistance of the transmission gate achieved we re 27 ohms and 10 M ohms respectively. The power dissipation achieved is around 0.79 μ W for a dynami c range of 1μ V to 0.4 V.

  14. Optimally designed moderately inverted double gate SOI MOSFETs for low-power RFICs

    International Nuclear Information System (INIS)

    A design methodology to significantly enhance peak values of two key analogue/RF performance metrics-–gm2/Ids and gmfT/Ids—without degrading linearity metric (VIP3) in moderately inverted MOSFETs is demonstrated. An impressive improvement of 22% in gm2/Ids and more than twice in gmfT/Ids can be achieved by adopting optimal underlap source/drain (S/D) architecture instead of a conventional abrupt S/D design. Apart from the well-known reduction in the voltage gain (gm/gds), it is demonstrated that linearity degradation is expected to be a major bottleneck for scaling low-power and energy efficient devices into the nanometre regime. The optimal range of S/D profile parameters is identified by evaluating process and performance trade-offs associated with the underlap doping profile. A parameter sensitivity analysis shows that an optimally designed underlap S/D MOSFET exhibits greater tolerance to the variation of parameters as compared to conventional abrupt S/D devices. The results are significant for the design of low-power RFICs with advanced MOSFETs in emerging technologies. (paper)

  15. Low Power Consumption Laser for Next Generation Miniature Optical Spectrometers for Trace Gas Analysis

    Science.gov (United States)

    Forouhar, S.; Frez, C.; Franz, K. J.; Ksendzov, A.; Qiu, Y.; Soibel, K. A.; Chen, J.; Hosoda, T.; Kipshidze, G.; Shterengas, L.; Belenky, G.

    2011-01-01

    The air quality of any manned spacecraft needs to be continuously monitored in order to safeguard the health of the crew. Air quality monitoring grows in importance as mission duration increases. Due to the small size, low power draw, and performance reliability, semiconductor laser-based instruments are viable candidates for this purpose. Achieving a minimum instrument size requires lasers with emission wavelength coinciding with the absorption of the fundamental absorption lines of the target gases, which are mostly in the 3.0-5.0 mu m wavelength range. In this paper we report on our progress developing high wall plug efficiency type-I quantum-well GaSb-based diode lasers operating at room temperatures in the spectral region near 3.0-3.5 mu m and quantum cascade (QC) lasers in the 4.0-5.0 mu m range. These lasers will enable the development of miniature, low-power laser spectrometers for environmental monitoring of the spacecraft

  16. Low-power non-volatile spintronic memory: STT-RAM and beyond

    Science.gov (United States)

    Wang, K. L.; Alzate, J. G.; Khalili Amiri, P.

    2013-02-01

    The quest for novel low-dissipation devices is one of the most critical for the future of semiconductor technology and nano-systems. The development of a low-power, universal memory will enable a new paradigm of non-volatile computation. Here we consider STT-RAM as one of the emerging candidates for low-power non-volatile memory. We show different configurations for STT memory and demonstrate strategies to optimize key performance parameters such as switching current and energy. The energy and scaling limits of STT-RAM are discussed, leading us to argue that alternative writing mechanisms may be required to achieve ultralow power dissipation, a necessary condition for direct integration with CMOS at the gate level for non-volatile logic purposes. As an example, we discuss the use of the giant spin Hall effect as a possible alternative to induce magnetization reversal in magnetic tunnel junctions using pure spin currents. Further, we concentrate on magnetoelectric effects, where electric fields are used instead of spin-polarized currents to manipulate the nanomagnets, as another candidate solution to address the challenges of energy efficiency and density. The possibility of an electric-field-controlled magnetoelectric RAM as a promising candidate for ultralow-power non-volatile memory is discussed in the light of experimental data demonstrating voltage-induced switching of the magnetization and reorientation of the magnetic easy axis by electric fields in nanomagnets.

  17. Low-Power Analog Processing for Sensing Applications: Low-Frequency Harmonic Signal Classification

    Directory of Open Access Journals (Sweden)

    Sina Balkir

    2013-07-01

    Full Text Available A low-power analog sensor front-end is described that reduces the energy required to extract environmental sensing spectral features without using Fast Fouri´er Transform (FFT or wavelet transforms. An Analog Harmonic Transform (AHT allows selection of only the features needed by the back-end, in contrast to the FFT, where all coefficients must be calculated simultaneously. We also show that the FFT coefficients can be easily calculated from the AHT results by a simple back-substitution. The scheme is tailored for low-power, parallel analog implementation in an integrated circuit (IC. Two different applications are tested with an ideal front-end model and compared to existing studies with the same data sets. Results from the military vehicle classification and identification of machine-bearing fault applications shows that the front-end suits a wide range of harmonic signal sources. Analog-related errors are modeled to evaluate the feasibility of and to set design parameters for an IC implementation to maintain good system-level performance. Design of a preliminary transistor-level integrator circuit in a 0:µm complementary metal-oxide-silicon (CMOS integrated circuit process showed the ability to use online self-calibration to reduce fabrication errors to a sufficiently low level. Estimated power dissipation is about three orders of magnitude less than similar vehicle classification systems that use commercially available FFT spectral extraction.

  18. Low Power Analysis of Network-Level On-chip communication using Asynchronous AMBA protocol

    Directory of Open Access Journals (Sweden)

    E. Sakthivel

    2012-07-01

    Full Text Available Network on-chip (NoC is a novel structuraldesign template, which can be defied for complicatedsystem level on-chip design. NoC has a potential tolimit and present the bus-based communication. In thispaper, the crisis to discuss is Low power consumptionin an Asynchronous Network on-chip (NoC levelcommunication. NoC is implemented using FPGAwhich has less fabrication cost and reduces thecomplexity. An Asynchronous NoC has beenimplemented in Spartan kit using Xilinx FPGA ISEtools and its network interface is AdvancedMicrocontroller Bus Architecture (AMBA whichfeatures numerous bus masters and a sole clock edgeevolution and so on. Here the AMBA highperformance 32-bit AHB bus is employed in which ithas a high clock frequency system and it is the heart ofour bus system. To accomplish low power consumptionby interfacing SoC with AMBA- AHB protocol. TheAHB model and an Asynchronous NoC are employedand executed using VHDL programming module

  19. THE EFFECT OF LOW POWER GLASSES AT CLOSE DISTANCES ON VISUAL PERFORMANCE.

    Science.gov (United States)

    Vidal-López, Joaquín; Javaloyes-Moreno, Beatriz; Benlloch-Fornés, Josefa

    2015-10-01

    The purpose of this study was to reveal if the use of low power ophthalmic glasses (diopter values within the ± 1.00D range) in ophthalmic care may be beneficial for the treatment of low refractive vision disorders. 40 university students (10 men, 30 women), who used low power glasses at close distances (for reading on paper or on a computer screen: 40-60 centimeters approximately), voluntarily took part in this study. Ages of the participants ranged from 20 to 43 years (M = 24.9, SD = 4.4). Mean spherical refractive error was -0.38 diopters (SD = 0.49; range= -1.00-0.88). A yes/no Signal Detection procedure was used to assess whether the participants' visual sensitivity (d') or criterion of response (c) changed when they used the optical correction. There were no changes in visual sensitivity index, but significant changes in criterion of response were observed when the students used their optical correction. Changes in the criterion of response suggested the presence of a placebo effect.

  20. Uncooled 17 μm ¼ VGA IRFPA development for compact and low power systems

    Science.gov (United States)

    Robert, P.; Tissot, J.; Pochic, D.; Gravot, V.; Bonnaire, F.; Clerambault, H.; Durand, A.; Tinnes, S.

    2012-11-01

    The high level of accumulated expertise by ULIS and CEA/LETI on uncooled microbolometers made from amorphous silicon enables ULIS to develop ¼ VGA IRFPA formats with 17μm pixel-pitch to enable the development of small power, small weight (SWAP) and high performance IR systems. ROIC architecture will be described where innovations are widely on-chip implemented to enable an easier operation by the user. The detector configuration (integration time, windowing, gain, scanning direction…), is driven by a standard I²C link. Like most of the visible arrays, the detector adopts the HSYNC/VSYNC free-run mode of operation driven with only one master clock (MC) supplied to the ROIC which feeds back pixel, line and frame synchronizations. On-chip PROM memory for customer operational condition storage is available for detector characteristics. Low power consumption has been taken into account and less than 60 mW is possible in analog mode at 60 Hz and design. This technology node associated with advanced packaging technique, paves the way to compact low power system.

  1. RELEVANCE OF GROOVED NMOSFETS IN ULTRA DEEP SUBMICRON REGION IN LOW POWER APPLICATIONS

    Directory of Open Access Journals (Sweden)

    Subhra Dhar

    2011-10-01

    Full Text Available To manage the increasing static leakage in low power applications, solutions for leakage reduction aresought at the device design and process technology levels. In this paper, 90nm, 70nm and 50 nm groovedgatenMOS devices are simulated using Silvaco device simulator. By changing the corner angle andadjusting few structural parameters, static leakage reduction is achieved in grooved nMOSFETS inultralow power applications. The simulation results show that leakage contributing currents like thesubthreshold current, punchthrough current and tunneling leakage current are reduced. The oxidethickness can be increased without increase in the gate induced drain leakage current, and ON-OFFcurrent ratio is improved and maintained constant even in the deep submicron region. This study can behelpful for low power applications as the static leakage is reduced drastically, as well as be applicable tohigh speed devices as the ON current is maintained at a constant value. The results are compared withthose of corresponding conventional planar devices to bring out the achievements of this work.

  2. A Low Power VITERBI Decoder Design With Minimum Transition Hybrid Register Exchange Processing For Wireless Applications

    Directory of Open Access Journals (Sweden)

    S. L. Haridas

    2010-12-01

    Full Text Available This work proposes the low power implementation of Viterbi Decoder. Majority of viterbi decoder designs in the past use simple Register Exchange or Traceback method to achieve very high speed and low power decoding respectively, but it suffers from both complex routing and high switching activity.Here simplification is made in survivor memory unit by storing only m-1 bits to identify previous state in the survivor path, and by assigning m-1 registers to decision vectors. This approach eliminates unnecessary shift operations. Also for storing the decoded data only half memory is required than register exchange method. In this paper Hybrid approach that combines both Traceback and Register Exchange schemes has been applied to the viterbi decoder design. By using distance properties of encoder we further modified to minimum transition hybrid register exchange method. It leads to lower dynamic power consumption because of lower switching activity. Dynamic power estimation obtained through gate level simulation indicates that the proposed design reduces the power dissipation of a conventional viterbi decoder design by 30%.

  3. A Low Power VITERBI Decoder Design With Minimum Transition Hybrid Register Exchange Processing For Wireless Applications

    Directory of Open Access Journals (Sweden)

    S. L. Haridas

    2010-12-01

    Full Text Available This work proposes the low power implementation of Viterbi Decoder. Majority of viterbi decoder designs in the past use simple Register Exchange or Trace back method to achieve very high speed and low power decoding respectively, but it suffers from both complex routing and high switching activity.Here simplification is made in survivor memory unit by storing only m-1 bits to identify previous state in the survivor path, and by assigning m-1 registers to decision vectors. This approach eliminates unnecessary shift operations. Also for storing the decoded data only half memory is required than register exchange method. In this paper Hybrid approach that combines both Trace back and Register Exchange schemes has been applied to the viterbi decoder design. By using distance properties of encoder we further modified to minimum transition hybrid register exchange method. It leads to lower dynamic power consumption because of lower switching activity. Dynamic power estimation obtained through gate level simulation indicates that the proposed design reduces the power dissipation of a conventional viterbi decoder design by 30%.

  4. [Analysis of Electric Stress in Human Head in High-frequency Low-power Electromagnetic Environment].

    Science.gov (United States)

    Zhou, Yongjun; Zhang, Hui; Niu, Zhongqi

    2015-04-01

    Action of electromagnetic radiation exerting on human body has been a concerned issue for people. Because electromagnetic waves could generate an electric stress in a discontinuous medium, we used the finite difference time domain (FDTD) as calculation methods to calculate the electric stress and its distribution in human head caused by high-frequency low-power electromagnetic environment, which was generated by dual-band (900 MHz and 1 800 MHz) PIFA antennas with radiated power 1 W, and we then performed the safety evaluation of cell phone radiation from the angle whether the electric stress further reached the human hearing threshold. The result showed that there existed the electric stress at the interface of different permittivity organization caused by the two kinds of high-frequency low-power electromagnetic environment and the maximum electric stress was located at the interface between skin and air of the phone side, and the electric stress peak at skull did not reach the threshold of auditory caused by bone tissue conduction so that it can not produce auditory effects.

  5. Low-power short-range transceivers for sensor network applications (Keynote Address)

    Science.gov (United States)

    Lopez-Villegas, J. M.

    2005-06-01

    Emerging technologies like ZigBee or Ultra Wide Band (UWB) Radio, based on the new standards of the IEEE 802.15 family, will, in a near future, compete with and/or complement Bluetooth technology in the development of Wireless Personal Area Networks (WPAN"s), capable to satisfy the increasing demand of high bit rate data transfer links as well as low power and small size constrains. Nowadays coexistence and interconnectivity of Wireless Local Area Networks (WLAN"s), WPAN"s and mobile phones is just the first step towards the implementation of the so called Ambient Intelligence. The main characteristics of this new paradigm are: ubiquity, transparency, and intelligence. In this context, sensor networks are the first front of the communication chain. Thus, most of the wireless data transfers will take place at very short distances and most of the information flow will be performed at very low rates. To implement the RF transceiver devices constituting sensor networks in an Ambient Intelligence environment, several challenges still need to be solved, among them: packaging (SoP vs. SoC approaches), powering (low power, batteryless systems, energy scavenging) and system architecture (new simplified direct conversion approaches). All these matters will be considered in this work.

  6. Ultra-low-power silicon photonics wavelength converter for phase-encoded telecommunication signals

    Science.gov (United States)

    Lacava, C.; Ettabib, M. A.; Cristiani, I.; Fedeli, J.-M.; Richardson, D. J.; Petropoulos, P.

    2016-03-01

    The development of compact, low power, silicon photonics CMOS compatible components for all-optical signal processing represents a key step towards the development of fully functional platforms for next generation all-optical communication networks. The wavelength conversion functionality at key nodes is highly desirable to achieve transparent interoperability and wavelength routing allowing efficient management of network resources operated with high speed, phase encoded signals. All optical wavelength conversion has already been demonstrated in Si-based devices, mainly utilizing the strong Kerr effect that silicon exhibits at telecommunication wavelengths. Unfortunately, Two Photon Absorption (TPA) and Free Carrier (FC) effects strongly limit their performance, even at moderate power levels, making them unsuitable for practical nonlinear applications. Amorphous silicon has recently emerged as a viable alternative to crystalline silicon (c-Si), showing both an enhanced Kerr as well as a reduced TPA coefficient at telecom wavelengths, with respect to its c-Si counterpart. Here we present an ultra-low power wavelength converter based on a passive, CMOS compatible, 1-mm long amorphous silicon waveguide operated at a maximum pump power level of only 70 mW. We demonstrate TPA-free Four Wave Mixing (FWM)-based wavelength conversion of Binary Phase Shift Keyed (BPSK) and Quadrature Phase Shift Keyed (QPSK) signals at 20 Gbit/s with <1 dB power penalty at BER = 10-5.

  7. A low power high gain UWB LNA in 0.18-μm CMOS

    Institute of Scientific and Technical Information of China (English)

    Cai Li; Fu Zhongqian; Huang Lu

    2009-01-01

    A low power high gain differential UWB low noise amplifier (LNA) operating at 3-5 GHz is presented.A common gate input stage is used for wideband input matching; capacitor cross coupling (CCC) and current reuse techniques are combined to achieve high gain under low power consumption. The prototypes fabricated in 0.18-μm CMOS achieve a peak power gain of 17.5 dB with a -3 dB bandwidth of 2.8-5 GHz, a measured minimum noise figure (NF) of 3.35 dB and -12.6 dBm input-referred compression point at 5 GHz, while drawing 4.4 mA from a 1.8 V supply. The peak power gain is 14 dB under a 4.5 mW power consumption (3 mA from a 1.5 V supply). The proposed differential LNA occupies an area of 1.01 mm~2 including test pads.

  8. Design of Low Power Phase Locked Loop (PLL Using 45NM VLSI Technology

    Directory of Open Access Journals (Sweden)

    Ms. Ujwala A. Belorkar

    2010-06-01

    Full Text Available Power has become one of the most important paradigms of design convergence for multigigahertz communication systems such as optical data links, wireless products, microprocessor &ASIC/SOC designs. POWER consumption has become a bottleneck in microprocessor design. The coreof a microprocessor, which includes the largest power density on the microprocessor. In an effort toreduce the power consumption of the circuit, the supply voltage can be reduced leading to reduction ofdynamic and static power consumption. Lowering the supply voltage, however, also reduces theperformance of the circuit, which is usually unacceptable. One way to overcome this limitation, availablein some application domains, is to replicate the circuit block whose supply voltage is being reduced inorder to maintain the same throughput .This paper introduces a design aspects for low power phaselocked loop using VLSI technology. This phase locked loop is designed using latest 45nm processtechnology parameters, which in turn offers high speed performance at low power. The main noveltyrelated to the 45nm technology such as the high-k gate oxide ,metal-gate and very low-k interconnectdielectric described. VLSI Technology includes process design, trends, chip fabrication, real circuitparameters, circuit design, electrical characteristics, configuration building blocks, switching circuitry,translation onto silicon, CAD, practical experience in layout design

  9. Reliability and availability analysis of low power portable direct methanol fuel cells

    Science.gov (United States)

    Sisworahardjo, N. S.; Alam, M. S.; Aydinli, G.

    This paper presents a methodology for modeling and calculating the reliability and availability of low power portable direct methanol fuel cells (DMFCs). System reliability and availability are critical factors for improving market acceptance and for determining the competitiveness of the low power DMFC. Two techniques have been used for analyzing the system reliability and availability requirements for various system components. Reliability block diagram (RBD) is formed based on the failure rates of irreparable system components. A state-space method is developed to calculate system availability using the Markov model (MM). The state-space method incorporates three different states-operational, derated, and fully faulted states. Since most system components spend their lifetime in performing normal functional task, this research is focused mainly on this operational period. The failure and repair rates for repairable DMFC systems are estimated on the basis of a homogeneous Poisson process (HPP) and exponential distribution. Extensive analytical modeling and simulation study has been performed to verify the effectiveness of the proposed technique.

  10. Design and Implementation of RF Energy Harvesting System for Low-Power Electronic Devices

    Science.gov (United States)

    Uzun, Yunus

    2016-03-01

    Radio frequency (RF) energy harvester systems are a good alternative for energizing of low-power electronics devices. In this work, an RF energy harvester is presented to obtain energy from Global System for Mobile Communications (GSM) 900 MHz signals. The energy harvester, consisting of a two-stage Dickson voltage multiplier circuit and L-type impedance matching circuits, was designed, simulated, fabricated and tested experimentally in terms of its performance. Simulation and experimental works were carried out for various input power levels, load resistances and input frequencies. Both simulation and experimental works have been carried out for this frequency band. An efficiency of 45% is obtained from the system at 0 dBm input power level using the impedance matching circuit. This corresponds to the power of 450 μW and this value is sufficient for many low-power devices. The most important parameters affecting the efficiency of the RF energy harvester are the input power level, frequency band, impedance matching and voltage multiplier circuits, load resistance and the selection of diodes. RF energy harvester designs should be optimized in terms of these parameters.

  11. Design for High Performance, Low Power, and Reliable 3D Integrated Circuits

    CERN Document Server

    Lim, Sung Kyu

    2013-01-01

    This book describes the design of through-silicon-via (TSV) based three-dimensional integrated circuits.  It includes details of numerous “manufacturing-ready” GDSII-level layouts of TSV-based 3D ICs, developed with tools covered in the book. Readers will benefit from the sign-off level analysis of timing, power, signal integrity, and thermo-mechanical reliability for 3D IC designs.  Coverage also includes various design-for-manufacturability (DFM), design-for-reliability (DFR), and design-for-testability (DFT) techniques that are considered critical to the 3D IC design process. Describes design issues and solutions for high performance and low power 3D ICs, such as the pros/cons of regular and irregular placement of TSVs, Steiner routing, buffer insertion, low power 3D clock routing, power delivery network design and clock design for pre-bond testability. Discusses topics in design-for-electrical-reliability for 3D ICs, such as TSV-to-TSV coupling, current crowding at the wire-to-TSV junction and the e...

  12. Architectural optimizations for low-power K-best MIMO decoders

    KAUST Repository

    Mondal, Sudip

    2009-09-01

    Maximum-likelihood (ML) detection for higher order multiple-input-multiple-output (MIMO) systems faces a major challenge in computational complexity. This limits the practicality of these systems from an implementation point of view, particularly for mobile battery-operated devices. In this paper, we propose a modified approach for MIMO detection, which takes advantage of the quadratic-amplitude modulation (QAM) constellation structure to accelerate the detection procedure. This approach achieves low-power operation by extending the minimum number of paths and reducing the number of required computations for each path extension, which results in an order-of-magnitude reduction in computations in comparison with existing algorithms. This paper also describes the very-large-scale integration (VLSI) design of the low-power path metric computation unit. The approach is applied to a 4 × 4, 64-QAM MIMO detector system. Results show negligible performance degradation compared with conventional algorithms while reducing the complexity by more than 50%. © 2009 IEEE.

  13. A scalable and low power VLIW DSP core for embedded system design

    Institute of Scientific and Technical Information of China (English)

    Sheraz Anjum; CHEN Jie; HAN Liang; LIN Chuan; ZHANG Xiao-xiao; SU Ye-hua; Chip Cheng

    2008-01-01

    Aims to provide the block architecture of CoStar3400 DSP that is a high performance, low power and scalable VLIW DSP core, it efficiently deployed a variable-length execution set (VLES) execution model which utilizes the maximum parallelism by allowing multiple address generations and data arithmetic logic units to exe-cute multiple instructions in a single clock cycle. The scalability was provided mainly in using more or less num-ber of functional units according to the intended application. Low power support was added by careful architectur-al design techniques such as fine-grain clock gating and activation of only the required number of control signals at each stage of the pipeline. The said features of the core make it a suitable candidate for many SoC configurations,especially for compute intensive applications such as wire-line and wireless communications, including infrastruc-ture and subscriber communications. The embedded system designers can efficiently use the scalability and VLIW features of the core by scaling the number of execution units according to specific needs of the application to effec-tively reduce the power consumption, chip area and time to market the intended final product.

  14. VGA 17 μm development for compact, low-power systems

    Science.gov (United States)

    Durand, A.; Tissot, J. L.; Robert, P.; Cortial, S.; Roman, C.; Vilain, M.; Legras, O.

    2011-06-01

    The high level of accumulated expertise by ULIS and CEA/LETI on uncooled microbolometers made from amorphous silicon has enabled ULIS to develop VGA IRFPA formats with 17 μm pixel-pitch, hence building up the currently available product catalog. This detector keeps all the innovations developed on the 25 μm pixel-pitch ROIC (detector configuration by serial link, low power consumption and wide electrical dynamic range). The specific appeal of this unit lies in the high spatial resolution it provides. The pixel-pitch reduction turns this TEC-less VGA array into a product well adapted for high resolution and compact systems. Electro-optical performances of this IRFPA are presented hereafter as well as recent performance improvement. We will focus on NETD trade-off with wide thermal dynamic range, as well as the high characteristics uniformity and pixel operability, achieved thanks to the mastering of amorphous silicon technology coupled with the ROIC design. Solar exposure is also taken into account and shows that ULIS amorphous silicon is perfectly well suited to sustain high intensity exposure. This technology node associated with advanced packaging technique paves the way to compact low power system.

  15. Sink-to-Sink Coordination Framework Using RPL: Routing Protocol for Low Power and Lossy Networks

    Directory of Open Access Journals (Sweden)

    Meer M. Khan

    2016-01-01

    Full Text Available RPL (Routing Protocol for low power and Lossy networks is recommended by Internet Engineering Task Force (IETF for IPv6-based LLNs (Low Power and Lossy Networks. RPL uses a proactive routing approach and each node always maintains an active path to the sink node. Sink-to-sink coordination defines syntax and semantics for the exchange of any network defined parameters among sink nodes like network size, traffic load, mobility of a sink, and so forth. The coordination allows sink to learn about the network condition of neighboring sinks. As a result, sinks can make coordinated decision to increase/decrease their network size for optimizing over all network performance in terms of load sharing, increasing network lifetime, and lowering end-to-end latency of communication. Currently, RPL does not provide any coordination framework that can define message exchange between different sink nodes for enhancing the network performance. In this paper, a sink-to-sink coordination framework is proposed which utilizes the periodic route maintenance messages issued by RPL to exchange network status observed at a sink with its neighboring sinks. The proposed framework distributes network load among sink nodes for achieving higher throughputs and longer network’s life time.

  16. Very Low Power Viterbi Decoder Employing Minimum Transition and Exchangeless Algorithms for Multimedia Mobile Communication

    Directory of Open Access Journals (Sweden)

    Prof. S. L. Haridas

    2011-12-01

    Full Text Available A very low power consumption viterbi decoder has been developed by low supply voltage and 0.15 µm CMOS process technology. Significant power reduction can be achieved by modifying the design and implementation of viterbi decoder using conventional techniques traceback and Register Exchange to Hybrid Register Exchange Method (HREM, Minimum Transition Register Exchange Method (MTREM, Minimum Transition Hybrid Register Exchange Method (MTHREM, Register exchangeless Method and Hybrid Register exchangeless Method. By employing the above said schemes such as, HREM, MTREM, MTHREM, Register exchangeless Method and Hybrid Register exchangeless Method; the viterbi decoder achieves a drastic reduction in power consumption below 100 µW at a supply voltage of 1.62 V when the data rate of 5 Mb/s and the bit error rate is less than 10-3. This excellent performance has been paved the way to employing the strong forward error correction and low power consumption portable terminals for personnel communication, mobile multimedia communication and digital audio broadcasting. Implementation insight and general conclusions can particularly benefit from this approach are given.

  17. A low power 2.4 GHz transceiver for ZigBee applications

    Institute of Scientific and Technical Information of China (English)

    Liu Weiyang; Chen Jingjing; Wang Haiyong; Wu Nanjian

    2013-01-01

    This paper presents a low power 2.4 GHz transceiver for ZigBee applications.This transceiver adopts low power system architecture with a low-IF receiver and a direct-conversion transmitter.The receiver consists of a new low noise amplifier (LNA) with a noise cancellation function,a new inverter-based variable gain complex filter (VGCF) for image rejection,a passive quadrature mixer,and a decibel linear programmable gain amplifier (PGA).The transmitter adopts a quadrature mixer and a class-B mode variable gain power amplifier (PA) to reduce power consumption.This transceiver is implemented in 0.18μm CMOS technology.The receiver achieves-95 dBm of sensitivity,28 dBc of image rejection,and-8 dBm of third-order input intercept point (IIP3).The transmitter can deliver a maximum of +3 dBm output power with PA efficiency of 30%.The whole chip area is less than 4.32 mm2.It only consumes 12.63 mW in receiving mode and 14.22 mW in transmitting mode,respectively.

  18. Controlling the phase locking of stochastic magnetic bits for ultra-low power computation

    Science.gov (United States)

    Mizrahi, Alice; Locatelli, Nicolas; Lebrun, Romain; Cros, Vincent; Fukushima, Akio; Kubota, Hitoshi; Yuasa, Shinji; Querlioz, Damien; Grollier, Julie

    2016-01-01

    When fabricating magnetic memories, one of the main challenges is to maintain the bit stability while downscaling. Indeed, for magnetic volumes of a few thousand nm3, the energy barrier between magnetic configurations becomes comparable to the thermal energy at room temperature. Then, switches of the magnetization spontaneously occur. These volatile, superparamagnetic nanomagnets are generally considered useless. But what if we could use them as low power computational building blocks? Remarkably, they can oscillate without the need of any external dc drive, and despite their stochastic nature, they can beat in unison with an external periodic signal. Here we show that the phase locking of superparamagnetic tunnel junctions can be induced and suppressed by electrical noise injection. We develop a comprehensive model giving the conditions for synchronization, and predict that it can be achieved with a total energy cost lower than 10−13 J. Our results open the path to ultra-low power computation based on the controlled synchronization of oscillators. PMID:27457034

  19. Multicolored, Low-Power, Flexible Electrochromic Devices Based on Ion Gels.

    Science.gov (United States)

    Moon, Hong Chul; Kim, Chang-Hyun; Lodge, Timothy P; Frisbie, C Daniel

    2016-03-01

    Ion gels composed of a copolymer and a room temperature ionic liquid are versatile solid-state electrolytes with excellent features including high ionic conductivity, nonvolatility, easily tunable mechanical properties, good flexibility and solution processability. Ion gels can be functionalized by incorporating redox-active species such as electrochemiluminescent (ECL) luminophores or electrochromic (EC) dyes. Here, we enhance the functionality of EC gels for realizing multicolored EC devices (ECDs), either by controlling the chemical equilibrium between a monomer and dimer of a colored EC species, or by modifying the molecular structures of the EC species. All devices in this work are conveniently fabricated by a "cut-and-stick" strategy, and require very low power for maintaining the colored state [i.e., 90 μW/cm(2) (113 μA/cm(2) at -0.8 V) for blue, 4 μW/cm(2) (10 μA/cm(2) at -0.4 V) for green, and 32 μW/cm(2) (79 μA/cm(2) at -0.4 V) for red ECD]. We also successfully demonstrate a patterned, multicolored, flexible ECD on plastic. Overall, these results suggest that gel-based ECDs have significant potential as low power displays in printed electronics powered by thin-film batteries. PMID:26867428

  20. Inactivation of viruses by coherent excitations with a low power visible femtosecond laser

    Directory of Open Access Journals (Sweden)

    Wu T-C

    2007-06-01

    Full Text Available Abstract Background Resonant microwave absorption has been proposed in the literature to excite the vibrational states of microorganisms in an attempt to destroy them. But it is extremely difficult to transfer microwave excitation energy to the vibrational energy of microorganisms due to severe absorption of water in this spectral range. We demonstrate for the first time that, by using a visible femtosecond laser, it is effective to inactivate viruses such as bacteriophage M13 through impulsive stimulated Raman scattering. Results and discussion By using a very low power (as low as 0.5 nj/pulse visible femtosecond laser having a wavelength of 425 nm and a pulse width of 100 fs, we show that M13 phages were inactivated when the laser power density was greater than or equal to 50 MW/cm2. The inactivation of M13 phages was determined by plaque counts and had been found to depend on the pulse width as well as power density of the excitation laser. Conclusion Our experimental findings lay down the foundation for an innovative new strategy of using a very low power visible femtosecond laser to selectively inactivate viruses and other microorganisms while leaving sensitive materials unharmed by manipulating and controlling with the femtosecond laser system.

  1. A Low-Power and Portable Biomedical Device for Respiratory Monitoring with a Stable Power Source

    Directory of Open Access Journals (Sweden)

    Jiachen Yang

    2015-08-01

    Full Text Available Continuous respiratory monitoring is an important tool for clinical monitoring. Associated with the development of biomedical technology, it has become more and more important, especially in the measuring of gas flow and CO2 concentration, which can reflect the status of the patient. In this paper, a new type of biomedical device is presented, which uses low-power sensors with a piezoresistive silicon differential pressure sensor to measure gas flow and with a pyroelectric sensor to measure CO2 concentration simultaneously. For the portability of the biomedical device, the sensors and low-power measurement circuits are integrated together, and the airway tube also needs to be miniaturized. Circuits are designed to ensure the stability of the power source and to filter out the existing noise. Modulation technology is used to eliminate the fluctuations at the trough of the waveform of the CO2 concentration signal. Statistical analysis with the coefficient of variation was performed to find out the optimal driving voltage of the pressure transducer. Through targeted experiments, the biomedical device showed a high accuracy, with a measuring precision of 0.23 mmHg, and it worked continuously and stably, thus realizing the real-time monitoring of the status of patients.

  2. A low power 20 GHz comparator in 90 nm COMS technology

    International Nuclear Information System (INIS)

    A low power 20 GHz CMOS dynamic latched regeneration comparator for ultra-high-speed, low-power analog-to-digital converters (ADCs) is proposed. The time constant in both the tracking and regeneration phases of the latch are analyzed based on the small signal model. A dynamic source-common logic (SCL) topology is adopted in the master-slave latch to increase the tracking and regeneration speeds. Implemented in 90 nm CMOS technology, this comparator only occupies a die area of 65 × 150 μm2 with a power dissipation of 14 mW from a 1.2 V power supply. The measurement results show that the comparator can work up to 20 GHz. Operating with an input frequency of 1 GHz, the circuit can oversample up to 20 Giga-sampling-per-second (GSps) with 5 bits resolution; while operating at Nyquist, the comparator can sample up to 20 GSps with 4 bits resolution. The comparator has been successfully used in a 20 GSps flash ADC and the circuit can be also used in other high speed applications. (semiconductor integrated circuits)

  3. A low power 20 GHz comparator in 90 nm COMS technology

    Science.gov (United States)

    Kai, Tang; Qiao, Meng; Zhigong, Wang; Ting, Guo

    2014-05-01

    A low power 20 GHz CMOS dynamic latched regeneration comparator for ultra-high-speed, low-power analog-to-digital converters (ADCs) is proposed. The time constant in both the tracking and regeneration phases of the latch are analyzed based on the small signal model. A dynamic source-common logic (SCL) topology is adopted in the master-slave latch to increase the tracking and regeneration speeds. Implemented in 90 nm CMOS technology, this comparator only occupies a die area of 65 × 150 μm2 with a power dissipation of 14 mW from a 1.2 V power supply. The measurement results show that the comparator can work up to 20 GHz. Operating with an input frequency of 1 GHz, the circuit can oversample up to 20 Giga-sampling-per-second (GSps) with 5 bits resolution; while operating at Nyquist, the comparator can sample up to 20 GSps with 4 bits resolution. The comparator has been successfully used in a 20 GSps flash ADC and the circuit can be also used in other high speed applications.

  4. Shutdown and low-power operation at commercial nuclear power plants in the United States. Final report

    Energy Technology Data Exchange (ETDEWEB)

    1993-09-01

    The report contains the results of the NRC Staff`s evaluation of shutdown and low-power operations at US commercial nuclear power plants. The report describes studies conducted by the staff in the following areas: Operating experience related to shutdown and low-power operations, probabilistic risk assessment of shutdown and low-power conditions and utility programs for planning and conducting activities during periods the plant is shut down. The report also documents evaluations of a number of technical issues regarding shutdown and low-power operations performed by the staff, including the principal findings and conclusions. Potential new regulatory requirements are discussed, as well as potential changes in NRC programs. A draft report was issued for comment in February 1992. This report is the final version and includes the responses to the comments along with the staff regulatory analysis of potential new requirements.

  5. Low Power, Small Form Factor, High Performance EVA Radio Employing Micromachined Contour Mode Piezoelectric Resonators and Filters Project

    Data.gov (United States)

    National Aeronautics and Space Administration — In Phase I Harmonic Devices proposes to investigate the feasibility of a low-power, low-volume, lightweight, frequency agile, and fault tolerant EVA radio based on...

  6. Design and Development of Low Power Wireless Sensor System for Measurement and Monitoring of Bio-Medical Parameters

    Directory of Open Access Journals (Sweden)

    D. Vishnu Vardhan, K. Soundara Rajan, Y. Narasimha Murthy

    2013-07-01

    Full Text Available This paper presents the design and development of a low power embedded system for the measurement and monitoring of physiological parameters like body temperature, respiration, blood pressure and ECG. The design is developed around a low power microcontroller MSP430 from Texas Instruments. A wireless sensor module is used to transfer the data from microcontroller to the PC and a graphical user interface (GUI is developed to display the measured data in the graphical form.

  7. A Low-Power Integrated Smart Sensor with on-Chip Real-Time Image Processing Capabilities

    Directory of Open Access Journals (Sweden)

    Barbaro Massimo

    2005-01-01

    Full Text Available A low-power, CMOS retina with real-time, pixel-level processing capabilities is presented. Features extraction and edge-enhancement are implemented with fully programmable 1D Gabor convolutions. An equivalent computation rate of 3 GOPS is obtained at the cost of very low-power consumption ( W per pixel, providing real-time performances ( microseconds for overall computation, . Experimental results from the first realized prototype show a very good matching between measures and expected outputs.

  8. An Extremely Low Power Quantum Optical Communication Link for Autonomous Robotic Explorers

    Science.gov (United States)

    Lekki, John; Nguyen, Quang-Viet; Bizon, Tom; Nguyen, Binh; Kojima, Jun

    2007-01-01

    One concept for planetary exploration involves using many small robotic landers that can cover more ground than a single conventional lander. In addressing this vision, NASA has been challenged in the National Nanotechnology Initiative to research the development of miniature robots built from nano-sized components. These robots have very significant challenges, such as mobility and communication, given the small size and limited power generation capability. The research presented here has been focused on developing a communications system that has the potential for providing ultra-low power communications for robots such as these. In this paper an optical communications technique that is based on transmitting recognizable sets of photons is presented. Previously pairs of photons that have an entangled quantum state have been shown to be recognizable in ambient light. The main drawback to utilizing entangled photons is that they can only be generated through a very energy inefficient nonlinear process. In this paper a new technique that generates sets of photons from pulsed sources is described and an experimental system demonstrating this technique is presented. This technique of generating photon sets from pulsed sources has the distinct advantage in that it is much more flexible and energy efficient, and is well suited to take advantage of the very high energy efficiencies that are possible when using nano scale sources. For these reasons the communication system presented in this paper is well suited for use in very small, low power landers and rovers. In this paper a very low power optical communications system for miniature robots, as small as 1 cu cm is addressed. The communication system is a variant of photon counting communications. Instead of counting individual photons the system only counts the arrival of time coincident sets of photons. Using sets of photons significantly decreases the bit error rate because they are highly identifiable in the

  9. A low-power DCO using inverter interlaced cascaded delay cell

    Institute of Scientific and Technical Information of China (English)

    Huang Qiang; Fan Tao; Dai Xiangming; Yuan Guoshun

    2014-01-01

    This paper presents a low-power small-area digitally controlled oscillator (DCO) using an inverters interlaced cascaded delay cell (ⅡCDC).It uses a coarse-fine architecture with binary-weighted delay stages for the delay range and resolution.The coarse-tuning stage of the DCO uses ⅡCDC,which is power and area efficient with low phase noise,as compared with conventional delay cells.The ADPLL with a DCO is fabricated in the UMC 180-nm CMOS process with an active area of 0.071 mm2.The output frequency range is 140-600 MHz at the power supply of 1.8 V.The power consumption is 2.34 mW@a 200 MHz output.

  10. A single lithium-ion battery protection circuit with high reliability and low power consumption

    Institute of Scientific and Technical Information of China (English)

    Jiang Jinguang; Li Sen

    2014-01-01

    A single lithium-ion battery protection circuit with high reliability and low power consumption is proposed.The protection circuit has high reliability because the voltage and current of the battery are controlled in a safe range.The protection circuit can immediately activate a protective function when the voltage and current of the battery are beyond the safe range.In order to reduce the circuit's power consumption,a sleep state control circuit is developed.Additionally,the output frequency of the ring oscillation can be adjusted continuously and precisely by the charging capacitors and the constant-current source.The proposed protection circuit is fabricated in a 0.5 μm mixed-signal CMOS process.The measured reference voltage is 1.19 V,the overvoltage is 4.2 V and the undervoltage is 2.2 V.The total power is about 9μW.

  11. Low-power operation using self-timed circuits and adaptive scaling of the supply voltage

    DEFF Research Database (Denmark)

    Nielsen, Lars Skovby; Niessen, C.; Sparsø, Jens;

    1994-01-01

    of voltage scaling has been used previously in synchronous circuits, and the contributions of the present paper are: 1) the combination of supply scaling and self-timed circuitry which has some unique advantages, and 2) the thorough analysis of the power savings that are possible using this technique.>......Recent research has demonstrated that for certain types of applications like sampled audio systems, self-timed circuits can achieve very low power consumption, because unused circuit parts automatically turn into a stand-by mode. Additional savings may be obtained by combining the self......-timed circuits with a mechanism that adaptively adjusts the supply voltage to the smallest possible, while maintaining the performance requirements. This paper describes such a mechanism, analyzes the possible power savings, and presents a demonstrator chip that has been fabricated and tested. The idea...

  12. A Study of LoRa: Long Range & Low Power Networks for the Internet of Things

    Science.gov (United States)

    Augustin, Aloÿs; Yi, Jiazi; Clausen, Thomas; Townsley, William Mark

    2016-01-01

    LoRa is a long-range, low-power, low-bitrate, wireless telecommunications system, promoted as an infrastructure solution for the Internet of Things: end-devices use LoRa across a single wireless hop to communicate to gateway(s), connected to the Internet and which act as transparent bridges and relay messages between these end-devices and a central network server. This paper provides an overview of LoRa and an in-depth analysis of its functional components. The physical and data link layer performance is evaluated by field tests and simulations. Based on the analysis and evaluations, some possible solutions for performance enhancements are proposed. PMID:27618064

  13. A Study of LoRa: Long Range & Low Power Networks for the Internet of Things

    Directory of Open Access Journals (Sweden)

    Aloÿs Augustin

    2016-09-01

    Full Text Available LoRa is a long-range, low-power, low-bitrate, wireless telecommunications system, promoted as an infrastructure solution for the Internet of Things: end-devices use LoRa across a single wireless hop to communicate to gateway(s, connected to the Internet and which act as transparent bridges and relay messages between these end-devices and a central network server. This paper provides an overview of LoRa and an in-depth analysis of its functional components. The physical and data link layer performance is evaluated by field tests and simulations. Based on the analysis and evaluations, some possible solutions for performance enhancements are proposed.

  14. A Low-Power Scalable Stream Compute Accelerator for General Matrix Multiply (GEMM

    Directory of Open Access Journals (Sweden)

    Antony Savich

    2014-01-01

    play an important role in determining the performance of such applications. This paper proposes a novel efficient, highly scalable hardware accelerator that is of equivalent performance to a 2 GHz quad core PC but can be used in low-power applications targeting embedded systems requiring high performance computation. Power, performance, and resource consumption are demonstrated on a fully-functional prototype. The proposed hardware accelerator is 36× more energy efficient per unit of computation compared to state-of-the-art Xeon processor of equal vintage and is 14× more efficient as a stand-alone platform with equivalent performance. An important comparison between simulated system estimates and real system performance is carried out.

  15. A single lithium-ion battery protection circuit with high reliability and low power consumption

    International Nuclear Information System (INIS)

    A single lithium-ion battery protection circuit with high reliability and low power consumption is proposed. The protection circuit has high reliability because the voltage and current of the battery are controlled in a safe range. The protection circuit can immediately activate a protective function when the voltage and current of the battery are beyond the safe range. In order to reduce the circuit's power consumption, a sleep state control circuit is developed. Additionally, the output frequency of the ring oscillation can be adjusted continuously and precisely by the charging capacitors and the constant-current source. The proposed protection circuit is fabricated in a 0.5 μm mixed-signal CMOS process. The measured reference voltage is 1.19 V, the overvoltage is 4.2 V and the undervoltage is 2.2 V. The total power is about 9 μW. (semiconductor integrated circuits)

  16. A Study of LoRa: Long Range & Low Power Networks for the Internet of Things.

    Science.gov (United States)

    Augustin, Aloÿs; Yi, Jiazi; Clausen, Thomas; Townsley, William Mark

    2016-09-09

    LoRa is a long-range, low-power, low-bitrate, wireless telecommunications system, promoted as an infrastructure solution for the Internet of Things: end-devices use LoRa across a single wireless hop to communicate to gateway(s), connected to the Internet and which act as transparent bridges and relay messages between these end-devices and a central network server. This paper provides an overview of LoRa and an in-depth analysis of its functional components. The physical and data link layer performance is evaluated by field tests and simulations. Based on the analysis and evaluations, some possible solutions for performance enhancements are proposed.

  17. Large area and low power dielectrowetting optical shutter with local deterministic fluid film breakup

    Science.gov (United States)

    Zhao, R.; Cumby, B.; Russell, A.; Heikenfeld, J.

    2013-11-01

    A large area (>10 cm2) and low-power (0.1-10 Hz AC voltage, ˜10's μW/cm2) dielectrowetting optical shutter requiring no pixelation is demonstrated. The device consists of 40 μm interdigitated electrodes covered by fluid splitting features and a hydrophobic fluoropolymer. When voltage is removed, the fluid splitting features initiate breakup of the fluid film into small droplets resulting in ˜80% transmission. Both the dielectrowetting and fluid splitting follow theory, allowing prediction of alternate designs and further improved performance. Advantages include scalability, optical polarization independence, high contrast ratio, fast response, and simple construction, which could be of use in switchable windows or transparent digital signage.

  18. Value of low-power lasers in the treatment of symptomatic spondilosis

    Science.gov (United States)

    Antipa, Ciprian; Moldoveanu, Vladimir; Rusca, Nicolae; Bruckner, Ion I.; Vlaiculescu, Mihaela; Ionescu, Elena; Vasiliu, Virgil V.

    1998-07-01

    Low power laser (LPL) use in the treatment of arthrosic rheumatism is well known. From a total number of 280 patients with symptomatic spondylosis we finally selected 66, with changes of the EEG color mapping. These investigation was done before and after treatment in order to obtain an objective method to appreciate these results. The patients were splitted in laser group (36 patients treated with HeNe and IR diode LPL) and control group (30 patients treated with placebo laser). The results indicate a significant improvement of the symptoms at 77% of the patients from laser group as compared with 33% favorable results at the placebo laser. The EEG mapping improved at 58% patients from laser group as compared with 20% at the control group.

  19. Low-power task scheduling algorithm for large-scale cloud data centers

    Institute of Scientific and Technical Information of China (English)

    Xiaolong Xu; Jiaxing Wu; Geng Yang; Ruchuan Wang

    2013-01-01

    How to effectively reduce the energy consumption of large-scale data centers is a key issue in cloud computing. This pa-per presents a novel low-power task scheduling algorithm (LTSA) for large-scale cloud data centers. The winner tree is introduced to make the data nodes as the leaf nodes of the tree and the final winner on the purpose of reducing energy consumption is selected. The complexity of large-scale cloud data centers is ful y consider, and the task comparson coefficient is defined to make task scheduling strategy more reasonable. Experiments and per-formance analysis show that the proposed algorithm can effec-tively improve the node utilization, and reduce the overal power consumption of the cloud data center.

  20. On the outage capacity of the block fading channel at low-power regime

    KAUST Repository

    Rezki, Zouheir

    2014-06-01

    Outage performance of the M-block fading with additive white Gaussian noise (BF-AWGN) is investigated at low-power regime. We consider delay-constrained constant-rate communications with perfect channel state information (CSI) at both the transmitter and the receiver (CSI-TR), under a short-term power constraint. We show that selection diversity that allocates all the power to the strongest block is asymptotically optimal. Then, we provide a simple characterization of the outage probability in the regime of interest. We quantify the reward due to CSI-TR over the constant-rate constant-power scheme and show that this reward increases with the delay constraint. For instance, for Rayleigh fading, we find that a power gain up to 4.3 dB is achievable. © 2014 IEEE.

  1. A Low Power CMOS Analog Circuit Design for Acquiring Multichannel EEG Signals

    Directory of Open Access Journals (Sweden)

    G.Deepika

    2015-02-01

    Full Text Available EEG signals are the signatures of neural activities and are captured by multiple-electrodes and the signals are recorded from pairs of electrodes. To acquire these multichannel signals a low power CMOS circuit was designed and implemented. The design operates in weak inversion region employing sub threshold source coupled logic. A 16 channel differential multiplexer is designed by utilizing a transmission gate with dynamic threshold logic and a 4 to 16 decoder is used to select the individual channels. The ON and OFF resistance of the transmission gate obtained is 27 ohms and 10 M ohms respectively. The power dissipation achieved is around 337nW for a dynamic range of 1µV to 0.4 V.

  2. Design of ternary low-power Domino JKL flip-flop and its application

    Institute of Scientific and Technical Information of China (English)

    Wang Pengjun; Yang Qiankun; Zheng Xuesong

    2012-01-01

    By researching the ternary flip-flop and the adiabatic Domino circuit,a novel design of low-power ternary Domino JKL flip-flop on the switch level is proposed.First,the switch-level structure of the ternary adiabatic Domino JKL flip-flop is derived according to the switch-signal theory and its truth table.Then the ternary loop operation circuit and ternary reverse loop operation circuit are achieved by employing the ternary JKL flip-flop.Finally,the circuit is simulated by using the Spice tool and the results show that the logic function is correct.The energy consumption of the ternary adiabatic Domino JKL flip-flop is 69% less than its conventional Domino counterpart.

  3. Fabrication and low-power RF test of C-band RF gun

    International Nuclear Information System (INIS)

    A C-band RF gun for compact radiation sources such as high-energy X-ray and terahertz radiation sources is developed at AIST and is designed to work at a frequency of 5.3 GHz. The total length of this equipment is about 1.5 m. An electron beam with a maximum energy of 0.9 MeV can be generated when the peak electric field is 85 MV/m, corresponding to an RF peak power of 600 kW. A coniferous-tree-type carbon nanostructure is used for the field emission cathode. We present the structural design and fabrication of the C-band RF cavity and a low-power RF test of it

  4. Supercontinuum generation in highly nonlinear hexagonal photonic crystal fiber at very low power

    Science.gov (United States)

    Sharma, Mohit; Konar, Swapan; Khan, Kaisar R.

    2015-01-01

    We present the design of a photonic crystal fiber which promises to yield very large optical nonlinearity ˜151 W-1 km-1 at 1.55 μm wavelength. The fiber possesses two zero dispersion points whose locations can be tuned by varying the air hole diameter and hole pitch. The fiber dispersion is anomalous between these two zero dispersion points and its value is moderate. The fiber has been used to numerically simulate optical supercontinuum (SC) generation using low power pump pulses of 50 fs duration at a 1.55-μm wavelength. At the end of 15-cm fiber, SC broadening of about 1200 and 1700 nm can be achieved with pulses of 1 and 5 kW peak power, respectively.

  5. A new bias scheme for a low power consumption ReRAM crossbar array

    Science.gov (United States)

    Sun, Wookyung; Choi, Sujin; Shin, Hyungsoon

    2016-08-01

    This paper proposes a new bias scheme for a crossbar array that can improve the power consumption and read margin. The concept of the newly proposed 5/12 bias scheme is to reduce the bias of the unselected cells for power consumption and the bias of half-selected cells for a reduced line voltage drop of the selected cell. In the 5/12 bias scheme, the unselected word line and bit line are biased to 5 × V app/12 and 7 × V app/12, respectively. The electrical characteristics of the 5/12 bias scheme are evaluated by HSPICE simulations and it is found that appropriate nonlinearity of selector can simultaneously achieve low power consumption and high read margin for 5/12 bias scheme.

  6. An experimental study of energy loss mechanisms and efficiency consideration in the low power dc arcjet

    Science.gov (United States)

    Curran, F. M.

    1985-01-01

    The potential utility of the low power dc arcjet in auxiliary propulsion was investigated. It was indicated that improvements in the areas of stability, energy efficiency, reliability, and electrode erosion are necessary to obtain a useful device. A water-cooled arcjet simulator was tested to investigate both the energy loss mechanisms at the electrodes and the stability of different conventional arcjet configurations in the presence of a vortex flow field. It is shown that in certain configurations only 25 to 30% of the input energy is lost to the electrodes. It is also shown that vortex stabilization is not difficult to obtain in many cases at the flow rates used and that a careful starting procedure is effective in minimizing electrode damage.

  7. An experimental study of energy loss mechanisms and efficiency considerations in the low power dc arcjet

    Science.gov (United States)

    Curran, F. M.

    1985-01-01

    The potential utility of the low power dc arcjet in auxiliary propulsion was investigated. It was indicated that improvements in the areas of stability, energy efficiency, reliability, and electrode erosion are necessary to obtain a useful device. A water-cooled arcjet simulator was tested to investigate both the energy loss mechanisms at the electrodes and the stability of different conventional arcjet configurations in the presence of a vortex flow field. It is shown that in certain configurations only 25 to 30 percent of the input energy is lost to the electrodes. It is also shown that vortex stabilization is not difficult to obtain in many cases at the flow rates used and that a careful starting procedure is effective in minimizing electrode damage.

  8. Very Low-Power Consumption Analog Pulse Processing ASIC for Semiconductor Radiation Detectors

    International Nuclear Information System (INIS)

    We describe a very-low power consumption circuit for processing the pulses from a semiconductor radiation detector. The circuit was designed for use with a cadmium zinc telluride (CZT) detector for unattended monitoring of stored nuclear materials. The device is intended to be battery powered and operate at low duty-cycles over a long period of time. This system will provide adequate performance for medium resolution gamma-ray pulse-height spectroscopy applications. The circuit incorporates the functions of a charge sensitive preamplifier, shaping amplifier, and peak sample and hold circuit. An application specific integrated circuit (ASIC) version of the design has been designed, built and tested. With the exception of the input field effect transistor (FET), the circuit is constructed using bipolar components. In this paper the design philosophy and measured performance characteristics of the circuit are described

  9. PERFORMANCE ANALYSIS OF HIGH EFFICIENT AND LOW POWER ARCHITECTURE FOR FUZZY BASED IMAGE FUSION

    Directory of Open Access Journals (Sweden)

    S. Anbumozhi

    2014-01-01

    Full Text Available Image fusion based on wavelet transform is the most commonly used image fusion method, which fuses the source images’ information in wavelet domain according to some fusion rules. But because of the uncertainties of the source images’ contributions to the fused image, how to design a good fusion rule to integrate as much information as possible into the fused image becomes the most important problem. This study proposed a image fusion algorithm based on wavelet transform and fuzzy reasoning. The edges in source images are detected using set of fuzzy rules. The hardware architecture for fuzzy based image fusion is proposed. This proposed hardware architecture reduces the hardware utilizations and best suitable for low power applications. The design possesses only two line memory buffers with very low computational complexity, thereby reducing the hardware cost and appropriate for several real-time applications. The proposed hardware architecture consumes 4179 gates and power consumption of 203.27 mW.

  10. Low-Power Maximum a Posteriori (MAP Algorithm for WiMAX Convolutional Turbo Decoder

    Directory of Open Access Journals (Sweden)

    Chitralekha Ngangbam

    2013-05-01

    Full Text Available We propose to design a Low-Power Memory-Reduced Traceback MAP iterative decoding of convolutional turbo code (CTC which has large data access with large memories consumption and verify the functionality by using simulation tool. The traceback maximum a posteriori algorithm (MAP decoding provides the best performance in terms of bit error rate (BER and reduce the power consumption of the state metric cache (SMC without losing the correction performance. The computation and accessing of different metrics reduce the size of the SMC with no requires complicated reversion checker, path selection, and reversion flag cache. Radix-2*2 and radix-4 traceback structures provide a tradeoff between power consumption and operating frequency for double-binary (DB MAP decoding. These two traceback structures achieve an around 25% power reduction of the SMC, and around 12% power reduction of the DB MAP decoders for WiMAX standard

  11. Construction and Testing of a Low-power Cryostat for MARS

    Energy Technology Data Exchange (ETDEWEB)

    Aalseth, Craig E.; Caggiano, Joseph A.; Day, Anthony R.; Fast, James E.; Fuller, Erin S.

    2007-10-01

    A low-power cryostat was designed and built for the Multi-sensor Airborne Radiation Survey (MARS) project for the purpose of housing a close-packed high-purity germanium (HPGe) detector array of 14 HPGe detectors. The power consumption of the cold mass in the cryostat was measured to be 4.07(11) watts, sufficient for 5.5 days of continuous operation using only 8 liters of liquid nitrogen. Temperatures throughout the cryostat were measured by platinum resistance temperature detectors. These measurements were used to determine the emissivity of the copper used in the floating radiation shield and outer cryostat wall, which was constructed using chemically cleaned and passivated copper metal. Using a PNNL-developed passivation process, an emissivity of 2.5(3)% was achieved for copper.

  12. Low Power Design of High Speed CMOS Pulse Stream Neuron Circuit

    Institute of Scientific and Technical Information of China (English)

    陈继伟; 石秉学

    2000-01-01

    A new pulse stream neuron circuit is presented, which can be obtained in the digital CMOS process and combines both the merits of digital circuits and analog ones. The output is expressed by the frequency of the pulses with transfer characteristic, which is correspondent with the ideal sigmoid curve perfectly. Moreover, the pulse-active strategy is introduced into the design of this CMOS pulse stream neuron circuit for the first time in order to reduce the power dissipation, which is applicable to the low-power design of mixed-signal circuits,too. A simple technical process and compact architecture make this circuit work at a higher speed and with lower power dissipation and smaller area.

  13. Design of Static Flip-Flops for Low-Power Digital Sequential Circuits

    Directory of Open Access Journals (Sweden)

    E. Jaya Kumar

    2015-12-01

    Full Text Available In this paper, we correlated various Master and slave flip-flops i.e., single edge triggered flipflops. The low-power flip-flops have place utmost necessary elements all the range of the constructing static or successive circuits. We accomplish the comparison for their performance, Delay, Rise time, Fall Time and Power dissipation. Because Power confide in the number of transistors in the circuits, so we are comparing and calculating the number of transistors of the each flip-flops. Analysis of a static/sequential circuits is done by Linear Feed Back Shift Register (LFSR using 45nm Technology with 5MHZ frequencies and their performance analysis.

  14. Ultra-low-power wireless transmitter for neural prostheses with modified pulse position modulation.

    Science.gov (United States)

    Goodarzy, Farhad; Skafidas, Stan E

    2014-01-01

    An ultra-low-power wireless transmitter for embedded bionic systems is proposed, which achieves 40 pJ/b energy efficiency and delivers 500 kb/s data using the medical implant communication service frequency band (402-405 MHz). It consumes a measured peak power of 200 µW from a 1.2 V supply while occupying an active area of 0.0016 mm(2) in a 130 nm technology. A modified pulse position modulation technique called saturated amplified signal is proposed and implemented, which can reduce the overall and per bit transferred power consumption of the transmitter while reducing the complexity of the transmitter architectures, and hence potentially shrinking the size of the implemented circuitry. The design is capable of being fully integrated on single-chip solutions for surgically implanted bionic systems, wearable devices and neural embedded systems. PMID:26609374

  15. A Study of LoRa: Long Range & Low Power Networks for the Internet of Things.

    Science.gov (United States)

    Augustin, Aloÿs; Yi, Jiazi; Clausen, Thomas; Townsley, William Mark

    2016-01-01

    LoRa is a long-range, low-power, low-bitrate, wireless telecommunications system, promoted as an infrastructure solution for the Internet of Things: end-devices use LoRa across a single wireless hop to communicate to gateway(s), connected to the Internet and which act as transparent bridges and relay messages between these end-devices and a central network server. This paper provides an overview of LoRa and an in-depth analysis of its functional components. The physical and data link layer performance is evaluated by field tests and simulations. Based on the analysis and evaluations, some possible solutions for performance enhancements are proposed. PMID:27618064

  16. Hardware-efficient low-power 2-bit ternary ALU design in CNTFET technology

    Science.gov (United States)

    Lata Murotiya, Sneh; Gupta, Anu

    2016-05-01

    This paper proposes a hardware-efficient low-power 2-bit ternary arithmetic logic unit (TALU) design in carbon nano tube field effect transistor technology. The proposed TALU architecture combines adder-subtractor and Ex-OR cell in one cell, thereby reducing the number of transistors by 71% in comparison with other TALU architecture. Further, the proposed TALU is optimised at transistor level with a new pass-transistor logic-based encoder circuit. Hspice simulation results show that the proposed design attains great advantages in power and power-delay product for addition and multiplication operations than reported designs. For instant, at power supply of 0.9 V, the proposed TALU consumes on average 91% and 95% less energy compared to their existing counterparts, for addition and multiplication operations, respectively.

  17. Low-power and shutdown models for the accident sequence precursor (ASP) program

    Energy Technology Data Exchange (ETDEWEB)

    Sattison, M.B.; Thatcher, T.A.; Knudsen, J.K. [Idaho National Engineering Lab., Idaho Falls, ID (United States)] [and others

    1997-02-01

    The US Nuclear Regulatory Commission (NRC) has been using full-power. Level 1, limited-scope risk models for the Accident Sequence Precursor (ASP) program for over fifteen years. These models have evolved and matured over the years, as have probabilistic risk assessment (PRA) and computer technologies. Significant upgrading activities have been undertaken over the past three years, with involvement from the Offices of Nuclear Reactor Regulation (NRR), Analysis and Evaluation of Operational Data (AEOD), and Nuclear Regulatory Research (RES), and several national laboratories. Part of these activities was an RES-sponsored feasibility study investigating the ability to extend the ASP models to include contributors to core damage from events initiated with the reactor at low power or shutdown (LP/SD), both internal events and external events. This paper presents only the LP/SD internal event modeling efforts.

  18. A Low-Power ASIC Signal Processor for a Vestibular Prosthesis.

    Science.gov (United States)

    Töreyin, Hakan; Bhatti, Pamela T

    2016-06-01

    A low-power ASIC signal processor for a vestibular prosthesis (VP) is reported. Fabricated with TI 0.35 μm CMOS technology and designed to interface with implanted inertial sensors, the digitally assisted analog signal processor operates extensively in the CMOS subthreshold region. During its operation the ASIC encodes head motion signals captured by the inertial sensors as electrical pulses ultimately targeted for in-vivo stimulation of vestibular nerve fibers. To achieve this, the ASIC implements a coordinate system transformation to correct for misalignment between natural sensors and implanted inertial sensors. It also mimics the frequency response characteristics and frequency encoding mappings of angular and linear head motions observed at the peripheral sense organs, semicircular canals and otolith. Overall the design occupies an area of 6.22 mm (2) and consumes 1.24 mW when supplied with ± 1.6 V. PMID:26800546

  19. Space charge dosimeters for extremely low power measurements of radiation in shipping containers

    Science.gov (United States)

    Britton, Jr.; Charles L.; Buckner, Mark A.; Hanson, Gregory R.; Bryan, William L.

    2011-04-26

    Methods and apparatus are described for space charge dosimeters for extremely low power measurements of radiation in shipping containers. A method includes in situ polling a suite of passive integrating ionizing radiation sensors including reading-out dosimetric data from a first passive integrating ionizing radiation sensor and a second passive integrating ionizing radiation sensor, where the first passive integrating ionizing radiation sensor and the second passive integrating ionizing radiation sensor remain situated where the dosimetric data was integrated while reading-out. Another method includes arranging a plurality of ionizing radiation sensors in a spatially dispersed array; determining a relative position of each of the plurality of ionizing radiation sensors to define a volume of interest; collecting ionizing radiation data from at least a subset of the plurality of ionizing radiation sensors; and triggering an alarm condition when a dose level of an ionizing radiation source is calculated to exceed a threshold.

  20. NAIADQ, a computer program for calculating reactivity transients in low power experimental water reactors

    International Nuclear Information System (INIS)

    The computer code NAIADQ is designed to simulate the course and consequences of non-destructive reactivity accidents in low power, experimental, water-cooled reactor cores fuelled with metal plate elements. It is a coupled neutron kinetics-hydrodynamics-heat transfer code which uses point kinetics and one-dimensional thermohydraulic equations. Nucleate boiling, which occurs at the fuel surface during transients, is modelled by the growth of a superheated layer of water in which vapour is generated at a non-equilibrium rate. It is assumed that this vapour is formed at its saturation temperature and that it mixes homogeneously with the water in this layer. The code is written in FORTRAN IV and has been programmed to run as a catalogued procedure on an IBM operating system such as MVT or MVS, with facility for the inclusion of user routines

  1. A low-power circuit for piezoelectric vibration control by synchronized switching on voltage sources

    CERN Document Server

    Shen, Hui; Ji, Hongli; Zhu, Kongjun; Balsi, Marco; Giorgio, Ivan; dell'Isola, Francesco

    2010-01-01

    In the paper, a vibration damping system powered by harvested energy with implementation of the so-called SSDV (synchronized switch damping on voltage source) technique is designed and investigated. In the semi-passive approach, the piezoelectric element is intermittently switched from open-circuit to specific impedance synchronously with the structural vibration. Due to this switching procedure, a phase difference appears between the strain induced by vibration and the resulting voltage, thus creating energy dissipation. By supplying the energy collected from the piezoelectric materials to the switching circuit, a new low-power device using the SSDV technique is proposed. Compared with the original self-powered SSDI (synchronized switch damping on inductor), such a device can significantly improve its performance of vibration control. Its effectiveness in the single-mode resonant damping of a composite beam is validated by the experimental results.

  2. Intense generation of respirable metal nanoparticles from a low-power soldering unit

    Energy Technology Data Exchange (ETDEWEB)

    Gómez, Virginia [Department of Chemical Engineering, Nanoscience Institute of Aragon (INA), 50018 Zaragoza (Spain); Irusta, Silvia [Department of Chemical Engineering, Nanoscience Institute of Aragon (INA), 50018 Zaragoza (Spain); Networking Biomedical Research Center of Bioengineering, Biomaterials and Nanomedicine (CIBER-BBN), 50018 Zaragoza (Spain); Balas, Francisco [Networking Biomedical Research Center of Bioengineering, Biomaterials and Nanomedicine (CIBER-BBN), 50018 Zaragoza (Spain); Instituto de Carboquímica – Consejo Superior de Investigaciones Científicas (ICB-CSIC), 50018 Zaragoza (Spain); Santamaria, Jesus, E-mail: Jesus.Santamaria@unizar.es [Department of Chemical Engineering, Nanoscience Institute of Aragon (INA), 50018 Zaragoza (Spain); Networking Biomedical Research Center of Bioengineering, Biomaterials and Nanomedicine (CIBER-BBN), 50018 Zaragoza (Spain)

    2013-07-15

    Highlights: • Intense generation of nanoparticles in the breathing range from a flux-soldering unit is detected. • Coagulation in the aerosol phase leads to 200-nm respirable nanoparticles up to 30 min after operation. • Nanoparticle concentration in the working environment depends on the presence of ambient air. • Metal-containing nanoparticles are collected in TEM grids and filters in the hundreds of nanometer range. -- Abstract: Evidence of intense nanoparticle generation from a low power (45 W) flux soldering unit is presented. This is a familiar device often used in daily life, including home repairs and school electronic laboratories. We demonstrate that metal-containing nanoparticles may reach high concentrations (ca. 10{sup 6} particles/cm{sup 3}) within the breathing range of the operator, with initial size distributions centered at 35–60 nm The morphological and chemical analysis of nanoparticle agglomerates collected on TEM grids and filters confirms their multiparticle structure and the presence of metals.

  3. Characterisation of beams of low power infrared lasers for medical uses

    International Nuclear Information System (INIS)

    Full text: The initial aim of this work was to investigate the power stability, both temporally and spatially, of the beams of low power infrared diode lasers of the type used by physiotherapists and vascular surgeons. Most of the lasers in this category are small, handheld devices, often with on/off switches which are manually held on while the laser is running. Two of those tested were larger, on stands, and could be set to run for a nominated time. Measurements made by one of us prior to the project had indicated that the power output of at least one of the lasers in use at Westmead Hospital was varying significantly over the treatment time. It is not at present known whether or not uniformity of power output is a significant factor in low power laser therapy, which has been shown to have beneficial effects for conditions ranging from torn muscles and arthritis to birth marks. Dramatic improvement in the healing of skin ulcers and wounds such as amputation scars has also been recorded. Equipment was chosen and a set of techniques developed for analysing the laser beams (some of which operated in continuous wave mode, some in pulsed mode, and some in both) with respect to: power output over time; power distribution within the beam, ie., beam profile; beam divergence; and pulse repetition frequency and pulse shape, if applicable. The fact that some of the lasers were continuous wave, some were pulsed and that some had very high pulse repetition frequencies placed restrictions on the type of power meter which could be used. Eventually a surface absorbing thermal power meter, responsive over a wide range of wavelengths, was chosen for temporal power measurements. Pulse repetition rates and pulse shapes were shown on a CRO; and spatial power distribution, beam shape, power distribution and divergence were recorded via a CCD camera and Spiricon laser beam analyser. 3D printouts from the Spiricon were made showing distribution of beam power. Nine lasers were analysed

  4. Ultra Low-Power Acoustic Detector Applicable in Ambient Assistance Living Systems

    Directory of Open Access Journals (Sweden)

    Iliev I.

    2009-12-01

    Full Text Available Ambient Assisted Living (AAL includes methods, concepts, systems, devices as well as services, which provide unobtrusive support for daily life based on the context and situation of the assisted person. The technologies applied for AAL are user-centric, i.e. oriented towards the needs and capabilities of the particular user. They are also integrated into the immediate personal environment of the user. As a consequence, the technology is adapting to the user rather than the other way around. The in-house monitoring of elderly or disabled people (hard of hearing, deaf, with limited movement ability, using intelligent sensors is a very desirable service that may potentially increase the user's autonomy and independence while minimizing the risks of living alone. The described ultra low-power acoustic detector allows upgrade of the presented warning systems. It features long-term autonomy and possibility to use it as an element of the wireless personal area network (WPAN.

  5. A low-power multi port register file design using a low-swing strategy

    Institute of Scientific and Technical Information of China (English)

    Yan Hao; Liu Yan; Hua Siliang; Wang Donghui; Hou Chaohuan

    2012-01-01

    a low-power register file is designed by using a low-swing strategy and modified NAND address decoders.The proposed low-swing strategy is based on the feedback scheme and uses dynamic logic to reduce the active feedback power.This method contains two parts:WRITE and READ strategy.In the WRITE low-swing scheme,the modified memory cell is used to support low-swing WRITE.The modified NAND decoder not only dissipates less power,but also enables a great deal of area reduction.Compared with the conventional single-ended register file,the low-swing strategy saves 34.5% and 51.15% bit-line power in WRITE and READ separately.The post simulation results indicate a 39.4% power improvement when the twelve ports are all busy.

  6. Low-Voltage, Low-Power, Organic Light-Emitting Transistors for Active Matrix Displays

    Science.gov (United States)

    McCarthy, M. A.; Liu, B.; Donoghue, E. P.; Kravchenko, I.; Kim, D. Y.; So, F.; Rinzler, A. G.

    2011-04-01

    Intrinsic nonuniformity in the polycrystalline-silicon backplane transistors of active matrix organic light-emitting diode displays severely limits display size. Organic semiconductors might provide an alternative, but their mobility remains too low to be useful in the conventional thin-film transistor design. Here we demonstrate an organic channel light-emitting transistor operating at low voltage, with low power dissipation, and high aperture ratio, in the three primary colors. The high level of performance is enabled by a single-wall carbon nanotube network source electrode that permits integration of the drive transistor and the light emitter into an efficient single stacked device. The performance demonstrated is comparable to that of polycrystalline-silicon backplane transistor-driven display pixels.

  7. A Low-Complexity Euclidean Orthogonal LDPC Architecture for Low Power Applications.

    Science.gov (United States)

    Revathy, M; Saravanan, R

    2015-01-01

    Low-density parity-check (LDPC) codes have been implemented in latest digital video broadcasting, broadband wireless access (WiMax), and fourth generation of wireless standards. In this paper, we have proposed a high efficient low-density parity-check code (LDPC) decoder architecture for low power applications. This study also considers the design and analysis of check node and variable node units and Euclidean orthogonal generator in LDPC decoder architecture. The Euclidean orthogonal generator is used to reduce the error rate of the proposed LDPC architecture, which can be incorporated between check and variable node architecture. This proposed decoder design is synthesized on Xilinx 9.2i platform and simulated using Modelsim, which is targeted to 45 nm devices. Synthesis report proves that the proposed architecture greatly reduces the power consumption and hardware utilizations on comparing with different conventional architectures.

  8. Tungsten carbide coatings with different binders prepared by low power plasma spray system

    Institute of Scientific and Technical Information of China (English)

    GAO Yang; M.F.Morks; FU Ying-qing

    2004-01-01

    Thermal spraying of cermet coatings is widely used for protection of machining parts against wear and corrosion. These coatings consist of WC particles in metal binders such as Co, Cr and Ni. Three kinds of WC powders with different metal binders (Co, NiCr and CoCr) were sprayed by low power plasma spray system on Al-Si-Cu alloy substrate. Fundamental aspects of sprayed cermet coatings, including (i) the effects of binder type on the coating structure, (ii) the hardness and (iii) the microstructure, were investigated. All cermet coatings have the same phase structure such as WC and W2 C. However, the intensities of these phases are different in each coating, mainly due to the difference in solidification rate in each case. Moreover, the hardness measurements are found to be different in each coating. The results show that, binder type has a significant effect on the physical and mechanical properties of the sprayed coatings.

  9. Lossless and Low-Power Image Compressor for Wireless Capsule Endoscopy

    Directory of Open Access Journals (Sweden)

    Tareq Hasan Khan

    2011-01-01

    Full Text Available We present a lossless and low-complexity image compression algorithm for endoscopic images. The algorithm consists of a static prediction scheme and a combination of golomb-rice and unary encoding. It does not require any buffer memory and is suitable to work with any commercial low-power image sensors that output image pixels in raster-scan fashion. The proposed lossless algorithm has compression ratio of approximately 73% for endoscopic images. Compared to the existing lossless compression standard such as JPEG-LS, the proposed scheme has better compression ratio, lower computational complexity, and lesser memory requirement. The algorithm is implemented in a 0.18 μm CMOS technology and consumes 0.16 mm × 0.16 mm silicon area and 18 μW of power when working at 2 frames per second.

  10. Electron Cross-field Transport in a Low Power Cylindrical Hall Thruster

    Energy Technology Data Exchange (ETDEWEB)

    A. Smirnov; Y. Raitses; N.J. Fisch

    2004-06-24

    Conventional annular Hall thrusters become inefficient when scaled to low power. Cylindrical Hall thrusters, which have lower surface-to-volume ratio, are therefore more promising for scaling down. They presently exhibit performance comparable with conventional annular Hall thrusters. Electron cross-field transport in a 2.6 cm miniaturized cylindrical Hall thruster (100 W power level) has been studied through the analysis of experimental data and Monte Carlo simulations of electron dynamics in the thruster channel. The numerical model takes into account elastic and inelastic electron collisions with atoms, electron-wall collisions, including secondary electron emission, and Bohm diffusion. We show that in order to explain the observed discharge current, the electron anomalous collision frequency {nu}{sub B} has to be on the order of the Bohm value, {nu}{sub B} {approx} {omega}{sub c}/16. The contribution of electron-wall collisions to cross-field transport is found to be insignificant.

  11. Low Power Thermodynamic Solar Energy Conversion: Coupling of a Parabolic Trough Concentrator and an Ericsson Engine

    Directory of Open Access Journals (Sweden)

    Pascal Stouffs

    2007-03-01

    Full Text Available This paper considers thermodynamic conversion of solar energy into electric energy (up to maximum 50 kWe, presenting a very brief review of the possible systems: the ‘Dish/Stirling’ technology, which relies on high temperature Stirling engines and requires high solar energy; low temperature differential thermal engine using direct solar energy without any concentration but with very low power per unit volume or unit mass of the system; and the intermediate solar energy concentration ratio.A theoretical investigation on the coupling of a two-stage parabolic trough concentrator with a reciprocating Joule cycle air engine (i.e. an Ericsson hot air engine in open cycle is presented. It is shown that there is an optimal operating point that maximises the mechanical power produced by the thermal engine. The interest of coupling a simple, low cost parabolic trough and a simple, low technology, mid-DT Ericsson engine is confirmed.

  12. Improved low-power semiconductor diode lasers for photodynamic therapy in veterinary medicine

    Science.gov (United States)

    Lee, Susanne M.; Mueller, Eduard K.; Van de Workeen, Brian C.; Mueller, Otward M.

    2001-05-01

    Cryogenically cooling semiconductor diode lasers provides higher power output, longer device lifetime, and greater monochromaticity. While these effects are well known, such improvements have not been quantified, and thus cryogenically operated semiconductor lasers have not been utilized in photodynamic therapy (PDT). We report quantification of these results from laser power meter and photospectrometer data. The emission wavelengths of these low power multiple quantum well semiconductor lasers were found to decrease and become more monochromatic with decreasing temperature. Significant power output improvements also were obtained at cryogenic temperatures. In addition, the threshold current, i.e. the current at which lasing begins, decreased with decreasing temperature. This lower threshold current combined with the increased power output produced dramatically higher device efficiencies. It is proposed that cryogenic operation of semiconductor diode lasers will reduce the number of devices needed to produce the requisite output for many veterinary and medical applications, permitting significant cost reductions.

  13. Design of a Low Power DSP with Distributed and Early Clock Gating

    Institute of Scientific and Technical Information of China (English)

    2007-01-01

    A novel clock structure of a low-power 16-bit very large instruction word (VLIW) digital signal processor (DSP) was proposed. To improve deterministic clock gating and to solve the drawback of conventional clock gating circuit in high speed circuit, a distributed and early clock gating method was developed on its instruction fetch &. decoder unit, its pipelined data-path unit and its super-Harvard memory interface unit. The core was im1.8-V 1P6M process, with a core size of 2 mm×2mm .Result shows that it can run under 200MHz with a powerperformance around 0.3mW/MIPS.Meanwhile,only39.7% circuit is active simultaneously in average,comparedto its non-gating counterparts.

  14. A Low-Power ASIC Signal Processor for a Vestibular Prosthesis.

    Science.gov (United States)

    Töreyin, Hakan; Bhatti, Pamela T

    2016-06-01

    A low-power ASIC signal processor for a vestibular prosthesis (VP) is reported. Fabricated with TI 0.35 μm CMOS technology and designed to interface with implanted inertial sensors, the digitally assisted analog signal processor operates extensively in the CMOS subthreshold region. During its operation the ASIC encodes head motion signals captured by the inertial sensors as electrical pulses ultimately targeted for in-vivo stimulation of vestibular nerve fibers. To achieve this, the ASIC implements a coordinate system transformation to correct for misalignment between natural sensors and implanted inertial sensors. It also mimics the frequency response characteristics and frequency encoding mappings of angular and linear head motions observed at the peripheral sense organs, semicircular canals and otolith. Overall the design occupies an area of 6.22 mm (2) and consumes 1.24 mW when supplied with ± 1.6 V.

  15. Evaluation and Choice of Various Branch Predictors for Low-Power Embedded Processor

    Institute of Scientific and Technical Information of China (English)

    FAN DongRui (范东睿); YANG HongBo (杨洪波); GAO GuangRong (高光荣); ZHAO RongCai (赵荣彩)

    2003-01-01

    Power is an important design constraint in embedded computing systems. To meet the power constraint, microarchitecture and hardware designed to achieve high performance need to be revisited, from both performance and power angles. This paper studies one of them:branch predictor. As well known, branch prediction is critical to exploit instruction level parallelism effectively, but may incur additional power consumption due to the hardware resource dedicated for branch prediction and the extra power consumed on mispredicted branches. This paper explores the design space of branch prediction mechanisms and tries to find the most beneficial one to realize low-power embedded processor. The sample processor studied is Godson-like processor, which is a dual-issue, out-of-order processor with deep pipeline, supporting MIPS instruction set.

  16. Nonlinear optics at low powers: new mechanism of on-chip optical frequency comb generation

    CERN Document Server

    Rogov, Andrei

    2016-01-01

    Nonlinear optical effects provide a natural way of light manipulation and interaction, and form the foundation of applied photonics -- from high-speed signal processing and telecommunication, to ultra-high bandwidth interconnects and information processing. However, relatively weak nonlinear response at optical frequencies calls for operation at high optical powers, or boosting efficiency of nonlinear parametric processes by enhancing local field intensity with high quality-factor resonators near cavity resonance, resulting in reduced operational bandwidth and increased loss due to multi-photon absorption. Here, we present an alternative to this conventional approach, with strong nonlinear optical effects at substantially lower local intensities, based on period-doubling bifurcations near nonlinear cavity anti-resonance, and apply it to low-power optical comb generation in a silicon chip.

  17. Interplay of Communication and Computation Energy Consumption for Low Power Sensor Network Design

    Directory of Open Access Journals (Sweden)

    Zeeshan Ali Khan

    2012-08-01

    Full Text Available The sensor network design approach normally conside rs the communication energy consumption for evaluating a communication protocol. This is true f or the low power devices such as MICAz/MICA2 which do not consume a lot of energy for the data t reatment. However, recently developed sensor device s for multimedia applications such as iMote2 do consu me considerable amount of energy for data processing. In this article, we consider various sc enarios for routing the data in wireless multimedia sensor networks by considering the local design par ameters of devices such as PXA27x and beagleboard. The proposed routing solution considers node level optimizations such as data compression, dynamic voltage and frequency scaling (DVFS for making a r outing decision. The proposed approaches have been simulated to prove the effectiveness of the ap proach.

  18. Robust motion estimation on a low-power multi-core DSP

    Science.gov (United States)

    Igual, Francisco D.; Botella, Guillermo; García, Carlos; Prieto, Manuel; Tirado, Francisco

    2013-12-01

    This paper addresses the efficient implementation of a robust gradient-based optical flow model in a low-power platform based on a multi-core digital signal processor (DSP). The aim of this work was to carry out a feasibility study on the use of these devices in autonomous systems such as robot navigation, biomedical assistance, or tracking, with not only power restrictions but also real-time requirements. We consider the C6678 DSP from Texas Instruments (Dallas, TX, USA) as the target platform of our implementation. The interest of this research is particularly relevant in optical flow scope because this system can be considered as an alternative solution for mid-range video resolutions when a combination of in-processor parallelism with optimizations such as efficient memory-hierarchy exploitation and multi-processor parallelization are applied.

  19. Performance Analysis of Modified Drain Gating Techniques for Low Power and High Speed Arithmetic Circuits

    Directory of Open Access Journals (Sweden)

    Shikha Panwar

    2014-01-01

    Full Text Available This paper presents several high performance and low power techniques for CMOS circuits. In these design methodologies, drain gating technique and its variations are modified by adding an additional NMOS sleep transistor at the output node which helps in faster discharge and thereby providing higher speed. In order to achieve high performance, the proposed design techniques trade power for performance in the delay critical sections of the circuit. Intensive simulations are performed using Cadence Virtuoso in a 45 nm standard CMOS technology at room temperature with supply voltage of 1.2 V. Comparative analysis of the present circuits with standard CMOS circuits shows smaller propagation delay and lesser power consumption.

  20. Low Power Design of Pipelined ADC for Power Line Baseband Communication

    Institute of Scientific and Technical Information of China (English)

    陈洋

    2013-01-01

    This paper presents a 10bit 5MS/s pipelined analog-to-digital converter(ADC)for single carrier power line communication transceiver.It’s a low-power method by using switched op amp technique,and proposes the switch capacitor(SC)bias circuitry to solve the startup issue of the current bias.Two common-mode feedback networks are employed to solve the problem of common-mode stability.Removes the sample and hold circuitry(SHA)to further reduce power consumption.Simulation result shows that the proposed ADC achieves 9.6 ENOB,75.8dB SFDR.The power consumption is 0.6 mA for 1.8V supply voltage.

  1. Very Low-Power Consumption Analog Pulse Processing ASIC for Semiconductor Radiation Detectors

    Energy Technology Data Exchange (ETDEWEB)

    Wessendorf, K.O.; Lund, J.C.; Brunett, B.A.; Laguna, G.R.; Clements, J.W.

    1999-08-23

    We describe a very-low power consumption circuit for processing the pulses from a semiconductor radiation detector. The circuit was designed for use with a cadmium zinc telluride (CZT) detector for unattended monitoring of stored nuclear materials. The device is intended to be battery powered and operate at low duty-cycles over a long period of time. This system will provide adequate performance for medium resolution gamma-ray pulse-height spectroscopy applications. The circuit incorporates the functions of a charge sensitive preamplifier, shaping amplifier, and peak sample and hold circuit. An application specific integrated circuit (ASIC) version of the design has been designed, built and tested. With the exception of the input field effect transistor (FET), the circuit is constructed using bipolar components. In this paper the design philosophy and measured performance characteristics of the circuit are described.

  2. An Ultra-Low-Power Oscillator with Temperature and Process Compensation for UHF RFID Transponder

    Directory of Open Access Journals (Sweden)

    Y. Wang

    2013-06-01

    Full Text Available This paper presents a 1.28MHz ultra-low-power oscillator with temperature and process compensation. It is very suitable for clock generation circuits used in ultra-high-frequency (UHF radio-frequency identification (RFID transponders. Detailed analysis of the oscillator design, including process and temperature compensation techniques are discussed. The circuit is designed using TSMC 0.18μm standard CMOS process and simulated with Spectre. Simulation results show that, without post-fabrication calibration or off-chip components, less than ±3% frequency variation is obtained from –40 to 85°C in three different process corners. Monte Carlo simulations have also been performed, and demonstrate a 3σ deviation of about 6%. The power for the proposed circuitry is only 1.18µW at 27°C.

  3. Sub-micron scale patterning of fluorescent silver nanoclusters using low-power laser

    Science.gov (United States)

    Kunwar, Puskal; Hassinen, Jukka; Bautista, Godofredo; Ras, Robin H. A.; Toivonen, Juha

    2016-04-01

    Noble metal nanoclusters are ultrasmall nanomaterials with tunable properties and huge application potential; however, retaining their enhanced functionality is difficult as they readily lose their properties without stabilization. Here, we demonstrate a facile synthesis of highly photostable silver nanoclusters in a polymer thin film using visible light photoreduction. Furthermore, the different stages of the nanocluster formation are investigated in detail using absorption and fluorescence spectroscopy, fluorescence microscopy, and atomic force microscopy. A cost-effective fabrication of photostable micron-sized fluorescent silver nanocluster barcode is demonstrated in silver-impregnated polymer films using a low-power continuous-wave laser diode. It is shown that a laser power of as low as 0.75 mW is enough to write fluorescent structures, corresponding to the specifications of a commercially available laser pointer. The as-formed nanocluster-containing microstructures can be useful in direct labeling applications such as authenticity marking and fluorescent labeling.

  4. Ultra-low power ADC on chip for high-performance IR detector

    Science.gov (United States)

    Decaens, Gilbert; Zecri, Michel; Maillart, Patrick; Advent, Frédéric; Baud, Laurent; Parola, Stephen; Billon-Lanfrey, David; Pistone, Frédéric; Martin, Sébastien

    2009-05-01

    The InfraRed staring arrays developed by SOFRADIR are more and more compact and offer system solutions for wide range of IR wavebands. IR detectors have been taken to an even more advanced level of sophistication to achieve staring arrays high performances. Latest developments have also been focused on the silicon readout circuit. Digital conversion on chip is one of the recent progresses in this field of activity. In order to match each system requirements, on chip high performance ultra low power ADCs have been developed. Beyond the performance aspects, digital focal plane arrays can be considered as the first step towards low cost Dewar family, since they allow for a more simple electrical interface on Dewar designs and on chip image processing. Recent results concerning these new readout circuit architectures are presented in this paper.

  5. Toward low-power electronics: tunneling phenomena in transition metal dichalcogenides.

    Science.gov (United States)

    Das, Saptarshi; Prakash, Abhijith; Salazar, Ramon; Appenzeller, Joerg

    2014-02-25

    In this article, we explore, experimentally, the impact of band-to-band tunneling on the electronic transport of double-gated WSe2 field-effect transistors (FETs) and Schottky barrier tunneling of holes in back-gated MoS2 FETs. We show that by scaling the flake thickness and the thickness of the gate oxide, the tunneling current can be increased by several orders of magnitude. We also perform numerical calculations based on Landauer formalism and WKB approximation to explain our experimental findings. Based on our simple model, we discuss the impact of band gap and effective mass on the band-to-band tunneling current and evaluate the performance limits for a set of dichalcogenides in the context of tunneling transistors for low-power applications. Our findings suggest that WTe2 is an excellent choice for tunneling field-effect transistors. PMID:24392853

  6. Low Cost, Low Power, Passive Muon Telescope For Interrogating Martian Sub-Surface

    Science.gov (United States)

    Naudet, C. J.; Tanaka, H.; Kedar, S.; Plaut, J. J.; Webb, F.

    2012-12-01

    Muon radiography is a technique that uses naturally occurring showers of muons (penetrating particles generated by cosmic rays) to image the interior of geological structures in much the same way as standard X-ray radiography. Unlike gamma rays and neutrons that penetrate only a few meters of rock, muons can traverse through up to several kilometers of a geological target. Recent development and application of the technique to terrestrial volcanoes, caves, and mines have demonstrated that a low-power, passive muon detector can image deep into kilometer-scale geological structures and provide unprecedentedly crisp density profile images of their interior. Preliminary estimates of muon production on Mars indicate that the near-horizontal Martian mu-on flux, which is used for muon radiography of surface features, is at least as strong as that on Earth, making the technique suitable for geological exploration of Mars. The muon telescope represents an entirely new class of instruments for planetary exploration, providing a wholly new type of measurement for delineation of potentially habitable subsurface environments through detection of caves, sub-surface ice, and water, and for the interpretation of composition and evolutionary state of the Martian surface. Muon radiography is a proven, sim-ple, low cost, and efficient technology that could detect subsurface radiation-shielded habitable environments that would not be detectable by any other technique available today. Thanks to its low power and low data rate demands, it could be integrated as a secondary instrument on future missions with minimal impact on primary mission operations. A mission that includes a muon detector could set the stage for a future mission to directly explore subsurface habitable envi-ronments on Mars. Developing the technology now would position it favorably for a surface mission in the 2018-2024 time period to explore Martian regions with previously-identified po-tential trace gas sources

  7. Low power wireless ultra-wide band transmission of bio-signals

    Science.gov (United States)

    Gabrielli, A.; Bastianini, S.; Crepaldi, M.; D'Amen, G.; Demarchi, D.; Lax, I.; Motto Ros, P.; Zoccoli, G.

    2014-12-01

    The paper shows the design of microelectronic circuits composed of an oscillator, a modulator, a transmitter and an antenna. Prototype chips were recently fabricated and tested exploiting commercial 130 nm [1] and 180 nm [2,3] CMOS technologies. Detected signals have been measured using a commercial Ultra-Wide-Band amplifier connected to custom designed filters and a digital demodulator. Preliminary results are summarized along with some waveforms of the transmitted and received signals. A digital Synchronized On-Off Keying (S-OOK) was implemented to exploit the Ultra-Wide-Band transmission. In this way, each transmitted bit is coded with a S-OOK protocol. Wireless transmission capabilities of the system have been also evaluated within a one-meter distance. The chips fit a large variety of applications like spot radiation monitoring, punctual measurements of radiation in High-Energy Physics experiments or, since they have been characterized as low-power components, readout of the system for medical applications. These latter fields are those that we are investigating for in-vivo measurements on small animals. In more detail, if we refer to electromyographic, electrocardiographic or electroencephalographic signals [4], we need to handle very small signal amplitudes, of the order of tens of μV, overwhelmed with a much higher (white) noise. In these cases the front-end of the readout circuit requires a so-called amplifier for instrumentation, here not described, to interface with metal-plate sensor's outputs such those used for electrocardiograms, to normal range of amplitude signals of the order of 1 V. We are also studying these circuits, to be also designed on a microelectronic device, without adding further details since these components are technically well known in the literature [5,6]. The main aim of this research is hence integrating all the described electronic components into a very small, low-powered, microelectronic circuit fully compatible with in

  8. Low-power Helium-Neon laser irradiation enhances the expression of VEGF in murine myocardium

    Institute of Scientific and Technical Information of China (English)

    张卫光; 吴长燕; 潘文潇; 田珑; 夏家骝

    2004-01-01

    Background Low-power helium-neon (He-Ne) lasers have been increasingly widely applied in the treatment of cardiovascular diseases, and its vasodilation effect has been proven. The aim of this study was to determine the effects of low-power He-Ne laser irradiation directed at the precardial region of Wistar rats on capillary permeability in the myocardium and the expression of myocardial vascular endothelial growth factor (VEGF). Methods Sixteen rats were divided randomly into control and irradiated groups (n=8, each). A He-Ne laser (632.8 nm) was applied to the irradiated group with a dose of 60.5 J/cm2. Ferritin was perfused into the left femoral vein and capillary permeability was examined under an electron microscope. VEGF expression in the myocardium was investigated by immunohistochemical methods, RT-PCR, and image analysis. Results The ultrastructures of the myocardial capillaries were examined. Compared to the control group, more high-density granules (ferritin), which were present within the capillary endothelium and the mitochondrions of myocardial cells in the internal layer of the myocardium, were observed in the irradiated group. VEGF staining of the myocardium was stronger in the irradiated group than that in the control group. The optic density of the irradiated group (0.246±0.015) was significantly higher than that of the control group (0.218±0.012, P<0.05). Finally, the levels of RT-PCR products of VEGF165 mRNA were 2.79 times higher in irradiated rats than in the control rats.Conclusions Our study demonstrates that He-Ne laser irradiation (in doses of 60.5 J/cm2) increases myocardial capillary permeability and the production of VEGF in myocardial microvessels and in myocardium. Our study provides experimental morphological evidence that myocardial microcirculation can be improved using He-Ne laser irradiation.

  9. Low power cogeneration prototype system; Prototipo de sistema de co-geracao de pequena potencia

    Energy Technology Data Exchange (ETDEWEB)

    Santos, Sara M.; Martins, Jose A.S.; Camara, Paulo R.; Cortes, Breno P.; Neves, Elierton E. [Centro de Tecnologias do Gas (CTGAS), Natal, RN (Brazil); F. Filho, Roberto; Campos, Michel F. [PETROBRAS, Rio de Janeiro, RJ (Brazil)

    2004-07-01

    The fuels from oil and natural gas play an important role, not only in the sector of primary energy, but also in almost all the other sectors of the economy, due to its imbrication as insum of these. The use of the natural gas will have great expansion in Brazil, motivated for the Government decision to increase the participation of this fuel in the Brazilian energy matrix from 4% to 12% up to 2010. Then, it's so important the investment in new technologies and also the improvement. In order to reach the objective related to increase the consumption of natural gas in the energy matrix, and to propose solutions to attend the electric requirements, of heat and refrigeration, using natural gas as primary power plant, the Center of Gas Technologies; CTGAS, in partnership with PETROBRAS and the Fockink Group, has developed the first modular system of generation and co-generation of energy by natural gas of low power, of easy installation and shipment with the characteristics techniques to take care of to companies or industrial sectors that consummate this band of power. The equipment generates 35 kW/55 kVA of electric energy, 7TR (Ton of Refrigeration) of energy for refrigeration and posses the ability to heat 2200 l/h of water in the temperature of 85 deg C. The equipment will be able to produce electric and thermal energy simultaneously, from an only fuel, the natural gas. The main objective of this work is to present the main phases of development of the archetype, functions techniques of the co-generator and its field of performance in the market of systems for generation and co-generation of energy by natural gas of low power. (author)

  10. Optimal Dynamic Sub-Threshold Technique for Extreme Low Power Consumption for VLSI

    Science.gov (United States)

    Duong, Tuan A.

    2012-01-01

    For miniaturization of electronics systems, power consumption plays a key role in the realm of constraints. Considering the very large scale integration (VLSI) design aspect, as transistor feature size is decreased to 50 nm and below, there is sizable increase in the number of transistors as more functional building blocks are embedded in the same chip. However, the consequent increase in power consumption (dynamic and leakage) will serve as a key constraint to inhibit the advantages of transistor feature size reduction. Power consumption can be reduced by minimizing the voltage supply (for dynamic power consumption) and/or increasing threshold voltage (V(sub th), for reducing leakage power). When the feature size of the transistor is reduced, supply voltage (V(sub dd)) and threshold voltage (V(sub th)) are also reduced accordingly; then, the leakage current becomes a bigger factor of the total power consumption. To maintain low power consumption, operation of electronics at sub-threshold levels can be a potentially strong contender; however, there are two obstacles to be faced: more leakage current per transistor will cause more leakage power consumption, and slow response time when the transistor is operated in weak inversion region. To enable low power consumption and yet obtain high performance, the CMOS (complementary metal oxide semiconductor) transistor as a basic element is viewed and controlled as a four-terminal device: source, drain, gate, and body, as differentiated from the traditional approach with three terminals: i.e., source and body, drain, and gate. This technique features multiple voltage sources to supply the dynamic control, and uses dynamic control to enable low-threshold voltage when the channel (N or P) is active, for speed response enhancement and high threshold voltage, and when the transistor channel (N or P) is inactive, to reduce the leakage current for low-leakage power consumption.

  11. Low power wireless ultra-wide band transmission of bio-signals

    International Nuclear Information System (INIS)

    The paper shows the design of microelectronic circuits composed of an oscillator, a modulator, a transmitter and an antenna. Prototype chips were recently fabricated and tested exploiting commercial 130 nm [1] and 180 nm [2,3] CMOS technologies. Detected signals have been measured using a commercial Ultra-Wide-Band amplifier connected to custom designed filters and a digital demodulator. Preliminary results are summarized along with some waveforms of the transmitted and received signals. A digital Synchronized On-Off Keying (S-OOK) was implemented to exploit the Ultra-Wide-Band transmission. In this way, each transmitted bit is coded with a S-OOK protocol. Wireless transmission capabilities of the system have been also evaluated within a one-meter distance. The chips fit a large variety of applications like spot radiation monitoring, punctual measurements of radiation in High-Energy Physics experiments or, since they have been characterized as low-power components, readout of the system for medical applications. These latter fields are those that we are investigating for in-vivo measurements on small animals. In more detail, if we refer to electromyographic, electrocardiographic or electroencephalographic signals [4], we need to handle very small signal amplitudes, of the order of tens of μV, overwhelmed with a much higher (white) noise. In these cases the front-end of the readout circuit requires a so-called amplifier for instrumentation, here not described, to interface with metal-plate sensor's outputs such those used for electrocardiograms, to normal range of amplitude signals of the order of 1 V. We are also studying these circuits, to be also designed on a microelectronic device, without adding further details since these components are technically well known in the literature [5,6]. The main aim of this research is hence integrating all the described electronic components into a very small, low-powered, microelectronic circuit fully compatible with in

  12. Physics, fabrication and characterization of III-V multi-gate FETs for low power electronics

    Science.gov (United States)

    Thathachary, Arun V.

    With transistor technology close to its limits for power constrained scaling and the simultaneous emergence of mobile devices as the dominant driver for new scaling, a pathway to significant reduction in transistor operating voltage to 0.5V or lower is urgently sought. This however implies a fundamental paradigm shift away from mature Silicon technology. III-V compound semiconductors hold great promise in this regard due to their vastly superior electron transport properties making them prime candidates to replace Silicon in the n-channel transistor. Among the plethora of binary and ternary compounds available in the III-V space, InxGa1-xAs alloys have attracted significant interest due to their excellent electron mobility, ideally placed bandgap and mature growth technology. Simultaneously, electrostatic control mandates multigate transistor designs such as the FinFET at extremely scaled nodes. This dissertation describes the experimental realization of III-V FinFETs incorporating InXGa1-XAs heterostructure channels for high performance, low power logic applications. The chapters that follow present experimental demonstrations, simulations and analysis on the following aspects (a) motivation and key figures of merit driving material selection and design; (b) dielectric integration schemes for high-k metal-gate stack (HKMG) realization on InXGa 1-XAs, including surface clean and passivation techniques developed for high quality interfaces; (c) novel techniques for transport (mobility) characterization in nanoscale multi-gate FET architectures with experimental demonstration on In0.7Ga0.3As nanowires; (d) Indium composition and quantum confined channel design for InXGa 1-XAs FinFETs and (e) InAs heterostructure designs for high performance FinFETs. Each chapter also contains detailed benchmarking of results against state of the art demonstrations in Silicon and III-V material systems. The dissertation concludes by assessing the feasibility of InXGa 1-XAs Fin

  13. Back End of Line Nanorelays for Ultra-low Power Monolithic Integrated NEMS-CMOS Circuits

    KAUST Repository

    Lechuga Aranda, Jesus Javier

    2016-05-01

    Since the introduction of Complementary-Metal-Oxide-Semiconductor (CMOS) technology, the chip industry has enjoyed many benefits of transistor feature size scaling, including higher speed and device density and improved energy efficiency. However, in the recent years, the IC designers have encountered a few roadblocks, namely reaching the physical limits of scaling and also increased device leakage which has resulted in a slow-down of supply voltage and power density scaling. Therefore, there has been an extensive hunt for alternative circuit architectures and switching devices that can alleviate or eliminate the current crisis in the semiconductor industry. The Nano-Electro-Mechanical (NEM) relay is a promising alternative switch that offers zero leakage and abrupt turn-on behaviour. Even though these devices are intrinsically slower than CMOS transistors, new circuit design techniques tailored for the electromechanical properties of such devices can be leveraged to design medium performance, ultra-low power integrated circuits. In this thesis, we deal with a new generation of such devices that is built in the back end of line (BEOL) CMOS process and is an ideal option for full integration with current CMOS transistor technology. Simulation and verification at the circuit and system level is a critical step in the design flow of microelectronic circuits, and this is especially important for new technologies that lack the standard design infrastructure and well-known verification platforms. Although most of the physical and electrical properties of NEM structures can be simulated using standard electronic automation software, there is no report of a reliable behavioural model for NEMS switches that enable large circuit simulations. In this work, we present an optimised model of a BEOL nano relay that encompasses all the electromechanical characteristics of the device and is robust and lightweight enough for VLSI applications that require simulation of thousands of

  14. Power Management and SRAM for Energy-Autonomous and Low-Power Systems

    Science.gov (United States)

    Chen, Gregory K.

    We demonstrate the two first-known, complete, self-powered millimeter-scale computer systems. These microsystems achieve zero-net-energy operation using solar energy harvesting and ultra-low-power circuits. A medical implant for monitoring intraocular pressure (IOP) is presented as part of a treatment for glaucoma. The 1.5mm3 IOP monitor is easily implantable because of its small size and measures IOP with 0.5mmHg accuracy. It wirelessly transmits data to an external wand while consuming 4.70nJ/bit. This provides rapid feedback about treatment efficacies to decrease physician response time and potentially prevent unnecessary vision loss. A nearly-perpetual temperature sensor is presented that processes data using a 2.1muW near-threshold ARMRTM Cortex-M3(TM) muP that provides a widely-used and trusted programming platform. Energy harvesting and power management techniques for these two microsystems enable energy-autonomous operation. The IOP monitor harvests 80nW of solar power while consuming only 5.3nW, extending lifetime indefinitely. This allows the device to provide medical information for extended periods of time, giving doctors time to converge upon the best glaucoma treatment. The temperature sensor uses on-demand power delivery to improve low-load dc-dc voltage conversion efficiency by 4.75x. It also performs linear regulation to deliver power with low noise, improved load regulation, and tight line regulation. Low-power high-throughput SRAM techniques help millimeter-scale microsystems meet stringent power budgets. VDD scaling in memory decreases energy per access, but also decreases stability margins. These margins can be improved using sizing, VTH selection, and assist circuits, as well as new bitcell designs. Adaptive Crosshairs modulation of SRAM power supplies fixes 70% of parametric failures. Half-differential SRAM design improves stability, reducing VMIN by 72mV. The circuit techniques for energy autonomy presented in this dissertation enable

  15. On the capacity of multiple access and broadcast fading Channels with full channel state information at low power regime

    KAUST Repository

    Rezki, Zouheir

    2013-07-01

    We study the throughput capacity region of the Gaussian multi-access (MAC) fading channel with perfect channel state information (CSI) at the receiver and at the transmitters (CSI-TR), at low power regime. We show that it has a multidimensional rectangle structure and thus is simply characterized by single user capacity points. More specifically, we show that at low power regime, the boundary surface of the capacity region shrinks to a single point corresponding to the sum-rate maximizer and that the coordinates of this point coincide with single user capacity bounds. Using the duality of Gaussian MAC and broadcast channels (BC), we provide a simple characterization of the BC capacity region at low power regime. © 2013 IEEE.

  16. Effect of the variable cross-section channel on performance of a cusped field thruster at low power

    International Nuclear Information System (INIS)

    The cusped field thruster has drawn much attention from many institutions due to its wide thrust range, high impulse, and long lifetime. However, lots of experimental results reveal that the cusped field thruster at low power has a poor performance. A cusped field thruster with a variable cross-section channel by putting a ceramic spacer in the channel is introduced in this paper, aimed at improving the thruster performance at low power. The DSMC results validate that the upstream atom density can be increased by a spacer, especially near the wall. Based on simulated results, spacers are put into different positions of the channel. The experimental results show that a suitable spacer can enhance thruster performance at low power, which can be confirmed by the results that the anode efficiency can achieve 40% at 400 V anode voltage and 20 sccm gas flow rate by contrast to 35% without a spacer under the same condition. (paper)

  17. Development of Risk Assessment Technology for Low Power, Shutdown and Digital I and C Systems

    Energy Technology Data Exchange (ETDEWEB)

    Jang, Seung Cheol; Kang, Hyung Gook; Lim, Ho Gon; Park, Jin Hee; Eom, Heung Sub; Kim, Tae Woon; Ha, Jae Joo

    2005-04-15

    There are two technical areas to deal with in the project; the low power and shutdown probabilistic safety assessment (PSA), and the digital I and C PSA. The scope and contents of each area could be summarized as follows: Quality assessment of a LPSD PSA model for a Korean Standard Nuclear Power Plant (KSNP), Quality improvement of the KSNP LPSD PSA model in the following four technical areas; plant operating status (POS), initiating event analysis, determination of success criteria, accident sequence analysis, Development of the LPSD risk management technologies, Unavailability analysis of Digital safety systems such as Digital Plant Protection System (DPPS) and Digital Engineered Safety Feature Actuation System (DESFAS), Impact analysis of the digital safety systems on plant risks throughout of the digital plant risk models for evaluating core damage frequency (CDF) and large early release frequency (LERF), Study on the methodologies for treating digital-specific problems in the digital I and C PSA such as reliability of safety-critical software, common cause failure (CCF) of digital components, fault coverage, etc.

  18. A low-power monolithic CMOS transceiver for 802.11b wireless LANs

    International Nuclear Information System (INIS)

    A single-chip low-power transceiver IC operating in the 2.4 GHz ISM band is presented. Designed in 0.18 μm CMOS, the transceiver system employs direct-conversion architecture for both the receiver and transmitter to realize a fully integrated wireless LAN product. A sigma-delta (ΣΔ) fractional-N frequency synthesizer provides on-chip quadrature local oscillator frequency. Measurement results show that the receiver achieves a maximum gain of 81 dB and a noise figure of 8.2 dB, the transmitter has maximum output power of -3.4 dBm and RMS EVM of 6.8%. Power dissipation of the transceiver is 74 mW in the receiving mode and 81 mW in the transmitting mode under a supply voltage of 1.8 V, including 30 mW consumed by the frequency synthesizer. The total chip area with pads is 2.7 x 4.2 mm2.

  19. A low-power column-parallel ADC for high-speed CMOS image sensor

    Science.gov (United States)

    Han, Ye; Li, Quanliang; Shi, Cong; Liu, Liyuan; Wu, Nanjian

    2013-08-01

    This paper presents a 10-bit low-power column-parallel cyclic analog-to-digital converter (ADC) used for high-speed CMOS image sensor (CIS). An opamp sharing technique is used to save power and area. Correlated double sampling (CDS) circuit and programmable gain amplifier (PGA) are integrated in the ADC, which avoids stand-alone circuit blocks. An offset cancellation technique is also introduced, which reduces the column fixed-pattern noise (FPN) effectively. One single channel ADC with an area less than 0.03mm2 was implemented in a 0.18μm 1P4M CMOS image sensor process. The resolution of the proposed ADC is 10-bit, and the conversion rate is 2MS/s. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.62 LSB and 2.1 LSB together with CDS, respectively. The power consumption from 1.8V supply is only 0.36mW.

  20. Distributed Processing of PIV images with a low power cluster supercomputer

    Science.gov (United States)

    Smith, Barton; Horne, Kyle; Hauser, Thomas

    2007-11-01

    Recent advances in digital photography and solid-state lasers make it possible to acquire images at up to 3000 frames per second. However, as the ability to acquire large samples very quickly has been realized, processing speed has not kept pace. A 2-D Particle Image Velocimetry (PIV) acquisition computer would require over five hours to process the data that can be acquired in one second with a Time-resolved Stereo PIV (TRSPIV) system. To decrease the computational time, parallel processing using a Beowulf cluster has been applied. At USU we have developed a low-power Beowulf cluster integrated with the data acquisition system of a TRSPIV system. This approach of integrating the PIV system and the Beowulf cluster eliminates the communication time, thus speeding up the process. In addition to improving the practicality of TRSPIV, this system will also be useful to researchers performing any PIV measurement where a large number of samples are required. Our presentation will describe the hardware and software implementation of our approach.

  1. Low-Power Miniaturized Helium Dielectric Barrier Discharge Photoionization Detectors for Highly Sensitive Vapor Detection.

    Science.gov (United States)

    Zhu, Hongbo; Zhou, Menglian; Lee, Jiwon; Nidetz, Robert; Kurabayashi, Katsuo; Fan, Xudong

    2016-09-01

    This paper presents the design, fabrication, and characterization of a microhelium dielectric barrier discharge photoionization detector (μHDBD-PID) on chip with dimensions of only ∼15 mm × ∼10 mm × ∼0.7 mm and weight of only ∼0.25 g. It offers low power consumption (4 orders of magnitude), and maintenance-free operation. Furthermore, the μHDBD-PID can be driven with a miniaturized (∼5 cm × ∼2.5 cm × ∼2.5 cm), light (22 g), and low cost (∼$2) power supply with only 1.5 VDC input. The dependence of the μHDBD-PID performance on bias voltage, auxiliary helium flow rate, carrier gas flow rate, and temperature was also systematically investigated. Finally, the μHDBD-PID was employed to detect permanent gases and a sublist of the EPA 8260 standard reagents that include 51 analytes. The μHDBD-PID developed here can have a broad range of applications in portable and microgas chromatography systems for in situ, real-time, and sensitive gas analysis. PMID:27559931

  2. A low-power small-area ADC array for IRFPA readout

    Science.gov (United States)

    Zhong, Shengyou; Yao, Libin

    2013-09-01

    The readout integrated circuit (ROIC) is a bridge between the infrared focal plane array (IRFPA) and image processing circuit in an infrared imaging system. The ROIC is the first part of signal processing circuit and connected to detectors directly, so its performance will greatly affect the detector or even the whole imaging system performance. With the development of CMOS technologies, it's possible to digitalize the signal inside the ROIC and develop the digital ROIC. Digital ROIC can reduce complexity of the whole system and improve the system reliability. More importantly, it can accommodate variety of digital signal processing techniques which the traditional analog ROIC cannot achieve. The analog to digital converter (ADC) is the most important building block in the digital ROIC. The requirements for ADCs inside the ROIC are low power, high dynamic range and small area. In this paper we propose an RC hybrid Successive Approximation Register (SAR) ADC as the column ADC for digital ROIC. In our proposed ADC structure, a resistor ladder is used to generate several voltages. The proposed RC hybrid structure not only reduces the area of capacitor array but also releases requirement for capacitor array matching. Theory analysis and simulation show RC hybrid SAR ADC is suitable for ADC array applications

  3. IC design of low power, wide tuning range VCO in 90 nm CMOS technology

    Science.gov (United States)

    Zhu, Li; Zhigong, Wang; Zhiqun, Li; Qin, Li; Faen, Liu

    2014-12-01

    A low power VCO with a wide tuning range and low phase noise has been designed and realized in a standard 90 nm CMOS technology. A newly proposed current-reuse cross-connected pair is utilized as a negative conductance generator to compensate the energy loss of the resonator. The supply current is reduced by half compared to that of the conventional LC-VCO. An improved inversion-mode MOSFET (IMOS) varactor is introduced to extend the capacitance tuning range from 32.8% to 66%. A detailed analysis of the proposed varactor is provided. The VCO achieves a tuning range of 27-32.5 GHz, exhibiting a frequency tuning range (FTR) of 18.4% and a phase noise of -101.38 dBc/Hz at 1 MHz offset from a 30 GHz carrier, and shows an excellent FOM of -185 dBc/Hz. With the voltage supply of 1.5 V, the core circuit of VCO draws only 2.1 mA DC current.

  4. VLSI Design of Low Power High Speed 4 Bit Resolution Pipeline ADC In Submicron CMOS Technology

    Directory of Open Access Journals (Sweden)

    Rita M. Shende

    2012-01-01

    Full Text Available Analog-to-digital converters (ADCs are key design blocks and are currently adopted in many application fields to improve digital systems, which achieve superior performances with respect to analog solutions. Application such as wireless communication and digital audio and video have created the need for costeffective data converters that will achieve higher speed and resolution. Widespread usage confers great importance to the design activities, which nowadays largely contributes to the production cost in integrated circuit devices (ICs. Various examples of ADC applications can be found in data acquisition systems, measurement systems and digital communication systems also imaging, instrumentation systems. Since theADC has a continuous, infinite –valued signal as its input, the important analog points on the transfer curve x-axis for an ADC are the ones that corresponding to changes in the digital output word. These input transitions determine the amount of INL and DNL associated with the converter. Hence, we have to considered all the parameters and improving the associated performance may significantly reduce the industrial cost of an ADC manufacturing process and improved the resolution and design specially powerconsumption . The paper presents a design of 4 bit Pipeline ADC with low power dissipation implemented in <0.18µm.

  5. First X-ray observations of Low-Power Compact Steep Spectrum Sources

    CERN Document Server

    Kunert-Bajraszewska, M; Siemiginowska, A; Guainazzi, M

    2013-01-01

    We report first X-ray Chandra observations of a sample of seven low luminosity compact (LLC) sources. They belong to a class of young compact steep spectrum (CSS) radio sources. Four of them have been detected, the other three have upper limit estimations for X-ray flux, one CSS galaxy is associated with an X-ray cluster. We have used the new observations together with the observational data for known strong CSS and gigahertz-peaked spectrum (GPS) objects and large scale FRIs and FRIIs to study the relation between morphology, X-ray properties and excitation modes in radio-loud AGNs. We found that: (1) The low power objects fit well to the already established X-ray - radio luminosity correlation for AGNs and occupy the space among, weaker in the X-rays, FRI objects. (2) The high excitation galaxies (HEG) and low excitation galaxies (LEG) occupy distinct locus in the radio/X-ray luminosity plane, notwithstanding their evolutionary stage. This is in agreement with the postulated different origin of the X-ray em...

  6. Standardized low-power wireless communication technologies for distributed sensing applications.

    Science.gov (United States)

    Vilajosana, Xavier; Tuset-Peiro, Pere; Vazquez-Gallego, Francisco; Alonso-Zarate, Jesus; Alonso, Luis

    2014-02-10

    Recent standardization efforts on low-power wireless communication technologies, including time-slotted channel hopping (TSCH) and DASH7 Alliance Mode (D7AM), are starting to change industrial sensing applications, enabling networks to scale up to thousands of nodes whilst achieving high reliability. Past technologies, such as ZigBee, rooted in IEEE 802.15.4, and ISO 18000-7, rooted in frame-slotted ALOHA (FSA), are based on contention medium access control (MAC) layers and have very poor performance in dense networks, thus preventing the Internet of Things (IoT) paradigm from really taking off. Industrial sensing applications, such as those being deployed in oil refineries, have stringent requirements on data reliability and are being built using new standards. Despite the benefits of these new technologies, industrial shifts are not happening due to the enormous technology development and adoption costs and the fact that new standards are not well-known and completely understood. In this article, we provide a deep analysis of TSCH and D7AM, outlining operational and implementation details with the aim of facilitating the adoption of these technologies to sensor application developers.

  7. Standardized Low-Power Wireless Communication Technologies for Distributed Sensing Applications

    Directory of Open Access Journals (Sweden)

    Xavier Vilajosana

    2014-02-01

    Full Text Available Recent standardization efforts on low-power wireless communication technologies, including time-slotted channel hopping (TSCH and DASH7 Alliance Mode (D7AM, are starting to change industrial sensing applications, enabling networks to scale up to thousands of nodes whilst achieving high reliability. Past technologies, such as ZigBee, rooted in IEEE 802.15.4, and ISO 18000-7, rooted in frame-slotted ALOHA (FSA, are based on contention medium access control (MAC layers and have very poor performance in dense networks, thus preventing the Internet of Things (IoT paradigm from really taking off. Industrial sensing applications, such as those being deployed in oil refineries, have stringent requirements on data reliability and are being built using new standards. Despite the benefits of these new technologies, industrial shifts are not happening due to the enormous technology development and adoption costs and the fact that new standards are not well-known and completely understood. In this article, we provide a deep analysis of TSCH and D7AM, outlining operational and implementation details with the aim of facilitating the adoption of these technologies to sensor application developers.

  8. Design of low-power hybrid digital pulse width modulator with piecewise calibration scheme

    Science.gov (United States)

    Zhen, Shaowei; Hou, Sijian; Gan, Wubing; Chen, Jingbo; Luo, Ping; Zhang, Bo

    2015-12-01

    A low-power hybrid digital pulse width modulator (DPWM) is proposed in the paper. Owing to the piecewise calibration scheme, the delay time of delay line is locked to target frequency. The delay line consists of two piecewise lines with different control codes. The delay time of each cell in one sub-delay-line is longer than the last significant bit (LSB) of DPWM, while the delay time of each cell in the other sub-delay-line is shorter than LSB. Optimum linearity is realised with minimum standard cells. Simulation results show that the differential nonlinearity and integral nonlinearity are improved from 5.1 to 0.4 and from 5 to 1.3, respectively. The DPWM is fully synthesised and fabricated in a 90-nm CMOS process. The proposed DPWM occupies a silicon area of 0.01 mm2, with 31.5 μw core power consumption. Experimental results are shown to demonstrate the 2-MHz, 10-bit resolution implementation. Pulse width histogram is firstly introduced to characterise the linearity of the DPWM.

  9. A low power 12-bit 1 Msps successive approximation register ADC with an improved switching procedure

    Science.gov (United States)

    Fubin, Xin; Tao, Yin; Qisong, Wu; Yuanlong, Yang; Fei, Liu; Haigang, Yang

    2015-08-01

    As a key building block of data acquisition systems, power dissipation of the successive approximation register (SAR) ADC determines the total power consumption of the system. In this paper, a low power 12-bit 1 Msps SAR ADC with an improved switching procedure is presented. Power consumption and area occupation could be significantly reduced by using the proposed switching procedure. Compared to converters that use the conventional switching procedure, the average switching energy could be reduced by about 80% and the total capacitance could be reduced by 50%. A simplified digital control logic is utilized to reduce power dissipation and area occupation of the digital control circuits. Simulation results show that the power dissipated by the proposed digital control circuits could be reduced by about 50% compared to the power dissipated by conventional control circuits. The chip has been processed in a standard 0.35 μm CMOS technology and has a core die area of 1.12 mm2. A signal-to-noise-and-distortion-ratio of 64.2 dB has been measured with a 100 kHz signal input under a wide range variation of temperature from -55 to 150 °C. The total power consumption of the prototype is only 0.72 mW with a 3.3 V supply voltage. Project supported by the National Basic Research Program of China (No. 2014CB744600) and the National Natural Science Foundation of China (No. 61474120).

  10. Low-power wide-locking-range injection-locked frequency divider for OFDM UWB systems

    Energy Technology Data Exchange (ETDEWEB)

    Yin Jiangwei; Li Ning; Zheng Renliang; Li Wei; Ren Junyan, E-mail: lining@fudan.edu.c [State Key Laboratory of ASIC and System, Fudan University, Shanghai 201203 (China)

    2009-05-01

    This paper describes a divide-by-two injection-locked frequency divider (ILFD) for frequency synthesizers as used in multiband orthogonal frequency division multiplexing (OFDM) ultra-wideband (UWB) systems. By means of dual-injection technique and other conventional tuning techniques, such as DCCA and varactor tuning, the divider demonstrates a wide locking range while consuming much less power. The chip was fabricated in the Jazz 0.18 mum RF CMOS process. The measurement results show that the divider achieves a locking range of 4.85 GHz (6.23 to 11.08 GHz) at an input power of 8 dBm. The core circuit without the test buffer consumes only 3.7 mA from a 1.8 V power supply and has a die area of 0.38 x 0.28 mm{sup 2}. The wide locking range combined with low power consumption makes the ILFD suitable for its application in UWB systems.

  11. DESIGN OF A LOW-POWER 1.65 GBPS DATA CHANNEL FOR HDMI TRANSMITTER

    Directory of Open Access Journals (Sweden)

    Ajay Agrawal

    2015-12-01

    Full Text Available This paper presents a design of low power data channel for application in High Definition Multimedia Interface (HDMI Transmitter circuit. The input is 10 bit parallel data and output is serial data at 1.65 Gbps. This circuit uses only a single frequency of serial clock input. All other timing signals are derived within the circuit from the serial clock. This design has dedicated lines to disable and enable all its channels within two pixel-clock periods only. A pair of disable and enable functions performed immediately after power-on of the circuit serves as the reset function. The presented design is immune to data-dependent switching spikes in supply current and pushes them in the range of serial frequency and its multiples. Thus filtering requirements are relaxed. The output stage uses a bias voltage of 2.8 volts for a receiver pull-up voltage of 3.3 volts. The reported data channel is designed using UMC 180 nm CMOS Technology. The design is modifiable for other inter-board serial interfaces like USB and LAN with different number of bits at the parallel input.

  12. Dual Wake-up Low Power Listening for Duty Cycled Wireless Sensor Networks

    Directory of Open Access Journals (Sweden)

    Jongkeun Na

    2008-01-01

    Full Text Available Energy management is an interesting research area for wireless sensor networks. Relevant dutycycling (or sleep scheduling algorithm has been actively studied at MAC, routing, and application levels. Low power listening (LPL MAC is one of effective dutycycling techniques. This paper proposes a novel approach called dual wake-up LPL (DW-LPL. Existing LPL scheme uses a preamble detection method for both broadcast and unicast, thus suffers from severe overhearing problem at unicast transmission. DW-LPL uses a different wake-up method for unicast while using LPL-like method for broadcast; DW-LPL introduces a receiver-initiated method in which a sender waits a signal from receiver to start unicast transmission, which incurs some signaling overhead but supports flexible adaptive listening as well as overhearing removal effect. Through analysis and Mote (Telosb experiment, we show that DW-LPL provides more energy saving than LPL and our adaptive listening scheme is effective for energy conservation in practical network topologies and traffic patterns.

  13. Cement Based Batteries and their Potential for Use in Low Power Operations

    Science.gov (United States)

    Byrne, A.; Holmes, N.; Norton, B.

    2015-11-01

    This paper presents the development of an innovative cement-electrolyte battery for low power operations such as cathodic protection of reinforced concrete. A battery design was refined by altering different constituents and examining the open circuit voltage, resistor loaded current and lifespan. The final design consisted of a copper plate cathode, aluminium plate anode, and a cement electrolyte which included additives of carbon black, plasticiser, Alum salt and Epsom salt. A relationship between age, temperature and hydration of the cell and the current it produced was determined. It was found that sealing the battery using varnish increased the moisture retention and current output. Current was also found to increase with internal temperature of the electrolyte and connecting two cells in parallel further doubled or even tripled the current. Parallel-connected cells could sustain an average current of 0.35mA through a 10Ω resistor over two weeks of recording. The preliminary findings demonstrate that cement-based batteries can produce sufficient sustainable electrical outputs with the correct materials and arrangement of components. Work is ongoing to determine how these batteries can be recharged using photovoltaics which will further enhance their sustainability properties.

  14. A Novel Low Power Bitcell Design Featuring Inherent SEU Prevention and Self Correction Capabilities

    Directory of Open Access Journals (Sweden)

    Oron Chertkow

    2015-06-01

    Full Text Available The pursuit of continuous scaling of electronic devices in the semiconductor industry has led to two unintended but significant outcomes: a rapid increase in susceptibility to radiation induced errors, and an overall rise in power consumption. Operating under low voltage to reduce power only aggravates radiation related reliability issues. The proposed “SEU Hardening Incorporating Extreme Low Power Bitcell Design” (SHIELD addresses these two major concerns simultaneously. It is based on the concept of gating the conventional cross-coupled inverters while introducing a novel “cut-off” network. This creates redundant storage nodes and eliminates the internal feedback loop during radiation particle impact. The SHIELD bitcell tolerates upsets with charge deposits over 1 pC. Simulations confirm its advantages in terms of leakage power, with more than twofold lower leakage currents than previous solutions when operated at a 700mV supply voltage in a 65 nm process. To validate the bitcell’s robustness, several test cases and special concerns, including multiple node upsets (MNU and half-select, are examined.

  15. A Low-Power Asynchronous Step-Down DC-DC Converter for Implantable Devices.

    Science.gov (United States)

    Al-Terkawi Hasib, Omar; Sawan, M; Savaria, Y

    2011-06-01

    In this paper, we present a fully integrated asynchronous step-down switched capacitor dc-dc conversion structure suitable for supporting ultra-low-power circuits commonly found in biomedical implants. The proposed converter uses a fully digital asynchronous state machine as the heart of the control circuitry to generate the drive signals. To minimize the switching losses, the asynchronous controller scales the switching frequency of the drive signals according to the loading conditions. It also turns on additional parallel switches when needed and has a backup synchronous drive mode. This circuit regulates load voltages from 300 mV to 1.1 V derived from a 1.2-V input voltage. A total of 350 pF on-chip capacitance was implemented to support a maximum of 230-μ W load power, while providing efficiency up to 80%. The circuit validating the proposed concepts was fabricated in 0.13- μm complementary metal-oxide semiconductor technology. Experimental test results confirm the expected functionality and performance of the proposed circuit.

  16. A Low Cost/Low Power Open Source Sensor System for Automated Tuberculosis Drug Susceptibility Testing.

    Science.gov (United States)

    Kim, Kyukwang; Kim, Hyeong Keun; Lim, Hwijoon; Myung, Hyun

    2016-06-22

    In this research an open source, low power sensor node was developed to check the growth of mycobacteria in a culture bottle with a nitrate reductase assay method for a drug susceptibility test. The sensor system reports the temperature and color sensor output frequency change of the culture bottle when the device is triggered. After the culture process is finished, a nitrite ion detecting solution based on a commercial nitrite ion detection kit is injected into the culture bottle by a syringe pump to check bacterial growth by the formation of a pigment by the reaction between the solution and the color sensor. Sensor status and NRA results are broadcasted via a Bluetooth low energy beacon. An Android application was developed to collect the broadcasted data, classify the status of cultured samples from multiple devices, and visualize the data for the end users, circumventing the need to examine each culture bottle manually during a long culture period. The authors expect that usage of the developed sensor will decrease the cost and required labor for handling large amounts of patient samples in local health centers in developing countries. All 3D-printerable hardware parts, a circuit diagram, and software are available online.

  17. A 130 nm CMOS low-power SAR ADC for wide-band communication systems

    International Nuclear Information System (INIS)

    This paper presents a low power 9-bit 80 MS/s SAR ADC with comparator-sharing technique in 130 nm CMOS process. Compared to the conventional SAR ADC, the sampling phase is removed to reach the full efficiency of the comparator. Thus the conversion rate increases by about 20% and its sampling time is relaxed. The design does not use any static components to achieve a widely scalable conversion rate with a constant FOM. The floorplan of the capacitor network is custom-designed to suppress the gain mismatch between the two DACs. The ‘set-and-down’ switching procedure and a novel binary-search error compensation scheme are utilized to further speed up the SA bit-cycling operation. A very fast logic controller is proposed with a delay time of only 90 ps. At 1.2 V supply and 80 MS/s the ADC achieves an SNDR of 51.4 dB and consumes 1.86 mW, resulting in an FOM of 76.6 fJ/conversion-step. The ADC core occupies an active area of only 0.089 mm2. (semiconductor integrated circuits)

  18. Linear-phase delay filters for ultra-low-power signal processing in neural recording implants.

    Science.gov (United States)

    Gosselin, Benoit; Sawan, Mohamad; Kerherve, Eric

    2010-06-01

    We present the design and implementation of linear-phase delay filters for ultra-low-power signal processing in neural recording implants. We use these filters as low-distortion delay elements along with an automatic biopotential detector to perform integral waveform extraction and efficient power management. The presented delay elements are realized employing continuous-time OTA-C filters featuring 9th-order equiripple transfer functions with constant group delay. Such analog delay enables processing neural waveforms with reduced overhead compared to a digital delay since it does not requires sampling and digitization. It uses an allpass transfer function for achieving wider constant-delay bandwidth than all-pole does. Two filters realizations are compared for implementing the delay element: the Cascaded structure and the Inverse follow-the-leader feedback filter. Their respective strengths and drawbacks are assessed by modeling parasitics and non-idealities of OTAs, and by transistor-level simulations. A budget of 200 nA is used in both filters. Experimental measurements with the chosen filter topology are presented and discussed.

  19. The power of glove: Soft microbial fuel cell for low-power electronics

    Science.gov (United States)

    Winfield, Jonathan; Chambers, Lily D.; Stinchcombe, Andrew; Rossiter, Jonathan; Ieropoulos, Ioannis

    2014-03-01

    A novel, soft microbial fuel cell (MFC) has been constructed using the finger-piece of a standard laboratory natural rubber latex glove. The natural rubber serves as structural and proton exchange material whilst untreated carbon veil is used for the anode. A soft, conductive, synthetic latex cathode is developed that coats the outside of the glove. This inexpensive, lightweight reactor can without any external power supply, start up and energise a power management system (PMS), which steps-up the MFC output (0.06-0.17 V) to practical levels for operating electronic devices (>3 V). The MFC is able to operate for up to 4 days on just 2 mL of feedstock (synthetic tryptone yeast extract) without any cathode hydration. The MFC responds immediately to changes in fuel-type when the introduction of urine accelerates the cycling times (35 vs. 50 min for charge/discharge) of the MFC and PMS. Following starvation periods of up to 60 h at 0 mV the MFC is able to cold start the PMS simply with the addition of 2 mL fresh feedstock. These findings demonstrate that cheap MFCs can be developed as sole power sources and in conjunction with advancements in ultra-low power electronics, can practically operate small electrical devices.

  20. Hydrodynamic and performance of low power turbines: conception, modelling and experimental tests

    Directory of Open Access Journals (Sweden)

    Mariana. Simão, Helena M. Ramos

    2010-05-01

    Full Text Available The present work comprises a research about hydraulic machines with the aim of optimization and the selection of adequate turbines of low power for exploitation of an available energy still unexplored in water supply systems based on analyses of 3D hydrodynamic flows and on characteristic curves which lead to the best efficiency point. The analysis is carried out based on non-dimensional parameters (i.e., discharge, head, efficiency, runner speed and mechanical power in order to be possible comparisons. Mathematical models based on the physical principles, associated to the development of volumetric and rotordynamic machines, are developed. New turbines are suggested, which are based on similar theory among turbo machines based on applications in hydraulic systems with guarantee discharge and available head. The hydrodynamic fluid mechanical analysis requires the use of complex advanced models (CFD which apply the equations of Navier-Stokes by using mathematical models of conservation laws, for the study of the turbulent flow behaviour. To determine the correlation between the flow velocity and pressure fields, the k-? model, is used in this research. Many turbines are evaluated (i.e., positive displacement (PD, pump as turbine (PAT, propeller with volute at inlet, four and five blades tubular propellers and sensitivity analyses, to the best configurations, as well as comparisons between performance curves and experimental tests. Results are presented with the appropriate range variation for each turbine type and application.

  1. Three-dimensional simulation of a low-power microwave-excited microstrip plasma source

    Science.gov (United States)

    Tong, Lizhu; Saito, Keiichiro

    2016-06-01

    A low-power microwave-excited argon microstrip plasma source operated at 2.45 GHz is studied by a three-dimensional fluid model. The electrodeless microwave-excited plasmas are produced in the gas channel with the gas pressures of 50 and 100 Torr at the input power of 2 W. Simulations are performed by the plasma module of COMSOL Multiphysics@. Results show that the electric field induced by the electromagnetic wave is concentrated in the neighborhood of the inner surface of gas channel under the microstrip line. The electromagnetic wave is restricted to transit from being propagating to evanescent in a very thin zone at which the electron density is equal to the critical density. The resonance zone is solved by adding an effective collision frequency to the momentum collision frequency. The governed ions are found to be atomic argon ions (Ar+) and molecular argon ions (Ar2 +) and the latter has a wider distribution. The three-body reactions to produce Ar2 + ions become important at high gas pressures.

  2. A Low Cost/Low Power Open Source Sensor System for Automated Tuberculosis Drug Susceptibility Testing.

    Science.gov (United States)

    Kim, Kyukwang; Kim, Hyeong Keun; Lim, Hwijoon; Myung, Hyun

    2016-01-01

    In this research an open source, low power sensor node was developed to check the growth of mycobacteria in a culture bottle with a nitrate reductase assay method for a drug susceptibility test. The sensor system reports the temperature and color sensor output frequency change of the culture bottle when the device is triggered. After the culture process is finished, a nitrite ion detecting solution based on a commercial nitrite ion detection kit is injected into the culture bottle by a syringe pump to check bacterial growth by the formation of a pigment by the reaction between the solution and the color sensor. Sensor status and NRA results are broadcasted via a Bluetooth low energy beacon. An Android application was developed to collect the broadcasted data, classify the status of cultured samples from multiple devices, and visualize the data for the end users, circumventing the need to examine each culture bottle manually during a long culture period. The authors expect that usage of the developed sensor will decrease the cost and required labor for handling large amounts of patient samples in local health centers in developing countries. All 3D-printerable hardware parts, a circuit diagram, and software are available online.

  3. Nanostructure deposition in the afterglow of a low power barrier discharge

    Energy Technology Data Exchange (ETDEWEB)

    Sonnenfeld, Axel; Papageorgiou, Vasileios; Reichen, Patrick; Koerner, Lutz; Von Rohr, Philipp Rudolf, E-mail: sonnenfeld@ipe.mavt.ethz.ch, E-mail: vonrohr@ipe.mavt.ethz.ch [ETH Zurich, Institute of Process Engineering, Sonneggstrasse 3, 8092 Zurich (Switzerland)

    2011-02-23

    The precipitation of solid-state sphere-like nanostructures from an organosilicon precursor at atmospheric pressure is investigated with the prospect of improving powder flowability by the attachment of nanoscopic spacers to the powder particles' surfaces. Tetramethylsilane (TMS) is admixed to the afterglow of a low power (<0.5 W) barrier discharge (BD). The BD occurs in a single miniature flow channel, where Ar or He enriched with O{sub 2} is excited favouring homogeneous gas phase reactions of atomic oxygen and TMS in the afterglow. The chemical and morphological influence of Ar or He on the formation of nanostructures is explored at two positions in the afterglow by Fourier transform infrared spectroscopy and scanning electron microscopy. For the Ar-based BD, larger spherical nanostructures (100-1000 nm) of higher oxide content are obtained, while for He polymeric deposits with characteristic sizes below 100 nm are found. In addition, the processing capability of a BD device, consisting of a set of 64 miniature flow channels, is probed by means of the wettability improvement of polymer powder particles, conveyed through the BD afterglow zone of a multi-channel device. The treatment is shown to decrease the benzyl alcohol contact angle significantly with increasing oxygen feed.

  4. An ultra-low power (ULP) bandage-type ECG sensor for efficient cardiac disease management.

    Science.gov (United States)

    Shin, Kunsoo; Park, G G; Kim, J P; Lee, T H; Ko, B H; Kim, Y H

    2013-01-01

    This paper proposed an ultra-low power bandage-type ECG sensor (the size: 76 × 34 × 3 (mm(3)) and the power consumption: 1 mW) which allows for a continuous and real-time monitoring of a user's ECG signals over 24h during daily activities. For its compact size and lower power consumption, we designed the analog front-end, the SRP (Samsung Reconfigurable Processor) based DSP of 30 uW/MHz, and the ULP wireless RF of 1 nJ/bit. Also, to tackle motion artifacts(MA), a MA monitoring technique based on the HCP (Half-cell Potential) is proposed which resulted in the high correlation between the MA and the HCP, the correlation coefficient of 0.75 ± 0.18. To assess its feasibility and validity as a wearable health monitor, we performed the comparison of two ECG signals recorded form it and a conventional Holter device. As a result, the performance of the former is a little lower as compared with the latter, although showing no statistical significant difference (the quality of the signal: 94.3% vs 99.4%; the accuracy of arrhythmia detection: 93.7% vs 98.7%). With those results, it has been confirmed that it can be used as a wearable health monitor due to its comfortability, its long operation lifetime and the good quality of the measured ECG signal.

  5. Low power readout electronics for a UV MCP detector with cross strip anode

    Science.gov (United States)

    Pfeifer, M.; Diebold, S.; Barnstedt, J.; Hermanutz, S.; Kalkuhl, C.; Kappelmann, N.; Schanz, T.; Werner, K.

    2014-03-01

    After the shutdown of the Hubble Space Telescope in a few years, new astronomical missions for the ultraviolet (UV) wavelength range between 91 and 300 nm with improved optics and detectors will be necessary. This fact drives our development of solar blind photon counting microchannel plate (MCP) UV detectors with high quantum efficiency, high spatial resolution, and low power readout electronics. We plan to use a cross-strip anode (XSA), which has a high spatial resolution and additionally allows a low gain operation of the MCPs which leads to an increased lifetime of the MCPs compared to detectors with other anode types. The main difficulty in implementing an XSA in a detector for space applications is the need for a (pre-) amplifier, a shaper, and an ADC for each of the strips, which means large power consumption and spatial requirements. The solution we are studying is the application of the so-called Beetle chip. This allows for an implementation of a readout electronics for an XSA with a power consumption of less then 10 W. For the tests of our readout electronics prototype, and for the burn-in of the MCPs, we recently finished a setup in a vacuum chamber that is similar to the configuration in the final detector. We present a brief overview of our detector design and details of the readout electronics setup as well as details of the setup in our vacuum chamber.

  6. Low noise - low power monolithic multiplexing readout electronics for silicon strip detectors

    International Nuclear Information System (INIS)

    A 128 channel readout chip suitable for readout with 50 μm pitch has been developed in CMOS technology. It provides signal amplification, parallel data storage and serial readout. Switched capacitor technique is used for noise reduction by multi correlated sampling and simultaneously for second stage amplification. Power consumption is controlled by an externally applied reference voltage thereby allowing for an optimization of speed and noise versus power consumption for the individual needs of the particular experiment. Pulsed mode operation for further reduction of heat dissipation is easily possible without cutting the supply voltages. Very good noise performance (250+45.CD[pF] electrons) low input impedance (Ceff > 200 pF) and large amplification (70 mV/fC) have been obtained at very low power consumption (1.6 mW per channel). The chip may be used for both synchronous (e.g. collider) and asynchronous (fixed target) applications where the time of the event is not known in advance. A second version with only 64 channels suitable for 100 μm pitch is in preparation. Further developments presently under way include the introduction of combined CMOS-JFET technology. (orig.)

  7. CORPORATE FEED WITH DUAL SEGMENT CIRCULAR POLARIZED ARRAY RECTENNA FOR LOW POWER RF ENERGY HARVESTING

    Directory of Open Access Journals (Sweden)

    CHIA CHAO KANG

    2016-06-01

    Full Text Available This paper focuses on the investigation of the level powers that can be scavenged from the ambient environment by using corporate feed with dual segment circular polarized antenna array . It will converts the received power to direct current (DC. Being a circular polarized antenna, it has higher inductance per unit area, a good Q-factor and compact capability. The design of corporate-series feed rectenna array is to achieve a high gain antenna and maximize the RF energy received by the rectenna system at ultra low power levels. The entire structure was investigated using a combination of harmonic balance nonlinear analysis and full wave electromagnetic field analysis. The results show that 5.0 dBi gain for circular polarized antenna array can be achieved at frequency 956 MHz. When the input power of 20 dBm fed into the transmitting antenna, the maximum distance for radio frequency (RF harvesting is 5.32m. The output DC voltage for various values of incident RF power is also presented. There are noticed reasonable agreements between the simulated and measured result and the works concludes that the investigation of RF energy harvesting system was successful.

  8. LOW POWER-AREA DESIGN OF FULL ADDER USING SELF RESETTING LOGIC WITH GDI TECHNIQUE

    Directory of Open Access Journals (Sweden)

    Simran Khokha1

    2016-08-01

    Full Text Available Various electronic devices such as mobile phones, DSPs,ALU etc., are designed by using VLSI (Very Large Scale Integration technology. In VLSI dynamic CMOS logic circuits are concentrating on the Area ,reducing the power consumption and increasing the Speed by reducing the delay. ALU (Arithmetic Logic Circuits are designed by using adder, subtractors, multiplier, divider, etc.Various adder circuits designs have been proposed over last few years with different logic styles. To reduce the power consumption several parameters are to be taken into account, such as feedthrough, leakage power single-event upsets, charge sharing by parasitic components while connecting source and drain of CMOS transistors There are situations in a logic that permit the use of circuits that can automatically precharge themselves (i.e., reset themselves after some prescribed delays. These circuits are hence called postcharge or self-resetting logic which are widely used in dynamic logic circuits. Overall performance of various adder designs is evaluated by using Tanner tool . The earlier and the proposed SRLGDI primitives are simulated using Tanner EDA with BSIM 0.250 lm technology with supply voltage ranging from 0 V to 5 V in steps of 0.2 V. On comparing the various SRLGDI logic adders, the proposed adder shows low power, delay and low PDP among its counterparts.

  9. Low-power and area-optimized VLSI implementation of AES coprocessor for Zigbee system

    Institute of Scientific and Technical Information of China (English)

    LI Zhen-rong; ZHUANG Yi-qi; ZHANG Chao; JIN Gang

    2009-01-01

    A low-power and low-cost advanced encryption standard (AES) coprocessor is proposed for Zigbee system-on-a-chip (SoC) design. The cost and power consumption of the proposed AES coprocessor are reduced considerably by optimizing the architectures of SubBytes/InvSubBytes and MixColumns/InvMixColumns, integrating the encryption and deeryption procedures together by the method of resource sharing, and using the hierarchical power management strategy based on finite state machine (FSM) and clock gating (CG) technologies. Based on SMIC 0.18 μm complementary metal oxide semiconductor (CMOS) technology, the scale of the AES coprocessor is only about 10.5 kgate, the corresponding power consumption is 69.1 μW/MHz,and the throughput is 32 Mb/s, which is reasonable and sufficient for Zigbee system. Compared with other designs, the proposed architecture consumes less power and fewer hardware resources, which is conducive to the Zigbee system and other portable devices.

  10. A Novel Low Power High Dynamic Threshold Swing Limited Repeater Insertion for On-Chip Interconnects

    Directory of Open Access Journals (Sweden)

    S.Rajendar

    2014-12-01

    Full Text Available In Very Large Scale Integration (VLSI, interconnec t design has become a supreme issue in high speed I Cs. With the decreased feature size of CMOS circuits, o n-chip interconnect now dominates both circuit dela y and power consumption. An eminent technique known a s repeater/buffer insertion is used in long interconnections to reduce delay in VLSI circuits. This paper deals with some distinct low power alternative circuits in buffer insertion technique and it proposes two new techniques: Dynamic Thresho ld Swing Limited (DTSL and High Dynamic Threshold Swi ng Limited (HDTSL. The DTSL uses Dynamic Threshold MOSFET configuration. In this gate is tie d to the body and it limits the output swing. High Dynamic Threshold Swing Limited (HDTSL also uses t he same configuration along with a high threshold voltage(high-Vth. The simulation results are perfo rmed in Cadence virtuoso environment tool using 45n m technology. By simulating and comparing these vario us repeater circuits along with the proposed circui ts it is analyzed that there is trade off among power, de lay and Power Delay Product and the 34.66% of power is reduced by using the high- V th in HDTSL w hen compared to DTSL

  11. A NOVEL LOW POWER HIGH DYNAMIC THRESHOLD SWING LIMITED REPEATER INSERTION FOR ON-CHIP INTERCONNECTS

    Directory of Open Access Journals (Sweden)

    S. Rajendar

    2014-12-01

    Full Text Available In Very Large Scale Integration (VLSI, interconnect design has become a supreme issue in high speed ICs. With the decreased feature size of CMOS circuits, on-chip interconnect now dominates both circuit delay and power consumption. An eminent technique known as repeater/buffer insertion is used in long interconnections to reduce delay in VLSI circuits. This paper deals with some distinct low power alternative circuits in buffer insertion technique and it proposes two new techniques: Dynamic Threshold Swing Limited (DTSL and High Dynamic Threshold Swing Limited (HDTSL. The DTSL uses Dynamic Threshold MOSFET configuration. In this gate is tied to the body and it limits the output swing. High Dynamic Threshold Swing Limited (HDTSL also uses the same configuration along with a high threshold voltage(high-Vth. The simulation results are performed in Cadence virtuoso environment tool using 45nm technology. By simulating and comparing these various repeater circuits along with the proposed circuits it is analyzed that there is trade off among power, delay and Power Delay Product and the 34.66% of power is reduced by using the high- Vth in HDTSL when compared to DTSL.

  12. A high-performance, low-power {sigma} {Delta} ADC for digital audio applications

    Energy Technology Data Exchange (ETDEWEB)

    Luo Hao; Han Yan; Han Xiaoxia; Ma Shaoyu; Ying Peng; Zhu Dazhong [Institute of Microelectronics and Photoelectronics, Zhejiang University, Hangzhou 310027 (China); Cheung, Ray C. C., E-mail: hany@zju.edu.c [Department of Electronic Engineering, City University of Hong Kong, Hong Kong 999077 (China)

    2010-05-15

    A high-performance low-power {sigma} {Delta} analog-to-digital converter (ADC) for digital audio applications is described. It consists of a 2-1 cascaded {sigma} {Delta} modulator and a decimation filter. Various design optimizations are implemented in the system design, circuit implementation and layout design, including a high-overload-level coefficient-optimized modulator architecture, a power-efficient class A/AB operational transconductance amplifier, as well as a multi-stage decimation filter conserving area and power consumption. The ADC is implemented in the SMIC 0.18-{mu}m CMOS mixed-signal process. The experimental chip achieves a peak signal-to-noise-plus-distortion ratio of 90 dB and a dynamic range of 94 dB over 22.05-kHz audio band and occupies 2.1 mm{sup 2}, which dissipates only 2.1 mA quiescent current in the analog circuits. (semiconductor integrated circuits)

  13. Low power penalty tunable slow light using vertical-cavity surface-emitting laser amplifier

    Institute of Scientific and Technical Information of China (English)

    Yanan Ma; Bin Luo; Lianshan Yan; Wei Pan; Xihua Zou; Jia Ye; Anlin Yi; Di Zheng

    2011-01-01

    A tunable slow light of 2,5-Gb/s pseudo-random binary sequence signal using a 1550-nm vertical-cavity surface-emitting laser (VCSEL) is experimentally demonstrated. The influences of the bias current and the gain saturation on the slow light are investignted. With bias current increasing, tunable optical group delay up to 98 ps is obtalned at room temperature. Demonstration of the time delay between 16 and 24 ps by signal intensity change is reported. Under an appropriate bias current, by tuning the input signal to track the peak gain wavelength of the VCSEL, slow light of a power penalty as low as 1 dB is achieved.With such a low power penalty, the VCSEL has a great potential application as a compact optical buffer.%@@ A tunable slow light of 2.5-Gb/s pseudo-random binary sequence signal using a 1550-nm vertical-cavity surface-emitting laser (VCSEL) is experimentally demonstrated.The influences of the bias current and the gain saturation on the slow light are investigated.With bias current increasing, tunable optical group delay up to 98 ps is obtained at room temperature.Demonstration of the time delay between 16 and 24 ps by signal intensity change is reported.

  14. Fabrication of microchannels on PMMA using a low power CO2 laser

    Science.gov (United States)

    Imran, Muhammad; Rahman, Rosly A.; Ahmad, Mukhtar; Akhtar, Majid N.; Usman, Arslan; Sattar, Abdul

    2016-09-01

    This study presents a cheap and quick method for the formation of microchannels on poly methyl methacrylate (PMMA). A continuous wave CO2 laser with a wavelength of 10.6 μm was used to inscribe periodic ripple structures on a PMMA substrate. A direct writing technique was employed for micromachining. As PMMA is very sensitive to such laser irradiations, a slightly low power CO2 laser was effective in inscribing such periodic structures. The results show that smooth and fine ripple structures can be fabricated by controlling the input laser parameters and interaction time of the laser beam. This direct laser writing technique is promising enough to prevent us from using complex optical arrangements. Laser power was tested starting from the ablation threshold and was gradually increased, together with the variation in scanning speed of the xy-translational stage, to observe the effects on the target surface in terms of depth and width of trenches. It was observed that the depth of the trenches increases on increasing the laser power, and the bulge formation on the outer sides of the trenches was also studied. It was evident that the formation of bulges across the trenches is dependent on the scanning speed and input laser power. The results depict that a focused laser beam with optimized parameters, such as controlling the scanning speed and laser power, results in fine, regular and tidy periodic structures.

  15. DESIGN OF PARAMETER EXTRACTOR IN LOW POWER PRECOMPUTATION BASED CONTENT ADDRESSABLE MEMORY

    Directory of Open Access Journals (Sweden)

    Saroja pasumarti,

    2011-07-01

    Full Text Available Content-addressable memory (CAM is frequently used in applications, such as lookup tables, databases, associative computing, and networking, that require high-speed searches due to its ability to improve application performance by using parallel comparison to reduce search time. Although the use of parallel comparison results in reduced search time, it also significantly increases power consumption. In this paper, we propose a Block-XOR approach to improve the efficiency of low power pre computation- based CAM (PBCAM. Through mathematical analysis, we found that our approach can effectively reduce the number of comparison operations by 50% on average as compared with the ones-count approach for 15-bit-long inputs. In our experiment, we used Synopsys Nanosim to estimate the power consumption in TSMC 0.35- m CMOS technology. Compared with the ones-count PB-CAM system, the experimental results show that our proposed approach can achieve on average 30% in power reduction and 32% in power performance reduction. The major contribution of this paper is that it presents theoretical and practical proofs to verify that our proposed Block- XOR PB-CAM system can achieve greater power reduction without the need for a special CAM cell design. This implies that our approach is more flexible and adaptive for general designs.

  16. A Systematic Approach to Design Low-Power Video Codec Cores

    Directory of Open Access Journals (Sweden)

    Corporaal Henk

    2007-01-01

    Full Text Available The higher resolutions and new functionality of video applications increase their throughput and processing requirements. In contrast, the energy and heat limitations of mobile devices demand low-power video cores. We propose a memory and communication centric design methodology to reach an energy-efficient dedicated implementation. First, memory optimizations are combined with algorithmic tuning. Then, a partitioning exploration introduces parallelism using a cyclo-static dataflow model that also expresses implementation-specific aspects of communication channels. Towards hardware, these channels are implemented as a restricted set of communication primitives. They enable an automated RTL development strategy for rigorous functional verification. The FPGA/ASIC design of an MPEG-4 Simple Profile video codec demonstrates the methodology. The video pipeline exploits the inherent functional parallelism of the codec and contains a tailored memory hierarchy with burst accesses to external memory. 4CIF encoding at 30 fps, consumes 71 mW in a 180 nm, 1.62 V UMC technology.

  17. A Systematic Approach to Design Low-Power Video Codec Cores

    Directory of Open Access Journals (Sweden)

    Kristof Denolf

    2007-05-01

    Full Text Available The higher resolutions and new functionality of video applications increase their throughput and processing requirements. In contrast, the energy and heat limitations of mobile devices demand low-power video cores. We propose a memory and communication centric design methodology to reach an energy-efficient dedicated implementation. First, memory optimizations are combined with algorithmic tuning. Then, a partitioning exploration introduces parallelism using a cyclo-static dataflow model that also expresses implementation-specific aspects of communication channels. Towards hardware, these channels are implemented as a restricted set of communication primitives. They enable an automated RTL development strategy for rigorous functional verification. The FPGA/ASIC design of an MPEG-4 Simple Profile video codec demonstrates the methodology. The video pipeline exploits the inherent functional parallelism of the codec and contains a tailored memory hierarchy with burst accesses to external memory. 4CIF encoding at 30 fps, consumes 71 mW in a 180 nm, 1.62 V UMC technology.

  18. Ultra sensitive sea water radioactivity monitoring system. Autonomous low power consumption equipped with wireless data communication

    International Nuclear Information System (INIS)

    Following the recognition of their usefulness by the States and the scientific community, the automatic water monitoring networks were developed again to be able to measure sea water. For that purpose they had to be fully autonomous, have low power consumption (solar panels power supply), use wireless communicating (satellite, GSM, Radio) and be very sensitive (few Bq/m3). It is important to note that radioactivity detection in sea has many constraints: The detection system sensitivity must be very high because of the dilution factor of the ocean. The analysis method has to be adapted: the detection of very low levels of artificial contamination is made difficult due to the natural radioactivity in seawater (i.e., more than 10 kBq of 40K/m3). The system has to be completely autonomous, 'wireless'. Additional conventional measuring probes must be connected to the system to increase its interest (pH, t deg, salinity, position, meteorology). The system maintenance must be very limited (1/year). Wind and corrosion resistance must be high. The probe must be installed on a buoy. Moreover, some improvements are needed to allow: Amplification Gain drifts due to NaI sensitivity to t deg to be compensated. Net peak area computation in a specific energy range. Interference correction to prevent false alarms due to natural radiation. Very long counting time. (author)

  19. Robust Quantum Based Low-power Switching Technique to improve System Performance

    Directory of Open Access Journals (Sweden)

    M. Lavanya

    2013-08-01

    Full Text Available Round Robin (RR is a pre-emptive algorithm used in multiprogrammed, conventional systems to schedule all the processes which are present in ready queue for execution. It has some advantages over other algorithms i.e., it gives a chance to all process to utilize processor for equal time interval. But this technique increases average turnaround time, average waiting time and if quantum value is very less, then CPU time is wasted in switching between processes and increases overheads. If it is high, the algorithm just works like FCFS and cannot be used in time sharing systems. The algorithm performance depends on quantum value. Turnaround time and waiting time are the criteria of the system which should be maintained as less as possible. Standard RR (SRR algorithm does not posses logic infixing quantum value. In our paper we propose Low-power Switching (LS algorithm which reduces context switching and also reduces average waiting time and average turnaround time. So throughput ofsystem will be raised. Experimental analysis shows the feasibility of the proposed algorithm which gives better turnaround time, waiting time and context switching compared with SRR technique and some related works. Pseudo code has been generated to prove the work.

  20. Investigation of a novel common subexpression elimination method for low power and area efficient DCT architecture.

    Science.gov (United States)

    Siddiqui, M F; Reza, A W; Kanesan, J; Ramiah, H

    2014-01-01

    A wide interest has been observed to find a low power and area efficient hardware design of discrete cosine transform (DCT) algorithm. This research work proposed a novel Common Subexpression Elimination (CSE) based pipelined architecture for DCT, aimed at reproducing the cost metrics of power and area while maintaining high speed and accuracy in DCT applications. The proposed design combines the techniques of Canonical Signed Digit (CSD) representation and CSE to implement the multiplier-less method for fixed constant multiplication of DCT coefficients. Furthermore, symmetry in the DCT coefficient matrix is used with CSE to further decrease the number of arithmetic operations. This architecture needs a single-port memory to feed the inputs instead of multiport memory, which leads to reduction of the hardware cost and area. From the analysis of experimental results and performance comparisons, it is observed that the proposed scheme uses minimum logic utilizing mere 340 slices and 22 adders. Moreover, this design meets the real time constraints of different video/image coders and peak-signal-to-noise-ratio (PSNR) requirements. Furthermore, the proposed technique has significant advantages over recent well-known methods along with accuracy in terms of power reduction, silicon area usage, and maximum operating frequency by 41%, 15%, and 15%, respectively.

  1. Use of negative capacitance to provide voltage amplification for low power nanoscale devices.

    Science.gov (United States)

    Salahuddin, Sayeef; Datta, Supriyo

    2008-02-01

    It is well-known that conventional field effect transistors (FETs) require a change in the channel potential of at least 60 mV at 300 K to effect a change in the current by a factor of 10, and this minimum subthreshold slope S puts a fundamental lower limit on the operating voltage and hence the power dissipation in standard FET-based switches. Here, we suggest that by replacing the standard insulator with a ferroelectric insulator of the right thickness it should be possible to implement a step-up voltage transformer that will amplify the gate voltage thus leading to values of S lower than 60 mV/decade and enabling low voltage/low power operation. The voltage transformer action can be understood intuitively as the result of an effective negative capacitance provided by the ferroelectric capacitor that arises from an internal positive feedback that in principle could be obtained from other microscopic mechanisms as well. Unlike other proposals to reduce S, this involves no change in the basic physics of the FET and thus does not affect its current drive or impose other restrictions. PMID:18052402

  2. Low Power 24 GHz ad hoc Networking System Based on TDOA for Indoor Localization

    Directory of Open Access Journals (Sweden)

    Melanie Jung

    2013-12-01

    Full Text Available This paper introduces the key elements of a novel low-power, high precision localization system based on Time-Difference-of-Arrival (TDOA distance measurements. The combination of multiple localizable sensor nodes, leads to an ad hoc network. Besides the localization functionality this ad hoc network has the additional advantage of a communication interface. Due to this a flexible positioning of the master station for information collection and the detection of static and mobile nodes is possible. These sensor nodes work in the 24 GHz ISM (Industrial Scientific and Medical frequency range and address several use cases and are able to improve various processes for production scheduling, logistics, quality management, medical applications and collection of geo information. The whole system design is explained briefly. Its core component is the frequency modulated continuous wave (FMCW synthesizer suitable for high performance indoor localization. This research work focuses on power and size reduction of this crucial system component. The comparison of the first and second generation of the system shows a significant size and power reduction as well as an increased precision.

  3. A Low Cost/Low Power Open Source Sensor System for Automated Tuberculosis Drug Susceptibility Testing

    Directory of Open Access Journals (Sweden)

    Kyukwang Kim

    2016-06-01

    Full Text Available In this research an open source, low power sensor node was developed to check the growth of mycobacteria in a culture bottle with a nitrate reductase assay method for a drug susceptibility test. The sensor system reports the temperature and color sensor output frequency change of the culture bottle when the device is triggered. After the culture process is finished, a nitrite ion detecting solution based on a commercial nitrite ion detection kit is injected into the culture bottle by a syringe pump to check bacterial growth by the formation of a pigment by the reaction between the solution and the color sensor. Sensor status and NRA results are broadcasted via a Bluetooth low energy beacon. An Android application was developed to collect the broadcasted data, classify the status of cultured samples from multiple devices, and visualize the data for the end users, circumventing the need to examine each culture bottle manually during a long culture period. The authors expect that usage of the developed sensor will decrease the cost and required labor for handling large amounts of patient samples in local health centers in developing countries. All 3D-printerable hardware parts, a circuit diagram, and software are available online.

  4. The low power miniature neutron source reactors: Design, safety and applications

    International Nuclear Information System (INIS)

    The Chinese Miniature Neutron Source Reactor (MNSR) is a low power research reactor with maximum thermal neutron flux of 1 x 1012 n.cm-2.s-1 in one of its inner irradiation channels and thermal power of approximately 30kW. The MNSR is designed based on the Canadian SLOWPOKE reactor and is one of the smallest commercial research reactors presently available in the world. Its commercial versions currently in operation in China, Ghana, Iran, Nigeria, Pakistan and Syria, is considered as an excellent tool for Neutron Activation Analysis (NAA), training of Scientist, and Engineers in nuclear science and technology and small scale radioisotope production. The paper highlights the basic design and theory of the commercial MNSR, its safety features, applications and advantages over the Chinese Prototype. The experimental flux characteristics determined in this work and in similar studies by other authors reveal that the commercial MNSR has more flux stability, longer life span, higher negative temperature coefficient of reactivity and low under-moderation compared to its prototype in China. The result shows that the facility is safe for reactor physics experiments, teaching and training of students and also ideal for application of NAA for the determination of elemental composition of biological and environmental samples. It can also be a useful tool for geochemical and soil fertility mapping. (author)

  5. Low noise, low power front end electronics for pixelized TFA sensors

    CERN Document Server

    Poltorak, K; Dabrowski, W; Despeisse, M; Jarron, P; Kaplon, J; Wyrschb, N

    2009-01-01

    Thin Film on ASIC (TFA) technology combines advantages of two commonly used pixel imaging detectors, namely, Monolithic Active Pixels (MAPs) and Hybrid Pixel detectors. Thanks to direct deposition of a hydrogenated amorphous silicon (a- Si:H) sensor lm on top of the readout ASIC, TFA shows the similarity to MAP imagers, allowing, however, more sophisticated front–end circuitry to extract the signals, like in case of Hybrid Pixel technology. In this paper we present preliminary experimental results of TFA structures, obtained with 10 μm thick hydrogenated amorphous silicon sensors, deposited directly on top of integrated circuit optimized for tracking applications at linear collider experiments. The signal charges delivered by such a-Si:H n-i-p diode are small; about 37 e-/μm for minimum ionizing particles, therefore a low noise, high gain and very low power of the front- end are of primary importance. The developed demonstrator chip, designed in 250 nm CMOS technology, comprises an array of 64 by 64 pi...

  6. An asynchronous pipeline architecture for the low-power AES S-box

    Institute of Scientific and Technical Information of China (English)

    Zeng Yonghong; Zou Xuecheng; Liu Zhenglin

    2008-01-01

    To obtain a low-power and compact implementation of the advanced encryption standard (AES) S-box, an asynchronous pipeline architecture over composite field arithmetic was proposed in this paper. In the presented S-box, some improvements were made as follows. (1) Level-sensitive latches were inserted in data path to block the propagation of the dynamic hazards, which lowered the power of data path circuit. (2) Operations of latches were controlled by latch controllers based on presented asynchronous sequence element: LC-element, which utilized static asymmetric C-element to construct a simple and power-efficient circuit structure. (3) Implementation of the data path circuit was a semi-custom standard-cell circuit on 0.25μm complementary mental oxide semiconductor (CMOS) process; and the full-custom design methodology was adopted in the handshake circuit design. Experimental results show that the resulting circuit achieves nearly 46% improvement with moderate area penalty (11.7%) compared with the related composite field S-box in power performance. The presented S-box circuit can be a hardware intelligent property (IP) embedded in the targeted systems such as wireless sensor networks (WSN), smartcards and radio frequency identification (RFID).

  7. Low-Power Amplifier-Discriminators for High Time Resolution Detection

    CERN Document Server

    Despeisse, M; Anghinolfi, F; Tiuraniemi, S; Osmic, F; Riedler, P; Kluge, A; Ceccucci, A

    2009-01-01

    Low-power amplifier-discriminators based on a so-called NINO architecture have been developed with high time resolution for the readout of radiation detectors. Two different circuits were integrated in the NINO13 chip, processed in IBM 130 nm CMOS technology. The LCO version (Low Capacitance and consumption Optimization) was designed for potential use as front-end electronics in the Gigatracker of the NA62 experiment at CERN. It was developed as pixel readout for solid-state pixel detectors to permit minimum ionizing particle detection with less than 180 ps rms resolution per pixel on the output pulse, for power consumption below 300 mu W per pixel. The HCO version (High Capacitance Optimization) was designed with 4 mW power consumption per channel to provide timing resolution below 20 ps rms on the output pulse, for charges above 10 fC. Results presented show the potential of the LCO and HCO circuits for the precise timing readout of solid-state detectors, vacuum tubes or gas detectors, for applications in h...

  8. Low-power laser irradiation inhibits Aβ25-35-induced cell apoptosis through Akt activation

    Science.gov (United States)

    Zhang, Zhigang; Tang, Yonghong

    2009-08-01

    Low-power laser irradiation (LPLI) can modulate various cellular processes such as proliferation, differentiation and apoptosis. Recently, LPLI has been applied to moderate Alzheimer's disease (AD), but the underlying mechanism remains unknown. The protective role of LPLI against the amyloid beta peptide (Aβ), a major constituent of AD plaques, has not been studied. PI3K/Akt pathway is extremely important in protecting cells from apoptosis caused by diverse stress stimuli. However, whether LPLI can inhibit Aβ-induced apoptosis through Akt activation is still unclear. In current study, using FRET (fluorescence resonance energy transfer) technique, we investigated the activity of Akt in response to LPLI treatment. B kinase activity reporter (BKAR), a recombinant FRET probe of Akt, was utilized to dynamically detect the activation of Akt after LPLI treatment. The results show that LPLI promoted the activation of Akt. Moreover, LPLI inhibits apoptosis induced by Aβ25-35 and the apoptosis inhibition can be abolished by wortmannin, a specific inhibitor of PI3K/Akt. Taken together, these results suggest that LPLI can inhibit Aβ25-35-induced cell apoptosis through Akt activation.

  9. Microbial fuel cells as power supply of a low-power temperature sensor

    Science.gov (United States)

    Khaled, Firas; Ondel, Olivier; Allard, Bruno

    2016-02-01

    Microbial fuel cells (MFCs) show great promise as a concomitant process for water treatment and as renewable energy sources for environmental sensors. The small energy produced by MFCs and the low output voltage limit the applications of MFCs. Specific converter topologies are required to step-up the output voltage of a MFC. A Power Management Unit (PMU) is proposed for operation at low input voltage and at very low power in a completely autonomous way to capture energy from MFCs with the highest possible efficiency. The application of sensors for monitoring systems in remote locations is an important approach. MFCs could be an alternative energy source in this case. Powering a sensor with MFCs may prove the fact that wastewater may be partly turned into renewable energy for realistic applications. The Power Management Unit is demonstrated for 3.6 V output voltage at 1 mW continuous power, based on a low-cost 0.7-L MFC. A temperature sensor may operate continuously on 2-MFCs in continuous flow mode. A flyback converter under discontinuous conduction mode is also tested to power the sensor. One continuously fed MFC was able to efficiently and continuously power the sensor.

  10. Low power proton exchange membrane fuel cell system identification and adaptive control

    Science.gov (United States)

    Yang, Yee-Pien; Wang, Fu-Cheng; Chang, Hsin-Ping; Ma, Ying-Wei; Weng, Biing-Jyh

    This paper proposes a systematic method of system identification and control of a proton exchange membrane (PEM) fuel cell. This fuel cell can be used for low-power communication devices involving complex electrochemical reactions of nonlinear and time-varying dynamic properties. From a system point of view, the dynamic model of PEM fuel cell is reduced to a configuration of two inputs, hydrogen and air flow rates, and two outputs, cell voltage and current. The corresponding transfer functions describe linearized subsystem dynamics with finite orders and time-varying parameters, which are expressed as discrete-time auto-regression moving-average with auxiliary input models for system identification by the recursive least square algorithm. In the experiments, a pseudo-random binary sequence of hydrogen or air flow rate is fed to a single fuel cell device to excite its dynamics. By measuring the corresponding output signals, each subsystem transfer function of reduced order is identified, while the unmodeled, higher-order dynamics and disturbances are described by the auxiliary input term. This provides a basis of adaptive control strategy to improve the fuel cell performance in terms of efficiency, as well as transient and steady state specifications. Simulation shows that adaptive controller is robust to the variation of fuel cell system dynamics, and it has proved promising from the experimental results.

  11. Overview and Evaluation of Bluetooth Low Energy: An Emerging Low-Power Wireless Technology

    Directory of Open Access Journals (Sweden)

    Josep Paradells

    2012-08-01

    Full Text Available Bluetooth Low Energy (BLE is an emerging low-power wireless technology developed for short-range control and monitoring applications that is expected to be incorporated into billions of devices in the next few years. This paper describes the main features of BLE, explores its potential applications, and investigates the impact of various critical parameters on its performance. BLE represents a trade-off between energy consumption, latency, piconet size, and throughput that mainly depends on parameters such as connInterval and connSlaveLatency. According to theoretical results, the lifetime of a BLE device powered by a coin cell battery ranges between 2.0 days and 14.1 years. The number of simultaneous slaves per master ranges between 2 and 5,917. The minimum latency for a master to obtain a sensor reading is 676 µs, although simulation results show that, under high bit error rate, average latency increases by up to three orders of magnitude. The paper provides experimental results that complement the theoretical and simulation findings, and indicates implementation constraints that may reduce BLE performance.

  12. Low power options for 32 nm always-on SRAM architecture

    Science.gov (United States)

    Hamouche, Lahcen; Allard, Bruno

    2011-04-01

    The SRAM 6T bit-cell suffers many limitations in advanced technology nodes among which variability effects. Various alternatives have been experimented and the paper focuses on the 5T-Portless bit-cell. Read and write operations are operated by varying voltage conditions. Literature regarding 32 nm CMOS for Portless SRAM has been reviewed and improvements are presented. The bit-cells are arranged in matrix to permit a current-mode read operation as opposed to voltage-based sensing techniques. Thus safety and stability of the bit-cell operation is established without constraints on memory periphery. The current-mode operation enables a significant gain in dynamic power consumption beneficial to always-on memories. The paper presents different existing solutions to limit the power consumption and their limitations in thin CMOS technologies. The portless bit-cell is presented as a low power architecture alternative to 6T-SRAM. A matrix test-chip is currently under fabrication in bulk CMOS 32 nm.

  13. Design of A Novel High Speed Dynamic Comparator with Low Power Dissipation for High Speed ADCs

    Directory of Open Access Journals (Sweden)

    Sougata Ghosh

    2013-01-01

    Full Text Available A new CMOS dynamic comparator using dual input single output differential amplifier as latch stage suitable for high speed analog-to-digital converters with High Speed, low power dissipation and immune to noise than the previous reported work is proposed. Back to-back inverter in the latch stage is replaced with dual-input single output differential amplifier. This topology completely removes the noise that is present in the input. The structure shows lower power dissipation and higher speed than the conventional comparators. The circuit is simulated with 1V DC supply voltage and 250 MHz clock frequency. The proposed topology is based on two cross coupled differential pairs positive feedback and switchable current sources, has a lower power dissipation, higher speed, less area, and it is shown to be very robust against transistor mismatch, noise immunity. Previous reported comparators are designed and simulated their DC response and Transient response in Cadence®Virtuoso Analog Design Environment using GPDK 90nm technology. Layouts of the proposed comparator have been done in Cadence® Virtuoso Layout XL Design Environment. DRC and LVS has been checked and compared with the corresponding circuits and RC extracted diagram has been generated. After that post layout simulation with 1V supply voltage has been done and compared the speed, power dissipation, Area, delay with the results before layout and the superior features of the proposed comparator are established

  14. Electron Transport and Ion Acceleration in a Low-power Cylindrical Hall Thruster

    Energy Technology Data Exchange (ETDEWEB)

    A. Smirnov; Y. Raitses; N.J. Fisch

    2004-06-24

    Conventional annular Hall thrusters become inefficient when scaled to low power. Cylindrical Hall thrusters, which have lower surface-to-volume ratio, are therefore more promising for scaling down. They presently exhibit performance comparable with conventional annular Hall thrusters. Electron cross-field transport in a 2.6 cm miniaturized cylindrical Hall thruster (100 W power level) has been studied through the analysis of experimental data and Monte Carlo simulations of electron dynamics in the thruster channel. The numerical model takes into account elastic and inelastic electron collisions with atoms, electron-wall collisions, including secondary electron emission, and Bohm diffusion. We show that in order to explain the observed discharge current, the electron anomalous collision frequency {nu}{sub B} has to be on the order of the Bohm value, {nu}{sub B} {approx} {omega}{sub c}/16. The contribution of electron-wall collisions to cross-field transport is found to be insignificant. The plasma density peak observed at the axis of the 2.6 cm cylindrical Hall thruster is likely to be due to the convergent flux of ions, which are born in the annular part of the channel and accelerated towards the thruster axis.

  15. Very Low Power, Low Voltage, High Accuracy, and High Performance Current Mirror

    Institute of Scientific and Technical Information of China (English)

    Hassan Faraji Baghtash; Khalil Monfaredi; Ahmad Ayatollahi

    2011-01-01

    A novel low power and low voltage current mirror with a very low current copy error is presented and the principle of its operation is discussed.In this circuit,the gain boosting regulated cascode scheme is used to improve the output resistance,while using inverter as an amplifier.The simulation results with HSPICE in TSMC 0.18 μm CMOS technology are given,which verify the high performance of the proposed structure.Simulation results show an input resistance of 0.014 Ω and an output resistance of 3 GΩ.The current copy error is favorable as low as 0.002% together with an input (the minimum input voltage of vin,min~ 0.24 V) and an output (the minimum output voltage of vout,min~ 0.16 V) compliances while working with the 1 V power supply and the 50 μA input current.The current copy error is near zero at the input current of 27 μA.It consumes only 76 μW and introduces a very low output offset current of 50 pA.

  16. Low-power resistive random access memory by confining the formation of conducting filaments

    Directory of Open Access Journals (Sweden)

    Yi-Jen Huang

    2016-06-01

    Full Text Available Owing to their small physical size and low power consumption, resistive random access memory (RRAM devices are potential for future memory and logic applications in microelectronics. In this study, a new resistive switching material structure, TiOx/silver nanoparticles/TiOx/AlTiOx, fabricated between the fluorine-doped tin oxide bottom electrode and the indium tin oxide top electrode is demonstrated. The device exhibits excellent memory performances, such as low operation voltage (<±1 V, low operation power, small variation in resistance, reliable data retention, and a large memory window. The current-voltage measurement shows that the conducting mechanism in the device at the high resistance state is via electron hopping between oxygen vacancies in the resistive switching material. When the device is switched to the low resistance state, conducting filaments are formed in the resistive switching material as a result of accumulation of oxygen vacancies. The bottom AlTiOx layer in the device structure limits the formation of conducting filaments; therefore, the current and power consumption of device operation are significantly reduced.

  17. Low power instruction Cache design%DSP中指令Cache的低功耗设计

    Institute of Scientific and Technical Information of China (English)

    杨晓刚; 屈凌翔; 张树丹

    2011-01-01

    设计了一种低功耗指令Cache:通过在CPU与一级指令Cache之间加入Line Buffer,来减少CPU对指令Cache的访问次数,从而降低指令Cache的功耗.此外在Line Buffer控制器中添加了重装控制单元,当指令Cache发生缺失时,能将片外存储单元中的指令直接送给CPU,从而最大限度地减少由于Cache缺失所引起CPU取指的延迟.经验证,该设计在降低功耗的同时,还提升了指令Cache的性能.%This paper designs a low power instruction Cache by adding a Line Buffer between CPU and instruction Cache to reduce the on-chip cache memory access activities,consequently it decreases the energy consumption of the Cache memory. What's more,it also minimizes the Cache miss penalty by adding refill engine to the Line Buffer.Simulation results show that the design can not only reduce the power consumption but also improve the instruction Cache performance.

  18. The Design of High Performance, Low Power Triple-Track Magnetic Sensor Chip

    Directory of Open Access Journals (Sweden)

    Junning Chen

    2013-07-01

    Full Text Available This paper presents a design of a high performance and low power consumption triple-track magnetic sensor chip which was fabricated in TSMC 0.35 μm CMOS process. This chip is able to simultaneously sense, decode and read out the information stored in triple-track magnetic cards. A reference voltage generating circuit, a low-cost filter circuit, a power-on reset circuit, an RC oscillator, and a pre-decoding circuit are utilized as the basic modules. The triple-track magnetic sensor chip has four states, i.e., reset, sleep, swiping card and data read-out. In sleep state, the internal RC oscillator is closed, which means that the digital part does not operate to optimize energy consumption. In order to improve decoding accuracy and expand the sensing range of the signal, two kinds of circuit are put forward, naming offset correction circuit, and tracking circuit. With these two circuits, the sensing function of this chip can be more efficiently and accurately. We simulated these circuit modules with TSMC technology library. The results showed that these modules worked well within wide range input signal. Based on these results, the layout and tape-out were carried out. The measurement results showed that the chip do function well within a wide swipe speed range, which achieved the design target.

  19. DESIGN OF LOW POWER 8T SRAM WITH SCHMITT TRIGGER LOGIC

    Directory of Open Access Journals (Sweden)

    A. KISHORE KUMAR

    2014-12-01

    Full Text Available Static Random Access Memory (SRAM has become a key element in modern VLSI systems. In this paper, a low power design of 8 Transistor SRAM cell with Schmitt Trigger (ST logic is proposed. The main intention of this paper is to design a new SRAM cell architecture to reduce the power consumption during both read / write operations and to improve SRAM access stability. The proposed design is simulated using 0.18 µm process technology and compared with conventional 6T cell. Simulation results show that the proposed memory cell achieves significant improvements in power consumption during read and write operations. It can retain data at a lower supply voltage of 300 mV. This new type of SRAM design can operate at a maximum frequency of 1 GHz at 1 V supply voltage. These qualities of the proposed design make it a best choice for high performance memory chips in the semiconductor industry where reliability and power consumption are of great interest.

  20. Nd:YVO4 amplifier for ultrafast low-power lasers.

    Science.gov (United States)

    Agnesi, Antonio; Carrà, Luca; Piccoli, Riccardo; Pirzio, Federico; Reali, Giancarlo

    2012-09-01

    An Nd:YVO4 amplifier consisting of two modules end pumped at 808 nm at 30 W total absorbed power has been designed for efficient, diffraction-limited amplification of ultrafast pulses from low-power seeders. We investigated amplification with a 50 mW, 7 ps Nd:YVO4 oscillator, a 2 mW, 15 ps Yb fiber laser, and a 30 mW, 300 fs Nd:glass laser. Output power as high as 9.5 W with 8 ps pulses was achieved with the 250 MHz vanadate seeder, whereas the 20 MHz fiber laser was amplified to 6 W. The femtosecond seeder allowed extracting Fourier-limited 4 ps pulses at 7 W output power. To our knowledge, these are the shortest pulses from any Nd:YVO4 laser device with at least 7 W output power. This suggests a novel approach to exploit the gain bandwidth of vanadate amplifiers with high output power levels. Such amplifier technology promises to offer an interesting alternative to high-power thin disk oscillators at few picoseconds duration, as well as to regenerative amplifiers with low-repetition-rate fiber seeders. PMID:22940966

  1. Low Power Architecture Design of De-Blocking Filter and Hardware Implementations in H.264/AVC

    Directory of Open Access Journals (Sweden)

    Mrs. T. Priyadarsini

    2014-11-01

    Full Text Available An adaptive in-loop de-blocking filter (DF is standardized in H.264/AVC to reduce blocking artifacts and improve compression efficiency. This paper proposes a low power DF architecture with hybrid and intelligent edge skip filtering order. We further adopt a four-stage pipeline to boost the speed of DF process and the proposed Horizontal Edge Skip Processing Architecture (HESPA offers an edge skip aware mechanism for filtering the horizontal edges that not only reduces power consumption but also reduces the filtering processes down to 100 clock cycles per macro block (MB. In addition, the architecture utilizes the buffers efficiently to store the temporary data without affecting the standard defined data dependency by a reasonable strategy of edge filtering order to enhance the reusability of the intermediate data. The system throughput can then be improved and the power consumption can also be reduced. Simulation results show that more than 34% of logic power measured in FPGA can be saved when the proposed HESPA is enabled. Furthermore, the proposed architecture is implemented on a 0.18μm standard cell library, which consumes 19.8K gates at a clock frequency of 200 MHz, which compares competitively with other state-of-the-art works in terms of hardware cost

  2. A low-power portable ECG sensor interface with dry electrodes

    International Nuclear Information System (INIS)

    This paper describes a low-power portable sensor interface dedicated to sensing and processing electrocardiogram (ECG) signals. Dry electrodes were employed in this ECG sensor, which eliminates the need of conductive gel and avoids complicated and mandatory skin preparation before electrode attachment. This ECG sensor system consists of two ICs, an analog front-end (AFE) and a successive approximation register analog-to-digital converter (SAR ADC) containing a relaxation oscillator. This proposed design was fabricated in a 0.18 μm 1P6M standard CMOS process. The AFE for extracting the biopotential signals is essential in this ECG sensor. In measurements, the AFE obtains a mid-band gain of 45 dB, a bandwidth from 0.6 to 160 Hz, and a total input referred noise of 2.8 μV rms while consuming 1 μW from the 1.8 V supply. The noise efficiency factor (NEF) of our design is 3.4. After conditioning, the amplified ECG signal is digitized by a 12-bit SAR ADC with 61.8 dB SNDR and 220 fJ/conversion-step. Finally, a complete ECG sensor interface with three dry copper electrodes is demonstrated in real-word setting, showing successful recordings of a capture ECG waveform. (semiconductor integrated circuits)

  3. Development of Risk Assessment Technology for Low Power, Shutdown and Digital I and C System

    International Nuclear Information System (INIS)

    There are two technical areas to deal with in the project: the low power and shutdown probabilistic safety assessment (PSA), and the digital I and C PSA. The scope and contents of each area could be summarized as follows: The LPSD PSA Area Ο Quality improvement of the KSNP LPSD PSA model in the following four technical areas; human reliability analysis (HR), system analysis (SY), data analysis (DA) and accident sequence quantification (QU) Ο Development of the LPSD configuration risk management(CRM) model - Study on the methodology for developing a CRM model, so-called ASLOC (Autonomous Shutdown LOgic Creation) - Development of the LPSD CRM model for the units of Ulchin 3 and 4 The Digital I and C PSA Area Ο Development of impact model of ESF-CCS on plant risks - Unavailability analysis of ESF-CCS for APR-1400 - Digital plant risk models for evaluating core damage frequency (CDF) Ο Study on the methodologies for treating digital-specific problems in the digital I and C PSA - Study on the methodology for evaluating safety-critical SW reliability by BBN techniques, including a feasibility study of reliability growth model - Study on the methodology for the safety-critical network system by Markov chain

  4. Influences of laser in low power YAG laser-MAG hybrid welding process

    Institute of Scientific and Technical Information of China (English)

    Ruisheng Huang; Liming Liu; Fan Zhang

    2008-01-01

    The influences of laser defocusing amount △z, laser power P, space distance DLA between laser and arc on weld penetration, arc modality and stability are investigated in low power YAG laser and metal active gas (laser-MAG) hybrid welding process. The experimental results indicate that the effects of laser-induced attraction and contraction of MAG arc are emerged in hybrid welding process, which result in the augmentation of hybrid welding energy. When DLA = -0.5 - 2 mm, △z = -2 - 2 mm and P ≥ 73 W, the synergic efficiency between laser and MAG arc is obvious, the cross section at the root of hybrid arc is contracted and the hybrid weld penetration is increased. The maximal ratio of hybrid/MAG weld penetration is 1.5 and the lowest YAG laser power that augments MAG arc is 73 W. The input of YAG laser makes the stabilities of arc ignition and combustion prominent in hybrid welding process.

  5. Electrothermal modeling, fabrication and analysis of low-power consumption thermal actuator with buckling arm

    KAUST Repository

    So, Hongyun

    2013-10-31

    © 2013, Springer-Verlag Berlin Heidelberg. This paper reports on a novel thermal actuator with sub-micron metallic structures and a buckling arm to operate with low voltages and to generate very large deflections, respectively. A lumped electrothermal model and analysis were also developed to validate the mechanical design and easily predict the temperature distribution along arms of the sub-micron actuator. The actuator was fabricated via the combination of electron beam lithography to form actuator arms with a minimum feature size of 200 nm and lift-off process to deposit a high aspect ratio nickel structure. Reproducible displacements of up to 1.9 μm at the tip were observed up to 250 mV under confocal microscope. The experimentally measured deflection values and theoretically calculated temperature distribution by the developed model were compared with finite element analysis results and they were in good agreement. This study shows a promising approach to develop more sophisticated nano actuators required larger deflections for manipulation of sub-micron scale objects with low-power consumption.

  6. The rotary zone thermal cycler: a low-power system enabling automated rapid PCR.

    Directory of Open Access Journals (Sweden)

    Michael S Bartsch

    Full Text Available Advances in molecular biology, microfluidics, and laboratory automation continue to expand the accessibility and applicability of these methods beyond the confines of conventional, centralized laboratory facilities and into point of use roles in clinical, military, forensic, and field-deployed applications. As a result, there is a growing need to adapt the unit operations of molecular biology (e.g., aliquoting, centrifuging, mixing, and thermal cycling to compact, portable, low-power, and automation-ready formats. Here we present one such adaptation, the rotary zone thermal cycler (RZTC, a novel wheel-based device capable of cycling up to four different fixed-temperature blocks into contact with a stationary 4-microliter capillary-bound sample to realize 1-3 second transitions with steady state heater power of less than 10 W. We demonstrate the utility of the RZTC for DNA amplification as part of a highly integrated rotary zone PCR (rzPCR system that uses low-volume valves and syringe-based fluid handling to automate sample loading and unloading, thermal cycling, and between-run cleaning functionalities in a compact, modular form factor. In addition to characterizing the performance of the RZTC and the efficacy of different online cleaning protocols, we present preliminary results for rapid single-plex PCR, multiplex short tandem repeat (STR amplification, and second strand cDNA synthesis.

  7. Comparative analysis of fixed and sun tracking low power PV systems considering energy consumption

    International Nuclear Information System (INIS)

    Highlights: • Photovoltaic system prototype with sun tracking. • Energy analysis of fixed and sun tracking built prototypes. • Experimental tests in different environmental conditions. • Theoretical and experimental validation of the prototype. - Abstract: Photovoltaic technology allows to directly convert solar energy into electrical energy with clear advantages: no environmental impact during operation, reliability and durability of the systems, reduced operating costs and maintenance, ability to both supply remote customers and simply connect to the electrical network. This paper evaluates the performance of two photovoltaic systems: one fixed and one equipped with a sun tracker. The objective of this research is to analyze the increase of daily produced energy by using the sun tracking system. The analysis accounts also the energy consumption of the sun tracker. An analytical approach is proposed. To validate the results through experimental tests, two alternative low power PV systems were built. Each system consists of a PV source, a MPPT (Maximum Power Point Tracker) power converter and a 12 V–40 A h electrochemical battery, which is used as electric load. The sun tracker system evidenced an important growth of power production during morning and evening

  8. A low-power CMOS trans-impedance amplifier for FM/cw ladar imaging system

    Science.gov (United States)

    Hu, Kai; Zhao, Yi-qiang; Sheng, Yun; Zhao, Hong-liang; Yu, Hai-xia

    2013-09-01

    A scannerless ladar imaging system based on a unique frequency modulation/continuous wave (FM/cw) technique is able to entirely capture the target environment, using a focal plane array to construct a 3D picture of the target. This paper presents a low power trans-impedance amplifier (TIA) designed and implemented by 0.18 μm CMOS technology, which is used in the FM/cw imaging ladar with a 64×64 metal-semiconductor-metal(MSM) self-mixing detector array. The input stage of the operational amplifier (op amp) in TIA is realized with folded cascade structure to achieve large open loop gain and low offset. The simulation and test results of TIA with MSM detectors indicate that the single-end trans-impedance gain is beyond 100 kΩ, and the -3 dB bandwidth of Op Amp is beyond 60 MHz. The input common mode voltage ranges from 0.2 V to 1.5 V, and the power dissipation is reduced to 1.8 mW with a supply voltage of 3.3 V. The performance test results show that the TIA is a candidate for preamplifier of the read-out integrated circuit (ROIC) in the FM/cw scannerless ladar imaging system.

  9. Design of Low Power CMOS Logic Circuits Using Gate Diffusion Input (GDI Technique

    Directory of Open Access Journals (Sweden)

    Y. Syamala

    2013-10-01

    Full Text Available The Gate diffusion input (GDI is a novel technique for low power digital circuit design. This technique reduces the power dissipation, propagation delay, area of digital circuits and it maintains low complexity of logic design. In this paper, the 4×1 Multiplexer, 8×3 Encoder, BCD Counter and Mealy State Machine were implemented by using Pass Transistors (PT, Transmission Gate (TG and Gate Diffusion Input (GDI technique and then they were compared with each other for power dissipation. The Multiplexers and Encoders are combinational circuits and Counters and mealy machines are sequential circuits both of them are very important digital systems so power optimization should be done to those digital circuits. The whole processes for development of digital circuits and simulation was done by using the mentor graphics backend tool. This method can also be extended to the processors and other high level designs for optimization of power dissipation, area and delay in order to increase the circuit efficiency.

  10. Low power analog readout front-end electronics for time and energy measurements

    International Nuclear Information System (INIS)

    We report on the design and measurements of an analog front-end readout electronics dedicated for silicon microstrip detectors with relatively large capacitance of the order of tens pF for time and energy measurements of incoming pulses. The front-end readout electronics is required to process input pulses with an average rate of 150 kHz/channel with low both power consumption and noise at the same time. In the presented solution the single channel is built of two different parallel processing paths: fast and slow. The fast path includes the fast CR–RC shaper with the peaking time tp=40 ns and is optimized to determine the input charge arrival time. The slow path, which consists of the slow CR–(RC)2 shaper with the peaking time tp=80 ns, is dedicated for low noise accurate energy measurement. The analog front-end electronics was implemented in UMC 180 nm CMOS technology as a prototype ASIC AFE. The AFE chip contains 8 channels with the size of 58 μm×1150 μm each. It has low power dissipation Pdiss=3.1 mW per single channel. The article presents the details of the front-end architecture and the measurement results

  11. Area-Efficient Low Power CMOS Image Sensor Readout Circuit with Fixed Pattern Noise Cancellation

    Institute of Scientific and Technical Information of China (English)

    ZHAO Shibin; YAO Suying; NIE Kaiming; XU Jiangtao

    2010-01-01

    A low cost of die area and power consumption CMOS image sensor readout circuit with fixed pattern noise(FPN)cancellation is proposed.By using only one coupling capacitor and switch in the double FPN cancelling correlative double sampling(CDS),pixel FPN is cancelled and column FPN is stored and eliminated by the sample-and-hold operation of digitally programmable gain amplifier(DPGA).The bandwidth balance technology based on operational amplifier(op-amp)sharing is also introduced to decrease the power dissipation of traditional multi-stage switched capacitor DPGA.The circuit is designed and simulated using 1P6M 0.18 μm 1.8 V/3.3 V process.Simulation results indicate that the proposed CDS scheme can achieve an FPN of less than 1 mV.The total sampling capacitor per column is 0.9 pF and no column-wise power is dissipated.The die area and FPN value are cut by 70% and 41% respectively compared with amplifier-based CDS.The op-amp sharing gain stage can achieve a 12-bit precision and also implement an 8-bit gain controlling within a gain range of 24 dB.Its power consumption is 1.4 mW,which is reduced by 57% compared with traditional schemes.The proposed readout circuit is suitable for the application of low power cost-sensitive imaging systems.

  12. A Low Cost/Low Power Open Source Sensor System for Automated Tuberculosis Drug Susceptibility Testing

    Science.gov (United States)

    Kim, Kyukwang; Kim, Hyeong Keun; Lim, Hwijoon; Myung, Hyun

    2016-01-01

    In this research an open source, low power sensor node was developed to check the growth of mycobacteria in a culture bottle with a nitrate reductase assay method for a drug susceptibility test. The sensor system reports the temperature and color sensor output frequency change of the culture bottle when the device is triggered. After the culture process is finished, a nitrite ion detecting solution based on a commercial nitrite ion detection kit is injected into the culture bottle by a syringe pump to check bacterial growth by the formation of a pigment by the reaction between the solution and the color sensor. Sensor status and NRA results are broadcasted via a Bluetooth low energy beacon. An Android application was developed to collect the broadcasted data, classify the status of cultured samples from multiple devices, and visualize the data for the end users, circumventing the need to examine each culture bottle manually during a long culture period. The authors expect that usage of the developed sensor will decrease the cost and required labor for handling large amounts of patient samples in local health centers in developing countries. All 3D-printerable hardware parts, a circuit diagram, and software are available online. PMID:27338406

  13. Experimental study of operation performance of a low power thermoelectric cooling dehumidifier

    Directory of Open Access Journals (Sweden)

    Wang Huajun, Qi Chengying

    2010-05-01

    Full Text Available The present work was performed to apply thermoelectric technology to a low power dehumidifying device as an alternative to the conventional vapor-compression refrigeration systems. The experimental prototype of a small-scale thermoelectric dehumidifier (TED with rectangular cooling fins was built and its operation performance was studied experimentally. The results showed that the TED experienced two typical thermodynamic processes including the cooling dehumidification and the isothermal dehumidification, where the latter was dominated. It was found that there existed a peak during the variation of the average coefficient of performance (COP as a function of the input power of the thermoelectric module. Under the present experimental conditions, the COP of the TED reached the maximum of 0.32 and the corresponding dehumidifying rate was 0.0097 g/min, when the input power was kept at 6.0 W. The rapid elimination of condensed liquid-drops on the cooling fins amounted on the thermoelectric module is a major approach to improving the operation performance of the TED.

  14. PERFORMANCE OF DIFFERENT CMOS LOGIC STYLES FOR LOW POWER AND HIGH SPEED

    Directory of Open Access Journals (Sweden)

    Sreenivasa Rao.Ijjada

    2012-06-01

    Full Text Available Designing high-speed low-power circuits with CMOS technology has been a major research problem for many years. Several logic families have been proposed and used to improve circuit performance beyond that of conventional static CMOS family. Fast circuit families are becoming attractive in deep sub micron technologies since the performance benefits obtained from process scaling are decreasing as feature size decreases. This paper presents CMOS differential circuit families such as Dual rail domino logic and pseudo Nmos logic their delay and power variations in terms of adder design and logical design. Domino CMOS has become the prevailing logic family for high performance CMOS applications and it is extensively used in most state-of-the-art processors due to its high speed capabilities. The drawback of domino CMOS is that it provides only non-inverting functions because of its monotonic nature. Dual-Rail Domino logic, (also known as clocked Cascade voltage switch logic where both polarities of the output are generated, provides a robust solution to this problem.

  15. PERFORMANCE OF DIFFERENT CMOS LOGIC STYLES FOR LOW POWER AND HIGH SPEED

    Directory of Open Access Journals (Sweden)

    Sreenivasa Rao.Ijjada

    2011-07-01

    Full Text Available Designing high-speed low-power circuits with CMOS technology has been a major research problem formany years. Several logic families have been proposed and used to improve circuit performance beyondthat of conventional static CMOS family. Fast circuit families are becoming attractive in deep submicrontechnologies since the performance benefits obtained from process scaling are decreasing as feature sizedecreases. This paper presents CMOS differential circuit families such as Dual rail domino logic andpseudo Nmos logic their delay and power variations in terms of adder design and logical design. DominoCMOS has become the prevailing logic family for high performance CMOS applications and it isextensively used in most state-of-the-art processors due to its high speed capabilities. The drawback ofdomino CMOS is that it provides only non-inverting functions because of its monotonic nature. Dual-RailDomino logic, (also known as clocked Cascade voltage switch logic where both polarities of the output aregenerated, provides a robust solution to this problem.

  16. A low-power portable ECG sensor interface with dry electrodes

    Institute of Scientific and Technical Information of China (English)

    Pu Xiaofei; Wan Lei; Zhang Hui; Qin Yajie; Hong Zhiliang

    2013-01-01

    This paper describes a low-power portable sensor interface dedicated to sensing and processing electrocardiogram (ECG) signals.Dry electrodes were employed in this ECG sensor,which eliminates the need of conductive gel and avoids complicated and mandatory skin preparation before electrode attachment.This ECG sensor system consists of two ICs,an analog front-end (AFE) and a successive approximation register analog-to-digital converter (SAR ADC) containing a relaxation oscillator.This proposed design was fabricated in a 0.18 μm 1P6M standard CMOS process.The AFE for extracting the biopotential signals is essential in this ECG sensor.In measurements,the AFE obtains a mid-band gain of 45 dB,a bandwidth from 0.6 to 160 Hz,and a total input referred noise of 2.8 μV rms while consuming 1 μW from the 1.8 V supply.The noise efficiency factor (NEF) of our design is 3.4.After conditioning,the amplified ECG signal is digitized by a 12-bit SAR ADC with 61.8 dB SNDR and 220 fJ/conversion-step.Finally,a complete ECG sensor interface with three dry copper electrodes is demonstrated in real-word setting,showing successful recordings of a capture ECG waveform.

  17. Design of an ultra low power CMOS pixel sensor for a future neutron personal dosimeter

    Energy Technology Data Exchange (ETDEWEB)

    Zhang, Y.; Hu-Guo, C.; Husson, D.; Hu, Y. [Institut Pluridisplinaire Hubert Curien IPHC, Univ. of Strasbourg, CNRS/IN2P3, 23 Rue du Loess, 67037 Strasbourg (France)

    2011-07-01

    Despite a continuously increasing demand, neutron electronic personal dosimeters (EPDs) are still far from being completely established because their development is a very difficult task. A low-noise, ultra low power consumption CMOS pixel sensor for a future neutron personal dosimeter has been implemented in a 0.35 {mu}m CMOS technology. The prototype is composed of a pixel array for detection of charged particles, and the readout electronics is integrated on the same substrate for signal processing. The excess electrons generated by an impinging particle are collected by the pixel array. The charge collection time and the efficiency are the crucial points of a CMOS detector. The 3-D device simulations using the commercially available Synopsys-SENTAURUS package address the detailed charge collection process. Within a time of 1.9 {mu}s, about 59% electrons created by the impact particle are collected in a cluster of 4 x 4 pixels with the pixel pitch of 80 {mu}m. A charge sensitive preamplifier (CSA) and a shaper are employed in the frond-end readout. The tests with electrical signals indicate that our prototype with a total active area of 2.56 x 2.56 mm{sup 2} performs an equivalent noise charge (ENC) of less than 400 e - and 314 {mu}W power consumption, leading to a promising prototype. (authors)

  18. Hydrodynamic and performance of low power turbines: conception, modelling and experimental tests

    Energy Technology Data Exchange (ETDEWEB)

    Simao, Mariana; Ramos, Helena M. [Civil Engineering Department and CEHIDRO, Instituto Superior Tecnico, Technical University of Lisbon, Av. Rovisco Pais, 1049-001, Lisbon (Portugal)

    2010-07-01

    The present work comprises a research about hydraulic machines with the aim of optimization and the selection of adequate turbines of low power for exploitation of an available energy still unexplored in water supply systems based on analyses of 3D hydrodynamic flows and on characteristic curves which lead to the best efficiency point. The analysis is carried out based on non-dimensional parameters (i.e., discharge, head, efficiency, runner speed and mechanical power) in order to be possible comparisons. Mathematical models based on the physical principles, associated to the development of volumetric and rotordynamic machines, are developed. New turbines are suggested, which are based on similar theory among turbo machines based on applications in hydraulic systems with guarantee discharge and available head. The hydrodynamic fluid mechanical analysis requires the use of complex advanced models (CFD) which apply the equations of Navier-Stokes by using mathematical models of conservation laws, for the study of the turbulent flow behaviour. To determine the correlation between the flow velocity and pressure fields, the k-epsilon model, is used in this research. Many turbines are evaluated (i.e., positive displacement (PD), pump as turbine (PAT), propeller with volute at inlet, four and five blades tubular propellers) and sensitivity analyses, to the best configurations, as well as comparisons between performance curves and experimental tests. Results are presented with the appropriate range variation for each turbine type and application.

  19. Simple Exact Algorithm for Transistor Sizing of Low-Power High-Speed Arithmetic Circuits

    Directory of Open Access Journals (Sweden)

    Tooraj Nikoubin

    2010-01-01

    Full Text Available A new transistor sizing algorithm, SEA (Simple Exact Algorithm, for optimizing low-power and high-speed arithmetic integrated circuits is proposed. In comparison with other transistor sizing algorithms, simplicity, accuracy, independency of order and initial sizing factors of transistors, and flexibility in choosing the optimization parameters such as power consumption, delay, Power-Delay Product (PDP, chip area or the combination of them are considered as the advantages of this new algorithm. More exhaustive rules of grouping transistors are the main trait of our algorithm. Hence, the SEA algorithm dominates some major transistor sizing metrics such as optimization rate, simulation speed, and reliability. According to approximate comparison of the SEA algorithm with MDE and ADC for a number of conventional full adder circuits, delay and PDP have been improved 55.01% and 57.92% on an average, respectively. By comparing the SEA and Chang's algorithm, 25.64% improvement in PDP and 33.16% improvement in delay have been achieved. All the simulations have been performed with 0.13 m technology based on the BSIM3v3 model using HSpice simulator software.

  20. A novel reactor concept for boron neutron capture therapy: annular low-low power reactor (ALLPR)

    Energy Technology Data Exchange (ETDEWEB)

    Petrovic, B.; Levine, S.H. [Department of Nuclear Engineering, Pennsylvania State University, University Park, PA 16802 (United States)

    1998-07-01

    Boron Neutron Capture Therapy (BNC), originally proposed in 50's, has been getting renewed attention over the last {approx}10 years. This is in particular due to its potential for treating deep-seated brain tumors by employing epithermal neutron beams. Large (several MW) research reactors are currently used to obtain epithermal beams for BNCT, but because of cost and licensing issues it is not likely that such high-power reactors can be placed in regular medical centers. This paper describes a novel reactor concept for BNCT devised to overcome this obstacle. The design objective was to produce a beam of epithermal neutrons of sufficient intensity for BNCT at <50 kW using low enriched uranium. It is achieved by the annular reactor design, which is called Annular Low-Low Power Reactor (ALLPR). Preliminary studies using Monte Carlo simulations are summarized in this paper. The ALLPR should be relatively economical to build, and safe and easy to operate. This novel concept may increase the viability of using BNCT in medical centers worldwide. (author)

  1. A vacuum tolerant high voltage system with a low noise and low power Cockcroft–Walton photomultiplier base

    International Nuclear Information System (INIS)

    We developed a high voltage system for the electromagnetic calorimeter of the KOTO detector. The system is designed around a low noise, low power Cockcroft–Walton (CW) photomultiplier tube base with a high gain preamplifier. The low power makes it suitable for operations in vacuum. The low noise and high gain allow detecting signals in the 1 MeV range. We achieved a final noise level below 180μVrms for a preamplifier gain of more than 40. A vacuum tolerant control system for the CW bases power distribution was also designed. This system is able to control and monitor the high voltage of each individual base

  2. A Low-Power Integrated Smart Sensor with on-Chip Real-Time Image Processing Capabilities

    Science.gov (United States)

    Barbaro, Massimo; Raffo, Luigi

    2005-12-01

    A low-power, CMOS retina with real-time, pixel-level processing capabilities is presented. Features extraction and edge-enhancement are implemented with fully programmable 1D Gabor convolutions. An equivalent computation rate of 3 GOPS is obtained at the cost of very low-power consumption ([InlineEquation not available: see fulltext.][InlineEquation not available: see fulltext.]W per pixel), providing real-time performances ([InlineEquation not available: see fulltext.] microseconds for overall computation,[InlineEquation not available: see fulltext.]). Experimental results from the first realized prototype show a very good matching between measures and expected outputs.

  3. A vacuum tolerant high voltage system with a low noise and low power Cockcroft–Walton photomultiplier base

    OpenAIRE

    Masuda, T.; Iwai, E.; Kawasaki, N; Kim, E. J.; Komatsubara, T. K.; Lee, J.W.; Lim, G. Y.; Maeda, Y.; Naito, D.; Nanjo, H.; Nomura, T.; Ri, Y. D.; Sasao, N.; Sato, K.; Seki, S.

    2014-01-01

    We developed a high voltage system for the electromagnetic calorimeter of the KOTO detector. The system is designed around a low noise, low power Cockcroft–Walton (CW) photomultiplier tube base with a high gain preamplifier. The low power makes it suitable for operations in vacuum. The low noise and high gain allow detecting signals in the 1 MeV range. We achieved a final noise level below 180 μV[rms] for a preamplifier gain of more than 40. A vacuum tolerant control system for the CW bases p...

  4. Very low power consumption Viterbi decoder LSIC employing the SST (Scarce State Transition) scheme for multimedia mobile communications

    Science.gov (United States)

    Seki, K.; Kubota, S.; Mizoguchi, M.; Kato, S.

    1994-04-01

    A very low power consumption Viterbi decoder LSIC has been developed by using a low supply voltage 0.8 micron CMOS master slice process technology. By employing the scarce state transition (SST) scheme, this LSIC achieves a drastic reduction in power consumption below 600 mu W at a supply voltage of IV when the data rate is 1152 kbit/s and the bit error rate is less than 10(exp - 3). This excellent performance has paved the way to employing the strong forward error correction and low power consumption portable terminals for personal communications, mobile multimedia communications, and digital and audio broadcasting.

  5. Low power laser in the treatment of the acute low back pain

    Directory of Open Access Journals (Sweden)

    Mandić Milan

    2011-01-01

    Full Text Available Beckground/Aim. Acute low back pain (ALBP is one of the most frequent painful conditions in the human population. The objective of the paper was to compare the efficacy of the low power laser (LPL in the pain and the muscular spasm reduction with conservative methods of physical medicine. Method. The prospective cohort study was done. The study involved 70 patients, both men and women, from 25 to 64 years of age with the diagnosis of ALBP. Two groups were formed. There were 40 patients in the first group and they were treated with the LPL with frequency of 73 Hz. The second group was the control one and it consisted of 30 patients who were treated with conservative methods of physical medicine (electrotherapy: diadynamic currents CP ± 3 and CP ± 3, interferent currents - 90 Hz for 15 min; electrophoresis with novocaine. The ALBP were diagnosed by clinical examination and by the nuclear magnetic resonance imaging (NMRI. The low power laser - Gallium Arsenide (GaAs was used. The laser sonde consisted of 4 laser diodes, each powered of 15 mW, wavelength 904 nm and with frequency 73Hz. The total period of time for each treatment was 10 minutes and the total dose per treatment was 15 J. The intensity of acute low back pain was assessed by Roland´s scale. The degree of the spasm was assessed in the relaxed position and during movements. Results. The average score in the first group before the onset of rehabilitation was 3.3 ± 1.1 (Me = 3.0, and in the control group was 3.43 ± 0.89 (Me = 3.0. After five treatments in patients who were treated with LPL the average score in Roland´s scale was decreased (1.12 ± 1.3, Me = 2.0 and in the control group there were no changes. After 10 treatments with the LPL the analgesic effect was obtained in 82.5% of patients from the first group and in 20% of patients in the control group. The analgesic effect in patients of the first group was obtained after 7.5 ± 2.1 treatments and in the second group after 17

  6. Low power energy harvesting and storage techniques from ambient human powered energy sources

    Science.gov (United States)

    Yildiz, Faruk

    small amounts of electricity to low-power electronic devices. These studies were focused to investigate and obtain power from different energy sources, such as vibration, light, sound, airflow, heat, waste mechanical energy and temperature variations. This research studied forms of ambient energy sources such as waste mechanical (rotational) energy from hydraulic door closers, and fitness exercise bicycles, and its conversion and storage into usable electrical energy. In both of these examples of applications, hydraulic door closers and fitness exercise bicycles, human presence is required. A person has to open the door in order for the hydraulic door closer mechanism to function. Fitness exercise bicycles need somebody to cycle the pedals to generate electricity (while burning calories.) Also vibrations, body motions, and compressions from human interactions were studied using small piezoelectric fiber composites which are capable of recovering waste mechanical energy and converting it to useful electrical energy. Based on ambient energy sources, electrical energy conversion and storage circuits were designed and tested for low power electronic applications. These sources were characterized according to energy harvesting (scavenging) methods, and power and energy density. At the end of the study, the ambient energy sources were matched with possible electronic applications as a viable energy source.

  7. Microminiature rotary Stirling cryocooler for compact, lightweight, and low-power thermal imaging systems

    Science.gov (United States)

    Filis, Avishai; Bar Haim, Zvi; Pundak, Nachman; Broyde, Ramon

    2009-05-01

    Novel compact and low power consuming cooled infrared thermal imagers as used in gyro-stabilized payloads of miniature unmanned aerial vehicles, Thermal small arms sights and tactical night vision goggles often rely on integral rotary micro-miniature closed cycle Stirling cryogenic engines. Development of EPI Antimonides technology and optimization of MCT technology allowed decreasing in order of magnitudes the level of dark current in infrared detectors thus enabling an increase in the optimal focal plane temperature in excess of 95K while keeping the same radiometric performances as achieved at 77K using regular technologies. Maintaining focal plane temperature in the range of 95K to 110K instead of 77K improves the efficiency of Stirling thermodynamic cycle thus enlarging cooling power and enabling the development of a mini micro cooler similar to RICOR's K562S model which is three times smaller, lighter and more compact than a standard tactical cryocooler like RICOR's K508 model. This cooler also features a new type of ball bearings and internal components which were optimized to fit tight bulk constraints and maintain the required life span, while keeping a low level of vibration and noise signature. Further, the functions of management the brushless DC motor and temperature stabilization are delivered by the newly developed high performance sensorless digital controller. By reducing Dewar Detector thermal losses and increasing the focal plane temperature, longer life time operation is expected as was proved with RICOR's K508 model. Resulting from this development, the RICOR K562S model cryogenic engine consumes 1.2 - 3.0 WDC while operating in the closed loop mode and maintaining the typical focal plane arrays at 200-100K. This makes it compatible with very compact battery packages allowing further reduction of the overall thermal imager weight thus making it comparable with the compatible uncooled infrared thermal imager relying on a microbolometer detector

  8. Low-power optically addressed spatial light modulators using MBE-grown III-V structures

    Science.gov (United States)

    Maserjian, Joseph L.; Larsson, Anders G.

    1991-12-01

    Device approaches are investigated for O-SLMs based on MBE engineered III-V materials and structures. Strong photo-optic effects can be achieved in periodically (delta) -doped multiple quantum well (MQW) structures. The doping-defined barriers serve to separate and delay recombination of the photo-generated electron-hole pairs. One can use this photo-effect to change the internal field across the MQWs giving rise to quantum-confined Stark shift. Alternately, the photo-generated electrons can be used to occupy the quantum wells, which in turn causes exciton quenching and a shift of the absorption edge. Recent work has shown that both of these predicted photo-optic effects can indeed be achieved in such MBE engineered structures. However, these enhanced effects are still insufficient for high contrast modulation with only single or double pass absorption through active layers of practical thickness. We use the asymmetric Fabry-Perot cavity approach which permits extinction of light due to interference of light reflected from the front and back surfaces of the cavity. Modulation of the absorption in the active cavity layers unbalances the cavity and 'turns on' the reflected output signal, thereby allowing large contrast ratios. This approach is realized with an all-MBE- grown structure consisting of a GaAs/AlAs quarter-wave stack reflector grown over the GaAs substrate as the high reflectance mirror (approximately equals 0.98) and the GaAs surface as the low reflectance mirror (approximately equals 0.3). We use for our active cavities InGaAs/GaAs MQWs separated by npn (delta) -doped GaAs barriers to achieve sensitive photo-optic effect due to exciton quenching. High contrast modulation (> 60:1) is achieved with the Fabry-Perot structures using low power (write signal.

  9. Risk contribution from low power, shutdown, and other operational modes beyond full power

    Energy Technology Data Exchange (ETDEWEB)

    Whitehead, D.W.; Brown, T.D. [Sandia National Labs., Albuquerque, NM (United States); Chu, T.L. [Brookhaven National Lab., Upton, NY (United States)] [and others

    1995-04-01

    During 1989 the Nuclear Regulatory Commission (NRC) initiated an extensive program to carefully examine the potential risks during low power and shutdown operations. Two plants, Surry (a pressurized water reactor) and Grand Gulf (a boiling water reactor), were selected for study by Brookhaven National Laboratory and Sandia National Laboratories, respectively. The program objectives included assessing the risks of severe accidents initiated during plant operational states other than full power and comparing estimated core damage frequencies, important accident sequences, and other qualitative and quantitative results with full power accidents as assessed in NUREG-1150. The scope included a Level 3 probabilistic risk assessment (PRA) for traditional internal events and a Level 1 PRA on fire, flooding, and seismically induced core damage sequences. A phased approach was used in Level 1. In Phase 1 the concept of plant operational states (POSs) was developed to provide a better representation of the plant as it transitions from power to nonpower operation. This included a coarse screening analysis of all POSs to identify vulnerable plant configurations, to characterize (on a high, medium, or low basis) potential frequencies of core damage accidents, and to provide a foundation for a detailed Phase 2 analysis. In Phase 2, selected POSs from both Grand Gulf and Surry were chosen for detailed analysis. For Grand Gulf, POS 5 (approximately cold shutdown as defined by Grand Gulf Technical Specifications) during a refueling outage was selected. For Surry, three POSs representing the time the plant spends in midloop operation were chosen for analysis. These included POS 6 and POS 10 of a refueling outage and POS 6 of a drained maintenance outage. Level 1 and Level 2/3 results from both the Surry and Grand Gulf analyses are presented.

  10. Multi-Threshold NULL Convention Logic (MTNCL: An Ultra-Low Power Asynchronous Circuit Design Methodology

    Directory of Open Access Journals (Sweden)

    Liang Zhou

    2015-05-01

    Full Text Available This paper develops an ultra-low power asynchronous circuit design methodology, called Multi-Threshold NULL Convention Logic (MTNCL, also known as Sleep Convention Logic (SCL, which combines Multi-Threshold CMOS (MTCMOS with NULL Convention Logic (NCL, to yield significant power reduction without any of the drawbacks of applying MTCMOS to synchronous circuits. In contrast to other power reduction techniques that usually result in large area overhead, MTNCL circuits are actually smaller than their original NCL versions. MTNCL utilizes high-Vt transistors to gate power and ground of a low-Vt logic block to provide for both fast switching and very low leakage power when idle. To demonstrate the advantages of MTNCL, a number of 32-bit IEEE single-precision floating-point co-processors were designed for comparison using the 1.2 V IBM 8RF-LM 130 nm CMOS process: original NCL, MTNCL with just combinational logic (C/L slept, Bit-Wise MTNCL (BWMTNCL, MTNCL with C/L and completion logic slept, MTNCL with C/L, completion logic, and registers slept, MTNCL with Safe Sleep architecture, and synchronous MTCMOS. These designs are compared in terms of throughput, area, dynamic energy, and idle power, showing the tradeoffs between the various MTNCL architectures, and that the best MTNCL design is much better than the original NCL design in all aspects, and much better than the synchronous MTCMOS design in terms of area, energy per operation, and idle power, although the synchronous design can operate faster.

  11. Plasmonics-Based Multifunctional Electrodes for Low-Power-Consumption Compact Color-Image Sensors.

    Science.gov (United States)

    Lin, Keng-Te; Chen, Hsuen-Li; Lai, Yu-Sheng; Chi, Yi-Min; Chu, Ting-Wei

    2016-03-01

    High pixel density, efficient color splitting, a compact structure, superior quantum efficiency, and low power consumption are all important features for contemporary color-image sensors. In this study, we developed a surface plasmonics-based color-image sensor displaying a high photoelectric response, a microlens-free structure, and a zero-bias working voltage. Our compact sensor comprised only (i) a multifunctional electrode based on a single-layer structured aluminum (Al) film and (ii) an underlying silicon (Si) substrate. This approach significantly simplifies the device structure and fabrication processes; for example, the red, green, and blue color pixels can be prepared simultaneously in a single lithography step. Moreover, such Schottky-based plasmonic electrodes perform multiple functions, including color splitting, optical-to-electrical signal conversion, and photogenerated carrier collection for color-image detection. Our multifunctional, electrode-based device could also avoid the interference phenomenon that degrades the color-splitting spectra found in conventional color-image sensors. Furthermore, the device took advantage of the near-field surface plasmonic effect around the Al-Si junction to enhance the optical absorption of Si, resulting in a significant photoelectric current output even under low-light surroundings and zero bias voltage. These plasmonic Schottky-based color-image devices could convert a photocurrent directly into a photovoltage and provided sufficient voltage output for color-image detection even under a light intensity of only several femtowatts per square micrometer. Unlike conventional color image devices, using voltage as the output signal decreases the area of the periphery read-out circuit because it does not require a current-to-voltage conversion capacitor or its related circuit. Therefore, this strategy has great potential for direct integration with complementary metal-oxide-semiconductor (CMOS)-compatible circuit

  12. A low-power 32-channel digitally programmable neural recording integrated circuit.

    Science.gov (United States)

    Wattanapanitch, W; Sarpeshkar, R

    2011-12-01

    We report the design of an ultra-low-power 32-channel neural-recording integrated circuit (chip) in a 0.18 μ m CMOS technology. The chip consists of eight neural recording modules where each module contains four neural amplifiers, an analog multiplexer, an A/D converter, and a serial programming interface. Each amplifier can be programmed to record either spikes or LFPs with a programmable gain from 49-66 dB. To minimize the total power consumption, an adaptive-biasing scheme is utilized to adjust each amplifier's input-referred noise to suit the background noise at the recording site. The amplifier's input-referred noise can be adjusted from 11.2 μVrms (total power of 5.4 μW) down to 5.4 μVrms (total power of 20 μW) in the spike-recording setting. The ADC in each recording module digitizes the a.c. signal input to each amplifier at 8-bit precision with a sampling rate of 31.25 kS/s per channel, with an average power consumption of 483 nW per channel, and, because of a.c. coupling, allows d.c. operation over a wide dynamic range. It achieves an ENOB of 7.65, resulting in a net efficiency of 77 fJ/State, making it one of the most energy-efficient designs for neural recording applications. The presented chip was successfully tested in an in vivo wireless recording experiment from a behaving primate with an average power dissipation per channel of 10.1 μ W. The neural amplifier and the ADC occupy areas of 0.03 mm(2) and 0.02 mm(2) respectively, making our design simultaneously area efficient and power efficient, thus enabling scaling to high channel-count systems.

  13. Statistics of 150-km echoes over Jicamarca based on low-power VHF observations

    Directory of Open Access Journals (Sweden)

    J. L. Chau

    2006-07-01

    Full Text Available In this work we summarize the statistics of the so-called 150-km echoes obtained with a low-power VHF radar operation at the Jicamarca Radio Observatory (11.97 S, 76.87 W, and 1.3 dip angle at 150-km altitude in Peru. Our results are based on almost four years of observations between August 2001 and July 2005 (approximately 150 days per year. The majority of the observations have been conducted between 08:00 and 17:00 LT. We present the statistics of occurrence of the echoes for each of the four seasons as a function of time of day and altitude. The occurrence frequency of the echoes is ~75% around noon and start decreasing after 15:00 LT and disappear after 17:00 LT in all seasons. As shown in previous campaign observations, the 150-echoes appear at a higher altitude (>150 km in narrow layers in the morning, reaching lower altitudes (~135 km around noon, and disappear at higher altitudes (>150 km after 17:00 LT. We show that although 150-km echoes are observed all year long, they exhibit a clear seasonal variability on altitudinal coverage and the percentage of occurrence around noon and early in the morning. We also show that there is a strong day-to-day variability, and no correlation with magnetic activity. Although our results do not solve the 150-km riddle, they should be taken into account when a reasonable theory is proposed.

  14. SmartStep: A Fully Integrated, Low-Power Insole Monitor

    Directory of Open Access Journals (Sweden)

    Nagaraj Hegde

    2014-06-01

    Full Text Available Shoe-mounted wearable sensors can be used in applications, such as activity monitoring, gait analysis, post-stroke rehabilitation, body weight measurements and energy expenditure studies. Such wearable sensors typically require the modification or alteration of the shoe, which is not typically feasible for large populations without the direct involvement of shoe manufacturers. This article presents an insole-based wearable sensor (SmartStep that has its electronics fully embedded into a generic insole, which is usable with a large variety of shoes and, thus, resolves the need for shoe modification. The SmartStep is an always-on electronic device that comprises a 3D accelerometer, a 3D gyroscope and resistive pressure sensors implemented around a CC2540 system-on-chip with an 8051 processor core, Bluetooth low energy (BLE connectivity and flash memory buffer. The SmartStep is wirelessly interfaced to an Android smart phone application with data logging and visualization capabilities. This article focuses on low-power implementation methods and on the method developed for reliable data buffering, alleviating intermittent connectivity resulting from the user leaving the vicinity of the smart phone. The conducted tests illustrate the power consumption for several possible usage scenarios and the reliability of the data retention method. The trade-off between the power consumption and supported functionality is discussed, demonstrating that SmartStep can be worn for more than two days between battery recharges. The results of the mechanical reliability test on the SmartStep indicate that the pressure sensors in the SmartStep tolerated prolonged human wear. The SmartStep system collected more than 98.5% of the sensor data, in real usage scenarios, having intermittent connectivity with the smart phone.

  15. Understanding the Performance of Low Power Raspberry Pi Cloud for Big Data

    Directory of Open Access Journals (Sweden)

    Wajdi Hajji

    2016-06-01

    Full Text Available Nowadays, Internet-of-Things (IoT devices generate data at high speed and large volume. Often the data require real-time processing to support high system responsiveness which can be supported by localised Cloud and/or Fog computing paradigms. However, there are considerably large deployments of IoT such as sensor networks in remote areas where Internet connectivity is sparse, challenging the localised Cloud and/or Fog computing paradigms. With the advent of the Raspberry Pi, a credit card-sized single board computer, there is a great opportunity to construct low-cost, low-power portable cloud to support real-time data processing next to IoT deployments. In this paper, we extend our previous work on constructing Raspberry Pi Cloud to study its feasibility for real-time big data analytics under realistic application-level workload in both native and virtualised environments. We have extensively tested the performance of a single node Raspberry Pi 2 Model B with httperf and a cluster of 12 nodes with Apache Spark and HDFS (Hadoop Distributed File System. Our results have demonstrated that our portable cloud is useful for supporting real-time big data analytics. On the other hand, our results have also unveiled that overhead for CPU-bound workload in virtualised environment is surprisingly high, at 67.2%. We have found that, for big data applications, the virtualisation overhead is fractional for small jobs but becomes more significant for large jobs, up to 28.6%.

  16. Building IoT Applications with Raspberry Pi and Low Power IQRF Communication Modules

    Directory of Open Access Journals (Sweden)

    Isidro Calvo

    2016-09-01

    Full Text Available Typical Internet of Things (IoT applications involve collecting information automatically from diverse geographically-distributed smart sensors and concentrating the information into more powerful computers. The Raspberry Pi platform has become a very interesting choice for IoT applications for several reasons: (1 good computing power/cost ratio; (2 high availability; it has become a de facto hardware standard; and (3 ease of use; it is based on operating systems with a big community of users. In IoT applications, data are frequently carried by means of wireless sensor networks in which energy consumption is a key issue. Energy consumption is especially relevant for smart sensors that are scattered over wide geographical areas and may need to work unattended on batteries for long intervals of time. In this scenario, it is convenient to ease the construction of IoT applications while keeping energy consumption to a minimum at the sensors. This work proposes a possible gateway implementation with specific technologies. It solves the following research question: how to build gateways for IoT applications with Raspberry Pi and low power IQRF communication modules. The following contributions are presented: (1 one architecture for IoT gateways that integrates data from sensor nodes into a higher level application based on low-cost/low-energy technologies; (2 bindings in Java and C that ease the construction of IoT applications; (3 an empirical model that describes the consumption of the communications at the nodes (smart sensors and allows scaling their batteries; and (4 validation of the proposed energy model at the battery-operated nodes.

  17. Long term observation of low-power diode laser welding after penetrating keratoplasty in human patients

    Science.gov (United States)

    Rossi, Francesca; Matteini, Paolo; Pini, Roberto; Menabuoni, Luca; Lenzetti, Ivo

    2010-02-01

    Low power diode laser welding is a recently developed technique used as a support tool for conventional suturing in ophthalmic surgery. The main application is in penetrating keratoplasty: in the last four years (2005-2009), clinical trials were performed at the Ophthalmic Department of Prato, Italy). In penetrating keratoplasty, diode laser welding is used to assure the transplanted corneal button in its final position. The donor tissue is positioned in the recipient eye and 8-16 single stitches are apposed. The surgical wound is then stained with a saturated (10% w/w) sterile water solution of Indocyanine Green (ICG), it is washed with sterile water and then a diode laser (810 nm, 13 W/cm2) is used to induce the sealing of the wound. The laser light induces a thermal effect, localized in the stained tissue. In vivo and ex vivo studies in animal models evidenced that welding induces a modification of the corneal collagen architecture through the wound walls, thus enabling a short healing time and a good restoration of the tissue. In this study on human subjects, we confirmed the results evidenced in animal models, by morphological observations. In two cases out of 60, transplant rejection was observed. It was thus possible to study the efficacy of laser welding in the closure of the wound one year after implant. Direct morphological observation evidenced good strengthens of the welded tissue. Histological analysis pointed out a good restoration of the regular collagen architecture at the external perimeter of the corneal button, where laser welding was performed, showing the occurrence of a correct and effective wound healing process.

  18. Silicon, germanium, and III-V-based tunneling devices for low-power applications

    Science.gov (United States)

    Smith, Joshua T.

    While the scaling of transistor dimensions has kept pace with Moore's Law, the voltages applied to these devices have not scaled in tandem, giving rise to ever-increasing power/heating challenges in state-of-the-art integrated circuits. A primary reason for this scaling mismatch is due to the thermal limit---the 60 mV minimum required at room temperature to change the current through the device by one order of magnitude. This voltage scaling limitation is inherent in devices that rely on the mechanism of thermal emission of charge carriers over a gate-controlled barrier to transition between the ON- and OFF-states, such as in the case of conventional CMOS-based technologies. To overcome this voltage scaling barrier, several steep-slope device concepts have been pursued that have experimentally demonstrated sub-60-mV/decade operation since 2004, including the tunneling-field effect transistor (TFET), impact ionization metal-oxide-semiconductor (IMOS), suspended-gate FET (SG-FET), and ferroelectric FET (Fe-FET). These reports have excited strong efforts within the semiconductor research community toward the realization of a low-power device that will support continued scaling efforts, while alleviating the heating issues prevalent in modern computer chips. Literature is replete with claims of sub-60-mV/decade operation, but often with neglect to other voltage scaling factors that offset this result. Ideally, a low-power device should be able to attain sub-60-mV/decade inverse subthreshold slopes (S) employing low supply and gate voltages with a foreseeable path toward integration. This dissertation describes the experimental development and realization of CMOS-compatible processes to enhance tunneling efficiency in Si and Si/Ge nanowire (NW) TFETs for improved average S (S avg) and ON-currents (ION), and a novel, III-V-based tunneling device alternative is also proposed. After reviewing reported efforts on the TFET, IMOS, and SG-FET, the TFET is highlighted as the

  19. Effect of Auricular Acupuncture with Low Power Laser on Four Chronic Allergic Dermatoses and Serum IgE Level

    Institute of Scientific and Technical Information of China (English)

    You-hong Hou; Fang Xu; Shao-xi Wu

    2005-01-01

    @@ The objective of the study was to investigate the effectiveness of low power laser irradiating auricular points on four chronic allergic dermatoses including eczema, urticaria, facial cosmetic dermatitis, and atopic dermatitis, and on the changes of serum IgE level.

  20. A Review on “FPGA Implementation of Low Power QPSK Modulator by Using Hardware Co-Simulation”

    Directory of Open Access Journals (Sweden)

    Preksha R. Kolankar

    2014-02-01

    Full Text Available This paper presents a study of different concepts of FPGA implementation of QPSK modulator based on simulation with Xilinx System Generator. The different way of designing QPSK Modulator are discussed in details along with its respective concerts such as low power, reduced hardware and many application oriented approaches.