WorldWideScience

Sample records for charge-based low-power high-snr

  1. High SNR Consistent Compressive Sensing

    OpenAIRE

    Kallummil, Sreejith; Kalyani, Sheetal

    2017-01-01

    High signal to noise ratio (SNR) consistency of model selection criteria in linear regression models has attracted a lot of attention recently. However, most of the existing literature on high SNR consistency deals with model order selection. Further, the limited literature available on the high SNR consistency of subset selection procedures (SSPs) is applicable to linear regression with full rank measurement matrices only. Hence, the performance of SSPs used in underdetermined linear models ...

  2. Free-space optical communications with peak and average constraints: High SNR capacity approximation

    KAUST Repository

    Chaaban, Anas

    2015-09-07

    The capacity of the intensity-modulation direct-detection (IM-DD) free-space optical channel with both average and peak intensity constraints is studied. A new capacity lower bound is derived by using a truncated-Gaussian input distribution. Numerical evaluation shows that this capacity lower bound is nearly tight at high signal-to-noise ratio (SNR), while it is shown analytically that the gap to capacity upper bounds is a small constant at high SNR. In particular, the gap to the high-SNR asymptotic capacity of the channel under either a peak or an average constraint is small. This leads to a simple approximation of the high SNR capacity. Additionally, a new capacity upper bound is derived using sphere-packing arguments. This bound is tight at high SNR for a channel with a dominant peak constraint.

  3. MIMO Intensity-Modulation Channels: Capacity Bounds and High SNR Characterization

    KAUST Repository

    Chaaban, Anas

    2016-10-01

    The capacity of MIMO intensity modulation channels is studied. The nonnegativity of the transmit signal (intensity) poses a challenge on the precoding of the transmit signal, which limits the applicability of classical schemes in this type of channels. To resolve this issue, capacity lower bounds are developed by using precoding-free schemes. This is achieved by channel inversion or QR decomposition to convert the MIMO channel to a set of parallel channels. The achievable rate of a DC-offset SVD based scheme is also derived as a benchmark. Then, a capacity upper bound is derived and is shown to coincide with the achievable rate of the QR decomposition based scheme at high SNR, consequently characterizing the high-SNR capacity of the channel. The high-SNR gap between capacity and the achievable rates of the channel inversion and the DC-offset SVD based schemes is also characterized. Finally, the ergodic capacity of the channel is also briefly discussed.

  4. Applications of Tauberian Theorem for High-SNR Analysis of Performance over Fading Channels

    CERN Document Server

    Zhang, Yuan

    2011-01-01

    This paper derives high-SNR asymptotic average error rates over fading channels by relating them to the outage probability, under mild assumptions. The analysis is based on the Tauberian theorem for Laplace transforms which is grounded on the notion of regular variation, and applies to a wider range of channel distributions than existing approaches. The theory of regular variation is argued to be the proper mathematical framework for finding sufficient and necessary conditions for outage events to dominate high-SNR error rate performance. It is proved that the diversity order being $d$ and the cumulative distribution function (CDF) of the channel power gain having variation exponent $d$ at 0 imply each other, provided that the instantaneous error rate is upper-bounded by an exponential function of the instantaneous SNR. High-SNR asymptotic average error rates are derived for specific instantaneous error rates. Compared to existing approaches in the literature, the asymptotic expressions are related to the cha...

  5. Quasi Cyclic Low Density Parity Check Code for High SNR Data Transfer

    Directory of Open Access Journals (Sweden)

    M. R. Islam

    2010-06-01

    Full Text Available An improved Quasi Cyclic Low Density Parity Check code (QC-LDPC is proposed to reduce the complexity of the Low Density Parity Check code (LDPC while obtaining the similar performance. The proposed QC-LDPC presents an improved construction at high SNR with circulant sub-matrices. The proposed construction yields a performance gain of about 1 dB at a 0.0003 bit error rate (BER and it is tested on 4 different decoding algorithms. Proposed QC-LDPC is compared with the existing QC-LDPC and the simulation results show that the proposed approach outperforms the existing one at high SNR. Simulations are also performed varying the number of horizontal sub matrices and the results show that the parity check matrix with smaller horizontal concatenation shows better performance.

  6. Optical intensity modulation direct detection versus heterodyne detection: A high-SNR capacity comparison

    KAUST Repository

    Chaaban, Anas

    2016-09-15

    An optical wireless communications system which employs either intensity-modulation and direct-detection (IM-DD) or heterodyne detection (HD) is considered. IM-DD has lower complexity and cost than HD, but on the other hand, has lower capacity. It is therefore interesting to investigate the capacity gap between the two systems. The main focus of this paper is to investigate this gap at high SNR. Bounds on this gap are established for two cases: between IM-DD and HD, and between IM-DD and an HD-PAM which is an HD system employing pulse-amplitude modulation (PAM). While the gap between IM-DD and HD increases as the signal-to-noise ratio (SNR) increases, the gap between IM-DD and an HD-PAM is upper bounded by a constant at high SNR. © 2015 IEEE.

  7. Low Power Folded Cascode OTA

    Directory of Open Access Journals (Sweden)

    Swati Kundra

    2012-03-01

    Full Text Available Low power is one of the key research area in today’s electronic industry. Need of low power has created a major pattern shift in the field of electronics where power dissipation is equally important as area, performance etc. Several low power portable electronic equipments, low voltage design techniques havebeen developed and have driven analog designers to create techniques eg. Self cascode mosfet and stacking technique. For this aim in mind we designed a Folded Cascode using low power techniques and analyzed its various properties through the Spice simulations for 0.13 micron CMOS technology from TSMC and thesupply voltage 1.8V.

  8. Low Power Folded Cascode OTA

    Directory of Open Access Journals (Sweden)

    Swati Kundra

    2012-02-01

    Full Text Available Low power is one of the key research area in today’s electronic industry. Need of low power has created a major pattern shift in the field of electronics where power dissipation is equally important as area, performance etc. Several low power portable electronic equipments, low voltage design techniques have been developed and have driven analog designers to create techniques eg. Self cascode mosfet and stacking technique. For this aim in mind we designed a Folded Cascode using low power techniques and analyzed its various properties through the Spice simulations for 0.13 micron CMOS technology from TSMC and the supply voltage 1.8V.

  9. Low power digital signal processing

    DEFF Research Database (Denmark)

    Paker, Ozgun

    2003-01-01

    This thesis introduces a novel approach to programmable and low power platform design for audio signal processing, in particular hearing aids. The proposed programmable platform is a heterogeneous multiprocessor architecture consisting of small and simple instruction set processors called mini...... data addressing capabilities lead to the design of low power mini-cores. The algorithm suite also consisted of less demanding and/or irregular algorithms (LMS, compression) that required subsample rate signal processing justifying the use of a DSP/CPU-core. The thesis also contributes to the recent...... trend in the development of intellectual property based design methodologies. The actual mini-core designs are parameterized in word-size, memory-size, etc. and can be instantiated according to the needs of the application at hand. They are intended as low power programmable building blocks...

  10. Low Power CMOS Analog Multiplier

    Directory of Open Access Journals (Sweden)

    Shipra Sachan

    2015-12-01

    Full Text Available In this paper Low power low voltage CMOS analog multiplier circuit is proposed. It is based on flipped voltage follower. It consists of four voltage adders and a multiplier core. The circuit is analyzed and designed in 0.18um CMOS process model and simulation results have shown that, under single 0.9V supply voltage, and it consumes only 31.8µW quiescent power and 110MHZ bandwidth.

  11. High-speed and high-SNR photoacoustic microscopy based on a galvanometer mirror in non-conducting liquid

    Science.gov (United States)

    Kim, Jin Young; Lee, Changho; Park, Kyungjin; Han, Sangyeob; Kim, Chulhong

    2016-10-01

    Optical-resolution photoacoustic microscopy (OR-PAM), a promising microscopic imaging technique with high ultrasound resolution and superior optical sensitivity, can provide anatomical, functional, and molecular information at scales ranging from the microvasculature to single red blood cells. In particular, real-time OR-PAM imaging with a high signal-to-noise ratio (SNR) is a prerequisite for widespread use in preclinical and clinical applications. Although several technical approaches have been pursued to simultaneously improve the imaging speed and SNR of OR-PAM, they are bulky, complex, not sensitive, and/or not actually real-time. In this paper, we demonstrate a simple and novel OR-PAM technique which is based on a typical galvanometer immersed in non-conducting liquid. Using an opto-ultrasound combiner, this OR-PAM system achieves a high SNR and fast imaging speed. It takes only 2 seconds to acquire a volumetric image with a wide field of view (FOV) of 4 × 8 mm2 along the X and Y axes, respectively. The measured lateral and axial resolutions are 6.0 and 37.7 μm, respectively. Finally, as a demonstration of the system’s capability, we successfully imaged the microvasculature in a mouse ear in vivo. Our new method will contribute substantially to the popularization and commercialization of OR-PAM in various preclinical and clinical applications.

  12. High-speed and high-SNR photoacoustic microscopy based on a galvanometer mirror in non-conducting liquid

    Science.gov (United States)

    Kim, Jin Young; Lee, Changho; Park, Kyungjin; Han, Sangyeob; Kim, Chulhong

    2016-01-01

    Optical-resolution photoacoustic microscopy (OR-PAM), a promising microscopic imaging technique with high ultrasound resolution and superior optical sensitivity, can provide anatomical, functional, and molecular information at scales ranging from the microvasculature to single red blood cells. In particular, real-time OR-PAM imaging with a high signal-to-noise ratio (SNR) is a prerequisite for widespread use in preclinical and clinical applications. Although several technical approaches have been pursued to simultaneously improve the imaging speed and SNR of OR-PAM, they are bulky, complex, not sensitive, and/or not actually real-time. In this paper, we demonstrate a simple and novel OR-PAM technique which is based on a typical galvanometer immersed in non-conducting liquid. Using an opto-ultrasound combiner, this OR-PAM system achieves a high SNR and fast imaging speed. It takes only 2 seconds to acquire a volumetric image with a wide field of view (FOV) of 4 × 8 mm2 along the X and Y axes, respectively. The measured lateral and axial resolutions are 6.0 and 37.7 μm, respectively. Finally, as a demonstration of the system’s capability, we successfully imaged the microvasculature in a mouse ear in vivo. Our new method will contribute substantially to the popularization and commercialization of OR-PAM in various preclinical and clinical applications. PMID:27708379

  13. Ultra low power full adder topologies

    DEFF Research Database (Denmark)

    Moradi, Farshad; Wisland, Dag T.; Mahmoodi, Hamid

    In this paper several low power full adder topologies are presented. The main idea of these circuits is based on the sense energy recovery full adder (SERF) design and the GDI (gate diffusion input) technique. These subthreshold circuits are employed for ultra low power applications. While...

  14. Low Power Mass Spectrometer employing TOF Project

    Data.gov (United States)

    National Aeronautics and Space Administration — A low power Mass Spectrometer employing multiple time of flight circuits for parallel processing is possible with a new innovation in design of the Time of flight...

  15. Dual Mode Low Power Hall Thruster Project

    Data.gov (United States)

    National Aeronautics and Space Administration — Sample and return missions desire and missions like Saturn Observer require a low power Hall thruster that can operate at high thrust to power as well as high...

  16. Exercise efficiency of low power output cycling.

    Science.gov (United States)

    Reger, M; Peterman, J E; Kram, R; Byrnes, W C

    2013-12-01

    Exercise efficiency at low power outputs, energetically comparable to daily living activities, can be influenced by homeostatic perturbations (e.g., weight gain/loss). However, an appropriate efficiency calculation for low power outputs used in these studies has not been determined. Fifteen active subjects (seven females, eight males) performed 14, 5-min cycling trials: two types of seated rest (cranks vertical and horizontal), passive (motor-driven) cycling, no-chain cycling, no-load cycling, cycling at low (10, 20, 30, 40 W), and moderate (50, 60, 80, 100, 120 W) power outputs. Mean delta efficiency was 57% for low power outputs compared to 41.3% for moderate power outputs. Means for gross (3.6%) and net (5.7%) efficiencies were low at the lowest power output. At low power outputs, delta and work efficiency values exceeded theoretical values. In conclusion, at low power outputs, none of the common exercise efficiency calculations gave values comparable to theoretical muscle efficiency. However, gross efficiency and the slope and intercept of the metabolic power vs mechanical power output regression provide insights that are still valuable when studying homeostatic perturbations.

  17. Low-power VLSI circuits and systems

    CERN Document Server

    Pal, Ajit

    2015-01-01

    The book provides a comprehensive coverage of different aspects of low power circuit synthesis at various levels of design hierarchy; starting from the layout level to the system level. For a seamless understanding of the subject, basics of MOS circuits has been introduced at transistor, gate and circuit level; followed by various low-power design methodologies, such as supply voltage scaling, switched capacitance minimization techniques and leakage power minimization approaches. The content of this book will prove useful to students, researchers, as well as practicing engineers.

  18. Low power implementation of datapath using regularity

    Institute of Scientific and Technical Information of China (English)

    LAI Li-ya; LIU Peng

    2005-01-01

    Datapath accounts for a considerable part of power consumption in VLSI circuit design. This paper presents a method for physical implementation of datapath to achieve low power consumption. Regularity is a characteristic of datapath and the key of the proposed method, where synthesis is tightly combined with placement to make full use of regularity, so that low power consumption is achieved. In This paper, a new concept of Synthesis In Relative Placement (SIRP) is given to deal with the semi-regularity in some datapath. Experimental results of a sample circuit validated the proposed method.

  19. Sensors and low power signal processing

    CERN Document Server

    Islam, Syed Kamrul

    2010-01-01

    Offers a general overview of a sensor's working principle and a discussion of various sensor technologies including chemical, electro-chemical and MEMS based sensors. This book includes a discussion on design challenges associated with low-power analog circuits and the schemes to overcome them.

  20. Low-Power Public Key Cryptography

    Energy Technology Data Exchange (ETDEWEB)

    BEAVER,CHERYL L.; DRAELOS,TIMOTHY J.; HAMILTON,VICTORIA A.; SCHROEPPEL,RICHARD C.; GONZALES,RITA A.; MILLER,RUSSELL D.; THOMAS,EDWARD V.

    2000-11-01

    This report presents research on public key, digital signature algorithms for cryptographic authentication in low-powered, low-computation environments. We assessed algorithms for suitability based on their signature size, and computation and storage requirements. We evaluated a variety of general purpose and special purpose computing platforms to address issues such as memory, voltage requirements, and special functionality for low-powered applications. In addition, we examined custom design platforms. We found that a custom design offers the most flexibility and can be optimized for specific algorithms. Furthermore, the entire platform can exist on a single Application Specific Integrated Circuit (ASIC) or can be integrated with commercially available components to produce the desired computing platform.

  1. Piezoelectric devices for generating low power

    Science.gov (United States)

    Chilibon, Irinela

    2016-12-01

    This paper reviews concepts and applications in low-power electronics and energy harvesting technologies. Various piezoelectric materials and devices for small power generators useful in renewable electricity are presented. The vibrating piezoelectric device differs from the typical electrical power source in that it has capacitive rather than inductive source impedance, and may be driven by mechanical vibrations of varying amplitude. In general, vibration energy could be converted into electrical energy using one of three techniques: electrostatic charge, magnetic fields and piezoelectric. A low power piezoelectric generator, having a PZT element was realised in order to supply small electronic elements, such as optoelectronic small devices, LEDs, electronic watches, small sensors, interferometry with lasers or Micro-electro-mechanical System (MEMS) array with multi-cantilevers.

  2. Designing Low Power Circuits: A Review

    Directory of Open Access Journals (Sweden)

    Rohan M Joshi

    2012-09-01

    Full Text Available The growing market of battery-operated portable applications like laptop, mobile etc requires microelectronic devices with low power consumption. As transistor size continues to shrink and as need for more complex chips increases, power management of the chip is one of the key challenges in VLSI industry. The manufacturers are looking for low power designs because providing adequate cooling and packaging increases the cost and limits the functionality of the device. This paper surveys the optimization techniques used to reduce power consumption in CMOS at all the levels of the design flow. It includes the technology used to implement digital circuits, the circuit design style and topology, the architecture for implementing the circuits, and at the highest level the software and algorithms that are implemented.

  3. Ultra-Low Power Transmitter Test Results

    Science.gov (United States)

    2014-12-01

    fabricate, and test an ultra-low-power transmitter and integrate it with a non-contact electroencephalogram ( EEG )/electrocardiogram (ECG) device...the current transmitter to investigate ways to remove design flaws and improve the design performance. The crystal oscillator had issues with its...it more robust. The chip will need to be re-designed and fabricated again to fix issues uncovered by testing. If the second revision of the chip is

  4. Low Power Band to Band Tunnel Transistors

    Science.gov (United States)

    2010-12-15

    the E-field and tunneling at the source- pocket junction you form a parasitic NPN + transistor and the injection mechanism of carriers into the...hypothesis that the 1000 ° C, 5s anneal split lead to a very wide pocket and the accidental formation of a NPN + transistor , while the 1000 ° C, 1s anneal...Low Power Band to Band Tunnel Transistors Anupama Bowonder Electrical Engineering and Computer Sciences University of California at Berkeley

  5. Testing Selective Transmission with Low Power Listening

    DEFF Research Database (Denmark)

    Hansen, Morten Tranberg; Arroyo-Valles, Rocio; Cid-Sueiro, Jesus

    2010-01-01

    Selective transmission policies allow nodes in a sensor network to autonomously decide between transmitting or discarding packets depending on the importance of the information content and the energetic cost of communications. The potential benefits of these policies depend on the capability...... of nodes to estimate its current energy consumption patterns. As a case study, this paper tests the performance of a particular selective transmission algorithm over a simple network using a low power listening MAC protocol on real sensor node hardware....

  6. Simultaneous Unbalanced Shared Local Oscillator Heterodyne Interferometry (SUSHI) for high SNR, minimally destructive dispersive detection of time-dependent atomic spins

    CERN Document Server

    Locke, Mary

    2013-01-01

    We demonstrate "Simultaneous Unbalanced Shared Local Oscillator Heterodyne Interferometry (SUSHI)," a new method for minimally destructive, high SNR dispersive detection of atomic spins. In SUSHI a dual-frequency probe laser interacts with atoms in one arm of a Mach-Zehnder interferometer, then beats against a bright local oscillator beam traversing the other arm, resulting in two simultaneous, independent heterodyne measurements of the atom-induced phase shift. Measurement noise due to mechanical disturbances of beam paths is strongly rejected by the technique of \\emph{active subtraction} in which anti-noise is actively written onto the local oscillator beam via an optical phase-locked-loop. In SUSHI, technical noise due to phase, amplitude, and frequency fluctuations of the various laser fields is strongly rejected (i) for any mean phase bias between the interferometer arms, (ii) without the use of piezo actuated mirrors, and (iii) without signal balancing. We experimentally demonstrate an ultra-low technic...

  7. Integrated low power digital gyro control electronics

    Science.gov (United States)

    M'Closkey, Robert (Inventor); Challoner, A. Dorian (Inventor); Grayver, Eugene (Inventor); Hayworth, Ken J. (Inventor)

    2005-01-01

    Embodiments of the invention generally encompass a digital, application specific integrated circuit (ASIC) has been designed to perform excitation of a selected mode within a vibratory rate gyroscope, damping, or force-rebalance, of other modes within the sensor, and signal demodulation of the in-phase and quadrature components of the signal containing the angular rate information. The ASIC filters dedicated to each channel may be individually programmed to accommodate different rate sensor designs/technology or variations within the same class of sensors. The ASIC architecture employs a low-power design, making the ASIC, particularly suitable for use in power-sensitive applications.

  8. Versatile experimental low power 4 K cryocooler

    Science.gov (United States)

    Lambert, N.; Barbanera, S.; Zimmerman, J. E.

    The construction of a low power cryocooler consisting of a five-stage plastic Stirling cooler with an additional Joule-Thomson stage is described. Among its novel features are a contamination-free, pneumatic helium compressor and displacer drive. Valve timing is under computer control. Titanium foil embedded in the cylinder wall reduces helium diffusion through the plastic. The Joule-Thomson stage uses the same low pressure helium as the Stirling stages. The Stirling system cools down below 9 K. The Joule-Thomson stage delivers a few mW cooling at 4.2 K.

  9. An Approach for Low Power CMOS Design

    Directory of Open Access Journals (Sweden)

    Ravindra kumar chejara

    2015-03-01

    Full Text Available Power dissipation has emerged an important parameter in design of Low Power CMOS circuits. For this level converter and dual supply voltage assignments are used to reduce the power dissipation and propagation delay. In this paper, variable supply-voltage scheme (dual-VS scheme for dual power supplies along with voltage level converter is presented. Also paper presents an overall comparative analysis among various methods to achieve voltage level shifter even in lower technology comparative to higher ones and help user to select the best methods for same at this technology.

  10. Low-power variable frequency PFC converters

    Energy Technology Data Exchange (ETDEWEB)

    Li Yani; Yang Yintang; Zhu Zhangming, E-mail: yanili@mail.xidian.edu.c [Key Laboratory of Wide Band-Gap Semiconductor Materials and Devices of the Ministry of Education, Institute of Microelectronics, Xidian University, Xi' an 710071 (China)

    2010-01-15

    Based on the SinoMOS 1 {mu}m 40 V CMOS process, a novel power factor contention (PFC) converter with a low-power variable frequency function is presented. The circuit introduces a multi-vector error amplifier and a programmable oscillator to achieve frequency modulation, which provides a rapid dynamic response and precise output voltage clamping with low power in the entire load. According to the external load variation, the system can modulate the circuit operating frequency linearly, thereby ensuring that the PFC converter can work in frequency conversion-mode. Measured results show that the normal operating frequency of the PFC converter is 5-6 kHz, the start-up current is 36 {mu}A, the stable operating current is only 2.43 mA, the efficiency is 97.3%, the power factor (PF) is 0.988, THD is 3.8%, the load adjust rate is 3%, and the linear adjust rate is less than 1%. Both theoretical and practical results reveal that the power consumption of the whole supply system is reduced efficiently, especially when the load varies. The active die area of the PFC converter chip is 1.61 x 1.52 mm{sup 2}. (semiconductor integrated circuits)

  11. Low-Power Wearable Respiratory Sound Sensing

    Directory of Open Access Journals (Sweden)

    Dinko Oletic

    2014-04-01

    Full Text Available Building upon the findings from the field of automated recognition of respiratory sound patterns, we propose a wearable wireless sensor implementing on-board respiratory sound acquisition and classification, to enable continuous monitoring of symptoms, such as asthmatic wheezing. Low-power consumption of such a sensor is required in order to achieve long autonomy. Considering that the power consumption of its radio is kept minimal if transmitting only upon (rare occurrences of wheezing, we focus on optimizing the power consumption of the digital signal processor (DSP. Based on a comprehensive review of asthmatic wheeze detection algorithms, we analyze the computational complexity of common features drawn from short-time Fourier transform (STFT and decision tree classification. Four algorithms were implemented on a low-power TMS320C5505 DSP. Their classification accuracies were evaluated on a dataset of prerecorded respiratory sounds in two operating scenarios of different detection fidelities. The execution times of all algorithms were measured. The best classification accuracy of over 92%, while occupying only 2.6% of the DSP’s processing time, is obtained for the algorithm featuring the time-frequency tracking of shapes of crests originating from wheezing, with spectral features modeled using energy.

  12. Low-Power Wireless Sensor Network Infrastructures

    DEFF Research Database (Denmark)

    Hansen, Morten Tranberg

    Advancements in wireless communication and electronics improving form factor and hardware capabilities has expanded the applicability of wireless sensor networks. Despite these advancements, devices are still limited in terms of energy which creates the need for duty-cycling and low-power protocols...... in order to achieve the wanted lifetimes. Through more than a decade of wireless sensor network research, progress towards realizing wanted lifetimes have been made and wireless standards for packet formatting and routing have been proposed. With standards in place, the wide-span between programming...... environments and communication primitives in wireless sensor network and traditional network development are closing. However, fundamental differences in wireless technology and energy constraints are still to be considered at the lower levels of the software stack. To fulfill energy requirements hardware...

  13. Power electronics for low power arcjets

    Science.gov (United States)

    Hamley, John A.; Hill, Gerald M.

    1991-01-01

    In anticipation of the needs of future light-weight low-power spacecraft, arcjet power electronics in the 100- to 400-W operating range were developed. Power topologies similar to those in the higher 2-kW and 5- to 30-kW power range were implemented, including a four-transistor bridge-switching circuit, current-mode pulse-width modulated control, and an output current averaging inductor with an integral pulse generation winding. Reduction of switching transients was accomplished using a low inductance power distribution network, and no passive snubber circuits were necessary for power switch protection. Phase shift control of the power bridge was accomplished using an improved pulse width modulation to phase shift converter circuit. These features, along with conservative magnetics designs, allowed power conversion efficiencies of greater than 92.5 percent to be achieved into resistive loads over the entire operating range of the converter.

  14. Faster and Low Power Twin Precision Multiplier

    CERN Document Server

    Sreedeep, V; Kittur, Harish M

    2011-01-01

    In this work faster unsigned multiplication has been achieved by using a combination of High Performance Multiplication [HPM] column reduction technique and implementing a N-bit multiplier using 4 N/2-bit multipliers (recursive multiplication) and acceleration of the final addition using a hybrid adder. Low power has been achieved by using clock gating technique. Based on the proposed technique 16 and 32-bit multipliers are developed. The performance of the proposed multiplier is analyzed by evaluating the delay, area and power, with TCBNPHP 90 nm process technology on interconnect and layout using Cadence NC launch, RTL compiler and ENCOUNTER tools. The results show that the 32-bit proposed multiplier is as much as 22% faster, occupies only 3% more area and consumes 30% lesser power with respect to the recently reported twin precision multiplier.

  15. Low Power Complex Multiplier based FFT Processor

    Directory of Open Access Journals (Sweden)

    V.Sarada

    2015-08-01

    Full Text Available High speed processing of signals has led to the requirement of very high speed conversion of signals from time domain to frequency domain. Recent years there has been increasing demand for low power designs in the field of Digital signal processing. Power consumption is the most important aspect while considering the system performance. In order to design high performance Fast Fourier Transform (FFT and realization, efficient internal structure is required. In this paper we present FFT Single Path Delay feedback (SDF pipeline architecture using radix -24 algorithm .The complex multiplier is realized by using Digit Slicing Concept multiplier less architecture. To reduce computation complexity radix 24 algorithms is used. The proposed design has been coded in Verilog HDL and synthesizes by Cadence tool. The result demonstrates that the power is reduced compared with complex multiplication used CSD (Canonic Signed Digit multiplier.

  16. Low power adder based auditory filter architecture.

    Science.gov (United States)

    Rahiman, P F Khaleelur; Jayanthi, V S

    2014-01-01

    Cochlea devices are powered up with the help of batteries and they should possess long working life to avoid replacing of devices at regular interval of years. Hence the devices with low power consumptions are required. In cochlea devices there are numerous filters, each responsible for frequency variant signals, which helps in identifying speech signals of different audible range. In this paper, multiplierless lookup table (LUT) based auditory filter is implemented. Power aware adder architectures are utilized to add the output samples of the LUT, available at every clock cycle. The design is developed and modeled using Verilog HDL, simulated using Mentor Graphics Model-Sim Simulator, and synthesized using Synopsys Design Compiler tool. The design was mapped to TSMC 65 nm technological node. The standard ASIC design methodology has been adapted to carry out the power analysis. The proposed FIR filter architecture has reduced the leakage power by 15% and increased its performance by 2.76%.

  17. Low Power Switching for Antenna Reconfiguration

    Science.gov (United States)

    Bauhahn, Paul E. (Inventor); Becker, Robert C. (Inventor); Meyers, David W. (Inventor); Muldoon, Kelly P. (Inventor)

    2008-01-01

    Methods and systems for low power switching are provided. In one embodiment, an optical switching system is provided. The system comprises at least one optically controlled switch adapted to maintain one of an open state and a closed state based on an associated light signal; and at least one light source adapted to output the associated light signal to the at least one switch, wherein the at least one light source cycles the light signal on and off, wherein the at least one light source is cycled on for a sufficient duration of time and with a sufficient periodicity to maintain the optically controlled switch in one of an open state and a closed state.

  18. Radiation Tolerant Low Power Precision Time Source Project

    Data.gov (United States)

    National Aeronautics and Space Administration — The availability of small, low power atomic clocks is now a reality for ground-based and airborne navigation systems. Kernco's Low Power Precision Time Source...

  19. Energy neutral and low power wireless communications

    Science.gov (United States)

    Orhan, Oner

    Wireless sensor nodes are typically designed to have low cost and small size. These design objectives impose restrictions on the capacity and efficiency of the transceiver components and energy storage units that can be used. As a result, energy becomes a bottleneck and continuous operation of the sensor network requires frequent battery replacements, increasing the maintenance cost. Energy harvesting and energy efficient transceiver architectures are able to overcome these challenges by collecting energy from the environment and utilizing the energy in an intelligent manner. However, due to the nature of the ambient energy sources, the amount of useful energy that can be harvested is limited and unreliable. Consequently, optimal management of the harvested energy and design of low power transceivers pose new challenges for wireless network design and operation. The first part of this dissertation is on energy neutral wireless networking, where optimal transmission schemes under different system setups and objectives are investigated. First, throughput maximization for energy harvesting two-hop networks with decode-and-forward half-duplex relays is studied. For a system with two parallel relays, various combinations of the following four transmission modes are considered: Broadcast from the source, multi-access from the relays, and successive relaying phases I and II. Next, the energy cost of the processing circuitry as well as the transmission energy are taken into account for communication over a broadband fading channel powered by an energy harvesting transmitter. Under this setup, throughput maximization, energy maximization, and transmission completion time minimization problems are studied. Finally, source and channel coding for an energy-limited wireless sensor node is investigated under various energy constraints including energy harvesting, processing and sampling costs. For each objective, optimal transmission policies are formulated as the solutions of a

  20. Low Power CMOS Digitally Controlled Oscillator

    Directory of Open Access Journals (Sweden)

    Sujata Pandey,

    2010-08-01

    Full Text Available Here, two new designs of CMOS digitally controlled oscillators (DCO for low power application have been proposed. First design has been implemented with one driving strength controlled delay cell and withtwo NAND gates used as inverters. The second design with one delay cell and by two NOR gates is presented. The proposed circuits have been simulated in spice with 0.35 μm (micrometer technology at supply voltage of 3.3V. The first design shows 35-40% reduction in power consumption and second design shows 37.5-41.8% power saving as compared to conventional DCO. The frequency range of first and second design varies [3.1316 - 3.1085] GHz and [3.8112 – 3.7867] GHz respectively with the variation in control word from ‘000000’ to ‘000001'. Power consumption of first and second design varies [640.3845 - 700.2977] μW and [617.6616 -6 77.3996] μW respectively.

  1. Design of Low Power Sigma Delta ADC

    Directory of Open Access Journals (Sweden)

    Mohammed Arifuddin Sohel

    2012-08-01

    Full Text Available A Low power discrete time sigma delta ADC consisting of a second order sigma delta modulator and third order Cascaded Integrated Comb (CIC filter is proposed. The second order modulator is designed to work at a signal band of 20 K Hz at an oversampling ratio of 64 with a sampling frequency of 2.56 MHz. It achieves a signal to noise ratio of 85.2dB and a resolution of 14 bits. The CIC digital filter is designed to implement a decimation factor of 64, operating at a maximum sampling frequency of 2.56 MHz. A second order sigma delta modulator is implemented in 0.18 micron CMOS technology using full custom design and the third order digital CIC decimation filter is implemented in verilog HDL. The complete Sigma Delta ADC, consisting of analog block of second order modulator and digital block of decimator consumes a total power 1.96mW.

  2. Design of Low Power Sigma Delta ADC

    Directory of Open Access Journals (Sweden)

    Mohammed Arifuddin Sohel

    2012-09-01

    Full Text Available A Low power discrete time sigma delta ADC consisting of a second order sigma delta modulator and third order Cascaded Integrated Comb (CIC filter is proposed. The second order modulator is designed to work at a signal band of 20K Hz at an oversampling ratio of 64 with a sampling frequency of 2.56 MHz. It achieves a signal to noise ratio of 85.2dB and a resolution of 14 bits. The CIC digital filter is designed to implement a decimation factor of 64, operating at a maximum sampling frequency of 2.56 MHz. A second order sigma delta modulator is implemented in 0.18micron CMOS technology using full custom design and the third order digital CIC decimation filter is implemented in verilog HDL. The complete Sigma Delta ADC, consisting of analog block of second order modulator and digital block of decimator consumes a total power 1.96mW.

  3. Design and Analysis of Sequential Elements for Low Power Clocking System with Low Power Techniques

    Directory of Open Access Journals (Sweden)

    S.Sasidhar Reddy

    2014-09-01

    Full Text Available This paper proposed the design of sequential elements for low power clocking system with low low power techniques for saving the power. Power consumption is a major bottleneck of system performance and is listed as one of the top three challenges in International Technology Roadmap for Semiconductor 2008. In practice, a large portion of the on chip power is consumed by the clock system which is made of the clock distribution network and flop-flops. In this paper, various design techniques for a low power clocking system are surveyed. Among them is an effective way to reduce capacity of the clock load by minimizing number of clocked transistors. To approach this, proposed a novel clocked pair shared flip-flop which reduces the number of local clocked transistors by approximately 40%. A 24% reduction of clock driving power is achieved. In addition, low swing and double edge clocking, can be easily incorporated into the new flip-flop to build clocking systems. As the feature size becomes smaller, shorter channel lengths result in increased sub-threshold leakage current through a transistor when it is off. Dual sleep and sleepy stack methods are proposed to avoid static power consumption; the flip flops are simulated using HSPICE.

  4. Low power-consumption quantum cascade lasers

    Science.gov (United States)

    Katsuyama, Tsukuru; Hashimoto, Jun-ichi; Yoshinaga, Hiroyuki; Mori, Hiroki; Tsuji, Yukihiro; Murata, Makoto; Ekawa, Mitsuru; Tanahashi, Toshiyuki

    2015-01-01

    Quantum cascade lasers (QCLs) are promising light sources for real time high-sensitivity gas sensing in the mid-infrared region. For the practical use of QCLs as a compact and portable gas sensor, their power-consumption needs to be reduced. We report a successful operation of a low power-consumption distributed feedback (DFB) QCL. For the reduction of power consumption, we introduced a vertical-transition structure in a core region to improve carrier transition efficiency and reduced the core volume. DFB-QCL epitaxial structure was grown by low-pressure OMVPE. The core region consists of AlInAs/GaInAs superlattices lattice-matched to InP. A first-order Bragg-grating was formed near the core region to obtain a large coupling coefficiency. A mesa-strip was formed by reactive ion etching and a buried-heterostructure was fabricated by the regrowth of semi-insulating InP. High-reflective facet coatings were also performed to decrease the mirror loss for the reduction of the threshold current. A device (5x500μm) operated with a single mode in the wavelength region from 7.23μm to 7.27μm. The threshold current and threshold voltage under CW operation at 20 °C were 52mA and 8.4V respectively. A very low threshold power-consumption as low as 0.44 W was achieved, which is among the lowest values at room temperature to our knowledge.

  5. Hacking and penetration testing with low power devices

    CERN Document Server

    Polstra, Philip

    2014-01-01

    Hacking and Penetration Testing with Low Power Devices shows you how to perform penetration tests using small, low-powered devices that are easily hidden and may be battery-powered. It shows how to use an army of devices, costing less than you might spend on a laptop, from distances of a mile or more. Hacking and Penetration Testing with Low Power Devices shows how to use devices running a version of The Deck, a full-featured penetration testing and forensics Linux distribution, and can run for days or weeks on batteries due to their low power consumption. Author Philip Polstra shows how to

  6. Low power wireless EEG headset for BCI applications

    NARCIS (Netherlands)

    Patki, S.; Grundlehner, B.; Nakada, T.; Penders, J.

    2011-01-01

    Miniaturized, low power and low noise circuits and systems are instrumental in bringing EEG monitoring to the home environment. In this paper, we present a miniaturized, low noise and low-power EEG wireless platform integrated into a wearable headset. The wireless EEG headset achieves remote and wea

  7. Low Power/Low Voltage Interface Circuitry for Capacitive Sensors

    DEFF Research Database (Denmark)

    Furst, Claus Efdmann

    This thesis focuses mainly on low power/low voltage interface circuits, implemented in CMOS, for capacitive sensors. A brief discussion of demands and possibilities for analog signal processing in the future is presented. Techniques for low power design is presented. This is done by analyzing power...... consumption of different amplifier topologies. Next, low power features of different amplifier types are analyzed on transistor level. A brief comparison of SI circuits for low power applications vs. SC circuits is presented. Methodologies for low voltage design is presented. This is followed by a collection...... power consumption. It is shown that the Sigma-Delta modulator is advantageous when embedded in a feedback loop with a mechanical sensor. Here a micro mechanical capacitive microphone. Feedback and detection circuitry for a capacitive microphone is presented. Practical implementations of low power...

  8. Compact Low-Power Driver for Deformable Mirror Systems Project

    Data.gov (United States)

    National Aeronautics and Space Administration — This proposal describes a new concept to drive MEMS DMs using low-power, high-voltage multiplexing. Compared to other reported approaches, the proposed architecture...

  9. Ultra-Low-Power MEMS Selective Gas Sensors Project

    Data.gov (United States)

    National Aeronautics and Space Administration — KWJ offers this proposal for a very low power but very practical "nano-watt" MEMS sensor platform for NASA requirements. The proposed nano-sensor platform is ultra...

  10. Design of ultra-low power impulse radios

    CERN Document Server

    Apsel, Alyssa; Dokania, Rajeev

    2014-01-01

    This book covers the fundamental principles behind the design of ultra-low power radios and how they can form networks to facilitate a variety of applications within healthcare and environmental monitoring, since they may operate for years off a small battery or even harvest energy from the environment. These radios are distinct from conventional radios in that they must operate with very constrained resources and low overhead.  This book provides a thorough discussion of the challenges associated with designing radios with such constrained resources, as well as fundamental design concepts and practical approaches to implementing working designs.  Coverage includes integrated circuit design, timing and control considerations, fundamental theory behind low power and time domain operation, and network/communication protocol considerations.   • Enables detailed understanding of the design space for ultra-low power radio; • Provides detailed discussion and examples of the design of a practical low power ...

  11. Compact Low-Power Driver for Deformable Mirror Systems Project

    Data.gov (United States)

    National Aeronautics and Space Administration — Boston Micromachines Corporation (BMC), a leading developer of unique, high-resolution micromachined deformable mirrors (DMs), will develop a compact, low-power,...

  12. Wireless powering for low-power distributed sensors

    Directory of Open Access Journals (Sweden)

    Popović Zoya B.

    2006-01-01

    Full Text Available In this paper, an overview of the field of wireless powering is presented with an emphasis on low-power applications. Several rectenna elements and arrays are discussed in more detail: (1 a 10-GHz array for powering sensors in aircraft wings; (2 a single antenna in the 2.4-GHz ISM band for low-power assisted-living sensors; and (3 a broadband array for power harvesting in the 2-18GHz frequency range.

  13. Ultra-Low-Power MEMS Selective Gas Sensors

    Science.gov (United States)

    Stetter, Joseph

    2012-01-01

    This innovation is a system for gas sensing that includes an ultra-low-power MEMS (microelectromechanical system) gas sensor, combined with unique electronic circuitry and a proprietary algorithm for operating the sensor. The electronics were created from scratch, and represent a novel design capable of low-power operation of the proprietary MEMS gas sensor platform. The algorithm is used to identify a specific target gas in a gas mixture, making the sensor selective to that target gas.

  14. A Comparative Performance Analysis of Low Power Bypassing Array Multipliers

    Directory of Open Access Journals (Sweden)

    Nirlakalla Ravi

    2013-07-01

    Full Text Available Low power design of VLSI circuits has been identified as vital technology in battery powered portable electronic devices and signal processing applications such as Digital Signal Processors (DSP. Multiplier has an important role in the DSPs. Without degrading the performance of the processor, low power parallel multipliers are needed to be design. Bypassing is the widely used technique in the DSPs when the input operand of the multiplier is zero. A Row based Bypassing Multiplier with compressor at the final addition of the ripple carry adder (RCA is designed to focus on low power and high speed. The proposed bypassing multiplier with compressor shows high performance and energy efficiency than Kuo multiplier with Carry Save Adder (CSA at the final RCA.

  15. High-Speed Low Power Design in CMOS

    DEFF Research Database (Denmark)

    Ghani, Arfan; Usmani, S. H.; Stassen, Flemming

    2004-01-01

    Static CMOS design displays benefits such as low power consumption, dominated by dynamic power consumption. In contrast, MOS Current Mode Logic (MCML) displays static rather than dynamic power consumption. High-speed low-power design is one of the many application areas in VLSI that require...... the appropriate domains of performance and power requirements in which MCML presents benefits over standard CMOS. An optimized cell library is designed and implemented in both CMOS and MCML in order to make a comparison with reference to speed and power. Much more time is spent in order to nderstand...

  16. Task scheduling for high performance low power embedded computing

    Science.gov (United States)

    Deniziak, Stanislaw; Dzitkowski, Albert

    2016-12-01

    In this paper we present a method of task scheduling for low-power real-time embedded systems. We assume that the system is specified as a task graph, then it is implemented using multi-core embedded processor with low-power processing capabilities. We propose a new scheduling method to create the optimal schedule. The goal of optimization is to minimize the power consumption while all time constraints will be satisfied. We present experimental results, obtained for some standard benchmarks, showing advantages of our method.

  17. Comparison of Preamplifiers for Low-power Consumption Design

    Energy Technology Data Exchange (ETDEWEB)

    Lee, Seung Hyun; Kim, Han Soo; Lee, Kyu Hong; Choi, Hyo Jeong; Na, Teresa W.; Ha, Jang Ho [Korea Atomic Energy Research Institute, Daejeon (Korea, Republic of); Chai, Jong Seo [Sungkyunkwan University, Suwon (Korea, Republic of)

    2011-10-15

    The commonly used electronic devices in radiation detector system are the preamplifier, the amplifier, ADC, and etc. to extract the signal from the detector and to process the signal. These components are composed of semiconductor devices like BJT, MOSFET, OPAMP, and etc. Performance and power consumption of these components are various according to the composition of semiconductor devices. In this study, preamplifiers, which are composed of high efficiency semiconductor devices, are compared to design low-power consumption and high performance preamplifier. To confirm the purpose, preamplifiers are designed for low-power consumption and high gain by some OPAMP (Operational Amplifier). The comparison was performed by experimental result and design simulation

  18. Low Power Systolic Array Based Digital Filter for DSP Applications

    Directory of Open Access Journals (Sweden)

    S. Karthick

    2015-01-01

    Full Text Available Main concepts in DSP include filtering, averaging, modulating, and correlating the signals in digital form to estimate characteristic parameter of a signal into a desirable form. This paper presents a brief concept of low power datapath impact for Digital Signal Processing (DSP based biomedical application. Systolic array based digital filter used in signal processing of electrocardiogram analysis is presented with datapath architectural innovations in low power consumption perspective. Implementation was done with ASIC design methodology using TSMC 65 nm technological library node. The proposed systolic array filter has reduced leakage power up to 8.5% than the existing filter architectures.

  19. Novel Low Power Comparator Design using Reversible Logic Gates

    Directory of Open Access Journals (Sweden)

    Nagamani A N

    2011-09-01

    Full Text Available Reversible logic has received great attention in the recent years due to its ability to reduce the power dissipation which is the main requirement in low power digital design. It has wide applications inadvanced computing, low power CMOS design, Optical information processing, DNA computing, bio information, quantum computation and nanotechnology. This paper presents a novel design of reversiblecomparator using the existing reversible gates and proposed new Reversible BJN gate. All the comparators have been modeled and verified using VHDL and ModelSim. A comparative result is presented in terms of number of gates, number of garbage outputs, number of constant inputs and Quantum cost.

  20. Low Power Systolic Array Based Digital Filter for DSP Applications.

    Science.gov (United States)

    Karthick, S; Valarmathy, S; Prabhu, E

    2015-01-01

    Main concepts in DSP include filtering, averaging, modulating, and correlating the signals in digital form to estimate characteristic parameter of a signal into a desirable form. This paper presents a brief concept of low power datapath impact for Digital Signal Processing (DSP) based biomedical application. Systolic array based digital filter used in signal processing of electrocardiogram analysis is presented with datapath architectural innovations in low power consumption perspective. Implementation was done with ASIC design methodology using TSMC 65 nm technological library node. The proposed systolic array filter has reduced leakage power up to 8.5% than the existing filter architectures.

  1. Low-power wearable sensing for preventive healthcare

    NARCIS (Netherlands)

    Penders, Julien; Altini, Marco; Wijsman, Jacqueline; Vullers, Rudolf; Van Hoof, C.

    2013-01-01

    Low-power wearable sensing will soon allow the quantitative and continuous measurement of health parameters. In this paper we illustrate how wearable sensors can be used to track activity and energy expenditure, and measure stress. Soon such information may empower people in managing their own healt

  2. CMOS Ultra Low Power Radiation Tolerant (CULPRiT) Microelectronics

    Science.gov (United States)

    Yeh, Penshu; Maki, Gary

    2007-01-01

    Space Electronics needs Radiation Tolerance or hardness to withstand the harsh space environment: high-energy particles can change the state of the electronics or puncture transistors making them disfunctional. This viewgraph document reviews the use of CMOS Ultra Low Power Radiation Tolerant circuits for NASA's electronic requirements.

  3. Ultra low power transceiver for wireless body area networks

    CERN Document Server

    Masuch, Jens

    2013-01-01

    This book describes the design of ultra low power transceivers for body area networks.  Since these applications have very limited energy resources, typically powered only by tiny batteries or through energy harvesting techniques, this book describes an architecture for a Bluetooth low energy transceiver to overcome these limitations. Coverage includes not only the main concepts for achieving low power consumption, but also the details of the circuit design and its implementation in a standard CMOS technology.     ·         Guides readers through the design of ultra low power transceivers for body area networks, from architecture to circuit-level implementation; ·         Describes 4 key strategies for ultra-low power transceiver design and specific, innovative techniques for circuit-level design; ·         Enables readers to design transceivers for body area networks that are 27% more energy efficient than those currently available; ·         Includes a review of the st...

  4. Low power DCVSL circuits employing AC power supply

    Institute of Scientific and Technical Information of China (English)

    2002-01-01

    In view of changing the type of energy conversion in CMOS circuits, this paper investigates low power CMOS circuit design, which adopts a gradually changing power clock. First, we discuss the algebraic expressions and the corresponding properties of clocked power signals. Then the design procedure is summed up for converting complementary CMOS logic gates employing DC power to the power-clocked CMOS gates employing AC power. On this basis, the design of differential cascode voltage switch logic (DCVSL) circuits employing AC power clocks is proposed. The PSPICE simulations using a sinusoidal power-clock demonstrate that the designed power-clocked DCVSL circuit has a correct logic function and low power characteristics. Finally, an interface circuit to convert clocked signals into the standard logic levels of a CMOS circuit is proposed, and its validity is verified by computer simulations.

  5. Numerical Analysis of Powder Properties in Low Power Plasma Torch

    Institute of Scientific and Technical Information of China (English)

    YAN Zhi-jun; GAO Yang; HEI Zhu-kun; AN Lian-tong

    2004-01-01

    A mathematical model was presented to describe the particle trajectory, velocity and temperature properties in the low power plasma spraying torch (3.6 kW)in which powder particles were directly injected into the region between the cathode and anode. The results show that the characteristics of the particles by low power plasma spraying are similar to that by traditional APS( Atmosphere plasma spraying) in 40 kW. The velocities of the particles increase with the increase of inlet gas flow rate, current and percentage of nitrogen and hydrogen, while the temperature of the powder increase with the decrease of the gas flow rate and with the increase of current and percentage of nitrogen and hydrogen.

  6. Low-power-laser therapy used in tendon damage

    Science.gov (United States)

    Strupinska, Ewa

    1996-03-01

    The following paper covers evaluation of low-power laser therapy results in chronic Achilles tendon damage and external Epicondylalia (tennis elbow). Fifty patients with Achilles damage (18 women and 32 men, age average 30, 24 plus or minus 10, 39 years) and fifty patients having external Epicondyalgiae (31 women and 19 men, age average 44, 36 plus or minus 10, 88 years) have been examined. The patients were irradiated by semiconductor infrared laser wavelength 904 nm separately or together with helium-neon laser wavelength 632.8 nm. The results of therapy have been based on the patient's interviews and examinations of patients as well as on the Laitinen pain questionnaire. The results prove analgesic effects in usage of low- power laser radiation therapy can be obtained.

  7. Design of Low Power Vedic Multiplier Based on Reversible Logic

    Directory of Open Access Journals (Sweden)

    Sagar

    2017-03-01

    Full Text Available Reversible logic is a new technique to reduce the power dissipation. There is no loss of information in reversible logic and produces unique output for specified inputs and vice-versa. There is no loss of bits so the power dissipation is reduced. In this paper new design for high speed, low power and area efficient 8-bit Vedic multiplier using Urdhva Tiryakbhyam Sutra (ancient methodology of Indian mathematics is introduced and implemented using Reversible logic to generate products with low power dissipation. UT Sutra generates partial product and sum in single step with less number of adders unit when compare to conventional booth and array multipliers which will reduce the delay and area utilized, Reversible logic will reduce the power dissipation. An 8-bit Vedic multiplier is realized using a 4-bit Vedic multiplier and modified ripple carry adders. The proposed logic blocks are implemented using Verilog HDL programming language, simulation using Xilinx ISE software.

  8. On the Development of Low Power MAC Protocol for WBANs

    CERN Document Server

    Ullah, Sana; Kwak, Kyung Sup

    2009-01-01

    Current advances in wireless communication, microelectronics, semiconductor technologies, and intelligent sensors have contributed to the development of unobtrusive WBANs. These networks provide long term health monitoring of patients without any constraint in their normal activities. Traditional MAC protocols do not accommodate the assorted WBAN traffic requirements in a power efficient manner. In this paper, we present a brief discussion on the development process of a low power MAC protocol for WBANs. We observe the behavior of a beacon-enabled IEEE 802.15.4 for on-body sensor networks. We further propose a low power technique called traffic based wakeup mechanism for a WBAN that exploits the traffic patterns of the BAN Nodes to ensure power efficient and reliable communication.

  9. Designing Asynchronous Circuits for Low Power: An IFIR Filter

    DEFF Research Database (Denmark)

    Nielsen, Lars Skovby; Sparsø, Jens

    1999-01-01

    by numerically small samples). Apart from the improved RAM design, these measures are only viable in an asynchronous design. The principles and techniques explained in this paper are of a general nature, and they apply to the design of asynchronous low-power digital signal-processing circuits in a broader......This paper addresses the design of asynchronous circuits for low power through an example: a filter bank for a digital hearing aid. The asynchronous design re-implements an existing synchronous circuit which is used in a commercial product. For comparison, both designs have been fabricated...... in the same 0.7 /spl mu/m CMOS technology. When processing typical data (less than 50 dB sound pressure), the asynchronous control and data-path logic, an improved RAM design, and by a mechanism that adapts the number range to the actual need (exploiting the fact that typical audio signals are characterized...

  10. Performance Analysis of Reconfigurable SRAM Cell for Low Power Applications

    Directory of Open Access Journals (Sweden)

    Dillibabu.Mannem

    2012-06-01

    Full Text Available The majority of space taken in an integrated circuit is the memory. SRAM design consists of key considerations, such as increased speed, low power and reduced layout area. A cell which is functional at the nominal supply voltage, can fail at a lower voltage. From a system perspective this leads to a higher bit-error rate with voltage scaling and limits the opportunity for power saving. While this is a serious bottleneck for SRAM arrays used for data storage. This paper presents a performance analysis of reconfigurable SRAM cell for low power application. Simulations using TSMC 0.35um technology show that the SRAM cell read & write access times are 1.53ns and 1.93ns. Mentor Graphics ELDO and EZ-wave are used for simulations.

  11. DESIGN OF MTCMOS LOGIC CIRCUITS FOR LOW POWER APPLICATIONS

    Directory of Open Access Journals (Sweden)

    V.LeelaRani

    2014-07-01

    Full Text Available Technology scaling leads to sub threshold leakages in deep sub micron regime. There is a need for effective leakage reduction techniques to minimize MOS leakage currents. Reduced leakage currents extend the life of all battery operated devices like cell phones, Laptops etc. This paper presents multi threshold CMOS circuit level technique to minimize leakages. MTCMOS technique is an effective solution for high-speed low-power applications. The proposed technique has been implemented in cadence virtuoso tool using standard cells of 90nm CMOS technology. For performance evaluation a full adder and 4x4 multipliers are considered as test circuits and applied with MTCMOS technique. Simulation results proved that MTCMOS technique is best in minimizing power compared with the conventional and dual threshold voltage techniques and can be used for low power applications.

  12. Low power RF circuit design in standard CMOS technology

    CERN Document Server

    Alvarado, Unai; Adín, Iñigo

    2012-01-01

    Low Power Consumption is one of the critical issues in the performance of small battery-powered handheld devices. Mobile terminals feature an ever increasing number of wireless communication alternatives including GPS, Bluetooth, GSM, 3G, WiFi or DVB-H. Considering that the total power available for each terminal is limited by the relatively slow increase in battery performance expected in the near future, the need for efficient circuits is now critical. This book presents the basic techniques available to design low power RF CMOS analogue circuits. It gives circuit designers a complete guide of alternatives to optimize power consumption and explains the application of these rules in the most common RF building blocks: LNA, mixers and PLLs. It is set out using practical examples and offers a unique perspective as it targets designers working within the standard CMOS process and all the limitations inherent in these technologies.

  13. Low-power attitude determination for magnetometry planetary missions

    DEFF Research Database (Denmark)

    Christensen, Thorbjørn Helvig

    This work covers the subject of orientation or attitude in space and on the surface of a planet. Different attitude sensor technologies have been investigated with emphasis on very low power consumption and mass. In addition robust methods for attitude determination have been covered again...... with emphasis on the limited budget onboard very small satellites. A true low-power attitude sensor using the Anisotropic Magneto Resistor effect have been designed to late prototype state. Two prototypes of the AMR magnetometer have been built. One of the prototypes has an analog output and the second...... calibration has been performed on both of the prototypes of the AMR magnetometer with very good overall result. Different attitude representations such as orthogonal matrices, Euler angles and quaternions are presented. Also methods for attitude determination of a sensor platform with more than one vector...

  14. Glitch Reduction in Low- Power Low- Frequency Multiplier

    Directory of Open Access Journals (Sweden)

    Bhethala Rajasekhar

    2014-01-01

    Full Text Available Multiplication is an essential arithmetic operation for common DSP applications, such as filtering and fast Fourier transform (FFT. To achieve high execution speed, parallel array multipliers are widely used. These multipliers tend to consume most of the power in DSP computations, and thus power-efficient multipliers are very important for the design of low-power DSP systems. A straightforward approach is to design a full adder (FA that consumes less power. Power reduction can also be achieved through structural modification. For example, rows of partial products can be ignored. In this project a 10 transistor full adder is designed for low power which is used in the implementation of different types of multipliers. All these multipliers are compared for different technologies. A power gating technique is used by placing an MTCMOS cell is used at fine grain level so as to minimize the leakage power.

  15. Low Power Shoe Integrated Intelligent Wireless Gait Measurement System

    Science.gov (United States)

    Wahab, Y.; Mazalan, M.; Bakar, N. A.; Anuar, A. F.; Zainol, M. Z.; Hamzah, F.

    2014-04-01

    Gait analysis measurement is a method to assess and identify gait events and the measurements of dynamic, motion and pressure parameters involving the lowest part of the body. This significant analysis is widely used in sports, rehabilitation as well as other health diagnostic towards improving the quality of life. This paper presents a new system empowered by Inertia Measurement Unit (IMU), ultrasonic sensors, piezoceramic sensors array, XBee wireless modules and Arduino processing unit. This research focuses on the design and development of a low power ultra-portable shoe integrated wireless intelligent gait measurement using MEMS and recent microelectronic devices for foot clearance, orientation, error correction, gait events and pressure measurement system. It is developed to be cheap, low power, wireless, real time and suitable for real life in-door and out-door environment.

  16. An approach to optimization of low-power Stirling cryocoolers

    Science.gov (United States)

    Sullivan, D. B.; Radebaugh, R.; Daney, D. E.; Zimmerman, J. E.

    1983-01-01

    A method for optimizing the design (shape of the displacer) of low power Stirling cryocoolers relative to the power required to operate the systems is described. A variational calculation which includes static conduction, shuttle and radiation losses, as well as regenerator inefficiency, was completed for coolers operating in the 300 K to 10 K range. While the calculations apply to tapered displacer machines, comparison of the results with stepped displacer cryocoolers indicates reasonable agreement.

  17. Analyzing the Low Power Wireless Links for Wireless Sensor Networks

    CERN Document Server

    Mamun, Md Mainul Islam; Kumar, Sumon; Islam, Md Zahidul

    2010-01-01

    There is now an increased understanding of the need for realistic link layer models in the wireless sensor networks. In this paper, we have used mathematical techniques from communication theory to model and analyze low power wireless links. Our work provides theoretical models for the link layer showing how Packet Reception Rate vary with Signal to Noise Ratio and distance for different modulation schemes and a comparison between MICA2 and TinyNode in terms of PRR.

  18. A Low-Power CoAP for Contiki

    OpenAIRE

    Kovatsch M.; Duquennoy S.; Dunkels A.

    2011-01-01

    Internet of Things devices will by and large be battery-operated, but existing application protocols have typically not been designed with power-efficiency in mind. In low-power wireless systems, power-efficiency is determined by the ability to maintain a low radio duty cycle: keeping the radio off as much as possible. We present an implementation of the IETF Constrained Application Protocol (CoAP) for the Contiki operating system that leverages the ContikiMAC low-powe...

  19. Radio link quality estimation in low-power wireless networks

    CERN Document Server

    2013-01-01

    This book provides a comprehensive survey on related work for radio link quality estimation, which covers the characteristics of low-power links, the fundamental concepts of link quality estimation in wireless sensor networks, a taxonomy of existing link quality estimators and their performance analysis. It then shows how link quality estimation can be used for designing protocols and mechanisms such as routing and hand-off. The final part is dedicated to radio interference estimation, generation and mitigation.

  20. Capacity of Fading Channels in the Low Power Regime

    KAUST Repository

    Benkhelifa, Fatma

    2013-01-01

    The low power regime has attracted various researchers in the information theory and communication communities to understand the performance limits of wireless systems. Indeed, the energy consumption is becoming one of the major limiting factors in wireless systems. As such, energy-efficient wireless systems are of major importance to the next generation wireless systems designers. The capacity is a metric that measures the performance limit of a wireless system. The study of the ergodic capacity of some fading channels in the low power regime is the main subject of this thesis. In our study, we consider that the receiver has always a full knowledge of the channel state information. However, we assume that the transmitter has possibly imperfect knowledge of the channel state information, i.e. he knows either perfectly the channel or only an estimated version of the channel. Both radio frequency and free space optical communication channel models are considered. The main contribution of this work is the explicit characterization of how the capacity scales as function of the signal-to-noise ratio in the low power regime. This allows us to characterize the gain due to the perfect knowledge compared to no knowledge of the channel state information at the transmitter. In particular, we show that the gain increases logarithmically for radio frequency communication. However, the gain increases as log2(Pavg) or log4(Pavg) for free-space optical communication, where Pavg is the average power constraint imposed to the input. Furthermore, we characterize the capacity of cascaded fading channels and we applied the result to Rayleigh-product fading channel and to a free-space optical link over gamma-gamma atmospheric turbulence in the presence of pointing errors. Finally, we study the capacity of Nakagami-m fading channel under quality of service constraints, namely the effective capacity. We have shown that the effective capacity converges to Shannon capacity in the very low

  1. Ultra-low power S-Boxes architecture for AES

    Institute of Scientific and Technical Information of China (English)

    XING Ji-peng; ZOU Xue-cheng; GUO Xu

    2008-01-01

    It is crucial to design energy-efficient advancedcncryption standard (AES) cryptography for low power embeddedsystems powered by limited battery. Since the S-Boxes consumemuch of the total AES circuit power, an efficient approach toreducing the AES power consumption consists in reducing theS-Boxes power consumption. Among various implementationsof S-Boxes, the most energy-efficient one is the decoder-switch-encoder (DSE) architecture. In this paper, we refine the DSEarchitecture and propose one faster, more compact S-Boxesarchitecture of lower power: an improved and full-balanced DSEarchitecture. This architecture achieves low power consumptionof 68 μW at 10 MHz using 0.25 μm 1.8V UMC CMOStechnology. Compared with the original DSE S-Boxes, it furtherreduces the delay, gate count and power consumption by 8%,14% and 10% respectively. At the sane time, simulation resultsshow that the improved DSE S-Boxes has the best performanceamong various S-Boxes architectures in terms of power-areaproduct and power-delay product, and it is optimal forimplementing low power AES cryptography.

  2. Next High Performance and Low Power Flash Memory Package Structure

    Institute of Scientific and Technical Information of China (English)

    Jung-Hoon Lee

    2007-01-01

    In general, SAND flash memory has advantages in low power consumption, storage capacity, and fast erase/write performance in contrast to NOR flash. But, main drawback of the SAND flash memory is the slow access time for random read operations. Therefore, we proposed the new SAND flash memory package for overcoming this major drawback. We present a high performance and low power SAND flash memory system with a dual cache memory. The proposed SAND flash package consists of two parts, i.e., an SAND flash memory module, and a dual cache module. The new SAND flash memory system can achieve dramatically higher performance and lower power consumption compared with any conventional NAND-type flash memory module. Our results show that the proposed system can reduce about 78% of write operations into the flash memory cell and about 70% of read operations from the flash memory cell by using only additional 3KB cache space. This value represents high potential to achieve low power consumption and high performance gain.

  3. Flash on disk for low-power multimedia computing

    Science.gov (United States)

    Singleton, Leo; Nathuji, Ripal; Schwan, Karsten

    2007-01-01

    Mobile multimedia computers require large amounts of data storage, yet must consume low power in order to prolong battery life. Solid-state storage offers low power consumption, but its capacity is an order of magnitude smaller than the hard disks needed for high-resolution photos and digital video. In order to create a device with the space of a hard drive, yet the low power consumption of solid-state storage, hardware manufacturers have proposed using flash memory as a write buffer on mobile systems. This paper evaluates the power savings of such an approach and also considers other possible flash allocation algorithms, using both hardware- and software-level flash management. Its contributions also include a set of typical multimedia-rich workloads for mobile systems and power models based upon current disk and flash technology. Based on these workloads, we demonstrate an average power savings of 267 mW (53% of disk power) using hardware-only approaches. Next, we propose another algorithm, termed Energy-efficient Virtual Storage using Application-Level Framing (EVS-ALF), which uses both hardware and software for power management. By collecting information from the applications and using this metadata to perform intelligent flash allocation and prefetching, EVS-ALF achieves an average power savings of 307 mW (61%), another 8% improvement over hardware-only techniques.

  4. Low power adder based digital filter for QRS detector.

    Science.gov (United States)

    Murali, L; Chitra, D; Manigandan, T

    2014-01-01

    Most of the Biomedical applications use dedicated processors for the implementation of complex signal processing. Among them, sensor network is also a type, which has the constraint of low power consumption. Since the processing elements are the most copiously used operations in the signal processors, the power consumption of this has the major impact on the system level application. In this paper, we introduce low power concept of transistor stacking to reduce leakage power; and new architectures based on stacking to implement the full adder and its significance at the digital filter level for QRS detector are implemented. The proposed concept has lesser leakage power at the adder as well as filter level with trade-off in other quality metrics of the design. This enabled the design to be dealt with as the low-power corner and can be made adaptable to any level of hierarchical abstractions as per the requirement of the application. The proposed architectures are designed, modeled at RTL level using the Verilog-HDL, and synthesized in Synopsys Design Compiler by mapping the design to 65 nm technology library standard cells.

  5. Low-power wireless sensor networks for environmental monitoring

    Science.gov (United States)

    Musaloiu-Elefteri, Razvan

    Significant progress has been made in the field of Wireless Sensor Networks in the decade that passed since its inception. This thesis presents several advances intended to make these networks a suitable instrument for environmental monitoring. The thesis first describes Koala, a low-power data-retrieval system that can achieve duty cycles below 1% by using bulk transfers, and Low Power Probing, a novel mechanism to efficiently wake up a network. The second contribution is Serendipity, another data-retrieval system, which takes advantage of the random rendezvous inherent in the Low Power Probing mechanism to achieve a very low duty cycle for low data rate networks. The third part explores the problem of and presents a solution for the interference between WSNs using IEEE 802.15.4 radios and the ubiquitous WiFi networks in the 2.4 GHz spectrum bandwidth. The last contribution of this thesis is Latte, a restricted version of the JavaScript language, that not only can be compiled to C and dynamically loaded on a sensing node, but can also be simulated and debugged in a JavaScript-enabled browser.

  6. 47 CFR 74.707 - Low power TV and TV translator station protection.

    Science.gov (United States)

    2010-10-01

    ... 47 Telecommunication 4 2010-10-01 2010-10-01 false Low power TV and TV translator station... SERVICES Low Power TV, TV Translator, and TV Booster Stations § 74.707 Low power TV and TV translator station protection. (a)(1) A low power TV or TV translator will be protected from interference from...

  7. Circuits and Systems for Low-Power Miniaturized Wireless Sensors

    Science.gov (United States)

    Nagaraju, Manohar

    The field of electronic sensors has witnessed a tremendous growth over the last decade particularly with the proliferation of mobile devices. New applications in Internet of Things (IoT), wearable technology, are further expected to fuel the demand for sensors from current numbers in the range of billions to trillions in the next decade. The main challenges for a trillion sensors are continued miniaturization, low-cost and large-scale manufacturing process, and low power consumption. Traditional integration and circuit design techniques in sensor systems are not suitable for applications in smart dust, IoT etc. The first part of this thesis demonstrates an example sensor system for biosignal recording and illustrates the tradeoffs in the design of low-power miniaturized sensors. The different components of the sensor system are integrated at the board level. The second part of the thesis demonstrates fully integrated sensors that enable extreme miniaturization of a sensing system with the sensor element, processing circuitry, a frequency reference for communication and the communication circuitry in a single hermetically sealed die. Design techniques to reduce the power consumption of the sensor interface circuitry at the architecture and circuit level are demonstrated. The principles are used to design sensors for two of the most common physical variables, mass and pressure. A low-power wireless mass and pressure sensor suitable for a wide variety of biological/chemical sensing applications and Tire Pressure Monitoring Systems (TPMS) respectively are demonstrated. Further, the idea of using high-Q resonators for a Voltage Controlled Oscillator (VCO) is proposed and a low-noise, wide bandwidth FBAR-based VCO is presented.

  8. Implementation of Different Low Power Multipliers Using Verilog

    Directory of Open Access Journals (Sweden)

    Koteswara Rao Ponnuru

    2014-06-01

    Full Text Available Low power consumption and smaller area are some of the most important criteria for the fabrication of DSP systems and high performance systems. Optimizing the speed and area of the multiplier is a major design issue. Multiplication represents a fundamental building block in all DSP tasks. The objective of a good multiplier is to provide a physically compact, good speed and low power consumption. To save significant power consumption of a VLSI design it is a good direction to reduce its dynamic power that is the major part of total power consumption. Two methods are common in current implementations: regular arrays and Wallace trees. The gate-level analyses have suggested that not only are Wallace trees faster than array schemes, they also consume much less power. However these analyses did not take wiring into account, resulting in optimistic timing and power estimates. Continuous advances of microelectronic technologies make better use of energy, encode data more effectively, reduce power consumption, etc. Particularly, many of these technologies address low-power consumption to meet the requirements of various portable applications. In these application systems, a multiplier is a fundamental arithmetic unit and widely used in circuits. I compare results for 8bit-width the working of different multipliers by comparing the power consumption by each of them. The result of my paper helps us to choose a better option between serial and parallel multiplier in fabricating different systems. Multipliers form one of the most important components of many systems. So, by analyzing the working of different multipliers helps to frame a better system with less power consumption and lesser area.

  9. Low-power Analog VLSI Implementation of Wavelet Transform

    Institute of Scientific and Technical Information of China (English)

    ZHANG Jiang-hong

    2009-01-01

    For applications requiring low-power, low-voltage and real-time, a novel analog VLSI implementation of continuous Marr wavelet transform based on CMOS log-domain integrator is proposed.Mart wavelet is approximated by a parameterized class of function and with Levenbery-Marquardt nonlinear least square method,the optimum parameters of this function are obtained.The circuits of implementating Mart wavelet transform are composed of analog filter whose impulse response is the required wavelet.The filter design is based on IFLF structure with CMOS log-domain integrators as the main building blocks.SPICE simulations indicate an excellent approximations of ideal wavelet.

  10. Low Power, Wide Dynamic Range Carbon Nanotube Vacuum Gauges

    Science.gov (United States)

    Kaul, Anupama B.; Manohara, Harish M.

    2008-01-01

    This slide presentation presents carbon nanotube vacuum pressure sensor gauges that operate at low power and exhibit a wide-dynamic range based on microelectromechanical systems (MEMS) technology. The fabrication facility, and the formation process are shown. Pressure sensitivity was found to increase rapidly as the bias power was increased. In addition, by etching part of the thermal SiO2 beneath the tubes and minimizing heat conduction through the substrate, pressure sensitivity was extended toward lower pressures. Results are compared to a conventional thin film meander resistor, which was fabricated and whose pressure response was also measured for comparative purposes.

  11. Extreme low-power mixed signal IC design

    CERN Document Server

    Tajalli, Armin

    2010-01-01

    This book describes a completely novel class of techniques for designing ultra-low-power integrated circuits (ICs). In many applications such as battery operated systems and battery-less (energy-scavenging) systems, power dissipation is a critical parameter. As a result, there is a growing demand for reducing the power (energy) consumption in ICs to extremely low levels, not achievable by using classical ""subthreshold CMOS"" techniques. This book introduces a new family of ""subthreshold circuits"" called ""source-coupled circuits"". This family of circuits can be used for implementing digita

  12. High Speed, Low Power Current Comparators with Hysteresis

    CERN Document Server

    Chasta, Neeraj K

    2012-01-01

    This paper, presents a novel idea for analog current comparison which compares input signal current and reference currents with high speed, low power and well controlled hysteresis. Proposed circuit is based on current mirror and voltage latching techniques which produces rail to rail output voltage as a result of current comparison. The same design can be extended to a simple current comparator without hysteresis (or very less hysteresis), where comparator gives high accuracy (less than 50nA) and speed at the cost of moderate power consumption. The comparators are designed optimally and studied at 180nm CMOS process technology for a supply voltage of 3V.

  13. Low power sessile droplet actuation via modulated surface acoustic waves

    CERN Document Server

    Baudoin, Michael; Matar, Olivier Bou; Herth, Etienne

    2012-01-01

    Low power actuation of sessile droplets is of primary interest for portable or hybrid lab-on-a-chip and harmless manipulation of biofluids. In this paper, we show that the acoustic power required to move or deform droplets via surface acoustic waves can be substantially reduced through the forcing of the drops inertio-capillary modes of vibrations. Indeed, harmonic, superharmonic and subharmonic (parametric) excitation of these modes are observed when the high frequency acoustic signal (19.5 MHz) is modulated around Rayleigh-Lamb inertio-capillary frequencies. This resonant behavior results in larger oscillations and quicker motion of the drops than in the non-modulated case.

  14. High Speed, Low Power Current Comparators with Hysteresis

    Directory of Open Access Journals (Sweden)

    Neeraj K. Chasta

    2012-02-01

    Full Text Available This paper, presents a novel idea for analog current comparison which compares input signal current and reference currents with high speed, low power and well controlled hysteresis. Proposed circuit is based on current mirror and voltage latching techniques which produces rail to rail output voltage as a result of current comparison. The same design can be extended to a simple current comparator without hysteresis (or very less hysteresis, where comparator gives high accuracy (less than 50nA and speed at the cost of moderate power consumption. The comparators are designed optimally and studied at 180 nm CMOS process technology for a supply voltage of 3V.

  15. High Speed, Low Power Current Comparators with Hysteresis

    Directory of Open Access Journals (Sweden)

    Neeraj K. Chasta

    2012-03-01

    Full Text Available This paper, presents a novel idea for analog current comparison which compares input signal current and reference currents with high speed, low power and well controlled hysteresis. Proposed circuit is based on current mirror and voltage latching techniques which produces rail to rail output voltage as a result of current comparison. The same design can be extended to a simple current comparator without hysteresis (or very less hysteresis, where comparator gives high accuracy (less than 50nA and speed at the cost of moderate power consumption. The comparators are designed optimally and studied at 180nm CMOS process technology for a supply voltage of 3V.

  16. A Comparative Study on SOI MOSFETs for Low Power Applications

    Directory of Open Access Journals (Sweden)

    Khairul Affendi Rosli

    2013-03-01

    Full Text Available Silicon on Insulator (SOI technology has become one of the most promising technologies in semiconductor fabrication industry for its numerous advantages. This study presents merits and demerits of different SOIs presented in literatures and a comparative study is done based on several design and performance issues for low power applications. From the study it is found that Fully Depleted SOI MOSFET (FDSOI technology is preferred due to its thin size, reduced leakage current and improved power consumption characteristics etc. compared to those of PDSOI and bulk silicon technology.

  17. FPGA Based Low Power ROM Design Using Capacitance Scaling

    DEFF Research Database (Denmark)

    Bansal, Meenakshi; Bansal, Neha; Saini, Rishita

    2015-01-01

    An ideal capacitor will not dissipate any power, but a real capacitor wil l have some power dissipation. In this work, we are going to design capacitance scaling based low power ROM design. In order to test the compatibility of this ROM design with latest i7 Processor, we are operating this ROM w...... in I/O Power, saving of 0.2% occur in Leakage Power, there will be a saving of 11.54% occur in Total Power. This design is implemented on Virtex-5 FPGA using Xilinx ISE and Verilog....

  18. Authenticated Encryption for Low-Power Reconfigurable Wireless Devices

    DEFF Research Database (Denmark)

    Khajuria, Samant; Andersen, Birger

    2013-01-01

    this enabling technology, these radios have to propose cryptographic services such as con- fidentiality, integrity and authentication. Therefore, integration of security services to these low-power devices is very challenging and crucial as they have limited resources and computational capabilities......With the rapid growth of new wireless communication standards, a solution that is capable of providing a seamless shift between existing wireless protocols and high flexibility as well as capability is crucial. Technology based on reconfigurable devices offers this flexibility. In order to avail...

  19. Ultra-low-power short-range radios

    CERN Document Server

    Chandrakasan, Anantha

    2015-01-01

    This book explores the design of ultra-low-power radio-frequency integrated circuits (RFICs), with communication distances ranging from a few centimeters to a few meters. Such radios have unique challenges compared to longer-range, higher-powered systems. As a result, many different applications are covered, ranging from body-area networks to transcutaneous implant communications and Internet-of-Things devices. A mix of introductory and cutting-edge design techniques and architectures which facilitate each of these applications are discussed in detail. Specifically, this book covers:.

  20. Ratiometric artifact reduction in low power reflective photoplethysmography.

    Science.gov (United States)

    Patterson, J A C; Guang-Zhong Yang

    2011-08-01

    This paper presents effective signal-processing techniques for the compensation of motion artifacts and ambient light offsets in a reflective photoplethysmography sensor suitable for wearable applications. A ratiometric comparison of infrared (IR) and red absorption characteristics cancels out noise that is multiplicative in nature and amplitude modulation of pulsatile absorption signals enables rejection of additive noise. A low-power, discrete-time pulse-oximeter platform is used to capture IR and red photoplethysmograms so that the data used for analysis have noise levels representative of what a true body sensor network device would experience. The proposed artifact rejection algorithm is designed for real-time implementation with a low-power microcontroller while being robust enough to compensate for varying levels in ambient light as well as reducing the effects of motion-induced artifacts. The performance of the system is illustrated by its ability to extract a typical plethysmogram heart-rate waveform since the sensor is subjected to a range of physical disturbances.

  1. Low-power portable scanning imaging ladar system

    Science.gov (United States)

    Pyburn, Dana; Leon, Roberto; Haji-Saeed, B.; Sengupta, Sandip K.; Testorf, Markus; Kierstead, John; Khoury, Jehad; Woods, Charles L.; Lorenzo, Joseph

    2003-08-01

    We propose and are in the process of progressively implementing an improved architecture for a laser based system to acquire intensity and range images of hard targets in real-time. The system design emphasizes the use of low power laser sources in conjunction with optical preamplification of target return signals to maintain eye safety without incurring the associated performance penalty. The design leverages advanced fiber optic component technology developed for the commercial market to achieve compactness and low power consumption without the high costs and long lead times associated with custom military devices. All important system parameters are designed to be configured in the field, by the user, in software, allowing for adaptive reconfiguration for different missions and targets. Recently we have started our transition from the initial test bed, using a laser in the visible wavelength, into the final system with a 1550nm diode laser. Currently we are able to acquire and display 3-D false-color and gray-scale images, in the laboratory, at moderate frame rates in real-time. Commercial off-the-shelf data acquisition and signal processing software on a desktop computer equipped with commercial acquisition hardware is utilized. Significant improvements in both range and spatial resolution are expected in the near future.

  2. Design of A Low Power Low Voltage CMOS Opamp

    CERN Document Server

    Baruah, Ratul Kr

    2010-01-01

    In this paper a CMOS operational amplifier is presented which operates at 2V power supply and 1microA input bias current at 0.8 micron technology using non conventional mode of operation of MOS transistors and whose input is depended on bias current. The unique behaviour of the MOS transistors in subthreshold region not only allows a designer to work at low input bias current but also at low voltage. While operating the device at weak inversion results low power dissipation but dynamic range is degraded. Optimum balance between power dissipation and dynamic range results when the MOS transistors are operated at moderate inversion. Power is again minimised by the application of input dependant bias current using feedback loops in the input transistors of the differential pair with two current substractors. In comparison with the reported low power low voltage opamps at 0.8 micron technology, this opamp has very low standby power consumption with a high driving capability and operates at low voltage. The opamp ...

  3. Wake-up receiver based ultra-low-power WBAN

    CERN Document Server

    Lont, Maarten; Roermund, Arthur van

    2014-01-01

    This book presents the cross-layer design and optimization of wake-up receivers for wireless body area networks (WBAN), with an emphasis on low-power circuit design. This includes the analysis of medium access control (MAC) protocols, mixer-first receiver design, and implications of receiver impairments on wideband frequency-shift-keying (FSK) receivers. Readers will learn how the overall power consumption is reduced by exploiting the characteristics of body area networks. Theoretical models presented are validated with two different receiver implementations, in 90nm and 40nm CMOS technology.   • Provides an overview of wireless body area network design from the network layer to the circuit implementation, and an overview of the cross-layer design trade-offs; • Discusses design at both the network or MAC-layer and circuit-level, with an emphasis on circuit design; • Covers the design of low-power frequency shift keying (FSK) wake-up-receivers; • Validates theory presented with two different recei...

  4. Coherent and noncoherent low-power diodes in clinical practice

    Science.gov (United States)

    Antipa, Ciprian; Pascu, Mihail-Lucian; Stanciulescu, Viorica; Vlaiculescu, Mihaela; Ionescu, Elena; Bordea, Daniel

    1997-05-01

    Clinical efficacy of the low power laser (LPL) in medical treatments is still not well established. In a double blind, placebo controlled study, we tried to find out first which type of LPL is more efficient, and second if coherence is an important character for clinical efficacy. We treated 1228 patients having different rheumatic diseases, with low power diode, used as follows: A group: IR coherent diode, continuous emission, 3 mW power; B group: IR coherent diode, pulsed emission, output power about 3 mW; C group: IR noncoherent diode continuous emission 9 mW power; D group: both IR diode lasers (continuous or pulsed) and HeNe laser, continuous emission, 2 mW power; E group: placebo laser as control group. The energy dose used for every group was the same, as well as the clinical protocols. The positive results were: 66.16% for A group; 64.06% for B group; 48.87% for C group; 76.66% for D group, and 39.07% for E group. Finally, we showed that LPL is really efficient in the treatment of some rheumatic diseases, especially when red and IR diode laser were used in combination. The type of emission (continuous or pulsed) is not important, but coherence is obviously necessary for clinical efficacy.

  5. Biophysical basis of low-power-laser effects

    Science.gov (United States)

    Karu, Tiina I.

    1996-06-01

    Biological responses of cells to visible and near IR (laser) radiation occur due to physical and/or chemical changes in photoacceptor molecules, components of respiratory chains (cyt a/a3 in mitochondria). As a result of the photoexcitation of electronic states, the following physical and/or chemical changes can occur: alteration of redox properties and acceleration of electron transfer, changes in biochemical activity due to local transient heating of chromophores, one-electron auto-oxidation and O2- production, and photodynamic action and 1O2 production. Different reaction channels can be activated to achieve the photobiological macroeffect. The primary physical and/or chemical changes induced by light in photoacceptor molecules are followed by a cascade of biochemical reactions in the cell that do not need further light activation and occur in the dark (photosignal transduction and amplification chains). These actions are connected with changes in cellular homeostasis parameters. The crucial step here is thought to be an alteration of the cellular redox state: a shift towards oxidation is associated with stimulation of cellular vitality, and a shift towards reduction is linked to inhibition. Cells with a lower than normal pH, where the redox state is shifted in the reduced direction, are considered to be more sensitive to the stimulative action of light than those with the respective parameters being optimal or near optimal. This circumstance explains the possible variations in observed magnitudes of low-power laser effects. Light action on the redox state of a cell via the respiratory chain also explains the diversity of low-power laser effects. Beside explaining many controversies in the field of low-power laser effects (i.e., the diversity of effects, the variable magnitude or absence of effects in certain studies), the proposed redox-regulation mechanism may be a fundamental explanation for some clinical effects of irradiation, for example the positive

  6. Ultra-Low-Power Hybrid Light-Matter Solitons

    CERN Document Server

    Tinkler, L; Skryabin, D V; Yulin, A; Royall, B; Farrer, I; Ritchie, D A; Krizhanovskii, D N; Skolnick, M S

    2014-01-01

    New functionalities in nonlinear optics will require systems with giant optical nonlinearity as well as compatibility with photonic circuit fabrication techniques. Here we introduce a new platform based on strong light-matter coupling between waveguide photons and quantum-well excitons. On a sub-millimeter length scale we generate sub-picosecond bright temporal solitons at a pulse energy of only 0.5 pico-Joules. From this we deduce an unprecedented nonlinear refractive index 3 orders of magnitude larger than in any other ultrafast system. We study both temporal and spatio-temporal nonlinear effects and for the first time observe dark-bright spatio-temporal solitons. Theoretical modelling of soliton formation in the strongly coupled system confirms the experimental observations. These results show the promise of our system as a high speed, low power, integrated platform for physics and devices based on strong interactions between photons.

  7. DAC for High Speed and Low Power Applications Using Abacus

    Directory of Open Access Journals (Sweden)

    Shankarayya G. Kambalimath

    2014-02-01

    Full Text Available This paper proposes a Chinese Abacus Digital-to-Ana log Converter (DAC for high speed and low power applications like audio and video applica tions. This circuit of DAC uses resister strings to get a good analog output. The designed D AC uses the algorithm of abacus. Instead of using binary code, here we use abacus code to contr ol the switches. So the complexity and the area will be reduced automatically. The 8-bit D AC is comprised of 12 resistors and 24 NMOS switches. The 8-bit Abacus resistor DAC requires 12 resistors and 24 switches. The 8-bit resistor-string DAC requires 255 resistors and 256 switches. The most important advantages are that the numbers of both resistors and switches are all reduced effectively. The simulation environment uses 1 μ m process technology

  8. Towards Low-Power On-chip Auditory Processing

    Directory of Open Access Journals (Sweden)

    Paul Hasler

    2005-05-01

    Full Text Available Machine perception is a difficult problem both from a practical or implementation point of view as well as from a theoretical or algorithm point of view. Machine perception systems based on biological perception systems show great promise in many areas but they often have processing requirements and/or data flow requirements that are difficult to implement, especially in small or low-power systems. We propose a system design approach that makes it possible to implement complex functionality using cooperative analog-digital signal processing to lower-power requirements dramatically over digital-only systems, as well as provide an architecture facilitating the development of biologically motivated perception systems. We show the architecture and application development approach. We also present several reference systems for speech recognition, noise suppression, and audio classification.

  9. Low-Power Design of Ethernet Data Transmission

    Institute of Scientific and Technical Information of China (English)

    Wen-Ming Pan; Qin Zhang; Jia-Feng Chen; Hao-Yuan Wang; Jia-Chong Kan

    2014-01-01

    For the reliability and power consumption issues of Ethernet data transmission based on the field programmable gate array (FPGA), a low-power consumption design method is proposed, which is suitable for FPGA implementation. To reduce the dynamic power consumption of integrated circuit (IC) design, the proposed method adopts the dynamic control of the clock frequency. For most of the time, when the port is in the idle state or lower-rate state, users can reduce or even turn off the reading clock frequency and reduce the clock flip frequency in order to reduce the dynamic power consumption. When the receiving rate is high, the reading clock frequency will be improved timely to ensure that no data will lost. Simulated and verified by Modelsim, the proposed method can dynamically control the clock frequency, including the dynamic switching of high-speed and low-speed clock flip rates, or stop of the clock flip.

  10. Power-optimal encoding for low-power address bus

    Institute of Scientific and Technical Information of China (English)

    2007-01-01

    This paper presented a novel bus encoding method to reduce the switching activity on address buses and hence reduce power dissipation. Dynamic-sorting encoding (DSE) method reduces the power dissipation of address bus based on the dynamic reordering of the modified offset address bus lines. This method reorders the ten least significant bits of offset address according to the range of offset address, and the optimal sorting pattern is transmitted through the high bits of address bus without the need for redundant bus lines. The experimental results using an instruction set simulator and SPEC2000 benchmarks show that DSE method can reduce signal transitions on the address bus by 88.2%, and the actual overhead of the encoder circuit is estimated after encoder is designed and synthesized in 0.18-μm CMOS technology. The results show that DSE method outperforms the low-power encoding schemes presented in the past.

  11. Low power RF amplifier circuit for ion trap applications

    Science.gov (United States)

    Noriega, J. R.; García-Delgado, L. A.; Gómez-Fuentes, R.; García-Juárez, A.

    2016-09-01

    A low power RF amplifier circuit for ion trap applications is presented and described. The amplifier is based on a class-D half-bridge amplifier with a voltage mirror driver. The RF amplifier is composed of an RF class-D amplifier, an envelope modulator to ramp up the RF voltage during the ion analysis stage, a detector or amplitude demodulation circuit for sensing the output signal amplitude, and a feedback amplifier that linearizes the steady state output of the amplifier. The RF frequency is set by a crystal oscillator and the series resonant circuit is tuned to the oscillator frequency. The resonant circuit components have been chosen, in this case, to operate at 1 MHz. In testings, the class-D stage operated at a maximum of 78 mW at 1.1356 MHz producing 225 V peak.

  12. Pulse swallowing frequency divider with low power and compact structure

    Institute of Scientific and Technical Information of China (English)

    Gao Haijun; Sun Lingling; Cai Chaobo; Zhan Haiting

    2012-01-01

    A pulse swallowing frequency divider with low power and compact structure is presented.One of the DFFs in the divided by 2/3 prescaler is controlled by the modulus control signal,and automatically powered off when it has no contribution to the operation of the prescaler.The DFFs in the program counter and the swallow counter are shared to compose a compact structure,which reduces the power consumption further.The proposed multi-modulus frequency divider was implemented in a standard 65 nm CMOS process with an area of 28 ×22 μm2.The power consumption of the divider is 0.6 mW under 1.2 V supply voltage when operating at 988 MHz.

  13. Low Power Reversible Parallel Binary Adder/Subtractor

    CERN Document Server

    Rangaraju, H G; Muralidhara, K N; Raja, K B; 10.5121/vlsic.2010.1303

    2010-01-01

    In recent years, Reversible Logic is becoming more and more prominent technology having its applications in Low Power CMOS, Quantum Computing, Nanotechnology, and Optical Computing. Reversibility plays an important role when energy efficient computations are considered. In this paper, Reversible eight-bit Parallel Binary Adder/Subtractor with Design I, Design II and Design III are proposed. In all the three design approaches, the full Adder and Subtractors are realized in a single unit as compared to only full Subtractor in the existing design. The performance analysis is verified using number reversible gates, Garbage input/outputs and Quantum Cost. It is observed that Reversible eight-bit Parallel Binary Adder/Subtractor with Design III is efficient compared to Design I, Design II and existing design.

  14. Low power linear actuator for direct drive electrohydraulic valves

    Institute of Scientific and Technical Information of China (English)

    Yong LI; Fan DING; Jian CUI; Qi-peng LI

    2008-01-01

    This paper presents a bi-directional permanent-magnet linear actuator for directly driving electrohydraulic valves with low power consumption. Its static and dynamic performances were analyzed using the 2D finite element method, taking into account the nonlinear characterization and the eddy current loss of the magnetic material. The experiment and simulation results agree well and show that the prototype actuator can produce a force of+100 N with the maximum power being 7 W and has linear characteristics with a positive magnetic stiffness within a stroke of±1 mm. Its non-linearity is less than 1.5% and the hysteresis less than 1.5%. The actuator's frequency response (-3 dB) of the displacement reaches about 15 Hz, and the most significant factor affecting the dynamic performance is identified as the eddy current loss of the magnetic material.

  15. Low Power Low Voltage Bulk Driven Balanced OTA

    Directory of Open Access Journals (Sweden)

    Neha Gupta

    2012-01-01

    Full Text Available The last few decades, a great deal of attention has been paid to low-voltage (LV low-power (LP integrated circuits design since the power consumption has become a critical issue. Among many techniques used for the design of LV LP analog circuits, the Bulk-driven principle offers a promising route towards this design for many aspects mainly the simplicity and using the conventional MOS technology to implement these designs. This paper is devoted to the Bulk-driven (BD principle and utilizing this principle to design LV LP building block of Operational Transconductance Amplifier (OTA in standard CMOS processes and supply voltage 0.9V. The simulation results have been carried out by the Spice simulatorusing the 130nm CMOS technology from TSMC.

  16. Low Power Low Voltage Bulk Driven Balanced OTA

    Directory of Open Access Journals (Sweden)

    Neha Gupta

    2011-12-01

    Full Text Available The last few decades, a great deal of attention has been paid to low-voltage (LV low-power (LP integrated circuits design since the power consumption has become a critical issue. Among many techniques used for the design of LV LP analog circuits, the Bulk-driven principle offers a promising route towards this design for many aspects mainly the simplicity and using the conventional MOS technology to implement these designs. This paper is devoted to the Bulk-driven (BD principle and utilizing this principle to design LV LP building block of Operational Trans conductance Amplifier (OTA in standard CMOS processes and supply voltage 0.9 V. The simulation results have been carried out by the Spice simulator using the 130 nm CMOS technology from TSMC.

  17. Low Power Low Voltage Bulk Driven Balanced OTA

    CERN Document Server

    Gupta, Neha; Suthar, Meenakshi; Soni, Priyanka

    2012-01-01

    The last few decades, a great deal of attention has been paid to low-voltage (LV) low-power (LP) integrated circuits design since the power consumption has become a critical issue. Among many techniques used for the design of LV LP analog circuits, the Bulk-driven principle offers a promising route towards this design for many aspects mainly the simplicity and using the conventional MOS technology to implement these designs. This paper is devoted to the Bulk-driven (BD) principle and utilizing this principle to design LV LP building block of Operational Transconductance Amplifier (OTA) in standard CMOS processes and supply voltage 0.9V. The simulation results have been carried out by the Spice simulator using the 130nm CMOS technology from TSMC.

  18. Recent advances in flexible low power cholesteric LCDs

    Science.gov (United States)

    Khan, Asad; Shiyanovskaya, Irina; Montbach, Erica; Schneider, Tod; Nicholson, Forrest; Miller, Nick; Marhefka, Duane; Ernst, Todd; Doane, J. W.

    2006-05-01

    Bistable reflective cholesteric displays are a liquid crystal display technology developed to fill a market need for very low power displays. Their unique look, high reflectivity, bistability, and simple structure make them an ideal flat panel display choice for handheld or other portable devices where small lightweight batteries with long lifetimes are important. Applications ranging from low resolution large signs to ultra high resolution electronic books can utilize cholesteric displays to not only benefit from the numerous features, but also create enabling features that other flat panel display technologies cannot. Flexible displays are the focus of attention of numerous research groups and corporations worldwide. Cholesteric displays have been demonstrated to be highly amenable to flexible substrates. This paper will review recent advances in flexible cholesteric displays including both phase separation and emulsification approaches to encapsulation. Both approaches provide unique benefits to various aspects of manufacturability, processes, flexibility, and conformability.

  19. Low Power Data Acquisition System for Bioimplantable Devices

    Directory of Open Access Journals (Sweden)

    Sadeque Reza Khan

    2014-01-01

    Full Text Available Signal acquisition represents the most important block in biomedical devices, because of its responsibilities to retrieve precise data from the biological tissues. In this paper an energy efficient data acquisition unit is presented which includes low power high bandwidth front-end amplifier and a 10-bit fully differential successive approximation ADC. The proposed system is designed with 0.18 µm CMOS technology and the simulation results show that the bioamplifier maintains a wide bandwidth versus low noise trade-off and the proposed SAR-ADC consumes 450 nW power under 1.8 V supply and retain the effective number of bit 9.55 in 100 KS/s sampling rate.

  20. Low-Power Architecture for an Optical Life Gas Analyzer

    Science.gov (United States)

    Pilgrim, Jeffrey; Vakhtin, Andrei

    2012-01-01

    Analog and digital electronic control architecture has been combined with an operating methodology for an optical trace gas sensor platform that allows very low power consumption while providing four independent gas measurements in essentially real time, as well as a user interface and digital data storage and output. The implemented design eliminates the cross-talk between the measurement channels while maximizing the sensitivity, selectivity, and dynamic range for each measured gas. The combination provides for battery operation on a simple camcorder battery for as long as eight hours. The custom, compact, rugged, self-contained design specifically targets applications of optical major constituent and trace gas detection for multiple gases using multiple lasers and photodetectors in an integrated package.

  1. DESIGN OF 16-BIT LOW POWER ALU - DBGPU

    Directory of Open Access Journals (Sweden)

    Dhanabal R

    2013-06-01

    Full Text Available Arithmetic and Logic Unit (ALU is one of the common and the most crucial components of an embedded system. Power consumption is a major design issue in the case of embedded systems. Usually ALU’s consists of a number of functional units for different arithmetic and logic operations which are realised using combinational circuits. Each of the functional unit performs a specific arithmetic or logic operation. In this paper the main concern is given for reducing the power of the adder and multiplier modules which are important functional units of ALU thereby reducing the overall power consumption without compromising the speed of the processor. The ALU circuit ensures the execution of either arithmetic or logic operation only at a time so that only one set of circuits is active at a time thus ensuring low power consumption. The entire ALU circuit isrealised using Verilog HDL and power analysis is obtained through same.

  2. Low Power Reversible Parallel Binary Adder/Subtractor

    Directory of Open Access Journals (Sweden)

    Rangaraju H G

    2010-09-01

    Full Text Available In recent years, Reversible Logic is becoming more and more prominent technology having its applications in Low Power CMOS, Quantum Computing, Nanotechnology, and Optical Computing. Reversibility plays an important role when energy efficient computations are considered. In this paper, Reversible eight-bit Parallel Binary Adder/Subtractor with Design I, Design II and Design III are proposed. In all the three design approaches, the full Adder and Subtractors are realized in a single unit as compared to only full Subtractor in the existing design. The performance analysis is verified using number reversible gates, Garbage input/outputs and Quantum Cost. It is observed that Reversible eight-bit Parallel Binary Adder/Subtractor with Design III is efficient compared to Design I, Design II and existing design

  3. Low Power Reversible Parallel Binary Adder/Subtractor

    Directory of Open Access Journals (Sweden)

    Muralidhara K N

    2010-09-01

    Full Text Available In recent years, Reversible Logic is becoming more and more prominent technology having its applications inLow Power CMOS, Quantum Computing, Nanotechnology, and Optical Computing. Reversibility plays animportant role when energy efficient computations are considered. In this paper, Reversible eight-bit ParallelBinary Adder/Subtractor with Design I, Design II and Design III are proposed. In all the three designapproaches, the full Adder and Subtractors are realized in a single unit as compared to only full Subtractorin the existing design. The performance analysis is verified using number reversible gates, Garbageinput/outputs and Quantum Cost. It is observed that Reversible eight-bit Parallel Binary Adder/Subtractorwith Design III is efficient compared to Design I, Design II and existing design

  4. A low-power SAR ADC for IRFPA ROIC

    Science.gov (United States)

    Gao, Lei; Ding, Ruijun; Zhou, Jie; Wang, Pan; Chen, Guoqiang

    2012-12-01

    This paper presents a low power ADC for the 512*512 infrared focal plane arrays (IRFPA) readout integrated circuit(ROIC). The major structure, the working mode and the simulation result of the readout integrated circuit are shown in this paper. The power supply voltage of 0.35μm standard CMOS process is 3.3V in this design, and then the output range of the Direct Injection (DI) input circuit is reached 2V. Successive-approximation-register (SAR) ADC architecture is used in this readout integrated circuit. And each ADC is shared by one column of the IRFPA. This SAR ADC is made up of a 13-bit digital-analog converter (DAC), a high resolution comparator, and a digital control circuit. The most important part is the voltage-scaling and charge-scaling charge redistribution DAC. In this DAC, charge scaling with a capacitor ladder to determine the least significant bits is combined with voltage scaling with a resister ladder to determine the most significant bits. The comparator uses three-stage operational amplifier structure to get a 77dB differential gain. The Common-Mode input rang of the comparator is 1V to 3V, and minimum resolvable voltage difference is 0.3mV. This SAR ADC has some advantages, especially in low power and high speed. The simulation result shows that the resolution of the ADC is 12 bit and the conversion time of the ADC is 6.5μs, while the power of each ADC is as low as 300μW. Finally, this SAR ADC can satisfy the request of 512*512 IRFPAs ROIC with a 100Hz frame rate.

  5. High-Voltage, Low-Power BNC Feedthrough Terminator

    Science.gov (United States)

    Bearden, Douglas

    2012-01-01

    This innovation is a high-voltage, lowpower BNC (Bayonet Neill-Concelman) feedthrough that enables the user to terminate an instrumentation cable properly while connected to a high voltage, without the use of a voltage divider. This feedthrough is low power, which will not load the source, and will properly terminate the instrumentation cable to the instrumentation, even if the cable impedance is not constant. The Space Shuttle Program had a requirement to measure voltage transients on the orbiter bus through the Ground Lightning Measurement System (GLMS). This measurement has a bandwidth requirement of 1 MHz. The GLMS voltage measurement is connected to the orbiter through a DC panel. The DC panel is connected to the bus through a nonuniform cable that is approximately 75 ft (approximately equal to 23 m) long. A 15-ft (approximately equal to 5-m), 50-ohm triaxial cable is connected between the DC panel and the digitizer. Based on calculations and simulations, cable resonances and reflections due to mismatched impedances of the cable connecting the orbiter bus and the digitizer causes the output not to reflect accurately what is on the bus. A voltage divider at the DC panel, and terminating the 50-ohm cable properly, would eliminate this issue. Due to implementation issues, an alternative design was needed to terminate the cable properly without the use of a voltage divider. Analysis shows how the cable resonances and reflections due to the mismatched impedances of the cable connecting the orbiter bus and the digitizer causes the output not to reflect accurately what is on the bus. After simulating a dampening circuit located at the digitizer, simulations were performed to show how the cable resonances were dampened and the accuracy was improved significantly. Test cables built to verify simulations were accurate. Since the dampening circuit is low power, it can be packaged in a BNC feedthrough.

  6. Low-power microfluidic electro-hydraulic pump (EHP).

    Science.gov (United States)

    Lui, Clarissa; Stelick, Scott; Cady, Nathaniel; Batt, Carl

    2010-01-07

    Low-power electrolysis-based microfluidic pumps utilizing the principle of hydraulics, integrated with microfluidic channels in polydimethylsiloxane (PDMS) substrates, are presented. The electro-hydraulic pumps (EHPs), consisting of electrolytic, hydraulic and fluidic chambers, were investigated using two types of electrodes: stainless steel for larger volumes and annealed gold electrodes for smaller-scale devices. Using a hydraulic fluid chamber and a thin flexible PDMS membrane, this novel prototype successfully separates the reagent fluid from the electrolytic fluid, which is particularly important for biological and chemical applications. The hydraulic advantage of the EHP device arises from the precise control of flow rate by changing the electrolytic pressure generated, independent of the volume of the reagent chamber, mimicking the function of a hydraulic press. Since the reservoirs are pre-filled with reagents and sealed prior to testing, external fluid coupling is minimized. The stainless steel electrode EHPs were manufactured with varying chamber volume ratios (1 : 1 to 1 : 3) as a proof-of-concept, and exhibited flow rates of 1.25 to 30 microl/min with electrolysis-based actuation at 2.5 to 10 V(DC). The miniaturized gold electrode EHPs were manufactured with 3 mm diameters and 1 : 1 chamber volume ratios, and produced flow rates of 1.24 to 7.00 microl/min at 2.5 to 10 V(AC), with a higher maximum sustained pressure of 343 KPa, suggesting greater device robustness using methods compatible with microfabrication. The proposed technology is low-cost, low-power and disposable, with a high level of reproducibility, allowing for ease of fabrication and integration into existing microfluidic lab-on-a-chip and analysis systems.

  7. Low power laser therapy — an introduction and a review of some biological effects

    OpenAIRE

    Thiel, Haymo

    1986-01-01

    This report gives a brief introduction to the characteristics of therapeutic low power laser devices. Absorption, tissue penetration and physiological mechanisms of laser irradiation are discussed. The biological effects of low power laser light are reviewed in the areas of collagen metabolism, woundhealing, inflammation and pain control. Contraindications, precautions and side effects of low power laser irradiation are discussed.

  8. 47 CFR 73.6019 - Digital Class A TV station protection of low power TV, TV translator, digital low power TV and...

    Science.gov (United States)

    2010-10-01

    ... 47 Telecommunication 4 2010-10-01 2010-10-01 false Digital Class A TV station protection of low power TV, TV translator, digital low power TV and digital TV translator stations. 73.6019 Section 73... BROADCAST SERVICES Class A Television Broadcast Stations § 73.6019 Digital Class A TV station protection...

  9. Low power laser therapy in treatment of bronchial asthma

    Directory of Open Access Journals (Sweden)

    Milojević Momir

    2003-01-01

    Full Text Available Introduction Modern concept of acupuncture is based on the fact there are designated locations on the surface of human body, which are related to integrative systems of an organism by means of sensory nerves, correlating and synchronizing organ functioning, depending on external and internal conditions, by means of nervous and neurohumoral regulation of metabolic and regenerative processes, including also mobilization of immunological, protective and antistress reactions. Apart from standard needle acupuncture, other methods of stimulating acupuncture points are also applied. Due to invention of low power lasers, irradiation laser acupuncture has been introduced into routine medical practice, characterized by painless and aseptic technique and outstanding clinical results. Material and methods The investigation was aimed at defining therapeutic effects of low power laser irradiation by stimulating acupuncture points or local treatment of asthma. A prospective analysis included 50 patients treated at the Institute of Pulmonary Diseases in Sremska Kamenica during 2000, 2001 and 2002. Together with conservative treatment of present disease, these patients were treated with laser stimulation of acupuncture points in duration of ten days. During treatment changes of functional respiratory parameters were recorded. Results were compared with those in the control group. The control group consisted of the same number of patients and differed from the examination group only by not using laser stimulation. Results Patients with bronchial asthma presented with significant improvement (p<0,0005 of all estimated lung function parameters just 30 minutes after laser stimulation. Improvements achieved on the third and the tenth day of treatment were significantly higher (p<0,001 to p<0,00005 in the examination group in comparison with the control group. Further investigation confirmed that improvement of measured lung function parameters was significantly

  10. Low-power nanophotonics: material and device technology

    Science.gov (United States)

    Thylén, Lars; Holmstrom, Petter; Wosinski, Lech; Lourdudoss, Sebastian

    2013-05-01

    Development in photonics for communications and interconnects pose increasing requirements on reduction of footprint, power dissipation and cost, as well as increased bandwidth. Nanophotonics integrated photonics has been viewed as a solution to this, capitalizing on development in nanotechnology and an increased understanding of light matter interaction on the nanoscale. The latter can be exemplified by plasmonics and low dimensional semiconductors such as quantum dots (QDs). In this scenario the development of improved electrooptic materials is of great importance, the electrooptic polymers being an example, since they potentially offer superior properties for optical phase modulators in terms of power and integratability. Phase modulators are essential for e.g. the rapidly developing advanced modulation formats, since phase modulation basically can generate any type of modulation. The electrooptic polymers, in combination with plasmonics nanoparticle array waveguides or nanostructured hybrid plasmonic media can give extremely compact and low power dissipation modulators. Low-dimensional semiconductors, e.g. in the shape of QDs, can be employed for modulation or switching functions, offering possibilities for scaling to 2 or 3 dimensions for advanced switching functions. In both the high field confinement plasmonics and QDs, the nanosizing is due to nearfield interactions, albeit being of different physical origin in the two cases. Epitaxial integration of III-V structures on Si plays an important role in developing high-performance light sources on silicon, eventually integrated with silicon electronics. A brief remark on all-optical vs. electronically controlled optical switching systems is also given.

  11. High-Resolution Low Power, Intergrated Aftershock and Microzonation System

    Science.gov (United States)

    Zimakov, L.; Passmore, P.

    2012-04-01

    Refraction Technology, Inc. has developed a self-contained, fully integrated Aftershock System, model 160-03, providing the customer simple and quick deployment during aftershock emergency mobilization and microzonation studies. The 160-03 has no external cables or peripheral equipment for command/control and operation in the field. The 160-03 contains three major components integrated in one case: a) 24-bit resolution state-of-the art low power ADC with CPU and Lid interconnect boards; b) power source; and c) three component 2 Hz sensors (two horizontals and one vertical), and built-in ±4g accelerometer. Optionally, the 1 Hz sensors can be built-in the 160-03 system at the customer's request. The self-contained rechargeable battery pack provides power autonomy up to 7 days during data acquisition at 200 sps on continuous three weak motion and triggered three strong motion recording channels. For longer power autonomy, the 160-03 Aftershock System battery pack can be charged from an external source (solar power system). The data in the field is recorded to a built-in swappable USB flash drive. The 160-03 configuration is fixed based on a configuration file stored on the system. The detailed specifications and performance are presented and discussed

  12. ``Low Power Wireless Technologies: An Approach to Medical Applications''

    Science.gov (United States)

    Bellido O., Francisco J.; González R., Miguel; Moreno M., Antonio; de La Cruz F, José Luis

    Wireless communication supposed a great both -quantitative and qualitative, jump in the management of the information, allowing the access and interchange of it without the need of a physical cable connection. The wireless transmission of voice and information has remained in constant evolution, arising new standards like BluetoothTM, WibreeTM or ZigbeeTM developed under the IEEE 802.15 norm. These newest wireless technologies are oriented to systems of communication of short-medium distance and optimized for a low cost and minor consume, becoming recognized as a flexible and reliable medium for data communications across a broad range of applications due to the potential that the wireless networks presents to operate in demanding environments providing clear advantages in cost, size, power, flexibility, and distributed intelligence. About the medical applications, the remote health or telecare (also called eHealth) is getting a bigger place into the manufacturers and medical companies, in order to incorporate products for assisted living and remote monitoring of health parameteres. At this point, the IEEE 1073, Personal Health Devices Working Group, stablish the framework for these kind of applications. Particularly, the 1073.3.X describes the physical and transport layers, where the new ultra low power short range wireless technologies can play a big role, providing solutions that allow the design of products which are particularly appropriate for monitor people’s health with interoperability requirements.

  13. Optimization of Passive Low Power Wireless Electromagnetic Energy Harvesters

    Directory of Open Access Journals (Sweden)

    Dario Grgić

    2012-10-01

    Full Text Available This work presents the optimization of antenna captured low power radio frequency (RF to direct current (DC power converters using Schottky diodes for powering remote wireless sensors. Linearized models using scattering parameters show that an antenna and a matched diode rectifier can be described as a form of coupled resonator with different individual resonator properties. The analytical models show that the maximum voltage gain of the coupled resonators is mainly related to the antenna, diode and load (remote sensor resistances at matched conditions or resonance. The analytical models were verified with experimental results. Different passive wireless RF power harvesters offering high selectivity, broadband response and high voltage sensitivity are presented. Measured results show that with an optimal resistance of antenna and diode, it is possible to achieve high RF to DC voltage sensitivity of 0.5 V and efficiency of 20% at −30 dBm antenna input power. Additionally, a wireless harvester (rectenna is built and tested for receiving range performance.

  14. Nanoelectromechanical Switches for Low-Power Digital Computing

    Directory of Open Access Journals (Sweden)

    Alexis Peschot

    2015-08-01

    Full Text Available The need for more energy-efficient solid-state switches beyond complementary metal-oxide-semiconductor (CMOS transistors has become a major concern as the power consumption of electronic integrated circuits (ICs steadily increases with technology scaling. Nano-Electro-Mechanical (NEM relays control current flow by nanometer-scale motion to make or break physical contact between electrodes, and offer advantages over transistors for low-power digital logic applications: virtually zero leakage current for negligible static power consumption; the ability to operate with very small voltage signals for low dynamic power consumption; and robustness against harsh environments such as extreme temperatures. Therefore, NEM logic switches (relays have been investigated by several research groups during the past decade. Circuit simulations calibrated to experimental data indicate that scaled relay technology can overcome the energy-efficiency limit of CMOS technology. This paper reviews recent progress toward this goal, providing an overview of the different relay designs and experimental results achieved by various research groups, as well as of relay-based IC design principles. Remaining challenges for realizing the promise of nano-mechanical computing, and ongoing efforts to address these, are discussed.

  15. Aircraft gas turbine low-power emissions reduction technology program

    Science.gov (United States)

    Dodds, W. J.; Gleason, C. C.; Bahr, D. W.

    1978-01-01

    Advanced aircraft turbine engine combustor technology was used to reduce low-power emissions of carbon monoxide and unburned hydrocarbons to levels significantly lower than those which were achieved with current technology. Three combustor design concepts, which were designated as the hot-wall liner concept, the recuperative-cooled liner concept, and the catalyst converter concept, were evaluated in a series of CF6-50 engine size 40 degree-sector combustor rig tests. Twenty-one configurations were tested at operating conditions spanning the design condition which was an inlet temperature and pressure of 422 K and 304 kPa, a reference velocity of 23 m/s and a fuel-air-ration of 10.5 g/kg. At the design condition typical of aircraft turbine engine ground idle operation, the best configurations of all three concepts met the stringent emission goals which were 10, 1, and 4 g/kg for CO, HC, and Nox, respectively.

  16. Compact, Low-power and Precision Timing Photodetector Readout

    Energy Technology Data Exchange (ETDEWEB)

    Varner, Gary S.; Ruckman, Larry L.; /Hawaii U.; Schwiening, Jochen; Vavra, Jaroslav; /SLAC

    2011-06-14

    Photodetector readout for next generation high event rate particle identification and single-photon detection requires a digitizer capable of integrated recording of dense arrays of sensor elements with high analog bandwidth (precision timing) and large record depth, in a cost-effective, compact and low-power way. Simply stated, one cannot do better than having a high-fidelity 'oscilloscope on a chip' for every sensor channel. A firs version of the Buffered Large Analog Bandwidth (BLAB1) ASIC has been designed based upon the lessons learned from the development of the Large Analog Bandwidth Recorder and Digitizer with Ordered Readout (LABRADOR) ASIC. While this LABRADOR ASIC has been very successful and forms the readout basis of a generation of new, large-scale radio neutrino detectors, its limited sampling depth is a major drawback. To address this shortcoming, a prototype intended for photodetector readout has been designed and fabricated with 64k deep sampling at multi-GSa/s operation. An evaluation system has been constructed for instrumentation of Time-Of-Propagation (TOP) and focusing DIRC prototypes and test results will be reported.

  17. Bone fracture consolidates faster with low-power laser

    Energy Technology Data Exchange (ETDEWEB)

    Trelles, M.A.; Mayayo, E.

    1987-01-01

    Low-power laser radiation is currently used in the treatment of pain and osteoarticular inflammation. However, the mechanisms of the laser biostimulating effects on tissue are still not completely understood. With laser treatment, we have achieved activation of osseous regeneration in human bone fractures. After 7 years of positive clinical control in human beings, we decided to start an experimental study of fractures in the tibia of mice, histologically controlling its reparation after exposure to 632 nm. He/Ne laser in doses of 2.4 Joules in one point was used. The radiation was directly applied to the area of fracture in a series of 12 treatments (one treatment every second day). By optic microscope we observed, in the treated animals, an important increase in vascularization and faster formation of osseous tissue with a dense trabecular net compared to the control group, which presented only chondroid tissue and poor vascularization corresponding to an earlier stage of bone consolidation (controls were also analyzed by electron microscopy). Potentially, the laser effect might modulate the function of osteocytes, promoting faster metabolism and reaction of bone callus.

  18. Low-Power Embedded DSP Core for Communication Systems

    Directory of Open Access Journals (Sweden)

    Tsao Ya-Lan

    2003-01-01

    Full Text Available This paper proposes a parameterized digital signal processor (DSP core for an embedded digital signal processing system designed to achieve demodulation/synchronization with better performance and flexibility. The features of this DSP core include parameterized data path, dual MAC unit, subword MAC, and optional function-specific blocks for accelerating communication system modulation operations. This DSP core also has a low-power structure, which includes the gray-code addressing mode, pipeline sharing, and advanced hardware looping. Users can select the parameters and special functional blocks based on the character of their applications and then generating a DSP core. The DSP core has been implemented via a cell-based design method using a synthesizable Verilog code with TSMC 0.35 m SPQM and 0.25 m 1P5M library. The equivalent gate count of the core area without memory is approximately 50 k. Moreover, the maximum operating frequency of a version is 100 MHz (0.35 m and 140 MHz (0.25 m.

  19. Low power offloading strategy for femto-cloud mobile network

    Directory of Open Access Journals (Sweden)

    Anwesha Mukherjee

    2016-03-01

    Full Text Available Nowadays offloading is a popular method of mobile cloud computing where the required computation takes place remotely inside the cloud. But whether to process an application inside the mobile device or to the cloud is a challenging issue because communication with the cloud involves latency and power consumption. This paper has proposed a method of decision making regarding whether to offload or not-to-offload an application to the cloud. According to the proposed strategy, application is offloaded only if it results in lower power consumption than local execution within the mobile device itself. If this condition is satisfied, computation time and deadline of the job are considered as the basic parameters to decide whether to offload or not. Experimental results demonstrate that the proposed offloading algorithm reduces the power consumption to approximately 3–32%. To achieve power-efficiency and security both, femto-cloud architecture is used in the proposed work. In this case offloading from the mobile device to the cloud takes place through the low power and secure femtocell base station. Simulation results present that using femto-cloud architecture 70–83% and 52–66% power savings are achieved than using macrocell and microcell base stations respectively while offloading an application to the cloud.

  20. A Low Power Single Phase Clock Distribution Multiband Network

    Directory of Open Access Journals (Sweden)

    Dr.A.Muruganandham#1,

    2014-02-01

    Full Text Available Frequency synthesizer is one of the important elements for wireless communication application. The speed of VCO and prescaler determines how fast the frequency synthesizer is. A dual modulus prescaler contains logic gates and flip-flops. This project aim for developing a low power single clock multiband network which will supply for the multi clock domain network. The multiband divider consists of a proposed wideband multi modulus 32/33/47/48 prescaler and an improved bitcell for swallow (S counter and can divide the frequencies in the three bands of 2.4–2.484 GHz, 5.15–5.35 GHz, and 5.725– 5.825 GHz with a resolution selectable from 1 to 25 MHz The proposed multiband flexible divider is silicon verified and consumes power of 0.96 and 2.2 mW in 2.4- and 5-GHz bands, respectively, when operated at 1.8-V power supply.

  1. Implementation of UART with BIST Technique Using Low Power LFSR

    Directory of Open Access Journals (Sweden)

    Vishalaxi Godi

    2014-07-01

    Full Text Available Asynchronous serial communication is usually implemented by Universal Asynchronous Receiver Transmitter (UART, mostly used for low expense, low speed, short distance data exchange between processor and peripherals. UART allows full duplex serial communication link, and is used in data communication and control system. There is a need for realizing the UART function in a single or a very few chips. Further, design systems without full testability are open to the increased possibility of product failures and missed market opportunities. Also, it is necessary to ensure the data transfer is error proof. This project targets the introduction of Built-in self test (BIST and Status register to UART. The basic idea is to reduce the switching activity among the test patterns at the most. In this approach, the single input change patterns generated by a counter and a gray code generator are Exclusive-ORed with the seed generated by the low power linear feedback shift register [LP-LFSR]. The 8-bit UART with status register and BIST module is coded in Verilog HDL and synthesized and simulated using Xilinx XST and ISim version 14.4 and realized on FPGA.

  2. A low power pulsed arcjet thruster for spacecraft propulsion

    Science.gov (United States)

    Willmes, Gary Francis

    1997-11-01

    An electrothermal thruster that operates in a pulsed mode at low power (pendulum-type thrust stand, and input power levels from 24 to 119 watts are determined from measurements of pulse rate and breakdown voltage. A maximum specific impulse of 305 seconds is achieved with 38% efficiency. A time-dependent, quasi-1D numerical model is developed to evaluate energy losses in the pulsed arcjet. The numerical model uses a time-marching procedure and the MacCormack predictor-corrector algorithm. Viscous and heat transfer effects are incorporated though a friction factor and an average heat transfer coefficient. A numerical study of nozzle parameters, capillary geometry, wall temperature, and pulse energy shows that the performance is insensitive to capillary and nozzle geometry and that thermal characteristics are the dominant factor affecting performance. The specific impulse and efficiency of the pulsed arcjet are found to be sensitive to wall temperature due to heat transfer losses in the subsonic region. A pulse-forming electrical circuit is developed to reduce energy losses in the storage capacitor, and greater than 85% of the initial stored energy is transferred to the arc in a unipolar pulse. A high current diode installed across the capacitor terminals is used to eliminate voltage reversals in the current. The experimental breakdown voltage of the helium gas between the electrodes is found to follow a Paschen relationship where the minimum electrode separation distance is used in evaluating the data.

  3. Failure analysis of a kind of low power connector

    Institute of Scientific and Technical Information of China (English)

    ZHOU Yi-lin; ZENG Ning; XU Liang-jun; J(O)RGENS Stefan

    2007-01-01

    A kind of low power connector used e.g. in household appliances was partly burned in routine experiment. The heat sources were four paralleled contacts constructed by springs (Sn/CuSn-alloy) in socket and a plug sheet (Ni/Steel) while mating. The contact interfaces were detected by scanning electronic microscope (SEM) and X-ray energy dispersive spectroscopy (XEDS), obvious wear tracks and various contaminants, including element Si, Al, Na, K, S, C1, O, etc., were found. The contamination degrees on the four paralleled contacts .were different, so that the ratio of average contact resistance on the four contacts was about 5:8:3:1. The maximum contact resistance on contacts of the plug sheet reached 28 Ω. The main failure reasons were fretting and contamination between the contact interfaces. Fretting simulation showed that connection resistance of connectors was raised up, even to ohms level. When the current increased to 5 A, the socket housing was heated and decomposed. By the thermal analysis, it was estimated that the connector would be burned under the lower current if the current was not evenly distributed on the four paralleled contacts caused by uneven contamination. Improvement methods for connector failure are also discussed.

  4. A Low Power Low Phase Noise Oscillator for MICS Transceivers.

    Science.gov (United States)

    Li, Dawei; Liu, Dongsheng; Kang, Chaojian; Zou, Xuecheng

    2017-01-12

    A low-power, low-phase-noise quadrature oscillator for Medical Implantable Communications Service (MICS) transceivers is presented. The proposed quadrature oscillator generates 349~689 MHz I/Q (In-phase and Quadrature) signals covering the MICS band. The oscillator is based on a differential pair with positive feedback. Each delay cell consists of a few transistors enabling lower voltage operation. Since the oscillator is very sensitive to disturbances in the supply voltage and ground, a self-bias circuit for isolating the voltage disturbance is proposed to achieve bias voltages which can track the disturbances from the supply and ground. The oscillation frequency, which is controlled by the bias voltages, is less sensitive to the supply and ground noise, and a low phase noise is achieved. The chip is fabricated in the UMC (United Microelectronics Corporation) 0.18 μm CMOS (Complementary Metal Oxide Semiconductor) process; the core just occupies a 28.5 × 22 μm² area. The measured phase noise is -108.45 dBc/Hz at a 1 MHz offset with a center frequency of 540 MHz. The gain of the oscillator is 0.309 MHz/mV with a control voltage from 0 V to 1.1 V. The circuit can work with a supply voltage as low as 1.2 V and the power consumption is only 0.46 mW at a 1.8 V supply voltage.

  5. Delay-Limited Capacity in the Low Power Regime

    KAUST Repository

    Rezki, Zouheir

    2016-02-11

    Outage performance of the M-block fading with additive white Gaussian noise (BF-AWGN) is investigated in the low-power regime. We consider delay-constrained constant-rate communications with perfect channel state information (CSI) at both the transmitter and the receiver (CSI-TR), under a shortterm power constraint (STPC) and a long-term power constraint (LTPC). Subject to STPC, we show that selection diversity that allocates all the power to the strongest block is asymptotically optimal. Then, we provide a simple characterization of the outage probability in the regime of interest. We quantify the reward due to CSI-TR over the constant-rate constant-power scheme and show that this reward increases with the delay constraint. For instance, for Rayleigh fading, we find that a power gain up to 4.3 dB is achievable. Subject to LTPC, we show that the above guidelines still holds and that the outage performance improves due to the flexibility of the LTPC over the STPC. More interestingly, we prove that LTPC allows zero-outage communication even at low SNR and characterize the delaylimited capacity at low SNR in a simple form. More precisely, we establish that the delay-limited capacity scales linearly with the power constraint, for a given M < 1. Our framework highlights the benefit of fading at low SNR as the delay-limited capacity may outperform the AWGN capacity. For instance, for Rayleigh fading and with M = 3, the delay-limited capacity is 16% higher than the capacity of an AWGN channel.

  6. Low Power Silicon Germanium Electronics for Microwave Radiometers

    Science.gov (United States)

    Doiron, Terence A.; Krebs, Carolyn (Technical Monitor)

    2001-01-01

    Space-based radiometric observations of key hydrological parameters (e.g., soil moisture) at the spatial and temporal scales required in the post-2002 era face significant technological challenges. These measurements are based on relatively low frequency thermal microwave emission (at 1.4 GHz for soil moisture and salinity, 10 GHz and up for precipitation, and 19 and 37 GHz for snow). The long wavelengths at these frequencies coupled with the high spatial and radiometric resolutions required by the various global hydrology communities necessitate the use of very large apertures (e.g., greater than 20 m at 1.4 GHz) and highly integrated stable RF electronics on orbit. Radio-interferometric techniques such as Synthetic Thinned Array Radiometry (STAR), using silicon germanium (SiGe) low power radio frequency integrated circuits (RFIC), is one of the most promising technologies to enable very large non-rotating apertures in space. STAR instruments are composed of arrays of small antenna/receiving elements that are arranged so that the collecting area is smaller than an equivalent real aperture system, allowing very high packing densities for launch. A 20 meter aperture at L-band, for example, will require greater than 1000 of these receiving elements. SiGe RFIC's reduce power consumption enough to make an array like this possible in the power-limited environment of space flight. An overview of the state-of-the-art will be given, and current work in the area of SiGe radiometer development for soil moisture remote sensing will be discussed.

  7. Low Power Design for Future Wearable and Implantable Devices

    Directory of Open Access Journals (Sweden)

    Katrine Lundager

    2016-10-01

    Full Text Available With the fast progress in miniaturization of sensors and advances in micromachinery systems, a gate has been opened to the researchers to develop extremely small wearable/implantable microsystems for different applications. However, these devices are reaching not to a physical limit but a power limit, which is a critical limit for further miniaturization to develop smaller and smarter wearable/implantable devices (WIDs, especially for multi-task continuous computing purposes. Developing smaller and smarter devices with more functionality requires larger batteries, which are currently the main power provider for such devices. However, batteries have a fixed energy density, limited lifetime and chemical side effect plus the fact that the total size of the WID is dominated by the battery size. These issues make the design very challenging or even impossible. A promising solution is to design batteryless WIDs scavenging energy from human or environment including but not limited to temperature variations through thermoelectric generator (TEG devices, body movement through Piezoelectric devices, solar energy through miniature solar cells, radio-frequency (RF harvesting through antenna etc. However, the energy provided by each of these harvesting mechanisms is very limited and thus cannot be used for complex tasks. Therefore, a more comprehensive solution is the use of different harvesting mechanisms on a single platform providing enough energy for more complex tasks without the need of batteries. In addition to this, complex tasks can be done by designing Integrated Circuits (ICs, as the main core and the most power consuming component of any WID, in an extremely low power mode by lowering the supply voltage utilizing low-voltage design techniques. Having the ICs operational at very low voltages, will enable designing battery-less WIDs for complex tasks, which will be discussed in details throughout this paper. In this paper, a path towards battery

  8. CMOS Low Power Cell Library for Digital Design

    Directory of Open Access Journals (Sweden)

    Kanika Kaur

    2013-06-01

    Full Text Available Historically, VLSI designers have focused on increasing the speed and reducing the area of digital systems. However, the evolution of portable systems and advanced Deep Sub-Micron fabrication technologies have brought power dissipation as another critical design factor. Low power design reduces cooling cost and increases reliability especially for high density systems. Moreover, it reduces the weight and size of portable devices. The power dissipation in CMOS circuits consists of static and dynamic components. Since dynamic power is proportional to V2 dd and static power is proportional to Vdd, lowering the supply voltage and device dimensions, the transistor threshold voltage also has to be scaled down to achieve the required performance. In case of static power, the power is consumed during the steady state condition i.e when there are no input/output transitions. Static power has two sources: DC power and Leakage power. Consecutively to facilitate voltage scaling without disturbing the performance, threshold voltage has to be minimized. Furthermore it leads to better noise margins and helps to avoid the hot carrier effects in short channel devices. In this paper we have been proposed the new CMOS library for the complex digital design using scaling the supply voltage and device dimensions and also suggest the methods to control the leakage current to obtain the minimum power dissipation at optimum value of supply voltage and transistor threshold. In this paper CMOS Cell library has been implemented using TSMC (0.18um and TSMC (90nm technology using HEP2 tool of IC designing from Mentor Graphics for various analysis and simulations.

  9. An ultra-low-power image compressor for capsule endoscope

    Directory of Open Access Journals (Sweden)

    Weng Ping-Kuo

    2006-02-01

    Full Text Available Abstract Background Gastrointestinal (GI endoscopy has been popularly applied for the diagnosis of diseases of the alimentary canal including Crohn's Disease, Celiac disease and other malabsorption disorders, benign and malignant tumors of the small intestine, vascular disorders and medication related small bowel injury. The wireless capsule endoscope has been successfully utilized to diagnose diseases of the small intestine and alleviate the discomfort and pain of patients. However, the resolution of demosaicked image is still low, and some interesting spots may be unintentionally omitted. Especially, the images will be severely distorted when physicians zoom images in for detailed diagnosis. Increasing resolution may cause significant power consumption in RF transmitter; hence, image compression is necessary for saving the power dissipation of RF transmitter. To overcome this drawback, we have been developing a new capsule endoscope, called GICam. Methods We developed an ultra-low-power image compression processor for capsule endoscope or swallowable imaging capsules. In applications of capsule endoscopy, it is imperative to consider battery life/performance trade-offs. Applying state-of-the-art video compression techniques may significantly reduce the image bit rate by their high compression ratio, but they all require intensive computation and consume much battery power. There are many fast compression algorithms for reducing computation load; however, they may result in distortion of the original image, which is not good for use in the medical care. Thus, this paper will first simplify traditional video compression algorithms and propose a scalable compression architecture. Conclusion As the result, the developed video compressor only costs 31 K gates at 2 frames per second, consumes 14.92 mW, and reduces the video size by 75% at least.

  10. Low power interface IC's for electrostatic energy harvesting applications

    Science.gov (United States)

    Kempitiya, Asantha

    interest where the storage capacitor can be optimized to produce almost 70% of the ideal power taken as the power harvested with synchronous converters when neglecting the power consumption associated with synchronizing control circuitry. Theoretical predictions are confirmed by measurements on an asynchronous EHC implemented with a macro-scale electrostatic converter prototype. Based on the preceding analysis, the design of a novel ultra low power electrostatic integrated energy harvesting circuit is proposed for efficient harvesting of mechanical energy. The fundamental challenges of designing reliable low power sensing circuits for charge constrained electrostatic energy harvesters with capacity to self power its controller and driver stages are addressed. Experimental results are presented for a controller design implemented in AMI 0.7muM high voltage CMOS process using a macro-scale electrostatic converter prototype. The EHC produces 1.126muW for a power investment of 417nW with combined conduction and controller losses of 450nW which is a 20-30% improvement compared to prior art on electrostatic EHCs operating under charge constrain. Inherently dual plate variable capacitors harvest energy only during half of the mechanical cycle with the other half unutilized for energy conversion. To harvest mechanical energy over the complete mechanical vibration cycle, a low power energy harvesting circuit (EHC) that performs charge constrained synchronous energy conversion on a tri-plate variable capacitor for maximizing energy conversion is proposed. The tri-plate macro electrostatic generator with capacitor variation of 405pF to 1.15nF and 405pF to 1.07nF on two complementary adjacent capacitors is fabricated and used in the characterization of the designed EHC. The integrated circuit fabricated in AMI 0.7muM high voltage CMOS process, produces a total output power of 497nW to a 10muF reservoir capacitor from a 98Hz vibration signal. In summary, the thesis lays out the

  11. Design of Low Power Test Pattern Generator using Low Transition LFSR for high Fault Coverage Analysis

    Directory of Open Access Journals (Sweden)

    Chethan J

    2013-08-01

    Full Text Available A low power Test Pattern Generator (TPG designed by modifying Linear Feedback Shift Register is proposed to produce low power test vectors that are deployed on Circuit under Test (CUT to slenderize thedynamic power consumption by CUT. The technique involved in generating low power test patterns is performed by increasing the correlativity between the successive vectors; the ambiguity in increasing the similarity between consecutive vectors is resolved by reducing the number of bit flips between successive test patterns. Upon deploying the low power test patterns at the inputs of CUT, slenderizes the switching activities inside CUT that in turn reduces its dynamic power consumption. The resulted low power test vectors are deployed on CUT to obtain fault coverage. The experimental results demonstrate significant power reduction by low power TPG than compared to standard LFSR.

  12. Low power laser irradiation does not affect the generation of signals in a sensory receptor

    Energy Technology Data Exchange (ETDEWEB)

    Lundeberg, T.; Zhou, J.

    1989-01-01

    The effect of low power Helium-Neon (He-Ne) and Gallium-Arsenide (Ga-As) laser on the slowly adapting crustacean stretch receptor was studied. The results showed that low power laser irradiation did not affect the membrane potential of the stretch receptor. These results are discussed in relation to the use of low power laser irradiation on the skin overlaying acupuncture points in treatment of pain syndrome.

  13. Ultra-low power integrated circuit design circuits, systems, and applications

    CERN Document Server

    Li, Dongmei; Wang, Zhihua

    2014-01-01

    This book describes the design of CMOS circuits for ultra-low power consumption including analog, radio frequency (RF), and digital signal processing circuits (DSP). The book addresses issues from circuit and system design to production design, and applies the ultra-low power circuits described to systems for digital hearing aids and capsule endoscope devices. Provides a valuable introduction to ultra-low power circuit design, aimed at practicing design engineers; Describes all key building blocks of ultra-low power circuits, from a systems perspective; Applies circuits and systems described to real product examples such as hearing aids and capsule endoscopes.

  14. 47 CFR 74.785 - Low power TV digital data service pilot project.

    Science.gov (United States)

    2010-10-01

    ... 47 Telecommunication 4 2010-10-01 2010-10-01 false Low power TV digital data service pilot project. 74.785 Section 74.785 Telecommunication FEDERAL COMMUNICATIONS COMMISSION (CONTINUED) BROADCAST RADIO SERVICES EXPERIMENTAL RADIO, AUXILIARY, SPECIAL BROADCAST AND OTHER PROGRAM DISTRIBUTIONAL SERVICES Low Power TV, TV Translator, and TV...

  15. 76 FR 72849 - Digital Low Power Television, Television Translator, and Television Booster Stations and To Amend...

    Science.gov (United States)

    2011-11-28

    ... COMMISSION 47 CFR Parts 73 and 74 Digital Low Power Television, Television Translator, and Television Booster... Rules to Establish Rules for Digital Low Power Television, Television Translator, and Television Booster Stations and to Amend Rules for Digital Class A Television Stations, MB Docket No. 03-185; FCC 11-110,...

  16. 76 FR 44821 - Digital Low Power Television, Television Translator, and Television Booster Stations and To Amend...

    Science.gov (United States)

    2011-07-27

    ... No. 03-185; FCC 11-110] Digital Low Power Television, Television Translator, and Television Booster Stations and To Amend Rules for Digital Class A Television Stations AGENCY: Federal Communications... the low power television digital transition. Although Congress established a hard deadline of June...

  17. 75 FR 63766 - Digital Low Power Television, Television Translator, and Television Booster Stations and Digital...

    Science.gov (United States)

    2010-10-18

    ... COMMISSION 47 CFR Parts 73 and 74 Digital Low Power Television, Television Translator, and Television Booster Stations and Digital Class A Television Stations AGENCY: Federal Communications Commission. ACTION... that need to be resolved to complete the low power television station digital transition....

  18. 76 FR 11680 - Digital Low Power Television, Television Translator, and Television Booster Stations and Digital...

    Science.gov (United States)

    2011-03-03

    ... COMMISSION 47 CFR Parts 73 and 74 Digital Low Power Television, Television Translator, and Television Booster Stations and Digital Class A Television Stations AGENCY: Federal Communications Commission. ACTION: Final... 73 and 74 of the Commission's Rules to Establish Rules for Digital Low Power, Television...

  19. 47 CFR 74.795 - Digital low power TV and TV translator transmission system facilities.

    Science.gov (United States)

    2010-10-01

    ... translator transmission system facilities. (a) A digital low power TV or TV translator station shall operate... 47 Telecommunication 4 2010-10-01 2010-10-01 false Digital low power TV and TV translator transmission system facilities. 74.795 Section 74.795 Telecommunication FEDERAL COMMUNICATIONS...

  20. FPGA Based Low Power Router Design Using High Speed Transeceiver Logic IO Standard

    DEFF Research Database (Denmark)

    Thind, Vandana; Hussain, Dil muhammed Akbar

    2015-01-01

    and information. Router is main component of computer networks is an intelligent device uses to transfer data packets between various computer networks. Router must consume low power to perform its work in an efficient manner. To achieve the same the work has been done to make a FPGA based low power design using...

  1. High voltage generator circuit with low power and high efficiency applied in EEPROM

    Institute of Scientific and Technical Information of China (English)

    Liu Yan; Zhang Shilin; Zhao Yiqiang

    2012-01-01

    This paper presents a low power and high efficiency high voltage generator circuit embedded in electrically erasable programmable read-only memory (EEPROM).The low power is minimized by a capacitance divider circuit and a regulator circuit using the controlling clock switch technique.The high efficiency is dependent on the zero threshold voltage (Vth) MOSFET and the charge transfer switch (CTS) charge pump.The proposed high voltage generator circuit has been implemented in a 0.35μm EEPROM CMOS process.Measured results show that the proposed high voltage generator circuit has a low power consumption of about 150.48 μW and a higher pumping efficiency (83.3%) than previously reported circuits.This high voltage generator circuit can also be widely used in low-power flash devices due to its high efficiency and low power dissipation.

  2. Low-power laser therapy for carpal tunnel syndrome: effective optical power

    OpenAIRE

    Yan Chen; Cheng-qiang Zhao; Gang Ye; Can-dong Liu; Wen-dong Xu

    2016-01-01

    Low-power laser therapy has been used for the non-surgical treatment of mild to moderate carpal tunnel syndrome, although its efficacy has been a long-standing controversy. The laser parameters in low-power laser therapy are closely related to the laser effect on human tissue. To evaluate the efficacy of low-power laser therapy, laser parameters should be accurately measured and controlled, which has been ignored in previous clinical trials. Here, we report the measurement of the effective op...

  3. Ultra-Low Power Extreme Environment Capable Avionics System-on-a-Chip Project

    Data.gov (United States)

    National Aeronautics and Space Administration — Develop ultra-low-power, wide-temperature (-150° C to +250 ° C), digital System-on-a-Chip (SOC) ASIC technology in a high resolution, inherently rad-hard IBM...

  4. Low Power WiFi: a study on power consumption for Internet of Things

    OpenAIRE

    Amozarrain Perez, Ugaitz

    2015-01-01

    An analysis of a Low-Power WiFi devices and the feasibility of using such a device for Internet of Things applications, for wireless sensor networks more specifically. The device is analyzed in power consumption and performance.

  5. Miniaturized, Low Power Cryogenic Inlet System with Sampling Probes for Titan Project

    Data.gov (United States)

    National Aeronautics and Space Administration — Thorleaf Research, Inc. has demonstrated feasibility in Phase 1 and now proposes a Phase 2 effort to develop a miniature, low power cryogenic inlet system with...

  6. Low-Power Ultra-Wideband Radio and Radar Chip Project

    Data.gov (United States)

    National Aeronautics and Space Administration — Prime Research LC (PRLC), Virginia Tech (VT), and the University of Texas at Arlington (UTA) propose to develop an ultra-low power radio/radar based on a CMOS...

  7. Miniaturized Low-Power Piezo Microvalve for NanoSat and CubeSat Propulsion Project

    Data.gov (United States)

    National Aeronautics and Space Administration — In space propulsion applications, an increasingly unmet need is compact, low-power, precision flow regulating valves. Propulsion for increasingly small spacecraft is...

  8. High-Speed, Low-Power ADC for Digital Beam Forming (DBF) Systems Project

    Data.gov (United States)

    National Aeronautics and Space Administration — Ridgetop Group will design a high-speed, low-power silicon germanium (SiGe)-based, analog-to-digital converter (ADC) to be a key element for digital beam forming...

  9. High-Speed, Low-Power ADC for Digital Beam Forming (DBF) Systems Project

    Data.gov (United States)

    National Aeronautics and Space Administration — In Phase 1, Ridgetop Group designed a high-speed, yet low-power silicon germanium (SiGe)-based, analog-to-digital converter (ADC) to be a key element for digital...

  10. Miniaturized, Low Power Cryogenic Inlet System with Sampling Probes for Titan Project

    Data.gov (United States)

    National Aeronautics and Space Administration — Thorleaf Research, Inc. proposes to develop a miniature, low power cryogenic inlet system with sampling probes for Titan. This addresses a key technology gap for...

  11. Design of Low-Power CMOS OTA Using Bulk-Drive Technique

    OpenAIRE

    2015-01-01

    This paper presents the design of low power CMOS- OTA (operational transconductance amplifier) using bulk drive (BD) technique with broad band. This technique is used for design of low power circuits with broad band for high frequency users, for example communication systems, mobile communication and communication forming of medical electronics. OTA is the base of amplifier .It is a fundamental building part of analog systems. Recently analog designer has been paid to low voltage (LV),low pow...

  12. Low power consumption O-band VCSEL sources for upstream channels in PON systems

    DEFF Research Database (Denmark)

    Vegas Olmos, Juan José; Rodes Lopez, Roberto; Tafur Monroy, Idelfonso

    2012-01-01

    This paper presents an experimental validation of a low power optical network unit employing vertical-cavity surface-emitting lasers as upstream sources for passive optical networks with an increased power budget, enabling even larger splitting ratios.......This paper presents an experimental validation of a low power optical network unit employing vertical-cavity surface-emitting lasers as upstream sources for passive optical networks with an increased power budget, enabling even larger splitting ratios....

  13. A Comparative Analysis of Low Power and Area Efficient Digital Circuit Design

    OpenAIRE

    B. Dilli Kumar; Chandra Babu, A.; Prasad, V.

    2013-01-01

    VLSI design technology. If the power consumption is less, then the amount of power dissipation is also less. The power dissipation of a device can be reduced by using different low power techniques. In the present paper the performance of 4x1 multiplexer in different low power techniques was analyzed and its power dissipation in those techniques is compared with the conventional CMOS design. Each of these techniques has different advantages depending on their logic of operation. The simulatio...

  14. Low Power Floating Point Computation Sharing Multiplier for Signal Processing Applications

    OpenAIRE

    Sivanantham S; Jagannadha Naidu K; Balamurugan S; Bhuvana Phaneendra D

    2013-01-01

    Design of low power, higher performance digital signal processing elements are the major requirements in ultra deep sub-micron technology. This paper presents an IEEE-754 standard compatible single precision Floating-point Computation SHaring Multiplier (FCSHM) scheme suitable for low-power and high-speed signal processing applications. The floating-point multiplier used at thefilter taps effectively uses the computation re-use concept. Experimental results on a 10-tap programmable FIR filter...

  15. Review of the status of low power research reactors and considerations for its development

    Energy Technology Data Exchange (ETDEWEB)

    Lim, In Cheol; Wu, Sang Ik; Lee, Byung Chul; Ha, Jae Joo [KAERI, Daejeon (Korea, Republic of)

    2012-10-15

    At present, 232 research reactors in the world are in operation and two thirds of them have a power less than 1 MW. Many countries have used research reactors as the tools for educating and training students or engineers and for scientific service such as neutron activation analysis. As the introduction of a research reactor is considered a stepping stone for a nuclear power development program, many newcomers are considering having a low power research reactor. The IAEA has continued to provide forums for the exchange of information and experiences regarding low power research reactors. Considering these, the Agency is recently working on the preparation of a guide for the preparation of technical specification possibly for a member state to use when wanting to purchase a low power research reactor. In addition, ANS has stated that special consideration should be given to the continued national support to maintain and expand research and test reactor programs and to the efforts in identifying and addressing the future needs by working toward the development and deployment of next generation nuclear research and training facilities. Thus, more interest will be given to low power research reactors and its role as a facility for education and training. Considering these, the status of low power research reactors was reviewed, and some aspects to be considered in developing a low power research reactor were studied.

  16. 47 CFR 74.793 - Digital low power TV and TV translator station protection of broadcast stations.

    Science.gov (United States)

    2010-10-01

    ... 47 Telecommunication 4 2010-10-01 2010-10-01 false Digital low power TV and TV translator station... DISTRIBUTIONAL SERVICES Low Power TV, TV Translator, and TV Booster Stations § 74.793 Digital low power TV and TV... TV or TV translator station or change the facilities of an existing station will not be accepted...

  17. Low-power analog integrated circuits for wireless ECG acquisition systems.

    Science.gov (United States)

    Tsai, Tsung-Heng; Hong, Jia-Hua; Wang, Liang-Hung; Lee, Shuenn-Yuh

    2012-09-01

    This paper presents low-power analog ICs for wireless ECG acquisition systems. Considering the power-efficient communication in the body sensor network, the required low-power analog ICs are developed for a healthcare system through miniaturization and system integration. To acquire the ECG signal, a low-power analog front-end system, including an ECG signal acquisition board, an on-chip low-pass filter, and an on-chip successive-approximation analog-to-digital converter for portable ECG detection devices is presented. A quadrature CMOS voltage-controlled oscillator and a 2.4 GHz direct-conversion transmitter with a power amplifier and upconversion mixer are also developed to transmit the ECG signal through wireless communication. In the receiver, a 2.4 GHz fully integrated CMOS RF front end with a low-noise amplifier, differential power splitter, and quadrature mixer based on current-reused folded architecture is proposed. The circuits have been implemented to meet the specifications of the IEEE 802.15.4 2.4 GHz standard. The low-power ICs of the wireless ECG acquisition systems have been fabricated using a 0.18 μm Taiwan Semiconductor Manufacturing Company (TSMC) CMOS standard process. The measured results on the human body reveal that ECG signals can be acquired effectively by the proposed low-power analog front-end ICs.

  18. Design and implementation of a DSP with multi-level low power strategies for cochlear implants

    Institute of Scientific and Technical Information of China (English)

    Mai Songping; Zhang Chun; Chao Jun; Wang Zhihua

    2009-01-01

    This paper presents the design and implementation of a low power digital signal processor (THUCIDSP-1) targeting at application for cochlear implants. Multi-level low power strategies including algorithm optimization, operand isolation, clock gating and memory partitioning are adopted in the processor design to reduce the power consumption. Experimental results show that the complexity of the Continuous Interleaved Sampling (CIS) algorithm is reduced by more than 80% and the power dissipation of the hardware alone is reduced by about 25% with the low power methods. The THUCIDSP-1 prototype, fabricated in 0.18-μm standard CMOS process, consumes only 1.91 mW when executing the CIS algorithm at 3 MHz.

  19. Design and Implementation of 16-Bit Magnitude Comparator Using Efficient Low Power High Performance Full Adders

    Directory of Open Access Journals (Sweden)

    Ajaykumar S Kulkarni

    2014-08-01

    Full Text Available In VLSI applications, area, delay and power are the important factors which must be taken into account in the design of a fast adder [1]. The paper attempts to examine the features of certain adder circuits which promise superior performance compared to existing circuits. The advantages of these circuits are low-power consumption, a high degree of regularity and simplicity. In this paper, the design of a 16-bit comparator is proposed. Magnitude comparison is one of the basic functions used for sorting in microprocessor, digital signal processing, so a high performance, effective magnitude comparator is required. The main objective of this paper is to provide new low power, area solution for Very Large Scale Integration (VLSI designers using low power high performance efficient full adders.

  20. Design Low Power Encoder for Threshold Inverter Quantization Based Flash ADC Converter

    Directory of Open Access Journals (Sweden)

    Mamta Gurjar

    2013-04-01

    Full Text Available Analog-to-Digital converters are the useful component in signal processing and communication system. In the digital signal processing low power and low voltage becomes a considerable component in that are challenging for designing high speed devices and converters. This paper describes the ultra high speed ADC design with a fat tree encoder that became highly suitable and accurate. Speed becomes the important part that enhanced by component of 2 guidelines of fat tree encoder. This paper also describes the implementation of TIQ based comparator that exhibits low power consumption as compared to other comparator based design. A 3 bit ADC has been designed and simulated in CMOS 45 nm technology with input voltage range of 0 V to 0.7 V. The simulated and analysed results shows low power and a high speed performance for optimised ADC

  1. Design of Transmission Gate VCO and Dynamic PFD for Low Power CMOS PLL

    Science.gov (United States)

    Yuan, S. C.

    2008-11-01

    To realize the high speed and low power CMOS PLL(Phase Locked Loop), the new circuits of VCO and PFD is designed in transistor level. In the VCO, the high speed and low power is realized using transmission-gate(TG) with an adaptive delay cell and low supply sensitivity. This delay cell has a built-in compensation circuit that senses and corrects the delay variation caused by supply fluctuation. And in the PFD, low power and small chip area is realized with the dynamic inverter. A fully CMOS PLL using these components has been designed based 0.6μm CMOS technology and its SPICE model. SPICE simulation results show that at 2.5V supply voltage, the designed PLL can operate over 1000MHz and dissipate power less than 50mW.

  2. A low-power RFID integrated circuits for intelligent healthcare systems.

    Science.gov (United States)

    Lee, Shuenn-Yuh; Wang, Liang-Hung; Fang, Qiang

    2010-11-01

    This paper presents low-power radio-frequency identification (RFID) technology for intelligent healthcare systems. With attention to power-efficient communication in the body sensor network, RF power transfer was estimated and the required low-power ICs, which are important in the development of a healthcare system with miniaturization and system integration, are discussed based on the RFID platform. To analyze the power transformation, this paper adopts a 915-MHz industrial, scientific, and medical RF with a radiation power of 70 mW to estimate the power loss under the 1-m communication distance between an RFID reader (bioinformation node) and a transponder (biosignal acquisition nodes). The low-power ICs of the transponder will be implemented in the TSMC 0.18-μm CMOS process. The simulation result reveals that the transponder's IC can fit in with the link budget of the UHF RFID system.

  3. An ECG Compressed Sensing Method of Low Power Body Area Network

    Directory of Open Access Journals (Sweden)

    Jizhong Liu

    2013-07-01

    Full Text Available Aimed at low power problem in body area network, an ECG compressed sensing method of low power body area network based on the compressed sensing theory was proposed. Random binary matrices were used as the sensing matrix to measure ECG signals on the sensor nodes. After measured value is transmitted to remote monitoring center, ECG signal sparse representation under the discrete cosine transform and block sparse Bayesian learning reconstruction algorithm is used to reconstruct the ECG signals. The simulation results show that the 30% of overall signal can get reconstruction signal which’s SNR is more than 60dB, each numbers in each rank of sensing matrix can be controlled below 5, which reduces the power of sensor node sampling, calculation and transmission. The method has the advantages of low power, high accuracy of signal reconstruction and easy to hardware implementation.  

  4. Design of Low Power Multiplier with Energy Efficient Full Adder Using DPTAAL

    Directory of Open Access Journals (Sweden)

    A. Kishore Kumar

    2013-01-01

    Full Text Available Asynchronous adiabatic logic (AAL is a novel lowpower design technique which combines the energy saving benefits of asynchronous systems with adiabatic benefits. In this paper, energy efficient full adder using double pass transistor with asynchronous adiabatic logic (DPTAAL is used to design a low power multiplier. Asynchronous adiabatic circuits are very low power circuits to preserve energy for reuse, which reduces the amount of energy drawn directly from the power supply. In this work, an 8×8 multiplier using DPTAAL is designed and simulated, which exhibits low power and reliable logical operations. To improve the circuit performance at reduced voltage level, double pass transistor logic (DPL is introduced. The power results of the proposed multiplier design are compared with the conventional CMOS implementation. Simulation results show significant improvement in power for clock rates ranging from 100 MHz to 300 MHz.

  5. Low Power Design with High-Level Power Estimation and Power-Aware Synthesis

    CERN Document Server

    Ahuja, Sumit; Shukla, Sandeep Kumar

    2012-01-01

    Low-power ASIC/FPGA based designs are important due to the need for extended battery life, reduced form factor, and lower packaging and cooling costs for electronic devices. These products require fast turnaround time because of the increasing demand for handheld electronic devices such as cell-phones, PDAs and high performance machines for data centers. To achieve short time to market, design flows must facilitate a much shortened time-to-product requirement. High-level modeling, architectural exploration and direct synthesis of design from high level description enable this design process. This book presents novel research techniques, algorithms,methodologies and experimental results for high level power estimation and power aware high-level synthesis. Readers will learn to apply such techniques to enable design flows resulting in shorter time to market and successful low power ASIC/FPGA design. Integrates power estimation and reduction for high level synthesis, with low-power, high-level design; Shows spec...

  6. Adaptive low-power listening MAC protocol based on transmission rates.

    Science.gov (United States)

    Hwang, Kwang-il; Yi, Gangman

    2014-01-01

    Even though existing low-power listening (LPL) protocols have enabled ultra-low-power operation in wireless sensor networks (WSN), they do not address trade-off between energy and delay, since they focused only on energy aspect. However, in recent years, a growing interest in various WSN applications is requiring new design factors, such as minimum delay and higher reliability, as well as energy efficiency. Therefore, in this paper we propose a novel sensor multiple access control (MAC) protocol, transmission rate based adaptive low-power listening MAC protocol (TRA-MAC), which is a kind of preamble-based LPL but is capable of controlling preamble sensing cycle adaptively to transmission rates. Through experiments, it is demonstrated that TRA-MAC enables LPL cycle (LC) and preamble transmission length to adapt dynamically to varying transmission rates, compensating trade-off between energy and response time.

  7. SEMICONDUCTOR INTEGRATED CIRCUITS: A low power fast-settling frequency-presetting PLL frequency synthesizer

    Science.gov (United States)

    Zhiqing, Geng; Xiaozhou, Yan; Wenfeng, Lou; Peng, Feng; Nanjian, Wu

    2010-08-01

    This work presents the design and implementation of a 2.4 GHz low power fast-settling frequency-presetting PLL frequency synthesizer in the 0.18 μm CMOS process. A low power mixed-signal LC VCO, a low power dual mode prescaler and a digital processor with non-volatile memory are developed to greatly reduce the power consumption and the setting time. The digital processor can automatically calibrate the presetting frequency and accurately preset the frequency of the VCO under process variations. The experimental results demonstrate that the power consumption of the synthesizer is about 4 mA @ 1.8 V and that the typical setting time of the synthesizer is less than 3 μs.

  8. A low power, on demand electrothermal valve for wireless drug delivery applications.

    Science.gov (United States)

    Li, Po-Ying; Givrad, Tina K; Sheybani, Roya; Holschneider, Daniel P; Maarek, Jean-Michel I; Meng, Ellis

    2010-01-01

    We present a low power, on demand Parylene MEMS electrothermal valve. A novel Omega-shaped thermal resistive element requires low power (approximately mW) and enables rapid valve opening (approximately ms). Using both finite element analysis and valve opening experiments, a robust resistive element design for improved valve opening performance in water was obtained. In addition, a thermistor, as an inrush current limiter, was added into the valve circuit to provide variable current ramping. Wireless activation of the valve using RF inductive power transfer was demonstrated.

  9. A Low Power down Conversion CMOS Gilbert Mixer for Wireless Communications

    Directory of Open Access Journals (Sweden)

    Manoj Kumar Pandram,

    2014-07-01

    Full Text Available In this paper a design of low power 2.4GHz (RF down conversion Gilbert Cell mixer, implemented in 0.18μm CMOS technology with 1.8V supply voltage is presented. The obtained result shows a conversion gain equal to 6.7dB and third order Input intercept point -1db, power consumption of 3.86mW at 1.8V supply voltage. The 50Ω matched impedance condition is applicable. Result shows a good potential of this CMOS mixer and justify its use for low-power wireless communications.

  10. A Low Power Linear Phase Digital FIR Filter for Wearable ECG Devices.

    Science.gov (United States)

    Lian, Yong; Yu, Jianghong

    2005-01-01

    In this paper we present a low power linear phase digital FIR filter which is a part of an ECG-on-Chip. The ECG-on-Chip can be embedded into clothing to acquire the electrocardiogram (ECG) signal and send a warning message to a mobile phone or PDA if an abnormal ECG is detected. The proposed new filter structure significantly reduces the arithmetic operations for each sample which in turn lowers the power consumption. The filter is developed based on the interpolated finite impulse filter technique and is very attractive for a low cost and low power VLSI implementation.

  11. Analysis and design of a low-power low-noise CMOS phase-locked loop

    OpenAIRE

    Zhang, Cheng

    2012-01-01

    This thesis covers the analysis, design and simulation of a low-power low-noise CMOS Phase-Locked Loop (PLL). Starting with the PLL basics, this thesis discussed the PLL loop dynamics and behavioral modeling. In this thesis, the detailed design and implementation of individual building blocks of the low-power low-noise PLL have been presented. In order to improve the PLL performance, several novel architectural solutions has been proposed. To reduce the effect of blind-zone and extend the det...

  12. A low-power multi-modal body sensor network with application to epileptic seizure monitoring.

    Science.gov (United States)

    Altini, Marco; Del Din, Silvia; Patel, Shyamal; Schachter, Steven; Penders, Julien; Bonato, Paolo

    2011-01-01

    Monitoring patients' physiological signals during their daily activities in the home environment is one of the challenge of the health care. New ultra-low-power wireless technologies could help to achieve this goal. In this paper we present a low-power, multi-modal, wearable sensor platform for the simultaneous recording of activity and physiological data. First we provide a description of the wearable sensor platform, and its characteristics with respect to power consumption. Second we present the preliminary results of the comparison between our sensors and a reference system, on healthy subjects, to test the reliability of the detected physiological (electrocardiogram and respiration) and electromyography signals.

  13. Low Power Floating Point Computation Sharing Multiplier for Signal Processing Applications

    Directory of Open Access Journals (Sweden)

    Sivanantham S

    2013-04-01

    Full Text Available Design of low power, higher performance digital signal processing elements are the major requirements in ultra deep sub-micron technology. This paper presents an IEEE-754 standard compatible single precision Floating-point Computation SHaring Multiplier (FCSHM scheme suitable for low-power and high-speed signal processing applications. The floating-point multiplier used at thefilter taps effectively uses the computation re-use concept. Experimental results on a 10-tap programmable FIR filter show that the proposed multiplier scheme can provide a power reduction of 39.7% and significant improvements in the performance compared to conventional floating-point carry save array multiplier implementations.

  14. Semidigital PLL Design for Low-Cost Low-Power Clock Generation

    Directory of Open Access Journals (Sweden)

    Ni Xu

    2011-01-01

    Full Text Available This paper describes recent semidigital architectures of the phase-locked loop (PLL systems for low-cost low-power clock generation. With the absence of the time-to-digital converter (TDC, the semi-digital PLL (SDPLL enables low-power linear phase detection and does not necessarily require advanced CMOS technology while maintaining a technology scalability feature. Two design examples in 0.18 μm CMOS and 65 nm CMOS are presented with hardware and simulation results, respectively.

  15. [Design of portable 12-lead digital ECG with low power consumption].

    Science.gov (United States)

    Sheng, Chuanguang; Yang, Cuiwei; Wu, Xiaomei; Wang, Yuanyuan; Qin, Yajie

    2013-11-01

    The design of portable and low power consumption 12-lead ECG is based on the digital signal processor TMS320C5515 and the analog front end ADS1298. The ADS1298 collects the ECG signals and deliver them to TMS320C5515. The preprocessed ECG signals are displayed real-time on a LCD and can be stored without compression for a long time. The ECG signals can also be sent to an up computer by a USB connector so that ECG data can be analyzed offline. The system has small volume, high precision and low power consumption.

  16. Optimizing efficiency on conventional transformer based low power AC/DC standby power supplies

    DEFF Research Database (Denmark)

    Nielsen, Nils

    2004-01-01

    This article describes the research results for simple and cheap methods to reduce the idle- and load-losses in very low power conventional transformer based power supplies intended for standby usage. In this case "very low power" means 50 Hz/230 V-AC to 5 V-DC@1 W. The efficiency is measured...... on two common power supply topologies designed for this power level. The two described topologies uses either a series (or linear) or a buck regulation approach. Common to the test power supplies is they either are using a standard cheap off-the-shelf transformer, or one, which are loss optimized by very...

  17. Low cost low power 24 GHz FMCW radar transceiver for indoor presence detection

    NARCIS (Netherlands)

    Suijker, E.M.; Bolt, R.J.; Wanum, M. van; Heijningen, M. van; Maas, A.P.M.; Vliet, F.E. van

    2014-01-01

    In this paper a first time right 24 GHz FMCW radar transceiver is presented. The MMIC has a low power consumption of 86 mW and an output power of -10 dBm. Due to the integrated IF amplifier, the conversion gain of the receiver is 51 dB and the base band signals are directly processed with an ADC. Th

  18. Low-power micro-scale CMOS-compatible silicon sensor on a suspended membrane.

    NARCIS (Netherlands)

    Kovalgin, A.Y.; Holleman, J.; Iordache, G.; Jenneboer, A.J.S.M.; Falke, F.; Zieren, V.; Goossens, M.J.

    2006-01-01

    In this paper we describe a new, simple and cheap silicon device operating at high temperature at a very low power of a few mW. The essential part of the device is a nano-size conductive link 10-100 nm in size (the so-called antifuse) formed in between two poly-silicon electrodes separated by a thin

  19. Low-Power, Antifuse-Based Silicon Chemical Sensor on a Suspended Membrane

    NARCIS (Netherlands)

    Kovalgin, A.Y.; Holleman, J.; Iordache, G.; Jenneboer, T.; Falke, F.; Zieren, V.; Goossens, M.J.

    2006-01-01

    In this paper we describe a new, simple, and cheap silicon sensor operating at a high temperature of about 1000 K and consuming a very low power of a few milliwatts. We developed a silicon-processing compatible, simple, and low-cost method for processing thermally isolated suspended membranes. This

  20. A heterogeneous multi-core platform for low power signal processing in systems-on-chip

    DEFF Research Database (Denmark)

    Paker, Ozgun; Sparsø, Jens; Haandbæk, Niels;

    2002-01-01

    This paper presents a low-power and programmable DSP architecture - a heterogeneous multiprocessor platform consisting of standard CPU/DSP cores, and a set of simple instruction set processors called mini-cores each optimized for a particular class of algorithm (FIR, IIR, LMS, etc.). Communication...

  1. A Case Study of Nanoscale FPGA Programmable Switches with Low Power

    Directory of Open Access Journals (Sweden)

    V.Elamaran

    2013-04-01

    Full Text Available The trend in VLSI and system design is moving away from high speed to low power due to the rapid growth in the portable consumer electronics market. The technology evolution of deep submicron (DSM will be able to manage the needs and demands of future computing world. A rapid growth of future computing have led to challenges of very deep submicron (DSM regime. Here, the leakage power plays a major contributor to the total power dissipation involved in the circuit as the threshold voltage becomes small while we reduce the operating supply voltage. We present some techniques to reduce the power dissipation involved while interconnecting logic blocks in the Field Programmable Gate Arrays (FPGAs. The interconnections or connectivity among logic blocks are done by routing switches. We use pass-transistor logic, transmission logic and multiplexers for the construction of these routing switches. We present a technique which has both sleep mode in which the leakage power is reduced and low-power mode in which the dynamic power is reduced. These models are built by using Electronic Design Automation (EDA tools like DSCH (Digital Schematic and Microwind layout tools using BSIM4 MOSFET model in 60 nm technology. Results show that the pass-transistor approach is having low power consumption . The leakage and dynamic power are also reduced by the circuit which has the programmability option to change sleep mode and low-power mode.

  2. Suitability of tile-based rendering for low-power 3d graphics accelerators

    NARCIS (Netherlands)

    Antochi, I.

    2007-01-01

    In this dissertation, we address low-power high performance 3D graphics accelerator architectures. The purpose of these accelerators is to relieve the burden of graphical computations from the main processor and also to achieve a better energy efficiency than can be achieved by executing these compu

  3. 77 FR 10576 - Methodology for Low Power/Shutdown Fire PRA

    Science.gov (United States)

    2012-02-22

    ... NUREG/CR; extension for public comment period. SUMMARY: On December 29, 2011 (76 FR 81998), the U.S... Draft NUREG/CR-7114, Revision 0, ``Methodology for Low Power/Shutdown Fire PRA.'' In response to request...-4209, (301) 415-4737, or by email to pdr.resource@nrc.gov . The draft NUREG is available...

  4. A low power biomedical signal processor ASIC based on hardware software codesign.

    Science.gov (United States)

    Nie, Z D; Wang, L; Chen, W G; Zhang, T; Zhang, Y T

    2009-01-01

    A low power biomedical digital signal processor ASIC based on hardware and software codesign methodology was presented in this paper. The codesign methodology was used to achieve higher system performance and design flexibility. The hardware implementation included a low power 32bit RISC CPU ARM7TDMI, a low power AHB-compatible bus, and a scalable digital co-processor that was optimized for low power Fast Fourier Transform (FFT) calculations. The co-processor could be scaled for 8-point, 16-point and 32-point FFTs, taking approximate 50, 100 and 150 clock circles, respectively. The complete design was intensively simulated using ARM DSM model and was emulated by ARM Versatile platform, before conducted to silicon. The multi-million-gate ASIC was fabricated using SMIC 0.18 microm mixed-signal CMOS 1P6M technology. The die area measures 5,000 microm x 2,350 microm. The power consumption was approximately 3.6 mW at 1.8 V power supply and 1 MHz clock rate. The power consumption for FFT calculations was less than 1.5 % comparing with the conventional embedded software-based solution.

  5. Design considerations on ultra-low-power wireless transmitters for wearable medical devices.

    Science.gov (United States)

    Manstretta, Danilo

    2010-01-01

    A wireless transmitter for wearable bio-sensing applications must fulfill very specialized requirements. It has been estimated that for truly wearable systems it must operate with an average power consumption of less than 140 microW. The alternatives, pitfalls, and realistic performance of robust, low power signal transmission will be addressed.

  6. Implementation of High Performance Fir Filter Using Low Power Multiplier and Adder

    Directory of Open Access Journals (Sweden)

    Sweety Kashyap,

    2014-01-01

    Full Text Available The ever increasing growth in laptop and portable systems in cellular networks has intensified the research efforts in low power microelectronics. Now a day, there are many portable applications requiring low power and high throughput than ever before. Thus, low power system design has become a significant performance goal. So this paper is face with more constraints: high speed, high throughput, and at the same time, consumes as minimal power as possible. The Finite Impulse Response (FIR Filter is the important component for designing an efficient digital signal processing system. So, in this paper author trying, a FIR filter is constructing, which is efficient not only in terms of power and speed but also in terms of delay. When consider the elementary structure of an FIR filter, it is found that it is a combination of multipliers and delays, which in turn are the combination of adders. . This paper presents an efficient implementation and analysis for performance evaluation of multiplier and adder to minimize the consumption of energy during multiplication and addition methodology to improve the performance by compares different type of Multipliers and adder, respectively. By using, power comparison result of adders and multiplier, choice low power adder and multiplier to implementation of high performance FIR filter.

  7. Low power and self-reconfigurable WBAN controller for continuous bio-signal monitoring system

    NARCIS (Netherlands)

    Lee, S.; Yoo, H.J.

    2013-01-01

    The WBAN controller with Branched Bus (BB) topology and Continuous Data Transmission (CDT) protocol with low power consumption and self- reconfigurability is proposed for wearable healthcare applications. The BB topology and CDT protocol is a combination of conventional Bus and Star topology and a v

  8. Low Power Penalty Operation of a Wide Input Dynamic Range Cross-Phase Modulation Wavelength Converter

    Institute of Scientific and Technical Information of China (English)

    Jun; Endo; Akira; Ohki; Rieko; Sato; Toshio; Ito; Yuichi; Tohmori; Yasuhiro; Suzuki

    2003-01-01

    We successfully demonstrated low power penalty operation of a cross-phase modulated (XPM) wavelength converter using a semiconductor optical amplifier (SOA) power equalizer. We also clarified the SOA equalizing level for more adaptive wavelength conversion and achieved a power penalty of less than 1 dB over the wide input dynamic range of 15 dB.

  9. An ultra low-voltage, low-power baseband-processor for UHF RFID tag

    Institute of Scientific and Technical Information of China (English)

    Yan HE; Jianyun HU; Hao MIN

    2008-01-01

    A novel ultra low-voltage, low-power baseband-processor for UHF radio frequency identification (RFID) tag is presented here. The baseband-processor is compa-tible with the EPCTM class-1 generation-2 (C1G2) UHF RFID protocol, and fits the requirements of ultra low-power of passive tags. Based on the analysis of the special power consumption of the tag, a new architecture is proposed. A novel scheme for generating pseudo-random numbers as well as a new method of partial-decoding is developed. Besides, other low-power techniques are also adopted for the special baseband-processor which imple-ments complex functions, such as encoding/coding, anti-collision and authorization scheme, and reading/writing operation to EEPROM. The chip was fabricated in 0.35 μm 1P3M standard CMOS process. Experimental results show that it achieves low power operation of 3.15 μW @ 1.5 V with the core area of 1.1 mm× 0.8 mm.

  10. 76 FR 81998 - Methodology for Low Power/Shutdown Fire PRA

    Science.gov (United States)

    2011-12-29

    ...) 492-3446. FOR FURTHER INFORMATION CONTACT: Felix E. Gonzalez, Division of Risk Analysis, Office of...: (301) 251- 7596, email: Felix.Gonzalez@nrc.gov or Hugh W. Woods, Division of Risk Analysis, Office of... quantitatively analyzing fire risk in commercial nuclear power plants during low power operation and...

  11. Achievable rate of spectrum sharing cognitive radio systems over fading channels at low-power regime

    KAUST Repository

    Sboui, Lokman

    2014-11-01

    We study the achievable rate of cognitive radio (CR) spectrum sharing systems at the low-power regime for general fading channels and then for Nakagami fading. We formally define the low-power regime and present the corresponding closed-form expressions of the achievable rate lower bound under various types of interference and/or power constraints, depending on the available channel state information of the cross link (CL) between the secondary-user transmitter and the primary-user receiver. We explicitly characterize two regimes where either the interference constraint or the power constraint dictates the optimal power profile. Our framework also highlights the effects of different fading parameters on the secondary link (SL) ergodic achievable rate. We also study more realistic scenarios when there is either 1-bit quantized channel feedback from the CL alone or 2-bit feedback from both the CL and the SL and propose simple power control schemes and show that these schemes achieve the previously achieved rate at the low-power regime. Interestingly, we show that the low-power regime analysis provides a specific insight into the maximum achievable rate behavior of CR that has not been reported by previous studies.

  12. Design of nodes for embedded and ultra low-power wireless sensor networks

    Science.gov (United States)

    Xu, Jun; You, Bo; Cui, Juan; Ma, Jing; Li, Xin

    2008-10-01

    Sensor network integrates sensor technology, MEMS (Micro-Electro-Mechanical system) technology, embedded computing, wireless communication technology and distributed information management technology. It is of great value to use it where human is quite difficult to reach. Power consumption and size are the most important consideration when nodes are designed for distributed WSN (wireless sensor networks). Consequently, it is of great importance to decrease the size of a node, reduce its power consumption and extend its life in network. WSN nodes have been designed using JN5121-Z01-M01 module produced by jennic company and IEEE 802.15.4/ZigBee technology. Its new features include support for CPU sleep modes and a long-term ultra low power sleep mode for the entire node. In low power configuration the node resembles existing small low power nodes. An embedded temperature sensor node has been developed to verify and explore our architecture. The experiment results indicate that the WSN has the characteristic of high reliability, good stability and ultra low power consumption.

  13. 47 CFR 73.3521 - Mutually exclusive applications for low power television, television translators and television...

    Science.gov (United States)

    2010-10-01

    ... television, television translators and television booster stations. 73.3521 Section 73.3521 Telecommunication... Applicable to All Broadcast Stations § 73.3521 Mutually exclusive applications for low power television, television translators and television booster stations. When there is a pending application for a new...

  14. Ultra low-power biomedical signal processing: an analog wavelet filter approach for pacemakers

    NARCIS (Netherlands)

    Pavlík Haddad, S.A.

    2006-01-01

    The purpose of this thesis is to describe novel signal processing methodologies and analog integrated circuit techniques for low-power biomedical systems. Physiological signals, such as the electrocardiogram (ECG), the electroencephalogram (EEG) and the electromyogram (EMG) are mostly non-stationary

  15. Adiabatic superconducting cells for ultra-low-power artificial neural networks

    Directory of Open Access Journals (Sweden)

    Andrey E. Schegolev

    2016-10-01

    Full Text Available We propose the concept of using superconducting quantum interferometers for the implementation of neural network algorithms with extremely low power dissipation. These adiabatic elements are Josephson cells with sigmoid- and Gaussian-like activation functions. We optimize their parameters for application in three-layer perceptron and radial basis function networks.

  16. Adiabatic superconducting cells for ultra-low-power artificial neural networks.

    Science.gov (United States)

    Schegolev, Andrey E; Klenov, Nikolay V; Soloviev, Igor I; Tereshonok, Maxim V

    2016-01-01

    We propose the concept of using superconducting quantum interferometers for the implementation of neural network algorithms with extremely low power dissipation. These adiabatic elements are Josephson cells with sigmoid- and Gaussian-like activation functions. We optimize their parameters for application in three-layer perceptron and radial basis function networks.

  17. Low power silicon-based thermal sensors and actuators for chemical applications

    NARCIS (Netherlands)

    Vereshchagina, Elizaveta

    2011-01-01

    In the Hot Silicon project low and ultra-low-power Si-based hot surface devices have been developed, i.e. thermal sensors and actuators, for application in catalytic gas micro sensors, micro- and nano- calorimeters. This work include several scientific and technological aspects: • Design and fabrica

  18. Low-power laser therapy for carpal tunnel syndrome:effective optical power

    Institute of Scientific and Technical Information of China (English)

    Yan Chen; Cheng-qiang Zhao; Gang Ye; Can-dong Liu; Wen-dong Xu

    2016-01-01

    Low-power laser therapy has been used for the non-surgical treatment of mild to moderate carpal tunnel syndrome, although its efifca-cy has been a long-standing controversy. The laser parameters in low-power laser therapy are closely related to the laser effect on human tissue. To evaluate the efifcacy of low-power laser therapy, laser parameters should be accurately measured and controlled, which has been ignored in previous clinical trials. Here, we report the measurement of the effective optical power of low-power laser therapy for carpal tunnel syndrome. By monitoring the backside relfection and scattering laser power from human skin at the wrist, the effective laser power can be inferred. Using clinical measurements from 30 cases, we found that the effective laser power differed signiifcantly among cases, with the measured laser relfection coefifcient ranging from 1.8%to 54%. The relfection coefifcient for 36.7%of these 30 cases was in the range of 10–20%, but for 16.7%of cases, it was higher than 40%. Consequently, monitoring the effective optical power during laser irradiation is necessary for the laser therapy of carpal tunnel syndrome.

  19. Low power proximity electronics for dust analysers based on light scattering

    Science.gov (United States)

    Molfese, C.; Esposito, F.; Cortecchia, F.; Cozzolino, F.

    2012-04-01

    The present paper focuses on the development of an optimized version of the Proximity Electronics (PE) for dust analysers based on static light scattering. This kind of instruments, aimed to the systematic measurement of the size of dust grains in Martian atmosphere, was developed by the Cosmic Physics and Planetology Group at the INAF Astronomical Observatory of Capodimonte (OAC) and University Parthenope (LFC group), in Naples, Italy. One of these instruments, the MEDUSA Experiment, was selected for the Humboldt Payload of the ExoMars mission, the first mission to Mars of the ESA Aurora Programme. Thereafter, this mission was revised because of increasing costs and lack of funds and the MEDUSA experiment has been completely re-engineered to meet more demanding constraints of mass and power consumption. The dust analyser under development is named MicroMED, as it is a lighter and more compact version of MEDUSA. MicroMED is provided with an Optical System (OS) based on the same concept of the one present in MEDUSA, but with a low power PE and low power laser source. This paper reports the features and the tests results of three versions of low power PE developed for MicroMED, and also compares two basic approaches, one based on a linear amplifier, derived from the solution implemented in two different MEDUSA breadboards (B/Bs), and the other one based on a logarithmic amplifier, with better performance in terms of compactness and low power consumption.

  20. Analog IC techniques for low-voltage low-power electronics

    NARCIS (Netherlands)

    Serdijn, W.A.; Verhoeven, C.J.M.; Van Roermund, A.H.M.

    1995-01-01

    Analog IC Techniques lor Low-Voltage Low Power Electronics addresses many very important, but recent, techniques which enable electronics to operate at a low supply voltage and consume a minimum amount of power. Apart from investigations at the device, circuit and system levels, the book provides a

  1. Single-Phase Hybrid Switched Reluctance Motor for Low-Power Low-Cost Applications

    DEFF Research Database (Denmark)

    Lu, Kaiyuan; Rasmussen, Peter Omand; Jakobsen, Uffe

    2011-01-01

    This paper presents a new single-phase, Hybrid Switched Reluctance (HSR) motor for low-cost, low-power, pump or fan drive systems. Its single-phase configuration allows use of a simple converter to reduce the system cost. Cheap ferrite magnets are used and arranged in a special flux concentration...

  2. Water energy resources of the United States with emphasis on low head/low power resources

    Energy Technology Data Exchange (ETDEWEB)

    Hall, Douglas G. [Idaho National Lab. (INL), Idaho Falls, ID (United States). Idaho National Engineering and Environmental Lab. (INEEL); Cherry, Shane J. [Idaho National Lab. (INL), Idaho Falls, ID (United States). Idaho National Engineering and Environmental Lab. (INEEL); Reeves, Kelly S. [Idaho National Lab. (INL), Idaho Falls, ID (United States). Idaho National Engineering and Environmental Lab. (INEEL); Lee, Randy D. [Idaho National Lab. (INL), Idaho Falls, ID (United States). Idaho National Engineering and Environmental Lab. (INEEL); Carroll, Gregory R. [Idaho National Lab. (INL), Idaho Falls, ID (United States). Idaho National Engineering and Environmental Lab. (INEEL); Sommers, Garold L. [Idaho National Lab. (INL), Idaho Falls, ID (United States). Idaho National Engineering and Environmental Lab. (INEEL); Verdin, Kristine L. [Idaho National Lab. (INL), Idaho Falls, ID (United States). Idaho National Engineering and Environmental Lab. (INEEL)

    2004-04-01

    Analytical assessments of the water energy resources in the 20 hydrologic regions of the United States were performed using state-of-the-art digital elevation models and geographic information system tools. The principal focus of the study was on low head (less than 30 ft)/low power (less than 1 MW) resources in each region. The assessments were made by estimating the power potential of all the stream segments in a region, which averaged 2 miles in length. These calculations were performed using hydrography and hydraulic heads that were obtained from the U.S. Geological Survey’s Elevation Derivatives for National Applications dataset and stream flow predictions from a regression equation or equations developed specifically for the region. Stream segments excluded from development and developed hydropower were accounted for to produce an estimate of total available power potential. The total available power potential was subdivided into high power (1 MW or more), high head (30 ft or more)/low power, and low head/low power total potentials. The low head/low power potential was further divided to obtain the fractions of this potential corresponding to the operating envelopes of three classes of hydropower technologies: conventional turbines, unconventional systems, and microhydro (less than 100 kW). Summing information for all the regions provided total power potential in various power classes for the entire United States. Distribution maps show the location and concentrations of the various classes of low power potential. No aspect of the feasibility of developing these potential resources was evaluated. Results for each of the 20 hydrologic regions are presented in Appendix A, and similar presentations for each of the 50 states are made in Appendix B.

  3. Designing BEE: A Hardware Emulation Engine for Signal Processing in Low-Power Wireless Applications

    Directory of Open Access Journals (Sweden)

    Chang Chen

    2003-01-01

    Full Text Available This paper describes the design of a large-scale emulation engine and an application example from the field of low-power wireless devices. The primary goal of the emulator is to support design space exploration of real-time algorithms. The emulator is customized for dataflow dominant architectures, especially focusing on telecommunication-related applications. Due to its novel routing architecture and application-specific nature, the emulator is capable of real-time execution of a class of algorithms in its application space. Moreover, the dataflow structure facilitates the development of a highly abstracted design flow for the emulator. Simulations and practical measurements on commercial development boards are used to verify that real-time emulation of a low-power TDMA receiver is feasible at a clock speed of 25 MHz.

  4. Ultra Low-Power Algorithm Design for Implantable Devices: Application to Epilepsy Prostheses

    Directory of Open Access Journals (Sweden)

    Shriram Raghunathan

    2011-05-01

    Full Text Available Low-power circuit design techniques have enabled the possibility of integrating signal processing and feature extraction algorithms on-board implantable medical devices, eliminating the need for wireless transfer of data outside the patient. Feature extraction algorithms also serve as valuable tools for modern-day artificial prostheses, made possible by implantable brain-computer-interface systems. This paper intends to review the challenges in designing feature extraction blocks for implantable devices, with specific focus on developing efficacious but computationally efficient algorithms to detect seizures. Common seizure detection features used to construct algorithms are evaluated and algorithmic, mathematical as well as circuit-level design techniques are suggested to effectively translate the algorithms into hardware implementations on low-power platforms.

  5. A low power mixed signal DC offset calibration circuit for direct conversion receiver applications

    Science.gov (United States)

    Lijun, Yang; Fang, Yuan; Zheng, Gong; Yin, Shi; Zhiming, Chen

    2011-12-01

    A low power mixed signal DC offset calibration (DCOC) circuit for direct conversion receiver applications is designed. The proposed DCOC circuit features low power consumption, fast settling time and a small die area by avoiding the trade-off between loop response time and the high pass frequency of the DCOC servo loop in conventional analog DCOC systems. By applying the proposed DC offset correction circuitry, the output residue DC offset voltages are reduced to less than 38 mV and the DCOC loop settling time is less than 100 μs. The DCOC chip is fabricated in a standard 0.13-μm CMOS technology and drains only 196 μA from a 1.2-V power supply with its chip area of only 0.372 × 0.419 mm2.

  6. Design of a Low Voltage low Power Double tail comparator in 180nm cmos Technology

    Directory of Open Access Journals (Sweden)

    Mr. Deepak Joseph Babu

    2014-09-01

    Full Text Available The need of analog to digital converters with ultra low power, area efficient and high speed is giving more chance to the use of dynamic regenerative comparators to maximize the speed and power efficiency. In this paper, an analysis on the delay and power of the dynamic comparators will be presented and based on the presented analysis, a new dynamic comparator is proposed, in which the conventional double tail comparator is modified for low power and fast operation even in small supply voltages. Here by adding a few transistors, the power consumptions can be reduced drastically. Post–layout simulation using 180nm CMOS technology confirms the analysis results of the proposed dynamic comparator.

  7. Design of Ultra Low Power 8-Channel Analog Multiplexer Using Dynamic Threshold for Biosignals

    Directory of Open Access Journals (Sweden)

    D.Hari Priya

    2013-10-01

    Full Text Available The design of an ultra low voltage, low power high speed 8 channel Analog multiplexer in 180nm CMOS technology is presented. A modified transmission gate using a dynamic threshold voltage MOSFET (DTMOS is employed in the design. The design is optimized with respect to critical requirements like short switching time, low power dissipation, good linearity and high dynamic range with an operating voltage of 0.4V. The ON and OFF resistances achieved are 32 ohms and 10Mohms respectively with a switching speed of 10MHz. The power dissipation obtained is around 2.65uW for a dynamic range of 1uV to 0.4V.

  8. Low-power multi-chip module and board-level links for data transfer

    Energy Technology Data Exchange (ETDEWEB)

    Carson, R.F.; Hardin, T.L.; Warren, M.E.; Lear, K.L.; Lovejoy, M.L.; Seigal, P.K.; Craft, D.C. [Sandia National Labs., Albuquerque, NM (United States); Enquist, P.J. [Research Triangle Inst., Research Triangle Park, NC (United States)

    1997-03-01

    Advanced device technologies such as Vertical Cavity Surface-Emitting Lasers (VCSELs) and diffractive micro lenses can be obtained with novel packaging techniques to allow low-power interconnection of parallel optical signals. These interconnections can be realized directly on circuit boards, in a multi-chip module format, or in packages that emulate electrical connectors. For applications such as stacking of Multi-Chip Module (MCM) layers, the links may be realized in bi-directional form using integrated diffractive microlenses. In the stacked MCM design, consumed electrical power is minimized by use of a relatively high laser output from high efficiency VCSELs, and a receiver design that is optimized for low power, at the expense of dynamic range. Within certain constraints, the design may be extended to other forms such as board-level interconnects.

  9. A 10-bit low power SAR A/D converter based on 90 nm CMOS

    Institute of Scientific and Technical Information of China (English)

    Tong Xingyuan; Yang Yintang; Zhu Zhangming; Xiao Yan; Chen Jianming

    2009-01-01

    Traditional and some recently reported low power, high speed and high resolution approaches for SAR A/D converters are discussed. Based on SMIC 65 nm CMOS technology, two typical low power methods reported in previous works are validated by circuit design and simulation. Design challenges and considerations for high speed SAR A/D converters are presented. Moreover, an R-C combination based method is also addressed and a 10-bit SAR A/D converter with this approach is implemented in SMIC 90 nm CMOS process. The DNL and INL are measured to be less than 0.31 LSB and 0.59 LSB respectively. With an input frequency of 420 kHz at 1 MS/s sampling rate, the SFDR and ENOB are measured to be 67.6 dB and 9.46 bits respectively, and the power dissipation is measured to be just 3.17 mW.

  10. A low-power 10-bit 250-KSPS cyclic ADC with offset and mismatch correction*

    Institute of Scientific and Technical Information of China (English)

    Zhao Hongliang; Zhao Yiqiang; Geng Junfeng; Li Peng; Zhang Zhisheng

    2011-01-01

    A low power 10-bit 250-k sample per second (KSPS) cyclic analog to digital converter (ADC) is presented. The ADC's offset errors are successfully cancelled out through the proper choice of a capacitor switching sequence. The improved redundant signed digit algorithm used in the ADC can tolerate high levels of the comparator's offset errors and switched capacitor mismatch errors. With this structure, it has the advantages of simple circuit configuration, small chip area and low power dissipation. The cyclic ADC manufactured with the Chartered 0.35 μm 2P4M process shows a 58.5 dB signal to noise and distortion ratio and a 9.4 bit effective number of bits at a 250 KSPS sample rate. It dissipates 0.72 mW with a 3.3 V power supply and occupies dimensions of 0.42 × 0.68 mm2.

  11. Two novel low-power and high-speed dynamic carbon nanotube full-adder cells.

    Science.gov (United States)

    Bagherizadeh, Mehdi; Eshghi, Mohammad

    2011-09-02

    In this paper, two novel low-power and high-speed carbon nanotube full-adder cells in dynamic logic style are presented. Carbon nanotube field-effect transistors (CNFETs) are efficient in designing a high performance circuit. To design our full-adder cells, CNFETs with three different threshold voltages (low threshold, normal threshold, and high threshold) are used. First design generates SUM and COUT through separate transistors, and second design is a multi-output dynamic full adder. Proposed full adders are simulated using HSPICE based on CNFET model with 0.9 V supply voltages. Simulation result shows that the proposed designs consume less power and have low power-delay product compared to other CNFET-based full-adder cells.

  12. Two novel low-power and high-speed dynamic carbon nanotube full-adder cells

    Directory of Open Access Journals (Sweden)

    Eshghi Mohammad

    2011-01-01

    Full Text Available Abstract In this paper, two novel low-power and high-speed carbon nanotube full-adder cells in dynamic logic style are presented. Carbon nanotube field-effect transistors (CNFETs are efficient in designing a high performance circuit. To design our full-adder cells, CNFETs with three different threshold voltages (low threshold, normal threshold, and high threshold are used. First design generates SUM and COUT through separate transistors, and second design is a multi-output dynamic full adder. Proposed full adders are simulated using HSPICE based on CNFET model with 0.9 V supply voltages. Simulation result shows that the proposed designs consume less power and have low power-delay product compared to other CNFET-based full-adder cells.

  13. A low-power high-speed ultra-wideband pulse radio transmission system.

    Science.gov (United States)

    Wei Tang; Culurciello, E

    2009-10-01

    We present a low-power high-speed ultra-wideband (UWB) transmitter with a wireless transmission test platform. The system is specifically designed for low-power high-speed wireless implantable biosensors. The integrated transmitter consists of a compact pulse generator and a modulator. The circuit is fabricated in the 0.5-mum silicon-on-sapphire process and occupies 420 mum times 420 mum silicon area. The transmitter is capable of generating pulses with 1-ns width and the pulse rate can be controlled between 90 MHz and 270 MHz. We built a demonstration/testing system for the transmitter. The transmitter achieves a 14-Mb/s data rate. With 50% duty cycle data, the power consumption of the chip is between 10 mW and 21 mW when the transmission distance is from 3.2 to 4 m. The core circuit size is 70 mum times 130 mum.

  14. Design of Low Power & High Speed Comparator with 0.18µm Technology for ADC Application

    Directory of Open Access Journals (Sweden)

    Rohit Mongre

    2014-08-01

    Full Text Available In Analog to Digital Converter (ADC, high speed comparator influences the overall performance of ADC directly. This paper presents the high speed & low power design of a CMOS comparator. Schematic design of this comparator is fabricated in a 0.18µm UMC Technology with 1.8V power supply and simulated in cadence Virtuoso. Simulation results are presented and it shows that this design can work under high speed of 0.8108 GHz. The design has a low offset voltage, low power dissipation 108.0318µw. In addition we have verified present results with schematic view design and also compared these results with earlier reported work and got improvement in this reported work.

  15. A Sub Threshold Source Coupled Logic Based Design of Low Power CMOS Analog Multiplexer

    Directory of Open Access Journals (Sweden)

    G.Deepika

    2014-11-01

    Full Text Available A novel approach for designing Ultra Low Power and wide dynamic range circuit for multiplexing analog signals is presented. The design operates in weak inversion (Sub threshold region and uses Source - Coupled Logic ( SCL circuit. The bias current of the SCL gates is varied to scale down linearly the power consumption and the operating frequency. The multiplexer design employs CMOS transistors as transmission gate with dynamic threshold voltage. The design exhibits low power dissipation, high dynamic range and good linearity. The design was implemented in 180 nm technology and was operated at a supply voltage of 400 mV with a bias current ranging in the order of few Pico-amperes. The ON and OFF resistance of the transmission gate achieved were 27 ohms and 10 M ohms respectively. The power dissipation achieved is around 0.79 µW for a dynamic range of 1µV to 0.4 V.

  16. Development of Ultra-Low Power Metal Oxide Sensors and Arrays for Embedded Applications

    Science.gov (United States)

    Lutz, Brent; Wind, Rikard; Kostelecky, Clayton; Routkevitch, Dmitri; Deininger, Debra

    2011-09-01

    Metal oxide semiconductor sensors are widely used as individual sensors and in arrays, and a variety of designs for low power microhotplates have been demonstrated.1 Synkera Technologies has developed an embeddable chemical microsensor platform, based on a unique ceramic MEMS technology, for practical implementation in cell phones and other mobile electronic devices. Key features of this microsensor platform are (1) small size, (2) ultra-low power consumption, (3) high chemical sensitivity, (4) accurate response to a wide-range of threats, and (5) low cost. The sensor platform is enabled by a combination of advances in ceramic micromachining, and precision deposition of sensing films inside the high aspect ratio pores of anodic aluminum oxide (AAO).

  17. Low Power Designing of PLL with 0.125μm CMOS technology

    Directory of Open Access Journals (Sweden)

    Divya Patel Yash Kshirsagar

    2011-10-01

    Full Text Available This paper deals with the designing of Low Power PLL by reducing power consumtion of VCO to generate well-timed on chip clock signals for digital signals. Switching of digital system introduce power supply or substrate noise which perturb the more sensitive blocks in VCO and clock buffer. Since power dissipation in PLL is small fraction of total active power but it increase with increasing operating frequency of digital system. This paper is describing the design of a fully-integrated low-jitter PLL for low power application. To achieve the low jitter performance, our work is proposed on jitter reduction method on both system and circuit level. The results are verified for both circuit and system level. The PLL is implemented in 0.25μm CMOS technology and consumes 10mW from a 2.5V supply

  18. A New Low-Power CMOS Quadrature VCO with Current Reused Structure

    Directory of Open Access Journals (Sweden)

    C. Wang

    2011-04-01

    Full Text Available A new quadrature voltage controlled oscillator (QVCO circuit topology is proposed for low-voltage and low-power applications. In the proposed circuit, two oscillators with current-reused structure are coupled to each other by two P&N-MOS pairs. In this way, low phase noise quadrature signals are generated with low-voltage and low-power. The simulation is made by Cadence in chartered 0.18 μm CMOS process. The simulation result shows that the QVCO phase noise is approximately - 117.1 dBc/Hz at 1MHz offset from 1.8 GHz operation frequency. The QVCO dissipates 1.92 mW with a 1.1 V supply voltage.

  19. Low-power Mid-IR Supercontinuum and Rogue Wave Generation in Chalcogenide Waveguides

    CERN Document Server

    Hernandez, Santiago M; Bonetti, Juan; Grosz, Diego F

    2016-01-01

    We present numerical results of supercontinuum (SC) generation in the mid-IR spectral region, specifically addressing the molecular fingerprint window ranging from 2.5 to 25 um. By solving the Generalized Nonlinear Schr\\"odinger Equation (GNLSE) in a chalcogenide waveguide, we demonstrate low-power SC generation beyond 10 um from a pump at 5 um. Further, we investigate the short-pulse and CW regimes, and show that a simple linear dispersion profile, applicable to a broad range of chalcogenide media, is sufficient to account for the broad SC generation, and yield rich pulse dynamics leading to the frequent occurrence of rogue wave events. Results are encouraging as they point to the feasibility of producing bright and coherent light, by means of single low-power tabletop laser pumping schemes, in a spectral region that finds applications in such diverse areas as molecular spectroscopy, metrology and tomography, among others, and that is not easily addressable with other light sources

  20. Analog-Digital Partitioning for Low-Power UWB Impulse Radios under CMOS Scaling

    Directory of Open Access Journals (Sweden)

    Desset Claude

    2006-01-01

    Full Text Available Ultra-wideband (UWB impulse radios show strong advantages for the implementation of low-power transceivers. In this paper, we analyze the impact of CMOS technology scaling on power consumption of UWB impulse radios. It is shown that the power consumption of the synchronization constitutes a large portion of the total power in the receiver. A traditional technique to reduce the power consumption at the receiver is to operate the UWB radios with a very low duty cycle on an architecture with extreme parallelism. On the other hand, this requires more silicon area and this is limited by the leakage power consumption, which becomes more and more a problem in future CMOS technologies. The proposed quantitative framework allows systematic use of digital low-power design techniques in future UWB transceivers.

  1. Design and Analysis of Multi Vt and Variable Vt based Pipelined Adder for Low Power applications

    Directory of Open Access Journals (Sweden)

    Shanthala S

    2010-12-01

    Full Text Available Majority of Digital Signal Processing (DSP applications require arithmetic blocks such as multipliers and adders for hardware realization of complex algorithms. Power consumption of arithmetic blocks need to be minimized by use of low power techniques. In this paper, an experimental setup is developed to identify the sources of power dissipation and remedies that can be adopted to minimize power dissipation in arithmetic blocks. Use of low power techniques such as Multi Vt, variable Vt, pipelining, geometry scaling and use of appropriate load capacitance have been used to reduce power dissipation. A 4-bitpipelined adder is designed and the power dissipation is reduced to 4.17µW from 9.6µW. The designed pipelined adder can be used for DSP applications.

  2. DSTN (Distributed Sleep Transistor Network) for Low Power Programmable Logic array Design

    CERN Document Server

    Singla, Pradeep; Malik, Naveen Kr; 10.5120/7004-9563

    2012-01-01

    With the high demand of the portable electronic products, Low- power design of VLSI circuits & Power dissipation has been recognized as a challenging technology in the recent years. PLA (Programming logic array) is one of the important off shelf part in the industrial application. This paper describes the new design of PLA using power gating structure sleep transistor at circuit level implementation for the low power applications. The important part of the power gating design i.e. header and footer switch selection is also describes in the paper. The simulating results of the proposed architecture of the new PLA is shown and compared with the conventional PLA. This paper clearly shows the optimization in the reduction of power dissipation in the new design implementation of the PLA. The transient response of the power gates structure of PLA is also illustrate in the paper by using TINA-PRO software.

  3. Design of an ultra-low-power digital processor for passive UHF RFID tags

    Institute of Scientific and Technical Information of China (English)

    Shi Wanggen; Zhuang Yiqi; Li Xiaoming; Wang Xianghua; Jin Zhao; Wang Dan

    2009-01-01

    A new architecture of digital processors for passive UHF radio-frequency identification tags is proposed.This architecture is based on ISO/IEC 18000-6C and targeted at ultra-low power consumption.By applying methods like system-level power management,global clock gating and low voltage implementation,the total power of the design is reduced to a few microwatts.In addition,an innovative way for the design of a true RNG is presented,which contributes to both low power and secure data transaction.The digital processor is verified by an integrated FPGA platform and implemented by the Synopsys design kit for ASIC flows.The design fits different CMOS technologies and has been taped out using the 2P4M 0.35μm process of Chartered Semiconductor.

  4. An ultra low power ECG signal processor design for cardiovascular disease detection.

    Science.gov (United States)

    Jain, Sanjeev Kumar; Bhaumik, Basabi

    2015-08-01

    This paper presents an ultra low power ASIC design based on a new cardiovascular disease diagnostic algorithm. This new algorithm based on forward search is designed for real time ECG signal processing. The algorithm is evaluated for Physionet PTB database from the point of view of cardiovascular disease diagnosis. The failed detection rate of QRS complex peak detection of our algorithm ranges from 0.07% to 0.26% for multi lead ECG signal. The ASIC is designed using 130-nm CMOS low leakage process technology. The area of ASIC is 1.21 mm(2). This ASIC consumes only 96 nW at an operating frequency of 1 kHz with a supply voltage of 0.9 V. Due to ultra low power consumption, our proposed ASIC design is most suitable for energy efficient wearable ECG monitoring devices.

  5. Relations between high and low power groups: the importance of legitimacy.

    Science.gov (United States)

    Hornsey, Matthew J; Spears, Russell; Cremers, Iris; Hogg, Michael A

    2003-02-01

    Using a social identity perspective, two experiments examined the effects of power and the legitimacy of power differentials on intergroup bias. In Experiment 1, 125 math-science students were led to believe that they had high or low representation in a university decision-making body relative to social-science students and that this power position was either legitimate or illegitimate. Power did not have an independent effect on bias; rather, members of both high and low power groups showed more bias when the power hierarchy was illegitimate than when it was legitimate. This effect was replicated in Experiment 2 (N = 105). In addition, Experiment 2 showed that groups located within an unfair power hierarchy expected the superordinate power body to be more discriminatory than did those who had legitimately high or low power. The results are discussed in terms of their implications for group relations.

  6. A low power level-crossing ADC for wearable wireless ECG sensors.

    Science.gov (United States)

    Zhenzhen Tian; Rendong Ying; Peilin Liu; Guoxing Wang; Yong Lian

    2016-08-01

    Ultra-low power consumption is desired in most wearable biomedical devices. The event-driven based Analog-to-Digital converter (ADC) could be an excellent candidate for low power system because of the reduction in sampling points for biosignals. In the existing event-driven based ADC architectures, two or more high precision comparators are utilized to sample the input signal. In this paper, we propose a new scheme utilizing only one high precision comparator to genertate samples with the assistance of a low precision one. From the Matlab simulations on real ECG signal, it is shown that around 25% reduction on the number of samples can be be achieved compared with the Nyquist sampling scheme.

  7. A proposed OEIC circuit with two metal layer silicon waveguide and low power photonic receiver circuit

    Directory of Open Access Journals (Sweden)

    Shiraz Afazal

    2012-09-01

    Full Text Available Recent development in the field of optical communication have increased the need for Opto Electronic Integrated circuit used for the high speed data transmission with low power consuming, high bandwidth and compact size. Presented is the OEIC chip with two metal layer waveguide and low power receiver circuit using standard CMOS technology. The silicon dioxide waveguide is composed of two metal layer reducing metal layer make OEIC cost effective , The silicon LED is fabricated using nwell/p-substrate with p+ octagonal rings, the p+/nwell forms the series pn junction to increase the light emitting area which operates in reverse bias mode. Photo detector is made of multiple PN junction to increase the depletion region width with n+ active implantation/n-well fabricated on the p substrate .the photocurrent receiver circuit is made of MOSFET to perform the function of photo detection and preamplification

  8. Low-Power Implantable Device for Onset Detection and Subsequent Treatment of Epileptic Seizures: A Review

    Directory of Open Access Journals (Sweden)

    Muhammad Tariqus Salam

    2010-01-01

    Full Text Available Over the past few years, there has been growing interest in neuro-responsive intracerebral local treatments of seizures, such as focal drug delivery, focal cooling, or electrical stimulation. This mode of treatment requires an effective intracerebral electroencephalographic acquisition system, seizure detector, brain stimulator, and wireless system that consume ultra-low power. This review focuses on alternative brain stimulation treatments for medically intractable epilepsy patients. We mainly discuss clinical studies of long-term responsive stimulation and suggest safer optimized therapeutic options for epilepsy. Finally, we conclude our study with the proposed low-power, implantable fully integrated device that automatically detects low-voltage fast activity ictal onsets and triggers focal treatment to disrupt seizure progression. The detection performance was verified using intracerebral electroencephalographic recordings from two patients with epilepsy. Further experimental validation of this prototype is underway.

  9. A Novel Photodiode for Reflectance Pulse Oximetry in low-power applications

    DEFF Research Database (Denmark)

    Haahr, Rasmus Grønbek; Duun, Sune; Birkelund, Karen;

    2007-01-01

    The amount of light collected is crucial for low-power applications of pulse oximetry. In this work a novel ring-shaped backside photodiode has been developed for a wearable reflectance pulse oximeter. The photodiode is proven to work with a dual LED with wavelengths of 660 nm and 940 nm. For the......The amount of light collected is crucial for low-power applications of pulse oximetry. In this work a novel ring-shaped backside photodiode has been developed for a wearable reflectance pulse oximeter. The photodiode is proven to work with a dual LED with wavelengths of 660 nm and 940 nm....... For the purpose of continuously monitoring vital signs of a human, a temperature sensor is integrated onto the chip containing the photodiode. This biomedical multisensor chip is made for integration into "the electronic patch", an autonomous monitoring system for humans....

  10. Low-Power and High Speed 128-Point Pipline FFT/IFFT Processor for OFDM Applications

    Directory of Open Access Journals (Sweden)

    D. Rajaveerappa

    2012-03-01

    Full Text Available This paper represents low power and high speed 128-point pipelined Fast Fourier Transform (FFT and its inverse Fast Fourier Transform (IFFT processor for OFDM. The Modified architecture also provides concept of ROM module and variable length support from 128~2048 point for FFT/IFFT for OFDM applications such as digital audio broadcasting (DAB, digital video broadcasting-terrestrial (DVB-T, asymmetric digital subscriber loop (ADSL and very-high-speed digital subscriber loop (VDSL. The 128-point architecture consists of an optimized pipeline implementation based on Radix-2 butterfly processor Element. To reduce power consumption and chip area, special current-mode SRAMs are adopted to replace shift registers in the delay lines. In low-power operation, when the supply voltage is scaled down to 2.3 V, the processor consumes 176mW when it runs at 17.8 MHz.

  11. Delay-limited capacity of fading multiple access and broadcast channels in the low power regime

    KAUST Repository

    Rezki, Zouheir

    2015-09-11

    We study delay-limited (also called zero-outage) capacity region of the fading multi-access channel (MAC) with Gaussian noise and perfect channel state information (CSI) at the receiver and at the transmitters (CSI-TR), in the low-power regime. We show that for fading channels where the MAC capacity region is strictly positive, it has a multidimensional rectangle structure and thus is simply characterized by single user capacity points. More specifically, we show that at low power, the boundary surface of the capacity region shrinks to a single point corresponding to the sum-rate maximizer and that the coordinates of this point coincide with single user capacity bounds. Using the duality of the Gaussian MAC and broadcast channels (BC), we show that time-sharing (or time division multiple access (TDMA)) is asymptotically optimal. © 2015 IEEE.

  12. An Identity-Based Group Key Agreement Proto col for Low-Power Mobile Devices

    Institute of Scientific and Technical Information of China (English)

    TENG Jikai; WU Chuankun

    2016-01-01

    In wireless mobile networks, group mem-bers join and leave the group frequently, a dynamic group key agreement protocol is required to provide a group of users with a shared secret key to achieve cryptographic goal. Most of previous group key agreement protocols for wireless mobile networks are static and employ traditional PKI. This paper presents an ID-based dynamic authen-ticated group key agreement protocol for wireless mobile networks. In Setup and Join algorithms, the protocol re-quires two rounds and each low-power node transmits con-stant size of messages. Furthermore, in Leave algorithm, only one round is required and none of low-power nodes is required to transmit any message, which improves the effi-ciency of the entire protocol. The protocol’s AKE-security with forward secrecy is proved under Decisional bilinear in-verse Diffie-Hellman (DBIDH) assumption. It is addition-ally proved to be contributory.

  13. Low Cost, Low Power, Passive Muon Telescope for Interrogating Martian Sub-Surface

    Science.gov (United States)

    Kedar, Sharon; Tanaka, Hirukui; Naudet, Charles; Plaut, Jeffrey J.; Jones, Cathleen E.; Webb, Frank H.

    2012-01-01

    It has been demonstrated on Earth that a low power, passive muon detector can penetrate deep into geological structures up to several kilometers in size providing high density images of their interiors. Muon tomography is an entirely new class of planetary instrumentation that is ideally suited to address key areas in Mars Science, such as: the search for life and habitable environments, the distribution and state of water and ice and the level of geologic activity on Mars today.

  14. HIGH SPEED LOW POWER CMOS DOMINO OR GATE DESIGN IN 16NM TECHNOLOGY

    Directory of Open Access Journals (Sweden)

    P. Koti Lakshmi

    2015-07-01

    Full Text Available Dynamic logic circuits provide more compact designs with faster switching speeds and low power consumption compared with the other CMOS design styles. This paper proposes a wide fan-in circuit with increased switching speed and noise immunity. Speed is achieved by quickly removing the charge on the dynamic node during evaluation phase, compared to the other circuits. The design also offers very less Power Delay Product (PDP. The design is exercised for 20% variation in supply voltage.

  15. Low power wind energy conversion system based on variable speed permanent magnet synchronous generators

    OpenAIRE

    Carranza Castillo, Oscar; Garcerá Sanfeliú, Gabriel; Figueres Amorós, Emilio; GONZÁLEZ MORALES, LUIS GERARDO

    2014-01-01

    This paper presents a low power wind energy conversion system (WECS) based on a permanent magnet synchronous generator and a high power factor (PF) rectifier. To achieve a high PF at the generator side, a power processing scheme based on a diode rectifier and a boost DC-DC converter working in discontinuous conduction mode is proposed. The proposed generator control structure is based on three cascaded control loops that regulate the generator current, the turbine speed and the amount of powe...

  16. A digital filter optimization method for low power digital wireless communication system

    OpenAIRE

    Tarumi, Kousuke; Tsujimoto, Taizo; Yasuura, Hiroto

    2003-01-01

    In this paper, we introduce a design method for a low power digital baseband processing circuit. In particular, we focus on a digital FIR(Finite Impulse Response) filter that is a part of the digital baseband processing. Because the digital filter contains large power consuming components, such as adders and multipliers. We propose a design method to reduce power consumption of the digital FIR filter circuit by optimizing bitwidth of inputs of the mutipliers and the adders. We found that the ...

  17. Ambipolar Organic Tri-Gate Transistor for Low-Power Complementary Electronics.

    Science.gov (United States)

    Torricelli, Fabrizio; Ghittorelli, Matteo; Smits, Edsger C P; Roelofs, Christian W S; Janssen, René A J; Gelinck, Gerwin H; Kovács-Vajna, Zsolt M; Cantatore, Eugenio

    2016-01-13

    Ambipolar transistors typically suffer from large off-current inherently due to ambipolar conduction. Using a tri-gate transistor it is shown that it is possible to electrostatically switch ambipolar polymer transistors from ambipolar to unipolar mode. In unipolar mode, symmetric characteristics with an on/off current ratio of larger than 10(5) are obtained. This enables easy integration into low-power complementary logic and volatile electronic memories.

  18. The vulnerability of laser warning systems against guided weapons based on low power lasers

    OpenAIRE

    Al-Jaberi, Mubarak

    2006-01-01

    Laser assisted weapons, such as laser guided bombs, laser guided missiles and laser beam-riding missiles pose a significant threat to military assets in the modern battlefield. Laser beam-riding missiles are particularly hard to detect because they use low power lasers. Most laser warning systems produced so far can not detect laser beam-riding missiles because of their weak emissions which have signals less than 1% of laser range finder power . They are even harder to defeat because current ...

  19. The effect of low-power lasers on intraoral wound healing.

    Science.gov (United States)

    Neiburger, E J

    1995-03-01

    Two types of helium-neon lasers were examined for their effectiveness in increasing the rate of wound healing by biostimulation. The diode helium-neon laser (670 nm) was as effective as the gas helium-neon laser (632 nm) in significantly speeding the rate of healing in rats. Thermal properties of low-power lasers and a controlled clinical case of helium-neon laser treatment of human aphthous stomatitis lesions were reported.

  20. Design and Optimization of a Low Power Pressure Sensor for Wireless Biomedical Applications

    Directory of Open Access Journals (Sweden)

    J. Sosa

    2015-01-01

    (ADC are designed, optimized, and integrated in the same substrate using a commercial 1 μm CMOS technology. As result of the optimization, we obtained a digital sensor with high sensitivity, low noise (0.002 μV/Hz, and low power consumption (358 μW. Finally, the piezoresistance noise does not affect the pressure sensor application since its value is lower than half least significant bit (LSB of the ADC.

  1. A low power MICS band phase-locked loop for high resolution retinal prosthesis.

    Science.gov (United States)

    Yang, Jiawei; Skafidas, Efstratios

    2013-08-01

    Ultra low power dissipation is essential in retinal prosthesis and many other biomedical implants. Extensive research has been undertaken in designing low power biomedical transceivers, however to date, most effort has been focused on low frequency inductive links. For higher frequency, more robust and more complex applications, such as Medical Implant Communication Service (MICS) band multichannel transceivers, power consumption remains high. This paper explores the design of micro-power data links at 400 MHz for a high resolution retinal prosthesis. By taking advantage of advanced small geometry CMOS technology and precise transistor-level modeling, we successfully utilized subthreshold FET operation, which has been historically limited to low frequency circuits due to the inadequate transistor operating speed in and near weak inversion; we have implemented a low power MICS transceiver. Particularly, a low power, MICS band multichannel phase-locked loop (PLL) that employs a subthreshold voltage controlled oscillator (VCO) and digital synchronous dividers has been implemented on a 65-nm CMOS. A design methodology is presented in detail with the demonstration of EKV model parameters extraction. This PLL provides 600- mVpp quadrature oscillations and exhibits a phase noise of -102 dBc/Hz at 200-kHz offset, while only consuming 430- μW from a 1-V supply. The VCO has a gain (KVCO) of 12 MHz/V and is designed to operate in the near-weak inversion region and consumes 220- μA DC current. The designed PLL has a core area of 0.54 mm(2). It satisfies all specifications of MICS band operation with the advantage of significant reduction in power which is crucial for high resolution retinal prosthesis.

  2. A low-power photovoltaic system with energy storage for radio communications: Description and design methodology

    Science.gov (United States)

    Chapman, C. P.; Chapman, P. D.; Lewison, A. H.

    1982-01-01

    A low power photovoltaic system was constructed with approximately 500 amp hours of battery energy storage to provide power to an emergency amateur radio communications center. The system can power the communications center for about 72 hours of continuous nonsun operation. Complete construction details and a design methodology algorithm are given with abundant engineering data and adequate theory to allow similar systems to be constructed, scaled up or down, with minimum design effort.

  3. A SCHEDULING SCHEME WITH DYNAMIC FREQUENCY CLOCKING AND MULTIPLE VOLTAGES FOR LOW POWER DESIGNS

    Institute of Scientific and Technical Information of China (English)

    Wen Dongxin; Wang Ling; Yang Xiaozong

    2007-01-01

    In this letter, a scheduling scheme based on Dynamic Frequency Clocking (DFC) and multiple voltages is proposed for low power designs under the timing and the resource constraints.Unlike the conventional methods at high level synthesis where only voltages of nodes were considered,the scheme based on a gain function considers both voltage and frequency simultaneously to reduce energy consumption. Experiments with a number of DSP benchmarks show that the proposed scheme achieves an effective energy reduction.

  4. Monte Carlo analysis of a low power domino gate under parameter fluctuation

    Institute of Scientific and Technical Information of China (English)

    Wang Jinhui; Wu Wuchen; Gong Na; Hou Ligang; Peng Xiaohong; Gao Daming

    2009-01-01

    Using the multiple-parameter Monte Carlo method, the effectiveness of the dual threshold voltage technique (DTV) in low power domino logic design is analyzed. Simulation results indicate that under significant temperature and process fluctuations, DTV is still highly effective in reducing the total leakage and active power consumption for domino gates with speed loss. Also, regarding power and delay characteristics, different structure domino gates with DTV have different robustness against temperature and process fluctuation.

  5. Adiabatic Improved Efficient Charge Recovery Logic for Low Power CMOS Logic

    Directory of Open Access Journals (Sweden)

    Prof. Mukesh Tiwar

    2012-08-01

    Full Text Available Power dissipation becoming a limiting factor in VLSI circuits and systems. Due to relatively high complexity of VLSI systems used in various applications, the power dissipation in CMOS inverter, arises from its switching activity, which is mainly influenced by the supply voltage and effective capacitance. The low-power requirements of present electronic systems have challenged the scientific research towards the study of technological, architectural and circuital solutions that allow a reduction of the energy dissipated by an electronic circuit. One of the main causes of energy dissipation in CMOS circuits is due to the charging and discharging of the node capacitances of the circuits, present both as a load and as parasitic. Such part of the total power dissipated by a circuit is called dynamic power. In order to reduce the dynamic power, an alternative approach to the traditional techniques of power consumption reduction, named adiabatic switching technique is use. Adiabatic switching is an approach to low-power digital circuits that differs fundamentally from other practical low-power techniques. The term adiabatic comes from thermodynamics, used to describe a process in which there is no exchange of heat with the environment. When adiabatic switching is used, the signal energies stored on circuit capacitances may be recycled instead of dissipated as heat. The adiabatic switching technique can achieve very low power dissipation, but at the expense of circuit complexity. Adiabatic logic offers a way to reuse the energy stored in the load capacitors rather than the traditional way of discharging the load capacitors to the ground and wasting this energy. Power reduction is achieved by recovering the energy in the recover phase of the supply clock.

  6. Charge-based MOSFET model based on the Hermite interpolation polynomial

    Science.gov (United States)

    Colalongo, Luigi; Richelli, Anna; Kovacs, Zsolt

    2017-04-01

    An accurate charge-based compact MOSFET model is developed using the third order Hermite interpolation polynomial to approximate the relation between surface potential and inversion charge in the channel. This new formulation of the drain current retains the same simplicity of the most advanced charge-based compact MOSFET models such as BSIM, ACM and EKV, but it is developed without requiring the crude linearization of the inversion charge. Hence, the asymmetry and the non-linearity in the channel are accurately accounted for. Nevertheless, the expression of the drain current can be worked out to be analytically equivalent to BSIM, ACM and EKV. Furthermore, thanks to this new mathematical approach the slope factor is rigorously defined in all regions of operation and no empirical assumption is required.

  7. Design of Low-Power CMOS OTA Using Bulk-Drive Technique

    Directory of Open Access Journals (Sweden)

    Maryam Ghadiri Modarres

    2015-10-01

    Full Text Available This paper presents the design of low power CMOS- OTA (operational transconductance amplifier using bulk drive (BD technique with broad band. This technique is used for design of low power circuits with broad band for high frequency users, for example communication systems, mobile communication and communication forming of medical electronics. OTA is the base of amplifier .It is a fundamental building part of analog systems. Recently analog designer has been paid to low voltage (LV,low power (LP integrated circuits. Many techniques are used for the design of LV LP circuits, the bulk driven offers principle this designs. This paper suggests a bulk driven OTA in standard CMOS processes and supply voltage 0.8 volt DC. It used of improved wilson current mirror. The simulation results have been carried out by the HSPICE simulator in 180 nm CMOS technology. The open loop gain is enhanced to 17.4dB at unity gain band with (UGB of 26.1 MHZ with sufficient output swing. Power consumption of the OTA is in range of few hundreds of nanowatts (6%.

  8. Designing of Low Power CNTFET Based D Flip-Flop Using Forced Stack Technique

    Directory of Open Access Journals (Sweden)

    Vikas Sharma

    2015-04-01

    Full Text Available Low Power devices in small packages is the need of present and future electronic devices. Electronics Industry is making devices which can be planted in human bodies. CMOS Technology won‟t be able to deliver such devices because it shows short channel effects in Nano scale. So, to overcome the problems of CMOS technology we use CNTs (Carbon Nano Tubes. In electronic devices, power is consumed by various elements like flip-flop, latches, clock sources. So in order to reduce power of a system we used to reduce power consumed by flip-flops. In this paper we design an existing flip-flop “Low power clocked pass transistor flip-flop (LCPTFF” on CNTFET using Stanford CNTFET model for reference. We propose a design of CNTFET based Forced Stack Low Power Clocked Pass Transistor Flip-Flop (CN-FS-LCPTFF and observe 12% to 25% power reduction in various conditions like temperature change, CNTFET diameter change, and different voltage supply.

  9. Low Power Greenhouse Gas Sensors for Unmanned Aerial Vehicles

    Directory of Open Access Journals (Sweden)

    David J. Lary

    2012-05-01

    Full Text Available We demonstrate compact, low power, lightweight laser-based sensors for measuring trace gas species in the atmosphere designed specifically for electronic unmanned aerial vehicle (UAV platforms. The sensors utilize non-intrusive optical sensing techniques to measure atmospheric greenhouse gas concentrations with unprecedented vertical and horizontal resolution (~1 m within the planetary boundary layer. The sensors are developed to measure greenhouse gas species including carbon dioxide, water vapor and methane in the atmosphere. Key innovations are the coupling of very low power vertical cavity surface emitting lasers (VCSELs to low power drive electronics and sensitive multi-harmonic wavelength modulation spectroscopic techniques. The overall mass of each sensor is between 1–2 kg including batteries and each one consumes less than 2 W of electrical power. In the initial field testing, the sensors flew successfully onboard a T-Rex Align 700E robotic helicopter and showed a precision of 1% or less for all three trace gas species. The sensors are battery operated and capable of fully automated operation for long periods of time in diverse sensing environments. Laser-based trace gas sensors for UAVs allow for high spatial mapping of local greenhouse gas concentrations in the atmospheric boundary layer where land/atmosphere fluxes occur. The high-precision sensors, coupled to the ease-of-deployment and cost effectiveness of UAVs, provide unprecedented measurement capabilities that are not possible with existing satellite-based and suborbital aircraft platforms.

  10. A low power sub- μW chemical gilbert cell for ISFET differential reaction monitoring.

    Science.gov (United States)

    Kalofonou, Melpomeni; Toumazou, Christofer

    2014-08-01

    This paper presents a low power current-mode method for monitoring differentially derived changes in pH from ion-sensitive field-effect transistor (ISFET) sensors, by adopting the Chemical Gilbert Cell. The fabricated system, with only a few transistors, achieves differential measurements and therefore drift minimisation of continuously recorded pH signals obtained from biochemical reactions such as DNA amplification in addition to combined gain tunability using only a single current. Experimental results are presented, demonstrating the capabilities of the front-end at a microscopic level through integration in a lab-on-chip (LoC) setup combining a microfluidic assembly, suitable for applications that require differential monitoring in small volumes, such as DNA detection where more than one gene needs to be studied. The system was designed and fabricated in a typical 0.35 μ m CMOS process with the resulting topology achieving good differential pH sensitivity with a measured low power consumption of only 165 nW due to weak inversion operation. A tunable gain is demonstrated with results confirming 15.56 dB gain at 20 nA of ISFET bias current and drift reduction of up to 100 times compared to a single-ended measurement is also reported due to the differential current output, making it ideal for robust, low-power chemical measurement.

  11. Outcomes of an international initiative for harmonization of low power and shutdown probabilistic safety assessment

    Directory of Open Access Journals (Sweden)

    Manna Giustino

    2010-01-01

    Full Text Available Many probabilistic safety assessment studies completed to the date have demonstrated that the risk dealing with low power and shutdown operation of nuclear power plants is often comparable with the risk of at-power operation, and the main contributors to the low power and shutdown risk often deal with human factors. Since the beginning of the nuclear power generation, human performance has been a very important factor in all phases of the plant lifecycle: design, commissioning, operation, maintenance, surveillance, modification, decommissioning and dismantling. The importance of this aspect has been confirmed by recent operating experience. This paper provides the insights and conclusions of a workshop organized in 2007 by the IAEA and the Joint Research Centre of the European Commission, on Harmonization of low power and shutdown probabilistic safety assessment for WWER nuclear power plants. The major objective of the workshop was to provide a comparison of the approaches and the results of human reliability analyses and gain insights in the enhanced handling of human factors.

  12. Low-Voltage Ultra-Low-Power Current Conveyor Based on Quasi-Floating Gate Transistors

    Directory of Open Access Journals (Sweden)

    F. Khateb

    2012-06-01

    Full Text Available The field of low-voltage low-power CMOS technology has grown rapidly in recent years; it is an essential prerequisite particularly for portable electronic equipment and implantable medical devices due to its influence on battery lifetime. Recently, significant improvements in implementing circuits working in the low-voltage low-power area have been achieved, but circuit designers face severe challenges when trying to improve or even maintain the circuit performance with reduced supply voltage. In this paper, a low-voltage ultra-low-power current conveyor second generation CCII based on quasi-floating gate transistors is presented. The proposed circuit operates at a very low supply voltage of only ±0.4 V with rail-to-rail voltage swing capability and a total quiescent power consumption of mere 9.5 µW. Further, the proposed circuit is not only able to process the AC signal as it's usual at quasi-floating gate transistors but also the DC which extends the applicability of the proposed circuit. In conclusion, an application example of the current-mode quadrature oscillator is presented. PSpice simulation results using the 0.18 µm TSMC CMOS technology are included to confirm the attractive properties of the proposed circuit.

  13. On the capacity of multiaccess fading channels with full channel state information at low power regime

    KAUST Repository

    Rezki, Zouheir

    2013-06-01

    We study the throughput capacity region of the Gaussian multiaccess (MAC) fading channel with perfect channel state information (CSI) at the receiver (CSI-R) and at the transmitters (CSI-T), at low power regime. We show that it has a multidimensional rectangle structure and thus is simply characterized by single user capacity points. More specifically, we show that at low power regime, the boundary surface of the capacity region shrinks to a single point corresponding to the sum rate maximizer and that the coordinates of this point coincide with single user capacity bounds. Inspired from this result, we propose an on-off scheme, compute its achievable rate, and provide a necessary condition on the fading channels under which this scheme achieves single user capacity bounds of the MAC channel at asymptotically low power regime. We argue that this necessary condition characterizes a class of fading that encompasses all known wireless channels, where the capacity region of the MAC channel has a simple expression in terms of users\\' average power constraints only. © 2013 IEEE.

  14. 47 CFR 73.6012 - Protection of Class A TV, low power TV and TV translator stations.

    Science.gov (United States)

    2010-10-01

    ... 47 Telecommunication 4 2010-10-01 2010-10-01 false Protection of Class A TV, low power TV and TV... of Class A TV, low power TV and TV translator stations. An application to change the facilities of an existing Class A TV station will not be accepted if it fails to protect other authorized Class A TV,...

  15. A very low power MAC (VLPM) protocol for Wireless Body Area Networks.

    Science.gov (United States)

    Ullah, Niamat; Khan, Pervez; Kwak, Kyung Sup

    2011-01-01

    Wireless Body Area Networks (WBANs) consist of a limited number of battery operated nodes that are used to monitor the vital signs of a patient over long periods of time without restricting the patient's movements. They are an easy and fast way to diagnose the patient's status and to consult the doctor. Device as well as network lifetime are among the most important factors in a WBAN. Prolonging the lifetime of the WBAN strongly depends on controlling the energy consumption of sensor nodes. To achieve energy efficiency, low duty cycle MAC protocols are used, but for medical applications, especially in the case of pacemakers where data have time-limited relevance, these protocols increase latency which is highly undesirable and leads to system instability. In this paper, we propose a low power MAC protocol (VLPM) based on existing wakeup radio approaches which reduce energy consumption as well as improving the response time of a node. We categorize the traffic into uplink and downlink traffic. The nodes are equipped with both a low power wake-up transmitter and receiver. The low power wake-up receiver monitors the activity on channel all the time with a very low power and keeps the MCU (Micro Controller Unit) along with main radio in sleep mode. When a node [BN or BNC (BAN Coordinator)] wants to communicate with another node, it uses the low-power radio to send a wakeup packet, which will prompt the receiver to power up its primary radio to listen for the message that follows shortly. The wake-up packet contains the desired node's ID along with some other information to let the targeted node to wake-up and take part in communication and let all other nodes to go to sleep mode quickly. The VLPM protocol is proposed for applications having low traffic conditions. For high traffic rates, optimization is needed. Analytical results show that the proposed protocol outperforms both synchronized and unsynchronized MAC protocols like T-MAC, SCP-MAC, B-MAC and X-MAC in terms

  16. A Very Low Power MAC (VLPM Protocol for Wireless Body Area Networks

    Directory of Open Access Journals (Sweden)

    Kyung Sup Kwak

    2011-03-01

    Full Text Available Wireless Body Area Networks (WBANs consist of a limited number of battery operated nodes that are used to monitor the vital signs of a patient over long periods of time without restricting the patient’s movements. They are an easy and fast way to diagnose the patient’s status and to consult the doctor. Device as well as network lifetime are among the most important factors in a WBAN. Prolonging the lifetime of the WBAN strongly depends on controlling the energy consumption of sensor nodes. To achieve energy efficiency, low duty cycle MAC protocols are used, but for medical applications, especially in the case of pacemakers where data have time-limited relevance, these protocols increase latency which is highly undesirable and leads to system instability. In this paper, we propose a low power MAC protocol (VLPM based on existing wakeup radio approaches which reduce energy consumption as well as improving the response time of a node. We categorize the traffic into uplink and downlink traffic. The nodes are equipped with both a low power wake-up transmitter and receiver. The low power wake-up receiver monitors the activity on channel all the time with a very low power and keeps the MCU (Micro Controller Unit along with main radio in sleep mode. When a node [BN or BNC (BAN Coordinator] wants to communicate with another node, it uses the low-power radio to send a wakeup packet, which will prompt the receiver to power up its primary radio to listen for the message that follows shortly. The wake-up packet contains the desired node’s ID along with some other information to let the targeted node to wake-up and take part in communication and let all other nodes to go to sleep mode quickly. The VLPM protocol is proposed for applications having low traffic conditions. For high traffic rates, optimization is needed. Analytical results show that the proposed protocol outperforms both synchronized and unsynchronized MAC protocols like T-MAC, SCP-MAC, B

  17. MENVOS - Methodologies for the design of low power systems. Low Power Workshop - in conjunction with ICCD2002; MENVOS - Methodiken fuer den Entwurf verlustleistungsoptimierter Systeme. Abschlussbericht

    Energy Technology Data Exchange (ETDEWEB)

    Kakerow, R.; Bierbaum, D.; Steinke, B.; Rossmann, U.; Rademacher, H.; Boettcher, R.; Kreutziger, P.; Scheithauer, F.; Goser; Schumacher, K.; Manoli, Y.; Becker, M.; Hitzelberger, C.

    2002-09-01

    The reduction of power consumption has become a very important objective in the design of battery operated systems, as well as circuits with high computation requirements. Besides time to market, power consumption belongs to the most dominating parameters in the development of circuits and systems. Today's methodologies are mainly focused on performance issues like timing and accuracy. To satisfy the need for innovative low-power methodologies, a power driven design flow has been developed in the project MENVOS. This design flow is based on two items: First a power estimation on all abstraction levels of the design phase is provided. Further on power optimisation methodologies for circuits and systems are developed for architectural, circuit and layout levels. It is relevant to assure a comprehensive multi-level approach for the design methodologies. Investigations have been done in the analog, digital and mixed-signal domain on circuit level, and on higher abstraction levels in terms of architecture partitioning and optimisation. The potential for optimisations in the physical layout level has also been pointed out. The project outcome shows an extensive examination of power optimisation strategies and their rating by applying them to hardware demonstrators. Results of MENVOS regarding power estimation and power optimisation are for the most part compatible with conventional design environment and directly applicable for system and circuit design. (orig.)

  18. Pre-exposure to low-power diode laser irradiation promotes cytoprotection in the rat retina.

    Science.gov (United States)

    Sun, Yue; Zhang, Shisheng; Liao, Huaping; Wang, Jing; Wang, Ling

    2015-01-01

    The aim of this study was to investigate whether pre-exposure to low-power laser irradiation can provoke an effect on cellular protection in the rat retina. The right eyes of 40 rats were exposed to a 3-mm diode laser beam for 1 min in different light intensities and different experimental sets: group A low power of 60 mW (34.27 J/cm(2) on the retina in consideration of the energy losses along the optical pathway) prior to high power of 80 mW (44.88 J/cm(2) on the retina in consideration of the energy losses along the optical pathway), group B high power, group C low power, group D (the left eyes from the counterpart of group A) and group E (untreated rat eyes) as controls. Morphological retinal change retinas were assessed using light microscopy and/or transmission electron microscopy. Heat shock protein (Hsp) 70 and cleaved caspase 3 protein expression were analyzed by immunohistochemical staining and Western blot. Cellular injury was assessed by terminal deoxynucleotidyl transferase-mediated dUTP nick end-labeling (TUNEL) assay. Hsp 70 expression in the inner plexiform layer and the outer plexiform layer in group A were 73.09 ± 6.49 and 78.03 ± 3.05%, respectively, which was significantly higher (P retina) power laser irradiation stimulates a hyperexpression of Hsp70 together with a hypoexpression of cleaved caspase 3 in rat retina, which may suggest a cellular protective effect.

  19. Effects of low power laser irradiation on bone healing in animals: a meta-analysis

    Directory of Open Access Journals (Sweden)

    Houghton Pamela

    2010-01-01

    Full Text Available Abstract Purpose The meta-analysis was performed to identify animal research defining the effects of low power laser irradiation on biomechanical indicators of bone regeneration and the impact of dosage. Methods We searched five electronic databases (MEDLINE, EMBASE, PubMed, CINAHL, and Cochrane Database of Randomised Clinical Trials for studies in the area of laser and bone healing published from 1966 to October 2008. Included studies had to investigate fracture healing in any animal model, using any type of low power laser irradiation, and use at least one quantitative biomechanical measures of bone strength. There were 880 abstracts related to the laser irradiation and bone issues (healing, surgery and assessment. Five studies met our inclusion criteria and were critically appraised by two raters independently using a structured tool designed for rating the quality of animal research studies. After full text review, two articles were deemed ineligible for meta-analysis because of the type of injury method and biomechanical variables used, leaving three studies for meta-analysis. Maximum bone tolerance force before the point of fracture during the biomechanical test, 4 weeks after bone deficiency was our main biomechanical bone properties for the Meta analysis. Results Studies indicate that low power laser irradiation can enhance biomechanical properties of bone during fracture healing in animal models. Maximum bone tolerance was statistically improved following low level laser irradiation (average random effect size 0.726, 95% CI 0.08 - 1.37, p 0.028. While conclusions are limited by the low number of studies, there is concordance across limited evidence that laser improves the strength of bone tissue during the healing process in animal models.

  20. MOSFET-like CNFET based logic gate library for low-power application: a comparative study

    Science.gov (United States)

    Gowri Sankar, P. A.; Udhayakumar, K.

    2014-07-01

    The next generation of logic gate devices are expected to depend upon radically new technologies mainly due to the increasing difficulties and limitations of existing CMOS technology. MOSFET like CNFETs should ideally be the best devices to work with for high-performance VLSI. This paper presents results of a comprehensive comparative study of MOSFET-like carbon nanotube field effect transistors (CNFETs) technology based logic gate library for high-speed, low-power operation than conventional bulk CMOS libraries. It focuses on comparing four promising logic families namely: complementary-CMOS (C-CMOS), transmission gate (TG), complementary pass logic (CPL) and Domino logic (DL) styles are presented. Based on these logic styles, the proposed library of static and dynamic NAND-NOR logic gates, XOR, multiplexer and full adder functions are implemented efficiently and carefully analyzed with a test bench to measure propagation delay and power dissipation as a function of supply voltage. This analysis provides the right choice of logic style for low-power, high-speed applications. Proposed logic gates libraries are simulated using Synopsys HSPICE based on the standard 32 nm CNFET model. The simulation results demonstrate that, it is best to use C-CMOS logic style gates that are implemented in CNFET technology which are superior in performance compared to other logic styles, because of their low average power-delay-product (PDP). The analysis also demonstrates how the optimum supply voltage varies with logic styles in ultra-low power systems. The robustness of the proposed logic gate library is also compared with conventional and state-art of CMOS logic gate libraries.

  1. Parallel design patterns for a low-power, software-defined compressed video encoder

    Science.gov (United States)

    Bruns, Michael W.; Hunt, Martin A.; Prasad, Durga; Gunupudi, Nageswara R.; Sonachalam, Sekar

    2011-06-01

    Video compression algorithms such as H.264 offer much potential for parallel processing that is not always exploited by the technology of a particular implementation. Consumer mobile encoding devices often achieve real-time performance and low power consumption through parallel processing in Application Specific Integrated Circuit (ASIC) technology, but many other applications require a software-defined encoder. High quality compression features needed for some applications such as 10-bit sample depth or 4:2:2 chroma format often go beyond the capability of a typical consumer electronics device. An application may also need to efficiently combine compression with other functions such as noise reduction, image stabilization, real time clocks, GPS data, mission/ESD/user data or software-defined radio in a low power, field upgradable implementation. Low power, software-defined encoders may be implemented using a massively parallel memory-network processor array with 100 or more cores and distributed memory. The large number of processor elements allow the silicon device to operate more efficiently than conventional DSP or CPU technology. A dataflow programming methodology may be used to express all of the encoding processes including motion compensation, transform and quantization, and entropy coding. This is a declarative programming model in which the parallelism of the compression algorithm is expressed as a hierarchical graph of tasks with message communication. Data parallel and task parallel design patterns are supported without the need for explicit global synchronization control. An example is described of an H.264 encoder developed for a commercially available, massively parallel memorynetwork processor device.

  2. Use of low power EM radar sensors for speech articulator measurements

    Energy Technology Data Exchange (ETDEWEB)

    Holzrichter, J.F.; Burnett, G.C.

    1997-05-14

    Very low power electromagnetic (EM) wave sensors are being used to measure speech articulator motions such as the vocal fold oscillations, jaw, tongue, and the soft palate. Data on vocal fold motions, that correlate well with established laboratory techniques, as well as data on the jaw, tongue, and soft palate are shown. The vocal fold measurements together with a volume air flow model are being used to perform pitch synchronous estimates of the voiced transfer functions using ARMA (autoregressive moving average) techniques. 6 refs., 5 figs.

  3. From Coherent States in Adjacent Graphene Layers toward Low-Power Logic Circuits

    Directory of Open Access Journals (Sweden)

    Leonard F. Register

    2011-01-01

    Full Text Available Colleagues and we recently proposed a new type of transistor, a Bilayer PseudoSpin Field Effect Transistor (BiSFET, based on many-body coherent states in coupled electron and hole layers in graphene. Here we review the basic BiSFET device concept and ongoing efforts to determine how such a device, which would be far from a drop-in replacement for MOSFETs in CMOS logic, could be used for low-power logic operation, and to model the effects of engineerable device parameters on the formation and gating of interlayer coherent state.

  4. Wireless ultra-wide-band transmission prototype ASICs for low-power space and radiation applications

    Energy Technology Data Exchange (ETDEWEB)

    Gabrielli, A. [Istituto Nazionale di Fisica Nucleare (INFN), Bologna (Italy); Department of Physics and Astronomy, University of Bologna, Bologna (Italy); Crepaldi, M. [IIT@Polito Istituto Italiano Tecnologia, Politecnico di Torino, Torino (Italy); Demarchi, D. [IIT@Polito Istituto Italiano Tecnologia, Politecnico di Torino, Torino (Italy); Department of Electronics (DELEN), Politecnico di Torino, Torino (Italy); Motto Ros, P. [IIT@Polito Istituto Italiano Tecnologia, Politecnico di Torino, Torino (Italy); Villani, G. [Science Technology Facility Council (STFC), Rutherford Appleton Laboratory (RAL), Didcot (United Kingdom)

    2014-11-21

    The paper describes the design and the fabrication of a microelectronic circuit composed of a sensor, an oscillator, a modulator, a transmitter and an antenna. The chip embeds a custom radiation sensor, provided by the silicon foundry that has fabricated the prototypes, but in principle the entire system can read a general sensor, as long as a proper interface circuit is used. The natural application for this circuit is radiation monitoring but the low-power budget extends the applications to space where wireless readout circuits can be applied to any type of sensors, even if not radiation sensitive devices.

  5. Indirect Control of a low power Single-Phase Active Power Filter

    Directory of Open Access Journals (Sweden)

    SILVIU EPURE

    2010-12-01

    Full Text Available This paper deals with a low power, single phase active filter used to compensate nonlinear loads. The filter uses the indirect control method and it is based on a particular connection between filter, polluting load and grid to avoid timeconsuming mathematic operations or signal processing computations and assures good rejection of harmonic currents injected by the nonlinear load into the grid. A scale model was first simulated in Simulink and then physically implemented. The paper presents simulation and experimental results, and highlight problems encountered during experiments.

  6. A NEW APPROACH TO DESIGN LOW POWER CMOS FLASH A/D CONVERTER

    Directory of Open Access Journals (Sweden)

    Sudakar S. Chauhan

    2011-07-01

    Full Text Available In the present paper, a 4-bit flash analog to digital converter for low power SoC application is presented.CMOS inverter has been used as a comparator and by adjusting the ratio of channel width and length, theswitching threshold of the CMOS inverter is varied to detect the input analog signal. The simulation resultsshow that this proposed 4-bit flash ADC consumes about 12.4 mW at 200M sample/s with 3.3V supplyvoltage in TSMC 0.35 μm process. Compared with the traditional flash ADC, this proposed method canreduce about 78% in power consumption.

  7. Low power laser generated ultrasound: Signal processing for time domain data acquisition

    Energy Technology Data Exchange (ETDEWEB)

    Cleary, A; Thursby, G; McKee, C; Armstrong, I; Culshaw, B [Centre for Microsystems and Photonics, Department of Electronic and Electrical Engineering, University of Strathclyde, Glasgow, G1 1XW (United Kingdom); Veres, I; Pierce, S G, E-mail: alison.cleary@eee.strath.ac.uk [Centre for Ultrasonic Engineering, Department of Electronic and Electrical Engineering, University of Strathclyde, Glasgow, G1 1XW (United Kingdom)

    2011-01-01

    The use of low power modulated laser diode systems has previously been established as a suitable method for non-destructive laser generation of ultrasound. Using a quasi-continuous optical excitation amplified by an erbium-doped fibre amplifier (EDFA) allows flexible generation of ultrasonic waves, offering control of further parameters such as the frequency content or signal shape. In addition, pseudo-random binary sequences (PRBS) can be used to improve the detected impulse response. Here we compare two sequences, the m-sequence and the Golay code, and discuss the advantages and practical limits of their application with laser diode based optical excitation of ultrasound.

  8. Shock-Tolerant Low-Power Generator Design for Landed Missions

    Science.gov (United States)

    Gelderloos, Carl J.; Decino, Jim; Lock, Jennifer; Miller, Dan D.; Taylor, Robert

    2004-02-01

    A shock-tolerant thermal enclosure has been designed for use in distributed landed missions. Missions such as Pascal and the Mars Long-Lived Landed Network require low power sources capable of surviving an omnidirectional load at impact and delivering reliable power for several Martian years. With the use of a radioisotope heat source and a thermoelectric converter, power can be generated reliably, but the challenge of developing an insulating canister that delivers sufficient power at end of life and is shock tolerant has been elusive. We describe a manufacturable design using conventional materials that meets mission requirements and show preliminary analysis of impact load response.

  9. A Compact, Low-Power Cantilever-Based Sensor Array for Chemical Detection

    Energy Technology Data Exchange (ETDEWEB)

    Loui, A; Ratto, T; Wilson, T; Mukerjee, E; Hu, Z; Sulchek, T; Hart, B

    2007-02-22

    A compact and low-power cantilever-based sensor array has been developed and used to detect various vapor analytes. This device employs sorptive polymers that are deposited onto piezoresistive cantilevers. We have successfully detected several organic vapors, representing a breadth of chemical properties and over a range of concentrations. Comparisons of the polymer/vapor partition coefficient to the cantilever deflection responses show that a simple linear relationship does not exist, emphasizing the need to develop an appropriate functional model to describe the chemical-to-mechanical transduction that is unique to this sensing modality.

  10. Development of gallium arsenide high-speed, low-power serial parallel interface modules: Executive summary

    Science.gov (United States)

    1988-01-01

    Final report to NASA LeRC on the development of gallium arsenide (GaAS) high-speed, low power serial/parallel interface modules. The report discusses the development and test of a family of 16, 32 and 64 bit parallel to serial and serial to parallel integrated circuits using a self aligned gate MESFET technology developed at the Honeywell Sensors and Signal Processing Laboratory. Lab testing demonstrated 1.3 GHz clock rates at a power of 300 mW. This work was accomplished under contract number NAS3-24676.

  11. A low-power asynchronous data-path for a FIR filter bank

    DEFF Research Database (Denmark)

    Nielsen, Lars Skovby; Sparsø, Jens

    1996-01-01

    This paper describes a number of design issues relating to the implementation of low-power asynchronous signal processing circuits. Specifically, the paper addresses the design of a dedicated processor structure that implements an audio FIR filter bank which is part of an industrial application. ...... the implications it has on the choice of architecture, handshake-protocol, data-encoding, and circuit design. This includes a tagging scheme that divides the data-path into slices, and an asynchronous ripple carry adder that avoids a completion tree....

  12. Surface roughness due to residual ice in the use of low power deicing systems

    Science.gov (United States)

    Shin, Jaiwon; Bond, Thomas H.

    1993-01-01

    Thicknesses of residual ice are presented to provide information on surface contamination and associated roughness during deicing events. Data was obtained from low power ice protection systems tests conducted in the Icing Research Tunnel at NASA Lewis Research Center (LeRC) with nine different deicing systems. Results show that roughness associated with residual ice is not characterized by uniformly distributed roughness. Results also show that deicing systems require a critical mass of ice to generate a sufficient expelling force to remove the ice.

  13. Dynamic Floating Output Stage for Low Power Buffer Amplifier for LCD Application

    Directory of Open Access Journals (Sweden)

    Hari Shanker Srivastava

    2015-02-01

    Full Text Available This topic proposes low-power buffer means low quiescent current buffer amplifier. A dynamic floating current node is used at the output of two-stage amplifier to increase the charging and discharging of output capacitor as well as settling time of buffer. It is designed for 10 bit digital analog converter to support for LCD column driver it is implemented in 180 nm CMOS technology with the quiescent current of 5 µA for 30 pF capacitance, the settling time calculated as 4.5µs, the slew rate obtained as 5V/µs and area on chip is 30×72µ

  14. A Low Power Front End Analog Multiplexing Unit for 12 Lead ECG Signal Acquisition

    Directory of Open Access Journals (Sweden)

    D.Hari Priya

    2014-10-01

    Full Text Available The design of CMOS analog circuitry for acquiring 12 lead ECG is presented. The existing methods employ separate multiplexers and associated circuitry for signal acquisition operating at typical voltage of ± 5V. The proposed system employs dynamic threshold logic to achieve low power, wide dynamic range good linearity with a supply voltage of 0.4V. The power dissipation obtained was 22.12µW. Utilizing the dynamic threshold logic the proposed circuitry is implemented with 0.18µm CMOS technology. This ECG signal processor is highly suitable for wearable applications of long term cardiac monitoring.

  15. A Low Power Front End Analog Multiplexing Unit for 12 Lead ECG Signal Acquisition

    OpenAIRE

    2014-01-01

    The design of CMOS analog circuitry for acquiring 12 lead ECG is presented. The existing methods employ separate multiplexers and associated circuitry for signal acquisition operating at typical voltage of ± 5V. The proposed system employs dynamic threshold logic to achieve low power, wide dynamic range good linearity with a supply voltage of 0.4V. The power dissipation obtained was 22.12µW. Utilizing the dynamic threshold logic the proposed circuitry is implemented with 0.18µm CMOS technolog...

  16. Low-Power Fully Integrated CMOS DTV Tuner Front-End for ATSC Terrestrial Broadcasting

    Directory of Open Access Journals (Sweden)

    Jianhong Xiao

    2007-01-01

    Full Text Available A low-cost low-power DTV tuner for current digital television application is described. In order to increase integration level and reduce power consumption for off-air DTV tuner application, an SAW-filterless tuner front-end architecture is adopted. As a part of the concept, key building blocks for this architecture are implemented on a main stream 0.35 μm CMOS technology. Experimental measurements for the prototype chip validate the system architecture; the prototype consumes 300 mw and achieves 45 dB of image rejection ratio within the entire 750 MHz frequency band.

  17. A Low Power Front End Analog Multiplexing Unit for 12 Lead ECG Signal Acquisition

    Directory of Open Access Journals (Sweden)

    D.Hari Priya

    2014-04-01

    Full Text Available The design of CMOS analog circuitry for acquiring 12 lead ECG is presented. The existing methods employ separate multiplexers and associated circuitry for signal acquisition operating at typical voltage of ± 5V. The proposed system employs dynamic threshold logic to achieve low power, wide dynamic range good linearity with a supply voltage of 0.4V. The power dissipation obtained was 22.12µW. Utilizing the dynamic threshold logic the proposed circuitry is implemented with 0.18µm CMOS technology. This ECG signal processor is highly suitable for wearable applications of long term cardiac monitoring.

  18. Application of energy recovery in low-power DSP system design

    Energy Technology Data Exchange (ETDEWEB)

    Suvakovic, D.

    2002-07-01

    The design and implementation of low power DSP energy recovery systems were examined in terms of energy efficiency. The thesis focuses on the design of arithmetic units suitable for energy recovery. The work is based on the fact that non-adiabatic dissipation associated with full-swing signals sets a practical limit for energy efficiency in adiabatic arithmetic circuits. The non-adiabatic dissipation is reduced through architectural, not circuit, optimizations. The study also developed a circuit method called OBDDL, which allows for reliable and efficient energy operation of complex logic gates. Simulation studies verified that the design is energy efficient.

  19. Low-power resistive switching in Au/NiO/Au nanowire arrays

    Science.gov (United States)

    Brivio, S.; Tallarida, G.; Perego, D.; Franz, S.; Deleruyelle, D.; Muller, C.; Spiga, S.

    2012-11-01

    Arrays of vertical nanowires structured in Au/NiO/Au segments with 50 nm diameter are characterized by conductive atomic force microscopy to investigate unipolar resistive switching in NiO at the nanoscale. The switching cycles are characterized by extremely low power consumption down to 1.3 nW, which constitutes a significant improvement in nanowire-based resistive switching memory devices. The trend of the reset current as a function of the set resistance, typical of unipolar memories, is extended to a much wider current range than what is reported in literature, confirming the role of Joule heating in the reset process for very low reset currents.

  20. A 90nm, Low Power VCO with Reduced KVCO and Sub−band Spacing Variation

    OpenAIRE

    Collins, Diarmuid; Keady, Aidan; Szczepkowski, Grzegorz; Farrell, Ronan

    2011-01-01

    In this paper we present the design of a low power VCO with reduced variations in VCO gain (KVCO) and subband spacing resolution (fres). The proposed VCO is designed using a 90nm CMOS process to cover a tuning range of 23%. Variations in KVCO and fres are reduced by factors of 6 and 17 respectively over a conventional sub-banded VCO, designed using the same process, to meet the same tuning range. This makes the proposed VCO more suited to stable PLL operation with its ...

  1. Low-power switching of phase-change materials with carbon nanotube electrodes.

    Science.gov (United States)

    Xiong, Feng; Liao, Albert D; Estrada, David; Pop, Eric

    2011-04-29

    Phase-change materials (PCMs) are promising candidates for nonvolatile data storage and reconfigurable electronics, but high programming currents have presented a challenge to realize low-power operation. We controlled PCM bits with single-wall and small-diameter multi-wall carbon nanotubes. This configuration achieves programming currents of 0.5 microampere (set) and 5 microamperes (reset), two orders of magnitude lower than present state-of-the-art devices. Pulsed measurements enable memory switching with very low energy consumption. Analysis of over 100 devices finds that the programming voltage and energy are highly scalable and could be below 1 volt and single femtojoules per bit, respectively.

  2. A Low Power High Bandwidth Four Quadrant Analog Multiplier in 32 NM CNFET Technology

    Directory of Open Access Journals (Sweden)

    Vitrag Sheth

    2012-05-01

    Full Text Available Carbon Nanotube Field Effect Transistor (CNFET is a promising new technology that overcomes several limitations of traditional silicon integrated circuit technology. In recent years, the potential of CNFET for analog circuit applications has been explored. This paper proposes a novel four quadrant analog multiplier design using CNFETs. The simulation based on 32nm CNFET technology shows that the proposed multiplier has very low harmonic distortion (<0.45%, large input range (±400mV, large bandwidth (~50GHz and low power consumption (~247µW, while operating at a supply voltage of ±0.9V.

  3. A low-power piecewise linear analog to digital converter for use in particle tracking

    Energy Technology Data Exchange (ETDEWEB)

    Valencic, V.; Deval, P. [MEAD Microelectronics S.A., St. Sulpice (Switzerland)]|[EPFL, Lausanne (Switzerland). Electronics Labs.; Anghinolfi, F. [CERN, Geneva (Switzerland); Bonino, R.; Marra, D. La; Kambara, Hisanori [Univ. of Geneva (Switzerland)

    1995-08-01

    This paper describes a low-power piecewise linear A/D converter. A 5MHz {at} 5V with 25mW power consumption prototype has been implemented in a 1.5{micro}m CMOS process. The die area excluding pads is 5mm{sup 2}. 11-bit absolute accuracy is obtained with a new DC offset plus charge injection compensation technique used in the comparators scheme. This ADC with large dynamic range and high resolution is developed for the readout of a tracker and/or preshower in the future LHC experiments.

  4. TCP over low-power and lossy networks: tuning the segment size to minimize energy consumption

    CERN Document Server

    Ayadi, Ahmed; Ros, David

    2010-01-01

    Low-power and Lossy Networks (LLNs), like wireless networks based upon the IEEE 802.15.4 standard, have strong energy constraints, and are moreover subject to frequent transmission errors, not only due to congestion but also to collisions and to radio channel conditions. This paper introduces an analytical model to compute the total energy consumption in an LLN due to the TCP protocol. The model allows us to highlight some tradeoffs as regards the choice of the TCP maximum segment size, of the Forward Error Correction (FEC) redundancy ratio, and of the number of link-layer retransmissions, in order to minimize the total energy consumption.

  5. Electronic imaging system for neutron radiography at a low power research reactor

    Energy Technology Data Exchange (ETDEWEB)

    Ferreira, F.J.O., E-mail: fferreira@ien.gov.b [Instituto de Engenharia Nuclear, Comissao Nacional de Energia Nuclear, Caixa Postal 68550, CEP 21945-970, Rio de Janeiro (Brazil); Silva, A.X.; Crispim, V.R. [PEN/COPPE-DNC/POLI CT, Universidade Federal do Rio de Janeiro, Ilha do Fundao, Caixa Postal 68509, 21945-970 Rio de Janeiro (Brazil)

    2010-08-15

    This paper describes an electronic imaging system for producing real time neutron radiography from a low power research reactor, which will allow inspections of samples with high efficiency, in terms of measuring time and result analysis. This system has been implanted because of its potential use in various scientific and industrial areas where neutron radiography with photographic film could not be applied. This real time system is installed in neutron radiography facility of Argonauta nuclear research reactor, at the Instituto de Engenharia Nuclear of the Comissao Nacional de Energia Nuclear, in Brazil. It is adequate to perform real time neutron radiography of static and dynamic events of samples.

  6. Ultra Low Power 14XM FinFET's Process-a Radical New Approach to Transistors

    Directory of Open Access Journals (Sweden)

    Suhas K. V.

    2013-05-01

    Full Text Available FinFET technology is a radical new technology that has been proposed by the industry to overcome large leakage power occurring in low power VLSI circuits. In this paper, the working of the basic MOSFET, condition of operations for any transistor and the FinFET along with its structure is described. This paper mainly covers how FinFET can be an advantage compared to basic MOSFET and how leakage can be reduced in FinFET is explained with the comparison of basic MOSFET. The fabrication steps are briefly discussed

  7. Survey and selection of Energy Storage System for Low Power Embedded System

    OpenAIRE

    Meenu Nair; Chandan Maity

    2012-01-01

    Energy storage for portable low power Embedded System is one of the biggest challenges for a long time operation in present research and application. These systems are designed to operate the lowest possible energy at micro-watt or Milli-Watt range and the power is supplied from a small primary or secondary cell. In this paper an extensive study and latest survey has been shown to estimate and select the right suitable energy storage device in theoretical aspects and also commercially availab...

  8. Low power continuous wave laser induced optical nonlinearities in saffron ( Crocus Sativus L.)

    Science.gov (United States)

    Nasibov, H.; Mamedbeili, I.

    2010-12-01

    We report on the low power CW laser induced nonlinear optical responses of Saffron (stigmata of Crocus Savitus L.) ethanol and methanol extracts. The optical nonlinearities were investigated by performing Z-scan measurements at 470 and 535 nm wavelengths. At both wavelengths the material has a strong nonlinear refraction, mainly of thermal origin. However, only at 470 nm wavelength the material exhibit pronounced saturable nonlinear absorption. Long-term (70 days) stability measurements indicated that the nonlinearities in the Saffron extracts are due to their nonvolatile components. This study shows that there is great potential for Saffron extracts to be used in nonlinear photonic applications.

  9. Competition at the Wireless Sensor Network MAC Layer: Low Power Probing interfering with X-MAC

    Science.gov (United States)

    Zacharias, Sven; Newe, Thomas

    2011-08-01

    Wireless Sensor Networks (WSNs) combine sensors with computer networks and enable very dense, in-situ and live measurements of data over a large area. Since this emerging technology has the potential to be embedded almost everywhere for numberless applications, interference between different networks can become a serious issue. For most WSNs, it is assumed today that the network medium access is non-competitive. On the basis of X-MAC interfered by Low Power Probing, this paper shows the danger and the effects of different sensor networks communicating on a single wireless channel of the 2.4 GHz band, which is used by the IEEE 802.15.4 standard.

  10. ABO System Dependence Of Erythrocyte Crenation By Low Power He-Ne Laser Radiation

    Science.gov (United States)

    Rasia, Rodolfo J.; Martinelli, Cristina; Valverde de Rasia, Juana R.

    1982-12-01

    Samples of erythrocytes of different ABO groups, diluted in normal saline, were irradiated with high concentrated low power He-Ne Laser beam during 30 minutes. By microscopic observations made every 5 minutes the crenation time history of the irradiated red cells were determined. Assuming the crenation to have two sequential steps, experimental data of the rate constants for each of two steps of each blood sample were calculated. All these parameters and crenation-time history curves appear different and characteristic for each group of ABO-System. Further work to verify detected sensibility changes in inmunohematological reactions with Laser treated red blood cells is under progress.

  11. Low-power system-on-chip implementation for respiratory rate detection and transmission.

    Science.gov (United States)

    Padasdao, Bryson; Yee, Roxanne; Boric-Lubecke, Olga

    2012-01-01

    Recent biosensors can measure respiratory rate non-invasively, but limits patient mobility or requires regular battery replacement. Respiratory effort, which can scavenge mW, may power the sensor, but requires minimal sensor power usage. This paper demonstrates feasibility of respiratory rate measurement by using a comparator instead of ADC. A low-power system-on-chip can implement respiratory rate detection and wireless data transmission with a total power consumption under 82 µW. This approach produces significant power savings, and transmission uses under 30% of total power consumption.

  12. An X-Band low-power and low-phase-noise VCO using bondwire inductor

    OpenAIRE

    Hu, K.; F. Herzel; Scheytt, J. C.

    2009-01-01

    In this paper a low-power low-phase-noise voltage-controlled-oscillator (VCO) has been designed and, fabricated in 0.25 μm SiGe BiCMOS process. The resonator of the VCO is implemented with on-chip MIM capacitors and a single aluminum bondwire. A tail current filter is realized to suppress flicker noise up-conversion. The measured phase noise is −126.6 dBc/Hz at 1 MHz offset from a 7.8 GHz carrier. The figure of merit (FOM) of the VCO is −192.5 dBc/Hz and the VCO cor...

  13. Low power and self-reconfigurable WBAN controller for continuous bio-signal monitoring system.

    Science.gov (United States)

    Lee, Seulki; Yoo, Hoi-Jun

    2013-04-01

    The WBAN controller with Branched Bus (BB) topology and Continuous Data Transmission (CDT) protocol with low power consumption and self-reconfigurability is proposed for wearable healthcare applications. The BB topology and CDT protocol is a combination of conventional Bus and Star topology and a variation from TDMA protocol, respectively, while they are able to compensate for the electrical fault in bio-signal monitoring system caused by the electrode deformation. Thanks to them, the proposed WBAN controller enables more reliable operation in continuous bio-signal monitoring applications such as sleep monitoring.

  14. Design of High Speed Low Power Reversible Logic Adder Using HNG Gate

    Directory of Open Access Journals (Sweden)

    Manjeet Singh Sankhwar,

    2014-01-01

    Full Text Available Reversibility plays a fundamental role when computations with minimal energy dissipation are considered. In recent years, reversible logic has emerged as one of the most important approaches for power optimization with its application in low power CMOS, optical information processing, quantum computing and nanotechnology. This research proposes a new implementation of adder in reversible logic. The design reduces the number of gate operations compared to the existing adder reversible logic implementations. So, this design gives rise to an implementation with a reduced area and delay. We can use it to construct more complex systems in nanotechnology.

  15. Low-power system for the acquisition of the respiratory signal of neonates using diaphragmatic electromyography

    Science.gov (United States)

    Torres, Róbinson; López-Isaza, Sergio; Mejía-Mejía, Elisa; Paniagua, Viviana; González, Víctor

    2017-01-01

    Introduction An apnea episode is defined as the cessation of breathing for ≥15 seconds or as any suspension of breathing accompanied by hypoxia and bradycardia. Obtaining information about the respiratory system in a neonate can be accomplished using electromyography signals from the diaphragm muscle. Objective The purpose of this paper is to illustrate a method by which the respiratory and electrocardiographic signals from neonates can be obtained using diaphragmatic electromyography. Materials and methods The system was developed using single-supply, micropower components, which deliver a low-power consumption system appropriate for the development of portable devices. The stages of the system were tested in both adult and neonate patients. Results The system delivers signals as those expected in both patients and allows the acquisition of respiratory signals directly from the diaphragmatic electromyography. Conclusion This low-power system may present a good alternative for monitoring the cardiac and respiratory activity in newborn babies, both in the hospital and at home. Significance The system delivers good signals but needs to be validated for its use in neonates. It is being used in the Neonatal Intensive Care Unit of the Hospital General de Medellín Luz Castro de Gutiérrez. PMID:28260954

  16. III-V/Ge MOS device technologies for low power integrated systems

    Science.gov (United States)

    Takagi, S.; Noguchi, M.; Kim, M.; Kim, S.-H.; Chang, C.-Y.; Yokoyama, M.; Nishi, K.; Zhang, R.; Ke, M.; Takenaka, M.

    2016-11-01

    CMOS utilizing high mobility III-V/Ge channels on Si substrates is expected to be one of the promising devices for high performance and low power integrated systems in the future technology nodes, because of the enhanced carrier transport properties. In addition, Tunneling-FETs (TFETs) using Ge/III-V materials are regarded as one of the most important steep slope devices for the ultra-low power applications. In this paper, we address the device and process technologies of Ge/III-V MOSFETs and TFETs on the Si CMOS platform. The channel formation, source/drain (S/D) formation and gate stack engineering are introduced for satisfying the device requirements. The plasma post oxidation to form GeOx interfacial layers is a key gate stack technology for Ge CMOS. Also, direct wafer bonding of ultrathin body quantum well III-V-OI channels, combined with Tri-gate structures, realizes high performance III-V n-MOSFETs on Si. We also demonstrate planar-type InGaAs and Ge/strained SOI TFETs. The defect-less p+-n source junction formation with steep impurity profiles is a key for high performance TFET operation.

  17. Continuous operation of an ultra-low-power microcontroller using glucose as the sole energy source.

    Science.gov (United States)

    Lee, Inyoung; Sode, Takashi; Loew, Noya; Tsugawa, Wakako; Lowe, Christopher Robin; Sode, Koji

    2017-07-15

    An ultimate goal for those engaged in research to develop implantable medical devices is to develop mechatronic implantable artificial organs such as artificial pancreas. Such devices would comprise at least a sensor module, an actuator module, and a controller module. For the development of optimal mechatronic implantable artificial organs, these modules should be self-powered and autonomously operated. In this study, we aimed to develop a microcontroller using the BioCapacitor principle. A direct electron transfer type glucose dehydrogenase was immobilized onto mesoporous carbon, and then deposited on the surface of a miniaturized Au electrode (7mm(2)) to prepare a miniaturized enzyme anode. The enzyme fuel cell was connected with a 100 μF capacitor and a power boost converter as a charge pump. The voltage of the enzyme fuel cell was increased in a stepwise manner by the charge pump from 330mV to 3.1V, and the generated electricity was charged into a 100μF capacitor. The charge pump circuit was connected to an ultra-low-power microcontroller. Thus prepared BioCapacitor based circuit was able to operate an ultra-low-power microcontroller continuously, by running a program for 17h that turned on an LED every 60s. Our success in operating a microcontroller using glucose as the sole energy source indicated the probability of realizing implantable self-powered autonomously operated artificial organs, such as artificial pancreas.

  18. A Low-Power Digitally Controlled Oscillator for All Digital Phase-Locked Loops

    Directory of Open Access Journals (Sweden)

    Jun Zhao

    2010-01-01

    Full Text Available A low-power and low-jitter 12-bit CMOS digitally controlled oscillator (DCO design is presented. The Low-Power CMOS DCO is designed based on the ring oscillator implemented with Schmitt trigger inverters. The proposed DCO circuit uses control codes of thermometer type to reduce jitters. Performance of the DCO is verified through a novel All Digital Phase-Locked Loop (ADPLL designed with a unique lock-in process by employing a time-to-digital converter, where both the frequency of the reference clock and the delay between DCO_output and DCO_clock is measured. A carefully designed reset process reduces the phase acquisition process to two cycles. The ADPLL was implemented using the 32 nm Predictive Technology Model (PTM at 0.9 V supply voltage, and the simulation results show that the proposed ADPLL achieves 10 and 2 reference cycles of frequency and phase acquisitions, respectively, at 700 MHz with less than 67 ps peak-to-peak jitter. The DCO consumes 2.2 mW at 650 MHz with 0.9 V power supply.

  19. Ultra-low-power silicon photonics wavelength converter for phase-encoded telecommunication signals

    Science.gov (United States)

    Lacava, C.; Ettabib, M. A.; Cristiani, I.; Fedeli, J.-M.; Richardson, D. J.; Petropoulos, P.

    2016-03-01

    The development of compact, low power, silicon photonics CMOS compatible components for all-optical signal processing represents a key step towards the development of fully functional platforms for next generation all-optical communication networks. The wavelength conversion functionality at key nodes is highly desirable to achieve transparent interoperability and wavelength routing allowing efficient management of network resources operated with high speed, phase encoded signals. All optical wavelength conversion has already been demonstrated in Si-based devices, mainly utilizing the strong Kerr effect that silicon exhibits at telecommunication wavelengths. Unfortunately, Two Photon Absorption (TPA) and Free Carrier (FC) effects strongly limit their performance, even at moderate power levels, making them unsuitable for practical nonlinear applications. Amorphous silicon has recently emerged as a viable alternative to crystalline silicon (c-Si), showing both an enhanced Kerr as well as a reduced TPA coefficient at telecom wavelengths, with respect to its c-Si counterpart. Here we present an ultra-low power wavelength converter based on a passive, CMOS compatible, 1-mm long amorphous silicon waveguide operated at a maximum pump power level of only 70 mW. We demonstrate TPA-free Four Wave Mixing (FWM)-based wavelength conversion of Binary Phase Shift Keyed (BPSK) and Quadrature Phase Shift Keyed (QPSK) signals at 20 Gbit/s with <1 dB power penalty at BER = 10-5.

  20. Sink-to-Sink Coordination Framework Using RPL: Routing Protocol for Low Power and Lossy Networks

    Directory of Open Access Journals (Sweden)

    Meer M. Khan

    2016-01-01

    Full Text Available RPL (Routing Protocol for low power and Lossy networks is recommended by Internet Engineering Task Force (IETF for IPv6-based LLNs (Low Power and Lossy Networks. RPL uses a proactive routing approach and each node always maintains an active path to the sink node. Sink-to-sink coordination defines syntax and semantics for the exchange of any network defined parameters among sink nodes like network size, traffic load, mobility of a sink, and so forth. The coordination allows sink to learn about the network condition of neighboring sinks. As a result, sinks can make coordinated decision to increase/decrease their network size for optimizing over all network performance in terms of load sharing, increasing network lifetime, and lowering end-to-end latency of communication. Currently, RPL does not provide any coordination framework that can define message exchange between different sink nodes for enhancing the network performance. In this paper, a sink-to-sink coordination framework is proposed which utilizes the periodic route maintenance messages issued by RPL to exchange network status observed at a sink with its neighboring sinks. The proposed framework distributes network load among sink nodes for achieving higher throughputs and longer network’s life time.

  1. [Analysis of Electric Stress in Human Head in High-frequency Low-power Electromagnetic Environment].

    Science.gov (United States)

    Zhou, Yongjun; Zhang, Hui; Niu, Zhongqi

    2015-04-01

    Action of electromagnetic radiation exerting on human body has been a concerned issue for people. Because electromagnetic waves could generate an electric stress in a discontinuous medium, we used the finite difference time domain (FDTD) as calculation methods to calculate the electric stress and its distribution in human head caused by high-frequency low-power electromagnetic environment, which was generated by dual-band (900 MHz and 1 800 MHz) PIFA antennas with radiated power 1 W, and we then performed the safety evaluation of cell phone radiation from the angle whether the electric stress further reached the human hearing threshold. The result showed that there existed the electric stress at the interface of different permittivity organization caused by the two kinds of high-frequency low-power electromagnetic environment and the maximum electric stress was located at the interface between skin and air of the phone side, and the electric stress peak at skull did not reach the threshold of auditory caused by bone tissue conduction so that it can not produce auditory effects.

  2. Ultra-low-power carbon nanotube FET-based quaternary logic gates

    Science.gov (United States)

    Sharifi, Fazel; Moaiyeri, Mohammad Hossein; Navi, Keivan; Bagherzadeh, Nader

    2016-09-01

    This paper presents low-power carbon nanotube field-effect transistor (CNTFET)-based quaternary logic circuits. The proposed quaternary circuits are designed based on the CNTFET unique properties, such as the same carrier mobility for N- and P-type devices and also providing desirable threshold voltages by adopting proper diameters for the nanotubes. In addition, no paths exist between supply and ground rails in the steady states of the proposed designs, which eliminates the ON state static current and also the stacking technique is utilised in order to significantly reduce the leakage currents. The results of the simulations, conducted using Synopsys HSPICE with the standard 32 nm CNTFET technology, confirm the significantly lower power consumption, higher energy efficiency and lower sensitivity to process variation of the proposed designs compared to the state-of-the-art quaternary logic circuits. The proposed quaternary logic circuits have on average 92, 99 and 91% less total power, static power and PDP, respectively, compared with the most low-power and energy-efficient CNTFET-based quaternary logic circuits, recently presented in the literature.

  3. A Low power and area efficient CLA adder design using Full swing GDI technique

    Directory of Open Access Journals (Sweden)

    Matcha Hemanth Kumar

    2015-10-01

    Full Text Available The low power VLSI design has an important role in designing of many electronic systems. While designing any combinational or sequential circuits, the important parameters like power consumption, implementation area, voltage leakage and performance of the circuit are to be considered. Design of area, high speed and powerefficient data path logic systems forms the largest areas of research in VLSI system design. This paper presents a low power Carry look ahead adder design using Full swing Gate diffusion (FS-GDI technique. The proposed CLA implementation utilizes improved full-swing GDI F1 and F2 gates, which are the counterparts of standard CMOS NAND and NOR gates. The basic Gate Diffusion Input (GDI logic style suffers from some practical limitations like swing degradation, fabrication complexity in standard CMOS process and bulk connections. These limitations can be overcome by Full swing GDI technique. The proposed technique utilizes a single swing restoration (SR transistor to improve the output swing of F1 and F2 GDI gates. A 16-bit CLA is designed and Simulations are performed by Mentor graphics 130nm CMOS technology ELDO simulator. Simulation results have shown a greater reduction in delay, power dissipation and area.

  4. THE EFFECT OF LOW POWER GLASSES AT CLOSE DISTANCES ON VISUAL PERFORMANCE.

    Science.gov (United States)

    Vidal-López, Joaquín; Javaloyes-Moreno, Beatriz; Benlloch-Fornés, Josefa

    2015-10-01

    The purpose of this study was to reveal if the use of low power ophthalmic glasses (diopter values within the ± 1.00D range) in ophthalmic care may be beneficial for the treatment of low refractive vision disorders. 40 university students (10 men, 30 women), who used low power glasses at close distances (for reading on paper or on a computer screen: 40-60 centimeters approximately), voluntarily took part in this study. Ages of the participants ranged from 20 to 43 years (M = 24.9, SD = 4.4). Mean spherical refractive error was -0.38 diopters (SD = 0.49; range= -1.00-0.88). A yes/no Signal Detection procedure was used to assess whether the participants' visual sensitivity (d') or criterion of response (c) changed when they used the optical correction. There were no changes in visual sensitivity index, but significant changes in criterion of response were observed when the students used their optical correction. Changes in the criterion of response suggested the presence of a placebo effect.

  5. Hardware-efficient low-power image processing system for wireless capsule endoscopy.

    Science.gov (United States)

    Turcza, Pawel; Duplaga, Mariusz

    2013-11-01

    This paper presents the design of a hardware-efficient, low-power image processing system for next-generation wireless endoscopy. The presented system is composed of a custom CMOS image sensor, a dedicated image compressor, a forward error correction (FEC) encoder protecting radio transmitted data against random and burst errors, a radio data transmitter, and a controller supervising all operations of the system. The most significant part of the system is the image compressor. It is based on an integer version of a discrete cosine transform and a novel, low complexity yet efficient, entropy encoder making use of an adaptive Golomb-Rice algorithm instead of Huffman tables. The novel hardware-efficient architecture designed for the presented system enables on-the-fly compression of the acquired image. Instant compression, together with elimination of the necessity of retransmitting erroneously received data by their prior FEC encoding, significantly reduces the size of the required memory in comparison to previous systems. The presented system was prototyped in a single, low-power, 65-nm field programmable gate arrays (FPGA) chip. Its power consumption is low and comparable to other application-specific-integrated-circuits-based systems, despite FPGA-based implementation.

  6. A low-power CMOS smart temperature sensor for RFID application

    Science.gov (United States)

    Liangbo, Xie; Jiaxin, Liu; Yao, Wang; Guangjun, Wen

    2014-11-01

    This paper presents the design and implement of a CMOS smart temperature sensor, which consists of a low power analog front-end and a 12-bit low-power successive approximation register (SAR) analog-to-digital converter (ADC). The analog front-end generates a proportional-to-absolute-temperature (PTAT) voltage with MOSFET circuits operating in the sub-threshold region. A reference voltage is also generated and optimized in order to minimize the temperature error and the 12-bit SAR ADC is used to digitize the PTAT voltage. Using 0.18 μm CMOS technology, measurement results show that the temperature error is -0.69/+0.85 °C after one-point calibration over a temperature range of -40 to 100 °C. Under a conversion speed of 1K samples/s, the power consumption is only 2.02 μW while the chip area is 230 × 225 μm2, and it is suitable for RFID application.

  7. A low-power CMOS smart temperature sensor for RFID application

    Institute of Scientific and Technical Information of China (English)

    Xie Liangbo; Liu Jiaxin; Wang Yao; Wen Guangjun

    2014-01-01

    This paper presents the design and implement ofa CMOS smart temperature sensor,which consists of a low power analog front-end and a 12-bit low-power successive approximation register (SAR) analog-to-digital converter (ADC).The analog front-end generates a proportional-to-absolute-temperature (PTAT) voltage with MOSFET circuits operating in the sub-threshold region.A reference voltage is also generated and optimized in order to minimize the temperature error and the 12-bit SAR ADC is used to digitize the PTAT voltage.Using 0.18 μm CMOS technology,measurement results show that the temperature error is-0.69/+0.85 ℃ after one-point calibration over a temperature range of-40 to 100 ℃.Under a conversion speed of 1K samples/s,the power consumption is only 2.02μW while the chip area is 230 × 225 μm2,and it is suitable for RFID application.

  8. A low power medium access control protocol for wireless medical sensor networks.

    Science.gov (United States)

    Lamprinos, I; Prentza, A; Sakka, E; Koutsouris, D

    2004-01-01

    The concept of a wireless integrated network of sensors, already applied in several sectors of our everyday life, such as security, transportation and environment monitoring, can as well provide an advanced monitor and control resource for healthcare services. By networking medical sensors wirelessly, attaching them in patient's body, we create the appropriate infrastructure for continuous and real-time monitoring of patient without discomforting him. This infrastructure can improve healthcare by providing the means for flexible acquisition of vital signs, while at the same time it provides more convenience to the patient. Given the type of wireless network, traditional medium access control (MAC) protocols cannot take advantage of the application specific requirements and information characteristics occurring in medical sensor networks, such as the demand for low power consumption and the rather limited and asymmetric data traffic. In this paper, we present the architecture of a low power MAC protocol, designated to support wireless networks of medical sensors. This protocol aims to improve energy efficiency by exploiting the inherent application features and requirements. It is oriented towards the avoidance of main energy wastage sources, such as idle listening, collision and power outspending.

  9. Very Low Power Viterbi Decoder Employing Minimum Transition and Exchangeless Algorithms for Multimedia Mobile Communication

    Directory of Open Access Journals (Sweden)

    Prof. S. L. Haridas

    2011-12-01

    Full Text Available A very low power consumption viterbi decoder has been developed by low supply voltage and 0.15 µm CMOS process technology. Significant power reduction can be achieved by modifying the design and implementation of viterbi decoder using conventional techniques traceback and Register Exchange to Hybrid Register Exchange Method (HREM, Minimum Transition Register Exchange Method (MTREM, Minimum Transition Hybrid Register Exchange Method (MTHREM, Register exchangeless Method and Hybrid Register exchangeless Method. By employing the above said schemes such as, HREM, MTREM, MTHREM, Register exchangeless Method and Hybrid Register exchangeless Method; the viterbi decoder achieves a drastic reduction in power consumption below 100 µW at a supply voltage of 1.62 V when the data rate of 5 Mb/s and the bit error rate is less than 10-3. This excellent performance has been paved the way to employing the strong forward error correction and low power consumption portable terminals for personnel communication, mobile multimedia communication and digital audio broadcasting. Implementation insight and general conclusions can particularly benefit from this approach are given.

  10. Low-power analog processing for sensing applications: low-frequency harmonic signal classification.

    Science.gov (United States)

    White, Daniel J; William, Peter E; Hoffman, Michael W; Balkir, Sina

    2013-07-25

    A low-power analog sensor front-end is described that reduces the energy required to extract environmental sensing spectral features without using Fast Fouriér Transform (FFT) or wavelet transforms. An Analog Harmonic Transform (AHT) allows selection of only the features needed by the back-end, in contrast to the FFT, where all coefficients must be calculated simultaneously. We also show that the FFT coefficients can be easily calculated from the AHT results by a simple back-substitution. The scheme is tailored for low-power, parallel analog implementation in an integrated circuit (IC). Two different applications are tested with an ideal front-end model and compared to existing studies with the same data sets. Results from the military vehicle classification and identification of machine-bearing fault applications shows that the front-end suits a wide range of harmonic signal sources. Analog-related errors are modeled to evaluate the feasibility of and to set design parameters for an IC implementation to maintain good system-level performance. Design of a preliminary transistor-level integrator circuit in a 0.13 µm complementary metal-oxide-silicon (CMOS) integrated circuit process showed the ability to use online self-calibration to reduce fabrication errors to a sufficiently low level. Estimated power dissipation is about three orders of magnitude less than similar vehicle classification systems that use commercially available FFT spectral extraction.

  11. A Low-Power and Portable Biomedical Device for Respiratory Monitoring with a Stable Power Source

    Directory of Open Access Journals (Sweden)

    Jiachen Yang

    2015-08-01

    Full Text Available Continuous respiratory monitoring is an important tool for clinical monitoring. Associated with the development of biomedical technology, it has become more and more important, especially in the measuring of gas flow and CO2 concentration, which can reflect the status of the patient. In this paper, a new type of biomedical device is presented, which uses low-power sensors with a piezoresistive silicon differential pressure sensor to measure gas flow and with a pyroelectric sensor to measure CO2 concentration simultaneously. For the portability of the biomedical device, the sensors and low-power measurement circuits are integrated together, and the airway tube also needs to be miniaturized. Circuits are designed to ensure the stability of the power source and to filter out the existing noise. Modulation technology is used to eliminate the fluctuations at the trough of the waveform of the CO2 concentration signal. Statistical analysis with the coefficient of variation was performed to find out the optimal driving voltage of the pressure transducer. Through targeted experiments, the biomedical device showed a high accuracy, with a measuring precision of 0.23 mmHg, and it worked continuously and stably, thus realizing the real-time monitoring of the status of patients.

  12. A low power dual-band multi-mode RF front-end for GNSS applications

    Energy Technology Data Exchange (ETDEWEB)

    Zhang Hao; Li Zhiqun; Wang Zhigong, E-mail: zhhseu@gmail.com [Institute of RF- and OE- ICs, Southeast University, Nanjing 210096 (China)

    2010-11-15

    A CMOS dual-band multi-mode RF front-end for the global navigation satellite system receivers of all GPS, Bei-Dou, Galileo and Glonass systems is presented. It consists of a reconfigurable low noise amplifier (LNA), a broadband active balun, a high linearity mixer and a bandgap reference (BGR) circuit. The effect of the input parasitic capacitance on the input impedance of the inductively degenerated common source LNA is analyzed in detail. By using two different LC networks at the input port and the switched capacitor at the output port, the LNA can work at two different frequency bands (1.2 GHz and 1.5 GHz) under low power consumption. The active balun uses a hybrid-connection structure to achieve high bandwidth. The mixer uses the multiple gated transistors technique to acquire a high linearity under low power consumption but does not deteriorate other performances. The measurement results of the proposed front-end achieve a noise figure of 2.1/2.0 dB, again of 33.9/33.8 dB and an input 1-dB compression point of 0/1 dBm at 1227.6/1575.42 MHz. The power consumption is about 16 mW under a 1.8 V power supply.

  13. Design for High Performance, Low Power, and Reliable 3D Integrated Circuits

    CERN Document Server

    Lim, Sung Kyu

    2013-01-01

    This book describes the design of through-silicon-via (TSV) based three-dimensional integrated circuits.  It includes details of numerous “manufacturing-ready” GDSII-level layouts of TSV-based 3D ICs, developed with tools covered in the book. Readers will benefit from the sign-off level analysis of timing, power, signal integrity, and thermo-mechanical reliability for 3D IC designs.  Coverage also includes various design-for-manufacturability (DFM), design-for-reliability (DFR), and design-for-testability (DFT) techniques that are considered critical to the 3D IC design process. Describes design issues and solutions for high performance and low power 3D ICs, such as the pros/cons of regular and irregular placement of TSVs, Steiner routing, buffer insertion, low power 3D clock routing, power delivery network design and clock design for pre-bond testability. Discusses topics in design-for-electrical-reliability for 3D ICs, such as TSV-to-TSV coupling, current crowding at the wire-to-TSV junction and the e...

  14. A low power 2.4 GHz transceiver for ZigBee applications

    Institute of Scientific and Technical Information of China (English)

    Liu Weiyang; Chen Jingjing; Wang Haiyong; Wu Nanjian

    2013-01-01

    This paper presents a low power 2.4 GHz transceiver for ZigBee applications.This transceiver adopts low power system architecture with a low-IF receiver and a direct-conversion transmitter.The receiver consists of a new low noise amplifier (LNA) with a noise cancellation function,a new inverter-based variable gain complex filter (VGCF) for image rejection,a passive quadrature mixer,and a decibel linear programmable gain amplifier (PGA).The transmitter adopts a quadrature mixer and a class-B mode variable gain power amplifier (PA) to reduce power consumption.This transceiver is implemented in 0.18μm CMOS technology.The receiver achieves-95 dBm of sensitivity,28 dBc of image rejection,and-8 dBm of third-order input intercept point (IIP3).The transmitter can deliver a maximum of +3 dBm output power with PA efficiency of 30%.The whole chip area is less than 4.32 mm2.It only consumes 12.63 mW in receiving mode and 14.22 mW in transmitting mode,respectively.

  15. A low power 2.4 GHz transceiver for ZigBee applications

    Science.gov (United States)

    Weiyang, Liu; Jingjing, Chen; Haiyong, Wang; Nanjian, Wu

    2013-08-01

    This paper presents a low power 2.4 GHz transceiver for ZigBee applications. This transceiver adopts low power system architecture with a low-IF receiver and a direct-conversion transmitter. The receiver consists of a new low noise amplifier (LNA) with a noise cancellation function, a new inverter-based variable gain complex filter (VGCF) for image rejection, a passive quadrature mixer, and a decibel linear programmable gain amplifier (PGA). The transmitter adopts a quadrature mixer and a class-B mode variable gain power amplifier (PA) to reduce power consumption. This transceiver is implemented in 0.18 μm CMOS technology. The receiver achieves -95 dBm of sensitivity, 28 dBc of image rejection, and -8 dBm of third-order input intercept point (IIP3). The transmitter can deliver a maximum of +3 dBm output power with PA efficiency of 30%. The whole chip area is less than 4.32 mm2. It only consumes 12.63 mW in receiving mode and 14.22 mW in transmitting mode, respectively.

  16. A low-power current self-adjusted VCO using a bottom PMOS current source

    Science.gov (United States)

    Zhixiong, Sheng; Fengqi, Yu

    2014-09-01

    This paper presents the design and implementation of a current self-adjusted VCO with low power consumption. In the proposed VCO, a bottom PMOS current source instead of a top one is adopted to decrease the tail noise. A current self-adjusted technique without additional external control signals is taken to ensure the VCO starts up in the whole band while keeping the power consumption relatively low. Meanwhile, the phase noise of the VCO at the low frequency (high Cvar) can be reduced by the technique. The circuit is implemented in 0.18 μm CMOS technology. The proposed VCO exhibits low power consumption of < 1.6 mW at a 1.5 V supply voltage and a tuning range from 11.79 to 12.53 GHz. The measured phase noise at 1 MHz offset from the frequency 11.79 GHz is -104.7 dBc/Hz, and the corresponding FOM is -184.2 dBc/Hz.

  17. MOCA: A Low-Power, Low-Cost Motion Capture System Based on Integrated Accelerometers

    Directory of Open Access Journals (Sweden)

    Elisabetta Farella

    2007-01-01

    Full Text Available Human-computer interaction (HCI and virtual reality applications pose the challenge of enabling real-time interfaces for natural interaction. Gesture recognition based on body-mounted accelerometers has been proposed as a viable solution to translate patterns of movements that are associated with user commands, thus substituting point-and-click methods or other cumbersome input devices. On the other hand, cost and power constraints make the implementation of a natural and efficient interface suitable for consumer applications a critical task. Even though several gesture recognition solutions exist, their use in HCI context has been poorly characterized. For this reason, in this paper, we consider a low-cost/low-power wearable motion tracking system based on integrated accelerometers called motion capture with accelerometers (MOCA that we evaluated for navigation in virtual spaces. Recognition is based on a geometric algorithm that enables efficient and robust detection of rotational movements. Our objective is to demonstrate that such a low-cost and a low-power implementation is suitable for HCI applications. To this purpose, we characterized the system from both a quantitative point of view and a qualitative point of view. First, we performed static and dynamic assessment of movement recognition accuracy. Second, we evaluated the effectiveness of user experience using a 3D game application as a test bed.

  18. A Sub Threshold Source Coupled Logic Based Design of Low Power CMOS Analog Multiplexer

    Directory of Open Access Journals (Sweden)

    G.Deepika

    2014-08-01

    Full Text Available A novel approach for designing Ultra Low Power and wide dynamic range circuit for multiplexing analog signals is presented. The design operates in weak i nversion (Sub threshold region and uses Source - Coupled Logic ( SCL circuit. The bias current of t he SCL gates is varied to scale down linearly the p ower consumption and the operating frequency. The multip lexer design employs CMOS transistors as transmission gate with dynamic threshold voltage. T he design exhibits low power dissipation, high dynamic range and good linearity. The design was im plemented in 180 nm technology and was operated at a supply voltage of 400 mV with a bias current rang ing in the order of few Pico-amperes. The ON and OFF resistance of the transmission gate achieved we re 27 ohms and 10 M ohms respectively. The power dissipation achieved is around 0.79 μ W for a dynami c range of 1μ V to 0.4 V.

  19. Low-Power Analog Processing for Sensing Applications: Low-Frequency Harmonic Signal Classification

    Directory of Open Access Journals (Sweden)

    Sina Balkir

    2013-07-01

    Full Text Available A low-power analog sensor front-end is described that reduces the energy required to extract environmental sensing spectral features without using Fast Fouri´er Transform (FFT or wavelet transforms. An Analog Harmonic Transform (AHT allows selection of only the features needed by the back-end, in contrast to the FFT, where all coefficients must be calculated simultaneously. We also show that the FFT coefficients can be easily calculated from the AHT results by a simple back-substitution. The scheme is tailored for low-power, parallel analog implementation in an integrated circuit (IC. Two different applications are tested with an ideal front-end model and compared to existing studies with the same data sets. Results from the military vehicle classification and identification of machine-bearing fault applications shows that the front-end suits a wide range of harmonic signal sources. Analog-related errors are modeled to evaluate the feasibility of and to set design parameters for an IC implementation to maintain good system-level performance. Design of a preliminary transistor-level integrator circuit in a 0:µm complementary metal-oxide-silicon (CMOS integrated circuit process showed the ability to use online self-calibration to reduce fabrication errors to a sufficiently low level. Estimated power dissipation is about three orders of magnitude less than similar vehicle classification systems that use commercially available FFT spectral extraction.

  20. Design and Implementation of RF Energy Harvesting System for Low-Power Electronic Devices

    Science.gov (United States)

    Uzun, Yunus

    2016-08-01

    Radio frequency (RF) energy harvester systems are a good alternative for energizing of low-power electronics devices. In this work, an RF energy harvester is presented to obtain energy from Global System for Mobile Communications (GSM) 900 MHz signals. The energy harvester, consisting of a two-stage Dickson voltage multiplier circuit and L-type impedance matching circuits, was designed, simulated, fabricated and tested experimentally in terms of its performance. Simulation and experimental works were carried out for various input power levels, load resistances and input frequencies. Both simulation and experimental works have been carried out for this frequency band. An efficiency of 45% is obtained from the system at 0 dBm input power level using the impedance matching circuit. This corresponds to the power of 450 μW and this value is sufficient for many low-power devices. The most important parameters affecting the efficiency of the RF energy harvester are the input power level, frequency band, impedance matching and voltage multiplier circuits, load resistance and the selection of diodes. RF energy harvester designs should be optimized in terms of these parameters.

  1. Design of Low Power Phase Locked Loop (PLL Using 45NM VLSI Technology

    Directory of Open Access Journals (Sweden)

    Ms. Ujwala A. Belorkar

    2010-06-01

    Full Text Available Power has become one of the most important paradigms of design convergence for multigigahertz communication systems such as optical data links, wireless products, microprocessor &ASIC/SOC designs. POWER consumption has become a bottleneck in microprocessor design. The coreof a microprocessor, which includes the largest power density on the microprocessor. In an effort toreduce the power consumption of the circuit, the supply voltage can be reduced leading to reduction ofdynamic and static power consumption. Lowering the supply voltage, however, also reduces theperformance of the circuit, which is usually unacceptable. One way to overcome this limitation, availablein some application domains, is to replicate the circuit block whose supply voltage is being reduced inorder to maintain the same throughput .This paper introduces a design aspects for low power phaselocked loop using VLSI technology. This phase locked loop is designed using latest 45nm processtechnology parameters, which in turn offers high speed performance at low power. The main noveltyrelated to the 45nm technology such as the high-k gate oxide ,metal-gate and very low-k interconnectdielectric described. VLSI Technology includes process design, trends, chip fabrication, real circuitparameters, circuit design, electrical characteristics, configuration building blocks, switching circuitry,translation onto silicon, CAD, practical experience in layout design

  2. Multicolored, Low-Power, Flexible Electrochromic Devices Based on Ion Gels.

    Science.gov (United States)

    Moon, Hong Chul; Kim, Chang-Hyun; Lodge, Timothy P; Frisbie, C Daniel

    2016-03-09

    Ion gels composed of a copolymer and a room temperature ionic liquid are versatile solid-state electrolytes with excellent features including high ionic conductivity, nonvolatility, easily tunable mechanical properties, good flexibility and solution processability. Ion gels can be functionalized by incorporating redox-active species such as electrochemiluminescent (ECL) luminophores or electrochromic (EC) dyes. Here, we enhance the functionality of EC gels for realizing multicolored EC devices (ECDs), either by controlling the chemical equilibrium between a monomer and dimer of a colored EC species, or by modifying the molecular structures of the EC species. All devices in this work are conveniently fabricated by a "cut-and-stick" strategy, and require very low power for maintaining the colored state [i.e., 90 μW/cm(2) (113 μA/cm(2) at -0.8 V) for blue, 4 μW/cm(2) (10 μA/cm(2) at -0.4 V) for green, and 32 μW/cm(2) (79 μA/cm(2) at -0.4 V) for red ECD]. We also successfully demonstrate a patterned, multicolored, flexible ECD on plastic. Overall, these results suggest that gel-based ECDs have significant potential as low power displays in printed electronics powered by thin-film batteries.

  3. A scalable and low power VLIW DSP core for embedded system design

    Institute of Scientific and Technical Information of China (English)

    Sheraz Anjum; CHEN Jie; HAN Liang; LIN Chuan; ZHANG Xiao-xiao; SU Ye-hua; Chip Cheng

    2008-01-01

    Aims to provide the block architecture of CoStar3400 DSP that is a high performance, low power and scalable VLIW DSP core, it efficiently deployed a variable-length execution set (VLES) execution model which utilizes the maximum parallelism by allowing multiple address generations and data arithmetic logic units to exe-cute multiple instructions in a single clock cycle. The scalability was provided mainly in using more or less num-ber of functional units according to the intended application. Low power support was added by careful architectur-al design techniques such as fine-grain clock gating and activation of only the required number of control signals at each stage of the pipeline. The said features of the core make it a suitable candidate for many SoC configurations,especially for compute intensive applications such as wire-line and wireless communications, including infrastruc-ture and subscriber communications. The embedded system designers can efficiently use the scalability and VLIW features of the core by scaling the number of execution units according to specific needs of the application to effec-tively reduce the power consumption, chip area and time to market the intended final product.

  4. Low-power laser irradiation inhibits amyloid beta-induced cell apoptosis

    Science.gov (United States)

    Zhang, Heng; Wu, Shengnan

    2011-03-01

    The deposition and accumulation of amyloid-β-peptide (Aβ) in the brain are considered a pathological hallmark of Alzheimer's disease(AD). Apoptosis is a contributing pathophysiological mechanism of AD. Low-power laser irradiation (LPLI), a non-damage physical therapy, which has been used clinically for decades of years, is shown to promote cell proliferation and prevent apoptosis. Recently, low-power laser irradiation (LPLI) has been applied to moderate AD. In this study, Rat pheochromocytoma (PC12) cells were treated with amyloid beta 25-35 (Aβ25-35) for induction of apoptosis before LPLI treatment. We measured cell viability with CCK-8 according to the manufacture's protocol, the cell viability assays show that low fluence of LPLI (2 J/cm2 ) could inhibit the cells apoptosis. Then using statistical analysis of proportion of apoptotic cells by flow cytometry based on Annexin V-FITC/PI, the assays also reveal that low fluence of LPLI (2 J/cm2 ) could inhibit the Aβ-induced cell apoptosis. Taken together, we demonstrated that low fluence of LPLI (2 J/cm2 ) could inhibit the Aβ-induced cell apoptosis, these results directly point to a therapeutic strategy for the treatment of AD through LPLI.

  5. A Low Power VITERBI Decoder Design With Minimum Transition Hybrid Register Exchange Processing For Wireless Applications

    Directory of Open Access Journals (Sweden)

    S. L. Haridas

    2010-12-01

    Full Text Available This work proposes the low power implementation of Viterbi Decoder. Majority of viterbi decoder designs in the past use simple Register Exchange or Traceback method to achieve very high speed and low power decoding respectively, but it suffers from both complex routing and high switching activity.Here simplification is made in survivor memory unit by storing only m-1 bits to identify previous state in the survivor path, and by assigning m-1 registers to decision vectors. This approach eliminates unnecessary shift operations. Also for storing the decoded data only half memory is required than register exchange method. In this paper Hybrid approach that combines both Traceback and Register Exchange schemes has been applied to the viterbi decoder design. By using distance properties of encoder we further modified to minimum transition hybrid register exchange method. It leads to lower dynamic power consumption because of lower switching activity. Dynamic power estimation obtained through gate level simulation indicates that the proposed design reduces the power dissipation of a conventional viterbi decoder design by 30%.

  6. A Low Power VITERBI Decoder Design With Minimum Transition Hybrid Register Exchange Processing For Wireless Applications

    Directory of Open Access Journals (Sweden)

    S. L. Haridas

    2010-12-01

    Full Text Available This work proposes the low power implementation of Viterbi Decoder. Majority of viterbi decoder designs in the past use simple Register Exchange or Trace back method to achieve very high speed and low power decoding respectively, but it suffers from both complex routing and high switching activity.Here simplification is made in survivor memory unit by storing only m-1 bits to identify previous state in the survivor path, and by assigning m-1 registers to decision vectors. This approach eliminates unnecessary shift operations. Also for storing the decoded data only half memory is required than register exchange method. In this paper Hybrid approach that combines both Trace back and Register Exchange schemes has been applied to the viterbi decoder design. By using distance properties of encoder we further modified to minimum transition hybrid register exchange method. It leads to lower dynamic power consumption because of lower switching activity. Dynamic power estimation obtained through gate level simulation indicates that the proposed design reduces the power dissipation of a conventional viterbi decoder design by 30%.

  7. Design of a compact low-power human-computer interaction equipment for hand motion

    Science.gov (United States)

    Wu, Xianwei; Jin, Wenguang

    2017-01-01

    Human-Computer Interaction (HCI) raises demand of convenience, endurance, responsiveness and naturalness. This paper describes a design of a compact wearable low-power HCI equipment applied to gesture recognition. System combines multi-mode sense signals: the vision sense signal and the motion sense signal, and the equipment is equipped with the depth camera and the motion sensor. The dimension (40 mm × 30 mm) and structure is compact and portable after tight integration. System is built on a module layered framework, which contributes to real-time collection (60 fps), process and transmission via synchronous confusion with asynchronous concurrent collection and wireless Blue 4.0 transmission. To minimize equipment's energy consumption, system makes use of low-power components, managing peripheral state dynamically, switching into idle mode intelligently, pulse-width modulation (PWM) of the NIR LEDs of the depth camera and algorithm optimization by the motion sensor. To test this equipment's function and performance, a gesture recognition algorithm is applied to system. As the result presents, general energy consumption could be as low as 0.5 W.

  8. Reliability and availability analysis of low power portable direct methanol fuel cells

    Energy Technology Data Exchange (ETDEWEB)

    Sisworahardjo, N.S. [School of Electrical Engineering and Informatics, Bandung Institute of Technology, Bandung, 40132 (Indonesia); Department of Electrical and Computer Engineering, University of South Alabama, Mobile, AL 36688 (United States); Alam, M.S.; Aydinli, G. [Department of Electrical and Computer Engineering, University of South Alabama, Mobile, AL 36688 (United States)

    2008-03-01

    This paper presents a methodology for modeling and calculating the reliability and availability of low power portable direct methanol fuel cells (DMFCs). System reliability and availability are critical factors for improving market acceptance and for determining the competitiveness of the low power DMFC. Two techniques have been used for analyzing the system reliability and availability requirements for various system components. Reliability block diagram (RBD) is formed based on the failure rates of irreparable system components. A state-space method is developed to calculate system availability using the Markov model (MM). The state-space method incorporates three different states - operational, derated, and fully faulted states. Since most system components spend their lifetime in performing normal functional task, this research is focused mainly on this operational period. The failure and repair rates for repairable DMFC systems are estimated on the basis of a homogeneous Poisson process (HPP) and exponential distribution. Extensive analytical modeling and simulation study has been performed to verify the effectiveness of the proposed technique. (author)

  9. Reliability and availability analysis of low power portable direct methanol fuel cells

    Science.gov (United States)

    Sisworahardjo, N. S.; Alam, M. S.; Aydinli, G.

    This paper presents a methodology for modeling and calculating the reliability and availability of low power portable direct methanol fuel cells (DMFCs). System reliability and availability are critical factors for improving market acceptance and for determining the competitiveness of the low power DMFC. Two techniques have been used for analyzing the system reliability and availability requirements for various system components. Reliability block diagram (RBD) is formed based on the failure rates of irreparable system components. A state-space method is developed to calculate system availability using the Markov model (MM). The state-space method incorporates three different states-operational, derated, and fully faulted states. Since most system components spend their lifetime in performing normal functional task, this research is focused mainly on this operational period. The failure and repair rates for repairable DMFC systems are estimated on the basis of a homogeneous Poisson process (HPP) and exponential distribution. Extensive analytical modeling and simulation study has been performed to verify the effectiveness of the proposed technique.

  10. Controlling the phase locking of stochastic magnetic bits for ultra-low power computation

    Science.gov (United States)

    Mizrahi, Alice; Locatelli, Nicolas; Lebrun, Romain; Cros, Vincent; Fukushima, Akio; Kubota, Hitoshi; Yuasa, Shinji; Querlioz, Damien; Grollier, Julie

    2016-07-01

    When fabricating magnetic memories, one of the main challenges is to maintain the bit stability while downscaling. Indeed, for magnetic volumes of a few thousand nm3, the energy barrier between magnetic configurations becomes comparable to the thermal energy at room temperature. Then, switches of the magnetization spontaneously occur. These volatile, superparamagnetic nanomagnets are generally considered useless. But what if we could use them as low power computational building blocks? Remarkably, they can oscillate without the need of any external dc drive, and despite their stochastic nature, they can beat in unison with an external periodic signal. Here we show that the phase locking of superparamagnetic tunnel junctions can be induced and suppressed by electrical noise injection. We develop a comprehensive model giving the conditions for synchronization, and predict that it can be achieved with a total energy cost lower than 10‑13 J. Our results open the path to ultra-low power computation based on the controlled synchronization of oscillators.

  11. Low-power wireless ECG acquisition and classification system for body sensor networks.

    Science.gov (United States)

    Lee, Shuenn-Yuh; Hong, Jia-Hua; Hsieh, Cheng-Han; Liang, Ming-Chun; Chang Chien, Shih-Yu; Lin, Kuang-Hao

    2015-01-01

    A low-power biosignal acquisition and classification system for body sensor networks is proposed. The proposed system consists of three main parts: 1) a high-pass sigma delta modulator-based biosignal processor (BSP) for signal acquisition and digitization, 2) a low-power, super-regenerative on-off keying transceiver for short-range wireless transmission, and 3) a digital signal processor (DSP) for electrocardiogram (ECG) classification. The BSP and transmitter circuits, which are the body-end circuits, can be operated for over 80 days using two 605 mAH zinc-air batteries as the power supply; the power consumption is 586.5 μW. As for the radio frequency receiver and DSP, which are the receiving-end circuits that can be integrated in smartphones or personal computers, power consumption is less than 1 mW. With a wavelet transform-based digital signal processing circuit and a diagnosis control by cardiologists, the accuracy of beat detection and ECG classification are close to 99.44% and 97.25%, respectively. All chips are fabricated in TSMC 0.18-μm standard CMOS process.

  12. Low-power secure body area network for vital sensors toward IEEE802.15.6.

    Science.gov (United States)

    Kuroda, Masahiro; Qiu, Shuye; Tochikubo, Osamu

    2009-01-01

    Many healthcare/medical services have started using personal area networks, such as Bluetooth and ZigBee; these networks consist of various types of vital sensors. These works focus on generalized functions for sensor networks that expect enough battery capacity and low-power CPU/RF (Radio Frequency) modules, but less attention to easy-to-use privacy protection. In this paper, we propose a commercially-deployable secure body area network (S-BAN) with reduced computational burden on a real sensor that has limited RAM/ROM sizes and CPU/RF power consumption under a light-weight battery. Our proposed S-BAN provides vital data ordering among sensors that are involved in an S-BAN and also provides low-power networking with zero-administration security by automatic private key generation. We design and implement the power-efficient media access control (MAC) with resource-constraint security in sensors. Then, we evaluate the power efficiency of the S-BAN consisting of small sensors, such as an accessory type ECG and ring-type SpO2. The evaluation of power efficiency of the S-BAN using real sensors convinces us in deploying S-BAN and will also help us in providing feedbacks to the IEEE802.15.6 MAC, which will be the standard for BANs.

  13. IEEE-802.15.4-based low-power body sensor node with RF energy harvester.

    Science.gov (United States)

    Tran, Thang Viet; Chung, Wan-Young

    2014-01-01

    This paper proposes the design and implementation of a low-voltage and low-power body sensor node based on the IEEE 802.15.4 standard to collect electrocardiography (ECG) and photoplethysmography (PPG) signals. To achieve compact size, low supply voltage, and low power consumption, the proposed platform is integrated into a ZigBee mote, which contains a DC-DC booster, a PPG sensor interface module, and an ECG front-end circuit that has ultra-low current consumption. The input voltage of the proposed node is very low and has a wide range, from 0.65 V to 3.3 V. An RF energy harvester is also designed to charge the battery during the working mode or standby mode of the node. The power consumption of the proposed node reaches 14 mW in working mode to prolong the battery lifetime. The software is supported by the nesC language under the TinyOS environment, which enables the proposed node to be easily configured to function as an individual health monitoring node or a node in a wireless body sensor network (BSN). The proposed node is used to set up a wireless BSN that can simultaneously collect ECG and PPG signals and monitor the results on the personal computer.

  14. Architectural optimizations for low-power K-best MIMO decoders

    KAUST Repository

    Mondal, Sudip

    2009-09-01

    Maximum-likelihood (ML) detection for higher order multiple-input-multiple-output (MIMO) systems faces a major challenge in computational complexity. This limits the practicality of these systems from an implementation point of view, particularly for mobile battery-operated devices. In this paper, we propose a modified approach for MIMO detection, which takes advantage of the quadratic-amplitude modulation (QAM) constellation structure to accelerate the detection procedure. This approach achieves low-power operation by extending the minimum number of paths and reducing the number of required computations for each path extension, which results in an order-of-magnitude reduction in computations in comparison with existing algorithms. This paper also describes the very-large-scale integration (VLSI) design of the low-power path metric computation unit. The approach is applied to a 4 × 4, 64-QAM MIMO detector system. Results show negligible performance degradation compared with conventional algorithms while reducing the complexity by more than 50%. © 2009 IEEE.

  15. Ultra low power CMOS-based sensor for on-body radiation dose measurements

    KAUST Repository

    Arsalan, Muhammad

    2012-03-01

    For the first time, a dosimeter employing two floating gate radiation field effect transistors (FGRADFET) and operating at mere 0.1 V is presented. The novel dosimeter requires no power during irradiation and consumes only 1 μ Wduring readout. Besides the low power operation, structural changes at the device level have enhanced the sensitivity of the dosimeter considerably as compared to previous designs. The dosimeter is integrated with a wireless transmitter chip, thus eliminating all unwanted communication and power cables. It has been realized monolithically in DALSA\\'s 0.8 μ m complementary metal-oxide-semiconductor process and characterized with X-ray and γ-ray sources. A maximum sensitivity of 5 mV/rad for X-rays and 1.1 mV/rad for gamma;-rays have been achieved in measurements. Due to its small size, low-power, and wireless operation, the design is highly suitable for miniaturized, wearable, and battery operated dosimeters intended for radiotherapy and space applications. © 2012 IEEE.

  16. Role of PKC isozymes in low-power light-stimulated proliferation of cultured skin cells

    Science.gov (United States)

    Grossman, Nili; Kleitman, Vered; Meller, Julia; Kaufmann, Roland; Akgun, Nermin; Ruck, Angelika; Livneh, Etta; Lubart, Rachel

    2000-11-01

    Exposure of cultured skin cells to low power visible light leads to a transiently stimulated proliferation. Facilitation of this response requires the presence of active PKC, elevation of intracellular calcium, and involves reactive oxygen species. In the present study, the role of PKC(alpha) and PCK(eta) was examined using paired murine fibroblasts, differing in the level of these isozymes expression. The ability of the cells to respond to low power UVA light or HeNe laser by stimulated proliferation was correlated with an active state or overexpression of PKC(alpha) , but not PKC(eta) . A parallel response was obtained in cells that were loaded with A1PcS4 before photosensitization. Whenever this latter treatment caused a light-stimulated inhibition, it was accompanied by the intracellular calcium and photosensitizer dynamics typical of the effect of PDT on rate epithelial cells. Accordingly, added antioxidants that suppressed light-stimulated proliferation also suppressed this light-stimulated inhibition. The model systems employed in this study are the first to demonstrate the specific effect of PKC isozymes on light-stimulated proliferation, in relation to oxidative stress, and indicate their dual role in light-tissue interaction.

  17. Shutdown and low-power operation at commercial nuclear power plants in the United States. Final report

    Energy Technology Data Exchange (ETDEWEB)

    1993-09-01

    The report contains the results of the NRC Staff`s evaluation of shutdown and low-power operations at US commercial nuclear power plants. The report describes studies conducted by the staff in the following areas: Operating experience related to shutdown and low-power operations, probabilistic risk assessment of shutdown and low-power conditions and utility programs for planning and conducting activities during periods the plant is shut down. The report also documents evaluations of a number of technical issues regarding shutdown and low-power operations performed by the staff, including the principal findings and conclusions. Potential new regulatory requirements are discussed, as well as potential changes in NRC programs. A draft report was issued for comment in February 1992. This report is the final version and includes the responses to the comments along with the staff regulatory analysis of potential new requirements.

  18. Low Power, Small Form Factor, High Performance EVA Radio Employing Micromachined Contour Mode Piezoelectric Resonators and Filters Project

    Data.gov (United States)

    National Aeronautics and Space Administration — In Phase I Harmonic Devices proposes to investigate the feasibility of a low-power, low-volume, lightweight, frequency agile, and fault tolerant EVA radio based on...

  19. A Low-Power Integrated Smart Sensor with on-Chip Real-Time Image Processing Capabilities

    Directory of Open Access Journals (Sweden)

    Barbaro Massimo

    2005-01-01

    Full Text Available A low-power, CMOS retina with real-time, pixel-level processing capabilities is presented. Features extraction and edge-enhancement are implemented with fully programmable 1D Gabor convolutions. An equivalent computation rate of 3 GOPS is obtained at the cost of very low-power consumption ( W per pixel, providing real-time performances ( microseconds for overall computation, . Experimental results from the first realized prototype show a very good matching between measures and expected outputs.

  20. Design and Development of Low Power Wireless Sensor System for Measurement and Monitoring of Bio-Medical Parameters

    Directory of Open Access Journals (Sweden)

    D. Vishnu Vardhan, K. Soundara Rajan, Y. Narasimha Murthy

    2013-07-01

    Full Text Available This paper presents the design and development of a low power embedded system for the measurement and monitoring of physiological parameters like body temperature, respiration, blood pressure and ECG. The design is developed around a low power microcontroller MSP430 from Texas Instruments. A wireless sensor module is used to transfer the data from microcontroller to the PC and a graphical user interface (GUI is developed to display the measured data in the graphical form.

  1. Measuring Atmospheric Emissions of CH4 from Permafrost with Remote Low-Power Automated Stations

    Science.gov (United States)

    Burba, G. G.; Anderson, T.; Haapanala, S.; Mammarella, I.; McDermitt, D. K.; Oechel, W. C.; Peltola, O.; Rinne, J.; Schreiber, P.; Sturtevant, C. S.; Zulueta, R. C.

    2012-12-01

    Permafrost regions accumulate considerable amounts of organic materials held in anaerobic conditions. This leads to production and storage of CH4 in the upper layers of bedrock and soil, under the ice, and at lake bottoms. Presently, the permafrost is undergoing significant change in response to warming trends, and may become a significant source of CH4 release into the atmosphere. Direct measurements of CH4 emission in permafrost regions have most often been made with static chambers, and few were made using closed-path eddy flux stations. Although both approaches have advantages, they also have significant limitations. Static chamber measurements are discrete in time and space, and are particularly difficult to use over a polygonal tundra with highly non-uniform micro-topography and an active water layer. Closed-path gas analyzers for measuring CH4 eddy fluxes employ advanced laser technologies, but require high flow rates at significantly reduced optical cell pressures to provide adequate response time and sharpen absorption features. As a result, they require vacuum pumps and 400-1500 Watts of system power and can weigh over 100-200 lbs, restricting practical applicability for remote studies. As a result, spatial coverage of eddy flux measurements of CH4 in cold regions remains limited. Alternatively, open-path stations allow CH4 flux measurements at normal pressure without the need for a pump. As a result, the measurements can be done with very low-power (7-10 Watts) lightweight (11-12 lbs) arrangement permitting solar- and wind-powered deployments in remote sites using small automated stations. Such stations are important for a number of ecosystems (rice fields, landfills, wetlands, cattle yards), but are especially important for permafrost regions where grid power and access roads are generally not available. Emerging new research on CH4 flux measurements using automated low-power stations equipped with high-speed open-path CH4 analyzers are presented for a

  2. An Extremely Low Power Quantum Optical Communication Link for Autonomous Robotic Explorers

    Science.gov (United States)

    Lekki, John; Nguyen, Quang-Viet; Bizon, Tom; Nguyen, Binh; Kojima, Jun

    2007-01-01

    One concept for planetary exploration involves using many small robotic landers that can cover more ground than a single conventional lander. In addressing this vision, NASA has been challenged in the National Nanotechnology Initiative to research the development of miniature robots built from nano-sized components. These robots have very significant challenges, such as mobility and communication, given the small size and limited power generation capability. The research presented here has been focused on developing a communications system that has the potential for providing ultra-low power communications for robots such as these. In this paper an optical communications technique that is based on transmitting recognizable sets of photons is presented. Previously pairs of photons that have an entangled quantum state have been shown to be recognizable in ambient light. The main drawback to utilizing entangled photons is that they can only be generated through a very energy inefficient nonlinear process. In this paper a new technique that generates sets of photons from pulsed sources is described and an experimental system demonstrating this technique is presented. This technique of generating photon sets from pulsed sources has the distinct advantage in that it is much more flexible and energy efficient, and is well suited to take advantage of the very high energy efficiencies that are possible when using nano scale sources. For these reasons the communication system presented in this paper is well suited for use in very small, low power landers and rovers. In this paper a very low power optical communications system for miniature robots, as small as 1 cu cm is addressed. The communication system is a variant of photon counting communications. Instead of counting individual photons the system only counts the arrival of time coincident sets of photons. Using sets of photons significantly decreases the bit error rate because they are highly identifiable in the

  3. Super low power consumption middle infrared LED-PD optopairs for chemical sensing

    Science.gov (United States)

    Stoyanov, Nikolay D.; Salikhov, Khafiz M.; Kalinina, Karina V.; Kizhaev, Sergey S.; Chernyaev, Anton V.

    2014-03-01

    The new photodiodes with cut-off wavelengths at 3640 nm, 4600 nm and 5150 nm have been recently developed in a high-tech company LED Microsensor NT (St.Petersburg, Russia) in cooperation with Aalto University (Espoo, Finland). Photodiode (PD) heterostructures InAsSb/InAsSbP were grown by MOVPE on InAs substrates. For the PDs with a cutoff wavelength at 3640 nm at room temperature the responsivity at 3300 nm reached 1.46 A/W and, detectivity was 1.56*1010 cm.Hz1/2/W. For the PDs with a cut-off 4600 nm the same parameters were: 1.91 A/W and 6.7*109 cm.Hz1/2/W respectively (lambda=4100 nm). For the third type of PDs with a cut-off at 5150 nm responsivity was 0.29 A/W, detectivity was 4.2*108 cm.Hz1/2/W (lambda=5000 nm). Creation of photodiodes for the spectral range 2500-5200 nm with acceptable efficiency in photovoltaic operation mode (with no reverse bias) and using them in a pair with spectrally matched LEDs driven by very short current pulses allows developing optical cells with very low power consumption (less than 1 mW). Small size of the LED and PD dies (0.4-0.8 mm) and low heating makes it possible to design very thin optical cells (less than 2 mm) for measuring CH4, CO2, CO, H2O and other substances [1]. Mounting of a few LED dies that emit at different wavelengths in such a small cell allows measuring different chemical substances simultaneously. Direct coating of optical filters on the LED or PD surface during post-growth process allows improving selectivity and sensitivity of the sensor. Super low power consumption of the diode-based optical cells makes them promising candidates for the wireless mesh sensor networks for various gas monitoring purposes as well as for HVAC systems. Combination of the low power consumption and thin size of the cells opens possibility to embed them in mobile devices.

  4. A Study of LoRa: Long Range & Low Power Networks for the Internet of Things

    Directory of Open Access Journals (Sweden)

    Aloÿs Augustin

    2016-09-01

    Full Text Available LoRa is a long-range, low-power, low-bitrate, wireless telecommunications system, promoted as an infrastructure solution for the Internet of Things: end-devices use LoRa across a single wireless hop to communicate to gateway(s, connected to the Internet and which act as transparent bridges and relay messages between these end-devices and a central network server. This paper provides an overview of LoRa and an in-depth analysis of its functional components. The physical and data link layer performance is evaluated by field tests and simulations. Based on the analysis and evaluations, some possible solutions for performance enhancements are proposed.

  5. Low Power Thermodynamic Solar Energy Conversion: Coupling of a Parabolic Trough Concentrator and an Ericsson Engine

    Directory of Open Access Journals (Sweden)

    Pascal Stouffs

    2007-03-01

    Full Text Available This paper considers thermodynamic conversion of solar energy into electric energy (up to maximum 50 kWe, presenting a very brief review of the possible systems: the ‘Dish/Stirling’ technology, which relies on high temperature Stirling engines and requires high solar energy; low temperature differential thermal engine using direct solar energy without any concentration but with very low power per unit volume or unit mass of the system; and the intermediate solar energy concentration ratio.A theoretical investigation on the coupling of a two-stage parabolic trough concentrator with a reciprocating Joule cycle air engine (i.e. an Ericsson hot air engine in open cycle is presented. It is shown that there is an optimal operating point that maximises the mechanical power produced by the thermal engine. The interest of coupling a simple, low cost parabolic trough and a simple, low technology, mid-DT Ericsson engine is confirmed.

  6. A Low-Power Scalable Stream Compute Accelerator for General Matrix Multiply (GEMM

    Directory of Open Access Journals (Sweden)

    Antony Savich

    2014-01-01

    play an important role in determining the performance of such applications. This paper proposes a novel efficient, highly scalable hardware accelerator that is of equivalent performance to a 2 GHz quad core PC but can be used in low-power applications targeting embedded systems requiring high performance computation. Power, performance, and resource consumption are demonstrated on a fully-functional prototype. The proposed hardware accelerator is 36× more energy efficient per unit of computation compared to state-of-the-art Xeon processor of equal vintage and is 14× more efficient as a stand-alone platform with equivalent performance. An important comparison between simulated system estimates and real system performance is carried out.

  7. Low-Power Maximum a Posteriori (MAP Algorithm for WiMAX Convolutional Turbo Decoder

    Directory of Open Access Journals (Sweden)

    Chitralekha Ngangbam

    2013-05-01

    Full Text Available We propose to design a Low-Power Memory-Reduced Traceback MAP iterative decoding of convolutional turbo code (CTC which has large data access with large memories consumption and verify the functionality by using simulation tool. The traceback maximum a posteriori algorithm (MAP decoding provides the best performance in terms of bit error rate (BER and reduce the power consumption of the state metric cache (SMC without losing the correction performance. The computation and accessing of different metrics reduce the size of the SMC with no requires complicated reversion checker, path selection, and reversion flag cache. Radix-2*2 and radix-4 traceback structures provide a tradeoff between power consumption and operating frequency for double-binary (DB MAP decoding. These two traceback structures achieve an around 25% power reduction of the SMC, and around 12% power reduction of the DB MAP decoders for WiMAX standard

  8. Development of a low power Delay-Locked Loop in two 130 nm CMOS technologies

    Science.gov (United States)

    Firlej, M.; Fiutowski, T.; Idzik, M.; Moron, J.; Swientek, K.

    2016-02-01

    The design and measurement results of two low power DLL prototypes for applications in particle physics readout systems are presented. The DLLs were fabricated in two different 130 nm CMOS technologies, called process A and process B, giving the opportunity to compare these two CMOS processes. Both circuits generate 64 uniform clock phases and operate at similar frequency range, from 20 MHz up to 60 MHz (10 MHz - 90 MHz in process B). The period jitter of both DLLs is in the range 2.5 ps - 12.1 ps (RMS) and depends on the selected output phase. The complete DLL functionality was experimentally verified, confirming a very low and frequency scalable power consumption of around 0.7 mW at typical 40 MHz input. The DLL prototype, designed in process A, occupies 680 μm × 210 μm, while the same circuit designed in process B occupies 430 μm × 190 μm.

  9. A low-power VLSI implementation for variable length decoder in MPEG-1 Layer III

    Science.gov (United States)

    Tsai, Tsung-Han; Liu, Chun-Nan; Chen, Wen-Cheng

    2004-04-01

    MPEG Layer III (MP3) audio coding algorithm is a widely used audio coding standard. It involves several complex coding techniques and is therefore difficult to create an efficient architecture design. The variable length decoding (VLD) e.g. Huffman decoding, is an important part of MP3, which needs great amount of search and memory access operations. In this paper a data driven variable length decoding algorithm is presented, which exploits the signal statistics of variable length codes to reduce power and a two-level table lookup method is presented. The decoder was designed based on simplicity and low-cost, low power consumption while retaining the high efficiency requirements. The total power saving is about 67%.

  10. Low-Voltage, Low-Power, Organic Light-Emitting Transistors for Active Matrix Displays

    Science.gov (United States)

    McCarthy, M. A.; Liu, B.; Donoghue, E. P.; Kravchenko, I.; Kim, D. Y.; So, F.; Rinzler, A. G.

    2011-04-01

    Intrinsic nonuniformity in the polycrystalline-silicon backplane transistors of active matrix organic light-emitting diode displays severely limits display size. Organic semiconductors might provide an alternative, but their mobility remains too low to be useful in the conventional thin-film transistor design. Here we demonstrate an organic channel light-emitting transistor operating at low voltage, with low power dissipation, and high aperture ratio, in the three primary colors. The high level of performance is enabled by a single-wall carbon nanotube network source electrode that permits integration of the drive transistor and the light emitter into an efficient single stacked device. The performance demonstrated is comparable to that of polycrystalline-silicon backplane transistor-driven display pixels.

  11. Comparison and Digital Circuit Analysis Based on Low Power Subthreshold Dual Mode Logic

    Directory of Open Access Journals (Sweden)

    D.Naveen Kumar

    2014-03-01

    Full Text Available In this brief, we propose new low power techniques such as Variable body bias method. This technique reduces the leakage power by increasing the body to source voltage of the sleep transistor in the design. By reducing the leakage power overall power of the design is reduced. The proposed logic switches between the active mode and sleep mode. To reduce the leakage current in sleep mode, the body to source voltage of the sleep transistor increased. To increase the voltage of Sleep transistor another transistor is connected to it. Average power and delay are the parameters compared between proposed logic to their CMOS and Dual Mode Logic counter parts in 180-nm process.

  12. Low-power and shutdown models for the accident sequence precursor (ASP) program

    Energy Technology Data Exchange (ETDEWEB)

    Sattison, M.B.; Thatcher, T.A.; Knudsen, J.K. [Idaho National Engineering Lab., Idaho Falls, ID (United States)] [and others

    1997-02-01

    The US Nuclear Regulatory Commission (NRC) has been using full-power. Level 1, limited-scope risk models for the Accident Sequence Precursor (ASP) program for over fifteen years. These models have evolved and matured over the years, as have probabilistic risk assessment (PRA) and computer technologies. Significant upgrading activities have been undertaken over the past three years, with involvement from the Offices of Nuclear Reactor Regulation (NRR), Analysis and Evaluation of Operational Data (AEOD), and Nuclear Regulatory Research (RES), and several national laboratories. Part of these activities was an RES-sponsored feasibility study investigating the ability to extend the ASP models to include contributors to core damage from events initiated with the reactor at low power or shutdown (LP/SD), both internal events and external events. This paper presents only the LP/SD internal event modeling efforts.

  13. Miniature, low-power X-ray tube using a microchannel electron generator electron source

    Science.gov (United States)

    Elam, Wm. Timothy (Inventor); Kelliher, Warren C. (Inventor); Hershyn, William (Inventor); DeLong, David P. (Inventor)

    2011-01-01

    Embodiments of the invention provide a novel, low-power X-ray tube and X-ray generating system. Embodiments of the invention use a multichannel electron generator as the electron source, thereby increasing reliability and decreasing power consumption of the X-ray tube. Unlike tubes using a conventional filament that must be heated by a current power source, embodiments of the invention require only a voltage power source, use very little current, and have no cooling requirements. The microchannel electron generator comprises one or more microchannel plates (MCPs), Each MCP comprises a honeycomb assembly of a plurality of annular components, which may be stacked to increase electron intensity. The multichannel electron generator used enables directional control of electron flow. In addition, the multichannel electron generator used is more robust than conventional filaments, making the resulting X-ray tube very shock and vibration resistant.

  14. A Low-Complexity Euclidean Orthogonal LDPC Architecture for Low Power Applications.

    Science.gov (United States)

    Revathy, M; Saravanan, R

    2015-01-01

    Low-density parity-check (LDPC) codes have been implemented in latest digital video broadcasting, broadband wireless access (WiMax), and fourth generation of wireless standards. In this paper, we have proposed a high efficient low-density parity-check code (LDPC) decoder architecture for low power applications. This study also considers the design and analysis of check node and variable node units and Euclidean orthogonal generator in LDPC decoder architecture. The Euclidean orthogonal generator is used to reduce the error rate of the proposed LDPC architecture, which can be incorporated between check and variable node architecture. This proposed decoder design is synthesized on Xilinx 9.2i platform and simulated using Modelsim, which is targeted to 45 nm devices. Synthesis report proves that the proposed architecture greatly reduces the power consumption and hardware utilizations on comparing with different conventional architectures.

  15. Energy-filtered Electron Transport Structures for Low-power Low-noise 2-D Electronics.

    Science.gov (United States)

    Pan, Xuan; Qiu, Wanzhi; Skafidas, Efstratios

    2016-10-31

    In addition to cryogenic techniques, energy filtering has the potential to achieve high-performance low-noise 2-D electronic systems. Assemblies based on graphene quantum dots (GQDs) have been demonstrated to exhibit interesting transport properties, including resonant tunnelling. In this paper, we investigate GQDs based structures with the goal of producing energy filters for next generation lower-power lower-noise 2-D electronic systems. We evaluate the electron transport properties of the proposed GQD device structures to demonstrate electron energy filtering and the ability to control the position and magnitude of the energy passband by appropriate device dimensioning. We also show that the signal-to-thermal noise ratio performance of the proposed nanoscale device can be modified according to device geometry. The tunability of two-dimensional GQD structures indicates a promising route for the design of electron energy filters to produce low-power and low-noise electronics.

  16. Toward low-power electronics: tunneling phenomena in transition metal dichalcogenides.

    Science.gov (United States)

    Das, Saptarshi; Prakash, Abhijith; Salazar, Ramon; Appenzeller, Joerg

    2014-02-25

    In this article, we explore, experimentally, the impact of band-to-band tunneling on the electronic transport of double-gated WSe2 field-effect transistors (FETs) and Schottky barrier tunneling of holes in back-gated MoS2 FETs. We show that by scaling the flake thickness and the thickness of the gate oxide, the tunneling current can be increased by several orders of magnitude. We also perform numerical calculations based on Landauer formalism and WKB approximation to explain our experimental findings. Based on our simple model, we discuss the impact of band gap and effective mass on the band-to-band tunneling current and evaluate the performance limits for a set of dichalcogenides in the context of tunneling transistors for low-power applications. Our findings suggest that WTe2 is an excellent choice for tunneling field-effect transistors.

  17. A NEW APPROACH TO DESIGN LOW POWER CMOS FLASH A/D CONVERTER

    Directory of Open Access Journals (Sweden)

    Sudakar S. Chauhan

    2011-06-01

    Full Text Available In the present paper, a 4-bit flash analog to digital converter for low power SoC application is presented. CMOS inverter has been used as a comparator and by adjusting the ratio of channel width and length, the switching threshold of the CMOS inverter is varied to detect the input analog signal. The simulation results show that this proposed 4-bit flash ADC consumes about 12.4 mW at 200M sample/s with 3.3V supply voltage in TSMC 0.35 μm process. Compared with the traditional flash ADC, this proposed method can reduce about 78% in power consumption.

  18. Improved low-power semiconductor diode lasers for photodynamic therapy in veterinary medicine

    Science.gov (United States)

    Lee, Susanne M.; Mueller, Eduard K.; Van de Workeen, Brian C.; Mueller, Otward M.

    2001-05-01

    Cryogenically cooling semiconductor diode lasers provides higher power output, longer device lifetime, and greater monochromaticity. While these effects are well known, such improvements have not been quantified, and thus cryogenically operated semiconductor lasers have not been utilized in photodynamic therapy (PDT). We report quantification of these results from laser power meter and photospectrometer data. The emission wavelengths of these low power multiple quantum well semiconductor lasers were found to decrease and become more monochromatic with decreasing temperature. Significant power output improvements also were obtained at cryogenic temperatures. In addition, the threshold current, i.e. the current at which lasing begins, decreased with decreasing temperature. This lower threshold current combined with the increased power output produced dramatically higher device efficiencies. It is proposed that cryogenic operation of semiconductor diode lasers will reduce the number of devices needed to produce the requisite output for many veterinary and medical applications, permitting significant cost reductions.

  19. Construction and Testing of a Low-power Cryostat for MARS

    Energy Technology Data Exchange (ETDEWEB)

    Aalseth, Craig E.; Caggiano, Joseph A.; Day, Anthony R.; Fast, James E.; Fuller, Erin S.

    2007-10-01

    A low-power cryostat was designed and built for the Multi-sensor Airborne Radiation Survey (MARS) project for the purpose of housing a close-packed high-purity germanium (HPGe) detector array of 14 HPGe detectors. The power consumption of the cold mass in the cryostat was measured to be 4.07(11) watts, sufficient for 5.5 days of continuous operation using only 8 liters of liquid nitrogen. Temperatures throughout the cryostat were measured by platinum resistance temperature detectors. These measurements were used to determine the emissivity of the copper used in the floating radiation shield and outer cryostat wall, which was constructed using chemically cleaned and passivated copper metal. Using a PNNL-developed passivation process, an emissivity of 2.5(3)% was achieved for copper.

  20. A low-power DCO using inverter interlaced cascaded delay cell

    Institute of Scientific and Technical Information of China (English)

    Huang Qiang; Fan Tao; Dai Xiangming; Yuan Guoshun

    2014-01-01

    This paper presents a low-power small-area digitally controlled oscillator (DCO) using an inverters interlaced cascaded delay cell (ⅡCDC).It uses a coarse-fine architecture with binary-weighted delay stages for the delay range and resolution.The coarse-tuning stage of the DCO uses ⅡCDC,which is power and area efficient with low phase noise,as compared with conventional delay cells.The ADPLL with a DCO is fabricated in the UMC 180-nm CMOS process with an active area of 0.071 mm2.The output frequency range is 140-600 MHz at the power supply of 1.8 V.The power consumption is 2.34 mW@a 200 MHz output.

  1. Design of Static Flip-Flops for Low-Power Digital Sequential Circuits

    Directory of Open Access Journals (Sweden)

    E. Jaya Kumar

    2015-12-01

    Full Text Available In this paper, we correlated various Master and slave flip-flops i.e., single edge triggered flipflops. The low-power flip-flops have place utmost necessary elements all the range of the constructing static or successive circuits. We accomplish the comparison for their performance, Delay, Rise time, Fall Time and Power dissipation. Because Power confide in the number of transistors in the circuits, so we are comparing and calculating the number of transistors of the each flip-flops. Analysis of a static/sequential circuits is done by Linear Feed Back Shift Register (LFSR using 45nm Technology with 5MHZ frequencies and their performance analysis.

  2. A single lithium-ion battery protection circuit with high reliability and low power consumption

    Institute of Scientific and Technical Information of China (English)

    Jiang Jinguang; Li Sen

    2014-01-01

    A single lithium-ion battery protection circuit with high reliability and low power consumption is proposed.The protection circuit has high reliability because the voltage and current of the battery are controlled in a safe range.The protection circuit can immediately activate a protective function when the voltage and current of the battery are beyond the safe range.In order to reduce the circuit's power consumption,a sleep state control circuit is developed.Additionally,the output frequency of the ring oscillation can be adjusted continuously and precisely by the charging capacitors and the constant-current source.The proposed protection circuit is fabricated in a 0.5 μm mixed-signal CMOS process.The measured reference voltage is 1.19 V,the overvoltage is 4.2 V and the undervoltage is 2.2 V.The total power is about 9μW.

  3. Design of ternary low-power Domino JKL flip-flop and its application

    Institute of Scientific and Technical Information of China (English)

    Wang Pengjun; Yang Qiankun; Zheng Xuesong

    2012-01-01

    By researching the ternary flip-flop and the adiabatic Domino circuit,a novel design of low-power ternary Domino JKL flip-flop on the switch level is proposed.First,the switch-level structure of the ternary adiabatic Domino JKL flip-flop is derived according to the switch-signal theory and its truth table.Then the ternary loop operation circuit and ternary reverse loop operation circuit are achieved by employing the ternary JKL flip-flop.Finally,the circuit is simulated by using the Spice tool and the results show that the logic function is correct.The energy consumption of the ternary adiabatic Domino JKL flip-flop is 69% less than its conventional Domino counterpart.

  4. Evaluation and Choice of Various Branch Predictors for Low-Power Embedded Processor

    Institute of Scientific and Technical Information of China (English)

    FAN DongRui (范东睿); YANG HongBo (杨洪波); GAO GuangRong (高光荣); ZHAO RongCai (赵荣彩)

    2003-01-01

    Power is an important design constraint in embedded computing systems. To meet the power constraint, microarchitecture and hardware designed to achieve high performance need to be revisited, from both performance and power angles. This paper studies one of them:branch predictor. As well known, branch prediction is critical to exploit instruction level parallelism effectively, but may incur additional power consumption due to the hardware resource dedicated for branch prediction and the extra power consumed on mispredicted branches. This paper explores the design space of branch prediction mechanisms and tries to find the most beneficial one to realize low-power embedded processor. The sample processor studied is Godson-like processor, which is a dual-issue, out-of-order processor with deep pipeline, supporting MIPS instruction set.

  5. Ultra-low-power wireless transmitter for neural prostheses with modified pulse position modulation.

    Science.gov (United States)

    Goodarzy, Farhad; Skafidas, Stan E

    2014-01-01

    An ultra-low-power wireless transmitter for embedded bionic systems is proposed, which achieves 40 pJ/b energy efficiency and delivers 500 kb/s data using the medical implant communication service frequency band (402-405 MHz). It consumes a measured peak power of 200 µW from a 1.2 V supply while occupying an active area of 0.0016 mm(2) in a 130 nm technology. A modified pulse position modulation technique called saturated amplified signal is proposed and implemented, which can reduce the overall and per bit transferred power consumption of the transmitter while reducing the complexity of the transmitter architectures, and hence potentially shrinking the size of the implemented circuitry. The design is capable of being fully integrated on single-chip solutions for surgically implanted bionic systems, wearable devices and neural embedded systems.

  6. Frequency Spectrum Based Low-Area Low-Power Parallel FIR Filter Design

    Directory of Open Access Journals (Sweden)

    Jin-Gyun Chung

    2002-09-01

    Full Text Available Parallel (or block FIR digital filters can be used either for high-speed or low-power (with reduced supply voltage applications. Traditional parallel filter implementations cause linear increase in the hardware cost with respect to the block size. Recently, an efficient parallel FIR filter implementation technique requiring a less-than linear increase in the hardware cost was proposed. This paper makes two contributions. First, the filter spectrum characteristics are exploited to select the best fast filter structures. Second, a novel block filter quantization algorithm is introduced. Using filter benchmarks, it is shown that the use of the appropriate fast FIR filter structures and the proposed quantization scheme can result in reduction in the number of binary adders up to 20%.

  7. A Study of LoRa: Long Range & Low Power Networks for the Internet of Things

    Science.gov (United States)

    Augustin, Aloÿs; Yi, Jiazi; Clausen, Thomas; Townsley, William Mark

    2016-01-01

    LoRa is a long-range, low-power, low-bitrate, wireless telecommunications system, promoted as an infrastructure solution for the Internet of Things: end-devices use LoRa across a single wireless hop to communicate to gateway(s), connected to the Internet and which act as transparent bridges and relay messages between these end-devices and a central network server. This paper provides an overview of LoRa and an in-depth analysis of its functional components. The physical and data link layer performance is evaluated by field tests and simulations. Based on the analysis and evaluations, some possible solutions for performance enhancements are proposed. PMID:27618064

  8. Very Low-Power Consumption Analog Pulse Processing ASIC for Semiconductor Radiation Detectors

    Energy Technology Data Exchange (ETDEWEB)

    Wessendorf, K.O.; Lund, J.C.; Brunett, B.A.; Laguna, G.R.; Clements, J.W.

    1999-08-23

    We describe a very-low power consumption circuit for processing the pulses from a semiconductor radiation detector. The circuit was designed for use with a cadmium zinc telluride (CZT) detector for unattended monitoring of stored nuclear materials. The device is intended to be battery powered and operate at low duty-cycles over a long period of time. This system will provide adequate performance for medium resolution gamma-ray pulse-height spectroscopy applications. The circuit incorporates the functions of a charge sensitive preamplifier, shaping amplifier, and peak sample and hold circuit. An application specific integrated circuit (ASIC) version of the design has been designed, built and tested. With the exception of the input field effect transistor (FET), the circuit is constructed using bipolar components. In this paper the design philosophy and measured performance characteristics of the circuit are described.

  9. Low Power Design of Pipelined ADC for Power Line Baseband Communication

    Institute of Scientific and Technical Information of China (English)

    陈洋

    2013-01-01

    This paper presents a 10bit 5MS/s pipelined analog-to-digital converter(ADC)for single carrier power line communication transceiver.It’s a low-power method by using switched op amp technique,and proposes the switch capacitor(SC)bias circuitry to solve the startup issue of the current bias.Two common-mode feedback networks are employed to solve the problem of common-mode stability.Removes the sample and hold circuitry(SHA)to further reduce power consumption.Simulation result shows that the proposed ADC achieves 9.6 ENOB,75.8dB SFDR.The power consumption is 0.6 mA for 1.8V supply voltage.

  10. A low-power multi port register file design using a low-swing strategy

    Institute of Scientific and Technical Information of China (English)

    Yan Hao; Liu Yan; Hua Siliang; Wang Donghui; Hou Chaohuan

    2012-01-01

    a low-power register file is designed by using a low-swing strategy and modified NAND address decoders.The proposed low-swing strategy is based on the feedback scheme and uses dynamic logic to reduce the active feedback power.This method contains two parts:WRITE and READ strategy.In the WRITE low-swing scheme,the modified memory cell is used to support low-swing WRITE.The modified NAND decoder not only dissipates less power,but also enables a great deal of area reduction.Compared with the conventional single-ended register file,the low-swing strategy saves 34.5% and 51.15% bit-line power in WRITE and READ separately.The post simulation results indicate a 39.4% power improvement when the twelve ports are all busy.

  11. A Low-Power ASIC Signal Processor for a Vestibular Prosthesis.

    Science.gov (United States)

    Töreyin, Hakan; Bhatti, Pamela T

    2016-06-01

    A low-power ASIC signal processor for a vestibular prosthesis (VP) is reported. Fabricated with TI 0.35 μm CMOS technology and designed to interface with implanted inertial sensors, the digitally assisted analog signal processor operates extensively in the CMOS subthreshold region. During its operation the ASIC encodes head motion signals captured by the inertial sensors as electrical pulses ultimately targeted for in-vivo stimulation of vestibular nerve fibers. To achieve this, the ASIC implements a coordinate system transformation to correct for misalignment between natural sensors and implanted inertial sensors. It also mimics the frequency response characteristics and frequency encoding mappings of angular and linear head motions observed at the peripheral sense organs, semicircular canals and otolith. Overall the design occupies an area of 6.22 mm (2) and consumes 1.24 mW when supplied with ± 1.6 V.

  12. A LOW POWER CMOS ANALOG CIRCUIT DESIGN FOR ACQUIRING MULTICHANNEL EEG SIGNALS

    Directory of Open Access Journals (Sweden)

    G. Deepika

    2015-02-01

    Full Text Available EEG signals are the signatures of neural activities and are captured by multiple-electrodes and the signals are recorded from pairs of electrodes. To acquire these multichannel signals a low power CMOS circuit was designed and implemented. The design operates in weak inversion region employing sub threshold source coupled logic. A 16 channel differential multiplexer is designed by utilizing a transmission gate with dynamic threshold logic and a 4 to 16 decoder is used to select the individual channels. The ON and OFF resistance of the transmission gate obtained is 27 ohms and 10 M ohms respectively. The power dissipation achieved is around 337nW for a dynamic range of 1µV to 0.4 V.

  13. Low power Analog Digital Converter for a silicon photomultiplier readout ASIC

    Science.gov (United States)

    Briggl, K.; Chen, H.; Shen, W.; Schultz-Coulon, H. C.

    2015-04-01

    We present an ADC designed in the UMC 0.18um CMOS technology. It will be used in the SiPM analog front-end ``KLauS" developed for the analog hadronic calorimeter at ILD. Key parameter in this application is an extremely low power consumption of the front-end electronics. For quantization of the energy depositions, a 10-bit ADC resolution is required. For calibration purposes, a 12-bit quantization is used. A successive approximation register split capacitor array structure is chosen to minimize the DC power consumption. A peak sensing block is used to minimize the required sampling rate. We present design details and simulation results of the ADC, as well as the peak sensing track & hold circuit.

  14. Delay-Tolerant, Low-Power Protocols for Large Security-Critical Wireless Sensor Networks

    Directory of Open Access Journals (Sweden)

    Claudio S. Malavenda

    2012-01-01

    Full Text Available This paper reports the analysis, implementation, and experimental testing of a delay-tolerant and energy-aware protocol for a wireless sensor node, oriented to security applications. The solution proposed takes advantages from different domains considering as a guideline the low power consumption and facing the problems of seamless and lossy connectivity offered by the wireless medium along with very limited resources offered by a wireless network node. The paper is organized as follows: first we give an overview on delay-tolerant wireless sensor networking (DTN; then we perform a simulation-based comparative analysis of state-of-the-art DTN approaches and illustrate the improvement offered by the proposed protocol; finally we present experimental data gathered from the implementation of the proposed protocol on a proprietary hardware node.

  15. Nonlinear optics at low powers: Alternative mechanism of on-chip optical frequency comb generation

    Science.gov (United States)

    Rogov, Andrei S.; Narimanov, Evgenii E.

    2016-12-01

    Nonlinear optical effects provide a natural way of light manipulation and interaction and form the foundation of applied photonics, from high-speed signal processing and telecommunication to ultrahigh-bandwidth interconnects and information processing. However, relatively weak nonlinear response at optical frequencies calls for operation at high optical powers or boosting efficiency of nonlinear parametric processes by enhancing local-field intensity with high-quality-factor resonators near cavity resonance, resulting in reduced operational bandwidth and increased loss due to multiphoton absorption. We present an alternative to this conventional approach, with strong nonlinear optical effects at low local intensities, based on period-doubling bifurcations near nonlinear cavity antiresonance and apply it to low-power optical frequency comb generation in a silicon chip.

  16. Robust motion estimation on a low-power multi-core DSP

    Science.gov (United States)

    Igual, Francisco D.; Botella, Guillermo; García, Carlos; Prieto, Manuel; Tirado, Francisco

    2013-12-01

    This paper addresses the efficient implementation of a robust gradient-based optical flow model in a low-power platform based on a multi-core digital signal processor (DSP). The aim of this work was to carry out a feasibility study on the use of these devices in autonomous systems such as robot navigation, biomedical assistance, or tracking, with not only power restrictions but also real-time requirements. We consider the C6678 DSP from Texas Instruments (Dallas, TX, USA) as the target platform of our implementation. The interest of this research is particularly relevant in optical flow scope because this system can be considered as an alternative solution for mid-range video resolutions when a combination of in-processor parallelism with optimizations such as efficient memory-hierarchy exploitation and multi-processor parallelization are applied.

  17. Low-power task scheduling algorithm for large-scale cloud data centers

    Institute of Scientific and Technical Information of China (English)

    Xiaolong Xu; Jiaxing Wu; Geng Yang; Ruchuan Wang

    2013-01-01

    How to effectively reduce the energy consumption of large-scale data centers is a key issue in cloud computing. This pa-per presents a novel low-power task scheduling algorithm (LTSA) for large-scale cloud data centers. The winner tree is introduced to make the data nodes as the leaf nodes of the tree and the final winner on the purpose of reducing energy consumption is selected. The complexity of large-scale cloud data centers is ful y consider, and the task comparson coefficient is defined to make task scheduling strategy more reasonable. Experiments and per-formance analysis show that the proposed algorithm can effec-tively improve the node utilization, and reduce the overal power consumption of the cloud data center.

  18. A Study of LoRa: Long Range & Low Power Networks for the Internet of Things.

    Science.gov (United States)

    Augustin, Aloÿs; Yi, Jiazi; Clausen, Thomas; Townsley, William Mark

    2016-09-09

    LoRa is a long-range, low-power, low-bitrate, wireless telecommunications system, promoted as an infrastructure solution for the Internet of Things: end-devices use LoRa across a single wireless hop to communicate to gateway(s), connected to the Internet and which act as transparent bridges and relay messages between these end-devices and a central network server. This paper provides an overview of LoRa and an in-depth analysis of its functional components. The physical and data link layer performance is evaluated by field tests and simulations. Based on the analysis and evaluations, some possible solutions for performance enhancements are proposed.

  19. Expansion machine for a low power-output steam Rankine-cycle engine

    Energy Technology Data Exchange (ETDEWEB)

    Badr, O.; Naik, S.; O' Callaghan, P.W.; Probert, S.D. (Cranfield Inst. of Tech., Bedford (United Kingdom). School of Mechanical Engineering)

    1991-01-01

    The performance of the expansion device in a rankine-cycle engine is one of the major parameters dictating the engine's overall energy-conversion efficiency. In this paper the screening process undertaken to choose the most suitable expansion machine for a steam Rankine-cycle engine, operating principally as a 'mini' combined heat-and-power unit, is described. In the low power-output range (i.e. 5-20 kW) envisaged rotary, positive-displacement machines offer many advantages compared with turbines and reciprocating-piston expanders. So rotary-vane, helical-screw and Wankel-type expansion devices were short listed. However further assessments, based upon operational problems and cost effectiveness, led finally to the choice of the Wankel-type expander for the proposed application. Nevertheless, for this machine to be commercially successful, existing designs need to be modified and optimised. (author).

  20. A Low Power CMOS Analog Circuit Design for Acquiring Multichannel EEG Signals

    Directory of Open Access Journals (Sweden)

    G.Deepika

    2015-02-01

    Full Text Available EEG signals are the signatures of neural activities and are captured by multiple-electrodes and the signals are recorded from pairs of electrodes. To acquire these multichannel signals a low power CMOS circuit was designed and implemented. The design operates in weak inversion region employing sub threshold source coupled logic. A 16 channel differential multiplexer is designed by utilizing a transmission gate with dynamic threshold logic and a 4 to 16 decoder is used to select the individual channels. The ON and OFF resistance of the transmission gate obtained is 27 ohms and 10 M ohms respectively. The power dissipation achieved is around 337nW for a dynamic range of 1µV to 0.4 V.

  1. Markov chain algorithms: a template for building future robust low-power systems.

    Science.gov (United States)

    Deka, Biplab; Birklykke, Alex A; Duwe, Henry; Mansinghka, Vikash K; Kumar, Rakesh

    2014-06-28

    Although computational systems are looking towards post CMOS devices in the pursuit of lower power, the expected inherent unreliability of such devices makes it difficult to design robust systems without additional power overheads for guaranteeing robustness. As such, algorithmic structures with inherent ability to tolerate computational errors are of significant interest. We propose to cast applications as stochastic algorithms based on Markov chains (MCs) as such algorithms are both sufficiently general and tolerant to transition errors. We show with four example applications--Boolean satisfiability, sorting, low-density parity-check decoding and clustering-how applications can be cast as MC algorithms. Using algorithmic fault injection techniques, we demonstrate the robustness of these implementations to transition errors with high error rates. Based on these results, we make a case for using MCs as an algorithmic template for future robust low-power systems.

  2. An Ultra-Low-Power Oscillator with Temperature and Process Compensation for UHF RFID Transponder

    Directory of Open Access Journals (Sweden)

    Y. Wang

    2013-06-01

    Full Text Available This paper presents a 1.28MHz ultra-low-power oscillator with temperature and process compensation. It is very suitable for clock generation circuits used in ultra-high-frequency (UHF radio-frequency identification (RFID transponders. Detailed analysis of the oscillator design, including process and temperature compensation techniques are discussed. The circuit is designed using TSMC 0.18μm standard CMOS process and simulated with Spectre. Simulation results show that, without post-fabrication calibration or off-chip components, less than ±3% frequency variation is obtained from –40 to 85°C in three different process corners. Monte Carlo simulations have also been performed, and demonstrate a 3σ deviation of about 6%. The power for the proposed circuitry is only 1.18µW at 27°C.

  3. Nonlinear optics at low powers: new mechanism of on-chip optical frequency comb generation

    CERN Document Server

    Rogov, Andrei

    2016-01-01

    Nonlinear optical effects provide a natural way of light manipulation and interaction, and form the foundation of applied photonics -- from high-speed signal processing and telecommunication, to ultra-high bandwidth interconnects and information processing. However, relatively weak nonlinear response at optical frequencies calls for operation at high optical powers, or boosting efficiency of nonlinear parametric processes by enhancing local field intensity with high quality-factor resonators near cavity resonance, resulting in reduced operational bandwidth and increased loss due to multi-photon absorption. Here, we present an alternative to this conventional approach, with strong nonlinear optical effects at substantially lower local intensities, based on period-doubling bifurcations near nonlinear cavity anti-resonance, and apply it to low-power optical comb generation in a silicon chip.

  4. Performance Analysis of Modified Drain Gating Techniques for Low Power and High Speed Arithmetic Circuits

    Directory of Open Access Journals (Sweden)

    Shikha Panwar

    2014-01-01

    Full Text Available This paper presents several high performance and low power techniques for CMOS circuits. In these design methodologies, drain gating technique and its variations are modified by adding an additional NMOS sleep transistor at the output node which helps in faster discharge and thereby providing higher speed. In order to achieve high performance, the proposed design techniques trade power for performance in the delay critical sections of the circuit. Intensive simulations are performed using Cadence Virtuoso in a 45 nm standard CMOS technology at room temperature with supply voltage of 1.2 V. Comparative analysis of the present circuits with standard CMOS circuits shows smaller propagation delay and lesser power consumption.

  5. Geeks, meta-Geeks, and gender trouble: activism, identity, and low-power FM radio.

    Science.gov (United States)

    Dunbar-Hester, Christina

    2008-04-01

    In this paper, I consider the activities of a group of individuals who tinker with and build radio hardware in an informal setting called 'Geek Group'. They conceive of Geek Group as a radical pedagogical activity, which constitutes an aspect of activism surrounding citizen access to low-power FM radio. They are also concerned with combating the gendered nature of hardware skills, yet in spite of their efforts men tend to have more skill and familiarity with radio hardware than women. Radio tinkering has a long history as a masculine undertaking and a site of masculine identity construction. I argue that this case represents an interplay between geek, activist, and gendered identities, all of which are salient for this group, but which do not occur together without some tension.

  6. Interplay of Communication and Computation Energy Consumption for Low Power Sensor Network Design

    Directory of Open Access Journals (Sweden)

    Zeeshan Ali Khan

    2012-08-01

    Full Text Available The sensor network design approach normally conside rs the communication energy consumption for evaluating a communication protocol. This is true f or the low power devices such as MICAz/MICA2 which do not consume a lot of energy for the data t reatment. However, recently developed sensor device s for multimedia applications such as iMote2 do consu me considerable amount of energy for data processing. In this article, we consider various sc enarios for routing the data in wireless multimedia sensor networks by considering the local design par ameters of devices such as PXA27x and beagleboard. The proposed routing solution considers node level optimizations such as data compression, dynamic voltage and frequency scaling (DVFS for making a r outing decision. The proposed approaches have been simulated to prove the effectiveness of the ap proach.

  7. Low-power operation using self-timed circuits and adaptive scaling of the supply voltage

    DEFF Research Database (Denmark)

    Nielsen, Lars Skovby; Niessen, C.; Sparsø, Jens;

    1994-01-01

    Recent research has demonstrated that for certain types of applications like sampled audio systems, self-timed circuits can achieve very low power consumption, because unused circuit parts automatically turn into a stand-by mode. Additional savings may be obtained by combining the self......-timed circuits with a mechanism that adaptively adjusts the supply voltage to the smallest possible, while maintaining the performance requirements. This paper describes such a mechanism, analyzes the possible power savings, and presents a demonstrator chip that has been fabricated and tested. The idea...... of voltage scaling has been used previously in synchronous circuits, and the contributions of the present paper are: 1) the combination of supply scaling and self-timed circuitry which has some unique advantages, and 2) the thorough analysis of the power savings that are possible using this technique.>...

  8. Electron Cross-field Transport in a Low Power Cylindrical Hall Thruster

    Energy Technology Data Exchange (ETDEWEB)

    A. Smirnov; Y. Raitses; N.J. Fisch

    2004-06-24

    Conventional annular Hall thrusters become inefficient when scaled to low power. Cylindrical Hall thrusters, which have lower surface-to-volume ratio, are therefore more promising for scaling down. They presently exhibit performance comparable with conventional annular Hall thrusters. Electron cross-field transport in a 2.6 cm miniaturized cylindrical Hall thruster (100 W power level) has been studied through the analysis of experimental data and Monte Carlo simulations of electron dynamics in the thruster channel. The numerical model takes into account elastic and inelastic electron collisions with atoms, electron-wall collisions, including secondary electron emission, and Bohm diffusion. We show that in order to explain the observed discharge current, the electron anomalous collision frequency {nu}{sub B} has to be on the order of the Bohm value, {nu}{sub B} {approx} {omega}{sub c}/16. The contribution of electron-wall collisions to cross-field transport is found to be insignificant.

  9. Space charge dosimeters for extremely low power measurements of radiation in shipping containers

    Science.gov (United States)

    Britton, Jr.; Charles L.; Buckner, Mark A.; Hanson, Gregory R.; Bryan, William L.

    2011-04-26

    Methods and apparatus are described for space charge dosimeters for extremely low power measurements of radiation in shipping containers. A method includes in situ polling a suite of passive integrating ionizing radiation sensors including reading-out dosimetric data from a first passive integrating ionizing radiation sensor and a second passive integrating ionizing radiation sensor, where the first passive integrating ionizing radiation sensor and the second passive integrating ionizing radiation sensor remain situated where the dosimetric data was integrated while reading-out. Another method includes arranging a plurality of ionizing radiation sensors in a spatially dispersed array; determining a relative position of each of the plurality of ionizing radiation sensors to define a volume of interest; collecting ionizing radiation data from at least a subset of the plurality of ionizing radiation sensors; and triggering an alarm condition when a dose level of an ionizing radiation source is calculated to exceed a threshold.

  10. The Optimized data path ANN for Low power and Embedded applications.

    Directory of Open Access Journals (Sweden)

    S N Prasad

    2016-04-01

    Full Text Available This present work is aimed at the optimization of ANN (artificial neural network for the low power & embedded applications. Due to rapid switching of the internal signals, power dissipation is very high in the modern VLSI systems. So the optimization is very much essential. This work explores the approaches to modify the existing building blocks of ANN in order to reduce the power (data path optimizations.by considering the 4:2 compressor architecture for the multiplier architecture of layered ANN. The design is modeled using Verilog HDL in the ASIC domain using the CMOS technological library of 65nm.The modified data path architecture consumes 15.91% of area and 26.09% of leakage power lesser when compared with existing architectures. This design provides the better speed up to 12.71%.

  11. An Implementation of Low Cost and Low-power Network Broadcast Data Transmission and Storage System

    Science.gov (United States)

    Yi, Qing-Ming; Shi, Min; He, Yi-Hua

    A connectivity and realization method for the one-to-many remote network data transmission and storage was introduced in this paper. 3D LED display array needs large size data to display a stereo picture. This method was used in 3D LED display array to resolve data secure transmission problem. Combining the Intel 28FJ3A series Flash and Ethernet control chip DM9000A,it applied the Field-Programmable Gate Array (FPGA) and Verilog HDL programming technology to the system, implemented synchronic display and storage of stereograph, and reached 100 Mbps in the network transmission .Testing shows that the system is of low-cost,low-power and high-speed.

  12. Implementation of Low Power And Propagation Delay Optimized Multiplexers Based Full Adder Cells

    Directory of Open Access Journals (Sweden)

    J. Mallikarjuna Rao

    2014-05-01

    Full Text Available Power consumption has emerged as a primary design constraint for integrated circuits (ICs. In the Nanometer technology regime, leakage power has become a major component of total power [1]. Full adder is the basic functional unit of an ALU. The power consumption of a processor is lowered by lowering the power consumption of an ALU, and the power consumption of an ALU can be lowered by lowering the power consumption of Full adder. So the full adder designs with low power characteristics are becoming more popular these days. In this paper we are going to design four different types of Full adder these are applied to 32-bit RCA .The four designs will be developed using Verilog HDL evaluating the performance using Cadence.

  13. Intense generation of respirable metal nanoparticles from a low-power soldering unit

    Energy Technology Data Exchange (ETDEWEB)

    Gómez, Virginia [Department of Chemical Engineering, Nanoscience Institute of Aragon (INA), 50018 Zaragoza (Spain); Irusta, Silvia [Department of Chemical Engineering, Nanoscience Institute of Aragon (INA), 50018 Zaragoza (Spain); Networking Biomedical Research Center of Bioengineering, Biomaterials and Nanomedicine (CIBER-BBN), 50018 Zaragoza (Spain); Balas, Francisco [Networking Biomedical Research Center of Bioengineering, Biomaterials and Nanomedicine (CIBER-BBN), 50018 Zaragoza (Spain); Instituto de Carboquímica – Consejo Superior de Investigaciones Científicas (ICB-CSIC), 50018 Zaragoza (Spain); Santamaria, Jesus, E-mail: Jesus.Santamaria@unizar.es [Department of Chemical Engineering, Nanoscience Institute of Aragon (INA), 50018 Zaragoza (Spain); Networking Biomedical Research Center of Bioengineering, Biomaterials and Nanomedicine (CIBER-BBN), 50018 Zaragoza (Spain)

    2013-07-15

    Highlights: • Intense generation of nanoparticles in the breathing range from a flux-soldering unit is detected. • Coagulation in the aerosol phase leads to 200-nm respirable nanoparticles up to 30 min after operation. • Nanoparticle concentration in the working environment depends on the presence of ambient air. • Metal-containing nanoparticles are collected in TEM grids and filters in the hundreds of nanometer range. -- Abstract: Evidence of intense nanoparticle generation from a low power (45 W) flux soldering unit is presented. This is a familiar device often used in daily life, including home repairs and school electronic laboratories. We demonstrate that metal-containing nanoparticles may reach high concentrations (ca. 10{sup 6} particles/cm{sup 3}) within the breathing range of the operator, with initial size distributions centered at 35–60 nm The morphological and chemical analysis of nanoparticle agglomerates collected on TEM grids and filters confirms their multiparticle structure and the presence of metals.

  14. Promise of a Low Power Mobile CPU based Embedded System in Artificial Leg Control

    Science.gov (United States)

    Hernandez, Robert; Zhang, Fan; Zhang, Xiaorong; Huang, He; Yang, Qing

    2013-01-01

    This paper presents the design and implementation of a low power embedded system using mobile processor technology (Intel Atom™ Z530 Processor) specifically tailored for a neural-machine interface (NMI) for artificial limbs. This embedded system effectively performs our previously developed NMI algorithm based on neuromuscular-mechanical fusion and phase-dependent pattern classification. The analysis shows that NMI embedded system can meet real-time constraints with high accuracies for recognizing the user's locomotion mode. Our implementation utilizes the mobile processor efficiently to allow a power consumption of 2.2 watts and low CPU utilization (less than 4.3%) while executing the complex NMI algorithm. Our experiments have shown that the highly optimized C program implementation on the embedded system has superb advantages over existing PC implementations on MATLAB. The study results suggest that mobile-CPU-based embedded system is promising for implementing advanced control for powered lower limb prostheses. PMID:23367113

  15. A 23 GHz low power VCO in SiGe BiCMOS technology

    Institute of Scientific and Technical Information of China (English)

    Huang Yinkun; Wu Danyu; Zhou Lei; Jiang Fan; Wu Jin; Jin Zhi

    2013-01-01

    A 23 GHz voltage controlled oscillator (VCO) with very low power consumption is presented.This paper presents the design and measurement of an integrated millimeter wave VCO.This VCO employs an on-chip inductor and MOS varactor to form a high Q resonator.The VCO RFIC was implemented in a 0.18 μm 120 GHz ft SiGe hetero-junction bipolar transistor (HBT) BiCMOS technology.The VCO oscillation frequency is around 23 GHz,targeting at the ultra wideband (UWB) and short range radar applications.The core of the VCO circuit consumes 1 mA current from a 2.5 V power supply and the VCO phase noise was measured at around-94 dBc/Hz at a 1 MHz frequency offset.The FOM of the VCO is-177 dBc/Hz.

  16. Low Power Design of High Speed CMOS Pulse Stream Neuron Circuit

    Institute of Scientific and Technical Information of China (English)

    陈继伟; 石秉学

    2000-01-01

    A new pulse stream neuron circuit is presented, which can be obtained in the digital CMOS process and combines both the merits of digital circuits and analog ones. The output is expressed by the frequency of the pulses with transfer characteristic, which is correspondent with the ideal sigmoid curve perfectly. Moreover, the pulse-active strategy is introduced into the design of this CMOS pulse stream neuron circuit for the first time in order to reduce the power dissipation, which is applicable to the low-power design of mixed-signal circuits,too. A simple technical process and compact architecture make this circuit work at a higher speed and with lower power dissipation and smaller area.

  17. Large area and low power dielectrowetting optical shutter with local deterministic fluid film breakup

    Science.gov (United States)

    Zhao, R.; Cumby, B.; Russell, A.; Heikenfeld, J.

    2013-11-01

    A large area (>10 cm2) and low-power (0.1-10 Hz AC voltage, ˜10's μW/cm2) dielectrowetting optical shutter requiring no pixelation is demonstrated. The device consists of 40 μm interdigitated electrodes covered by fluid splitting features and a hydrophobic fluoropolymer. When voltage is removed, the fluid splitting features initiate breakup of the fluid film into small droplets resulting in ˜80% transmission. Both the dielectrowetting and fluid splitting follow theory, allowing prediction of alternate designs and further improved performance. Advantages include scalability, optical polarization independence, high contrast ratio, fast response, and simple construction, which could be of use in switchable windows or transparent digital signage.

  18. A low power, area efficient fpga based beamforming technique for 1-D CMUT arrays.

    Science.gov (United States)

    Joseph, Bastin; Joseph, Jose; Vanjari, Siva Rama Krishna

    2015-08-01

    A low power area efficient digital beamformer targeting low frequency (2MHz) 1-D linear Capacitive Micromachined Ultrasonic Transducer (CMUT) array is developed. While designing the beamforming logic, the symmetry of the CMUT array is well exploited to reduce the area and power consumption. The proposed method is verified in Matlab by clocking an Arbitrary Waveform Generator(AWG). The architecture is successfully implemented in Xilinx Spartan 3E FPGA kit to check its functionality. The beamforming logic is implemented for 8, 16, 32, and 64 element CMUTs targeting Application Specific Integrated Circuit (ASIC) platform at Vdd 1.62V for UMC 90nm technology. It is observed that the proposed architecture consumes significantly lesser power and area (1.2895 mW power and 47134.4 μm(2) area for a 64 element digital beamforming circuit) compared to the conventional square root based algorithm.

  19. Multi-Functional Micro Projection Device as Screen Substitute for Low Power Consumption Computing

    Directory of Open Access Journals (Sweden)

    Zeev Zalevsky

    2012-03-01

    Full Text Available One of the major power consuming components in a computer is its display unit. On average the screen consumes ten times more power than the DSP processor itself. Thus, reducing the power consumption should be one of the most important tasks in the development of low power consumption computing systems. In this paper we present one possible solution involving micro projection device based upon lasers and a digital light processing (DLP matrix which is a matrix of electrically controllable mirrors capable of translating electrical signal to a time varying projected image. It can serve to substitute a screen and consume ten times less power than a conventional screen. The described device is a multifunctional highly efficient customized DLP light engine being capable of serving as an image projector and simultaneously to support range and topography estimation measurements.

  20. Design of a Low Power DSP with Distributed and Early Clock Gating

    Institute of Scientific and Technical Information of China (English)

    2007-01-01

    A novel clock structure of a low-power 16-bit very large instruction word (VLIW) digital signal processor (DSP) was proposed. To improve deterministic clock gating and to solve the drawback of conventional clock gating circuit in high speed circuit, a distributed and early clock gating method was developed on its instruction fetch &. decoder unit, its pipelined data-path unit and its super-Harvard memory interface unit. The core was im1.8-V 1P6M process, with a core size of 2 mm×2mm .Result shows that it can run under 200MHz with a powerperformance around 0.3mW/MIPS.Meanwhile,only39.7% circuit is active simultaneously in average,comparedto its non-gating counterparts.

  1. Phase-Noise and Amplitude-Noise Measurement of Low-Power Signals

    Science.gov (United States)

    Rubiola, Enrico; Salik, Ertan; Yu, Nan; Maleki, Lute

    2004-01-01

    Measuring the phase fluctuation between a pair of low-power microwave signals, the signals must be amplified before detection. In such cases the phase noise of the amplifier pair is the main cause of 1/f background noise of the instrument. this article proposes a scheme that makes amplification possible while rejecting the close in 1/f (flicker) noise of the two amplifiers. Noise rejection, which relies upon the understanding of the amplifier noise mechanism does not require averaging. Therefore, our scheme can also be the detector of a closed loop noise reduction system. the first prototype, compared to a traditional saturated mixer system under the same condition, show a 24 dB noise reduction of the 1/f region.

  2. An X-Band low-power and low-phase-noise VCO using bondwire inductor

    Directory of Open Access Journals (Sweden)

    K. Hu

    2009-05-01

    Full Text Available In this paper a low-power low-phase-noise voltage-controlled-oscillator (VCO has been designed and, fabricated in 0.25 μm SiGe BiCMOS process. The resonator of the VCO is implemented with on-chip MIM capacitors and a single aluminum bondwire. A tail current filter is realized to suppress flicker noise up-conversion. The measured phase noise is −126.6 dBc/Hz at 1 MHz offset from a 7.8 GHz carrier. The figure of merit (FOM of the VCO is −192.5 dBc/Hz and the VCO core consumes 4 mA from a 3.3 V power supply. To the best of our knowledge, this is the best FOM and the lowest phase noise for bondwire VCOs in the X-band. This VCO will be used for satellite communications.

  3. Direct and indirect measures of speech articulator motions using low power EM sensors

    Energy Technology Data Exchange (ETDEWEB)

    Barnes, T; Burnett, G; Gable, T; Holzrichter, J F; Ng, L

    1999-05-12

    Low power Electromagnetic (EM) Wave sensors can measure general properties of human speech articulator motions, as speech is produced. See Holzrichter, Burnett, Ng, and Lea, J.Acoust.Soc.Am. 103 (1) 622 (1998). Experiments have demonstrated extremely accurate pitch measurements (< 1 Hz per pitch cycle) and accurate onset of voiced speech. Recent measurements of pressure-induced tracheal motions enable very good spectra and amplitude estimates of a voiced excitation function. The use of the measured excitation functions and pitch synchronous processing enable the determination of each pitch cycle of an accurate transfer function and, indirectly, of the corresponding articulator motions. In addition, direct measurements have been made of EM wave reflections from articulator interfaces, including jaw, tongue, and palate, simultaneously with acoustic and glottal open/close signals. While several types of EM sensors are suitable for speech articulator measurements, the homodyne sensor has been found to provide good spatial and temporal resolution for several applications.

  4. Tungsten carbide coatings with different binders prepared by low power plasma spray system

    Institute of Scientific and Technical Information of China (English)

    GAO Yang; M.F.Morks; FU Ying-qing

    2004-01-01

    Thermal spraying of cermet coatings is widely used for protection of machining parts against wear and corrosion. These coatings consist of WC particles in metal binders such as Co, Cr and Ni. Three kinds of WC powders with different metal binders (Co, NiCr and CoCr) were sprayed by low power plasma spray system on Al-Si-Cu alloy substrate. Fundamental aspects of sprayed cermet coatings, including (i) the effects of binder type on the coating structure, (ii) the hardness and (iii) the microstructure, were investigated. All cermet coatings have the same phase structure such as WC and W2 C. However, the intensities of these phases are different in each coating, mainly due to the difference in solidification rate in each case. Moreover, the hardness measurements are found to be different in each coating. The results show that, binder type has a significant effect on the physical and mechanical properties of the sprayed coatings.

  5. A low-power circuit for piezoelectric vibration control by synchronized switching on voltage sources

    CERN Document Server

    Shen, Hui; Ji, Hongli; Zhu, Kongjun; Balsi, Marco; Giorgio, Ivan; dell'Isola, Francesco

    2010-01-01

    In the paper, a vibration damping system powered by harvested energy with implementation of the so-called SSDV (synchronized switch damping on voltage source) technique is designed and investigated. In the semi-passive approach, the piezoelectric element is intermittently switched from open-circuit to specific impedance synchronously with the structural vibration. Due to this switching procedure, a phase difference appears between the strain induced by vibration and the resulting voltage, thus creating energy dissipation. By supplying the energy collected from the piezoelectric materials to the switching circuit, a new low-power device using the SSDV technique is proposed. Compared with the original self-powered SSDI (synchronized switch damping on inductor), such a device can significantly improve its performance of vibration control. Its effectiveness in the single-mode resonant damping of a composite beam is validated by the experimental results.

  6. On the outage capacity of the block fading channel at low-power regime

    KAUST Repository

    Rezki, Zouheir

    2014-06-01

    Outage performance of the M-block fading with additive white Gaussian noise (BF-AWGN) is investigated at low-power regime. We consider delay-constrained constant-rate communications with perfect channel state information (CSI) at both the transmitter and the receiver (CSI-TR), under a short-term power constraint. We show that selection diversity that allocates all the power to the strongest block is asymptotically optimal. Then, we provide a simple characterization of the outage probability in the regime of interest. We quantify the reward due to CSI-TR over the constant-rate constant-power scheme and show that this reward increases with the delay constraint. For instance, for Rayleigh fading, we find that a power gain up to 4.3 dB is achievable. © 2014 IEEE.

  7. Reconfigurable Multiparameter Biosignal Acquisition SoC for Low Power Wearable Platform.

    Science.gov (United States)

    Kim, Jongpal; Ko, Hyoungho

    2016-11-25

    A low power and low noise reconfigurable analog front-end (AFE) system on a chip (SoC) for biosignal acquisition is presented. The presented AFE can be reconfigured for use in electropotential, bioimpedance, electrochemical, and photoelectrical modes. The advanced healthcare services based on multiparameter physiological biosignals can be easily implemented with these multimodal and highly reconfigurable features of the proposed system. The reconfigurable gain and input referred noise of the core instrumentation amplifier block are 25 dB to 52 dB, and 1 μVRMS, respectively. The power consumption of the analog blocks in one readout channel is less than 52 μW. The reconfigurable capability among various modes of applications including electrocardiogram, blood glucose concentration, respiration, and photoplethysmography are shown experimentally.

  8. Programmable Low-Power Low-Noise Capacitance to Voltage Converter for MEMS Accelerometers.

    Science.gov (United States)

    Royo, Guillermo; Sánchez-Azqueta, Carlos; Gimeno, Cecilia; Aldea, Concepción; Celma, Santiago

    2016-12-30

    In this work, we present a capacitance-to-voltage converter (CVC) for capacitive accelerometers based on microelectromechanical systems (MEMS). Based on a fully-differential transimpedance amplifier (TIA), it features a 34-dB transimpedance gain control and over one decade programmable bandwidth, from 75 kHz to 1.2 MHz. The TIA is aimed for low-cost low-power capacitive sensor applications. It has been designed in a standard 0.18-μm CMOS technology and its power consumption is only 54 μW. At the maximum transimpedance configuration, the TIA shows an equivalent input noise of 42 fA/ Hz at 50 kHz, which corresponds to 100 μg/ Hz .

  9. A coaxial HOM coupler for a superconducting RF cavity and its low-power measurement results

    Institute of Scientific and Technical Information of China (English)

    SUN An; TANG Ya-Zhe; ZHANG Li-Ping; LI Ying-Min; Han-Sung Kim

    2011-01-01

    A resonant buildup of beam-induced fields in a superconducting radio frequency(RF)cavity may make a beam unstable or a superconducting RF cavity quench. Higher-order mode(HOM)couplers are used for damping higher-order modes to avoid such a resonant buildup. A coaxial HOM coupler based on the TTF (TESLA Test Facility)HOM coupler has been designed for the superconducting RF cavities at the Proton Engineering Frontier Project(PEFP)in order to overcome notch frequency shift and feed-through tip melting issues. In order to confirm the HOM coupler design and finalize its structural dimensions, two prototype HOM couplers have been fabricated and tested. Low-power testing and measurement of the HOM couplers has shown that the HOM coupler has good filter properties and can fully meet the damping requirements of the PEFP low-beta superconducting RF linac.

  10. Low-power Helium-Neon laser irradiation enhances the expression of VEGF in murine myocardium

    Institute of Scientific and Technical Information of China (English)

    张卫光; 吴长燕; 潘文潇; 田珑; 夏家骝

    2004-01-01

    Background Low-power helium-neon (He-Ne) lasers have been increasingly widely applied in the treatment of cardiovascular diseases, and its vasodilation effect has been proven. The aim of this study was to determine the effects of low-power He-Ne laser irradiation directed at the precardial region of Wistar rats on capillary permeability in the myocardium and the expression of myocardial vascular endothelial growth factor (VEGF). Methods Sixteen rats were divided randomly into control and irradiated groups (n=8, each). A He-Ne laser (632.8 nm) was applied to the irradiated group with a dose of 60.5 J/cm2. Ferritin was perfused into the left femoral vein and capillary permeability was examined under an electron microscope. VEGF expression in the myocardium was investigated by immunohistochemical methods, RT-PCR, and image analysis. Results The ultrastructures of the myocardial capillaries were examined. Compared to the control group, more high-density granules (ferritin), which were present within the capillary endothelium and the mitochondrions of myocardial cells in the internal layer of the myocardium, were observed in the irradiated group. VEGF staining of the myocardium was stronger in the irradiated group than that in the control group. The optic density of the irradiated group (0.246±0.015) was significantly higher than that of the control group (0.218±0.012, P<0.05). Finally, the levels of RT-PCR products of VEGF165 mRNA were 2.79 times higher in irradiated rats than in the control rats.Conclusions Our study demonstrates that He-Ne laser irradiation (in doses of 60.5 J/cm2) increases myocardial capillary permeability and the production of VEGF in myocardial microvessels and in myocardium. Our study provides experimental morphological evidence that myocardial microcirculation can be improved using He-Ne laser irradiation.

  11. Optimal Dynamic Sub-Threshold Technique for Extreme Low Power Consumption for VLSI

    Science.gov (United States)

    Duong, Tuan A.

    2012-01-01

    For miniaturization of electronics systems, power consumption plays a key role in the realm of constraints. Considering the very large scale integration (VLSI) design aspect, as transistor feature size is decreased to 50 nm and below, there is sizable increase in the number of transistors as more functional building blocks are embedded in the same chip. However, the consequent increase in power consumption (dynamic and leakage) will serve as a key constraint to inhibit the advantages of transistor feature size reduction. Power consumption can be reduced by minimizing the voltage supply (for dynamic power consumption) and/or increasing threshold voltage (V(sub th), for reducing leakage power). When the feature size of the transistor is reduced, supply voltage (V(sub dd)) and threshold voltage (V(sub th)) are also reduced accordingly; then, the leakage current becomes a bigger factor of the total power consumption. To maintain low power consumption, operation of electronics at sub-threshold levels can be a potentially strong contender; however, there are two obstacles to be faced: more leakage current per transistor will cause more leakage power consumption, and slow response time when the transistor is operated in weak inversion region. To enable low power consumption and yet obtain high performance, the CMOS (complementary metal oxide semiconductor) transistor as a basic element is viewed and controlled as a four-terminal device: source, drain, gate, and body, as differentiated from the traditional approach with three terminals: i.e., source and body, drain, and gate. This technique features multiple voltage sources to supply the dynamic control, and uses dynamic control to enable low-threshold voltage when the channel (N or P) is active, for speed response enhancement and high threshold voltage, and when the transistor channel (N or P) is inactive, to reduce the leakage current for low-leakage power consumption.

  12. Examination of risk significant configuration during low power and shutdown with ORION and PSA

    Energy Technology Data Exchange (ETDEWEB)

    Park, Chul Kyu; Oh, Seung Jong [KEPCO International Nuclear Graduate School, Ulsan (Korea, Republic of)

    2015-10-15

    This paper suggests an approach to calculate the increased CDF corresponding to Orange and Red states in ORION program and analyzed the result of calculation. This approach is expected to be useful for checking the adequacy of the LPSD PSA. And also, the result of this calculation can provide the information about which SSCs for certain SF are more sensitive to risk in particular POS. Defense-in-depth is a safety philosophy in which multiple lines of defense and conservative design and evaluation methods are applied to ensure the safety of the public. Based on this philosophy EPRI developed Outage Risk Assessment and Management (ORAM) program as a qualitative assessment to better manage the risk during low power and shutdown event after the Vogtle loss of vital AC power and RHR event in 1990. Each risk level of RED, ORANGE color status caused by the degradation of each key safety function might be different depend on the importance of each key safety function. However we can't know how much different. If we know the quantitative information about the risk level represented by color, we can take and prepare concrete actions to reduce the risk level of the plant with rescheduling maintenance, strengthen surveillance for important safety function, and developing outage management strategy. The probabilistic safety analysis for low power and shutdown period can provide risk information with quantitative value related on the degradation of redundancy and diversity level for the safety functions during outage. In this study, we calculated the increased Core Damage frequency (CDF) of each RED and ORANGE states in ORION program caused by the degradation of each key safety function by modifying LPSD PSA model. The result of calculation and analysis could be effective to check adequacy and find improvement for these two methods.

  13. Low-power system for the acquisition of the respiratory signal of neonates using diaphragmatic electromyography

    Directory of Open Access Journals (Sweden)

    Torres R

    2017-02-01

    Full Text Available Róbinson Torres,1,2 Sergio López-Isaza,1,2 Elisa Mejía-Mejía,1,2 Viviana Paniagua,1,2 Víctor González3 1Biomedical Engineering Department, Universidad EIA, Envigado, 2Biomedical Engineering Department, Universidad CES, 3Neonathology Department, Hospital General de Medellín Luz Castro de Gutiérrez, Medellín, Antioquia, Colombia Introduction: An apnea episode is defined as the cessation of breathing for ≥15 seconds or as any suspension of breathing accompanied by hypoxia and bradycardia. Obtaining information about the respiratory system in a neonate can be accomplished using electromyography signals from the diaphragm muscle.Objective: The purpose of this paper is to illustrate a method by which the respiratory and electrocardiographic signals from neonates can be obtained using diaphragmatic electromyography.Materials and methods: The system was developed using single-supply, micropower components, which deliver a low-power consumption system appropriate for the development of portable devices. The stages of the system were tested in both adult and neonate patients.Results: The system delivers signals as those expected in both patients and allows the acquisition of respiratory signals directly from the diaphragmatic electromyography.Conclusion: This low-power system may present a good alternative for monitoring the cardiac and respiratory activity in newborn babies, both in the hospital and at home.Significance: The system delivers good signals but needs to be validated for its use in neonates. It is being used in the Neonatal Intensive Care Unit of the Hospital General de Medellín Luz Castro de Gutiérrez. Keywords: apnea, diaphragm, electromyography, neonates, respiratory signal

  14. Uncooled 17 μm ¼ VGA IRFPA development for compact and low power systems

    Science.gov (United States)

    Robert, P.; Tissot, J.; Pochic, D.; Gravot, V.; Bonnaire, F.; Clerambault, H.; Durand, A.; Tinnes, S.

    2012-11-01

    The high level of accumulated expertise by ULIS and CEA/LETI on uncooled microbolometers made from amorphous silicon enables ULIS to develop ¼ VGA IRFPA formats with 17μm pixel-pitch to enable the development of small power, small weight (SWAP) and high performance IR systems. ROIC architecture will be described where innovations are widely on-chip implemented to enable an easier operation by the user. The detector configuration (integration time, windowing, gain, scanning direction…), is driven by a standard I²C link. Like most of the visible arrays, the detector adopts the HSYNC/VSYNC free-run mode of operation driven with only one master clock (MC) supplied to the ROIC which feeds back pixel, line and frame synchronizations. On-chip PROM memory for customer operational condition storage is available for detector characteristics. Low power consumption has been taken into account and less than 60 mW is possible in analog mode at 60 Hz and CMOS node. The specific appeal of this unit lies in the high uniformity and easy operation it provides. The reduction of the pixel-pitch turns this TEC-less ¼ VGA array into a product well adapted for high resolution and compact systems. NETD of 35 mK and thermal time constant of 10 ms have been measured leading to 350 mK.ms figure of merit. We insist on NETD trade-off with wide thermal dynamic range, as well as the high characteristics uniformity and pixel operability, achieved thanks to the mastering of the amorphous silicon technology coupled with the ROIC design. This technology node associated with advanced packaging technique, paves the way to compact low power system.

  15. Low power cogeneration prototype system; Prototipo de sistema de co-geracao de pequena potencia

    Energy Technology Data Exchange (ETDEWEB)

    Santos, Sara M.; Martins, Jose A.S.; Camara, Paulo R.; Cortes, Breno P.; Neves, Elierton E. [Centro de Tecnologias do Gas (CTGAS), Natal, RN (Brazil); F. Filho, Roberto; Campos, Michel F. [PETROBRAS, Rio de Janeiro, RJ (Brazil)

    2004-07-01

    The fuels from oil and natural gas play an important role, not only in the sector of primary energy, but also in almost all the other sectors of the economy, due to its imbrication as insum of these. The use of the natural gas will have great expansion in Brazil, motivated for the Government decision to increase the participation of this fuel in the Brazilian energy matrix from 4% to 12% up to 2010. Then, it's so important the investment in new technologies and also the improvement. In order to reach the objective related to increase the consumption of natural gas in the energy matrix, and to propose solutions to attend the electric requirements, of heat and refrigeration, using natural gas as primary power plant, the Center of Gas Technologies; CTGAS, in partnership with PETROBRAS and the Fockink Group, has developed the first modular system of generation and co-generation of energy by natural gas of low power, of easy installation and shipment with the characteristics techniques to take care of to companies or industrial sectors that consummate this band of power. The equipment generates 35 kW/55 kVA of electric energy, 7TR (Ton of Refrigeration) of energy for refrigeration and posses the ability to heat 2200 l/h of water in the temperature of 85 deg C. The equipment will be able to produce electric and thermal energy simultaneously, from an only fuel, the natural gas. The main objective of this work is to present the main phases of development of the archetype, functions techniques of the co-generator and its field of performance in the market of systems for generation and co-generation of energy by natural gas of low power. (author)

  16. An ultra-low-power RF transceiver for WBANs in medical applications

    Science.gov (United States)

    Qi, Zhang; Xiaofei, Kuang; Nanjian, Wu

    2011-06-01

    A 2.4 GHz ultra-low-power RF transceiver with a 900 MHz auxiliary wake-up link for wireless body area networks (WBANs) in medical applications is presented. The RF transceiver with an asymmetric architecture is proposed to achieve high energy efficiency according to the asymmetric communication in WBANs. The transceiver consists of a main receiver (RX) with an ultra-low-power free-running ring oscillator and a high speed main transmitter (TX) with fast lock-in PLL. A passive wake-up receiver (WuRx) for wake-up function with a high power conversion efficiency (PCE) CMOS rectifier is designed to offer the sensor node the capability of work-on-demand with zero standby power. The chip is implemented in a 0.18 μm CMOS process. Its core area is 1.6 mm2. The main RX achieves a sensitivity of -55 dBm at a 100 kbps OOK data rate while consuming just 210 μA current from the 1 V power supply. The main TX achieves +3 dBm output power with a 4 Mbps/500 kbps/200 kbps data rate for OOK/4 FSK/2 FSK modulation and dissipates 3.25 mA/6.5 mA/6.5 mA current from a 1.8 V power supply. The minimum detectable RF input energy for the wake-up RX is -15 dBm and the PCE is more than 25%.

  17. An ultra-low-power RF transceiver for WBANs in medical applications

    Energy Technology Data Exchange (ETDEWEB)

    Zhang Qi; Wu Nanjian [State Key Laboratory for Superlattices and Microstructures, Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083 (China); Kuang Xiaofei, E-mail: nanjian@semi.ac.cn [College of Electronic Information, Hangzhou Dianzi University, Hangzhou 310018 (China)

    2011-06-15

    A 2.4 GHz ultra-low-power RF transceiver with a 900 MHz auxiliary wake-up link for wireless body area networks (WBANs) in medical applications is presented. The RF transceiver with an asymmetric architecture is proposed to achieve high energy efficiency according to the asymmetric communication in WBANs. The transceiver consists of a main receiver (RX) with an ultra-low-power free-running ring oscillator and a high speed main transmitter (TX) with fast lock-in PLL. A passive wake-up receiver (WuRx) for wake-up function with a high power conversion efficiency (PCE) CMOS rectifier is designed to offer the sensor node the capability of work-on-demand with zero standby power. The chip is implemented in a 0.18 {mu}m CMOS process. Its core area is 1.6 mm{sup 2}. The main RX achieves a sensitivity of -55 dBm at a 100 kbps OOK data rate while consuming just 210 {mu}A current from the 1 V power supply. The main TX achieves +3 dBm output power with a 4 Mbps/500 kbps/200 kbps data rate for OOK/4 FSK/2 FSK modulation and dissipates 3.25 mA/6.5 mA/6.5 mA current from a 1.8 V power supply. The minimum detectable RF input energy for the wake-up RX is -15 dBm and the PCE is more than 25%. (semiconductor integrated circuits)

  18. Autonomous low-power magnetic data collection platform to enable remote high latitude array deployment.

    Science.gov (United States)

    Musko, Stephen B; Clauer, C Robert; Ridley, Aaron J; Arnett, Kennneth L

    2009-04-01

    A major driver in the advancement of geophysical sciences is improvement in the quality and resolution of data for use in scientific analysis, discovery, and for assimilation into or validation of empirical and physical models. The need for more and better measurements together with improvements in technical capabilities is driving the ambition to deploy arrays of autonomous geophysical instrument platforms in remote regions. This is particularly true in the southern polar regions where measurements are presently sparse due to the remoteness, lack of infrastructure, and harshness of the environment. The need for the acquisition of continuous long-term data from remote polar locations exists across geophysical disciplines and is a generic infrastructure problem. The infrastructure, however, to support autonomous instrument platforms in polar environments is still in the early stages of development. We report here the development of an autonomous low-power magnetic variation data collection system. Following 2 years of field testing at the south pole station, the system is being reproduced to establish a dense chain of stations on the Antarctic plateau along the 40 degrees magnetic meridian. The system is designed to operate for at least 5 years unattended and to provide data access via satellite communication. The system will store 1 s measurements of the magnetic field variation (<0.2 nT resolution) in three vector components plus a variety of engineering status and environment parameters. We believe that the data collection platform can be utilized by a variety of low-power instruments designed for low-temperature operation. The design, technical characteristics, and operation results are presented here.

  19. A unified charge-based model for SOI MOSFETs applicable from intrinsic to heavily doped channel

    Institute of Scientific and Technical Information of China (English)

    Zhang Jian; Han Yu; Chan Mansun; He Jin; Zhou Xing-Ye; Zhang Li-Ning; Ma Yu-Tao; Chen Qin; Zhang Xu-Kai; Yang Zhang; Wang Rui-Fei

    2012-01-01

    A unified charge-based model for fully depleted silicon-on-insulator (SOI) metal-oxide semiconductor field-effect transistors (MOSFETs) is presented.The proposed model is accurate and applicable from intrinsic to heavily doped channels with various structure parameters.The framework starts from the one-dimensional Poisson-Boltzmann equation,and based on the full depletion approximation,an accurate inversion charge density equation is obtained.With the inversion charge density solution,the unified drain current expression is derived,and a unified terminal charge and intrinsic capacitance model is also derived in the quasi-static case.The validity and accuracy of the presented analytic model is proved by numerical simulations.

  20. Investigation of switching mechanism in HfOx-ReRAM under low power and conventional operation modes

    Science.gov (United States)

    Feng, Wei; Shima, Hisashi; Ohmori, Kenji; Akinaga, Hiroyuki

    2016-12-01

    Low-power resistive random access memory (LP-ReRAM) devices have attracted increasing attention owing to their advantages of low operation power. In this study, a vertical-type LP-ReRAM consisting of TiN/Ti/HfO2/TiN structure was fabricated. The switching mechanism for LP-ReRAM was elucidated as the conductive filament mechanism for conventional mode, and an interface-type switching mechanism for low power mode was proposed. The analysis of low frequency noise shows that power spectral density (PSD) is approximately proportional to 1/f for conventional operation mode. Nevertheless, for low power mode, the PSD of low resistance state (LRS) is proportional to 1/f, while that of high resistance state (HRS) is clear proportional to 1/f2. The envelope of multiple Lorentzian spectra of 1/f2 characteristics due to different traps reveals the characteristics of 1/f. For HRS of low power mode, a limited number of traps results in a characteristic of 1/f2. During the set process, the number of oxygen vacancies increases for LRS. Therefore, the PSD value is proportional to 1/f. Owing to the increase in the number of traps when the operation mode changes to conventional mode, the PSD value is proportional to 1/f. To the best of our knowledge, this is the first study that reveals the different noise characteristics in the low power operation mode from that in the conventional operation mode.

  1. Methane Emissions from Permafrost Regions using Low-Power Eddy Covariance Stations

    Science.gov (United States)

    Burba, G.; Sturtevant, C.; Schreiber, P.; Peltola, O.; Zulueta, R.; Mammarella, I.; Haapanala, S.; Rinne, J.; Vesala, T.; McDermitt, D.; Oechel, W.

    2012-04-01

    result, spatial coverage of eddy covariance methane flux measurements remains limited. Remote permafrost wetlands of Arctic tundra, northern boreal peatlands of Canada and Siberia, and other highly methanogenic ecosystems have few eddy covariance methane measurement stations. Those existing are often located near grid power sources and roads rather than in the middle of the methane-producing ecosystem, while those that are placed appropriately may require extraordinary efforts to build and maintain them, with large investments into man-power and infrastructure. Alternatively, open-path approach allows methane flux measurements at ambient pressure without the need for a pump. As a result, the measurements can be done with very low-power (e.g. 5-10 Watts), light (5 .2 kg) instruments permitting solar- and wind- powered remote deployments in hard-to-reach sites from permanent, portable or mobile stations, and cost-effective additions of a methane measurement to the present array of CO2 and H2O measurements. The low-power operation and light weight of open-path eddy covariance stations is important for a number of ecosystems (rice fields, landfills, wetlands, cattle yards), but it is especially important for permafrost regions where grid power and access roads are generally not available, and the logistics of running the experiments are particularly expensive. Emerging research on methane flux measurements using low-power stations equipped with LI-7700 open-path methane analyzer (LI-COR Biosciences) are presented from several permafrost ecosystems with contrasting setups, and weather conditions. Principles of operation, station characteristics and requirements are also discussed.

  2. LOW POWER BRACHYTHERAPY IN COMBINED TREATMENT IN PATIENTS WITH INTERMEDIATE RISK OF LOCALIZED PROST ATE CANCER

    Directory of Open Access Journals (Sweden)

    V. A. Biryukov

    2014-01-01

    Full Text Available Objective. Estimation of the effectiveness of low power brachytherapy sources I-125 in the combined treatment in group of patients of intermediate risk of localized prostate cancer.Material and methods. The study included 126 patients with prostate cancer of intermediate risk. 104 patients (83,9% were conducted low power brachytherapy I‑125 in combination with hormone therapy by analogues of LHWG. 22 patients (16.1% received external beam irradiation in combination with brachytherapy I‑125 and hormonal treatment. Relapse-free survival of patients was evaluated in accordance with the criteria Phoenix (Nadir PSA + ng/ml. Evaluation of side effects of radiation treatment were carried out according to the RTOG criteria.Results. PSA relapse-free survival in the group of brachytherapy and hormone treatment at the time of observation 5 years amounted to 97.1%. In the group of combined radiation therapy with brachytherapy, and hormonal treatment PSA relapse-free survival rate was 95.5%.In both groups, relapse-free survival was noted in 96,8% of cases. Tumor-specific and overall survival in bothgroups was 100%. The major complications of treatment in both groups were radiation urethritis 1 to 2 degrees in 9.5% of cases (12 patients, urethral stricture in 5 patients (3.9% of cases, acute urinary retention in 1 patient (0.8% of cases and late radiation rectitis of 2 degree in 1.58% of cases (2 patients.Conclusions. It is possible to draw tentative conclusions about the high rate of survival without progression in both treatment groups on the background of the relatively low frequency of adverse reactions. It is necessary further follow-up for patients with estimating of survival for a longer period.

  3. Physics, fabrication and characterization of III-V multi-gate FETs for low power electronics

    Science.gov (United States)

    Thathachary, Arun V.

    With transistor technology close to its limits for power constrained scaling and the simultaneous emergence of mobile devices as the dominant driver for new scaling, a pathway to significant reduction in transistor operating voltage to 0.5V or lower is urgently sought. This however implies a fundamental paradigm shift away from mature Silicon technology. III-V compound semiconductors hold great promise in this regard due to their vastly superior electron transport properties making them prime candidates to replace Silicon in the n-channel transistor. Among the plethora of binary and ternary compounds available in the III-V space, InxGa1-xAs alloys have attracted significant interest due to their excellent electron mobility, ideally placed bandgap and mature growth technology. Simultaneously, electrostatic control mandates multigate transistor designs such as the FinFET at extremely scaled nodes. This dissertation describes the experimental realization of III-V FinFETs incorporating InXGa1-XAs heterostructure channels for high performance, low power logic applications. The chapters that follow present experimental demonstrations, simulations and analysis on the following aspects (a) motivation and key figures of merit driving material selection and design; (b) dielectric integration schemes for high-k metal-gate stack (HKMG) realization on InXGa 1-XAs, including surface clean and passivation techniques developed for high quality interfaces; (c) novel techniques for transport (mobility) characterization in nanoscale multi-gate FET architectures with experimental demonstration on In0.7Ga0.3As nanowires; (d) Indium composition and quantum confined channel design for InXGa 1-XAs FinFETs and (e) InAs heterostructure designs for high performance FinFETs. Each chapter also contains detailed benchmarking of results against state of the art demonstrations in Silicon and III-V material systems. The dissertation concludes by assessing the feasibility of InXGa 1-XAs Fin

  4. A low-power configurable neural recording system for epileptic seizure detection.

    Science.gov (United States)

    Qian, Chengliang; Shi, Jess; Parramon, Jordi; Sánchez-Sinencio, Edgar

    2013-08-01

    This paper describes a low-power configurable neural recording system capable of capturing and digitizing both neural action-potential (AP) and fast-ripple (FR) signals. It demonstrates the functionality of epileptic seizure detection through FR recording. This system features a fixed-gain, variable-bandwidth (BW) front-end circuit and a sigma-delta ADC with scalable bandwidth and power consumption. The ADC employs a 2nd-order single-bit sigma-delta modulator (SDM) followed by a low-power decimation filter. Direct impulse-response implementation of a sinc(3) filter and 8-cycle data pipelining in an IIR filter are proposed for the decimation filter design to improve the power and area efficiency. In measurements, the front end exhibits 39.6-dB DC gain, 0.8 Hz to 5.2 kHz of BW, 5.86- μVrms input-referred noise, and 2.4- μW power consumption in AP mode, while showing 38.5-dB DC gain, 250 to 486 Hz of BW, 2.48- μVrms noise, and 4.5- μW power consumption in FR mode. The noise efficiency factor (NEF) is 2.93 and 7.6 for the AP and FR modes, respectively. At 77-dB dynamic range (DR), the ADC has a peak SNR and SNDR of 75.9 dB and 67 dB, respectively, while consuming 2.75-mW power in AP mode. It achieves 78-dB DR, 76.2-dB peak SNR, 73.2-dB peak SNDR, and 588- μW power consumption in FR mode. Both analog and digital power supply voltages are 2.8 V. The chip is fabricated in a standard 0.6- μm CMOS process. The die size is 11.25 mm(2).

  5. Power Management and SRAM for Energy-Autonomous and Low-Power Systems

    Science.gov (United States)

    Chen, Gregory K.

    We demonstrate the two first-known, complete, self-powered millimeter-scale computer systems. These microsystems achieve zero-net-energy operation using solar energy harvesting and ultra-low-power circuits. A medical implant for monitoring intraocular pressure (IOP) is presented as part of a treatment for glaucoma. The 1.5mm3 IOP monitor is easily implantable because of its small size and measures IOP with 0.5mmHg accuracy. It wirelessly transmits data to an external wand while consuming 4.70nJ/bit. This provides rapid feedback about treatment efficacies to decrease physician response time and potentially prevent unnecessary vision loss. A nearly-perpetual temperature sensor is presented that processes data using a 2.1muW near-threshold ARMRTM Cortex-M3(TM) muP that provides a widely-used and trusted programming platform. Energy harvesting and power management techniques for these two microsystems enable energy-autonomous operation. The IOP monitor harvests 80nW of solar power while consuming only 5.3nW, extending lifetime indefinitely. This allows the device to provide medical information for extended periods of time, giving doctors time to converge upon the best glaucoma treatment. The temperature sensor uses on-demand power delivery to improve low-load dc-dc voltage conversion efficiency by 4.75x. It also performs linear regulation to deliver power with low noise, improved load regulation, and tight line regulation. Low-power high-throughput SRAM techniques help millimeter-scale microsystems meet stringent power budgets. VDD scaling in memory decreases energy per access, but also decreases stability margins. These margins can be improved using sizing, VTH selection, and assist circuits, as well as new bitcell designs. Adaptive Crosshairs modulation of SRAM power supplies fixes 70% of parametric failures. Half-differential SRAM design improves stability, reducing VMIN by 72mV. The circuit techniques for energy autonomy presented in this dissertation enable

  6. Back End of Line Nanorelays for Ultra-low Power Monolithic Integrated NEMS-CMOS Circuits

    KAUST Repository

    Lechuga Aranda, Jesus Javier

    2016-05-01

    Since the introduction of Complementary-Metal-Oxide-Semiconductor (CMOS) technology, the chip industry has enjoyed many benefits of transistor feature size scaling, including higher speed and device density and improved energy efficiency. However, in the recent years, the IC designers have encountered a few roadblocks, namely reaching the physical limits of scaling and also increased device leakage which has resulted in a slow-down of supply voltage and power density scaling. Therefore, there has been an extensive hunt for alternative circuit architectures and switching devices that can alleviate or eliminate the current crisis in the semiconductor industry. The Nano-Electro-Mechanical (NEM) relay is a promising alternative switch that offers zero leakage and abrupt turn-on behaviour. Even though these devices are intrinsically slower than CMOS transistors, new circuit design techniques tailored for the electromechanical properties of such devices can be leveraged to design medium performance, ultra-low power integrated circuits. In this thesis, we deal with a new generation of such devices that is built in the back end of line (BEOL) CMOS process and is an ideal option for full integration with current CMOS transistor technology. Simulation and verification at the circuit and system level is a critical step in the design flow of microelectronic circuits, and this is especially important for new technologies that lack the standard design infrastructure and well-known verification platforms. Although most of the physical and electrical properties of NEM structures can be simulated using standard electronic automation software, there is no report of a reliable behavioural model for NEMS switches that enable large circuit simulations. In this work, we present an optimised model of a BEOL nano relay that encompasses all the electromechanical characteristics of the device and is robust and lightweight enough for VLSI applications that require simulation of thousands of

  7. On the capacity of multiple access and broadcast fading Channels with full channel state information at low power regime

    KAUST Repository

    Rezki, Zouheir

    2013-07-01

    We study the throughput capacity region of the Gaussian multi-access (MAC) fading channel with perfect channel state information (CSI) at the receiver and at the transmitters (CSI-TR), at low power regime. We show that it has a multidimensional rectangle structure and thus is simply characterized by single user capacity points. More specifically, we show that at low power regime, the boundary surface of the capacity region shrinks to a single point corresponding to the sum-rate maximizer and that the coordinates of this point coincide with single user capacity bounds. Using the duality of Gaussian MAC and broadcast channels (BC), we provide a simple characterization of the BC capacity region at low power regime. © 2013 IEEE.

  8. A Design of Low Power Single Axis Solar Tracking System Regardless of Motor Speed

    Directory of Open Access Journals (Sweden)

    Asmarashid Ponniran

    2011-12-01

    Full Text Available Solar power generation had been used as a renewable energy since years ago. Residential that uses solar power as their alternative power supply will bring benefits to them. The main objective of this paper is to present development of an automatic solar tracking system whereby the system will caused solar panels will keep aligned with the Sunlight in order to maximize in harvesting solar power. The system focuses on the controller design whereby it will caused the system is able to tracks the maximum intensity of Sunlight is hit. When the intensity of Sunlight is decreasing, this system automatically changes its direction to get maximum intensity of Sunlight. LDR light detector acts as a sensor is used to trace the coordinate of the Sunlight by detecting brightness level of Sunlight. While to rotate the appropriate position of the panel, a DC-geared motor is used. The system is controlled by two relays as a DC-geared motor driver and a microcontroller as a main processor. This project is covered for a single axis and is designed for low power and residential usage applications. From the hardware testing, the system is able to track and follow the Sunlight intensity in order to get maximum solar power at the output regardless motor speed.

  9. Low-power light and isolated rat hearts after ischemia of myocardium

    Science.gov (United States)

    Monich, Victor A.; Drugova, Olga V.; Lazukin, Valery F.; Bavrina, Anna B.

    2010-02-01

    Total ischemia of myocardium has been simulated on isolated hearts of rats. Effects of a low-power HeNe laser (λ=632.8 nm) and a fiber optic photo-luminescent radiation source of red light ( λ of the spectral peak is equal to 630 nm) on isolated heart contractile function characteristics and on lipid peroxidation (LPO) level in myocardium tissues have been investigated. Two groups of the specimens have been irradiated with red light during the postischemia (reperfusion) period of time. The first group has been treated with laser light and the second one with the luminescent radiation. More rapid restoration of the speed of contraction, of the force of contraction, of the relaxation speed and of the heart rate with respect to the data of the control group has been observed in both experimental groups. The similar tendency was observed in the laser treated specimens. The effects of fibrillation of myocardium of isolated hearts irradiated by lowpower He-Ne laser light were observed. These effects could be caused by the local light fluence rate excess in the interference pattern of laser light diffracted on the heart muscle structures.

  10. Relaxation of vascular smooth muscle induced by low-power laser radiation.

    Science.gov (United States)

    Chaudhry, H; Lynch, M; Schomacker, K; Birngruber, R; Gregory, K; Kochevar, I

    1993-11-01

    The relaxation of rabbit aorta rings induced by low-power laser radiation was investigated in vitro to determine the location of the chromophore(s) responsible for this response and evaluate possible mechanisms. An action spectrum for relaxation was measured on rabbit thoracic aorta rings precontracted with norepinephrine. The decrease in isometric tension was measured during exposure to laser light (351-625 nm) delivered via a fiber optic to a small spot on the adventitial surface. The shortest UV wavelength (351 nm) was 35-fold more effective than 390 nm and 1700-fold more effective than 460 nm. Ultraviolet wavelengths also produced greater maximum relaxation (0.40-0.45) than visible wavelengths (0.20-0.25), suggesting that photovasorelaxation involves more than one chromophore. The adventitial layer was not necessary for photovasorelaxation, indicating that the light is absorbed by a chromophore in the medial layer. The same degree of relaxation was obtained on rings without adventitia when either one-half of the ring, or a small spot was irradiated indicating that communication between smooth muscle cells spreads a signal from the area illuminated to the entire ring. The mechanism for photovasorelaxation was investigated using potential inhibitors. N-monomethyl-L-arginine and N-amino-L-arginine, inhibitors of nitric oxide synthase, did not alter photovasorelaxation nor did indomethacin, an inhibitor of cyclooxygenase, and zinc protoporphyrin, an inhibitor of heme oxygenase.

  11. A heterogeneous multiprocessor architecture for low-power audio signal processing applications

    DEFF Research Database (Denmark)

    Paker, Ozgun; Sparsø, Jens; Haandbæk, Niels;

    2001-01-01

    . The processors are tailored for different classes of filtering algorithms (FIR, IIR, N-LMS etc.), and in a typical system the communication among processors occurs at the sampling rate only. The processors are parameterized in word-size, memory-size, etc. and can be instantiated according to the needs...... of the application at hand using a normal synthesis based ASIC design flow. To give an impression of the size of a processor we mention that one of the FIR processors in a prototype design has 16 instructions, a 32 word×16 bit program memory, a 64 word×16 bit data memory and a 25 word×16 bit coefficient memory....... Early results obtained from the design of a prototype chip containing filter processors for a hearing aid application, indicate a power consumption that is an order of magnitude better than current state of the art low-power audio DSPs implemented using full-custom techniques. This is due to: (1...

  12. Linear-phase delay filters for ultra-low-power signal processing in neural recording implants.

    Science.gov (United States)

    Gosselin, Benoit; Sawan, Mohamad; Kerherve, Eric

    2010-06-01

    We present the design and implementation of linear-phase delay filters for ultra-low-power signal processing in neural recording implants. We use these filters as low-distortion delay elements along with an automatic biopotential detector to perform integral waveform extraction and efficient power management. The presented delay elements are realized employing continuous-time OTA-C filters featuring 9th-order equiripple transfer functions with constant group delay. Such analog delay enables processing neural waveforms with reduced overhead compared to a digital delay since it does not requires sampling and digitization. It uses an allpass transfer function for achieving wider constant-delay bandwidth than all-pole does. Two filters realizations are compared for implementing the delay element: the Cascaded structure and the Inverse follow-the-leader feedback filter. Their respective strengths and drawbacks are assessed by modeling parasitics and non-idealities of OTAs, and by transistor-level simulations. A budget of 200 nA is used in both filters. Experimental measurements with the chosen filter topology are presented and discussed.

  13. The power of glove: Soft microbial fuel cell for low-power electronics

    Science.gov (United States)

    Winfield, Jonathan; Chambers, Lily D.; Stinchcombe, Andrew; Rossiter, Jonathan; Ieropoulos, Ioannis

    2014-03-01

    A novel, soft microbial fuel cell (MFC) has been constructed using the finger-piece of a standard laboratory natural rubber latex glove. The natural rubber serves as structural and proton exchange material whilst untreated carbon veil is used for the anode. A soft, conductive, synthetic latex cathode is developed that coats the outside of the glove. This inexpensive, lightweight reactor can without any external power supply, start up and energise a power management system (PMS), which steps-up the MFC output (0.06-0.17 V) to practical levels for operating electronic devices (>3 V). The MFC is able to operate for up to 4 days on just 2 mL of feedstock (synthetic tryptone yeast extract) without any cathode hydration. The MFC responds immediately to changes in fuel-type when the introduction of urine accelerates the cycling times (35 vs. 50 min for charge/discharge) of the MFC and PMS. Following starvation periods of up to 60 h at 0 mV the MFC is able to cold start the PMS simply with the addition of 2 mL fresh feedstock. These findings demonstrate that cheap MFCs can be developed as sole power sources and in conjunction with advancements in ultra-low power electronics, can practically operate small electrical devices.

  14. Flexible low-power RF nanoelectronics in the GHz regime using CVD MoS2

    Science.gov (United States)

    Yogeesh, Maruthi

    Two-dimensional (2D) materials have attracted substantial interest for flexible nanoelectronics due to the overall device mechanical flexibility and thickness scalability for high mechanical performance and low operating power. In this work, we demonstrate the first MoS2 RF transistors on flexible substrates based on CVD-grown monolayers, featuring record GHz cutoff frequency (5.6 GHz) and saturation velocity (~1.8×106 cm/s), which is significantly superior to contemporary organic and metal oxide thin-film transistors. Furthermore, multicycle three-point bending results demonstrated the electrical robustness of our flexible MoS2 transistors after 10,000 cycles of mechanical bending. Additionally, basic RF communication circuit blocks such as amplifier, mixer and wireless AM receiver have been demonstrated. These collective results indicate that MoS2 is an ideal advanced semiconducting material for low-power, RF devices for large-area flexible nanoelectronics and smart nanosystems owing to its unique combination of large bandgap, high saturation velocity and high mechanical strength.

  15. Fabrication of microchannels on PMMA using a low power CO2 laser

    Science.gov (United States)

    Imran, Muhammad; Rahman, Rosly A.; Ahmad, Mukhtar; Akhtar, Majid N.; Usman, Arslan; Sattar, Abdul

    2016-09-01

    This study presents a cheap and quick method for the formation of microchannels on poly methyl methacrylate (PMMA). A continuous wave CO2 laser with a wavelength of 10.6 μm was used to inscribe periodic ripple structures on a PMMA substrate. A direct writing technique was employed for micromachining. As PMMA is very sensitive to such laser irradiations, a slightly low power CO2 laser was effective in inscribing such periodic structures. The results show that smooth and fine ripple structures can be fabricated by controlling the input laser parameters and interaction time of the laser beam. This direct laser writing technique is promising enough to prevent us from using complex optical arrangements. Laser power was tested starting from the ablation threshold and was gradually increased, together with the variation in scanning speed of the xy-translational stage, to observe the effects on the target surface in terms of depth and width of trenches. It was observed that the depth of the trenches increases on increasing the laser power, and the bulge formation on the outer sides of the trenches was also studied. It was evident that the formation of bulges across the trenches is dependent on the scanning speed and input laser power. The results depict that a focused laser beam with optimized parameters, such as controlling the scanning speed and laser power, results in fine, regular and tidy periodic structures.

  16. Investigation of a Novel Common Subexpression Elimination Method for Low Power and Area Efficient DCT Architecture

    Directory of Open Access Journals (Sweden)

    M. F. Siddiqui

    2014-01-01

    Full Text Available A wide interest has been observed to find a low power and area efficient hardware design of discrete cosine transform (DCT algorithm. This research work proposed a novel Common Subexpression Elimination (CSE based pipelined architecture for DCT, aimed at reproducing the cost metrics of power and area while maintaining high speed and accuracy in DCT applications. The proposed design combines the techniques of Canonical Signed Digit (CSD representation and CSE to implement the multiplier-less method for fixed constant multiplication of DCT coefficients. Furthermore, symmetry in the DCT coefficient matrix is used with CSE to further decrease the number of arithmetic operations. This architecture needs a single-port memory to feed the inputs instead of multiport memory, which leads to reduction of the hardware cost and area. From the analysis of experimental results and performance comparisons, it is observed that the proposed scheme uses minimum logic utilizing mere 340 slices and 22 adders. Moreover, this design meets the real time constraints of different video/image coders and peak-signal-to-noise-ratio (PSNR requirements. Furthermore, the proposed technique has significant advantages over recent well-known methods along with accuracy in terms of power reduction, silicon area usage, and maximum operating frequency by 41%, 15%, and 15%, respectively.

  17. An ultra low-power front-end IC for wearable health monitoring system.

    Science.gov (United States)

    Yu-Pin Hsu; Zemin Liu; Hella, Mona M

    2016-08-01

    This paper presents a low-power front-end IC for wearable health monitoring systems. The IC, designed in a standard 0.13μm CMOS technology, fully integrates a low-noise analog front-end (AFE) to process the weak bio-signals, followed by an analog-to-digital converter (ADC) to digitize the extracted signals. An AC-coupled driving buffer, that interfaces between the AFE and the ADC is introduced to scale down the power supply of the ADC. The power consumption decreases by 50% compared to the case without power supply scaling. The AFE passes signals from 0.5Hz to 280Hz and from 0.7Hz to 160Hz with a simulated input referred noise of 1.6μVrms and achieves a maximum gain of 35dB/41dB respectively, with a noise-efficiency factor (NEF) of the AFE is 1. The 8-bit ADC achieves a simulated 7.96-bit resolution at 10KS/s sampling rate under 0.5V supply voltage. The overall system consumes only 0.86μW at dual supply voltages of 1V (AFE) and 0.5 V (ADC).

  18. Miniaturized Low-power Electro-optic Modulator Based on Silicon Integrated Nanophotonics and Organic Polymers

    CERN Document Server

    Zhang, Xingyu; Luo, Jingdong; Jen, Alex K -Y; Chen, Ray T

    2014-01-01

    We design and demonstrate a compact, low-power, low-dispersion and broadband optical modulator based on electro-optic (EO) polymer refilled silicon slot photonic crystal waveguide (PCW). The EO polymer is engineered for large EO activity and near-infrared transparency. The half-wave switching-voltage is measured to be V{\\pi}=0.97V over optical spectrum range of 8nm, corresponding to a record-high effective in-device r33 of 1190pm/V and V{\\pi} L of 0.291Vmm in a push-pull configuration. Excluding the slow-light effect, we estimate the EO polymer is poled with an ultra-high efficiency of 89pm/V in the slot. In addition, to achieve high-speed modulation, silicon PCW is selectively doped to reduce RC time delay. The 3-dB RF bandwidth of the modulator is measured to be 11GHz, and a modulation response up to 40GHz is observed.

  19. First X-ray observations of Low-Power Compact Steep Spectrum Sources

    CERN Document Server

    Kunert-Bajraszewska, M; Siemiginowska, A; Guainazzi, M

    2013-01-01

    We report first X-ray Chandra observations of a sample of seven low luminosity compact (LLC) sources. They belong to a class of young compact steep spectrum (CSS) radio sources. Four of them have been detected, the other three have upper limit estimations for X-ray flux, one CSS galaxy is associated with an X-ray cluster. We have used the new observations together with the observational data for known strong CSS and gigahertz-peaked spectrum (GPS) objects and large scale FRIs and FRIIs to study the relation between morphology, X-ray properties and excitation modes in radio-loud AGNs. We found that: (1) The low power objects fit well to the already established X-ray - radio luminosity correlation for AGNs and occupy the space among, weaker in the X-rays, FRI objects. (2) The high excitation galaxies (HEG) and low excitation galaxies (LEG) occupy distinct locus in the radio/X-ray luminosity plane, notwithstanding their evolutionary stage. This is in agreement with the postulated different origin of the X-ray em...

  20. Hydrodynamic and performance of low power turbines: conception, modelling and experimental tests

    Directory of Open Access Journals (Sweden)

    Mariana. Simão, Helena M. Ramos

    2010-05-01

    Full Text Available The present work comprises a research about hydraulic machines with the aim of optimization and the selection of adequate turbines of low power for exploitation of an available energy still unexplored in water supply systems based on analyses of 3D hydrodynamic flows and on characteristic curves which lead to the best efficiency point. The analysis is carried out based on non-dimensional parameters (i.e., discharge, head, efficiency, runner speed and mechanical power in order to be possible comparisons. Mathematical models based on the physical principles, associated to the development of volumetric and rotordynamic machines, are developed. New turbines are suggested, which are based on similar theory among turbo machines based on applications in hydraulic systems with guarantee discharge and available head. The hydrodynamic fluid mechanical analysis requires the use of complex advanced models (CFD which apply the equations of Navier-Stokes by using mathematical models of conservation laws, for the study of the turbulent flow behaviour. To determine the correlation between the flow velocity and pressure fields, the k-? model, is used in this research. Many turbines are evaluated (i.e., positive displacement (PD, pump as turbine (PAT, propeller with volute at inlet, four and five blades tubular propellers and sensitivity analyses, to the best configurations, as well as comparisons between performance curves and experimental tests. Results are presented with the appropriate range variation for each turbine type and application.

  1. Low-power laser irradiation of blood inhibits platelet function: role of cyclic GMP

    Science.gov (United States)

    Brill, Alexander G.; Brill, Gregory E.; Shenkman, Boris; Tamarin, Ilya; Dardik, Rima; Varon, David; Savion, Naphtali

    1998-12-01

    The aim of the present work was to investigate effect of low power laser irradiation (LPLI) on platelet function in vitro. He-Ne laser (Optronix, USA; (lambda) - 632.8 nm, output power - 7 mW) was employed. Platelet adhesion and aggregation in whole blood (WB) under defined shear conditions were assayed by a Cone and Plate(let) Analyzer. Platelet activation was evaluated by flow cytometry. Level of platelet cGMP was estimated by immunoenzyme assay. Experiments performed showed that LPLI of WB resulted in decrease of platelet deposition on extracellular matrix at high shear rate (1300 s-1). Similar results were obtained using surfaces precoated with either collagen type I or von Willebrand factor. LPLI inhibited fibrinogen binding as well as P-selectin expression on the platelet membrane, induced by thrombin analogue. It was found out that primary acceptor of laser energy responsible for the effect on platelets was located in platelets themselves and not in blood plasma or in other blood cells. LPLI of gel- filtered platelets resulted in increase of intracellular level of cGMP both in the absence and in presence of izobutylmethylxantine (phosphodiesterase inhibitor) suggesting stimulation of synthesis rather than destruction of cGMP under the influence of LPLI. It is suggested that guanylate cyclase and/or NO-synthase might serve as primary acceptors of He-Ne laser light in platelets.

  2. Microbial fuel cells as power supply of a low-power temperature sensor

    Science.gov (United States)

    Khaled, Firas; Ondel, Olivier; Allard, Bruno

    2016-02-01

    Microbial fuel cells (MFCs) show great promise as a concomitant process for water treatment and as renewable energy sources for environmental sensors. The small energy produced by MFCs and the low output voltage limit the applications of MFCs. Specific converter topologies are required to step-up the output voltage of a MFC. A Power Management Unit (PMU) is proposed for operation at low input voltage and at very low power in a completely autonomous way to capture energy from MFCs with the highest possible efficiency. The application of sensors for monitoring systems in remote locations is an important approach. MFCs could be an alternative energy source in this case. Powering a sensor with MFCs may prove the fact that wastewater may be partly turned into renewable energy for realistic applications. The Power Management Unit is demonstrated for 3.6 V output voltage at 1 mW continuous power, based on a low-cost 0.7-L MFC. A temperature sensor may operate continuously on 2-MFCs in continuous flow mode. A flyback converter under discontinuous conduction mode is also tested to power the sensor. One continuously fed MFC was able to efficiently and continuously power the sensor.

  3. Low-power laser irradiation inhibits Aβ25-35-induced cell apoptosis through Akt activation

    Science.gov (United States)

    Zhang, Zhigang; Tang, Yonghong

    2009-08-01

    Low-power laser irradiation (LPLI) can modulate various cellular processes such as proliferation, differentiation and apoptosis. Recently, LPLI has been applied to moderate Alzheimer's disease (AD), but the underlying mechanism remains unknown. The protective role of LPLI against the amyloid beta peptide (Aβ), a major constituent of AD plaques, has not been studied. PI3K/Akt pathway is extremely important in protecting cells from apoptosis caused by diverse stress stimuli. However, whether LPLI can inhibit Aβ-induced apoptosis through Akt activation is still unclear. In current study, using FRET (fluorescence resonance energy transfer) technique, we investigated the activity of Akt in response to LPLI treatment. B kinase activity reporter (BKAR), a recombinant FRET probe of Akt, was utilized to dynamically detect the activation of Akt after LPLI treatment. The results show that LPLI promoted the activation of Akt. Moreover, LPLI inhibits apoptosis induced by Aβ25-35 and the apoptosis inhibition can be abolished by wortmannin, a specific inhibitor of PI3K/Akt. Taken together, these results suggest that LPLI can inhibit Aβ25-35-induced cell apoptosis through Akt activation.

  4. Low power proton exchange membrane fuel cell system identification and adaptive control

    Science.gov (United States)

    Yang, Yee-Pien; Wang, Fu-Cheng; Chang, Hsin-Ping; Ma, Ying-Wei; Weng, Biing-Jyh

    This paper proposes a systematic method of system identification and control of a proton exchange membrane (PEM) fuel cell. This fuel cell can be used for low-power communication devices involving complex electrochemical reactions of nonlinear and time-varying dynamic properties. From a system point of view, the dynamic model of PEM fuel cell is reduced to a configuration of two inputs, hydrogen and air flow rates, and two outputs, cell voltage and current. The corresponding transfer functions describe linearized subsystem dynamics with finite orders and time-varying parameters, which are expressed as discrete-time auto-regression moving-average with auxiliary input models for system identification by the recursive least square algorithm. In the experiments, a pseudo-random binary sequence of hydrogen or air flow rate is fed to a single fuel cell device to excite its dynamics. By measuring the corresponding output signals, each subsystem transfer function of reduced order is identified, while the unmodeled, higher-order dynamics and disturbances are described by the auxiliary input term. This provides a basis of adaptive control strategy to improve the fuel cell performance in terms of efficiency, as well as transient and steady state specifications. Simulation shows that adaptive controller is robust to the variation of fuel cell system dynamics, and it has proved promising from the experimental results.

  5. LOW POWER-AREA DESIGN OF FULL ADDER USING SELF RESETTING LOGIC WITH GDI TECHNIQUE

    Directory of Open Access Journals (Sweden)

    Simran Khokha1

    2016-08-01

    Full Text Available Various electronic devices such as mobile phones, DSPs,ALU etc., are designed by using VLSI (Very Large Scale Integration technology. In VLSI dynamic CMOS logic circuits are concentrating on the Area ,reducing the power consumption and increasing the Speed by reducing the delay. ALU (Arithmetic Logic Circuits are designed by using adder, subtractors, multiplier, divider, etc.Various adder circuits designs have been proposed over last few years with different logic styles. To reduce the power consumption several parameters are to be taken into account, such as feedthrough, leakage power single-event upsets, charge sharing by parasitic components while connecting source and drain of CMOS transistors There are situations in a logic that permit the use of circuits that can automatically precharge themselves (i.e., reset themselves after some prescribed delays. These circuits are hence called postcharge or self-resetting logic which are widely used in dynamic logic circuits. Overall performance of various adder designs is evaluated by using Tanner tool . The earlier and the proposed SRLGDI primitives are simulated using Tanner EDA with BSIM 0.250 lm technology with supply voltage ranging from 0 V to 5 V in steps of 0.2 V. On comparing the various SRLGDI logic adders, the proposed adder shows low power, delay and low PDP among its counterparts.

  6. A Low-Power High-Speed Smart Sensor Design for Space Exploration Missions

    Science.gov (United States)

    Fang, Wai-Chi

    1997-01-01

    A low-power high-speed smart sensor system based on a large format active pixel sensor (APS) integrated with a programmable neural processor for space exploration missions is presented. The concept of building an advanced smart sensing system is demonstrated by a system-level microchip design that is composed with an APS sensor, a programmable neural processor, and an embedded microprocessor in a SOI CMOS technology. This ultra-fast smart sensor system-on-a-chip design mimics what is inherent in biological vision systems. Moreover, it is programmable and capable of performing ultra-fast machine vision processing in all levels such as image acquisition, image fusion, image analysis, scene interpretation, and control functions. The system provides about one tera-operation-per-second computing power which is a two order-of-magnitude increase over that of state-of-the-art microcomputers. Its high performance is due to massively parallel computing structures, high data throughput rates, fast learning capabilities, and advanced VLSI system-on-a-chip implementation.

  7. Low-Power, 8-Channel EEG Recorder and Seizure Detector ASIC for a Subdermal Implantable System.

    Science.gov (United States)

    Do Valle, Bruno G; Cash, Sydney S; Sodini, Charles G

    2016-12-01

    EEG remains the mainstay test for the diagnosis and treatment of patients with epilepsy. Unfortunately, ambulatory EEG systems are far from ideal for patients who have infrequent seizures. These systems only last up to 3 days and if a seizure is not captured during the recordings, a definite diagnosis of the patient's condition cannot be given. This work aims to address this need by proposing a subdermal implantable, eight-channel EEG recorder and seizure detector that has two modes of operation: diagnosis and seizure counting. In the diagnosis mode, EEG is continuously recorded until a number of seizures are recorded. In the seizure counting mode, the system uses a low-power algorithm to track the number of seizures a patient has, providing doctors with a reliable count to help determine medication efficacy or other clinical endpoint. An ASIC that implements the EEG recording and seizure detection algorithm was designed and fabricated in a 0.18 μm CMOS process. The ASIC includes eight EEG channels and is designed to minimize the system's power and size. The result is a power-efficient analog front end that requires 2.75 μW per channel in diagnosis mode and 0.84 μW per channel in seizure counting mode. Both modes have an input referred noise of approximately 1.1 μVrms.

  8. A low power CMOS VCO using inductive-biasing with high performance FoM

    Science.gov (United States)

    Weihao, Liu; Lu, Huang

    2016-04-01

    A novel voltage-controlled oscillator (VCO) topology with low voltage and low power is presented. It employed the inductive-biasing to build a feedback path between the tank and the MOS gate to enhance the voltage gain from output nodes of the tank to the gate node of the cross-coupled transistor. Theoretical analysis using time-varying phase noise theory derives closed-form symbolic formulas for the 1/f 2 phase noise region, showing that this feedback path could improve the phase noise performance. The proposed VCO is fabricated in TSMC 0.13 μm CMOS technology. Working under a 0.3 V supply voltage with 1.2 mW power consumption, the measured phase noise of the VCO is -119.4 dBc/Hz at 1 MHz offset frequency from the carrier of 4.92 GHz, resulting in an FoM of 192.5 dBc/Hz. Project supported by the National Science and Technology Major Project of China (No. 2011ZX03004-002-01).

  9. Low power analog readout front-end electronics for time and energy measurements

    Energy Technology Data Exchange (ETDEWEB)

    Kleczek, R., E-mail: rafal.kleczek@agh.edu.pl; Grybos, P.; Szczygiel, R.

    2014-06-01

    We report on the design and measurements of an analog front-end readout electronics dedicated for silicon microstrip detectors with relatively large capacitance of the order of tens pF for time and energy measurements of incoming pulses. The front-end readout electronics is required to process input pulses with an average rate of 150 kHz/channel with low both power consumption and noise at the same time. In the presented solution the single channel is built of two different parallel processing paths: fast and slow. The fast path includes the fast CR–RC shaper with the peaking time t{sub p}=40 ns and is optimized to determine the input charge arrival time. The slow path, which consists of the slow CR–(RC){sup 2} shaper with the peaking time t{sub p}=80 ns, is dedicated for low noise accurate energy measurement. The analog front-end electronics was implemented in UMC 180 nm CMOS technology as a prototype ASIC AFE. The AFE chip contains 8 channels with the size of 58 μm×1150 μm each. It has low power dissipation P{sub diss}=3.1 mW per single channel. The article presents the details of the front-end architecture and the measurement results.

  10. A low-power portable ECG sensor interface with dry electrodes

    Institute of Scientific and Technical Information of China (English)

    Pu Xiaofei; Wan Lei; Zhang Hui; Qin Yajie; Hong Zhiliang

    2013-01-01

    This paper describes a low-power portable sensor interface dedicated to sensing and processing electrocardiogram (ECG) signals.Dry electrodes were employed in this ECG sensor,which eliminates the need of conductive gel and avoids complicated and mandatory skin preparation before electrode attachment.This ECG sensor system consists of two ICs,an analog front-end (AFE) and a successive approximation register analog-to-digital converter (SAR ADC) containing a relaxation oscillator.This proposed design was fabricated in a 0.18 μm 1P6M standard CMOS process.The AFE for extracting the biopotential signals is essential in this ECG sensor.In measurements,the AFE obtains a mid-band gain of 45 dB,a bandwidth from 0.6 to 160 Hz,and a total input referred noise of 2.8 μV rms while consuming 1 μW from the 1.8 V supply.The noise efficiency factor (NEF) of our design is 3.4.After conditioning,the amplified ECG signal is digitized by a 12-bit SAR ADC with 61.8 dB SNDR and 220 fJ/conversion-step.Finally,a complete ECG sensor interface with three dry copper electrodes is demonstrated in real-word setting,showing successful recordings of a capture ECG waveform.

  11. Design and implementation of an ultra-low power passive UHF RFID tag

    Science.gov (United States)

    Jinpeng, Shen; Xin'an, Wang; Shan, Liu; Hongqiang, Zong; Jinfeng, Huang; Xin, Yang; Xiaoxing, Feng; Binjie, Ge

    2012-11-01

    This paper presents a fully integrated passive UHF RFID tag chip complying with the ISO18000-6B protocol. The tag chip includes an RF/analog front-end, a baseband processor, and a 512-bit EEPROM memory. To improve power conversion efficiency, a Schottky barrier diode based rectifier is adopted. A novel voltage reference using the peaking current source is discussed in detail, which can meet the low-power, low-voltage requirement while retaining circuit simplicity. Most of the analog blocks are designed to work under sub-1 V to reduce power consumption, and several practical methods are used to further reduce the power consumption of the baseband processor. The whole tag chip is implemented in a TSMC 0.18 μm CMOS process with a die size of 800 × 800 μm2. Measurement results show that the total power consumption of the tag chip is only 7.4 μW with a sensitivity of -12 dBm.

  12. Design and implementation of an ultra-low power passive UHF RFID tag

    Institute of Scientific and Technical Information of China (English)

    Shen Jinpeng; Wang Xin'an; Liu Shan; Zong Hongqiang; Huang Jinfeng; Yang Xin; Feng Xiaoxing; Ge Binjie

    2012-01-01

    This paper presents a fully integrated passive UHF RFID tag chip complying with the ISO18000-6B protocol.The tag chip includes an RF/analog front-end,a baseband processor,and a 512-bit EEPROM memory.To improve power conversion efficiency,a Schottky barrier diode based rectifier is adopted.A novel voltage reference using the peaking current source is discussed in detail,which can meet the low-power,low-voltage requirement while retaining circuit simplicity.Most of the analog blocks are designed to work under sub-1 V to reduce power consumption,and several practical methods are used to further reduce the power consumption of the baseband processor.The whole tag chip is implemented in a TSMC 0.18 μm CMOS process with a die size of 800 × 800 μm2.Measurement results show that the total power consumption of the tag chip is only 7.4 μW with a sensitivity of -12 dBm.

  13. Accurate geometry scalable complementary metal oxide semiconductor modelling of low-power 90 nm amplifier circuits

    Directory of Open Access Journals (Sweden)

    Apratim Roy

    2014-05-01

    Full Text Available This paper proposes a technique to accurately estimate radio frequency behaviour of low-power 90 nm amplifier circuits with geometry scalable discrete complementary metal oxide semiconductor (CMOS modelling. Rather than characterising individual elements, the scheme is able to predict gain, noise and reflection loss of low-noise amplifier (LNA architectures made with bias, active and passive components. It reduces number of model parameters by formulating dependent functions in symmetric distributed modelling and shows that simple fitting factors can account for extraneous (interconnect effects in LNA structure. Equivalent-circuit model equations based on physical structure and describing layout parasites are developed for major amplifier elements like metal–insulator–metal (MIM capacitor, spiral symmetric inductor, polysilicon (PS resistor and bulk RF transistor. The models are geometry scalable with respect to feature dimensions, i.e. MIM/PS width and length, outer-dimension/turns of planar inductor and channel-width/fingers of active device. Results obtained with the CMOS models are compared against measured literature data for two 1.2 V amplifier circuits where prediction accuracy for RF parameters (S(21, noise figure, S(11, S(22 lies within the range of 92–99%.

  14. A Novel Low Power High Dynamic Threshold Swing Limited Repeater Insertion for On-Chip Interconnects

    Directory of Open Access Journals (Sweden)

    S.Rajendar

    2014-12-01

    Full Text Available In Very Large Scale Integration (VLSI, interconnec t design has become a supreme issue in high speed I Cs. With the decreased feature size of CMOS circuits, o n-chip interconnect now dominates both circuit dela y and power consumption. An eminent technique known a s repeater/buffer insertion is used in long interconnections to reduce delay in VLSI circuits. This paper deals with some distinct low power alternative circuits in buffer insertion technique and it proposes two new techniques: Dynamic Thresho ld Swing Limited (DTSL and High Dynamic Threshold Swi ng Limited (HDTSL. The DTSL uses Dynamic Threshold MOSFET configuration. In this gate is tie d to the body and it limits the output swing. High Dynamic Threshold Swing Limited (HDTSL also uses t he same configuration along with a high threshold voltage(high-Vth. The simulation results are perfo rmed in Cadence virtuoso environment tool using 45n m technology. By simulating and comparing these vario us repeater circuits along with the proposed circui ts it is analyzed that there is trade off among power, de lay and Power Delay Product and the 34.66% of power is reduced by using the high- V th in HDTSL w hen compared to DTSL

  15. A NOVEL LOW POWER HIGH DYNAMIC THRESHOLD SWING LIMITED REPEATER INSERTION FOR ON-CHIP INTERCONNECTS

    Directory of Open Access Journals (Sweden)

    S. Rajendar

    2014-12-01

    Full Text Available In Very Large Scale Integration (VLSI, interconnect design has become a supreme issue in high speed ICs. With the decreased feature size of CMOS circuits, on-chip interconnect now dominates both circuit delay and power consumption. An eminent technique known as repeater/buffer insertion is used in long interconnections to reduce delay in VLSI circuits. This paper deals with some distinct low power alternative circuits in buffer insertion technique and it proposes two new techniques: Dynamic Threshold Swing Limited (DTSL and High Dynamic Threshold Swing Limited (HDTSL. The DTSL uses Dynamic Threshold MOSFET configuration. In this gate is tied to the body and it limits the output swing. High Dynamic Threshold Swing Limited (HDTSL also uses the same configuration along with a high threshold voltage(high-Vth. The simulation results are performed in Cadence virtuoso environment tool using 45nm technology. By simulating and comparing these various repeater circuits along with the proposed circuits it is analyzed that there is trade off among power, delay and Power Delay Product and the 34.66% of power is reduced by using the high- Vth in HDTSL when compared to DTSL.

  16. Electrothermal modeling, fabrication and analysis of low-power consumption thermal actuator with buckling arm

    KAUST Repository

    So, Hongyun

    2013-10-31

    © 2013, Springer-Verlag Berlin Heidelberg. This paper reports on a novel thermal actuator with sub-micron metallic structures and a buckling arm to operate with low voltages and to generate very large deflections, respectively. A lumped electrothermal model and analysis were also developed to validate the mechanical design and easily predict the temperature distribution along arms of the sub-micron actuator. The actuator was fabricated via the combination of electron beam lithography to form actuator arms with a minimum feature size of 200 nm and lift-off process to deposit a high aspect ratio nickel structure. Reproducible displacements of up to 1.9 μm at the tip were observed up to 250 mV under confocal microscope. The experimentally measured deflection values and theoretically calculated temperature distribution by the developed model were compared with finite element analysis results and they were in good agreement. This study shows a promising approach to develop more sophisticated nano actuators required larger deflections for manipulation of sub-micron scale objects with low-power consumption.

  17. The Design of High Performance, Low Power Triple-Track Magnetic Sensor Chip

    Directory of Open Access Journals (Sweden)

    Junning Chen

    2013-07-01

    Full Text Available This paper presents a design of a high performance and low power consumption triple-track magnetic sensor chip which was fabricated in TSMC 0.35 μm CMOS process. This chip is able to simultaneously sense, decode and read out the information stored in triple-track magnetic cards. A reference voltage generating circuit, a low-cost filter circuit, a power-on reset circuit, an RC oscillator, and a pre-decoding circuit are utilized as the basic modules. The triple-track magnetic sensor chip has four states, i.e., reset, sleep, swiping card and data read-out. In sleep state, the internal RC oscillator is closed, which means that the digital part does not operate to optimize energy consumption. In order to improve decoding accuracy and expand the sensing range of the signal, two kinds of circuit are put forward, naming offset correction circuit, and tracking circuit. With these two circuits, the sensing function of this chip can be more efficiently and accurately. We simulated these circuit modules with TSMC technology library. The results showed that these modules worked well within wide range input signal. Based on these results, the layout and tape-out were carried out. The measurement results showed that the chip do function well within a wide swipe speed range, which achieved the design target.

  18. The design of high performance, low power triple-track magnetic sensor chip.

    Science.gov (United States)

    Wu, Xiulong; Li, Minghua; Lin, Zhiting; Xi, Mengyuan; Chen, Junning

    2013-07-09

    This paper presents a design of a high performance and low power consumption triple-track magnetic sensor chip which was fabricated in TSMC 0.35 μm CMOS process. This chip is able to simultaneously sense, decode and read out the information stored in triple-track magnetic cards. A reference voltage generating circuit, a low-cost filter circuit, a power-on reset circuit, an RC oscillator, and a pre-decoding circuit are utilized as the basic modules. The triple-track magnetic sensor chip has four states, i.e., reset, sleep, swiping card and data read-out. In sleep state, the internal RC oscillator is closed, which means that the digital part does not operate to optimize energy consumption. In order to improve decoding accuracy and expand the sensing range of the signal, two kinds of circuit are put forward, naming offset correction circuit, and tracking circuit. With these two circuits, the sensing function of this chip can be more efficiently and accurately. We simulated these circuit modules with TSMC technology library. The results showed that these modules worked well within wide range input signal. Based on these results, the layout and tape-out were carried out. The measurement results showed that the chip do function well within a wide swipe speed range, which achieved the design target.

  19. Studies on photochemical vapor generation of selenium with germicidal low power ultraviolet mercury lamp

    Science.gov (United States)

    Campanella, B.; Menciassi, A.; Onor, M.; Ferrari, C.; Bramanti, E.; D'Ulivo, A.

    2016-12-01

    Photochemical vapor generation (photo-CVG) with flow injection - atomic fluorescence spectrometry was investigated for the determination of selenium, using formic and acetic acids as photochemical reagents. Using a germicidal low power ultraviolet mercury-based lamp, emitting both the 185 and 254 nm Hg lines, mild reaction conditions can be achieved in formic acid medium, where optimal sensitivity was obtained at 0.3-0.5% w/w acid concentrations, whereas the optimal sensitivity could be attained with acetic acid in the range from 12 to 35% w/w. The only volatile Se product identified by gas chromatography-mass spectrometry from formic acid-based photo-CVG was selenium carbonyl. A series of dedicated experiments were performed using photo-CVG and pure dimethylselenide in order to identify reaction pathways contributing to the formation of non-volatile selenium species or to the degradation of volatile selenium species. Under the optimized conditions in formic acid, using 250 μL sample volume, the limits of detection and quantification were 0.10 and 0.35 μg L- 1, respectively. The effect of several interfering species was investigated and the method was tested in the analysis of certified reference materials.

  20. An ultra-low power (ULP) bandage-type ECG sensor for efficient cardiac disease management.

    Science.gov (United States)

    Shin, Kunsoo; Park, G G; Kim, J P; Lee, T H; Ko, B H; Kim, Y H

    2013-01-01

    This paper proposed an ultra-low power bandage-type ECG sensor (the size: 76 × 34 × 3 (mm(3)) and the power consumption: 1 mW) which allows for a continuous and real-time monitoring of a user's ECG signals over 24h during daily activities. For its compact size and lower power consumption, we designed the analog front-end, the SRP (Samsung Reconfigurable Processor) based DSP of 30 uW/MHz, and the ULP wireless RF of 1 nJ/bit. Also, to tackle motion artifacts(MA), a MA monitoring technique based on the HCP (Half-cell Potential) is proposed which resulted in the high correlation between the MA and the HCP, the correlation coefficient of 0.75 ± 0.18. To assess its feasibility and validity as a wearable health monitor, we performed the comparison of two ECG signals recorded form it and a conventional Holter device. As a result, the performance of the former is a little lower as compared with the latter, although showing no statistical significant difference (the quality of the signal: 94.3% vs 99.4%; the accuracy of arrhythmia detection: 93.7% vs 98.7%). With those results, it has been confirmed that it can be used as a wearable health monitor due to its comfortability, its long operation lifetime and the good quality of the measured ECG signal.

  1. A Novel Low Power Bitcell Design Featuring Inherent SEU Prevention and Self Correction Capabilities

    Directory of Open Access Journals (Sweden)

    Oron Chertkow

    2015-06-01

    Full Text Available The pursuit of continuous scaling of electronic devices in the semiconductor industry has led to two unintended but significant outcomes: a rapid increase in susceptibility to radiation induced errors, and an overall rise in power consumption. Operating under low voltage to reduce power only aggravates radiation related reliability issues. The proposed “SEU Hardening Incorporating Extreme Low Power Bitcell Design” (SHIELD addresses these two major concerns simultaneously. It is based on the concept of gating the conventional cross-coupled inverters while introducing a novel “cut-off” network. This creates redundant storage nodes and eliminates the internal feedback loop during radiation particle impact. The SHIELD bitcell tolerates upsets with charge deposits over 1 pC. Simulations confirm its advantages in terms of leakage power, with more than twofold lower leakage currents than previous solutions when operated at a 700mV supply voltage in a 65 nm process. To validate the bitcell’s robustness, several test cases and special concerns, including multiple node upsets (MNU and half-select, are examined.

  2. A low-power column-parallel ADC for high-speed CMOS image sensor

    Science.gov (United States)

    Han, Ye; Li, Quanliang; Shi, Cong; Liu, Liyuan; Wu, Nanjian

    2013-08-01

    This paper presents a 10-bit low-power column-parallel cyclic analog-to-digital converter (ADC) used for high-speed CMOS image sensor (CIS). An opamp sharing technique is used to save power and area. Correlated double sampling (CDS) circuit and programmable gain amplifier (PGA) are integrated in the ADC, which avoids stand-alone circuit blocks. An offset cancellation technique is also introduced, which reduces the column fixed-pattern noise (FPN) effectively. One single channel ADC with an area less than 0.03mm2 was implemented in a 0.18μm 1P4M CMOS image sensor process. The resolution of the proposed ADC is 10-bit, and the conversion rate is 2MS/s. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.62 LSB and 2.1 LSB together with CDS, respectively. The power consumption from 1.8V supply is only 0.36mW.

  3. A low power readout circuit approach for uncooled resistive microbolometer FPAs

    Science.gov (United States)

    Tepegoz, Murat; Toprak, Alperen; Akin, Tayfun

    2008-04-01

    This paper presents a new, low power readout circuit approach for uncooled resistive microbolometer FPAs. The readout circuits of the microbolometer detectors contain parallel readout channels whose outputs are driven and multiplexed on large bus capacitances in order to form the output of the readout circuit. High number of opamps used in the readout channel array and large output capacitances that these opamps should drive necessitates the use of high output current capacity structures, which results in large power dissipation. This paper proposes two new methods in order to decrease the power dissipation of the readout circuits for uncooled thermal FPAs. The first method is called the readout channel group concept, where the readout channel array is separated into groups in order to decrease the load capacitance seen by the readout channel output. The second method utilizes a special opamp architecture where the output current driving capacity can be digitally controlled. This method enables efficient use of power by activating the high output current driving capacity only during the output multiplexing. The simulations show that using these methods results in a power dissipation reduction of 80% and 91% for the readout channels optimized for a single output 384x288 FPA operating at 25 fps and for a two-output 640x480 FPA operating at 30 fps, respectively.

  4. Low-power and area-optimized VLSI implementation of AES coprocessor for Zigbee system

    Institute of Scientific and Technical Information of China (English)

    LI Zhen-rong; ZHUANG Yi-qi; ZHANG Chao; JIN Gang

    2009-01-01

    A low-power and low-cost advanced encryption standard (AES) coprocessor is proposed for Zigbee system-on-a-chip (SoC) design. The cost and power consumption of the proposed AES coprocessor are reduced considerably by optimizing the architectures of SubBytes/InvSubBytes and MixColumns/InvMixColumns, integrating the encryption and deeryption procedures together by the method of resource sharing, and using the hierarchical power management strategy based on finite state machine (FSM) and clock gating (CG) technologies. Based on SMIC 0.18 μm complementary metal oxide semiconductor (CMOS) technology, the scale of the AES coprocessor is only about 10.5 kgate, the corresponding power consumption is 69.1 μW/MHz,and the throughput is 32 Mb/s, which is reasonable and sufficient for Zigbee system. Compared with other designs, the proposed architecture consumes less power and fewer hardware resources, which is conducive to the Zigbee system and other portable devices.

  5. Area-Efficient Low Power CMOS Image Sensor Readout Circuit with Fixed Pattern Noise Cancellation

    Institute of Scientific and Technical Information of China (English)

    ZHAO Shibin; YAO Suying; NIE Kaiming; XU Jiangtao

    2010-01-01

    A low cost of die area and power consumption CMOS image sensor readout circuit with fixed pattern noise(FPN)cancellation is proposed.By using only one coupling capacitor and switch in the double FPN cancelling correlative double sampling(CDS),pixel FPN is cancelled and column FPN is stored and eliminated by the sample-and-hold operation of digitally programmable gain amplifier(DPGA).The bandwidth balance technology based on operational amplifier(op-amp)sharing is also introduced to decrease the power dissipation of traditional multi-stage switched capacitor DPGA.The circuit is designed and simulated using 1P6M 0.18 μm 1.8 V/3.3 V process.Simulation results indicate that the proposed CDS scheme can achieve an FPN of less than 1 mV.The total sampling capacitor per column is 0.9 pF and no column-wise power is dissipated.The die area and FPN value are cut by 70% and 41% respectively compared with amplifier-based CDS.The op-amp sharing gain stage can achieve a 12-bit precision and also implement an 8-bit gain controlling within a gain range of 24 dB.Its power consumption is 1.4 mW,which is reduced by 57% compared with traditional schemes.The proposed readout circuit is suitable for the application of low power cost-sensitive imaging systems.

  6. Investigation of a novel common subexpression elimination method for low power and area efficient DCT architecture.

    Science.gov (United States)

    Siddiqui, M F; Reza, A W; Kanesan, J; Ramiah, H

    2014-01-01

    A wide interest has been observed to find a low power and area efficient hardware design of discrete cosine transform (DCT) algorithm. This research work proposed a novel Common Subexpression Elimination (CSE) based pipelined architecture for DCT, aimed at reproducing the cost metrics of power and area while maintaining high speed and accuracy in DCT applications. The proposed design combines the techniques of Canonical Signed Digit (CSD) representation and CSE to implement the multiplier-less method for fixed constant multiplication of DCT coefficients. Furthermore, symmetry in the DCT coefficient matrix is used with CSE to further decrease the number of arithmetic operations. This architecture needs a single-port memory to feed the inputs instead of multiport memory, which leads to reduction of the hardware cost and area. From the analysis of experimental results and performance comparisons, it is observed that the proposed scheme uses minimum logic utilizing mere 340 slices and 22 adders. Moreover, this design meets the real time constraints of different video/image coders and peak-signal-to-noise-ratio (PSNR) requirements. Furthermore, the proposed technique has significant advantages over recent well-known methods along with accuracy in terms of power reduction, silicon area usage, and maximum operating frequency by 41%, 15%, and 15%, respectively.

  7. New low power adders in Self Resetting Logic with Gate Diffusion Input Technique

    Directory of Open Access Journals (Sweden)

    R. Uma

    2017-04-01

    Full Text Available The objective vividly defines a new low-power and high-speed logic family; named Self Resetting Logic with Gate Diffusion Input (SRLGDI. This logic family resolves the issues in dynamic circuits like charge sharing, charge leakage, short circuit power dissipation, monotonicity requirement and low output voltage. In the proposed design structure of SRLGDI, the pull down tree is implemented with Gate Diffusion Input (GDI with level restoration which apparently eliminated the conductance overlap between nMOS and pMOS devices, thereby reducing the short circuit power dissipation and providing High Output Voltage VoH. The output stage of SRLGDI has been incorporated with an inverter to produce both true and complementary output function. The Resistance Capacitance (RC delay model has been proposed to obtain the total delay of the circuit during precharge and evaluation phases. Using SRLGDI, the primitive cells and 3 different full adder circuits were designed and simulated in a 0.250 μm Complementary Metal Oxide Semiconductor (CMOS process technology. The simulated result demonstrates that the proposed SRLGDI logic family is superior in terms of speed and power consumption with respect to other logic families like Dynamic logic (DY, CMOS, Self Resetting CMOS (SRCMOS and GDI.

  8. Modified 16-b Square-root Low Power Area Efficient Carry Select Adder

    Directory of Open Access Journals (Sweden)

    R.P. Meenaakshi Sundhari

    2014-12-01

    Full Text Available Due to acceptance of the portable system with fast growth of power density in the integrated circuits, the power dissipation and the performance is considered while the system is designed. The main goal of the VLSI design is to design the adders in more efficient way. By that way the Carry Select Adder (CSLA is an adder designed, which computes n+1 bit sum of two n bit numbers. In this study Modified 16-b SQRT with Modified Area efficient CSLA is proposed. From the design of Modified Area Efficient CSLA it is experiential that there is an option of reducing the area more and consumes low power when compared with Regular CSLA. Modified Area Efficient CSLA (MA-CSLA utilizes BEC which reduces the area more and the total gate count is also gets condensed. The proposed study makes use of a simple and well-organized gate-level alteration to considerably reduce the area and power of the CSLA. By the support of alteration 8-, 16-, 32- and 64-b, respectively Square-Root CSLA (SQRT CSLA model have been evolved and evaluated with the regular SQRT CSLA model. This study estimates the performance of the proposed designs in terms of delay, area and power. The results analysis shows that the proposed Modified Area Efficient CSLA structure is better than the regular SQRT CSLA.

  9. Low-power resistive random access memory by confining the formation of conducting filaments

    Science.gov (United States)

    Huang, Yi-Jen; Shen, Tzu-Hsien; Lee, Lan-Hsuan; Wen, Cheng-Yen; Lee, Si-Chen

    2016-06-01

    Owing to their small physical size and low power consumption, resistive random access memory (RRAM) devices are potential for future memory and logic applications in microelectronics. In this study, a new resistive switching material structure, TiOx/silver nanoparticles/TiOx/AlTiOx, fabricated between the fluorine-doped tin oxide bottom electrode and the indium tin oxide top electrode is demonstrated. The device exhibits excellent memory performances, such as low operation voltage (<±1 V), low operation power, small variation in resistance, reliable data retention, and a large memory window. The current-voltage measurement shows that the conducting mechanism in the device at the high resistance state is via electron hopping between oxygen vacancies in the resistive switching material. When the device is switched to the low resistance state, conducting filaments are formed in the resistive switching material as a result of accumulation of oxygen vacancies. The bottom AlTiOx layer in the device structure limits the formation of conducting filaments; therefore, the current and power consumption of device operation are significantly reduced.

  10. Low-power resistive random access memory by confining the formation of conducting filaments

    Directory of Open Access Journals (Sweden)

    Yi-Jen Huang

    2016-06-01

    Full Text Available Owing to their small physical size and low power consumption, resistive random access memory (RRAM devices are potential for future memory and logic applications in microelectronics. In this study, a new resistive switching material structure, TiOx/silver nanoparticles/TiOx/AlTiOx, fabricated between the fluorine-doped tin oxide bottom electrode and the indium tin oxide top electrode is demonstrated. The device exhibits excellent memory performances, such as low operation voltage (<±1 V, low operation power, small variation in resistance, reliable data retention, and a large memory window. The current-voltage measurement shows that the conducting mechanism in the device at the high resistance state is via electron hopping between oxygen vacancies in the resistive switching material. When the device is switched to the low resistance state, conducting filaments are formed in the resistive switching material as a result of accumulation of oxygen vacancies. The bottom AlTiOx layer in the device structure limits the formation of conducting filaments; therefore, the current and power consumption of device operation are significantly reduced.

  11. A low power 12-bit 1 Msps successive approximation register ADC with an improved switching procedure

    Science.gov (United States)

    Fubin, Xin; Tao, Yin; Qisong, Wu; Yuanlong, Yang; Fei, Liu; Haigang, Yang

    2015-08-01

    As a key building block of data acquisition systems, power dissipation of the successive approximation register (SAR) ADC determines the total power consumption of the system. In this paper, a low power 12-bit 1 Msps SAR ADC with an improved switching procedure is presented. Power consumption and area occupation could be significantly reduced by using the proposed switching procedure. Compared to converters that use the conventional switching procedure, the average switching energy could be reduced by about 80% and the total capacitance could be reduced by 50%. A simplified digital control logic is utilized to reduce power dissipation and area occupation of the digital control circuits. Simulation results show that the power dissipated by the proposed digital control circuits could be reduced by about 50% compared to the power dissipated by conventional control circuits. The chip has been processed in a standard 0.35 μm CMOS technology and has a core die area of 1.12 mm2. A signal-to-noise-and-distortion-ratio of 64.2 dB has been measured with a 100 kHz signal input under a wide range variation of temperature from -55 to 150 °C. The total power consumption of the prototype is only 0.72 mW with a 3.3 V supply voltage. Project supported by the National Basic Research Program of China (No. 2014CB744600) and the National Natural Science Foundation of China (No. 61474120).

  12. A 130 nm CMOS low-power SAR ADC for wide-band communication systems

    Science.gov (United States)

    Chenghao, Bian; Jun, Yan; Yin, Shi; Ling, Sun

    2014-02-01

    This paper presents a low power 9-bit 80 MS/s SAR ADC with comparator-sharing technique in 130 nm CMOS process. Compared to the conventional SAR ADC, the sampling phase is removed to reach the full efficiency of the comparator. Thus the conversion rate increases by about 20% and its sampling time is relaxed. The design does not use any static components to achieve a widely scalable conversion rate with a constant FOM. The floorplan of the capacitor network is custom-designed to suppress the gain mismatch between the two DACs. The ‘set-and-down’ switching procedure and a novel binary-search error compensation scheme are utilized to further speed up the SA bit-cycling operation. A very fast logic controller is proposed with a delay time of only 90 ps. At 1.2 V supply and 80 MS/s the ADC achieves an SNDR of 51.4 dB and consumes 1.86 mW, resulting in an FOM of 76.6 fJ/conversion-step. The ADC core occupies an active area of only 0.089 mm2.

  13. Dual Wake-up Low Power Listening for Duty Cycled Wireless Sensor Networks

    Directory of Open Access Journals (Sweden)

    Jongkeun Na

    2008-01-01

    Full Text Available Energy management is an interesting research area for wireless sensor networks. Relevant dutycycling (or sleep scheduling algorithm has been actively studied at MAC, routing, and application levels. Low power listening (LPL MAC is one of effective dutycycling techniques. This paper proposes a novel approach called dual wake-up LPL (DW-LPL. Existing LPL scheme uses a preamble detection method for both broadcast and unicast, thus suffers from severe overhearing problem at unicast transmission. DW-LPL uses a different wake-up method for unicast while using LPL-like method for broadcast; DW-LPL introduces a receiver-initiated method in which a sender waits a signal from receiver to start unicast transmission, which incurs some signaling overhead but supports flexible adaptive listening as well as overhearing removal effect. Through analysis and Mote (Telosb experiment, we show that DW-LPL provides more energy saving than LPL and our adaptive listening scheme is effective for energy conservation in practical network topologies and traffic patterns.

  14. Dual Wake-up Low Power Listening for Duty Cycled Wireless Sensor Networks

    Directory of Open Access Journals (Sweden)

    Lim Sangsoon

    2008-01-01

    Full Text Available Abstract Energy management is an interesting research area for wireless sensor networks. Relevant dutycycling (or sleep scheduling algorithm has been actively studied at MAC, routing, and application levels. Low power listening (LPL MAC is one of effective dutycycling techniques. This paper proposes a novel approach called dual wake-up LPL (DW-LPL. Existing LPL scheme uses a preamble detection method for both broadcast and unicast, thus suffers from severe overhearing problem at unicast transmission. DW-LPL uses a different wake-up method for unicast while using LPL-like method for broadcast; DW-LPL introduces a receiver-initiated method in which a sender waits a signal from receiver to start unicast transmission, which incurs some signaling overhead but supports flexible adaptive listening as well as overhearing removal effect. Through analysis and Mote (Telosb experiment, we show that DW-LPL provides more energy saving than LPL and our adaptive listening scheme is effective for energy conservation in practical network topologies and traffic patterns.

  15. Low-power, intelligent sensor hardware interface for medical data preprocessing.

    Science.gov (United States)

    Hu, Fei; Lakdawala, Shruti; Hao, Qi; Qiu, Meikang

    2009-07-01

    This work proposes an interface design of a low-power programmable system on chip for intelligent wireless sensor nodes to reduce the overall power consumption of the heart disease monitoring system, by lending them the capability of processing complex functions and performing rapid computations on a large amount of data at the node. This facilitates the node to intelligently monitor a medical signal for impending events instead of transmitting the signal to the base station constantly. Lowering the transmission data rate decreases the transmission power consumption in a node, thereby lengthening the node life and in turn increasing the reliability of the network. This work also implements a thresholding technique, which controls the data transmission rate depending on the value of the monitored signal, and a cardiac monitoring system that performs computations at the node for the detection of either a skipped heart beat or a reduced heart rate variability, in which event the signal is transmitted to the base station for monitoring/recording or alerting the crew. The performance analysis of the system shows that there are reductions in the system power consumption and data transmission rate, which in turn reduces the network traffic and averts congestion.

  16. Low Power 24 GHz ad hoc Networking System Based on TDOA for Indoor Localization

    Directory of Open Access Journals (Sweden)

    Melanie Jung

    2013-12-01

    Full Text Available This paper introduces the key elements of a novel low-power, high precision localization system based on Time-Difference-of-Arrival (TDOA distance measurements. The combination of multiple localizable sensor nodes, leads to an ad hoc network. Besides the localization functionality this ad hoc network has the additional advantage of a communication interface. Due to this a flexible positioning of the master station for information collection and the detection of static and mobile nodes is possible. These sensor nodes work in the 24 GHz ISM (Industrial Scientific and Medical frequency range and address several use cases and are able to improve various processes for production scheduling, logistics, quality management, medical applications and collection of geo information. The whole system design is explained briefly. Its core component is the frequency modulated continuous wave (FMCW synthesizer suitable for high performance indoor localization. This research work focuses on power and size reduction of this crucial system component. The comparison of the first and second generation of the system shows a significant size and power reduction as well as an increased precision.

  17. Improved Switching Energy Reduction Approach in Low-Power SAR ADC for Bioelectronics

    Directory of Open Access Journals (Sweden)

    Xingyuan Tong

    2016-01-01

    Full Text Available Low-power analog-to-digital converter (ADC is a crucial part of wearable or implantable bioelectronics. In order to reduce the power of successive-approximation-register (SAR ADC, an improved energy-efficient capacitor switching scheme of SAR ADC is proposed for implantable bioelectronic applications. With sequence initialization, novel logic control, and capacitive subconversion, 97.6% switching energy is reduced compared to the traditional structure. Moreover, thanks to the top-plate sampling and capacitive subconversion, 87% input-capacitance reduction can be achieved over the conventional structure. A 10-bit SAR ADC with this proposed switching scheme is realized in 65 nm CMOS. With 1.514 KHz differential sinusoidal input signals sampled at 50 KS/s, the ADC achieves an SNDR of 61.4 dB and only consumes power of 450 nW. The area of this SAR ADC IP core is only 136 μm × 176 μm, making it also area-efficient and very suitable for biomedical electronics application.

  18. Design of A Novel High Speed Dynamic Comparator with Low Power Dissipation for High Speed ADCs

    Directory of Open Access Journals (Sweden)

    Sougata Ghosh

    2013-01-01

    Full Text Available A new CMOS dynamic comparator using dual input single output differential amplifier as latch stage suitable for high speed analog-to-digital converters with High Speed, low power dissipation and immune to noise than the previous reported work is proposed. Back to-back inverter in the latch stage is replaced with dual-input single output differential amplifier. This topology completely removes the noise that is present in the input. The structure shows lower power dissipation and higher speed than the conventional comparators. The circuit is simulated with 1V DC supply voltage and 250 MHz clock frequency. The proposed topology is based on two cross coupled differential pairs positive feedback and switchable current sources, has a lower power dissipation, higher speed, less area, and it is shown to be very robust against transistor mismatch, noise immunity. Previous reported comparators are designed and simulated their DC response and Transient response in Cadence®Virtuoso Analog Design Environment using GPDK 90nm technology. Layouts of the proposed comparator have been done in Cadence® Virtuoso Layout XL Design Environment. DRC and LVS has been checked and compared with the corresponding circuits and RC extracted diagram has been generated. After that post layout simulation with 1V supply voltage has been done and compared the speed, power dissipation, Area, delay with the results before layout and the superior features of the proposed comparator are established

  19. Design of low-power hybrid digital pulse width modulator with piecewise calibration scheme

    Science.gov (United States)

    Zhen, Shaowei; Hou, Sijian; Gan, Wubing; Chen, Jingbo; Luo, Ping; Zhang, Bo

    2015-12-01

    A low-power hybrid digital pulse width modulator (DPWM) is proposed in the paper. Owing to the piecewise calibration scheme, the delay time of delay line is locked to target frequency. The delay line consists of two piecewise lines with different control codes. The delay time of each cell in one sub-delay-line is longer than the last significant bit (LSB) of DPWM, while the delay time of each cell in the other sub-delay-line is shorter than LSB. Optimum linearity is realised with minimum standard cells. Simulation results show that the differential nonlinearity and integral nonlinearity are improved from 5.1 to 0.4 and from 5 to 1.3, respectively. The DPWM is fully synthesised and fabricated in a 90-nm CMOS process. The proposed DPWM occupies a silicon area of 0.01 mm2, with 31.5 μw core power consumption. Experimental results are shown to demonstrate the 2-MHz, 10-bit resolution implementation. Pulse width histogram is firstly introduced to characterise the linearity of the DPWM.

  20. A Low Cost/Low Power Open Source Sensor System for Automated Tuberculosis Drug Susceptibility Testing

    Directory of Open Access Journals (Sweden)

    Kyukwang Kim

    2016-06-01

    Full Text Available In this research an open source, low power sensor node was developed to check the growth of mycobacteria in a culture bottle with a nitrate reductase assay method for a drug susceptibility test. The sensor system reports the temperature and color sensor output frequency change of the culture bottle when the device is triggered. After the culture process is finished, a nitrite ion detecting solution based on a commercial nitrite ion detection kit is injected into the culture bottle by a syringe pump to check bacterial growth by the formation of a pigment by the reaction between the solution and the color sensor. Sensor status and NRA results are broadcasted via a Bluetooth low energy beacon. An Android application was developed to collect the broadcasted data, classify the status of cultured samples from multiple devices, and visualize the data for the end users, circumventing the need to examine each culture bottle manually during a long culture period. The authors expect that usage of the developed sensor will decrease the cost and required labor for handling large amounts of patient samples in local health centers in developing countries. All 3D-printerable hardware parts, a circuit diagram, and software are available online.