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Sample records for central trigger processor

  1. The Central Trigger Processor (CTP)

    CERN Multimedia

    Franchini, Matteo

    2016-01-01

    The Central Trigger Processor (CTP) receives trigger information from the calorimeter and muon trigger processors, as well as from other sources of trigger. It makes the Level-1 decision (L1A) based on a trigger menu.

  2. The ALICE Central Trigger Processor (CTP) upgrade

    Science.gov (United States)

    Krivda, M.; Alexandre, D.; Barnby, L. S.; Evans, D.; Jones, P. G.; Jusko, A.; Lietava, R.; Pospíšil, J.; Villalobos Baillie, O.

    2016-03-01

    The ALICE Central Trigger Processor (CTP) at the CERN LHC has been upgraded for LHC Run 2, to improve the Transition Radiation Detector (TRD) data-taking efficiency and to improve the physics performance of ALICE. There is a new additional CTP interaction record sent using a new second Detector Data Link (DDL), a 2 GB DDR3 memory and an extension of functionality for classes. The CTP switch has been incorporated directly onto the new LM0 board. A design proposal for an ALICE CTP upgrade for LHC Run 3 is also presented. Part of the development is a low latency high bandwidth interface whose purpose is to minimize an overall trigger latency.

  3. The ATLAS Level-1 Central Trigger Processor (CTP)

    CERN Document Server

    Spiwoks, Ralf; Ellis, Nick; Farthouat, P; Gällnö, P; Haller, J; Krasznahorkay, A; Maeno, T; Pauly, T; Pessoa-Lima, H; Resurreccion-Arcas, I; Schuler, G; De Seixas, J M; Torga-Teixeira, R; Wengler, T

    2005-01-01

    The ATLAS Level-1 Central Trigger Processor (CTP) combines information from calorimeter and muon trigger processors and makes the final Level-1 Accept (L1A) decision on the basis of lists of selection criteria (trigger menus). In addition to the event-selection decision, the CTP also provides trigger summary information to the Level-2 trigger and the data acquisition system. It further provides accumulated and bunch-by-bunch scaler data for monitoring of the trigger, detector and beam conditions. The CTP is presented and results are shown from tests with the calorimeter adn muon trigger processors connected to detectors in a particle beam, as well as from stand-alone full-system tests in the laboratory which were used to validate the CTP.

  4. The ATLAS Level-1 Muon to Central Trigger Processor Interface

    CERN Document Server

    Berge, D; Farthouat, P; Haas, S; Klofver, P; Krasznahorkay, A; Messina, A; Pauly, T; Schuler, G; Spiwoks, R; Wengler, T; PH-EP

    2007-01-01

    The Muon to Central Trigger Processor Interface (MUCTPI) is part of the ATLAS Level-1 trigger system and connects the output of muon trigger system to the Central Trigger Processor (CTP). At every bunch crossing (BC), the MUCTPI receives information on muon candidates from each of the 208 muon trigger sectors and calculates the total multiplicity for each of six transverse momentum (pT) thresholds. This multiplicity value is then sent to the CTP, where it is used together with the input from the Calorimeter trigger to make the final Level-1 Accept (L1A) decision. In addition the MUCTPI provides summary information to the Level-2 trigger and to the data acquisition (DAQ) system for events selected at Level-1. This information is used to define the regions of interest (RoIs) that drive the Level-2 muontrigger processing. The MUCTPI system consists of a 9U VME chassis with a dedicated active backplane and 18 custom designed modules. The design of the modules is based on state-of-the-art FPGA devices and special ...

  5. Hardware and firmware developments for the upgrade of the ATLAS Level-1 Central Trigger Processor

    International Nuclear Information System (INIS)

    The Central Trigger Processor (CTP) is the final stage of the ATLAS first level trigger system which reduces the collision rate of 40 MHz to a Level-1 event rate of 100 kHz. An upgrade of the CTP is currently underway to significantly increase the number of trigger inputs and trigger combinations, allowing additional flexibility for the trigger menu. We present the hardware and FPGA firmware of the newly designed core module (CTPCORE+) module of the CTP, as well as results from a system used for early firmware and software prototyping based on commercial FPGA evaluation boards. First test result from the CTPCORE+ module will also be shown

  6. Operation of the upgraded ATLAS Central Trigger Processor during the LHC Run 2

    Science.gov (United States)

    Bertelsen, H.; Carrillo Montoya, G.; Deviveiros, P.-O.; Eifert, T.; Galster, G.; Glatzer, J.; Haas, S.; Marzin, A.; Silva Oliveira, M. V.; Pauly, T.; Schmieden, K.; Spiwoks, R.; Stelzer, J.

    2016-02-01

    The ATLAS Central Trigger Processor (CTP) is responsible for forming the Level-1 trigger decision based on the information from the calorimeter and muon trigger processors. In order to cope with the increase of luminosity and physics cross-sections in Run 2, several components of this system have been upgraded. In particular, the number of usable trigger inputs and trigger items have been increased from 160 to 512 and from 256 to 512, respectively. The upgraded CTP also provides extended monitoring capabilities and allows to operate simultaneously up to three independent combinations of sub-detectors with full trigger functionality, which is particularly useful for commissioning, calibration and test runs. The software has also undergone a major upgrade to take advantage of all these new functionalities. An overview of the commissioning and the operation of the upgraded CTP during the LHC Run 2 is given.

  7. Topological and Central Trigger Processor for 2014 LHC luminosities

    CERN Document Server

    Simioni, E; The ATLAS collaboration; Bauss, B; Berge, D; Buscher, V; Childers, T; Degele, R; Dobson, E; Ebling, A; Ellis, N; Farthouat, P; Gabaldon, C; Gorini, B; Haas, S; Ji, W; Kaneda, M; Mattig, S; Messina, A; Meyer, C; Moritz, S; Pauly, T; Pottgen, R; Schafer, U; Spiwoks, R; Tapprogge, S; Wengler, T; Wenzel, V

    2012-01-01

    The ATLAS experiment is located at the European Center for Nuclear Research (CERN) in Switzerland. It is designed to observe phenomena that involve highly massive particles produced in the collisions at the Large Hadron Collider (LHC): the world’s largest and highest-energy particle accelerator. Event triggering and Data Acquisition is one of the extraordinary challenges faced by the detectors at the high luminosity LHC collider. During 2011, the LHC reached instantaneous luminosities of 4 10^33 cm−1 s−1 and produced events with up to 24 interactions per colliding proton bunch. This places stringent operational and physical requirements on the ATLAS Trigger in order to reduce the 40MHz collision rate to a manageable event storage rate of 400Hz and, at the same time, selecting those events considered interesting. The Level-1 Trigger is the first rate-reducing step in the ATLAS Trigger, with an output rate of 75kHz and decision latency of less than 2.5 micro seconds. It is primarily composed of the Calori...

  8. Topological and Central Trigger Processor for 2014 LHC luminosities

    CERN Document Server

    Simioni, E; The ATLAS collaboration; Bauss, B; Berge, D; B\\"{u}scher, V; Childers, T; Degele, R; Dobson, E; Ebling, A; Ellis, N; Farthouat, P; Gabaldon, C; Gorini, B; Haas, S; Ji, W; Kaneda, M; M\\"{a}ttig, S; Messina, A; Meyer, C; Moritz, S; Pauly, T; Pottgen, R; Sch\\"{a}fer, U; Spiwoks, R; Tapprogge, S; Wengler, T; Wenzel, V

    2012-01-01

    The ATLAS experiment is located at the European Center for Nu- clear Research (CERN) in Switzerland. It is designed to observe phe- nomena that involve highly massive particles produced in the collisions at the Large Hadron Collider (LHC): the world’s largest and highest-energy particle accelerator. Event triggering and Data Acquisition is one of the extraordinary challenges faced by the detectors at the high luminosity LHC collider. During 2011, the LHC reached instantaneous luminosities of 4×10^33 cm−1 s−1 and produced events with up to 24 interactions per colliding proton bunch. This places stringent operational and physical requirements on the AT- LAS Trigger in order to reduce the 40MHz collision rate to a manageable event storage rate of 400Hz and, at the same time, selecting those events considered interesting. The Level-1 Trigger is the first rate-reducing step in the ATLAS Trigger, with an output rate of 75kHz and decision latency of less than 2.5μs. It is primarily composed of the Calorimete...

  9. ATLAS Central Trigger Processor Input Module (CTPIN) Firmware Upgrade

    CERN Document Server

    Fountas, Petros

    2013-01-01

    The upgraded CTPIN firmware is designed to receive its inputs at twice the design speed. A constraint is that the CTPIN hardware will not be changed, so the upgrade is constrained to the firmware of the Pipeline FPGA and the Monitoring FPGA. The Pipeline FPGA is configured to latch in DDR registers the 32 XSDP input signals at 80 MHz and then decode and latch them internally in 64 registers operating at 40 MHz. After synchronization and alignment these 64 trigger signals are encoded and exported in 31 output lines, using Double-Data-Rate (DDR) registers. Again in the Monitoring module the 31 input trigger signals are decoded and latched in 62 internal signals, using DDR registers. The Pipeline FPGA and Monitoring FPGA firmware have been successfully verified in timing simulation, which shows that an upgrade of the CTPIN without redesigning the hardware is feasible.

  10. The Octant Module of the ATLAS Level-1 Muon to Central Trigger Processor Interface

    CERN Document Server

    Haas, Stefan; Berge, D; Ellis, Nick; Farthouat, P; Krasznahorkay, A; Pauly, T; Schuler, G; Spiwoks, R; Wengler, T

    2007-01-01

    The Muon to Central Trigger Processor Interface (MUCTPI) of the ATLAS Level-1 trigger receives data from the sector logic modules of the muon trigger at every bunch crossing and calculates the total multiplicity of muon candidates, which is then sent to the Central Trigger Processor where the final Level-1 decision is taken. The MUCTPI system consists of a 9U VME crate with a special backplane and 18 custom designed modules. We focus on the design and implementation of the octant module (MIOCT). Each of the 16 MIOCT modules processes the muon candidates from 13 sectors of one half-octant of the detector and forms the local muon candidate multiplicities for the trigger decision. It also resolves the overlaps between chambers in order to avoid double-counting of muon candidates that are detected in more than one sector. The handling of overlapping sectors is based on Look-Up-Tables (LUT) for maximum flexibility. The MIOCT also sends the information on the muon candidates over the custom backplane via the Readou...

  11. Trigger and decision processors

    International Nuclear Information System (INIS)

    In recent years there have been many attempts in high energy physics to make trigger and decision processes faster and more sophisticated. This became necessary due to a permanent increase of the number of sensitive detector elements in wire chambers and calorimeters, and in fact it was possible because of the fast developments in integrated circuits technique. In this paper the present situation will be reviewed. The discussion will be mainly focussed upon event filtering by pure software methods and - rather hardware related - microprogrammable processors as well as random access memory triggers. (orig.)

  12. The ATLAS Local Trigger Processor (LTP) 018

    CERN Document Server

    Borrego-Amaral, P; Farthouat, Philippe; Gällnö, P; Pessoa-Lima, H; Maeno, T; Resurreccion-Arcas, I; De Seixas, J M; Schuler, G; Spiwoks, R; Torga-Teixeira, R; Wengler, T; 10th Workshop on Electronics for LHC and Future Experiments

    2004-01-01

    The Local Trigger Processor (LTP) receives timing and trigger signals from the Central Trigger Processor (CTP) and injects them into the Timing, Trigger and Control (TTC) system of a sub-detector front-end TTC partition. The LTP allows stand-alone running by using local timing and trigger signals or by generating them from memory. In addition, several LTPs of the same sub-detector can be daisy-chained. The LTP can thus be regarded as a switching element for timing and trigger signals with input from the CTP or the daisy-chain, from local input, or from the internal data generator, and with output to the daisy-chain, to the TTC partition, or to local output. Finally, in combined mode several LTPs can be connected together using their local outputs and local inputs to allow stand-alone running of combinations of different sub-detectors.

  13. A new VME trigger processor for the NA57 experiment

    CERN Document Server

    Antinori, Federico; Bloodworth, Ian J; Evans, D; Feofilov, G A; Jones, G T; Jovanovic, P; Kinson, J B; Kirk, A; Kocper, B; Kolojvari, A A; Králik, I; Lenti, V; Lupták, M; Norman, P I; Piuz, François; Staroba, P; Stokes, W N; Suchdolinská, I; Tomasicchio, G; Thompson, M; Van de Vyvre, P; Vascotto, Alessandro; Villalobos Baillie, O; Votruba, M F; Závada, P

    1997-01-01

    The ALICE experiment will use a trigger concept requiring independent deadtimes for each sub-detector system, and with detector-specific past-future protection. These features are implemented in a new VME-based trigger processor for the NA57 experiment. Monitoring and diagnostic features of the new trigger processor are also described.List of Figures Figure 1:ALICE trigger logic diagram. Figure 2:Layout of the NA57 experiment. Figure 3:Schematic layout of NA57 VME central trigger processor. Figure 4:Example of a trigger definition script.

  14. Report of the trigger processor subgroup

    International Nuclear Information System (INIS)

    This is a summary report of a small group of people who met one afternoon to discuss trigger processors. The trigger processor group spent much of its time discussing new architecture's for high rate experiments. There was an attempt to differentiate between data driven architectures and the more conventional systems where triggers are divided into a series of levels. This was not too successful because most people felt that there were elements of the data driven architecture in almost all trigger systems -- particularly at the front end. There are, however, broad divisions that are present in almost every trigger system. The typical trigger levels are defined as: level 1 - This is the section of the trigger that is truly dead timeless. The data is pipelined with enough buffers so that no crossing (event in fixed target) is lost. A trigger decision is generated at every crossing (but delayed by the length of the pipeline); level 3 - Processor farm with one complete event per processor; level 2 - Everything in between

  15. The UA1 upgrade calorimeter trigger processor

    International Nuclear Information System (INIS)

    The increased luminosity of the improved CERN Collider and the more subtle signals of second-generation collider physics demand increasingly sophisticated triggering. We have built a new first-level trigger processor designed to use the excellent granularity of the UA1 upgrade calorimeter. This device is entirely digital and handles events in 1.5 μs, thus introducing no deadtime. Its most novel feature is fast two-dimensional electromagnetic cluster-finding with the possibility of demanding an isolated shower of limited penetration. The processor allows multiple combinations of triggers on electromagnetic showers, hadronic jets and energy sums, including a total-energy veto of multiple interactions and a full vector sum of missing transverse energy. This hard-wired processor is about five times more powerful than its predecessor, and makes extensive use of pipelining techniques. It was used extensively in the 1988 and 1989 runs of the CERN Collider. (author)

  16. The Topological Processor for the future ATLAS Level-1 Trigger

    CERN Document Server

    Kahra, C; The ATLAS collaboration

    2014-01-01

    ATLAS is an experiment on the Large Hadron Collider (LHC), located at the European Organization for Nuclear Research (CERN) in Switzerland. By 2015 the LHC instantaneous luminosity will be increased from $10^{34}$ up to $3\\cdot 10^{34} \\mathrm{cm}^{-2} \\mathrm{s}^{-1}$. This places stringent operational and physical requirements on the ATLAS Trigger in order to reduce the 40MHz collision rate to a manageable event storage rate of 1kHz while at the same time, selecting those events that contain interesting physics events. The Level-1 Trigger is the first rate-reducing step in the ATLAS Trigger, with an output rate of 100kHz and decision latency of less than $2.5 \\mu \\mathrm{s}$. It is composed of the Calorimeter Trigger, the Muon Trigger and the Central Trigger Processor (CTP). In 2014, there will be a new electronics module: the Topological Processor (L1Topo). The L1Topo will make it possible, for the first time, to use detailed information from subdetectors in a single Level-1 module. This allows the determi...

  17. The Trigger Processor and Trigger Processor Algorithms for the ATLAS New Small Wheel Upgrade

    CERN Document Server

    Lazovich, Tomo; The ATLAS collaboration

    2015-01-01

    The ATLAS New Small Wheel (NSW) is an upgrade to the ATLAS muon endcap detectors that will be installed during the next long shutdown of the LHC. Comprising both MicroMegas (MMs) and small-strip Thin Gap Chambers (sTGCs), this system will drastically improve the performance of the muon system in a high cavern background environment. The NSW trigger, in particular, will significantly reduce the rate of fake triggers coming from track segments in the endcap not originating from the interaction point. We will present an overview of the trigger, the proposed sTGC and MM trigger algorithms, and the hardware implementation of the trigger. In particular, we will discuss both the heart of the trigger, an ATCA system with FPGA-based trigger processors (using the same hardware platform for both MM and sTGC triggers), as well as the full trigger electronics chain, including dedicated cards for transmission of data via GBT optical links. Finally, we will detail the challenges of ensuring that the trigger electronics can ...

  18. The ATLAS level-1 Central Trigger

    CERN Document Server

    Spiwoks, R; Berge, D; Caracinha, D; Ellis, Nick; Farthouat, P; Gällnö, P; Haas, S; Klofver, P; Krasznahorkay, A; Messina, A; Ohm, C; Pauly, T; Perantoni, M; Pessoa Lima Junior, H; Schuler, G; De Seixas, J M; Wengler, T; PH-EP

    2007-01-01

    The ATLAS Level-1 Central Trigger consists of the Muon-to-Central-Trigger-Processor Interface (MUCTPI), the Central Trigger Processor (CTP), and the Timing, Trigger and Control (TTC) partitions of the sub-detectors. The MUCTPI connects the output of the muon trigger system to the CTP. At every bunch crossing it receives information on muon candidates from each of the 208 muon trigger sectors and calculates the total multiplicity for each of six pT thresholds. The CTP combines information from the calorimeter trigger and the MUCTPI and makes the final Level-1 Accept (L1A) decision on the basis of lists of selection criteria (trigger menus). The MUCTPI and the CTP provide trigger summary information to the Level-2 trigger and to the data acquisition (DAQ) for every event selected at the Level-1. They further provide accumulated and, for the CTP, bunch-by-bunch counter data for monitoring of the trigger, detector and beam conditions. The TTC partitions send timing, trigger and control signals from the CTP to the...

  19. Parallel processor trigger with distributed real-time kernel

    Energy Technology Data Exchange (ETDEWEB)

    Korhonen, T.; Sakamoto, H.; Watase, Y. (National Lab. for High Energy Physics, Oho 1-1, Tsukuba, Ibaraki 305 (JP))

    1991-04-01

    This paper reports on a second level trigger system, based on 40 microprocessors working in parallel, designed and installed into the VENUS experiment. The purpose of the system is to find particle tracks in Central Drift Chamber on-line during A/D conversion time, in about 10 milliseconds. The authors' hardware is designed to be easily modified by software to get the optimum configuration for the task in hand. To realize sufficient computing power for the task, the task must be divided and distributed to processors as evenly as possible and a good balance between computation and communication load must be achieved. To be able to manage such a complicated system, several software tools have been developed. The software for the system has been entirely written in high level language. Sufficient performance for the trigger operation has been realized in tests with real event data.

  20. Review of trigger and on-line processors at SLAC

    International Nuclear Information System (INIS)

    The role of trigger and on-line processors in reducing data rates to manageable proportions in e+e- physics experiments is defined not by high physics or background rates, but by the large event sizes of the general-purpose detectors employed. The rate of e+e- annihilation is low, and backgrounds are not high; yet the number of physics processes which can be studied is vast and varied. This paper begins by briefly describing the role of trigger processors in the e+e- context. The usual flow of the trigger decision process is illustrated with selected examples of SLAC trigger processing. The features are mentioned of triggering at the SLC and the trigger processing plans of the two SLC detectors: The Mark II and the SLD. The most common on-line processors at SLAC, the BADC, the SLAC Scanner Processor, the SLAC FASTBUS Controller, and the VAX CAMAC Channel, are discussed. Uses of the 168/E, 3081/E, and FASTBUS VAX processors are mentioned. The manner in which these processors are interfaced and the function they serve on line is described. Finally, the accelerator control system for the SLC is outlined. This paper is a survey in nature, and hence, relies heavily upon references to previous publications for detailed description of work mentioned here. 27 references, 9 figures, 1 table

  1. The Level 0 Trigger Processor for the NA62 experiment

    Science.gov (United States)

    Chiozzi, S.; Gamberini, E.; Gianoli, A.; Mila, G.; Neri, I.; Petrucci, F.; Soldi, D.

    2016-07-01

    In the NA62 experiment at CERN, the intense flux of particles requires a high-performance trigger for the data acquisition system. A Level 0 Trigger Processor (L0TP) was realized, performing the event selection based on trigger primitives coming from sub-detectors and reducing the trigger rate from 10 to 1 MHz. The L0TP is based on a commercial FPGA device and has been implemented in two different solutions. The performance of the two systems are highlighted and compared.

  2. A general-purpose trigger processor system and its application to fast vertex trigger

    International Nuclear Information System (INIS)

    A general-purpose hardware trigger system has been developed. The system comprises programmable trigger processors and pattern generator/samplers. The hardware design of the system is described. An application as a prototype of the very fast vertex trigger in an asymmetric B-factory at KEK is also explained. (author)

  3. The fast tracker processor for hadron collider triggers

    CERN Document Server

    Annovi, A; Bardi, A; Carosi, R; Dell'Orso, Mauro; D'Onofrio, M; Giannetti, P; Iannaccone, G; Morsani, E; Pietri, M; Varotto, G

    2001-01-01

    Perspectives for precise and fast track reconstruction in future hadron collider experiments are addressed. We discuss the feasibility of a pipelined highly parallel processor dedicated to the implementation of a very fast tracking algorithm. The algorithm is based on the use of a large bank of pre-stored combinations of trajectory points, called patterns, for extremely complex tracking systems. The CMS experiment at LHC is used as a benchmark. Tracking data from the events selected by the level-1 trigger are sorted and filtered by the Fast Tracker processor at an input rate of 100 kHz. This data organization allows the level-2 trigger logic to reconstruct full resolution tracks with transverse momentum above a few GeV and search for secondary vertices within typical level-2 times. (15 refs).

  4. Commissioning of the ATLAS Level-1 Central Trigger

    CERN Document Server

    Berge, D; Ellis, N; Farthouat, P; Fischer, G; Haas, S; Haller, J; Maettig, S; Messina, A; Pauly, T; Sherman, D; Spiwoks, R

    2010-01-01

    The ATLAS Level-1 Central Trigger (L1CT) consists of the Central Trigger Processor (CTP) and the Muon to Central Trigger Processor Interface (MUCTPI). The CTP forms the final Level-1 Accept (L1A) decision based on the information received from the Level-1 Calorimeter Trigger system and from the muon trigger system through the MUCTPI. Additional inputs are provided for the forward detectors, the filled-bunch trigger, and the minimum-bias trigger scintillators. The CTP also receives timing signals from the Large Hadron Collider (LHC) machine. It fans out the L1A together with timing and control signals to the Local Trigger Processor (LTP) of the subdetectors. Via the same connections it receives the Busy signal to throttle the Level-1 generation. Upon generation of L1A the L1CT sends trigger summary information to the DAQ and Region-of-Interest to the Level-2 Trigger system. In this contribution we present an overview of the final L1CT trigger system as it is now installed in the ATLAS experiment and we describ...

  5. Upgrade of the ATLAS Level-1 trigger with an FPGA based Topological Processor

    CERN Document Server

    Simioni, Eduard; The ATLAS collaboration

    2015-01-01

    The Large Hadron Collider (LHC) in 2015 will collide proton beams with increased luminosity from $10^{34}$ up to $3 \\times 10^{34}cm^{-2}s^{-1}$. ATLAS is an LHC experiment designed to measure decay properties of high energetic particles produced in the protons collisions. The higher luminosity places stringent operational and physical requirements on the ATLAS Trigger in order to reduce the 40MHz collision rate to a manageable event storage rate of 1kHz while at the same time, selecting those events with valuable physics meaning. The Level-1 Trigger is the first rate-reducing step in the ATLAS Trigger, with an output rate of 100kHz and decision latency of less than 2.5$\\mu s$. It is composed of the Calorimeter Trigger (L1Calo), the Muon Trigger (L1Muon) and the Central Trigger Processor (CTP). In 2014, there will be a new electronics element in the chain: the Topological Processor System (L1Topo system). The L1Topo system consist of a single AdvancedTCA shelf equipped with three L1Topo processor blades. It w...

  6. The Topological Processor for the future ATLAS Level-1 Trigger: from design to commissioning

    CERN Document Server

    Simioni, E; The ATLAS collaboration

    2014-01-01

    The ATLAS experiment is located at the European Centre for Nuclear Research (CERN) in Switzerland. It is designed to measure decay properties of highly energetic particles produced in the protons collisions at the Large Hadron Collider (LHC). The LHC has a beam collision frequency of 40 MHz, and thus requires a trigger system to efficiently select events, thereby reducing the storage rate to a manageable level of about 400 Hz. Event triggering is therefore one of the extraordinary challenges faced by the ATLAS detector. The Level-1 Trigger is the first rate-reducing step in the ATLAS Trigger, with an output rate of 75kHz and decision latency of less than 2.5 s. It is primarily composed of the Calorimeter Trigger, Muon Trigger, the Central Trigger Processor (CTP). Due to the increase in the LHC instantaneous luminosity up 3 x 10^34/cm2 s from 2015 onwards, a new element will be included in the Level-1 Trigger scheme: the Topological Processor (L1Topo). The L1Topo receives data in a specialized format from the ...

  7. The ATLAS Level-1 Central Trigger System 012

    CERN Document Server

    Borrego-Amaral, P; Farthouat, Philippe; Gällnö, P; Haller, J; Maeno, T; Pauly, T; Schuler, G; Spiwoks, R; Torga-Teixeira, R; Wengler, T; Pessoa-Lima, H; De Seixas, J M

    2004-01-01

    The central part of the ATLAS Level-1 trigger system consists of the Central Trigger Processor (CTP), the Local Trigger Processors (LTPs), the Timing, Trigger and Control (TTC) system, and the Read-out Driver Busy (ROD_BUSY) modules. The CTP combines information from calorimeter and muon trigger processors, as well as from other sources and makes the final Level-1 Accept decision (L1A) on the basis of lists of selection criteria, implemented as a trigger menu. Timing and trigger signals are fanned out to about 40 LTPs which inject them into the sub-detector TTC partitions. The LTPs also support stand-alone running and can generate all necessary signals from memory. The TTC partitions fan out the timing and trigger signals to the sub-detector front-end electronics. The ROD_BUSY modules receive busy signals from the front-end electronics and send them to the CTP (via an LTP) to throttle the generation of L1As. An overview of the ATLAS Level-1 Central trigger system will be presented, with emphasis on the design...

  8. A VME RISC processor farm for third level triggering

    International Nuclear Information System (INIS)

    The need for very fast, compact, VME based farms of processors exists in many areas of experimental physics. Reported in this paper, is a development for such a farm targeted at the requirements of the online and trigger system of the CERN experiment PS195 (CPLEAR). The system is characterized as being VME based, and requiring small events (around 1KByte) to be processed at high rate (greater than 1KHz). The development was for a single chassis system, using the MIPS R3000 chip mounted on a commercially available board

  9. Network Processors for a 1-MHz trigger-DAQ system

    CERN Document Server

    Barczyk, A; Jost, B; Neufeld, N

    2004-01-01

    Network processors (NP), originally developed for applications in high-end network routers, have a great potential as building blocks for a high-speed networked data acquisition (DAQ)-Trigger system. After an introduction to NP, we will present several applications which illustrate their power in coping with high event rates and aggregate traffic of above 10 GB/s. All these applications can be implemented in a single, versatile, generic NP-based module, where the specific functionality is provided by the software. We will discuss the impact of protocol overheads on link utilization, and demonstrate a NP-based way of enhancing the portion of the bandwidth occupied by user data. One other application deals with sorting of trigger decision frames, and finally, we will look into the advantages of implementing a large switching network with the NP- based module. (7 refs).

  10. The global trigger processor: a VXS switch module for triggering large scale data acquisition systems

    International Nuclear Information System (INIS)

    The 12 GeV upgrade for Jefferson Lab's Continuous Electron Beam Accelerator Facility requires the development of a new data acquisition system to accommodate the proposed 200 kHz Level 1 trigger rates expected for fixed target experiments at 12 GeV. As part of a suite of trigger electronics comprised of VXS switch and payload modules, the Global Trigger Processor (GTP) will handle up to 32,768 channels of pre-processed trigger data from multiple detector systems that surround the beam target at a system clock rate of 250 MHz. The GTP is configured with user programmable Physics trigger equations and when trigger conditions are satisfied, the GTP will activate the storage of data for subsequent analysis. The GTP features an Altera Stratix IV GX FPGA allowing interface to 16 Sub-System Processor modules via 32 5-Gbps links, DDR2 and flash memory devices, two gigabit Ethernet interfaces using Nios II embedded processors, fiber optic transceivers, and trigger output signals. The GTP's high-bandwidth interconnect with the payload modules in the VXS crate, the Ethernet interface for parameter control, status monitoring, and remote update, and the inherent nature of its FPGA give it the flexibility to be used large variety of tasks and adapt to future needs. This paper details the responsibilities of the GTP, the hardware's role in meeting those requirements, and elements of the VXS architecture that facilitated the design of the trigger system. Also presented will be the current status of development including significant milestones and challenges. (authors)

  11. The TIGER trigger processor for the CAMERA detector at COMPASS-II

    International Nuclear Information System (INIS)

    In today's nuclear and high-energy physics experiments the background-induced occupancy of the detector channels can be quite high; therefore it is important to have sophisticated trigger subsystems which process the data in real-time to generate trigger objects for the global trigger decision. In this work we present a FPGA based low-latency trigger processor for the COMPASS-II experiment. TIGER is a high-performance trigger processor that was developed to fit perfectly in the GANDALF framework and extend its versatility. It is designed as a VXS module and is allocated to the central VXS switch slot, which has a direct link from every payload slot. The synchronous transfer protocol was optimized for low latencies and offers a bandwidth of up to 8 Gbit/s per link. The centerpiece of the board is a Xilinx Virtex-6 SX315T FPGA, offering vast programmable logic, embedded memory and DSP resources. It is accompanied by DDR3 memory, a COM Express CPU and a MXM GPU. Besides the VXS backplane ports, the board features two SFP+ transceivers, 32 LVDS inputs and 32 LVDS outputs to interface with the global trigger system and a Gigabit Ethernet port for configuration and monitoring.

  12. An Upgraded ATLAS Central Trigger for 2014 LHC Luminosities

    CERN Document Server

    Kaneda, M; The ATLAS collaboration

    2012-01-01

    During 2011, the LHC reached instantaneous luminosities of 4*10^33 cm-2*s-1 and produced events with up to 24 interactions per colliding proton bunch. Thisplaces stringent operational and physical requirements on the ATLAS Trigger in order to reduce the 40MHz collision rate to a manageable event storage rate of ~400Hz and, atthe same time, selecting those events considered interesting. The Level-1 Trigger is the first rate-reducing step in the ATLAS Trigger, with an output rate of 75kHz and adecision latency of less than 2.5us. It is primarily composed of the Calorimeter Trigger, Muon Trigger, and the Central Trigger Processor which are implemented in custom builtVME electronics. The Central Trigger Processor collects trigger information from all Level-1 systems and produces a Level-1 trigger decision that initiates the readout of all ATLAS subdetectors. In 2014, the LHC will run at a center of mass energy of 14 TeV, compared to the current 8 TeV, and the luminosity will exceed 10^34 cm^-2*s^-1. With higher l...

  13. An Upgraded ATLAS Central Trigger for 2014 Luminosities

    CERN Document Server

    Anders, G; The ATLAS collaboration; Bertelsen, H; Childers, T; Dam, M; Dobson, E; Ellis, N; Farthouat, P; Gabaldon, C; Gorini, B; Haas, S; Kaneda, M; Maettig, S; Messina, A; Pauly, T; Pöttgen, R; Spiwoks, R; Wengler, T; Xella, S

    2012-01-01

    During 2011, the LHC reached instantaneous luminosities of 4*10^33 cm-2*s-1 and produced events with up to 24 interactions per colliding proton bunch. This places stringent operational and physical requirements on the ATLAS Trigger in order to reduce the 40MHz collision rate to a manageable event storage rate of ~400Hz and, at the same time, selecting those events considered interesting. The Level-1 Trigger is the first rate-reducing step in the ATLAS Trigger, with an output rate of 75kHz and a decision latency of less than 2.5us. It is primarily composed of the Calorimeter Trigger, Muon Trigger, and the Central Trigger Processor which are implemented in custom built VME electronics. The Central Trigger Processor collects trigger information from all Level-1 systems and produces a Level-1 trigger decision that initiates the readout of all ATLAS detectors. In 2014, the LHC will run at a center of mass energy of 14 TeV, compared to the current 8 TeV, and the luminosity will exceed 10^34 cm^-2*s^-1. With higher ...

  14. An Upgraded ATLAS Central Trigger for 2014 LHC Luminosities

    CERN Document Server

    Kaneda, M; The ATLAS collaboration

    2012-01-01

    During 2011, the LHC reached instantaneous luminosities of 4*10^33 cm^-1*s^-1 and produced events with up to 24 interactions per colliding proton bunch. This places stringent operational and physical requirements on the ATLAS Trigger in order to reduce the 40MHz collision rate to a manageable event storage rate of ~400Hz and, at the same time, selecting those events considered interesting. The Level-1 Trigger is the first rate-reducing step in the ATLAS Trigger, with an output rate of 75kHz and a decision latency of less than 2.5us. It is primarily composed of the Calorimeter Trigger, Muon Trigger, and the Central Trigger Processor which are implemented in custom built VME electronics. The Central Trigger Processor collects trigger information from all Level-1 systems and produces a Level-1 trigger decision that initiates the readout of all ATLAS sub-detectors. In 2014, the LHC will run at a center of mass energy of 14 TeV, compared to the current 8 TeV, and the luminosity will exceed 10^34 cm^-1*s^-1. With h...

  15. An upgraded ATLAS Central Trigger for post-2014 LHC luminosities

    CERN Document Server

    Anders, G; The ATLAS collaboration; Bertelsen, H; Childers, T; Dam, M; Dobson, E; Ellis, N; Farthouat, P; Gabaldon, C; Gorini, B; Haas, S; Kaneda, M; Maettig, S; Messina, A; Ohm, C; Pauly, T; Poettgen, R; Spiwoks, R; Wengler, T; Xella, S

    2012-01-01

    During 2011, the LHC reached instantaneous luminosities of 6.7 · 10^33 cm−2s−1 and produced events with up to 40 interactions per colliding proton bunch. This places stringent operational and physical requirements on the ATLAS trigger in order to reduce the 40 MHz collision rate to a manageable event storage rate of 400 Hz without discarding those events considered interesting. The Level-1 trigger is the first rate-reducing step in the ATLAS trigger, with an output rate of 75 kHz and a decision latency of less than 2.5 μ s. It is primarily composed of the Calorimeter Trigger, Muon Trigger, and the Central Trigger Processor which are implemented in custom built VME electronics. The Central Trigger Processor collects trigger information from all Level-1 systems and produces a Level-1 trigger decision that initiates the readout of all ATLAS detectors. After 2014, the LHC will run at a center of mass energy of up to 14 TeV, compared to the current 8 TeV, and the luminosity will exceed 10^34 cm−2s−1. Wit...

  16. The ATLAS Level-1 Central Trigger System in operation

    Science.gov (United States)

    Pauly, Thilo; ATLAS Collaboration

    2010-04-01

    The ATLAS Level-1 Central Trigger (L1CT) system is a central part of ATLAS data-taking. It receives the 40 MHz bunch clock from the LHC machine and distributes it to all sub-detectors. It initiates the detector read-out by forming the Level-1 Accept decision, which is based on information from the calorimeter and muon trigger processors, plus a variety of additional trigger inputs from detectors in the forward regions. The L1CT also provides trigger-summary information to the data acquisition and the Level-2 trigger systems for use in higher levels of the selection process, in offline analysis, and for monitoring. In this paper we give an overview of the operational framework of the L1CT with particular emphasis on cross-system aspects. The software framework allows a consistent configuration with respect to the LHC machine, upstream and downstream trigger processors, and the data acquisition. Trigger and dead-time rates are monitored coherently on all stages of processing and are logged by the online computing system for physics analysis, data quality assurance and operational debugging. In addition, the synchronisation of trigger inputs is watched based on bunch-by-bunch trigger information. Several software tools allow to efficiently display the relevant information in the control room in a way useful for shifters and experts. We present the overall performance during cosmic-ray data taking with the full ATLAS detector and the experience with first beam in the LHC.

  17. The ATLAS Level-1 Central Trigger System in operation

    International Nuclear Information System (INIS)

    The ATLAS Level-1 Central Trigger (L1CT) system is a central part of ATLAS data-taking. It receives the 40 MHz bunch clock from the LHC machine and distributes it to all sub-detectors. It initiates the detector read-out by forming the Level-1 Accept decision, which is based on information from the calorimeter and muon trigger processors, plus a variety of additional trigger inputs from detectors in the forward regions. The L1CT also provides trigger-summary information to the data acquisition and the Level-2 trigger systems for use in higher levels of the selection process, in offline analysis, and for monitoring. In this paper we give an overview of the operational framework of the L1CT with particular emphasis on cross-system aspects. The software framework allows a consistent configuration with respect to the LHC machine, upstream and downstream trigger processors, and the data acquisition. Trigger and dead-time rates are monitored coherently on all stages of processing and are logged by the online computing system for physics analysis, data quality assurance and operational debugging. In addition, the synchronisation of trigger inputs is watched based on bunch-by-bunch trigger information. Several software tools allow to efficiently display the relevant information in the control room in a way useful for shifters and experts. We present the overall performance during cosmic-ray data taking with the full ATLAS detector and the experience with first beam in the LHC.

  18. Data driven processor 'Vertex Trigger' for B experiments

    International Nuclear Information System (INIS)

    Data Driven Processors (DDP's) are specialized computation engines configured to solve specific numerical problems, such as vertex reconstruction. The architecture of the DDP which is the subject of this talk was designed and implemented by W. Sippach and B.C. Knapp at Nevis Lab. in the early 1980's. This particular implementation allows multiple parallel streams of data to provide input to a heterogenous collection of simple operators whose interconnection form an algorithm. The local data flow control allows this device to execute algorithms extremely quickly provided that care is taken in the layout of the algorithm. I/O rates of several hundred megabytes/second are routinely achieved thus making DDP's attractive candidates for complex online calculations. The original question was open-quote can a DDP reconstruct tracks in a Silicon Vertex Detector, find events with a separated vertex and do it fast enough to be used as an online trigger?close-quote Restating this inquiry as three questions and describing the answers to the questions will be the subject of this talk. The three specific questions are: (1) Can an algorithm be found which reconstructs tracks in a planar geometry and no magnetic field; (2) Can separated vertices be recognized in some way; (3) Can the algorithm be implemented in the Nevis-UMass and DDP and execute in 10-20 μs?

  19. The ATLAS Level-1 Central Trigger System in Operation

    CERN Document Server

    Pauly, T

    2010-01-01

    The ATLAS Level-1 Central Trigger (L1CT) electronics is a central part of ATLAS data-taking. It receives the 40 MHz bunch clock from the LHC machine and distributes it to all sub-detectors. It initiates the detector read-out by forming the Level-1 Accept decision, which is based on information from the calorimeter and muon trigger processors, plus a variety of additional trigger inputs from detectors in the forward regions. The L1CT also provides trigger-summary information to the data acquisition and the Level-2 trigger systems for use in higher levels of the selection process, in offline analysis, and for monitoring. In this paper we give an overview of the operational framework of the L1CT with particular emphasis on cross-system aspects. The software framework allows a consistent configuration with respect to the LHC machine, upstream and downstream trigger processors, and the data acquisition. Trigger and dead-time rates are monitored coherently on all stages of processing and are logged by the online c...

  20. Simulation of the new topological processor in the ATLAS first level trigger

    International Nuclear Information System (INIS)

    The LHC will start again in May 2015 with proton-proton collisions at a center of mass energy of √(s)=13 TeV. This results in an increased rate of collisions and a new approach is needed in order to keep high efficiencies for processes of interest at the first level trigger stage. A new trigger module for the first level trigger stage of the ATLAS experiment has been developed in order to achieve this. This new trigger module, the topological processor, is able to make trigger decisions based on topological observables, for example angular correlations of trigger objects from the ATLAS calorimeter and muon system. This talk concentrates on the validation of the trigger decision and read-out of the topological processor by using a bit-wise simulation of the module. The basic strategy how the hardware is validated, and first results are presented.

  1. The ATLAS Level-1 Calorimeter Trigger: PreProcessor implementation and performance

    International Nuclear Information System (INIS)

    The PreProcessor system of the ATLAS Level-1 Calorimeter Trigger (L1Calo) receives about 7200 analogue signals from the electromagnetic and hadronic components of the calorimetric detector system. Lateral division results in cells which are pre-summed to so-called Trigger Towers of size 0.1 × 0.1 along azimuth (φ) and pseudorapidity (η). The received calorimeter signals represent deposits of transverse energy. The system consists of 124 individual PreProcessor modules that digitise the input signals for each LHC collision, and provide energy and timing information to the digital processors of the L1Calo system, which identify physics objects forming much of the basis for the full ATLAS first level trigger decision. This paper describes the architecture of the PreProcessor, its hardware realisation, functionality, and performance.

  2. Testing the PreProcessor modules of the ATLAS level-1 calorimeter Trigger

    International Nuclear Information System (INIS)

    The PreProcessor (PPr) System of the ATLAS Level-1 Calorimeter Trigger is a highly parallel system which receives, digitises and processes about 7200 analogue calorimeter trigger signals from the entire ATLAS Calorimetry. Its key component is a custom build ASIC which determines the transverse energy deposits and transmits them to the object-finding processors of the calorimeter trigger: Cluster Processor and Jet/Energy-Sum Processor. The PPr System consists of 124 identical 9U VME PreProcessor Modules (PPMs), which fit into 8 crates. Each module receives and processes 64 analogue calorimeter trigger signals. Before the modules are installed in the electronic cavern of the experiment, their proper operation has to be ensured. An extensive test procedure has been developed to establish all functions of the PPM in short and long periods of operation. The modules are tested both individually as well as in a crate configuration similar to that of the final system. The transmission of the real-time data over 15m long LVDS cables and the readout are checked with a dedicated VME based system, which emulates both the processors of the calorimeter trigger and a DAQ readout module. Additionally, periodic monitoring of the temperatures and voltages across each board is performed during tests to verify the operating conditions of the modules

  3. The ATLAS Barrel Level-1 Muon Trigger Processor Performances

    CERN Document Server

    Bocci, V; Ciapetti, G; De Pedis, D; Di Girolamo, A; Di Mattia, A; Gennari, E; Luci, C; Nisati, A; Pasqualucci, E; Pastore, F; Petrolo, E; Spila, F; Vari,, R; Veneziano, S; Zanelli, L; Aielli, G; Cardarelli, R; Di Ciaccio, A; Di Simone, A; Di Stante, L; Salamon, A; Santonico, R; Aloisio, A; Alviggi, M G; Canale, V; Carlino, G; Conventi, F; De Asmundis, R; Della Pietra, M; Delle Volpe, D; Iengo, P; Izzo, V; Migliaccio, A; Patricelli, S; Sekhniaidze, G; Brambilla, Elena; Cataldi, G; Gorini, E; Grancagnolo, F; Perrino, R; Primavera, M; Spagnolo, S; Aprodo, V; Bartos, D; Buda, S; Constantin, S; Dogaru, M; Magureanu, C; Pectu, M; Prodan, L; Rusu, A; Uroseviteanu, C

    2005-01-01

    The ATLAS level-1 muon trigger will select events with high transverse momentum and tag them to the correct machine bunch-crossing number with high efficiency. Three stations of dedicated fast detectors provide a coarse pT measurement, with tracking capability on bending and non-bending pro jections. In the Barrel region, hits from doublets of Resistive Plate Chambers are processed by custom ASIC, the Coincidence Matrices, which performs almost all the functionalities required by the trigger algorithm and the readout. In this paper we present the performance of the level-1 trigger system studied on a cosmic test stand at CERN, concerning studies on expected trigger rates and efficiencies.

  4. Operation of the Upgraded ATLAS Level-1 Central Trigger System

    CERN Document Server

    Glatzer, Julian Maximilian Volker; The ATLAS collaboration

    2015-01-01

    The ATLAS Level-1 Central Trigger (L1CT) system is a central part of ATLAS data-taking and has undergone a major upgrade for Run 2 of the LHC, in order to cope with the expected increase of instantaneous luminosity of a factor of 2 with respect to Run 1. The upgraded hardware offers more flexibility in the trigger decisions due to the double amount of trigger inputs and usable trigger channels. It also provides an interface to the new topological trigger system. Operationally - particularly useful for commissioning, calibration and test runs - it allows concurrent running of up to 3 different subdetector combinations. An overview of the operational software framework of the L1CT system with particular emphasis of the configuration, controls and monitoring aspects is given. The software framework allows a consistent configuration with respect to the ATLAS experiment and the LHC machine, upstream and downstream trigger processors, and the data acquisition. Trigger and dead-time rates are monitored coherently at...

  5. Operation of the Upgraded ATLAS Level-1 Central Trigger System

    CERN Document Server

    Glatzer, Julian Maximilian Volker; The ATLAS collaboration

    2015-01-01

    The ATLAS Level-1 Central Trigger (L1CT) system is a central part of ATLAS data-taking and has undergone a major upgrade for Run 2 of the LHC, in order to cope with the expected increase of instantaneous luminosity of a factor of 2 with respect to Run 1. The upgraded hardware offers more flexibility in the trigger decisions due to the double amount of trigger inputs and usable trigger channels. It also provides an interface to the new topological trigger system. Operationally - particularly useful for commissioning, calibration and test runs - it allows concurrent running of up to 3 different sub-detector combinations. In this contribution, we give an overview of the operational software framework of the L1CT system with particular emphasis of the configuration, controls and monitoring aspects. The software framework allows a consistent configuration with respect to the ATLAS experiment and the LHC machine, upstream and downstream trigger processors, and the data acquisition. Trigger and dead-time rates are m...

  6. Operation of the Upgraded ATLAS Level-1 Central Trigger System

    Science.gov (United States)

    Glatzer, Julian

    2015-12-01

    The ATLAS Level-1 Central Trigger (L1CT) system is a central part of ATLAS data-taking and has undergone a major upgrade for Run 2 of the LHC, in order to cope with the expected increase of instantaneous luminosity of a factor of two with respect to Run 1. The upgraded hardware offers more flexibility in the trigger decisions due to the factor of two increase in the number of trigger inputs and usable trigger channels. It also provides an interface to the new topological trigger system. Operationally - particularly useful for commissioning, calibration and test runs - it allows concurrent running of up to three different subdetector combinations. An overview of the operational software framework of the L1CT system with particular emphasis on the configuration, controls and monitoring aspects is given. The software framework allows a consistent configuration with respect to the ATLAS experiment and the LHC machine, upstream and downstream trigger processors, and the data acquisition system. Trigger and dead-time rates are monitored coherently at all stages of processing and are logged by the online computing system for physics analysis, data quality assurance and operational debugging. In addition, the synchronisation of trigger inputs is watched based on bunch-by-bunch trigger information. Several software tools allow for efficient display of the relevant information in the control room in a way useful for shifters and experts. The design of the framework aims at reliability, flexibility, and robustness of the system and takes into account the operational experience gained during Run 1. The Level-1 Central Trigger was successfully operated with high efficiency during the cosmic-ray, beam-splash and first Run 2 data taking with the full ATLAS detector.

  7. Monitoring the pre-processor system of the ATLAS level-1 calorimeter trigger

    International Nuclear Information System (INIS)

    The Pre-Processor (PPr) System of the ATLAS Level-1 Calorimeter Trigger is a highly parallel system, with hard-wired algorithms implemented in ASICs, to receive, digitise and process over 7000 analogue trigger tower signals from the entire ATLAS Calorimetry, and to transmit the determined transverse energy deposits to the object-finding processors of the calorimeter trigger: Cluster Processor and Jet/Energy-sum Processor. The PPr System consists of 8 crates, each of which being equipped with 16 Preprocessor Modules, that can each receive and process 64 analogue input signals. The Preprocessor System provides facilities to monitor the operation and performance of both its individual components and the Level-1 Calorimeter Trigger: pipelined readout of event based monitoring data to the DAQ System, in order to document the Level-1 Trigger decision, diagnostic features implemented in PPrASIC to establish rate maps and energy spectra per trigger tower, and output interface to the crate controller CPU. Monitoring software for trigger-specific applications is developed and presented in this talk. (orig.)

  8. The Calorimeter Trigger Processor Card: the next generation of high speed algorithmic data processing at CMS

    Science.gov (United States)

    Svetek, A.; Blake, M.; Cepeda Hermida, M.; Dasu, S.; Dodd, L.; Fobes, R.; Gomber, B.; Gorski, T.; Guo, Z.; Klabbers, P.; Levine, A.; Ojalvo, I.; Ruggles, T.; Smith, N.; Smith, W. H.; Tikalsky, J.; Vicente, M.; Woods, N.

    2016-02-01

    The CMS Level-1 upgraded calorimeter trigger requires a powerful, flexible and compact processing card. The Calorimeter Trigger Processor Card (CTP7) uses the Virtex-7 FPGA as its primary data processor and is the first FPGA based processing card in CMS to employ the ZYNQ System-on-Chip (SoC) running embedded Linux to provide TCP/IP communication and board support functions. The CTP7 was built from the ground up to support AXI infrastructure to provide flexible and modular designs with minimal time from project conception to final implementation.

  9. The Calorimeter Trigger Processor Card: the next generation of high speed algorithmic data processing at CMS

    International Nuclear Information System (INIS)

    The CMS Level-1 upgraded calorimeter trigger requires a powerful, flexible and compact processing card. The Calorimeter Trigger Processor Card (CTP7) uses the Virtex-7 FPGA as its primary data processor and is the first FPGA based processing card in CMS to employ the ZYNQ System-on-Chip (SoC) running embedded Linux to provide TCP/IP communication and board support functions. The CTP7 was built from the ground up to support AXI infrastructure to provide flexible and modular designs with minimal time from project conception to final implementation

  10. The ATLAS Level-1 Central Trigger

    International Nuclear Information System (INIS)

    The ATLAS Level-1 trigger system is responsible for reducing the anticipated LHC collision rate from 40 MHz to less than 100 kHz. This Level-1 selection counts jet, tau/hadron, electron/photon and muon candidates, with additional triggers for missing and total energy. The results are used by the Level-1 Central Trigger to form a Level-1 Accept decision. This decision, along with timing signals, is sent to the sub-detectors from the Level-1 Central trigger, while summary information is passed into the higher levels of the trigger system. The performance of the Central Trigger during the first collisions will be shown. This includes details of how the trigger information, along with dead-time rates, are monitored and logged by the online system for physics analysis, data quality assurance and operational debugging. Also presented are the software tools used to efficiently display the relevant information in the control room in a way useful for shifters and experts.

  11. A high speed Sorting Processor ASIC for the RPC Trigger system of the CMS experiment

    CERN Document Server

    De Robertis, G; Ranieri, A

    1999-01-01

    The design of a high speed Sorting Processor ASIC is presented. It was designed in BiCMOS 0.8 mu m technology and its aim is to reorder and provide the four highest words among eight input words, in decreasing order. This chip is the main component of the sorting tree of the Trigger Muon System of the CMS experiment.

  12. A high speed Sorting Processor ASIC for the RPC Trigger system of the CMS experiment

    Energy Technology Data Exchange (ETDEWEB)

    De Robertis, G.; Loddo, F. E-mail: flavio.loddo@ba.infn.it; Ranieri, A

    1999-11-01

    The design of a high speed Sorting Processor ASIC is presented. It was designed in BiCMOS 0.8 {mu}m technology and its aim is to reorder and provide the four highest words among eight input words, in decreasing order. This chip is the main component of the sorting tree of the Trigger Muon System of the CMS experiment.

  13. A high speed Sorting Processor ASIC for the RPC Trigger system of the CMS experiment

    International Nuclear Information System (INIS)

    The design of a high speed Sorting Processor ASIC is presented. It was designed in BiCMOS 0.8 μm technology and its aim is to reorder and provide the four highest words among eight input words, in decreasing order. This chip is the main component of the sorting tree of the Trigger Muon System of the CMS experiment

  14. A fast filter processor as part of the trigger logic in an elastic scattering experiment

    International Nuclear Information System (INIS)

    A fast special purpose processor as a part of the trigger logic in an elastic scattering experiment is described. The decision to incorporate such a processoras taken because the trigger rate w was estimated to be an order of magnitude higher than the data taking capability of the on-line minicomputer, a NORD 10. The processor is capable of checking the coplanarity and the opening angle of the two outgoing tracks within about 100 microsec. This is done with a spatial resolution of 1 mm by using two points along each track given by 3 MWPC's. For comparison this is two orders of magnitude faster than the same algorithm coded in assembler language on a PDP11/40. The main contribution to this increased speed is due to extensive use pipelining and parallelism. When running with the processor in the trigger, 75% more elastic events per incoming beam particle were collected, and 3 times as many elastic events per trigger were recorded on to tape for further in-depth analysis, than previously. Due to major improvements in the primary trigger logic this was less than the gain initially anticipated. (Auth.)

  15. Fast track-finding trigger processor for the SLAC/LBL Mark II Detector

    International Nuclear Information System (INIS)

    The SLAC/LBL Mark II Magnetic Detector consists of various particle detectors arranged in cylindrical symmetry located in and around an axial magnetic field. A versatile, programmable secondary trigger processor was designed and built to find curved tracks in the detector. The system operates at a 10 MHz clock rate with a total processing time of 34 μsec and is used to ''trigger'' the data processing computer, thereby rejecting background and greatly improving the data acquisition aspects of the detector-computer combination

  16. A track reconstructing low-latency trigger processor for high-energy physics

    International Nuclear Information System (INIS)

    The detection and analysis of the large number of particles emerging from high-energy collisions between atomic nuclei is a major challenge in experimental heavy-ion physics. Efficient trigger systems help to focus the analysis on relevant events. A primary objective of the Transition Radiation Detector of the ALICE experiment at the LHC is to trigger on high-momentum electrons. In this thesis, a trigger processor is presented that employs massive parallelism to perform the required online event reconstruction within 2 μs to contribute to the Level-1 trigger decision. Its three-stage hierarchical architecture comprises 109 nodes based on FPGA technology. Ninety processing nodes receive data from the detector front-end at an aggregate net bandwidth of 2.16 Tbit/s via 1080 optical links. Using specifically developed components and interconnections, the system combines high bandwidth with minimum latency. The employed tracking algorithm three-dimensionally reassembles the track segments found in the detector's drift chambers based on explicit value comparisons, calculates the momentum of the originating particles from the course of the reconstructed tracks, and finally leads to a trigger decision. The architecture is capable of processing up to 20 000 track segments in less than 2 μs with high detection efficiency and reconstruction precision for high-momentum particles. As a result, this thesis shows how a trigger processor performing complex online track reconstruction within tight real-time requirements can be realized. The presented hardware has been built and is in continuous data taking operation in the ALICE experiment. (orig.)

  17. A track reconstructing low-latency trigger processor for high-energy physics

    Energy Technology Data Exchange (ETDEWEB)

    Cuveland, Jan de

    2009-09-17

    The detection and analysis of the large number of particles emerging from high-energy collisions between atomic nuclei is a major challenge in experimental heavy-ion physics. Efficient trigger systems help to focus the analysis on relevant events. A primary objective of the Transition Radiation Detector of the ALICE experiment at the LHC is to trigger on high-momentum electrons. In this thesis, a trigger processor is presented that employs massive parallelism to perform the required online event reconstruction within 2 {mu}s to contribute to the Level-1 trigger decision. Its three-stage hierarchical architecture comprises 109 nodes based on FPGA technology. Ninety processing nodes receive data from the detector front-end at an aggregate net bandwidth of 2.16 Tbit/s via 1080 optical links. Using specifically developed components and interconnections, the system combines high bandwidth with minimum latency. The employed tracking algorithm three-dimensionally reassembles the track segments found in the detector's drift chambers based on explicit value comparisons, calculates the momentum of the originating particles from the course of the reconstructed tracks, and finally leads to a trigger decision. The architecture is capable of processing up to 20 000 track segments in less than 2 {mu}s with high detection efficiency and reconstruction precision for high-momentum particles. As a result, this thesis shows how a trigger processor performing complex online track reconstruction within tight real-time requirements can be realized. The presented hardware has been built and is in continuous data taking operation in the ALICE experiment. (orig.)

  18. A 3-D Track-Finding Processor for the CMS Level-1 Muon Trigger

    OpenAIRE

    Acosta, D.(University of Florida, Gainesville, USA); Golovtsov, V.; Kan, M.; Madorsky, A.; Scurlock, B; Stoeck, H; Uvarov, L.; Wang, S. M.

    2003-01-01

    We report on the design and test results of a prototype processor for the CMS Level-1 trigger that performs 3-D track reconstruction and measurement from data recorded by the cathode strip chambers of the endcap muon system. The tracking algorithms are written in C++ using a class library we developed that facilitates automatic conversion to Verilog. The code is synthesized into firmware for field-programmable gate-arrays from the Xilinx Virtex-II series. A second-generation prototype has bee...

  19. An FPGA based demonstrator for a topological processor in the future ATLAS L1-Calo trigger “GOLD”

    CERN Document Server

    Ebling, A; Büscher, V; Degele, R; Ji, W; Meyer, C; Moritz, S; Schäfer, U; Simioni, E; Tapprogge, S; Wenzel, V

    2012-01-01

    Abstract: The existing ATLAS trigger consists of three levels. The level 1 (L1) is an FPGAs based custom designed trigger, while the second and third levels are software based. The LHC machine plans to bring the beam energy to the maximum value of 7 TeV and to increase the luminosity in the coming years. The current L1 trigger system is therefore seriously challenged. To cope with the resulting higher event rate, as part of the ATLAS trigger upgrade, a new electronics module is foreseen to be added in the ATLAS Level-1 Calorimeter Trigger electronics chain: the Topological Processor (TP). Such a processor needs fast optical I/O and large aggregate bandwidth to use the information on trigger object position in space (e.g. jets in the calorimeters or muons measured in the muon detectors) to improve the purity of the L1 triggers streams by applying topological cuts within the L1 latency budget. In this paper, an overview of the adopted technological solutions and the R&D activities on the demonstrator for th...

  20. An FPGA based demonstrator for a topological processor in the future ATLAS L1-Calo trigger 'GOLD'

    International Nuclear Information System (INIS)

    The existing ATLAS trigger consists of three levels. The level 1 (L1) is an FPGAs based custom designed trigger, while the second and third levels are software based. The LHC machine plans to bring the beam energy to the maximum value of 7 TeV and to increase the luminosity in the coming years. The current L1 trigger system is therefore seriously challenged. To cope with the resulting higher event rate, as part of the ATLAS trigger upgrade, a new electronics module is foreseen to be added into the ATLAS Level-1 Calorimeter Trigger electronics chain: the topological Processor (TP). Such a processor needs fast optical I/O and large aggregate bandwidth to use the information on trigger object position in space (e.g. jets in the calorimeters or muons measured in the muon detectors) to improve the purity of the L1 triggers streams by applying topological cuts within the L1 latency budget. In this paper, an overview of the adopted technological solutions and the R and D activities on the demonstrator for the TP ('GOLD') are presented.

  1. Metabolic pathway engineering using the central signal processor PII

    OpenAIRE

    Watzer, Björn; Engelbrecht, Alicia; Hauf, Waldemar; Stahl, Mark; Maldener, Iris; Forchhammer, Karl

    2015-01-01

    Background PII signal processor proteins are wide spread in prokaryotes and plants where they control a multitude of anabolic reactions. Efficient overproduction of metabolites requires relaxing the tight cellular control circuits. Here we demonstrate that a single point mutation in the PII signaling protein from the cyanobacterium Synechocystis sp. PCC 6803 is sufficient to unlock the arginine pathway causing over accumulation of the biopolymer cyanophycin (multi-l-arginyl-poly-l-aspartate)....

  2. An FPGA based demonstrator for a topological processor in the,future ATLAS L1-Calo trigger (“GOLD”)

    CERN Document Server

    "Bauss, B"; The ATLAS collaboration; "Degele, R"; "Ebling, A"; "Ji, W"; "Meyer, C"; "Moritz, S"; "Schaefer, U"; "Simioni, E"; "Tapprogge, S"; "Wenzel, V"

    2011-01-01

    The existing ATLAS trigger consists of three levels. The level 1 (L1) is an FPGAs based custom designed trigger, while the second and third levels are software based. The LHC machine plans to bring the beam energy to the nominal value of 7 TeV and to increase the luminosity in the coming years. The current L1 trigger system is therefore seriously challenged. To cope with the resulting higher event rate, as part of the ATLAS trigger upgrade, a new electronics module is foreseen to be added in the L1-Calo electronics chain: the topological processor. Such processor is provided with fast optical I/O and large bandwidth capability, in order to use the information on the cluster position in space (i.e. jets in the calorimeters or muons in the muon detectors) and improve the purity of the L1 triggers streams by applying topological cuts within the latency budget. In this talk, an overview of the adopted tecnological solutions and the R&D activities on the demonstrator (“GOLD”) are presented.

  3. Organization of multi-level triggering and data acquisition in experiments on studing relativistic positronium using dialog and microprogrammed processors

    International Nuclear Information System (INIS)

    A multilevel triggering system for data acquisition on studying positronium decay in experiments at the U-70 accelerator is considered. Produced electrons and positrons are detected by two telescopes comprising three sets of drift chambers (2500 detecting channels) as well as scintillation and Cherenkov counters. Detector loading makes up 1.5x106 particlesxs-1. The multilevel triggering system ensures decrease of dead time of the system and increase of the coefficient of legitimate event selection. A special 16-digit microprogrammed processor which executs of data selection by two geometrical criteria in X-projection is used for increase of efficiency of data acquisition system. The facility control is realized using a dialog microcomputer without data receipt. Software of data acquisition system is essentially simplified here and a possibility of quick development and initiation of new programs arises

  4. TRIGGER

    CERN Multimedia

    W. Smith

    At the March meeting, the CMS trigger group reported on progress in production, tests in the Electronics Integration Center (EIC) in Prevessin 904, progress on trigger installation in the underground counting room at point 5, USC55, the program of trigger pattern tests and vertical slice tests and planning for the Global Runs starting this summer. The trigger group is engaged in the final stages of production testing, systems integration, and software and firmware development. Most systems are delivering final tested electronics to CERN. The installation in USC55 is underway and integration testing is in full swing. A program of orderly connection and checkout with subsystems and central systems has been developed. This program includes a series of vertical subsystem slice tests providing validation of a portion of each subsystem from front-end electronics through the trigger and DAQ to data captured and stored. After full checkout, trigger subsystems will be then operated in the CMS Global Runs. Continuous...

  5. Commodity multi-processor systems in the ATLAS level-2 trigger

    International Nuclear Information System (INIS)

    Low cost SMP (Symmetric Multi-Processor) systems provide substantial CPU and I/O capacity. These features together with the ease of system integration make them an attractive and cost effective solution for a number of real-time applications in event selection. In ATLAS the authors consider them as intelligent input buffers (active ROB complex), as event flow supervisors or as powerful processing nodes. Measurements of the performance of one off-the-shelf commercial 4-processor PC with two PCI buses, equipped with commercial FPGA based data source cards (microEnable) and running commercial software are presented and mapped on such applications together with a long-term program of work. The SMP systems may be considered as an important building block in future data acquisition systems

  6. Commodity multi-processor systems in the ATLAS level-2 trigger

    CERN Document Server

    Abolins, M; Bock, R; Bogaerts, J A C; Dawson, J; Ermoline, Y; Hauser, R; Kugel, A; Lay, R; Müller, M; Noffz, K H; Pope, B; Schlereth, J L; Werner, P

    2000-01-01

    Low cost SMP (symmetric multi-processor) systems provide substantial CPU and I/O capacity. These features together with the ease of system integration make them an attractive and cost effective solution for a number of real-time applications in event selection. In ATLAS we consider them as intelligent input buffers (an "active" ROB complex), as event flow supervisors or as powerful processing nodes. Measurements of the performance of one off-the-shelf commercial 4- processor PC with two PCI buses, equipped with commercial FPGA based data source cards (microEnable) and running commercial software are presented and mapped on such applications together with a long-term programme of work. The SMP systems may be considered as an important building block in future data acquisition systems. (9 refs).

  7. TRIGGER

    CERN Multimedia

    Wesley Smith

    Trigger Hardware The status of the trigger components was presented during the September CMS Week and Annual Review and at the monthly trigger meetings in October and November. Procedures for cold and warm starts (e.g. refreshing of trigger parameters stored in registers) of the trigger subsystems have been studied. Reviews of parts of the Global Calorimeter Trigger (GCT) and the Global Trigger (GT) have taken place in October and November. The CERN group summarized the status of the Trigger Timing and Control (TTC) system. All TTC crates and boards are installed in the underground counting room, USC55. The central clock system will be upgraded in December (after the Global Run at the end of November GREN) to the new RF2TTC LHC machine interface timing module. Migration of subsystem's TTC PCs to SLC4/ XDAQ 3.12 is being prepared. Work is on going to unify the access to Local Timing Control (LTC) and TTC CMS interface module (TTCci) via SOAP (Simple Object Access Protocol, a lightweight XML-based messaging ...

  8. A compact pre-processor system for the ATLAS level-1 calorimeter trigger

    CERN Document Server

    Pfeiffer, U

    1999-01-01

    This thesis describ es the researc h whose aim is to dev elop a compact Pre-Pro cessor system for the A TLAS Lev el-1 Calorimeter T rigger. Con tributions to the p erformance and the arc hitecture of the Pre-Pro cessor w ere made. A demonstrator Multi-Chip Mo dule (PPrD- MCM) w as dev elop ed and assem bled whic h p erforms most of the prepro cessing of four analogue trigger-to w er signals. The prepro cessing includes digitisation to 8-bit precision, iden ti cation of the corresp onding bunc h-crossing in time (BCID), calibration of the transv erse energy , readout of ra w trigger data, and high-sp eed serial data transmission to the trigger pro cessors. The demonstrator Multi-Chip Mo dule has a size of 15.9 cm 2 and it consists of 9 dies. The MCM w as designed with a smallest feature size of 100 m and it w as fabricated in a laminated MCM-L pro cess o ered b yW urth Elektronik. A Flip-Chip in terconnection ASIC (Finco) w as dev elop ed for the PPrD-MCM and fabricated in a 0.8 m BiCMOS- pro cess o ered b ...

  9. TRIGGER

    CERN Multimedia

    W. Smith

    At the December meeting, the CMS trigger group reported on progress in production, tests in the Electronics Integration Center (EIC) in Prevessin 904, progress on trigger installation in the underground counting room at point 5, USC55, and results from the Magnet Test and Cosmic Challenge (MTCC) phase II. The trigger group is engaged in the final stages of production testing, systems integration, and software and firmware development. Most systems are delivering final tested electronics to CERN. The installation in USC55 is underway and moving towards integration testing. A program of orderly connection and checkout with subsystems and central systems has been developed. This program includes a series of vertical subsystem slice tests providing validation of a portion of each subsystem from front-end electronics through the trigger and DAQ to data captured and stored. This is combined with operations and testing without beam that will continue until startup. The plans for start-up, pilot and early running tri...

  10. Use of fast processors for on line triggering and event filtering

    International Nuclear Information System (INIS)

    Within the framework of 3 SPS experiment we have inserted (or we shall soon be doing so) one or more bit slice microprocessors in order to obtain: an improvement of data quality and time efficiency (software triggering, event filtering, data formatting), more flexibility in adapting to experimental conditions (during development and production). For experiment WA 2 (1976-1978), apart from the control of the multi DMA transfers, analysis by microprogrammes of ADC data, MWPC and TDC multiplicities (times compatible with transfer times from CAMAC to minicomputer) and TDC data formatting has made it possible to reject 70% of events. This in turn allows an efficient on line control and savings of approx. equal to 100 h CDC CPU time. In experiment NA 10 (1980-1981) physics requires an increase in beam intensity by a factor 10. 4 microprocessors working in parallel allows us to concile the readout data flow with the acquisition capacity of the two computers N 10-N 500 due to a factor 10 reduction of the data flow. The use of modular units adapting to the different readout systems (CAMAC, RmH...) and to the experiment (wired operators) permits easy integration. A complete development system (cross-assembler, micro-code compiler, loader) facilitates the updating of software. (orig.)

  11. The ATLAS Muon Trigger

    CERN Document Server

    Ventura, A; The ATLAS collaboration

    2013-01-01

    The ATLAS experiment at CERN's Large Hadron Collider (LHC) deploys a three-levels processing scheme for the trigger system. The Level-1 muon trigger system gets its input from fast muon trigger detectors. Fast sector logic boards select muon candidates, which are passed via an interface board to the central trigger processor and then to the High Level Trigger (HLT). The muon HLT is purely software based and encompasses a Level-2 trigger followed by an event filter for a staged trigger approach. It has access to the data of the precision muon detectors and other detector elements to refine the muon hypothesis. The ATLAS experiment has taken data with high efficiency continuously over entire running periods from 2010 to 2012, for which sophisticated triggers to guard the highest physics output while reducing effectively the event rate were mandatory. The ATLAS muon trigger has successfully adapted to this changing environment. The selection strategy has been optimized for the various physics analyses involving ...

  12. TRIGGER

    CERN Multimedia

    Wesley Smith

    Level-1 Trigger Hardware and Software The hardware of the trigger components has been mostly finished. The ECAL Endcap Trigger Concentrator Cards (TCC) are in production while Barrel TCC firmware has been upgraded, and the Trigger Primitives can now be stored by the Data Concentrator Card for readout by the DAQ. The Regional Calorimeter Trigger (RCT) system is complete, and the timing is being finalized. All 502 HCAL trigger links to RCT run without error. The HCAL muon trigger timing has been equalized with DT, RPC, CSC and ECAL. The hardware and firmware for the Global Calorimeter Trigger (GCT) jet triggers are being commissioned and data from these triggers is available for readout. The GCT energy sums from rings of trigger towers around the beam pipe beam have been changed to include two rings from both sides. The firmware for Drift Tube Track Finder, Barrel Sorter and Wedge Sorter has been upgraded, and the synchronization of the DT trigger is satisfactory. The CSC local trigger has operated flawlessly u...

  13. Prestaciones del Detector Central de Muones del Experimento CMS: las Camaras de Deriva y su Sistema de Trigger (Performance of the Central Muon Detector of the Experiment CMS: the Drift Tube Chambers and its Trigger System)

    CERN Document Server

    Muñoz, Carlos Villanueva

    2007-01-01

    Prestaciones del Detector Central de Muones del Experimento CMS: las Camaras de Deriva y su Sistema de Trigger (Performance of the Central Muon Detector of the Experiment CMS: the Drift Tube Chambers and its Trigger System)

  14. TRIGGER

    CERN Multimedia

    Roberta Arcidiacono

    2013-01-01

    Trigger Studies Group (TSG) The Trigger Studies Group has just concluded its third 2013 workshop, where all POGs presented the improvements to the physics object reconstruction, and all PAGs have shown their plans for Trigger development aimed at the 2015 High Level Trigger (HLT) menu. The Strategy for Trigger Evolution And Monitoring (STEAM) group is responsible for Trigger menu development, path timing, Trigger performance studies coordination, HLT offline DQM as well as HLT release, menu and conditions validation – this last task in collaboration with PdmV (Physics Data and Monte Carlo Validation group). In the last months the group has delivered several HLT rate estimates and comparisons, using the available data and Monte Carlo samples. The studies were presented at the Trigger workshops in September and December, and STEAM has contacted POGs and PAGs to understand the origin of the discrepancies observed between 8 TeV data and Monte Carlo simulations. The most recent results show what the...

  15. TRIGGER

    CERN Multimedia

    Wesley Smith

    Level-1 Trigger Hardware and Software The trigger synchronization procedures for running with cosmic muons and operating with the LHC were reviewed during the May electronics week. Firmware maintenance issues were also reviewed. Link tests between the new ECAL endcap trigger concentrator cards (TCC48) and the Regional Calorimeter Trigger have been performed. Firmware for the energy sum triggers and an upgraded tau trigger of the Global Calorimeter Triggers has been developed and is under test. The optical fiber receiver boards for the Track-Finder trigger theta links of the DT chambers are now all installed. The RPC trigger is being made more robust by additional chamber and cable shielding and also by firmware upgrades. For the CSC’s the front-end and trigger motherboard firmware have been updated. New RPC patterns and DT/CSC lookup tables taking into account phi asymmetries in the magnetic field configuration are under study. The motherboard for the new pipeline synchronizer of the Global Trigg...

  16. TRIGGER

    CERN Multimedia

    W. Smith

    2012-01-01

      Level-1 Trigger The Level-1 Trigger group is ready to deploy improvements to the L1 Trigger algorithms for 2012. These include new high-PT patterns for the RPC endcap, an improved CSC PT assignment, a new PT-matching algorithm for the Global Muon Trigger, and new calibrations for ECAL, HCAL, and the Regional Calorimeter Trigger. These should improve the efficiency, rate, and stability of the L1 Trigger. The L1 Trigger group also is migrating the online systems to SLC5. To make the data transfer from the Global Calorimeter Trigger to the Global Trigger more reliable and also to allow checking the data integrity online, a new optical link system has been developed by the GCT and GT groups and successfully tested at the CMS electronics integration facility in building 904. This new system is now undergoing further tests at Point 5 before being deployed for data-taking this year. New L1 trigger menus have recently been studied and proposed by Emmanuelle Perez and the L1 Detector Performance Group...

  17. TRIGGER

    CERN Multimedia

    by Wesley Smith

    2010-01-01

    Level-1 Trigger Hardware and Software The overall status of the L1 trigger has been excellent and the running efficiency has been high during physics fills. The timing is good to about 1%. The fine-tuning of the time synchronization of muon triggers is ongoing and will be completed after more than 10 nb-1 of data have been recorded. The CSC trigger primitive and RPC trigger timing have been refined. A new configuration for the CSC Track Finder featured modified beam halo cuts and improved ghost cancellation logic. More direct control was provided for the DT opto-receivers. New RPC Cosmic Trigger (RBC/TTU) trigger algorithms were enabled for collision runs. There is further work planned during the next technical stop to investigate a few of the links from the ECAL to the Regional Calorimeter Trigger (RCT). New firmware and a new configuration to handle trigger rate spikes in the ECAL barrel are also being tested. A board newly developed by the tracker group (ReTRI) has been installed and activated to block re...

  18. TRIGGER

    CERN Multimedia

    Wesley Smith

    Level-1 Trigger Hardware and Software The production of the trigger hardware is now basically finished, and in time for the turn-on of the LHC. The last boards produced are the Trigger Concentrator Cards for the ECAL Endcaps (TCC-EE). After the recent installation of the four EE Dees, the TCC-EE prototypes were used for their commissioning. Production boards are arriving and are being tested continuously, with the last ones expected in November. The Regional Calorimeter Trigger hardware is fully integrated after installation of the last EE cables. Pattern tests from the HCAL up to the GCT have been performed successfully. The HCAL triggers are fully operational, including the connection of the HCAL-outer and forward-HCAL (HO/HF) technical triggers to the Global Trigger. The HCAL Trigger and Readout (HTR) board firmware has been updated to permit recording of the tower “feature bit” in the data. The Global Calorimeter Trigger hardware is installed, but some firmware developments are still n...

  19. TRIGGER

    CERN Multimedia

    W. Smith

    2010-01-01

    Level-1 Trigger Hardware and Software The Level-1 Trigger hardware has performed well during both the recent proton-proton and heavy ion running. Efforts were made to improve the visibility and handling of alarms and warnings. The tracker ReTRI boards that prevent fixed frequencies of Level-1 Triggers are now configured through the Trigger Supervisor. The Global Calorimeter Trigger (GCT) team has introduced a buffer cleanup procedure at stops and a reset of the QPLL during configuring to ensure recalibration in case of a switch from the LHC clock to the local clock. A device to test the cables between the Regional Calorimeter Trigger and the GCT has been manufactured. A wrong charge bit was fixed in the CSC Trigger. The ECAL group is improving crystal masking and spike suppression in the trigger primitives. New firmware for the Drift Tube Track Finder (DTTF) sorters was developed to improve fake track tagging and sorting. Zero suppression was implemented in the DT Sector Collector readout. The track finder b...

  20. TRIGGER

    CERN Multimedia

    W. Smith from contributions of C. Leonidopoulos

    2010-01-01

    Level-1 Trigger Hardware and Software Since nearly all of the Level-1 (L1) Trigger hardware at Point 5 has been commissioned, activities during the past months focused on the fine-tuning of synchronization, particularly for the ECAL and the CSC systems, on firmware upgrades and on improving trigger operation and monitoring. Periodic resynchronizations or hard resets and a shortened luminosity section interval of 23 seconds were implemented. For the DT sector collectors, an automatic power-off was installed in case of high temperatures, and the monitoring capabilities of the opto-receivers and the mini-crates were enhanced. The DTTF and the CSCTF now have improved memory lookup tables. The HCAL trigger primitive logic implemented a new algorithm providing better stability of the energy measurement in the presence of any phase misalignment. For the Global Calorimeter Trigger, additional Source Cards have been manufactured and tested. Testing of the new tau, missing ET and missing HT algorithms is underw...

  1. TRIGGER

    CERN Multimedia

    R. Carlin with contributions from D. Acosta

    2012-01-01

    Level-1 Trigger Data-taking continues at cruising speed, with high availability of all components of the Level-1 trigger. We have operated the trigger up to a luminosity of 7.6E33, where we approached 100 kHz using the 7E33 prescale column.  Recently, the pause without triggers in case of an automatic "RESYNC" signal (the "settle" and "recover" time) was reduced in order to minimise the overall dead-time. This may become very important when the LHC comes back with higher energy and luminosity after LS1. We are also preparing for data-taking in the proton-lead run in early 2013. The CASTOR detector will make its comeback into CMS and triggering capabilities are being prepared for this. Steps to be taken include improved cooperation with the TOTEM trigger system and using the LHC clock during the injection and ramp phases of LHC. Studies are being finalised that will have a bearing on the Trigger Technical Design Report (TDR), which is to be rea...

  2. TRIGGER

    CERN Multimedia

    W. Smith

    Level-1 Trigger Hardware and Software The trigger system has been constantly in use in cosmic and commissioning data taking periods. During CRAFT running it delivered 300 million muon and calorimeter triggers to CMS. It has performed stably and reliably. During the abort gaps it has also provided laser and other calibration triggers. Timing issues, namely synchronization and latency issues, have been solved. About half of the Trigger Concentrator Cards for the ECAL Endcap (TCC-EE) are installed, and the firmware is being worked on. The production of the other half has started. The HCAL Trigger and Readout (HTR) card firmware has been updated, and new features such as fast parallel zero-suppression have been included. Repairs of drift tube (DT) trigger mini-crates, optical links and receivers of sector collectors are under way and have been completed on YB0. New firmware for the optical receivers of the theta links to the drift tube track finder is being installed. In parallel, tests with new eta track finde...

  3. TRIGGER

    CERN Multimedia

    Wesley Smith

    Level-1 Trigger Hardware and Software The final parts of the Level-1 trigger hardware are now being put in place. For the ECAL endcaps, more than half of the Trigger Concentrator Cards for the ECAL Endcap (TCC-EE) are now available at CERN, such that one complete endcap can be covered. The Global Trigger now correctly handles ECAL calibration sequences, without being influenced by backpressure. The Regional Calorimeter Trigger (RCT) hardware is complete and working in USC55. Intra-crate tests of all 18 RCT crates and the Global Calorimeter Trigger (GCT) are regularly taking place. Pattern tests have successfully captured data from HCAL through RCT to the GCT Source Cards. HB/HE trigger data are being compared with emulator results to track down the very few remaining hardware problems. The treatment of hot and dead cells, including their recording in the database, has been defined. For the GCT, excellent agreement between the emulator and data has been achieved for jets and HF ET sums. There is still som...

  4. The central trigger control system of the CMS experiment at CERN

    International Nuclear Information System (INIS)

    The Large Hadron Collider will deliver up to 32 million physics collisions per second. This rate is far too high to be processed by present-day computer farms, let alone stored on disk by the experiments for offline analysis. A fast selection of interesting events must therefore be made. In the CMS experiment, this is implemented in two stages: the Level-1 Trigger of the CMS experiment uses custom-made, fast electronics, while the experiment's high-level trigger is implemented in computer farms. The Level-1 Global Trigger electronics has to receive signals from the subdetector systems that enter the trigger (mostly from muon detectors and calorimeters), synchronize them, determine if a pre-set trigger condition is fulfilled, check if the various subsystems are ready to accept triggers based on information from the Trigger Throttling System and on calculations of possible dead-times, and finally distribute the trigger decision ('Level-1 Accept') together with timing signals to the subdetectors over the so-called ''Trigger, Timing and Control'' distribution tree of the experiment. These functions are fulfilled by several specialized, custom-made VME modules, most of which are housed in one crate. The overall control is exerted by the central 'Trigger Control System', which is described in this paper. It consists of one main module and several ancillary boards for input and output functions.

  5. TRIGGER

    CERN Multimedia

    W. Smith

    Level-1 Trigger Hardware and Software The road map for the final commissioning of the level-1 trigger system has been set. The software for the trigger subsystems is being upgraded to run under CERN Scientific Linux 4 (SLC4). There is also a new release for the Trigger Supervisor (TS 1.4), which implies upgrade work by the subsystems. As reported by the CERN group, a campaign to tidy the Trigger Timing and Control (TTC) racks has begun. The machine interface was upgraded by installing the new RF2TTC module, which receives RF signals from LHC Point 4. Two Beam Synchronous Timing (BST) signals, one for each beam, can now be received in CMS. The machine group will define the exact format of the information content shortly. The margin on the locking range of the CMS QPLL is planned for study for different subsystems in the next Global Runs, using a function generator. The TTC software has been successfully tested on SLC4. Some TTC subsystems have already been upgraded to SLC4. The TTCci Trigger Supervisor ...

  6. TRIGGER

    CERN Multimedia

    W. Smith from contributions of C. Leonidopoulos, I. Mikulec, J. Varela and C. Wulz.

    Level-1 Trigger Hardware and Software Over the past few months, the Level-1 trigger has successfully recorded data with cosmic rays over long continuous stretches as well as LHC splash events, beam halo, and collision events. The L1 trigger hardware, firmware, synchronization, performance and readiness for beam operation were reviewed in October. All L1 trigger hardware is now installed at Point 5, and most of it is completely commissioned. While the barrel ECAL Trigger Concentrator Cards are fully operational, the recently delivered endcap ECAL TCC system is still being commissioned. For most systems there is a sufficient number of spares available, but for a few systems additional reserve modules are needed. It was decided to increase the overall L1 latency by three bunch crossings to increase the safety margin for trigger timing adjustments. In order for CMS to continue data taking during LHC frequency ramps, the clock distribution tree needs to be reset. The procedures for this have been tested. A repl...

  7. TRIGGER

    CERN Multimedia

    W. Smith, from contributions of D. Acosta

    2012-01-01

      The L1 Trigger group deployed several major improvements this year. Compared to 2011, the single-muon trigger rate has been reduced by a factor of 2 and the η coverage has been restored to 2.4, with high efficiency. During the current technical stop, a higher jet seed threshold will be applied in the Global Calorimeter Trigger in order to significantly reduce the strong pile-up dependence of the HT and multi-jet triggers. The currently deployed L1 menu, with the “6E33” prescales, has a total rate of less than 100 kHz and operates with detector readout dead time of less than 3% for luminosities up to 6.5 × 1033 cm–2s–1. Further prescale sets have been created for 7 and 8 × 1033 cm–2s–1 luminosities. The L1 DPG is evaluating the performance of the Trigger for upcoming conferences and publication. Progress on the Trigger upgrade was reviewed during the May Upgrade Week. We are investigating scenarios for stagin...

  8. TRIGGER

    CERN Multimedia

    R. Arcidiacono

    2013-01-01

      In 2013 the Trigger Studies Group (TSG) has been restructured in three sub-groups: STEAM, for the development of new HLT menus and monitoring their performance; STORM, for the development of HLT tools, code and actual configurations; and FOG, responsible for the online operations of the High Level Trigger. The Strategy for Trigger Evolution And Monitoring (STEAM) group is responsible for Trigger Menu development, path timing, trigger performance studies coordination, HLT offline DQM as well as HLT release, menu and conditions validation – in collaboration and with the technical support of the PdmV group. Since the end of proton-proton data taking, the group has started preparing for 2015 data taking, with collisions at 13 TeV and 25 ns bunch spacing. The reliability of the extrapolation to higher energy is being evaluated comparing the trigger rates on 7 and 8 TeV Monte Carlo samples with the data taken in the past two years. The effect of 25 ns bunch spacing is being studied on the d...

  9. TRIGGER

    CERN Multimedia

    Wesley Smith

    2011-01-01

    Level-1 Trigger Hardware and Software New Forward Scintillating Counters (FSC) for rapidity gap measurements have been installed and integrated into the Trigger recently. For the Global Muon Trigger, tuning of quality criteria has led to improvements in muon trigger efficiencies. Several subsystems have started campaigns to increase spares by recovering boards or producing new ones. The barrel muon sector collector test system has been reactivated, new η track finder boards are in production, and φ track finder boards are under revision. In the CSC track finder, an η asymmetry problem has been corrected. New pT look-up tables have also improved efficiency. RPC patterns were changed from four out of six coincident layers to three out of six in the barrel, which led to a significant increase in efficiency. A new PAC firmware to trigger on heavy stable charged particles allows looking for chamber hit coincidences in two consecutive bunch-crossings. The redesign of the L1 Trigger Emulator...

  10. TRIGGER

    CERN Multimedia

    by Wesley Smith

    2011-01-01

    Level-1 Trigger Hardware and Software After the winter shutdown minor hardware problems in several subsystems appeared and were corrected. A reassessment of the overall latency has been made. In the TTC system shorter cables between TTCci and TTCex have been installed, which saved one bunch crossing, but which may have required an adjustment of the RPC timing. In order to tackle Pixel out-of-syncs without influencing other subsystems, a special hardware/firmware re-sync protocol has been introduced in the Global Trigger. The link between the Global Calorimeter Trigger and the Global Trigger with the new optical Global Trigger Interface and optical receiver daughterboards has been successfully tested in the Electronics Integration Centre in building 904. New firmware in the GCT now allows a setting to remove the HF towers from energy sums. The HF sleeves have been replaced, which should lead to reduced rates of anomalous signals, which may allow their inclusion after this is validated. For ECAL, improvements i...

  11. TRIGGER

    CERN Multimedia

    J. Alimena

    2013-01-01

    Trigger Strategy Group The Strategy for Trigger Evolution And Monitoring (STEAM) group is responsible for the development of future High-Level Trigger menus, as well as of its DQM and validation, in collaboration and with the technical support of the PdmV group. Taking into account the beam energy and luminosity expected in 2015, a rough estimate of the trigger rates indicates a factor four increase with respect to 2012 conditions. Assuming that a factor two can be tolerated thanks to the increase in offline storage and processing capabilities, a toy menu has been developed using the new OpenHLT workflow to estimate the transverse energy/momentum thresholds that would halve the current trigger rates. The CPU time needed to run the HLT has been compared between data taken with 25 ns and 50 ns bunch spacing, for equivalent pile-up: no significant difference was observed on the global time per event distribution at the only available data point, corresponding to a pile-up of about 10 interactions. Using th...

  12. TRIGGER

    CERN Multimedia

    W. Smith

    2011-01-01

    Level-1 Trigger Hardware and Software Overall the L1 trigger hardware has been running very smoothly during the last months of proton running. Modifications for the heavy-ion run have been made where necessary. The maximal design rate of 100 kHz can be sustained without problems. All L1 latencies have been rechecked. The recently installed Forward Scintillating Counters (FSC) are being used in the heavy ion run. The ZDC scintillators have been dismantled, but the calorimeter itself remains. We now send the L1 accept signal and other control signals to TOTEM. Trigger cables from TOTEM to CMS will be installed during the Christmas shutdown, so that the TOTEM data can be fully integrated within the CMS readout. New beam gas triggers have been developed, since the BSC-based trigger is no longer usable at high luminosities. In particular, a special BPTX signal is used after a quiet period with no collisions. There is an ongoing campaign to provide enough spare modules for the different subsystems. For example...

  13. TRIGGER

    CERN Multimedia

    W. Smith

    Level-1 Trigger Hardware The CERN group is working on the TTC system. Seven out of nine sub-detector TTC VME crates with all fibers cabled are installed in USC55. 17 Local Trigger Controller (LTC) boards have been received from production and are in the process of being tested. The RF2TTC module replacing the TTCmi machine interface has been delivered and will replace the TTCci module used to mimic the LHC clock. 11 out of 12 crates housing the barrel ECAL off-detector electronics have been installed in USC55 after commissioning at the Electronics Integration Centre in building 904. The cabling to the Regional Calorimeter Trigger (RCT) is terminated. The Lisbon group has completed the Synchronization and Link mezzanine board (SLB) production. The Palaiseau group has fully tested and installed 33 out of 40 Trigger Concentrator Cards (TCC). The seven remaining boards are being remade. The barrel TCC boards have been tested at the H4 test beam, and good agreement with emulator predictions were found. The cons...

  14. Improvement in the CDF L2 electron trigger using the central shower max detector

    International Nuclear Information System (INIS)

    As part of a trigger upgrade for CDF run 1b, new electronics will bring the central shower max detector (CES) into the open-quote level-2 close-quote trigger algorithm. This upgrade will allow the trigger to select electrons within a finer segmentation in the r - φ view. This will be achieved by requiring a pulse height in the shower max detector be associated with a projected track from the central fast tracker to within 2 degrees. In CDF run la, the track was only required to point to the same 15 degree wedge as the electron electromagnetic cluster. This tighter matching will decrease the open-quote level-2 close-quote electron cross section by about a factor 2, while maintaining the electron purity

  15. Implementation of the shower max electron trigger at CDF

    International Nuclear Information System (INIS)

    The authors have built and installed new electronics which brings the central shower max detector into the CDF Level-2 trigger. By matching a stiff track from the central fast track processor to an associated shower max cluster, this trigger improvement reduces the electron Level-2 cross section by approximately 50% while retaining greater than 85% of real electrons and allows the authors to lower their electron trigger threshold

  16. The ATLAS Level-1 Topological Trigger Performance

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00371751; The ATLAS collaboration

    2016-01-01

    The LHC will collide protons in the ATLAS detector with increasing luminosity through 2016, placing stringent operational and physical requirements to the ATLAS trigger system in order to reduce the 40 MHz collision rate to a manageable event storage rate of 1 kHz, while not rejecting interesting physics events. The Level-1 trigger is the first rate-reducing step in the ATLAS trigger system with an output rate of 100 kHz and decision latency smaller than 2.5 μs. It consists of a calorimeter trigger, muon trigger and a central trigger processor. During the LHC shutdown after the Run 1 finished in 2013, the Level-1 trigger system was upgraded including hardware, firmware and software updates. In particular, new electronics modules were introduced in the real-time data processing path: the Topological Processor System (L1Topo). It consists of a single AdvancedCTA shelf equipped with two Level-1 topological processor blades. They receive real-time information from the Level-1 calorimeter and muon triggers, which...

  17. Poor vigilance affects attentional orienting triggered by central uninformative gaze and arrow cues.

    Science.gov (United States)

    Marotta, Andrea; Martella, Diana; Maccari, Lisa; Sebastiani, Mara; Casagrande, Maria

    2014-11-01

    Behaviour and neuroimaging studies have shown that poor vigilance (PV) due to sleep deprivation (SD) negatively affects exogenously cued selective attention. In the current study, we assessed the impact of PV due to both partial SD and night-time hours on reflexive attentional orienting triggered by central un-informative eye-gaze and arrow cues. Subjective mood and interference performance in emotional Stroop task were also investigated. Twenty healthy participants performed spatial cueing tasks using central directional arrow and eye-gaze as a cue to orient attention. The target was a word written in different coloured inks. The participant's task was to identify the colour of the ink while ignoring the semantic content of the word (with negative or neutral emotional valence). The experiment took place on 2 days. On the first day, each participant performed a 10-min training session of the spatial cueing task. On the second day, half of participants performed the task once at 4:30 p.m. (BSL) and once at 6:30 a.m. (PV), whereas the other half performed the task in the reversed order. Results showed that mean reaction times on the spatial cueing tasks were worsened by PV, although gaze paradigm was more resistant to this effect as compared to the arrow paradigm. Moreover, PV negatively affects attentional orienting triggered by both central un-informative gaze and arrow cues. Finally, prolonged wakefulness affects self-reported mood but does not influence interference control in emotional Stroop task. PMID:24718933

  18. Triggering the D0 experiment

    International Nuclear Information System (INIS)

    The D0 event selection consists of 3 levels of hardware trigger and one level of software trigger. Events passing the hardware trigger are read out to filtering processors, where the event is assembled in the multiported memory of the processor. Our trigger simulation runs from the same configuration files which specify the hardware and software trigger online. We outline the design and performance (rejection, efficiency, and throughput) of the trigger system for muons, electrons, photons, jets, and missing pT

  19. Trigger strategies for central exclusive $H \\to b\\overline{b}$ studies with the AFP detector

    CERN Document Server

    Brown, G J A; Kupco, A; Pilkington, A; Tasevsky, M

    2009-01-01

    The ATLAS Forward Proton (AFP) upgrade proposes to install proton detectors at 220 m and 420 m either side of the ATLAS interaction point, turning the LHC into a giant magnetic spectrometer. The physics motivation for this upgrade focuses on final states in which the colliding protons remain intact, allowing a full reconstruction of the event, even in the forward region. One such process is the production of the Higgs boson in the central exclusive channel and tagging the outgoing protons allows the possible extraction of the Higgs quantum numbers, mass and couplings regardless of the decay channel. Studying this exclusive production channel for the presently favoured low Higgs mass depends on the possibility of efficiently triggering, up to the highest luminosities, on a pair of relatively soft jets coming from the decay of b quarks or τ leptons. As jet triggers will inevitably be heavily pre-scaled, even at modest luminosities, it is essential to make a coincidence betweeen information from the tagging d...

  20. Modular formal analysis of the central guardian in the Time-Triggered Architecture

    International Nuclear Information System (INIS)

    The Time-Triggered Protocol TTP/C constitutes the core of the communication level of the Time-Triggered Architecture for dependable real-time systems. TTP/C ensures consistent data distribution, even in the presence of faults occurring to nodes or the communication channel. However, the protocol mechanisms of TTP/C rely on a rather optimistic fault hypothesis. Therefore, an independent component, the central guardian, employs static knowledge about the system to transform arbitrary node failures into failure modes that are covered by the fault hypothesis. This paper presents a modular formal analysis of the communication properties of TTP/C based on the guardian approach. Through a hierarchy of formal models, we give a precise description of the arguments that support the desired correctness properties of TTP/C. First, requirements for correct communication are expressed on an abstract level. By stepwise refinement we show both that these abstract requirements are met under the optimistic fault hypothesis, and how the guardian model allows a broader class of node failures to be tolerated. The models have been developed and mechanically checked using the specification and verification system PVS

  1. Angiotensin II-triggered kinase signaling cascade in the central nervous system.

    Science.gov (United States)

    Bali, Anjana; Jaggi, Amteshwar Singh

    2016-04-01

    Recent studies have projected the renin-angiotensin system as a central component of the physiological and pathological processes of assorted neurological disorders. Its primary effector hormone, angiotensin II (Ang II), not only mediates the physiological effects of vasoconstriction and blood pressure regulation in cardiovascular disease but is also implicated in a much wider range of neuronal activities and diseases, including Alzheimer's disease, neuronal injury, and cognitive disorders. Ang II produces different actions by acting on its two subtypes of receptors (AT1 and AT2); however, the well-known physiological actions of Ang II are mainly mediated through AT1 receptors. Moreover, recent studies also suggest the important functional role of AT2 receptor in the brain. Ang II acts on AT1 receptors and conducts its functions via MAP kinases (ERK1/2, JNK, and p38MAPK), glycogen synthase kinase, Rho/ROCK kinase, receptor tyrosine kinases (PDGF and EGFR), and nonreceptor tyrosine kinases (Src, Pyk2, and JAK/STAT). AT1R-mediated NADPH oxidase activation also leads to the generation of reactive oxygen species, widely implicated in neuroinflammation. These signaling cascades lead to glutamate excitotoxicity, apoptosis, cerebral infarction, astrocyte proliferation, nociception, neuroinflammation, and progression of other neurological disorders. The present review focuses on the Ang II-triggered signal transduction pathways in central nervous system. PMID:26574890

  2. Level-1 Calorimeter Trigger starts firing

    CERN Multimedia

    Stephen Hillier

    2007-01-01

    L1Calo is one of the major components of ATLAS First Level trigger, along with the Muon Trigger and Central Trigger Processor. It forms all of the first-level calorimeter-based triggers, including electron, jet, tau and missing ET. The final system consists of over 250 custom designed 9U VME boards, most containing a dense array of FPGAs or ASICs. It is subdivided into a PreProcessor, which digitises the incoming trigger signals from the Liquid Argon and Tile calorimeters, and two separate processor systems, which perform the physics algorithms. All of these are highly flexible, allowing the possibility to adapt to beam conditions and luminosity. All parts of the system are read out through Read-Out Drivers, which provide monitoring data and Region of Interest (RoI) information for the Level-2 trigger. Production of the modules is now essentially complete, and enough modules exist to populate the full scale system in USA15. Installation is proceeding rapidly - approximately 90% of the final modules are insta...

  3. Beam Test of the ATLAS Level-1 Calorimeter Trigger System

    CERN Document Server

    Garvey, J; Mahout, G; Moye, T H; Staley, R J; Thomas, J P; Typaldos, D; Watkins, P M; Watson, A; Achenbach, R; Föhlisch, F; Geweniger, C; Hanke, P; Kluge, E E; Mahboubi, K; Meier, K; Meshkov, P; Rühr, F; Schmitt, K; Schultz-Coulon, H C; Ay, C; Bauss, B; Belkin, A; Rieke, S; Schäfer, U; Tapprogge, T; Trefzger, T; Weber, GA; Eisenhandler, E F; Landon, M; Apostologlou, P; Barnett, B M; Brawn, I P; Davis, A O; Edwards, J; Gee, C N P; Gillman, A R; Mirea, A; Perera, V J O; Qian, W; Sankey, D P C; Bohm, C; Hellman, S; Hidvegi, A; Silverstein, S

    2005-01-01

    The Level-1 Calorimter Trigger consists of a Preprocessor (PP), a Cluster Processor (CP), and a Jet/Energy-sum Processor (JEP). The CP and JEP receive digitised trigger-tower data from the Preprocessor and produce Region-of-Interest (RoIs) and trigger multiplicities. The latter are sent in real time to the Central Trigger Processor (CTP) where the Level-1 decision is made. On receipt of a Level-1 Accept, Readout Driver Modules (RODs), provide intermediate results to the data acquisition (DAQ) system for monitoring and diagnostic purpose. RoI information is sent to the RoI builder (RoIB) to help reduce the amount of data required for the Level-2 Trigger The Level-1 Calorimeter Trigger System at the test beam consisted of 1 Preprocessor module, 1 Cluster Processor Module, 1 Jet/Energy Module and 2 Common Merger Modules. Calorimeter energies were sucessfully handled thourghout the chain and trigger object sent to the CTP. Level-1 Accepts were sucessfully produced and used to drive the readout path. Online diagno...

  4. Physics performances with the new ATLAS Level-1 Topological trigger in Run 2

    CERN Document Server

    Artz, Sebastian; The ATLAS collaboration

    2016-01-01

    The ATLAS trigger system aims at reducing the 40 MHz proton-proton collision event rate to a manageable event storage rate of 1 kHz, preserving events valuable for physics analysis. The Level-1 trigger is the first rate-reducing step in the ATLAS trigger system, with an output rate of 100 kHz and decision latency of less than 2.5 micro seconds. It is composed of the calorimeter trigger, muon trigger and central trigger processor. During the last upgrade, a new electronics element was introduced to Level-1: The Topological Processor System. It will make it possible to use detailed realtime information from the Level-1 calorimeter and muon triggers, processed in individual state of the art FPGA processors to determine angles between jets and/or leptons and calculate kinematic variables based on lists of selected/sorted objects. More than one hundred VHDL algorithms are producing trigger outputs to be incorporated into the central trigger processor. This information will be essential to improve background reject...

  5. ATLAS Muon Trigger

    CERN Document Server

    Woudstra, MJ; The ATLAS collaboration

    2013-01-01

    CERN’s Large Hadron Collider (LHC) is the highest energy proton-proton collider, providing also the highest instantaneous luminosity as a hadron collider. Bunch crossings occurred every 50 ns in 2012 runs. Amongst of which the online event selection system should reduce the event recording rate down to a few 100 Hz, while events are in a harsh condition with many overlapping proton-proton collisions occurring in a same bunch crossing. Muons often provide an important and clear signature of physics processes that are searched for, for instance as in the discovery of Higgs particle in year 2012. The ATLAS experiment deploys a three-levels processing scheme at online. The level-1 muon trigger system gets its input from fast muon trigger detectors. Fast sector logic boards select muon candidates, which are passed via an interface board to the central trigger processor and then to the High Level Trigger (HLT). The muon HLT is purely software based and encompasses a level-2 (L2) trigger followed by an event filte...

  6. Alpine debris flows triggered by a 28 July 1999 thunderstorm in the central Front Range, Colorado

    Science.gov (United States)

    Godt, J.W.; Coe, J.A.

    2007-01-01

    On 28 July 1999, about 480 alpine debris flows were triggered by an afternoon thunderstorm along the Continental Divide in Clear Creek and Summit counties in the central Front Range of Colorado. The thunderstorm produced about 43??mm of rain in 4??h, 35??mm of which fell in the first 2??h. Several debris flows triggered by the storm impacted Interstate Highway 70, U.S. Highway 6, and the Arapahoe Basin ski area. We mapped the debris flows from color aerial photography and inspected many of them in the field. Three processes initiated debris flows. The first process initiated 11% of the debris flows and involved the mobilization of shallow landslides in thick, often well vegetated, colluvium. The second process, which was responsible for 79% of the flows, was the transport of material eroded from steep unvegetated hillslopes via a system of coalescing rills. The third, which has been termed the "firehose effect," initiated 10% of the debris flows and occurred where overland flow became concentrated in steep bedrock channels and scoured debris from talus deposits and the heads of debris fans. These three processes initiated high on steep hillsides (> 30??) in catchments with small contributing areas (< 8000??m2), however, shallow landslides occurred on slopes that were significantly less steep than either overland flow process. Based on field observations and examination of soils mapping of the northern part of the study area, we identified a relation between the degree of soil development and the process type that generated debris flows. In general, areas with greater soil development were less likely to generate runoff and therefore less likely to generate debris flows by the firehose effect or by rilling. The character of the surficial cover and the spatially variable hydrologic response to intense rainfall, rather than a threshold of contributing area and topographic slope, appears to control the initiation process in the high alpine of the Front Range. Because

  7. Intense interface seismicity triggered by a shallow slow slip event in the Central Ecuador subduction zone

    Science.gov (United States)

    ValléE, Martin; Nocquet, Jean-Mathieu; Battaglia, Jean; Font, Yvonne; Segovia, Monica; RéGnier, Marc; Mothes, Patricia; Jarrin, Paul; Cisneros, David; Vaca, Sandro; Yepes, Hugo; Martin, Xavier; BéThoux, Nicole; Chlieh, Mohamed

    2013-06-01

    document a 1 week long slow slip event (SSE) with an equivalent moment magnitude of 6.0-6.3 which occurred in August 2010 below La Plata Island (Ecuador), south of the rupture area of the 1906 Mw = 8.8 megathrust earthquake. GPS data reveal that the SSE occurred at a depth of about 10 km, within the downdip part of a shallow (earthquakes detected, among which 50 have a moment magnitude between 1.8 and 4.1. However, the cumulative moment released through earthquakes accounts, at most, for 0.2% of the total moment release estimated from GPS displacements. Most of the largest earthquakes are located along or very close to the subduction interface with focal mechanism consistent with the relative plate motion. While the earthquake sizes show a classical distribution (Gutenberg-Richter law with a b-value close to 1), the space-time occurrence presents a specific pattern. First, the largest earthquakes appear to occur randomly during the slow slip sequence, which further evidence that the seismicity is driven by the stress fluctuations related to aseismic slip. Moreover, the seismicity observed during the SSE consists in individual events and families of repeating earthquakes. These observations indicate that the stress increment induced by the episodic aseismic slip may lead both to sudden seismic moment release and to progressive rupture within small locked patches. This study offers an a posteriori interpretation of the seismogenesis in the Central Ecuador subduction zone, where intense seismic swarms have been regularly observed (1977, 1998, 2002, and 2005). These swarms have likely been triggered by large-magnitude slow slip events.

  8. FORMULATION AND OPTIMIZATION OF OSMOTICALLY CONTROLLED, MICROBIALLY TRIGGERED COLON TARGETED SYSTEM USING FACE CENTERED CENTRAL COMPOSITE DESIGN

    OpenAIRE

    Rajesh Saini et al

    2012-01-01

    The purpose of present investigation was to achieve successful delivery especially to colon using microbially triggered, osmotically controlled approach. Prednisolone was chosen model drug for treatment of inflammatory bowel disease (IBD). Prednisolone-β-cyclodextrin complex were prepared and phase solubility study was carried out. Cellulose acetate solution containing chitosan was used to prepare semi-permeable. Face centered central composite design was employed to study the effect on indep...

  9. ATLAS Trigger: design and commissioning

    CERN Document Server

    Pastore, F; The ATLAS collaboration

    2009-01-01

    The ATLAS detector at CERN's Large Hadron Collider (LHC) will be exposed to proton-proton collisions from beams crossing at 40 MHz. A three-level trigger system was designed to select potentially interesting events and reduce the incoming rate to 100-200 Hz. The first trigger level (LVL1) is implemented in custom-built electronics, the second and third trigger levels are realised in software. Based on calorimeter information and hits in dedicated muon-trigger detectors, the LVL1 decision is made by the central-trigger processor yielding an output rate of less than 100 kHz. The allowed latency for the trigger decision at this stage is less than 2.5 micro seconds. The two subsequent levels, called, High-Level Trigger (HLT) further reduce the rate to the offline storage rate while retaining the most interesting physics. The HLT is implemented in software running in commercially available computer farms and consists of Level 2 and Event Filter. To reduce the network data traffic and the processing time to managea...

  10. Physics performances with the new ATLAS Level-1 Topological trigger in the LHC High-Luminosity Era

    CERN Document Server

    Artz, Sebastian; The ATLAS collaboration

    2016-01-01

    The ATLAS trigger system aim at reducing the 40 MHz protons collision event rate to a manageable event storage rate of 1 kHz, preserving events with valuable physics meaning. The Level-1 trigger is the first rate-reducing step in the ATLAS trigger system, with an output rate of 100 kHz and decision latency of less than 2.5 micro seconds. It is composed of the calorimeter trigger, muon trigger and central trigger processor. During the last upgrade, a new electronics element was introduced to Level-1: L1Topo, the Topological Processor System. It will make it possible to use detailed realtime information from the Level-1 calorimeter and muon triggers, processed in individual state of the art FPGA processors to determine angles between jets and/or leptons and calculate kinematic variables based on lists of selected/sorted objects. Over hundred VHDL algorithms are producing trigger outputs to be incorporated into the central trigger processor. Such information will be essential to improve background rejection and ...

  11. The NA62 trigger system

    International Nuclear Information System (INIS)

    The main aim of the NA62 experiment (NA62 Technical Design Report, 〈http://na62.web.cern.ch/NA62/Documents/TDFulldocv1.pdf〉 [1]) is to study ultra-rare Kaon decays. In order to select rare events over the overwhelming background, central systems with high-performance, high bandwidth, flexibility and configurability are necessary, that minimize dead time while maximizing data collection reliability. The NA62 experiment consists of 12 sub-detector systems and several trigger and control systems, for a total channel count of less than 100,000. The GigaTracKer (GTK) has the largest number of channels (54,000), and the Liquid Krypton (LKr) calorimeter shares with it the largest raw data rate (19 GB/s). The NA62 trigger system works with 3 trigger levels. The first trigger level is based on a hardware central trigger unit, so-called L0 Trigger Processor (L0TP), and Local Trigger Units (LTU), which are all located in the experimental cavern. Other two trigger levels are based on software, and done with a computer farm located on surface. The L0TP receives information from triggering sub-detectors asynchronously via Ethernet; it processes the information, and then transmits a final trigger decision synchronously to each sub-detector through the Trigger and Timing Control (TTC) system. The interface between L0TP and the TTC system, which is used for trigger and clock distribution, is provided by the Local Trigger Unit board (LTU). The LTU can work in two modes: global and stand-alone. In the global mode, the LTU provides an interface between L0TP and TTC system. In the stand-alone mode, the LTU can fully emulate L0TP and so provides an independent way for each sub-detector for testing or calibration purposes. In addition to the emulation functionality, a further functionality is implemented that allows to synchronize the clock of the LTU with the L0TP and the TTC system. For testing and debugging purposes, a Snap Shot Memory (SSM) interface is implemented, that can work

  12. A second level trigger system based on a microprocessor array

    Energy Technology Data Exchange (ETDEWEB)

    Sakamoto, H.; Watase, Y. (National Laboratory for High Energy Physics, KEK, 1-1 Oho, Tsukuba, Ibaraki 305 (Japan)); Korhonen, T. (Department of High Energy Physics, Helsinki University, Siltavuorenpenger 20 D, 00170 Helsinki (Finland)); Taketani, A. (Department of Physics, Hiroshima University, Higashi-senda-machi, Naka-ku, Hiroshima 730 (Japan))

    1990-08-01

    A second level trigger system is being introduced to the KEK TRISTAN VENUS experiment. The system consists of a TRANSPUTER array of 2-dimensional lattice and several kinds of interfacing modulus. TRANSPUTER chips are mounted on these modules. Trigger data are all transferred using high speed serial links which connect the processors. The system is applied to the central drift chamber to perform track finding using its hit information. A data acquistion module attached to each FASTBUS crate gathers the hit wire pattern and transfers it to the processor array through its link. Track finding is performed in parallel form by sharing the data. The results is also transferred to a master FPI (FASTBUS Processor Interface) via a link. It takes less than 1 millisecond to distribute pattern data into the array and fast tracking less than 8 milliseconds was achieved.

  13. The ATLAS Muon Trigger - Experience and Performance in the first 3 years of LHC pp runs

    CERN Document Server

    Ventura, A; The ATLAS collaboration

    2013-01-01

    The ATLAS experiment at CERN's Large Hadron Collider (LHC) deploys three-levels processing scheme for the trigger system. The level-1 muon trigger system gets its input from fast muon trigger detectors. Fast sector logic boards select muon candidates, which are passed via an interface board to the central trigger processor and then to the High Level Trigger (HLT). The muon HLT is purely software based and encompasses a level-2 trigger followed by an event filter for a staged trigger approach. It has access to the data of the precision muon detectors and other detector elements to refine the muon hypothesis. The ATLAS experiment has taken data with high efficiency continuously over entire running periods form 2010 to 2012, for which sophisticated triggers to guard the highest physics output while reducing effectively the event rate were mandatory. The ATLAS Muon trigger has successfully adapted to this changing environment. The selection strategy has been optimized for the various physics analysis involving mu...

  14. The ATLAS Muon and Tau Trigger

    CERN Document Server

    Dell'Asta, L; The ATLAS collaboration

    2013-01-01

    [Muon] The ATLAS experiment at CERN's Large Hadron Collider (LHC) deploys a three-levels processing scheme for the trigger system. The level-1 muon trigger system gets its input from fast muon trigger detectors. Fast sector logic boards select muon candidates, which are passed via an interface board to the central trigger processor and then to the High Level Trigger (HLT). The muon HLT is purely software based and encompasses a level-2 (L2) trigger followed by an event filter (EF) for a staged trigger approach. It has access to the data of the precision muon detectors and other detector elements to refine the muon hypothesis. Trigger-specific algorithms were developed and are used for the L2 to increase processing speed for instance by making use of look-up tables and simpler algorithms, while the EF muon triggers mostly benefit from offline reconstruction software to obtain most precise determination of the track parameters. There are two algorithms with different approaches, namely inside-out and outside-in...

  15. Stimulation of the Basal and Central Amygdala in the Mustached Bat Triggers Echolocation and Agonistic Vocalizations within Multimodal Output

    Directory of Open Access Journals (Sweden)

    JagmeetSKanwal

    2014-03-01

    Full Text Available The neural substrate for the perception of vocalization is relatively well described, but we know much less about how the timing and specificity of vocalizations is tightly coupled with audiovocal communication behavior. In many vocal species, well-timed vocalizations accompany fear, vigilance and aggression. These emotive responses likely originate within the amygdala and other limbic structures, but the organization of motor outputs for triggering species-appropriate behaviors remains unclear. We performed electrical microstimulation at 461 highly restricted loci within the basal and central amygdala in awake mustached bats. At a subset of these sites, high frequency stimulation with weak constant current pulses presented at near-threshold levels triggered vocalization of either echolocation pulses or social calls. At the vast majority of locations, microstimulation produced a constellation of changes in autonomic and somatomotor outputs. These changes included widespread co-activation of significant tachycardia and hyperventilation and/or rhythmic ear pinna movements. In a few locations, responses were constrained to vocalization and/or pinna movements despite increases in the intensity of stimulation. The probability of eliciting echolocation pulses versus social calls decreased in a medial-posterior to anterolateral direction within the centrobasal amygdala. Microinjections of kainic acid at stimulation sites confirmed the contribution of cellular activity rather than fibers-of-passage in the control of multimodal outputs. The results suggest that multimodal clusters of neurons may simultaneously modulate the activity of multiple central pattern generators present within the brainstem.

  16. Proceedings of the workshop on triggering and data acquisition for experiments at the Supercollider

    Energy Technology Data Exchange (ETDEWEB)

    Donaldson, R. [ed.

    1989-04-01

    This meeting covered the following subjects: triggering requirements for SSC physics; CDF level 3 trigger; D0 trigger design; AMY trigger systems; Zeus calorimeter first level trigger; data acquisition for the Zeus Central Tracking Detector; trigger and data acquisition aspects for SSC tracking; data acquisition systems for the SSC; validating triggers in CDF level 3; optical data transmission at SSC; time measurement system at SSC; SSC/BCD data acquisition system; microprocessors and other processors for triggering and filtering at the SSC; data acquisition, event building, and on-line processing; LAA real-time benchmarks; object-oriented system building at SSC; and software and project management. Selected papers are indexed separately for inclusion in the Energy Science and Technology Database.

  17. Non-triggered quantification of central and peripheral pulse-wave velocity

    Directory of Open Access Journals (Sweden)

    Langham Michael C

    2011-12-01

    Full Text Available Abstract Purpose Stiffening of the arteries results in increased pulse-wave velocity (PWV, the propagation velocity of the blood. Elevated aortic PWV has been shown to correlate with aging and atherosclerotic alterations. We extended a previous non-triggered projection-based cardiovascular MR method and demonstrate its feasibility by mapping the PWV of the aortic arch, thoraco-abdominal aorta and iliofemoral arteries in a cohort of healthy adults. Materials and Methods The proposed method "simultaneously" excites and collects a series of velocity-encoded projections at two arterial segments to estimate the wave-front velocity, which inherently probes the high-frequency component of the dynamic vessel wall modulus in response to oscillatory pressure waves. The regional PWVs were quantified in a small pilot study in healthy subjects (N = 10, age range 23 to 68 yrs at 3T. Results The projection-based method successfully time-resolved regional PWVs for 8-10 cardiac cycles without gating and demonstrated the feasibility of monitoring beat-to-beat changes in PWV resulting from heart rate irregularities. For dul-slice excitation the aliasing was negligible and did not interfere with PWV quantification. The aortic arch and thoracoabdominal aorta PWV were positively correlated with age (p Conclusion The PWV map of the arterial tree from ascending aorta to femoral arteries may provide additional insight into pathophysiology of vascular aging and atherosclerosis.

  18. XOP: a second generation fast processor for on-line use in high energy physics experiments

    CERN Document Server

    Lingjaerde, Tor

    1981-01-01

    Processors for trigger calculations and data compression in high energy physics are characterized by a high data input capability combined with fast execution of relatively simple routines. In order to achieve the required performance it is advantageous to replace the classical computer instruction-set by microcoded instructions, the various fields of which control the internal subunits in parallel. The fast processor called ESOP is based on such a principle: the different operations are handled step by step by dedicated optimized modules under control of a central instruction unit. Thus, the arithmetic operations, address calculations, conditional checking, loop counts and next instruction evaluation all overlap in time. Based upon the experience from ESOP the architecture of a new processor "XOP" is beginning to take shape which will be faster and easier to use. In this context the most important innovations are: easy handling of operands in the arithmetic unit by means of three data buses and large data fi...

  19. System architecture and hardware design of the CDF XFT online track processor

    International Nuclear Information System (INIS)

    A trigger track processor is being designed for CDF Run 2. This processor identifies high momentum (PT > 1.5 GeV/c) charged tracks in the new central outer tracking chamber for the CDF II detector. The design of the track processor, called the eXtremely Fast Tracker (XFT), is highly parallel and handle an input rate of 183 Gbits/sec and output rate of 44 Gbits/sec. The XFT is pipelined and reports the results for a new event every 132ns. The XFT uses three stages, hit classification, segment finding, and segment linking. The pattern recognition algorithms for the three stages are implemented in Programmable Logic Devices (PLDs) which allow for in-situ modification of the algorithm at any time. The PLDs reside on three different types of modules. Prototypes of each of these modules have been designed and built, and are working. An overview of the hardware design and the system architecture are presented

  20. Central anticholinergic syndrome vs. idiosyncratic reaction triggered by a small IV dose of atropine.

    Science.gov (United States)

    Cao, X; Cui, Y; White, P F; Tang, J; Ma, H

    2016-02-01

    A 58-year-old male was scheduled to undergo radical gastrectomy for cancer under general anesthesia. The patient developed agitation and irregular breathing after receiving a single dose of atropine (0.5 mg) to treat bradycardia immediately prior to induction of anesthesia. Within 5 min after the atropine injection, the patient became unresponsive with facial flushing and diaphoresis. When a drop in oxygen saturation was observed, a laryngeal mask airway was inserted after administering a small bolus dose of propofol (80 mg) and the patient was ventilated with 100% oxygen. Physostigmine was not administered because of the relatively low dose of atropine and the fact that his symptoms were not totally consistent with central anticholinergic syndrome (CAS). The differential diagnosis at the time also included an acute cardiovascular event and an idiosyncratic reaction to atropine. The patient fully recovered within 80 min from this highly unusual reaction to a single 0.5 mg IV dose of atropine. PMID:26471203

  1. Trigger processing using reconfigurable logic in the CMS calorimeter trigger

    CERN Document Server

    Brooke, J J; Heath, G P; Maddox, A J; Newbold, D; Rabbetts, P D

    2001-01-01

    We present the design of the Global Calorimeter Trigger processor for the CMS detector at LHC. This is a fully pipelined processor system which collects data from all the CMS calorimeters and produces summary information used in forming the Level-1 trigger decision for each event. The design in based on the use of state-of-the-art reconfigurable logic devices (FPGAs) and fast data links. We present the results of device testing using a low-latency pipelined sort algorithm, which demonstrate that an FPGA can be used to perform processing previously foreseen to require custom ASICs. Our design approach results in a powerful, flexible and compact processor system. (0 refs).

  2. FORMULATION AND OPTIMIZATION OF OSMOTICALLY CONTROLLED, MICROBIALLY TRIGGERED COLON TARGETED SYSTEM USING FACE CENTERED CENTRAL COMPOSITE DESIGN

    Directory of Open Access Journals (Sweden)

    Rajesh Saini et al

    2012-09-01

    Full Text Available The purpose of present investigation was to achieve successful delivery especially to colon using microbially triggered, osmotically controlled approach. Prednisolone was chosen model drug for treatment of inflammatory bowel disease (IBD. Prednisolone-β-cyclodextrin complex were prepared and phase solubility study was carried out. Cellulose acetate solution containing chitosan was used to prepare semi-permeable. Face centered central composite design was employed to study the effect on independent variables (concentration of sodium chloride, polyethylene glycol, and chitosan, % cumulative release and disintegration time. Both independent variables, the proportion of chitosan (X1 and proportion of NaCl and PEG (X2 had an influence on the % drug release in both the media (buffers and buffer with rat ceacal content. Formulations were evaluated for their Preformulation parameters and found within the specified limit. Formulation code F8 and S8 were the optimized batches with an in vitro release of 83.77 and 99.13 % respectively. The formulations containing PEG was found to be a promising drug delivery system better release kinetics.

  3. Upgrade of the ATLAS Level-1 Trigger with event topology information

    Science.gov (United States)

    Simioni, E.; Artz, S.; Bauβ, B.; Büscher, V.; Jakobi, K.; Kaluza, A.; Kahra, C.; Palka, M.; Reiβ, A.; Schäffer, J.; Schäfer, U.; Schulte, A.; Simon, M.; Tapprogge, S.; Vogel, A.; Zinser, M.

    2015-12-01

    The Large Hadron Collider (LHC) in 2015 will collide proton beams with increased luminosity from 1034 up to 3 × 1034cm-2s-1. ATLAS is an LHC experiment designed to measure decay properties of high energetic particles produced in the protons collisions. The higher luminosity places stringent operational and physical requirements on the ATLAS Trigger in order to reduce the 40MHz collision rate to a manageable event storage rate of 1kHz while at the same time, selecting those events with valuable physics meaning. The Level-1 Trigger is the first rate-reducing step in the ATLAS Trigger, with an output rate of 100kHz and decision latency of less than 2.5µs. It is composed of the Calorimeter Trigger (L1Calo), the Muon Trigger (L1Muon) and the Central Trigger Processor (CTP). By 2015, there will be a new electronics element in the chain: the Topological Processor System (L1Topo system). The L1Topo system consist of a single AdvancedTCA shelf equipped with three L1Topo processor blades. It will make it possible to use detailed information from L1Calo and L1Muon processed in individual state-of-the-art FPGA processors. This allows the determination of angles between jets and/or leptons and calculates kinematic variables based on lists of selected/sorted objects. The system is designed to receive and process up to 6Tb/s of real time data. The paper reports the relevant upgrades of the Level-1 trigger with focus on the topological processor design and commissioning.

  4. Intense interface seismicity triggered by a shallow slow-slip event in the Central-Ecuador subduction zone

    Science.gov (United States)

    Vallee, M.; Nocquet, J.; Battaglia, J.; Font, Y.; Segovia, M.; Regnier, M. M.; Mothes, P. A.; Jarrín, P.; Cisneros, D.; Vaca, S.; Yepes, H. A.; Martin, X.; Béthoux, N.; Chlieh, M.

    2013-12-01

    Slow slip events (SSE) are more often associated with non-volcanic tremors than with classical earthquakes. We document here a deformation episode where an abundant seismicity has been triggered by an SSE. In August 2010, a one week long slow-slip event (SSE) with an equivalent moment magnitude of 6.0-6.3 occurred below La Plata Island (Ecuador), south of the rupture area of the Mw=8.8 1906 megathrust earthquake. GPS data reveal that the SSE occurred at a depth of about 10km, within the downdip part of a shallow (earthquakes detected, among which 50 have a moment magnitude between 1.8 and 4.1. However, the cumulative moment released through earthquakes accounts at most for 0.2% of the total moment release estimated from GPS displacements. Most of the largest earthquakes are located along or very close to the subduction interface with focal mechanism consistent with the relative plate motion. These largest events appear to occur randomly during the slow slip sequence, which further evidence that the seismicity is driven by the stress fluctuations related to aseismic slip. A large part of the seismic events observed during the SSE is organized into families of repeating earthquakes, which may indicate a progressive rupture within small locked patches. Recent observations show that this zone of the subduction is prone to SSEs, as evidenced by a new SSE observed in January 2013. These findings offer an a posteriori interpretation of the seismogenesis in the Central-Ecuador subduction zone, where intense seismic swarms have been regularly observed (1977, 1998, 2002, 2005). These swarms have likely been triggered by large magnitude slow-slip events. Joint observations of the geodetic displacement and of the seismicity rate at La Plata Island (ISPT station) during the 2010 SSE. (Red) Number of seismic events detected over 2 hours sessions for an LTA/STA ratio higher than 6.0. (Grey dots) East displacement recorded by the GPS station, calculated every 6 hours.

  5. CO-EVOLUTION OF GALAXIES AND CENTRAL BLACK HOLES: OBSERVATIONAL EVIDENCE ON THE TRIGGER OF AGN FEEDBACK

    International Nuclear Information System (INIS)

    A comprehensive analysis of the extended emission-line region (EELR) around quasars is presented. A new Subaru/Suprime-Cam observation is combined with a literature search, resulting in a compilation of 81 EELR measurements for type-1 and type-2 quasars with an associated active galactic nucleus (AGN) and host galaxy properties. It is found that the EELR phenomenon shows clear correlation with the Eddington ratio, which links EELR to the constituents of principal component 1, or eigenvector 1, of the AGN emission correlations. We also find that EELR is preferentially associated with gas-rich, massive blue galaxies. This supports the idea that the primary determinant of EELR creation is gas availability and that the gas may be brought in by galaxy merger, triggering the current star formation as well as AGN activity, and also gives an explanation for the fact that most luminous EELRs are found around radio-loud sources with low Eddington ratio. By combining all the observations, it is suggested that EELR quasars occupy the massive blue corner of the green valley, the AGN realm, on the galaxy color-stellar mass diagram. Once a galaxy is pushed to this corner, an activated AGN would create an EELR by energy injection into the interstellar gas and eventually blow it away, leading to star formation quenching. The results presented here provide a piece of evidence for the presence of such an AGN feedback process, which may play a leading role in the co-evolution of galaxies and central super-massive black holes.

  6. Upgrade of the ATLAS Level-1 Trigger with event topology information

    CERN Document Server

    Simioni, Eduard; The ATLAS collaboration; Bauss, B; Büscher, V; Jakobi, K; Kaluza, A; Kahra, C; Reiss, A; Schäffer, J; Schulte, A; Simon, M; Tapprogge, S; Vogel, A; Zinser, M; Palka, M

    2015-01-01

    The Large Hadron Collider (LHC) in 2015 will collide proton beams with increased luminosity from \\unit{10^{34}} up to \\unit{3 \\times 10^{34}cm^{-2}s^{-1}}. ATLAS is an LHC experiment designed to measure decay properties of high energetic particles produced in the protons collisions. The higher luminosity places stringent operational and physical requirements on the ATLAS Trigger in order to reduce the 40MHz collision rate to a manageable event storage rate of 1kHz while at the same time, selecting those events with valuable physics meaning. The Level-1 Trigger is the first rate-reducing step in the ATLAS Trigger, with an output rate of 100kHz and decision latency of less than 2.5$\\mu s$. It is composed of the Calorimeter Trigger (L1Calo), the Muon Trigger (L1Muon) and the Central Trigger Processor (CTP). In 2014, there will be a new electronics element in the chain: the Topological Processor System (L1Topo system).\\\\ The L1Topo system consist of a single AdvancedTCA shelf equipped with three L1Topo processor ...

  7. Sequence information signal processor

    Science.gov (United States)

    Peterson, John C.; Chow, Edward T.; Waterman, Michael S.; Hunkapillar, Timothy J.

    1999-01-01

    An electronic circuit is used to compare two sequences, such as genetic sequences, to determine which alignment of the sequences produces the greatest similarity. The circuit includes a linear array of series-connected processors, each of which stores a single element from one of the sequences and compares that element with each successive element in the other sequence. For each comparison, the processor generates a scoring parameter that indicates which segment ending at those two elements produces the greatest degree of similarity between the sequences. The processor uses the scoring parameter to generate a similar scoring parameter for a comparison between the stored element and the next successive element from the other sequence. The processor also delivers the scoring parameter to the next processor in the array for use in generating a similar scoring parameter for another pair of elements. The electronic circuit determines which processor and alignment of the sequences produce the scoring parameter with the highest value.

  8. The Cell Processor

    OpenAIRE

    Hoefler, Torsten

    2006-01-01

    Mainstream processor development is mostly targeted at compatibility and continuity. Thus, the processor market is dominated by x86 compatible CPUs since more than two decades now. Several new concepts tried to gain some market share, but it was not possible to overtake the old compatibility driven concepts. A group of three corporates tries another way to come into the market with a new idea, the cell design. The cell processor is a new try to leverage the increasing amount...

  9. BAT trigger 700791 (the possible GRB 160622A) is 2E 1613.5-5053, the central source in SNR RCW103

    Science.gov (United States)

    D'Ai, A.; Evans, P. A.; Gehrels, N.; Gronwall, C.; Kennea, J. A.; Lien, A. Y.; Marshall, F. E.; Maselli, A.; Sakamoto, T.; Siegel, M. H.

    2016-06-01

    Swift has gathered 5.8 ks of WT mode data and 463 s of PC mode data on the field of the BAT trigger 700791 (= possible GRB 160622A, GCN Circ. 19547). The XRT image is dominated by diffuse emission from the supernova remnant RCW 103 (Frank et al., ApJ, 2015, 810,113), with a bright central source at RA,Dec.

  10. Embedded Processor Laboratory

    Data.gov (United States)

    Federal Laboratory Consortium — The Embedded Processor Laboratory provides the means to design, develop, fabricate, and test embedded computers for missile guidance electronics systems in support...

  11. Array processors in chemistry

    Energy Technology Data Exchange (ETDEWEB)

    Ostlund, N.S.

    1980-01-01

    The field of attached scientific processors (''array processors'') is surveyed, and an attempt is made to indicate their present and possible future use in computational chemistry. The current commercial products from Floating Point Systems, Inc., Datawest Corporation, and CSP, Inc. are discussed.

  12. A Video Control Processor

    OpenAIRE

    Tripp, Gerald

    1992-01-01

    This report describes the design and implementation of a simple microprogrammable processor with a fast response time to external events. This processor was designed as a controller for a testbench video system capable of performing a number of functions such as windowing and frame rate conversion.

  13. Timing, Trigger and Control Systems for LHC Detectors

    CERN Multimedia

    2002-01-01

    \\\\ \\\\At the LHC, precise bunch-crossing clock and machine orbit signals must be broadcast over distances of several km from the Prevessin Control Room to the four experiment areas and other destinations. At the LHC experiments themselves, quite extensive distribution systems are also required for the transmission of timing, trigger and control (TTC) signals to large numbers of front-end electronics controllers from a single location in the vicinity of the central trigger processor. The systems must control the detector synchronization and deliver the necessary fast signals and messages that are phased with the LHC clock, orbit or bunch structure. These include the bunch-crossing clock, level-1 trigger decisions, bunch and event numbers, as well as test signals and broadcast commands. A common solution to this TTC system requirement is expected to result in important economies of scale and permit a rationalization of the development, operational and support efforts required. LHC Common Project RD12 is developi...

  14. The ARGUS vertex trigger

    International Nuclear Information System (INIS)

    A fast second level trigger has been developed for the ARGUS experiment which recognizes tracks originating from the interaction region. The processor compares the hits in the ARGUS Micro Vertex Drift Chamber to 245760 masks stored in random access memories. The masks which are fully defined in three dimensions are able to reject tracks originating in the wall of the narrow beampipe of 10.5 mm radius. (orig.)

  15. Stimulation of the Basal and Central Amygdala in the Mustached Bat Triggers Echolocation and Agonistic Vocalizations within Multimodal Output

    OpenAIRE

    JagmeetSKanwal

    2014-01-01

    The neural substrate for the perception of vocalization is relatively well described, but we know much less about how the timing and specificity of vocalizations is tightly coupled with audiovocal communication behavior. In many vocal species, well-timed vocalizations accompany fear, vigilance and aggression. These emotive responses likely originate within the amygdala and other limbic structures, but the organization of motor outputs for triggering species-appropriate behaviors remains uncl...

  16. Adaptive signal processor

    International Nuclear Information System (INIS)

    An experimental, general purpose adaptive signal processor system has been developed, utilizing a quantized (clipped) version of the Widrow-Hoff least-mean-square adaptive algorithm developed by Moschner. The system accommodates 64 adaptive weight channels with 8-bit resolution for each weight. Internal weight update arithmetic is performed with 16-bit resolution, and the system error signal is measured with 12-bit resolution. An adapt cycle of adjusting all 64 weight channels is accomplished in 8 μsec. Hardware of the signal processor utilizes primarily Schottky-TTL type integrated circuits. A prototype system with 24 weight channels has been constructed and tested. This report presents details of the system design and describes basic experiments performed with the prototype signal processor. Finally some system configurations and applications for this adaptive signal processor are discussed

  17. Array processor architecture

    Science.gov (United States)

    Barnes, George H. (Inventor); Lundstrom, Stephen F. (Inventor); Shafer, Philip E. (Inventor)

    1983-01-01

    A high speed parallel array data processing architecture fashioned under a computational envelope approach includes a data base memory for secondary storage of programs and data, and a plurality of memory modules interconnected to a plurality of processing modules by a connection network of the Omega gender. Programs and data are fed from the data base memory to the plurality of memory modules and from hence the programs are fed through the connection network to the array of processors (one copy of each program for each processor). Execution of the programs occur with the processors operating normally quite independently of each other in a multiprocessing fashion. For data dependent operations and other suitable operations, all processors are instructed to finish one given task or program branch before all are instructed to proceed in parallel processing fashion on the next instruction. Even when functioning in the parallel processing mode however, the processors are not locked-step but execute their own copy of the program individually unless or until another overall processor array synchronization instruction is issued.

  18. The Run Control System and the Central Hint and Information Processor of the Data Acquisition System of the ATLAS Experiment at the LHC

    CERN Document Server

    Anders, G; The ATLAS collaboration; Lehmann Miotto, G; Magnoni, L

    2014-01-01

    The Trigger and Data Acquisition (TDAQ) system of the ATLAS detector is composed of a large number of distributed hardware and software components (about 3000 machines and more than 15000 concurrent processes at the end of LHC’s Run I) which in a coordinated manner provide the data-taking functionality of the overall system. The Run Control (RC) system steers the data acquisition by starting and stopping processes and by carrying all data-taking elements through well-defined states in a coherent way (finite state machine pattern). The RC is organized as a hierarchical tree (run control tree) of run controllers following the functional de-composition into systems and sub-systems of the ATLAS detector. During the LHC Long Shutdown 1 (LS1) the RC has been completely re-designed and re-implemented in order to better fulfill the new requirements which emerged during the LHC Run 1 and were not foreseen during the initial design phase, and in order to improve the error management and recovery mechanisms. Indeed gi...

  19. Hardware multiplier processor

    Science.gov (United States)

    Pierce, Paul E.

    1986-01-01

    A hardware processor is disclosed which in the described embodiment is a memory mapped multiplier processor that can operate in parallel with a 16 bit microcomputer. The multiplier processor decodes the address bus to receive specific instructions so that in one access it can write and automatically perform single or double precision multiplication involving a number written to it with or without addition or subtraction with a previously stored number. It can also, on a single read command automatically round and scale a previously stored number. The multiplier processor includes two concatenated 16 bit multiplier registers, two 16 bit concatenated 16 bit multipliers, and four 16 bit product registers connected to an internal 16 bit data bus. A high level address decoder determines when the multiplier processor is being addressed and first and second low level address decoders generate control signals. In addition, certain low order address lines are used to carry uncoded control signals. First and second control circuits coupled to the decoders generate further control signals and generate a plurality of clocking pulse trains in response to the decoded and address control signals.

  20. The Level 0 Pixel Trigger System for the ALICE Silicon Pixel Detector: implementation, testing and commissioning

    CERN Document Server

    Aglieri-Rinella, G

    2008-01-01

    The ALICE Silicon Pixel Detector transmits 1200 Fast-OR signals every 100 ns on 120 optical readout channels. They indicate the presence of at least one hit in the pixel matrix of each readout chip. The ALICE Level 0 Pixel Trigger System extracts them, processes them and delivers an input signal to the Central Trigger Processor for the first level trigger decision within a latency of 800 ns. This paper describes tests and measurements made on the system during the qualification and commissioning phases. These included Bit Error Rate tests on the Fast-OR data path, the measurement of the overall process latency and the recording of calibration data with cosmic rays. The first results of the operation of the Pixel Trigger System with the SPD detector in the ALICE experiment are also presented.

  1. A PC based digital pulse processor

    International Nuclear Information System (INIS)

    This is the second of two papers concerning the architecture, circuitry design and performance of a pulse processing station. This multifunction system, hosted on a Personal Computer's ISA bus, incorporates a high performance Pulse Height Analyzer, a Multichannel Scaler and a Digital Pulse Processor. This paper focus on this last operation mode. The Digital Pulse Processor is mainly based on a floating point digital signal processor, TMS320C31, on a 100 MSPS dash ADC, AD9012, and on a trigger and pulse locator mechanism based on a 16-bit counter synchronized with the sample clock. The preamplifier output is directly sampled and digitized and the incoming pulses are processed in real-time with reduced dead time. The implementation of the pulse processor is discussed and some preliminary results obtained with a HPGe detector are presented. The system is fully controlled by a Windows 95 / NT user friendly software package built around the client-server model. It enables remote data assessment and system configuration in a network environment

  2. Progress on the Level-1 Calorimeter Trigger

    CERN Multimedia

    Eric Eisenhandler

    The Level-1 Calorimeter Trigger (L1Calo) has recently passed a number of major hurdles. The various electronic modules that make up the trigger are either in full production or are about to be, and preparations in the ATLAS pit are well advanced. L1Calo has three main subsystems. The PreProcessor converts analogue calorimeter signals to digital, associates the rather broad trigger pulses with the correct proton-proton bunch crossing, and does a final calibration in transverse energy before sending digital data streams to the two algorithmic trigger processors. The Cluster Processor identifies and counts electrons, photons and taus, and the Jet/Energy-sum Processor looks for jets and also sums missing and total transverse energy. Readout drivers allow the performance of the trigger to be monitored online and offline, and also send region-of-interest information to the Level-2 Trigger. The PreProcessor (Heidelberg) is the L1Calo subsystem with the largest number of electronic modules (124), and most of its fu...

  3. Beyond processor sharing

    NARCIS (Netherlands)

    Aalto, S.; Ayesta, U.; Borst, S.C.; Misra, V.; Núñez Queija, R.

    2007-01-01

    While the (Egalitarian) Processor-Sharing (PS) discipline offers crucial insights in the performance of fair resource allocation mechanisms, it is inherently limited in analyzing and designing differentiated scheduling algorithms such as Weighted Fair Queueing and Weighted Round-Robin. The Discrimin

  4. Estimating precise location the tremor triggered by the surface waves of teleseismic events beneath the Yatsushiro Sea, central Kyushu, Japan

    Science.gov (United States)

    Miyazaki, M.; Matsumoto, S.; Shimizu, H.

    2013-12-01

    Non-volcanic tremors induced by large amplitude surface waves have been detected by many studies. One of the tremors occurred beneath the Yatsushiro Sea, west part of Kyushu Island, Japan is located far from both volcanoes and the plate boundary (Chao and Obara, 2012). The precise location of the event could provide important information about stress condition in the crust. We determined the hypocenter of the event by analyzing envelope of the seismograms at the seismic stations in the area. Envelope correlation method developed by Obara (2002) is suitable for detecting and locating tremors. Applying their method, we obtained the location of the event. However, the accuracy of the hypocenter over several kilometers in depth was not always sufficient to discuss the triggering mechanisms of the event. In the record of the passing surface waves of the 2012 Sumatra earthquake, we found the tremor that consists of two phases. The phase in the early part is rich in vertical component and the later one is rich in horizontal component. The apparent velocity of the early phase is higher than the latter, implying that the phases in vertical and horizontal components could be P- and S-wave from the hypocenter, respectively. We determined the hypocenter using envelope correlation method not only in horizontal component but also in vertical one. Cross correlograms of MS envelopes between vertical and horizontal components were calculated to obtain S-P time at the station. Then, we obtained the location using both of the relative S-wave arrival time of the station pair and S-P time. The hypocenters were located beneath the seismogenic zone in the area. It seems that the stress condition is critical at the bottom of the zone.

  5. Innovative communication processors: A survey

    OpenAIRE

    Gunningberg, Per

    1987-01-01

    Some existing innovative processors for execution of multilayer protocols are surveyed in order to identify performance limits and processor architectural trade-offs. The survey is restricted to packet or message handling processors with dedicated software and/or hardware. The processors are compared with respect to; performance, i.e. throughput and delay, to available protocols, and to implementation trade-offs, i.e. modularity, service access point accessibility, interface to host machine, ...

  6. Highly integrated pulse processor

    International Nuclear Information System (INIS)

    A digital pulse processor for a multichannel solid-state detector has been designed, using highly integrated analog and digital signal processing circuits. The detector preamplifier output is digitized and a parametrizable synchro is elaborated by a dedicated chipset. The digitized signal is then processed by a finite impulse response filter chip (FIR) whose programming is discussed, after which a pile-up protected peak detector sorts it into a histogram. All parameters are digitally controlled. ((orig.))

  7. Adaptive optical processors.

    Science.gov (United States)

    Ghosh, A

    1989-06-15

    There are two different approaches for improving the accuracy of analog optical associative processors: postprocessing with a bimodal system and preprocessing with a preconditioner. These two approaches can be combined to develop an adaptive optical multiprocessor that can adjust the computational steps depending on the data and produce solutions of linear algebra problems with a specified accuracy in a given amount of time. PMID:19752909

  8. The microprogrammable processor ESOP in a small elastic scattering experiment

    International Nuclear Information System (INIS)

    The microprogrammable processor ESOP has been introduced in the trigger system of a small angle elastic scattering experiment on a polarized proton beam at the Saturne synchrotron. Its implementation in a data acquisition system based on a Hewlett-Packard computer is described and preliminary results on the performance of a straight tracks rejecting algorithm are presented

  9. Multimode power processor

    Science.gov (United States)

    O'Sullivan, George A.; O'Sullivan, Joseph A.

    1999-01-01

    In one embodiment, a power processor which operates in three modes: an inverter mode wherein power is delivered from a battery to an AC power grid or load; a battery charger mode wherein the battery is charged by a generator; and a parallel mode wherein the generator supplies power to the AC power grid or load in parallel with the battery. In the parallel mode, the system adapts to arbitrary non-linear loads. The power processor may operate on a per-phase basis wherein the load may be synthetically transferred from one phase to another by way of a bumpless transfer which causes no interruption of power to the load when transferring energy sources. Voltage transients and frequency transients delivered to the load when switching between the generator and battery sources are minimized, thereby providing an uninterruptible power supply. The power processor may be used as part of a hybrid electrical power source system which may contain, in one embodiment, a photovoltaic array, diesel engine, and battery power sources.

  10. New Generation Processor Architecture Research

    Institute of Scientific and Technical Information of China (English)

    Chen Hongsong(陈红松); Hu Mingzeng; Ji Zhenzhou

    2003-01-01

    With the rapid development of microelectronics and hardware,the use of ever faster micro-processors and new architecture must be continued to meet tomorrow′s computing needs. New processor microarchitectures are needed to push performance further and to use higher transistor counts effectively.At the same time,aiming at different usages,the processor has been optimized in different aspects,such as high performace,low power consumption,small chip area and high security. SOC (System on chip)and SCMP (Single Chip Multi Processor) constitute the main processor system architecture.

  11. The sources of the shallow, upper plate earthquakes in Central Mexico, and their possible triggering by the subduction earthquakes, 'normal' and slow

    Science.gov (United States)

    Manighetti, I.; Vergnolle, M.; Campillo, M.; Cotton, F.; Thollon, O.

    2008-12-01

    Large earthquakes have broken the Central Mexico upper plate in the historical time (1887, M5.3; 1912, M6.9; 1920, M6.5; 1976, M5.3; 1979, M5.3), but the faults responsible for those earthquakes are not precisely known. Nor is their link with the subduction, especially in terms of possible triggering between subduction and shallow earthquakes. To address those issues, we first identify the major active faults that cut the upper plate, and determine their slip mode and overall organization. For that, we conduct a morphological analysis of the region, based on the use of satellite and topographic images. The upper plate appears dissected by a dense network of hundreds of major active faults, which overall form 2 distinct large-scale systems, named Jalisco and Mexico. The Jalisco system is made of the N-S Colima normal fault system which runs from the coast to the Transmexican Belt (TMB) where it ends in a large fishtail centered on the Chapala Lake. The western branch of the fishtail is made of NW-striking, N-dipping faults that are both normal and left-lateral, while the eastern branch is made of ENE-trending, N-dipping normal faults. The Mexico system resembles a large-scale horsetail. It is made of a major NNW-trending left-lateral strike-slip fault that runs from the coast to the TMB, at the eastern edge of the Oaxaca region. As it enters the TMB, that NNW system connects to a series of E-W, N-dipping, normal-right-lateral faults, while extending further north through a series of NNW, E-dipping normal-left-lateral faults. Together these faults bound to the south and west a series of rhomboidal half-grabens, among those are the basins of Mexico City and Acambay. Mexico City is thus bounded by large active faults but also dissected by smaller ones, both E-W and NNW. The E-W fault system that bounds the Acambay half-graben to the south is likely the one to have ruptured in 1912. Second, we examine whether the subduction interface and the upper plate active faults

  12. Fuel processors for fuel cell APU applications

    Science.gov (United States)

    Aicher, T.; Lenz, B.; Gschnell, F.; Groos, U.; Federici, F.; Caprile, L.; Parodi, L.

    The conversion of liquid hydrocarbons to a hydrogen rich product gas is a central process step in fuel processors for auxiliary power units (APUs) for vehicles of all kinds. The selection of the reforming process depends on the fuel and the type of the fuel cell. For vehicle power trains, liquid hydrocarbons like gasoline, kerosene, and diesel are utilized and, therefore, they will also be the fuel for the respective APU systems. The fuel cells commonly envisioned for mobile APU applications are molten carbonate fuel cells (MCFC), solid oxide fuel cells (SOFC), and proton exchange membrane fuel cells (PEMFC). Since high-temperature fuel cells, e.g. MCFCs or SOFCs, can be supplied with a feed gas that contains carbon monoxide (CO) their fuel processor does not require reactors for CO reduction and removal. For PEMFCs on the other hand, CO concentrations in the feed gas must not exceed 50 ppm, better 20 ppm, which requires additional reactors downstream of the reforming reactor. This paper gives an overview of the current state of the fuel processor development for APU applications and APU system developments. Furthermore, it will present the latest developments at Fraunhofer ISE regarding fuel processors for high-temperature fuel cell APU systems on board of ships and aircrafts.

  13. Video frame processor

    International Nuclear Information System (INIS)

    This report provides technical description regarding the Video Frame Processor (VFP) developed at Bhabha Atomic Research Centre. The instrument provides capture of video images available in CCIR format. Two memory planes each with a capacity of 512 x 512 x 8 bit data enable storage of two video image frames. The stored image can be processed on-line and on-line image subtraction can also be carried out for image comparisons. The VFP is a PC Add-on board and is I/O mapped within the host IBM PC/AT compatible computer. (author). 9 refs., 4 figs., 19 photographs

  14. Processor Technological Advancement

    Directory of Open Access Journals (Sweden)

    Sapan kr. Gupta, Manuj Gupta, and Rahul Pandey

    2012-08-01

    Full Text Available During the last decade Intel has introduced several technologies for different generation processors. Different architectures are added featuring enhanced energy efficiency, power management, affordable performance, fast execution, multitasking demands, optimized multithreading, CPU performance boost, higher data throughput, improved virtualization performance, smart security. This paper provides insight into recently added technologies and architectures. This paper discusses about the features enabled by the latest technologies along with the current issues and future prospects. This paper also deals with some constraints and limitations of these technologies highlighting the upcoming solution and the options

  15. Software for embedded processors: Problems and solutions

    Science.gov (United States)

    Bogaerts, J. A. C.

    1990-08-01

    Data Acquistion systems in HEP experiments use a wide spectrum of computers to cope with two major problems: high event rates and a large data volume. They do this by using special fast trigger processors at the source to reduce the event rate by several orders of magnitude. The next stage of a data acquisition system consists of a network of fast but conventional microprocessors which are embedded in high speed bus systems where data is still further reduced, filtered and merged. In the final stage complete events are farmed out to a another collection of processors, which reconstruct the events and perhaps achieve a further event rejection by a small factor, prior to recording onto magnetic tape. Detectors are monitored by analyzing a fraction of the data. This may be done for individual detectors at an early state of the data acquisition or it may be delayed till the complete events are available. A network of workstations is used for monitoring, displays and run control. Software for trigger processors must have a simple structure. Rejection algorithms are carefully optimized, and overheads introduced by system software cannot be tolerated. The embedded microprocessors have to co-operate, and need to be synchronized with the preceding and following stages. Real time kernels are typically used to solve synchronization and communication problems. Applications are usually coded in C, which is reasonably efficient and allows direct control over low level hardware functions. Event reconstruction software is very similar or even identical to offline software, predominantly written in FORTRAN. With the advent of powerful RISC processors, and with manufacturers tending to adopt open bus architectures, there is a move towards commercial processors and hence the introduction of the UNIX operating system. Building and controlling such a heterogeneous data acquisition system puts a heavy strain on the software. Communications is now as important as CPU capacity and I

  16. Distributed processor allocation for launching applications in a massively connected processors complex

    Science.gov (United States)

    Pedretti, Kevin

    2008-11-18

    A compute processor allocator architecture for allocating compute processors to run applications in a multiple processor computing apparatus is distributed among a subset of processors within the computing apparatus. Each processor of the subset includes a compute processor allocator. The compute processor allocators can share a common database of information pertinent to compute processor allocation. A communication path permits retrieval of information from the database independently of the compute processor allocators.

  17. VLSI array processor

    Science.gov (United States)

    Greenwood, E.

    1982-07-01

    The Arithmetic Processor Unit (APU) data base design check was completed. Minor design rule violations and design improvements were accomplished. The APU mask set has been fabricated and checked. Initial checking of all mask layers revealed a design rule problem in one layer. That layer was corrected, refabricated and checked out. The mask set has been delivered to the chip fabrication area. The fabrication process has been initiated. All work on the Array Processor Demonstration System (APDS) has been suspended at CHI until the additionally requested funding was received. That funding has been authorized and CHI will begin work on the APDS in July. The following activities are planned in the following quarter: 1) Complete fabrication of the first lot of VLSI APU devices. 2) Complete integration and check-out of the APDS simulator. 3) Complete integration and check-out of the APU breadboard. 4) Verify the VLSI APU wafer tests with the APU breadboard. 5) Complete check-out of the APDS using the APU breadboard.

  18. Spaceborne Processor Array

    Science.gov (United States)

    Chow, Edward T.; Schatzel, Donald V.; Whitaker, William D.; Sterling, Thomas

    2008-01-01

    A Spaceborne Processor Array in Multifunctional Structure (SPAMS) can lower the total mass of the electronic and structural overhead of spacecraft, resulting in reduced launch costs, while increasing the science return through dynamic onboard computing. SPAMS integrates the multifunctional structure (MFS) and the Gilgamesh Memory, Intelligence, and Network Device (MIND) multi-core in-memory computer architecture into a single-system super-architecture. This transforms every inch of a spacecraft into a sharable, interconnected, smart computing element to increase computing performance while simultaneously reducing mass. The MIND in-memory architecture provides a foundation for high-performance, low-power, and fault-tolerant computing. The MIND chip has an internal structure that includes memory, processing, and communication functionality. The Gilgamesh is a scalable system comprising multiple MIND chips interconnected to operate as a single, tightly coupled, parallel computer. The array of MIND components shares a global, virtual name space for program variables and tasks that are allocated at run time to the distributed physical memory and processing resources. Individual processor- memory nodes can be activated or powered down at run time to provide active power management and to configure around faults. A SPAMS system is comprised of a distributed Gilgamesh array built into MFS, interfaces into instrument and communication subsystems, a mass storage interface, and a radiation-hardened flight computer.

  19. AMD's 64-bit Opteron processor

    CERN Document Server

    CERN. Geneva

    2003-01-01

    This talk concentrates on issues that relate to obtaining peak performance from the Opteron processor. Compiler options, memory layout, MPI issues in multi-processor configurations and the use of a NUMA kernel will be covered. A discussion of recent benchmarking projects and results will also be included.BiographiesDavid RichDavid directs AMD's efforts in high performance computing and also in the use of Opteron processors...

  20. Emerging Trends in Embedded Processors

    Directory of Open Access Journals (Sweden)

    Gurvinder Singh

    2014-05-01

    Full Text Available An Embedded Processors is simply a µProcessors that has been “Embedded” into a device. Embedded systems are important part of human life. For illustration, one cannot visualize life without mobile phones for personal communication. Embedded systems are used in many places like healthcare, automotive, daily life, and in different offices and industries.Embedded Processors develop new research area in the field of hardware designing.

  1. ATLAS FTK: Fast Track Trigger

    CERN Document Server

    Volpi, Guido; The ATLAS collaboration

    2015-01-01

    An overview of the ATLAS Fast Tracker processor is presented, reporting the design of the system, its expected performance, and the integration status. The next LHC runs, with a significant increase in instantaneous luminosity, will provide a big challenge to the trigger and data acquisition systems of all the experiments. An intensive use of the tracking information at the trigger level will be important to keep high efficiency in interesting events, despite the increase in multiple p-p collisions per bunch crossing (pile-up). In order to increase the use of tracks within the High Level Trigger (HLT), the ATLAS experiment planned the installation of an hardware processor dedicated to tracking: the Fast TracKer (FTK) processor. The FTK is designed to perform full scan track reconstruction at every Level-1 accept. To achieve this goal, the FTK uses a fully parallel architecture, with algorithms designed to exploit the computing power of custom VLSI chips, the Associative Memory, as well as modern FPGAs. The FT...

  2. Commissioning of the ATLAS Muon Trigger with Beam Collisions at the LHC

    CERN Document Server

    Oh, A; The ATLAS collaboration

    2010-01-01

    The ATLAS experiment at CERN's Large Hadron Collider (LHC) has taken its first data with colliding beams. The LHC aims to deliver an integrated luminosity of 1 fb-1 in the run period 2010/2011 at luminosities of up to 1032 cm-2 s-1, which requires active rejection of events in the trigger system. The muon system is the largest sub-detector of the ATLAS experiment and has the capability to reconstruct muons in standalone mode, as well as in combination with the Inner Detector tracking. It deploys different detector technologies, resistive plate chambers and thin gap chambers to provide fast trigger signals, and monitored drift tubes and cathode strip chambers for precision measurements. The L1 muon trigger gets its input from the fast muon trigger detectors. Fast sector logic boards select muon candidates, which are passed via an interface board to the central trigger processor and then to the High Level Trigger (HLT). The Muon HLT is purely software based and encompasses a level 2 trigger followed by an event...

  3. Commissioning of the ATLAS Muon High Level Trigger with beam collisions at the LHC

    CERN Document Server

    Kanno, T; The ATLAS collaboration

    2010-01-01

    The ATLAS experiment at CERN's Large Hadron Collider (LHC) has taken its first data with colliding beams. The LHC aims to deliver an integrated luminosity of 1 fb-1 in the run period 2010/2011 at luminosities of up to 10^32 cm^-2s^-1, which requires active rejection of events in the trigger system. The muon system is the largest sub-detector of the ATLAS experiment and has the capability to reconstruct muons in standalone mode, as well as in combination with the Inner Detector tracking. The L1 muon trigger gets its input from fast muon trigger detectors. Fast sector logic boards select muon candidates, which are passed via an interface board to the central trigger processor and then to the High Level Trigger (HLT). The Muon HLT is purely software based and encompasses a level 2 trigger followed by an event filter for a staged trigger approach. It has access to the data of the precision muon detectors and other detector elements to refine the muon hypothesis. The muon HLT has been extensively tested with cosmi...

  4. Never Trust Your Word Processor

    Science.gov (United States)

    Linke, Dirk

    2009-01-01

    In this article, the author talks about the auto correction mode of word processors that leads to a number of problems and describes an example in biochemistry exams that shows how word processors can lead to mistakes in databases and in papers. The author contends that, where this system is applied, spell checking should not be left to a word…

  5. Embedded Processor Oriented Compiler Infrastructure

    Directory of Open Access Journals (Sweden)

    DJUKIC, M.

    2014-08-01

    Full Text Available In the recent years, research of special compiler techniques and algorithms for embedded processors broaden the knowledge of how to achieve better compiler performance in irregular processor architectures. However, industrial strength compilers, besides ability to generate efficient code, must also be robust, understandable, maintainable, and extensible. This raises the need for compiler infrastructure that provides means for convenient implementation of embedded processor oriented compiler techniques. Cirrus Logic Coyote 32 DSP is an example that shows how traditional compiler infrastructure is not able to cope with the problem. That is why the new compiler infrastructure was developed for this processor, based on research. in the field of embedded system software tools and experience in development of industrial strength compilers. The new infrastructure is described in this paper. Compiler generated code quality is compared with code generated by the previous compiler for the same processor architecture.

  6. The ATLAS fast tracker processor design

    CERN Document Server

    Volpi, Guido; Albicocco, Pietro; Alison, John; Ancu, Lucian Stefan; Anderson, James; Andari, Nansi; Andreani, Alessandro; Andreazza, Attilio; Annovi, Alberto; Antonelli, Mario; Asbah, Needa; Atkinson, Markus; Baines, J; Barberio, Elisabetta; Beccherle, Roberto; Beretta, Matteo; Biesuz, Nicolo Vladi; Blair, R E; Bogdan, Mircea; Boveia, Antonio; Britzger, Daniel; Bryant, Partick; Burghgrave, Blake; Calderini, Giovanni; Camplani, Alessandra; Cavaliere, Viviana; Cavasinni, Vincenzo; Chakraborty, Dhiman; Chang, Philip; Cheng, Yangyang; Citraro, Saverio; Citterio, Mauro; Crescioli, Francesco; Dawe, Noel; Dell'Orso, Mauro; Donati, Simone; Dondero, Paolo; Drake, G; Gadomski, Szymon; Gatta, Mauro; Gentsos, Christos; Giannetti, Paola; Gkaitatzis, Stamatios; Gramling, Johanna; Howarth, James William; Iizawa, Tomoya; Ilic, Nikolina; Jiang, Zihao; Kaji, Toshiaki; Kasten, Michael; Kawaguchi, Yoshimasa; Kim, Young Kee; Kimura, Naoki; Klimkovich, Tatsiana; Kolb, Mathis; Kordas, K; Krizka, Karol; Kubota, T; Lanza, Agostino; Li, Ho Ling; Liberali, Valentino; Lisovyi, Mykhailo; Liu, Lulu; Love, Jeremy; Luciano, Pierluigi; Luongo, Carmela; Magalotti, Daniel; Maznas, Ioannis; Meroni, Chiara; Mitani, Takashi; Nasimi, Hikmat; Negri, Andrea; Neroutsos, Panos; Neubauer, Mark; Nikolaidis, Spiridon; Okumura, Y; Pandini, Carlo; Petridou, Chariclia; Piendibene, Marco; Proudfoot, James; Rados, Petar Kevin; Roda, Chiara; Rossi, Enrico; Sakurai, Yuki; Sampsonidis, Dimitrios; Saxon, James; Schmitt, Stefan; Schoening, Andre; Shochet, Mel; Shoijaii, Jafar; Soltveit, Hans Kristian; Sotiropoulou, Calliope-Louisa; Stabile, Alberto; Swiatlowski, Maximilian J; Tang, Fukun; Taylor, Pierre Thor Elliot; Testa, Marianna; Tompkins, Lauren; Vercesi, V; Wang, Rui; Watari, Ryutaro; Zhang, Jianhong; Zeng, Jian Cong; Zou, Rui; Bertolucci, Federico

    2015-01-01

    The extended use of tracking information at the trigger level in the LHC is crucial for the trigger and data acquisition (TDAQ) system to fulfill its task. Precise and fast tracking is important to identify specific decay products of the Higgs boson or new phenomena, as well as to distinguish the contributions coming from the many collisions that occur at every bunch crossing. However, track reconstruction is among the most demanding tasks performed by the TDAQ computing farm; in fact, complete reconstruction at full Level-1 trigger accept rate (100 kHz) is not possible. In order to overcome this limitation, the ATLAS experiment is planning the installation of a dedicated processor, the Fast Tracker (FTK), which is aimed at achieving this goal. The FTK is a pipeline of high performance electronics, based on custom and commercial devices, which is expected to reconstruct, with high resolution, the trajectories of charged-particle tracks with a transverse momentum above 1 GeV, using the ATLAS inner tracker info...

  7. Distributed processor systems

    International Nuclear Information System (INIS)

    In recent years, there has been a growing tendency in high-energy physics and in other fields to solve computational problems by distributing tasks among the resources of inter-coupled processing devices and associated system elements. This trend has gained further momentum more recently with the increased availability of low-cost processors and with the development of the means of data distribution. In two lectures, the broad question of distributed computing systems is examined and the historical development of such systems reviewed. An attempt is made to examine the reasons for the existence of these systems and to discern the main trends for the future. The components of distributed systems are discussed in some detail and particular emphasis is placed on the importance of standards and conventions in certain key system components. The ideas and principles of distributed systems are discussed in general terms, but these are illustrated by a number of concrete examples drawn from the context of the high-energy physics environment. (Auth.)

  8. THE STAR LEVEL-3 TRIGGER SYSTEM.

    Energy Technology Data Exchange (ETDEWEB)

    LANGE, J.S.; ADLER, C.; BERGER, J.; DEMELLO, M.; FLIERL, D.; ET AL

    1999-11-15

    The STAR level-3 trigger is a MYRINET interconnected ALPHA processor farm, performing online tracking of N{sub track} {ge} 8000 particles (N{sub point} {le} 45 per track) with a design input rate of R=100 Hz. A large scale prototype system was tested in 12/99 with laser and cosmic particle events.

  9. Calibration for the ATLAS Level-1 Calorimeter-Trigger

    Energy Technology Data Exchange (ETDEWEB)

    Foehlisch, F.

    2007-12-19

    This thesis describes developments and tests that are necessary to operate the Pre-Processor of the ATLAS Level-1 Calorimeter Trigger for data acquisition. The major tasks of Pre-Processor comprise the digitizing, time-alignment and the calibration of signals that come from the ATLAS calorimeter. Dedicated hardware has been developed that must be configured in order to fulfill these tasks. Software has been developed that implements the register-model of the Pre-Processor Modules and allows to set up the Pre-Processor. In order to configure the Pre-Processor in the context of an ATLAS run, user-settings and the results of calibration measurements are used to derive adequate settings for registers of the Pre-Processor. The procedures that allow to perform the required measurements and store the results into a database are demonstrated. Furthermore, tests that go along with the ATLAS installation are presented and results are shown. (orig.)

  10. Calibration for the ATLAS Level-1 Calorimeter-Trigger

    International Nuclear Information System (INIS)

    This thesis describes developments and tests that are necessary to operate the Pre-Processor of the ATLAS Level-1 Calorimeter Trigger for data acquisition. The major tasks of Pre-Processor comprise the digitizing, time-alignment and the calibration of signals that come from the ATLAS calorimeter. Dedicated hardware has been developed that must be configured in order to fulfill these tasks. Software has been developed that implements the register-model of the Pre-Processor Modules and allows to set up the Pre-Processor. In order to configure the Pre-Processor in the context of an ATLAS run, user-settings and the results of calibration measurements are used to derive adequate settings for registers of the Pre-Processor. The procedures that allow to perform the required measurements and store the results into a database are demonstrated. Furthermore, tests that go along with the ATLAS installation are presented and results are shown. (orig.)

  11. Building custom processors with Handel-C

    CERN Document Server

    Lokier, J

    1999-01-01

    Triggering and data acquisition for the ATLAS LHC experiment requires state of the art computer hardware. Amongst other things, specialised processors may be required. To build these economically we are looking at reconfigurable computing, and a high-level hardware description language: Handel-C. We had previously implemented a specialised network hardware application in AHDL-a hardware description at the level of gates, flip-flops and state machines. As a feasibility study, we have rewritten the application in Handel-C -a language similar to C, except that it can be translated into hardware. There were problems to solve: high data throughput with complex pipelines; timing constraints; I/O interfaces to external devices; difficulties with the Altera devices. We gained valuable experience, wrote useful support tools, and discovered clean new ways to make the most of the language in the high-speed domain. (0 refs).

  12. Smart trigger logic for focal plane arrays

    Science.gov (United States)

    Levy, James E; Campbell, David V; Holmes, Michael L; Lovejoy, Robert; Wojciechowski, Kenneth; Kay, Randolph R; Cavanaugh, William S; Gurrieri, Thomas M

    2014-03-25

    An electronic device includes a memory configured to receive data representing light intensity values from pixels in a focal plane array and a processor that analyzes the received data to determine which light values correspond to triggered pixels, where the triggered pixels are those pixels that meet a predefined set of criteria, and determines, for each triggered pixel, a set of neighbor pixels for which light intensity values are to be stored. The electronic device also includes a buffer that temporarily stores light intensity values for at least one previously processed row of pixels, so that when a triggered pixel is identified in a current row, light intensity values for the neighbor pixels in the previously processed row and for the triggered pixel are persistently stored, as well as a data transmitter that transmits the persistently stored light intensity values for the triggered and neighbor pixels to a data receiver.

  13. Seismometer array station processors

    International Nuclear Information System (INIS)

    A description is given of the design, construction and initial testing of two types of Seismometer Array Station Processor (SASP), one to work with data stored on magnetic tape in analogue form, the other with data in digital form. The purpose of a SASP is to detect the short period P waves recorded by a UK-type array of 20 seismometers and to edit these on to a a digital library tape or disc. The edited data are then processed to obtain a rough location for the source and to produce seismograms (after optimum processing) for analysis by a seismologist. SASPs are an important component in the scheme for monitoring underground explosions advocated by the UK in the Conference of the Committee on Disarmament. With digital input a SASP can operate at 30 times real time using a linear detection process and at 20 times real time using the log detector of Weichert. Although the log detector is slower, it has the advantage over the linear detector that signals with lower signal-to-noise ratio can be detected and spurious large amplitudes are less likely to produce a detection. It is recommended, therefore, that where possible array data should be recorded in digital form for input to a SASP and that the log detector of Weichert be used. Trial runs show that a SASP is capable of detecting signals down to signal-to-noise ratios of about two with very few false detections, and at mid-continental array sites it should be capable of detecting most, if not all, the signals with magnitude above msub(b) 4.5; the UK argues that, given a suitable network, it is realistic to hope that sources of this magnitude and above can be detected and identified by seismological means alone. (author)

  14. Burst-mode optical label processor with ultralow power consumption.

    Science.gov (United States)

    Ibrahim, Salah; Nakahara, Tatsushi; Ishikawa, Hiroshi; Takahashi, Ryo

    2016-04-01

    A novel label processor subsystem for 100-Gbps (25-Gbps × 4λs) burst-mode optical packets is developed, in which a highly energy-efficient method is pursued for extracting and interfacing the ultrafast packet-label to a CMOS-based processor where label recognition takes place. The method involves performing serial-to-parallel conversion for the label bits on a bit-by-bit basis by using an optoelectronic converter that is operated with a set of optical triggers generated in a burst-mode manner upon packet arrival. Here we present three key achievements that enabled a significant reduction in the total power consumption and latency of the whole subsystem; 1) based on a novel operation mechanism for providing amplification with bit-level selectivity, an optical trigger pulse generator, that consumes power for a very short duration upon packet arrival, is proposed and experimentally demonstrated, 2) the energy of optical triggers needed by the optoelectronic serial-to-parallel converter is reduced by utilizing a negative-polarity signal while employing an enhanced conversion scheme entitled the discharge-or-hold scheme, 3) the necessary optical trigger energy is further cut down by half by coupling the triggers through the chip's backside, whereas a novel lens-free packaging method is developed to enable a low-cost alignment process that works with simple visual observation. PMID:27136992

  15. ALICE High Level Trigger

    CERN Multimedia

    Alt, T

    2013-01-01

    The ALICE High Level Trigger (HLT) is a computing farm designed and build for the real-time, online processing of the raw data produced by the ALICE detectors. Events are fully reconstructed from the raw data, analyzed and compressed. The analysis summary together with the compressed data and a trigger decision is sent to the DAQ. In addition the reconstruction of the events allows for on-line monitoring of physical observables and this information is provided to the Data Quality Monitor (DQM). The HLT can process event rates of up to 2 kHz for proton-proton and 200 Hz for Pb-Pb central collisions.

  16. Optical timing, trigger and control distribution for LHC detectors

    International Nuclear Information System (INIS)

    At CERN's future Large Hadron Collider, timing, trigger-accept and control signals must be distributed from a small number of sources to many thousands of front-end electronics destinations located on the ATLAS and CMS detectors. The LHC timing reference must be delivered with sub-nanosecond jitter and programmable phase. First-level trigger decisions must be broadcast from the central trigger processor to all the front-end pipeline controllers and delivered synchronously with the appropriate bunch identification, compensated for particle flight times and detector, electronics and propagation delays. In addition, broadcast control signals and individually-addressed controls and parameters such as calibration data have to be distributed. This paper describes how it is planned to broadcast all the signals over entirely passive multichannel optical fiber networks with uncontrolled path lengths. It reviews some of the technology options which are currently available and those which are likely to mature within the time frame of LHC preparation. It discusses how synchronization can be established over the system and describes how different distribution network configurations, laser transmitters and encoding methods can be used to deliver the signal using optoelectronic receivers which are becoming affordable for extensive deployment

  17. Triggering Klystrons

    Energy Technology Data Exchange (ETDEWEB)

    Stefan, Kelton D.; /Purdue U. /SLAC

    2010-08-25

    To determine if klystrons will perform to the specifications of the LCLS (Linac Coherent Light Source) project, a new digital trigger controller is needed for the Klystron/Microwave Department Test Laboratory. The controller needed to be programmed and Windows based user interface software needed to be written to interface with the device over a USB (Universal Serial Bus). Programming the device consisted of writing logic in VHDL (VHSIC (Very High Speed Integrated Circuits) hardware description language), and the Windows interface software was written in C++. Xilinx ISE (Integrated Software Environment) was used to compile the VHDL code and program the device, and Microsoft Visual Studio 2005 was used to compile the C++ based Windows software. The device was programmed in such a way as to easily allow read/write operations to it using a simple addressing model, and Windows software was developed to interface with the device over a USB connection. A method of setting configuration registers in the trigger device is absolutely necessary to the development of a new triggering system, and the method developed will fulfill this need adequately. More work is needed before the new trigger system is ready for use. The configuration registers in the device need to be fully integrated with the logic that will generate the RF signals, and this system will need to be tested extensively to determine if it meets the requirements for low noise trigger outputs.

  18. 7 CFR 926.13 - Processor.

    Science.gov (United States)

    2010-01-01

    ... 7 Agriculture 8 2010-01-01 2010-01-01 false Processor. 926.13 Section 926.13 Agriculture... Processor. Processor means any person who receives or acquires fresh or frozen cranberries or cranberries in the form of concentrate from handlers, producer-handlers, importers, brokers or other processors...

  19. 40 CFR 791.45 - Processors.

    Science.gov (United States)

    2010-07-01

    ... 40 Protection of Environment 31 2010-07-01 2010-07-01 true Processors. 791.45 Section 791.45...) DATA REIMBURSEMENT Basis for Proposed Order § 791.45 Processors. (a) Generally, processors will be... processors will have a responsibility to provide reimbursement directly to those paying for the testing:...

  20. The ATLAS Muon Trigger Performance in pp Collisions at sqrt(s)=8 TeV in Year 2012 Runs

    CERN Document Server

    Nobe, T; The ATLAS collaboration

    2012-01-01

    Events with muons in the final state are an important signature for many physics topics at Large Hadron Collider (LHC), for instance, searches for Higgs boson production or new phenomena, measurements on the standard model processes like top-quark, W, Z production. Thus, efficient trigger on muons in data taking and understanding its performance are crucial to perform these physics studies. At LHC high rejection power against large backgrounds, while maintaining high efficiency for rare signal events, is required for online selection at the trigger level. The ATLAS experiment employs a multi-level trigger architecture that selects the events in three sequential steps of increasing complexity and accuracy to cope with this challenging task. The L1 muon trigger system gets its input from fast muon trigger detectors. Fast sector logic boards select muon candidates, which are passed via an interface board to the central trigger processor and then to the High Level Trigger (HLT). The Muon HLT is purely software ba...

  1. The ATLAS muon trigger performance in pp collisions at sqrt(s) = 8 TeV in year 2012 runs

    CERN Document Server

    Nobe, T; The ATLAS collaboration

    2012-01-01

    Events with muons in the final state are an important signature for many physics topics at Large Hadron Collider (LHC), for instance, searches for Higgs boson production or new phenomena, measurements on the standard model processes like top-quark, W, Z production. Thus, efficient trigger on muons in data taking and understanding its performance are crucial to perform these physics studies. At LHC high rejection power against large backgrounds, while maintaining high efficiency for rare signal events, is required for online selection at the trigger level. The ATLAS experiment employs a multi-level trigger architecture that selects the events in three sequential steps of increasing complexity and accuracy to cope with this challenging task. The L1 muon trigger system gets its input from fast muon trigger detectors. Fast sector logic boards select muon candidates, which are passed via an interface board to the central trigger processor and then to the High Level Trigger (HLT). The Muon HLT is purely software ba...

  2. A Time-Multiplexed Track-Trigger architecture for CMS

    CERN Document Server

    Hall, Geoffrey; Pesaresi, Mark Franco; Rose, A

    2014-01-01

    The CMS Tracker under development for the High Luminosity LHC includes an outer tracker based on ``PT-modules'' which will provide track stubs based on coincident clusters in two closely spaced sensor layers, aiming to reject low transverse momentum track hits before data transmission to the Level-1 trigger. The tracker data will be used to reconstruct track segments in dedicated processors before onward transmission to other trigger processors which will combine tracker information with data originating from the calorimeter and muon detectors, to make the final L1 trigger decision. The architecture for processing the tracker data is still an open question. One attractive option is to explore a Time Multiplexed design similar to one which is currently being implemented in the CMS calorimeter trigger as part of the Phase I trigger upgrade. The Time Multiplexed Trigger concept is explained, the potential benefits of applying it for processing future tracker data are described and a possible design based on cur...

  3. Natrium: Use of FPGA embedded processors for real-time data compression

    International Nuclear Information System (INIS)

    We present test results and characterization of a data compression system for the readout of the NA62 liquid krypton calorimeter trigger processor. The Level-0 electromagnetic calorimeter trigger processor of the NA62 experiment at CERN receives digitized data from the calorimeter main readout board. These data are stored on an on-board DDR2 RAM memory and read out upon reception of a Level-0 accept signal. The maximum raw data throughput from the trigger front-end cards is 2.6 Gbps. To readout these data over two Gbit Ethernet interfaces we investigated different implementations of a data compression system based on the Rice-Golomb coding: one is implemented in the FPGA as a custom block and one is implemented on the FPGA embedded processor running a C code. The two implementations are tested on a set of sample events and compared with respect to achievable readout bandwidth.

  4. A two level FASTBUS based trigger system for CDF

    International Nuclear Information System (INIS)

    We describe a two level FASTBUS based trigger processor designed and built for the CDF detector at the Fermilab anti pp collider. The Level 1 decision is based on the global energy deposition in the calorimeters as well as on the presence of muon candidates and stiff tracks in the central drift chamber. The Level 1 decision is made in the 3.5 μs between beam crossings, incurring no deadtime while reducing a raw event rate of 50-75 kHz to a few kHz. The remaining events are passed on to Level 2. The Level 2 decision is driven by the topology of the event, operating on calorimeter clusters, central stiff tracks and muon candidates. Level 2 is designed to reduce the rate to 1-100 Hz, incurring less than 10% deadtime, before initiating readout of all the detector elements. A large fraction of the trigger hardware is used for both the Level 1 and Level 2 decisions. (orig.)

  5. The trigger system for the Collider Detector Facility

    International Nuclear Information System (INIS)

    The trigger logic for the Collider Detector Facility (CDF) at Fermilab is described. An analog/digital system constructs triggers based on clusters of energy in the calorimetry. These triggers are then combined with signals from the muon and central tracking systems to make a global trigger. Two levels of trigger logic have been implemented: a 'Level 1' trigger which is dead-timeless, and a more sophisticated Level 2 trigger. The rejection factor provided by these two systems will be 103 - 104

  6. Integrated fuel processor development challenges

    International Nuclear Information System (INIS)

    In the absence of a hydrogen-refueling infrastructure, the success of the fuel cell system in the market will depend on fuel processors to enable the use of available fuels, such as gasoline, natural gas, etc. The fuel processor includes several catalytic reactors, scrubbers to remove chemical species that can poison downstream catalysts or the fuel cell electrocatalyst, and heat exchangers. Most fuel cell power applications seek compact, lightweight hardware with rapid-start and load- following capabilities. Although packaging can partially address the size and volume, balancing the performance parameters while maintaining the fuel conversion (to hydrogen) efficiency requires careful integration of the unit operations and processes. Argonne National Laboratory has developed integrated fuel processors that are compact and light, and that operate efficiently. This paper discusses some of the difficulties encountered in the development process, focusing on the factors/components that constrain performance, and areas that need further research and development

  7. Java Processor Optimized for RTSJ

    Directory of Open Access Journals (Sweden)

    Tu Shiliang

    2007-01-01

    Full Text Available Due to the preeminent work of the real-time specification for Java (RTSJ, Java is increasingly expected to become the leading programming language in real-time systems. To provide a Java platform suitable for real-time applications, a Java processor which can execute Java bytecode is directly proposed in this paper. It provides efficient support in hardware for some mechanisms specified in the RTSJ and offers a simpler programming model through ameliorating the scoped memory of the RTSJ. The worst case execution time (WCET of the bytecodes implemented in this processor is predictable by employing the optimization method proposed in our previous work, in which all the processing interfering predictability is handled before bytecode execution. Further advantage of this method is to make the implementation of the processor simpler and suited to a low-cost FPGA chip.

  8. MAKASSAR COPRA AS A TRIGGER OF STRUGGLING FOR POWER BETWEEN CENTRAL AND LOCAL GOVERMENT: A HISTORICAL STUDY OF REGIONAL POLITICAL ECONOMY IN INDONESIA

    OpenAIRE

    Asba, A. Rasyid

    2011-01-01

    central government of Jakarta. For example, there was a claim of South Moluccas Republic Movement and Permesta (Whole people struggling) for economic equity. The gain of copra trading which divided into 70% for local and 30% for central government became national political problem in maintaining the central and local government relationship. That???s why, the local conflict in Eastern Indonesia had been occuring until now and being a problem for developing a democratic modern Indonesia. N...

  9. The evolution of the trigger and data acquisition system in the ATLAS experiment (CHEP2013: 20. international conference on computing in high energy and nuclear physics)

    International Nuclear Information System (INIS)

    The ATLAS experiment, which records the results of LHC proton-proton collisions, is upgrading its Trigger and Data Acquisition (TDAQ) system during the current LHC first long shutdown. The purpose of this upgrade is to add robustness and flexibility to the selection and the conveyance of the physics data, simplify the maintenance of the infrastructure, exploit new technologies and, overall, make ATLAS data-taking capable of dealing with increasing event rates. While the TDAQ system successfully operated well beyond the original design goals, the accumulated experience stimulated interest to explore possible evolutions. With higher luminosities, the required number and complexity of Level-1 triggers will increase in order to satisfy the physics goals of ATLAS, while keeping the total Level-1 rates at or below 100 kHz. The Central Trigger Processor will be upgraded to increase the number ofmanageable inputs and accommodate additional hardware for improved performance, and a new Topological Processor will be included. A single homogeneous high level trigger system will be deployed. The current second and third trigger levels will be executed together on a unique hardware node. This design has many advantages: the radical simplification of the architecture, the flexible and automatically balanced distribution of the computing resources, the sharing of code and services on nodes. In this paper, we report on the design and the development status of the upgraded TDAQ system, with particular attention to the tests currently on-going to identify the required performance and to spot its possible limitations.

  10. A fast programmable trigger for isolated cluster counting in the BELLE experiment

    OpenAIRE

    Kim, H. J.; Kim, S. K.; Lee, S. H.; Hur, T. W.; Kim, C. H.; Wang, F.; Park, I. C.; Kim, Hee Jong; Cheon, B. G.; Won, E.

    1999-01-01

    We have developed a fast programmable trigger processor board based on a field programmable gate array and a complex programmable logic device for use in the BELLE experiment. The trigger board accommodates 144 ECL input signals, 2 NIM input signals, 24 ECL output signals, and the VME bus specification. An asynchronous trigger logic for counting isolated clusters is used. We have obtained trigger latency of 50 ns with a full access to input and output signals via a VME interface. The trigger ...

  11. Realtime processor of SAR systems

    Science.gov (United States)

    Schotter, R.

    Attention is given to potential applications of a synthetic aperture radar (SAR) real time processor which was developed for Space Shuttle-based earth sensing, and which may prove useful in military surveillance, ocean wave studies, ship movements in territorial waters, land conservation, geology, and mineralogical prospecting. The SAR processor's signal processing task is characterized by complex algorithms and large quantities of raw data/time unit. A 'pipeline' configuration has been judged optimal for this type of processing, and it will consist of digital hardware modules for Fourier transform, digital filtering, two-dimensional image memory, and complex multiplication.

  12. Reconfigurable Communication Processor:A New Approach for Network Processor

    Institute of Scientific and Technical Information of China (English)

    孙华; 陈青山; 张文渊

    2003-01-01

    As the traditional RISC +ASIC/ASSP approach for network processor design can not meet the today'srequirements, this paper described an alternate approach, Reconfigurable Processing Architecture, to boost theperformance to ASIC level while reserve the programmability of the traditional RISC based system. This papercovers both the hardware architecture and the software development environment architecture.

  13. A Course on Reconfigurable Processors

    Science.gov (United States)

    Shoufan, Abdulhadi; Huss, Sorin A.

    2010-01-01

    Reconfigurable computing is an established field in computer science. Teaching this field to computer science students demands special attention due to limited student experience in electronics and digital system design. This article presents a compact course on reconfigurable processors, which was offered at the Technische Universitat Darmstadt,…

  14. Higher level trigger systems for the HERA-B experiment

    International Nuclear Information System (INIS)

    The HERA-B experiment is designed for observation of CP violation in the B-meson system at the HERA machine in DESY. The data acquisition and triggering system must cope with a half million detector channels, a 40 MHz interaction rate and a signal to background ratio of 10-10. A highly selective multi-level trigger and high bandwidth data acquisition system has been designed and is currently being implemented. The second-level event buffer and mid-level trigger switch will be built from DSP boards carrying SHARC processors. The second and third level trigger code will run on a farm of 100--200 Pentium processors under Linux. The switch to the 4th level trigger farm will be based on Fast-Ethernet

  15. The Global Second Level Trigger for ZEUS

    International Nuclear Information System (INIS)

    The HERA (Hadron Electron Ring Anlage) collider at DESY in Hamburg is the 1st electron-proton collider ever built. It collides 30 GeV electrons with 820 GeV protons, resulting in centre of mass energies of the order of 300 GeV. The HERA-collider and its physics potential are discussed in this thesis. Physics data-taking with the HERA collider is expected to start in the late spring of 1992. At present two detectors are under construction for the HERA-collider: ZEUS and H1. The ZEUS-detector, and in particular its trigger and data acquisition system, is described in detail. The trigger system is divided into three levels. In both the first and second level trigger, the data from the detector components processors are transferred to the Global First Level Trigger (GFLT) or Global Second Level Trigger (GSLT) respectively. The Global Triggers combine and cross-check the information from the various components and decide to accept or reject the event. In order to study trigger strategies for both the GFLT and GSLT, a computer model of the ZEUS detector was developed. It is shown that a combination of tracking and calorimeter information can be used to reject the background at the second level trigger by a factor of 55 without significant losses in the interesting physics. The hardware implementation and the software for the processors in the GSLT are also described. Finally test results of the GSLT are presented. The maximum (empty) event rate that the GSLT can handle is (3.2±0.2) kHZ. The GSLT introduces a latency of (3.2 ±0.15) ms. The GSLT has been integrated with other components in the ZEUS trigger and data-acquisition system. A variety of tests has been performed and the results are presented. (author). 91 refs.; 77 figs.; 29 tabs

  16. Triggering Artefacts

    DEFF Research Database (Denmark)

    Mogensen, Preben Holst; Robinson, Mike

    1995-01-01

    The paper presents a general critique of the use of conceptual frameworks in design, illustrated by the well known synchronous/asynchronous, co-located/non-co-located framework. It argues that while frameworks are a necessary and inevitable starting point for design, the business of tailoring and...... adapting them to specific situations need not be ad hoc.Triggering artefacts are a way of systematically challenging both designers' preunderstandings and the conservatism of work practice. Experiences from the Great Belt tunnel and bridge project are used to illustrate howtriggering artefacts change...

  17. Processor architecture for Turbo Pascal language

    Energy Technology Data Exchange (ETDEWEB)

    Kofahi, N.A.K.

    1987-01-01

    This dissertation describes the functional design of a high-level language architecture directed towards the execution of programs written in Turbo Pascal language in particular, with the ideas being applied to other block-structured languages in general. The language processor does not require the complex software of compilers, assemblers, and linkage editors in order to run Turbo Pascal source code programs. The language processor can execute Turbo Pascal programs several orders of magnitude faster than conventional systems without language orientation. The Turbo Pascal language processor closely reflects the data and control constructs of the high-level language. The language processor is designed as a pipelined processor in which several dedicated hardware processors are operating at the same time. Other innovations of the language processor are also described. The language processor can make a better use of current developments in Very Large Scale Integration (VLSI) technology.

  18. Trigger Algorithms and Electronics for the ATLAS Muon NSW Upgrade

    CERN Document Server

    Guan, Liang; The ATLAS collaboration

    2015-01-01

    The ATLAS New Small Wheel (NSW), comprising MicroMegas (MMs) and small-strip Thin Gap Chambers (sTGCs), will upgrade the ATLAS muon system for a high background environment. Particularly, the NSW trigger will reduce the rate of fake triggers coming from background tracks in the endcap. We will present an overview of the FPGA-based trigger processor for NSW and trigger algorithms for sTGC and Micromegas detector sub systems. In additional, we will present development of NSW trigger electronics, in particular, the sTGC Trigger Data Serializer (TDS) ASIC, sTGC Pad Trigger board, the sTGC data packet router and L1 Data Driver Card. Finally, we will detail the challenges of meeting the low latency requirements of the trigger system and coping with the high background rates of the HL-LHC.

  19. JPP: A Java Pre-Processor

    OpenAIRE

    Kiniry, Joseph R.; Cheong, Elaine

    1998-01-01

    The Java Pre-Processor, or JPP for short, is a parsing pre-processor for the Java programming language. Unlike its namesake (the C/C++ Pre-Processor, cpp), JPP provides functionality above and beyond simple textual substitution. JPP's capabilities include code beautification, code standard conformance checking, class and interface specification and testing, and documentation generation.

  20. 7 CFR 989.13 - Processor.

    Science.gov (United States)

    2010-01-01

    ... 7 Agriculture 8 2010-01-01 2010-01-01 false Processor. 989.13 Section 989.13 Agriculture Regulations of the Department of Agriculture (Continued) AGRICULTURAL MARKETING SERVICE (Marketing Agreements... CALIFORNIA Order Regulating Handling Definitions § 989.13 Processor. Processor means any person who...

  1. 7 CFR 1215.14 - Processor.

    Science.gov (United States)

    2010-01-01

    ... 7 Agriculture 10 2010-01-01 2010-01-01 false Processor. 1215.14 Section 1215.14 Agriculture Regulations of the Department of Agriculture (Continued) AGRICULTURAL MARKETING SERVICE (MARKETING AGREEMENTS... Processor. Processor means a person engaged in the preparation of unpopped popcorn for the market who...

  2. 7 CFR 927.14 - Processor.

    Science.gov (United States)

    2010-01-01

    ... 7 Agriculture 8 2010-01-01 2010-01-01 false Processor. 927.14 Section 927.14 Agriculture Regulations of the Department of Agriculture (Continued) AGRICULTURAL MARKETING SERVICE (Marketing Agreements... Order Regulating Handling Definitions § 927.14 Processor. Processor means any person who as owner,...

  3. The use of low-cost SMPs in the Atlas level-2 trigger

    CERN Document Server

    Bock, R; Ermolin, Y; Kugel, A; Lay, R; Werner, P

    2000-01-01

    Low-cost SMP (Symmetric Multi-Processor) systems have become generallyavailable since 1998; they provide substantial CPU and I/O capacity along with a memory that is shared by all processors. We have investigated two areas of application in the Atlas level-2 trigger.

  4. Invasive tightly coupled processor arrays

    CERN Document Server

    LARI, VAHID

    2016-01-01

    This book introduces new massively parallel computer (MPSoC) architectures called invasive tightly coupled processor arrays. It proposes strategies, architecture designs, and programming interfaces for invasive TCPAs that allow invading and subsequently executing loop programs with strict requirements or guarantees of non-functional execution qualities such as performance, power consumption, and reliability. For the first time, such a configurable processor array architecture consisting of locally interconnected VLIW processing elements can be claimed by programs, either in full or in part, using the principle of invasive computing. Invasive TCPAs provide unprecedented energy efficiency for the parallel execution of nested loop programs by avoiding any global memory access such as GPUs and may even support loops with complex dependencies such as loop-carried dependencies that are not amenable to parallel execution on GPUs. For this purpose, the book proposes different invasion strategies for claiming a desire...

  5. Online Fastbus processor for LEP

    International Nuclear Information System (INIS)

    The author describes the online computing aspects of Fastbus systems using a processor module which has been developed at CERN and is now available commercially. These General Purpose Master/Slaves (GPMS) are based on 68000/10 (or optionally 68020/68881) processors. Applications include use as event-filters (DELPHI), supervisory controllers, Fastbus stand-alone diagnostic tools, and multiprocessor array components. The direct mapping of single, 32-bit assembly instructions to execute Fastbus protocols makes the use of a GPM both simple and flexible. Loosely coupled processing in Fastbus networks is possible between GPM's as they support access semaphores and use a two port memory as I/O buffer for Fastbus. Both master and slave-ports support block transfers up to 20 Mbytes/s. The CERN standard Fastbus software and the MoniCa symbolic debugging monitor are available on the GPM with real time, multiprocessing support. (Auth.)

  6. The D-Zero Run II Trigger

    International Nuclear Information System (INIS)

    The general purpose D0 collider detector, located at Fermi National Accelerator Laboratory, requires significantly enhanced data acquisition and triggering to operate in the high luminosity (L = 2 x 1032 cm-2 s-1), high rate environment (7 MHz or 132 ns beam crossings) of the upgraded TeVatron proton anti-proton accelerator. This article describes the three major levels and frameworks of the new trigger. Information from the first trigger stage (L1) which includes scintillating, tracking and calorimeter detectors will provide a deadtimeless, 4.2 (micro)s trigger decision with an accept rate of 10 kHz. The second stage (L2), comprised of hardware engines associated with specific detectors and a single global processor will test for correlations between L1 triggers. L2 will have an accept rate of 1 kHz at a maximum deadtime of 5% and require a 100 (micro)s decision time. The third and final stage (L3) will reconstruct events in a farm of processors for a final instantaneous accept rate of 50 Hz

  7. Minimum Bias Trigger in ATLAS

    International Nuclear Information System (INIS)

    Since the restart of the LHC in November 2009, ATLAS has collected inelastic pp collisions to perform first measurements on charged particle densities. These measurements will help to constrain various models describing phenomenologically soft parton interactions. Understanding the trigger efficiencies for different event types are therefore crucial to minimize any possible bias in the event selection. ATLAS uses two main minimum bias triggers, featuring complementary detector components and trigger levels. While a hardware based first trigger level situated in the forward regions with 2.2 < |η| < 3.8 has been proven to select pp-collisions very efficiently, the Inner Detector based minimum bias trigger uses a random seed on filled bunches and central tracking detectors for the event selection. Both triggers were essential for the analysis of kinematic spectra of charged particles. Their performance and trigger efficiency measurements as well as studies on possible bias sources will be presented. We also highlight the advantage of these triggers for particle correlation analyses. (author)

  8. Rhapsody on small processor platforms

    OpenAIRE

    Andersson, Per-Oskar

    2008-01-01

    Rhapsody is a Model-Driven Development (MDD) tool for embedded and real-time system design. The purpose of this thesis is to determine if Rhapsody can be used for software development on small processor platforms such as the Atmel AVR. Rhapsody is normally used on platforms running an operating system. Therefore certain adaptations are needed in order to use it on platforms without an operating system. These adaptations and their affect on the usability of the tool, advantages and disadvantag...

  9. Jet-like correlations with neutral pion triggers in pp and central Pb-Pb collisions at 2.76 TeV

    CERN Document Server

    Adam, Jaroslav; Aggarwal, Madan Mohan; Aglieri Rinella, Gianluca; Agnello, Michelangelo; Agrawal, Neelima; Ahammed, Zubayer; Ahmad, Shakeel; Ahn, Sang Un; Aiola, Salvatore; Akindinov, Alexander; Alam, Sk Noor; Silva De Albuquerque, Danilo; Aleksandrov, Dmitry; Alessandro, Bruno; Alexandre, Didier; Alfaro Molina, Jose Ruben; Alici, Andrea; Alkin, Anton; Alme, Johan; Alt, Torsten; Altinpinar, Sedat; Altsybeev, Igor; Alves Garcia Prado, Caio; An, Mangmang; Andrei, Cristian; Andrews, Harry Arthur; Andronic, Anton; Anguelov, Venelin; Anson, Christopher Daniel; Anticic, Tome; Antinori, Federico; Antonioli, Pietro; Aphecetche, Laurent Bernard; Appelshaeuser, Harald; Arcelli, Silvia; Arnaldi, Roberta; Arnold, Oliver Werner; Arsene, Ionut Cristian; Arslandok, Mesut; Audurier, Benjamin; Augustinus, Andre; Averbeck, Ralf Peter; Azmi, Mohd Danish; Badala, Angela; Baek, Yong Wook; Bagnasco, Stefano; Bailhache, Raphaelle Marie; Bala, Renu; Balasubramanian, Supraja; Baldisseri, Alberto; Baral, Rama Chandra; Barbano, Anastasia Maria; Barbera, Roberto; Barile, Francesco; Barnafoldi, Gergely Gabor; Barnby, Lee Stuart; Ramillien Barret, Valerie; Bartalini, Paolo; Barth, Klaus; Bartke, Jerzy Gustaw; Bartsch, Esther; Basile, Maurizio; Bastid, Nicole; Basu, Sumit; Bathen, Bastian; Batigne, Guillaume; Batista Camejo, Arianna; Batyunya, Boris; Batzing, Paul Christoph; Bearden, Ian Gardner; Beck, Hans; Bedda, Cristina; Behera, Nirbhay Kumar; Belikov, Iouri; Bellini, Francesca; Bello Martinez, Hector; Bellwied, Rene; Belmont Moreno, Ernesto; Espinoza Beltran, Lucina Gabriela; Belyaev, Vladimir; Bencedi, Gyula; Beole, Stefania; Berceanu, Ionela; Bercuci, Alexandru; Berdnikov, Yaroslav; Berenyi, Daniel; Bertens, Redmer Alexander; Berzano, Dario; Betev, Latchezar; Bhasin, Anju; Bhat, Inayat Rasool; Bhati, Ashok Kumar; Bhattacharjee, Buddhadeb; Bhom, Jihyun; Bianchi, Livio; Bianchi, Nicola; Bianchin, Chiara; Bielcik, Jaroslav; Bielcikova, Jana; Bilandzic, Ante; Biro, Gabor; Biswas, Rathijit; Biswas, Saikat; Bjelogrlic, Sandro; Blair, Justin Thomas; Blau, Dmitry; Blume, Christoph; Bock, Friederike; Bogdanov, Alexey; Boggild, Hans; Boldizsar, Laszlo; Bombara, Marek; Bonora, Matthias; Book, Julian Heinz; Borel, Herve; Borissov, Alexander; Borri, Marcello; Bossu, Francesco; Botta, Elena; Bourjau, Christian; Braun-munzinger, Peter; Bregant, Marco; Broker, Theo Alexander; Browning, Tyler Allen; Broz, Michal; Brucken, Erik Jens; Bruna, Elena; Bruno, Giuseppe Eugenio; Budnikov, Dmitry; Buesching, Henner; Bufalino, Stefania; Buhler, Paul; Buncic, Predrag; Busch, Oliver; Buthelezi, Edith Zinhle; Bashir Butt, Jamila; Buxton, Jesse Thomas; Cabala, Jan; Caffarri, Davide; Cai, Xu; Caines, Helen Louise; Caliva, Alberto; Calvo Villar, Ernesto; Camerini, Paolo; Carena, Francesco; Carena, Wisla; Carnesecchi, Francesca; Castillo Castellanos, Javier Ernesto; Castro, Andrew John; Casula, Ester Anna Rita; Ceballos Sanchez, Cesar; Cepila, Jan; Cerello, Piergiorgio; Cerkala, Jakub; Chang, Beomsu; Chapeland, Sylvain; Chartier, Marielle; Charvet, Jean-luc Fernand; Chattopadhyay, Subhasis; Chattopadhyay, Sukalyan; Chauvin, Alex; Chelnokov, Volodymyr; Cherney, Michael Gerard; Cheshkov, Cvetan Valeriev; Cheynis, Brigitte; Chibante Barroso, Vasco Miguel; Dobrigkeit Chinellato, David; Cho, Soyeon; Chochula, Peter; Choi, Kyungeon; Chojnacki, Marek; Choudhury, Subikash; Christakoglou, Panagiotis; Christensen, Christian Holm; Christiansen, Peter; Chujo, Tatsuya; Chung, Suh-urk; Cicalo, Corrado; Cifarelli, Luisa; Cindolo, Federico; Cleymans, Jean Willy Andre; Colamaria, Fabio Filippo; Colella, Domenico; Collu, Alberto; Colocci, Manuel; Conesa Balbastre, Gustavo; Conesa Del Valle, Zaida; Connors, Megan Elizabeth; Contreras Nuno, Jesus Guillermo; Cormier, Thomas Michael; Corrales Morales, Yasser; Cortes Maldonado, Ismael; Cortese, Pietro; Cosentino, Mauro Rogerio; Costa, Filippo; Crkovska, Jana; Crochet, Philippe; Cruz Albino, Rigoberto; Cuautle Flores, Eleazar; Cunqueiro Mendez, Leticia; Dahms, Torsten; Dainese, Andrea; Danisch, Meike Charlotte; Danu, Andrea; Das, Debasish; Das, Indranil; Das, Supriya; Dash, Ajay Kumar; Dash, Sadhana; De, Sudipan; De Caro, Annalisa; De Cataldo, Giacinto; De Conti, Camila; De Cuveland, Jan; De Falco, Alessandro; De Gruttola, Daniele; De Marco, Nora; De Pasquale, Salvatore; Derradi De Souza, Rafael; Deisting, Alexander; Deloff, Andrzej; Deplano, Caterina; Dhankher, Preeti; Di Bari, Domenico; Di Mauro, Antonio; Di Nezza, Pasquale; Di Ruzza, Benedetto; Diaz Corchero, Miguel Angel; Dietel, Thomas; Dillenseger, Pascal; Divia, Roberto; Djuvsland, Oeystein; Dobrin, Alexandru Florin; Domenicis Gimenez, Diogenes; Donigus, Benjamin; Dordic, Olja; Drozhzhova, Tatiana; Dubey, Anand Kumar; Dubla, Andrea; Ducroux, Laurent; Duggal, Ashpreet Kaur; Dupieux, Pascal; Ehlers Iii, Raymond James; Elia, Domenico; Endress, Eric; Engel, Heiko; Epple, Eliane; Erazmus, Barbara Ewa; Erhardt, Filip; Espagnon, Bruno; Estienne, Magali Danielle; Esumi, Shinichi; Eulisse, Giulio; Eum, Jongsik; Evans, David; Evdokimov, Sergey; Eyyubova, Gyulnara; Fabbietti, Laura; Fabris, Daniela; Faivre, Julien; Fantoni, Alessandra; Fasel, Markus; Feldkamp, Linus; Feliciello, Alessandro; Feofilov, Grigorii; Ferencei, Jozef; Fernandez Tellez, Arturo; Gonzalez Ferreiro, Elena; Ferretti, Alessandro; Festanti, Andrea; Feuillard, Victor Jose Gaston; Figiel, Jan; Araujo Silva Figueredo, Marcel; Filchagin, Sergey; Finogeev, Dmitry; Fionda, Fiorella; Fiore, Enrichetta Maria; Floris, Michele; Foertsch, Siegfried Valentin; Foka, Panagiota; Fokin, Sergey; Fragiacomo, Enrico; Francescon, Andrea; Francisco, Audrey; Frankenfeld, Ulrich Michael; Fronze, Gabriele Gaetano; Fuchs, Ulrich; Furget, Christophe; Furs, Artur; Fusco Girard, Mario; Gaardhoeje, Jens Joergen; Gagliardi, Martino; Gago Medina, Alberto Martin; Gajdosova, Katarina; Gallio, Mauro; Duarte Galvan, Carlos; Gangadharan, Dhevan Raja; Ganoti, Paraskevi; Gao, Chaosong; Garabatos Cuadrado, Jose; Garcia-solis, Edmundo Javier; Garg, Kunal; Garg, Prakhar; Gargiulo, Corrado; Gasik, Piotr Jan; Gauger, Erin Frances; Germain, Marie; Gheata, Mihaela; Ghosh, Premomoy; Ghosh, Sanjay Kumar; Gianotti, Paola; Giubellino, Paolo; Giubilato, Piero; Gladysz-dziadus, Ewa; Glassel, Peter; Gomez Coral, Diego Mauricio; Gomez Ramirez, Andres; Sanchez Gonzalez, Andres; Gonzalez, Victor; Gonzalez Zamora, Pedro; Gorbunov, Sergey; Gorlich, Lidia Maria; Gotovac, Sven; Grabski, Varlen; Grachov, Oleg Anatolievich; Graczykowski, Lukasz Kamil; Graham, Katie Leanne; Grelli, Alessandro; Grigoras, Costin; Grigoryev, Vladislav; Grigoryan, Ara; Grigoryan, Smbat; Grynyov, Borys; Grion, Nevio; Gronefeld, Julius Maximilian; Grosse-oetringhaus, Jan Fiete; Grosso, Raffaele; Gruber, Lukas; Guber, Fedor; Guernane, Rachid; Guerzoni, Barbara; Gulbrandsen, Kristjan Herlache; Gunji, Taku; Gupta, Anik; Gupta, Ramni; Bautista Guzman, Irais; Haake, Rudiger; Hadjidakis, Cynthia Marie; Haiduc, Maria; Hamagaki, Hideki; Hamar, Gergoe; Hamon, Julien Charles; Harris, John William; Harton, Austin Vincent; Hatzifotiadou, Despina; Hayashi, Shinichi; Heckel, Stefan Thomas; Hellbar, Ernst; Helstrup, Haavard; Herghelegiu, Andrei Ionut; Herrera Corral, Gerardo Antonio; Herrmann, Florian; Hess, Benjamin Andreas; Hetland, Kristin Fanebust; Hillemanns, Hartmut; Hippolyte, Boris; Horak, David; Hosokawa, Ritsuya; Hristov, Peter Zahariev; Hughes, Charles; Humanic, Thomas; Hussain, Nur; Hussain, Tahir; Hutter, Dirk; Hwang, Dae Sung; Ilkaev, Radiy; Inaba, Motoi; Incani, Elisa; Ippolitov, Mikhail; Irfan, Muhammad; Isakov, Vladimir; Ivanov, Marian; Ivanov, Vladimir; Izucheev, Vladimir; Jacak, Barbara; Jacazio, Nicolo; Jacobs, Peter Martin; Jadhav, Manoj Bhanudas; Jadlovska, Slavka; Jadlovsky, Jan; Jahnke, Cristiane; Jakubowska, Monika Joanna; Janik, Malgorzata Anna; Pahula Hewage, Sandun; Jena, Chitrasen; Jena, Satyajit; Jimenez Bustamante, Raul Tonatiuh; Jones, Peter Graham; Jung, Hyungtaik; Jusko, Anton; Kalinak, Peter; Kalweit, Alexander Philipp; Kang, Ju Hwan; Kaplin, Vladimir; Kar, Somnath; Karasu Uysal, Ayben; Karavichev, Oleg; Karavicheva, Tatiana; Karayan, Lilit; Karpechev, Evgeny; Kebschull, Udo Wolfgang; Keidel, Ralf; Keijdener, Darius Laurens; Keil, Markus; Khan, Mohammed Mohisin; Khan, Palash; Khan, Shuaib Ahmad; Khanzadeev, Alexei; Kharlov, Yury; Khatun, Anisa; Khuntia, Arvind; Kileng, Bjarte; Kim, Do Won; Kim, Dong Jo; Kim, Daehyeok; Kim, Hyeonjoong; Kim, Jinsook; Kim, Jiyoung; Kim, Minjung; Kim, Minwoo; Kim, Se Yong; Kim, Taesoo; Kirsch, Stefan; Kisel, Ivan; Kiselev, Sergey; Kisiel, Adam Ryszard; Kiss, Gabor; Klay, Jennifer Lynn; Klein, Carsten; Klein, Jochen; Klein-boesing, Christian; Klewin, Sebastian; Kluge, Alexander; Knichel, Michael Linus; Knospe, Anders Garritt; Kobdaj, Chinorat; Kofarago, Monika; Kollegger, Thorsten; Kolozhvari, Anatoly; Kondratev, Valerii; Kondratyeva, Natalia; Kondratyuk, Evgeny; Konevskikh, Artem; Kopcik, Michal; Kour, Mandeep; Kouzinopoulos, Charalampos; Kovalenko, Oleksandr; Kovalenko, Vladimir; Kowalski, Marek; Koyithatta Meethaleveedu, Greeshma; Kralik, Ivan; Kravcakova, Adela; Krivda, Marian; Krizek, Filip; Kryshen, Evgeny; Krzewicki, Mikolaj; Kubera, Andrew Michael; Kucera, Vit; Kuhn, Christian Claude; Kuijer, Paulus Gerardus; Kumar, Ajay; Kumar, Jitendra; Kumar, Lokesh; Kumar, Shyam; Kundu, Sourav; Kurashvili, Podist; Kurepin, Alexander; Kurepin, Alexey; Kuryakin, Alexey; Kweon, Min Jung; Kwon, Youngil; La Pointe, Sarah Louise; La Rocca, Paola; Lagana Fernandes, Caio; Lakomov, Igor; Langoy, Rune; Lapidus, Kirill; Lara Martinez, Camilo Ernesto; Lardeux, Antoine Xavier; Lattuca, Alessandra; Laudi, Elisa; Lazaridis, Lazaros; Lea, Ramona; Leardini, Lucia; Lee, Seongjoo; Lehas, Fatiha; Lehner, Sebastian; Lehrbach, Johannes; Lemmon, Roy Crawford; Lenti, Vito; Leogrande, Emilia; Leon Monzon, Ildefonso; Leon Vargas, Hermes; Leoncino, Marco; Levai, Peter; Li, Shuang; Li, Xiaomei; Lien, Jorgen Andre; Lietava, Roman; Lindal, Svein; Lindenstruth, Volker; Lippmann, Christian; Lisa, Michael Annan; Ljunggren, Hans Martin; Lodato, Davide Francesco; Lonne, Per-ivar; Loginov, Vitaly; Loizides, Constantinos; Lopez, Xavier Bernard; Lopez Torres, Ernesto; Lowe, Andrew John; Luettig, Philipp Johannes; Lunardon, Marcello; Luparello, Grazia; Lupi, Matteo; Lutz, Tyler Harrison; Maevskaya, Alla; Mager, Magnus; Mahajan, Sanjay; Mahmood, Sohail Musa; Maire, Antonin; Majka, Richard Daniel; Malaev, Mikhail; Maldonado Cervantes, Ivonne Alicia; Malinina, Liudmila; Mal'kevich, Dmitry; Malzacher, Peter; Mamonov, Alexander; Manko, Vladislav; Manso, Franck; Manzari, Vito; Mao, Yaxian; Marchisone, Massimiliano; Mares, Jiri; Margagliotti, Giacomo Vito; Margotti, Anselmo; Margutti, Jacopo; Marin, Ana Maria; Markert, Christina; Marquard, Marco; Martin, Nicole Alice; Martinengo, Paolo; Martinez Hernandez, Mario Ivan; Martinez-garcia, Gines; Martinez Pedreira, Miguel; Mas, Alexis Jean-michel; Masciocchi, Silvia; Masera, Massimo; Masoni, Alberto; Mastroserio, Annalisa; Matyja, Adam Tomasz; Mayer, Christoph; Mazer, Joel Anthony; Mazzilli, Marianna; Mazzoni, Alessandra Maria; Meddi, Franco; Melikyan, Yuri; Menchaca-rocha, Arturo Alejandro; Meninno, Elisa; Mercado-perez, Jorge; Meres, Michal; Mhlanga, Sibaliso; Miake, Yasuo; Mieskolainen, Matti Mikael; Mikhaylov, Konstantin; Milosevic, Jovan; Mischke, Andre; Mishra, Aditya Nath; Mishra, Tribeni; Miskowiec, Dariusz Czeslaw; Mitra, Jubin; Mitu, Ciprian Mihai; Mohammadi, Naghmeh; Mohanty, Bedangadas; Molnar, Levente; Montes Prado, Esther; Moreira De Godoy, Denise Aparecida; Perez Moreno, Luis Alberto; Moretto, Sandra; Morreale, Astrid; Morsch, Andreas; Muccifora, Valeria; Mudnic, Eugen; Muhlheim, Daniel Michael; Muhuri, Sanjib; Mukherjee, Maitreyee; Mulligan, James Declan; Gameiro Munhoz, Marcelo; Munning, Konstantin; Munzer, Robert Helmut; Murakami, Hikari; Murray, Sean; Musa, Luciano; Musinsky, Jan; Naik, Bharati; Nair, Rahul; Nandi, Basanta Kumar; Nania, Rosario; Nappi, Eugenio; Naru, Muhammad Umair; Ferreira Natal Da Luz, Pedro Hugo; Nattrass, Christine; Rosado Navarro, Sebastian; Nayak, Kishora; Nayak, Ranjit; Nayak, Tapan Kumar; Nazarenko, Sergey; Nedosekin, Alexander; Negrao De Oliveira, Renato Aparecido; Nellen, Lukas; Ng, Fabian; Nicassio, Maria; Niculescu, Mihai; Niedziela, Jeremi; Nielsen, Borge Svane; Nikolaev, Sergey; Nikulin, Sergey; Nikulin, Vladimir; Noferini, Francesco; Nomokonov, Petr; Nooren, Gerardus; Cabanillas Noris, Juan Carlos; Norman, Jaime; Nyanin, Alexander; Nystrand, Joakim Ingemar; Oeschler, Helmut Oskar; Oh, Saehanseul; Oh, Sun Kun; Ohlson, Alice Elisabeth; Okatan, Ali; Okubo, Tsubasa; Oleniacz, Janusz; Oliveira Da Silva, Antonio Carlos; Oliver, Michael Henry; Onderwaater, Jacobus; Oppedisano, Chiara; Orava, Risto; Oravec, Matej; Ortiz Velasquez, Antonio; Oskarsson, Anders Nils Erik; Otwinowski, Jacek Tomasz; Oyama, Ken; Ozdemir, Mahmut; Pachmayer, Yvonne Chiara; Pagano, Davide; Pagano, Paola; Paic, Guy; Pal, Susanta Kumar; Palni, Prabhakar; Pan, Jinjin; Pandey, Ashutosh Kumar; Papikyan, Vardanush; Pappalardo, Giuseppe; Pareek, Pooja; Park, Jonghan; Park, Woojin; Parmar, Sonia; Passfeld, Annika; Paticchio, Vincenzo; Patra, Rajendra Nath; Paul, Biswarup; Pei, Hua; Peitzmann, Thomas; Peng, Xinye; Pereira Da Costa, Hugo Denis Antonio; Peresunko, Dmitry Yurevich; Perez Lezama, Edgar; Peskov, Vladimir; Pestov, Yury; Petracek, Vojtech; Petrov, Viacheslav; Petrovici, Mihai; Petta, Catia; Piano, Stefano; Pikna, Miroslav; Pillot, Philippe; Ozelin De Lima Pimentel, Lais; Pinazza, Ombretta; Pinsky, Lawrence; Piyarathna, Danthasinghe; Ploskon, Mateusz Andrzej; Planinic, Mirko; Pluta, Jan Marian; Pochybova, Sona; Podesta Lerma, Pedro Luis Manuel; Poghosyan, Martin; Polishchuk, Boris; Poljak, Nikola; Poonsawat, Wanchaloem; Pop, Amalia; Poppenborg, Hendrik; Porteboeuf, Sarah Julie; Porter, R Jefferson; Pospisil, Jan; Prasad, Sidharth Kumar; Preghenella, Roberto; Prino, Francesco; Pruneau, Claude Andre; Pshenichnov, Igor; Puccio, Maximiliano; Puddu, Giovanna; Pujahari, Prabhat Ranjan; Punin, Valery; Putschke, Jorn Henning; Qvigstad, Henrik; Rachevski, Alexandre; Raha, Sibaji; Rajput, Sonia; Rak, Jan; Rakotozafindrabe, Andry Malala; Ramello, Luciano; Rami, Fouad; Raniwala, Rashmi; Raniwala, Sudhir; Rasanen, Sami Sakari; Rascanu, Bogdan Theodor; Rathee, Deepika; Ratza, Viktor; Ravasenga, Ivan; Read, Kenneth Francis; Redlich, Krzysztof; Rehman, Attiq Ur; Reichelt, Patrick Simon; Reidt, Felix; Ren, Xiaowen; Renfordt, Rainer Arno Ernst; Reolon, Anna Rita; Reshetin, Andrey; Reygers, Klaus Johannes; Riabov, Viktor; Ricci, Renato Angelo; Richert, Tuva Ora Herenui; Richter, Matthias Rudolph; Riedler, Petra; Riegler, Werner; Riggi, Francesco; Ristea, Catalin-lucian; Rodriguez Cahuantzi, Mario; Roeed, Ketil; Rogochaya, Elena; Rohr, David Michael; Roehrich, Dieter; Ronchetti, Federico; Ronflette, Lucile; Rosnet, Philippe; Rossi, Andrea; Roukoutakis, Filimon; Roy, Ankhi; Roy, Christelle Sophie; Roy, Pradip Kumar; Rubio Montero, Antonio Juan; Rui, Rinaldo; Russo, Riccardo; Ryabinkin, Evgeny; Ryabov, Yury; Rybicki, Andrzej; Saarinen, Sampo; Sadhu, Samrangy; Sadovskiy, Sergey; Safarik, Karel; Sahlmuller, Baldo; Sahoo, Pragati; Sahoo, Raghunath; Sahoo, Sarita; Sahu, Pradip Kumar; Saini, Jogender; Sakai, Shingo; Saleh, Mohammad Ahmad; Salzwedel, Jai Samuel Nielsen; Sambyal, Sanjeev Singh; Samsonov, Vladimir; Sandor, Ladislav; Sandoval, Andres; Sano, Masato; Sarkar, Debojit; Sarkar, Nachiketa; Sarma, Pranjal; Scapparone, Eugenio; Scarlassara, Fernando; Schiaua, Claudiu Cornel; Schicker, Rainer Martin; Schmidt, Christian Joachim; Schmidt, Hans Rudolf; Schmidt, Martin; Schukraft, Jurgen; Schutz, Yves Roland; Schwarz, Kilian Eberhard; Schweda, Kai Oliver; Scioli, Gilda; Scomparin, Enrico; Scott, Rebecca Michelle; Sefcik, Michal; Seger, Janet Elizabeth; Sekiguchi, Yuko; Sekihata, Daiki; Selyuzhenkov, Ilya; Senosi, Kgotlaesele; Senyukov, Serhiy; Serradilla Rodriguez, Eulogio; Sevcenco, Adrian; Shabanov, Arseniy; Shabetai, Alexandre; Shadura, Oksana; Shahoyan, Ruben; Shangaraev, Artem; Sharma, Ankita; Sharma, Anjali; Sharma, Mona; Sharma, Monika; Sharma, Natasha; Sheikh, Ashik Ikbal; Shigaki, Kenta; Shou, Qiye; Shtejer Diaz, Katherin; Sibiryak, Yury; Siddhanta, Sabyasachi; Sielewicz, Krzysztof Marek; Siemiarczuk, Teodor; Silvermyr, David Olle Rickard; Silvestre, Catherine Micaela; Simatovic, Goran; Simonetti, Giuseppe; Singaraju, Rama Narayana; Singh, Ranbir; Singhal, Vikas; Sarkar - Sinha, Tinku; Sitar, Branislav; Sitta, Mario; Skaali, Bernhard; Slupecki, Maciej; Smirnov, Nikolai; Snellings, Raimond; Snellman, Tomas Wilhelm; Song, Jihye; Song, Myunggeun; Song, Zixuan; Soramel, Francesca; Sorensen, Soren Pontoppidan; Sozzi, Federica; Spiriti, Eleuterio; Sputowska, Iwona Anna; Spyropoulou-stassinaki, Martha; Stachel, Johanna; Stan, Ionel; Stankus, Paul; Stenlund, Evert Anders; Steyn, Gideon Francois; Stiller, Johannes Hendrik; Stocco, Diego; Strmen, Peter; Alarcon Do Passo Suaide, Alexandre; Sugitate, Toru; Suire, Christophe Pierre; Suleymanov, Mais Kazim Oglu; Suljic, Miljenko; Sultanov, Rishat; Sumbera, Michal; Sumowidagdo, Suharyo; Suzuki, Ken; Swain, Sagarika; Szabo, Alexander; Szarka, Imrich; Szczepankiewicz, Adam; Szymanski, Maciej Pawel; Tabassam, Uzma; Takahashi, Jun; Tambave, Ganesh Jagannath; Tanaka, Naoto; Tarhini, Mohamad; Tariq, Mohammad; Tarzila, Madalina-gabriela; Tauro, Arturo; Tejeda Munoz, Guillermo; Telesca, Adriana; Terasaki, Kohei; Terrevoli, Cristina; Teyssier, Boris; Thaeder, Jochen Mathias; Thakur, Dhananjaya; Thomas, Deepa; Tieulent, Raphael Noel; Tikhonov, Anatoly; Timmins, Anthony Robert; Toia, Alberica; Tripathy, Sushanta; Trogolo, Stefano; Trombetta, Giuseppe; Trubnikov, Victor; Trzaska, Wladyslaw Henryk; Tsuji, Tomoya; Tumkin, Alexandr; Turrisi, Rosario; Tveter, Trine Spedstad; Ullaland, Kjetil; Uras, Antonio; Usai, Gianluca; Utrobicic, Antonija; Vala, Martin; Van Der Maarel, Jasper; Van Hoorne, Jacobus Willem; Van Leeuwen, Marco; Vanat, Tomas; Vande Vyvre, Pierre; Varga, Dezso; Varga, Michal; Vargas Trevino, Aurora Diozcora; Vargyas, Marton; Varma, Raghava; Vasileiou, Maria; Vasiliev, Andrey; Vauthier, Astrid; Vazquez Doce, Oton; Vechernin, Vladimir; Veen, Annelies Marianne; Velure, Arild; Vercellin, Ermanno; Vergara Limon, Sergio; Vernet, Renaud; Vertesi, Robert; Vickovic, Linda; Vigolo, Sonia; Viinikainen, Jussi Samuli; Vilakazi, Zabulon; Villalobos Baillie, Orlando; Villatoro Tello, Abraham; Vinogradov, Alexander; Vinogradov, Leonid; Virgili, Tiziano; Vislavicius, Vytautas; Vodopyanov, Alexander; Volkl, Martin Andreas; Voloshin, Kirill; Voloshin, Sergey; Volpe, Giacomo; Von Haller, Barthelemy; Vorobyev, Ivan; Voscek, Dominik; Vranic, Danilo; Vrlakova, Janka; Vulpescu, Bogdan; Wagner, Boris; Wagner, Jan; Wang, Hongkai; Wang, Mengliang; Watanabe, Daisuke; Watanabe, Yosuke; Weber, Michael; Weber, Steffen Georg; Weiser, Dennis Franz; Wessels, Johannes Peter; Westerhoff, Uwe; Whitehead, Andile Mothegi; Wiechula, Jens; Wikne, Jon; Wilk, Grzegorz Andrzej; Wilkinson, Jeremy John; Willems, Guido Alexander; Williams, Crispin; Windelband, Bernd Stefan; Winn, Michael Andreas; Yalcin, Serpil; Yang, Ping; Yano, Satoshi; Yin, Zhongbao; Yokoyama, Hiroki; Yoo, In-kwon; Yoon, Jin Hee; Yurchenko, Volodymyr; Zaccolo, Valentina; Zaman, Ali; Zampolli, Chiara; Correia Zanoli, Henrique Jose; Zaporozhets, Sergey; Zardoshti, Nima; Zarochentsev, Andrey; Zavada, Petr; Zavyalov, Nikolay; Zbroszczyk, Hanna Paulina; Zgura, Sorin Ion; Zhalov, Mikhail; Zhang, Haitao; Zhang, Xiaoming; Zhang, Yonghong; Chunhui, Zhang; Zhang, Zuman; Zhao, Chengxin; Zhigareva, Natalia; Zhou, Daicui; Zhou, You; Zhou, Zhuo; Zhu, Hongsheng; Zhu, Jianhui; Zhu, Xiangrong; Zichichi, Antonino; Zimmermann, Alice; Zimmermann, Markus Bernhard; Zinovjev, Gennady; Zmeskal, Johann; Zyzak, Maksym

    2016-01-01

    We present measurements of two-particle correlations with neutral pion trigger particles of transverse momenta $8 3~\\mathrm{GeV}/c$, while with decreasing momenta an enhancement develops reaching about $5$ at low $p_{\\mathrm{T}}^{\\rm assoc}$. On the near side, an enhancement of $I_{\\mathrm{AA}}$ between $1.2$ at the highest to $1.8$ at the lowest $p_{\\mathrm{T}}^{\\rm assoc}$ is observed. The data are compared to parton-energy-loss predictions of the JEWEL and AMPT event generators, as well as to a perturbative QCD calculation with medium-modified fragmentation functions. All calculations qualitatively describe the away-side suppression at high $p_{\\mathrm{T}}^{\\rm assoc}$. Only AMPT captures the enhancement at low $p_{\\mathrm{T}}^{\\rm assoc}$, both on the near and away side. However, it also underpredicts $I_{\\mathrm{AA}}$ above $5$ GeV/$c$, in particular on the near-side.

  10. Speculative segmented sum for sparse matrix-vector multiplication on heterogeneous processors

    DEFF Research Database (Denmark)

    Liu, Weifeng; Vinter, Brian

    2015-01-01

    of the same chip is triggered to re-arrange the predicted partial sums for a correct resulting vector. On three heterogeneous processors from Intel, AMD and nVidia, using 20 sparse matrices as a benchmark suite, the experimental results show that our method obtains significant performance improvement...

  11. Design Principles for Synthesizable Processor Cores

    DEFF Research Database (Denmark)

    Schleuniger, Pascal; McKee, Sally A.; Karlsson, Sven

    2012-01-01

    As FPGAs get more competitive, synthesizable processor cores become an attractive choice for embedded computing. Currently popular commercial processor cores do not fully exploit current FPGA architectures. In this paper, we propose general design principles to increase instruction throughput on...... FPGA-based processor cores: first, superpipelining enables higher-frequency system clocks, and second, predicated instructions circumvent costly pipeline stalls due to branches. To evaluate their effects, we develop Tinuso, a processor architecture optimized for FPGA implementation. We demonstrate...... through the use of micro-benchmarks that our principles guide the design of a processor core that improves performance by an average of 38% over a similar Xilinx MicroBlaze configuration....

  12. Communications systems and methods for subsea processors

    Energy Technology Data Exchange (ETDEWEB)

    Gutierrez, Jose; Pereira, Luis

    2016-04-26

    A subsea processor may be located near the seabed of a drilling site and used to coordinate operations of underwater drilling components. The subsea processor may be enclosed in a single interchangeable unit that fits a receptor on an underwater drilling component, such as a blow-out preventer (BOP). The subsea processor may issue commands to control the BOP and receive measurements from sensors located throughout the BOP. A shared communications bus may interconnect the subsea processor and underwater components and the subsea processor and a surface or onshore network. The shared communications bus may be operated according to a time division multiple access (TDMA) scheme.

  13. Firearm trigger assembly

    Science.gov (United States)

    Crandall, David L.; Watson, Richard W.

    2010-02-16

    A firearm trigger assembly for use with a firearm includes a trigger mounted to a forestock of the firearm so that the trigger is movable between a rest position and a triggering position by a forwardly placed support hand of a user. An elongated trigger member operatively associated with the trigger operates a sear assembly of the firearm when the trigger is moved to the triggering position. An action release assembly operatively associated with the firearm trigger assembly and a movable assembly of the firearm prevents the trigger from being moved to the triggering position when the movable assembly is not in the locked position.

  14. Operation of the enhanced ATLAS First Level Calorimeter Trigger at the start of Run-2

    CERN Document Server

    Palka, Marek; The ATLAS collaboration

    2015-01-01

    In 2015 the LHC will operate with a higher center-of-mass energy and proton beams luminosity. To keep a high trigger efficiency against an increased event rate, part of ATLAS Level-1 Calorimeter Trigger electronics have been re-designed or newly introduced (Pre-Processors, Merging Modules and Topological Processors). Additionally, to achieve the best possible resolution for the reconstructed physics objects, complex calibration and monitoring systems are employed. Hit rates and energy spectra down to channel level, based on reconstructed events, are supervised with the calorimeter trigger hardware. The performance of the upgraded Level-1 Calorimeter Trigger at the beginning of LHC Run-2 is illustrated.

  15. Taxonomy of Data Prefetching for Multicore Processors

    Institute of Scientific and Technical Information of China (English)

    Surendra Byna; Yong Chen; Xian-He Sun

    2009-01-01

    Data prefetching is an effective data access latency hiding technique to mask the CPU stall caused by cache misses and to bridge the performance gap between processor and memory. With hardware and/or software support, data prefetching brings data closer to a processor before it is actually needed. Many prefetching techniques have been developed for single-core processors. Recent developments in processor technology have brought multicore processors into mainstream.While some of the single-core prefetching techniques are directly applicable to multicore processors, numerous novel strategies have been proposed in the past few years to take advantage of multiple cores. This paper aims to provide a comprehensive review of the state-of-the-art prefetching techniques, and proposes a taxonomy that classifies various design concerns in developing a prefetching strategy, especially for multicore processors. We compare various existing methods through analysis as well.

  16. AFFECT OF PARALLEL COMPUTING ON MULTICORE PROCESSORS

    Directory of Open Access Journals (Sweden)

    V R Rao Konkimalla

    2013-02-01

    Full Text Available Our main aim of research is to find the limit of Amdahl's Law for multicore processors, to make number of cores giving more efficiency to overall architecture of the CMP(Chip Multi Processor a.k.a. Multicore Processor. As it is expected this limit will be in the architecture of Multicore Processor, or in the programming. We surveyed the architecture of the Multicore processors of various chip manufacturers namely INTEL™, AMD™, IBM™ etc., and the various techniques there followed in, for improving the performance of the Multicore Processors. We conducted cluster experiments to find this limit. In this paper we propose an alternate design of Multicore processor based on the results of our cluster experiment.

  17. The multilevel trigger system of the DIRAC experiment

    International Nuclear Information System (INIS)

    The multilevel trigger system of the DIRAC experiment at CERN is presented. It includes a fast first level trigger as well as various trigger processors to select events with a pair of pions having a low relative momentum typical of the physical process under study. One of these processors employs the drift chamber data, another one is based on a neural network algorithm and the others use various hit-map detector correlations. Two versions of the trigger system used at different stages of the experiment are described. The complete system reduces the event rate by a factor of 1000, with efficiency ≥ 95 % of detecting the events in the relative momentum range of interest

  18. The Database Query Support Processor (QSP)

    Science.gov (United States)

    1993-01-01

    The number and diversity of databases available to users continues to increase dramatically. Currently, the trend is towards decentralized, client server architectures that (on the surface) are less expensive to acquire, operate, and maintain than information architectures based on centralized, monolithic mainframes. The database query support processor (QSP) effort evaluates the performance of a network level, heterogeneous database access capability. Air Force Material Command's Rome Laboratory has developed an approach, based on ANSI standard X3.138 - 1988, 'The Information Resource Dictionary System (IRDS)' to seamless access to heterogeneous databases based on extensions to data dictionary technology. To successfully query a decentralized information system, users must know what data are available from which source, or have the knowledge and system privileges necessary to find out this information. Privacy and security considerations prohibit free and open access to every information system in every network. Even in completely open systems, time required to locate relevant data (in systems of any appreciable size) would be better spent analyzing the data, assuming the original question was not forgotten. Extensions to data dictionary technology have the potential to more fully automate the search and retrieval for relevant data in a decentralized environment. Substantial amounts of time and money could be saved by not having to teach users what data resides in which systems and how to access each of those systems. Information describing data and how to get it could be removed from the application and placed in a dedicated repository where it belongs. The result simplified applications that are less brittle and less expensive to build and maintain. Software technology providing the required functionality is off the shelf. The key difficulty is in defining the metadata required to support the process. The database query support processor effort will provide

  19. Parallel Neutrino Triggers using GPUs for an underwater telescope

    OpenAIRE

    Bouhadef, Bachir; Morganti, Mauro; Terreni, Giuseppe; KM3Net-It Collaboration

    2015-01-01

    Graphics Processing Units are high performance co-processors originally intended to improve the use and the acceleration of computer graphics applications. Because of their performance, researchers have extended their use beyond the computer graphics scope. We have investigated the possibility of implementing online neutrino trigger algorithms in the KM3Net-It experiment using a CPU-GPU system. The results of a neutrino trigger simulation on a NEMO Phase II tower and a KM3-It 14 floors tower ...

  20. Parallel Neutrino Triggers using GPUs for an underwater telescope

    OpenAIRE

    Bouhadef, Bachir; Morganti, Mauro; Terreni, Giuseppe

    2014-01-01

    Graphics Processing Units are high performance co-processors originally intended to improve the use and the acceleration of computer graphics applications. Because of their performance, researchers have extended their use beyond the computer graphics scope. We have investigated the possibility of implementing online neutrino trigger algorithms in the KM3Net-It experiment using a CPU-GPU system. The results of a neutrino trigger simulation on a NEMO Phase II tower and a KM3-It 14 floors tower ...

  1. Computer security and network processor

    International Nuclear Information System (INIS)

    The network security somehow is similar to the SARS virus's protection, at present status of the network security implementations exist many inadequate, the necessary of the security monitoring has been enhanced in this paper, as well as relative methods of the segregation of the network when attack happening. Arming the broadband data of high-speed network, the Network Processor was introduced, the prospect applications of it including the data acquisition and analyzing the experiment high energy physics and nuclear physics has been discussed. (authors)

  2. Configurable Multi-Purpose Processor

    Science.gov (United States)

    Valencia, J. Emilio; Forney, Chirstopher; Morrison, Robert; Birr, Richard

    2010-01-01

    Advancements in technology have allowed the miniaturization of systems used in aerospace vehicles. This technology is driven by the need for next-generation systems that provide reliable, responsive, and cost-effective range operations while providing increased capabilities such as simultaneous mission support, increased launch trajectories, improved launch, and landing opportunities, etc. Leveraging the newest technologies, the command and telemetry processor (CTP) concept provides for a compact, flexible, and integrated solution for flight command and telemetry systems and range systems. The CTP is a relatively small circuit board that serves as a processing platform for high dynamic, high vibration environments. The CTP can be reconfigured and reprogrammed, allowing it to be adapted for many different applications. The design is centered around a configurable field-programmable gate array (FPGA) device that contains numerous logic cells that can be used to implement traditional integrated circuits. The FPGA contains two PowerPC processors running the Vx-Works real-time operating system and are used to execute software programs specific to each application. The CTP was designed and developed specifically to provide telemetry functions; namely, the command processing, telemetry processing, and GPS metric tracking of a flight vehicle. However, it can be used as a general-purpose processor board to perform numerous functions implemented in either hardware or software using the FPGA s processors and/or logic cells. Functionally, the CTP was designed for range safety applications where it would ultimately become part of a vehicle s flight termination system. Consequently, the major functions of the CTP are to perform the forward link command processing, GPS metric tracking, return link telemetry data processing, error detection and correction, data encryption/ decryption, and initiate flight termination action commands. Also, the CTP had to be designed to survive and

  3. SMART AS A CRYPTOGRAPHIC PROCESSOR

    OpenAIRE

    Saroja Kanchi; Nozar Tabrizi; Cody Hayden

    2016-01-01

    SMaRT is a 16-bit 2.5-address RISC-type single-cycle processor, which was recently designed and successfully mapped into a FPGA chip in our ECE department. In this paper, we use SMaRT to run the well-known encryption algorithm, Data Encryption Standard. For information security purposes, encryption is a must in today’s sophisticated and ever-increasing computer communications such as ATM machines and SIM cards. For comparison and evaluation purposes, we also map the same algori...

  4. Upgrade of the CMS Global Muon Trigger

    CERN Document Server

    Lingemann, Joschka; Sakulin, Hannes; Jeitler, Manfred; Stahl, Achim

    2015-01-01

    The increase in center-of-mass energy and luminosity for Run 2 of the Large Hadron Collider pose new challenges for the trigger systems of the experiments. To keep triggering with a similar performance as in Run 1, the CMS muon trigger is currently being upgraded. The new algorithms will provide higher resolution, especially for the muon transverse momentum and will make use of isolation criteria that combine calorimeter with muon information already in the level-1 trigger. The demands of the new algorithms can only be met by upgrading the level-1 trigger system to new powerful FPGAs with high bandwidth I/O. The processing boards will be based on the new microTCA standard. We report on the planned algorithms for the upgraded Global Muon Trigger (GMT) which combines information from the muon trigger sub-systems and assigns the isolation variable. The upgraded GMT will be implemented using a Master Processor 7 card, built by Imperial College, that features a large Xilinx Virtex 7 FPGA. Up to 72 optical links at...

  5. Alternative Water Processor Test Development

    Science.gov (United States)

    Pickering, Karen D.; Mitchell, Julie; Vega, Leticia; Adam, Niklas; Flynn, Michael; Wjee (er. Rau); Lunn, Griffin; Jackson, Andrew

    2012-01-01

    The Next Generation Life Support Project is developing an Alternative Water Processor (AWP) as a candidate water recovery system for long duration exploration missions. The AWP consists of biological water processor (BWP) integrated with a forward osmosis secondary treatment system (FOST). The basis of the BWP is a membrane aerated biological reactor (MABR), developed in concert with Texas Tech University. Bacteria located within the MABR metabolize organic material in wastewater, converting approximately 90% of the total organic carbon to carbon dioxide. In addition, bacteria convert a portion of the ammonia-nitrogen present in the wastewater to nitrogen gas, through a combination of nitrogen and denitrification. The effluent from the BWP system is low in organic contaminants, but high in total dissolved solids. The FOST system, integrated downstream of the BWP, removes dissolved solids through a combination of concentration-driven forward osmosis and pressure driven reverse osmosis. The integrated system is expected to produce water with a total organic carbon less than 50 mg/l and dissolved solids that meet potable water requirements for spaceflight. This paper describes the test definition, the design of the BWP and FOST subsystems, and plans for integrated testing.

  6. Alternative Water Processor Test Development

    Science.gov (United States)

    Pickering, Karen D.; Mitchell, Julie L.; Adam, Niklas M.; Barta, Daniel; Meyer, Caitlin E.; Pensinger, Stuart; Vega, Leticia M.; Callahan, Michael R.; Flynn, Michael; Wheeler, Ray; Birmele, Michele; Lunn, Griffin; Jackson, Andrew

    2013-01-01

    The Next Generation Life Support Project is developing an Alternative Water Processor (AWP) as a candidate water recovery system for long duration exploration missions. The AWP consists of biological water processor (BWP) integrated with a forward osmosis secondary treatment system (FOST). The basis of the BWP is a membrane aerated biological reactor (MABR), developed in concert with Texas Tech University. Bacteria located within the MABR metabolize organic material in wastewater, converting approximately 90% of the total organic carbon to carbon dioxide. In addition, bacteria convert a portion of the ammonia-nitrogen present in the wastewater to nitrogen gas, through a combination of nitrification and denitrification. The effluent from the BWP system is low in organic contaminants, but high in total dissolved solids. The FOST system, integrated downstream of the BWP, removes dissolved solids through a combination of concentration-driven forward osmosis and pressure driven reverse osmosis. The integrated system is expected to produce water with a total organic carbon less than 50 mg/l and dissolved solids that meet potable water requirements for spaceflight. This paper describes the test definition, the design of the BWP and FOST subsystems, and plans for integrated testing.

  7. CPU accounting in multi-threaded processors

    OpenAIRE

    Ruiz Luque, José Carlos

    2014-01-01

    In recent years, multi-threaded processors have become more and more popular in industry in order to increase the system aggregated performance and per-application performance, overcoming the limitations imposed by the limited instruction-level parallelism, and by power and thermal constraints. Multi-threaded processors are widely used in servers, desktop computers, lap-tops, and mobile devices. However, multi-threaded processors introduce complexities when accounting CPU (computation) c...

  8. Automatic data distribution for massively parallel processors

    OpenAIRE

    García Almiñana, Jordi

    1997-01-01

    Massively Parallel Processor systems provide the required computational power to solve most large scale High Performance Computing applications. Machines with physically distributed memory allow a cost-effective way to achieve this performance, however, these systems are very diffcult to program and tune. In a distributed-memory organization each processor has direct access to its local memory, and indirect access to the remote memories of other processors. But the cost of accessing a local m...

  9. Controlling Quantum Transport with a Programmable Nanophotonic Processor

    Science.gov (United States)

    Harris, Nicholas; Steinbrecher, Gregory; Mower, Jacob; Lihini, Yoav; Prabhu, Mihika; Baehr-Jones, Tom; Hochberg, Michael; Lloyd, Seth; Englund, Dirk

    Recent experimental and theoretical work has revealed emergent, counter-intuitive quantum transport effects in a range of physical medial including solid-state and biological systems. Photonic integrated circuits are promising platforms for studying such effects. A central goal in for photonic quantum transport simulators has been the ability to rapidly control all parameters of the transport problem. Here, we present a large-scale programmable nanophotonic processor composed of 56 Mach-Zehnder interferometers that enables control over modal couplings and differential phases between modes--enabling observations of Anderson localization, environment-assisted quantum transport, ballistic transport, and a number of intermediate quantum transport regimes. Rapid programmability enables tens of thousands of realizations of disordered and noisy systems. In addition, low loss makes this nanophotonic processor a promising platform for many-boson quantum simulation experiments.

  10. Optimizing pipeline for a RISC processor with multimedia extension ISA

    Institute of Scientific and Technical Information of China (English)

    XIAO Zhi-bin; LIU Peng; YAO Ying-biao; YAO Qing-dong

    2006-01-01

    The 32-bit extensible embedded processor RISC3200 originating from an RTL prototype core is intended for low-cost consumer multimedia products. In order to incorporate the reduced instruction set and the multimedia extension instruction set in a unifying pipeline, a scalable super-pipeline technique is adopted. Several other optimization techniques are proposed to boost the frequency and reduce the average CPI of the unifying pipeline. Based on a data flow graph (DFG) with delay information, the critical path of the pipeline stage can be located and shortened. This paper presents a distributed data bypass unit and a centralized pipeline control scheme for achieving lower CPI. Synthesis and simulation showed that the optimization techniques enable RISC3200 to operate at 200 MHz with an average CPI of 1.16. The core was integrated into a media SOC chip taped out in SMIC 0.18-micron technology. Preliminary testing result showed that the processor works well as we expected.

  11. The ZEUS second level calorimeter trigger

    International Nuclear Information System (INIS)

    ZEUS is a detector for the HERA ep collider, consisting of several large components. The most important being the inner tracking detectors, which are positioned nearest to the interaction point, the calorimeter surrounding the inner tracking detectors and the muon detectors on the outside of the experimental setup. Each component will deliver a vast amount of information. In order to keep this information manageable, data is preprocessed and condensed per component and then combined to obtain the final global trigger result. The main subject of this thesis is the second level calorimeter trigger processor of the ZEUS detector. In order to be able to reject the unwanted events passing the first level, the topological event signature will have to be used at the second level. The most demanding task of the second level is the recognition of local energy depositions corresponding to isolated electrons and hadron jets. Also part of the work performed by the first level will be repeated with a higher level of accuracy. Additional information not available to the first level trigger will be processed and will be made available to the global second level trigger decision module. For the second level calorimeter trigger processor a special VME module, containing two transputers, has been developed. The second level calorimeter trigger algorithm described in this thesis was tested with simulated events, that were tracked through a computer simulation of the ZEUS detector. A part of this thesis is therefore devoted to the description of the various Monte Carlo models and the justification of the way in which they were used. (author). 132 refs.; 76 figs.; 18 tabs

  12. Producing chopped firewood with firewood processors

    International Nuclear Information System (INIS)

    The TTS Institute's research and development project studied both the productivity of new, chopped firewood processors (cross-cutting and splitting machines) suitable for professional and independent small-scale production, and the costs of the chopped firewood produced. Seven chopped firewood processors were tested in the research, six of which were sawing processors and one shearing processor. The chopping work was carried out using wood feeding racks and a wood lifter. The work was also carried out without any feeding appliances. Altogether 132.5 solid m3 of wood were chopped in the time studies. The firewood processor used had the most significant impact on chopping work productivity. In addition to the firewood processor, the stem mid-diameter, the length of the raw material, and of the firewood were also found to affect productivity. The wood feeding systems also affected productivity. If there is a feeding rack and hydraulic grapple loader available for use in chopping firewood, then it is worth using the wood feeding rack. A wood lifter is only worth using with the largest stems (over 20 cm mid-diameter) if a feeding rack cannot be used. When producing chopped firewood from small-diameter wood, i.e. with a mid-diameter less than 10 cm, the costs of chopping work were over 10 EUR solid m-3 with sawing firewood processors. The shearing firewood processor with a guillotine blade achieved a cost level of 5 EUR solid m-3 when the mid-diameter of the chopped stem was 10 cm. In addition to the raw material, the cost-efficient chopping work also requires several hundred annual operating hours with a firewood processor, which is difficult for individual firewood entrepreneurs to achieve. The operating hours of firewood processors can be increased to the required level by the joint use of the processors by a number of firewood entrepreneurs. (author)

  13. Trigger and Readout System for the Ashra-1 Detector

    Science.gov (United States)

    Aita, Y.; Aoki, T.; Asaoka, Y.; Morimoto, Y.; Motz, H. M.; Sasaki, M.; Abiko, C.; Kanokohata, C.; Ogawa, S.; Shibuya, H.; Takada, T.; Kimura, T.; Learned, J. G.; Matsuno, S.; Kuze, S.; Binder, P. M.; Goldman, J.; Sugiyama, N.; Watanabe, Y.

    Highly sophisticated trigger and readout system has been developed for All-sky Survey High Resolution Air-shower (Ashra) detector. Ashra-1 detector has 42 degree diameter field of view. Detection of Cherenkov and fluorescence light from large background in the large field of view requires finely segmented and high speed trigger and readout system. The system is composed of optical fiber image transmission system, 64 × 64 channel trigger sensor and FPGA based trigger logic processor. The system typically processes the image within 10 to 30 ns and opens the shutter on the fine CMOS sensor. 64 × 64 coarse split image is transferred via 64 × 64 precisely aligned optical fiber bundle to a photon sensor. Current signals from the photon sensor are discriminated by custom made trigger amplifiers. FPGA based processor processes 64 × 64 hit pattern and correspondent partial area of the fine image is acquired. Commissioning earth skimming tau neutrino observational search was carried out with this trigger system. In addition to the geometrical advantage of the Ashra observational site, the excellent tau shower axis measurement based on the fine imaging and the night sky background rejection based on the fine and fast imaging allow zero background tau shower search. Adoption of the optical fiber bundle and trigger LSI realized 4k channel trigger system cheaply. Detectability of tau shower is also confirmed by simultaneously observed Cherenkov air shower. Reduction of the trigger threshold appears to enhance the effective area especially in PeV tau neutrino energy region. New two dimensional trigger LSI was introduced and the trigger threshold was lowered. New calibration system of the trigger system was recently developed and introduced to the Ashra detector

  14. Commissioning of the CMS High Level Trigger

    Energy Technology Data Exchange (ETDEWEB)

    Agostino, Lorenzo; et al.

    2009-08-01

    The CMS experiment will collect data from the proton-proton collisions delivered by the Large Hadron Collider (LHC) at a centre-of-mass energy up to 14 TeV. The CMS trigger system is designed to cope with unprecedented luminosities and LHC bunch-crossing rates up to 40 MHz. The unique CMS trigger architecture only employs two trigger levels. The Level-1 trigger is implemented using custom electronics, while the High Level Trigger (HLT) is based on software algorithms running on a large cluster of commercial processors, the Event Filter Farm. We present the major functionalities of the CMS High Level Trigger system as of the starting of LHC beams operations in September 2008. The validation of the HLT system in the online environment with Monte Carlo simulated data and its commissioning during cosmic rays data taking campaigns are discussed in detail. We conclude with the description of the HLT operations with the first circulating LHC beams before the incident occurred the 19th September 2008.

  15. Ultrafast Fourier-transform parallel processor

    Energy Technology Data Exchange (ETDEWEB)

    Greenberg, W.L.

    1980-04-01

    A new, flexible, parallel-processing architecture is developed for a high-speed, high-precision Fourier transform processor. The processor is intended for use in 2-D signal processing including spatial filtering, matched filtering and image reconstruction from projections.

  16. The TM3270 Media-processor

    NARCIS (Netherlands)

    van de Waerdt, J.W.

    2006-01-01

    I n this thesis, we present the TM3270 VLIW media-processor, the latest of TriMedia processors, and describe the innovations with respect to its prede- cessor: the TM3260. We describe enhancements to the load/store unit design, such as a new data prefetching technique, and architectural enhancements

  17. Models of Communication for Multicore Processors

    DEFF Research Database (Denmark)

    Schoeberl, Martin; Sørensen, Rasmus Bo; Sparsø, Jens

    2015-01-01

    To efficiently use multicore processors we need to ensure that almost all data communication stays on chip, i.e., the bits moved between tasks executing on different processor cores do not leave the chip. Different forms of on-chip communication are supported by different hardware mechanism, e...

  18. Adapting implicit methods to parallel processors

    Energy Technology Data Exchange (ETDEWEB)

    Reeves, L.; McMillin, B.; Okunbor, D.; Riggins, D. [Univ. of Missouri, Rolla, MO (United States)

    1994-12-31

    When numerically solving many types of partial differential equations, it is advantageous to use implicit methods because of their better stability and more flexible parameter choice, (e.g. larger time steps). However, since implicit methods usually require simultaneous knowledge of the entire computational domain, these methods axe difficult to implement directly on distributed memory parallel processors. This leads to infrequent use of implicit methods on parallel/distributed systems. The usual implementation of implicit methods is inefficient due to the nature of parallel systems where it is common to take the computational domain and distribute the grid points over the processors so as to maintain a relatively even workload per processor. This creates a problem at the locations in the domain where adjacent points are not on the same processor. In order for the values at these points to be calculated, messages have to be exchanged between the corresponding processors. Without special adaptation, this will result in idle processors during part of the computation, and as the number of idle processors increases, the lower the effective speed improvement by using a parallel processor.

  19. Towards a Process Algebra for Shared Processors

    DEFF Research Database (Denmark)

    Buchholtz, Mikael; Andersen, Jacob; Løvengreen, Hans Henrik

    2002-01-01

    We present initial work on a timed process algebra that models sharing of processor resources allowing preemption at arbitrary points in time. This enables us to model both the functional and the timely behaviour of concurrent processes executed on a single processor. We give a refinement relation...

  20. SCAN secure processor and its biometric capabilities

    Science.gov (United States)

    Kannavara, Raghudeep; Mertoguno, Sukarno; Bourbakis, Nikolaos

    2011-04-01

    This paper presents the design of the SCAN secure processor and its extended instruction set to enable secure biometric authentication. The SCAN secure processor is a modified SparcV8 processor architecture with a new instruction set to handle voice, iris, and fingerprint-based biometric authentication. The algorithms for processing biometric data are based on the local global graph methodology. The biometric modules are synthesized in reconfigurable logic and the results of the field-programmable gate array (FPGA) synthesis are presented. We propose to implement the above-mentioned modules in an off-chip FPGA co-processor. Further, the SCAN-secure processor will offer a SCAN-based encryption and decryption of 32 bit instructions and data.

  1. Upgrades to the ATLAS Level-1 Calorimeter Trigger

    CERN Document Server

    Plucinski, P; The ATLAS collaboration; Qian, W

    2014-01-01

    ABSTRACT: 2015 the Large Hadron Collider will run with increased center-of-mass energy and luminosity. To maintain trigger efficiency against increased pileup rates, event topology information will be added to the ATLAS Level-1 real time data path and processed by a new Topology Processor (L1Topo). In phase-I, a new digital readout for the Liquid Argon calorimeters will provide finer granularity and depth segmentation in the electromagnetic layer to new Level-1 feature extractors (FEX) for improved EM, tau and jet identification. We present the topology and phase-I trigger upgrades to the ATLAS Level-1 trigger.

  2. Upgrades to the ATLAS Level-1 Calorimeter Trigger

    CERN Document Server

    Plucinski, P; The ATLAS collaboration; Qian, W

    2013-01-01

    In 2015 the Large Hadron Collider will run with increased center-of-mass energy and luminosity. To maintain trigger efficiency against increased pileup rates, event topology information will be added to the ATLAS Level-1 real time data path and processed by a new Topology Processor (L1Topo). In phase-I, a new digital readout for the Liquid Argon calorimeters will provide finer granularity and depth segmentation in the electromagnetic layer to new Level-1 feature extractors (FEX) for improved EM, tau and jet identification. We present the topology and phase-I trigger upgrades to the ATLAS Level-1 trigger.

  3. Direct Processor Access for Non Dedicated Server using Multi Core Processor

    OpenAIRE

    P. S. BALAMURUGAN,; Dr.K.Thanushkodi

    2010-01-01

    The objective of the paper is to design a co processor for a desktop machine which enables the machine to act as non dedicated server, such that the co processor will act as a server processor and the multi-core processor to act as desktop processor. By implementing this methodology a client machine can be made to act as a non dedicated server and a client machine. This type of machine can be used in autonomy networks. This design will lead to design of a cost effective server and machine whi...

  4. Comparison of Processor Performance of SPECint2006 Benchmarks of some Intel Xeon Processors

    OpenAIRE

    Abdul Kareem PARCHUR; Ram Asaray SINGH

    2012-01-01

    High performance is a critical requirement to all microprocessors manufacturers. The present paper describes the comparison of performance in two main Intel Xeon series processors (Type A: Intel Xeon X5260, X5460, E5450 and L5320 and Type B: Intel Xeon X5140, 5130, 5120 and E5310). The microarchitecture of these processors is implemented using the basis of a new family of processors from Intel starting with the Pentium 4 processor. These processors can provide a performance boost for many ke...

  5. The Database Driven ATLAS Trigger Configuration System

    CERN Document Server

    Martyniuk, Alex; The ATLAS collaboration

    2015-01-01

    This contribution describes the trigger selection configuration system of the ATLAS low- and high-level trigger (HLT) and the upgrades it received in preparation for LHC Run 2. The ATLAS trigger configuration system is responsible for applying the physics selection parameters for the online data taking at both trigger levels and the proper connection of the trigger lines across those levels. Here the low-level trigger consists of the already existing central trigger (CT) and the new Level-1 Topological trigger (L1Topo), which has been added for Run 2. In detail the tasks of the configuration system during the online data taking are Application of the selection criteria, e.g. energy cuts, minimum multiplicities, trigger object correlation, at the three trigger components L1Topo, CT, and HLT On-the-fly, e.g. rate-dependent, generation and application of prescale factors to the CT and HLT to adjust the trigger rates to the data taking conditions, such as falling luminosity or rate spikes in the detector readout ...

  6. Performance of ATLAS RPC Level-1 Muon trigger during the 2015 data taking

    CERN Document Server

    Corradi, Massimo; The ATLAS collaboration

    2016-01-01

    The Level-1 Muon Barrel Trigger is one of the main elements of the event selection of the ATLAS experiment at the Large Hadron Collider. Its input stage consists of an array of processors receiving the full granularity of data from Resistive Plate Chambers in the central area of the ATLAS detector ("Barrel"). The trigger efficiency and the level of synchronisation of its elements with the rest of ATLAS and the LHC clock are crucial figures of this system: many parameters of the constituent RPC detector and the trigger electronics have to be constantly and carefully checked to assure a correct functioning of the Level-1 selection. Notwithstanding the complexity of such a large array of integrated RPC detectors, the ATLAS Level-1 system has resumed operations successfully after the past 2 year shutdown, with levels similar to those of Run 1. We present the inclusive monitoring of the RPC+L1 system that we have developed to characterise the behaviour of the system, using reconstructed muons in events selected by...

  7. Very Large-Scale Integrated Processor

    Directory of Open Access Journals (Sweden)

    Shigeyuki Takano

    2013-01-01

    Full Text Available In the near future, improvements in semiconductor technology will allow thousands of resources to be implementable on chip. However, a limitation remains for both single large-scale processors and many-core processors. For single processors, this limitation arises from their  design complexity, and regarding the many-core processors, an application is partitioned to several tasks and these partitioned tasks are mapped onto the cores. In this article,  we propose a dynamic chip multiprocessor (CMP model that consists of simple modules (realizing a low design complexity and does not require the application partitioning since the scale of the processor is dynamically variable, looking like up or down scale on demand. This model is based on prior work on adaptive processors that can gather and release resources on chip to dynamically form a processor. The adaptive processor takes a linear topology that realizes a locality based placement and replacement using processing elements themselves through a stack shift of information on the linear topology of the processing element array. Therefore, for the scaling of the processor, a linear topology of the interconnection network has to support the stack shift before and after the up- or down-scaling. Therefore, we propose an interconnection network architecture called a dynamic channel segmentation distribution (dynamic CSD network. In addition the linear topology must be folded on-chip into two-dimensional plane. We also propose a new conceptual topology and its cluster which is a unit of the new topology and is replicated on the chip. We analyzed the cost in terms of the available number of clusters (adaptive processors with a minimum scale and delay in Manhattan-distance of the chip, as well as its peak Giga-Operations per Second (GOPS across the process technology scaling.

  8. Enabling Future Robotic Missions with Multicore Processors

    Science.gov (United States)

    Powell, Wesley A.; Johnson, Michael A.; Wilmot, Jonathan; Some, Raphael; Gostelow, Kim P.; Reeves, Glenn; Doyle, Richard J.

    2011-01-01

    Recent commercial developments in multicore processors (e.g. Tilera, Clearspeed, HyperX) have provided an option for high performance embedded computing that rivals the performance attainable with FPGA-based reconfigurable computing architectures. Furthermore, these processors offer more straightforward and streamlined application development by allowing the use of conventional programming languages and software tools in lieu of hardware design languages such as VHDL and Verilog. With these advantages, multicore processors can significantly enhance the capabilities of future robotic space missions. This paper will discuss these benefits, along with onboard processing applications where multicore processing can offer advantages over existing or competing approaches. This paper will also discuss the key artchitecural features of current commercial multicore processors. In comparison to the current art, the features and advancements necessary for spaceflight multicore processors will be identified. These include power reduction, radiation hardening, inherent fault tolerance, and support for common spacecraft bus interfaces. Lastly, this paper will explore how multicore processors might evolve with advances in electronics technology and how avionics architectures might evolve once multicore processors are inserted into NASA robotic spacecraft.

  9. Improving performance of probabilistic programmable quantum processors

    CERN Document Server

    Hillery, M; Buzek, V; Hillery, Mark; Ziman, Mario; Buzek, Vladimir

    2003-01-01

    We present a systematic analysis how one can improve performance of probabilistic programmable quantum processors. We generalize a simple Vidal-Masanes-Cirac processor that realizes U(1) rotations on a qubit with the phase of the rotation encoded in a state of the program register. We show how the probability of success of the probabilistic processor can be enhanced by using the processor in loops. In addition we show that the same strategy can be utilized for a probabilistic implementation of non-unitary transformations on qubits. In addtion, we show that an arbitrary SU(2) transformations of qubits can be encoded in program state of a universal programmable probabilistic quantum processor. The probability of success of this processor can be enhanced by a systematic correction of errors via conditional loops. Finally, we show that all our results can be generalized also for qudits. In particular, we show how to implement SU (N) rotations of qudits via programmable quantum processor and how the performance of...

  10. Making CSB+-Tree Processor Conscious

    DEFF Research Database (Denmark)

    Samuel, Michael; Pedersen, Anders Uhl; Bonnet, Philippe

    2005-01-01

    Cache-conscious indexes, such as CSB+-tree, are sensitive to the underlying processor architecture. In this paper, we focus on how to adapt the CSB+-tree so that it performs well on a range of different processor architectures. Previous work has focused on the impact of node size on the performance...... of the CSB+-tree. We argue that it is necessary to consider a larger group of parameters in order to adapt CSB+-tree to processor architectures as different as Pentium and Itanium. We identify this group of parameters and study how it impacts the performance of CSB+-tree on Itanium 2. Finally, we...

  11. A hardware and software overview of the Delphi contiguity trigger

    International Nuclear Information System (INIS)

    The contiguity processor of the Delphi detector, which is composed of 12 Fastbus modules (one for each TPC sector), is the main second-level track trigger component in the experiment. More than 3000 Mips of processing power are achieved by 4608 processing elements (PE) packed in specially designed ASIC IC's. High interconnectivity among PE's (bidimensional lattice) and a highly parallel algorithm (contiguity mask) allow a three-dimensional vertex reconstruction in less than 5μs. In this paper an overview of the single instruction multiple data (SIMD) architecture, together with the programming language and the interactive debugging tools for the processor, are given

  12. An On Board Processor (OBP) for OAO C

    Science.gov (United States)

    Hartenstein, R. G.

    1972-01-01

    A stored program computer and its application on OAO is considered. The parallel computer has a memory capacity of 16,384 words of 18 bits each, one central processor unit, two 4096 word memory units, and one input/output unit. The I/O has no direct data connection with the CPU so that all data flow between these two units must pass through memory by way of the memory data bus. The primary functions of the onboard computer are auxiliary command storage, spacecraft monitoring and malfunction reporting, data compression and status summary, and possible performance of emergency corrective action.

  13. The D/Ø Silicon Track Trigger

    Science.gov (United States)

    Steinbrück, Georg

    2003-09-01

    We describe a trigger preprocessor to be used by the D Ø experiment for selecting events with tracks from the decay of long-lived particles. This Level 2 impact parameter trigger utilizes information from the Silicon Microstrip Tracker to reconstruct tracks with improved spatial and momentum resolutions compared to those obtained by the Level 1 tracking trigger. It is constructed of VME boards with much of the logic existing in programmable processors. A common motherboard provides the I/O infrastructure and three different daughter boards perform the tasks of identifying the roads from the tracking trigger data, finding the clusters in the roads in the silicon detector, and fitting tracks to the clusters. This approach provides flexibility for the design, testing and maintenance phases of the project. The track parameters are provided to the trigger framework in 25 μs. The effective impact parameter resolution for high-momentum tracks is 35 μm, dominated by the size of the Tevatron beam.

  14. Fast Track Pattern Recognition in High Energy Physics Experiments with the Automata Processor

    CERN Document Server

    Wang, Michael H L S; Green, Christopher; Guo, Deyuan; Wang, Ke; Zmuda, Ted

    2016-01-01

    We explore the Micron Automata Processor (AP) as a suitable commodity technology that can address the growing computational needs of track pattern recognition in High Energy Physics experiments. A toy detector model is developed for which a track trigger based on the Micron AP is used to demonstrate a proof-of-principle. Although primarily meant for high speed text-based searches, we demonstrate that the Micron AP is ideally suited to track finding applications.

  15. SMART AS A CRYPTOGRAPHIC PROCESSOR

    Directory of Open Access Journals (Sweden)

    Saroja Kanchi

    2016-05-01

    Full Text Available SMaRT is a 16-bit 2.5-address RISC-type single-cycle processor, which was recently designed and successfully mapped into a FPGA chip in our ECE department. In this paper, we use SMaRT to run the well-known encryption algorithm, Data Encryption Standard. For information security purposes, encryption is a must in today’s sophisticated and ever-increasing computer communications such as ATM machines and SIM cards. For comparison and evaluation purposes, we also map the same algorithm on the HC12, a same-size but CISC-type off-the-shelf microcontroller, Our results show that compared to HC12, SMaRT code is only 14% longer in terms of the static number of instructions but about 10 times faster in terms of the number of clock cycles, and 7% smaller in terms of code size. Our results also show that 2.5- address instructions, a SMaRT selling point, amount to 45% of the whole R-type instructions resulting in significant improvement in static number of instructions hence code size as well as performance. Additionally, we see that the SMaRT short-branch range is sufficiently wide in 90% of cases in the SMaRT code. Our results also reveal that the SMaRT novel concept of locality of reference in using the MSBs of the registers in non-subroutine branch instructions stays valid with a remarkable hit rate of 95%!

  16. Grundy - Parallel processor architecture makes programming easy

    Science.gov (United States)

    Meier, R. J., Jr.

    1985-01-01

    The hardware, software, and firmware of the parallel processor, Grundy, are examined. The Grundy processor uses a simple processor that has a totally orthogonal three-address instruction set. The system contains a relative and indirect processing mode to support the high-level language, and uses pseudoprocessors and read-only memory. The system supports high-level language in which arbitrary degrees of algorithmic parallelism is expressed. The functions of the compiler and invocation frame are described. Grundy uses an operating system that can be accessed by an arbitrary number of processes simultaneously, and the access time grows only as the logarithm of the number of active processes. Applications for the parallel processor are discussed.

  17. Implementation of Middleware Switch ASIC Processor

    Directory of Open Access Journals (Sweden)

    S. Montenegro

    2012-11-01

    Full Text Available The new spacecraft area network (SCAN system for internal satellite communication provides data transfer between different satellite components. The satellite components have their own communication protocols, which are translated by middleware (MW switch processor into a universal middleware protocol, understandable for the satellite operating system. The MW switch processor is the main part of a new proposed approach. Instead of current board computer based systems, the new data transfer approach based on network provides a more reliable solution. The processor is fabricated in the 250 nm IHP technology. This paper introduces a description of MW switch architecture, a comparison between possible architecture approaches and the characteristics of the implemented MW Switch processor.

  18. Photonics and Fiber Optics Processor Lab

    Data.gov (United States)

    Federal Laboratory Consortium — The Photonics and Fiber Optics Processor Lab develops, tests and evaluates high speed fiber optic network components as well as network protocols. In addition, this...

  19. Radiation Tolerant Software Defined Video Processor Project

    Data.gov (United States)

    National Aeronautics and Space Administration — MaXentric's is proposing a radiation tolerant Software Define Video Processor, codenamed SDVP, for the problem of advanced motion imaging in the space environment....

  20. Processor-Dependent Malware... and codes

    CERN Document Server

    Desnos, Anthony; Filiol, Eric

    2010-01-01

    Malware usually target computers according to their operating system. Thus we have Windows malwares, Linux malwares and so on ... In this paper, we consider a different approach and show on a technical basis how easily malware can recognize and target systems selectively, according to the onboard processor chip. This technology is very easy to build since it does not rely on deep analysis of chip logical gates architecture. Floating Point Arithmetic (FPA) looks promising to define a set of tests to identify the processor or, more precisely, a subset of possible processors. We give results for different families of processors: AMD, Intel (Dual Core, Atom), Sparc, Digital Alpha, Cell, Atom ... As a conclusion, we propose two {\\it open problems} that are new, to the authors' knowledge.

  1. Optimization of adaptive fuzzy processor design

    OpenAIRE

    Baturone, I.; Sánchez-Solano, Santiago; Barriga, Angel; Huertas-Díaz, J. L.

    1998-01-01

    A fuzzy processor is programmed to provide anoptimum output for solving a given problem. It could theoretically solve any problem (from a static point of view) if it is an universal approximator. This paper addresses the design of fuzzy processors aiming at a twofold objective: efficient adaptive approximation of different and even dynamically changing surfaces and hardware simplicity. Adequate programmable parameters and a fully-parallel architecture are selected. Mixed-signal blocks b...

  2. Keystone Business Models for Network Security Processors

    OpenAIRE

    Arthur Low; Steven Muegge

    2013-01-01

    Network security processors are critical components of high-performance systems built for cybersecurity. Development of a network security processor requires multi-domain experience in semiconductors and complex software security applications, and multiple iterations of both software and hardware implementations. Limited by the business models in use today, such an arduous task can be undertaken only by large incumbent companies and government organizations. Neither the “fabless semiconductor...

  3. Software-defined universal microwave photonics processor

    OpenAIRE

    Pérez, Daniel; Gasulla Mestre, Ivana; Capmany Francoy, José

    2015-01-01

    We propose, for the first time to our knowledge, a software-defined reconfigurable microwave photonics signal processor architecture that can be integrated on a chip and is capable of performing all the main functionalities by suitable programming of its control signals. The basic configuration is presented and a thorough end-to-end design model derived that accounts for the performance of the overall processor taking into consideration the impact and interdependencies of both its photonic an...

  4. Real time monitoring of electron processors

    International Nuclear Information System (INIS)

    A real time radiation monitor (RTRM) has been developed for monitoring the dose rate (current density) of electron beam processors. The system provides continuous monitoring of processor output, electron beam uniformity, and an independent measure of operating voltage or electron energy. In view of the device's ability to replace labor-intensive dosimetry in verification of machine performance on a real-time basis, its application to providing archival performance data for in-line processing is discussed. (author)

  5. Matrix Manipulation Algorithms for Hasse Processor Implementation

    OpenAIRE

    Hahanov, Vladimir; Dahiri, Farid

    2014-01-01

    The processor is implemented in software-hardware modules, which are based on the use of programming languages: C ++, Verilog, Python 2.7 and platforms: Microsoft Windows, X Window (in Unix and Linux) and Macintosh OS X. HDL-code generator makes it possible to automatically synthesize HDL-code of the processor structure from 1 to 16 bits for parallel processing corresponding number of input vectors or words.

  6. The new Global Muon Trigger of the CMS experiment

    CERN Document Server

    Fulcher, Jonathan Richard; Rabady, Dinyar Sebastian; Reis, Thomas; Sakulin, Hannes

    2016-01-01

    For the 2016 physics data runs the L1 trigger system of the Compact Muon Solenoid (CMS) experiment underwent a major upgrade to cope with the increasing instantaneous luminosity of the CERN LHC whilst maintaining a high event selection efficiency for the CMS physics program. Most subsystem specific trigger processor boards were replaced with powerful general purpose processor boards, conforming to the MicroTCA standard, whose tasks are performed by firmware on an FPGA of the Xilinx Virtex 7 family. Furthermore, the muon trigger system moved from a subsystem centered approach, where each of the three muon detector systems provides muon candidates to the Global Muon Trigger (GMT), to a region based system, where muon track finders (TFs) combine information from the subsystems to generate muon candidates in three detector regions, that are then sent to the upgraded GMT. The upgraded GMT receives up to 108 muons from the processors of the muon TFs in the barrel, overlap, and endcap detector regions. The muons are...

  7. A time-multiplexed track-trigger architecture for CMS

    Science.gov (United States)

    Hall, G.; Newbol, D.; Pesaresi, M.; Rose, A.

    2014-10-01

    The CMS Tracker under development for the High Luminosity LHC includes an outer tracker based on ``PT-modules'' which will provide track stubs based on coincident clusters in two closely spaced sensor layers, aiming to reject low transverse momentum track hits before data transmission to the Level-1 trigger. The tracker data will be used to reconstruct track segments in dedicated processors before onward transmission to other trigger processors which will combine tracker information with data originating from the calorimeter and muon detectors, to make the final L1 trigger decision. The architecture for processing the tracker data is still an open question. One attractive option is to explore a Time Multiplexed design similar to one which is currently being implemented in the CMS calorimeter trigger as part of the Phase I trigger upgrade. The Time Multiplexed Trigger concept is explained, the potential benefits of applying it for processing future tracker data are described and a possible design based on currently existing hardware is presented.

  8. A time-multiplexed track-trigger architecture for CMS

    International Nuclear Information System (INIS)

    The CMS Tracker under development for the High Luminosity LHC includes an outer tracker based on ''PT-modules'' which will provide track stubs based on coincident clusters in two closely spaced sensor layers, aiming to reject low transverse momentum track hits before data transmission to the Level-1 trigger. The tracker data will be used to reconstruct track segments in dedicated processors before onward transmission to other trigger processors which will combine tracker information with data originating from the calorimeter and muon detectors, to make the final L1 trigger decision. The architecture for processing the tracker data is still an open question. One attractive option is to explore a Time Multiplexed design similar to one which is currently being implemented in the CMS calorimeter trigger as part of the Phase I trigger upgrade. The Time Multiplexed Trigger concept is explained, the potential benefits of applying it for processing future tracker data are described and a possible design based on currently existing hardware is presented

  9. Trigger Finger (Stenosing Tenosynovitis)

    Science.gov (United States)

    ... Symptom Picker Hand and Arm Conditions Carpal Tunnel Ganglion Cysts Trigger Finger Arthritis Base of the Thumb See ... Symptom Picker Hand and Arm Conditions Carpal Tunnel Ganglion Cysts Trigger Finger Arthritis Base of the Thumb See ...

  10. The KLOE trigger system

    Energy Technology Data Exchange (ETDEWEB)

    Adinolfi, M.; Aloisio, A.; Ambrosino, F.; Andryakov, A.; Antonelli, A.; Antonelli, M.; Anulli, F.; Bacci, C.; Bankamp, A.; Barbiellini, G.; Bellini, F.; Bencivenni, G.; Bertolucci, S.; Bini, C.; Bloise, C.; Bocci, V.; Bossi, F.; Branchini, P.; Bulychjov, S.A.; Cabibbo, G.; Calcaterra, A.; Caloi, R.; Campana, P.; Capon, G.; Carboni, G.; Cardini, A.; Casarsa, M.; Cataldi, G.; Ceradini, F.; Cervelli, F.; Cevenini, F.; Chiefari, G.; Ciambrone, P.; Conetti, S.; Conticelli, S.; De Lucia, E.; De Robertis, G.; De Sangro, R.; De Simone, P.; De Zorzi, G.; Dell' Agnello, S.; Denig, E.; Di Domenico, A.; Di Donato, C.; Di Falco, S.; Doria, A.; Drago, E.; Elia, V.; Erriquez, O.; Farilla, A.; Felici, G.; Ferrari, A.; Ferrer, M.L.; Finocchiaro, G.; Forti, C.; Franceschi, A.; Franzini, P.; Gao, M.L.; Gatti, C.; Gauzzi, P.; Giovannella, S.; Golovatyuk, V.; Gorini, E.; Grancagnolo, F.; Grandegger, W.; Graziani, E.; Guarnaccia, P.; Hagel, U. von; Han, H.G.; Han, S.W.; Huang, X.; Incagli, M.; Ingrosso, L.; Jang, Y.Y.; Kim, W.; Kluge, W.; Kulikov, V.; Lacava, F.; Lanfranchi, G.; Lee-Franzini, J.; Lomtadze, F.; Luisi, C.; Mao, C.S.; Martemianov, M.; Matsyuk, M.; Mei, W.; Merola, L.; Messi, R.; Miscetti, S.; Moalem, A.; Moccia, S.; Moulson, M.; Mueller, S.; Murtas, F.; Napolitano, M.; Nedosekin, A.; Panareo, M.; Pacciani, L.; Pages, P.; Palutan, M.; Paoluzi, L.; Pasqualucci, E.; Passalacqua, L.; Passaseo, M.; Passeri, A.; Patera, V.; Petrolo, E.; Petrucci, G.; Picca, D.; Pirozzi, G.; Pistillo, C.; Pollack, M.; Pontecorvo, L.; Primavera, M.; Ruggieri, F.; Santangelo, P.; Santovetti, E.; Saracino, G.; Schamberger, R.D.; Schwick, C.; Sciascia, B. E-mail: barbara.sciascia@romal.infn.it; Sciubba, A.; Scuri, F.; Sfiligoi, I.; Shan, J.; Silano, P.; Spadaro, T.; Spagnolo, S.; Spiriti, E.; Stanescu, C.; Tong, G.L.; Tortora, L.; Valente, E.; Valente, P.; Valeriani, B.; Venanzoni, G.; Veneziano, S.; Wu, Y.; Xie, Y.G.; Zhao, P.P.; Zhou, Y

    2001-04-01

    A double-level trigger system has been developed for the KLOE experiment. Custom electronics asserts a trigger in a 2 {mu}s decision time. The decision is based on the combined information of the electromagnetic calorimeter and the drift chamber. The entire trigger system is continuously monitored, and data flowing from the trigger system have allowed both an efficient online monitoring of the detector and an online luminosity measurement.

  11. The KLOE trigger system

    International Nuclear Information System (INIS)

    A double-level trigger system has been developed for the KLOE experiment. Custom electronics asserts a trigger in a 2 μs decision time. The decision is based on the combined information of the electromagnetic calorimeter and the drift chamber. The entire trigger system is continuously monitored, and data flowing from the trigger system have allowed both an efficient online monitoring of the detector and an online luminosity measurement

  12. 7 CFR 1160.108 - Fluid milk processor.

    Science.gov (United States)

    2010-01-01

    ... 7 Agriculture 9 2010-01-01 2009-01-01 true Fluid milk processor. 1160.108 Section 1160.108... Order Definitions § 1160.108 Fluid milk processor. (a) Fluid milk processor means any person who... term fluid milk processor shall not include in each of the respective fiscal periods those persons...

  13. The TriggerTool Graphical User Interface to the ATLAS Trigger Configuration Database

    CERN Document Server

    Bell, P; Brunet, S; Fischer, G; Goebel, M; Haller, J; Head, S; Höcker, A; Kohno, T; Martyniuk, A; Nozicka, M; Owen, M; Spiwoks, R; Stelzer, J; Wengler, T; Wiedenmann, W

    2009-01-01

    A system has been designed and implemented to configure all three levels of the ATLAS trigger system from a centrally provided relational database, in which an archive of all trigger configurations used in data taking is also maintained. The user interaction with this database is via a Java-based graphical user interface known as the TriggerTool. We describe here how the TriggerTool has been designed to fulfill several different roles for users of varying expertise, from being a browser of the database to a tool for creating and modifying configurations

  14. A Time-Multiplexed Track-Trigger for the CMS HL-LHC upgrade

    CERN Document Server

    Hall, Geoffrey

    2015-01-01

    A new CMS Tracker is under development for operation at the High Luminosity LHC from 2025. It includes an outer tracker based on special modules of two different types which will construct track stubs using spatially coincident clusters in two closely spaced sensor layers, to reject low transverse momentum track hits and reduce the data volume before data transmission to the Level-1 trigger. The tracker data will be used to reconstruct track segments in dedicated processors before onward transmission to other trigger processors which will combine tracker information with data originating from the calorimeter and muon detectors, to make the final L1 trigger decision. The architecture for processing the tracker data outside the detector is under study, using several alternative approaches. One attractive possibility is to exploit a Time Multiplexed design similar to the one which is currently being implemented in the CMS calorimeter trigger as part of the Phase I trigger upgrade. The novel Time Multiplexed Trig...

  15. Centralized digital control of accelerators

    International Nuclear Information System (INIS)

    In contrasting the title of this paper with a second paper to be presented at this conference entitled Distributed Digital Control of Accelerators, a potential reader might be led to believe that this paper will focus on systems whose computing intelligence is centered in one or more computers in a centralized location. Instead, this paper will describe the architectural evolution of SLAC's computer based accelerator control systems with respect to the distribution of their intelligence. However, the use of the word centralized in the title is appropriate because these systems are based on the use of centralized large and computationally powerful processors that are typically supported by networks of smaller distributed processors

  16. PRODUCTIVE CO PROCESSOR DESIGN BASED ON PROGRAM BENCHMARK

    OpenAIRE

    P. S. Balamurugan; Dr. K.THANUSHKODI

    2010-01-01

    The objective of this paper is to design a methodology where many co-processors are accessed by the processor in array mode. By using co processor, the work on the multi core processor gets reduced by accessing it in array manner. A multi core processor is an efficient processor which can enable parallel processing and perform multi threading effectively. In this paper, in order to improve the performance of multi-core processor two major factors are taken intoconsideration one is to improve ...

  17. PRODUCTIVE CO PROCESSOR DESIGN BASED ON PROGRAM BENCHMARK

    Directory of Open Access Journals (Sweden)

    P. S. BALAMURUGAN

    2010-09-01

    Full Text Available The objective of this paper is to design a methodology where many co-processors are accessed by the processor in array mode. By using co processor, the work on the multi core processor gets reduced by accessing it in array manner. A multi core processor is an efficient processor which can enable parallel processing and perform multi threading effectively. In this paper, in order to improve the performance of multi-core processor two major factors are taken intoconsideration one is to improve the execution of array methodology by using co processor and other is yo design an array based co processor to improve the hit ratio of the co processor.

  18. ATLAS calorimetry. Trigger, simulation and jet calibration

    International Nuclear Information System (INIS)

    The Pre-Processor system of the ATLAS Level-1 Calorimeter Trigger performs complex processing of analog trigger tower signals from electromagnetic and hadronic calorimeters. The main processing block of the Pre-Processor System is the Multi-Chip Module (MCM). The first part of this thesis describes MCM quality assurance tests that have been developed, their use in the MCM large scale production and the results that have been obtained. In the second part of the thesis a validation of a shower parametrisation model for the ATLAS fast simulation package ATLFAST based on QCD dijet events is performed. A detailed comparison of jet response and jet energy resolution between the fast and the full simulation is presented. The uniformity of the calorimeter response has a significant impact on the accuracy of the jet energy measurement. A study of the calorimeter intercalibration using QCD dijet events is presented in the last part of the thesis. The intercalibration study is performed in azimuth angle φ and in pseudorapidity η. The performance of the calibration methods including possible systematic and statistical effects is described. (orig.)

  19. ATLAS calorimetry. Trigger, simulation and jet calibration

    Energy Technology Data Exchange (ETDEWEB)

    Weber, P.

    2007-02-06

    The Pre-Processor system of the ATLAS Level-1 Calorimeter Trigger performs complex processing of analog trigger tower signals from electromagnetic and hadronic calorimeters. The main processing block of the Pre-Processor System is the Multi-Chip Module (MCM). The first part of this thesis describes MCM quality assurance tests that have been developed, their use in the MCM large scale production and the results that have been obtained. In the second part of the thesis a validation of a shower parametrisation model for the ATLAS fast simulation package ATLFAST based on QCD dijet events is performed. A detailed comparison of jet response and jet energy resolution between the fast and the full simulation is presented. The uniformity of the calorimeter response has a significant impact on the accuracy of the jet energy measurement. A study of the calorimeter intercalibration using QCD dijet events is presented in the last part of the thesis. The intercalibration study is performed in azimuth angle {phi} and in pseudorapidity {eta}. The performance of the calibration methods including possible systematic and statistical effects is described. (orig.)

  20. The ATLAS Level-1 Calorimeter Trigger Architecture

    CERN Document Server

    Garvey, J; Mahout, G; Moye, T H; Staley, R J; Watkins, P M; Watson, A T; Achenbach, R; Hanke, P; Kluge, E E; Meier, K; Meshkov, P; Nix, O; Penno, K; Schmitt, K; Ay, Cc; Bauss, B; Dahlhoff, A; Jakobs, K; Mahboubi, K; Schäfer, U; Trefzger, T M; Eisenhandler, E F; Landon, M; Moyse, E; Thomas, J; Apostoglou, P; Barnett, B M; Brawn, I P; Davis, A O; Edwards, J; Gee, C N P; Gillman, A R; Perera, V J O; Qian, W; Bohm, C; Hellman, S; Hidvégi, A; Silverstein, S; RT 2003 13th IEEE-NPSS Real Time Conference

    2004-01-01

    The architecture of the ATLAS Level-1 Calorimeter Trigger system (L1Calo) is presented. Common approaches have been adopted for data distribution, result merging, readout, and slow control across the three different subsystems. A significant amount of common hardware is utilized, yielding substantial savings in cost, spares, and development effort. A custom, high-density backplane has been developed with data paths suitable for both the em/tt cluster processor (CP) and jet/energy-summation processor (JEP) subsystems. Common modules also provide interfaces to VME, CANbus and the LHC Timing, Trigger and Control system (TTC). A common data merger module (CMM) uses FPGAs with multiple configurations for summing electron/photon and tau/hadron cluster multiplicities, jet multiplicities, or total and missing transverse energy. The CMM performs both crate- and system-level merging. A common, FPGA-based readout driver (ROD) is used by all of the subsystems to send input, intermediate and output data to the data acquis...

  1. Studies for the development of the Inner Detector trigger algorithms at ATLAS

    CERN Document Server

    The ATLAS collaboration

    2013-01-01

    A description of the ATLAS Inner Detector (ID) sofware trigger algorithms running online on the high level trigger (HLT) processor farm is presented. The prospects for a redesign of the ID trigger afforded by the 2013-2014 long shutdown are discussed. The ID trigger HLT algorithms are essential for many trigger signatures within the ATLAS trigger. During the shutdown, the ATLAS HLT software will be restructured to run in a single stage rather than in the two distinct levels present during the Run I operation. This poses significant challenges for the trigger algorithms both in terms of execution time, and physics perfor- mance. Expected future improvements in the timing and efficiencies of the Inner Detector triggers within the new merged single stage architecture are also discussed. In addition, potential improvements in the algorithm performance resulting from the additional spacepoint information from the new Insertable B-Layer are also presented.

  2. A lock circuit for a multi-core processor

    OpenAIRE

    Strøm, Torur Biskopstø

    2015-01-01

    An integrated circuit comprising a multiple processor cores and a lock circuit that comprises a queue register with respective bits set or reset via respective, connections dedicated to respective processor cores, whereby the queue register identifies those among the multiple processor cores that are enqueued in the queue register. Furthermore, the integrated circuit comprises a current register and a selector circuit configured to select a processor core and identify that processor core by a...

  3. Fault-tolerant parallel processor

    Energy Technology Data Exchange (ETDEWEB)

    Harper, R.E.; Lala, J.H. (Charles Stark Draper Laboratory, Inc., Cambridge, MA (USA))

    1991-06-01

    This paper addresses issues central to the design and operation of an ultrareliable, Byzantine resilient parallel computer. Interprocessor connectivity requirements are met by treating connectivity as a resource that is shared among many processing elements, allowing flexibility in their configuration and reducing complexity. Redundant groups are synchronized solely by message transmissions and receptions, which aslo provide input data consistency and output voting. Reliability analysis results are presented that demonstrate the reduced failure probability of such a system. Performance analysis results are presented that quantify the temporal overhead involved in executing such fault-tolerance-specific operations. Empirical performance measurements of prototypes of the architecture are presented. 30 refs.

  4. Functional Verification of Enhanced RISC Processor

    Directory of Open Access Journals (Sweden)

    SHANKER NILANGI

    2013-10-01

    Full Text Available This paper presents design and verification of a 32-bit enhanced RISC processor core having floating point computations integrated within the core, has been designed to reduce the cost and complexity. The designed 3 stage pipelined 32-bit RISC processor is based on the ARM7 processor architecture with single precision floating point multiplier, floating point adder/subtractor for floating point operations and 32 x 32 booths multiplier added to the integer core of ARM7. The binary representation of the floating point numbers employed in the design eliminates the need for floating point registers and uses same set of registers thereby reducing the complexity, area and cost. Mask based data reversal barrel shifter performs parallel flag computations during shift or rotate and has least worst case delay of 0.94 ns compared to other barrel shifters. The hardware of the 32-bit RISC processor core has been modeled in Verilog HDL, simulated in VCS. Verification of a complex design such as 32-bit RISC is one of the major challenges as it consumes more time. In this work, a verification environment is being developed to verify the design RISC processor core.

  5. Direct Processor Access for Non Dedicated Server using Multi Core Processor

    Directory of Open Access Journals (Sweden)

    P. S. BALAMURUGAN,

    2010-08-01

    Full Text Available The objective of the paper is to design a co processor for a desktop machine which enables the machine to act as non dedicated server, such that the co processor will act as a server processor and the multi-core processor to act as desktop processor. By implementing this methodology a client machine can be made to act as a non dedicated server and a client machine. This type of machine can be used in autonomy networks. This design will lead to design of a cost effective server and machine which can parallel act as a non dedicatedserver and a client machine or it can be made to switch and act as client or server.

  6. Run-Time Adaptive Processor Allocation of Self-Configurable Intel IXP2400 Network Processor

    Directory of Open Access Journals (Sweden)

    A.Satheesh

    2010-03-01

    Full Text Available An ideal Network Processor, that is, a programmable multi-processor device must be capable of offering both the flexibility and speed required for packet processing. But current Network Processor systems generally fall short of the above benchmarks due to traffic fluctuations inherent in packet networks, and the resulting workload variation on individual pipeline stage over a period of time ultimately affects the overall performance of even an otherwise sound system. One potential solution would be to change the code running at these stages so as to adapt to the fluctuations; a near robust system with standing traffic fluctuations is the dynamic adaptive processor, reconfiguring the entire system, which we introduce and study to some extent in this paper. We achieve this by using a crucial decision making model, transferring the binary code to the processor through the SOAP protocol.

  7. The read-out processors of the Aleph time projection chamber and their performance

    International Nuclear Information System (INIS)

    The Aleph detector is installed on the LEP electron-positron storage ring. Its central tracking detector, a time projection chamber, has about 50,000 channels of sampling electronics. The digitized signals are processed by 72 double width Fastbus modules, built around an MC 68020 processor. The time projection processor is described and the solutions, both hardware and software, adopted to run and manage such a complex system in a Fastbus-VAX environment are discussed. Practical experience with the system is reported

  8. Parallel Neutrino Triggers using GPUs for an underwater telescope

    CERN Document Server

    Bouhadef, Bachir; Terreni, Giuseppe

    2014-01-01

    Graphics Processing Units are high performance co-processors originally intended to improve the use and the acceleration of computer graphics applications. Because of their performance, researchers have extended their use beyond the computer graphics scope. We have investigate the possibility of implementing and speeding up online neutrino trigger algorithms in the KM3Net-It experiment using a CPU-GPU system. The results of a neutrino trigger simulation on NEMO Phase II tower and a KM3-It 14 floors Tower are reported.

  9. Neural second-level trigger system based on calorimetry

    Science.gov (United States)

    Seixas, J. M.; Caloba, L. P.; Souza, M. N.; Braga, A. L.; Rodrigues, A. P.

    1996-06-01

    A second-level triggering system based on calorimetry is analyzed using neural networks. Calorimeter data in a LHC environment is obtained with Monte Carlo simulations and an algorithm for the first-level trigger operation is applied. The surviving events are then available as a 20×20 matrix information corresponding to the calorimeter towers in the region of interest. The dominant background for triggering on electrons is assumed to consist of QCD jets which passed the first-level trigger condition. The main features of the calorimeter are extracted. Matrix information, shower deposition in concentric rings and tail weighting procedures are studied. The processed information is sent to a fully connected backpropagation neural network. In this analysis we also consider pileup effects of an average of 20 minimum bias events. The neural network based system achieved up to 99% electron efficiency with less than 9% of jets being misclassified as electrons. Implementation on digital signal processors is suggested.

  10. Criticality calculations on BARC parallel processor- ANUPAM

    International Nuclear Information System (INIS)

    Parallel processing offers an increase in computational speed beyond the technological limitations of single processor systems. BARC has recently developed a parallel processing system (ANUPAM) based Multiple Instruction Multiple Data (MIMD) distributed memory architecture. In the work reported here, the sequential version of Monte Carlo code MONALI is modified to work on the ANUPAM for criticality calculations. The problem of random number generation in a parallel environment is handled using leapfrog technique. The code is modified to use variable number of slave processors. The parallel version of MONALI is used to calculate multiplication factor, fluxes and absorptions in one of the 8x8 fuel assemblies of IAEA BWR benchmark in 69 groups. To compare gain in execution time, the benchmark is also solved on LANDMARK and ND-570 systems (both serial) using the sequential version of the code. Speedup and efficiencies achieved on varying the number of slave processors are encouraging. (author). 5 refs., 1 tab

  11. SWIFT Privacy: Data Processor Becomes Data Controller

    Directory of Open Access Journals (Sweden)

    Edwin Jacobs

    2007-04-01

    Full Text Available Last month, SWIFT emphasised the urgent need for a solution to compliance with US Treasury subpoenas that provides legal certainty for the financial industry as well as for SWIFT. SWIFT will continue its activities to adhere to the Safe Harbor framework of the European data privacy legislation. Safe Harbor is a framework negotiated by the EU and US in 2000 to provide a way for companies in Europe, with operations in the US, to conform to EU data privacy regulations. This seems to conclude a complex privacy case, widely covered by the US and European media. A fundamental question in this case was who is a data controller and who is a mere data processor. Both the Belgian and the European privacy authorities considered SWIFT, jointly with the banks, as a data controller whereas SWIFT had considered itself as a mere data processor that processed financial data for banks. The difference between controller and processor has far reaching consequences.

  12. Programmable DNA-mediated multitasking processor

    CERN Document Server

    Shu, Jian-Jun; Yong, Kian-Yan; Shao, Fangwei; Lee, Kee Jin

    2015-01-01

    Because of DNA appealing features as perfect material, including minuscule size, defined structural repeat and rigidity, programmable DNA-mediated processing is a promising computing paradigm, which employs DNAs as information storing and processing substrates to tackle the computational problems. The massive parallelism of DNA hybridization exhibits transcendent potential to improve multitasking capabilities and yield a tremendous speed-up over the conventional electronic processors with stepwise signal cascade. As an example of multitasking capability, we present an in vitro programmable DNA-mediated optimal route planning processor as a functional unit embedded in contemporary navigation systems. The novel programmable DNA-mediated processor has several advantages over the existing silicon-mediated methods, such as conducting massive data storage and simultaneous processing via much fewer materials than conventional silicon devices.

  13. Control structures for high speed processors

    Science.gov (United States)

    Maki, G. K.; Mankin, R.; Owsley, P. A.; Kim, G. M.

    1982-01-01

    A special processor was designed to function as a Reed Solomon decoder with throughput data rate in the Mhz range. This data rate is significantly greater than is possible with conventional digital architectures. To achieve this rate, the processor design includes sequential, pipelined, distributed, and parallel processing. The processor was designed using a high level language register transfer language. The RTL can be used to describe how the different processes are implemented by the hardware. One problem of special interest was the development of dependent processes which are analogous to software subroutines. For greater flexibility, the RTL control structure was implemented in ROM. The special purpose hardware required approximately 1000 SSI and MSI components. The data rate throughput is 2.5 megabits/second. This data rate is achieved through the use of pipelined and distributed processing. This data rate can be compared with 800 kilobits/second in a recently proposed very large scale integration design of a Reed Solomon encoder.

  14. ETHERNET PACKET PROCESSOR FOR SOC APPLICATION

    Directory of Open Access Journals (Sweden)

    Raja Jitendra Nayaka

    2012-07-01

    Full Text Available As the demand for Internet expands significantly in numbers of users, servers, IP addresses, switches and routers, the IP based network architecture must evolve and change. The design of domain specific processors that require high performance, low power and high degree of programmability is the bottleneck in many processor based applications. This paper describes the design of ethernet packet processor for system-on-chip (SoC which performs all core packet processing functions, including segmentation and reassembly, packetization classification, route and queue management which will speedup switching/routing performance. Our design has been configured for use with multiple projects ttargeted to a commercial configurable logic device the system is designed to support 10/100/1000 links with a speed advantage. VHDL has been used to implement and simulated the required functions in FPGA.

  15. Boosted object hardware trigger development and testing for the Phase I upgrade of the ATLAS Experiment

    Science.gov (United States)

    Stark, Giordon; Atlas Collaboration

    2015-04-01

    The Global Feature Extraction (gFEX) module is a Level 1 jet trigger system planned for installation in ATLAS during the Phase 1 upgrade in 2018. The gFEX selects large-radius jets for capturing Lorentz-boosted objects by means of wide-area jet algorithms refined by subjet information. The architecture of the gFEX permits event-by-event local pile-up suppression for these jets using the same subtraction techniques developed for offline analyses. The gFEX architecture is also suitable for other global event algorithms such as missing transverse energy (MET), centrality for heavy ion collisions, and ``jets without jets.'' The gFEX will use 4 processor FPGAs to perform calculations on the incoming data and a Hybrid APU-FPGA for slow control of the module. The gFEX is unique in both design and implementation and substantially enhance the selectivity of the L1 trigger and increases sensitivity to key physics channels.

  16. Boosted object hardware trigger development and testing for the Phase I upgrade of the ATLAS Experiment

    CERN Document Server

    Stark, Giordon Holtsberg; The ATLAS collaboration

    2015-01-01

    The Global Feature Extraction (gFEX) module is a Level 1 jet trigger system planned for installation in ATLAS during the Phase 1 upgrade in 2018. The gFEX selects large-radius jets for capturing Lorentz-boosted objects by means of wide-area jet algorithms refined by subjet information. The architecture of the gFEX permits event-by-event local pile-up suppression for these jets using the same subtraction techniques developed for offline analyses. The gFEX architecture is also suitable for other global event algorithms such as missing transverse energy (MET), centrality for heavy ion collisions, and "jets without jets". The gFEX will use 4 processor FPGAs to perform calculations on the incoming data and a Hybrid APU-FPGA for slow control of the module. The gFEX is unique in both design and implementation and substantially enhance the selectivity of the L1 trigger and increases sensitivity to key physics channels.

  17. The LVL2 trigger goes online

    CERN Multimedia

    David Berge

    On Friday, the 9th of February, the ATLAS TDAQ community reached an important milestone. In a successful integration test, cosmic-ray muons were recorded with parts of the muon spectrometer, the central-trigger system and a second-level trigger algorithm. This was actually the first time that a full trigger slice all the way from the first-level trigger muon chambers up to event building after event selection by the second-level trigger ran online with cosmic rays. The ATLAS trigger and data acquisition system has a three-tier structure that is designed to cope with the enormous demands of proton-proton collisions at a bunch-crossing frequency of 40 MHz, with a typical event size of 1-2 MB. The online event selection has to reduce the incoming rate by a factor of roughly 200,000 to 200 Hz, a rate digestible by the archival-storage and offline-processing facilities. ATLAS has a mixed system: the first-level trigger (LVL1) is in hardware, while the other two consecutive levels, the second-level trigger (LVL2)...

  18. The ATLAS online High Level Trigger framework: Experience reusing offline software components in the ATLAS trigger

    International Nuclear Information System (INIS)

    Event selection in the ATLAS High Level Trigger is accomplished to a large extent by reusing software components and event selection algorithms developed and tested in an offline environment. Many of these offline software modules are not specifically designed to run in a heavily multi-threaded online data flow environment. The ATLAS High Level Trigger (HLT) framework based on the GAUDI and ATLAS ATHENA frameworks, forms the interface layer, which allows the execution of the HLT selection and monitoring code within the online run control and data flow software. While such an approach provides a unified environment for trigger event selection across all of ATLAS, it also poses strict requirements on the reused software components in terms of performance, memory usage and stability. Experience of running the HLT selection software in the different environments and especially on large multi-node trigger farms has been gained in several commissioning periods using preloaded Monte Carlo events, in data taking periods with cosmic events and in a short period with proton beams from LHC. The contribution discusses the architectural aspects of the HLT framework, its performance and its software environment within the ATLAS computing, trigger and data flow projects. Emphasis is also put on the architectural implications for the software by the use of multi-core processors in the computing farms and the experiences gained with multi-threading and multi-process technologies.

  19. Multi-core processors - An overview

    CERN Document Server

    Venu, Balaji

    2011-01-01

    Microprocessors have revolutionized the world we live in and continuous efforts are being made to manufacture not only faster chips but also smarter ones. A number of techniques such as data level parallelism, instruction level parallelism and hyper threading (Intel's HT) already exists which have dramatically improved the performance of microprocessor cores. This paper briefs on evolution of multi-core processors followed by introducing the technology and its advantages in today's world. The paper concludes by detailing on the challenges currently faced by multi-core processors and how the industry is trying to address these issues.

  20. Software-defined reconfigurable microwave photonics processor.

    Science.gov (United States)

    Pérez, Daniel; Gasulla, Ivana; Capmany, José

    2015-06-01

    We propose, for the first time to our knowledge, a software-defined reconfigurable microwave photonics signal processor architecture that can be integrated on a chip and is capable of performing all the main functionalities by suitable programming of its control signals. The basic configuration is presented and a thorough end-to-end design model derived that accounts for the performance of the overall processor taking into consideration the impact and interdependencies of both its photonic and RF parts. We demonstrate the model versatility by applying it to several relevant application examples. PMID:26072824

  1. Efficient SIMD optimization for media processors

    Institute of Scientific and Technical Information of China (English)

    Jian-peng ZHOU; Ce SHI

    2008-01-01

    Single instruction multiple data (SIMD) instructions are often implemented in modem media processors. Although SIMD instructions are useful in multimedia applications, most compilers do not have good support for SIMD instructions. This paper focuses on SIMD instructions generation for media processors. We present an efficient code optimization approach that is integrated into a retargetable C compiler. SIMD instructions are generated by finding and combining the same operations in programs. Experimental results for the UltraSPARC VIS instruction set show that a speedup factor up to 2.639 is obtained.

  2. Time Manager Software for a Flight Processor

    Science.gov (United States)

    Zoerne, Roger

    2012-01-01

    Data analysis is a process of inspecting, cleaning, transforming, and modeling data to highlight useful information and suggest conclusions. Accurate timestamps and a timeline of vehicle events are needed to analyze flight data. By moving the timekeeping to the flight processor, there is no longer a need for a redundant time source. If each flight processor is initially synchronized to GPS, they can freewheel and maintain a fairly accurate time throughout the flight with no additional GPS time messages received. How ever, additional GPS time messages will ensure an even greater accuracy. When a timestamp is required, a gettime function is called that immediately reads the time-base register.

  3. A lock circuit for a multi-core processor

    DEFF Research Database (Denmark)

    2015-01-01

    An integrated circuit comprising a multiple processor cores and a lock circuit that comprises a queue register with respective bits set or reset via respective, connections dedicated to respective processor cores, whereby the queue register identifies those among the multiple processor cores that...... are enqueued in the queue register. Furthermore, the integrated circuit comprises a current register and a selector circuit configured to select a processor core and identify that processor core by a value in the current register. A selected processor core is a prioritized processor core among the...... cores that have a bit that is set in the queue register. The processor cores are connected to receive a signal from the current register. Correspondingly: a method of synchronizing access to software and/or hardware resources by a core of a multi-core processor by means of a lock circuit; a multi...

  4. Topology in the future ATLAS Level-1 Trigger

    CERN Document Server

    Kahra, C; The ATLAS collaboration

    2014-01-01

    The ATLAS experiment examines the decays of high energetic particles produced in proton-proton collisions at the Large Hadron Collider (LHC). Resuming operation at the beginning of 2015 for Run 2 the LHC will work with an increased center-of-mass energy of $13-14 \\mathrm{TeV}$, which will result in an unprecedented luminosity. The first trigger level (Level-1) of the ATLAS trigger system, based on custom-made electronic modules, needs to be upgraded to control the increased trigger rate, while keeping good efficiency for interesting physics events. In Run 1 the Level-1 trigger decisions were mostly based only on multiplicities of trigger objects (such as electrons / photons, jets, hadrons, muons above energy/momentum thresholds) observed in the calorimeters and the muon spectrometer. As part of the Level-1 upgrade a new trigger module, the topological processor (L1Topo) will be included into the trigger chain. It is intended to evaluate the spatial correlations of trigger objects and to perform more complex k...

  5. Antibody producing B lineage cells invade the central nervous system predominantly at the time of and triggered by acute Epstein-Barr virus infection: A hypothesis on the origin of intrathecal immunoglobulin synthesis in multiple sclerosis.

    Science.gov (United States)

    Otto, Carolin; Hofmann, Jörg; Ruprecht, Klemens

    2016-06-01

    Patients with multiple sclerosis (MS), a chronic inflammatory disease of the central nervous system (CNS), typically have an intrathecal synthesis of immunoglobulin (Ig)G. Intrathecal IgG is produced by B lineage cells that entered the CNS, but why and when these cells invade the CNS of patients with MS is unknown. The intrathecal IgG response in patients with MS is polyspecific and part of it is directed against different common viruses (e.g. measles virus, rubella virus, varicella zoster virus). Strong and consistent evidence suggests an association of MS and Epstein-Barr virus (EBV) infection and EBV seroprevalence in patients with MS is practically 100%. However, intriguingly, despite of the universal EBV seroprevalence, the frequency of intrathecally produced IgG to EBV in patients with MS is much lower than that of intrathecally produced IgG to other common viruses. The acute phase of primary EBV infection is characterized by a strong polyclonal B cell activation. As typical for humoral immune responses against viruses, EBV specific IgG is produced only with a temporal delay after acute EBV infection. Aiming to put the above facts into a logical structure, we here propose the hypothesis that in individuals going on to develop MS antibody producing B lineage cells invade the CNS predominantly at the time of and triggered by acute primary EBV infection. Because at the time of acute EBV infection EBV IgG producing B lineage cells have not yet occurred, the hypothesis could explain the universal EBV seroprevalence and the low frequency of intrathecally produced IgG to EBV in patients with MS. Evidence supporting the hypothesis could be provided by large prospective follow-up studies of individuals with symptomatic primary EBV infection (infectious mononucleosis). Furthermore, the clarification of the molecular mechanism underlying an EBV induced invasion of B lineage cells into the CNS of individuals going on to develop MS could corroborate it, too. If true, our

  6. Comparison of Processor Performance of SPECint2006 Benchmarks of some Intel Xeon Processors

    Directory of Open Access Journals (Sweden)

    Abdul Kareem PARCHUR

    2012-08-01

    Full Text Available High performance is a critical requirement to all microprocessors manufacturers. The present paper describes the comparison of performance in two main Intel Xeon series processors (Type A: Intel Xeon X5260, X5460, E5450 and L5320 and Type B: Intel Xeon X5140, 5130, 5120 and E5310. The microarchitecture of these processors is implemented using the basis of a new family of processors from Intel starting with the Pentium 4 processor. These processors can provide a performance boost for many key application areas in modern generation. The scaling of performance in two major series of Intel Xeon processors (Type A: Intel Xeon X5260, X5460, E5450 and L5320 and Type B: Intel Xeon X5140, 5130, 5120 and E5310 has been analyzed using the performance numbers of 12 CPU2006 integer benchmarks, performance numbers that exhibit significant differences in performance. The results and analysis can be used by performance engineers, scientists and developers to better understand the performance scaling in modern generation processors.

  7. Design and use of a PPMC processor as shared-memory SCI node

    CERN Document Server

    Altmann, D; Müller, H; Toledo, J

    2002-01-01

    The MCU mezzanine was designed as a networked processor-PMC for monitoring and control in the LHCb Readout Unit (RU) with remote boot capability. As PCI monarch on the RU, it configures all PCI devices (FPGAs and readout network interface) that can then be used by user programs running under the LINUX operating system. A new MCU application is within the LHCb L1-Velo trigger where a CPU-farm is interconnected by a 2-dimensional SCI network, with event data input from RU modules at each row of the network: the SCI interface on the RU is hosted by the MCU which exports and imports shareable memory with the trigger farm in order to quasi become part as one of it's CPU. After this initialisation, the hardware DMA engines of the RU can transfer trigger data, by using physical PCI addresses that directly map to the remote CPU memory. (10 refs).

  8. Tidal triggering of earthquakes

    OpenAIRE

    Heaton, Thomas H.

    1982-01-01

    Analysis of the tidal stress tensor at the time of moderate to large earthquakes strongly suggests that shallow (< 30 km) larger magnitude oblique-slip and dip-slip earthquakes are triggered by tidal stresses. No corresponding triggering effect is seen for shallow strike-slip earthquakes or for any type of intermediate or deep focus earthquakes which have been studied. Tidal triggering is also discussed from the viewpoint of the ‘dilatancy-diffusion’ model. Specifically, the model as usually ...

  9. gFEX, the ATLAS Calorimeter Level 1 Real Time Processor

    CERN Document Server

    Tang, Shaochun; The ATLAS collaboration

    2015-01-01

    The global feature extractor (gFEX) is a component of the Level-1Calorimeter trigger Phase-I upgrade for the ATLAS experiment. It is intended to identify patterns of energy associated with the hadronic decays of high momentum Higgs, W, & Z bosons, top quarks, and exotic particles in real time at the LHC crossing rate. The single processor board will be packaged in an Advanced Telecommunications Computing Architecture (ATCA) module and implemented as a fast reconfigurable processor based on three Xilinx Ultra-scale FPGAs. The board will receive coarse-granularity information from all the ATLAS calorimeters on 264 optical fibers with the data transferred at the 40 MHz LHC clock frequency. The gFEX will be controlled by a single system-on-chip processor, ZYNQ, that will be used to configure all the processor FPGAs, monitor board health, and interface to external signals. Now, the pre-prototype board which includes one ZYNQ and one Vertex-7 FPGA has been designed for testing and verification. The performance ...

  10. gFEX, the ATLAS Calorimeter Level-1 Real Time Processor

    CERN Document Server

    Tang, Shaochun; The ATLAS collaboration; Chen, Hucheng; Lanni, Francesco; Takai, Helio; Wu, Weihao

    2015-01-01

    The global feature extractor (gFEX) is a component of the Level-1 Calorimeter trigger Phase-I upgrade for the ATLAS experiment. It is intended to identify patterns of energy associated with the hadronic decays of high momentum Higgs, W, & Z bosons, top quarks, and exotic particles in real time at the LHC crossing rate. The single processor board will be packaged in an Advanced Telecommunications Computing Architecture (ATCA) module and implemented as a fast reconfigurable processor based on three Xilinx Vertex Ultra-scale FPGAs. The board will receive coarse-granularity information from all the ATLAS calorimeters on 276 optical fibers with the data transferred at the 40 MHz Large Hadron Collider (LHC) clock frequency. The gFEX will be controlled by a single system-on-chip processor, ZYNQ, that will be used to configure all the processor Field-Programmable Gate Array (FPGAs), monitor board health, and interface to external signals. Now, the pre-prototype board which includes one ZYNQ and one Vertex-7 FPGA ...

  11. Inter Processor Communication for Fault Diagnosis in Multiprocessor Systems

    Directory of Open Access Journals (Sweden)

    C. D. Malleswar

    1994-04-01

    Full Text Available In the preseJlt paper a simple technique is proposed for fault diagnosis for multiprocessor and multiple system environments, wherein all microprocessors in the system are used in part to check the health of their neighbouring processors. It involves building simple fail-safe serial communication links between processors. Processors communicate with each other over these links and each processor is made to go through certain sequences of actions intended for diagnosis, under the observation of another processor .With limited overheads, fault detection can be done by this method. Also outlined are some of the popular techniques used for health check of processor-based systems.

  12. Design of Variable Width Barrel Shifter for High Speed Processor Architecture

    Directory of Open Access Journals (Sweden)

    Rajeev Kumar

    2012-04-01

    Full Text Available Microprocessor is the brain of the computer. It works as the Central Processing Unit of the computer. It contains Arithmetic Logical Unit (ALU that performs the arithmetic operations such as Addition, Subtraction, Multiplication and Division. It also performs the Logical operations such as AND, NAND, OR, NOR, EXOR, EXNOR and NOT. It also contains register file to store the operand in load/store instructions in RISC Processor Architecture. Control Unit genetares the control signals that synchronize the operation of the processor which tells the microarchitecture which operation is done at which time. Now during the multiplication partial product is shifted and added. So shifter is an important part of the processor architecture. Barrel Shifter is an important combinational logic block. It was incorporated in 386 processor and is also used in microcontroller design. Intel has since moved to software implemented shifters in the Pentium 4 Processor Architecture but AMD still uses it. Here the design of the variable width barrel shifter is presented in which we can shift 4bit, 8bit, 16bit, and 32bit and maximum 64bit partial product during multiplication. Functionality is check using Modelsim 6.4a.Now to generate the gate level netlist Xilinx ISE 9.2i is used.

  13. Globe hosts launch of new processor

    CERN Multimedia

    2006-01-01

    Launch of the quadecore processor chip at the Globe. On 14 November, in a series of major media events around the world, the chip-maker Intel launched its new 'quadcore' processor. For the regions of Europe, the Middle East and Africa, the day-long launch event took place in CERN's Globe of Science and Innovation, with over 30 journalists in attendance, coming from as far away as Johannesburg and Dubai. CERN was a significant choice for the event: the first tests of this new generation of processor in Europe had been made at CERN over the preceding months, as part of CERN openlab, a research partnership with leading IT companies such as Intel, HP and Oracle. The event also provided the opportunity for the journalists to visit ATLAS and the CERN Computer Centre. The strategy of putting multiple processor cores on the same chip, which has been pursued by Intel and other chip-makers in the last few years, represents an important departure from the more traditional improvements in the sheer speed of such chips. ...

  14. A high-speed analog neural processor

    NARCIS (Netherlands)

    Masa, Peter; Hoen, Klaas; Wallinga, Hans

    1994-01-01

    Targeted at high-energy physics research applications, our special-purpose analog neural processor can classify up to 70 dimensional vectors within 50 nanoseconds. The decision-making process of the implemented feedforward neural network enables this type of computation to tolerate weight discretiza

  15. Analysis of Reconfigurable Processors Using Petri Net

    Directory of Open Access Journals (Sweden)

    Hadis Heidari

    2013-07-01

    Full Text Available In this paper, we propose Petri net models for processing elements. The processing elements include: a general-purpose processor (GPP, a reconfigurable element (RE, and a hybrid element (combining a GPP with an RE. The models consist of many transitions and places. The model and associated analysis methods provide a promising tool for modeling and performance evaluation of reconfigurable processors. The model is demonstrated by considering a simple example. This paper describes the development of a reconfigurable processor; the developed system is based on the Petri net concept. Petri nets are becoming suitable as a formal model for hardware system design. Designers can use Petri net as a modeling language to perform high level analysis of complex processors designs processing chips. The simulation does with PIPEv4.1 simulator. The simulation results show that Petri net state spaces are bounded and safe and have not deadlock and the average of number tokens in first token is 0.9901 seconds. In these models, there are only 5% errors; also the analysis time in these models is 0.016 seconds.

  16. Practical guide to energy management for processors

    CERN Document Server

    Consortium, Energywise

    2012-01-01

    Do you know how best to manage and reduce your energy consumption? This book gives comprehensive guidance on effective energy management for organisations in the polymer processing industry. This book is one of three which support the ENERGYWISE Plastics Project eLearning platform for European plastics processors to increase their knowledge and understanding of energy management. Topics covered include: Understanding Energy,

  17. Continuous history variable for programmable quantum processors

    OpenAIRE

    Vlasov, Alexander Yu.

    2010-01-01

    In this brief note is discussed application of continuous quantum history ("trash") variable for simplification of scheme of programmable quantum processor. Similar scheme may be tested also in other models of the theory of quantum algorithms and complexity, because provides modification of a standard operation: quantum function evaluation.

  18. Space Station Water Processor Process Pump

    Science.gov (United States)

    Parker, David

    1995-01-01

    This report presents the results of the development program conducted under contract NAS8-38250-12 related to the International Space Station (ISS) Water Processor (WP) Process Pump. The results of the Process Pumps evaluation conducted on this program indicates that further development is required in order to achieve the performance and life requirements for the ISSWP.

  19. A Demo Processor as an Educational Tool

    NARCIS (Netherlands)

    van Moergestel, L.; van Nieuwland, K.; Vermond, L.; Meyer, John-Jules Charles

    2014-01-01

    Explaining the workings of a processor can be done in several ways. Just a written explanation, some pictures, a simulator program or a real hardware demo. The research presented here is based on the idea that a slowly working hardware demo could be a nice tool to explain to IT students the inner wo

  20. Microarchitecture of the Godson-2 Processor

    Institute of Scientific and Technical Information of China (English)

    Wei-Wu Hu; Fu-Xin Zhang; Zu-Song Li

    2005-01-01

    The Godson project is the first attempt to design high performance general-purpose microprocessors in China.This paper introduces the microarchitecture of the Godson-2 processor which is a 64-bit, 4-issue, out-of-order execution RISC processor that implements the 64-bit MIPS-like instruction set. The adoption of the aggressive out-of-order execution techniques (such as register mapping, branch prediction, and dynamic scheduling) and cache techniques (such as non-blocking cache, load speculation, dynamic memory disambiguation) helps the Godson-2 processor to achieve high performance even at not so high frequency. The Godson-2 processor has been physically implemented on a 6-metal 0.18μm CMOS technology based on the automatic placing and routing flow with the help of some crafted library cells and macros. The area of the chip is 6,700 micrometers by 6,200 micrometers and the clock cycle at typical corner is 2.3ns.

  1. Aladdin signal processor and architecture modeling

    Science.gov (United States)

    Branstetter, Reagan; Harper, Angela; Denton, Larry

    1993-10-01

    Texas Instruments (TI) is developing the Aladdin computer under contract with the U. S. Army Communications and Electronics Command (CECOM). The program is sponsored by the Defense Advanced Research Projects Agency (DARPA) and the U. S. Army Night Vision and Electro-Optics Directorate (NVEOD). Processors currently available for today's advanced weapons systems are limited in their real-time processing capabilities and are generally specific to a selected mission. The lack of availability of a high performance, general purpose, programmable processor in a small volume applicable to a variety of weapons systems applications creates a high non-recurring development cost for each new program. Automatic target acquisition systems are specifically in need of processors that meet the required real- time processing throughput of a variety of algorithms within very restrictive volume constraints. The objective of the Aladdin program is to develop a very high performance miniature processor that fits within a 75 cubic inch cylindrical volume, and is easily programmable to provide the ability to detect, recognize, identify, and locate the optimal aimpoint of a target or targets.

  2. Acousto-Optical/Electronic Processor For SAR

    Science.gov (United States)

    Bicknell, T. J.; Farr, W. H.

    1992-01-01

    Lightweight, compact, low-power apparatus processes synthetic-aperture-radar (SAR) returns in real time, providing imagery aboard moving aircraft or spacecraft platform. Processor includes optical and electronic subsystems that, together, resolve range and azimuth coordinates of radar targets by combination of spatial and temporal integrations.

  3. The design and performance of the ATLAS Inner Detector trigger for Run 2

    CERN Document Server

    Penc, Ondrej; The ATLAS collaboration

    2015-01-01

    The design and performance of the ATLAS Inner Detector (ID) trigger algorithms running online on the high level trigger (HLT) processor farm with the early LHC Run 2 data are discussed. The redesign of the ID trigger, which took place during the 2013-15 long shutdown, in order to satisfy the demands of the higher energy LHC Run 2 operation is described. The ID trigger HLT algorithms are essential for nearly all trigger signatures within the ATLAS trigger. The detailed performance of the tracking algorithms with the early Run 2 data for the different trigger signatures is presented, including the detailed timing performance for the algorithms running on the redesigned single stage ATLAS HLT Farm. Comparison with the Run 1 strategy are made and demonstrate the superior performance of the strategy adopted for Run 2.

  4. The design and performance of the ATLAS Inner Detector trigger for Run 2

    CERN Document Server

    Penc, Ondrej; The ATLAS collaboration

    2016-01-01

    The design and performance of the ATLAS Inner Detector (ID) trigger algorithms running online on the high level trigger (HLT) processor farm with the early LHC Run 2 data are discussed. The redesign of the ID trigger, which took place during the 2013-15 long shutdown, in order to satisfy the demands of the higher energy LHC Run 2 operation is described. The ID trigger HLT algorithms are essential for nearly all trigger signatures within the ATLAS trigger. The detailed performance of the tracking algorithms with the early Run 2 data for the different trigger signatures is presented, including the detailed timing performance for the algorithms running on the redesigned single stage ATLAS HLT Farm. Comparison with the Run 1 strategy are made and demonstrate the superior performance of the strategy adopted for Run 2.

  5. Trigger algorithms and electronics for the ATLAS muon new small wheel upgrade

    International Nuclear Information System (INIS)

    The New Small Wheel Upgrade for the ATLAS experiment will replace the innermost station of the Muon Spectrometer in the forward region in order to maintain its current performance during high luminosity data-taking after the LHC Phase-I upgrade. The New Small Wheel, comprising Micromegas and small Thin Gap Chambers, will reduce the rate of fake triggers coming from backgrounds in the forward region and significantly improve the Level-1 muon trigger selectivity by providing precise on-line segment measurements with ∼ 1 mrad angular resolution. Such demanding precision, together with the short time (∼ 1 μs) to prepare trigger data and perform on-line reconstruction, implies very stringent requirements on the design of trigger system and trigger electronics. This paper presents an overview of the design of the New Small Wheel trigger system, trigger algorithms and processor hardware

  6. Operational Experience of the ATLAS High Level Trigger with Single-Beam and Cosmic Rays

    CERN Document Server

    Aracena, I; The ATLAS collaboration

    2009-01-01

    After giving an overview of the ATLAS trigger design and its innovative features, this paper focuses on the operational experience gained in running the trigger in the fast-changing environment of the detector commissioning. It will emphasize the commissioning of the High Level Trigger (HLT) system, including its monitoring and configuration. Preliminary results from initial LHC running in 2009 will be included if available. ATLAS is one of two general-purpose detectors at the LHC. Using fast reconstruction algorithms, the trigger system needs to efficiently reject a large rate of background events while keeping potentially interesting ones with high efficiency. After a first level trigger implemented in custom electronics, the trigger selection is made by software running on two processor farms (the High Level Trigger system), containing a total of around two thousand multi-core machines. To reduce the network data traffic and the processing time to manageable levels, the HLT uses seeded, step-wise event rec...

  7. Operational Experience of the ATLAS High Level Trigger with Single-Beam and Cosmic Rays

    CERN Document Server

    Aracena, I; The ATLAS collaboration

    2009-01-01

    ATLAS is one of two general-purpose detectors at the LHC. Using fast reconstruction algorithms, the trigger system needs to efficiently reject a large rate of background events while keeping potentially interesting ones with high efficiency. After a first level trigger implemented in custom electronics, the trigger selection is made by software running on two processor farms (the High Level Trigger system), containing a total of around two thousand multi-core machines. To reduce the network data traffic and the processing time to manageable levels, the HLT uses seeded, step-wise event reconstruction, aiming at the earliest possible rejection of background events. The LHC start up and single-beam run periods in 2008 provided a "stress test" of the trigger system. Following this period, ATLAS continued to collect cosmic-ray events for detector alignment and calibration as well as for commissioning the trigger. These running periods allowed us to exercise the trigger system online, including its configuration an...

  8. Operation of the enhanced ATLAS First Level Calorimeter Trigger at the start of LHC Run-2

    CERN Document Server

    Palka, Marek; The ATLAS collaboration

    2015-01-01

    In 2015 the LHC is already operating with a higher center-of-mass energy and proton beams luminosity. To keep a high trigger efficiency against an increased event rate, part of ATLAS Level-1 Calorimeter Trigger electronics have been re-designed or newly introduced (Pre-Processors, Merging Modules and Topological Processors). Additionally, to achieve the best possible resolution for the reconstructed physics objects, complex calibration and monitoring systems are employed. Hit rates and energy spectra down to channel level, based on reconstructed events, are supervised with the calorimeter trigger hardware. In this paper the performance of the upgraded Level-1 Calorimeter Trigger at the beginning of LHC Run-2 is illustrated.

  9. Design and performance of the fermilab E781 (SELEX) hardware scattering trigger

    International Nuclear Information System (INIS)

    The design and performance of the Fermilab E781 (SELEX) Hardware Scattering Trigger (HST) are described. This trigger functioned by distinguishing beam scattering at small angles (>150 μrad) from non-interacting beam. Six 50 μm pitch silicon planes grouped in three (x,y) stations, two before and one after the target, were used as the particle detectors. The triggering system involved 1920 channels of readout providing data to the Fast Encoding and Readout System (FERS) with programmable trigger logic processor. The overall system was tested successfully at Fermilab during the 1996-1997 fixed target run. The encoding time of the readout part of the FERS device was 30 ns and the processor decision time was 55 ns. The HST provided an output signal 250 ns after beam traversal of the target

  10. Optical Spectra of Triggered Lightning

    Science.gov (United States)

    Walker, T. D.; Biagi, C. J.; Hill, J. D.; Jordan, D. M.; Uman, M. A.; Christian, H. J., Jr.

    2009-12-01

    In August 2009, the first optical spectra of triggered lightning flashes were acquired. Data from two triggered lightning flashes were obtained at the International Center for Lightning Research and Testing in north-central Florida. The spectrometer that was used has an average dispersion of 260 Å/mm resulting in an average resolution of 5 Å when mated to a Photron (SA1.1) high-speed camera. The spectra captured with this system had a free spectral range of 3800-8000 Å. The spectra were captured at 300,000 frames per second. The spectrometer's vertical field of view was 3 m at an altitude 50 m above the launch tower, intended to view the middle of the triggering wire. Preliminary results show that the copper spectrum dominated the earliest part of the flash and copper lines persisted during the total lifetime of the detectable spectrum. Animations over the lifetime of the stroke from the initial wire illumination to multiple return strokes show the evolution of the spectrum. In addition, coordinated high speed channel base current, electric field and imagery measurements of the exploding wire, downward leaders, and return strokes were recorded. Quantitative analysis of the spectral evolution will be discussed in the context of the overall flash development.

  11. AMY trigger system

    Energy Technology Data Exchange (ETDEWEB)

    Sakai, Yoshihide [National Laboratory for High Energy Physics, Tsukuba, Ibaraki (Japan)

    1989-04-01

    A trigger system of the AMY detector at TRISTAN e{sup +}e{sup -} collider is described briefly. The system uses simple track segment and shower cluster counting scheme to classify events to be triggered. It has been operating successfully since 1987.

  12. Data collection from FASTBUS to a DEC UNIBUS processor through the UNIBUS-Processor Interface

    International Nuclear Information System (INIS)

    This paper describes the use of the UNIBUS Processor Interface, an interface between FASTBUS and the Digital Equipment Corporation UNIBUS. The UPI was developed by Fermilab and the University of Illinois. Details of the use of this interface in a high energy physics experiment at Fermilab are given. The paper includes a discussion of the operation of the UPI on the UNIBUS of a VAX-11, and plans for using the UPI to perform data acquisition from FASTBUS to a VAX-11 Processor

  13. Research on seismic stress triggering

    Institute of Scientific and Technical Information of China (English)

    万永革; 吴忠良; 周公威; 黄静; 秦立新

    2002-01-01

    This paper briefly reviews basic theory of seismic stress triggering. Recent development on seismic stress triggering has been reviewed in the views of seismic static and dynamic stress triggering, application of viscoelastic model in seismic stress triggering, the relation between earthquake triggering and volcanic eruption or explosion, other explanation of earthquake triggering, etc. And some suggestions for further study on seismic stress triggering in near future are given.

  14. Array processors based on Gaussian fraction-free method

    Energy Technology Data Exchange (ETDEWEB)

    Peng, S.; Sedukhin, S. [Aizu Univ., Aizuwakamatsu, Fukushima (Japan); Sedukhin, I.

    1998-03-01

    The design of algorithmic array processors for solving linear systems of equations using fraction-free Gaussian elimination method is presented. The design is based on a formal approach which constructs a family of planar array processors systematically. These array processors are synthesized and analyzed. It is shown that some array processors are optimal in the framework of linear allocation of computations and in terms of number of processing elements and computing time. (author)

  15. Design and Implementation of an Asynchronous Pipelined FFT Processor

    OpenAIRE

    Claesson, Jonas

    2003-01-01

    FFT processors are today one of the most important blocks in communication equipment. They are used in everything from broadband to 3G and digital TV to Radio LANs. This master's thesis project will deal with pipelined hardware solutions for FFT processors with long FFT transforms, 1K to 8K points. These processors could be used for instance in OFDM communication systems. The final implementation of the FFT processor uses a GALS (Globally Asynchronous Locally Synchronous) architecture, that ...

  16. Cache Energy Optimization Techniques For Modern Processors

    Energy Technology Data Exchange (ETDEWEB)

    Mittal, Sparsh [ORNL

    2013-01-01

    Modern multicore processors are employing large last-level caches, for example Intel's E7-8800 processor uses 24MB L3 cache. Further, with each CMOS technology generation, leakage energy has been dramatically increasing and hence, leakage energy is expected to become a major source of energy dissipation, especially in last-level caches (LLCs). The conventional schemes of cache energy saving either aim at saving dynamic energy or are based on properties specific to first-level caches, and thus these schemes have limited utility for last-level caches. Further, several other techniques require offline profiling or per-application tuning and hence are not suitable for product systems. In this book, we present novel cache leakage energy saving schemes for single-core and multicore systems; desktop, QoS, real-time and server systems. Also, we present cache energy saving techniques for caches designed with both conventional SRAM devices and emerging non-volatile devices such as STT-RAM (spin-torque transfer RAM). We present software-controlled, hardware-assisted techniques which use dynamic cache reconfiguration to configure the cache to the most energy efficient configuration while keeping the performance loss bounded. To profile and test a large number of potential configurations, we utilize low-overhead, micro-architecture components, which can be easily integrated into modern processor chips. We adopt a system-wide approach to save energy to ensure that cache reconfiguration does not increase energy consumption of other components of the processor. We have compared our techniques with state-of-the-art techniques and have found that our techniques outperform them in terms of energy efficiency and other relevant metrics. The techniques presented in this book have important applications in improving energy-efficiency of higher-end embedded, desktop, QoS, real-time, server processors and multitasking systems. This book is intended to be a valuable guide for both

  17. A Medical Language Processor for Two Indo-European Languages

    OpenAIRE

    Nhan, Ngo Thanh; Sager, Naomi; Lyman, Margaret; Tick, Leo J.; Borst, François; Su, Yun

    1989-01-01

    The syntax and semantics of clinical narrative across Indo-European languages are quite similar, making it possible to envison a single medical language processor that can be adapted for different European languages. The Linguistic String Project of New York University is continuing the development of its Medical Language Processor in this direction. The paper describes how the processor operates on English and French.

  18. Anatomy of the focal-plane sensor-processor arrays

    OpenAIRE

    Zarándy, Ákos

    2011-01-01

    This introductory chapter describes the zoo of the basic focal-plane sensor-processor array architectures. The typical sensor-processor arrangements are shown, the operators are listed in separate groups, and the processor structures are analyzed. The chapter gives a compass to the reader to navigate among the dif-ferent chip implementations, designs, and applications when reading the book.

  19. 21 CFR 892.1900 - Automatic radiographic film processor.

    Science.gov (United States)

    2010-04-01

    ... 21 Food and Drugs 8 2010-04-01 2010-04-01 false Automatic radiographic film processor. 892.1900 Section 892.1900 Food and Drugs FOOD AND DRUG ADMINISTRATION, DEPARTMENT OF HEALTH AND HUMAN SERVICES... processor. (a) Identification. An automatic radiographic film processor is a device intended to be used...

  20. 21 CFR 864.3875 - Automated tissue processor.

    Science.gov (United States)

    2010-04-01

    ... 21 Food and Drugs 8 2010-04-01 2010-04-01 false Automated tissue processor. 864.3875 Section 864.3875 Food and Drugs FOOD AND DRUG ADMINISTRATION, DEPARTMENT OF HEALTH AND HUMAN SERVICES (CONTINUED... Automated tissue processor. (a) Identification. An automated tissue processor is an automated system used...

  1. LHCb Topological Trigger Reoptimization

    Science.gov (United States)

    Likhomanenko, Tatiana; Ilten, Philip; Khairullin, Egor; Rogozhnikov, Alex; Ustyuzhanin, Andrey; Williams, Michael

    2015-12-01

    The main b-physics trigger algorithm used by the LHCb experiment is the so- called topological trigger. The topological trigger selects vertices which are a) detached from the primary proton-proton collision and b) compatible with coming from the decay of a b-hadron. In the LHC Run 1, this trigger, which utilized a custom boosted decision tree algorithm, selected a nearly 100% pure sample of b-hadrons with a typical efficiency of 60-70%; its output was used in about 60% of LHCb papers. This talk presents studies carried out to optimize the topological trigger for LHC Run 2. In particular, we have carried out a detailed comparison of various machine learning classifier algorithms, e.g., AdaBoost, MatrixNet and neural networks. The topological trigger algorithm is designed to select all ’interesting” decays of b-hadrons, but cannot be trained on every such decay. Studies have therefore been performed to determine how to optimize the performance of the classification algorithm on decays not used in the training. Methods studied include cascading, ensembling and blending techniques. Furthermore, novel boosting techniques have been implemented that will help reduce systematic uncertainties in Run 2 measurements. We demonstrate that the reoptimized topological trigger is expected to significantly improve on the Run 1 performance for a wide range of b-hadron decays.

  2. The LHCb Trigger

    CERN Document Server

    van Herwijnen, Eric

    2010-01-01

    The Large Hadron Collider beauty experiment (LHCb) is a dedicated heavy flavour physics experiment at the LHC. The trigger system employs the finite lifetime and relative large mass of charm and beauty hadrons to distinguish heavy flavour and background from inelastic pp-scattering. The LHCb trigger is a two level system. The first level is implemented in hardware, it reduces the visible interaction rate to a maximum of 1MHz, at which the whole detector can be readout. The second trigger level is a C++ application running on an Event Filter Farm composed of several thousand CPU nodes. The full trigger is operational in the experiment. In this talk, an overview of the LHCb trigger system will be given. We put special emphasis on the experience obtained with the initial data taking at the LHC, and the commissioning and monitoring of the software trigger. The method to obtain the efficiency of the trigger from real data will be described, and first results will be presented.

  3. Iterative electro-optic matrix processor

    Science.gov (United States)

    Carlotto, M. J.

    An electro-optic vector matrix processor with electronic feedback is described. The iterative optical processor (IOP) is designed for the rapid solution of linear algebraic equations. The IOP and the iterative algorithm it realizes are analyzed and simulated. A version of the system was fabricated using advanced solid state light sources and detectors plus fiber optic technology, and its performance is evaluated. An extension of the system using wavelength multiplexing is developed and the basic system concepts demonstrated. Its use in the restoration of degraded images or signals (deconvolution) and the computation of matrix eigenvectors and eigenvalues and matrix inversion are demonstrated. The two major case studies pursued are: adaptive phased array radar processing and optimal control. In the former case, the system is used to compute the adaptive antenna weights for a radar system. In the latter case, the IOP solves the linear quadratic regular and algebraic Ricatti equations of modern control theory.

  4. A quantum information processor with trapped ions

    International Nuclear Information System (INIS)

    Quantum computers hold the promise to solve certain problems exponentially faster than their classical counterparts. Trapped atomic ions are among the physical systems in which building such a computing device seems viable. In this work we present a small-scale quantum information processor based on a string of 40Ca+ ions confined in a macroscopic linear Paul trap. We review our set of operations which includes non-coherent operations allowing us to realize arbitrary Markovian processes. In order to build a larger quantum information processor it is mandatory to reduce the error rate of the available operations which is only possible if the physics of the noise processes is well understood. We identify the dominant noise sources in our system and discuss their effects on different algorithms. Finally we demonstrate how our entire set of operations can be used to facilitate the implementation of algorithms by examples of the quantum Fourier transform and the quantum order finding algorithm. (paper)

  5. Metasurface Spatial Processor for Electromagnetic Remote Control

    CERN Document Server

    Achouri, Karim; Salem, Mohamed Ahmed; Caloz, Christophe

    2015-01-01

    We introduce the concept of metasurface spatial processor, whose transmission is remotely and coherently controlled by the superposition of an incident wave and a control wave through the metasurface. The conceptual operation of this device is analogous to both that of a transistor and a Mach-Zehnder interferometer, while offering much more diversity in terms of electromagnetic transformations. We demonstrate two metasurfaces, that perform the operation of electromagnetic switching and amplification.

  6. Metasurface Spatial Processor for Electromagnetic Remote Control

    OpenAIRE

    Achouri, Karim; Lavigne, Guillaume; Salem, Mohamed Ahmed; Caloz, Christophe

    2015-01-01

    We introduce the concept of metasurface spatial processor, whose transmission is remotely and coherently controlled by the superposition of an incident wave and a control wave through the metasurface. The conceptual operation of this device is analogous to both that of a transistor and a Mach-Zehnder interferometer, while offering much more diversity in terms of electromagnetic transformations. We demonstrate two metasurfaces, that perform the operation of electromagnetic switching and amplif...

  7. Metasurface Spatial Processor for Electromagnetic Remote Control

    Science.gov (United States)

    Achouri, Karim; Lavigne, Guillaume; Salem, Mohamed A.; Caloz, Christophe

    2016-05-01

    We introduce the concept of metasurface spatial processor, whose transmission is remotely and coherently controlled by the superposition of an incident wave and a control wave through the metasurface. The conceptual operation of this device is analogous to both that of a transistor and a Mach-Zehnder interferometer, while offering much more diversity in terms of electromagnetic transformations. We demonstrate two metasurfaces, that perform the operation of electromagnetic switching and amplification.

  8. High-pressure coal fuel processor development

    Energy Technology Data Exchange (ETDEWEB)

    Greenhalgh, M.L.

    1992-11-01

    The objective of Subtask 1.1 Engine Feasibility was to conduct research needed to establish the technical feasibility of ignition and stable combustion of directly injected, 3,000 psi, low-Btu gas with glow plug ignition assist at diesel engine compression ratios. This objective was accomplished by designing, fabricating, testing and analyzing the combustion performance of synthesized low-Btu coal gas in a single-cylinder test engine combustion rig located at the Caterpillar Technical Center engine lab in Mossville, Illinois. The objective of Subtask 1.2 Fuel Processor Feasibility was to conduct research needed to establish the technical feasibility of air-blown, fixed-bed, high-pressure coal fuel processing at up to 3,000 psi operating pressure, incorporating in-bed sulfur and particulate capture. This objective was accomplished by designing, fabricating, testing and analyzing the performance of bench-scale processors located at Coal Technology Corporation (subcontractor) facilities in Bristol, Virginia. These two subtasks were carried out at widely separated locations and will be discussed in separate sections of this report. They were, however, independent in that the composition of the synthetic coal gas used to fuel the combustion rig was adjusted to reflect the range of exit gas compositions being produced on the fuel processor rig. Two major conclusions resulted from this task. First, direct injected, ignition assisted Diesel cycle engine combustion systems can be suitably modified to efficiently utilize these low-Btu gas fuels. Second, high pressure gasification of selected run-of-the-mine coals in batch-loaded fuel processors is feasible. These two findings, taken together, significantly reduce the perceived technical risks associated with the further development of the proposed coal gas fueled Diesel cycle power plant concept.

  9. Keystone Business Models for Network Security Processors

    Directory of Open Access Journals (Sweden)

    Arthur Low

    2013-07-01

    Full Text Available Network security processors are critical components of high-performance systems built for cybersecurity. Development of a network security processor requires multi-domain experience in semiconductors and complex software security applications, and multiple iterations of both software and hardware implementations. Limited by the business models in use today, such an arduous task can be undertaken only by large incumbent companies and government organizations. Neither the “fabless semiconductor” models nor the silicon intellectual-property licensing (“IP-licensing” models allow small technology companies to successfully compete. This article describes an alternative approach that produces an ongoing stream of novel network security processors for niche markets through continuous innovation by both large and small companies. This approach, referred to here as the "business ecosystem model for network security processors", includes a flexible and reconfigurable technology platform, a “keystone” business model for the company that maintains the platform architecture, and an extended ecosystem of companies that both contribute and share in the value created by innovation. New opportunities for business model innovation by participating companies are made possible by the ecosystem model. This ecosystem model builds on: i the lessons learned from the experience of the first author as a senior integrated circuit architect for providers of public-key cryptography solutions and as the owner of a semiconductor startup, and ii the latest scholarly research on technology entrepreneurship, business models, platforms, and business ecosystems. This article will be of interest to all technology entrepreneurs, but it will be of particular interest to owners of small companies that provide security solutions and to specialized security professionals seeking to launch their own companies.

  10. EROS to universal tape conversion processor

    Science.gov (United States)

    Obrien, S. O. (Principal Investigator)

    1980-01-01

    The function of the EROS processor is to allow a user to select a specific area from a full frame LANDSAT image which is written on tape in the EROS format. The area of interest is read from the EROS formatted tape and converted to the JSC Universal format and written onto another tape. This tape can then be read by the IMDACS processing system and normal analysis can be performed.

  11. CoNNeCT Baseband Processor Module

    Science.gov (United States)

    Yamamoto, Clifford K; Jedrey, Thomas C.; Gutrich, Daniel G.; Goodpasture, Richard L.

    2011-01-01

    A document describes the CoNNeCT Baseband Processor Module (BPM) based on an updated processor, memory technology, and field-programmable gate arrays (FPGAs). The BPM was developed from a requirement to provide sufficient computing power and memory storage to conduct experiments for a Software Defined Radio (SDR) to be implemented. The flight SDR uses the AT697 SPARC processor with on-chip data and instruction cache. The non-volatile memory has been increased from a 20-Mbit EEPROM (electrically erasable programmable read only memory) to a 4-Gbit Flash, managed by the RTAX2000 Housekeeper, allowing more programs and FPGA bit-files to be stored. The volatile memory has been increased from a 20-Mbit SRAM (static random access memory) to a 1.25-Gbit SDRAM (synchronous dynamic random access memory), providing additional memory space for more complex operating systems and programs to be executed on the SPARC. All memory is EDAC (error detection and correction) protected, while the SPARC processor implements fault protection via TMR (triple modular redundancy) architecture. Further capability over prior BPM designs includes the addition of a second FPGA to implement features beyond the resources of a single FPGA. Both FPGAs are implemented with Xilinx Virtex-II and are interconnected by a 96-bit bus to facilitate data exchange. Dedicated 1.25- Gbit SDRAMs are wired to each Xilinx FPGA to accommodate high rate data buffering for SDR applications as well as independent SpaceWire interfaces. The RTAX2000 manages scrub and configuration of each Xilinx.

  12. Prototype COBRA near-real-time processor

    Science.gov (United States)

    Earp, Samuel L.; Marshall, J. W.; Anthony, E. R.

    1996-05-01

    The U.S. Marine Corps COBRA countermine surveillance program has developed, as a risk- reduction alternative, a near real-time processor for the output of the COBRA multispectral camera. This processor has been tested using approximately 13.5 hours of video data from the COBRA DT-0 developmental test, representing approximately 243,000 frames of multispectral data. The results have been very encouraging--the system is robust and the minefield detection performance has met the goals of the COBRA program. The MITRE COBRA prototype processor is built from commercial-off-the-shelf VME bus technology. Video capture is provided by a Transtech TDM 435 capture/display VME card. Control is performed on a GMSV64 Super Sparc card that resides in two VME slots. The compute engine consists of two Pentek 4270 Quad TMS320C40 digital signal processing boards. There are two additional 6U VME boards to provide fast SCSI IO. The system is capable of capturing, digitizing and processing the COBRA data stream at between one-eighth and one-half real-time, depending on processing options. The nominal compute power of the system is 2.2 GOPS, 450 MFLOPS. The system is easily upgradeable due to the open architecture--one proposed upgrade will be to increase the number of available TMS320C40 processors to sixteen, providing real-time performance without compromising the current investment in software and hardware. The software for the system is primarily written in C, with hand-optimized assembler code for portions of the compute kernel. The algorithm that is implemented is based on the MITRE minefield detection algorithm detailed at AeroSense '95. The system development required a registration algorithm--this was the only algorithm development that was performed, the rest of the algorithms coming from previous MITRE effort on the COBRA program. Lessons learned from the development and upgrade/test plans will be presented.

  13. A post-processor for Gurmukhi OCR

    Indian Academy of Sciences (India)

    G S Lehal; Chandan Singh

    2002-02-01

    A post-processing system for OCR of Gurmukhi script has been developed. Statistical information of Punjabi language syllable combinations, corpora look-up and certain heuristics based on Punjabi grammar rules have been combined to design the post-processor. An improvement of 3% in recognition rate, from 94.35% to 97.34%, has been reported on clean images using the post-processing techniques.

  14. Digital signal processor and energy control

    OpenAIRE

    Nishikori, Yutaka; Nakamura, Yoshimichi; Matsuo, Hirofumi

    2009-01-01

    Power supply was consisted of several analog parts and various circuits had been conventionally researched before. While, digitalization research of power supply is proceeding, but it has some problem of performance and cost to create digital control power supply. Now the revolution is occurred at Energy Control area after appearing DSP (Digital Signal Processor). Until now, a power supply was one of component of system. However, the digital control power supply using DSP can realize more int...

  15. Breadboard Signal Processor for Arraying DSN Antennas

    Science.gov (United States)

    Jongeling, Andre; Sigman, Elliott; Chandra, Kumar; Trinh, Joseph; Soriano, Melissa; Navarro, Robert; Rogstad, Stephen; Goodhart, Charles; Proctor, Robert; Jourdan, Michael; Rayhrer, Benno

    2008-01-01

    A recently developed breadboard version of an advanced signal processor for arraying many antennas in NASA s Deep Space Network (DSN) can accept inputs in a 500-MHz-wide frequency band from six antennas. The next breadboard version is expected to accept inputs from 16 antennas, and a following developed version is expected to be designed according to an architecture that will be scalable to accept inputs from as many as 400 antennas. These and similar signal processors could also be used for combining multiple wide-band signals in non-DSN applications, including very-long-baseline interferometry and telecommunications. This signal processor performs functions of a wide-band FX correlator and a beam-forming signal combiner. [The term "FX" signifies that the digital samples of two given signals are fast Fourier transformed (F), then the fast Fourier transforms of the two signals are multiplied (X) prior to accumulation.] In this processor, the signals from the various antennas are broken up into channels in the frequency domain (see figure). In each frequency channel, the data from each antenna are correlated against the data from each other antenna; this is done for all antenna baselines (that is, for all antenna pairs). The results of the correlations are used to obtain calibration data to align the antenna signals in both phase and delay. Data from the various antenna frequency channels are also combined and calibration corrections are applied. The frequency-domain data thus combined are then synthesized back to the time domain for passing on to a telemetry receiver

  16. Debugging in a multi-processor environment

    International Nuclear Information System (INIS)

    The Supervisory Control and Diagnostic System (SCDS) for the Mirror Fusion Test Facility (MFTF) consists of nine 32-bit minicomputers arranged in a tightly coupled distributed computer system utilizing a share memory as the data exchange medium. Debugging of more than one program in the multi-processor environment is a difficult process. This paper describes what new tools were developed and how the testing of software is performed in the SCDS for the MFTF project

  17. Multi-core processors - An overview

    OpenAIRE

    Venu, Balaji

    2011-01-01

    Microprocessors have revolutionized the world we live in and continuous efforts are being made to manufacture not only faster chips but also smarter ones. A number of techniques such as data level parallelism, instruction level parallelism and hyper threading (Intel's HT) already exists which have dramatically improved the performance of microprocessor cores. This paper briefs on evolution of multi-core processors followed by introducing the technology and its advantages in today's world. The...

  18. Quantum Algorithm Processors to Reveal Hamiltonian Cycles

    OpenAIRE

    Burger, John Robert

    2005-01-01

    Quantum computer versus quantum algorithm processor in CMOS are compared to find (in parallel) all Hamiltonian cycles in a graph with m edges and n vertices, each represented by k bits. A quantum computer uses quantum states analogous to CMOS registers. With efficient initialization, number of CMOS registers is proportional to (n-1)! Number of qubits in a quantum computer is approximately proportional to kn+2mn in the approach below. Using CMOS, the bits per register is about proportional to ...

  19. A CNN-Specific Integrated Processor

    OpenAIRE

    Suleyman Malki; Lambert Spaanenburg

    2009-01-01

    Integrated Processors (IP) are algorithm-specific cores that either by programming or by configuration can be re-used within many microelectronic systems. This paper looks at Cellular Neural Networks (CNN) to become realized as IP. First current digital implementations are reviewed, and the memoryprocessor bandwidth issues are analyzed. Then a generic view is taken on the structure of the network, and a new intra-communication protocol based on rotating wheels is proposed. It is shown that th...

  20. The Advanced On-board Processor (AOP)

    Science.gov (United States)

    Hartenstein, R. G.; Trevathan, C. E.; Stewart, W. N.

    1971-01-01

    The goal of the Advanced On-Board Processor (AOP) development program is to design, build, and flight qualify a highly reliable, moderately priced, digital computer for application on a variety of spacecraft. Included in this development program is the preparation of a complete support software package which consists of an assembler, simulator, loader, system diagnostic, operational executive, and many useful subroutines. The AOP hardware/software system is an extension of the On-Board Processor (OBP) which was developed for general purpose use on earth orbiting spacecraft with its initial application being on-board the fourth Orbiting Astronomical Observatory (OAO-C). Although the OBP possesses the significant features that are required for space application, however, when operating at 100% duty cycle the OBP is too power-consuming for use on many smaller spacecraft. Computer volume will be minimized by implementing the processor and input/output portions of the machine with large scale integrated circuits. Power consumption will be reduced through the use of plated wire and, in some cases, semiconductor memory elements.

  1. Techniques for optimizing inerting in electron processors

    International Nuclear Information System (INIS)

    The design of an ''inert gas'' distribution system in an electron processor must satisfy a number of requirements. The first of these is the elimination or control of beam produced ozone and NOx which can be transported from the process zone by the product into the work area. Since the tolerable levels for O3 in occupied areas around the processor are 3 in the beam heated process zone, or exhausting and dilution of the gas at the processor exit. The second requirement of the inerting system is to provide a suitable environment for completing efficient, free radical initiated addition polymerization. The competition between radical loss through de-excitation and that from O2 quenching must be understood. This group has used gas chromatographic analysis of electron cured coatings to study the trade-offs of delivered dose, dose rate and O2 concentrations in the process zone to determine the tolerable ranges of parameter excursions for production quality control purposes. These techniques are described for an ink coating system on paperboard, where a broad range of process parameters have been studied (D, D radical, O2). It is then shown how the technique is used to optimize the use of higher purity (10-100 ppm O2) nitrogen gas for inerting, in combination with lower purity (2-20,000 ppm O2) non-cryogenically produced gas, as from a membrane or pressure swing adsorption generators. (author)

  2. Supervision of the ATLAS High Level Trigger System

    CERN Document Server

    Wheeler, S; Baines, J T M; Bee, C P; Biglietti, M; Bogaerts, A; Boisvert, V; Bosman, M; Brandt, S; Caron, B; Casado, M P; Cataldi, G; Cavalli, D; Cervetto, M; Comune, G; Corso-Radu, A; De Seixas, J M; Di Mattia, A; Dos Anjos, A; Drohan, J; Díaz-Gómez, M; Ellis, Nick; Elsing, M; Epp, B; Etienne, F; Falciano, S; Farilla, A; Flammer, J; George, S; Ghete, V M; González, S; Grothe, M; Kaczmarska, A; Karr, K M; Khomich, A; Konstantinidis, N P; Krasny, W; Li, W; Lowe, A; Luminari, L; Ma, H; Meessen, C; Mello, A G; Merino, G; Morettini, P; Moyse, E; Nairz, A; Negri, A; Negri, F A; Nikitin, N V; Nisati, A; Padilla, C; Parodi, F; Pinfold, J L; Pinto, P; Polesello, G; Pérez-Réale, V; Qian, Z; Rajagopalan, S; Resconi, S; Rosati, S; Scannicchio, D A; Schiavi, C; Schörner-Sadenius, T; Segura, E; Shears, T G; Sivoklokov, S Yu; Smizanska, M; Soluk, R A; Stanescu, C; Tapprogge, Stefan; Touchard, F; Vercesi, V; Watson, A; Wengler, T; Werner, P; Wickens, F J; Wiedenmann, W; Wielers, M; Zobernig, G; Zobernig, H; CHEP 2003 Computing in High Energy Physics; Negri, France A.

    2003-01-01

    The ATLAS High Level Trigger (HLT) system provides software-based event selection after the initial LVL1 hardware trigger. It is composed of two stages, the LVL2 trigger and the Event Filter. The HLT is implemented as software tasks running on large processor farms. An essential part of the HLT is the supervision system, which is responsible for configuring, coordinating, controlling and monitoring the many hundreds of processes running in the HLT. A prototype implementation of the supervision system, using tools from the ATLAS Online Software system is presented. Results from scalability tests are also presented where the supervision system was shown to be capable of controlling over 1000 HLT processes running on 230 nodes.

  3. The ATLAS tau trigger

    CERN Document Server

    Casado, MP; Benslama, K; Bosman, M; Brenner, R; Czyczula, Z; Dam, M; Demers, S; Farrington, S; Igonkina, O; Kalinowski, A; Kanaya, N; Osuna, C; Pérez, E; Ptacek, E; Reinsch, A; Saavedra, A; Sfyrla, A; Shamin, M; Sopczak, A; Strom, D; Torrence, E; Tsuno, S; Vorwerk, V; Watson, A; Xella, S

    2008-01-01

    The implementation of a trigger for hadronically decaying tau leptons at the Large Hadronic Collider (LHC) is challenging due to the high background rate, on the other hand it increases tremendously the discovery potential of ATLAS in searches for Standard Model (SM) or Supersymmetric (SUSY) Higgs or other more exotic final states. In this paper we describe the ATLAS tau trigger system, focusing on the early data taking period, and present results from studies based on GEANT 4 simulated events, including trigger rates and the acceptance of tau leptons from SM processes. In order to cope with the rate and optimize the efficiency of important physics channels, the results of the current simulation studies indicate that ATLAS tau triggers should include either relatively high transverse momentum single tau signatures, or low transverse momentum tau signatures in combination with other signatures, such as missing transverse energy, leptons, or jets.

  4. The ATLAS tau trigger

    International Nuclear Information System (INIS)

    The implementation of a trigger for hadronically decaying tau leptons at the Large Hadronic Collider (LHC) is challenging due to the high background rate, on the other hand it increases tremendously the discovery potential of ATLAS in searches for Standard Model (SM) or Supersymmetric (SUSY) Higgs or other more exotic final states. In this paper we describe the ATLAS tau trigger system, focusing on the early data taking period, and present results from studies based on GEANT 4 simulated events, including trigger rates and the acceptance of tau leptons from SM processes. In order to cope with the rate and optimize the efficiency of important physics channels, the results of the current simulation studies indicate that ATLAS tau triggers should include either relatively high transverse momentum single tau signatures, or low transverse momentum tau signatures in combination with other signatures, such as missing transverse energy, leptons, or jets.

  5. Calorimetry triggering in ATLAS

    International Nuclear Information System (INIS)

    The ATLAS experiment is preparing for data taking at 14 TeV collision energy. A rich discovery physics program is being prepared in addition to the detailed study of Standard Model processes which will be produced in abundance. The ATLAS multi-level trigger system is designed to accept one event in 2 | 105 to enable the selection of rare and unusual physics events. The ATLAS calorimeter system is a precise instrument, which includes liquid Argon electro-magnetic and hadronic components as well as a scintillator-tile hadronic calorimeter. All these components are used in the various levels of the trigger system. A wide physics coverage is ensured by inclusively selecting events with candidate electrons, photons, taus, jets or those with large missing transverse energy. The commissioning of the trigger system is being performed with cosmic ray events and by replaying simulated Monte Carlo events through the trigger and data acquisition system.

  6. Calo trigger acquisition system

    CERN Multimedia

    Franchini, Matteo

    2016-01-01

    Calo trigger acquisition system - Evolution of the acquisition system from a multiple boards system (upper, orange cables) to a single board one (below, light blue cables) where all the channels are collected in a single board.

  7. Dealing with Asthma Triggers

    Science.gov (United States)

    ... reactions stuff in the air, like smoke and pollution colds or the flu weather conditions exercise continue ... given off by paint or gas, and air pollution. If you notice that an irritant triggers your ...

  8. VLSI Design of a 16-bit Pipelined RISC Processor

    Directory of Open Access Journals (Sweden)

    Tannu Chhabra

    2012-06-01

    Full Text Available In this paper we have described the design of a 16-bit pipelined RISC processor for applications in real-time embedded systems. The processor executes most of the instructions in single machine cycle making it ideal for use in high speed systems. The processor has been designed to be implemented on an FPGA using VHDL such that one can reconfigure it according to specific requirements of the target applications. The processor is powerful enough to be used as a stand-alone processing element and is generic enough to be used in multi-processor System on Chip.

  9. PERFORMANCE EVALUATION OF DIRECT PROCESSOR ACCESS FOR NON DEDICATED SERVER

    OpenAIRE

    P. S. Balamurugan; Dr.K.Thanushkodi

    2010-01-01

    The objective of the paper is to design a co processor for a desktop machine which enables the machine to act as non dedicated server, such that the co processor will act as a server processor and the multi-core processor to act as desktop processor. By implementing this methodology a client machine can be made to act as a non dedicated server and a client machine. These type of machine can be used in autonomy networks. This design will lead to design of a cost effective server and machine wh...

  10. Multi-Core Processor Memory Contention Benchmark Analysis Case Study

    Science.gov (United States)

    Simon, Tyler; McGalliard, James

    2009-01-01

    Multi-core processors dominate current mainframe, server, and high performance computing (HPC) systems. This paper provides synthetic kernel and natural benchmark results from an HPC system at the NASA Goddard Space Flight Center that illustrate the performance impacts of multi-core (dual- and quad-core) vs. single core processor systems. Analysis of processor design, application source code, and synthetic and natural test results all indicate that multi-core processors can suffer from significant memory subsystem contention compared to similar single-core processors.

  11. Modeling heterogeneous processor scheduling for real time systems

    Science.gov (United States)

    Leathrum, J. F.; Mielke, R. R.; Stoughton, J. W.

    1994-01-01

    A new model is presented to describe dataflow algorithms implemented in a multiprocessing system. Called the resource/data flow graph (RDFG), the model explicitly represents cyclo-static processor schedules as circuits of processor arcs which reflect the order that processors execute graph nodes. The model also allows the guarantee of meeting hard real-time deadlines. When unfolded, the model identifies statically the processor schedule. The model therefore is useful for determining the throughput and latency of systems with heterogeneous processors. The applicability of the model is demonstrated using a space surveillance algorithm.

  12. Considerations for control system software verification and validation specific to implementations using distributed processor architectures

    International Nuclear Information System (INIS)

    Until recently, digital control systems have been implemented on centralized processing systems to function in one of several ways: (1) as a single processor control system; (2) as a supervisor at the top of a hierarchical network of multiple processors; or (3) in a client-server mode. Each of these architectures uses a very different set of communication protocols. The latter two architectures also belong to the category of distributed control systems. Distributed control systems can have a central focus, as in the cases just cited, or be quite decentralized in a loosely coupled, shared responsibility arrangement. This last architecture is analogous to autonomous hosts on a local area network. Each of the architectures identified above will have a different set of architecture-associated issues to be addressed in the verification and validation activities during software development. This paper summarizes results of efforts to identify, describe, contrast, and compare these issues

  13. Dynamic Triggering Stress Modeling

    Science.gov (United States)

    Gonzalez-Huizar, H.; Velasco, A. A.

    2008-12-01

    It has been well established that static (permanent) stress changes can trigger nearby earthquakes, within a few fault lengths from the causative event, whereas triggering by dynamic (transient) stresses carried by seismic waves both nearby and at remote distances has not been as well documented nor understood. An analysis of the change in the local stress caused by the passing of surfaces waves is important for the understanding of this phenomenon. In this study, we modeled the change in the stress that the passing of Rayleigh and Loves waves causes on a fault plane of arbitrary orientation, and applied a Coulomb failure criteria to calculate the potential of these stress changes to trigger reverse, normal or strike-slip failure. We preliminarily test these model results with data from dynamically triggering earthquakes in the Australian Bowen Basin. In the Bowen region, the modeling predicts a maximum triggering potential for Rayleigh waves arriving perpendicularly to the strike of the reverse faults present in the region. The modeled potentials agree with our observations, and give us an understanding of the dynamic stress orientation needed to trigger different type of earthquakes.

  14. The VERITAS Trigger System

    CERN Document Server

    Weinstein, A

    2007-01-01

    The VERITAS gamma-ray observatory, situated in southern Arizona, is an array of four 12m diameter imaging Cherenkov telescopes, each with a 499-pixel photomultiplier-tube camera. The instrument is designed to detect astrophysical gamma rays at energies above 100 GeV. At the low end of the VERITAS energy range, fluctuations in the night sky background light and single muons from cosmic-ray showers constitute significant backgrounds. VERITAS employs a three-tier trigger system to reduce the rate of these background events: an initial trigger which acts at the single pixel level, a pattern trigger which acts on the relative timing and pixel level, a pattern trigger which acts on the relative timing and distribution of pixel-level triggers within a single telescope camera, and an array-level trigger which requires simultaneous observation of an air-shower event in multiple telescopes. This final coincidence requirement significantly reduces the rate of background events, particularly those due to single muons. In...

  15. LHCb Topological Trigger Reoptimization

    CERN Document Server

    Likhomanenko, Tatiana; Khairullin, Egor; Rogozhnikov, Alex; Ustyuzhanin, Andrey; Williams, Michael

    2015-01-01

    The main b-physics trigger algorithm used by the LHCb experiment is the so-called topological trigger. The topological trigger selects vertices which are a) detached from the primary proton-proton collision and b) compatible with coming from the decay of a b-hadron. In the LHC Run 1, this trigger, which utilized a custom boosted decision tree algorithm, selected a nearly 100% pure sample of b-hadrons with a typical efficiency of 60-70%; its output was used in about 60% of LHCb papers. This talk presents studies carried out to optimize the topological trigger for LHC Run 2. In particular, we have carried out a detailed comparison of various machine learning classifier algorithms, e.g., AdaBoost, MatrixNet and neural networks. The topological trigger algorithm is designed to select all "interesting" decays of b-hadrons, but cannot be trained on every such decay. Studies have therefore been performed to determine how to optimize the performance of the classification algorithm on decays not used in the training. ...

  16. The ATLAS tau trigger

    International Nuclear Information System (INIS)

    The ATLAS experiment at CERN's LHC has implemented a dedicated tau trigger system to select hadronically decaying tau leptons from the enormous background of QCD jets. This promises a significant increase in the discovery potential to the Higgs boson and in searches for physics beyond the Standard Model. The three level trigger system has been optimized for efficiency and good background rejection. The first level uses information from the calorimeters only, while the two higher levels include also information from the tracking detectors. Shower shape variables and the track multiplicity are important variables to distinguish taus from QCD jets. At the initial luminosity of 1031 cm-2s-1, single tau triggers with a transverse energy threshold of 50 GeV or higher can be run stand-alone. Below this level, the tau signatures will be combined with other event signatures. During the collection of a large sample of cosmic ray events in Autumn 2008, the tau trigger was operated as an integrated part of the ATLAS trigger system. This allowed the commissioning of technical aspects of the tau trigger.

  17. The LHCb Trigger System

    CERN Document Server

    Rodrigues, E

    2006-01-01

    The LHCb detector has been conceived to study with high precision CP violation and rare decays of b-flavoured hadrons produced at the LHC. The LHCb trigger is of crucial importance in selecting among the bulk of collisions those that are of interest for b-physics studies. The trigger is based on a two-level system. The first level, Level-0, is implemented in hardware and uses information from the calorimeter, muon and pile-up systems to select events containing particles with relatively large transverse momentum, typically above 1-2 GeV. The Level-0 trigger accepts events at a rate of 1 MHz. All the detector information is then read out and fed into the High Level Trigger. This software trigger runs in the event filter farm composed of about 1800 CPU nodes. Events are selected at a rate of 2kHz and sent for mass storage and subsequent offline reconstruction and analysis. The current status and expected performance of the trigger system are described.

  18. Topological Trigger Developments

    CERN Multimedia

    Likhomanenko, Tatiana

    2015-01-01

    The main b-physics trigger algorithm used by the LHCb experiment is the so-called topological trigger. The topological trigger selects vertices which are a) detached from the primary proton-proton collision and b) compatible with coming from the decay of a b-hadron. In the LHC Run 1, this trigger utilized a custom boosted decision tree algorithm, selected an almost 100% pure sample of b-hadrons with a typical efficiency of 60-70%, and its output was used in about 60% of LHCb papers. This talk presents studies carried out to optimize the topological trigger for LHC Run 2. In particular, we have carried out a detailed comparison of various machine learning classifier algorithms, e.g., AdaBoost, MatrixNet and uBoost. The topological trigger algorithm is designed to select all "interesting" decays of b-hadrons, but cannot be trained on every such decay. Studies have therefore been performed to determine how to optimize the performance of the classification algorithm on decays not used in the training. These inclu...

  19. Network to transmit prioritized subtask pockets to dedicated processors

    Energy Technology Data Exchange (ETDEWEB)

    Neches, P.M.

    1989-03-21

    A multiprocessor system distributing a workload among individual processors and operating with low usage of executive software and inter-processor communication to provide an overall workload processing function divisible into parallel processing subtasks is described, comprising: at least one processor system providing tasks for processing in the form of task messages; means coupled to receive the task messages from the processor system and including means to transform the task messages into subtask request packets including information as to one or more appropriate recipients; processor modules, each having assigned responsibilities with respect to the workload and each including means to determine whether the subtask is appropriate therefor, means for executing an appropriate subtask and means for providing a responsive task result packet after executing the subtask, the task result packet competing for priority with task result packets from at least one other processor module and with the subtask request packets from the interface processor means; and means coupling the interface processor means to the processor modules and the processor modules to each other and including means for concurrently receiving the packets and for determining priority between contending packets and distributing each packet having priority concurrently to all processor modules.

  20. Testing and operating a multiprocessor chip with processor redundancy

    Science.gov (United States)

    Bellofatto, Ralph E; Douskey, Steven M; Haring, Rudolf A; McManus, Moyra K; Ohmacht, Martin; Schmunkamp, Dietmar; Sugavanam, Krishnan; Weatherford, Bryan J

    2014-10-21

    A system and method for improving the yield rate of a multiprocessor semiconductor chip that includes primary processor cores and one or more redundant processor cores. A first tester conducts a first test on one or more processor cores, and encodes results of the first test in an on-chip non-volatile memory. A second tester conducts a second test on the processor cores, and encodes results of the second test in an external non-volatile storage device. An override bit of a multiplexer is set if a processor core fails the second test. In response to the override bit, the multiplexer selects a physical-to-logical mapping of processor IDs according to one of: the encoded results in the memory device or the encoded results in the external storage device. On-chip logic configures the processor cores according to the selected physical-to-logical mapping.

  1. Fault-tolerant computer architecture based on INMOS transputer processor

    Science.gov (United States)

    Ortiz, Jorge L.

    1987-01-01

    Redundant processing was used for several years in mission flight systems. In these systems, more than one processor performs the same task at the same time but only one processor is actually in real use. A fault-tolerance computer architecture based on the features provided by INMOS Transputers is presented. The Transputer architecture provides several communication links that allow data and command communication with other Transputers without the use of a bus. Additionally the Transputer allows the use of parallel processing to increase the system speed considerably. The processor architecture consists of three processors working in parallel keeping all the processors at the same operational level but only one processor is in real control of the process. The design allows each Transputer to perform a test to the other two Transputers and report the operating condition of the neighboring processors. A graphic display was developed to facilitate the identification of any problem by the user.

  2. Architecture of a Level 1 Track Trigger for the CMS Experiment

    CERN Document Server

    Heintz, Ulrich

    2010-01-01

    The luminosity goal for the Super-LHC is 1035/cm2/s. At this luminosity the number of proton-proton interactions in each beam crossing will be in the hundreds. This will stress many components of the CMS detector. One system that has to be upgraded is the trigger system. To keep the rate at which the level 1 trigger fires manageable, information from the tracker has to be integrated into the level 1 trigger. Current design proposals foresee tracking detectors that perform on-detector filtering to reject hits from low-momentum particles. In order to build a trigger system, the filtered hit data from different layers and sectors of the tracker will have to be transmitted off the detector and brought together in a logic processor that generates trigger tracks within the time window allowed by the level 1 trigger latency. I will describe a possible architecture for the off-detector logic that accomplishes this goal.

  3. Design of Variable Width Barrel Shifter for High Speed Processor Architecture

    OpenAIRE

    Rajeev Kumar; Dr.Anil Vohra

    2012-01-01

    Microprocessor is the brain of the computer. It works as the Central Processing Unit of the computer. It contains Arithmetic Logical Unit (ALU) that performs the arithmetic operations such as Addition, Subtraction, Multiplication and Division. It also performs the Logical operations such as AND, NAND, OR, NOR, EXOR, EXNOR and NOT. It also contains register file to store the operand in load/store instructions in RISC Processor Architecture. Control Unit genetares the control signals that synch...

  4. The ALICE electromagnetic calorimeter high level triggers

    International Nuclear Information System (INIS)

    The ALICE (A Large Ion Collider Experiment) detector yields a huge sample of data from different sub-detectors. On-line data processing is applied to select and reduce the volume of the stored data. ALICE applies a multi-level hardware trigger scheme where fast detectors are used to feed a three-level (L0, L1, and L2) deep chain. The High-Level Trigger (HLT) is a fourth filtering stage sitting logically between the L2 trigger and the data acquisition event building. The EMCal detector comprises a large area electromagnetic calorimeter that extends the momentum measurement of photons and neutral mesons up to pT = 250 GeV/c, which improves the ALICE capability to perform jet reconstruction with measurement of the neutral energy component of jets. An online reconstruction and trigger chain has been developed within the HLT framework to sharpen the EMCal hardware triggers, by combining the central barrel tracking information with the shower reconstruction (clusters) in the calorimeter. In the present report the status and the functionality of the software components developed for the EMCal HLT online reconstruction and trigger chain will be discussed, as well as preliminary results from their commissioning performed during the 2011 LHC running period.

  5. Description and Optimisation of the ALICE dimuon trigger

    CERN Document Server

    Roig, O

    1998-01-01

    The main considerations about the ALICE dimuon trigger can be found in the Addendum to the ALICE Technical Proposal (T.P. in this note), concerning the forward muon spectrometer. The main task of the trigger is to select the dimuon signals, mainly from J/Psi and Upsilon resonances, amongst the huge background of muons from pions, kaons, charm decays and soft background in order to keep the acquisition rates at a satisfactory level. This is achieved with a cut on the muon transverse momentum performed by the trigger electronics and processors. A dimuon mass cut can also be done (not treated in this note). This note presents a detailed simulation which goal is to optimize the dimuon trigger. It includes the description of the set-up geometry and segmentation as well as the trigger electronics functions. Many improvements are suggested by the results of this simulation, as compared to the T.P. An update of the trigger rates and efficiency is given. Even though we describe the main elements of the dimuon trigge...

  6. The CMS trigger system

    CERN Document Server

    Khachatryan, Vardan; CMS Collaboration; Tumasyan, Armen; Adam, Wolfgang; Aşılar, Ece; Bergauer, Thomas; Brandstetter, Johannes; Brondolin, Erica; Dragicevic, Marko; Erö, Janos; Flechl, Martin; Friedl, Markus; Fruehwirth, Rudolf; Ghete, Vasile Mihai; Hartl, Christian; Hörmann, Natascha; Hrubec, Josef; Jeitler, Manfred; Knünz, Valentin; König, Axel; Krammer, Manfred; Krätschmer, Ilse; Liko, Dietrich; Matsushita, Takashi; Mikulec, Ivan; Rabady, Dinyar; Rahbaran, Babak; Rohringer, Herbert; Schieck, Jochen; Schöfbeck, Robert; Strauss, Josef; Treberer-Treberspurg, Wolfgang; Waltenberger, Wolfgang; Wulz, Claudia-Elisabeth; Mossolov, Vladimir; Shumeiko, Nikolai; Suarez Gonzalez, Juan; Alderweireldt, Sara; Cornelis, Tom; De Wolf, Eddi A; Janssen, Xavier; Knutsson, Albert; Lauwers, Jasper; Luyckx, Sten; Van De Klundert, Merijn; Van Haevermaet, Hans; Van Mechelen, Pierre; Van Remortel, Nick; Van Spilbeeck, Alex; Abu Zeid, Shimaa; Blekman, Freya; D'Hondt, Jorgen; Daci, Nadir; De Bruyn, Isabelle; Deroover, Kevin; Heracleous, Natalie; Keaveney, James; Lowette, Steven; Moreels, Lieselotte; Olbrechts, Annik; Python, Quentin; Strom, Derek; Tavernier, Stefaan; Van Doninck, Walter; Van Mulders, Petra; Van Onsem, Gerrit Patrick; Van Parijs, Isis; Barria, Patrizia; Brun, Hugues; Caillol, Cécile; Clerbaux, Barbara; De Lentdecker, Gilles; Fasanella, Giuseppe; Favart, Laurent; Grebenyuk, Anastasia; Karapostoli, Georgia; Lenzi, Thomas; Léonard, Alexandre; Maerschalk, Thierry; Marinov, Andrey; Perniè, Luca; Randle-conde, Aidan; Reis, Thomas; Seva, Tomislav; Vander Velde, Catherine; Vanlaer, Pascal; Yonamine, Ryo; Zenoni, Florian; Zhang, Fengwangdong; Beernaert, Kelly; Benucci, Leonardo; Cimmino, Anna; Crucy, Shannon; Dobur, Didar; Fagot, Alexis; Garcia, Guillaume; Gul, Muhammad; Mccartin, Joseph; Ocampo Rios, Alberto Andres; Poyraz, Deniz; Ryckbosch, Dirk; Salva Diblen, Sinem; Sigamani, Michael; Strobbe, Nadja; Tytgat, Michael; Van Driessche, Ward; Yazgan, Efe; Zaganidis, Nicolas; Basegmez, Suzan; Beluffi, Camille; Bondu, Olivier; Brochet, Sébastien; Bruno, Giacomo; Caudron, Adrien; Ceard, Ludivine; Da Silveira, Gustavo Gil; Delaere, Christophe; Favart, Denis; Forthomme, Laurent; Giammanco, Andrea; Hollar, Jonathan; Jafari, Abideh; Jez, Pavel; Komm, Matthias; Lemaitre, Vincent; Mertens, Alexandre; Musich, Marco; Nuttens, Claude; Perrini, Lucia; Pin, Arnaud; Piotrzkowski, Krzysztof; Popov, Andrey; Quertenmont, Loic; Selvaggi, Michele; Vidal Marono, Miguel; Beliy, Nikita; Hammad, Gregory Habib; Aldá Júnior, Walter Luiz; Alves, Fábio Lúcio; Alves, Gilvan; Brito, Lucas; Correa Martins Junior, Marcos; Hamer, Matthias; Hensel, Carsten; Mora Herrera, Clemencia; Moraes, Arthur; Pol, Maria Elena; Rebello Teles, Patricia; Belchior Batista Das Chagas, Ewerton; Carvalho, Wagner; Chinellato, Jose; Custódio, Analu; Da Costa, Eliza Melo; De Jesus Damiao, Dilson; De Oliveira Martins, Carley; Fonseca De Souza, Sandro; Huertas Guativa, Lina Milena; Malbouisson, Helena; Matos Figueiredo, Diego; Mundim, Luiz; Nogima, Helio; Prado Da Silva, Wanda Lucia; Santoro, Alberto; Sznajder, Andre; Tonelli Manganote, Edmilson José; Vilela Pereira, Antonio; Ahuja, Sudha; Bernardes, Cesar Augusto; De Souza Santos, Angelo; Dogra, Sunil; Tomei, Thiago; De Moraes Gregores, Eduardo; Mercadante, Pedro G; Moon, Chang-Seong; Novaes, Sergio F; Padula, Sandra; Romero Abad, David; Ruiz Vargas, José Cupertino; Aleksandrov, Aleksandar; Hadjiiska, Roumyana; Iaydjiev, Plamen; Rodozov, Mircho; Stoykova, Stefka; Sultanov, Georgi; Vutova, Mariana; Dimitrov, Anton; Glushkov, Ivan; Litov, Leander; Pavlov, Borislav; Petkov, Peicho; Ahmad, Muhammad; Bian, Jian-Guo; Chen, Guo-Ming; Chen, He-Sheng; Chen, Mingshui; Cheng, Tongguang; Du, Ran; Jiang, Chun-Hua; Plestina, Roko; Romeo, Francesco; Shaheen, Sarmad Masood; Spiezia, Aniello; Tao, Junquan; Wang, Chunjie; Wang, Zheng; Zhang, Huaqiao; Asawatangtrakuldee, Chayanit; Ban, Yong; Li, Qiang; Liu, Shuai; Mao, Yajun; Qian, Si-Jin; Wang, Dayong; Xu, Zijun; Avila, Carlos; Cabrera, Andrés; Chaparro Sierra, Luisa Fernanda; Florez, Carlos; Gomez, Juan Pablo; Gomez Moreno, Bernardo; Sanabria, Juan Carlos; Godinovic, Nikola; Lelas, Damir; Puljak, Ivica; Ribeiro Cipriano, Pedro M; Antunovic, Zeljko; Kovac, Marko; Brigljevic, Vuko; Kadija, Kreso; Luetic, Jelena; Micanovic, Sasa; Sudic, Lucija; Attikis, Alexandros; Mavromanolakis, Georgios; Mousa, Jehad; Nicolaou, Charalambos; Ptochos, Fotios; Razis, Panos A; Rykaczewski, Hans; Bodlak, Martin; Finger, Miroslav; Finger Jr, Michael; Assran, Yasser; El Sawy, Mai; Elgammal, Sherif; Ellithi Kamel, Ali; Mahmoud, Mohammed; Calpas, Betty; Kadastik, Mario; Murumaa, Marion; Raidal, Martti; Tiko, Andres; Veelken, Christian; Eerola, Paula; Pekkanen, Juska; Voutilainen, Mikko; Härkönen, Jaakko; Karimäki, Veikko; Kinnunen, Ritva; Lampén, Tapio; Lassila-Perini, Kati; Lehti, Sami; Lindén, Tomas; Luukka, Panja-Riina; Mäenpää, Teppo; Peltola, Timo; Tuominen, Eija; Tuominiemi, Jorma; Tuovinen, Esa; Wendland, Lauri; Talvitie, Joonas; Tuuva, Tuure; Besancon, Marc; Couderc, Fabrice; Dejardin, Marc; Denegri, Daniel; Fabbro, Bernard; Faure, Jean-Louis; Favaro, Carlotta; Ferri, Federico; Ganjour, Serguei; Givernaud, Alain; Gras, Philippe; Hamel de Monchenault, Gautier; Jarry, Patrick; Locci, Elizabeth; Machet, Martina; Malcles, Julie; Rander, John; Rosowsky, André; Titov, Maksym; Zghiche, Amina; Antropov, Iurii; Baffioni, Stephanie; Beaudette, Florian; Busson, Philippe; Cadamuro, Luca; Chapon, Emilien; Charlot, Claude; Dahms, Torsten; Davignon, Olivier; Filipovic, Nicolas; Florent, Alice; Granier de Cassagnac, Raphael; Lisniak, Stanislav; Mastrolorenzo, Luca; Miné, Philippe; Naranjo, Ivo Nicolas; Nguyen, Matthew; Ochando, Christophe; Ortona, Giacomo; Paganini, Pascal; Pigard, Philipp; Regnard, Simon; Salerno, Roberto; Sauvan, Jean-Baptiste; Sirois, Yves; Strebler, Thomas; Yilmaz, Yetkin; Zabi, Alexandre; Agram, Jean-Laurent; Andrea, Jeremy; Aubin, Alexandre; Bloch, Daniel; Brom, Jean-Marie; Buttignol, Michael; Chabert, Eric Christian; Chanon, Nicolas; Collard, Caroline; Conte, Eric; Coubez, Xavier; Fontaine, Jean-Charles; Gelé, Denis; Goerlach, Ulrich; Goetzmann, Christophe; Le Bihan, Anne-Catherine; Merlin, Jeremie Alexandre; Skovpen, Kirill; Van Hove, Pierre; Gadrat, Sébastien; Beauceron, Stephanie; Bernet, Colin; Boudoul, Gaelle; Bouvier, Elvire; Carrillo Montoya, Camilo Andres; Chierici, Roberto; Contardo, Didier; Courbon, Benoit; Depasse, Pierre; El Mamouni, Houmani; Fan, Jiawei; Fay, Jean; Gascon, Susan; Gouzevitch, Maxime; Ille, Bernard; Lagarde, Francois; Laktineh, Imad Baptiste; Lethuillier, Morgan; Mirabito, Laurent; Pequegnot, Anne-Laure; Perries, Stephane; Ruiz Alvarez, José David; Sabes, David; Sgandurra, Louis; Sordini, Viola; Vander Donckt, Muriel; Verdier, Patrice; Viret, Sébastien; Toriashvili, Tengizi; Tsamalaidze, Zviad; Autermann, Christian; Beranek, Sarah; Edelhoff, Matthias; Feld, Lutz; Heister, Arno; Kiesel, Maximilian Knut; Klein, Katja; Lipinski, Martin; Ostapchuk, Andrey; Preuten, Marius; Raupach, Frank; Schael, Stefan; Schulte, Jan-Frederik; Verlage, Tobias; Weber, Hendrik; Wittmer, Bruno; Zhukov, Valery; Ata, Metin; Brodski, Michael; Dietz-Laursonn, Erik; Duchardt, Deborah; Endres, Matthias; Erdmann, Martin; Erdweg, Sören; Esch, Thomas; Fischer, Robert; Güth, Andreas; Hebbeker, Thomas; Heidemann, Carsten; Hoepfner, Kerstin; Klingebiel, Dennis; Knutzen, Simon; Kreuzer, Peter; Merschmeyer, Markus; Meyer, Arnd; Millet, Philipp; Olschewski, Mark; Padeken, Klaas; Papacz, Paul; Pook, Tobias; Radziej, Markus; Reithler, Hans; Rieger, Marcel; Scheuch, Florian; Sonnenschein, Lars; Teyssier, Daniel; Thüer, Sebastian; Cherepanov, Vladimir; Erdogan, Yusuf; Flügge, Günter; Geenen, Heiko; Geisler, Matthias; Hoehle, Felix; Kargoll, Bastian; Kress, Thomas; Kuessel, Yvonne; Künsken, Andreas; Lingemann, Joschka; Nehrkorn, Alexander; Nowack, Andreas; Nugent, Ian Michael; Pistone, Claudia; Pooth, Oliver; Stahl, Achim; Aldaya Martin, Maria; Asin, Ivan; Bartosik, Nazar; Behnke, Olaf; Behrens, Ulf; Bell, Alan James; Borras, Kerstin; Burgmeier, Armin; Campbell, Alan; Choudhury, Somnath; Costanza, Francesco; Diez Pardos, Carmen; Dolinska, Ganna; Dooling, Samantha; Dorland, Tyler; Eckerlin, Guenter; Eckstein, Doris; Eichhorn, Thomas; Flucke, Gero; Gallo, Elisabetta; Garay Garcia, Jasone; Geiser, Achim; Gizhko, Andrii; Gunnellini, Paolo; Hauk, Johannes; Hempel, Maria; Jung, Hannes; Kalogeropoulos, Alexis; Karacheban, Olena; Kasemann, Matthias; Katsas, Panagiotis; Kieseler, Jan; Kleinwort, Claus; Korol, Ievgen; Lange, Wolfgang; Leonard, Jessica; Lipka, Katerina; Lobanov, Artur; Lohmann, Wolfgang; Mankel, Rainer; Marfin, Ihar; Melzer-Pellmann, Isabell-Alissandra; Meyer, Andreas Bernhard; Mittag, Gregor; Mnich, Joachim; Mussgiller, Andreas; Naumann-Emme, Sebastian; Nayak, Aruna; Ntomari, Eleni; Perrey, Hanno; Pitzl, Daniel; Placakyte, Ringaile; Raspereza, Alexei; Roland, Benoit; Sahin, Mehmet Özgür; Saxena, Pooja; Schoerner-Sadenius, Thomas; Schröder, Matthias; Seitz, Claudia; Spannagel, Simon; Trippkewitz, Karim Damun; Walsh, Roberval; Wissing, Christoph; Blobel, Volker; Centis Vignali, Matteo; Draeger, Arne-Rasmus; Erfle, Joachim; Garutti, Erika; Goebel, Kristin; Gonzalez, Daniel; Görner, Martin; Haller, Johannes; Hoffmann, Malte; Höing, Rebekka Sophie; Junkes, Alexandra; Klanner, Robert; Kogler, Roman; Kovalchuk, Nataliia; Lapsien, Tobias; Lenz, Teresa; Marchesini, Ivan; Marconi, Daniele; Meyer, Mareike; Nowatschin, Dominik; Ott, Jochen; Pantaleo, Felice; Peiffer, Thomas; Perieanu, Adrian; Pietsch, Niklas; Poehlsen, Jennifer; Rathjens, Denis; Sander, Christian; Scharf, Christian; Schettler, Hannes; Schleper, Peter; Schlieckau, Eike; Schmidt, Alexander; Schwandt, Joern; Sola, Valentina; Stadie, Hartmut; Steinbrück, Georg; Tholen, Heiner; Troendle, Daniel; Usai, Emanuele; Vanelderen, Lukas; Vanhoefer, Annika; Vormwald, Benedikt; Akbiyik, Melike; Barth, Christian; Baus, Colin; Berger, Joram; Böser, Christian; Butz, Erik; Chwalek, Thorsten; Colombo, Fabio; De Boer, Wim; Descroix, Alexis; Dierlamm, Alexander; Fink, Simon; Frensch, Felix; Friese, Raphael; Giffels, Manuel; Gilbert, Andrew; Haitz, Dominik; Hartmann, Frank; Heindl, Stefan Michael; Husemann, Ulrich; Katkov, Igor; Kornmayer, Andreas; Lobelle Pardo, Patricia; Maier, Benedikt; Mildner, Hannes; Mozer, Matthias Ulrich; Müller, Thomas; Müller, Thomas; Plagge, Michael; Quast, Gunter; Rabbertz, Klaus; Röcker, Steffen; Roscher, Frank; Sieber, Georg; Simonis, Hans-Jürgen; Stober, Fred-Markus Helmut; Ulrich, Ralf; Wagner-Kuhr, Jeannine; Wayand, Stefan; Weber, Marc; Weiler, Thomas; Wöhrmann, Clemens; Wolf, Roger; Anagnostou, Georgios; Daskalakis, Georgios; Geralis, Theodoros; Giakoumopoulou, Viktoria Athina; Kyriakis, Aristotelis; Loukas, Demetrios; Psallidas, Andreas; Topsis-Giotis, Iasonas; Agapitos, Antonis; Kesisoglou, Stilianos; Panagiotou, Apostolos; Saoulidou, Niki; Tziaferi, Eirini; Evangelou, Ioannis; Flouris, Giannis; Foudas, Costas; Kokkas, Panagiotis; Loukas, Nikitas; Manthos, Nikolaos; Papadopoulos, Ioannis; Paradas, Evangelos; Strologas, John; Bencze, Gyorgy; Hajdu, Csaba; Hazi, Andras; Hidas, Pàl; Horvath, Dezso; Sikler, Ferenc; Veszpremi, Viktor; Vesztergombi, Gyorgy; Zsigmond, Anna Julia; Beni, Noemi; Czellar, Sandor; Karancsi, János; Molnar, Jozsef; Szillasi, Zoltan; Bartók, Márton; Makovec, Alajos; Raics, Peter; Trocsanyi, Zoltan Laszlo; Ujvari, Balazs; Mal, Prolay; Mandal, Koushik; Sahoo, Deepak Kumar; Sahoo, Niladribihari; Swain, Sanjay Kumar; Bansal, Sunil; Beri, Suman Bala; Bhatnagar, Vipin; Chawla, Ridhi; Gupta, Ruchi; Bhawandeep, Bhawandeep; Kalsi, Amandeep Kaur; Kaur, Anterpreet; Kaur, Manjit; Kumar, Ramandeep; Mehta, Ankita; Mittal, Monika; Singh, Jasbir; Walia, Genius; Kumar, Ashok; Bhardwaj, Ashutosh; Choudhary, Brajesh C; Garg, Rocky Bala; Kumar, Ajay; Malhotra, Shivali; Naimuddin, Md; Nishu, Nishu; Ranjan, Kirti; Sharma, Ramkrishna; Sharma, Varun; Bhattacharya, Satyaki; Chatterjee, Kalyanmoy; Dey, Sourav; Dutta, Suchandra; Jain, Sandhya; Majumdar, Nayana; Modak, Atanu; Mondal, Kuntal; Mukherjee, Swagata; Mukhopadhyay, Supratik; Roy, Ashim; Roy, Debarati; Roy Chowdhury, Suvankar; Sarkar, Subir; Sharan, Manoj; Abdulsalam, Abdulla; Chudasama, Ruchi; Dutta, Dipanwita; Jha, Vishwajeet; Kumar, Vineet; Mohanty, Ajit Kumar; Pant, Lalit Mohan; Shukla, Prashant; Topkar, Anita; Aziz, Tariq; Banerjee, Sudeshna; Bhowmik, Sandeep; Chatterjee, Rajdeep Mohan; Dewanjee, Ram Krishna; Dugad, Shashikant; Ganguly, Sanmay; Ghosh, Saranya; Guchait, Monoranjan; Gurtu, Atul; Kole, Gouranga; Kumar, Sanjeev; Mahakud, Bibhuprasad; Maity, Manas; Majumder, Gobinda; Mazumdar, Kajari; Mitra, Soureek; Mohanty, Gagan Bihari; Parida, Bibhuti; Sarkar, Tanmay; Sur, Nairit; Sutar, Bajrang; Wickramage, Nadeesha; Chauhan, Shubhanshu; Dube, Sourabh; Kothekar, Kunal; Sharma, Seema; Bakhshiansohi, Hamed; Behnamian, Hadi; Etesami, Seyed Mohsen; Fahim, Ali; Goldouzian, Reza; Khakzad, Mohsen; Mohammadi Najafabadi, Mojtaba; Naseri, Mohsen; Paktinat Mehdiabadi, Saeid; Rezaei Hosseinabadi, Ferdos; Safarzadeh, Batool; Zeinali, Maryam; Felcini, Marta; Grunewald, Martin; Abbrescia, Marcello; Calabria, Cesare; Caputo, Claudio; Colaleo, Anna; Creanza, Donato; Cristella, Leonardo; De Filippis, Nicola; De Palma, Mauro; Fiore, Luigi; Iaselli, Giuseppe; Maggi, Giorgio; Maggi, Marcello; Miniello, Giorgia; My, Salvatore; Nuzzo, Salvatore; Pompili, Alexis; Pugliese, Gabriella; Radogna, Raffaella; Ranieri, Antonio; Selvaggi, Giovanna; Silvestris, Lucia; Venditti, Rosamaria; Verwilligen, Piet; Abbiendi, Giovanni; Battilana, Carlo; Benvenuti, Alberto; Bonacorsi, Daniele; Braibant-Giacomelli, Sylvie; Brigliadori, Luca; Campanini, Renato; Capiluppi, Paolo; Castro, Andrea; Cavallo, Francesca Romana; Chhibra, Simranjit Singh; Codispoti, Giuseppe; Cuffiani, Marco; Dallavalle, Gaetano-Marco; Fabbri, Fabrizio; Fanfani, Alessandra; Fasanella, Daniele; Giacomelli, Paolo; Grandi, Claudio; Guiducci, Luigi; Marcellini, Stefano; Masetti, Gianni; Montanari, Alessandro; Navarria, Francesco; Perrotta, Andrea; Rossi, Antonio; Rovelli, Tiziano; Siroli, Gian Piero; Tosi, Nicolò; Travaglini, Riccardo; Cappello, Gigi; Chiorboli, Massimiliano; Costa, Salvatore; Di Mattia, Alessandro; Giordano, Ferdinando; Potenza, Renato; Tricomi, Alessia; Tuve, Cristina; Barbagli, Giuseppe; Ciulli, Vitaliano; Civinini, Carlo; D'Alessandro, Raffaello; Focardi, Ettore; Gonzi, Sandro; Gori, Valentina; Lenzi, Piergiulio; Meschini, Marco; Paoletti, Simone; Sguazzoni, Giacomo; Tropiano, Antonio; Viliani, Lorenzo; Benussi, Luigi; Bianco, Stefano; Fabbri, Franco; Piccolo, Davide; Primavera, Federica; Calvelli, Valerio; Ferro, Fabrizio; Lo Vetere, Maurizio; Monge, Maria Roberta; Robutti, Enrico; Tosi, Silvano; Brianza, Luca; Dinardo, Mauro Emanuele; Fiorendi, Sara; Gennai, Simone; Gerosa, Raffaele; Ghezzi, Alessio; Govoni, Pietro; Malvezzi, Sandra; Manzoni, Riccardo Andrea; Marzocchi, Badder; Menasce, Dario; Moroni, Luigi; Paganoni, Marco; Pedrini, Daniele; Ragazzi, Stefano; Redaelli, Nicola; Tabarelli de Fatis, Tommaso; Buontempo, Salvatore; Cavallo, Nicola; Di Guida, Salvatore; Esposito, Marco; Fabozzi, Francesco; Iorio, Alberto Orso Maria; Lanza, Giuseppe; Lista, Luca; Meola, Sabino; Merola, Mario; Paolucci, Pierluigi; Sciacca, Crisostomo; Thyssen, Filip; Bacchetta, Nicola; Bellato, Marco; Benato, Lisa; Bisello, Dario; Boletti, Alessio; Carlin, Roberto; Checchia, Paolo; Dall'Osso, Martino; Dosselli, Umberto; Gasparini, Fabrizio; Gasparini, Ugo; Gozzelino, Andrea; Lacaprara, Stefano; Margoni, Martino; Meneguzzo, Anna Teresa; Montecassiano, Fabio; Passaseo, Marina; Pazzini, Jacopo; Pegoraro, Matteo; Pozzobon, Nicola; Simonetto, Franco; Torassa, Ezio; Tosi, Mia; Vanini, Sara; Ventura, Sandro; Zanetti, Marco; Zotto, Pierluigi; Zucchetta, Alberto; Zumerle, Gianni; Braghieri, Alessandro; Magnani, Alice; Montagna, Paolo; Ratti, Sergio P; Re, Valerio; Riccardi, Cristina; Salvini, Paola; Vai, Ilaria; Vitulo, Paolo; Alunni Solestizi, Luisa; Biasini, Maurizio; Bilei, Gian Mario; Ciangottini, Diego; Fanò, Livio; Lariccia, Paolo; Mantovani, Giancarlo; Menichelli, Mauro; Saha, Anirban; Santocchia, Attilio; Androsov, Konstantin; Azzurri, Paolo; Bagliesi, Giuseppe; Bernardini, Jacopo; Boccali, Tommaso; Castaldi, Rino; Ciocci, Maria Agnese; Dell'Orso, Roberto; Donato, Silvio; Fedi, Giacomo; Foà, Lorenzo; Giassi, Alessandro; Grippo, Maria Teresa; Ligabue, Franco; Lomtadze, Teimuraz; Martini, Luca; Messineo, Alberto; Palla, Fabrizio; Rizzi, Andrea; Savoy-Navarro, Aurore; Serban, Alin Titus; Spagnolo, Paolo; Tenchini, Roberto; Tonelli, Guido; Venturi, Andrea; Verdini, Piero Giorgio; Barone, Luciano; Cavallari, Francesca; D'imperio, Giulia; Del Re, Daniele; Diemoz, Marcella; Gelli, Simone; Jorda, Clara; Longo, Egidio; Margaroli, Fabrizio; Meridiani, Paolo; Organtini, Giovanni; Paramatti, Riccardo; Preiato, Federico; Rahatlou, Shahram; Rovelli, Chiara; Santanastasio, Francesco; Traczyk, Piotr; Amapane, Nicola; Arcidiacono, Roberta; Argiro, Stefano; Arneodo, Michele; Bellan, Riccardo; Biino, Cristina; Cartiglia, Nicolo; Costa, Marco; Covarelli, Roberto; Degano, Alessandro; Demaria, Natale; Finco, Linda; Kiani, Bilal; Mariotti, Chiara; Maselli, Silvia; Migliore, Ernesto; Monaco, Vincenzo; Monteil, Ennio; Obertino, Maria Margherita; Pacher, Luca; Pastrone, Nadia; Pelliccioni, Mario; Pinna Angioni, Gian Luca; Ravera, Fabio; Romero, Alessandra; Ruspa, Marta; Sacchi, Roberto; Solano, Ada; Staiano, Amedeo; Tamponi, Umberto; Belforte, Stefano; Candelise, Vieri; Casarsa, Massimo; Cossutti, Fabio; Della Ricca, Giuseppe; Gobbo, Benigno; La Licata, Chiara; Marone, Matteo; Schizzi, Andrea; Zanetti, Anna; Kropivnitskaya, Anna; Nam, Soon-Kwon; Kim, Dong Hee; Kim, Gui Nyun; Kim, Min Suk; Kong, Dae Jung; Lee, Sangeun; Oh, Young Do; Sakharov, Alexandre; Son, Dong-Chul; Brochero Cifuentes, Javier Andres; Kim, Hyunsoo; Kim, Tae Jeong; Song, Sanghyeon; Choi, Suyong; Go, Yeonju; Gyun, Dooyeon; Hong, Byung-Sik; Jo, Mihee; Kim, Hyunchul; Kim, Yongsun; Lee, Byounghoon; Lee, Kisoo; Lee, Kyong Sei; Lee, Songkyo; Park, Sung Keun; Roh, Youn; Yoo, Hwi Dong; Choi, Minkyoo; Kim, Hyunyong; Kim, Ji Hyun; Lee, Jason Sang Hun; Park, Inkyu; Ryu, Geonmo; Ryu, Min Sang; Choi, Young-Il; Goh, Junghwan; Kim, Donghyun; Kwon, Eunhyang; Lee, Jongseok; Yu, Intae; Dudenas, Vytautas; Juodagalvis, Andrius; Vaitkus, Juozas; Ahmed, Ijaz; Ibrahim, Zainol Abidin; Komaragiri, Jyothsna Rani; Md Ali, Mohd Adli Bin; Mohamad Idris, Faridah; Wan Abdullah, Wan Ahmad Tajuddin; Yusli, Mohd Nizam; Casimiro Linares, Edgar; Castilla-Valdez, Heriberto; De La Cruz-Burelo, Eduard; Heredia-De La Cruz, Ivan; Hernandez-Almada, Alberto; Lopez-Fernandez, Ricardo; Sánchez Hernández, Alberto; Carrillo Moreno, Salvador; Vazquez Valencia, Fabiola; Pedraza, Isabel; Salazar Ibarguen, Humberto Antonio; Morelos Pineda, Antonio; Krofcheck, David; Butler, Philip H; Ahmad, Ashfaq; Ahmad, Muhammad; Hassan, Qamar; Hoorani, Hafeez R; Khan, Wajid Ali; Khurshid, Taimoor; Shoaib, Muhammad; Bialkowska, Helena; Bluj, Michal; Boimska, Bożena; Frueboes, Tomasz; Górski, Maciej; Kazana, Malgorzata; Nawrocki, Krzysztof; Romanowska-Rybinska, Katarzyna; Szleper, Michal; Zalewski, Piotr; Brona, Grzegorz; Bunkowski, Karol; Byszuk, Adrian; Doroba, Krzysztof; Kalinowski, Artur; Konecki, Marcin; Krolikowski, Jan; Misiura, Maciej; Olszewski, Michal; Pozniak, Krzysztof; Walczak, Marek; Bargassa, Pedrame; Beirão Da Cruz E Silva, Cristóvão; Di Francesco, Agostino; Faccioli, Pietro; Ferreira Parracho, Pedro Guilherme; Gallinaro, Michele; Leonardo, Nuno; Lloret Iglesias, Lara; Nguyen, Federico; Rodrigues Antunes, Joao; Seixas, Joao; Toldaiev, Oleksii; Vadruccio, Daniele; Varela, Joao; Vischia, Pietro; Afanasiev, Serguei; Bunin, Pavel; Gavrilenko, Mikhail; Golutvin, Igor; Gorbunov, Ilya; Kamenev, Alexey; Karjavin, Vladimir; Konoplyanikov, Viktor; Lanev, Alexander; Malakhov, Alexander; Matveev, Viktor; Moisenz, Petr; Palichik, Vladimir; Perelygin, Victor; Shmatov, Sergey; Shulha, Siarhei; Skatchkov, Nikolai; Smirnov, Vitaly; Zarubin, Anatoli; Golovtsov, Victor; Ivanov, Yury; Kim, Victor; Kuznetsova, Ekaterina; Levchenko, Petr; Murzin, Victor; Oreshkin, Vadim; Smirnov, Igor; Sulimov, Valentin; Uvarov, Lev; Vavilov, Sergey; Vorobyev, Alexey; Andreev, Yuri; Dermenev, Alexander; Gninenko, Sergei; Golubev, Nikolai; Karneyeu, Anton; Kirsanov, Mikhail; Krasnikov, Nikolai; Pashenkov, Anatoli; Tlisov, Danila; Toropin, Alexander; Epshteyn, Vladimir; Gavrilov, Vladimir; Lychkovskaya, Natalia; Popov, Vladimir; Pozdnyakov, Ivan; Safronov, Grigory; Spiridonov, Alexander; Vlasov, Evgueni; Zhokin, Alexander; Bylinkin, Alexander; Andreev, Vladimir; Azarkin, Maksim; Dremin, Igor; Kirakosyan, Martin; Leonidov, Andrey; Mesyats, Gennady; Rusakov, Sergey V; Baskakov, Alexey; Belyaev, Andrey; Boos, Edouard; Dubinin, Mikhail; Dudko, Lev; Ershov, Alexander; Gribushin, Andrey; Kaminskiy, Alexandre; Klyukhin, Vyacheslav; Kodolova, Olga; Lokhtin, Igor; Miagkov, Igor; Obraztsov, Stepan; Petrushanko, Sergey; Savrin, Viktor; Azhgirey, Igor; Bayshev, Igor; Bitioukov, Sergei; Kachanov, Vassili; Kalinin, Alexey; Konstantinov, Dmitri; Krychkine, Victor; Petrov, Vladimir; Ryutin, Roman; Sobol, Andrei; Tourtchanovitch, Leonid; Troshin, Sergey; Tyurin, Nikolay; Uzunian, Andrey; Volkov, Alexey; Adzic, Petar; Milosevic, Jovan; Rekovic, Vladimir; Alcaraz Maestre, Juan; Calvo, Enrique; Cerrada, Marcos; Chamizo Llatas, Maria; Colino, Nicanor; De La Cruz, Begona; Delgado Peris, Antonio; Domínguez Vázquez, Daniel; Escalante Del Valle, Alberto; Fernandez Bedoya, Cristina; Fernández Ramos, Juan Pablo; Flix, Jose; Fouz, Maria Cruz; Garcia-Abia, Pablo; Gonzalez Lopez, Oscar; Goy Lopez, Silvia; Hernandez, Jose M; Josa, Maria Isabel; Navarro De Martino, Eduardo; Pérez-Calero Yzquierdo, Antonio María; Puerta Pelayo, Jesus; Quintario Olmeda, Adrián; Redondo, Ignacio; Romero, Luciano; Santaolalla, Javier; Soares, Mara Senghi; Albajar, Carmen; de Trocóniz, Jorge F; Missiroli, Marino; Moran, Dermot; Cuevas, Javier; Fernandez Menendez, Javier; Folgueras, Santiago; Gonzalez Caballero, Isidro; Palencia Cortezon, Enrique; Vizan Garcia, Jesus Manuel; Cabrillo, Iban Jose; Calderon, Alicia; Castiñeiras De Saa, Juan Ramon; De Castro Manzano, Pablo; Duarte Campderros, Jordi; Fernandez, Marcos; Garcia-Ferrero, Juan; Gomez, Gervasio; Lopez Virto, Amparo; Marco, Jesus; Marco, Rafael; Martinez Rivero, Celso; Matorras, Francisco; Munoz Sanchez, Francisca Javiela; Piedra Gomez, Jonatan; Rodrigo, Teresa; Rodríguez-Marrero, Ana Yaiza; Ruiz-Jimeno, Alberto; Scodellaro, Luca; Trevisani, Nicolò; Vila, Ivan; Vilar Cortabitarte, Rocio; Abbaneo, Duccio; Auffray, Etiennette; Auzinger, Georg; Bachtis, Michail; Baillon, Paul; Ball, Austin; Barney, David; Benaglia, Andrea; Bendavid, Joshua; Benhabib, Lamia; Benitez, Jose F; Berruti, Gaia Maria; Bloch, Philippe; Bocci, Andrea; Bonato, Alessio; Botta, Cristina; Breuker, Horst; Camporesi, Tiziano; Castello, Roberto; Cerminara, Gianluca; D'Alfonso, Mariarosaria; D'Enterria, David; Dabrowski, Anne; Daponte, Vincenzo; David Tinoco Mendes, Andre; De Gruttola, Michele; De Guio, Federico; De Roeck, Albert; De Visscher, Simon; Di Marco, Emanuele; Dobson, Marc; Dordevic, Milos; Dorney, Brian; Du Pree, Tristan; Dünser, Marc; Dupont, Niels; Elliott-Peisert, Anna; Franzoni, Giovanni; Funk, Wolfgang; Gigi, Dominique; Gill, Karl; Giordano, Domenico; Girone, Maria; Glege, Frank; Guida, Roberto; Gundacker, Stefan; Guthoff, Moritz; Hammer, Josef; Harris, Philip; Hegeman, Jeroen; Innocente, Vincenzo; Janot, Patrick; Kirschenmann, Henning; Kortelainen, Matti J; Kousouris, Konstantinos; Krajczar, Krisztian; Lecoq, Paul; Lourenco, Carlos; Lucchini, Marco Toliman; Magini, Nicolo; Malgeri, Luca; Mannelli, Marcello; Martelli, Arabella; Masetti, Lorenzo; Meijers, Frans; Mersi, Stefano; Meschi, Emilio; Moortgat, Filip; Morovic, Srecko; Mulders, Martijn; Nemallapudi, Mythra Varun; Neugebauer, Hannes; Orfanelli, Styliani; Orsini, Luciano; Pape, Luc; Perez, Emmanuelle; Peruzzi, Marco; Petrilli, Achille; Petrucciani, Giovanni; Pfeiffer, Andreas; Piparo, Danilo; Racz, Attila; Rolandi, Gigi; Rovere, Marco; Ruan, Manqi; Sakulin, Hannes; Schäfer, Christoph; Schwick, Christoph; Seidel, Markus; Sharma, Archana; Silva, Pedro; Simon, Michal; Sphicas, Paraskevas; Steggemann, Jan; Stieger, Benjamin; Stoye, Markus; Takahashi, Yuta; Treille, Daniel; Triossi, Andrea; Tsirou, Andromachi; Veres, Gabor Istvan; Wardle, Nicholas; Wöhri, Hermine Katharina; Zagoździńska, Agnieszka; Zeuner, Wolfram Dietrich; Bertl, Willi; Deiters, Konrad; Erdmann, Wolfram; Horisberger, Roland; Ingram, Quentin; Kaestli, Hans-Christian; Kotlinski, Danek; Langenegger, Urs; Renker, Dieter; Rohe, Tilman; Bachmair, Felix; Bäni, Lukas; Bianchini, Lorenzo; Casal, Bruno; Dissertori, Günther; Dittmar, Michael; Donegà, Mauro; Eller, Philipp; Grab, Christoph; Heidegger, Constantin; Hits, Dmitry; Hoss, Jan; Kasieczka, Gregor; Lustermann, Werner; Mangano, Boris; Marionneau, Matthieu; Martinez Ruiz del Arbol, Pablo; Masciovecchio, Mario; Meister, Daniel; Micheli, Francesco; Musella, Pasquale; Nessi-Tedaldi, Francesca; Pandolfi, Francesco; Pata, Joosep; Pauss, Felicitas; Perrozzi, Luca; Quittnat, Milena; Rossini, Marco; Starodumov, Andrei; Takahashi, Maiko; Tavolaro, Vittorio Raoul; Theofilatos, Konstantinos; Wallny, Rainer; Aarrestad, Thea Klaeboe; Amsler, Claude; Caminada, Lea; Canelli, Maria Florencia; Chiochia, Vincenzo; De Cosa, Annapaola; Galloni, Camilla; Hinzmann, Andreas; Hreus, Tomas; Kilminster, Benjamin; Lange, Clemens; Ngadiuba, Jennifer; Pinna, Deborah; Robmann, Peter; Ronga, Frederic Jean; Salerno, Daniel; Yang, Yong; Cardaci, Marco; Chen, Kuan-Hsin; Doan, Thi Hien; Jain, Shilpi; Khurana, Raman; Konyushikhin, Maxim; Kuo, Chia-Ming; Lin, Willis; Lu, Yun-Ju; Yu, Shin-Shan; Kumar, Arun; Bartek, Rachel; Chang, Paoti; Chang, You-Hao; Chang, Yu-Wei; Chao, Yuan; Chen, Kai-Feng; Chen, Po-Hsun; Dietz, Charles; Fiori, Francesco; Grundler, Ulysses; Hou, George Wei-Shu; Hsiung, Yee; Liu, Yueh-Feng; Lu, Rong-Shyang; Miñano Moya, Mercedes; Petrakou, Eleni; Tsai, Jui-fa; Tzeng, Yeng-Ming; Asavapibhop, Burin; Kovitanggoon, Kittikul; Singh, Gurpreet; Srimanobhas, Norraphat; Suwonjandee, Narumon; Adiguzel, Aytul; Bakirci, Mustafa Numan; Demiroglu, Zuhal Seyma; Dozen, Candan; Eskut, Eda; Girgis, Semiray; Gokbulut, Gul; Guler, Yalcin; Gurpinar, Emine; Hos, Ilknur; Kangal, Evrim Ersin; Onengut, Gulsen; Ozdemir, Kadri; Polatoz, Ayse; Sunar Cerci, Deniz; Tali, Bayram; Topakli, Huseyin; Vergili, Mehmet; Zorbilmez, Caglar; Akin, Ilina Vasileva; Bilin, Bugra; Bilmis, Selcuk; Isildak, Bora; Karapinar, Guler; Yalvac, Metin; Zeyrek, Mehmet; Gülmez, Erhan; Kaya, Mithat; Kaya, Ozlem; Yetkin, Elif Asli; Yetkin, Taylan; Cakir, Altan; Cankocak, Kerem; Sen, Sercan; Vardarlı, Fuat Ilkehan; Grynyov, Boris; Levchuk, Leonid; Sorokin, Pavel; Aggleton, Robin; Ball, Fionn; Beck, Lana; Brooke, James John; Clement, Emyr; Cussans, David; Flacher, Henning; Goldstein, Joel; Grimes, Mark; Heath, Greg P; Heath, Helen F; Jacob, Jeson; Kreczko, Lukasz; Lucas, Chris; Meng, Zhaoxia; Newbold, Dave M; Paramesvaran, Sudarshan; Poll, Anthony; Sakuma, Tai; Seif El Nasr-storey, Sarah; Senkin, Sergey; Smith, Dominic; Smith, Vincent J; Bell, Ken W; Belyaev, Alexander; Brew, Christopher; Brown, Robert M; Calligaris, Luigi; Cieri, Davide; Cockerill, David JA; Coughlan, John A; Harder, Kristian; Harper, Sam; Olaiya, Emmanuel; Petyt, David; Shepherd-Themistocleous, Claire; Thea, Alessandro; Tomalin, Ian R; Williams, Thomas; Womersley, William John; Worm, Steven; Baber, Mark; Bainbridge, Robert; Buchmuller, Oliver; Bundock, Aaron; Burton, Darren; Casasso, Stefano; Citron, Matthew; Colling, David; Corpe, Louie; Cripps, Nicholas; Dauncey, Paul; Davies, Gavin; De Wit, Adinda; Della Negra, Michel; Dunne, Patrick; Elwood, Adam; Ferguson, William; Fulcher, Jonathan; Futyan, David; Hall, Geoffrey; Iles, Gregory; Kenzie, Matthew; Lane, Rebecca; Lucas, Robyn; Lyons, Louis; Magnan, Anne-Marie; Malik, Sarah; Nash, Jordan; Nikitenko, Alexander; Pela, Joao; Pesaresi, Mark; Petridis, Konstantinos; Raymond, David Mark; Richards, Alexander; Rose, Andrew; Seez, Christopher; Tapper, Alexander; Uchida, Kirika; Vazquez Acosta, Monica; Virdee, Tejinder; Zenz, Seth Conrad; Cole, Joanne; Hobson, Peter R; Khan, Akram; Kyberd, Paul; Leggat, Duncan; Leslie, Dawn; Reid, Ivan; Symonds, Philip; Teodorescu, Liliana; Turner, Mark; Borzou, Ahmad; Call, Kenneth; Dittmann, Jay; Hatakeyama, Kenichi; Liu, Hongxuan; Pastika, Nathaniel; Charaf, Otman; Cooper, Seth; Henderson, Conor; Rumerio, Paolo; Arcaro, Daniel; Avetisyan, Aram; Bose, Tulika; Fantasia, Cory; Gastler, Daniel; Lawson, Philip; Rankin, Dylan; Richardson, Clint; Rohlf, James; St John, Jason; Sulak, Lawrence; Zou, David; Alimena, Juliette; Berry, Edmund; Bhattacharya, Saptaparna; Cutts, David; Dhingra, Nitish; Ferapontov, Alexey; Garabedian, Alex; Hakala, John; Heintz, Ulrich; Laird, Edward; Landsberg, Greg; Mao, Zaixing; Narain, Meenakshi; Piperov, Stefan; Sagir, Sinan; Syarif, Rizki; Breedon, Richard; Breto, Guillermo; Calderon De La Barca Sanchez, Manuel; Chauhan, Sushil; Chertok, Maxwell; Conway, John; Conway, Rylan; Cox, Peter Timothy; Erbacher, Robin; Gardner, Michael; Ko, Winston; Lander, Richard; Mulhearn, Michael; Pellett, Dave; Pilot, Justin; Ricci-Tam, Francesca; Shalhout, Shalhout; Smith, John; Squires, Michael; Stolp, Dustin; Tripathi, Mani; Wilbur, Scott; Yohay, Rachel; Cousins, Robert; Everaerts, Pieter; Farrell, Chris; Hauser, Jay; Ignatenko, Mikhail; Saltzberg, David; Takasugi, Eric; Valuev, Vyacheslav; Weber, Matthias; Burt, Kira; Clare, Robert; Ellison, John Anthony; Gary, J William; Hanson, Gail; Heilman, Jesse; Paneva, Mirena Ivova; Jandir, Pawandeep; Kennedy, Elizabeth; Lacroix, Florent; Long, Owen Rosser; Luthra, Arun; Malberti, Martina; Olmedo Negrete, Manuel; Shrinivas, Amithabh; Wei, Hua; Wimpenny, Stephen; Yates, Brent; Branson, James G; Cerati, Giuseppe Benedetto; Cittolin, Sergio; D'Agnolo, Raffaele Tito; Derdzinski, Mark; Holzner, André; Kelley, Ryan; Klein, Daniel; Letts, James; Macneill, Ian; Olivito, Dominick; Padhi, Sanjay; Pieri, Marco; Sani, Matteo; Sharma, Vivek; Simon, Sean; Tadel, Matevz; Vartak, Adish; Wasserbaech, Steven; Welke, Charles; Würthwein, Frank; Yagil, Avraham; Zevi Della Porta, Giovanni; Bradmiller-Feld, John; Campagnari, Claudio; Dishaw, Adam; Dutta, Valentina; Flowers, Kristen; Franco Sevilla, Manuel; Geffert, Paul; George, Christopher; Golf, Frank; Gouskos, Loukas; Gran, Jason; Incandela, Joe; Mccoll, Nickolas; Mullin, Sam Daniel; Richman, Jeffrey; Stuart, David; Suarez, Indara; West, Christopher; Yoo, Jaehyeok; Anderson, Dustin; Apresyan, Artur; Bornheim, Adolf; Bunn, Julian; Chen, Yi; Duarte, Javier; Mott, Alexander; Newman, Harvey B; Pena, Cristian; Pierini, Maurizio; Spiropulu, Maria; Vlimant, Jean-Roch; Xie, Si; Zhu, Ren-Yuan; Andrews, Michael Benjamin; Azzolini, Virginia; Calamba, Aristotle; Carlson, Benjamin; Ferguson, Thomas; Paulini, Manfred; Russ, James; Sun, Menglei; Vogel, Helmut; Vorobiev, Igor; Cumalat, John Perry; Ford, William T; Gaz, Alessandro; Jensen, Frank; Johnson, Andrew; Krohn, Michael; Mulholland, Troy; Nauenberg, Uriel; Stenson, Kevin; Wagner, Stephen Robert; Alexander, James; Chatterjee, Avishek; Chaves, Jorge; Chu, Jennifer; Dittmer, Susan; Eggert, Nicholas; Mirman, Nathan; Nicolas Kaufman, Gala; Patterson, Juliet Ritchie; Rinkevicius, Aurelijus; Ryd, Anders; Skinnari, Louise; Soffi, Livia; Sun, Werner; Tan, Shao Min; Teo, Wee Don; Thom, Julia; Thompson, Joshua; Tucker, Jordan; Weng, Yao; Wittich, Peter; Abdullin, Salavat; Albrow, Michael; Anderson, Jacob; Apollinari, Giorgio; Banerjee, Sunanda; Bauerdick, Lothar AT; Beretvas, Andrew; Berryhill, Jeffrey; Bhat, Pushpalatha C; Bolla, Gino; Burkett, Kevin; Butler, Joel Nathan; Cheung, Harry; Chlebana, Frank; Cihangir, Selcuk; Elvira, Victor Daniel; Fisk, Ian; Freeman, Jim; Gottschalk, Erik; Gray, Lindsey; Green, Dan; Grünendahl, Stefan; Gutsche, Oliver; Hanlon, Jim; Hare, Daryl; Harris, Robert M; Hasegawa, Satoshi; Hirschauer, James; Hu, Zhen; Jayatilaka, Bodhitha; Jindariani, Sergo; Johnson, Marvin; Joshi, Umesh; Jung, Andreas Werner; Klima, Boaz; Kreis, Benjamin; Kwan, Simon; Lammel, Stephan; Linacre, Jacob; Lincoln, Don; Lipton, Ron; Liu, Tiehui; Lopes De Sá, Rafael; Lykken, Joseph; Maeshima, Kaori; Marraffino, John Michael; Martinez Outschoorn, Verena Ingrid; Maruyama, Sho; Mason, David; McBride, Patricia; Merkel, Petra; Mishra, Kalanand; Mrenna, Stephen; Nahn, Steve; Newman-Holmes, Catherine; O'Dell, Vivian; Pedro, Kevin; Prokofyev, Oleg; Rakness, Gregory; Sexton-Kennedy, Elizabeth; Soha, Aron; Spalding, William J; Spiegel, Leonard; Taylor, Lucas; Tkaczyk, Slawek; Tran, Nhan Viet; Uplegger, Lorenzo; Vaandering, Eric Wayne; Vernieri, Caterina; Verzocchi, Marco; Vidal, Richard; Weber, Hannsjoerg Artur; Whitbeck, Andrew; Yang, Fan; Acosta, Darin; Avery, Paul; Bortignon, Pierluigi; Bourilkov, Dimitri; Carnes, Andrew; Carver, Matthew; Curry, David; Das, Souvik; Di Giovanni, Gian Piero; Field, Richard D; Furic, Ivan-Kresimir; Gleyzer, Sergei V; Hugon, Justin; Konigsberg, Jacobo; Korytov, Andrey; Low, Jia Fu; Ma, Peisen; Matchev, Konstantin; Mei, Hualin; Milenovic, Predrag; Mitselmakher, Guenakh; Rank, Douglas; Rossin, Roberto; Shchutska, Lesya; Snowball, Matthew; Sperka, David; Terentyev, Nikolay; Thomas, Laurent; Wang, Jian; Wang, Sean-Jiun; Yelton, John; Hewamanage, Samantha; Linn, Stephan; Markowitz, Pete; Martinez, German; Rodriguez, Jorge Luis; Ackert, Andrew; Adams, Jordon Rowe; Adams, Todd; Askew, Andrew; Bochenek, Joseph; Diamond, Brendan; Haas, Jeff; Hagopian, Sharon; Hagopian, Vasken; Johnson, Kurtis F; Khatiwada, Ajeeta; Prosper, Harrison; Weinberg, Marc; Baarmand, Marc M; Bhopatkar, Vallary; Colafranceschi, Stefano; Hohlmann, Marcus; Kalakhety, Himali; Noonan, Daniel; Roy, Titas; Yumiceva, Francisco; Adams, Mark Raymond; Apanasevich, Leonard; Berry, Douglas; Betts, Russell Richard; Bucinskaite, Inga; Cavanaugh, Richard; Evdokimov, Olga; Gauthier, Lucie; Gerber, Cecilia Elena; Hofman, David Jonathan; Kurt, Pelin; O'Brien, Christine; Sandoval Gonzalez, Irving Daniel; Silkworth, Christopher; Turner, Paul; Varelas, Nikos; Wu, Zhenbin; Zakaria, Mohammed; Bilki, Burak; Clarida, Warren; Dilsiz, Kamuran; Durgut, Süleyman; Gandrajula, Reddy Pratap; Haytmyradov, Maksat; Khristenko, Viktor; Merlo, Jean-Pierre; Mermerkaya, Hamit; Mestvirishvili, Alexi; Moeller, Anthony; Nachtman, Jane; Ogul, Hasan; Onel, Yasar; Ozok, Ferhat; Penzo, Aldo; Snyder, Christina; Tiras, Emrah; Wetzel, James; Yi, Kai; Anderson, Ian; Barnett, Bruce Arnold; Blumenfeld, Barry; Eminizer, Nicholas; Fehling, David; Feng, Lei; Gritsan, Andrei; Maksimovic, Petar; Martin, Christopher; Osherson, Marc; Roskes, Jeffrey; Cocoros, Alice; Sarica, Ulascan; Swartz, Morris; Xiao, Meng; Xin, Yongjie; You, Can; Baringer, Philip; Bean, Alice; Benelli, Gabriele; Bruner, Christopher; Kenny III, Raymond Patrick; Majumder, Devdatta; Malek, Magdalena; Murray, Michael; Sanders, Stephen; Stringer, Robert; Wang, Quan; Ivanov, Andrew; Kaadze, Ketino; Khalil, Sadia; Makouski, Mikhail; Maravin, Yurii; Mohammadi, Abdollah; Saini, Lovedeep Kaur; Skhirtladze, Nikoloz; Toda, Sachiko; Lange, David; Rebassoo, Finn; Wright, Douglas; Anelli, Christopher; Baden, Drew; Baron, Owen; Belloni, Alberto; Calvert, Brian; Eno, Sarah Catherine; Ferraioli, Charles; Gomez, Jaime; Hadley, Nicholas John; Jabeen, Shabnam; Kellogg, Richard G; Kolberg, Ted; Kunkle, Joshua; Lu, Ying; Mignerey, Alice; Shin, Young Ho; Skuja, Andris; Tonjes, Marguerite; Tonwar, Suresh C; Apyan, Aram; Barbieri, Richard; Baty, Austin; Bierwagen, Katharina; Brandt, Stephanie; Busza, Wit; Cali, Ivan Amos; Demiragli, Zeynep; Di Matteo, Leonardo; Gomez Ceballos, Guillelmo; Goncharov, Maxim; Gulhan, Doga; Iiyama, Yutaro; Innocenti, Gian Michele; Klute, Markus; Kovalskyi, Dmytro; Lai, Yue Shi; Lee, Yen-Jie; Levin, Andrew; Luckey, Paul David; Marini, Andrea Carlo; Mcginn, Christopher; Mironov, Camelia; Narayanan, Siddharth; Niu, Xinmei; Paus, Christoph; Ralph, Duncan; Roland, Christof; Roland, Gunther; Salfeld-Nebgen, Jakob; Stephans, George; Sumorok, Konstanty; Varma, Mukund; Velicanu, Dragos; Veverka, Jan; Wang, Jing; Wang, Ta-Wei; Wyslouch, Bolek; Yang, Mingming; Zhukova, Victoria; Dahmes, Bryan; Evans, Andrew; Finkel, Alexey; Gude, Alexander; Hansen, Peter; Kalafut, Sean; Kao, Shih-Chuan; Klapoetke, Kevin; Kubota, Yuichi; Lesko, Zachary; Mans, Jeremy; Nourbakhsh, Shervin; Ruckstuhl, Nicole; Rusack, Roger; Tambe, Norbert; Turkewitz, Jared; Acosta, John Gabriel; Oliveros, Sandra; Avdeeva, Ekaterina; Bloom, Kenneth; Bose, Suvadeep; Claes, Daniel R; Dominguez, Aaron; Fangmeier, Caleb; Gonzalez Suarez, Rebeca; Kamalieddin, Rami; Keller, Jason; Knowlton, Dan; Kravchenko, Ilya; Meier, Frank; Monroy, Jose; Ratnikov, Fedor; Siado, Joaquin Emilo; Snow, Gregory R; Alyari, Maral; Dolen, James; George, Jimin; Godshalk, Andrew; Harrington, Charles; Iashvili, Ia; Kaisen, Josh; Kharchilava, Avto; Kumar, Ashish; Rappoccio, Salvatore; Roozbahani, Bahareh; Alverson, George; Barberis, Emanuela; Baumgartel, Darin; Chasco, Matthew; Hortiangtham, Apichart; Massironi, Andrea; Morse, David Michael; Nash, David; Orimoto, Toyoko; Teixeira De Lima, Rafael; Trocino, Daniele; Wang, Ren-Jie; Wood, Darien; Zhang, Jinzhong; Hahn, Kristan Allan; Kubik, Andrew; Mucia, Nicholas; Odell, Nathaniel; Pollack, Brian; Pozdnyakov, Andrey; Schmitt, Michael Henry; Stoynev, Stoyan; Sung, Kevin; Trovato, Marco; Velasco, Mayda; Brinkerhoff, Andrew; Dev, Nabarun; Hildreth, Michael; Jessop, Colin; Karmgard, Daniel John; Kellams, Nathan; Lannon, Kevin; Lynch, Sean; Marinelli, Nancy; Meng, Fanbo; Mueller, Charles; Musienko, Yuri; Pearson, Tessa; Planer, Michael; Reinsvold, Allison; Ruchti, Randy; Smith, Geoffrey; Taroni, Silvia; Valls, Nil; Wayne, Mitchell; Wolf, Matthias; Woodard, Anna; Antonelli, Louis; Brinson, Jessica; Bylsma, Ben; Durkin, Lloyd Stanley; Flowers, Sean; Hart, Andrew; Hill, Christopher; Hughes, Richard; Ji, Weifeng; Kotov, Khristian; Ling, Ta-Yung; Liu, Bingxuan; Luo, Wuming; Puigh, Darren; Rodenburg, Marissa; Winer, Brian L; Wulsin, Howard Wells; Driga, Olga; Elmer, Peter; Hardenbrook, Joshua; Hebda, Philip; Koay, Sue Ann; Lujan, Paul; Marlow, Daniel; Medvedeva, Tatiana; Mooney, Michael; Olsen, James; Palmer, Christopher; Piroué, Pierre; Saka, Halil; Stickland, David; Tully, Christopher; Zuranski, Andrzej; Malik, Sudhir; Barnes, Virgil E; Benedetti, Daniele; Bortoletto, Daniela; Gutay, Laszlo; Jha, Manoj; Jones, Matthew; Jung, Kurt; Miller, David Harry; Neumeister, Norbert; Radburn-Smith, Benjamin Charles; Shi, Xin; Shipsey, Ian; Silvers, David; Sun, Jian; Svyatkovskiy, Alexey; Wang, Fuqiang; Xie, Wei; Xu, Lingshan; Parashar, Neeti; Stupak, John; Adair, Antony; Akgun, Bora; Chen, Zhenyu; Ecklund, Karl Matthew; Geurts, Frank JM; Guilbaud, Maxime; Li, Wei; Michlin, Benjamin; Northup, Michael; Padley, Brian Paul; Redjimi, Radia; Roberts, Jay; Rorie, Jamal; Tu, Zhoudunming; Zabel, James; Betchart, Burton; Bodek, Arie; de Barbaro, Pawel; Demina, Regina; Eshaq, Yossof; Ferbel, Thomas; Galanti, Mario; Garcia-Bellido, Aran; Han, Jiyeon; Harel, Amnon; Hindrichs, Otto; Khukhunaishvili, Aleko; Petrillo, Gianluca; Tan, Ping; Verzetti, Mauro; Arora, Sanjay; Barker, Anthony; Chou, John Paul; Contreras-Campana, Christian; Contreras-Campana, Emmanuel; Duggan, Daniel; Ferencek, Dinko; Gershtein, Yuri; Gray, Richard; Halkiadakis, Eva; Hidas, Dean; Hughes, Elliot; Kaplan, Steven; Kunnawalkam Elayavalli, Raghav; Lath, Amitabh; Nash, Kevin; Panwalkar, Shruti; Park, Michael; Salur, Sevil; Schnetzer, Steve; Sheffield, David; Somalwar, Sunil; Stone, Robert; Thomas, Scott; Thomassen, Peter; Walker, Matthew; Foerster, Mark; Riley, Grant; Rose, Keith; Spanier, Stefan; York, Andrew; Bouhali, Othmane; Castaneda Hernandez, Alfredo; Dalchenko, Mykhailo; De Mattia, Marco; Delgado, Andrea; Dildick, Sven; Eusebi, Ricardo; Gilmore, Jason; Kamon, Teruki; Krutelyov, Vyacheslav; Mueller, Ryan; Osipenkov, Ilya; Pakhotin, Yuriy; Patel, Rishi; Perloff, Alexx; Rose, Anthony; Safonov, Alexei; Tatarinov, Aysen; Ulmer, Keith; Akchurin, Nural; Cowden, Christopher; Damgov, Jordan; Dragoiu, Cosmin; Dudero, Phillip Russell; Faulkner, James; Kunori, Shuichi; Lamichhane, Kamal; Lee, Sung Won; Libeiro, Terence; Undleeb, Sonaina; Volobouev, Igor; Appelt, Eric; Delannoy, Andrés G; Greene, Senta; Gurrola, Alfredo; Janjam, Ravi; Johns, Willard; Maguire, Charles; Mao, Yaxian; Melo, Andrew; Ni, Hong; Sheldon, Paul; Snook, Benjamin; Tuo, Shengquan; Velkovska, Julia; Xu, Qiao; Arenton, Michael Wayne; Cox, Bradley; Francis, Brian; Goodell, Joseph; Hirosky, Robert; Ledovskoy, Alexander; Li, Hengne; Lin, Chuanzhe; Neu, Christopher; Sinthuprasith, Tutanon; Sun, Xin; Wang, Yanchu; Wolfe, Evan; Wood, John; Xia, Fan; Clarke, Christopher; Harr, Robert; Karchin, Paul Edmund; Kottachchi Kankanamge Don, Chamath; Lamichhane, Pramod; Sturdy, Jared; Belknap, Donald; Carlsmith, Duncan; Cepeda, Maria; Dasu, Sridhara; Dodd, Laura; Duric, Senka; Gomber, Bhawna; Grothe, Monika; Hall-Wilton, Richard; Herndon, Matthew; Hervé, Alain; Klabbers, Pamela; Lanaro, Armando; Levine, Aaron; Long, Kenneth; Loveless, Richard; Mohapatra, Ajit; Ojalvo, Isabel; Perry, Thomas; Pierro, Giuseppe Antonio; Polese, Giovanni; Ruggles, Tyler; Sarangi, Tapas; Savin, Alexander; Sharma, Archana; Smith, Nicholas; Smith, Wesley H; Taylor, Devin; Woods, Nathaniel

    2016-01-01

    This paper describes the CMS trigger system and its performance during Run 1 of the LHC. The trigger system consists of two levels designed to select events of potential physics interest from a GHz (MHz) interaction rate of proton-proton (heavy ion) collisions. The first level of the trigger is implemented in hardware, and selects events containing detector signals consistent with an electron, photon, muon, $\\tau$ lepton, jet, or missing transverse energy. A programmable menu of up to 128 object-based algorithms is used to select events for subsequent processing. The trigger thresholds are adjusted to the LHC instantaneous luminosity during data taking in order to restrict the output rate to 100 kHz, the upper limit imposed by the CMS readout electronics. The second level, implemented in software, further refines the purity of the output stream, selecting an average rate of 400 Hz for offline event storage. The objectives, strategy and performance of the trigger system during the LHC Run 1 are described.

  7. Implementation of a level 1 trigger system using high speed serial (VXS) techniques for the 12GeV high luminosity experimental programs at Thomas Jefferson National Accelerator Facility

    International Nuclear Information System (INIS)

    We will demonstrate a hardware and firmware solution for a complete fully pipelined multi-crate trigger system that takes advantage of the elegant high speed VXS serial extensions for VME. This trigger system includes three sections starting with the front end crate trigger processor (CTP), a global Sub-System Processor (SSP) and a Trigger Supervisor that manages the timing, synchronization and front end event readout. Within a front end crate, trigger information is gathered from each 16 Channel, 12 bit Flash ADC module at 4 nS intervals via the VXS backplane, to a Crate Trigger Processor (CTP). Each Crate Trigger Processor receives these 500 MB/S VXS links from the 16 FADC-250 modules, aligns skewed data inherent of Aurora protocol, and performs real time crate level trigger algorithms. The algorithm results are encoded using a Reed-Solomon technique and transmission of this Level 1 trigger data is sent to the SSP using a multi-fiber link. The multi-fiber link achieves an aggregate trigger data transfer rate to the global trigger at 8 Gb/s. The SSP receives and decodes Reed-Solomon error correcting transmission from each crate, aligns the data, and performs the global level trigger algorithms. The entire trigger system is synchronous and operates at 250 MHz with the Trigger Supervisor managing not only the front end event readout, but also the distribution of the critical timing clocks, synchronization signals, and the global trigger signals to each front end readout crate. These signals are distributed to the front end crates on a separate fiber link and each crate is synchronized using a unique encoding scheme to guarantee that each front end crate is synchronous with a fixed latency, independent of the distance between each crate. The overall trigger signal latency is <3 uS, and the proposed 12GeV experiments at Jefferson Lab require up to 200KHz Level 1 trigger rate.

  8. Design studies for the Double Chooz trigger

    International Nuclear Information System (INIS)

    The main characteristic of the neutrino mixing effect is assumed to be the coupling between the flavor and the mass eigenstates. Three mixing angles (θ12, θ23, θ13) are describing the magnitude of this effect. Still unknown, θ13 is considered very small, based on the measurement done by the CHOOZ experiment. A leading experiment will be Double Chooz, placed in the Ardennes region, on the same site as used by CHOOZ. The Double Chooz goal is the exploration of ∝80% from the currently allowed θ13 region, by searching the disappearance of reactor antineutrinos. Double Chooz will use two similar detectors, located at different distances from the reactor cores: a near one at ∝150 m where no oscillations are expected and a far one at 1.05 km distance, close to the first minimum of the survival probability function. The measurement foresees a precise comparison of neutrino rates and spectra between both detectors. The detection mechanism is based on the inverse β-decay. The Double Chooz detectors have been designed to minimize the rate of random background. In a simplified view, two optically separated regions are considered. The target, filled with Gd-doped liquid scintillator, is the main antineutrino interaction volume. Surrounding the target, the inner veto region aims to tag the cosmogenic muon background which hits the detector. Both regions are viewed by photomultipliers. The Double Chooz trigger system has to be highly efficient for antineutrino events as well as for several types of background. The trigger analyzes discriminated signals from the central region and the inner veto photomultipliers. The trigger logic is fully programmable and can combine the input signals. The trigger conditions are based on the total energy released in event and on the PMT groups multiplicity. For redundancy, two independent trigger boards will be used for the central region, each of them receiving signals from half of the photomultipliers. A third trigger board will

  9. Design studies for the Double Chooz trigger

    Energy Technology Data Exchange (ETDEWEB)

    Cucoanes, Andi Sebastian

    2009-07-24

    The main characteristic of the neutrino mixing effect is assumed to be the coupling between the flavor and the mass eigenstates. Three mixing angles ({theta}{sub 12}, {theta}{sub 23}, {theta}{sub 13}) are describing the magnitude of this effect. Still unknown, {theta}{sub 13} is considered very small, based on the measurement done by the CHOOZ experiment. A leading experiment will be Double Chooz, placed in the Ardennes region, on the same site as used by CHOOZ. The Double Chooz goal is the exploration of {proportional_to}80% from the currently allowed {theta}{sub 13} region, by searching the disappearance of reactor antineutrinos. Double Chooz will use two similar detectors, located at different distances from the reactor cores: a near one at {proportional_to}150 m where no oscillations are expected and a far one at 1.05 km distance, close to the first minimum of the survival probability function. The measurement foresees a precise comparison of neutrino rates and spectra between both detectors. The detection mechanism is based on the inverse {beta}-decay. The Double Chooz detectors have been designed to minimize the rate of random background. In a simplified view, two optically separated regions are considered. The target, filled with Gd-doped liquid scintillator, is the main antineutrino interaction volume. Surrounding the target, the inner veto region aims to tag the cosmogenic muon background which hits the detector. Both regions are viewed by photomultipliers. The Double Chooz trigger system has to be highly efficient for antineutrino events as well as for several types of background. The trigger analyzes discriminated signals from the central region and the inner veto photomultipliers. The trigger logic is fully programmable and can combine the input signals. The trigger conditions are based on the total energy released in event and on the PMT groups multiplicity. For redundancy, two independent trigger boards will be used for the central region, each of

  10. Associative Memory design for the Fast TracK processor (FTK) at Atlas

    CERN Document Server

    Annovi, A; The ATLAS collaboration; Bossini, E; Crescioli, F; Dell'Orso, M; Giannetti, P; Piendibene, M; Sacco, I; Sartori, L; Tripiccione, R

    2010-01-01

    We describe a VLSI processor for pattern recognition based on Content Addressable Memory (CAM) architecture, optimized for on-line track finding in high-energy physics experiments. A large CAM bank stores all trajectories of interest and extracts the ones compatible with a given event. This task is naturally parallelized by a CAM architecture able to output identified trajectories, recognized among a huge amount of possible combinations, in just a few 100 MHz clock cycles. We have developed this device (called the AMchip03 processor), using 180 nm technology, for the Silicon Vertex Trigger (SVT) upgrade at CDF using a standard-cell VLSI design methodology. We propose now a new design (90 nm technology) where we introduce a full custom standard cell. This is a customized design that allows to maximize the pattern density and to minimize the power consumption. We discuss also possible future extensions based on 3-D technology. This processor has a flexible and easily configurable structure that makes it suitabl...

  11. Modcomp MAX IV System Processors reference guide

    Energy Technology Data Exchange (ETDEWEB)

    Cummings, J.

    1990-10-01

    A user almost always faces a big problem when having to learn to use a new computer system. The information necessary to use the system is often scattered throughout many different manuals. The user also faces the problem of extracting the information really needed from each manual. Very few computer vendors supply a single Users Guide or even a manual to help the new user locate the necessary manuals. Modcomp is no exception to this, Modcomp MAX IV requires that the user be familiar with the system file usage which adds to the problem. At General Atomics there is an ever increasing need for new users to learn how to use the Modcomp computers. This paper was written to provide a condensed Users Reference Guide'' for Modcomp computer users. This manual should be of value not only to new users but any users that are not Modcomp computer systems experts. This Users Reference Guide'' is intended to provided the basic information for the use of the various Modcomp System Processors necessary to, create, compile, link-edit, and catalog a program. Only the information necessary to provide the user with a basic understanding of the Systems Processors is included. This document provides enough information for the majority of programmers to use the Modcomp computers without having to refer to any other manuals. A lot of emphasis has been placed on the file description and usage for each of the System Processors. This allows the user to understand how Modcomp MAX IV does things rather than just learning the system commands.

  12. Comparison of triggering systems for neonatal patient triggered ventilation.

    OpenAIRE

    Hird, M F; Greenough, A

    1991-01-01

    The efficacy of two triggering systems was compared during neonatal patient triggered ventilation: the Graseby MR10 respiration monitor and airway pressure changes. Ten preterm infants were studied, median gestational age 33 weeks (range 28-35). Patient triggered ventilation was administered via the SLE ventilator at a series of inflation times (0.24, 0.3, and 0.4 seconds). Comparison was made between the trigger systems of the trigger delay, inflation volume delivered, and proportion of spon...

  13. Optical linear algebra processors - Architectures and algorithms

    Science.gov (United States)

    Casasent, David

    1986-01-01

    Attention is given to the component design and optical configuration features of a generic optical linear algebra processor (OLAP) architecture, as well as the large number of OLAP architectures, number representations, algorithms and applications encountered in current literature. Number-representation issues associated with bipolar and complex-valued data representations, high-accuracy (including floating point) performance, and the base or radix to be employed, are discussed, together with case studies on a space-integrating frequency-multiplexed architecture and a hybrid space-integrating and time-integrating multichannel architecture.

  14. Introduction to programming multiple-processor computers

    International Nuclear Information System (INIS)

    FORTRAN applications programs can be executed on multiprocessor computers in either a unitasking (traditional) or multitasking form. The latter allows a single job to use more than one processor simultaneously, with a consequent reduction in wall-clock time and, perhaps, the cost of the calculation. An introduction to programming in this environment is presented. The concepts of synchronization and data sharing using EVENTS and LOCKS are illustrated with examples. The strategy of strong synchronization and the use of synchronization templates are proposed. We emphasize that incorrect multitasking programs can produce irreproducible results, which makes debugging more difficult

  15. Integral Fast Reactor fuel pin processor

    International Nuclear Information System (INIS)

    This report discusses the pin processor which receives metal alloy pins cast from recycled Integral Fast Reactor (IFR) fuel and prepares them for assembly into new IFR fuel elements. Either full length as-cast or precut pins are fed to the machine from a magazine, cut if necessary, and measured for length, weight, diameter and deviation from straightness. Accepted pins are loaded into cladding jackets located in a magazine, while rejects and cutting scraps are separated into trays. The magazines, trays, and the individual modules that perform the different machine functions are assembled and removed using remote manipulators and master-slaves

  16. Generalized measurements via programmable quantum processor

    CERN Document Server

    Rosko, M; Chouha, P R; Hillery, M; Rosko, Marian; Buzek, Vladimir; Chouha, Paul Robert; Hillery, Mark

    2003-01-01

    We show that it is possible to control the trade-off between information gain and disturbance in generalized measurements of qudits by utilizing the programmable quantum processor. This universal quantum machine allows us to perform a generalized measurement on the initial state of the input qudit to construct a Husimi function of this state. The trade-off between the gain and the disturbance of the qudit is controlled by the initial state of ancillary system that acts as a program register for the quantum-information distributor. The trade-off fidelity does not depend on the initial state of the qudit.

  17. Generalized measurements via a programmable quantum processor

    International Nuclear Information System (INIS)

    We show that it is possible to control the trade-off between information gain and disturbance in generalized measurements of qudits by utilizing a programmable quantum processor. This universal quantum machine allows us to perform a generalized measurement on the initial state of the input qudit to construct a Husimi function of this state. The trade-off between the gain and the disturbance of the qudit is controlled by the initial state of ancillary system that acts as a program for the quantum-information distributor. The trade-off fidelity does not depend on the initial state of the qudit

  18. Processor Reformats Data For Transmission In Bursts

    Science.gov (United States)

    Steele, Glen F.

    1991-01-01

    Data-processor-and-buffer electronic system receives audio signals digitized in first standard format at relatively low data rate, rearranges data for transmission in bursts in second standard format at relatively high rate, stores second-format bursts, and releases them at higher rate upon request. Conceived for asynchronous, one-way transmission of digitized speech in outer-space communications, concept of system applied in other digital communication systems in which data transmitted from low-rate sources to high-rate sinks not synchronized with sources.

  19. Initial upgrade of the ATLAS Level-1 Calorimeter Trigger

    CERN Document Server

    Ta, DB; The ATLAS collaboration

    2014-01-01

    The Level-1 calorimeter trigger~(L1Calo) of the ATLAS experiment has been operating well since the start of Large Hadron Collider~(LHC) data taking, and played a major role in the Higgs boson discovery. To face the new challenges posed by the upcoming increases of the LHC proton beam energy and luminosity, a series of upgrades is planned for the L1Calo. This paper presents the first L1Calo upgrade program for the initial upgrade phase in 2013-14. The program includes substantial improvements to the analogue and digital signal processing. Two existing digital algorithm processor subsystems will receive substantial hardware and firmware upgrades, allowing topological information to be transmitted and processed. An entirely new subsystem, the L1 topological processor, will receive real-time data from both the upgraded L1Calo and L1 muon trigger to perform trigger algorithms based on entire event topologies. The expected performance improvements are described together with the upgraded hardware and firmware imple...

  20. Trigger/front end electronics and data collection

    International Nuclear Information System (INIS)

    The data collection system in the B factory at KEK is planned to have the features that the beam cross intervals will be small (15-30 necs), that the first-step trigger frequency will be 1 kHz, that the frequency of data transfer from the mass storage will be around 10 Hz, and that the data capacity will be 256 kilobyte/sec at most. A possible approach to meet these requirements is to use a trigger system of a pipeline mechanism, a multiple front end system, a high-speed data scanning module and a large-scale processor farm. The trigger system is intended to extract high-speed signals from the detector and to start and control the entire data collection system. The start signals and control signals should synchronize with the beam cross. The front end electronics comprises high-sensitivity analog electronics, including front amplifier, and an analog/digital converter. The data collection system has a tree structure. Its lowest layer comprises a multiple buffered memory. Required data are extracted by the high-speed data scanning module, stored in a memory incorporated in the scanning module, and then transferred to the processor farm. (N.K.)

  1. Triggering and Delivery Algorithms for AGN Feedback

    CERN Document Server

    Meece, Gregory R; O'Shea, Brian W

    2016-01-01

    We compare several common sub-grid implementations of AGN feedback, focusing on the effects of different triggering mechanisms and the differences between thermal and kinetic feedback. Our main result is that pure thermal feedback that is centrally injected behaves differently from feedback with even a small kinetic component. Specifically, pure thermal feedback results in excessive condensation and smothering of the AGN by cold gas because the feedback energy does not propagate to large enough radii. We do not see large differences between implementations of different triggering mechanisms, as long as the spatial resolution is sufficiently high, probably because all of the implementations tested here trigger strong AGN feedback under similar conditions. In order to assess the role of resolution, we vary the size of the "accretion zone" in which properties are measured to determine the AGN accretion rate and resulting feedback power. We find that a larger accretion zone results in steadier jets but can also a...

  2. The data path of the ATLAS level-1 calorimeter trigger preprocessor

    Energy Technology Data Exchange (ETDEWEB)

    Andrei, George Victor

    2010-10-27

    The PreProcessor of the ATLAS Level-1 Calorimeter Trigger provides digital values of transverse energy in real-time to the subsequent object-finding processors. The input comprises more than 7000 analogue signals of reduced granularity from the calorimeters of the ATLAS detector. The Level-1 trigger decision must be verified. For this, the PreProcessor transmits copies of the real-time digital data to the Data Acquisition (DAQ) system. In addition, the PreProcessor system provides a standard VMEbus interface to the computing infrastructure of the experiment, on which configuration data is loaded and control or monitoring data are read out. A dedicated system that ensures both the transfer of event data to storage in ATLAS and the data transfer over the VME was implemented on the 124 modules of the PreProcessor system in the form of a ''Readout Manager''. The ''Field Programmable Gate Array'' (FPGA) is located on each module. The rst part of this work describes the algorithms developed to meet the functionality of the Readout Manager. The second part deals with the tests that were carried out to ensure the proper functionality of the modules before they were installed at CERN in the ATLAS cavern. (orig.)

  3. The data path of the ATLAS level-1 calorimeter trigger preprocessor

    International Nuclear Information System (INIS)

    The PreProcessor of the ATLAS Level-1 Calorimeter Trigger provides digital values of transverse energy in real-time to the subsequent object-finding processors. The input comprises more than 7000 analogue signals of reduced granularity from the calorimeters of the ATLAS detector. The Level-1 trigger decision must be verified. For this, the PreProcessor transmits copies of the real-time digital data to the Data Acquisition (DAQ) system. In addition, the PreProcessor system provides a standard VMEbus interface to the computing infrastructure of the experiment, on which configuration data is loaded and control or monitoring data are read out. A dedicated system that ensures both the transfer of event data to storage in ATLAS and the data transfer over the VME was implemented on the 124 modules of the PreProcessor system in the form of a ''Readout Manager''. The ''Field Programmable Gate Array'' (FPGA) is located on each module. The rst part of this work describes the algorithms developed to meet the functionality of the Readout Manager. The second part deals with the tests that were carried out to ensure the proper functionality of the modules before they were installed at CERN in the ATLAS cavern. (orig.)

  4. A 250 MHz Level 1 Trigger and Distribution System for the GlueX experiment

    Energy Technology Data Exchange (ETDEWEB)

    Abbott, David J. [JLAB; Cuevas, R. Christopher [JLAB; Doughty, David Charles [Christopher Newport U., JLAB; Jastrzembski, Edward A. [JLAB; Barbosa, Fernando J. [JLAB; Raydo, Benjamin J. [JLAB; Dong, Hai T. [JLAB; Wilson, Jeffrey S. [JLAB; Gupta, Abishek [JLAB; Taylor, Mark [JLAB; Somov, S. [JLAB

    2009-11-01

    The GlueX detector now under construction at Jefferson Lab will search for exotic mesons though photoproduction (10^8 tagged photons per second) on a liquid hydrogen target. A Level 1 hardware trigger design is being developed to reduce total electromagnetic (>200 MHz) and hadronic (>350 kHz) rates to less than 200 kHz. This trigger is dead timeless and operates on a global synchronized 250 MHz clock. The core of the trigger design is based on a custom pipelined flash ADC board that uses a VXS backplane to collect samples from all ADCs in a VME crate. A custom switch-slot board called a Crate Trigger Processor (CTP) processes this data and passes the crate level data via a multi-lane fiber optic link to the Global Trigger Processing Crate (also VXS). Within this crate detector sub-system processor (SSP) boards can accept all individual crate links. The subsystem data are processed and finally passed to global trigger boards (GTP) where the final L1 decision is made. We present details of the trigger design and report some performance results on current prototype systems.

  5. The ISS Water Processor Catalytic Reactor as a Post Processor for Advanced Water Reclamation Systems

    Science.gov (United States)

    Nalette, Tim; Snowdon, Doug; Pickering, Karen D.; Callahan, Michael

    2007-01-01

    Advanced water processors being developed for NASA s Exploration Initiative rely on phase change technologies and/or biological processes as the primary means of water reclamation. As a result of the phase change, volatile compounds will also be transported into the distillate product stream. The catalytic reactor assembly used in the International Space Station (ISS) water processor assembly, referred to as Volatile Removal Assembly (VRA), has demonstrated high efficiency oxidation of many of these volatile contaminants, such as low molecular weight alcohols and acetic acid, and is considered a viable post treatment system for all advanced water processors. To support this investigation, two ersatz solutions were defined to be used for further evaluation of the VRA. The first solution was developed as part of an internal research and development project at Hamilton Sundstrand (HS) and is based primarily on ISS experience related to the development of the VRA. The second ersatz solution was defined by NASA in support of a study contract to Hamilton Sundstrand to evaluate the VRA as a potential post processor for the Cascade Distillation system being developed by Honeywell. This second ersatz solution contains several low molecular weight alcohols, organic acids, and several inorganic species. A range of residence times, oxygen concentrations and operating temperatures have been studied with both ersatz solutions to provide addition performance capability of the VRA catalyst.

  6. Recommending the heterogeneous cluster type multi-processor system computing

    International Nuclear Information System (INIS)

    Real-time reactor simulator had been developed by reusing the equipment of the Musashi reactor and its performance improvement became indispensable for research tools to increase sampling rate with introduction of arithmetic units using multi-Digital Signal Processor(DSP) system (cluster). In order to realize the heterogeneous cluster type multi-processor system computing, combination of two kinds of Control Processor (CP) s, Cluster Control Processor (CCP) and System Control Processor (SCP), were proposed with Large System Control Processor (LSCP) for hierarchical cluster if needed. Faster computing performance of this system was well evaluated by simulation results for simultaneous execution of plural jobs and also pipeline processing between clusters, which showed the system led to effective use of existing system and enhancement of the cost performance. (T. Tanaka)

  7. Associative Memory Design for the Fast TracKer Processor (FTK)at ATLAS

    CERN Document Server

    Annovi, A; The ATLAS collaboration; Beretta, M; Bossini, E; Crescioli, F; Dell'Orso, M; Giannetti, P; Hoff, J; Liu, T; Liberali, V; Sacco, I; Schoening, A; Soltveit, H K; Stabile, A; Tripiccione, R

    2011-01-01

    We describe a VLSI processor for pattern recognition based on Content Addressable Memory (CAM) architecture, optimized for on-line track finding in high-energy physics experiments. A large CAM bank stores all trajectories of interest and extracts the ones compatible with a given event. This task is naturally parallelized by a CAM architecture able to output identified trajectories, recognized among a huge amount of possible combinations, in just a few 100 MHz clock cycles. We have developed this device (called the AMchip03 processor), using 180 nm technology, for the Silicon Vertex Trigger (SVT) upgrade at CDF [1] using a standard-cell VLSI design methodology. We propose a new design that introduces a full custom CAM cell and takes advantage of 65 nm technology. The customized design maximizes the pattern density, minimizes the power consumption and implements the functionalities needed for the planned Fast Tracker (FTK) [2], an ATLAS trigger upgrade project at LHC. We introduce a new variable resolution patt...

  8. Reconfigurable Very Long Instruction Word (VLIW) Processor

    Science.gov (United States)

    Velev, Miroslav N.

    2015-01-01

    Future NASA missions will depend on radiation-hardened, power-efficient processing systems-on-a-chip (SOCs) that consist of a range of processor cores custom tailored for space applications. Aries Design Automation, LLC, has developed a processing SOC that is optimized for software-defined radio (SDR) uses. The innovation implements the Institute of Electrical and Electronics Engineers (IEEE) RazorII voltage management technique, a microarchitectural mechanism that allows processor cores to self-monitor, self-analyze, and selfheal after timing errors, regardless of their cause (e.g., radiation; chip aging; variations in the voltage, frequency, temperature, or manufacturing process). This highly automated SOC can also execute legacy PowerPC 750 binary code instruction set architecture (ISA), which is used in the flight-control computers of many previous NASA space missions. In developing this innovation, Aries Design Automation has made significant contributions to the fields of formal verification of complex pipelined microprocessors and Boolean satisfiability (SAT) and has developed highly efficient electronic design automation tools that hold promise for future developments.

  9. RISC Processors and High Performance Computing

    Science.gov (United States)

    Saini, Subhash; Bailey, David H.; Lasinski, T. A. (Technical Monitor)

    1995-01-01

    In this tutorial, we will discuss top five current RISC microprocessors: The IBM Power2, which is used in the IBM RS6000/590 workstation and in the IBM SP2 parallel supercomputer, the DEC Alpha, which is in the DEC Alpha workstation and in the Cray T3D; the MIPS R8000, which is used in the SGI Power Challenge; the HP PA-RISC 7100, which is used in the HP 700 series workstations and in the Convex Exemplar; and the Cray proprietary processor, which is used in the new Cray J916. The architecture of these microprocessors will first be presented. The effective performance of these processors will then be compared, both by citing standard benchmarks and also in the context of implementing a real applications. In the process, different programming models such as data parallel (CM Fortran and HPF) and message passing (PVM and MPI) will be introduced and compared. The latest NAS Parallel Benchmark (NPB) absolute performance and performance per dollar figures will be presented. The next generation of the NP13 will also be described. The tutorial will conclude with a discussion of general trends in the field of high performance computing, including likely future developments in hardware and software technology, and the relative roles of vector supercomputers tightly coupled parallel computers, and clusters of workstations. This tutorial will provide a unique cross-machine comparison not available elsewhere.

  10. Graph-Based Dynamic Assignment Of Multiple Processors

    Science.gov (United States)

    Hayes, Paul J.; Andrews, Asa M.

    1994-01-01

    Algorithm-to-architecture mapping model (ATAMM) is strategy minimizing time needed to periodically execute graphically described, data-driven application algorithm on multiple data processors. Implemented as operating system managing flow of data and dynamically assigns nodes of graph to processors. Predicts throughput versus number of processors available to execute given application algorithm. Includes rules ensuring application algorithm represented by graph executed periodically without deadlock and in shortest possible repetition time. ATAMM proves useful in maximizing effectiveness of parallel computing systems.

  11. Cluster computing performances using virtual processors and mathematical software

    OpenAIRE

    Argentini, Gianluca

    2004-01-01

    In this paper I describe some results on the use of virtual processors technology for parallelize some SPMD computational programs in a cluster environment. The tested technology is the INTEL Hyper Threading on real processors, and the programs are MATLAB 6.5 Release 13 scripts for floating points computation. By the use of this technology, I tested that a cluster can run with benefit a number of concurrent processes double the amount of physical processors. The conclusions of the work concer...

  12. Efficiency of Parallel Processing in Multi-Core Processors

    OpenAIRE

    AZIMFAR, Seyed Javad

    2015-01-01

     Abstract. This paper evaluates efficiency in the parallelization of multi-core processors. Early  computer systems would work in series. With the aim of enhancing efficiency, processors were directed towards parallelization. This study evaluates parallelization efficiency at the level of multi-core processors, compares the efficiency and productivity of Super Scalar with Pipe line, Super Pipe line techniques, discusses parallelization techniques and examines challenges that may affect these ...

  13. Common Asthma Triggers

    Science.gov (United States)

    ... air pollution can trigger an asthma attack. This pollution can come from factories, cars, and other sources. Pay attention to air quality forecasts on radio, television, and the Internet and check your newspaper to plan ... levels will be low. Cockroach Allergen Cockroaches and ...

  14. The ALFA Trigger Simulator

    CERN Document Server

    Dziedzic B

    2015-01-01

    The paper presents basic information about ALFA detectors used in the ATLAS experiment, and the structure of currently developed device used to test a new ALFA trigger interface. It discusses the block diagram of the device, principle of its operation, implementation details and future plans for developing the Simulator.

  15. DZERO Level 3 DAQ/Trigger Closeout

    CERN Document Server

    CERN. Geneva

    2012-01-01

    The Tevatron Collider, located at the Fermi National Accelerator Laboratory, delivered its last 1.96 TeV proton-antiproton collisions on September 30th, 2011. The DZERO experiment continues to take cosmic data for final alignment for several more months . Since Run 2 started, in March 2001, all DZERO data has been collected by the DZERO Level 3 Trigger/DAQ System. The system is a modern, networked, commodity hardware trigger and data acquisition system based around a large central switch with about 60 front ends and 200 trigger computers. DZERO front end crates are VME based. Single Board Computer interfaces between detector data on VME and the network transport for the DAQ system. Event flow is controlled by the Routing Master which can steer events to clusters of farm nodes based on the low level trigger bits that fired. The farm nodes are multi-core commodity computer boxes, without special hardware, that run isolated software to make the final Level 3 trigger decision. Passed events are transferred to th...

  16. Compiler Optimization to Improve Data Locality for Processor Multithreading

    Directory of Open Access Journals (Sweden)

    Balaram Sinharoy

    1999-01-01

    Full Text Available Over the last decade processor speed has increased dramatically, whereas the speed of the memory subsystem improved at a modest rate. Due to the increase in the cache miss latency (in terms of the processor cycle, processors stall on cache misses for a significant portion of its execution time. Multithreaded processors has been proposed in the literature to reduce the processor stall time due to cache misses. Although multithreading improves processor utilization, it may also increase cache miss rates, because in a multithreaded processor multiple threads share the same cache, which effectively reduces the cache size available to each individual thread. Increased processor utilization and the increase in the cache miss rate demands higher memory bandwidth. A novel compiler optimization method has been presented in this paper that improves data locality for each of the threads and enhances data sharing among the threads. The method is based on loop transformation theory and optimizes both spatial and temporal data locality. The created threads exhibit high level of intra‐thread and inter‐thread data locality which effectively reduces both the data cache miss rates and the total execution time of numerically intensive computation running on a multithreaded processor.

  17. Performance evaluation of the JPL interim digital SAR processor

    Science.gov (United States)

    Wu, C.; Barkan, B.; Curlander, J.; Jin, M.; Pang, S.

    1983-01-01

    The performance of the Interim Digital SAR Processor (IDP) was evaluated. The IDP processor was originally developed for experimental processing of digital SEASAT SAR data. One phase of the system upgrade which features parallel processing in three peripheral array processors, automated estimation for Doppler parameters, and unsupervised image pixel location determination and registration was executed. The method to compensate for the target range curvature effect was improved. A four point interpolation scheme is implemented to replace the nearest neighbor scheme used in the original IDP. The processor still maintains its fast throughput speed. The current performance and capability of the processing modes now available on the IDP system are updated.

  18. Hash sorter - firmware implementation and an application for the Fermilab BTeV level 1 trigger system

    Energy Technology Data Exchange (ETDEWEB)

    Jinyuan Wu et al.

    2003-11-05

    A hardware hash sorter for the Fermilab BTeV Level 1 trigger system will be presented. The has sorter examines track-segment data before the data are sent to a system comprised of 2500 Level 1 processors, and rearranges the data into bins based on the slope of track segments. They have found that by using the rearranged data, processing time is significantly reduced allowing the total number of processors required for the Level 1 trigger system to be reduced. The hash sorter can be implemented in an FPGA that is already included as part of the design of the trigger system. Hash sorting has potential applications in a broad area in trigger and DAQ systems. It is a simple O(n) process and is suitable for FPGA implementation. Several implementation strategies will also be discussed in this document.

  19. Burst Memory and Event Trigger System for the Magnetospheric Multiscale Mission

    Science.gov (United States)

    Kletzing, C. A.; Ergun, R. E.; Torbert, R. B.; Burch, J. L.; Bounds, S. R.; Hesse, M.; Mauk, B.; Moore, T. E.; Young, D. T.

    2005-12-01

    To achieve the highest resolution measurement of the physics of magnetic reconnection, the MMS SMART measurements will utilize a high data rate burst storage system for capturing those intervals when the MMS spacecraft traverse important regions of interest. Two basic modes of data taking are planned, Slow Survey and Fast Survey. Fast Survey mode is targeted at the broad regions of the magnetosphere where reconnection can occur. Slow Survey is aimed an regions of secondary science importance. In Fast Survey, all instruments in the SMART suite continually send high rate data to the Central Instrument Data Processor (CIDP) which holds this data in a circular buffer. Along with this data, each instrument sends a burst data quality (BDQ) flag which represents the scientific "quality" of the preceding period for consideration as a burst interval. The CIDP on each spacecraft collects the individual BDQ's and combines them via a predetermined algorithm into a spacecraft data quality (SDQ) flag. Each spacecraft then sends its individual SDQ to the other three spacecraft via the Interspacecraft Ranging and Alarm System (IRAS). After a short latency period all four spacecraft have all four SDQ values and compute a mission data quality (MDQ) flag. If this flag is above the appropriate threshold then all spacecraft save identical data intervals from from the circular buffer for transmission to the ground during the next downlink. If This flexible scheme will yield optimized science data collection and allows the evolution of the burst data criteria as the best burst triggers are identified.

  20. Self-Triggered Control: trading actuation for computation

    CERN Document Server

    Mazo, Manuel; Tabuada, Paulo

    2009-01-01

    Event-triggered and self-triggered control have recently been proposed as alternatives to the well established periodic implementation of control loops on digital platforms. In a self-triggered implementation, the control task is responsible for computing the new actuator values as well as the next instant of time at which the state should be sampled, the control law recomputed, and the actuator values updated. In between these time instants, the system under control requires no attention and can operate in open loop. Self-triggered implementations can be seen as double edged swords: on the one hand, by using the state of the plant to determine when the control law needs to be recomputed, desired levels of control performance are enforced while drastically reducing the resources (processor time, communication bandwidth, etc) used for control; on the other hand, by operating the plant in open loop for extended periods of time, robustness of self-triggered implementations becomes an honest concern. In this pape...

  1. The Fast Tracker Real Time Processor

    CERN Document Server

    Annovi, A; The ATLAS collaboration

    2011-01-01

    As the LHC luminosity is ramped up to the SLHC Phase I level and beyond, the high rates, multiplicities, and energies of particles seen by the detectors will pose a unique challenge. Only a tiny fraction of the produced collisions can be stored on tape and immense real-time data reduction is needed. An effective trigger system must maintain high trigger efficiencies for the physics we are most interested in, and at the same time suppress the enormous QCD backgrounds. This requires massive computing power to minimize the online execution time of complex algorithms. A multi-level trigger is an effective solution for an otherwise impossible problem. The Fast Tracker (FTK)[1], is a proposed upgrade to the current ATLAS trigger system that will operate at full Level-1 output rates and provide high quality tracks reconstructed over the entire detector by the start of processing in Level-2. FTK solves the combinatorial challenge inherent to tracking by exploiting massive parallelism of associative memories [2] that ...

  2. Scalable Architecture for a Room Temperature Solid-State Quantum Information Processor

    CERN Document Server

    Yao, Norman Y; Gorshkov, Alexey V; Maurer, Peter C; Giedke, Geza; Cirac, J Ignacio; Lukin, Mikhail D

    2010-01-01

    The realization of a scalable quantum information processor has emerged over the past decade as one of the central challenges at the interface of fundamental science and engineering. Much progress has been made towards this goal. Indeed, quantum operations have been demonstrated on several trapped ion qubits, and other solid-state systems are approaching similar levels of control. Extending these techniques to achieve fault-tolerant operations in larger systems with more qubits remains an extremely challenging goal, in part, due to the substantial technical complexity of current implementations. Here, we propose and analyze an architecture for a scalable, solid-state quantum information processor capable of operating at or near room temperature. The architecture is applicable to realistic conditions, which include disorder and relevant decoherence mechanisms, and includes a hierarchy of control at successive length scales. Our approach is based upon recent experimental advances involving Nitrogen-Vacancy colo...

  3. A New Approach to Design of an Address Generation Unit in a DSP Processor

    Directory of Open Access Journals (Sweden)

    Kabiraj Sethi

    2011-11-01

    Full Text Available This paper presents the behavioral model of an Address Generation Unit (AGU in a DSP Processor whose instructions are almost compatible with the Motorola DSP56002. The proposed AGU unit can handle 4 different types of arithmetic – linear addressing, modulo addressing, wrap around modulo addressing and reverse carry addressing. It also handles various means of calculating addressesas post/pre increment/decrement by a number. The novelty in this proposal is that it can address 2 different memories, where 2 new addresses are calculated concurrently. The central idea behind thisdesign is address sequence generation by means of reverse carry addition, the use of modulo adder and offset adder. The designed AGU circuit generates the actual address as per the given set of inputs.Simulation results are compared with the theoretical data and found correct. The designed AGU may be implemented in a DSP Processor with optimized power and speed.

  4. Centralized digital control of accelerators

    Energy Technology Data Exchange (ETDEWEB)

    Melen, R.E.

    1983-09-01

    In contrasting the title of this paper with a second paper to be presented at this conference entitled Distributed Digital Control of Accelerators, a potential reader might be led to believe that this paper will focus on systems whose computing intelligence is centered in one or more computers in a centralized location. Instead, this paper will describe the architectural evolution of SLAC's computer based accelerator control systems with respect to the distribution of their intelligence. However, the use of the word centralized in the title is appropriate because these systems are based on the use of centralized large and computationally powerful processors that are typically supported by networks of smaller distributed processors.

  5. The data processor of the EUSO-Balloon experiment

    International Nuclear Information System (INIS)

    The JEM-EUSO instrument is a wide-angle refractive telescope in near-ultraviolet wavelength region being proposed for attachment to the Japanese Experiment Module (JEM) onboard International Space Station (ISS). The main scientific goal of the mission is the study of Extreme Energy Cosmic Rays (EECR) above 5 × 1019 eV. The instrument consists of high transmittance optical Fresnel lenses with a diameter of 2.5 m, a focal surface covered by ∼ 5000 Multi Anode Photo Multiplier Tubes of 64 pixels, front-end readout, trigger and system electronics. The EUSO-Balloon experiment is a pathfinder mission in which a telescope of smaller dimension than the one designed for the ISS will be mounted onboard a stratospheric balloon. The main objective of this pathfinder mission, planned for 2014, is to perform a full scale end-to-end test of all the key technologies and instrumentation of JEM-EUSO detectors and to prove the global detection chain. Furthermore, EUSO-Balloon will measure the atmospheric and terrestrial UV background components, in different observational modes, fundamental for the development of the simulations. Through a series of stratospheric balloon flights performed by the French Space Agency CNES, EUSO-Balloon also has the potential to detect Extensive Air Showers from above, paving the way for any future large scale, space-based EECR observatory. In this paper we will present the Data Processor (DP) of EUSO-Balloon, which is the component of the Electronics System which performs the data management and the instrument control. More in detail, the DP controls the front-end electronics, performs the 2nd level trigger filtering, tags events with arrival time and payload position through a GPS system, manages the Mass Memory for data storage, measures live and dead time of the telescope, provides signals for time synchronization of the event, performs housekeeping monitor, and handles the interface to the telemetry system. The DP has to operate at high altitude

  6. Vector and parallel processors in computational science

    International Nuclear Information System (INIS)

    This volume contains papers from most of the invited talks and from several of the contributed talks and poster sessions presented at VAPP II. The contents present an extensive coverage of all important aspects of vector and parallel processors, including hardware, languages, numerical algorithms and applications. The topics covered include descriptions of new machines (both research and commercial machines), languages and software aids, and general discussions of whole classes of machines and their uses. Numerical methods papers include Monte Carlo algorithms, iterative and direct methods for solving large systems, finite elements, optimization, random number generation and mathematical software. The specific applications covered include neutron diffusion calculations, molecular dynamics, weather forecasting, lattice gauge calculations, fluid dynamics, flight simulation, cartography, image processing and cryptography. Most machines and architecture types are being used for these applications. (orig.)

  7. Face feature processor on mobile service robot

    Science.gov (United States)

    Ahn, Ho Seok; Park, Myoung Soo; Na, Jin Hee; Choi, Jin Young

    2005-12-01

    In recent years, many mobile service robots have been developed. These robots are different from industrial robots. Service robots were confronted to unexpected changes in the human environment. So many capabilities were needed to service mobile robot, for example, the capability to recognize people's face and voice, the capability to understand people's conversation, and the capability to express the robot's thinking etc. This research considered face detection, face tracking and face recognition from continuous camera image. For face detection module, it used CBCH algorithm using openCV library from Intel Corporation. For face tracking module, it used the fuzzy controller to control the pan-tilt camera movement smoothly with face detection result. A PCA-FX, which adds class information to PCA, was used for face recognition module. These three procedures were called face feature processor, which were implemented on mobile service robot OMR to verify.

  8. Comparison of the Discriminatory Processor Sharing Policies

    CERN Document Server

    Osipova, Natalia

    2008-01-01

    Discriminatory Processor Sharing policy introduced by Kleinrock is of a great interest in many application areas, including telecommunications, web applications and TCP flow modelling. Under the DPS policy the job priority is controlled by the vector of weights. Verifying the vector of weights it is possible to modify the service rates of the jobs and optimize system characteristics. In the present paper we present the results concerning the comparison of two DPS policies with different weight vectors. We show the monotonicity of the expected sojourn time of the system depending on the weight vector under certain condition on the system. Namely, the system has to consist of classes with means which are quite different from each other. The classes with similar means can be organized together and considered as one class, so the given restriction can be overcame.

  9. Signal Processor for Spring8 Linac BPM

    CERN Document Server

    Yanagida, K; Dewa, H; Hanaki, H; Hori, T; Kobayashi, T; Mizuno, A; Sasaki, S; Suzuki, S; Takashima, T; Taniushi, T; Tomizawa, H

    2001-01-01

    A signal processor of the single shot BPM system consists of a narrow-band BPF unit, a detector unit, a P/H circuit, an S/H IC and a 16-bit ADC. The BPF unit extracts a pure 2856MHz RF signal component from a BPM and makes the pulse width longer than 100ns. The detector unit that includes a demodulating logarithmic amplifier is used to detect an S-band RF amplitude. A wide dynamic range of beam current has been achieved; 0.01 ~ 3.5nC for below 100ns input pulse width, or 0.06 ~ 20mA for above 100ns input pulse width. The maximum acquisition rate with a VME system has been achieved up to 1kHz.

  10. Efficient quantum walk on a quantum processor.

    Science.gov (United States)

    Qiang, Xiaogang; Loke, Thomas; Montanaro, Ashley; Aungskunsiri, Kanin; Zhou, Xiaoqi; O'Brien, Jeremy L; Wang, Jingbo B; Matthews, Jonathan C F

    2016-01-01

    The random walk formalism is used across a wide range of applications, from modelling share prices to predicting population genetics. Likewise, quantum walks have shown much potential as a framework for developing new quantum algorithms. Here we present explicit efficient quantum circuits for implementing continuous-time quantum walks on the circulant class of graphs. These circuits allow us to sample from the output probability distributions of quantum walks on circulant graphs efficiently. We also show that solving the same sampling problem for arbitrary circulant quantum circuits is intractable for a classical computer, assuming conjectures from computational complexity theory. This is a new link between continuous-time quantum walks and computational complexity theory and it indicates a family of tasks that could ultimately demonstrate quantum supremacy over classical computers. As a proof of principle, we experimentally implement the proposed quantum circuit on an example circulant graph using a two-qubit photonics quantum processor. PMID:27146471

  11. Automated Sequence Processor: Something Old, Something New

    Science.gov (United States)

    Streiffert, Barbara; Schrock, Mitchell; Fisher, Forest; Himes, Terry

    2012-01-01

    High productivity required for operations teams to meet schedules Risk must be minimized. Scripting used to automate processes. Scripts perform essential operations functions. Automated Sequence Processor (ASP) was a grass-roots task built to automate the command uplink process System engineering task for ASP revitalization organized. ASP is a set of approximately 200 scripts written in Perl, C Shell, AWK and other scripting languages.. ASP processes/checks/packages non-interactive commands automatically.. Non-interactive commands are guaranteed to be safe and have been checked by hardware or software simulators.. ASP checks that commands are non-interactive.. ASP processes the commands through a command. simulator and then packages them if there are no errors.. ASP must be active 24 hours/day, 7 days/week..

  12. Efficient quantum walk on a quantum processor

    Science.gov (United States)

    Qiang, Xiaogang; Loke, Thomas; Montanaro, Ashley; Aungskunsiri, Kanin; Zhou, Xiaoqi; O'Brien, Jeremy L.; Wang, Jingbo B.; Matthews, Jonathan C. F.

    2016-05-01

    The random walk formalism is used across a wide range of applications, from modelling share prices to predicting population genetics. Likewise, quantum walks have shown much potential as a framework for developing new quantum algorithms. Here we present explicit efficient quantum circuits for implementing continuous-time quantum walks on the circulant class of graphs. These circuits allow us to sample from the output probability distributions of quantum walks on circulant graphs efficiently. We also show that solving the same sampling problem for arbitrary circulant quantum circuits is intractable for a classical computer, assuming conjectures from computational complexity theory. This is a new link between continuous-time quantum walks and computational complexity theory and it indicates a family of tasks that could ultimately demonstrate quantum supremacy over classical computers. As a proof of principle, we experimentally implement the proposed quantum circuit on an example circulant graph using a two-qubit photonics quantum processor.

  13. The LPS trigger system

    International Nuclear Information System (INIS)

    The Leading Proton Spectrometer (LPS) has been equipped with microstrip silicon detectors specially designed to trigger events with high values of xLvertical stroke anti p'p vertical stroke / vertical stroke anti pp vertical stroke ≥0.95 where vertical stroke anti p'p vertical stroke and vertical stroke anti pp vertical stroke are respectively the momenta of outgoing and incoming protons. The LPS First Level Trigger can provide a clear tag for very high momentum protons in a kinematical region never explored before. In the following we discuss the physics motivation in tagging very forward protons and present a detailed description of the detector design, the front end electronics, the readout electronics, the Monte Carlo simulation and some preliminary results from 1995 data taking. (orig.)

  14. Patient triggered ventilation using a flow triggered system.

    OpenAIRE

    Hird, M F; Greenough, A

    1991-01-01

    The role of patient triggered ventilation (PTV) for the newborn was assessed using a new patient triggered ventilator, the Draeger Bablylog 8000, which incorporates significant improvements in both ventilator performance and the triggering system. Thirty three infants, median gestational age 30 weeks and postnatal age 2.5 days, were entered into the study to compare blood gases obtained during conventional and patient triggered ventilation. Oxygenation did not improve with PTV in the group ov...

  15. GLAST's GBM Burst Trigger

    Science.gov (United States)

    Band, D.; Briggs, M.; Connaughton, V.; Kippen, M.; Preece, R.

    2003-01-01

    The GLAST Burst Monitor (GBM) will detect and localize bursts for the GLAST mission, and provide the spectral and temporal context in the traditional 10 keV to 25 MeV band for the high energy observations by the Large Area Telescope (LAT). The GBM will use traditional rate triggers in up to three energy bands, and on a variety of timescales between 16 ms and 16 s.

  16. Neural networks for triggering

    Energy Technology Data Exchange (ETDEWEB)

    Denby, B. (Fermi National Accelerator Lab., Batavia, IL (USA)); Campbell, M. (Michigan Univ., Ann Arbor, MI (USA)); Bedeschi, F. (Istituto Nazionale di Fisica Nucleare, Pisa (Italy)); Chriss, N.; Bowers, C. (Chicago Univ., IL (USA)); Nesti, F. (Scuola Normale Superiore, Pisa (Italy))

    1990-01-01

    Two types of neural network beauty trigger architectures, based on identification of electrons in jets and recognition of secondary vertices, have been simulated in the environment of the Fermilab CDF experiment. The efficiencies for B's and rejection of background obtained are encouraging. If hardware tests are successful, the electron identification architecture will be tested in the 1991 run of CDF. 10 refs., 5 figs., 1 tab.

  17. Neural networks for triggering

    International Nuclear Information System (INIS)

    Two types of neural network beauty trigger architectures, based on identification of electrons in jets and recognition of secondary vertices, have been simulated in the environment of the Fermilab CDF experiment. The efficiencies for B's and rejection of background obtained are encouraging. If hardware tests are successful, the electron identification architecture will be tested in the 1991 run of CDF. 10 refs., 5 figs., 1 tab

  18. A trigger for beauty

    International Nuclear Information System (INIS)

    The possibility of B-meson experiments, in a fixed-target high-energy proton machine (Tevatron) is discussed. Compared to a B-meson factory experiment, it can produce 105, Banti B's per hour, using 108 protons per second, but it suffers from high background and needs high selectivity to cope with the million times higher interaction rate. To overcome these difficulties a technique called the 'optical trigger for beauty' is proposed, based on the detection of Cherenkov photons produced in a 2 mm thick LiF crystal, through a fast photodetector. Its virtue is that it is opaque to minimum-bias events originating in a small target, but sensitive to the high impact parameter B-meson decay charged particles from a secondary vertex. Calculations and first simulations results give a good efficiency for B-meson detection. A multistep trigger, combining the 'optical trigger' and a tracking detector, allows significant selection and a consequent enrichment of the data sample. Taking into account its fast response (∝ 1 ns), the above considerations can be extended to other hadronic machines, especially those with high-rate environments such as the LHC or SSC. (orig.)

  19. Control and diagnosis of the L3 energy Trigger

    International Nuclear Information System (INIS)

    An expert system is being developed for the control and the diagnosis of the L3 level-1 energy trigger, which is an hardware processor made of several hundred CAMAC modules. The system has been implemented through various tools, among which conventional programming languages and NEXPERT Object (Neuron Data) for a structural representation of the trigger circuit and forward and backward inferencing mechanism. Deep reasoning and euristic rules are combined in the diagnostic process, which consists in spanning different levels of description to progressively reduce the search space and possibly making hypotheses about the causes of malfunctioning. In the verification phase, a fault generation mechanism is activated to locally produce, according to the hypotheses made, each possible misbehaviour, whose effects are propagated through detailed simulation of the hardware behaviour. The system has been tested with simulated data: soon it will be put to the test in the real environment

  20. Designing a dataflow processor using CλaSH

    NARCIS (Netherlands)

    Niedermeier, Anja; Wester, Rinse; Rovers, Kenneth; Baaij, Christiaan; Kuper, Jan; Smit, Gerard

    2010-01-01

    In this paper we show how a simple dataflow processor can be fully implemented using CλaSH, a high level HDL based on the functional programming language Haskell. The processor was described using Haskell, the CλaSH compiler was then used to translate the design into a fully synthesisable VHDL code.

  1. Soft-core processor study for node-based architectures.

    Energy Technology Data Exchange (ETDEWEB)

    Van Houten, Jonathan Roger; Jarosz, Jason P.; Welch, Benjamin James; Gallegos, Daniel E.; Learn, Mark Walter

    2008-09-01

    Node-based architecture (NBA) designs for future satellite projects hold the promise of decreasing system development time and costs, size, weight, and power and positioning the laboratory to address other emerging mission opportunities quickly. Reconfigurable Field Programmable Gate Array (FPGA) based modules will comprise the core of several of the NBA nodes. Microprocessing capabilities will be necessary with varying degrees of mission-specific performance requirements on these nodes. To enable the flexibility of these reconfigurable nodes, it is advantageous to incorporate the microprocessor into the FPGA itself, either as a hardcore processor built into the FPGA or as a soft-core processor built out of FPGA elements. This document describes the evaluation of three reconfigurable FPGA based processors for use in future NBA systems--two soft cores (MicroBlaze and non-fault-tolerant LEON) and one hard core (PowerPC 405). Two standard performance benchmark applications were developed for each processor. The first, Dhrystone, is a fixed-point operation metric. The second, Whetstone, is a floating-point operation metric. Several trials were run at varying code locations, loop counts, processor speeds, and cache configurations. FPGA resource utilization was recorded for each configuration. Cache configurations impacted the results greatly; for optimal processor efficiency it is necessary to enable caches on the processors. Processor caches carry a penalty; cache error mitigation is necessary when operating in a radiation environment.

  2. Design of Cache Controller for Multi-core Processor System

    Directory of Open Access Journals (Sweden)

    Vipin S. Bhure

    2012-03-01

    Full Text Available To meet the growing needs of computing power, communication speed and performance requirements demanded by today’s applications, processor clock speed has to be increased. However, increasing clock speed is not viable due to heat dissipation and power consumption constraints. Hence Instead of trying to increase the clock speed, multi-core processor architectures with the lower frequency can be used. A multi-core processor is a single integrated circuit in which two or more processors have been attached for enhanced performance, reduced power consumption and more efficient simultaneous processing of multipletasks. Multi-core processors, which have multiple processing units on a single chip, are widely viewed as a way to achieve higher processor performance. Well scheduling of running threads on these processors will result in achieving higher performance. Modern multi-core systems are designed to allow clusters of cores to share various hardware structures, such as last-level caches, memory controllers, and interconnections without considering these shared resources, scheduling the threads will cause serious degradation in overall performance of the system. In this paper we are showing one basic problem in multicore processor. The simulation results showed that the requirement of scheduler or cache-controller to avoid lot of problems that come in to the existence during shared caches memory shared by many cores located on single chip as well as the simple solution on it with simulation result

  3. Evaluation of the Intel Sandy Bridge-EP server processor

    CERN Document Server

    Jarp, S; Leduc, J; Nowak, A; CERN. Geneva. IT Department

    2012-01-01

    In this paper we report on a set of benchmark results recently obtained by CERN openlab when comparing an 8-core “Sandy Bridge-EP” processor with Intel’s previous microarchitecture, the “Westmere-EP”. The Intel marketing names for these processors are “Xeon E5-2600 processor series” and “Xeon 5600 processor series”, respectively. Both processors are produced in a 32nm process, and both platforms are dual-socket servers. Multiple benchmarks were used to get a good understanding of the performance of the new processor. We used both industry-standard benchmarks, such as SPEC2006, and specific High Energy Physics benchmarks, representing both simulation of physics detectors and data analysis of physics events. Before summarizing the results we must stress the fact that benchmarking of modern processors is a very complex affair. One has to control (at least) the following features: processor frequency, overclocking via Turbo mode, the number of physical cores in use, the use of logical cores ...

  4. ACP/R3000 processors in data acquisition systems

    International Nuclear Information System (INIS)

    We describe ACP/R3000 processor based data acquisition systems for high energy physics. This VME bus compatible processor board, with a computational power equivalent to 15 VAX 11/780s or better, contains 8 Mb of memory for event buffering and has a high speed secondary bus that allows data gathering from front end electronics. 2 refs., 3 figs

  5. Digital image processing software system using an array processor

    International Nuclear Information System (INIS)

    A versatile array processor-based system for general-purpose image processing was developed. At the heart of this system is an extensive, flexible software package that incorporates the array processor for effective interactive image processing. The software system is described in detail, and its application to a diverse set of applications at LLNL is briefly discussed. 4 figures, 1 table

  6. A Simple and Affordable TTL Processor for the Classroom

    Science.gov (United States)

    Feinberg, Dave

    2007-01-01

    This paper presents a simple 4 bit computer processor design that may be built using TTL chips for less than $65. In addition to describing the processor itself in detail, we discuss our experience using the laboratory kit and its associated machine instruction set to teach computer architecture to high school students. (Contains 3 figures and 5…

  7. Temporal Partitioning and Multi-Processor Scheduling for Reconfigurable Architectures

    DEFF Research Database (Denmark)

    Popp, Andreas; Le Moullec, Yannick; Koch, Peter

    This poster presentation outlines a proposed framework for handling mapping of signal processing applications to heterogeneous reconfigurable architectures. The methodology consists of an extension to traditional multi-processor scheduling by creating a separate HW track for generation of groups of...... tasks that are handled similarly to SW processes in a traditional multi-processor scheduling context....

  8. Digital Signal Processor System for AC Power Drivers

    Directory of Open Access Journals (Sweden)

    Ovidiu Neamtu

    2009-10-01

    Full Text Available DSP (Digital Signal Processor is the bestsolution for motor control systems to make possible thedevelopment of advanced motor drive systems. The motorcontrol processor calculates the required motor windingvoltage magnitude and frequency to operate the motor atthe desired speed. A PWM (Pulse Width Modulationcircuit controls the on and off duty cycle of the powerinverter switches to vary the magnitude of the motorvoltages.

  9. 7 CFR 1435.310 - Sharing processors' allocations with producers.

    Science.gov (United States)

    2010-01-01

    ... processors upon their request for growers delivering to their mill. In the case of multiple producers on a... subject to appeal to the Office of the Administrative Law Judge, USDA. ... proportionate share data. (e) Any producer or processor may request arbitration of a dispute regarding...

  10. Optoelectronic correlation processors with photorefractive crystals for the storage elements

    Directory of Open Access Journals (Sweden)

    Lipinskii A. Y.

    2011-12-01

    Full Text Available The paper presents review of optical and acousto-optic correlation processors that contain photorefractive crystals. Optical correlators are the efficient devices for the image recognition due to the parallel way high operation rate processing of significant data amount. The shift-invariant holographic joint-transform correlators, dynamic holographic correlator, acousto-optic correlation processors with memory were considered.

  11. Optoelectronic correlation processors with photorefractive crystals for the storage elements

    OpenAIRE

    Lipinskii A. Y.; Rudiakova A. N.; Danilov V. V.

    2011-01-01

    The paper presents review of optical and acousto-optic correlation processors that contain photorefractive crystals. Optical correlators are the efficient devices for the image recognition due to the parallel way high operation rate processing of significant data amount. The shift-invariant holographic joint-transform correlators, dynamic holographic correlator, acousto-optic correlation processors with memory were considered.

  12. The second level trigger of the L3 experiment. Pt. 1

    International Nuclear Information System (INIS)

    The second level trigger of the L3 experiment performs online background rejection and reduces the first level trigger rate to a value fitting with the third level trigger processing capability. Designed around a set of three bit-slice XOP microprocessors, it can process up to 500 first level triggers per second without significant dead time in the data acquisition. At each LEP beam crossing (45/90 kHz) the complete trigger information (5 kbytes) is memorized in a 1.4 gigabyte bandwidth real dual port memory. The XOP processor builds up the trigger block in less than 400 μs, and signs the background or physics origin of the current event in less than 3 ms. These very high performances rely essentially on the association of parallelism with high speed ECL technology, provided by dedicated processors fully integrated in Fastbus. Emphasis is given here to the specific hardware developed, to its operation and technical aspects of its installation and integration. The system described here ensures the L3 data taking since the beginning of LEP in July 1989 and the online rejection since 1990. (orig.)

  13. A time-multiplexed track-trigger for the CMS HL-LHC upgrade

    Science.gov (United States)

    Hall, G.

    2016-07-01

    A new CMS Tracker is under development for operation at the High Luminosity LHC from 2025. It includes an outer tracker based on special modules of two different types which will construct track stubs using spatially coincident clusters in two closely spaced sensor layers, to reject low transverse momentum track hits and reduce the data volume before data transmission to the Level-1 trigger. The tracker data will be used to reconstruct track segments in dedicated processors before onward transmission to other trigger processors which will combine tracker information with data originating from the calorimeter and muon detectors, to make the final L1 trigger decision. The architecture for processing the tracker data outside the detector is under study, using several alternative approaches. One attractive possibility is to exploit a Time Multiplexed design similar to the one which is currently being implemented in the CMS calorimeter trigger as part of the Phase I trigger upgrade. The novel Time Multiplexed Trigger concept is explained, the potential benefits for processing future tracker data are described and a feasible design based on currently existing hardware is outlined.

  14. Isolating Triggered Star Formation

    Energy Technology Data Exchange (ETDEWEB)

    Barton, Elizabeth J.; Arnold, Jacob A.; /UC, Irvine; Zentner, Andrew R.; /KICP, Chicago /Chicago U., EFI; Bullock, James S.; /UC, Irvine; Wechsler, Risa H.; /KIPAC, Menlo

    2007-09-12

    Galaxy pairs provide a potentially powerful means of studying triggered star formation from galaxy interactions. We use a large cosmological N-body simulation coupled with a well-tested semi-analytic substructure model to demonstrate that the majority of galaxies in close pairs reside within cluster or group-size halos and therefore represent a biased population, poorly suited for direct comparison to 'field' galaxies. Thus, the frequent observation that some types of galaxies in pairs have redder colors than 'field' galaxies is primarily a selection effect. We use our simulations to devise a means to select galaxy pairs that are isolated in their dark matter halos with respect to other massive subhalos (N= 2 halos) and to select a control sample of isolated galaxies (N= 1 halos) for comparison. We then apply these selection criteria to a volume-limited subset of the 2dF Galaxy Redshift Survey with M{sub B,j} {le} -19 and obtain the first clean measure of the typical fraction of galaxies affected by triggered star formation and the average elevation in the star formation rate. We find that 24% (30.5 %) of these L* and sub-L* galaxies in isolated 50 (30) h{sup -1} kpc pairs exhibit star formation that is boosted by a factor of {approx}> 5 above their average past value, while only 10% of isolated galaxies in the control sample show this level of enhancement. Thus, 14% (20 %) of the galaxies in these close pairs show clear triggered star formation. Our orbit models suggest that 12% (16%) of 50 (30) h{sup -1} kpc close pairs that are isolated according to our definition have had a close ({le} 30 h{sup -1} kpc) pass within the last Gyr. Thus, the data are broadly consistent with a scenario in which most or all close passes of isolated pairs result in triggered star formation. The isolation criteria we develop provide a means to constrain star formation and feedback prescriptions in hydrodynamic simulations and a very general method of understanding

  15. Simulation of a processor switching circuit with APLSV

    International Nuclear Information System (INIS)

    The report describes the simulation of a processor switching circuit with APL. Furthermore an APL function is represented to simulate a processor in an assembly like language. Both together serve as a tool for studying processor properties. By means of the programming function it is also possible to program other simulated processors. The processor is to be used in the processing of data in real time analysis that occur in high energy physics experiments. The data are already offered to the computer in digitalized form. A typical data rate is at 10 KB/ sec. The data are structured in blocks. The particular blocks are 1 KB wide and are independent from each other. Aprocessor has to decide, whether the block data belong to an event that is part of the backround noise and can therefore be forgotten, or whether the data should be saved for a later evaluation. (orig./WB)

  16. An Efficient Graph-Coloring Algorithm for Processor Allocation

    Directory of Open Access Journals (Sweden)

    Mohammed Hasan Mahafzah

    2013-06-01

    Full Text Available This paper develops an efficient exact graph-coloring algorithm based on Maximum Independent Set (MIS for allocating processors in distributed systems. This technique represents the allocated processors in specific time in a fully connected graph and prevents each processor in multiprocessor system to be assigned to more than one process at a time. This research uses a sequential technique to distribute processes among processors. Moreover, the proposed method has been constructed by modifying the FMIS algorithm. The proposed algorithm has been programmed in Visual C++ and implemented on an Intel core i7. The experiments show that the proposed algorithm gets better performance in terms of CPU utilization, and minimum time for of graph coloring, comparing with the latest FMIS algorithm. The proposed algorithm can be developed to detect defected processor in the system.

  17. PERFORMANCE EVALUATION OF DIRECT PROCESSOR ACCESS FOR NON DEDICATED SERVER

    Directory of Open Access Journals (Sweden)

    P. S. BALAMURUGAN

    2010-10-01

    Full Text Available The objective of the paper is to design a co processor for a desktop machine which enables the machine to act as non dedicated server, such that the co processor will act as a server processor and the multi-core processor to act as desktop processor. By implementing this methodology a client machine can be made to act as a non dedicated server and a client machine. These type of machine can be used in autonomy networks. This design will lead to design of a cost effective server and machine which can parallel act as a non dedicated server and a client machine or it can be made to switch and act as client or server.

  18. Explore the Performance of the ARM Processor Using JPEG

    Directory of Open Access Journals (Sweden)

    A.D. Jadhav

    2010-01-01

    Full Text Available Recently, the evolution of embedded systems has shown a strong trend towards application- specific, single- chip solutions. The ARM processor core is a leading RISC processor architecture in the embedded domain. The ARM family of processors supports a unique feature of code size reduction. In this paper it is illustrated using an embedded platform trying to design an image encoder, more specifically a JPEG encoder using ARM7TDMI processor. Here gray scale image is used and it is coded by using keil software and same procedure is repeated by using MATLAB software for compare the results with standard one. Successfully putting a new application of JPEG on ARM7 processor.

  19. MPC Related Computational Capabilities of ARMv7A Processors

    DEFF Research Database (Denmark)

    Frison, Gianluca; Jørgensen, John Bagterp

    2015-01-01

    In recent years, the mass market of mobile devices has pushed the demand for increasingly fast but cheap processors. ARM, the world leader in this sector, has developed the Cortex-A series of processors with focus on computationally intensive applications. If properly programmed, these processors...... are powerful enough to solve the complex optimization problems arising in MPC in real-time, while keeping the traditional low-cost and low-power consumption. This makes these processors ideal candidates for use in embedded MPC. In this paper, we investigate the floating-point capabilities of Cortex A7......, A9 and A15 and show how to exploit the unique features of each processor to obtain the best performance, in the context of a novel implementation method for the linear-algebra routines used in MPC solvers. This method adapts high-performance computing techniques to the needs of embedded MPC. In...

  20. APRON: A Cellular Processor Array Simulation and Hardware Design Tool

    Directory of Open Access Journals (Sweden)

    David R. W. Barr

    2009-01-01

    Full Text Available We present a software environment for the efficient simulation of cellular processor arrays (CPAs. This software (APRON is used to explore algorithms that are designed for massively parallel fine-grained processor arrays, topographic multilayer neural networks, vision chips with SIMD processor arrays, and related architectures. The software uses a highly optimised core combined with a flexible compiler to provide the user with tools for the design of new processor array hardware architectures and the emulation of existing devices. We present performance benchmarks for the software processor array implemented on standard commodity microprocessors. APRON can be configured to use additional processing hardware if necessary and can be used as a complete graphical user interface and development environment for new or existing CPA systems, allowing more users to develop algorithms for CPA systems.

  1. Testing and calibrating analogue inputs to the ATLAS Level-1 Calorimeter Trigger

    CERN Document Server

    Achenbach, R; Aharrouche, M; Andrei, V; Åsman, B; Barnett, B M; Bauss, B; Bendel, M; Bohm, C; Booth, J R A; Bracinik, J; Brawn, I P; Charlton, D G; Childers, J T; Collins, N J; Curtis, C J; Davis, A O; Eckweiler, S; Eisenhandler, E F; Faulkner, P J W; Fleckner, J; Föhlisch, F; Gee, C N P; Gillman, A R; Goringer, C; Groll, M; Hadley, D R; Hanke, P; Hellman, S; Hidvegi, A; Hillier, S J; Johansen, M; Kluge, E E; Kühl, T; Landon, M; Lendermann, V; Lilley, J N; Mahboubi, K; Mahout, G; Meier, K; Middleton, R P; Moa, T; Morris, J D; Müller, F; Neusiedl, A; Ohm, C; Oltmann, B; Perera, V J O; Prieur, D P F; Qian, W; Rieke, S; Rühr, F; Sankey, D P C; Schäfer, U; Schmitt, K; Schultz-Coulon, H C; Seidler, P; Silverstein, S; Sjölin, J; Staley, R J; Stamen, R; Stockton, M C; Tan, C L A; Tapprogge, S; Thomas, J P; Thompson, P D; Watkins, P M; Watson, A; Weber, P; Wessels, M; Wildt, M

    2008-01-01

    The ATLAS Level-1 Calorimeter Trigger is a hardwarebased system which aims to identify objects with high transverse momentum within an overall latency of 2.5 μs. It is composed of a PreProcessor system (PPr) which digitises 7200 analogue input channels, determines the bunch crossing of the interaction, applies a digital noise filter, and provides a fine calibration; and two subsequent digital processors. The PreProcessor system needs various channel dependent parameters to be set in order to provide digital signals which are aligned in time and have proper energy calibration. The different techniques which are used to derive these parameters are described along with the quality tests of the analogue input signals.

  2. Launching applications on compute and service processors running under different operating systems in scalable network of processor boards with routers

    Science.gov (United States)

    Tomkins, James L.; Camp, William J.

    2009-03-17

    A multiple processor computing apparatus includes a physical interconnect structure that is flexibly configurable to support selective segregation of classified and unclassified users. The physical interconnect structure also permits easy physical scalability of the computing apparatus. The computing apparatus can include an emulator which permits applications from the same job to be launched on processors that use different operating systems.

  3. Insight into the physics of rupture: Dynamic triggering seismicity

    Science.gov (United States)

    Gonzalez-Huizar, Hector

    2009-12-01

    Seismic waves can trigger earthquakes and tremor at large distances from the causable event. Dynamic triggering occurs when the surface waves from large earthquakes change the stresses conditions on previously overstressed faults, promoting failure. To understand the causative stresses and environments behind dynamic triggering, we model the change in the stress field that the passing of Rayleigh and Love waves cause on a fault plane of arbitrary orientation relative to the direction of propagation of the waves, and apply a Coulomb failure criterion to calculate the potential of these stress changes to trigger seismicity. We apply our model to three different study regions and compare with observations. In the first case, we compare our model results with data from dynamically triggered earthquakes in the Australian Bowen Basin, Our data analysis shows that for this region, surface waves arriving at 45 degrees from the average local stress field are the most likely to trigger local seismicity. This agrees with our observations. In the second study case, we show how the same model can be applied to dynamic triggering of Non-volcanic tremor (NVT). Our modeling predicts the potential of a seismic wave to trigger slip on a fault plane promoting NVT. We search for tremor in the Central Range in Taiwan triggered by surfaces waves and compare the observations with our modeling. In the last study case, we present our modeling of the dynamic stress that triggered two events in Utah, one triggered by the 1992 Landers earthquake and the other by the 2002 Denali Fault earthquake. We show how dynamic stress modeling can be used to discriminate between the two axial planes of a first motion focal mechanism of a dynamically triggered event.

  4. Triggering filamentation using turbulence

    CERN Document Server

    Eeltink, D; Marchiando, N; Hermelin, S; Gateau, J; Brunetti, M; Wolf, J P; Kasparian, J

    2016-01-01

    We study the triggering of single filaments due to turbulence in the beam path for a laser of power below the filamenting threshold. Turbulence can act as a switch between the beam not filamenting and producing single filaments. This 'positive' effect of turbulence on the filament probability, combined with our observation of off-axis filaments suggests the underlying mechanism is modulation instability caused by transverse perturbations. We hereby experimentally explore the interaction of modulation instability and turbulence, commonly associated with multiple-filaments, in the single-filament regime.

  5. ALMA Correlator Real-Time Data Processor

    Science.gov (United States)

    Pisano, J.; Amestica, R.; Perez, J.

    2005-10-01

    The design of a real-time Linux application utilizing Real-Time Application Interface (RTAI) to process real-time data from the radio astronomy correlator for the Atacama Large Millimeter Array (ALMA) is described. The correlator is a custom-built digital signal processor which computes the cross-correlation function of two digitized signal streams. ALMA will have 64 antennas with 2080 signal streams each with a sample rate of 4 giga-samples per second. The correlator's aggregate data output will be 1 gigabyte per second. The software is defined by hard deadlines with high input and processing data rates, while requiring interfaces to non real-time external computers. The designed computer system - the Correlator Data Processor or CDP, consists of a cluster of 17 SMP computers, 16 of which are compute nodes plus a master controller node all running real-time Linux kernels. Each compute node uses an RTAI kernel module to interface to a 32-bit parallel interface which accepts raw data at 64 megabytes per second in 1 megabyte chunks every 16 milliseconds. These data are transferred to tasks running on multiple CPUs in hard real-time using RTAI's LXRT facility to perform quantization corrections, data windowing, FFTs, and phase corrections for a processing rate of approximately 1 GFLOPS. Highly accurate timing signals are distributed to all seventeen computer nodes in order to synchronize them to other time-dependent devices in the observatory array. RTAI kernel tasks interface to the timing signals providing sub-millisecond timing resolution. The CDP interfaces, via the master node, to other computer systems on an external intra-net for command and control, data storage, and further data (image) processing. The master node accesses these external systems utilizing ALMA Common Software (ACS), a CORBA-based client-server software infrastructure providing logging, monitoring, data delivery, and intra-computer function invocation. The software is being developed in tandem

  6. Initial experience with the CDF SVT trigger

    CERN Document Server

    Ashmanskas, B; Bardi, A; Bari, M; Baumgart, M; Belforte, S; Berryhill, J W; Bogdan, M; Carosi, R; Cerri, A; Chlachidze, G; Culberston, R; Dell'Orso, Mauro; Donati, S; Fiori, I; Frisch, H; Galeotti, S; Giannetti, P; Glagolev, V; Léger, A; Liu, Y; Meschi, E; Moneta, L; Morsani, F; Nakaya, T; Punzi, G; Rescigno, M; Ristori, L; Sanders, H; Sarkar, S; Semenov, A; Shochet, M; Speer, T; Spinella, F; Vataga, H; Wu, X; Yang, U; Zanello, L; Zanetti, A M

    2003-01-01

    The Collider Detector at Fermilab (CDF) Silicon Vertex Tracker (SVT) is a device that works inside the CDF Level 2 trigger to find and fit tracks in real time using the central silicon vertex detector information. SVT starts from tracks found by the Level 1 central chamber fast trigger and adds the silicon information to compute transverse track parameters with offline quality in about 15 mu s. The CDF SVT is fully installed and functional and has been exercised with real data during the spring and summer 2001. It is a complex digital device of more than 100 VME boards that performs a dramatic data reduction (only about one event in a thousand is accepted by the trigger). Diagnosing rare failures poses a special challenge and SVT internal data flow is monitored by dedicated hardware and software. This paper briefly covers the SVT architecture and design and reports on the SVT building/commissioning experience (hardware and software) and on the first results from the initial running.

  7. Initial experience with the CDF SVT trigger

    Energy Technology Data Exchange (ETDEWEB)

    Ashmanskas, B.; Barchiesi, A.; Bardi, A.; Bari, M.; Baumgart, M.; Belforte, Stefano E-mail: belforte@fnal.gov; Berryhill, J.; Bogdan, M.; Carosi, R.; Cerri, A.; Chlachidze, G.; Culberston, R.; Dell' Orso, M.; Donati, S.; Fiori, I.; Frisch, H.; Galeotti, S.; Giannetti, P.; Glagolev, V.; Leger, A.; Liu, Y.; Meschi, E.; Moneta, L.; Morsani, F.; Nakaya, T.; Punzi, G.; Rescigno, M.; Ristori, L.; Sanders, H.; Sarkar, S.; Semenov, A.; Shochet, M.; Speer, T.; Spinella, F.; Vataga, H.; Wu, X.; Yang, U.; Zanello, L.; Zanetti, A.M

    2003-03-21

    The Collider Detector at Fermilab (CDF) Silicon Vertex Tracker (SVT) is a device that works inside the CDF Level 2 trigger to find and fit tracks in real time using the central silicon vertex detector information. SVT starts from tracks found by the Level 1 central chamber fast trigger and adds the silicon information to compute transverse track parameters with offline quality in about 15 {mu}s. The CDF SVT is fully installed and functional and has been exercised with real data during the spring and summer 2001. It is a complex digital device of more than 100 VME boards that performs a dramatic data reduction (only about one event in a thousand is accepted by the trigger). Diagnosing rare failures poses a special challenge and SVT internal data flow is monitored by dedicated hardware and software. This paper briefly covers the SVT architecture and design and reports on the SVT building/commissioning experience (hardware and software) and on the first results from the initial running.

  8. Initial experience with the CDF SVT trigger

    International Nuclear Information System (INIS)

    The Collider Detector at Fermilab (CDF) Silicon Vertex Tracker (SVT) is a device that works inside the CDF Level 2 trigger to find and fit tracks in real time using the central silicon vertex detector information. SVT starts from tracks found by the Level 1 central chamber fast trigger and adds the silicon information to compute transverse track parameters with offline quality in about 15 μs. The CDF SVT is fully installed and functional and has been exercised with real data during the spring and summer 2001. It is a complex digital device of more than 100 VME boards that performs a dramatic data reduction (only about one event in a thousand is accepted by the trigger). Diagnosing rare failures poses a special challenge and SVT internal data flow is monitored by dedicated hardware and software. This paper briefly covers the SVT architecture and design and reports on the SVT building/commissioning experience (hardware and software) and on the first results from the initial running

  9. Resource efficiency of hardware extensions of a 4-issue VLIW processor for elliptic curve cryptography

    Science.gov (United States)

    Jungeblut, T.; Puttmann, C.; Dreesen, R.; Porrmann, M.; Thies, M.; Rückert, U.; Kastens, U.

    2010-12-01

    The secure transmission of data plays a significant role in today's information era. Especially in the area of public-key-cryptography methods, which are based on elliptic curves (ECC), gain more and more importance. Compared to asymmetric algorithms, like RSA, ECC can be used with shorter key lengths, while achieving an equal level of security. The performance of ECC-algorithms can be increased significantly by adding application specific hardware extensions. Due to their fine grained parallelism, VLIW-processors are well suited for the execution of ECC algorithms. In this work, we extended the fourfold parallel CoreVA-VLIW-architecture by several hardware accelerators to increase the resource efficiency of the overall system. For the design-space exploration we use a dual design flow, which is based on the automatic generation of a complete C-compiler based tool chain from a central processor specification. Using the hardware accelerators the performance of the scalar multiplication on binary fields can be increased by the factor of 29. The energy consumption can be reduced by up to 90%. The extended processor hardware was mapped on a current 65 nm low-power standard-cell-technology. The chip area of the CoreVA-VLIW-architecture is 0.24 mm2 at a power consumption of 29 mW/MHz. The performance gain is analyzed in respect to the increased hardware costs, as chip area or power consumption.

  10. Factors Affecting Women’s Capacities as Traditional Sago Starch Processors in Maluku, Indonesia

    Directory of Open Access Journals (Sweden)

    Inta P.N. Damanik

    2013-04-01

    Full Text Available The objectives of this research were to describe the capacity level of women as traditional sago starch processors and to analyze factors which affected women’s capacity in processing sago starch as traditional home industry. Research was conduct in the Districts of Central Maluku and West Seram involved 204 households of sago starch processing as respondents which determined from population (416 households by Slovin formula with degree of error 5% and drawn by simple random sampling method. Data collection was undertaken in January until April 2012. Data were analyzed using Statistical Package for the Social Science (SPSS v.20. Result showed that characteristics of social economic of traditional sago starch processor (namely age, length of time in business, informal education, motivation, family size, and individual beliefs about the social and cultural values of sago and support from institution of agriculture extension affected personal capacity. Personal capacity affected business capacity and in the next term business capacity affected productivity. Increasing productivity will increase income. This means that the sago starch processors with higher personal capacity will do better in business.

  11. Multiple DAG Applications Scheduling on a Cluster of Processors

    Directory of Open Access Journals (Sweden)

    Uma Boregowda

    2014-03-01

    Full Text Available Many computational solutions can be expressed as Di rected Acyclic Graph (DAG, in which nodes represent tasks to be executed and edges repr esent precedence constraints among tasks. A Cluster of processors is a shared resource among several users and hence the need for a scheduler which deals with multi-user jobs presente d as DAGs. The scheduler must find the number of processors to be allotted for each DAG an d schedule tasks on allotted processors. In this work, a new method to find optimal and maximum number of processors that can be allotted for a DAG is proposed. Regression analysis is used to find the best possible way to share available processors, among suitable number of subm itted DAGs. An instance of a scheduler for each DAG, schedules tasks on the allotted proce ssors. Towards this end, a new framework to receive online submission of DAGs, allot process ors to each DAG and schedule tasks, is proposed and experimented using a simulator. This s pace-sharing of processors among multiple DAGs shows better performance than the other method s found in literature. Because of space- sharing, an online scheduler can be used for each D AG within the allotted processors. The use of online scheduler overcomes the drawbacks of stat ic scheduling which relies on inaccurate estimated computation and communication costs. Thus the proposed framework is a promising solution to perform online scheduling of tasks usin g static information of DAG, a kind of hybrid scheduling .

  12. The selective read-out processor for the CMS electromagnetic calorimeter

    CERN Document Server

    Girão de Almeida, Nuño Miguel; Faure, Jean Louis; Gachelin, Olivier; Gras, Philippe; Mandjavidze, Irakli; Mur, Michel; Varela, João

    2005-01-01

    This paper describes the selective read-out processor (SRP) proposed for the electromagnetic calorimeter (ECAL) of the Compact Muon Solenoid (CMS) experiment at LHC (CERN). The aim is to reduce raw ECAL data to a level acceptable by the CMS data acquisition (DAQ) system. For each positive level 1 trigger, the SRP is guided by trigger primitive generation electronics to identify ECAL regions with energy deposition satisfying certain programmable criteria. It then directs the ECAL read-out electronics to apply predefined zero suppression levels to the crystal data, depending whether the crystals fall within these regions or not. The main challenges for the SRP are some 200 high speed (1.6 Gbit/s) I/O channels, asynchronous operation at up to 100 kHz level 1 trigger rate, a 5- mu s real-time latency requirement and a need to retain flexibility in choice of selection algorithms. The architecture adopted for the SRP is based on modern parallel optic pluggable modules and high density field programmable gate array ...

  13. ATLAS Tau Trigger

    CERN Document Server

    Belanger-Champagne, C; Bosman, M; Brenner, R; Casado, MP; Czyczula, Z; Dam, M; Demers, S; Farrington, S; Igonkina, O; Kalinowski, A; Kanaya, N; Osuna, C; Pérez, E; Ptacek, E; Reinsch, A; Saavedra, A; Sopczak, A; Strom, D; Torrence, E; Tsuno, S; Vorwerk, V; Watson, A; Xella, S

    2008-01-01

    Moving to the high energy scale of the LHC, the identification of tau leptons will become a necessary and very powerful tool, allowing a discovery of physics beyond Standard Model. Many models, among them light SM Higgs and various SUSY models, predict an abundant production of taus with respect to other leptons. The reconstruction of hadronic tau decays, although a very challenging task in hadronic enviroments, allows to increase a signal efficiency by at least of factor 2, and provides an independent control sample to disantangle lepton tau decays from prompt electrons and muons. Thanks to the advanced calorimetry and tracking, the ATLAS experiment has developed tools to efficiently identify hadronic taus at the trigger level. In this presentation we will review the characteristics of taus and the methods to suppress low-multiplicity, low-energy jets contributions as well as we will address the tau trigger chain which provide a rejection rate of 10^5. We will further present plans for commissioning the ATLA...

  14. A Fast hardware Tracker for the ATLAS Trigger system

    CERN Document Server

    Pandini, Carlo Enrico; The ATLAS collaboration

    2015-01-01

    The trigger system at the ATLAS experiment is designed to lower the event rate occurring from the nominal bunch crossing at 40 MHz to about 1 kHz for a designed LHC luminosity of 10$^{34}$ cm$^{-2}$ s$^{-1}$. After a very successful data taking run the LHC is expected to run starting in 2015 with much higher instantaneous luminosities and this will increase the load on the High Level Trigger system. More sophisticated algorithms will be needed to achieve higher background rejection while maintaining good efficiency for interesting physics signals, which requires a more extensive use of tracking information. The Fast Tracker (FTK) trigger system, part of the ATLAS trigger upgrade program, is a highly parallel hardware device designed to perform full-scan track-finding at the event rate of 100 kHz. FTK is a dedicated processor based on a mixture of advanced technologies. Modern, powerful, Field Programmable Gate Arrays form an important part of the system architecture, and the combinatorial problem of pattern r...

  15. The programmable analog circuitry of the CDF trigger

    International Nuclear Information System (INIS)

    A flexible trigger has been partially built to trigger the CDF, Colliding Detector at Fermilab. A programmable analog system can yield a large dynamic range of outputs. With suitable management it will control noise to achieve the high resolution and fast process necessary for such a trigger. The first level output will be delivered in three microseconds after a beam crossing. The system is designed to have a resolution of one part in one thousand. Analog processing, where just summing is involved, can handle many channels faster than an equivalent digital processor exhibiting the same resolution. As a result, this system will be much simpler with far less components. Digital intervention controls channel gain and bias. It also sets a comparison level, and includes or excludes individual channels in the various output summing networks that will determine the trigger result. The results of the analog processing which are input to the digital control include the value of the channel magnitude comparison, the sign of the results of the various sums and finally the fast flash analog to digital converter output values. A set of DACS are used to control the pedestal of the respective various sum networks

  16. The ATLAS Jet Trigger for LHC Run 2

    CERN Document Server

    Anjos, Nuno; The ATLAS collaboration

    2015-01-01

    The ATLAS Jet Trigger for LHC Run 2 The new centre of mass energy and high luminosity conditions expected for Run 2 at the Large Hadron Collider (LHC) impose more demanding constraints on the ATLAS online trigger than ever before. An immense rate of proton-proton collisions must be reduced from the bunch-crossing rate of 40 MHz to approximately 1 kHz before data can be written on disk for offline analysis. The ATLAS trigger system performs real-time reconstruction and selection of these events in order to achieve this reduction. The selection of events containing jets is uniquely challenging at a hadron collider where nearly every event contains significant hadronic activity. It is, however, of crucial importance to exploit the new data in many physics topics in the new kinematic regime, ranging from early Standard Model measurements to searches for New Physics. Following the very successful first LHC run in 2010/12, the ATLAS trigger was much improved, including a new hardware topological processor and the r...

  17. Digital Filtering Performance in the ATLAS Level-1 Calorimeter Trigger

    CERN Document Server

    Hadley, D R; The ATLAS collaboration

    2010-01-01

    The ATLAS Level-1 Calorimeter Trigger is a hardware-based system designed to identify high-pT jets, elec- tron/photon and tau candidates, and to measure total and missing ET in the ATLAS Liquid Argon and Tile calorimeters. It is a pipelined processor system, with a new set of inputs being evaluated every 25ns. The overall trigger decision has a latency budget of 2µs, including all transmission delays. The calorimeter trigger uses about 7200 reduced granularity analogue signals, which are first digitized at the 40 MHz LHC bunch-crossing frequency, before being passed to a digital Finite Impulse Re- sponse (FIR) filter. Due to latency and chip real-estate constraints, only a simple 5-element filter with limited precision can be used. Nevertheless, this filter achieves a significant reduction in noise, along with improving the bunch-crossing assignment and energy resolution for small signals. The context in which digital filters are used for the ATLAS Level-1 Calorimeter Trigger is presented, before descr...

  18. Digital Filter Performance for the ATLAS Level-1 Calorimeter Trigger

    CERN Document Server

    Hadley, D R; The ATLAS collaboration

    2010-01-01

    The ATLAS Level-1 Calorimeter Trigger is a hardware-based system designed to identify high-pT jets, electron/photon and tau candidates, and to measure total and missing ET in the ATLAS Liquid Argon and Tile calorimeters. It is a pipelined processor system, with a new set of inputs being evaluated every 25ns. The overall trigger decision has a latency budget of 2µs, including all transmission delays. The calorimeter trigger uses about 7200 reduced granularity analogue signals, which are first digitized at the 40 MHz LHC bunch-crossing frequency, before being passed to a digital Finite Impulse Response (FIR) filter. Due to latency and chip real-estate constraints, only a simple 5-element filter with limited precision can be used. Nevertheless this filter achieves a significant reduction in noise, along with improving the bunch-crossing assignment and energy resolution for small signals. The context in which digital filters are used for the ATLAS Level-1 Calorimeter Trigger will be presented, before describing ...

  19. Contribution to the elaboration and implementation of LEP-L3 second level microcoded Trigger

    International Nuclear Information System (INIS)

    This thesis is devoted to the elaboration of the L3 second level trigger which is based on the dedicated programmable XOP processor. This system will reduce the trigger rate by a factor of ten and will ensure that the hardwired level-one processors function correctly. The present document describes all developments that L.A.P.P. is engaged in from the system design up to the complete experimental set up, especially: - The hardware development of the fast input memories as well as the FASTBUS interface unit which allows the microprocessor XOP to run as a performant FASTBUS Master, - the associated software developments, - the implementation of a VME test system dedicated to all control tasks

  20. Autonomous Space Processor for Orbital Debris (ASPOD)

    Science.gov (United States)

    Ramohalli, Kumar; Mitchell, Dominique; Taft, Brett

    1992-01-01

    A project in the Advanced Design Program at the University of Arizona is described. The project is named the Autonomous Space Processor for Orbital Debris (ASPOD) and is a Universities Space Research Association (USRA) sponsored design project. The development of ASPOD and the students' abilities in designing and building a prototype spacecraft are the ultimate goals of this project. This year's focus entailed the development of a secondary robotic arm and end-effector to work in tandem with an existent arm in the removal of orbital debris. The new arm features the introduction of composite materials and a linear drive system, thus producing a light-weight and more accurate prototype. The main characteristic of the end-effector design is that it incorporates all of the motors and gearing internally, thus not subjecting them to the harsh space environment. Furthermore, the arm and the end-effector are automated by a control system with positional feedback. This system is composed of magnetic and optical encoders connected to a 486 PC via two servo-motor controller cards. Programming a series of basic routines and sub-routines allowed the ASPOD prototype to become more autonomous. The new system is expected to perform specified tasks with a positional accuracy of 0.5 cm.

  1. Scientific Computing Kernels on the Cell Processor

    Energy Technology Data Exchange (ETDEWEB)

    Williams, Samuel W.; Shalf, John; Oliker, Leonid; Kamil, Shoaib; Husbands, Parry; Yelick, Katherine

    2007-04-04

    The slowing pace of commodity microprocessor performance improvements combined with ever-increasing chip power demands has become of utmost concern to computational scientists. As a result, the high performance computing community is examining alternative architectures that address the limitations of modern cache-based designs. In this work, we examine the potential of using the recently-released STI Cell processor as a building block for future high-end computing systems. Our work contains several novel contributions. First, we introduce a performance model for Cell and apply it to several key scientific computing kernels: dense matrix multiply, sparse matrix vector multiply, stencil computations, and 1D/2D FFTs. The difficulty of programming Cell, which requires assembly level intrinsics for the best performance, makes this model useful as an initial step in algorithm design and evaluation. Next, we validate the accuracy of our model by comparing results against published hardware results, as well as our own implementations on a 3.2GHz Cell blade. Additionally, we compare Cell performance to benchmarks run on leading superscalar (AMD Opteron), VLIW (Intel Itanium2), and vector (Cray X1E) architectures. Our work also explores several different mappings of the kernels and demonstrates a simple and effective programming model for Cell's unique architecture. Finally, we propose modest microarchitectural modifications that could significantly increase the efficiency of double-precision calculations. Overall results demonstrate the tremendous potential of the Cell architecture for scientific computations in terms of both raw performance and power efficiency.

  2. JNT multiplexer and analog input processor

    International Nuclear Information System (INIS)

    This paper discusses the design, implementation, and performance of a working model of the Multiplexer-Analog Input Processor (AIP) System for the transmission and measurements of Johnson Noise Power Thermometer sensor information. The goal of this study was to determine the practical circuit limitations, investigate the circuit/component degradations due to radiation, develop an interference cancellation technique, and evaluate the measurements accuracy as a function of temperature, radition, and interference levels. By using a Fast Fourier Transform (FFT) for spectral estimation, the tuned-circuit parameters of the JNT Preamplifiers can be measured and the temperature computed from the power integrated over a limited bandwidth, thereby greatly reducing the system bandwidth requirements and the amplifier noise contamination. Preliminary measurements show that the temperature measurement can be made to ±10K for temperatures below 1000 K and ±1% above 1000K, for approximately 1 second of integration time. Multiple interfering signals, down to negative Signal-to-Interference Ratios (SIR), are eliminated with no significant degradation in the temperature measured. The AIP also adaptively monitors and extracts an estimate of the Preamplifier's noise contribution, eliminating this error from the overall JNT noise power measurement

  3. A CNN-Specific Integrated Processor

    Directory of Open Access Journals (Sweden)

    Suleyman Malki

    2009-01-01

    Full Text Available Integrated Processors (IP are algorithm-specific cores that either by programming or by configuration can be re-used within many microelectronic systems. This paper looks at Cellular Neural Networks (CNN to become realized as IP. First current digital implementations are reviewed, and the memoryprocessor bandwidth issues are analyzed. Then a generic view is taken on the structure of the network, and a new intra-communication protocol based on rotating wheels is proposed. It is shown that this provides for guaranteed high-performance with a minimal network interface. The resulting node is small and supports multi-level CNN designs, giving the system a 30-fold increase in capacity compared to classical designs. As it facilitates multiple operations on a single image, and single operations on multiple images, with minimal access to the external image memory, balancing the internal and external data transfer requirements optimizes the system operation. In conventional digital CNN designs, the treatment of boundary nodes requires additional logic to handle the CNN value propagation scheme. In the new architecture, only a slight modification of the existing cells is necessary to model the boundary effect. A typical prototype for visual pattern recognition will house 4096 CNN cells with a 2% overhead for making it an IP.

  4. Project Report: Automatic Sequence Processor Software Analysis

    Science.gov (United States)

    Benjamin, Brandon

    2011-01-01

    The Mission Planning and Sequencing (MPS) element of Multi-Mission Ground System and Services (MGSS) provides space missions with multi-purpose software to plan spacecraft activities, sequence spacecraft commands, and then integrate these products and execute them on spacecraft. Jet Propulsion Laboratory (JPL) is currently is flying many missions. The processes for building, integrating, and testing the multi-mission uplink software need to be improved to meet the needs of the missions and the operations teams that command the spacecraft. The Multi-Mission Sequencing Team is responsible for collecting and processing the observations, experiments and engineering activities that are to be performed on a selected spacecraft. The collection of these activities is called a sequence and ultimately a sequence becomes a sequence of spacecraft commands. The operations teams check the sequence to make sure that no constraints are violated. The workflow process involves sending a program start command, which activates the Automatic Sequence Processor (ASP). The ASP is currently a file-based system that is comprised of scripts written in perl, c-shell and awk. Once this start process is complete, the system checks for errors and aborts if there are any; otherwise the system converts the commands to binary, and then sends the resultant information to be radiated to the spacecraft.

  5. Element Load Data Processor (ELDAP) Users Manual

    Science.gov (United States)

    Ramsey, John K., Jr.; Ramsey, John K., Sr.

    2015-01-01

    Often, the shear and tensile forces and moments are extracted from finite element analyses to be used in off-line calculations for evaluating the integrity of structural connections involving bolts, rivets, and welds. Usually the maximum forces and moments are desired for use in the calculations. In situations where there are numerous structural connections of interest for numerous load cases, the effort in finding the true maximum force and/or moment combinations among all fasteners and welds and load cases becomes difficult. The Element Load Data Processor (ELDAP) software described herein makes this effort manageable. This software eliminates the possibility of overlooking the worst-case forces and moments that could result in erroneous positive margins of safety and/or selecting inconsistent combinations of forces and moments resulting in false negative margins of safety. In addition to forces and moments, any scalar quantity output in a PATRAN report file may be evaluated with this software. This software was originally written to fill an urgent need during the structural analysis of the Ares I-X Interstage segment. As such, this software was coded in a straightforward manner with no effort made to optimize or minimize code or to develop a graphical user interface.

  6. Slime mould processors, logic gates and sensors.

    Science.gov (United States)

    Adamatzky, A

    2015-07-28

    A heterotic, or hybrid, computation implies that two or more substrates of different physical nature are merged into a single device with indistinguishable parts. These hybrid devices then undertake coherent acts on programmable and sensible processing of information. We study the potential of heterotic computers using slime mould acting under the guidance of chemical, mechanical and optical stimuli. Plasmodium of acellular slime mould Physarum polycephalum is a gigantic single cell visible to the unaided eye. The cell shows a rich spectrum of behavioural morphological patterns in response to changing environmental conditions. Given data represented by chemical or physical stimuli, we can employ and modify the behaviour of the slime mould to make it solve a range of computing and sensing tasks. We overview results of laboratory experimental studies on prototyping of the slime mould morphological processors for approximation of Voronoi diagrams, planar shapes and solving mazes, and discuss logic gates implemented via collision of active growing zones and tactile responses of P. polycephalum. We also overview a range of electronic components--memristor, chemical, tactile and colour sensors-made of the slime mould. PMID:26078344

  7. A CNN-Specific Integrated Processor

    Science.gov (United States)

    Malki, Suleyman; Spaanenburg, Lambert

    2009-12-01

    Integrated Processors (IP) are algorithm-specific cores that either by programming or by configuration can be re-used within many microelectronic systems. This paper looks at Cellular Neural Networks (CNN) to become realized as IP. First current digital implementations are reviewed, and the memoryprocessor bandwidth issues are analyzed. Then a generic view is taken on the structure of the network, and a new intra-communication protocol based on rotating wheels is proposed. It is shown that this provides for guaranteed high-performance with a minimal network interface. The resulting node is small and supports multi-level CNN designs, giving the system a 30-fold increase in capacity compared to classical designs. As it facilitates multiple operations on a single image, and single operations on multiple images, with minimal access to the external image memory, balancing the internal and external data transfer requirements optimizes the system operation. In conventional digital CNN designs, the treatment of boundary nodes requires additional logic to handle the CNN value propagation scheme. In the new architecture, only a slight modification of the existing cells is necessary to model the boundary effect. A typical prototype for visual pattern recognition will house 4096 CNN cells with a 2% overhead for making it an IP.

  8. Extensible circuit QED processor architecture with vertical I/O

    Science.gov (United States)

    Bruno, Alessandro; Poletto, Stefano; Haider, Nadia; Dicarlo, Leonardo

    Achieving quantum fault tolerance in an extensible architecture is an outstanding challenge across experimental quantum computing platforms today. Traditionally, circuit QED processors have millimeter dimensions and lateral coupling for all input/output (I/O) signals, precluding the increase in qubit numbers beyond ~10. We present a scalable footprint for circuit QED processors with vertically coupled I/O. Our demonstration using centimeter scale chips can accommodate the ~50 qubits needed in next-generation processors targeting the experimental demonstration of quantum fault tolerance. We acknowledge funding from FOM, NWO and the EU FP7 Project SCALEQIT.

  9. CNS disease triggering Takotsubo stress cardiomyopathy.

    Science.gov (United States)

    Finsterer, Josef; Wahbi, Karim

    2014-12-15

    There are a number of hereditary and non-hereditary central nervous system (CNS) disorders, which directly or indirectly affect the heart (brain-heart disorders). The most well-known of these CNS disorders are epilepsy, stroke, infectious or immunological encephalitis/meningitis, migraine, and traumatic brain injury. In addition, a number of hereditary and non-hereditary neurodegenerative disorders may impair cardiac functions. Affection of the heart may manifest not only as arrhythmias, myocardial infarction, autonomic impairment, systolic dysfunction/heart failure, arterial hypertension, or pulmonary hypertension, but also as stress cardiomyopathy (Takotsubo syndrome, TTS). CNS disease triggering TTS includes subarachnoid bleeding, epilepsy, ischemic stroke, intracerebral bleeding, migraine, encephalitis, traumatic brain injury, PRES syndrome, or ALS. Usually, TTS is acutely precipitated by stress triggered by various different events. TTS is one of the cardiac abnormalities most frequently induced by CNS disorders. Appropriate management of TTS from CNS disorders is essential to improve the outcome of affected patients. PMID:25213573

  10. L0 Project: Monitoring H1 Triggers with SpaCal

    OpenAIRE

    Barrelet, E.; Acounis, S; Durant, O.

    2001-01-01

    We have built a VME module using H1’s ADC and BaBar TDC interfaced to H1’s 29K processor. It is used to monitor SpaCal trigger, energy sums and trigger elements, by reading up to 130Kevents/s. The timing resolution is found to be surprisingly good ( »1ns) for energy sum signals. The performances under various beam conditions are shown, including a first study of the “hotspot” counters designed as a veto against e-beam background.

  11. Design of a hardware track finder (Fast TracKer) for the ATLAS trigger

    International Nuclear Information System (INIS)

    The ATLAS Fast TracKer is a custom electronics system that will operate at the full Level-1 accept trigger rate, 100 kHz, to provide high quality tracks as input to the high level trigger. The event reconstruction is performed in hardware, thanks to the massive parallelism of associative memories and FPGAs. We present the advantages for the physics goals of the ATLAS experiment at LHC as well as the recent results on the design, technological advancements and test of some of the core components used in the processor

  12. Design of a hardware track finder (Fast Tracker) for the ATLAS trigger

    International Nuclear Information System (INIS)

    The use of tracking information at the trigger level in the LHC Run II period is crucial for the trigger and data acquisition system and will be even more so as contemporary collisions that occur at every bunch crossing will increase in Run III. The Fast TracKer is part of the ATLAS trigger upgrade project; it is a hardware processor that will provide every Level-1 accepted event (100 kHz) and within 100μs, full tracking information for tracks with momentum as low as 1 GeV . Providing fast, extensive access to tracking information, with resolution comparable to the offline reconstruction, FTK will help in precise detection of the primary and secondary vertices to ensure robust selections and improve the trigger performance

  13. Performance of the ATLAS Trigger and Data-Acquisition system

    CERN Document Server

    Dobson, E

    2011-01-01

    The ATLAS Trigger and Data Acquisition (TDAQ) system cite{TriggerPerf} is responsible for reducing the event rate from the design bunch-crossing rate of 40 MHz to an average recording rate of 200 Hz. The ATLAS trigger is designed to select signal-like events from a large background in three levels: a first-level (L1) implemented in custom-built electronics, as well as the two levels of the high level trigger (HLT) software triggers executed on large computing farms.\\ indent The first-level trigger is comprised of calorimeter, muon and forward triggers to identify event features such as missing transverse energy, as well as candidate electrons, photons, jets and muons. Input signals from these objects are processed by the L1 Central Trigger to form a L1 Accept (L1A) decision. L1A and timing information is consequently sent to all sub-detectors, which push their data to DAQ buffers. The first part of the HLT system (called Level 2) pulls the data from the buffers on demand, while the second part (called Event F...

  14. Pattern-Recognition Processor Using Holographic Photopolymer

    Science.gov (United States)

    Chao, Tien-Hsin; Cammack, Kevin

    2006-01-01

    proposed joint-transform optical correlator (JTOC) would be capable of operating as a real-time pattern-recognition processor. The key correlation-filter reading/writing medium of this JTOC would be an updateable holographic photopolymer. The high-resolution, high-speed characteristics of this photopolymer would enable pattern-recognition processing to occur at a speed three orders of magnitude greater than that of state-of-the-art digital pattern-recognition processors. There are many potential applications in biometric personal identification (e.g., using images of fingerprints and faces) and nondestructive industrial inspection. In order to appreciate the advantages of the proposed JTOC, it is necessary to understand the principle of operation of a conventional JTOC. In a conventional JTOC (shown in the upper part of the figure), a collimated laser beam passes through two side-by-side spatial light modulators (SLMs). One SLM displays a real-time input image to be recognized. The other SLM displays a reference image from a digital memory. A Fourier-transform lens is placed at its focal distance from the SLM plane, and a charge-coupled device (CCD) image detector is placed at the back focal plane of the lens for use as a square-law recorder. Processing takes place in two stages. In the first stage, the CCD records the interference pattern between the Fourier transforms of the input and reference images, and the pattern is then digitized and saved in a buffer memory. In the second stage, the reference SLM is turned off and the interference pattern is fed back to the input SLM. The interference pattern thus becomes Fourier-transformed, yielding at the CCD an image representing the joint-transform correlation between the input and reference images. This image contains a sharp correlation peak when the input and reference images are matched. The drawbacks of a conventional JTOC are the following: The CCD has low spatial resolution and is not an ideal square

  15. Multi-processor developments in the United States for future high energy physics experiments and accelerators

    International Nuclear Information System (INIS)

    The use of multi-processors for analysis and high-level triggering in High Energy Physics experiments, pioneered by the early emulator systems, has reached maturity, in particular with the multiple microprocessor systems in use at Fermilab. It is widely acknowledged that such systems will fulfill the major portion of the computing needs of future large experiments. Recent developments at Fermilab's Advanced Computer Program will make such systems even more powerful, cost-effective, and easier to use than they are at present. The next generation of microprocessors, already available, will provide CPU power of about one VAX 780 equivalent/$300, while supporting most VMS FORTRAN extensions and large (>8MB) amounts of memory. Low cost high density mass storage devices (based on video tape cartridge technology) will allow parallel I/O to remove potential I/O bottlenecks in systems of over 1000 VAX equipment processors. New interconnection schemes and system software will allow more flexible topologies and extremely high data bandwidth, especially for on-line systems. This talk will summarize the work at the Advanced Computer Program and the rest of the US in this field. 3 refs., 4 figs

  16. Application-Specific Instruction Set Processor Implementation of List Sphere Detector

    Directory of Open Access Journals (Sweden)

    Salmela Perttu

    2007-01-01

    Full Text Available Multiple-input multiple-output (MIMO technology enables higher transmission capacity without additional frequency spectrum and is becoming a part of many wireless system standards. Sphere detection has been introduced in MIMO systems to achieve maximum likelihood (ML or near-ML estimation with reduced complexity. This paper reviews related work on sphere detector implementations and presents an application-specific instruction set processor (ASIP implementation of K-best list sphere detector (LSD using transport triggered architecture (TTA. The implementation is based on using memory and heap data structure for symbol vector sorting. The design space is explored by presenting several variations of the implementation and comparing them with each other in terms of their latencies and hardware complexities. An early proposal for a parallelized architecture with a decoding throughput of approximately 5.3 Mbps is presented

  17. 2009 Survey of Gulf of Mexico Dockside Seafood Processors

    Data.gov (United States)

    National Oceanic and Atmospheric Administration, Department of Commerce — This survey gathered and analyze economic data from seafood processors throughout the states in the Gulf region. The survey sought to collect financial variables...

  18. On some parallel algorithms on a ring of processors

    Science.gov (United States)

    Sameh, A.

    1985-07-01

    In this paper we describe some linear algebra multiprocessor algorithms which are suitable for a ring of processors. These algorithms are organized in such a way as to be easily modified for general-purpose multiprocessors with shared global memories.

  19. Compiler for Fast, Accurate Mathematical Computing on Integer Processors Project

    Data.gov (United States)

    National Aeronautics and Space Administration — The proposers will develop a computer language compiler to enable inexpensive, low-power, integer-only processors to carry our mathematically-intensive...

  20. Architecture and Design of Medical Processor Units for Medical Networks

    CERN Document Server

    Ahamed, Syed V; 10.5121/ijcnc.2010.2602

    2011-01-01

    This paper introduces analogical and deductive methodologies for the design medical processor units (MPUs). From the study of evolution of numerous earlier processors, we derive the basis for the architecture of MPUs. These specialized processors perform unique medical functions encoded as medical operational codes (mopcs). From a pragmatic perspective, MPUs function very close to CPUs. Both processors have unique operation codes that command the hardware to perform a distinct chain of subprocesses upon operands and generate a specific result unique to the opcode and the operand(s). In medical environments, MPU decodes the mopcs and executes a series of medical sub-processes and sends out secondary commands to the medical machine. Whereas operands in a typical computer system are numerical and logical entities, the operands in medical machine are objects such as such as patients, blood samples, tissues, operating rooms, medical staff, medical bills, patient payments, etc. We follow the functional overlap betw...