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Sample records for central trigger processor

  1. The Central Trigger Processor (CTP)

    CERN Multimedia

    Franchini, Matteo

    2016-01-01

    The Central Trigger Processor (CTP) receives trigger information from the calorimeter and muon trigger processors, as well as from other sources of trigger. It makes the Level-1 decision (L1A) based on a trigger menu.

  2. The ATLAS Level-1 Central Trigger Processor

    CERN Document Server

    Pauly, T; Ellis, Nick; Farthouat, P; Gällnö, P; Haller, J; Krasznahorkay, A; Maeno, T; Pessoa-Lima, H; Resurreccion-Arcas, I; Schuler, G; De Seixas, J M; Spiwoks, R; Torga-Teixeira, R; Wengler, T; 14th IEEE-NPSS Real Time Conference 2005

    2005-01-01

    ATLAS is a multi-purpose particle physics detector at CERN’s Large Hadron Collider where two pulsed beams of protons are brought to collision at very high energy. There are collisions every 25 ns, corresponding to a rate of 40 MHz. A three-level trigger system reduces this rate to about 200 Hz while keeping bunch crossings which potentially contain interesting processes. The Level-1 trigger, implemented in electronics and firmware, makes an initial selection in under 2.5 us with an output rate of less than 100 kHz. A key element of this is the Central Trigger Processor (CTP) which combines trigger information from the calorimeter and muon trigger processors to make the final Level-1 accept decision in under 100 ns on the basis of lists of selection criteria, implemented as a trigger menu. Timing and trigger signals are fanned out to all sub-detectors, while busy signals from all sub-detector read-out systems are collected and fed into the CTP in order to throttle the generation of Level-1 triggers.

  3. The ATLAS Level-1 Central Trigger Processor (CTP)

    CERN Document Server

    Spiwoks, Ralf; Ellis, Nick; Farthouat, P; Gällnö, P; Haller, J; Krasznahorkay, A; Maeno, T; Pauly, T; Pessoa-Lima, H; Resurreccion-Arcas, I; Schuler, G; De Seixas, J M; Torga-Teixeira, R; Wengler, T

    2005-01-01

    The ATLAS Level-1 Central Trigger Processor (CTP) combines information from calorimeter and muon trigger processors and makes the final Level-1 Accept (L1A) decision on the basis of lists of selection criteria (trigger menus). In addition to the event-selection decision, the CTP also provides trigger summary information to the Level-2 trigger and the data acquisition system. It further provides accumulated and bunch-by-bunch scaler data for monitoring of the trigger, detector and beam conditions. The CTP is presented and results are shown from tests with the calorimeter adn muon trigger processors connected to detectors in a particle beam, as well as from stand-alone full-system tests in the laboratory which were used to validate the CTP.

  4. The ATLAS Level-1 Muon to Central Trigger Processor Interface

    CERN Document Server

    Berge, D; Farthouat, P; Haas, S; Klofver, P; Krasznahorkay, A; Messina, A; Pauly, T; Schuler, G; Spiwoks, R; Wengler, T; PH-EP

    2007-01-01

    The Muon to Central Trigger Processor Interface (MUCTPI) is part of the ATLAS Level-1 trigger system and connects the output of muon trigger system to the Central Trigger Processor (CTP). At every bunch crossing (BC), the MUCTPI receives information on muon candidates from each of the 208 muon trigger sectors and calculates the total multiplicity for each of six transverse momentum (pT) thresholds. This multiplicity value is then sent to the CTP, where it is used together with the input from the Calorimeter trigger to make the final Level-1 Accept (L1A) decision. In addition the MUCTPI provides summary information to the Level-2 trigger and to the data acquisition (DAQ) system for events selected at Level-1. This information is used to define the regions of interest (RoIs) that drive the Level-2 muontrigger processing. The MUCTPI system consists of a 9U VME chassis with a dedicated active backplane and 18 custom designed modules. The design of the modules is based on state-of-the-art FPGA devices and special ...

  5. Hardware, firmware and software developments for the upgrade of the ATLAS Level-1 Central Trigger Processor

    CERN Document Server

    Ghibaudi, M; The ATLAS collaboration; Spiwoks, R; Anders, G; Bertelsen, H; Boisen, A; Childers, T; Dam, M; Ellis, N; Farthouat, P; Gabaldon Ruiz, C; Gorini, B; Kaneda, M; Ohm, C; Silva Oliveira, M; Pauly, T; Pottgen, R; Schmieden, K; Xella, S

    2013-01-01

    The Central Trigger Processor (CTP) is the final stage of the ATLAS first level trigger system which reduces the collision rate of 40 MHz to a Level-1 event rate of 100 kHz. An upgrade of the CTP is currently underway to significantly increase the number of trigger inputs and trigger combinations, allowing additional flexibility for the trigger menu.\

  6. Hardware and firmware developments for the upgrade of the ATLAS Level-1 Central Trigger Processor

    CERN Document Server

    Anders, G; Boisen, A; Childers, T; Dam, M; Ellis, N; Farthouat, P; Gabaldon Ruiz, C; Ghibaudi, M; Gorini, B; Haas, S; Kaneda, M; Ohm, C; Silva Oliveira, M; Pauly, T; Pottgen, R; Schmieden, K; Spiwoks, R; Xella, S

    2014-01-01

    The Central Trigger Processor (CTP) is the final stage of the ATLAS first level trigger system which reduces the collision rate of 40 MHz to a Level-1 event rate of 100 kHz. An upgrade of the CTP is currently underway to significantly increase the number of trigger inputs and trigger combinations, allowing additional flexibility for the trigger menu. We present the hardware and FPGA firmware of the newly designed core module (CTPCORE+) module of the CTP, as well as results from a system used for early firmware and software prototyping based on commercial FPGA evaluation boards. First test result from the CTPCORE+ module will also be shown.

  7. Topological and Central Trigger Processor for 2014 LHC luminosities

    CERN Document Server

    Simioni, E; The ATLAS collaboration; Bauss, B; Berge, D; Buscher, V; Childers, T; Degele, R; Dobson, E; Ebling, A; Ellis, N; Farthouat, P; Gabaldon, C; Gorini, B; Haas, S; Ji, W; Kaneda, M; Mattig, S; Messina, A; Meyer, C; Moritz, S; Pauly, T; Pottgen, R; Schafer, U; Spiwoks, R; Tapprogge, S; Wengler, T; Wenzel, V

    2012-01-01

    The ATLAS experiment is located at the European Center for Nuclear Research (CERN) in Switzerland. It is designed to observe phenomena that involve highly massive particles produced in the collisions at the Large Hadron Collider (LHC): the world’s largest and highest-energy particle accelerator. Event triggering and Data Acquisition is one of the extraordinary challenges faced by the detectors at the high luminosity LHC collider. During 2011, the LHC reached instantaneous luminosities of 4 10^33 cm−1 s−1 and produced events with up to 24 interactions per colliding proton bunch. This places stringent operational and physical requirements on the ATLAS Trigger in order to reduce the 40MHz collision rate to a manageable event storage rate of 400Hz and, at the same time, selecting those events considered interesting. The Level-1 Trigger is the first rate-reducing step in the ATLAS Trigger, with an output rate of 75kHz and decision latency of less than 2.5 micro seconds. It is primarily composed of the Calori...

  8. Topological and Central Trigger Processor for 2014 LHC luminosities

    CERN Document Server

    Simioni, E; The ATLAS collaboration; Bauss, B; Berge, D; B\\"{u}scher, V; Childers, T; Degele, R; Dobson, E; Ebling, A; Ellis, N; Farthouat, P; Gabaldon, C; Gorini, B; Haas, S; Ji, W; Kaneda, M; M\\"{a}ttig, S; Messina, A; Meyer, C; Moritz, S; Pauly, T; Pottgen, R; Sch\\"{a}fer, U; Spiwoks, R; Tapprogge, S; Wengler, T; Wenzel, V

    2012-01-01

    The ATLAS experiment is located at the European Center for Nu- clear Research (CERN) in Switzerland. It is designed to observe phe- nomena that involve highly massive particles produced in the collisions at the Large Hadron Collider (LHC): the world’s largest and highest-energy particle accelerator. Event triggering and Data Acquisition is one of the extraordinary challenges faced by the detectors at the high luminosity LHC collider. During 2011, the LHC reached instantaneous luminosities of 4×10^33 cm−1 s−1 and produced events with up to 24 interactions per colliding proton bunch. This places stringent operational and physical requirements on the AT- LAS Trigger in order to reduce the 40MHz collision rate to a manageable event storage rate of 400Hz and, at the same time, selecting those events considered interesting. The Level-1 Trigger is the first rate-reducing step in the ATLAS Trigger, with an output rate of 75kHz and decision latency of less than 2.5μs. It is primarily composed of the Calorimete...

  9. ATLAS Central Trigger Processor Input Module (CTPIN) Firmware Upgrade

    CERN Document Server

    Fountas, Petros

    2013-01-01

    The upgraded CTPIN firmware is designed to receive its inputs at twice the design speed. A constraint is that the CTPIN hardware will not be changed, so the upgrade is constrained to the firmware of the Pipeline FPGA and the Monitoring FPGA. The Pipeline FPGA is configured to latch in DDR registers the 32 XSDP input signals at 80 MHz and then decode and latch them internally in 64 registers operating at 40 MHz. After synchronization and alignment these 64 trigger signals are encoded and exported in 31 output lines, using Double-Data-Rate (DDR) registers. Again in the Monitoring module the 31 input trigger signals are decoded and latched in 62 internal signals, using DDR registers. The Pipeline FPGA and Monitoring FPGA firmware have been successfully verified in timing simulation, which shows that an upgrade of the CTPIN without redesigning the hardware is feasible.

  10. The Octant Module of the ATLAS Level-1 Muon to Central Trigger Processor Interface

    CERN Document Server

    Haas, Stefan; Berge, D; Ellis, Nick; Farthouat, P; Krasznahorkay, A; Pauly, T; Schuler, G; Spiwoks, R; Wengler, T

    2007-01-01

    The Muon to Central Trigger Processor Interface (MUCTPI) of the ATLAS Level-1 trigger receives data from the sector logic modules of the muon trigger at every bunch crossing and calculates the total multiplicity of muon candidates, which is then sent to the Central Trigger Processor where the final Level-1 decision is taken. The MUCTPI system consists of a 9U VME crate with a special backplane and 18 custom designed modules. We focus on the design and implementation of the octant module (MIOCT). Each of the 16 MIOCT modules processes the muon candidates from 13 sectors of one half-octant of the detector and forms the local muon candidate multiplicities for the trigger decision. It also resolves the overlaps between chambers in order to avoid double-counting of muon candidates that are detected in more than one sector. The handling of overlapping sectors is based on Look-Up-Tables (LUT) for maximum flexibility. The MIOCT also sends the information on the muon candidates over the custom backplane via the Readou...

  11. Trigger and decision processors

    International Nuclear Information System (INIS)

    In recent years there have been many attempts in high energy physics to make trigger and decision processes faster and more sophisticated. This became necessary due to a permanent increase of the number of sensitive detector elements in wire chambers and calorimeters, and in fact it was possible because of the fast developments in integrated circuits technique. In this paper the present situation will be reviewed. The discussion will be mainly focussed upon event filtering by pure software methods and - rather hardware related - microprogrammable processors as well as random access memory triggers. (orig.)

  12. The ATLAS Local Trigger Processor (LTP) 018

    CERN Document Server

    Borrego-Amaral, P; Farthouat, Philippe; Gällnö, P; Pessoa-Lima, H; Maeno, T; Resurreccion-Arcas, I; De Seixas, J M; Schuler, G; Spiwoks, R; Torga-Teixeira, R; Wengler, T; 10th Workshop on Electronics for LHC and Future Experiments

    2004-01-01

    The Local Trigger Processor (LTP) receives timing and trigger signals from the Central Trigger Processor (CTP) and injects them into the Timing, Trigger and Control (TTC) system of a sub-detector front-end TTC partition. The LTP allows stand-alone running by using local timing and trigger signals or by generating them from memory. In addition, several LTPs of the same sub-detector can be daisy-chained. The LTP can thus be regarded as a switching element for timing and trigger signals with input from the CTP or the daisy-chain, from local input, or from the internal data generator, and with output to the daisy-chain, to the TTC partition, or to local output. Finally, in combined mode several LTPs can be connected together using their local outputs and local inputs to allow stand-alone running of combinations of different sub-detectors.

  13. The UA1 upgrade calorimeter trigger processor

    International Nuclear Information System (INIS)

    The increased luminosity of the improved CERN Collider and the more subtle signals of second-generation collider physics demand increasingly sophisticated triggering. We have built a new first-level trigger processor designed to use the excellent granularity of the UA1 upgrade calorimeter. This device is entirely digital and handles events in 1.5 μs, thus introducing no deadtime. Its most novel feature is fast two-dimensional electromagnetic cluster-finding with the possibility of demanding an isolated shower of limited penetration. The processor allows multiple combinations of triggers on electromagnetic showers, hadronic jets and energy sums, including a total-energy veto of multiple interactions and a full vector sum of missing transverse energy. This hard-wired processor is about five times more powerful than its predecessor, and makes extensive use of pipelining techniques. It was used extensively in the 1988 and 1989 runs of the CERN Collider. (author)

  14. Intelligent trigger processor for the crystal box

    CERN Document Server

    Sanders, G H; Cooper, M D; Hart, G W; Hoffman, C M; Hogan, G E; Hughes, E B; Matis, H S; Rolfe, J; Sandberg, V D; Williams, R A; Wilson, S; Zeman, H

    1981-01-01

    A large solid angle angular modular NaI(Tl) detector with 432 phototubes and 88 trigger scintillators is being used to search simultaneously for three lepton flavor-changing decays of the muon. A beam of up to 10/sup 6/ muons stopping per second with a 6% duty factor would yield up to 1000 triggers per second from random triple coincidences. A reduction of the trigger rate to 10 Hz is required from a hardwired primary trigger processor. Further reduction to <1 Hz is achieved by a microprocessor-based secondary trigger processor. The primary trigger hardware imposes voter coincidence logic, stringent timing requirements, and a non-adjacency requirement in the trigger scintillators defined by hardwired circuits. Sophisticated geometric requirements are imposed by a PROM-based matrix logic, and energy and vector-momentum cuts are imposed by a hardwired processor using LSI flash ADC's and digital arithmetic logic. The secondary trigger employs four satellite microprocessors to do a sparse data scan, multiplex ...

  15. The Topological Processor for the future ATLAS Level-1 Trigger

    CERN Document Server

    Kahra, C; The ATLAS collaboration

    2014-01-01

    ATLAS is an experiment on the Large Hadron Collider (LHC), located at the European Organization for Nuclear Research (CERN) in Switzerland. By 2015 the LHC instantaneous luminosity will be increased from $10^{34}$ up to $3\\cdot 10^{34} \\mathrm{cm}^{-2} \\mathrm{s}^{-1}$. This places stringent operational and physical requirements on the ATLAS Trigger in order to reduce the 40MHz collision rate to a manageable event storage rate of 1kHz while at the same time, selecting those events that contain interesting physics events. The Level-1 Trigger is the first rate-reducing step in the ATLAS Trigger, with an output rate of 100kHz and decision latency of less than $2.5 \\mu \\mathrm{s}$. It is composed of the Calorimeter Trigger, the Muon Trigger and the Central Trigger Processor (CTP). In 2014, there will be a new electronics module: the Topological Processor (L1Topo). The L1Topo will make it possible, for the first time, to use detailed information from subdetectors in a single Level-1 module. This allows the determi...

  16. The ATLAS level-1 Central Trigger

    CERN Document Server

    Spiwoks, R; Berge, D; Caracinha, D; Ellis, Nick; Farthouat, P; Gällnö, P; Haas, S; Klofver, P; Krasznahorkay, A; Messina, A; Ohm, C; Pauly, T; Perantoni, M; Pessoa Lima Junior, H; Schuler, G; De Seixas, J M; Wengler, T; PH-EP

    2007-01-01

    The ATLAS Level-1 Central Trigger consists of the Muon-to-Central-Trigger-Processor Interface (MUCTPI), the Central Trigger Processor (CTP), and the Timing, Trigger and Control (TTC) partitions of the sub-detectors. The MUCTPI connects the output of the muon trigger system to the CTP. At every bunch crossing it receives information on muon candidates from each of the 208 muon trigger sectors and calculates the total multiplicity for each of six pT thresholds. The CTP combines information from the calorimeter trigger and the MUCTPI and makes the final Level-1 Accept (L1A) decision on the basis of lists of selection criteria (trigger menus). The MUCTPI and the CTP provide trigger summary information to the Level-2 trigger and to the data acquisition (DAQ) for every event selected at the Level-1. They further provide accumulated and, for the CTP, bunch-by-bunch counter data for monitoring of the trigger, detector and beam conditions. The TTC partitions send timing, trigger and control signals from the CTP to the...

  17. Parallel processor trigger with distributed real-time kernel

    Energy Technology Data Exchange (ETDEWEB)

    Korhonen, T.; Sakamoto, H.; Watase, Y. (National Lab. for High Energy Physics, Oho 1-1, Tsukuba, Ibaraki 305 (JP))

    1991-04-01

    This paper reports on a second level trigger system, based on 40 microprocessors working in parallel, designed and installed into the VENUS experiment. The purpose of the system is to find particle tracks in Central Drift Chamber on-line during A/D conversion time, in about 10 milliseconds. The authors' hardware is designed to be easily modified by software to get the optimum configuration for the task in hand. To realize sufficient computing power for the task, the task must be divided and distributed to processors as evenly as possible and a good balance between computation and communication load must be achieved. To be able to manage such a complicated system, several software tools have been developed. The software for the system has been entirely written in high level language. Sufficient performance for the trigger operation has been realized in tests with real event data.

  18. Review of trigger and on-line processors at SLAC

    International Nuclear Information System (INIS)

    The role of trigger and on-line processors in reducing data rates to manageable proportions in e+e- physics experiments is defined not by high physics or background rates, but by the large event sizes of the general-purpose detectors employed. The rate of e+e- annihilation is low, and backgrounds are not high; yet the number of physics processes which can be studied is vast and varied. This paper begins by briefly describing the role of trigger processors in the e+e- context. The usual flow of the trigger decision process is illustrated with selected examples of SLAC trigger processing. The features are mentioned of triggering at the SLC and the trigger processing plans of the two SLC detectors: The Mark II and the SLD. The most common on-line processors at SLAC, the BADC, the SLAC Scanner Processor, the SLAC FASTBUS Controller, and the VAX CAMAC Channel, are discussed. Uses of the 168/E, 3081/E, and FASTBUS VAX processors are mentioned. The manner in which these processors are interfaced and the function they serve on line is described. Finally, the accelerator control system for the SLC is outlined. This paper is a survey in nature, and hence, relies heavily upon references to previous publications for detailed description of work mentioned here. 27 references, 9 figures, 1 table

  19. The Level 0 Trigger Processor for the NA62 experiment

    Science.gov (United States)

    Chiozzi, S.; Gamberini, E.; Gianoli, A.; Mila, G.; Neri, I.; Petrucci, F.; Soldi, D.

    2016-07-01

    In the NA62 experiment at CERN, the intense flux of particles requires a high-performance trigger for the data acquisition system. A Level 0 Trigger Processor (L0TP) was realized, performing the event selection based on trigger primitives coming from sub-detectors and reducing the trigger rate from 10 to 1 MHz. The L0TP is based on a commercial FPGA device and has been implemented in two different solutions. The performance of the two systems are highlighted and compared.

  20. The fast tracker processor for hadron collider triggers

    CERN Document Server

    Annovi, A; Bardi, A; Carosi, R; Dell'Orso, Mauro; D'Onofrio, M; Giannetti, P; Iannaccone, G; Morsani, E; Pietri, M; Varotto, G

    2001-01-01

    Perspectives for precise and fast track reconstruction in future hadron collider experiments are addressed. We discuss the feasibility of a pipelined highly parallel processor dedicated to the implementation of a very fast tracking algorithm. The algorithm is based on the use of a large bank of pre-stored combinations of trajectory points, called patterns, for extremely complex tracking systems. The CMS experiment at LHC is used as a benchmark. Tracking data from the events selected by the level-1 trigger are sorted and filtered by the Fast Tracker processor at an input rate of 100 kHz. This data organization allows the level-2 trigger logic to reconstruct full resolution tracks with transverse momentum above a few GeV and search for secondary vertices within typical level-2 times. (15 refs).

  1. Commissioning of the ATLAS Level-1 Central Trigger

    CERN Document Server

    Berge, D; Ellis, N; Farthouat, P; Fischer, G; Haas, S; Haller, J; Maettig, S; Messina, A; Pauly, T; Sherman, D; Spiwoks, R

    2010-01-01

    The ATLAS Level-1 Central Trigger (L1CT) consists of the Central Trigger Processor (CTP) and the Muon to Central Trigger Processor Interface (MUCTPI). The CTP forms the final Level-1 Accept (L1A) decision based on the information received from the Level-1 Calorimeter Trigger system and from the muon trigger system through the MUCTPI. Additional inputs are provided for the forward detectors, the filled-bunch trigger, and the minimum-bias trigger scintillators. The CTP also receives timing signals from the Large Hadron Collider (LHC) machine. It fans out the L1A together with timing and control signals to the Local Trigger Processor (LTP) of the subdetectors. Via the same connections it receives the Busy signal to throttle the Level-1 generation. Upon generation of L1A the L1CT sends trigger summary information to the DAQ and Region-of-Interest to the Level-2 Trigger system. In this contribution we present an overview of the final L1CT trigger system as it is now installed in the ATLAS experiment and we describ...

  2. The ATLAS Level-1 Central Trigger System 012

    CERN Document Server

    Borrego-Amaral, P; Farthouat, Philippe; Gällnö, P; Haller, J; Maeno, T; Pauly, T; Schuler, G; Spiwoks, R; Torga-Teixeira, R; Wengler, T; Pessoa-Lima, H; De Seixas, J M

    2004-01-01

    The central part of the ATLAS Level-1 trigger system consists of the Central Trigger Processor (CTP), the Local Trigger Processors (LTPs), the Timing, Trigger and Control (TTC) system, and the Read-out Driver Busy (ROD_BUSY) modules. The CTP combines information from calorimeter and muon trigger processors, as well as from other sources and makes the final Level-1 Accept decision (L1A) on the basis of lists of selection criteria, implemented as a trigger menu. Timing and trigger signals are fanned out to about 40 LTPs which inject them into the sub-detector TTC partitions. The LTPs also support stand-alone running and can generate all necessary signals from memory. The TTC partitions fan out the timing and trigger signals to the sub-detector front-end electronics. The ROD_BUSY modules receive busy signals from the front-end electronics and send them to the CTP (via an LTP) to throttle the generation of L1As. An overview of the ATLAS Level-1 Central trigger system will be presented, with emphasis on the design...

  3. An Upgraded ATLAS Central Trigger for 2014 LHC Luminosities

    CERN Document Server

    Kaneda, M; The ATLAS collaboration

    2012-01-01

    During 2011, the LHC reached instantaneous luminosities of 4*10^33 cm-2*s-1 and produced events with up to 24 interactions per colliding proton bunch. Thisplaces stringent operational and physical requirements on the ATLAS Trigger in order to reduce the 40MHz collision rate to a manageable event storage rate of ~400Hz and, atthe same time, selecting those events considered interesting. The Level-1 Trigger is the first rate-reducing step in the ATLAS Trigger, with an output rate of 75kHz and adecision latency of less than 2.5us. It is primarily composed of the Calorimeter Trigger, Muon Trigger, and the Central Trigger Processor which are implemented in custom builtVME electronics. The Central Trigger Processor collects trigger information from all Level-1 systems and produces a Level-1 trigger decision that initiates the readout of all ATLAS subdetectors. In 2014, the LHC will run at a center of mass energy of 14 TeV, compared to the current 8 TeV, and the luminosity will exceed 10^34 cm^-2*s^-1. With higher l...

  4. An Upgraded ATLAS Central Trigger for 2014 Luminosities

    CERN Document Server

    Anders, G; The ATLAS collaboration; Bertelsen, H; Childers, T; Dam, M; Dobson, E; Ellis, N; Farthouat, P; Gabaldon, C; Gorini, B; Haas, S; Kaneda, M; Maettig, S; Messina, A; Pauly, T; Pöttgen, R; Spiwoks, R; Wengler, T; Xella, S

    2012-01-01

    During 2011, the LHC reached instantaneous luminosities of 4*10^33 cm-2*s-1 and produced events with up to 24 interactions per colliding proton bunch. This places stringent operational and physical requirements on the ATLAS Trigger in order to reduce the 40MHz collision rate to a manageable event storage rate of ~400Hz and, at the same time, selecting those events considered interesting. The Level-1 Trigger is the first rate-reducing step in the ATLAS Trigger, with an output rate of 75kHz and a decision latency of less than 2.5us. It is primarily composed of the Calorimeter Trigger, Muon Trigger, and the Central Trigger Processor which are implemented in custom built VME electronics. The Central Trigger Processor collects trigger information from all Level-1 systems and produces a Level-1 trigger decision that initiates the readout of all ATLAS detectors. In 2014, the LHC will run at a center of mass energy of 14 TeV, compared to the current 8 TeV, and the luminosity will exceed 10^34 cm^-2*s^-1. With higher ...

  5. An Upgraded ATLAS Central Trigger for 2014 LHC Luminosities

    CERN Document Server

    Kaneda, M; The ATLAS collaboration

    2012-01-01

    During 2011, the LHC reached instantaneous luminosities of 4*10^33 cm^-1*s^-1 and produced events with up to 24 interactions per colliding proton bunch. This places stringent operational and physical requirements on the ATLAS Trigger in order to reduce the 40MHz collision rate to a manageable event storage rate of ~400Hz and, at the same time, selecting those events considered interesting. The Level-1 Trigger is the first rate-reducing step in the ATLAS Trigger, with an output rate of 75kHz and a decision latency of less than 2.5us. It is primarily composed of the Calorimeter Trigger, Muon Trigger, and the Central Trigger Processor which are implemented in custom built VME electronics. The Central Trigger Processor collects trigger information from all Level-1 systems and produces a Level-1 trigger decision that initiates the readout of all ATLAS sub-detectors. In 2014, the LHC will run at a center of mass energy of 14 TeV, compared to the current 8 TeV, and the luminosity will exceed 10^34 cm^-1*s^-1. With h...

  6. An upgraded ATLAS Central Trigger for post-2014 LHC luminosities

    CERN Document Server

    Anders, G; The ATLAS collaboration; Bertelsen, H; Childers, T; Dam, M; Dobson, E; Ellis, N; Farthouat, P; Gabaldon, C; Gorini, B; Haas, S; Kaneda, M; Maettig, S; Messina, A; Ohm, C; Pauly, T; Poettgen, R; Spiwoks, R; Wengler, T; Xella, S

    2012-01-01

    During 2011, the LHC reached instantaneous luminosities of 6.7 · 10^33 cm−2s−1 and produced events with up to 40 interactions per colliding proton bunch. This places stringent operational and physical requirements on the ATLAS trigger in order to reduce the 40 MHz collision rate to a manageable event storage rate of 400 Hz without discarding those events considered interesting. The Level-1 trigger is the first rate-reducing step in the ATLAS trigger, with an output rate of 75 kHz and a decision latency of less than 2.5 μ s. It is primarily composed of the Calorimeter Trigger, Muon Trigger, and the Central Trigger Processor which are implemented in custom built VME electronics. The Central Trigger Processor collects trigger information from all Level-1 systems and produces a Level-1 trigger decision that initiates the readout of all ATLAS detectors. After 2014, the LHC will run at a center of mass energy of up to 14 TeV, compared to the current 8 TeV, and the luminosity will exceed 10^34 cm−2s−1. Wit...

  7. Data driven processor 'Vertex Trigger' for B experiments

    International Nuclear Information System (INIS)

    Data Driven Processors (DDP's) are specialized computation engines configured to solve specific numerical problems, such as vertex reconstruction. The architecture of the DDP which is the subject of this talk was designed and implemented by W. Sippach and B.C. Knapp at Nevis Lab. in the early 1980's. This particular implementation allows multiple parallel streams of data to provide input to a heterogenous collection of simple operators whose interconnection form an algorithm. The local data flow control allows this device to execute algorithms extremely quickly provided that care is taken in the layout of the algorithm. I/O rates of several hundred megabytes/second are routinely achieved thus making DDP's attractive candidates for complex online calculations. The original question was open-quote can a DDP reconstruct tracks in a Silicon Vertex Detector, find events with a separated vertex and do it fast enough to be used as an online trigger?close-quote Restating this inquiry as three questions and describing the answers to the questions will be the subject of this talk. The three specific questions are: (1) Can an algorithm be found which reconstructs tracks in a planar geometry and no magnetic field; (2) Can separated vertices be recognized in some way; (3) Can the algorithm be implemented in the Nevis-UMass and DDP and execute in 10-20 μs?

  8. Testing the PreProcessor modules of the ATLAS level-1 calorimeter Trigger

    International Nuclear Information System (INIS)

    The PreProcessor (PPr) System of the ATLAS Level-1 Calorimeter Trigger is a highly parallel system which receives, digitises and processes about 7200 analogue calorimeter trigger signals from the entire ATLAS Calorimetry. Its key component is a custom build ASIC which determines the transverse energy deposits and transmits them to the object-finding processors of the calorimeter trigger: Cluster Processor and Jet/Energy-Sum Processor. The PPr System consists of 124 identical 9U VME PreProcessor Modules (PPMs), which fit into 8 crates. Each module receives and processes 64 analogue calorimeter trigger signals. Before the modules are installed in the electronic cavern of the experiment, their proper operation has to be ensured. An extensive test procedure has been developed to establish all functions of the PPM in short and long periods of operation. The modules are tested both individually as well as in a crate configuration similar to that of the final system. The transmission of the real-time data over 15m long LVDS cables and the readout are checked with a dedicated VME based system, which emulates both the processors of the calorimeter trigger and a DAQ readout module. Additionally, periodic monitoring of the temperatures and voltages across each board is performed during tests to verify the operating conditions of the modules

  9. Simulation of the new topological processor in the ATLAS first level trigger

    International Nuclear Information System (INIS)

    The LHC will start again in May 2015 with proton-proton collisions at a center of mass energy of √(s)=13 TeV. This results in an increased rate of collisions and a new approach is needed in order to keep high efficiencies for processes of interest at the first level trigger stage. A new trigger module for the first level trigger stage of the ATLAS experiment has been developed in order to achieve this. This new trigger module, the topological processor, is able to make trigger decisions based on topological observables, for example angular correlations of trigger objects from the ATLAS calorimeter and muon system. This talk concentrates on the validation of the trigger decision and read-out of the topological processor by using a bit-wise simulation of the module. The basic strategy how the hardware is validated, and first results are presented.

  10. Monitoring the pre-processor system of the ATLAS level-1 calorimeter trigger

    International Nuclear Information System (INIS)

    The Pre-Processor (PPr) System of the ATLAS Level-1 Calorimeter Trigger is a highly parallel system, with hard-wired algorithms implemented in ASICs, to receive, digitise and process over 7000 analogue trigger tower signals from the entire ATLAS Calorimetry, and to transmit the determined transverse energy deposits to the object-finding processors of the calorimeter trigger: Cluster Processor and Jet/Energy-sum Processor. The PPr System consists of 8 crates, each of which being equipped with 16 Preprocessor Modules, that can each receive and process 64 analogue input signals. The Preprocessor System provides facilities to monitor the operation and performance of both its individual components and the Level-1 Calorimeter Trigger: pipelined readout of event based monitoring data to the DAQ System, in order to document the Level-1 Trigger decision, diagnostic features implemented in PPrASIC to establish rate maps and energy spectra per trigger tower, and output interface to the crate controller CPU. Monitoring software for trigger-specific applications is developed and presented in this talk. (orig.)

  11. Operation of the Upgraded ATLAS Level-1 Central Trigger System

    CERN Document Server

    Glatzer, Julian Maximilian Volker; The ATLAS collaboration

    2015-01-01

    The ATLAS Level-1 Central Trigger (L1CT) system is a central part of ATLAS data-taking and has undergone a major upgrade for Run 2 of the LHC, in order to cope with the expected increase of instantaneous luminosity of a factor of 2 with respect to Run 1. The upgraded hardware offers more flexibility in the trigger decisions due to the double amount of trigger inputs and usable trigger channels. It also provides an interface to the new topological trigger system. Operationally - particularly useful for commissioning, calibration and test runs - it allows concurrent running of up to 3 different subdetector combinations. An overview of the operational software framework of the L1CT system with particular emphasis of the configuration, controls and monitoring aspects is given. The software framework allows a consistent configuration with respect to the ATLAS experiment and the LHC machine, upstream and downstream trigger processors, and the data acquisition. Trigger and dead-time rates are monitored coherently at...

  12. Operation of the Upgraded ATLAS Level-1 Central Trigger System

    CERN Document Server

    Glatzer, Julian Maximilian Volker; The ATLAS collaboration

    2015-01-01

    The ATLAS Level-1 Central Trigger (L1CT) system is a central part of ATLAS data-taking and has undergone a major upgrade for Run 2 of the LHC, in order to cope with the expected increase of instantaneous luminosity of a factor of 2 with respect to Run 1. The upgraded hardware offers more flexibility in the trigger decisions due to the double amount of trigger inputs and usable trigger channels. It also provides an interface to the new topological trigger system. Operationally - particularly useful for commissioning, calibration and test runs - it allows concurrent running of up to 3 different sub-detector combinations. In this contribution, we give an overview of the operational software framework of the L1CT system with particular emphasis of the configuration, controls and monitoring aspects. The software framework allows a consistent configuration with respect to the ATLAS experiment and the LHC machine, upstream and downstream trigger processors, and the data acquisition. Trigger and dead-time rates are m...

  13. Operation of the Upgraded ATLAS Level-1 Central Trigger System

    Science.gov (United States)

    Glatzer, Julian

    2015-12-01

    The ATLAS Level-1 Central Trigger (L1CT) system is a central part of ATLAS data-taking and has undergone a major upgrade for Run 2 of the LHC, in order to cope with the expected increase of instantaneous luminosity of a factor of two with respect to Run 1. The upgraded hardware offers more flexibility in the trigger decisions due to the factor of two increase in the number of trigger inputs and usable trigger channels. It also provides an interface to the new topological trigger system. Operationally - particularly useful for commissioning, calibration and test runs - it allows concurrent running of up to three different subdetector combinations. An overview of the operational software framework of the L1CT system with particular emphasis on the configuration, controls and monitoring aspects is given. The software framework allows a consistent configuration with respect to the ATLAS experiment and the LHC machine, upstream and downstream trigger processors, and the data acquisition system. Trigger and dead-time rates are monitored coherently at all stages of processing and are logged by the online computing system for physics analysis, data quality assurance and operational debugging. In addition, the synchronisation of trigger inputs is watched based on bunch-by-bunch trigger information. Several software tools allow for efficient display of the relevant information in the control room in a way useful for shifters and experts. The design of the framework aims at reliability, flexibility, and robustness of the system and takes into account the operational experience gained during Run 1. The Level-1 Central Trigger was successfully operated with high efficiency during the cosmic-ray, beam-splash and first Run 2 data taking with the full ATLAS detector.

  14. The Calorimeter Trigger Processor Card: the next generation of high speed algorithmic data processing at CMS

    Science.gov (United States)

    Svetek, A.; Blake, M.; Cepeda Hermida, M.; Dasu, S.; Dodd, L.; Fobes, R.; Gomber, B.; Gorski, T.; Guo, Z.; Klabbers, P.; Levine, A.; Ojalvo, I.; Ruggles, T.; Smith, N.; Smith, W. H.; Tikalsky, J.; Vicente, M.; Woods, N.

    2016-02-01

    The CMS Level-1 upgraded calorimeter trigger requires a powerful, flexible and compact processing card. The Calorimeter Trigger Processor Card (CTP7) uses the Virtex-7 FPGA as its primary data processor and is the first FPGA based processing card in CMS to employ the ZYNQ System-on-Chip (SoC) running embedded Linux to provide TCP/IP communication and board support functions. The CTP7 was built from the ground up to support AXI infrastructure to provide flexible and modular designs with minimal time from project conception to final implementation.

  15. The ATLAS Level-1 Central Trigger

    CERN Document Server

    Stockton, M; The ATLAS collaboration

    2011-01-01

    The ATLAS Level-1 trigger system is responsible for reducing the anticipated LHC collision rate from 40 MHz to less than 100 kHz. This Level-1 selection identifies, jet, tau/hadron, electron/photon and muon candidates, with additional triggers for missing and total energy. These inputs are used by the Level-1 Central Trigger to form a Level-1 Accept decision. This decision, along with summary information, is then passed into the higher levels of the trigger system and sub-detectors, which also receive the clock from the Level-1 Central trigger. The performance of the Central Trigger during the first collisions will be shown. This includes details of how the trigger information, along with dead-time rates, are monitored and logged by the online system for physics analysis, data quality assurance and operational debugging. Also presented are the software tools used to efficiently display the relevant information in the control room in a way useful for shifters and experts.

  16. An upgraded ATLAS Central Trigger for 2015 LHC luminosities

    CERN Document Server

    Ohm, C

    2014-01-01

    The LHC collides protons at a rate of 40 MHz and each collision produces $\\sim$1.5~MB of data from the ATLAS detector. The ATLAS trigger system is implemented in three levels and selects only the most interesting collision events to reduce the event storage rate to about 400 Hz. The first level is implemented in custom electronics and reduces the input rate to $\\sim$75 kHz with a decision latency of $\\sim$2.5 us. It is also responsible for initiating the read-out of data from all the sub-detectors in ATLAS. Based primarily on information from calorimeters and muon trigger detectors, the Central Trigger Processor (CTP) produces the Level-­1 trigger decision. After a very successful first run, the LHC is now being upgraded to operate with increased luminosity and a center-of-mass energy of up to 14 TeV. To cope with the higher luminosities, the Level-1 trigger system will have to perform a more refined selection in order to not lose interesting physics data while keeping the total Level-1 rate below 100~kHz. I...

  17. Data flow analysis of a highly parallel processor for a level 1 pixel trigger

    Energy Technology Data Exchange (ETDEWEB)

    Cancelo, G. [Fermi National Accelerator Laboratory (FNAL), Batavia, IL (United States); Gottschalk, Erik Edward [Fermi National Accelerator Laboratory (FNAL), Batavia, IL (United States); Pavlicek, V. [Fermi National Accelerator Laboratory (FNAL), Batavia, IL (United States); Wang, M. [Fermi National Accelerator Laboratory (FNAL), Batavia, IL (United States); Wu, J. [Fermi National Accelerator Laboratory (FNAL), Batavia, IL (United States)

    2003-01-01

    The present work describes the architecture and data flow analysis of a highly parallel processor for the Level 1 Pixel Trigger for the BTeV experiment at Fermilab. First the Level 1 Trigger system is described. Then the major components are analyzed by resorting to mathematical modeling. Also, behavioral simulations are used to confirm the models. Results from modeling and simulations are fed back into the system in order to improve the architecture, eliminate bottlenecks, allocate sufficient buffering between processes and obtain other important design parameters. An interesting feature of the current analysis is that the models can be extended to a large class of architectures and parallel systems.

  18. Fast track-finding trigger processor for the SLAC/LBL Mark II Detector

    International Nuclear Information System (INIS)

    The SLAC/LBL Mark II Magnetic Detector consists of various particle detectors arranged in cylindrical symmetry located in and around an axial magnetic field. A versatile, programmable secondary trigger processor was designed and built to find curved tracks in the detector. The system operates at a 10 MHz clock rate with a total processing time of 34 μsec and is used to ''trigger'' the data processing computer, thereby rejecting background and greatly improving the data acquisition aspects of the detector-computer combination

  19. A track reconstructing low-latency trigger processor for high-energy physics

    International Nuclear Information System (INIS)

    The detection and analysis of the large number of particles emerging from high-energy collisions between atomic nuclei is a major challenge in experimental heavy-ion physics. Efficient trigger systems help to focus the analysis on relevant events. A primary objective of the Transition Radiation Detector of the ALICE experiment at the LHC is to trigger on high-momentum electrons. In this thesis, a trigger processor is presented that employs massive parallelism to perform the required online event reconstruction within 2 μs to contribute to the Level-1 trigger decision. Its three-stage hierarchical architecture comprises 109 nodes based on FPGA technology. Ninety processing nodes receive data from the detector front-end at an aggregate net bandwidth of 2.16 Tbit/s via 1080 optical links. Using specifically developed components and interconnections, the system combines high bandwidth with minimum latency. The employed tracking algorithm three-dimensionally reassembles the track segments found in the detector's drift chambers based on explicit value comparisons, calculates the momentum of the originating particles from the course of the reconstructed tracks, and finally leads to a trigger decision. The architecture is capable of processing up to 20 000 track segments in less than 2 μs with high detection efficiency and reconstruction precision for high-momentum particles. As a result, this thesis shows how a trigger processor performing complex online track reconstruction within tight real-time requirements can be realized. The presented hardware has been built and is in continuous data taking operation in the ALICE experiment. (orig.)

  20. A track reconstructing low-latency trigger processor for high-energy physics

    Energy Technology Data Exchange (ETDEWEB)

    Cuveland, Jan de

    2009-09-17

    The detection and analysis of the large number of particles emerging from high-energy collisions between atomic nuclei is a major challenge in experimental heavy-ion physics. Efficient trigger systems help to focus the analysis on relevant events. A primary objective of the Transition Radiation Detector of the ALICE experiment at the LHC is to trigger on high-momentum electrons. In this thesis, a trigger processor is presented that employs massive parallelism to perform the required online event reconstruction within 2 {mu}s to contribute to the Level-1 trigger decision. Its three-stage hierarchical architecture comprises 109 nodes based on FPGA technology. Ninety processing nodes receive data from the detector front-end at an aggregate net bandwidth of 2.16 Tbit/s via 1080 optical links. Using specifically developed components and interconnections, the system combines high bandwidth with minimum latency. The employed tracking algorithm three-dimensionally reassembles the track segments found in the detector's drift chambers based on explicit value comparisons, calculates the momentum of the originating particles from the course of the reconstructed tracks, and finally leads to a trigger decision. The architecture is capable of processing up to 20 000 track segments in less than 2 {mu}s with high detection efficiency and reconstruction precision for high-momentum particles. As a result, this thesis shows how a trigger processor performing complex online track reconstruction within tight real-time requirements can be realized. The presented hardware has been built and is in continuous data taking operation in the ALICE experiment. (orig.)

  1. An FPGA based demonstrator for a topological processor in the,future ATLAS L1-Calo trigger (“GOLD”)

    CERN Document Server

    "Bauss, B"; The ATLAS collaboration; "Degele, R"; "Ebling, A"; "Ji, W"; "Meyer, C"; "Moritz, S"; "Schaefer, U"; "Simioni, E"; "Tapprogge, S"; "Wenzel, V"

    2011-01-01

    The existing ATLAS trigger consists of three levels. The level 1 (L1) is an FPGAs based custom designed trigger, while the second and third levels are software based. The LHC machine plans to bring the beam energy to the nominal value of 7 TeV and to increase the luminosity in the coming years. The current L1 trigger system is therefore seriously challenged. To cope with the resulting higher event rate, as part of the ATLAS trigger upgrade, a new electronics module is foreseen to be added in the L1-Calo electronics chain: the topological processor. Such processor is provided with fast optical I/O and large bandwidth capability, in order to use the information on the cluster position in space (i.e. jets in the calorimeters or muons in the muon detectors) and improve the purity of the L1 triggers streams by applying topological cuts within the latency budget. In this talk, an overview of the adopted tecnological solutions and the R&D activities on the demonstrator (“GOLD”) are presented.

  2. First-Level Trigger Systems for LHC Experiments

    CERN Multimedia

    Staley, R; Leake, J; Corre, A; Hoelscher, A; Rensch, B; Bodo, J P; Sundblad, R; Svensson, C; Yuan, Jiren; Pentney, M; Lackey, J; Piccinelli, G; Cardarelli, R; Appelquist, G; Prytz, K; Zhao, Xing

    2002-01-01

    % RD27 \\\\ \\\\ We have carried out a broad-based programme of R\\&D on level-1 trigger systems for LHC experiments, including subtrigger processors for muon and calorimeter triggers, the central trigger processor, and the interaction with the level-2 trigger. The R\\&D included detailed design studies for the whole level-1 trigger system and prototyping of key components. Beam tests have been made with prototype calorimeter and muon trigger processors.

  3. Triggering of repeating earthquakes in central California

    Science.gov (United States)

    Wu, Chunquan; Gomberg, Joan; Ben-Naim, Eli; Johnson, Paul

    2014-01-01

    Dynamic stresses carried by transient seismic waves have been found capable of triggering earthquakes instantly in various tectonic settings. Delayed triggering may be even more common, but the mechanisms are not well understood. Catalogs of repeating earthquakes, earthquakes that recur repeatedly at the same location, provide ideal data sets to test the effects of transient dynamic perturbations on the timing of earthquake occurrence. Here we employ a catalog of 165 families containing ~2500 total repeating earthquakes to test whether dynamic perturbations from local, regional, and teleseismic earthquakes change recurrence intervals. The distance to the earthquake generating the perturbing waves is a proxy for the relative potential contributions of static and dynamic deformations, because static deformations decay more rapidly with distance. Clear changes followed the nearby 2004 Mw6 Parkfield earthquake, so we study only repeaters prior to its origin time. We apply a Monte Carlo approach to compare the observed number of shortened recurrence intervals following dynamic perturbations with the distribution of this number estimated for randomized perturbation times. We examine the comparison for a series of dynamic stress peak amplitude and distance thresholds. The results suggest a weak correlation between dynamic perturbations in excess of ~20 kPa and shortened recurrence intervals, for both nearby and remote perturbations.

  4. Multi­-Threaded Algorithms for General purpose Graphics Processor Units in the ATLAS High Level Trigger

    CERN Document Server

    Conde Mui\\~no, Patricia; The ATLAS collaboration

    2016-01-01

    General purpose Graphics Processor Units (GPGPU) are being evaluated for possible future inclusion in an upgraded ATLAS High Level Trigger farm. We have developed a demonstrator including GPGPU implementations of Inner Detector and Muon tracking and Calorimeter clustering within the ATLAS software framework. ATLAS is a general purpose particle physics experiment located on the LHC collider at CERN. The ATLAS Trigger system consists of two levels, with level 1 implemented in hardware and the High Level Trigger implemented in software running on a farm of commodity CPU. The High Level Trigger reduces the trigger rate from the 100 kHz level 1 acceptance rate to 1 kHz for recording, requiring an average per­-event processing time of ~250 ms for this task. The selection in the high level trigger is based on reconstructing tracks in the Inner Detector and Muon Spectrometer and clusters of energy deposited in the Calorimeter. Performing this reconstruction within the available farm resources presents a significant ...

  5. An FPGA-based trigger processor for a measurement of deeply virtual Compton scattering at the COMPASS-II experiment

    Energy Technology Data Exchange (ETDEWEB)

    Schopferer, Sebastian

    2013-12-16

    The COMPASS-II experiment at CERN is focusing on a measurement of the deeply virtual Compton scattering. Several upgrades of the experimental setup have been performed in 2012, namely the construction of a long liquid hydrogen target and a surrounding recoil proton detector called CAMERA. Based on a time-of-flight measurement between two barrels of scintillators, the CAMERA detector allows to detect protons with a kinetic energy down to 35 MeV, which leave the target under large polar angles. At the same time, protons can be distinguished from other particles resulting from background processes by means of an energy loss measurement in the scintillating material. In order to extend the existing COMPASS trigger scheme, a digital trigger system has been developed, which is detailed in the thesis at hand. The trigger system is able to select events with a recoil proton in the final state while suppressing background events, using the particle identification capabilities of the CAMERA detector. Challenging selection criteria based on both the time-of-flight and the energy loss measurement call for a powerful programmable logic board. At the same time, the integration into the existing COMPASS trigger system poses strict constraints on the latency of the trigger decision. For the implementation of the proton trigger system, a new FPGA-based trigger and DAQ hardware called TIGER has been built. The module is operated in two firmware configurations, serving two distinct purposes. Firstly, the trigger processor is responsible for the generation of a trigger signal based on recoil particles, which is included in the global first-level trigger decision. Secondly, a readout concentrator allows to multiplex the data streams of up to 18 readout modules into one link to the DAQ. The CAMERA detector and the corresponding readout and trigger electronics was commissioned during a test run in autumn 2012. This thesis contains details about the trigger concept, the development of the

  6. TRIGGER

    CERN Multimedia

    W. Smith

    At the March meeting, the CMS trigger group reported on progress in production, tests in the Electronics Integration Center (EIC) in Prevessin 904, progress on trigger installation in the underground counting room at point 5, USC55, the program of trigger pattern tests and vertical slice tests and planning for the Global Runs starting this summer. The trigger group is engaged in the final stages of production testing, systems integration, and software and firmware development. Most systems are delivering final tested electronics to CERN. The installation in USC55 is underway and integration testing is in full swing. A program of orderly connection and checkout with subsystems and central systems has been developed. This program includes a series of vertical subsystem slice tests providing validation of a portion of each subsystem from front-end electronics through the trigger and DAQ to data captured and stored. After full checkout, trigger subsystems will be then operated in the CMS Global Runs. Continuous...

  7. A compact pre-processor system for the ATLAS level-1 calorimeter trigger

    CERN Document Server

    Pfeiffer, U

    1999-01-01

    This thesis describ es the researc h whose aim is to dev elop a compact Pre-Pro cessor system for the A TLAS Lev el-1 Calorimeter T rigger. Con tributions to the p erformance and the arc hitecture of the Pre-Pro cessor w ere made. A demonstrator Multi-Chip Mo dule (PPrD- MCM) w as dev elop ed and assem bled whic h p erforms most of the prepro cessing of four analogue trigger-to w er signals. The prepro cessing includes digitisation to 8-bit precision, iden ti cation of the corresp onding bunc h-crossing in time (BCID), calibration of the transv erse energy , readout of ra w trigger data, and high-sp eed serial data transmission to the trigger pro cessors. The demonstrator Multi-Chip Mo dule has a size of 15.9 cm 2 and it consists of 9 dies. The MCM w as designed with a smallest feature size of 100 m and it w as fabricated in a laminated MCM-L pro cess o ered b yW urth Elektronik. A Flip-Chip in terconnection ASIC (Finco) w as dev elop ed for the PPrD-MCM and fabricated in a 0.8 m BiCMOS- pro cess o ered b ...

  8. TRIGGER

    CERN Multimedia

    Wesley Smith

    Trigger Hardware The status of the trigger components was presented during the September CMS Week and Annual Review and at the monthly trigger meetings in October and November. Procedures for cold and warm starts (e.g. refreshing of trigger parameters stored in registers) of the trigger subsystems have been studied. Reviews of parts of the Global Calorimeter Trigger (GCT) and the Global Trigger (GT) have taken place in October and November. The CERN group summarized the status of the Trigger Timing and Control (TTC) system. All TTC crates and boards are installed in the underground counting room, USC55. The central clock system will be upgraded in December (after the Global Run at the end of November GREN) to the new RF2TTC LHC machine interface timing module. Migration of subsystem's TTC PCs to SLC4/ XDAQ 3.12 is being prepared. Work is on going to unify the access to Local Timing Control (LTC) and TTC CMS interface module (TTCci) via SOAP (Simple Object Access Protocol, a lightweight XML-based messaging ...

  9. TRIGGER

    CERN Multimedia

    W. Smith

    At the December meeting, the CMS trigger group reported on progress in production, tests in the Electronics Integration Center (EIC) in Prevessin 904, progress on trigger installation in the underground counting room at point 5, USC55, and results from the Magnet Test and Cosmic Challenge (MTCC) phase II. The trigger group is engaged in the final stages of production testing, systems integration, and software and firmware development. Most systems are delivering final tested electronics to CERN. The installation in USC55 is underway and moving towards integration testing. A program of orderly connection and checkout with subsystems and central systems has been developed. This program includes a series of vertical subsystem slice tests providing validation of a portion of each subsystem from front-end electronics through the trigger and DAQ to data captured and stored. This is combined with operations and testing without beam that will continue until startup. The plans for start-up, pilot and early running tri...

  10. The Efficiency Improvement of Central European Corporate Milk Processors in 2008 - 2013

    Directory of Open Access Journals (Sweden)

    J. Špička

    2016-12-01

    Full Text Available The aim of the article is to evaluate the technical efficiency improvement of the Czech, Polish and Slovak corporate milk processors in the period 2008 – 2013 to identify the possible source of low competitiveness of the Czech and Slovak milk processors towards Poland. The analysis was based on individual data of 130 milk processors (NACE 10.51. The sample covers medium-sized and large companies only. Deflated data on sales, material and energy costs, staff costs and depreciation were used as output and inputs for efficiency calculation. The DEA method was used for calculation of technical efficiency, Malmquist index estimated the efficiency change in time. Two-sample t-test and the analysis of variance enhanced by Sheffe’s test verified the statistical hypotheses. The results proved that the Czech and Slovak milk processors had lower efficiency improvement than Polish companies. Investment activity did not significantly affect the efficiency improvement. The Czech and Slovak milk processors should effectively use quite big amount of public subsidies from the Rural Development Programme in the period 2014 – 2020 to improve the efficiency since the Polish companies outstripped the Czech and Slovak companies in the period 2007 - 2013.

  11. TRIGGER

    CERN Multimedia

    Wesley Smith

    Level-1 Trigger Hardware and Software The hardware of the trigger components has been mostly finished. The ECAL Endcap Trigger Concentrator Cards (TCC) are in production while Barrel TCC firmware has been upgraded, and the Trigger Primitives can now be stored by the Data Concentrator Card for readout by the DAQ. The Regional Calorimeter Trigger (RCT) system is complete, and the timing is being finalized. All 502 HCAL trigger links to RCT run without error. The HCAL muon trigger timing has been equalized with DT, RPC, CSC and ECAL. The hardware and firmware for the Global Calorimeter Trigger (GCT) jet triggers are being commissioned and data from these triggers is available for readout. The GCT energy sums from rings of trigger towers around the beam pipe beam have been changed to include two rings from both sides. The firmware for Drift Tube Track Finder, Barrel Sorter and Wedge Sorter has been upgraded, and the synchronization of the DT trigger is satisfactory. The CSC local trigger has operated flawlessly u...

  12. TRIGGER

    CERN Multimedia

    Roberta Arcidiacono

    2013-01-01

    Trigger Studies Group (TSG) The Trigger Studies Group has just concluded its third 2013 workshop, where all POGs presented the improvements to the physics object reconstruction, and all PAGs have shown their plans for Trigger development aimed at the 2015 High Level Trigger (HLT) menu. The Strategy for Trigger Evolution And Monitoring (STEAM) group is responsible for Trigger menu development, path timing, Trigger performance studies coordination, HLT offline DQM as well as HLT release, menu and conditions validation – this last task in collaboration with PdmV (Physics Data and Monte Carlo Validation group). In the last months the group has delivered several HLT rate estimates and comparisons, using the available data and Monte Carlo samples. The studies were presented at the Trigger workshops in September and December, and STEAM has contacted POGs and PAGs to understand the origin of the discrepancies observed between 8 TeV data and Monte Carlo simulations. The most recent results show what the...

  13. Prestaciones del Detector Central de Muones del Experimento CMS: las Camaras de Deriva y su Sistema de Trigger (Performance of the Central Muon Detector of the Experiment CMS: the Drift Tube Chambers and its Trigger System)

    CERN Document Server

    Muñoz, Carlos Villanueva

    2007-01-01

    Prestaciones del Detector Central de Muones del Experimento CMS: las Camaras de Deriva y su Sistema de Trigger (Performance of the Central Muon Detector of the Experiment CMS: the Drift Tube Chambers and its Trigger System)

  14. TRIGGER

    CERN Multimedia

    Wesley Smith

    Level-1 Trigger Hardware and Software The trigger synchronization procedures for running with cosmic muons and operating with the LHC were reviewed during the May electronics week. Firmware maintenance issues were also reviewed. Link tests between the new ECAL endcap trigger concentrator cards (TCC48) and the Regional Calorimeter Trigger have been performed. Firmware for the energy sum triggers and an upgraded tau trigger of the Global Calorimeter Triggers has been developed and is under test. The optical fiber receiver boards for the Track-Finder trigger theta links of the DT chambers are now all installed. The RPC trigger is being made more robust by additional chamber and cable shielding and also by firmware upgrades. For the CSC’s the front-end and trigger motherboard firmware have been updated. New RPC patterns and DT/CSC lookup tables taking into account phi asymmetries in the magnetic field configuration are under study. The motherboard for the new pipeline synchronizer of the Global Trigg...

  15. TRIGGER

    CERN Multimedia

    W. Smith

    2012-01-01

      Level-1 Trigger The Level-1 Trigger group is ready to deploy improvements to the L1 Trigger algorithms for 2012. These include new high-PT patterns for the RPC endcap, an improved CSC PT assignment, a new PT-matching algorithm for the Global Muon Trigger, and new calibrations for ECAL, HCAL, and the Regional Calorimeter Trigger. These should improve the efficiency, rate, and stability of the L1 Trigger. The L1 Trigger group also is migrating the online systems to SLC5. To make the data transfer from the Global Calorimeter Trigger to the Global Trigger more reliable and also to allow checking the data integrity online, a new optical link system has been developed by the GCT and GT groups and successfully tested at the CMS electronics integration facility in building 904. This new system is now undergoing further tests at Point 5 before being deployed for data-taking this year. New L1 trigger menus have recently been studied and proposed by Emmanuelle Perez and the L1 Detector Performance Group...

  16. TRIGGER

    CERN Multimedia

    by Wesley Smith

    2010-01-01

    Level-1 Trigger Hardware and Software The overall status of the L1 trigger has been excellent and the running efficiency has been high during physics fills. The timing is good to about 1%. The fine-tuning of the time synchronization of muon triggers is ongoing and will be completed after more than 10 nb-1 of data have been recorded. The CSC trigger primitive and RPC trigger timing have been refined. A new configuration for the CSC Track Finder featured modified beam halo cuts and improved ghost cancellation logic. More direct control was provided for the DT opto-receivers. New RPC Cosmic Trigger (RBC/TTU) trigger algorithms were enabled for collision runs. There is further work planned during the next technical stop to investigate a few of the links from the ECAL to the Regional Calorimeter Trigger (RCT). New firmware and a new configuration to handle trigger rate spikes in the ECAL barrel are also being tested. A board newly developed by the tracker group (ReTRI) has been installed and activated to block re...

  17. TRIGGER

    CERN Multimedia

    Wesley Smith

    Level-1 Trigger Hardware and Software The production of the trigger hardware is now basically finished, and in time for the turn-on of the LHC. The last boards produced are the Trigger Concentrator Cards for the ECAL Endcaps (TCC-EE). After the recent installation of the four EE Dees, the TCC-EE prototypes were used for their commissioning. Production boards are arriving and are being tested continuously, with the last ones expected in November. The Regional Calorimeter Trigger hardware is fully integrated after installation of the last EE cables. Pattern tests from the HCAL up to the GCT have been performed successfully. The HCAL triggers are fully operational, including the connection of the HCAL-outer and forward-HCAL (HO/HF) technical triggers to the Global Trigger. The HCAL Trigger and Readout (HTR) board firmware has been updated to permit recording of the tower “feature bit” in the data. The Global Calorimeter Trigger hardware is installed, but some firmware developments are still n...

  18. TRIGGER

    CERN Multimedia

    W. Smith

    2010-01-01

    Level-1 Trigger Hardware and Software The Level-1 Trigger hardware has performed well during both the recent proton-proton and heavy ion running. Efforts were made to improve the visibility and handling of alarms and warnings. The tracker ReTRI boards that prevent fixed frequencies of Level-1 Triggers are now configured through the Trigger Supervisor. The Global Calorimeter Trigger (GCT) team has introduced a buffer cleanup procedure at stops and a reset of the QPLL during configuring to ensure recalibration in case of a switch from the LHC clock to the local clock. A device to test the cables between the Regional Calorimeter Trigger and the GCT has been manufactured. A wrong charge bit was fixed in the CSC Trigger. The ECAL group is improving crystal masking and spike suppression in the trigger primitives. New firmware for the Drift Tube Track Finder (DTTF) sorters was developed to improve fake track tagging and sorting. Zero suppression was implemented in the DT Sector Collector readout. The track finder b...

  19. TRIGGER

    CERN Multimedia

    W. Smith from contributions of C. Leonidopoulos

    2010-01-01

    Level-1 Trigger Hardware and Software Since nearly all of the Level-1 (L1) Trigger hardware at Point 5 has been commissioned, activities during the past months focused on the fine-tuning of synchronization, particularly for the ECAL and the CSC systems, on firmware upgrades and on improving trigger operation and monitoring. Periodic resynchronizations or hard resets and a shortened luminosity section interval of 23 seconds were implemented. For the DT sector collectors, an automatic power-off was installed in case of high temperatures, and the monitoring capabilities of the opto-receivers and the mini-crates were enhanced. The DTTF and the CSCTF now have improved memory lookup tables. The HCAL trigger primitive logic implemented a new algorithm providing better stability of the energy measurement in the presence of any phase misalignment. For the Global Calorimeter Trigger, additional Source Cards have been manufactured and tested. Testing of the new tau, missing ET and missing HT algorithms is underw...

  20. TRIGGER

    CERN Multimedia

    Wesley Smith

    Level-1 Trigger Hardware and Software The final parts of the Level-1 trigger hardware are now being put in place. For the ECAL endcaps, more than half of the Trigger Concentrator Cards for the ECAL Endcap (TCC-EE) are now available at CERN, such that one complete endcap can be covered. The Global Trigger now correctly handles ECAL calibration sequences, without being influenced by backpressure. The Regional Calorimeter Trigger (RCT) hardware is complete and working in USC55. Intra-crate tests of all 18 RCT crates and the Global Calorimeter Trigger (GCT) are regularly taking place. Pattern tests have successfully captured data from HCAL through RCT to the GCT Source Cards. HB/HE trigger data are being compared with emulator results to track down the very few remaining hardware problems. The treatment of hot and dead cells, including their recording in the database, has been defined. For the GCT, excellent agreement between the emulator and data has been achieved for jets and HF ET sums. There is still som...

  1. TRIGGER

    CERN Multimedia

    W. Smith

    Level-1 Trigger Hardware and Software The trigger system has been constantly in use in cosmic and commissioning data taking periods. During CRAFT running it delivered 300 million muon and calorimeter triggers to CMS. It has performed stably and reliably. During the abort gaps it has also provided laser and other calibration triggers. Timing issues, namely synchronization and latency issues, have been solved. About half of the Trigger Concentrator Cards for the ECAL Endcap (TCC-EE) are installed, and the firmware is being worked on. The production of the other half has started. The HCAL Trigger and Readout (HTR) card firmware has been updated, and new features such as fast parallel zero-suppression have been included. Repairs of drift tube (DT) trigger mini-crates, optical links and receivers of sector collectors are under way and have been completed on YB0. New firmware for the optical receivers of the theta links to the drift tube track finder is being installed. In parallel, tests with new eta track finde...

  2. TRIGGER

    CERN Multimedia

    R. Carlin with contributions from D. Acosta

    2012-01-01

    Level-1 Trigger Data-taking continues at cruising speed, with high availability of all components of the Level-1 trigger. We have operated the trigger up to a luminosity of 7.6E33, where we approached 100 kHz using the 7E33 prescale column.  Recently, the pause without triggers in case of an automatic "RESYNC" signal (the "settle" and "recover" time) was reduced in order to minimise the overall dead-time. This may become very important when the LHC comes back with higher energy and luminosity after LS1. We are also preparing for data-taking in the proton-lead run in early 2013. The CASTOR detector will make its comeback into CMS and triggering capabilities are being prepared for this. Steps to be taken include improved cooperation with the TOTEM trigger system and using the LHC clock during the injection and ramp phases of LHC. Studies are being finalised that will have a bearing on the Trigger Technical Design Report (TDR), which is to be rea...

  3. TRIGGER

    CERN Multimedia

    W. Smith, from contributions of D. Acosta

    2012-01-01

      The L1 Trigger group deployed several major improvements this year. Compared to 2011, the single-muon trigger rate has been reduced by a factor of 2 and the η coverage has been restored to 2.4, with high efficiency. During the current technical stop, a higher jet seed threshold will be applied in the Global Calorimeter Trigger in order to significantly reduce the strong pile-up dependence of the HT and multi-jet triggers. The currently deployed L1 menu, with the “6E33” prescales, has a total rate of less than 100 kHz and operates with detector readout dead time of less than 3% for luminosities up to 6.5 × 1033 cm–2s–1. Further prescale sets have been created for 7 and 8 × 1033 cm–2s–1 luminosities. The L1 DPG is evaluating the performance of the Trigger for upcoming conferences and publication. Progress on the Trigger upgrade was reviewed during the May Upgrade Week. We are investigating scenarios for stagin...

  4. TRIGGER

    CERN Multimedia

    W. Smith from contributions of C. Leonidopoulos, I. Mikulec, J. Varela and C. Wulz.

    Level-1 Trigger Hardware and Software Over the past few months, the Level-1 trigger has successfully recorded data with cosmic rays over long continuous stretches as well as LHC splash events, beam halo, and collision events. The L1 trigger hardware, firmware, synchronization, performance and readiness for beam operation were reviewed in October. All L1 trigger hardware is now installed at Point 5, and most of it is completely commissioned. While the barrel ECAL Trigger Concentrator Cards are fully operational, the recently delivered endcap ECAL TCC system is still being commissioned. For most systems there is a sufficient number of spares available, but for a few systems additional reserve modules are needed. It was decided to increase the overall L1 latency by three bunch crossings to increase the safety margin for trigger timing adjustments. In order for CMS to continue data taking during LHC frequency ramps, the clock distribution tree needs to be reset. The procedures for this have been tested. A repl...

  5. TRIGGER

    CERN Multimedia

    W. Smith

    Level-1 Trigger Hardware and Software The road map for the final commissioning of the level-1 trigger system has been set. The software for the trigger subsystems is being upgraded to run under CERN Scientific Linux 4 (SLC4). There is also a new release for the Trigger Supervisor (TS 1.4), which implies upgrade work by the subsystems. As reported by the CERN group, a campaign to tidy the Trigger Timing and Control (TTC) racks has begun. The machine interface was upgraded by installing the new RF2TTC module, which receives RF signals from LHC Point 4. Two Beam Synchronous Timing (BST) signals, one for each beam, can now be received in CMS. The machine group will define the exact format of the information content shortly. The margin on the locking range of the CMS QPLL is planned for study for different subsystems in the next Global Runs, using a function generator. The TTC software has been successfully tested on SLC4. Some TTC subsystems have already been upgraded to SLC4. The TTCci Trigger Supervisor ...

  6. TRIGGER

    CERN Multimedia

    Wesley Smith

    2011-01-01

    Level-1 Trigger Hardware and Software New Forward Scintillating Counters (FSC) for rapidity gap measurements have been installed and integrated into the Trigger recently. For the Global Muon Trigger, tuning of quality criteria has led to improvements in muon trigger efficiencies. Several subsystems have started campaigns to increase spares by recovering boards or producing new ones. The barrel muon sector collector test system has been reactivated, new η track finder boards are in production, and φ track finder boards are under revision. In the CSC track finder, an η asymmetry problem has been corrected. New pT look-up tables have also improved efficiency. RPC patterns were changed from four out of six coincident layers to three out of six in the barrel, which led to a significant increase in efficiency. A new PAC firmware to trigger on heavy stable charged particles allows looking for chamber hit coincidences in two consecutive bunch-crossings. The redesign of the L1 Trigger Emulator...

  7. TRIGGER

    CERN Multimedia

    R. Arcidiacono

    2013-01-01

      In 2013 the Trigger Studies Group (TSG) has been restructured in three sub-groups: STEAM, for the development of new HLT menus and monitoring their performance; STORM, for the development of HLT tools, code and actual configurations; and FOG, responsible for the online operations of the High Level Trigger. The Strategy for Trigger Evolution And Monitoring (STEAM) group is responsible for Trigger Menu development, path timing, trigger performance studies coordination, HLT offline DQM as well as HLT release, menu and conditions validation – in collaboration and with the technical support of the PdmV group. Since the end of proton-proton data taking, the group has started preparing for 2015 data taking, with collisions at 13 TeV and 25 ns bunch spacing. The reliability of the extrapolation to higher energy is being evaluated comparing the trigger rates on 7 and 8 TeV Monte Carlo samples with the data taken in the past two years. The effect of 25 ns bunch spacing is being studied on the d...

  8. TRIGGER

    CERN Multimedia

    W. Smith

    2011-01-01

    Level-1 Trigger Hardware and Software Overall the L1 trigger hardware has been running very smoothly during the last months of proton running. Modifications for the heavy-ion run have been made where necessary. The maximal design rate of 100 kHz can be sustained without problems. All L1 latencies have been rechecked. The recently installed Forward Scintillating Counters (FSC) are being used in the heavy ion run. The ZDC scintillators have been dismantled, but the calorimeter itself remains. We now send the L1 accept signal and other control signals to TOTEM. Trigger cables from TOTEM to CMS will be installed during the Christmas shutdown, so that the TOTEM data can be fully integrated within the CMS readout. New beam gas triggers have been developed, since the BSC-based trigger is no longer usable at high luminosities. In particular, a special BPTX signal is used after a quiet period with no collisions. There is an ongoing campaign to provide enough spare modules for the different subsystems. For example...

  9. TRIGGER

    CERN Multimedia

    J. Alimena

    2013-01-01

    Trigger Strategy Group The Strategy for Trigger Evolution And Monitoring (STEAM) group is responsible for the development of future High-Level Trigger menus, as well as of its DQM and validation, in collaboration and with the technical support of the PdmV group. Taking into account the beam energy and luminosity expected in 2015, a rough estimate of the trigger rates indicates a factor four increase with respect to 2012 conditions. Assuming that a factor two can be tolerated thanks to the increase in offline storage and processing capabilities, a toy menu has been developed using the new OpenHLT workflow to estimate the transverse energy/momentum thresholds that would halve the current trigger rates. The CPU time needed to run the HLT has been compared between data taken with 25 ns and 50 ns bunch spacing, for equivalent pile-up: no significant difference was observed on the global time per event distribution at the only available data point, corresponding to a pile-up of about 10 interactions. Using th...

  10. TRIGGER

    CERN Multimedia

    by Wesley Smith

    2011-01-01

    Level-1 Trigger Hardware and Software After the winter shutdown minor hardware problems in several subsystems appeared and were corrected. A reassessment of the overall latency has been made. In the TTC system shorter cables between TTCci and TTCex have been installed, which saved one bunch crossing, but which may have required an adjustment of the RPC timing. In order to tackle Pixel out-of-syncs without influencing other subsystems, a special hardware/firmware re-sync protocol has been introduced in the Global Trigger. The link between the Global Calorimeter Trigger and the Global Trigger with the new optical Global Trigger Interface and optical receiver daughterboards has been successfully tested in the Electronics Integration Centre in building 904. New firmware in the GCT now allows a setting to remove the HF towers from energy sums. The HF sleeves have been replaced, which should lead to reduced rates of anomalous signals, which may allow their inclusion after this is validated. For ECAL, improvements i...

  11. TRIGGER

    CERN Multimedia

    W. Smith

    Level-1 Trigger Hardware The CERN group is working on the TTC system. Seven out of nine sub-detector TTC VME crates with all fibers cabled are installed in USC55. 17 Local Trigger Controller (LTC) boards have been received from production and are in the process of being tested. The RF2TTC module replacing the TTCmi machine interface has been delivered and will replace the TTCci module used to mimic the LHC clock. 11 out of 12 crates housing the barrel ECAL off-detector electronics have been installed in USC55 after commissioning at the Electronics Integration Centre in building 904. The cabling to the Regional Calorimeter Trigger (RCT) is terminated. The Lisbon group has completed the Synchronization and Link mezzanine board (SLB) production. The Palaiseau group has fully tested and installed 33 out of 40 Trigger Concentrator Cards (TCC). The seven remaining boards are being remade. The barrel TCC boards have been tested at the H4 test beam, and good agreement with emulator predictions were found. The cons...

  12. The ATLAS Level-1 Topological Trigger Performance

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00371751; The ATLAS collaboration

    2016-01-01

    The LHC will collide protons in the ATLAS detector with increasing luminosity through 2016, placing stringent operational and physical requirements to the ATLAS trigger system in order to reduce the 40 MHz collision rate to a manageable event storage rate of 1 kHz, while not rejecting interesting physics events. The Level-1 trigger is the first rate-reducing step in the ATLAS trigger system with an output rate of 100 kHz and decision latency smaller than 2.5 μs. It consists of a calorimeter trigger, muon trigger and a central trigger processor. During the LHC shutdown after the Run 1 finished in 2013, the Level-1 trigger system was upgraded including hardware, firmware and software updates. In particular, new electronics modules were introduced in the real-time data processing path: the Topological Processor System (L1Topo). It consists of a single AdvancedCTA shelf equipped with two Level-1 topological processor blades. They receive real-time information from the Level-1 calorimeter and muon triggers, which...

  13. Alpine debris flows triggered by a 28 July 1999 thunderstorm in the central Front Range, Colorado

    Science.gov (United States)

    Godt, Jonathan W.; Coe, Jeffrey A.

    2007-02-01

    On 28 July 1999, about 480 alpine debris flows were triggered by an afternoon thunderstorm along the Continental Divide in Clear Creek and Summit counties in the central Front Range of Colorado. The thunderstorm produced about 43 mm of rain in 4 h, 35 mm of which fell in the first 2 h. Several debris flows triggered by the storm impacted Interstate Highway 70, U.S. Highway 6, and the Arapahoe Basin ski area. We mapped the debris flows from color aerial photography and inspected many of them in the field. Three processes initiated debris flows. The first process initiated 11% of the debris flows and involved the mobilization of shallow landslides in thick, often well vegetated, colluvium. The second process, which was responsible for 79% of the flows, was the transport of material eroded from steep unvegetated hillslopes via a system of coalescing rills. The third, which has been termed the "firehose effect," initiated 10% of the debris flows and occurred where overland flow became concentrated in steep bedrock channels and scoured debris from talus deposits and the heads of debris fans. These three processes initiated high on steep hillsides (> 30°) in catchments with small contributing areas (material along their paths.

  14. Trigger strategies for central exclusive $H \\to b\\overline{b}$ studies with the AFP detector

    CERN Document Server

    Brown, G J A; Kupco, A; Pilkington, A; Tasevsky, M

    2009-01-01

    The ATLAS Forward Proton (AFP) upgrade proposes to install proton detectors at 220 m and 420 m either side of the ATLAS interaction point, turning the LHC into a giant magnetic spectrometer. The physics motivation for this upgrade focuses on final states in which the colliding protons remain intact, allowing a full reconstruction of the event, even in the forward region. One such process is the production of the Higgs boson in the central exclusive channel and tagging the outgoing protons allows the possible extraction of the Higgs quantum numbers, mass and couplings regardless of the decay channel. Studying this exclusive production channel for the presently favoured low Higgs mass depends on the possibility of efficiently triggering, up to the highest luminosities, on a pair of relatively soft jets coming from the decay of b quarks or τ leptons. As jet triggers will inevitably be heavily pre-scaled, even at modest luminosities, it is essential to make a coincidence betweeen information from the tagging d...

  15. Remotely triggered microearthquakes and tremor in central California following the 2010 Mw 8.8 Chile earthquake

    Science.gov (United States)

    Peng, Zhigang; Hill, David P.; Shelly, David R.; Aiken, Chastity

    2010-01-01

    We examine remotely triggered microearthquakes and tectonic tremor in central California following the 2010 Mw 8.8 Chile earthquake. Several microearthquakes near the Coso Geothermal Field were apparently triggered, with the largest earthquake (Ml 3.5) occurring during the large-amplitude Love surface waves. The Chile mainshock also triggered numerous tremor bursts near the Parkfield-Cholame section of the San Andreas Fault (SAF). The locally triggered tremor bursts are partially masked at lower frequencies by the regionally triggered earthquake signals from Coso, but can be identified by applying high-pass or matched filters. Both triggered tremor along the SAF and the Ml 3.5 earthquake in Coso are consistent with frictional failure at different depths on critically-stressed faults under the Coulomb failure criteria. The triggered tremor, however, appears to be more phase-correlated with the surface waves than the triggered earthquakes, likely reflecting differences in constitutive properties between the brittle, seismogenic crust and the underlying lower crust.

  16. Level-1 Calorimeter Trigger starts firing

    CERN Multimedia

    Stephen Hillier

    2007-01-01

    L1Calo is one of the major components of ATLAS First Level trigger, along with the Muon Trigger and Central Trigger Processor. It forms all of the first-level calorimeter-based triggers, including electron, jet, tau and missing ET. The final system consists of over 250 custom designed 9U VME boards, most containing a dense array of FPGAs or ASICs. It is subdivided into a PreProcessor, which digitises the incoming trigger signals from the Liquid Argon and Tile calorimeters, and two separate processor systems, which perform the physics algorithms. All of these are highly flexible, allowing the possibility to adapt to beam conditions and luminosity. All parts of the system are read out through Read-Out Drivers, which provide monitoring data and Region of Interest (RoI) information for the Level-2 trigger. Production of the modules is now essentially complete, and enough modules exist to populate the full scale system in USA15. Installation is proceeding rapidly - approximately 90% of the final modules are insta...

  17. Beam Test of the ATLAS Level-1 Calorimeter Trigger System

    CERN Document Server

    Garvey, J; Mahout, G; Moye, T H; Staley, R J; Thomas, J P; Typaldos, D; Watkins, P M; Watson, A; Achenbach, R; Föhlisch, F; Geweniger, C; Hanke, P; Kluge, E E; Mahboubi, K; Meier, K; Meshkov, P; Rühr, F; Schmitt, K; Schultz-Coulon, H C; Ay, C; Bauss, B; Belkin, A; Rieke, S; Schäfer, U; Tapprogge, T; Trefzger, T; Weber, GA; Eisenhandler, E F; Landon, M; Apostologlou, P; Barnett, B M; Brawn, I P; Davis, A O; Edwards, J; Gee, C N P; Gillman, A R; Mirea, A; Perera, V J O; Qian, W; Sankey, D P C; Bohm, C; Hellman, S; Hidvegi, A; Silverstein, S

    2005-01-01

    The Level-1 Calorimter Trigger consists of a Preprocessor (PP), a Cluster Processor (CP), and a Jet/Energy-sum Processor (JEP). The CP and JEP receive digitised trigger-tower data from the Preprocessor and produce Region-of-Interest (RoIs) and trigger multiplicities. The latter are sent in real time to the Central Trigger Processor (CTP) where the Level-1 decision is made. On receipt of a Level-1 Accept, Readout Driver Modules (RODs), provide intermediate results to the data acquisition (DAQ) system for monitoring and diagnostic purpose. RoI information is sent to the RoI builder (RoIB) to help reduce the amount of data required for the Level-2 Trigger The Level-1 Calorimeter Trigger System at the test beam consisted of 1 Preprocessor module, 1 Cluster Processor Module, 1 Jet/Energy Module and 2 Common Merger Modules. Calorimeter energies were sucessfully handled thourghout the chain and trigger object sent to the CTP. Level-1 Accepts were sucessfully produced and used to drive the readout path. Online diagno...

  18. Physics performances with the new ATLAS Level-1 Topological trigger in Run 2

    CERN Document Server

    Artz, Sebastian; The ATLAS collaboration

    2016-01-01

    The ATLAS trigger system aims at reducing the 40 MHz proton-proton collision event rate to a manageable event storage rate of 1 kHz, preserving events valuable for physics analysis. The Level-1 trigger is the first rate-reducing step in the ATLAS trigger system, with an output rate of 100 kHz and decision latency of less than 2.5 micro seconds. It is composed of the calorimeter trigger, muon trigger and central trigger processor. During the last upgrade, a new electronics element was introduced to Level-1: The Topological Processor System. It will make it possible to use detailed realtime information from the Level-1 calorimeter and muon triggers, processed in individual state of the art FPGA processors to determine angles between jets and/or leptons and calculate kinematic variables based on lists of selected/sorted objects. More than one hundred VHDL algorithms are producing trigger outputs to be incorporated into the central trigger processor. This information will be essential to improve background reject...

  19. ATLAS Muon Trigger

    CERN Document Server

    Woudstra, MJ; The ATLAS collaboration

    2013-01-01

    CERN’s Large Hadron Collider (LHC) is the highest energy proton-proton collider, providing also the highest instantaneous luminosity as a hadron collider. Bunch crossings occurred every 50 ns in 2012 runs. Amongst of which the online event selection system should reduce the event recording rate down to a few 100 Hz, while events are in a harsh condition with many overlapping proton-proton collisions occurring in a same bunch crossing. Muons often provide an important and clear signature of physics processes that are searched for, for instance as in the discovery of Higgs particle in year 2012. The ATLAS experiment deploys a three-levels processing scheme at online. The level-1 muon trigger system gets its input from fast muon trigger detectors. Fast sector logic boards select muon candidates, which are passed via an interface board to the central trigger processor and then to the High Level Trigger (HLT). The muon HLT is purely software based and encompasses a level-2 (L2) trigger followed by an event filte...

  20. Alpine debris flows triggered by a 28 July 1999 thunderstorm in the central Front Range, Colorado

    Science.gov (United States)

    Godt, J.W.; Coe, J.A.

    2007-01-01

    On 28 July 1999, about 480 alpine debris flows were triggered by an afternoon thunderstorm along the Continental Divide in Clear Creek and Summit counties in the central Front Range of Colorado. The thunderstorm produced about 43??mm of rain in 4??h, 35??mm of which fell in the first 2??h. Several debris flows triggered by the storm impacted Interstate Highway 70, U.S. Highway 6, and the Arapahoe Basin ski area. We mapped the debris flows from color aerial photography and inspected many of them in the field. Three processes initiated debris flows. The first process initiated 11% of the debris flows and involved the mobilization of shallow landslides in thick, often well vegetated, colluvium. The second process, which was responsible for 79% of the flows, was the transport of material eroded from steep unvegetated hillslopes via a system of coalescing rills. The third, which has been termed the "firehose effect," initiated 10% of the debris flows and occurred where overland flow became concentrated in steep bedrock channels and scoured debris from talus deposits and the heads of debris fans. These three processes initiated high on steep hillsides (> 30??) in catchments with small contributing areas (< 8000??m2), however, shallow landslides occurred on slopes that were significantly less steep than either overland flow process. Based on field observations and examination of soils mapping of the northern part of the study area, we identified a relation between the degree of soil development and the process type that generated debris flows. In general, areas with greater soil development were less likely to generate runoff and therefore less likely to generate debris flows by the firehose effect or by rilling. The character of the surficial cover and the spatially variable hydrologic response to intense rainfall, rather than a threshold of contributing area and topographic slope, appears to control the initiation process in the high alpine of the Front Range. Because

  1. Chronic whiplash and central sensitization; an evaluation of the role of a myofascial trigger points in pain modulation

    Directory of Open Access Journals (Sweden)

    Freeman Michael D

    2009-04-01

    Full Text Available Abstract Objective it has been established that chronic neck pain following whiplash is associated with the phenomenon of central sensitization, in which injured and uninjured parts of the body exhibit lowered pain thresholds due to an alteration in central pain processing. it has furthermore been hypothesized that peripheral sources of nociception in the muscles may perpetuate central sensitization in chronic whiplash. the hypothesis explored in the present study was whether myofascial trigger points serve as a modulator of central sensitization in subjects with chronic neck pain. Design controlled case series. Setting outpatient chronic pain clinic. Subjects seventeen patients with chronic and intractable neck pain and 10 healthy controls without complaints of neck pain. Intervention symptomatic subjects received anesthetic infiltration of myofascial trigger points in the upper trapezius muscles and controls received the anesthetic in the thigh. Outcome measures: pre and post injection cervical range of motion, pressure pain thresholds (ppt over the infraspinatus, wrist extensor, and tibialis anterior muscles. sensitivity to light (photophobia and subjects' perception of pain using a visual analog scale (vas were also evaluated before and after injections. only the ppt was evaluated in the asymptomatic controls. Results immediate (within 1 minute alterations in cervical range of motion and pressure pain thresholds were observed following an average of 3.8 injections with 1–2 cc of 1% lidocaine into carefully identified trigger points. cervical range of motion increased by an average of 49% (p = 0.000 in flexion and 44% (p = 0.001 in extension, 47% (p = 0.000 and 28% (p Conclusion the present data suggest that myofascial trigger points serve to perpetuate lowered pain thresholds in uninjured tissues. additionally, it appears that lowered pain thresholds associated with central sensitization can be immediately reversed, even when associated

  2. Physics performances with the new ATLAS Level-1 Topological trigger in the LHC High-Luminosity Era

    CERN Document Server

    Artz, Sebastian; The ATLAS collaboration

    2016-01-01

    The ATLAS trigger system aim at reducing the 40 MHz protons collision event rate to a manageable event storage rate of 1 kHz, preserving events with valuable physics meaning. The Level-1 trigger is the first rate-reducing step in the ATLAS trigger system, with an output rate of 100 kHz and decision latency of less than 2.5 micro seconds. It is composed of the calorimeter trigger, muon trigger and central trigger processor. During the last upgrade, a new electronics element was introduced to Level-1: L1Topo, the Topological Processor System. It will make it possible to use detailed realtime information from the Level-1 calorimeter and muon triggers, processed in individual state of the art FPGA processors to determine angles between jets and/or leptons and calculate kinematic variables based on lists of selected/sorted objects. Over hundred VHDL algorithms are producing trigger outputs to be incorporated into the central trigger processor. Such information will be essential to improve background rejection and ...

  3. A second level trigger system based on a microprocessor array

    Energy Technology Data Exchange (ETDEWEB)

    Sakamoto, H.; Watase, Y. (National Laboratory for High Energy Physics, KEK, 1-1 Oho, Tsukuba, Ibaraki 305 (Japan)); Korhonen, T. (Department of High Energy Physics, Helsinki University, Siltavuorenpenger 20 D, 00170 Helsinki (Finland)); Taketani, A. (Department of Physics, Hiroshima University, Higashi-senda-machi, Naka-ku, Hiroshima 730 (Japan))

    1990-08-01

    A second level trigger system is being introduced to the KEK TRISTAN VENUS experiment. The system consists of a TRANSPUTER array of 2-dimensional lattice and several kinds of interfacing modulus. TRANSPUTER chips are mounted on these modules. Trigger data are all transferred using high speed serial links which connect the processors. The system is applied to the central drift chamber to perform track finding using its hit information. A data acquistion module attached to each FASTBUS crate gathers the hit wire pattern and transfers it to the processor array through its link. Track finding is performed in parallel form by sharing the data. The results is also transferred to a master FPI (FASTBUS Processor Interface) via a link. It takes less than 1 millisecond to distribute pattern data into the array and fast tracking less than 8 milliseconds was achieved.

  4. The ATLAS Muon Trigger - Experience and Performance in the first 3 years of LHC pp runs

    CERN Document Server

    Ventura, A; The ATLAS collaboration

    2013-01-01

    The ATLAS experiment at CERN's Large Hadron Collider (LHC) deploys three-levels processing scheme for the trigger system. The level-1 muon trigger system gets its input from fast muon trigger detectors. Fast sector logic boards select muon candidates, which are passed via an interface board to the central trigger processor and then to the High Level Trigger (HLT). The muon HLT is purely software based and encompasses a level-2 trigger followed by an event filter for a staged trigger approach. It has access to the data of the precision muon detectors and other detector elements to refine the muon hypothesis. The ATLAS experiment has taken data with high efficiency continuously over entire running periods form 2010 to 2012, for which sophisticated triggers to guard the highest physics output while reducing effectively the event rate were mandatory. The ATLAS Muon trigger has successfully adapted to this changing environment. The selection strategy has been optimized for the various physics analysis involving mu...

  5. The first-level trigger of ATLAS

    CERN Document Server

    Haller, J; Aielli, G; Aloisio, A; Alviggi, M G; Aprodu, V; Ask, S; Barnett, B M; Bartos, D; Bauss, B; Belkin, A; Benhammou, Ya; Bocci, V; Booth, J R A; Brambilla, Elena; Brawn, I P; Bressler, S; Buda, S; Bohm, C; Canale, V; Caracinha, D; Cardarelli, R; Carlino, G; Cataldi, G; Charlton, D G; Chiodi, G; Ciapetti, G; Constantin, S; Conventi, F; Davis, A O; De Asmundis, R; De Pedis, D; De Seixas, J M; Della Pietra, M; Della Volpe, D; Di Ciaccio, A; Di Girolamo, A; Di Mattia, A; Di Simone, A; Distante, L; Dogaru, M; Edwards, J; Eisenhandler, E F; Ellis, Nick; Etzion, E; Farthouat, P; Fukunaga, C; Föhlisch, F; Gee, C N P; Gennari, E; Geweniger, C; Gillman, A R; Gorini, E; Grancagnolo, F; Gällnö, P; Haas, S; Hanke, P; Harel, A; Hasegawa, Y; Hellman, S; Hidvegi, A; Hillier, S J; Ichimiya, R; Iengo, P; Ikeno, M; Ishino, M; Iwasaki, H; Izzo, V; Kagawa, S; Kanaya, N; Kawagoe, K; Kawamoto, T; Kiyamura, H; Kluge, E -E; Kobayashi, T; Krasznahorkay, A; Kurashige, H; Kuwabara, T; Landon, M; Lellouch, D; Levinson, L; Lifshitz, R; Luci, C; Lupu, N; Magureanu, C; Mahboubi, K; Mahout, G; Meier, K; Migliaccio, A; Mikenberg, G; Mirea, A; Moye, T H; Nagano, K; Nisati, A; Nomachi, M; Nomoto, H; Nozaki, M; Ochi, A; Ogata, T; Omachi, C; Oshita, H; Pasqualucci, E; Pastore, F; Patricelli, S; Pauly, T; Pectu, M; Perantoni, M; Perera, V J O; Perrino, R; Pessoa-Lima, H; Petrolo, E; Primavera, M; Prodan, L; Qian, W; Rieke, S; Rusu, A; Rühr, F; Sakamoto, H; Salamon, A; Sankey, D P C; Santonico, R; Sasaki, O; Schmitt, K; Schuler, G; Schultz-Coulon, H C; Schäfer, U; Sekhniaidze, G; Silverstein, S; Spagnolo, S; Spila, F; Spiwoks, R; Staley, R J; Sugaya, Y; Sugimoto, T; Takeda, H; Takeshita, T; Tanaka, S; Tapprogge, S; Tarem, S; Thomas, J P; Trefzger, T; Typaldos, D; Uroseviteanu, C; Vari, R; Veneziano, Stefano; Watkins, P M; Watson, A; Weber, G A; Weber, P; Wengler, T; Woerling, E E; Yamaguchi, Y; Yasu, Y; Zanello, L

    2006-01-01

    Due to the huge interaction rates and the tough experimental environment of pp collisions at a centre-of-mass energy sqrt(s)=14 TeV and luminosities of up to 10^34cm^-2s^-1, one of the experimental challenges at the LHC is the triggering of interesting events. In the ATLAS experiment a three-level trigger system is foreseen for this purpose. The first-level trigger is implemented in custom hardware and has been designed to reduce the data rate from the initial bunch-crossing rate of 40MHz to around 75 kHz. Its event selection is based on information from the calorimeters and dedicated muon detectors. This article gives an overview over the full first-level trigger system including the Calorimeter Trigger, the Muon Trigger and the Central Trigger Processor. In addition, recent results are reported that have been obtained from test-beam studies performed at CERN where the full first-level trigger chain was established successfully for the first time and used to trigger the read-out of up to nine ATLAS sub-detec...

  6. The ATLAS Muon and Tau Trigger

    CERN Document Server

    Dell'Asta, L; The ATLAS collaboration

    2013-01-01

    [Muon] The ATLAS experiment at CERN's Large Hadron Collider (LHC) deploys a three-levels processing scheme for the trigger system. The level-1 muon trigger system gets its input from fast muon trigger detectors. Fast sector logic boards select muon candidates, which are passed via an interface board to the central trigger processor and then to the High Level Trigger (HLT). The muon HLT is purely software based and encompasses a level-2 (L2) trigger followed by an event filter (EF) for a staged trigger approach. It has access to the data of the precision muon detectors and other detector elements to refine the muon hypothesis. Trigger-specific algorithms were developed and are used for the L2 to increase processing speed for instance by making use of look-up tables and simpler algorithms, while the EF muon triggers mostly benefit from offline reconstruction software to obtain most precise determination of the track parameters. There are two algorithms with different approaches, namely inside-out and outside-in...

  7. Landslides triggered by earthquakes in the central Mississippi Valley, Tennessee and Kentucky

    Science.gov (United States)

    Jibson, Randall W.; Keefer, David K.

    1988-01-01

    We mapped 221 large (more than 200 ft across) landslides of three morphologically distinct types on the bluffs bordering the Mississippi alluvial plain in western Tennessee and Kentucky Old coherent slides (146 landslides, or 66 percent of the total) include translational block slides and single and multiple-block rotational slumps, all of which are covered by mature vegetation and have eroded features; no active analogs exist in the area. Earth flows (51 landslides, or 23 percent of the total) are also largely revegetated and eroded, though a few active earth flows are present on bluffs that have been cleared of vegetation. Young rotational slumps (24 landslides, or 11 percent of the total) form solely along actively eroding near-river bluffs and are the only active or recently active landslides in the area. Two investigations conducted around 1900 indicate that the old coherent slides, in at least part of the area, formed during the 1811-12 earthquakes. The present investigation uses dendrochronology, geomorphology, historic topographic maps, local historical accounts, and comparisons with landslides triggered by other earthquakes to show that most or all of the old coherent slides and earth flows formed during the 1811-12 New Madrid earthquakes. Evidence clearly indicates that the only large, aseismic landslide activity in the area results from fluvial undercutting of near-river bluffs. This erosion of the base of the bluffs triggers slumps that are morphologically distinct from the old slumps on bluffs away from the river. Our conclusions are consistent with the findings of other recent investigations of the same landslides that indicate extensive seismic triggering of coherent slides and earth flows during the 1811-12 New Madrid earthquakes.

  8. Stimulation of the Basal and Central Amygdala in the Mustached Bat Triggers Echolocation and Agonistic Vocalizations within Multimodal Output

    Directory of Open Access Journals (Sweden)

    Jie eMa

    2014-03-01

    Full Text Available The neural substrate for the perception of vocalization is relatively well described, but we know much less about how the timing and specificity of vocalizations is tightly coupled with audiovocal communication behavior. In many vocal species, well-timed vocalizations accompany fear, vigilance and aggression. These emotive responses likely originate within the amygdala and other limbic structures, but the organization of motor outputs for triggering species-appropriate behaviors remains unclear. We performed electrical microstimulation at 461 highly restricted loci within the basal and central amygdala in awake mustached bats. At a subset of these sites, high frequency stimulation with weak constant current pulses presented at near-threshold levels triggered vocalization of either echolocation pulses or social calls. At the vast majority of locations, microstimulation produced a constellation of changes in autonomic and somatomotor outputs. These changes included widespread co-activation of significant tachycardia and hyperventilation and/or rhythmic ear pinna movements. In a few locations, responses were constrained to vocalization and/or pinna movements despite increases in the intensity of stimulation. The probability of eliciting echolocation pulses versus social calls decreased in a medial-posterior to anterolateral direction within the centrobasal amygdala. Microinjections of kainic acid at stimulation sites confirmed the contribution of cellular activity rather than fibers-of-passage in the control of multimodal outputs. The results suggest that multimodal clusters of neurons may simultaneously modulate the activity of multiple central pattern generators present within the brainstem.

  9. Proceedings of the workshop on triggering and data acquisition for experiments at the Supercollider

    Energy Technology Data Exchange (ETDEWEB)

    Donaldson, R. [ed.

    1989-04-01

    This meeting covered the following subjects: triggering requirements for SSC physics; CDF level 3 trigger; D0 trigger design; AMY trigger systems; Zeus calorimeter first level trigger; data acquisition for the Zeus Central Tracking Detector; trigger and data acquisition aspects for SSC tracking; data acquisition systems for the SSC; validating triggers in CDF level 3; optical data transmission at SSC; time measurement system at SSC; SSC/BCD data acquisition system; microprocessors and other processors for triggering and filtering at the SSC; data acquisition, event building, and on-line processing; LAA real-time benchmarks; object-oriented system building at SSC; and software and project management. Selected papers are indexed separately for inclusion in the Energy Science and Technology Database.

  10. Sequence information signal processor

    Science.gov (United States)

    Peterson, John C.; Chow, Edward T.; Waterman, Michael S.; Hunkapillar, Timothy J.

    1999-01-01

    An electronic circuit is used to compare two sequences, such as genetic sequences, to determine which alignment of the sequences produces the greatest similarity. The circuit includes a linear array of series-connected processors, each of which stores a single element from one of the sequences and compares that element with each successive element in the other sequence. For each comparison, the processor generates a scoring parameter that indicates which segment ending at those two elements produces the greatest degree of similarity between the sequences. The processor uses the scoring parameter to generate a similar scoring parameter for a comparison between the stored element and the next successive element from the other sequence. The processor also delivers the scoring parameter to the next processor in the array for use in generating a similar scoring parameter for another pair of elements. The electronic circuit determines which processor and alignment of the sequences produce the scoring parameter with the highest value.

  11. The Cell Processor

    OpenAIRE

    Hoefler, Torsten

    2006-01-01

    Mainstream processor development is mostly targeted at compatibility and continuity. Thus, the processor market is dominated by x86 compatible CPUs since more than two decades now. Several new concepts tried to gain some market share, but it was not possible to overtake the old compatibility driven concepts. A group of three corporates tries another way to come into the market with a new idea, the cell design. The cell processor is a new try to leverage the increasing amount...

  12. Embedded Processor Laboratory

    Data.gov (United States)

    Federal Laboratory Consortium — The Embedded Processor Laboratory provides the means to design, develop, fabricate, and test embedded computers for missile guidance electronics systems in support...

  13. A Video Control Processor

    OpenAIRE

    Tripp, Gerald

    1992-01-01

    This report describes the design and implementation of a simple microprogrammable processor with a fast response time to external events. This processor was designed as a controller for a testbench video system capable of performing a number of functions such as windowing and frame rate conversion.

  14. BAT trigger 700791 (the possible GRB 160622A) is 2E 1613.5-5053, the central source in SNR RCW103

    Science.gov (United States)

    D'Ai, A.; Evans, P. A.; Gehrels, N.; Gronwall, C.; Kennea, J. A.; Lien, A. Y.; Marshall, F. E.; Maselli, A.; Sakamoto, T.; Siegel, M. H.

    2016-06-01

    Swift has gathered 5.8 ks of WT mode data and 463 s of PC mode data on the field of the BAT trigger 700791 (= possible GRB 160622A, GCN Circ. 19547). The XRT image is dominated by diffuse emission from the supernova remnant RCW 103 (Frank et al., ApJ, 2015, 810,113), with a bright central source at RA,Dec.

  15. Adaptive signal processor

    International Nuclear Information System (INIS)

    An experimental, general purpose adaptive signal processor system has been developed, utilizing a quantized (clipped) version of the Widrow-Hoff least-mean-square adaptive algorithm developed by Moschner. The system accommodates 64 adaptive weight channels with 8-bit resolution for each weight. Internal weight update arithmetic is performed with 16-bit resolution, and the system error signal is measured with 12-bit resolution. An adapt cycle of adjusting all 64 weight channels is accomplished in 8 μsec. Hardware of the signal processor utilizes primarily Schottky-TTL type integrated circuits. A prototype system with 24 weight channels has been constructed and tested. This report presents details of the system design and describes basic experiments performed with the prototype signal processor. Finally some system configurations and applications for this adaptive signal processor are discussed

  16. Sub-nanosecond clock synchronization and trigger management in the nuclear physics experiment AGATA

    Science.gov (United States)

    Bellato, M.; Bortolato, D.; Chavas, J.; Isocrate, R.; Rampazzo, G.; Triossi, A.; Bazzacco, D.; Mengoni, D.; Recchia, F.

    2013-07-01

    The new-generation spectrometer AGATA, the Advanced GAmma Tracking Array, requires sub-nanosecond clock synchronization among readout and front-end electronics modules that may lie hundred meters apart. We call GTS (Global Trigger and Synchronization System) the infrastructure responsible for precise clock synchronization and for the trigger management of AGATA. It is made of a central trigger processor and nodes, connected in a tree structure by means of optical fibers operated at 2Gb/s. The GTS tree handles the synchronization and the trigger data flow, whereas the trigger processor analyses and eventually validates the trigger primitives centrally. Sub-nanosecond synchronization is achieved by measuring two different types of round-trip times and by automatically correcting for phase-shift differences. For a tree of depth two, the peak-to-peak clock jitter at each leaf is 70 ps; the mean phase difference is 180 ps, while the standard deviation over such phase difference, namely the phase equalization repeatability, is 20 ps. The GTS system has run flawlessly for the two-year long AGATA campaign, held at the INFN Legnaro National Laboratories, Italy, where five triple clusters of the AGATA sub-array were coupled with a variety of ancillary detectors.

  17. Timing, Trigger and Control Systems for LHC Detectors

    CERN Multimedia

    2002-01-01

    \\\\ \\\\At the LHC, precise bunch-crossing clock and machine orbit signals must be broadcast over distances of several km from the Prevessin Control Room to the four experiment areas and other destinations. At the LHC experiments themselves, quite extensive distribution systems are also required for the transmission of timing, trigger and control (TTC) signals to large numbers of front-end electronics controllers from a single location in the vicinity of the central trigger processor. The systems must control the detector synchronization and deliver the necessary fast signals and messages that are phased with the LHC clock, orbit or bunch structure. These include the bunch-crossing clock, level-1 trigger decisions, bunch and event numbers, as well as test signals and broadcast commands. A common solution to this TTC system requirement is expected to result in important economies of scale and permit a rationalization of the development, operational and support efforts required. LHC Common Project RD12 is developi...

  18. Array processor architecture

    Science.gov (United States)

    Barnes, George H. (Inventor); Lundstrom, Stephen F. (Inventor); Shafer, Philip E. (Inventor)

    1983-01-01

    A high speed parallel array data processing architecture fashioned under a computational envelope approach includes a data base memory for secondary storage of programs and data, and a plurality of memory modules interconnected to a plurality of processing modules by a connection network of the Omega gender. Programs and data are fed from the data base memory to the plurality of memory modules and from hence the programs are fed through the connection network to the array of processors (one copy of each program for each processor). Execution of the programs occur with the processors operating normally quite independently of each other in a multiprocessing fashion. For data dependent operations and other suitable operations, all processors are instructed to finish one given task or program branch before all are instructed to proceed in parallel processing fashion on the next instruction. Even when functioning in the parallel processing mode however, the processors are not locked-step but execute their own copy of the program individually unless or until another overall processor array synchronization instruction is issued.

  19. The ARGUS vertex trigger

    International Nuclear Information System (INIS)

    A fast second level trigger has been developed for the ARGUS experiment which recognizes tracks originating from the interaction region. The processor compares the hits in the ARGUS Micro Vertex Drift Chamber to 245760 masks stored in random access memories. The masks which are fully defined in three dimensions are able to reject tracks originating in the wall of the narrow beampipe of 10.5 mm radius. (orig.)

  20. Hardware multiplier processor

    Science.gov (United States)

    Pierce, Paul E.

    1986-01-01

    A hardware processor is disclosed which in the described embodiment is a memory mapped multiplier processor that can operate in parallel with a 16 bit microcomputer. The multiplier processor decodes the address bus to receive specific instructions so that in one access it can write and automatically perform single or double precision multiplication involving a number written to it with or without addition or subtraction with a previously stored number. It can also, on a single read command automatically round and scale a previously stored number. The multiplier processor includes two concatenated 16 bit multiplier registers, two 16 bit concatenated 16 bit multipliers, and four 16 bit product registers connected to an internal 16 bit data bus. A high level address decoder determines when the multiplier processor is being addressed and first and second low level address decoders generate control signals. In addition, certain low order address lines are used to carry uncoded control signals. First and second control circuits coupled to the decoders generate further control signals and generate a plurality of clocking pulse trains in response to the decoded and address control signals.

  1. A afferent fibers are involved in the pathology of central changes in the spinal dorsal horn associated with myofascial trigger spots in rats.

    Science.gov (United States)

    Meng, Fei; Ge, Hong-You; Wang, Yong-Hui; Yue, Shou-Wei

    2015-11-01

    A afferent fibers have been reported to participate in the development of the central sensitization induced by inflammation and injuries. Current evidence suggests that myofascial trigger points (MTrPs) induce central sensitization in the related spinal dorsal horn, and clinical studies indicate that A fibers are associated with pain behavior. Because most of these clinical studies applied behavioral indexes, objective evidence is needed. Additionally, MTrP-related neurons in dorsal root ganglia and the spinal ventral horn have been reported to be smaller than normal, and these neurons were considered to be related to A fibers. To confirm the role of A fibers in MTrP-related central changes in the spinal dorsal horn, we studied central sensitization as well as the size of neurons associated with myofascial trigger spots (MTrSs, equivalent to MTrPs in humans) in the biceps femoris muscle of rats and provided some objective morphological evidence. Cholera toxin B subunit-conjugated horseradish peroxidase was applied to label the MTrS-related neurons, and tetrodotoxin was used to block A fibers specifically. The results showed that in the spinal dorsal horn associated with MTrS, the expression of glutamate receptor (mGluR1α/mGluR5/NMDAR1) increased, while the mean size of MTrS-related neurons was smaller than normal. After blocking A fibers, these changes reversed to some extent. Therefore, we concluded that A fibers participated in the development and maintenance of the central sensitization induced by MTrPs and were related to the mean size of neurons associated with MTrPs in the spinal dorsal horn.

  2. The Run Control System and the Central Hint and Information Processor of the Data Acquisition System of the ATLAS Experiment at the LHC

    CERN Document Server

    Anders, G; The ATLAS collaboration; Lehmann Miotto, G; Magnoni, L

    2014-01-01

    The Trigger and Data Acquisition (TDAQ) system of the ATLAS detector is composed of a large number of distributed hardware and software components (about 3000 machines and more than 15000 concurrent processes at the end of LHC’s Run I) which in a coordinated manner provide the data-taking functionality of the overall system. The Run Control (RC) system steers the data acquisition by starting and stopping processes and by carrying all data-taking elements through well-defined states in a coherent way (finite state machine pattern). The RC is organized as a hierarchical tree (run control tree) of run controllers following the functional de-composition into systems and sub-systems of the ATLAS detector. During the LHC Long Shutdown 1 (LS1) the RC has been completely re-designed and re-implemented in order to better fulfill the new requirements which emerged during the LHC Run 1 and were not foreseen during the initial design phase, and in order to improve the error management and recovery mechanisms. Indeed gi...

  3. The Milstar Advanced Processor

    Science.gov (United States)

    Tjia, Khiem-Hian; Heely, Stephen D.; Morphet, John P.; Wirick, Kevin S.

    The Milstar Advanced Processor (MAP) is a 'drop-in' replacement for its predecessor which preserves existing interfaces with other Milstar satellite processors and minimizes the impact of such upgrading to already-developed application software. In addition to flight software development, and hardware development that involves the application of VHSIC technology to the electrical design, the MAP project is developing two sophisticated and similar test environments. High density RAM and ROM are employed by the MAP memory array. Attention is given to the fine-pitch VHSIC design techniques and lead designs used, as well as the tole of TQM and concurrent engineering in the development of the MAP manufacturing process.

  4. Beyond processor sharing

    NARCIS (Netherlands)

    Aalto, S.; Ayesta, U.; Borst, S.C.; Misra, V.; Núñez Queija, R.

    2007-01-01

    While the (Egalitarian) Processor-Sharing (PS) discipline offers crucial insights in the performance of fair resource allocation mechanisms, it is inherently limited in analyzing and designing differentiated scheduling algorithms such as Weighted Fair Queueing and Weighted Round-Robin. The Discrimin

  5. The Level 0 Pixel Trigger System for the ALICE Silicon Pixel Detector: implementation, testing and commissioning

    CERN Document Server

    Aglieri-Rinella, G

    2008-01-01

    The ALICE Silicon Pixel Detector transmits 1200 Fast-OR signals every 100 ns on 120 optical readout channels. They indicate the presence of at least one hit in the pixel matrix of each readout chip. The ALICE Level 0 Pixel Trigger System extracts them, processes them and delivers an input signal to the Central Trigger Processor for the first level trigger decision within a latency of 800 ns. This paper describes tests and measurements made on the system during the qualification and commissioning phases. These included Bit Error Rate tests on the Fast-OR data path, the measurement of the overall process latency and the recording of calibration data with cosmic rays. The first results of the operation of the Pixel Trigger System with the SPD detector in the ALICE experiment are also presented.

  6. Innovative communication processors: A survey

    OpenAIRE

    Gunningberg, Per

    1987-01-01

    Some existing innovative processors for execution of multilayer protocols are surveyed in order to identify performance limits and processor architectural trade-offs. The survey is restricted to packet or message handling processors with dedicated software and/or hardware. The processors are compared with respect to; performance, i.e. throughput and delay, to available protocols, and to implementation trade-offs, i.e. modularity, service access point accessibility, interface to host machine, ...

  7. Progress on the Level-1 Calorimeter Trigger

    CERN Multimedia

    Eric Eisenhandler

    The Level-1 Calorimeter Trigger (L1Calo) has recently passed a number of major hurdles. The various electronic modules that make up the trigger are either in full production or are about to be, and preparations in the ATLAS pit are well advanced. L1Calo has three main subsystems. The PreProcessor converts analogue calorimeter signals to digital, associates the rather broad trigger pulses with the correct proton-proton bunch crossing, and does a final calibration in transverse energy before sending digital data streams to the two algorithmic trigger processors. The Cluster Processor identifies and counts electrons, photons and taus, and the Jet/Energy-sum Processor looks for jets and also sums missing and total transverse energy. Readout drivers allow the performance of the trigger to be monitored online and offline, and also send region-of-interest information to the Level-2 Trigger. The PreProcessor (Heidelberg) is the L1Calo subsystem with the largest number of electronic modules (124), and most of its fu...

  8. Trigger finger

    Science.gov (United States)

    Digital stenosing tenosynovitis; Trigger digit; Trigger finger release ... JH. Carpal tunnel syndrome, ulnar tunnel syndrome, and stenosing tenosynovitis. In: Canale ST, Beaty JH, eds. Campbell's Operative ...

  9. New Generation Processor Architecture Research

    Institute of Scientific and Technical Information of China (English)

    Chen Hongsong(陈红松); Hu Mingzeng; Ji Zhenzhou

    2003-01-01

    With the rapid development of microelectronics and hardware,the use of ever faster micro-processors and new architecture must be continued to meet tomorrow′s computing needs. New processor microarchitectures are needed to push performance further and to use higher transistor counts effectively.At the same time,aiming at different usages,the processor has been optimized in different aspects,such as high performace,low power consumption,small chip area and high security. SOC (System on chip)and SCMP (Single Chip Multi Processor) constitute the main processor system architecture.

  10. Multimode power processor

    Science.gov (United States)

    O'Sullivan, George A.; O'Sullivan, Joseph A.

    1999-01-01

    In one embodiment, a power processor which operates in three modes: an inverter mode wherein power is delivered from a battery to an AC power grid or load; a battery charger mode wherein the battery is charged by a generator; and a parallel mode wherein the generator supplies power to the AC power grid or load in parallel with the battery. In the parallel mode, the system adapts to arbitrary non-linear loads. The power processor may operate on a per-phase basis wherein the load may be synthetically transferred from one phase to another by way of a bumpless transfer which causes no interruption of power to the load when transferring energy sources. Voltage transients and frequency transients delivered to the load when switching between the generator and battery sources are minimized, thereby providing an uninterruptible power supply. The power processor may be used as part of a hybrid electrical power source system which may contain, in one embodiment, a photovoltaic array, diesel engine, and battery power sources.

  11. Autoimmune central diabetes insipidus in a patient with ureaplasma urealyticum infection and review on new triggers of immune response.

    Science.gov (United States)

    Murdaca, Giuseppe; Russo, Rodolfo; Spanò, Francesca; Ferone, Diego; Albertelli, Manuela; Schenone, Angelo; Contatore, Miriam; Guastalla, Andrea; De Bellis, Annamaria; Garibotto, Giacomo; Puppo, Francesco

    2015-12-01

    Diabetes insipidus is a disease in which large volumes of dilute urine (polyuria) are excreted due to vasopressin (AVP) deficiency [central diabetes insipidus (CDI)] or to AVP resistance (nephrogenic diabetes insipidus). In the majority of patients, the occurrence of CDI is related to the destruction or degeneration of neurons of the hypothalamic supraoptic and paraventricular nuclei. The most common and well recognized causes include local inflammatory or autoimmune diseases, vascular disorders, Langerhans cell histiocytosis (LCH), sarcoidosis, tumors such as germinoma/craniopharyngioma or metastases, traumatic brain injuries, intracranial surgery, and midline cerebral and cranial malformations. Here we have the opportunity to describe an unusual case of female patient who developed autoimmune CDI following ureaplasma urealyticum infection and to review the literature on this uncommon feature. Moreover, we also discussed the potential mechanisms by which ureaplasma urealyticum might favor the development of autoimmune CDI.

  12. Fuel processors for fuel cell APU applications

    Science.gov (United States)

    Aicher, T.; Lenz, B.; Gschnell, F.; Groos, U.; Federici, F.; Caprile, L.; Parodi, L.

    The conversion of liquid hydrocarbons to a hydrogen rich product gas is a central process step in fuel processors for auxiliary power units (APUs) for vehicles of all kinds. The selection of the reforming process depends on the fuel and the type of the fuel cell. For vehicle power trains, liquid hydrocarbons like gasoline, kerosene, and diesel are utilized and, therefore, they will also be the fuel for the respective APU systems. The fuel cells commonly envisioned for mobile APU applications are molten carbonate fuel cells (MCFC), solid oxide fuel cells (SOFC), and proton exchange membrane fuel cells (PEMFC). Since high-temperature fuel cells, e.g. MCFCs or SOFCs, can be supplied with a feed gas that contains carbon monoxide (CO) their fuel processor does not require reactors for CO reduction and removal. For PEMFCs on the other hand, CO concentrations in the feed gas must not exceed 50 ppm, better 20 ppm, which requires additional reactors downstream of the reforming reactor. This paper gives an overview of the current state of the fuel processor development for APU applications and APU system developments. Furthermore, it will present the latest developments at Fraunhofer ISE regarding fuel processors for high-temperature fuel cell APU systems on board of ships and aircrafts.

  13. Distributed processor allocation for launching applications in a massively connected processors complex

    Science.gov (United States)

    Pedretti, Kevin

    2008-11-18

    A compute processor allocator architecture for allocating compute processors to run applications in a multiple processor computing apparatus is distributed among a subset of processors within the computing apparatus. Each processor of the subset includes a compute processor allocator. The compute processor allocators can share a common database of information pertinent to compute processor allocation. A communication path permits retrieval of information from the database independently of the compute processor allocators.

  14. Dynamic triggering

    Science.gov (United States)

    Hill, David P.; Prejean, Stephanie; Schubert, Gerald

    2015-01-01

    Dynamic stresses propagating as seismic waves from large earthquakes trigger a spectrum of responses at global distances. In addition to locally triggered earthquakes in a variety of tectonic environments, dynamic stresses trigger tectonic (nonvolcanic) tremor in the brittle–plastic transition zone along major plate-boundary faults, activity changes in hydrothermal and volcanic systems, and, in hydrologic domains, changes in spring discharge, water well levels, soil liquefaction, and the eruption of mud volcanoes. Surface waves with periods of 15–200 s are the most effective triggering agents; body-wave trigger is less frequent. Triggering dynamic stresses can be < 1 kPa.

  15. AMD's 64-bit Opteron processor

    CERN Document Server

    CERN. Geneva

    2003-01-01

    This talk concentrates on issues that relate to obtaining peak performance from the Opteron processor. Compiler options, memory layout, MPI issues in multi-processor configurations and the use of a NUMA kernel will be covered. A discussion of recent benchmarking projects and results will also be included.BiographiesDavid RichDavid directs AMD's efforts in high performance computing and also in the use of Opteron processors...

  16. Spaceborne Processor Array

    Science.gov (United States)

    Chow, Edward T.; Schatzel, Donald V.; Whitaker, William D.; Sterling, Thomas

    2008-01-01

    A Spaceborne Processor Array in Multifunctional Structure (SPAMS) can lower the total mass of the electronic and structural overhead of spacecraft, resulting in reduced launch costs, while increasing the science return through dynamic onboard computing. SPAMS integrates the multifunctional structure (MFS) and the Gilgamesh Memory, Intelligence, and Network Device (MIND) multi-core in-memory computer architecture into a single-system super-architecture. This transforms every inch of a spacecraft into a sharable, interconnected, smart computing element to increase computing performance while simultaneously reducing mass. The MIND in-memory architecture provides a foundation for high-performance, low-power, and fault-tolerant computing. The MIND chip has an internal structure that includes memory, processing, and communication functionality. The Gilgamesh is a scalable system comprising multiple MIND chips interconnected to operate as a single, tightly coupled, parallel computer. The array of MIND components shares a global, virtual name space for program variables and tasks that are allocated at run time to the distributed physical memory and processing resources. Individual processor- memory nodes can be activated or powered down at run time to provide active power management and to configure around faults. A SPAMS system is comprised of a distributed Gilgamesh array built into MFS, interfaces into instrument and communication subsystems, a mass storage interface, and a radiation-hardened flight computer.

  17. The sources of the shallow, upper plate earthquakes in Central Mexico, and their possible triggering by the subduction earthquakes, 'normal' and slow

    Science.gov (United States)

    Manighetti, I.; Vergnolle, M.; Campillo, M.; Cotton, F.; Thollon, O.

    2008-12-01

    Large earthquakes have broken the Central Mexico upper plate in the historical time (1887, M5.3; 1912, M6.9; 1920, M6.5; 1976, M5.3; 1979, M5.3), but the faults responsible for those earthquakes are not precisely known. Nor is their link with the subduction, especially in terms of possible triggering between subduction and shallow earthquakes. To address those issues, we first identify the major active faults that cut the upper plate, and determine their slip mode and overall organization. For that, we conduct a morphological analysis of the region, based on the use of satellite and topographic images. The upper plate appears dissected by a dense network of hundreds of major active faults, which overall form 2 distinct large-scale systems, named Jalisco and Mexico. The Jalisco system is made of the N-S Colima normal fault system which runs from the coast to the Transmexican Belt (TMB) where it ends in a large fishtail centered on the Chapala Lake. The western branch of the fishtail is made of NW-striking, N-dipping faults that are both normal and left-lateral, while the eastern branch is made of ENE-trending, N-dipping normal faults. The Mexico system resembles a large-scale horsetail. It is made of a major NNW-trending left-lateral strike-slip fault that runs from the coast to the TMB, at the eastern edge of the Oaxaca region. As it enters the TMB, that NNW system connects to a series of E-W, N-dipping, normal-right-lateral faults, while extending further north through a series of NNW, E-dipping normal-left-lateral faults. Together these faults bound to the south and west a series of rhomboidal half-grabens, among those are the basins of Mexico City and Acambay. Mexico City is thus bounded by large active faults but also dissected by smaller ones, both E-W and NNW. The E-W fault system that bounds the Acambay half-graben to the south is likely the one to have ruptured in 1912. Second, we examine whether the subduction interface and the upper plate active faults

  18. Never Trust Your Word Processor

    Science.gov (United States)

    Linke, Dirk

    2009-01-01

    In this article, the author talks about the auto correction mode of word processors that leads to a number of problems and describes an example in biochemistry exams that shows how word processors can lead to mistakes in databases and in papers. The author contends that, where this system is applied, spell checking should not be left to a word…

  19. Embedded Processor Oriented Compiler Infrastructure

    Directory of Open Access Journals (Sweden)

    DJUKIC, M.

    2014-08-01

    Full Text Available In the recent years, research of special compiler techniques and algorithms for embedded processors broaden the knowledge of how to achieve better compiler performance in irregular processor architectures. However, industrial strength compilers, besides ability to generate efficient code, must also be robust, understandable, maintainable, and extensible. This raises the need for compiler infrastructure that provides means for convenient implementation of embedded processor oriented compiler techniques. Cirrus Logic Coyote 32 DSP is an example that shows how traditional compiler infrastructure is not able to cope with the problem. That is why the new compiler infrastructure was developed for this processor, based on research. in the field of embedded system software tools and experience in development of industrial strength compilers. The new infrastructure is described in this paper. Compiler generated code quality is compared with code generated by the previous compiler for the same processor architecture.

  20. ATLAS FTK: Fast Track Trigger

    CERN Document Server

    Volpi, Guido; The ATLAS collaboration

    2015-01-01

    An overview of the ATLAS Fast Tracker processor is presented, reporting the design of the system, its expected performance, and the integration status. The next LHC runs, with a significant increase in instantaneous luminosity, will provide a big challenge to the trigger and data acquisition systems of all the experiments. An intensive use of the tracking information at the trigger level will be important to keep high efficiency in interesting events, despite the increase in multiple p-p collisions per bunch crossing (pile-up). In order to increase the use of tracks within the High Level Trigger (HLT), the ATLAS experiment planned the installation of an hardware processor dedicated to tracking: the Fast TracKer (FTK) processor. The FTK is designed to perform full scan track reconstruction at every Level-1 accept. To achieve this goal, the FTK uses a fully parallel architecture, with algorithms designed to exploit the computing power of custom VLSI chips, the Associative Memory, as well as modern FPGAs. The FT...

  1. Distributed processor systems

    International Nuclear Information System (INIS)

    In recent years, there has been a growing tendency in high-energy physics and in other fields to solve computational problems by distributing tasks among the resources of inter-coupled processing devices and associated system elements. This trend has gained further momentum more recently with the increased availability of low-cost processors and with the development of the means of data distribution. In two lectures, the broad question of distributed computing systems is examined and the historical development of such systems reviewed. An attempt is made to examine the reasons for the existence of these systems and to discern the main trends for the future. The components of distributed systems are discussed in some detail and particular emphasis is placed on the importance of standards and conventions in certain key system components. The ideas and principles of distributed systems are discussed in general terms, but these are illustrated by a number of concrete examples drawn from the context of the high-energy physics environment. (Auth.)

  2. The ATLAS fast tracker processor design

    CERN Document Server

    Volpi, Guido; Albicocco, Pietro; Alison, John; Ancu, Lucian Stefan; Anderson, James; Andari, Nansi; Andreani, Alessandro; Andreazza, Attilio; Annovi, Alberto; Antonelli, Mario; Asbah, Needa; Atkinson, Markus; Baines, J; Barberio, Elisabetta; Beccherle, Roberto; Beretta, Matteo; Biesuz, Nicolo Vladi; Blair, R E; Bogdan, Mircea; Boveia, Antonio; Britzger, Daniel; Bryant, Partick; Burghgrave, Blake; Calderini, Giovanni; Camplani, Alessandra; Cavaliere, Viviana; Cavasinni, Vincenzo; Chakraborty, Dhiman; Chang, Philip; Cheng, Yangyang; Citraro, Saverio; Citterio, Mauro; Crescioli, Francesco; Dawe, Noel; Dell'Orso, Mauro; Donati, Simone; Dondero, Paolo; Drake, G; Gadomski, Szymon; Gatta, Mauro; Gentsos, Christos; Giannetti, Paola; Gkaitatzis, Stamatios; Gramling, Johanna; Howarth, James William; Iizawa, Tomoya; Ilic, Nikolina; Jiang, Zihao; Kaji, Toshiaki; Kasten, Michael; Kawaguchi, Yoshimasa; Kim, Young Kee; Kimura, Naoki; Klimkovich, Tatsiana; Kolb, Mathis; Kordas, K; Krizka, Karol; Kubota, T; Lanza, Agostino; Li, Ho Ling; Liberali, Valentino; Lisovyi, Mykhailo; Liu, Lulu; Love, Jeremy; Luciano, Pierluigi; Luongo, Carmela; Magalotti, Daniel; Maznas, Ioannis; Meroni, Chiara; Mitani, Takashi; Nasimi, Hikmat; Negri, Andrea; Neroutsos, Panos; Neubauer, Mark; Nikolaidis, Spiridon; Okumura, Y; Pandini, Carlo; Petridou, Chariclia; Piendibene, Marco; Proudfoot, James; Rados, Petar Kevin; Roda, Chiara; Rossi, Enrico; Sakurai, Yuki; Sampsonidis, Dimitrios; Saxon, James; Schmitt, Stefan; Schoening, Andre; Shochet, Mel; Shoijaii, Jafar; Soltveit, Hans Kristian; Sotiropoulou, Calliope-Louisa; Stabile, Alberto; Swiatlowski, Maximilian J; Tang, Fukun; Taylor, Pierre Thor Elliot; Testa, Marianna; Tompkins, Lauren; Vercesi, V; Wang, Rui; Watari, Ryutaro; Zhang, Jianhong; Zeng, Jian Cong; Zou, Rui; Bertolucci, Federico

    2015-01-01

    The extended use of tracking information at the trigger level in the LHC is crucial for the trigger and data acquisition (TDAQ) system to fulfill its task. Precise and fast tracking is important to identify specific decay products of the Higgs boson or new phenomena, as well as to distinguish the contributions coming from the many collisions that occur at every bunch crossing. However, track reconstruction is among the most demanding tasks performed by the TDAQ computing farm; in fact, complete reconstruction at full Level-1 trigger accept rate (100 kHz) is not possible. In order to overcome this limitation, the ATLAS experiment is planning the installation of a dedicated processor, the Fast Tracker (FTK), which is aimed at achieving this goal. The FTK is a pipeline of high performance electronics, based on custom and commercial devices, which is expected to reconstruct, with high resolution, the trajectories of charged-particle tracks with a transverse momentum above 1 GeV, using the ATLAS inner tracker info...

  3. THE STAR LEVEL-3 TRIGGER SYSTEM.

    Energy Technology Data Exchange (ETDEWEB)

    LANGE, J.S.; ADLER, C.; BERGER, J.; DEMELLO, M.; FLIERL, D.; ET AL

    1999-11-15

    The STAR level-3 trigger is a MYRINET interconnected ALPHA processor farm, performing online tracking of N{sub track} {ge} 8000 particles (N{sub point} {le} 45 per track) with a design input rate of R=100 Hz. A large scale prototype system was tested in 12/99 with laser and cosmic particle events.

  4. Burst-mode optical label processor with ultralow power consumption.

    Science.gov (United States)

    Ibrahim, Salah; Nakahara, Tatsushi; Ishikawa, Hiroshi; Takahashi, Ryo

    2016-04-01

    A novel label processor subsystem for 100-Gbps (25-Gbps × 4λs) burst-mode optical packets is developed, in which a highly energy-efficient method is pursued for extracting and interfacing the ultrafast packet-label to a CMOS-based processor where label recognition takes place. The method involves performing serial-to-parallel conversion for the label bits on a bit-by-bit basis by using an optoelectronic converter that is operated with a set of optical triggers generated in a burst-mode manner upon packet arrival. Here we present three key achievements that enabled a significant reduction in the total power consumption and latency of the whole subsystem; 1) based on a novel operation mechanism for providing amplification with bit-level selectivity, an optical trigger pulse generator, that consumes power for a very short duration upon packet arrival, is proposed and experimentally demonstrated, 2) the energy of optical triggers needed by the optoelectronic serial-to-parallel converter is reduced by utilizing a negative-polarity signal while employing an enhanced conversion scheme entitled the discharge-or-hold scheme, 3) the necessary optical trigger energy is further cut down by half by coupling the triggers through the chip's backside, whereas a novel lens-free packaging method is developed to enable a low-cost alignment process that works with simple visual observation. PMID:27136992

  5. Calibration for the ATLAS Level-1 Calorimeter-Trigger

    Energy Technology Data Exchange (ETDEWEB)

    Foehlisch, F.

    2007-12-19

    This thesis describes developments and tests that are necessary to operate the Pre-Processor of the ATLAS Level-1 Calorimeter Trigger for data acquisition. The major tasks of Pre-Processor comprise the digitizing, time-alignment and the calibration of signals that come from the ATLAS calorimeter. Dedicated hardware has been developed that must be configured in order to fulfill these tasks. Software has been developed that implements the register-model of the Pre-Processor Modules and allows to set up the Pre-Processor. In order to configure the Pre-Processor in the context of an ATLAS run, user-settings and the results of calibration measurements are used to derive adequate settings for registers of the Pre-Processor. The procedures that allow to perform the required measurements and store the results into a database are demonstrated. Furthermore, tests that go along with the ATLAS installation are presented and results are shown. (orig.)

  6. Calibration for the ATLAS Level-1 Calorimeter-Trigger

    International Nuclear Information System (INIS)

    This thesis describes developments and tests that are necessary to operate the Pre-Processor of the ATLAS Level-1 Calorimeter Trigger for data acquisition. The major tasks of Pre-Processor comprise the digitizing, time-alignment and the calibration of signals that come from the ATLAS calorimeter. Dedicated hardware has been developed that must be configured in order to fulfill these tasks. Software has been developed that implements the register-model of the Pre-Processor Modules and allows to set up the Pre-Processor. In order to configure the Pre-Processor in the context of an ATLAS run, user-settings and the results of calibration measurements are used to derive adequate settings for registers of the Pre-Processor. The procedures that allow to perform the required measurements and store the results into a database are demonstrated. Furthermore, tests that go along with the ATLAS installation are presented and results are shown. (orig.)

  7. 7 CFR 926.13 - Processor.

    Science.gov (United States)

    2010-01-01

    ... 7 Agriculture 8 2010-01-01 2010-01-01 false Processor. 926.13 Section 926.13 Agriculture... Processor. Processor means any person who receives or acquires fresh or frozen cranberries or cranberries in the form of concentrate from handlers, producer-handlers, importers, brokers or other processors...

  8. 40 CFR 791.45 - Processors.

    Science.gov (United States)

    2010-07-01

    ... 40 Protection of Environment 31 2010-07-01 2010-07-01 true Processors. 791.45 Section 791.45...) DATA REIMBURSEMENT Basis for Proposed Order § 791.45 Processors. (a) Generally, processors will be... processors will have a responsibility to provide reimbursement directly to those paying for the testing:...

  9. Smart trigger logic for focal plane arrays

    Science.gov (United States)

    Levy, James E; Campbell, David V; Holmes, Michael L; Lovejoy, Robert; Wojciechowski, Kenneth; Kay, Randolph R; Cavanaugh, William S; Gurrieri, Thomas M

    2014-03-25

    An electronic device includes a memory configured to receive data representing light intensity values from pixels in a focal plane array and a processor that analyzes the received data to determine which light values correspond to triggered pixels, where the triggered pixels are those pixels that meet a predefined set of criteria, and determines, for each triggered pixel, a set of neighbor pixels for which light intensity values are to be stored. The electronic device also includes a buffer that temporarily stores light intensity values for at least one previously processed row of pixels, so that when a triggered pixel is identified in a current row, light intensity values for the neighbor pixels in the previously processed row and for the triggered pixel are persistently stored, as well as a data transmitter that transmits the persistently stored light intensity values for the triggered and neighbor pixels to a data receiver.

  10. ALICE High Level Trigger

    CERN Multimedia

    Alt, T

    2013-01-01

    The ALICE High Level Trigger (HLT) is a computing farm designed and build for the real-time, online processing of the raw data produced by the ALICE detectors. Events are fully reconstructed from the raw data, analyzed and compressed. The analysis summary together with the compressed data and a trigger decision is sent to the DAQ. In addition the reconstruction of the events allows for on-line monitoring of physical observables and this information is provided to the Data Quality Monitor (DQM). The HLT can process event rates of up to 2 kHz for proton-proton and 200 Hz for Pb-Pb central collisions.

  11. Integrated fuel processor development challenges

    International Nuclear Information System (INIS)

    In the absence of a hydrogen-refueling infrastructure, the success of the fuel cell system in the market will depend on fuel processors to enable the use of available fuels, such as gasoline, natural gas, etc. The fuel processor includes several catalytic reactors, scrubbers to remove chemical species that can poison downstream catalysts or the fuel cell electrocatalyst, and heat exchangers. Most fuel cell power applications seek compact, lightweight hardware with rapid-start and load- following capabilities. Although packaging can partially address the size and volume, balancing the performance parameters while maintaining the fuel conversion (to hydrogen) efficiency requires careful integration of the unit operations and processes. Argonne National Laboratory has developed integrated fuel processors that are compact and light, and that operate efficiently. This paper discusses some of the difficulties encountered in the development process, focusing on the factors/components that constrain performance, and areas that need further research and development

  12. Java Processor Optimized for RTSJ

    Directory of Open Access Journals (Sweden)

    Tu Shiliang

    2007-01-01

    Full Text Available Due to the preeminent work of the real-time specification for Java (RTSJ, Java is increasingly expected to become the leading programming language in real-time systems. To provide a Java platform suitable for real-time applications, a Java processor which can execute Java bytecode is directly proposed in this paper. It provides efficient support in hardware for some mechanisms specified in the RTSJ and offers a simpler programming model through ameliorating the scoped memory of the RTSJ. The worst case execution time (WCET of the bytecodes implemented in this processor is predictable by employing the optimization method proposed in our previous work, in which all the processing interfering predictability is handled before bytecode execution. Further advantage of this method is to make the implementation of the processor simpler and suited to a low-cost FPGA chip.

  13. Libera Electron Beam Position Processor

    CERN Document Server

    Ursic, Rok

    2005-01-01

    Libera is a product family delivering unprecedented possibilities for either building powerful single station solutions or architecting complex feedback systems in the field of accelerator instrumentation and controls. This paper presents functionality and field performance of its first member, the electron beam position processor. It offers superior performance with multiple measurement channels delivering simultaneously position measurements in digital format with MHz kHz and Hz bandwidths. This all-in-one product, facilitating pulsed and CW measurements, is much more than simply a high performance beam position measuring device delivering micrometer level reproducibility with sub-micrometer resolution. Rich connectivity options and innate processing power make it a powerful feedback building block. By interconnecting multiple Libera electron beam position processors one can build a low-latency high throughput orbit feedback system without adding additional hardware. Libera electron beam position processor ...

  14. The ATLAS Muon Trigger Performance in pp Collisions at sqrt(s)=8 TeV in Year 2012 Runs

    CERN Document Server

    Nobe, T; The ATLAS collaboration

    2012-01-01

    Events with muons in the final state are an important signature for many physics topics at Large Hadron Collider (LHC), for instance, searches for Higgs boson production or new phenomena, measurements on the standard model processes like top-quark, W, Z production. Thus, efficient trigger on muons in data taking and understanding its performance are crucial to perform these physics studies. At LHC high rejection power against large backgrounds, while maintaining high efficiency for rare signal events, is required for online selection at the trigger level. The ATLAS experiment employs a multi-level trigger architecture that selects the events in three sequential steps of increasing complexity and accuracy to cope with this challenging task. The L1 muon trigger system gets its input from fast muon trigger detectors. Fast sector logic boards select muon candidates, which are passed via an interface board to the central trigger processor and then to the High Level Trigger (HLT). The Muon HLT is purely software ba...

  15. The ATLAS muon trigger performance in pp collisions at sqrt(s) = 8 TeV in year 2012 runs

    CERN Document Server

    Nobe, T; The ATLAS collaboration

    2012-01-01

    Events with muons in the final state are an important signature for many physics topics at Large Hadron Collider (LHC), for instance, searches for Higgs boson production or new phenomena, measurements on the standard model processes like top-quark, W, Z production. Thus, efficient trigger on muons in data taking and understanding its performance are crucial to perform these physics studies. At LHC high rejection power against large backgrounds, while maintaining high efficiency for rare signal events, is required for online selection at the trigger level. The ATLAS experiment employs a multi-level trigger architecture that selects the events in three sequential steps of increasing complexity and accuracy to cope with this challenging task. The L1 muon trigger system gets its input from fast muon trigger detectors. Fast sector logic boards select muon candidates, which are passed via an interface board to the central trigger processor and then to the High Level Trigger (HLT). The Muon HLT is purely software ba...

  16. A Time-Multiplexed Track-Trigger architecture for CMS

    CERN Document Server

    Hall, Geoffrey; Pesaresi, Mark Franco; Rose, A

    2014-01-01

    The CMS Tracker under development for the High Luminosity LHC includes an outer tracker based on ``PT-modules'' which will provide track stubs based on coincident clusters in two closely spaced sensor layers, aiming to reject low transverse momentum track hits before data transmission to the Level-1 trigger. The tracker data will be used to reconstruct track segments in dedicated processors before onward transmission to other trigger processors which will combine tracker information with data originating from the calorimeter and muon detectors, to make the final L1 trigger decision. The architecture for processing the tracker data is still an open question. One attractive option is to explore a Time Multiplexed design similar to one which is currently being implemented in the CMS calorimeter trigger as part of the Phase I trigger upgrade. The Time Multiplexed Trigger concept is explained, the potential benefits of applying it for processing future tracker data are described and a possible design based on cur...

  17. Triggering Klystrons

    Energy Technology Data Exchange (ETDEWEB)

    Stefan, Kelton D.; /Purdue U. /SLAC

    2010-08-25

    To determine if klystrons will perform to the specifications of the LCLS (Linac Coherent Light Source) project, a new digital trigger controller is needed for the Klystron/Microwave Department Test Laboratory. The controller needed to be programmed and Windows based user interface software needed to be written to interface with the device over a USB (Universal Serial Bus). Programming the device consisted of writing logic in VHDL (VHSIC (Very High Speed Integrated Circuits) hardware description language), and the Windows interface software was written in C++. Xilinx ISE (Integrated Software Environment) was used to compile the VHDL code and program the device, and Microsoft Visual Studio 2005 was used to compile the C++ based Windows software. The device was programmed in such a way as to easily allow read/write operations to it using a simple addressing model, and Windows software was developed to interface with the device over a USB connection. A method of setting configuration registers in the trigger device is absolutely necessary to the development of a new triggering system, and the method developed will fulfill this need adequately. More work is needed before the new trigger system is ready for use. The configuration registers in the device need to be fully integrated with the logic that will generate the RF signals, and this system will need to be tested extensively to determine if it meets the requirements for low noise trigger outputs.

  18. Reconfigurable Communication Processor:A New Approach for Network Processor

    Institute of Scientific and Technical Information of China (English)

    孙华; 陈青山; 张文渊

    2003-01-01

    As the traditional RISC +ASIC/ASSP approach for network processor design can not meet the today'srequirements, this paper described an alternate approach, Reconfigurable Processing Architecture, to boost theperformance to ASIC level while reserve the programmability of the traditional RISC based system. This papercovers both the hardware architecture and the software development environment architecture.

  19. A Course on Reconfigurable Processors

    Science.gov (United States)

    Shoufan, Abdulhadi; Huss, Sorin A.

    2010-01-01

    Reconfigurable computing is an established field in computer science. Teaching this field to computer science students demands special attention due to limited student experience in electronics and digital system design. This article presents a compact course on reconfigurable processors, which was offered at the Technische Universitat Darmstadt,…

  20. The evolution of the trigger and data acquisition system in the ATLAS experiment (CHEP2013: 20. international conference on computing in high energy and nuclear physics)

    International Nuclear Information System (INIS)

    The ATLAS experiment, which records the results of LHC proton-proton collisions, is upgrading its Trigger and Data Acquisition (TDAQ) system during the current LHC first long shutdown. The purpose of this upgrade is to add robustness and flexibility to the selection and the conveyance of the physics data, simplify the maintenance of the infrastructure, exploit new technologies and, overall, make ATLAS data-taking capable of dealing with increasing event rates. While the TDAQ system successfully operated well beyond the original design goals, the accumulated experience stimulated interest to explore possible evolutions. With higher luminosities, the required number and complexity of Level-1 triggers will increase in order to satisfy the physics goals of ATLAS, while keeping the total Level-1 rates at or below 100 kHz. The Central Trigger Processor will be upgraded to increase the number ofmanageable inputs and accommodate additional hardware for improved performance, and a new Topological Processor will be included. A single homogeneous high level trigger system will be deployed. The current second and third trigger levels will be executed together on a unique hardware node. This design has many advantages: the radical simplification of the architecture, the flexible and automatically balanced distribution of the computing resources, the sharing of code and services on nodes. In this paper, we report on the design and the development status of the upgraded TDAQ system, with particular attention to the tests currently on-going to identify the required performance and to spot its possible limitations.

  1. A fast programmable trigger for isolated cluster counting in the BELLE experiment

    OpenAIRE

    Kim, H. J.; Kim, S. K.; Lee, S. H.; Hur, T. W.; Kim, C. H.; Wang, F.; Park, I. C.; Kim, Hee Jong; Cheon, B. G.; Won, E.

    1999-01-01

    We have developed a fast programmable trigger processor board based on a field programmable gate array and a complex programmable logic device for use in the BELLE experiment. The trigger board accommodates 144 ECL input signals, 2 NIM input signals, 24 ECL output signals, and the VME bus specification. An asynchronous trigger logic for counting isolated clusters is used. We have obtained trigger latency of 50 ns with a full access to input and output signals via a VME interface. The trigger ...

  2. MAKASSAR COPRA AS A TRIGGER OF STRUGGLING FOR POWER BETWEEN CENTRAL AND LOCAL GOVERMENT: A HISTORICAL STUDY OF REGIONAL POLITICAL ECONOMY IN INDONESIA

    OpenAIRE

    Asba, A. Rasyid

    2011-01-01

    central government of Jakarta. For example, there was a claim of South Moluccas Republic Movement and Permesta (Whole people struggling) for economic equity. The gain of copra trading which divided into 70% for local and 30% for central government became national political problem in maintaining the central and local government relationship. That???s why, the local conflict in Eastern Indonesia had been occuring until now and being a problem for developing a democratic modern Indonesia. N...

  3. JPP: A Java Pre-Processor

    OpenAIRE

    Kiniry, Joseph R.; Cheong, Elaine

    1998-01-01

    The Java Pre-Processor, or JPP for short, is a parsing pre-processor for the Java programming language. Unlike its namesake (the C/C++ Pre-Processor, cpp), JPP provides functionality above and beyond simple textual substitution. JPP's capabilities include code beautification, code standard conformance checking, class and interface specification and testing, and documentation generation.

  4. 7 CFR 989.13 - Processor.

    Science.gov (United States)

    2010-01-01

    ... 7 Agriculture 8 2010-01-01 2010-01-01 false Processor. 989.13 Section 989.13 Agriculture Regulations of the Department of Agriculture (Continued) AGRICULTURAL MARKETING SERVICE (Marketing Agreements... CALIFORNIA Order Regulating Handling Definitions § 989.13 Processor. Processor means any person who...

  5. 7 CFR 1215.14 - Processor.

    Science.gov (United States)

    2010-01-01

    ... 7 Agriculture 10 2010-01-01 2010-01-01 false Processor. 1215.14 Section 1215.14 Agriculture Regulations of the Department of Agriculture (Continued) AGRICULTURAL MARKETING SERVICE (MARKETING AGREEMENTS... Processor. Processor means a person engaged in the preparation of unpopped popcorn for the market who...

  6. 7 CFR 927.14 - Processor.

    Science.gov (United States)

    2010-01-01

    ... 7 Agriculture 8 2010-01-01 2010-01-01 false Processor. 927.14 Section 927.14 Agriculture Regulations of the Department of Agriculture (Continued) AGRICULTURAL MARKETING SERVICE (Marketing Agreements... Order Regulating Handling Definitions § 927.14 Processor. Processor means any person who as owner,...

  7. Invasive tightly coupled processor arrays

    CERN Document Server

    LARI, VAHID

    2016-01-01

    This book introduces new massively parallel computer (MPSoC) architectures called invasive tightly coupled processor arrays. It proposes strategies, architecture designs, and programming interfaces for invasive TCPAs that allow invading and subsequently executing loop programs with strict requirements or guarantees of non-functional execution qualities such as performance, power consumption, and reliability. For the first time, such a configurable processor array architecture consisting of locally interconnected VLIW processing elements can be claimed by programs, either in full or in part, using the principle of invasive computing. Invasive TCPAs provide unprecedented energy efficiency for the parallel execution of nested loop programs by avoiding any global memory access such as GPUs and may even support loops with complex dependencies such as loop-carried dependencies that are not amenable to parallel execution on GPUs. For this purpose, the book proposes different invasion strategies for claiming a desire...

  8. Rhapsody on small processor platforms

    OpenAIRE

    Andersson, Per-Oskar

    2008-01-01

    Rhapsody is a Model-Driven Development (MDD) tool for embedded and real-time system design. The purpose of this thesis is to determine if Rhapsody can be used for software development on small processor platforms such as the Atmel AVR. Rhapsody is normally used on platforms running an operating system. Therefore certain adaptations are needed in order to use it on platforms without an operating system. These adaptations and their affect on the usability of the tool, advantages and disadvantag...

  9. An Experimental Digital Image Processor

    Science.gov (United States)

    Cok, Ronald S.

    1986-12-01

    A prototype digital image processor for enhancing photographic images has been built in the Research Laboratories at Kodak. This image processor implements a particular version of each of the following algorithms: photographic grain and noise removal, edge sharpening, multidimensional image-segmentation, image-tone reproduction adjustment, and image-color saturation adjustment. All processing, except for segmentation and analysis, is performed by massively parallel and pipelined special-purpose hardware. This hardware runs at 10 MHz and can be adjusted to handle any size digital image. The segmentation circuits run at 30 MHz. The segmentation data are used by three single-board computers for calculating the tonescale adjustment curves. The system, as a whole, has the capability of completely processing 10 million three-color pixels per second. The grain removal and edge enhancement algorithms represent the largest part of the pipelined hardware, operating at over 8 billion integer operations per second. The edge enhancement is performed by unsharp masking, and the grain removal is done using a collapsed Walsh-hadamard transform filtering technique (U.S. Patent No. 4549212). These two algo-rithms can be realized using four basic processing elements, some of which have been imple-mented as VLSI semicustom integrated circuits. These circuits implement the algorithms with a high degree of efficiency, modularity, and testability. The digital processor is controlled by a Digital Equipment Corporation (DEC) PDP 11 minicomputer and can be interfaced to electronic printing and/or electronic scanning de-vices. The processor has been used to process over a thousand diagnostic images.

  10. Design Principles for Synthesizable Processor Cores

    DEFF Research Database (Denmark)

    Schleuniger, Pascal; McKee, Sally A.; Karlsson, Sven

    2012-01-01

    As FPGAs get more competitive, synthesizable processor cores become an attractive choice for embedded computing. Currently popular commercial processor cores do not fully exploit current FPGA architectures. In this paper, we propose general design principles to increase instruction throughput...... through the use of micro-benchmarks that our principles guide the design of a processor core that improves performance by an average of 38% over a similar Xilinx MicroBlaze configuration....... on FPGA-based processor cores: first, superpipelining enables higher-frequency system clocks, and second, predicated instructions circumvent costly pipeline stalls due to branches. To evaluate their effects, we develop Tinuso, a processor architecture optimized for FPGA implementation. We demonstrate...

  11. Communications systems and methods for subsea processors

    Science.gov (United States)

    Gutierrez, Jose; Pereira, Luis

    2016-04-26

    A subsea processor may be located near the seabed of a drilling site and used to coordinate operations of underwater drilling components. The subsea processor may be enclosed in a single interchangeable unit that fits a receptor on an underwater drilling component, such as a blow-out preventer (BOP). The subsea processor may issue commands to control the BOP and receive measurements from sensors located throughout the BOP. A shared communications bus may interconnect the subsea processor and underwater components and the subsea processor and a surface or onshore network. The shared communications bus may be operated according to a time division multiple access (TDMA) scheme.

  12. The use of low-cost SMPs in the Atlas level-2 trigger

    CERN Document Server

    Bock, R; Ermolin, Y; Kugel, A; Lay, R; Werner, P

    2000-01-01

    Low-cost SMP (Symmetric Multi-Processor) systems have become generallyavailable since 1998; they provide substantial CPU and I/O capacity along with a memory that is shared by all processors. We have investigated two areas of application in the Atlas level-2 trigger.

  13. Speculative segmented sum for sparse matrix-vector multiplication on heterogeneous processors

    DEFF Research Database (Denmark)

    Liu, Weifeng; Vinter, Brian

    2015-01-01

    of the same chip is triggered to re-arrange the predicted partial sums for a correct resulting vector. On three heterogeneous processors from Intel, AMD and nVidia, using 20 sparse matrices as a benchmark suite, the experimental results show that our method obtains significant performance improvement...

  14. Taxonomy of Data Prefetching for Multicore Processors

    Institute of Scientific and Technical Information of China (English)

    Surendra Byna; Yong Chen; Xian-He Sun

    2009-01-01

    Data prefetching is an effective data access latency hiding technique to mask the CPU stall caused by cache misses and to bridge the performance gap between processor and memory. With hardware and/or software support, data prefetching brings data closer to a processor before it is actually needed. Many prefetching techniques have been developed for single-core processors. Recent developments in processor technology have brought multicore processors into mainstream.While some of the single-core prefetching techniques are directly applicable to multicore processors, numerous novel strategies have been proposed in the past few years to take advantage of multiple cores. This paper aims to provide a comprehensive review of the state-of-the-art prefetching techniques, and proposes a taxonomy that classifies various design concerns in developing a prefetching strategy, especially for multicore processors. We compare various existing methods through analysis as well.

  15. Triggering Artefacts

    DEFF Research Database (Denmark)

    Mogensen, Preben Holst; Robinson, Mike

    1995-01-01

    The paper presents a general critique of the use of conceptual frameworks in design, illustrated by the well known synchronous/asynchronous, co-located/non-co-located framework. It argues that while frameworks are a necessary and inevitable starting point for design, the business of tailoring and...... adapting them to specific situations need not be ad hoc.Triggering artefacts are a way of systematically challenging both designers' preunderstandings and the conservatism of work practice. Experiences from the Great Belt tunnel and bridge project are used to illustrate howtriggering artefacts change...

  16. Timing in the ALICE trigger system

    CERN Document Server

    Lietava, Roman; Evans, D; Jones, G T; Jovanovic, P; Jusko, A; Králik, I; Krivda, M; Pastircák, B; Sándor, L; Urbán, J; Villalobos Baillie, O

    2007-01-01

    In this paper we discuss trigger signals synchronisation and trigger input alignment in the ALICE trigger system. The synchronisation procedure adjusts the phase of the input signals with respect to the local Bunch Crossing (BC) clock and, indirectly, with respect to the LHC bunch crossing instant. The synchronisation delays are within one clock period: 0-25 ns. The alignment assures that the trigger signals originating from the same bunch crossing reach the processor logic in the same clock cycle. It is achieved by delaying signals by an appropriate number of full clock periods. We propose a procedure which will allow us to nd alignment delays during the system con guration, and to monitor them during the data taking.

  17. Operation of the enhanced ATLAS First Level Calorimeter Trigger at the start of Run-2

    CERN Document Server

    Palka, Marek; The ATLAS collaboration

    2015-01-01

    In 2015 the LHC will operate with a higher center-of-mass energy and proton beams luminosity. To keep a high trigger efficiency against an increased event rate, part of ATLAS Level-1 Calorimeter Trigger electronics have been re-designed or newly introduced (Pre-Processors, Merging Modules and Topological Processors). Additionally, to achieve the best possible resolution for the reconstructed physics objects, complex calibration and monitoring systems are employed. Hit rates and energy spectra down to channel level, based on reconstructed events, are supervised with the calorimeter trigger hardware. The performance of the upgraded Level-1 Calorimeter Trigger at the beginning of LHC Run-2 is illustrated.

  18. The Database Query Support Processor (QSP)

    Science.gov (United States)

    1993-01-01

    The number and diversity of databases available to users continues to increase dramatically. Currently, the trend is towards decentralized, client server architectures that (on the surface) are less expensive to acquire, operate, and maintain than information architectures based on centralized, monolithic mainframes. The database query support processor (QSP) effort evaluates the performance of a network level, heterogeneous database access capability. Air Force Material Command's Rome Laboratory has developed an approach, based on ANSI standard X3.138 - 1988, 'The Information Resource Dictionary System (IRDS)' to seamless access to heterogeneous databases based on extensions to data dictionary technology. To successfully query a decentralized information system, users must know what data are available from which source, or have the knowledge and system privileges necessary to find out this information. Privacy and security considerations prohibit free and open access to every information system in every network. Even in completely open systems, time required to locate relevant data (in systems of any appreciable size) would be better spent analyzing the data, assuming the original question was not forgotten. Extensions to data dictionary technology have the potential to more fully automate the search and retrieval for relevant data in a decentralized environment. Substantial amounts of time and money could be saved by not having to teach users what data resides in which systems and how to access each of those systems. Information describing data and how to get it could be removed from the application and placed in a dedicated repository where it belongs. The result simplified applications that are less brittle and less expensive to build and maintain. Software technology providing the required functionality is off the shelf. The key difficulty is in defining the metadata required to support the process. The database query support processor effort will provide

  19. Jet-like correlations with neutral pion triggers in pp and central Pb-Pb collisions at 2.76 TeV

    CERN Document Server

    Adam, Jaroslav; Aggarwal, Madan Mohan; Aglieri Rinella, Gianluca; Agnello, Michelangelo; Agrawal, Neelima; Ahammed, Zubayer; Ahmad, Shakeel; Ahn, Sang Un; Aiola, Salvatore; Akindinov, Alexander; Alam, Sk Noor; Silva De Albuquerque, Danilo; Aleksandrov, Dmitry; Alessandro, Bruno; Alexandre, Didier; Alfaro Molina, Jose Ruben; Alici, Andrea; Alkin, Anton; Alme, Johan; Alt, Torsten; Altinpinar, Sedat; Altsybeev, Igor; Alves Garcia Prado, Caio; An, Mangmang; Andrei, Cristian; Andrews, Harry Arthur; Andronic, Anton; Anguelov, Venelin; Anson, Christopher Daniel; Anticic, Tome; Antinori, Federico; Antonioli, Pietro; Aphecetche, Laurent Bernard; Appelshaeuser, Harald; Arcelli, Silvia; Arnaldi, Roberta; Arnold, Oliver Werner; Arsene, Ionut Cristian; Arslandok, Mesut; Audurier, Benjamin; Augustinus, Andre; Averbeck, Ralf Peter; Azmi, Mohd Danish; Badala, Angela; Baek, Yong Wook; Bagnasco, Stefano; Bailhache, Raphaelle Marie; Bala, Renu; Balasubramanian, Supraja; Baldisseri, Alberto; Baral, Rama Chandra; Barbano, Anastasia Maria; Barbera, Roberto; Barile, Francesco; Barnafoldi, Gergely Gabor; Barnby, Lee Stuart; Ramillien Barret, Valerie; Bartalini, Paolo; Barth, Klaus; Bartke, Jerzy Gustaw; Bartsch, Esther; Basile, Maurizio; Bastid, Nicole; Basu, Sumit; Bathen, Bastian; Batigne, Guillaume; Batista Camejo, Arianna; Batyunya, Boris; Batzing, Paul Christoph; Bearden, Ian Gardner; Beck, Hans; Bedda, Cristina; Behera, Nirbhay Kumar; Belikov, Iouri; Bellini, Francesca; Bello Martinez, Hector; Bellwied, Rene; Belmont Moreno, Ernesto; Espinoza Beltran, Lucina Gabriela; Belyaev, Vladimir; Bencedi, Gyula; Beole, Stefania; Berceanu, Ionela; Bercuci, Alexandru; Berdnikov, Yaroslav; Berenyi, Daniel; Bertens, Redmer Alexander; Berzano, Dario; Betev, Latchezar; Bhasin, Anju; Bhat, Inayat Rasool; Bhati, Ashok Kumar; Bhattacharjee, Buddhadeb; Bhom, Jihyun; Bianchi, Livio; Bianchi, Nicola; Bianchin, Chiara; Bielcik, Jaroslav; Bielcikova, Jana; Bilandzic, Ante; Biro, Gabor; Biswas, Rathijit; Biswas, Saikat; Bjelogrlic, Sandro; Blair, Justin Thomas; Blau, Dmitry; Blume, Christoph; Bock, Friederike; Bogdanov, Alexey; Boggild, Hans; Boldizsar, Laszlo; Bombara, Marek; Bonora, Matthias; Book, Julian Heinz; Borel, Herve; Borissov, Alexander; Borri, Marcello; Bossu, Francesco; Botta, Elena; Bourjau, Christian; Braun-munzinger, Peter; Bregant, Marco; Broker, Theo Alexander; Browning, Tyler Allen; Broz, Michal; Brucken, Erik Jens; Bruna, Elena; Bruno, Giuseppe Eugenio; Budnikov, Dmitry; Buesching, Henner; Bufalino, Stefania; Buhler, Paul; Buncic, Predrag; Busch, Oliver; Buthelezi, Edith Zinhle; Bashir Butt, Jamila; Buxton, Jesse Thomas; Cabala, Jan; Caffarri, Davide; Cai, Xu; Caines, Helen Louise; Caliva, Alberto; Calvo Villar, Ernesto; Camerini, Paolo; Carena, Francesco; Carena, Wisla; Carnesecchi, Francesca; Castillo Castellanos, Javier Ernesto; Castro, Andrew John; Casula, Ester Anna Rita; Ceballos Sanchez, Cesar; Cepila, Jan; Cerello, Piergiorgio; Cerkala, Jakub; Chang, Beomsu; Chapeland, Sylvain; Chartier, Marielle; Charvet, Jean-luc Fernand; Chattopadhyay, Subhasis; Chattopadhyay, Sukalyan; Chauvin, Alex; Chelnokov, Volodymyr; Cherney, Michael Gerard; Cheshkov, Cvetan Valeriev; Cheynis, Brigitte; Chibante Barroso, Vasco Miguel; Dobrigkeit Chinellato, David; Cho, Soyeon; Chochula, Peter; Choi, Kyungeon; Chojnacki, Marek; Choudhury, Subikash; Christakoglou, Panagiotis; Christensen, Christian Holm; Christiansen, Peter; Chujo, Tatsuya; Chung, Suh-urk; Cicalo, Corrado; Cifarelli, Luisa; Cindolo, Federico; Cleymans, Jean Willy Andre; Colamaria, Fabio Filippo; Colella, Domenico; Collu, Alberto; Colocci, Manuel; Conesa Balbastre, Gustavo; Conesa Del Valle, Zaida; Connors, Megan Elizabeth; Contreras Nuno, Jesus Guillermo; Cormier, Thomas Michael; Corrales Morales, Yasser; Cortes Maldonado, Ismael; Cortese, Pietro; Cosentino, Mauro Rogerio; Costa, Filippo; Crkovska, Jana; Crochet, Philippe; Cruz Albino, Rigoberto; Cuautle Flores, Eleazar; Cunqueiro Mendez, Leticia; Dahms, Torsten; Dainese, Andrea; Danisch, Meike Charlotte; Danu, Andrea; Das, Debasish; Das, Indranil; Das, Supriya; Dash, Ajay Kumar; Dash, Sadhana; De, Sudipan; De Caro, Annalisa; De Cataldo, Giacinto; De Conti, Camila; De Cuveland, Jan; De Falco, Alessandro; De Gruttola, Daniele; De Marco, Nora; De Pasquale, Salvatore; Derradi De Souza, Rafael; Deisting, Alexander; Deloff, Andrzej; Deplano, Caterina; Dhankher, Preeti; Di Bari, Domenico; Di Mauro, Antonio; Di Nezza, Pasquale; Di Ruzza, Benedetto; Diaz Corchero, Miguel Angel; Dietel, Thomas; Dillenseger, Pascal; Divia, Roberto; Djuvsland, Oeystein; Dobrin, Alexandru Florin; Domenicis Gimenez, Diogenes; Donigus, Benjamin; Dordic, Olja; Drozhzhova, Tatiana; Dubey, Anand Kumar; Dubla, Andrea; Ducroux, Laurent; Duggal, Ashpreet Kaur; Dupieux, Pascal; Ehlers Iii, Raymond James; Elia, Domenico; Endress, Eric; Engel, Heiko; Epple, Eliane; Erazmus, Barbara Ewa; Erhardt, Filip; Espagnon, Bruno; Estienne, Magali Danielle; Esumi, Shinichi; Eulisse, Giulio; Eum, Jongsik; Evans, David; Evdokimov, Sergey; Eyyubova, Gyulnara; Fabbietti, Laura; Fabris, Daniela; Faivre, Julien; Fantoni, Alessandra; Fasel, Markus; Feldkamp, Linus; Feliciello, Alessandro; Feofilov, Grigorii; Ferencei, Jozef; Fernandez Tellez, Arturo; Gonzalez Ferreiro, Elena; Ferretti, Alessandro; Festanti, Andrea; Feuillard, Victor Jose Gaston; Figiel, Jan; Araujo Silva Figueredo, Marcel; Filchagin, Sergey; Finogeev, Dmitry; Fionda, Fiorella; Fiore, Enrichetta Maria; Floris, Michele; Foertsch, Siegfried Valentin; Foka, Panagiota; Fokin, Sergey; Fragiacomo, Enrico; Francescon, Andrea; Francisco, Audrey; Frankenfeld, Ulrich Michael; Fronze, Gabriele Gaetano; Fuchs, Ulrich; Furget, Christophe; Furs, Artur; Fusco Girard, Mario; Gaardhoeje, Jens Joergen; Gagliardi, Martino; Gago Medina, Alberto Martin; Gajdosova, Katarina; Gallio, Mauro; Duarte Galvan, Carlos; Gangadharan, Dhevan Raja; Ganoti, Paraskevi; Gao, Chaosong; Garabatos Cuadrado, Jose; Garcia-solis, Edmundo Javier; Garg, Kunal; Garg, Prakhar; Gargiulo, Corrado; Gasik, Piotr Jan; Gauger, Erin Frances; Germain, Marie; Gheata, Mihaela; Ghosh, Premomoy; Ghosh, Sanjay Kumar; Gianotti, Paola; Giubellino, Paolo; Giubilato, Piero; Gladysz-dziadus, Ewa; Glassel, Peter; Gomez Coral, Diego Mauricio; Gomez Ramirez, Andres; Sanchez Gonzalez, Andres; Gonzalez, Victor; Gonzalez Zamora, Pedro; Gorbunov, Sergey; Gorlich, Lidia Maria; Gotovac, Sven; Grabski, Varlen; Grachov, Oleg Anatolievich; Graczykowski, Lukasz Kamil; Graham, Katie Leanne; Grelli, Alessandro; Grigoras, Costin; Grigoryev, Vladislav; Grigoryan, Ara; Grigoryan, Smbat; Grynyov, Borys; Grion, Nevio; Gronefeld, Julius Maximilian; Grosse-oetringhaus, Jan Fiete; Grosso, Raffaele; Gruber, Lukas; Guber, Fedor; Guernane, Rachid; Guerzoni, Barbara; Gulbrandsen, Kristjan Herlache; Gunji, Taku; Gupta, Anik; Gupta, Ramni; Bautista Guzman, Irais; Haake, Rudiger; Hadjidakis, Cynthia Marie; Haiduc, Maria; Hamagaki, Hideki; Hamar, Gergoe; Hamon, Julien Charles; Harris, John William; Harton, Austin Vincent; Hatzifotiadou, Despina; Hayashi, Shinichi; Heckel, Stefan Thomas; Hellbar, Ernst; Helstrup, Haavard; Herghelegiu, Andrei Ionut; Herrera Corral, Gerardo Antonio; Herrmann, Florian; Hess, Benjamin Andreas; Hetland, Kristin Fanebust; Hillemanns, Hartmut; Hippolyte, Boris; Horak, David; Hosokawa, Ritsuya; Hristov, Peter Zahariev; Hughes, Charles; Humanic, Thomas; Hussain, Nur; Hussain, Tahir; Hutter, Dirk; Hwang, Dae Sung; Ilkaev, Radiy; Inaba, Motoi; Incani, Elisa; Ippolitov, Mikhail; Irfan, Muhammad; Isakov, Vladimir; Ivanov, Marian; Ivanov, Vladimir; Izucheev, Vladimir; Jacak, Barbara; Jacazio, Nicolo; Jacobs, Peter Martin; Jadhav, Manoj Bhanudas; Jadlovska, Slavka; Jadlovsky, Jan; Jahnke, Cristiane; Jakubowska, Monika Joanna; Janik, Malgorzata Anna; Pahula Hewage, Sandun; Jena, Chitrasen; Jena, Satyajit; Jimenez Bustamante, Raul Tonatiuh; Jones, Peter Graham; Jung, Hyungtaik; Jusko, Anton; Kalinak, Peter; Kalweit, Alexander Philipp; Kang, Ju Hwan; Kaplin, Vladimir; Kar, Somnath; Karasu Uysal, Ayben; Karavichev, Oleg; Karavicheva, Tatiana; Karayan, Lilit; Karpechev, Evgeny; Kebschull, Udo Wolfgang; Keidel, Ralf; Keijdener, Darius Laurens; Keil, Markus; Khan, Mohammed Mohisin; Khan, Palash; Khan, Shuaib Ahmad; Khanzadeev, Alexei; Kharlov, Yury; Khatun, Anisa; Khuntia, Arvind; Kileng, Bjarte; Kim, Do Won; Kim, Dong Jo; Kim, Daehyeok; Kim, Hyeonjoong; Kim, Jinsook; Kim, Jiyoung; Kim, Minjung; Kim, Minwoo; Kim, Se Yong; Kim, Taesoo; Kirsch, Stefan; Kisel, Ivan; Kiselev, Sergey; Kisiel, Adam Ryszard; Kiss, Gabor; Klay, Jennifer Lynn; Klein, Carsten; Klein, Jochen; Klein-boesing, Christian; Klewin, Sebastian; Kluge, Alexander; Knichel, Michael Linus; Knospe, Anders Garritt; Kobdaj, Chinorat; Kofarago, Monika; Kollegger, Thorsten; Kolozhvari, Anatoly; Kondratev, Valerii; Kondratyeva, Natalia; Kondratyuk, Evgeny; Konevskikh, Artem; Kopcik, Michal; Kour, Mandeep; Kouzinopoulos, Charalampos; Kovalenko, Oleksandr; Kovalenko, Vladimir; Kowalski, Marek; Koyithatta Meethaleveedu, Greeshma; Kralik, Ivan; Kravcakova, Adela; Krivda, Marian; Krizek, Filip; Kryshen, Evgeny; Krzewicki, Mikolaj; Kubera, Andrew Michael; Kucera, Vit; Kuhn, Christian Claude; Kuijer, Paulus Gerardus; Kumar, Ajay; Kumar, Jitendra; Kumar, Lokesh; Kumar, Shyam; Kundu, Sourav; Kurashvili, Podist; Kurepin, Alexander; Kurepin, Alexey; Kuryakin, Alexey; Kweon, Min Jung; Kwon, Youngil; La Pointe, Sarah Louise; La Rocca, Paola; Lagana Fernandes, Caio; Lakomov, Igor; Langoy, Rune; Lapidus, Kirill; Lara Martinez, Camilo Ernesto; Lardeux, Antoine Xavier; Lattuca, Alessandra; Laudi, Elisa; Lazaridis, Lazaros; Lea, Ramona; Leardini, Lucia; Lee, Seongjoo; Lehas, Fatiha; Lehner, Sebastian; Lehrbach, Johannes; Lemmon, Roy Crawford; Lenti, Vito; Leogrande, Emilia; Leon Monzon, Ildefonso; Leon Vargas, Hermes; Leoncino, Marco; Levai, Peter; Li, Shuang; Li, Xiaomei; Lien, Jorgen Andre; Lietava, Roman; Lindal, Svein; Lindenstruth, Volker; Lippmann, Christian; Lisa, Michael Annan; Ljunggren, Hans Martin; Lodato, Davide Francesco; Lonne, Per-ivar; Loginov, Vitaly; Loizides, Constantinos; Lopez, Xavier Bernard; Lopez Torres, Ernesto; Lowe, Andrew John; Luettig, Philipp Johannes; Lunardon, Marcello; Luparello, Grazia; Lupi, Matteo; Lutz, Tyler Harrison; Maevskaya, Alla; Mager, Magnus; Mahajan, Sanjay; Mahmood, Sohail Musa; Maire, Antonin; Majka, Richard Daniel; Malaev, Mikhail; Maldonado Cervantes, Ivonne Alicia; Malinina, Liudmila; Mal'kevich, Dmitry; Malzacher, Peter; Mamonov, Alexander; Manko, Vladislav; Manso, Franck; Manzari, Vito; Mao, Yaxian; Marchisone, Massimiliano; Mares, Jiri; Margagliotti, Giacomo Vito; Margotti, Anselmo; Margutti, Jacopo; Marin, Ana Maria; Markert, Christina; Marquard, Marco; Martin, Nicole Alice; Martinengo, Paolo; Martinez Hernandez, Mario Ivan; Martinez-garcia, Gines; Martinez Pedreira, Miguel; Mas, Alexis Jean-michel; Masciocchi, Silvia; Masera, Massimo; Masoni, Alberto; Mastroserio, Annalisa; Matyja, Adam Tomasz; Mayer, Christoph; Mazer, Joel Anthony; Mazzilli, Marianna; Mazzoni, Alessandra Maria; Meddi, Franco; Melikyan, Yuri; Menchaca-rocha, Arturo Alejandro; Meninno, Elisa; Mercado-perez, Jorge; Meres, Michal; Mhlanga, Sibaliso; Miake, Yasuo; Mieskolainen, Matti Mikael; Mikhaylov, Konstantin; Milosevic, Jovan; Mischke, Andre; Mishra, Aditya Nath; Mishra, Tribeni; Miskowiec, Dariusz Czeslaw; Mitra, Jubin; Mitu, Ciprian Mihai; Mohammadi, Naghmeh; Mohanty, Bedangadas; Molnar, Levente; Montes Prado, Esther; Moreira De Godoy, Denise Aparecida; Perez Moreno, Luis Alberto; Moretto, Sandra; Morreale, Astrid; Morsch, Andreas; Muccifora, Valeria; Mudnic, Eugen; Muhlheim, Daniel Michael; Muhuri, Sanjib; Mukherjee, Maitreyee; Mulligan, James Declan; Gameiro Munhoz, Marcelo; Munning, Konstantin; Munzer, Robert Helmut; Murakami, Hikari; Murray, Sean; Musa, Luciano; Musinsky, Jan; Naik, Bharati; Nair, Rahul; Nandi, Basanta Kumar; Nania, Rosario; Nappi, Eugenio; Naru, Muhammad Umair; Ferreira Natal Da Luz, Pedro Hugo; Nattrass, Christine; Rosado Navarro, Sebastian; Nayak, Kishora; Nayak, Ranjit; Nayak, Tapan Kumar; Nazarenko, Sergey; Nedosekin, Alexander; Negrao De Oliveira, Renato Aparecido; Nellen, Lukas; Ng, Fabian; Nicassio, Maria; Niculescu, Mihai; Niedziela, Jeremi; Nielsen, Borge Svane; Nikolaev, Sergey; Nikulin, Sergey; Nikulin, Vladimir; Noferini, Francesco; Nomokonov, Petr; Nooren, Gerardus; Cabanillas Noris, Juan Carlos; Norman, Jaime; Nyanin, Alexander; Nystrand, Joakim Ingemar; Oeschler, Helmut Oskar; Oh, Saehanseul; Oh, Sun Kun; Ohlson, Alice Elisabeth; Okatan, Ali; Okubo, Tsubasa; Oleniacz, Janusz; Oliveira Da Silva, Antonio Carlos; Oliver, Michael Henry; Onderwaater, Jacobus; Oppedisano, Chiara; Orava, Risto; Oravec, Matej; Ortiz Velasquez, Antonio; Oskarsson, Anders Nils Erik; Otwinowski, Jacek Tomasz; Oyama, Ken; Ozdemir, Mahmut; Pachmayer, Yvonne Chiara; Pagano, Davide; Pagano, Paola; Paic, Guy; Pal, Susanta Kumar; Palni, Prabhakar; Pan, Jinjin; Pandey, Ashutosh Kumar; Papikyan, Vardanush; Pappalardo, Giuseppe; Pareek, Pooja; Park, Jonghan; Park, Woojin; Parmar, Sonia; Passfeld, Annika; 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Rakotozafindrabe, Andry Malala; Ramello, Luciano; Rami, Fouad; Raniwala, Rashmi; Raniwala, Sudhir; Rasanen, Sami Sakari; Rascanu, Bogdan Theodor; Rathee, Deepika; Ratza, Viktor; Ravasenga, Ivan; Read, Kenneth Francis; Redlich, Krzysztof; Rehman, Attiq Ur; Reichelt, Patrick Simon; Reidt, Felix; Ren, Xiaowen; Renfordt, Rainer Arno Ernst; Reolon, Anna Rita; Reshetin, Andrey; Reygers, Klaus Johannes; Riabov, Viktor; Ricci, Renato Angelo; Richert, Tuva Ora Herenui; Richter, Matthias Rudolph; Riedler, Petra; Riegler, Werner; Riggi, Francesco; Ristea, Catalin-lucian; Rodriguez Cahuantzi, Mario; Roeed, Ketil; Rogochaya, Elena; Rohr, David Michael; Roehrich, Dieter; Ronchetti, Federico; Ronflette, Lucile; Rosnet, Philippe; Rossi, Andrea; Roukoutakis, Filimon; Roy, Ankhi; Roy, Christelle Sophie; Roy, Pradip Kumar; Rubio Montero, Antonio Juan; Rui, Rinaldo; Russo, Riccardo; Ryabinkin, Evgeny; Ryabov, Yury; Rybicki, Andrzej; Saarinen, Sampo; Sadhu, Samrangy; Sadovskiy, Sergey; Safarik, Karel; Sahlmuller, Baldo; Sahoo, Pragati; Sahoo, Raghunath; Sahoo, Sarita; Sahu, Pradip Kumar; Saini, Jogender; Sakai, Shingo; Saleh, Mohammad Ahmad; Salzwedel, Jai Samuel Nielsen; Sambyal, Sanjeev Singh; Samsonov, Vladimir; Sandor, Ladislav; Sandoval, Andres; Sano, Masato; Sarkar, Debojit; Sarkar, Nachiketa; Sarma, Pranjal; Scapparone, Eugenio; Scarlassara, Fernando; Schiaua, Claudiu Cornel; Schicker, Rainer Martin; Schmidt, Christian Joachim; Schmidt, Hans Rudolf; Schmidt, Martin; Schukraft, Jurgen; Schutz, Yves Roland; Schwarz, Kilian Eberhard; Schweda, Kai Oliver; Scioli, Gilda; Scomparin, Enrico; Scott, Rebecca Michelle; Sefcik, Michal; Seger, Janet Elizabeth; Sekiguchi, Yuko; Sekihata, Daiki; Selyuzhenkov, Ilya; Senosi, Kgotlaesele; Senyukov, Serhiy; Serradilla Rodriguez, Eulogio; Sevcenco, Adrian; Shabanov, Arseniy; Shabetai, Alexandre; Shadura, Oksana; Shahoyan, Ruben; Shangaraev, Artem; Sharma, Ankita; Sharma, Anjali; Sharma, Mona; Sharma, Monika; Sharma, Natasha; Sheikh, Ashik Ikbal; Shigaki, Kenta; Shou, Qiye; Shtejer Diaz, Katherin; Sibiryak, Yury; Siddhanta, Sabyasachi; Sielewicz, Krzysztof Marek; Siemiarczuk, Teodor; Silvermyr, David Olle Rickard; Silvestre, Catherine Micaela; Simatovic, Goran; Simonetti, Giuseppe; Singaraju, Rama Narayana; Singh, Ranbir; Singhal, Vikas; Sarkar - Sinha, Tinku; Sitar, Branislav; Sitta, Mario; Skaali, Bernhard; Slupecki, Maciej; Smirnov, Nikolai; Snellings, Raimond; Snellman, Tomas Wilhelm; Song, Jihye; Song, Myunggeun; Song, Zixuan; Soramel, Francesca; Sorensen, Soren Pontoppidan; Sozzi, Federica; Spiriti, Eleuterio; Sputowska, Iwona Anna; Spyropoulou-stassinaki, Martha; Stachel, Johanna; Stan, Ionel; Stankus, Paul; Stenlund, Evert Anders; Steyn, Gideon Francois; Stiller, Johannes Hendrik; Stocco, Diego; Strmen, Peter; Alarcon Do Passo Suaide, Alexandre; Sugitate, Toru; Suire, Christophe Pierre; Suleymanov, Mais Kazim Oglu; Suljic, Miljenko; Sultanov, Rishat; Sumbera, Michal; Sumowidagdo, Suharyo; Suzuki, Ken; Swain, Sagarika; Szabo, Alexander; Szarka, Imrich; Szczepankiewicz, Adam; Szymanski, Maciej Pawel; Tabassam, Uzma; Takahashi, Jun; Tambave, Ganesh Jagannath; Tanaka, Naoto; Tarhini, Mohamad; Tariq, Mohammad; Tarzila, Madalina-gabriela; Tauro, Arturo; Tejeda Munoz, Guillermo; Telesca, Adriana; Terasaki, Kohei; Terrevoli, Cristina; Teyssier, Boris; Thaeder, Jochen Mathias; Thakur, Dhananjaya; Thomas, Deepa; Tieulent, Raphael Noel; Tikhonov, Anatoly; Timmins, Anthony Robert; Toia, Alberica; Tripathy, Sushanta; Trogolo, Stefano; Trombetta, Giuseppe; Trubnikov, Victor; Trzaska, Wladyslaw Henryk; Tsuji, Tomoya; Tumkin, Alexandr; Turrisi, Rosario; Tveter, Trine Spedstad; Ullaland, Kjetil; Uras, Antonio; Usai, Gianluca; Utrobicic, Antonija; Vala, Martin; Van Der Maarel, Jasper; Van Hoorne, Jacobus Willem; Van Leeuwen, Marco; Vanat, Tomas; Vande Vyvre, Pierre; Varga, Dezso; Varga, Michal; Vargas Trevino, Aurora Diozcora; Vargyas, Marton; Varma, Raghava; Vasileiou, Maria; Vasiliev, Andrey; Vauthier, Astrid; Vazquez Doce, Oton; Vechernin, Vladimir; Veen, Annelies Marianne; Velure, Arild; Vercellin, Ermanno; Vergara Limon, Sergio; Vernet, Renaud; Vertesi, Robert; Vickovic, Linda; Vigolo, Sonia; Viinikainen, Jussi Samuli; Vilakazi, Zabulon; Villalobos Baillie, Orlando; Villatoro Tello, Abraham; Vinogradov, Alexander; Vinogradov, Leonid; Virgili, Tiziano; Vislavicius, Vytautas; Vodopyanov, Alexander; Volkl, Martin Andreas; Voloshin, Kirill; Voloshin, Sergey; Volpe, Giacomo; Von Haller, Barthelemy; Vorobyev, Ivan; Voscek, Dominik; Vranic, Danilo; Vrlakova, Janka; Vulpescu, Bogdan; Wagner, Boris; Wagner, Jan; Wang, Hongkai; Wang, Mengliang; Watanabe, Daisuke; Watanabe, Yosuke; Weber, Michael; Weber, Steffen Georg; Weiser, Dennis Franz; Wessels, Johannes Peter; Westerhoff, Uwe; Whitehead, Andile Mothegi; Wiechula, Jens; Wikne, Jon; Wilk, Grzegorz Andrzej; Wilkinson, Jeremy John; Willems, Guido Alexander; Williams, Crispin; Windelband, Bernd Stefan; Winn, Michael Andreas; Yalcin, Serpil; Yang, Ping; Yano, Satoshi; Yin, Zhongbao; Yokoyama, Hiroki; Yoo, In-kwon; Yoon, Jin Hee; Yurchenko, Volodymyr; Zaccolo, Valentina; Zaman, Ali; Zampolli, Chiara; Correia Zanoli, Henrique Jose; Zaporozhets, Sergey; Zardoshti, Nima; Zarochentsev, Andrey; Zavada, Petr; Zavyalov, Nikolay; Zbroszczyk, Hanna Paulina; Zgura, Sorin Ion; Zhalov, Mikhail; Zhang, Haitao; Zhang, Xiaoming; Zhang, Yonghong; Chunhui, Zhang; Zhang, Zuman; Zhao, Chengxin; Zhigareva, Natalia; Zhou, Daicui; Zhou, You; Zhou, Zhuo; Zhu, Hongsheng; Zhu, Jianhui; Zhu, Xiangrong; Zichichi, Antonino; Zimmermann, Alice; Zimmermann, Markus Bernhard; Zinovjev, Gennady; Zmeskal, Johann; Zyzak, Maksym

    2016-01-01

    We present measurements of two-particle correlations with neutral pion trigger particles of transverse momenta $8 3~\\mathrm{GeV}/c$, while with decreasing momenta an enhancement develops reaching about $5$ at low $p_{\\mathrm{T}}^{\\rm assoc}$. On the near side, an enhancement of $I_{\\mathrm{AA}}$ between $1.2$ at the highest to $1.8$ at the lowest $p_{\\mathrm{T}}^{\\rm assoc}$ is observed. The data are compared to parton-energy-loss predictions of the JEWEL and AMPT event generators, as well as to a perturbative QCD calculation with medium-modified fragmentation functions. All calculations qualitatively describe the away-side suppression at high $p_{\\mathrm{T}}^{\\rm assoc}$. Only AMPT captures the enhancement at low $p_{\\mathrm{T}}^{\\rm assoc}$, both on the near and away side. However, it also underpredicts $I_{\\mathrm{AA}}$ above $5$ GeV/$c$, in particular on the near-side.

  20. SMART AS A CRYPTOGRAPHIC PROCESSOR

    OpenAIRE

    Saroja Kanchi; Nozar Tabrizi; Cody Hayden

    2016-01-01

    SMaRT is a 16-bit 2.5-address RISC-type single-cycle processor, which was recently designed and successfully mapped into a FPGA chip in our ECE department. In this paper, we use SMaRT to run the well-known encryption algorithm, Data Encryption Standard. For information security purposes, encryption is a must in today’s sophisticated and ever-increasing computer communications such as ATM machines and SIM cards. For comparison and evaluation purposes, we also map the same algori...

  1. Configurable Multi-Purpose Processor

    Science.gov (United States)

    Valencia, J. Emilio; Forney, Chirstopher; Morrison, Robert; Birr, Richard

    2010-01-01

    Advancements in technology have allowed the miniaturization of systems used in aerospace vehicles. This technology is driven by the need for next-generation systems that provide reliable, responsive, and cost-effective range operations while providing increased capabilities such as simultaneous mission support, increased launch trajectories, improved launch, and landing opportunities, etc. Leveraging the newest technologies, the command and telemetry processor (CTP) concept provides for a compact, flexible, and integrated solution for flight command and telemetry systems and range systems. The CTP is a relatively small circuit board that serves as a processing platform for high dynamic, high vibration environments. The CTP can be reconfigured and reprogrammed, allowing it to be adapted for many different applications. The design is centered around a configurable field-programmable gate array (FPGA) device that contains numerous logic cells that can be used to implement traditional integrated circuits. The FPGA contains two PowerPC processors running the Vx-Works real-time operating system and are used to execute software programs specific to each application. The CTP was designed and developed specifically to provide telemetry functions; namely, the command processing, telemetry processing, and GPS metric tracking of a flight vehicle. However, it can be used as a general-purpose processor board to perform numerous functions implemented in either hardware or software using the FPGA s processors and/or logic cells. Functionally, the CTP was designed for range safety applications where it would ultimately become part of a vehicle s flight termination system. Consequently, the major functions of the CTP are to perform the forward link command processing, GPS metric tracking, return link telemetry data processing, error detection and correction, data encryption/ decryption, and initiate flight termination action commands. Also, the CTP had to be designed to survive and

  2. High-fat simple carbohydrate feeding impairs central and peripheral monoamine metabolic pathway triggering the onset of metabolic syndrome in C57Bl/6J mice

    Directory of Open Access Journals (Sweden)

    Serena S D'Souza

    2016-01-01

    Conclusion: HFSC diet impairs the central and peripheral dopaminergic and noradrenergic pathways in mice as evidenced by the disturbances in their hypothalamic, plasma, and urine levels and this might be one of the early factors contributing towards the development of the MetS.

  3. Minimum Bias Trigger in ATLAS

    International Nuclear Information System (INIS)

    Since the restart of the LHC in November 2009, ATLAS has collected inelastic pp collisions to perform first measurements on charged particle densities. These measurements will help to constrain various models describing phenomenologically soft parton interactions. Understanding the trigger efficiencies for different event types are therefore crucial to minimize any possible bias in the event selection. ATLAS uses two main minimum bias triggers, featuring complementary detector components and trigger levels. While a hardware based first trigger level situated in the forward regions with 2.2 < |η| < 3.8 has been proven to select pp-collisions very efficiently, the Inner Detector based minimum bias trigger uses a random seed on filled bunches and central tracking detectors for the event selection. Both triggers were essential for the analysis of kinematic spectra of charged particles. Their performance and trigger efficiency measurements as well as studies on possible bias sources will be presented. We also highlight the advantage of these triggers for particle correlation analyses. (author)

  4. Firearm trigger assembly

    Science.gov (United States)

    Crandall, David L.; Watson, Richard W.

    2010-02-16

    A firearm trigger assembly for use with a firearm includes a trigger mounted to a forestock of the firearm so that the trigger is movable between a rest position and a triggering position by a forwardly placed support hand of a user. An elongated trigger member operatively associated with the trigger operates a sear assembly of the firearm when the trigger is moved to the triggering position. An action release assembly operatively associated with the firearm trigger assembly and a movable assembly of the firearm prevents the trigger from being moved to the triggering position when the movable assembly is not in the locked position.

  5. Digital Signal Processor For GPS Receivers

    Science.gov (United States)

    Thomas, J. B.; Meehan, T. K.; Srinivasan, J. M.

    1989-01-01

    Three innovative components combined to produce all-digital signal processor with superior characteristics: outstanding accuracy, high-dynamics tracking, versatile integration times, lower loss-of-lock signal strengths, and infrequent cycle slips. Three components are digital chip advancer, digital carrier downconverter and code correlator, and digital tracking processor. All-digital signal processor intended for use in receivers of Global Positioning System (GPS) for geodesy, geodynamics, high-dynamics tracking, and ionospheric calibration.

  6. Automatic data distribution for massively parallel processors

    OpenAIRE

    García Almiñana, Jordi

    1997-01-01

    Massively Parallel Processor systems provide the required computational power to solve most large scale High Performance Computing applications. Machines with physically distributed memory allow a cost-effective way to achieve this performance, however, these systems are very diffcult to program and tune. In a distributed-memory organization each processor has direct access to its local memory, and indirect access to the remote memories of other processors. But the cost of accessing a local m...

  7. Alternative Water Processor Test Development

    Science.gov (United States)

    Pickering, Karen D.; Mitchell, Julie; Vega, Leticia; Adam, Niklas; Flynn, Michael; Wjee (er. Rau); Lunn, Griffin; Jackson, Andrew

    2012-01-01

    The Next Generation Life Support Project is developing an Alternative Water Processor (AWP) as a candidate water recovery system for long duration exploration missions. The AWP consists of biological water processor (BWP) integrated with a forward osmosis secondary treatment system (FOST). The basis of the BWP is a membrane aerated biological reactor (MABR), developed in concert with Texas Tech University. Bacteria located within the MABR metabolize organic material in wastewater, converting approximately 90% of the total organic carbon to carbon dioxide. In addition, bacteria convert a portion of the ammonia-nitrogen present in the wastewater to nitrogen gas, through a combination of nitrogen and denitrification. The effluent from the BWP system is low in organic contaminants, but high in total dissolved solids. The FOST system, integrated downstream of the BWP, removes dissolved solids through a combination of concentration-driven forward osmosis and pressure driven reverse osmosis. The integrated system is expected to produce water with a total organic carbon less than 50 mg/l and dissolved solids that meet potable water requirements for spaceflight. This paper describes the test definition, the design of the BWP and FOST subsystems, and plans for integrated testing.

  8. Alternative Water Processor Test Development

    Science.gov (United States)

    Pickering, Karen D.; Mitchell, Julie L.; Adam, Niklas M.; Barta, Daniel; Meyer, Caitlin E.; Pensinger, Stuart; Vega, Leticia M.; Callahan, Michael R.; Flynn, Michael; Wheeler, Ray; Birmele, Michele; Lunn, Griffin; Jackson, Andrew

    2013-01-01

    The Next Generation Life Support Project is developing an Alternative Water Processor (AWP) as a candidate water recovery system for long duration exploration missions. The AWP consists of biological water processor (BWP) integrated with a forward osmosis secondary treatment system (FOST). The basis of the BWP is a membrane aerated biological reactor (MABR), developed in concert with Texas Tech University. Bacteria located within the MABR metabolize organic material in wastewater, converting approximately 90% of the total organic carbon to carbon dioxide. In addition, bacteria convert a portion of the ammonia-nitrogen present in the wastewater to nitrogen gas, through a combination of nitrification and denitrification. The effluent from the BWP system is low in organic contaminants, but high in total dissolved solids. The FOST system, integrated downstream of the BWP, removes dissolved solids through a combination of concentration-driven forward osmosis and pressure driven reverse osmosis. The integrated system is expected to produce water with a total organic carbon less than 50 mg/l and dissolved solids that meet potable water requirements for spaceflight. This paper describes the test definition, the design of the BWP and FOST subsystems, and plans for integrated testing.

  9. The case for a generic implant processor.

    Science.gov (United States)

    Strydis, Christos; Gaydadjiev, Georgi N

    2008-01-01

    A more structured and streamlined design of implants is nowadays possible. In this paper we focus on implant processors located in the heart of implantable systems. We present a real and representative biomedical-application scenario where such a new processor can be employed. Based on a suitably selected processor simulator, various operational aspects of the application are being monitored. Findings on performance, cache behavior, branch prediction, power consumption, energy expenditure and instruction mixes are presented and analyzed. The suitability of such an implant processor and directions for future work are given.

  10. Parallel Neutrino Triggers using GPUs for an underwater telescope

    OpenAIRE

    Bouhadef, Bachir; Morganti, Mauro; Terreni, Giuseppe; KM3Net-It Collaboration

    2015-01-01

    Graphics Processing Units are high performance co-processors originally intended to improve the use and the acceleration of computer graphics applications. Because of their performance, researchers have extended their use beyond the computer graphics scope. We have investigated the possibility of implementing online neutrino trigger algorithms in the KM3Net-It experiment using a CPU-GPU system. The results of a neutrino trigger simulation on a NEMO Phase II tower and a KM3-It 14 floors tower ...

  11. Parallel Neutrino Triggers using GPUs for an underwater telescope

    OpenAIRE

    Bouhadef, Bachir; Morganti, Mauro; Terreni, Giuseppe

    2014-01-01

    Graphics Processing Units are high performance co-processors originally intended to improve the use and the acceleration of computer graphics applications. Because of their performance, researchers have extended their use beyond the computer graphics scope. We have investigated the possibility of implementing online neutrino trigger algorithms in the KM3Net-It experiment using a CPU-GPU system. The results of a neutrino trigger simulation on a NEMO Phase II tower and a KM3-It 14 floors tower ...

  12. Controlling Quantum Transport with a Programmable Nanophotonic Processor

    Science.gov (United States)

    Harris, Nicholas; Steinbrecher, Gregory; Mower, Jacob; Lihini, Yoav; Prabhu, Mihika; Baehr-Jones, Tom; Hochberg, Michael; Lloyd, Seth; Englund, Dirk

    Recent experimental and theoretical work has revealed emergent, counter-intuitive quantum transport effects in a range of physical medial including solid-state and biological systems. Photonic integrated circuits are promising platforms for studying such effects. A central goal in for photonic quantum transport simulators has been the ability to rapidly control all parameters of the transport problem. Here, we present a large-scale programmable nanophotonic processor composed of 56 Mach-Zehnder interferometers that enables control over modal couplings and differential phases between modes--enabling observations of Anderson localization, environment-assisted quantum transport, ballistic transport, and a number of intermediate quantum transport regimes. Rapid programmability enables tens of thousands of realizations of disordered and noisy systems. In addition, low loss makes this nanophotonic processor a promising platform for many-boson quantum simulation experiments.

  13. Optimizing pipeline for a RISC processor with multimedia extension ISA

    Institute of Scientific and Technical Information of China (English)

    XIAO Zhi-bin; LIU Peng; YAO Ying-biao; YAO Qing-dong

    2006-01-01

    The 32-bit extensible embedded processor RISC3200 originating from an RTL prototype core is intended for low-cost consumer multimedia products. In order to incorporate the reduced instruction set and the multimedia extension instruction set in a unifying pipeline, a scalable super-pipeline technique is adopted. Several other optimization techniques are proposed to boost the frequency and reduce the average CPI of the unifying pipeline. Based on a data flow graph (DFG) with delay information, the critical path of the pipeline stage can be located and shortened. This paper presents a distributed data bypass unit and a centralized pipeline control scheme for achieving lower CPI. Synthesis and simulation showed that the optimization techniques enable RISC3200 to operate at 200 MHz with an average CPI of 1.16. The core was integrated into a media SOC chip taped out in SMIC 0.18-micron technology. Preliminary testing result showed that the processor works well as we expected.

  14. Upgrade of the CMS Global Muon Trigger

    CERN Document Server

    Lingemann, Joschka; Sakulin, Hannes; Jeitler, Manfred; Stahl, Achim

    2015-01-01

    The increase in center-of-mass energy and luminosity for Run 2 of the Large Hadron Collider pose new challenges for the trigger systems of the experiments. To keep triggering with a similar performance as in Run 1, the CMS muon trigger is currently being upgraded. The new algorithms will provide higher resolution, especially for the muon transverse momentum and will make use of isolation criteria that combine calorimeter with muon information already in the level-1 trigger. The demands of the new algorithms can only be met by upgrading the level-1 trigger system to new powerful FPGAs with high bandwidth I/O. The processing boards will be based on the new microTCA standard. We report on the planned algorithms for the upgraded Global Muon Trigger (GMT) which combines information from the muon trigger sub-systems and assigns the isolation variable. The upgraded GMT will be implemented using a Master Processor 7 card, built by Imperial College, that features a large Xilinx Virtex 7 FPGA. Up to 72 optical links at...

  15. Towards a Process Algebra for Shared Processors

    DEFF Research Database (Denmark)

    Buchholtz, Mikael; Andersen, Jacob; Løvengreen, Hans Henrik

    2002-01-01

    We present initial work on a timed process algebra that models sharing of processor resources allowing preemption at arbitrary points in time. This enables us to model both the functional and the timely behaviour of concurrent processes executed on a single processor. We give a refinement relation...

  16. Adapting implicit methods to parallel processors

    Energy Technology Data Exchange (ETDEWEB)

    Reeves, L.; McMillin, B.; Okunbor, D.; Riggins, D. [Univ. of Missouri, Rolla, MO (United States)

    1994-12-31

    When numerically solving many types of partial differential equations, it is advantageous to use implicit methods because of their better stability and more flexible parameter choice, (e.g. larger time steps). However, since implicit methods usually require simultaneous knowledge of the entire computational domain, these methods axe difficult to implement directly on distributed memory parallel processors. This leads to infrequent use of implicit methods on parallel/distributed systems. The usual implementation of implicit methods is inefficient due to the nature of parallel systems where it is common to take the computational domain and distribute the grid points over the processors so as to maintain a relatively even workload per processor. This creates a problem at the locations in the domain where adjacent points are not on the same processor. In order for the values at these points to be calculated, messages have to be exchanged between the corresponding processors. Without special adaptation, this will result in idle processors during part of the computation, and as the number of idle processors increases, the lower the effective speed improvement by using a parallel processor.

  17. Verilog Implementation of 32-Bit CISC Processor

    Directory of Open Access Journals (Sweden)

    P.Kanaka Sirisha

    2016-04-01

    Full Text Available The Project deals with the design of the 32-Bit CISC Processor and modeling of its components using Verilog language. The Entire Processor uses 32-Bit bus to deal with all the registers and the memories. This Processor implements various arithmetic, logical, Data Transfer operations etc., using variable length instructions, which is the core property of the CISC Architecture. The Processor also supports various addressing modes to perform a 32-Bit instruction. Our Processor uses Harvard Architecture (i.e., to have a separate program and data memory and hence has different buses to negotiate with the Program Memory and Data Memory individually. This feature enhances the speed of our processor. Hence it has two different Program Counters to point to the memory locations of the Program Memory and Data Memory.Our processor has ‘Instruction Queuing’ which enables it to save the time needed to fetch the instruction and hence increases the speed of operation. ‘Interrupt Service Routine’ is provided in our Processor to make it address the Interrupts.

  18. Models of Communication for Multicore Processors

    DEFF Research Database (Denmark)

    Schoeberl, Martin; Sørensen, Rasmus Bo; Sparsø, Jens

    2015-01-01

    To efficiently use multicore processors we need to ensure that almost all data communication stays on chip, i.e., the bits moved between tasks executing on different processor cores do not leave the chip. Different forms of on-chip communication are supported by different hardware mechanism, e...

  19. An Empirical Evaluation of XQuery Processors

    NARCIS (Netherlands)

    Manegold, S.

    2008-01-01

    This paper presents an extensive and detailed experimental evaluation of XQuery processors. The study consists of running five publicly available XQuery benchmarks --- the Michigan benchmark (MBench), XBench, XMach-1, XMark and X007 --- on six XQuery processors, three stand-alone (file-based) XQuery

  20. Ultrafast Fourier-transform parallel processor

    Energy Technology Data Exchange (ETDEWEB)

    Greenberg, W.L.

    1980-04-01

    A new, flexible, parallel-processing architecture is developed for a high-speed, high-precision Fourier transform processor. The processor is intended for use in 2-D signal processing including spatial filtering, matched filtering and image reconstruction from projections.

  1. The TM3270 Media-processor

    NARCIS (Netherlands)

    van de Waerdt, J.W.

    2006-01-01

    I n this thesis, we present the TM3270 VLIW media-processor, the latest of TriMedia processors, and describe the innovations with respect to its prede- cessor: the TM3260. We describe enhancements to the load/store unit design, such as a new data prefetching technique, and architectural enhancements

  2. Advanced Multiple Processor Configuration Study. Final Report.

    Science.gov (United States)

    Clymer, S. J.

    This summary of a study on multiple processor configurations includes the objectives, background, approach, and results of research undertaken to provide the Air Force with a generalized model of computer processor combinations for use in the evaluation of proposed flight training simulator computational designs. An analysis of a real-time flight…

  3. The Case for a Generic Implant Processor

    NARCIS (Netherlands)

    Strydis, C.; Gaydadjiev, G.N.

    2008-01-01

    A more structured and streamlined design of implants is nowadays possible. In this paper we focus on implant processors located in the heart of implantable systems. We present a real and representative biomedical-application scenario where such a new processor can be employed. Based on a suitably se

  4. Porting GCC to Exposed Pipeline VLIW Processors

    NARCIS (Netherlands)

    Turjan, A.; Cheresiz, D.; Trienekens, R.

    2009-01-01

    EVP and TriMedia are embedded application processors targeted at mobile communication and multimedia domains. Both architectures originate from Philips Semiconductors and are currently developed by ST-Ericsson and NXP Semiconductors, respectively. Both processors have a VLIWarchitecture with an expo

  5. Direct Processor Access for Non Dedicated Server using Multi Core Processor

    OpenAIRE

    P. S. BALAMURUGAN,; Dr.K.Thanushkodi

    2010-01-01

    The objective of the paper is to design a co processor for a desktop machine which enables the machine to act as non dedicated server, such that the co processor will act as a server processor and the multi-core processor to act as desktop processor. By implementing this methodology a client machine can be made to act as a non dedicated server and a client machine. This type of machine can be used in autonomy networks. This design will lead to design of a cost effective server and machine whi...

  6. Very Large-Scale Integrated Processor

    Directory of Open Access Journals (Sweden)

    Shigeyuki Takano

    2013-01-01

    Full Text Available In the near future, improvements in semiconductor technology will allow thousands of resources to be implementable on chip. However, a limitation remains for both single large-scale processors and many-core processors. For single processors, this limitation arises from their  design complexity, and regarding the many-core processors, an application is partitioned to several tasks and these partitioned tasks are mapped onto the cores. In this article,  we propose a dynamic chip multiprocessor (CMP model that consists of simple modules (realizing a low design complexity and does not require the application partitioning since the scale of the processor is dynamically variable, looking like up or down scale on demand. This model is based on prior work on adaptive processors that can gather and release resources on chip to dynamically form a processor. The adaptive processor takes a linear topology that realizes a locality based placement and replacement using processing elements themselves through a stack shift of information on the linear topology of the processing element array. Therefore, for the scaling of the processor, a linear topology of the interconnection network has to support the stack shift before and after the up- or down-scaling. Therefore, we propose an interconnection network architecture called a dynamic channel segmentation distribution (dynamic CSD network. In addition the linear topology must be folded on-chip into two-dimensional plane. We also propose a new conceptual topology and its cluster which is a unit of the new topology and is replicated on the chip. We analyzed the cost in terms of the available number of clusters (adaptive processors with a minimum scale and delay in Manhattan-distance of the chip, as well as its peak Giga-Operations per Second (GOPS across the process technology scaling.

  7. The ZEUS second level calorimeter trigger

    International Nuclear Information System (INIS)

    ZEUS is a detector for the HERA ep collider, consisting of several large components. The most important being the inner tracking detectors, which are positioned nearest to the interaction point, the calorimeter surrounding the inner tracking detectors and the muon detectors on the outside of the experimental setup. Each component will deliver a vast amount of information. In order to keep this information manageable, data is preprocessed and condensed per component and then combined to obtain the final global trigger result. The main subject of this thesis is the second level calorimeter trigger processor of the ZEUS detector. In order to be able to reject the unwanted events passing the first level, the topological event signature will have to be used at the second level. The most demanding task of the second level is the recognition of local energy depositions corresponding to isolated electrons and hadron jets. Also part of the work performed by the first level will be repeated with a higher level of accuracy. Additional information not available to the first level trigger will be processed and will be made available to the global second level trigger decision module. For the second level calorimeter trigger processor a special VME module, containing two transputers, has been developed. The second level calorimeter trigger algorithm described in this thesis was tested with simulated events, that were tracked through a computer simulation of the ZEUS detector. A part of this thesis is therefore devoted to the description of the various Monte Carlo models and the justification of the way in which they were used. (author). 132 refs.; 76 figs.; 18 tabs

  8. Enabling Future Robotic Missions with Multicore Processors

    Science.gov (United States)

    Powell, Wesley A.; Johnson, Michael A.; Wilmot, Jonathan; Some, Raphael; Gostelow, Kim P.; Reeves, Glenn; Doyle, Richard J.

    2011-01-01

    Recent commercial developments in multicore processors (e.g. Tilera, Clearspeed, HyperX) have provided an option for high performance embedded computing that rivals the performance attainable with FPGA-based reconfigurable computing architectures. Furthermore, these processors offer more straightforward and streamlined application development by allowing the use of conventional programming languages and software tools in lieu of hardware design languages such as VHDL and Verilog. With these advantages, multicore processors can significantly enhance the capabilities of future robotic space missions. This paper will discuss these benefits, along with onboard processing applications where multicore processing can offer advantages over existing or competing approaches. This paper will also discuss the key artchitecural features of current commercial multicore processors. In comparison to the current art, the features and advancements necessary for spaceflight multicore processors will be identified. These include power reduction, radiation hardening, inherent fault tolerance, and support for common spacecraft bus interfaces. Lastly, this paper will explore how multicore processors might evolve with advances in electronics technology and how avionics architectures might evolve once multicore processors are inserted into NASA robotic spacecraft.

  9. Improving performance of probabilistic programmable quantum processors

    CERN Document Server

    Hillery, M; Buzek, V; Hillery, Mark; Ziman, Mario; Buzek, Vladimir

    2003-01-01

    We present a systematic analysis how one can improve performance of probabilistic programmable quantum processors. We generalize a simple Vidal-Masanes-Cirac processor that realizes U(1) rotations on a qubit with the phase of the rotation encoded in a state of the program register. We show how the probability of success of the probabilistic processor can be enhanced by using the processor in loops. In addition we show that the same strategy can be utilized for a probabilistic implementation of non-unitary transformations on qubits. In addtion, we show that an arbitrary SU(2) transformations of qubits can be encoded in program state of a universal programmable probabilistic quantum processor. The probability of success of this processor can be enhanced by a systematic correction of errors via conditional loops. Finally, we show that all our results can be generalized also for qudits. In particular, we show how to implement SU (N) rotations of qudits via programmable quantum processor and how the performance of...

  10. Commissioning of the CMS High Level Trigger

    CERN Document Server

    Agostino, Lorenzo; Beccati, Barbara; Behrens, Ulf; Berryhil, Jeffrey; Biery, Kurt; Bose, Tulika; Brett, Angela; Branson, James; Cano, Eric; Cheung, Harry; Ciganek, Marek; Cittolin, Sergio; Coarasa, Jose Antonio; Dahmes, Bryan; Deldicque, Christian; Dusinberre, Elizabeth; Erhan, Samim; Gigi, Dominique; Glege, Frank; Gomez-Reino, Robert; Gutleber, Johannes; Hatton, Derek; Laurens, Jean-Francois; Loizides, Constantin; Ma, Frank; Meijers, Frans; Meschi, Emilio; Meyer, Andreas; Mommsen, Remigius K; Moser, Roland; O'Dell, Vivian; Oh, Alexander; Orsini, Luciano; Patras, Vaios; Paus, Christoph; Petrucci, Andrea; Pieri, Marco; Racz, Attila; Sakulin, Hannes; Sani, Matteo; Schieferdeckerd, Philipp; Schwick, Christoph; Serrano Margaleff, Josep Francesc; Shpakov, Dennis; Simon, Sean; Sumorok, Konstanty; Sungho Yoon, Andre; Wittich, Peter; Zanetti, Marco

    2009-01-01

    The CMS experiment will collect data from the proton-proton collisions delivered by the Large Hadron Collider (LHC) at a centre-of-mass energy up to 14 TeV. The CMS trigger system is designed to cope with unprecedented luminosities and LHC bunch-crossing rates up to 40 MHz. The unique CMS trigger architecture only employs two trigger levels. The Level-1 trigger is implemented using custom electronics, while the High Level Trigger (HLT) is based on software algorithms running on a large cluster of commercial processors, the Event Filter Farm. We present the major functionalities of the CMS High Level Trigger system as of the starting of LHC beams operations in September 2008. The validation of the HLT system in the online environment with Monte Carlo simulated data and its commissioning during cosmic rays data taking campaigns are discussed in detail. We conclude with the description of the HLT operations with the first circulating LHC beams before the incident occurred the 19th September 2008.

  11. Commissioning of the CMS High Level Trigger

    Energy Technology Data Exchange (ETDEWEB)

    Agostino, Lorenzo; et al.

    2009-08-01

    The CMS experiment will collect data from the proton-proton collisions delivered by the Large Hadron Collider (LHC) at a centre-of-mass energy up to 14 TeV. The CMS trigger system is designed to cope with unprecedented luminosities and LHC bunch-crossing rates up to 40 MHz. The unique CMS trigger architecture only employs two trigger levels. The Level-1 trigger is implemented using custom electronics, while the High Level Trigger (HLT) is based on software algorithms running on a large cluster of commercial processors, the Event Filter Farm. We present the major functionalities of the CMS High Level Trigger system as of the starting of LHC beams operations in September 2008. The validation of the HLT system in the online environment with Monte Carlo simulated data and its commissioning during cosmic rays data taking campaigns are discussed in detail. We conclude with the description of the HLT operations with the first circulating LHC beams before the incident occurred the 19th September 2008.

  12. Using the automata processor for fast pattern recognition in high energy physics experiments-A proof of concept

    Science.gov (United States)

    Wang, Michael H. L. S.; Cancelo, Gustavo; Green, Christopher; Guo, Deyuan; Wang, Ke; Zmuda, Ted

    2016-10-01

    We explore the Micron Automata Processor (AP) as a suitable commodity technology that can address the growing computational needs of pattern recognition in High Energy Physics (HEP) experiments. A toy detector model is developed for which an electron track confirmation trigger based on the Micron AP serves as a test case. Although primarily meant for high speed text-based searches, we demonstrate a proof of concept for the use of the Micron AP in a HEP trigger application.

  13. Performance of ATLAS RPC Level-1 Muon trigger during the 2015 data taking

    CERN Document Server

    Corradi, Massimo; The ATLAS collaboration

    2016-01-01

    The Level-1 Muon Barrel Trigger is one of the main elements of the event selection of the ATLAS experiment at the Large Hadron Collider. Its input stage consists of an array of processors receiving the full granularity of data from Resistive Plate Chambers in the central area of the ATLAS detector ("Barrel"). The trigger efficiency and the level of synchronisation of its elements with the rest of ATLAS and the LHC clock are crucial figures of this system: many parameters of the constituent RPC detector and the trigger electronics have to be constantly and carefully checked to assure a correct functioning of the Level-1 selection. Notwithstanding the complexity of such a large array of integrated RPC detectors, the ATLAS Level-1 system has resumed operations successfully after the past 2 year shutdown, with levels similar to those of Run 1. We present the inclusive monitoring of the RPC+L1 system that we have developed to characterise the behaviour of the system, using reconstructed muons in events selected by...

  14. An On Board Processor (OBP) for OAO C

    Science.gov (United States)

    Hartenstein, R. G.

    1972-01-01

    A stored program computer and its application on OAO is considered. The parallel computer has a memory capacity of 16,384 words of 18 bits each, one central processor unit, two 4096 word memory units, and one input/output unit. The I/O has no direct data connection with the CPU so that all data flow between these two units must pass through memory by way of the memory data bus. The primary functions of the onboard computer are auxiliary command storage, spacecraft monitoring and malfunction reporting, data compression and status summary, and possible performance of emergency corrective action.

  15. The Database Driven ATLAS Trigger Configuration System

    CERN Document Server

    Martyniuk, Alex; The ATLAS collaboration

    2015-01-01

    This contribution describes the trigger selection configuration system of the ATLAS low- and high-level trigger (HLT) and the upgrades it received in preparation for LHC Run 2. The ATLAS trigger configuration system is responsible for applying the physics selection parameters for the online data taking at both trigger levels and the proper connection of the trigger lines across those levels. Here the low-level trigger consists of the already existing central trigger (CT) and the new Level-1 Topological trigger (L1Topo), which has been added for Run 2. In detail the tasks of the configuration system during the online data taking are Application of the selection criteria, e.g. energy cuts, minimum multiplicities, trigger object correlation, at the three trigger components L1Topo, CT, and HLT On-the-fly, e.g. rate-dependent, generation and application of prescale factors to the CT and HLT to adjust the trigger rates to the data taking conditions, such as falling luminosity or rate spikes in the detector readout ...

  16. PERFORMANCE EVALUATION OF OR1200 PROCESSOR WITH EVOLUTIONARY PARALLEL HPRC USING GEP

    Directory of Open Access Journals (Sweden)

    R. Maheswari

    2012-04-01

    Full Text Available In this fast computing era, most of the embedded system requires more computing power to complete the complex function/ task at the lesser amount of time. One way to achieve this is by boosting up the processor performance which allows processor core to run faster. This paper presents a novel technique of increasing the performance by parallel HPRC (High Performance Reconfigurable Computing in the CPU/DSP (Digital Signal Processor unit of OR1200 (Open Reduced Instruction Set Computer (RISC 1200 using Gene Expression Programming (GEP an evolutionary programming model. OR1200 is a soft-core RISC processor of the Intellectual Property cores that can efficiently run any modern operating system. In the manufacturing process of OR1200 a parallel HPRC is placed internally in the Integer Execution Pipeline unit of the CPU/DSP core to increase the performance. The GEP Parallel HPRC is activated /deactivated by triggering the signals i HPRC_Gene_Start ii HPRC_Gene_End. A Verilog HDL(Hardware Description language functional code for Gene Expression Programming parallel HPRC is developed and synthesised using XILINX ISE in the former part of the work and a CoreMark processor core benchmark is used to test the performance of the OR1200 soft core in the later part of the work. The result of the implementation ensures the overall speed-up increased to 20.59% by GEP based parallel HPRC in the execution unit of OR1200.

  17. Concept of a Supervector Processor: A Vector Approach to Superscalar Processor, Design and Performance Analysis

    Directory of Open Access Journals (Sweden)

    Deepak Kumar, Ranjan Kumar Behera, K. S. Pandey

    2013-07-01

    Full Text Available To maximize the available performance is always a goal in microprocessor design. In this paper a new technique has been implemented which exploits the advantage of both superscalar and vector processing technique in a proposed processor called Supervector processor. Vector processor operates on array of data called vector and can greatly improve certain task such as numerical simulation and tasks which requires huge number crunching. On other handsuperscalar processor issues multiple instructions per cyclewhich can enhance the throughput. To implement parallelism multiple vector instructions were issued and executed per cycle in superscalar fashion. Case study has been done on various benchmarks to compare the performance of proposedsupervector processor architecture with superscalar and vectorprocessor architecture. Trimaran Framework has been used in order to evaluate the performance of the proposed supervector processor scheme.

  18. Photonics and Fiber Optics Processor Lab

    Data.gov (United States)

    Federal Laboratory Consortium — The Photonics and Fiber Optics Processor Lab develops, tests and evaluates high speed fiber optic network components as well as network protocols. In addition, this...

  19. Radiation Tolerant Software Defined Video Processor Project

    Data.gov (United States)

    National Aeronautics and Space Administration — MaXentric's is proposing a radiation tolerant Software Define Video Processor, codenamed SDVP, for the problem of advanced motion imaging in the space environment....

  20. Fast Track Pattern Recognition in High Energy Physics Experiments with the Automata Processor

    CERN Document Server

    Wang, Michael H L S; Green, Christopher; Guo, Deyuan; Wang, Ke; Zmuda, Ted

    2016-01-01

    We explore the Micron Automata Processor (AP) as a suitable commodity technology that can address the growing computational needs of track pattern recognition in High Energy Physics experiments. A toy detector model is developed for which a track trigger based on the Micron AP is used to demonstrate a proof-of-principle. Although primarily meant for high speed text-based searches, we demonstrate that the Micron AP is ideally suited to track finding applications.

  1. Latent myofascial trigger points.

    Science.gov (United States)

    Ge, Hong-You; Arendt-Nielsen, Lars

    2011-10-01

    A latent myofascial trigger point (MTP) is defined as a focus of hyperirritability in a muscle taut band that is clinically associated with local twitch response and tenderness and/or referred pain upon manual examination. Current evidence suggests that the temporal profile of the spontaneous electrical activity at an MTP is similar to focal muscle fiber contraction and/or muscle cramp potentials, which contribute significantly to the induction of local tenderness and pain and motor dysfunctions. This review highlights the potential mechanisms underlying the sensory-motor dysfunctions associated with latent MTPs and discusses the contribution of central sensitization associated with latent MTPs and the MTP network to the spatial propagation of pain and motor dysfunctions. Treating latent MTPs in patients with musculoskeletal pain may not only decrease pain sensitivity and improve motor functions, but also prevent latent MTPs from transforming into active MTPs, and hence, prevent the development of myofascial pain syndrome.

  2. SMART AS A CRYPTOGRAPHIC PROCESSOR

    Directory of Open Access Journals (Sweden)

    Saroja Kanchi

    2016-05-01

    Full Text Available SMaRT is a 16-bit 2.5-address RISC-type single-cycle processor, which was recently designed and successfully mapped into a FPGA chip in our ECE department. In this paper, we use SMaRT to run the well-known encryption algorithm, Data Encryption Standard. For information security purposes, encryption is a must in today’s sophisticated and ever-increasing computer communications such as ATM machines and SIM cards. For comparison and evaluation purposes, we also map the same algorithm on the HC12, a same-size but CISC-type off-the-shelf microcontroller, Our results show that compared to HC12, SMaRT code is only 14% longer in terms of the static number of instructions but about 10 times faster in terms of the number of clock cycles, and 7% smaller in terms of code size. Our results also show that 2.5- address instructions, a SMaRT selling point, amount to 45% of the whole R-type instructions resulting in significant improvement in static number of instructions hence code size as well as performance. Additionally, we see that the SMaRT short-branch range is sufficiently wide in 90% of cases in the SMaRT code. Our results also reveal that the SMaRT novel concept of locality of reference in using the MSBs of the registers in non-subroutine branch instructions stays valid with a remarkable hit rate of 95%!

  3. The Associative Memory system for the FTK processor at ATLAS

    CERN Document Server

    Cipriani, R; The ATLAS collaboration; Donati, S; Giannetti, P; Lanza, A; Luciano, P; Magalotti, D; Piendibene, M

    2013-01-01

    Experiments at the LHC hadron collider search for extremely rare processes hidden in much larger background levels. As the experiment complexity, the accelerator backgrounds and instantaneus luminosity increase, increasingly complex and exclusive selections are necessary. We present results and performances of a new prototype of Associative Memory (AM) system, the core of the Fast Tracker processor (FTK). FTK is a real time tracking device for the ATLAS experiment trigger upgrade. The AM system provides massive computing power to minimize the online execution time of complex tracking algorithms. The time consuming pattern recognition problem, generally referred to as the "combinatorial challenge", is beat by the AM technology exploiting parallelism to the maximum level. The Associative Memory compares the event to pre-calculated "expectations" or "patterns" (pattern matching) at once and look for candidate tracks called "roads". The problem is solved by the time data are loaded into the AM devices. We report ...

  4. The Associative Memory system for the FTK processor at ATLAS

    CERN Document Server

    Cipriani, R; The ATLAS collaboration; Donati, S; Giannetti, P; Lanza, A; Luciano, P; Magalotti, D; Piendibene, M

    2013-01-01

    Modern experiments search for extremely rare processes hidden in much larger background levels. As the experiment complexity, the accelerator backgrounds and luminosity increase we need increasingly complex and exclusive selections. We present results and performances of a new prototype of Associative Memory system, the core of the Fast Tracker processor (FTK). FTK is a real time tracking device for the Atlas experiment trigger upgrade. The AM system provides massive computing power to minimize the online execution time of complex tracking algorithms. The time consuming pattern recognition problem, generally referred to as the “combinatorial challenge”, is beat by the Associative Memory (AM) technology exploiting parallelism to the maximum level: it compares the event to pre-calculated “expectations” or “patterns” (pattern matching) at once looking for candidate tracks called “roads”. The problem is solved by the time data are loaded into the AM devices. We report on the tests of the integrate...

  5. The Associative Memory system for the FTK processor at ATLAS

    CERN Document Server

    Cipriani, R; The ATLAS collaboration; Donati, S; Giannetti, P; Lanza, A; Luciano, P; Magalotti, D; Piendibene, M

    2014-01-01

    Modern experiments search for extremely rare processes hidden in much larger background levels. As the experiment complexity, the accelerator backgrounds and luminosity increase we need increasingly complex and exclusive selections. We present results and performances of a new prototype of Associative Memory system, the core of the Fast Tracker processor (FTK). FTK is a real time tracking device for the Atlas experiment trigger upgrade. The AM system provides massive computing power to minimize the online execution time of complex tracking algorithms. The time consuming pattern recognition problem, generally referred to as the “combinatorial challenge”, is beat by the Associative Memory (AM) technology exploiting parallelism to the maximum level: it compares the event to pre-calculated “expectations” or “patterns” (pattern matching) at once looking for candidate tracks called “roads”. The problem is solved by the time data are loaded into the AM devices. We report on the tests of the integrate...

  6. Optimization of adaptive fuzzy processor design

    OpenAIRE

    Baturone, I.; Sánchez-Solano, Santiago; Barriga, Angel; Huertas-Díaz, J. L.

    1998-01-01

    A fuzzy processor is programmed to provide anoptimum output for solving a given problem. It could theoretically solve any problem (from a static point of view) if it is an universal approximator. This paper addresses the design of fuzzy processors aiming at a twofold objective: efficient adaptive approximation of different and even dynamically changing surfaces and hardware simplicity. Adequate programmable parameters and a fully-parallel architecture are selected. Mixed-signal blocks b...

  7. Matrix Manipulation Algorithms for Hasse Processor Implementation

    OpenAIRE

    Hahanov, Vladimir; Dahiri, Farid

    2014-01-01

    The processor is implemented in software-hardware modules, which are based on the use of programming languages: C ++, Verilog, Python 2.7 and platforms: Microsoft Windows, X Window (in Unix and Linux) and Macintosh OS X. HDL-code generator makes it possible to automatically synthesize HDL-code of the processor structure from 1 to 16 bits for parallel processing corresponding number of input vectors or words.

  8. Keystone Business Models for Network Security Processors

    OpenAIRE

    Arthur Low; Steven Muegge

    2013-01-01

    Network security processors are critical components of high-performance systems built for cybersecurity. Development of a network security processor requires multi-domain experience in semiconductors and complex software security applications, and multiple iterations of both software and hardware implementations. Limited by the business models in use today, such an arduous task can be undertaken only by large incumbent companies and government organizations. Neither the “fabless semiconductor...

  9. Software-defined universal microwave photonics processor

    OpenAIRE

    Pérez, Daniel; Gasulla Mestre, Ivana; Capmany Francoy, José

    2015-01-01

    We propose, for the first time to our knowledge, a software-defined reconfigurable microwave photonics signal processor architecture that can be integrated on a chip and is capable of performing all the main functionalities by suitable programming of its control signals. The basic configuration is presented and a thorough end-to-end design model derived that accounts for the performance of the overall processor taking into consideration the impact and interdependencies of both its photonic an...

  10. A hardware and software overview of the Delphi contiguity trigger

    International Nuclear Information System (INIS)

    The contiguity processor of the Delphi detector, which is composed of 12 Fastbus modules (one for each TPC sector), is the main second-level track trigger component in the experiment. More than 3000 Mips of processing power are achieved by 4608 processing elements (PE) packed in specially designed ASIC IC's. High interconnectivity among PE's (bidimensional lattice) and a highly parallel algorithm (contiguity mask) allow a three-dimensional vertex reconstruction in less than 5μs. In this paper an overview of the single instruction multiple data (SIMD) architecture, together with the programming language and the interactive debugging tools for the processor, are given

  11. Identifying asthma triggers.

    Science.gov (United States)

    McCarty, Justin C; Ferguson, Berrylin J

    2014-02-01

    Asthma has many triggers including rhinosinusitis; allergy; irritants; medications (aspirin in aspirin-exacerbated respiratory disease); and obesity. Paradoxic vocal fold dysfunction mimics asthma and may be present along with asthma. This article reviews each of these triggers, outlining methods of recognizing the trigger and then its management. In many patients more than one trigger may be present. Full appreciation of the complexity of these relationships and targeted therapy to the trigger is needed to best care for the patient with asthma.

  12. 7 CFR 1160.108 - Fluid milk processor.

    Science.gov (United States)

    2010-01-01

    ... 7 Agriculture 9 2010-01-01 2009-01-01 true Fluid milk processor. 1160.108 Section 1160.108... Order Definitions § 1160.108 Fluid milk processor. (a) Fluid milk processor means any person who... term fluid milk processor shall not include in each of the respective fiscal periods those persons...

  13. The D/Ø Silicon Track Trigger

    Science.gov (United States)

    Steinbrück, Georg

    2003-09-01

    We describe a trigger preprocessor to be used by the D Ø experiment for selecting events with tracks from the decay of long-lived particles. This Level 2 impact parameter trigger utilizes information from the Silicon Microstrip Tracker to reconstruct tracks with improved spatial and momentum resolutions compared to those obtained by the Level 1 tracking trigger. It is constructed of VME boards with much of the logic existing in programmable processors. A common motherboard provides the I/O infrastructure and three different daughter boards perform the tasks of identifying the roads from the tracking trigger data, finding the clusters in the roads in the silicon detector, and fitting tracks to the clusters. This approach provides flexibility for the design, testing and maintenance phases of the project. The track parameters are provided to the trigger framework in 25 μs. The effective impact parameter resolution for high-momentum tracks is 35 μm, dominated by the size of the Tevatron beam.

  14. The LHCb level 1 vertex trigger

    CERN Document Server

    Koratzinos, M

    1999-01-01

    Summary form only given. The Level 1 Vertex trigger of LHCb has certain features that make it unique amongst the LHC experiment trigger schemes: The problem it addresses is a reduction factor of 25 for minimum bias events while retaining good efficiency for signal B events. The best way to achieve such reduction factors is to rely on the most striking property of those B events, the long decay time of the B particles. The trigger therefore has to reconstruct the event around the interaction region and tag signal events using topological criteria. An accurate vertex detector is one of the key components of LHCb and a natural choice for providing the data for such a triggering scheme. The algorithm for the reconstruction of the event is complicated and not readily parallelisable in its totality. We are therefore proposing an architecture that resembles a high-level trigger architecture, where the event building function is performed by a switch network and each event is processed by a single processor, part of ...

  15. PRODUCTIVE CO PROCESSOR DESIGN BASED ON PROGRAM BENCHMARK

    OpenAIRE

    P. S. Balamurugan; Dr. K.THANUSHKODI

    2010-01-01

    The objective of this paper is to design a methodology where many co-processors are accessed by the processor in array mode. By using co processor, the work on the multi core processor gets reduced by accessing it in array manner. A multi core processor is an efficient processor which can enable parallel processing and perform multi threading effectively. In this paper, in order to improve the performance of multi-core processor two major factors are taken intoconsideration one is to improve ...

  16. PRODUCTIVE CO PROCESSOR DESIGN BASED ON PROGRAM BENCHMARK

    Directory of Open Access Journals (Sweden)

    P. S. BALAMURUGAN

    2010-09-01

    Full Text Available The objective of this paper is to design a methodology where many co-processors are accessed by the processor in array mode. By using co processor, the work on the multi core processor gets reduced by accessing it in array manner. A multi core processor is an efficient processor which can enable parallel processing and perform multi threading effectively. In this paper, in order to improve the performance of multi-core processor two major factors are taken intoconsideration one is to improve the execution of array methodology by using co processor and other is yo design an array based co processor to improve the hit ratio of the co processor.

  17. The new Global Muon Trigger of the CMS experiment

    CERN Document Server

    Fulcher, Jonathan Richard; Rabady, Dinyar Sebastian; Reis, Thomas; Sakulin, Hannes

    2016-01-01

    For the 2016 physics data runs the L1 trigger system of the Compact Muon Solenoid (CMS) experiment underwent a major upgrade to cope with the increasing instantaneous luminosity of the CERN LHC whilst maintaining a high event selection efficiency for the CMS physics program. Most subsystem specific trigger processor boards were replaced with powerful general purpose processor boards, conforming to the MicroTCA standard, whose tasks are performed by firmware on an FPGA of the Xilinx Virtex 7 family. Furthermore, the muon trigger system moved from a subsystem centered approach, where each of the three muon detector systems provides muon candidates to the Global Muon Trigger (GMT), to a region based system, where muon track finders (TFs) combine information from the subsystems to generate muon candidates in three detector regions, that are then sent to the upgraded GMT. The upgraded GMT receives up to 108 muons from the processors of the muon TFs in the barrel, overlap, and endcap detector regions. The muons are...

  18. A lock circuit for a multi-core processor

    OpenAIRE

    Strøm, Torur Biskopstø

    2015-01-01

    An integrated circuit comprising a multiple processor cores and a lock circuit that comprises a queue register with respective bits set or reset via respective, connections dedicated to respective processor cores, whereby the queue register identifies those among the multiple processor cores that are enqueued in the queue register. Furthermore, the integrated circuit comprises a current register and a selector circuit configured to select a processor core and identify that processor core by a...

  19. A time-multiplexed track-trigger architecture for CMS

    International Nuclear Information System (INIS)

    The CMS Tracker under development for the High Luminosity LHC includes an outer tracker based on ''PT-modules'' which will provide track stubs based on coincident clusters in two closely spaced sensor layers, aiming to reject low transverse momentum track hits before data transmission to the Level-1 trigger. The tracker data will be used to reconstruct track segments in dedicated processors before onward transmission to other trigger processors which will combine tracker information with data originating from the calorimeter and muon detectors, to make the final L1 trigger decision. The architecture for processing the tracker data is still an open question. One attractive option is to explore a Time Multiplexed design similar to one which is currently being implemented in the CMS calorimeter trigger as part of the Phase I trigger upgrade. The Time Multiplexed Trigger concept is explained, the potential benefits of applying it for processing future tracker data are described and a possible design based on currently existing hardware is presented

  20. Run-Time Adaptive Processor Allocation of Self-Configurable Intel IXP2400 Network Processor

    Directory of Open Access Journals (Sweden)

    A.Satheesh

    2010-03-01

    Full Text Available An ideal Network Processor, that is, a programmable multi-processor device must be capable of offering both the flexibility and speed required for packet processing. But current Network Processor systems generally fall short of the above benchmarks due to traffic fluctuations inherent in packet networks, and the resulting workload variation on individual pipeline stage over a period of time ultimately affects the overall performance of even an otherwise sound system. One potential solution would be to change the code running at these stages so as to adapt to the fluctuations; a near robust system with standing traffic fluctuations is the dynamic adaptive processor, reconfiguring the entire system, which we introduce and study to some extent in this paper. We achieve this by using a crucial decision making model, transferring the binary code to the processor through the SOAP protocol.

  1. Direct Processor Access for Non Dedicated Server using Multi Core Processor

    Directory of Open Access Journals (Sweden)

    P. S. BALAMURUGAN,

    2010-08-01

    Full Text Available The objective of the paper is to design a co processor for a desktop machine which enables the machine to act as non dedicated server, such that the co processor will act as a server processor and the multi-core processor to act as desktop processor. By implementing this methodology a client machine can be made to act as a non dedicated server and a client machine. This type of machine can be used in autonomy networks. This design will lead to design of a cost effective server and machine which can parallel act as a non dedicatedserver and a client machine or it can be made to switch and act as client or server.

  2. Functional Verification of Enhanced RISC Processor

    Directory of Open Access Journals (Sweden)

    SHANKER NILANGI

    2013-10-01

    Full Text Available This paper presents design and verification of a 32-bit enhanced RISC processor core having floating point computations integrated within the core, has been designed to reduce the cost and complexity. The designed 3 stage pipelined 32-bit RISC processor is based on the ARM7 processor architecture with single precision floating point multiplier, floating point adder/subtractor for floating point operations and 32 x 32 booths multiplier added to the integer core of ARM7. The binary representation of the floating point numbers employed in the design eliminates the need for floating point registers and uses same set of registers thereby reducing the complexity, area and cost. Mask based data reversal barrel shifter performs parallel flag computations during shift or rotate and has least worst case delay of 0.94 ns compared to other barrel shifters. The hardware of the 32-bit RISC processor core has been modeled in Verilog HDL, simulated in VCS. Verification of a complex design such as 32-bit RISC is one of the major challenges as it consumes more time. In this work, a verification environment is being developed to verify the design RISC processor core.

  3. Centralized digital control of accelerators

    International Nuclear Information System (INIS)

    In contrasting the title of this paper with a second paper to be presented at this conference entitled Distributed Digital Control of Accelerators, a potential reader might be led to believe that this paper will focus on systems whose computing intelligence is centered in one or more computers in a centralized location. Instead, this paper will describe the architectural evolution of SLAC's computer based accelerator control systems with respect to the distribution of their intelligence. However, the use of the word centralized in the title is appropriate because these systems are based on the use of centralized large and computationally powerful processors that are typically supported by networks of smaller distributed processors

  4. A Time-Multiplexed Track-Trigger for the CMS HL-LHC upgrade

    CERN Document Server

    Hall, Geoffrey

    2015-01-01

    A new CMS Tracker is under development for operation at the High Luminosity LHC from 2025. It includes an outer tracker based on special modules of two different types which will construct track stubs using spatially coincident clusters in two closely spaced sensor layers, to reject low transverse momentum track hits and reduce the data volume before data transmission to the Level-1 trigger. The tracker data will be used to reconstruct track segments in dedicated processors before onward transmission to other trigger processors which will combine tracker information with data originating from the calorimeter and muon detectors, to make the final L1 trigger decision. The architecture for processing the tracker data outside the detector is under study, using several alternative approaches. One attractive possibility is to exploit a Time Multiplexed design similar to the one which is currently being implemented in the CMS calorimeter trigger as part of the Phase I trigger upgrade. The novel Time Multiplexed Trig...

  5. Asthma triggers (image)

    Science.gov (United States)

    ... things make your asthma worse. These are called asthma "triggers". Avoiding them is your first step toward feeling better. The most common asthma triggers are mold, pets, dust, grasses, pollen, cockroaches, odors ...

  6. Criticality calculations on BARC parallel processor- ANUPAM

    International Nuclear Information System (INIS)

    Parallel processing offers an increase in computational speed beyond the technological limitations of single processor systems. BARC has recently developed a parallel processing system (ANUPAM) based Multiple Instruction Multiple Data (MIMD) distributed memory architecture. In the work reported here, the sequential version of Monte Carlo code MONALI is modified to work on the ANUPAM for criticality calculations. The problem of random number generation in a parallel environment is handled using leapfrog technique. The code is modified to use variable number of slave processors. The parallel version of MONALI is used to calculate multiplication factor, fluxes and absorptions in one of the 8x8 fuel assemblies of IAEA BWR benchmark in 69 groups. To compare gain in execution time, the benchmark is also solved on LANDMARK and ND-570 systems (both serial) using the sequential version of the code. Speedup and efficiencies achieved on varying the number of slave processors are encouraging. (author). 5 refs., 1 tab

  7. SWIFT Privacy: Data Processor Becomes Data Controller

    Directory of Open Access Journals (Sweden)

    Edwin Jacobs

    2007-04-01

    Full Text Available Last month, SWIFT emphasised the urgent need for a solution to compliance with US Treasury subpoenas that provides legal certainty for the financial industry as well as for SWIFT. SWIFT will continue its activities to adhere to the Safe Harbor framework of the European data privacy legislation. Safe Harbor is a framework negotiated by the EU and US in 2000 to provide a way for companies in Europe, with operations in the US, to conform to EU data privacy regulations. This seems to conclude a complex privacy case, widely covered by the US and European media. A fundamental question in this case was who is a data controller and who is a mere data processor. Both the Belgian and the European privacy authorities considered SWIFT, jointly with the banks, as a data controller whereas SWIFT had considered itself as a mere data processor that processed financial data for banks. The difference between controller and processor has far reaching consequences.

  8. ETHERNET PACKET PROCESSOR FOR SOC APPLICATION

    Directory of Open Access Journals (Sweden)

    Raja Jitendra Nayaka

    2012-07-01

    Full Text Available As the demand for Internet expands significantly in numbers of users, servers, IP addresses, switches and routers, the IP based network architecture must evolve and change. The design of domain specific processors that require high performance, low power and high degree of programmability is the bottleneck in many processor based applications. This paper describes the design of ethernet packet processor for system-on-chip (SoC which performs all core packet processing functions, including segmentation and reassembly, packetization classification, route and queue management which will speedup switching/routing performance. Our design has been configured for use with multiple projects ttargeted to a commercial configurable logic device the system is designed to support 10/100/1000 links with a speed advantage. VHDL has been used to implement and simulated the required functions in FPGA.

  9. Control structures for high speed processors

    Science.gov (United States)

    Maki, G. K.; Mankin, R.; Owsley, P. A.; Kim, G. M.

    1982-01-01

    A special processor was designed to function as a Reed Solomon decoder with throughput data rate in the Mhz range. This data rate is significantly greater than is possible with conventional digital architectures. To achieve this rate, the processor design includes sequential, pipelined, distributed, and parallel processing. The processor was designed using a high level language register transfer language. The RTL can be used to describe how the different processes are implemented by the hardware. One problem of special interest was the development of dependent processes which are analogous to software subroutines. For greater flexibility, the RTL control structure was implemented in ROM. The special purpose hardware required approximately 1000 SSI and MSI components. The data rate throughput is 2.5 megabits/second. This data rate is achieved through the use of pipelined and distributed processing. This data rate can be compared with 800 kilobits/second in a recently proposed very large scale integration design of a Reed Solomon encoder.

  10. Programmable DNA-mediated multitasking processor

    CERN Document Server

    Shu, Jian-Jun; Yong, Kian-Yan; Shao, Fangwei; Lee, Kee Jin

    2015-01-01

    Because of DNA appealing features as perfect material, including minuscule size, defined structural repeat and rigidity, programmable DNA-mediated processing is a promising computing paradigm, which employs DNAs as information storing and processing substrates to tackle the computational problems. The massive parallelism of DNA hybridization exhibits transcendent potential to improve multitasking capabilities and yield a tremendous speed-up over the conventional electronic processors with stepwise signal cascade. As an example of multitasking capability, we present an in vitro programmable DNA-mediated optimal route planning processor as a functional unit embedded in contemporary navigation systems. The novel programmable DNA-mediated processor has several advantages over the existing silicon-mediated methods, such as conducting massive data storage and simultaneous processing via much fewer materials than conventional silicon devices.

  11. ATLAS calorimetry. Trigger, simulation and jet calibration

    International Nuclear Information System (INIS)

    The Pre-Processor system of the ATLAS Level-1 Calorimeter Trigger performs complex processing of analog trigger tower signals from electromagnetic and hadronic calorimeters. The main processing block of the Pre-Processor System is the Multi-Chip Module (MCM). The first part of this thesis describes MCM quality assurance tests that have been developed, their use in the MCM large scale production and the results that have been obtained. In the second part of the thesis a validation of a shower parametrisation model for the ATLAS fast simulation package ATLFAST based on QCD dijet events is performed. A detailed comparison of jet response and jet energy resolution between the fast and the full simulation is presented. The uniformity of the calorimeter response has a significant impact on the accuracy of the jet energy measurement. A study of the calorimeter intercalibration using QCD dijet events is presented in the last part of the thesis. The intercalibration study is performed in azimuth angle φ and in pseudorapidity η. The performance of the calibration methods including possible systematic and statistical effects is described. (orig.)

  12. The ATLAS Level-1 Calorimeter Trigger Architecture

    CERN Document Server

    Garvey, J; Mahout, G; Moye, T H; Staley, R J; Watkins, P M; Watson, A T; Achenbach, R; Hanke, P; Kluge, E E; Meier, K; Meshkov, P; Nix, O; Penno, K; Schmitt, K; Ay, Cc; Bauss, B; Dahlhoff, A; Jakobs, K; Mahboubi, K; Schäfer, U; Trefzger, T M; Eisenhandler, E F; Landon, M; Moyse, E; Thomas, J; Apostoglou, P; Barnett, B M; Brawn, I P; Davis, A O; Edwards, J; Gee, C N P; Gillman, A R; Perera, V J O; Qian, W; Bohm, C; Hellman, S; Hidvégi, A; Silverstein, S; RT 2003 13th IEEE-NPSS Real Time Conference

    2004-01-01

    The architecture of the ATLAS Level-1 Calorimeter Trigger system (L1Calo) is presented. Common approaches have been adopted for data distribution, result merging, readout, and slow control across the three different subsystems. A significant amount of common hardware is utilized, yielding substantial savings in cost, spares, and development effort. A custom, high-density backplane has been developed with data paths suitable for both the em/tt cluster processor (CP) and jet/energy-summation processor (JEP) subsystems. Common modules also provide interfaces to VME, CANbus and the LHC Timing, Trigger and Control system (TTC). A common data merger module (CMM) uses FPGAs with multiple configurations for summing electron/photon and tau/hadron cluster multiplicities, jet multiplicities, or total and missing transverse energy. The CMM performs both crate- and system-level merging. A common, FPGA-based readout driver (ROD) is used by all of the subsystems to send input, intermediate and output data to the data acquis...

  13. ATLAS calorimetry. Trigger, simulation and jet calibration

    Energy Technology Data Exchange (ETDEWEB)

    Weber, P.

    2007-02-06

    The Pre-Processor system of the ATLAS Level-1 Calorimeter Trigger performs complex processing of analog trigger tower signals from electromagnetic and hadronic calorimeters. The main processing block of the Pre-Processor System is the Multi-Chip Module (MCM). The first part of this thesis describes MCM quality assurance tests that have been developed, their use in the MCM large scale production and the results that have been obtained. In the second part of the thesis a validation of a shower parametrisation model for the ATLAS fast simulation package ATLFAST based on QCD dijet events is performed. A detailed comparison of jet response and jet energy resolution between the fast and the full simulation is presented. The uniformity of the calorimeter response has a significant impact on the accuracy of the jet energy measurement. A study of the calorimeter intercalibration using QCD dijet events is presented in the last part of the thesis. The intercalibration study is performed in azimuth angle {phi} and in pseudorapidity {eta}. The performance of the calibration methods including possible systematic and statistical effects is described. (orig.)

  14. Time Manager Software for a Flight Processor

    Science.gov (United States)

    Zoerne, Roger

    2012-01-01

    Data analysis is a process of inspecting, cleaning, transforming, and modeling data to highlight useful information and suggest conclusions. Accurate timestamps and a timeline of vehicle events are needed to analyze flight data. By moving the timekeeping to the flight processor, there is no longer a need for a redundant time source. If each flight processor is initially synchronized to GPS, they can freewheel and maintain a fairly accurate time throughout the flight with no additional GPS time messages received. How ever, additional GPS time messages will ensure an even greater accuracy. When a timestamp is required, a gettime function is called that immediately reads the time-base register.

  15. Making CSB+-Tree Processor Conscious

    DEFF Research Database (Denmark)

    Samuel, Michael; Pedersen, Anders Uhl; Bonnet, Philippe

    2005-01-01

    Cache-conscious indexes, such as CSB+-tree, are sensitive to the underlying processor architecture. In this paper, we focus on how to adapt the CSB+-tree so that it performs well on a range of different processor architectures. Previous work has focused on the impact of node size on the performan...... a systematic method for adapting CSB+-tree to new platforms. This work is a first step towards integrating CSB+-tree in MySQL’s heap storage manager....

  16. Efficient SIMD optimization for media processors

    Institute of Scientific and Technical Information of China (English)

    Jian-peng ZHOU; Ce SHI

    2008-01-01

    Single instruction multiple data (SIMD) instructions are often implemented in modem media processors. Although SIMD instructions are useful in multimedia applications, most compilers do not have good support for SIMD instructions. This paper focuses on SIMD instructions generation for media processors. We present an efficient code optimization approach that is integrated into a retargetable C compiler. SIMD instructions are generated by finding and combining the same operations in programs. Experimental results for the UltraSPARC VIS instruction set show that a speedup factor up to 2.639 is obtained.

  17. Multi-core processors - An overview

    CERN Document Server

    Venu, Balaji

    2011-01-01

    Microprocessors have revolutionized the world we live in and continuous efforts are being made to manufacture not only faster chips but also smarter ones. A number of techniques such as data level parallelism, instruction level parallelism and hyper threading (Intel's HT) already exists which have dramatically improved the performance of microprocessor cores. This paper briefs on evolution of multi-core processors followed by introducing the technology and its advantages in today's world. The paper concludes by detailing on the challenges currently faced by multi-core processors and how the industry is trying to address these issues.

  18. Studies for the development of the Inner Detector trigger algorithms at ATLAS

    CERN Document Server

    The ATLAS collaboration

    2013-01-01

    A description of the ATLAS Inner Detector (ID) sofware trigger algorithms running online on the high level trigger (HLT) processor farm is presented. The prospects for a redesign of the ID trigger afforded by the 2013-2014 long shutdown are discussed. The ID trigger HLT algorithms are essential for many trigger signatures within the ATLAS trigger. During the shutdown, the ATLAS HLT software will be restructured to run in a single stage rather than in the two distinct levels present during the Run I operation. This poses significant challenges for the trigger algorithms both in terms of execution time, and physics perfor- mance. Expected future improvements in the timing and efficiencies of the Inner Detector triggers within the new merged single stage architecture are also discussed. In addition, potential improvements in the algorithm performance resulting from the additional spacepoint information from the new Insertable B-Layer are also presented.

  19. The TriggerTool Graphical User Interface to the ATLAS Trigger Configuration Database

    CERN Document Server

    Bell, P; Brunet, S; Fischer, G; Goebel, M; Haller, J; Head, S; Höcker, A; Kohno, T; Martyniuk, A; Nozicka, M; Owen, M; Spiwoks, R; Stelzer, J; Wengler, T; Wiedenmann, W

    2009-01-01

    A system has been designed and implemented to configure all three levels of the ATLAS trigger system from a centrally provided relational database, in which an archive of all trigger configurations used in data taking is also maintained. The user interaction with this database is via a Java-based graphical user interface known as the TriggerTool. We describe here how the TriggerTool has been designed to fulfill several different roles for users of varying expertise, from being a browser of the database to a tool for creating and modifying configurations

  20. Comparison of Processor Performance of SPECint2006 Benchmarks of some Intel Xeon Processors

    Directory of Open Access Journals (Sweden)

    Abdul Kareem PARCHUR

    2012-08-01

    Full Text Available High performance is a critical requirement to all microprocessors manufacturers. The present paper describes the comparison of performance in two main Intel Xeon series processors (Type A: Intel Xeon X5260, X5460, E5450 and L5320 and Type B: Intel Xeon X5140, 5130, 5120 and E5310. The microarchitecture of these processors is implemented using the basis of a new family of processors from Intel starting with the Pentium 4 processor. These processors can provide a performance boost for many key application areas in modern generation. The scaling of performance in two major series of Intel Xeon processors (Type A: Intel Xeon X5260, X5460, E5450 and L5320 and Type B: Intel Xeon X5140, 5130, 5120 and E5310 has been analyzed using the performance numbers of 12 CPU2006 integer benchmarks, performance numbers that exhibit significant differences in performance. The results and analysis can be used by performance engineers, scientists and developers to better understand the performance scaling in modern generation processors.

  1. Inter Processor Communication for Fault Diagnosis in Multiprocessor Systems

    Directory of Open Access Journals (Sweden)

    C. D. Malleswar

    1994-04-01

    Full Text Available In the preseJlt paper a simple technique is proposed for fault diagnosis for multiprocessor and multiple system environments, wherein all microprocessors in the system are used in part to check the health of their neighbouring processors. It involves building simple fail-safe serial communication links between processors. Processors communicate with each other over these links and each processor is made to go through certain sequences of actions intended for diagnosis, under the observation of another processor .With limited overheads, fault detection can be done by this method. Also outlined are some of the popular techniques used for health check of processor-based systems.

  2. gFEX, the ATLAS Calorimeter Level-1 Real Time Processor

    CERN Document Server

    Tang, Shaochun; The ATLAS collaboration; Chen, Hucheng; Lanni, Francesco; Takai, Helio; Wu, Weihao

    2015-01-01

    The global feature extractor (gFEX) is a component of the Level-1 Calorimeter trigger Phase-I upgrade for the ATLAS experiment. It is intended to identify patterns of energy associated with the hadronic decays of high momentum Higgs, W, & Z bosons, top quarks, and exotic particles in real time at the LHC crossing rate. The single processor board will be packaged in an Advanced Telecommunications Computing Architecture (ATCA) module and implemented as a fast reconfigurable processor based on three Xilinx Vertex Ultra-scale FPGAs. The board will receive coarse-granularity information from all the ATLAS calorimeters on 276 optical fibers with the data transferred at the 40 MHz Large Hadron Collider (LHC) clock frequency. The gFEX will be controlled by a single system-on-chip processor, ZYNQ, that will be used to configure all the processor Field-Programmable Gate Array (FPGAs), monitor board health, and interface to external signals. Now, the pre-prototype board which includes one ZYNQ and one Vertex-7 FPGA ...

  3. gFEX, the ATLAS Calorimeter Level 1 Real Time Processor

    CERN Document Server

    Tang, Shaochun; The ATLAS collaboration

    2015-01-01

    The global feature extractor (gFEX) is a component of the Level-1Calorimeter trigger Phase-I upgrade for the ATLAS experiment. It is intended to identify patterns of energy associated with the hadronic decays of high momentum Higgs, W, & Z bosons, top quarks, and exotic particles in real time at the LHC crossing rate. The single processor board will be packaged in an Advanced Telecommunications Computing Architecture (ATCA) module and implemented as a fast reconfigurable processor based on three Xilinx Ultra-scale FPGAs. The board will receive coarse-granularity information from all the ATLAS calorimeters on 264 optical fibers with the data transferred at the 40 MHz LHC clock frequency. The gFEX will be controlled by a single system-on-chip processor, ZYNQ, that will be used to configure all the processor FPGAs, monitor board health, and interface to external signals. Now, the pre-prototype board which includes one ZYNQ and one Vertex-7 FPGA has been designed for testing and verification. The performance ...

  4. Accuracy of the lattice-Boltzmann method using the Cell processor

    Science.gov (United States)

    Harvey, M. J.; de Fabritiis, G.; Giupponi, G.

    2008-11-01

    Accelerator processors like the new Cell processor are extending the traditional platforms for scientific computation, allowing orders of magnitude more floating-point operations per second (flops) compared to standard central processing units. However, they currently lack double-precision support and support for some IEEE 754 capabilities. In this work, we develop a lattice-Boltzmann (LB) code to run on the Cell processor and test the accuracy of this lattice method on this platform. We run tests for different flow topologies, boundary conditions, and Reynolds numbers in the range Re=6 350 . In one case, simulation results show a reduced mass and momentum conservation compared to an equivalent double-precision LB implementation. All other cases demonstrate the utility of the Cell processor for fluid dynamics simulations. Benchmarks on two Cell-based platforms are performed, the Sony Playstation3 and the QS20/QS21 IBM blade, obtaining a speed-up factor of 7 and 21, respectively, compared to the original PC version of the code, and a conservative sustained performance of 28 gigaflops per single Cell processor. Our results suggest that choice of IEEE 754 rounding mode is possibly as important as double-precision support for this specific scientific application.

  5. Design of Variable Width Barrel Shifter for High Speed Processor Architecture

    Directory of Open Access Journals (Sweden)

    Rajeev Kumar

    2012-04-01

    Full Text Available Microprocessor is the brain of the computer. It works as the Central Processing Unit of the computer. It contains Arithmetic Logical Unit (ALU that performs the arithmetic operations such as Addition, Subtraction, Multiplication and Division. It also performs the Logical operations such as AND, NAND, OR, NOR, EXOR, EXNOR and NOT. It also contains register file to store the operand in load/store instructions in RISC Processor Architecture. Control Unit genetares the control signals that synchronize the operation of the processor which tells the microarchitecture which operation is done at which time. Now during the multiplication partial product is shifted and added. So shifter is an important part of the processor architecture. Barrel Shifter is an important combinational logic block. It was incorporated in 386 processor and is also used in microcontroller design. Intel has since moved to software implemented shifters in the Pentium 4 Processor Architecture but AMD still uses it. Here the design of the variable width barrel shifter is presented in which we can shift 4bit, 8bit, 16bit, and 32bit and maximum 64bit partial product during multiplication. Functionality is check using Modelsim 6.4a.Now to generate the gate level netlist Xilinx ISE 9.2i is used.

  6. Design and use of a PPMC processor as shared-memory SCI node

    CERN Document Server

    Altmann, D; Müller, H; Toledo, J

    2002-01-01

    The MCU mezzanine was designed as a networked processor-PMC for monitoring and control in the LHCb Readout Unit (RU) with remote boot capability. As PCI monarch on the RU, it configures all PCI devices (FPGAs and readout network interface) that can then be used by user programs running under the LINUX operating system. A new MCU application is within the LHCb L1-Velo trigger where a CPU-farm is interconnected by a 2-dimensional SCI network, with event data input from RU modules at each row of the network: the SCI interface on the RU is hosted by the MCU which exports and imports shareable memory with the trigger farm in order to quasi become part as one of it's CPU. After this initialisation, the hardware DMA engines of the RU can transfer trigger data, by using physical PCI addresses that directly map to the remote CPU memory. (10 refs).

  7. Parallel Neutrino Triggers using GPUs for an underwater telescope

    CERN Document Server

    Bouhadef, Bachir; Terreni, Giuseppe

    2014-01-01

    Graphics Processing Units are high performance co-processors originally intended to improve the use and the acceleration of computer graphics applications. Because of their performance, researchers have extended their use beyond the computer graphics scope. We have investigate the possibility of implementing and speeding up online neutrino trigger algorithms in the KM3Net-It experiment using a CPU-GPU system. The results of a neutrino trigger simulation on NEMO Phase II tower and a KM3-It 14 floors Tower are reported.

  8. Boosted object hardware trigger development and testing for the Phase I upgrade of the ATLAS Experiment

    Science.gov (United States)

    Stark, Giordon; Atlas Collaboration

    2015-04-01

    The Global Feature Extraction (gFEX) module is a Level 1 jet trigger system planned for installation in ATLAS during the Phase 1 upgrade in 2018. The gFEX selects large-radius jets for capturing Lorentz-boosted objects by means of wide-area jet algorithms refined by subjet information. The architecture of the gFEX permits event-by-event local pile-up suppression for these jets using the same subtraction techniques developed for offline analyses. The gFEX architecture is also suitable for other global event algorithms such as missing transverse energy (MET), centrality for heavy ion collisions, and ``jets without jets.'' The gFEX will use 4 processor FPGAs to perform calculations on the incoming data and a Hybrid APU-FPGA for slow control of the module. The gFEX is unique in both design and implementation and substantially enhance the selectivity of the L1 trigger and increases sensitivity to key physics channels.

  9. Boosted object hardware trigger development and testing for the Phase I upgrade of the ATLAS Experiment

    CERN Document Server

    Stark, Giordon Holtsberg; The ATLAS collaboration

    2015-01-01

    The Global Feature Extraction (gFEX) module is a Level 1 jet trigger system planned for installation in ATLAS during the Phase 1 upgrade in 2018. The gFEX selects large-radius jets for capturing Lorentz-boosted objects by means of wide-area jet algorithms refined by subjet information. The architecture of the gFEX permits event-by-event local pile-up suppression for these jets using the same subtraction techniques developed for offline analyses. The gFEX architecture is also suitable for other global event algorithms such as missing transverse energy (MET), centrality for heavy ion collisions, and "jets without jets". The gFEX will use 4 processor FPGAs to perform calculations on the incoming data and a Hybrid APU-FPGA for slow control of the module. The gFEX is unique in both design and implementation and substantially enhance the selectivity of the L1 trigger and increases sensitivity to key physics channels.

  10. L0 trigger unit prototype for BM@N setup

    Science.gov (United States)

    Batenkov, O. I.; Bogoslovski, D. N.; Rogov, V. Y.; Sergeev, S. V.; Yurevich, V. I.

    2016-09-01

    The BM@N facility is a fixed target experiment based on heavy ion beams of the Nuclotron-M accelerator. The aim of the BM@N is to study nucleus - nucleus collisions at energies up to 4.5 GeV per nucleon. A level 0 trigger processor unit (Trigger L0 unit, T0U) for the BM@N deuterons and carbon ions at Run'2015 has been developed. The T0U is used to generate a BM@N zero level trigger and a TOF detector precise start.T0U generates trigger signal based on beam line and target area detector signals. This module also provides both control and monitoring of the detector front-end electronics power supplies. This article presents a concept, characteristics and test results of the T0U module during the Run 2015.

  11. Aladdin signal processor and architecture modeling

    Science.gov (United States)

    Branstetter, Reagan; Harper, Angela; Denton, Larry

    1993-10-01

    Texas Instruments (TI) is developing the Aladdin computer under contract with the U. S. Army Communications and Electronics Command (CECOM). The program is sponsored by the Defense Advanced Research Projects Agency (DARPA) and the U. S. Army Night Vision and Electro-Optics Directorate (NVEOD). Processors currently available for today's advanced weapons systems are limited in their real-time processing capabilities and are generally specific to a selected mission. The lack of availability of a high performance, general purpose, programmable processor in a small volume applicable to a variety of weapons systems applications creates a high non-recurring development cost for each new program. Automatic target acquisition systems are specifically in need of processors that meet the required real- time processing throughput of a variety of algorithms within very restrictive volume constraints. The objective of the Aladdin program is to develop a very high performance miniature processor that fits within a 75 cubic inch cylindrical volume, and is easily programmable to provide the ability to detect, recognize, identify, and locate the optimal aimpoint of a target or targets.

  12. Practical guide to energy management for processors

    CERN Document Server

    Consortium, Energywise

    2012-01-01

    Do you know how best to manage and reduce your energy consumption? This book gives comprehensive guidance on effective energy management for organisations in the polymer processing industry. This book is one of three which support the ENERGYWISE Plastics Project eLearning platform for European plastics processors to increase their knowledge and understanding of energy management. Topics covered include: Understanding Energy,

  13. Noise limitations in optical linear algebra processors.

    Science.gov (United States)

    Batsell, S G; Jong, T L; Walkup, J F; Krile, T F

    1990-05-10

    A general statistical noise model is presented for optical linear algebra processors. A statistical analysis which includes device noise, the multiplication process, and the addition operation is undertaken. We focus on those processes which are architecturally independent. Finally, experimental results which verify the analytical predictions are also presented.

  14. Acousto-Optical/Electronic Processor For SAR

    Science.gov (United States)

    Bicknell, T. J.; Farr, W. H.

    1992-01-01

    Lightweight, compact, low-power apparatus processes synthetic-aperture-radar (SAR) returns in real time, providing imagery aboard moving aircraft or spacecraft platform. Processor includes optical and electronic subsystems that, together, resolve range and azimuth coordinates of radar targets by combination of spatial and temporal integrations.

  15. A Demo Processor as an Educational Tool

    NARCIS (Netherlands)

    van Moergestel, L.; van Nieuwland, K.; Vermond, L.; Meyer, John-Jules Charles

    2014-01-01

    Explaining the workings of a processor can be done in several ways. Just a written explanation, some pictures, a simulator program or a real hardware demo. The research presented here is based on the idea that a slowly working hardware demo could be a nice tool to explain to IT students the inner wo

  16. A high-speed analog neural processor

    NARCIS (Netherlands)

    Masa, Peter; Hoen, Klaas; Wallinga, Hans

    1994-01-01

    Targeted at high-energy physics research applications, our special-purpose analog neural processor can classify up to 70 dimensional vectors within 50 nanoseconds. The decision-making process of the implemented feedforward neural network enables this type of computation to tolerate weight discretiza

  17. A Double Precision High Speed Convolution Processor

    Science.gov (United States)

    Larochelle, F.; Coté, J. F.; Malowany, A. S.

    1989-11-01

    There exist several convolution processors on the market that can process images at video rate. However, none of these processors operates in floating point arithmetic. Unfortunately, many image processing algorithms presently under development are inoperable in integer arithmetic, forcing the researchers to use regular computers. To solve this problem, we designed a specialized convolution processor that operates in double precision floating point arithmetic with a throughput several thousand times faster than the one obtained on regular computer. Its high performance is attributed to a VLSI double precision convolution systolic cell designed in our laboratories. A 9X9 systolic array carries out, in a pipeline manner, every arithmetic operation. The processor is designed to interface directly with the VME Bus. A DMA chip is responsible for bringing the original pixel intensities from the memory of the computer to the systolic array and to return the convolved pixels back to memory. A special use of 8K RAMs allows an inexpensive and efficient way of delaying the pixel intensities in order to supply the right sequence to the systolic array. On board circuitry converts pixel values into floating point representation when the image is originally represented with integer values. An additional systolic cell, used as a pipeline adder at the output of the systolic array, offers the possibility of combining images together which allows a variable convolution window size and color image processing.

  18. Simplifying cochlear implant speech processor fitting

    NARCIS (Netherlands)

    Willeboer, C.

    2008-01-01

    Conventional fittings of the speech processor of a cochlear implant (CI) rely to a large extent on the implant recipient's subjective responses. For each of the 22 intracochlear electrodes the recipient has to indicate the threshold level (T-level) and comfortable loudness level (C-level) while stim

  19. Globe hosts launch of new processor

    CERN Document Server

    2006-01-01

    Launch of the quadecore processor chip at the Globe. On 14 November, in a series of major media events around the world, the chip-maker Intel launched its new 'quadcore' processor. For the regions of Europe, the Middle East and Africa, the day-long launch event took place in CERN's Globe of Science and Innovation, with over 30 journalists in attendance, coming from as far away as Johannesburg and Dubai. CERN was a significant choice for the event: the first tests of this new generation of processor in Europe had been made at CERN over the preceding months, as part of CERN openlab, a research partnership with leading IT companies such as Intel, HP and Oracle. The event also provided the opportunity for the journalists to visit ATLAS and the CERN Computer Centre. The strategy of putting multiple processor cores on the same chip, which has been pursued by Intel and other chip-makers in the last few years, represents an important departure from the more traditional improvements in the sheer speed of such chips. ...

  20. Analysis of Reconfigurable Processors Using Petri Net

    Directory of Open Access Journals (Sweden)

    Hadis Heidari

    2013-07-01

    Full Text Available In this paper, we propose Petri net models for processing elements. The processing elements include: a general-purpose processor (GPP, a reconfigurable element (RE, and a hybrid element (combining a GPP with an RE. The models consist of many transitions and places. The model and associated analysis methods provide a promising tool for modeling and performance evaluation of reconfigurable processors. The model is demonstrated by considering a simple example. This paper describes the development of a reconfigurable processor; the developed system is based on the Petri net concept. Petri nets are becoming suitable as a formal model for hardware system design. Designers can use Petri net as a modeling language to perform high level analysis of complex processors designs processing chips. The simulation does with PIPEv4.1 simulator. The simulation results show that Petri net state spaces are bounded and safe and have not deadlock and the average of number tokens in first token is 0.9901 seconds. In these models, there are only 5% errors; also the analysis time in these models is 0.016 seconds.

  1. Microarchitecture of the Godson-2 Processor

    Institute of Scientific and Technical Information of China (English)

    Wei-Wu Hu; Fu-Xin Zhang; Zu-Song Li

    2005-01-01

    The Godson project is the first attempt to design high performance general-purpose microprocessors in China.This paper introduces the microarchitecture of the Godson-2 processor which is a 64-bit, 4-issue, out-of-order execution RISC processor that implements the 64-bit MIPS-like instruction set. The adoption of the aggressive out-of-order execution techniques (such as register mapping, branch prediction, and dynamic scheduling) and cache techniques (such as non-blocking cache, load speculation, dynamic memory disambiguation) helps the Godson-2 processor to achieve high performance even at not so high frequency. The Godson-2 processor has been physically implemented on a 6-metal 0.18μm CMOS technology based on the automatic placing and routing flow with the help of some crafted library cells and macros. The area of the chip is 6,700 micrometers by 6,200 micrometers and the clock cycle at typical corner is 2.3ns.

  2. The LVL2 trigger goes online

    CERN Multimedia

    David Berge

    On Friday, the 9th of February, the ATLAS TDAQ community reached an important milestone. In a successful integration test, cosmic-ray muons were recorded with parts of the muon spectrometer, the central-trigger system and a second-level trigger algorithm. This was actually the first time that a full trigger slice all the way from the first-level trigger muon chambers up to event building after event selection by the second-level trigger ran online with cosmic rays. The ATLAS trigger and data acquisition system has a three-tier structure that is designed to cope with the enormous demands of proton-proton collisions at a bunch-crossing frequency of 40 MHz, with a typical event size of 1-2 MB. The online event selection has to reduce the incoming rate by a factor of roughly 200,000 to 200 Hz, a rate digestible by the archival-storage and offline-processing facilities. ATLAS has a mixed system: the first-level trigger (LVL1) is in hardware, while the other two consecutive levels, the second-level trigger (LVL2)...

  3. Stay away from asthma triggers

    Science.gov (United States)

    Asthma triggers - stay away from; Asthma triggers - avoiding; Reactive airway disease - triggers; Bronchial asthma - triggers ... to them. Have someone who does not have asthma cut the grass, or wear a facemask if ...

  4. Array processors based on Gaussian fraction-free method

    Energy Technology Data Exchange (ETDEWEB)

    Peng, S.; Sedukhin, S. [Aizu Univ., Aizuwakamatsu, Fukushima (Japan); Sedukhin, I.

    1998-03-01

    The design of algorithmic array processors for solving linear systems of equations using fraction-free Gaussian elimination method is presented. The design is based on a formal approach which constructs a family of planar array processors systematically. These array processors are synthesized and analyzed. It is shown that some array processors are optimal in the framework of linear allocation of computations and in terms of number of processing elements and computing time. (author)

  5. Antibody producing B lineage cells invade the central nervous system predominantly at the time of and triggered by acute Epstein-Barr virus infection: A hypothesis on the origin of intrathecal immunoglobulin synthesis in multiple sclerosis.

    Science.gov (United States)

    Otto, Carolin; Hofmann, Jörg; Ruprecht, Klemens

    2016-06-01

    Patients with multiple sclerosis (MS), a chronic inflammatory disease of the central nervous system (CNS), typically have an intrathecal synthesis of immunoglobulin (Ig)G. Intrathecal IgG is produced by B lineage cells that entered the CNS, but why and when these cells invade the CNS of patients with MS is unknown. The intrathecal IgG response in patients with MS is polyspecific and part of it is directed against different common viruses (e.g. measles virus, rubella virus, varicella zoster virus). Strong and consistent evidence suggests an association of MS and Epstein-Barr virus (EBV) infection and EBV seroprevalence in patients with MS is practically 100%. However, intriguingly, despite of the universal EBV seroprevalence, the frequency of intrathecally produced IgG to EBV in patients with MS is much lower than that of intrathecally produced IgG to other common viruses. The acute phase of primary EBV infection is characterized by a strong polyclonal B cell activation. As typical for humoral immune responses against viruses, EBV specific IgG is produced only with a temporal delay after acute EBV infection. Aiming to put the above facts into a logical structure, we here propose the hypothesis that in individuals going on to develop MS antibody producing B lineage cells invade the CNS predominantly at the time of and triggered by acute primary EBV infection. Because at the time of acute EBV infection EBV IgG producing B lineage cells have not yet occurred, the hypothesis could explain the universal EBV seroprevalence and the low frequency of intrathecally produced IgG to EBV in patients with MS. Evidence supporting the hypothesis could be provided by large prospective follow-up studies of individuals with symptomatic primary EBV infection (infectious mononucleosis). Furthermore, the clarification of the molecular mechanism underlying an EBV induced invasion of B lineage cells into the CNS of individuals going on to develop MS could corroborate it, too. If true, our

  6. A lock circuit for a multi-core processor

    DEFF Research Database (Denmark)

    2015-01-01

    An integrated circuit comprising a multiple processor cores and a lock circuit that comprises a queue register with respective bits set or reset via respective, connections dedicated to respective processor cores, whereby the queue register identifies those among the multiple processor cores that...

  7. Anatomy of the focal-plane sensor-processor arrays

    OpenAIRE

    Zarándy, Ákos

    2011-01-01

    This introductory chapter describes the zoo of the basic focal-plane sensor-processor array architectures. The typical sensor-processor arrangements are shown, the operators are listed in separate groups, and the processor structures are analyzed. The chapter gives a compass to the reader to navigate among the dif-ferent chip implementations, designs, and applications when reading the book.

  8. 21 CFR 864.3875 - Automated tissue processor.

    Science.gov (United States)

    2010-04-01

    ... 21 Food and Drugs 8 2010-04-01 2010-04-01 false Automated tissue processor. 864.3875 Section 864.3875 Food and Drugs FOOD AND DRUG ADMINISTRATION, DEPARTMENT OF HEALTH AND HUMAN SERVICES (CONTINUED... Automated tissue processor. (a) Identification. An automated tissue processor is an automated system used...

  9. 21 CFR 892.1900 - Automatic radiographic film processor.

    Science.gov (United States)

    2010-04-01

    ... 21 Food and Drugs 8 2010-04-01 2010-04-01 false Automatic radiographic film processor. 892.1900... (CONTINUED) MEDICAL DEVICES RADIOLOGY DEVICES Diagnostic Devices § 892.1900 Automatic radiographic film processor. (a) Identification. An automatic radiographic film processor is a device intended to be used...

  10. Tidal triggering of earthquakes

    OpenAIRE

    Heaton, Thomas H.

    1982-01-01

    Analysis of the tidal stress tensor at the time of moderate to large earthquakes strongly suggests that shallow (< 30 km) larger magnitude oblique-slip and dip-slip earthquakes are triggered by tidal stresses. No corresponding triggering effect is seen for shallow strike-slip earthquakes or for any type of intermediate or deep focus earthquakes which have been studied. Tidal triggering is also discussed from the viewpoint of the ‘dilatancy-diffusion’ model. Specifically, the model as usually ...

  11. Intraplate triggered earthquakes: Observations and interpretation

    Science.gov (United States)

    Hough, S.E.; Seeber, L.; Armbruster, J.G.

    2003-01-01

    We present evidence that at least two of the three 1811-1812 New Madrid, central United States, mainshocks and the 1886 Charleston, South Carolina, earthquake triggered earthquakes at regional distances. In addition to previously published evidence for triggered earthquakes in the northern Kentucky/southern Ohio region in 1812, we present evidence suggesting that triggered events might have occurred in the Wabash Valley, to the south of the New Madrid Seismic Zone, and near Charleston, South Carolina. We also discuss evidence that earthquakes might have been triggered in northern Kentucky within seconds of the passage of surface waves from the 23 January 1812 New Madrid mainshock. After the 1886 Charleston earthquake, accounts suggest that triggered events occurred near Moodus, Connecticut, and in southern Indiana. Notwithstanding the uncertainty associated with analysis of historical accounts, there is evidence that at least three out of the four known Mw 7 earthquakes in the central and eastern United States seem to have triggered earthquakes at distances beyond the typically assumed aftershock zone of 1-2 mainshock fault lengths. We explore the possibility that remotely triggered earthquakes might be common in low-strain-rate regions. We suggest that in a low-strain-rate environment, permanent, nonelastic deformation might play a more important role in stress accumulation than it does in interplate crust. Using a simple model incorporating elastic and anelastic strain release, we show that, for realistic parameter values, faults in intraplate crust remain close to their failure stress for a longer part of the earthquake cycle than do faults in high-strain-rate regions. Our results further suggest that remotely triggered earthquakes occur preferentially in regions of recent and/or future seismic activity, which suggests that faults are at a critical stress state in only some areas. Remotely triggered earthquakes may thus serve as beacons that identify regions of

  12. Cache Energy Optimization Techniques For Modern Processors

    Energy Technology Data Exchange (ETDEWEB)

    Mittal, Sparsh [ORNL

    2013-01-01

    Modern multicore processors are employing large last-level caches, for example Intel's E7-8800 processor uses 24MB L3 cache. Further, with each CMOS technology generation, leakage energy has been dramatically increasing and hence, leakage energy is expected to become a major source of energy dissipation, especially in last-level caches (LLCs). The conventional schemes of cache energy saving either aim at saving dynamic energy or are based on properties specific to first-level caches, and thus these schemes have limited utility for last-level caches. Further, several other techniques require offline profiling or per-application tuning and hence are not suitable for product systems. In this book, we present novel cache leakage energy saving schemes for single-core and multicore systems; desktop, QoS, real-time and server systems. Also, we present cache energy saving techniques for caches designed with both conventional SRAM devices and emerging non-volatile devices such as STT-RAM (spin-torque transfer RAM). We present software-controlled, hardware-assisted techniques which use dynamic cache reconfiguration to configure the cache to the most energy efficient configuration while keeping the performance loss bounded. To profile and test a large number of potential configurations, we utilize low-overhead, micro-architecture components, which can be easily integrated into modern processor chips. We adopt a system-wide approach to save energy to ensure that cache reconfiguration does not increase energy consumption of other components of the processor. We have compared our techniques with state-of-the-art techniques and have found that our techniques outperform them in terms of energy efficiency and other relevant metrics. The techniques presented in this book have important applications in improving energy-efficiency of higher-end embedded, desktop, QoS, real-time, server processors and multitasking systems. This book is intended to be a valuable guide for both

  13. Operation of the enhanced ATLAS First Level Calorimeter Trigger at the start of LHC Run-2

    CERN Document Server

    Palka, Marek; The ATLAS collaboration

    2015-01-01

    In 2015 the LHC is already operating with a higher center-of-mass energy and proton beams luminosity. To keep a high trigger efficiency against an increased event rate, part of ATLAS Level-1 Calorimeter Trigger electronics have been re-designed or newly introduced (Pre-Processors, Merging Modules and Topological Processors). Additionally, to achieve the best possible resolution for the reconstructed physics objects, complex calibration and monitoring systems are employed. Hit rates and energy spectra down to channel level, based on reconstructed events, are supervised with the calorimeter trigger hardware. In this paper the performance of the upgraded Level-1 Calorimeter Trigger at the beginning of LHC Run-2 is illustrated.

  14. The design and performance of the ATLAS Inner Detector trigger for Run 2

    CERN Document Server

    Penc, Ondrej; The ATLAS collaboration

    2016-01-01

    The design and performance of the ATLAS Inner Detector (ID) trigger algorithms running online on the high level trigger (HLT) processor farm with the early LHC Run 2 data are discussed. The redesign of the ID trigger, which took place during the 2013-15 long shutdown, in order to satisfy the demands of the higher energy LHC Run 2 operation is described. The ID trigger HLT algorithms are essential for nearly all trigger signatures within the ATLAS trigger. The detailed performance of the tracking algorithms with the early Run 2 data for the different trigger signatures is presented, including the detailed timing performance for the algorithms running on the redesigned single stage ATLAS HLT Farm. Comparison with the Run 1 strategy are made and demonstrate the superior performance of the strategy adopted for Run 2.

  15. The design and performance of the ATLAS Inner Detector trigger for Run 2

    CERN Document Server

    Penc, Ondrej; The ATLAS collaboration

    2015-01-01

    The design and performance of the ATLAS Inner Detector (ID) trigger algorithms running online on the high level trigger (HLT) processor farm with the early LHC Run 2 data are discussed. The redesign of the ID trigger, which took place during the 2013-15 long shutdown, in order to satisfy the demands of the higher energy LHC Run 2 operation is described. The ID trigger HLT algorithms are essential for nearly all trigger signatures within the ATLAS trigger. The detailed performance of the tracking algorithms with the early Run 2 data for the different trigger signatures is presented, including the detailed timing performance for the algorithms running on the redesigned single stage ATLAS HLT Farm. Comparison with the Run 1 strategy are made and demonstrate the superior performance of the strategy adopted for Run 2.

  16. Trigger Algorithms and Electronics for the ATLAS Muon New Small Wheel Upgrade

    CERN Document Server

    Guan, Liang; The ATLAS collaboration

    2015-01-01

    The New Small Wheel Upgrade for the ATLAS experiment will replace the innermost station of the Muon Spectrometer in the forward region in order to maintain its current performance during high luminosity data-taking after the LHC Phase-I upgrade. The New Small Wheel, comprising Micromegas and small Thin Gap Chambers, will reduce the rate of fake triggers coming from backgrounds in the forward region and significantly improve the Level-1 muon trigger selectivity by providing precise on-line segment measurements with $\\sim$1 mrad angular resolution. Such demanding precision, together with the short time ($\\sim$ 1 $\\mu$s) to prepare trigger data and perform on-line reconstruction, implies very stringent requirements on the design of trigger system and trigger electronics. This paper presents an overview of the design of the New Small Wheel trigger system, trigger algorithms and processor hardware.

  17. Operational Experience of the ATLAS High Level Trigger with Single-Beam and Cosmic Rays

    CERN Document Server

    Aracena, I; The ATLAS collaboration

    2009-01-01

    After giving an overview of the ATLAS trigger design and its innovative features, this paper focuses on the operational experience gained in running the trigger in the fast-changing environment of the detector commissioning. It will emphasize the commissioning of the High Level Trigger (HLT) system, including its monitoring and configuration. Preliminary results from initial LHC running in 2009 will be included if available. ATLAS is one of two general-purpose detectors at the LHC. Using fast reconstruction algorithms, the trigger system needs to efficiently reject a large rate of background events while keeping potentially interesting ones with high efficiency. After a first level trigger implemented in custom electronics, the trigger selection is made by software running on two processor farms (the High Level Trigger system), containing a total of around two thousand multi-core machines. To reduce the network data traffic and the processing time to manageable levels, the HLT uses seeded, step-wise event rec...

  18. Operational Experience of the ATLAS High Level Trigger with Single-Beam and Cosmic Rays

    CERN Document Server

    Aracena, I; The ATLAS collaboration

    2009-01-01

    ATLAS is one of two general-purpose detectors at the LHC. Using fast reconstruction algorithms, the trigger system needs to efficiently reject a large rate of background events while keeping potentially interesting ones with high efficiency. After a first level trigger implemented in custom electronics, the trigger selection is made by software running on two processor farms (the High Level Trigger system), containing a total of around two thousand multi-core machines. To reduce the network data traffic and the processing time to manageable levels, the HLT uses seeded, step-wise event reconstruction, aiming at the earliest possible rejection of background events. The LHC start up and single-beam run periods in 2008 provided a "stress test" of the trigger system. Following this period, ATLAS continued to collect cosmic-ray events for detector alignment and calibration as well as for commissioning the trigger. These running periods allowed us to exercise the trigger system online, including its configuration an...

  19. Iterative electro-optic matrix processor

    Science.gov (United States)

    Carlotto, M. J.

    An electro-optic vector matrix processor with electronic feedback is described. The iterative optical processor (IOP) is designed for the rapid solution of linear algebraic equations. The IOP and the iterative algorithm it realizes are analyzed and simulated. A version of the system was fabricated using advanced solid state light sources and detectors plus fiber optic technology, and its performance is evaluated. An extension of the system using wavelength multiplexing is developed and the basic system concepts demonstrated. Its use in the restoration of degraded images or signals (deconvolution) and the computation of matrix eigenvectors and eigenvalues and matrix inversion are demonstrated. The two major case studies pursued are: adaptive phased array radar processing and optimal control. In the former case, the system is used to compute the adaptive antenna weights for a radar system. In the latter case, the IOP solves the linear quadratic regular and algebraic Ricatti equations of modern control theory.

  20. Model of computation for Fourier optical processors

    Science.gov (United States)

    Naughton, Thomas J.

    2000-05-01

    We present a novel and simple theoretical model of computation that captures what we believe are the most important characteristics of an optical Fourier transform processor. We use this abstract model to reason about the computational properties of the physical systems it describes. We define a grammar for our model's instruction language, and use it to write algorithms for well-known filtering and correlation techniques. We also suggest suitable computational complexity measures that could be used to analyze any coherent optical information processing technique, described with the language, for efficiency. Our choice of instruction language allows us to argue that algorithms describable with this model should have optical implementations that do not require a digital electronic computer to act as a master unit. Through simulation of a well known model of computation from computer theory we investigate the general-purpose capabilities of analog optical processors.

  1. Design of Processors with Reconfigurable Microarchitecture

    Directory of Open Access Journals (Sweden)

    Andrey Mokhov

    2014-01-01

    Full Text Available Energy becomes a dominating factor for a wide spectrum of computations: from intensive data processing in “big data” companies resulting in large electricity bills, to infrastructure monitoring with wireless sensors relying on energy harvesting. In this context it is essential for a computation system to be adaptable to the power supply and the service demand, which often vary dramatically during runtime. In this paper we present an approach to building processors with reconfigurable microarchitecture capable of changing the way they fetch and execute instructions depending on energy availability and application requirements. We show how to use Conditional Partial Order Graphs to formally specify the microarchitecture of such a processor, explore the design possibilities for its instruction set, and synthesise the instruction decoder using correct-by-construction techniques. The paper is focused on the design methodology, which is evaluated by implementing a power-proportional version of Intel 8051 microprocessor.

  2. A polarization diversity radar data processor

    Science.gov (United States)

    Metcalf, J. I.; Armstrong, G. M.

    1983-04-01

    A real time data processor has been designed for use with the AFGL 10-cm Doppler weather radar which is to be operated with alternating transmission of horizontally and vertically polarized signals. In this mode of operation the reception of backscattered signals of polarizations identical to those of the transmitted signals allows the computation of the differential reflectivity between the two polarizations in addition to the absolute reflectivity and the Doppler mean velocity and variance. The switching of transmitted polarization introduces difficulties in the estimation of the autocovariance of the received signals, from which the Doppler velocity parameters are derived. The processor design and the allowed modes of radar operation circumvent these difficulties. This report describes the processing algorithms theoretically and presents details of the implementation of these algorithms in hardware.

  3. Metasurface Spatial Processor for Electromagnetic Remote Control

    OpenAIRE

    Achouri, Karim; Lavigne, Guillaume; Salem, Mohamed Ahmed; Caloz, Christophe

    2015-01-01

    We introduce the concept of metasurface spatial processor, whose transmission is remotely and coherently controlled by the superposition of an incident wave and a control wave through the metasurface. The conceptual operation of this device is analogous to both that of a transistor and a Mach-Zehnder interferometer, while offering much more diversity in terms of electromagnetic transformations. We demonstrate two metasurfaces, that perform the operation of electromagnetic switching and amplif...

  4. High-pressure coal fuel processor development

    Energy Technology Data Exchange (ETDEWEB)

    Greenhalgh, M.L.

    1992-11-01

    The objective of Subtask 1.1 Engine Feasibility was to conduct research needed to establish the technical feasibility of ignition and stable combustion of directly injected, 3,000 psi, low-Btu gas with glow plug ignition assist at diesel engine compression ratios. This objective was accomplished by designing, fabricating, testing and analyzing the combustion performance of synthesized low-Btu coal gas in a single-cylinder test engine combustion rig located at the Caterpillar Technical Center engine lab in Mossville, Illinois. The objective of Subtask 1.2 Fuel Processor Feasibility was to conduct research needed to establish the technical feasibility of air-blown, fixed-bed, high-pressure coal fuel processing at up to 3,000 psi operating pressure, incorporating in-bed sulfur and particulate capture. This objective was accomplished by designing, fabricating, testing and analyzing the performance of bench-scale processors located at Coal Technology Corporation (subcontractor) facilities in Bristol, Virginia. These two subtasks were carried out at widely separated locations and will be discussed in separate sections of this report. They were, however, independent in that the composition of the synthetic coal gas used to fuel the combustion rig was adjusted to reflect the range of exit gas compositions being produced on the fuel processor rig. Two major conclusions resulted from this task. First, direct injected, ignition assisted Diesel cycle engine combustion systems can be suitably modified to efficiently utilize these low-Btu gas fuels. Second, high pressure gasification of selected run-of-the-mine coals in batch-loaded fuel processors is feasible. These two findings, taken together, significantly reduce the perceived technical risks associated with the further development of the proposed coal gas fueled Diesel cycle power plant concept.

  5. Keystone Business Models for Network Security Processors

    Directory of Open Access Journals (Sweden)

    Arthur Low

    2013-07-01

    Full Text Available Network security processors are critical components of high-performance systems built for cybersecurity. Development of a network security processor requires multi-domain experience in semiconductors and complex software security applications, and multiple iterations of both software and hardware implementations. Limited by the business models in use today, such an arduous task can be undertaken only by large incumbent companies and government organizations. Neither the “fabless semiconductor” models nor the silicon intellectual-property licensing (“IP-licensing” models allow small technology companies to successfully compete. This article describes an alternative approach that produces an ongoing stream of novel network security processors for niche markets through continuous innovation by both large and small companies. This approach, referred to here as the "business ecosystem model for network security processors", includes a flexible and reconfigurable technology platform, a “keystone” business model for the company that maintains the platform architecture, and an extended ecosystem of companies that both contribute and share in the value created by innovation. New opportunities for business model innovation by participating companies are made possible by the ecosystem model. This ecosystem model builds on: i the lessons learned from the experience of the first author as a senior integrated circuit architect for providers of public-key cryptography solutions and as the owner of a semiconductor startup, and ii the latest scholarly research on technology entrepreneurship, business models, platforms, and business ecosystems. This article will be of interest to all technology entrepreneurs, but it will be of particular interest to owners of small companies that provide security solutions and to specialized security professionals seeking to launch their own companies.

  6. Communication Efficient Multi-processor FFT

    Science.gov (United States)

    Lennart Johnsson, S.; Jacquemin, Michel; Krawitz, Robert L.

    1992-10-01

    Computing the fast Fourier transform on a distributed memory architecture by a direct pipelined radix-2, a bi-section, or a multisection algorithm, all yield the same communications requirement, if communication for all FFT stages can be performed concurrently, the input data is in normal order, and the data allocation is consecutive. With a cyclic data allocation, or bit-reversed input data and a consecutive allocation, multi-sectioning offers a reduced communications requirement by approximately a factor of two. For a consecutive data allocation, normal input order, a decimation-in-time FFT requires that P/ N + d-2 twiddle factors be stored for P elements distributed evenly over N processors, and the axis that is subject to transformation be distributed over 2 d processors. No communication of twiddle factors is required. The same storage requirements hold for a decimation-in-frequency FFT, bit-reversed input order, and consecutive data allocation. The opposite combination of FFT type and data ordering requires a factor of log 2N more storage for N processors. The peak performance for a Connection Machine system CM-200 implementation is 12.9 Gflops/s in 32-bit precision, and 10.7 Gflops/s in 64-bit precision for unordered transforms local to each processor. The corresponding execution rates for ordered transforms are 11.1 Gflops/s and 8.5 Gflops/s, respectively. For distributed one- and two-dimensional transforms the peak performance for unordered transforms exceeds 5 Gflops/s in 32-bit precision and 3 Gflops/s in 64-bit precision. Three-dimensional transforms execute at a slightly lower rate. Distributed ordered transforms execute at a rate of about {1}/{2}to {2}/{3} of the unordered transforms.

  7. Debugging in a multi-processor environment

    International Nuclear Information System (INIS)

    The Supervisory Control and Diagnostic System (SCDS) for the Mirror Fusion Test Facility (MFTF) consists of nine 32-bit minicomputers arranged in a tightly coupled distributed computer system utilizing a share memory as the data exchange medium. Debugging of more than one program in the multi-processor environment is a difficult process. This paper describes what new tools were developed and how the testing of software is performed in the SCDS for the MFTF project

  8. Multi-core processors - An overview

    OpenAIRE

    Venu, Balaji

    2011-01-01

    Microprocessors have revolutionized the world we live in and continuous efforts are being made to manufacture not only faster chips but also smarter ones. A number of techniques such as data level parallelism, instruction level parallelism and hyper threading (Intel's HT) already exists which have dramatically improved the performance of microprocessor cores. This paper briefs on evolution of multi-core processors followed by introducing the technology and its advantages in today's world. The...

  9. Prototype COBRA near-real-time processor

    Science.gov (United States)

    Earp, Samuel L.; Marshall, J. W.; Anthony, E. R.

    1996-05-01

    The U.S. Marine Corps COBRA countermine surveillance program has developed, as a risk- reduction alternative, a near real-time processor for the output of the COBRA multispectral camera. This processor has been tested using approximately 13.5 hours of video data from the COBRA DT-0 developmental test, representing approximately 243,000 frames of multispectral data. The results have been very encouraging--the system is robust and the minefield detection performance has met the goals of the COBRA program. The MITRE COBRA prototype processor is built from commercial-off-the-shelf VME bus technology. Video capture is provided by a Transtech TDM 435 capture/display VME card. Control is performed on a GMSV64 Super Sparc card that resides in two VME slots. The compute engine consists of two Pentek 4270 Quad TMS320C40 digital signal processing boards. There are two additional 6U VME boards to provide fast SCSI IO. The system is capable of capturing, digitizing and processing the COBRA data stream at between one-eighth and one-half real-time, depending on processing options. The nominal compute power of the system is 2.2 GOPS, 450 MFLOPS. The system is easily upgradeable due to the open architecture--one proposed upgrade will be to increase the number of available TMS320C40 processors to sixteen, providing real-time performance without compromising the current investment in software and hardware. The software for the system is primarily written in C, with hand-optimized assembler code for portions of the compute kernel. The algorithm that is implemented is based on the MITRE minefield detection algorithm detailed at AeroSense '95. The system development required a registration algorithm--this was the only algorithm development that was performed, the rest of the algorithms coming from previous MITRE effort on the COBRA program. Lessons learned from the development and upgrade/test plans will be presented.

  10. Breadboard Signal Processor for Arraying DSN Antennas

    Science.gov (United States)

    Jongeling, Andre; Sigman, Elliott; Chandra, Kumar; Trinh, Joseph; Soriano, Melissa; Navarro, Robert; Rogstad, Stephen; Goodhart, Charles; Proctor, Robert; Jourdan, Michael; Rayhrer, Benno

    2008-01-01

    A recently developed breadboard version of an advanced signal processor for arraying many antennas in NASA s Deep Space Network (DSN) can accept inputs in a 500-MHz-wide frequency band from six antennas. The next breadboard version is expected to accept inputs from 16 antennas, and a following developed version is expected to be designed according to an architecture that will be scalable to accept inputs from as many as 400 antennas. These and similar signal processors could also be used for combining multiple wide-band signals in non-DSN applications, including very-long-baseline interferometry and telecommunications. This signal processor performs functions of a wide-band FX correlator and a beam-forming signal combiner. [The term "FX" signifies that the digital samples of two given signals are fast Fourier transformed (F), then the fast Fourier transforms of the two signals are multiplied (X) prior to accumulation.] In this processor, the signals from the various antennas are broken up into channels in the frequency domain (see figure). In each frequency channel, the data from each antenna are correlated against the data from each other antenna; this is done for all antenna baselines (that is, for all antenna pairs). The results of the correlations are used to obtain calibration data to align the antenna signals in both phase and delay. Data from the various antenna frequency channels are also combined and calibration corrections are applied. The frequency-domain data thus combined are then synthesized back to the time domain for passing on to a telemetry receiver

  11. EROS to universal tape conversion processor

    Science.gov (United States)

    Obrien, S. O. (Principal Investigator)

    1980-01-01

    The function of the EROS processor is to allow a user to select a specific area from a full frame LANDSAT image which is written on tape in the EROS format. The area of interest is read from the EROS formatted tape and converted to the JSC Universal format and written onto another tape. This tape can then be read by the IMDACS processing system and normal analysis can be performed.

  12. Metasurface Spatial Processor for Electromagnetic Remote Control

    Science.gov (United States)

    Achouri, Karim; Lavigne, Guillaume; Salem, Mohamed A.; Caloz, Christophe

    2016-05-01

    We introduce the concept of metasurface spatial processor, whose transmission is remotely and coherently controlled by the superposition of an incident wave and a control wave through the metasurface. The conceptual operation of this device is analogous to both that of a transistor and a Mach-Zehnder interferometer, while offering much more diversity in terms of electromagnetic transformations. We demonstrate two metasurfaces, that perform the operation of electromagnetic switching and amplification.

  13. CoNNeCT Baseband Processor Module

    Science.gov (United States)

    Yamamoto, Clifford K; Jedrey, Thomas C.; Gutrich, Daniel G.; Goodpasture, Richard L.

    2011-01-01

    A document describes the CoNNeCT Baseband Processor Module (BPM) based on an updated processor, memory technology, and field-programmable gate arrays (FPGAs). The BPM was developed from a requirement to provide sufficient computing power and memory storage to conduct experiments for a Software Defined Radio (SDR) to be implemented. The flight SDR uses the AT697 SPARC processor with on-chip data and instruction cache. The non-volatile memory has been increased from a 20-Mbit EEPROM (electrically erasable programmable read only memory) to a 4-Gbit Flash, managed by the RTAX2000 Housekeeper, allowing more programs and FPGA bit-files to be stored. The volatile memory has been increased from a 20-Mbit SRAM (static random access memory) to a 1.25-Gbit SDRAM (synchronous dynamic random access memory), providing additional memory space for more complex operating systems and programs to be executed on the SPARC. All memory is EDAC (error detection and correction) protected, while the SPARC processor implements fault protection via TMR (triple modular redundancy) architecture. Further capability over prior BPM designs includes the addition of a second FPGA to implement features beyond the resources of a single FPGA. Both FPGAs are implemented with Xilinx Virtex-II and are interconnected by a 96-bit bus to facilitate data exchange. Dedicated 1.25- Gbit SDRAMs are wired to each Xilinx FPGA to accommodate high rate data buffering for SDR applications as well as independent SpaceWire interfaces. The RTAX2000 manages scrub and configuration of each Xilinx.

  14. A post-processor for Gurmukhi OCR

    Indian Academy of Sciences (India)

    G S Lehal; Chandan Singh

    2002-02-01

    A post-processing system for OCR of Gurmukhi script has been developed. Statistical information of Punjabi language syllable combinations, corpora look-up and certain heuristics based on Punjabi grammar rules have been combined to design the post-processor. An improvement of 3% in recognition rate, from 94.35% to 97.34%, has been reported on clean images using the post-processing techniques.

  15. Digital signal processor and energy control

    OpenAIRE

    Nishikori, Yutaka; Nakamura, Yoshimichi; Matsuo, Hirofumi

    2009-01-01

    Power supply was consisted of several analog parts and various circuits had been conventionally researched before. While, digitalization research of power supply is proceeding, but it has some problem of performance and cost to create digital control power supply. Now the revolution is occurred at Energy Control area after appearing DSP (Digital Signal Processor). Until now, a power supply was one of component of system. However, the digital control power supply using DSP can realize more int...

  16. Metasurface Spatial Processor for Electromagnetic Remote Control

    CERN Document Server

    Achouri, Karim; Salem, Mohamed Ahmed; Caloz, Christophe

    2015-01-01

    We introduce the concept of metasurface spatial processor, whose transmission is remotely and coherently controlled by the superposition of an incident wave and a control wave through the metasurface. The conceptual operation of this device is analogous to both that of a transistor and a Mach-Zehnder interferometer, while offering much more diversity in terms of electromagnetic transformations. We demonstrate two metasurfaces, that perform the operation of electromagnetic switching and amplification.

  17. Multiple core computer processor with globally-accessible local memories

    Energy Technology Data Exchange (ETDEWEB)

    Shalf, John; Donofrio, David; Oliker, Leonid

    2016-09-20

    A multi-core computer processor including a plurality of processor cores interconnected in a Network-on-Chip (NoC) architecture, a plurality of caches, each of the plurality of caches being associated with one and only one of the plurality of processor cores, and a plurality of memories, each of the plurality of memories being associated with a different set of at least one of the plurality of processor cores and each of the plurality of memories being configured to be visible in a global memory address space such that the plurality of memories are visible to two or more of the plurality of processor cores.

  18. VLSI Design of a 16-bit Pipelined RISC Processor

    Directory of Open Access Journals (Sweden)

    Tannu Chhabra

    2012-06-01

    Full Text Available In this paper we have described the design of a 16-bit pipelined RISC processor for applications in real-time embedded systems. The processor executes most of the instructions in single machine cycle making it ideal for use in high speed systems. The processor has been designed to be implemented on an FPGA using VHDL such that one can reconfigure it according to specific requirements of the target applications. The processor is powerful enough to be used as a stand-alone processing element and is generic enough to be used in multi-processor System on Chip.

  19. Multi-Core Processor Memory Contention Benchmark Analysis Case Study

    Science.gov (United States)

    Simon, Tyler; McGalliard, James

    2009-01-01

    Multi-core processors dominate current mainframe, server, and high performance computing (HPC) systems. This paper provides synthetic kernel and natural benchmark results from an HPC system at the NASA Goddard Space Flight Center that illustrate the performance impacts of multi-core (dual- and quad-core) vs. single core processor systems. Analysis of processor design, application source code, and synthetic and natural test results all indicate that multi-core processors can suffer from significant memory subsystem contention compared to similar single-core processors.

  20. PERFORMANCE EVALUATION OF DIRECT PROCESSOR ACCESS FOR NON DEDICATED SERVER

    OpenAIRE

    P. S. Balamurugan; Dr.K.Thanushkodi

    2010-01-01

    The objective of the paper is to design a co processor for a desktop machine which enables the machine to act as non dedicated server, such that the co processor will act as a server processor and the multi-core processor to act as desktop processor. By implementing this methodology a client machine can be made to act as a non dedicated server and a client machine. These type of machine can be used in autonomy networks. This design will lead to design of a cost effective server and machine wh...

  1. The Advanced On-board Processor (AOP)

    Science.gov (United States)

    Hartenstein, R. G.; Trevathan, C. E.; Stewart, W. N.

    1971-01-01

    The goal of the Advanced On-Board Processor (AOP) development program is to design, build, and flight qualify a highly reliable, moderately priced, digital computer for application on a variety of spacecraft. Included in this development program is the preparation of a complete support software package which consists of an assembler, simulator, loader, system diagnostic, operational executive, and many useful subroutines. The AOP hardware/software system is an extension of the On-Board Processor (OBP) which was developed for general purpose use on earth orbiting spacecraft with its initial application being on-board the fourth Orbiting Astronomical Observatory (OAO-C). Although the OBP possesses the significant features that are required for space application, however, when operating at 100% duty cycle the OBP is too power-consuming for use on many smaller spacecraft. Computer volume will be minimized by implementing the processor and input/output portions of the machine with large scale integrated circuits. Power consumption will be reduced through the use of plated wire and, in some cases, semiconductor memory elements.

  2. Techniques for optimizing inerting in electron processors

    International Nuclear Information System (INIS)

    The design of an ''inert gas'' distribution system in an electron processor must satisfy a number of requirements. The first of these is the elimination or control of beam produced ozone and NOx which can be transported from the process zone by the product into the work area. Since the tolerable levels for O3 in occupied areas around the processor are 3 in the beam heated process zone, or exhausting and dilution of the gas at the processor exit. The second requirement of the inerting system is to provide a suitable environment for completing efficient, free radical initiated addition polymerization. The competition between radical loss through de-excitation and that from O2 quenching must be understood. This group has used gas chromatographic analysis of electron cured coatings to study the trade-offs of delivered dose, dose rate and O2 concentrations in the process zone to determine the tolerable ranges of parameter excursions for production quality control purposes. These techniques are described for an ink coating system on paperboard, where a broad range of process parameters have been studied (D, D radical, O2). It is then shown how the technique is used to optimize the use of higher purity (10-100 ppm O2) nitrogen gas for inerting, in combination with lower purity (2-20,000 ppm O2) non-cryogenically produced gas, as from a membrane or pressure swing adsorption generators. (author)

  3. AMY trigger system

    Energy Technology Data Exchange (ETDEWEB)

    Sakai, Yoshihide [National Laboratory for High Energy Physics, Tsukuba, Ibaraki (Japan)

    1989-04-01

    A trigger system of the AMY detector at TRISTAN e{sup +}e{sup -} collider is described briefly. The system uses simple track segment and shower cluster counting scheme to classify events to be triggered. It has been operating successfully since 1987.

  4. Considerations for control system software verification and validation specific to implementations using distributed processor architectures

    International Nuclear Information System (INIS)

    Until recently, digital control systems have been implemented on centralized processing systems to function in one of several ways: (1) as a single processor control system; (2) as a supervisor at the top of a hierarchical network of multiple processors; or (3) in a client-server mode. Each of these architectures uses a very different set of communication protocols. The latter two architectures also belong to the category of distributed control systems. Distributed control systems can have a central focus, as in the cases just cited, or be quite decentralized in a loosely coupled, shared responsibility arrangement. This last architecture is analogous to autonomous hosts on a local area network. Each of the architectures identified above will have a different set of architecture-associated issues to be addressed in the verification and validation activities during software development. This paper summarizes results of efforts to identify, describe, contrast, and compare these issues

  5. Network to transmit prioritized subtask pockets to dedicated processors

    Energy Technology Data Exchange (ETDEWEB)

    Neches, P.M.

    1989-03-21

    A multiprocessor system distributing a workload among individual processors and operating with low usage of executive software and inter-processor communication to provide an overall workload processing function divisible into parallel processing subtasks is described, comprising: at least one processor system providing tasks for processing in the form of task messages; means coupled to receive the task messages from the processor system and including means to transform the task messages into subtask request packets including information as to one or more appropriate recipients; processor modules, each having assigned responsibilities with respect to the workload and each including means to determine whether the subtask is appropriate therefor, means for executing an appropriate subtask and means for providing a responsive task result packet after executing the subtask, the task result packet competing for priority with task result packets from at least one other processor module and with the subtask request packets from the interface processor means; and means coupling the interface processor means to the processor modules and the processor modules to each other and including means for concurrently receiving the packets and for determining priority between contending packets and distributing each packet having priority concurrently to all processor modules.

  6. Testing and operating a multiprocessor chip with processor redundancy

    Energy Technology Data Exchange (ETDEWEB)

    Bellofatto, Ralph E; Douskey, Steven M; Haring, Rudolf A; McManus, Moyra K; Ohmacht, Martin; Schmunkamp, Dietmar; Sugavanam, Krishnan; Weatherford, Bryan J

    2014-10-21

    A system and method for improving the yield rate of a multiprocessor semiconductor chip that includes primary processor cores and one or more redundant processor cores. A first tester conducts a first test on one or more processor cores, and encodes results of the first test in an on-chip non-volatile memory. A second tester conducts a second test on the processor cores, and encodes results of the second test in an external non-volatile storage device. An override bit of a multiplexer is set if a processor core fails the second test. In response to the override bit, the multiplexer selects a physical-to-logical mapping of processor IDs according to one of: the encoded results in the memory device or the encoded results in the external storage device. On-chip logic configures the processor cores according to the selected physical-to-logical mapping.

  7. Research on seismic stress triggering

    Institute of Scientific and Technical Information of China (English)

    万永革; 吴忠良; 周公威; 黄静; 秦立新

    2002-01-01

    This paper briefly reviews basic theory of seismic stress triggering. Recent development on seismic stress triggering has been reviewed in the views of seismic static and dynamic stress triggering, application of viscoelastic model in seismic stress triggering, the relation between earthquake triggering and volcanic eruption or explosion, other explanation of earthquake triggering, etc. And some suggestions for further study on seismic stress triggering in near future are given.

  8. An implementation of the LHCb level 0 muon trigger using the 3D-Flow ASIC

    CERN Document Server

    Corti, G; Crosetto, D; Nelson, K

    1998-01-01

    The implementation of the LHCb level 0 muon trigger using the 3D-flow technique is discussed. The connection of the LHCb muon detector front-end electronics to the L0 3D-flow processor is also discussed.1

  9. LHCb Topological Trigger Reoptimization

    Science.gov (United States)

    Likhomanenko, Tatiana; Ilten, Philip; Khairullin, Egor; Rogozhnikov, Alex; Ustyuzhanin, Andrey; Williams, Michael

    2015-12-01

    The main b-physics trigger algorithm used by the LHCb experiment is the so- called topological trigger. The topological trigger selects vertices which are a) detached from the primary proton-proton collision and b) compatible with coming from the decay of a b-hadron. In the LHC Run 1, this trigger, which utilized a custom boosted decision tree algorithm, selected a nearly 100% pure sample of b-hadrons with a typical efficiency of 60-70%; its output was used in about 60% of LHCb papers. This talk presents studies carried out to optimize the topological trigger for LHC Run 2. In particular, we have carried out a detailed comparison of various machine learning classifier algorithms, e.g., AdaBoost, MatrixNet and neural networks. The topological trigger algorithm is designed to select all ’interesting” decays of b-hadrons, but cannot be trained on every such decay. Studies have therefore been performed to determine how to optimize the performance of the classification algorithm on decays not used in the training. Methods studied include cascading, ensembling and blending techniques. Furthermore, novel boosting techniques have been implemented that will help reduce systematic uncertainties in Run 2 measurements. We demonstrate that the reoptimized topological trigger is expected to significantly improve on the Run 1 performance for a wide range of b-hadron decays.

  10. The LHCb Trigger

    CERN Document Server

    van Herwijnen, Eric

    2010-01-01

    The Large Hadron Collider beauty experiment (LHCb) is a dedicated heavy flavour physics experiment at the LHC. The trigger system employs the finite lifetime and relative large mass of charm and beauty hadrons to distinguish heavy flavour and background from inelastic pp-scattering. The LHCb trigger is a two level system. The first level is implemented in hardware, it reduces the visible interaction rate to a maximum of 1MHz, at which the whole detector can be readout. The second trigger level is a C++ application running on an Event Filter Farm composed of several thousand CPU nodes. The full trigger is operational in the experiment. In this talk, an overview of the LHCb trigger system will be given. We put special emphasis on the experience obtained with the initial data taking at the LHC, and the commissioning and monitoring of the software trigger. The method to obtain the efficiency of the trigger from real data will be described, and first results will be presented.

  11. Performance Analysis of the ATLAS Second Level Trigger Software

    CERN Document Server

    Bogaerts, J A C; Li, W; Middleton, R P; Werner, P; Wickens, F J; Zobernig, H

    2002-01-01

    Abstract--In this paper we analyse the performance of the prototype software developed for the ATLAS Second Level Trigger. The OO framework written in C++ has been used to implement a distributed system which collects (simulated) detector data on which it executes event selection algorithms. The software has been used on testbeds of up to 100 nodes with various interconnect technologies. The final system will have to sustain traffic of ~ 40 Gbits/s and require an estimated number of ~750 processors. Timing measurements are crucial for issues such as trigger decision latency, assessment of required CPU and network capacity, scalability, and load-balancing. In addition, final architectural and technological choices, code optimisation and system tuning require a detailed understanding of both CPU utilisation and trigger decision latency. In this paper we describe the instrumentation used to disentangle effects due to such factors as OS system intervention, blocking on interlocks (applications are multi-threaded)...

  12. The Level-1 Calorimeter Global Feature Extractor (gFEX) Boosted Object Trigger for the Phase-I Upgrade of the ATLAS Experiment

    CERN Document Server

    Camacho Toro, Reina; The ATLAS collaboration

    2016-01-01

    The Global Feature Extractor (gFEX) module is a planned component of the Level 1 online trigger system for the ATLAS experiment planned for installation during the Phase I upgrade in 2018. This unique single electronics board with multiple high speed processors will receive coarse-granularity information from all the ATLAS calorimeters enabling the identification in real time of large-radius jets for capturing Lorentz-boosted objects such as top quarks, Higgs, $Z$ and $W$ bosons. The gFEX architecture also facilitates the calculation of global event variables such as missing transverse energy, centrality for heavy ion collisions, and event-by-event pile-up energy density. Details of the electronics architecture that provides these capabilities are presented, along with results of tests of the prototype systems now available. The status of the firmware algorithm design and implementation as well as monitoring capabilities are also presented.

  13. Calo trigger acquisition system

    CERN Multimedia

    Franchini, Matteo

    2016-01-01

    Calo trigger acquisition system - Evolution of the acquisition system from a multiple boards system (upper, orange cables) to a single board one (below, light blue cables) where all the channels are collected in a single board.

  14. Associative Memory design for the Fast TracK processor (FTK) at Atlas

    CERN Document Server

    Annovi, A; The ATLAS collaboration; Bossini, E; Crescioli, F; Dell'Orso, M; Giannetti, P; Piendibene, M; Sacco, I; Sartori, L; Tripiccione, R

    2010-01-01

    We describe a VLSI processor for pattern recognition based on Content Addressable Memory (CAM) architecture, optimized for on-line track finding in high-energy physics experiments. A large CAM bank stores all trajectories of interest and extracts the ones compatible with a given event. This task is naturally parallelized by a CAM architecture able to output identified trajectories, recognized among a huge amount of possible combinations, in just a few 100 MHz clock cycles. We have developed this device (called the AMchip03 processor), using 180 nm technology, for the Silicon Vertex Trigger (SVT) upgrade at CDF using a standard-cell VLSI design methodology. We propose now a new design (90 nm technology) where we introduce a full custom standard cell. This is a customized design that allows to maximize the pattern density and to minimize the power consumption. We discuss also possible future extensions based on 3-D technology. This processor has a flexible and easily configurable structure that makes it suitabl...

  15. Introduction to programming multiple-processor computers

    International Nuclear Information System (INIS)

    FORTRAN applications programs can be executed on multiprocessor computers in either a unitasking (traditional) or multitasking form. The latter allows a single job to use more than one processor simultaneously, with a consequent reduction in wall-clock time and, perhaps, the cost of the calculation. An introduction to programming in this environment is presented. The concepts of synchronization and data sharing using EVENTS and LOCKS are illustrated with examples. The strategy of strong synchronization and the use of synchronization templates are proposed. We emphasize that incorrect multitasking programs can produce irreproducible results, which makes debugging more difficult

  16. Processor Reformats Data For Transmission In Bursts

    Science.gov (United States)

    Steele, Glen F.

    1991-01-01

    Data-processor-and-buffer electronic system receives audio signals digitized in first standard format at relatively low data rate, rearranges data for transmission in bursts in second standard format at relatively high rate, stores second-format bursts, and releases them at higher rate upon request. Conceived for asynchronous, one-way transmission of digitized speech in outer-space communications, concept of system applied in other digital communication systems in which data transmitted from low-rate sources to high-rate sinks not synchronized with sources.

  17. Topological Trigger Developments

    CERN Multimedia

    Likhomanenko, Tatiana

    2015-01-01

    The main b-physics trigger algorithm used by the LHCb experiment is the so-called topological trigger. The topological trigger selects vertices which are a) detached from the primary proton-proton collision and b) compatible with coming from the decay of a b-hadron. In the LHC Run 1, this trigger utilized a custom boosted decision tree algorithm, selected an almost 100% pure sample of b-hadrons with a typical efficiency of 60-70%, and its output was used in about 60% of LHCb papers. This talk presents studies carried out to optimize the topological trigger for LHC Run 2. In particular, we have carried out a detailed comparison of various machine learning classifier algorithms, e.g., AdaBoost, MatrixNet and uBoost. The topological trigger algorithm is designed to select all "interesting" decays of b-hadrons, but cannot be trained on every such decay. Studies have therefore been performed to determine how to optimize the performance of the classification algorithm on decays not used in the training. These inclu...

  18. The VERITAS Trigger System

    CERN Document Server

    Weinstein, A

    2007-01-01

    The VERITAS gamma-ray observatory, situated in southern Arizona, is an array of four 12m diameter imaging Cherenkov telescopes, each with a 499-pixel photomultiplier-tube camera. The instrument is designed to detect astrophysical gamma rays at energies above 100 GeV. At the low end of the VERITAS energy range, fluctuations in the night sky background light and single muons from cosmic-ray showers constitute significant backgrounds. VERITAS employs a three-tier trigger system to reduce the rate of these background events: an initial trigger which acts at the single pixel level, a pattern trigger which acts on the relative timing and pixel level, a pattern trigger which acts on the relative timing and distribution of pixel-level triggers within a single telescope camera, and an array-level trigger which requires simultaneous observation of an air-shower event in multiple telescopes. This final coincidence requirement significantly reduces the rate of background events, particularly those due to single muons. In...

  19. The LHCb Trigger System

    Science.gov (United States)

    Rodrigues, E.; LHCb Collaboration

    2007-08-01

    The LHCb detector has been conceived to study with high precision CP violation and rare decays of b-flavoured hadrons produced at the LHC. The LHCb trigger is of crucial importance in selecting the collisions of interest for b-physics studies. The trigger is based on a two-level system. The first level, Level-0, is implemented in hardware and uses information from the calorimeter, muon and pile-up systems to select events containing particles with relatively large transverse momentum, typically above 1-2 GeV. The Level-0 trigger accepts events at a rate of 1 MHz. All the detector information is then read out and fed into the High Level Trigger. This software trigger runs in the event-filter farm composed of about 1800 CPU nodes. Events are selected at a rate of 2 kHz and sent for mass storage and subsequent offline reconstruction and analysis. The current status and expected performance of the trigger system are described.

  20. LHCb Topological Trigger Reoptimization

    CERN Document Server

    Likhomanenko, Tatiana; Khairullin, Egor; Rogozhnikov, Alex; Ustyuzhanin, Andrey; Williams, Michael

    2015-01-01

    The main b-physics trigger algorithm used by the LHCb experiment is the so-called topological trigger. The topological trigger selects vertices which are a) detached from the primary proton-proton collision and b) compatible with coming from the decay of a b-hadron. In the LHC Run 1, this trigger, which utilized a custom boosted decision tree algorithm, selected a nearly 100% pure sample of b-hadrons with a typical efficiency of 60-70%; its output was used in about 60% of LHCb papers. This talk presents studies carried out to optimize the topological trigger for LHC Run 2. In particular, we have carried out a detailed comparison of various machine learning classifier algorithms, e.g., AdaBoost, MatrixNet and neural networks. The topological trigger algorithm is designed to select all "interesting" decays of b-hadrons, but cannot be trained on every such decay. Studies have therefore been performed to determine how to optimize the performance of the classification algorithm on decays not used in the training. ...

  1. Dynamic Triggering Stress Modeling

    Science.gov (United States)

    Gonzalez-Huizar, H.; Velasco, A. A.

    2008-12-01

    It has been well established that static (permanent) stress changes can trigger nearby earthquakes, within a few fault lengths from the causative event, whereas triggering by dynamic (transient) stresses carried by seismic waves both nearby and at remote distances has not been as well documented nor understood. An analysis of the change in the local stress caused by the passing of surfaces waves is important for the understanding of this phenomenon. In this study, we modeled the change in the stress that the passing of Rayleigh and Loves waves causes on a fault plane of arbitrary orientation, and applied a Coulomb failure criteria to calculate the potential of these stress changes to trigger reverse, normal or strike-slip failure. We preliminarily test these model results with data from dynamically triggering earthquakes in the Australian Bowen Basin. In the Bowen region, the modeling predicts a maximum triggering potential for Rayleigh waves arriving perpendicularly to the strike of the reverse faults present in the region. The modeled potentials agree with our observations, and give us an understanding of the dynamic stress orientation needed to trigger different type of earthquakes.

  2. The ISS Water Processor Catalytic Reactor as a Post Processor for Advanced Water Reclamation Systems

    Science.gov (United States)

    Nalette, Tim; Snowdon, Doug; Pickering, Karen D.; Callahan, Michael

    2007-01-01

    Advanced water processors being developed for NASA s Exploration Initiative rely on phase change technologies and/or biological processes as the primary means of water reclamation. As a result of the phase change, volatile compounds will also be transported into the distillate product stream. The catalytic reactor assembly used in the International Space Station (ISS) water processor assembly, referred to as Volatile Removal Assembly (VRA), has demonstrated high efficiency oxidation of many of these volatile contaminants, such as low molecular weight alcohols and acetic acid, and is considered a viable post treatment system for all advanced water processors. To support this investigation, two ersatz solutions were defined to be used for further evaluation of the VRA. The first solution was developed as part of an internal research and development project at Hamilton Sundstrand (HS) and is based primarily on ISS experience related to the development of the VRA. The second ersatz solution was defined by NASA in support of a study contract to Hamilton Sundstrand to evaluate the VRA as a potential post processor for the Cascade Distillation system being developed by Honeywell. This second ersatz solution contains several low molecular weight alcohols, organic acids, and several inorganic species. A range of residence times, oxygen concentrations and operating temperatures have been studied with both ersatz solutions to provide addition performance capability of the VRA catalyst.

  3. Description and Optimisation of the ALICE dimuon trigger

    CERN Document Server

    Roig, O

    1998-01-01

    The main considerations about the ALICE dimuon trigger can be found in the Addendum to the ALICE Technical Proposal (T.P. in this note), concerning the forward muon spectrometer. The main task of the trigger is to select the dimuon signals, mainly from J/Psi and Upsilon resonances, amongst the huge background of muons from pions, kaons, charm decays and soft background in order to keep the acquisition rates at a satisfactory level. This is achieved with a cut on the muon transverse momentum performed by the trigger electronics and processors. A dimuon mass cut can also be done (not treated in this note). This note presents a detailed simulation which goal is to optimize the dimuon trigger. It includes the description of the set-up geometry and segmentation as well as the trigger electronics functions. Many improvements are suggested by the results of this simulation, as compared to the T.P. An update of the trigger rates and efficiency is given. Even though we describe the main elements of the dimuon trigge...

  4. User microprogrammable processors for high data rate telemetry preprocessing

    Science.gov (United States)

    Pugsley, J. H.; Ogrady, E. P.

    1973-01-01

    The use of microprogrammable processors for the preprocessing of high data rate satellite telemetry is investigated. The following topics are discussed along with supporting studies: (1) evaluation of commercial microprogrammable minicomputers for telemetry preprocessing tasks; (2) microinstruction sets for telemetry preprocessing; and (3) the use of multiple minicomputers to achieve high data processing. The simulation of small microprogrammed processors is discussed along with examples of microprogrammed processors.

  5. Reconfigurable Very Long Instruction Word (VLIW) Processor

    Science.gov (United States)

    Velev, Miroslav N.

    2015-01-01

    Future NASA missions will depend on radiation-hardened, power-efficient processing systems-on-a-chip (SOCs) that consist of a range of processor cores custom tailored for space applications. Aries Design Automation, LLC, has developed a processing SOC that is optimized for software-defined radio (SDR) uses. The innovation implements the Institute of Electrical and Electronics Engineers (IEEE) RazorII voltage management technique, a microarchitectural mechanism that allows processor cores to self-monitor, self-analyze, and selfheal after timing errors, regardless of their cause (e.g., radiation; chip aging; variations in the voltage, frequency, temperature, or manufacturing process). This highly automated SOC can also execute legacy PowerPC 750 binary code instruction set architecture (ISA), which is used in the flight-control computers of many previous NASA space missions. In developing this innovation, Aries Design Automation has made significant contributions to the fields of formal verification of complex pipelined microprocessors and Boolean satisfiability (SAT) and has developed highly efficient electronic design automation tools that hold promise for future developments.

  6. RISC Processors and High Performance Computing

    Science.gov (United States)

    Saini, Subhash; Bailey, David H.; Lasinski, T. A. (Technical Monitor)

    1995-01-01

    In this tutorial, we will discuss top five current RISC microprocessors: The IBM Power2, which is used in the IBM RS6000/590 workstation and in the IBM SP2 parallel supercomputer, the DEC Alpha, which is in the DEC Alpha workstation and in the Cray T3D; the MIPS R8000, which is used in the SGI Power Challenge; the HP PA-RISC 7100, which is used in the HP 700 series workstations and in the Convex Exemplar; and the Cray proprietary processor, which is used in the new Cray J916. The architecture of these microprocessors will first be presented. The effective performance of these processors will then be compared, both by citing standard benchmarks and also in the context of implementing a real applications. In the process, different programming models such as data parallel (CM Fortran and HPF) and message passing (PVM and MPI) will be introduced and compared. The latest NAS Parallel Benchmark (NPB) absolute performance and performance per dollar figures will be presented. The next generation of the NP13 will also be described. The tutorial will conclude with a discussion of general trends in the field of high performance computing, including likely future developments in hardware and software technology, and the relative roles of vector supercomputers tightly coupled parallel computers, and clusters of workstations. This tutorial will provide a unique cross-machine comparison not available elsewhere.

  7. Coordinated Energy Management in Heterogeneous Processors

    Directory of Open Access Journals (Sweden)

    Indrani Paul

    2014-01-01

    Full Text Available This paper examines energy management in a heterogeneous processor consisting of an integrated CPU–GPU for high-performance computing (HPC applications. Energy management for HPC applications is challenged by their uncompromising performance requirements and complicated by the need for coordinating energy management across distinct core types – a new and less understood problem. We examine the intra-node CPU–GPU frequency sensitivity of HPC applications on tightly coupled CPU–GPU architectures as the first step in understanding power and performance optimization for a heterogeneous multi-node HPC system. The insights from this analysis form the basis of a coordinated energy management scheme, called DynaCo, for integrated CPU–GPU architectures. We implement DynaCo on a modern heterogeneous processor and compare its performance to a state-of-the-art power- and performance-management algorithm. DynaCo improves measured average energy-delay squared (ED2 product by up to 30% with less than 2% average performance loss across several exascale and other HPC workloads.

  8. Efficiency of Cache Mechanism for Network Processors

    Institute of Scientific and Technical Information of China (English)

    XU Bo; CHANG Jian; HUANG Shimeng; XUE Yibo; LI Jun

    2009-01-01

    With the explosion of network bandwidth and the ever-changing requirements for diverse net-work-based applications, the traditional processing architectures, i.e., general purpose processor (GPP) and application specific integrated circuits (ASIC) cannot provide sufficient flexibility and high performance at the same time. Thus, the network processor (NP) has emerged as an altemative to meet these dual demands for today's network processing. The NP combines embedded multi-threaded cores with a dch memory hierarchy that can adapt to different networking circumstances when customized by the application developers. In to-day's NP architectures, muitithreading prevails over cache mechanism, which has achieved great success in GPP to hide memory access latencies. This paper focuses on the efficiency of the cache mechanism in an NP. Theoretical timing models of packet processing are established for evaluating cache efficiency and experi-ments are performed based on real-life network backbone traces. Testing results show that an improvement of neady 70% can be gained in throughput with assistance from the cache mechanism. Accordingly, the cache mechanism is still efficient and irreplaceable in network processing, despite the existing of multithreading.

  9. Associative Memory Design for the Fast TracKer Processor (FTK)at ATLAS

    CERN Document Server

    Annovi, A; The ATLAS collaboration; Beretta, M; Bossini, E; Crescioli, F; Dell'Orso, M; Giannetti, P; Hoff, J; Liu, T; Liberali, V; Sacco, I; Schoening, A; Soltveit, H K; Stabile, A; Tripiccione, R

    2011-01-01

    We describe a VLSI processor for pattern recognition based on Content Addressable Memory (CAM) architecture, optimized for on-line track finding in high-energy physics experiments. A large CAM bank stores all trajectories of interest and extracts the ones compatible with a given event. This task is naturally parallelized by a CAM architecture able to output identified trajectories, recognized among a huge amount of possible combinations, in just a few 100 MHz clock cycles. We have developed this device (called the AMchip03 processor), using 180 nm technology, for the Silicon Vertex Trigger (SVT) upgrade at CDF [1] using a standard-cell VLSI design methodology. We propose a new design that introduces a full custom CAM cell and takes advantage of 65 nm technology. The customized design maximizes the pattern density, minimizes the power consumption and implements the functionalities needed for the planned Fast Tracker (FTK) [2], an ATLAS trigger upgrade project at LHC. We introduce a new variable resolution patt...

  10. The data path of the ATLAS level-1 calorimeter trigger preprocessor

    Energy Technology Data Exchange (ETDEWEB)

    Andrei, George Victor

    2010-10-27

    The PreProcessor of the ATLAS Level-1 Calorimeter Trigger provides digital values of transverse energy in real-time to the subsequent object-finding processors. The input comprises more than 7000 analogue signals of reduced granularity from the calorimeters of the ATLAS detector. The Level-1 trigger decision must be verified. For this, the PreProcessor transmits copies of the real-time digital data to the Data Acquisition (DAQ) system. In addition, the PreProcessor system provides a standard VMEbus interface to the computing infrastructure of the experiment, on which configuration data is loaded and control or monitoring data are read out. A dedicated system that ensures both the transfer of event data to storage in ATLAS and the data transfer over the VME was implemented on the 124 modules of the PreProcessor system in the form of a ''Readout Manager''. The ''Field Programmable Gate Array'' (FPGA) is located on each module. The rst part of this work describes the algorithms developed to meet the functionality of the Readout Manager. The second part deals with the tests that were carried out to ensure the proper functionality of the modules before they were installed at CERN in the ATLAS cavern. (orig.)

  11. The data path of the ATLAS level-1 calorimeter trigger preprocessor

    International Nuclear Information System (INIS)

    The PreProcessor of the ATLAS Level-1 Calorimeter Trigger provides digital values of transverse energy in real-time to the subsequent object-finding processors. The input comprises more than 7000 analogue signals of reduced granularity from the calorimeters of the ATLAS detector. The Level-1 trigger decision must be verified. For this, the PreProcessor transmits copies of the real-time digital data to the Data Acquisition (DAQ) system. In addition, the PreProcessor system provides a standard VMEbus interface to the computing infrastructure of the experiment, on which configuration data is loaded and control or monitoring data are read out. A dedicated system that ensures both the transfer of event data to storage in ATLAS and the data transfer over the VME was implemented on the 124 modules of the PreProcessor system in the form of a ''Readout Manager''. The ''Field Programmable Gate Array'' (FPGA) is located on each module. The rst part of this work describes the algorithms developed to meet the functionality of the Readout Manager. The second part deals with the tests that were carried out to ensure the proper functionality of the modules before they were installed at CERN in the ATLAS cavern. (orig.)

  12. Compiler Optimization to Improve Data Locality for Processor Multithreading

    Directory of Open Access Journals (Sweden)

    Balaram Sinharoy

    1999-01-01

    Full Text Available Over the last decade processor speed has increased dramatically, whereas the speed of the memory subsystem improved at a modest rate. Due to the increase in the cache miss latency (in terms of the processor cycle, processors stall on cache misses for a significant portion of its execution time. Multithreaded processors has been proposed in the literature to reduce the processor stall time due to cache misses. Although multithreading improves processor utilization, it may also increase cache miss rates, because in a multithreaded processor multiple threads share the same cache, which effectively reduces the cache size available to each individual thread. Increased processor utilization and the increase in the cache miss rate demands higher memory bandwidth. A novel compiler optimization method has been presented in this paper that improves data locality for each of the threads and enhances data sharing among the threads. The method is based on loop transformation theory and optimizes both spatial and temporal data locality. The created threads exhibit high level of intra‐thread and inter‐thread data locality which effectively reduces both the data cache miss rates and the total execution time of numerically intensive computation running on a multithreaded processor.

  13. Trigger/front end electronics and data collection

    International Nuclear Information System (INIS)

    The data collection system in the B factory at KEK is planned to have the features that the beam cross intervals will be small (15-30 necs), that the first-step trigger frequency will be 1 kHz, that the frequency of data transfer from the mass storage will be around 10 Hz, and that the data capacity will be 256 kilobyte/sec at most. A possible approach to meet these requirements is to use a trigger system of a pipeline mechanism, a multiple front end system, a high-speed data scanning module and a large-scale processor farm. The trigger system is intended to extract high-speed signals from the detector and to start and control the entire data collection system. The start signals and control signals should synchronize with the beam cross. The front end electronics comprises high-sensitivity analog electronics, including front amplifier, and an analog/digital converter. The data collection system has a tree structure. Its lowest layer comprises a multiple buffered memory. Required data are extracted by the high-speed data scanning module, stored in a memory incorporated in the scanning module, and then transferred to the processor farm. (N.K.)

  14. Upgrade of the ATLAS Level-1 Calorimeter Trigger

    CERN Document Server

    Wessels, M; The ATLAS collaboration

    2014-01-01

    The Level-1 Calorimeter Trigger (L1Calo) of the ATLAS experiment has been operating well since the start of LHC data taking, and played a major role in the Higgs boson discovery. To face the new challenges posed by the upcoming increases of the LHC proton beam energy and luminosity, a series of upgrades is planned for L1Calo. The initial upgrade phase in 2013-14 includes substantial improvements to the analogue and digital signal processing to allow more sophisticated digital filters for energy and timing measurement, as well as compensate for pile-up and baseline shifting effects. Two existing digital algorithm processor subsystems will receive substantial hardware and firmware upgrades to increase the real-time data path bandwidth, allowing topological information to be transmitted and processed at Level-1. An entirely new subsystem, the Level-1 Topological Processor, will receive real-time data from both the upgraded L1Calo and Level-1 Muon Trigger to perform trigger algorithms based on entire event topolo...

  15. The CMS trigger system

    CERN Document Server

    Khachatryan, Vardan; CMS Collaboration; Tumasyan, Armen; Adam, Wolfgang; Aşılar, Ece; Bergauer, Thomas; Brandstetter, Johannes; Brondolin, Erica; Dragicevic, Marko; Erö, Janos; Flechl, Martin; Friedl, Markus; Fruehwirth, Rudolf; Ghete, Vasile Mihai; Hartl, Christian; Hörmann, Natascha; Hrubec, Josef; Jeitler, Manfred; Knünz, Valentin; König, Axel; Krammer, Manfred; Krätschmer, Ilse; Liko, Dietrich; Matsushita, Takashi; Mikulec, Ivan; Rabady, Dinyar; Rahbaran, Babak; Rohringer, Herbert; Schieck, Jochen; Schöfbeck, Robert; Strauss, Josef; Treberer-Treberspurg, Wolfgang; Waltenberger, Wolfgang; Wulz, Claudia-Elisabeth; Mossolov, Vladimir; Shumeiko, Nikolai; Suarez Gonzalez, Juan; Alderweireldt, Sara; Cornelis, Tom; De Wolf, Eddi A; Janssen, Xavier; Knutsson, Albert; Lauwers, Jasper; Luyckx, Sten; Van De Klundert, Merijn; Van Haevermaet, Hans; Van Mechelen, Pierre; Van Remortel, Nick; Van Spilbeeck, Alex; Abu Zeid, Shimaa; Blekman, Freya; D'Hondt, Jorgen; Daci, Nadir; De Bruyn, Isabelle; Deroover, Kevin; Heracleous, Natalie; Keaveney, James; Lowette, Steven; Moreels, Lieselotte; Olbrechts, Annik; Python, Quentin; Strom, Derek; Tavernier, Stefaan; Van Doninck, Walter; Van Mulders, Petra; Van Onsem, Gerrit Patrick; Van Parijs, Isis; Barria, Patrizia; Brun, Hugues; Caillol, Cécile; Clerbaux, Barbara; De Lentdecker, Gilles; Fasanella, Giuseppe; Favart, Laurent; Grebenyuk, Anastasia; Karapostoli, Georgia; Lenzi, Thomas; Léonard, Alexandre; Maerschalk, Thierry; Marinov, Andrey; Perniè, Luca; Randle-conde, Aidan; Reis, Thomas; Seva, Tomislav; Vander Velde, Catherine; Vanlaer, Pascal; Yonamine, Ryo; Zenoni, Florian; Zhang, Fengwangdong; Beernaert, Kelly; Benucci, Leonardo; Cimmino, Anna; Crucy, Shannon; Dobur, Didar; Fagot, Alexis; Garcia, Guillaume; Gul, Muhammad; Mccartin, Joseph; Ocampo Rios, Alberto Andres; Poyraz, Deniz; Ryckbosch, Dirk; Salva Diblen, Sinem; Sigamani, Michael; Strobbe, Nadja; Tytgat, Michael; Van Driessche, Ward; Yazgan, Efe; Zaganidis, Nicolas; Basegmez, Suzan; Beluffi, Camille; Bondu, Olivier; Brochet, Sébastien; Bruno, Giacomo; Caudron, Adrien; Ceard, Ludivine; Da Silveira, Gustavo Gil; Delaere, Christophe; Favart, Denis; Forthomme, Laurent; Giammanco, Andrea; Hollar, Jonathan; Jafari, Abideh; Jez, Pavel; Komm, Matthias; Lemaitre, Vincent; Mertens, Alexandre; Musich, Marco; Nuttens, Claude; Perrini, Lucia; Pin, Arnaud; Piotrzkowski, Krzysztof; Popov, Andrey; Quertenmont, Loic; Selvaggi, Michele; Vidal Marono, Miguel; Beliy, Nikita; Hammad, Gregory Habib; Aldá Júnior, Walter Luiz; Alves, Fábio Lúcio; Alves, Gilvan; Brito, Lucas; Correa Martins Junior, Marcos; Hamer, Matthias; Hensel, Carsten; Mora Herrera, Clemencia; Moraes, Arthur; Pol, Maria Elena; Rebello Teles, Patricia; Belchior Batista Das Chagas, Ewerton; Carvalho, Wagner; Chinellato, Jose; Custódio, Analu; Da Costa, Eliza Melo; De Jesus Damiao, Dilson; De Oliveira Martins, Carley; Fonseca De Souza, Sandro; Huertas Guativa, Lina Milena; Malbouisson, Helena; Matos Figueiredo, Diego; Mundim, Luiz; Nogima, Helio; Prado Da Silva, Wanda Lucia; Santoro, Alberto; Sznajder, Andre; Tonelli Manganote, Edmilson José; Vilela Pereira, Antonio; Ahuja, Sudha; Bernardes, Cesar Augusto; De Souza Santos, Angelo; Dogra, Sunil; Tomei, Thiago; De Moraes Gregores, Eduardo; Mercadante, Pedro G; Moon, Chang-Seong; Novaes, Sergio F; Padula, Sandra; Romero Abad, David; Ruiz Vargas, José Cupertino; Aleksandrov, Aleksandar; Hadjiiska, Roumyana; Iaydjiev, Plamen; Rodozov, Mircho; Stoykova, Stefka; Sultanov, Georgi; Vutova, Mariana; Dimitrov, Anton; Glushkov, Ivan; Litov, Leander; Pavlov, Borislav; Petkov, Peicho; Ahmad, Muhammad; Bian, Jian-Guo; Chen, Guo-Ming; Chen, He-Sheng; Chen, Mingshui; Cheng, Tongguang; Du, Ran; Jiang, Chun-Hua; Plestina, Roko; Romeo, Francesco; Shaheen, Sarmad Masood; Spiezia, Aniello; Tao, Junquan; Wang, Chunjie; Wang, Zheng; Zhang, Huaqiao; Asawatangtrakuldee, Chayanit; Ban, Yong; Li, Qiang; Liu, Shuai; Mao, Yajun; Qian, Si-Jin; Wang, Dayong; Xu, Zijun; Avila, Carlos; Cabrera, Andrés; Chaparro Sierra, Luisa Fernanda; Florez, Carlos; Gomez, Juan Pablo; Gomez Moreno, Bernardo; Sanabria, Juan Carlos; Godinovic, Nikola; Lelas, Damir; Puljak, Ivica; Ribeiro Cipriano, Pedro M; Antunovic, Zeljko; Kovac, Marko; Brigljevic, Vuko; Kadija, Kreso; Luetic, Jelena; Micanovic, Sasa; Sudic, Lucija; Attikis, Alexandros; Mavromanolakis, Georgios; Mousa, Jehad; Nicolaou, Charalambos; Ptochos, Fotios; Razis, Panos A; Rykaczewski, Hans; Bodlak, Martin; Finger, Miroslav; Finger Jr, Michael; Assran, Yasser; El Sawy, Mai; Elgammal, Sherif; Ellithi Kamel, Ali; Mahmoud, Mohammed; Calpas, Betty; Kadastik, Mario; Murumaa, Marion; Raidal, Martti; Tiko, Andres; Veelken, Christian; Eerola, Paula; Pekkanen, Juska; Voutilainen, Mikko; Härkönen, Jaakko; Karimäki, Veikko; Kinnunen, Ritva; Lampén, Tapio; Lassila-Perini, Kati; Lehti, Sami; Lindén, Tomas; Luukka, Panja-Riina; Mäenpää, Teppo; Peltola, Timo; Tuominen, Eija; Tuominiemi, Jorma; Tuovinen, Esa; Wendland, Lauri; Talvitie, Joonas; Tuuva, Tuure; Besancon, Marc; Couderc, Fabrice; Dejardin, Marc; Denegri, Daniel; Fabbro, Bernard; Faure, Jean-Louis; Favaro, Carlotta; Ferri, Federico; Ganjour, Serguei; Givernaud, Alain; Gras, Philippe; Hamel de Monchenault, Gautier; Jarry, Patrick; Locci, Elizabeth; Machet, Martina; Malcles, Julie; Rander, John; Rosowsky, André; Titov, Maksym; Zghiche, Amina; Antropov, Iurii; Baffioni, Stephanie; Beaudette, Florian; Busson, Philippe; Cadamuro, Luca; Chapon, Emilien; Charlot, Claude; Dahms, Torsten; Davignon, Olivier; Filipovic, Nicolas; Florent, Alice; Granier de Cassagnac, Raphael; Lisniak, Stanislav; Mastrolorenzo, Luca; Miné, Philippe; Naranjo, Ivo Nicolas; Nguyen, Matthew; Ochando, Christophe; Ortona, Giacomo; Paganini, Pascal; Pigard, Philipp; Regnard, Simon; Salerno, Roberto; Sauvan, Jean-Baptiste; Sirois, Yves; Strebler, Thomas; Yilmaz, Yetkin; Zabi, Alexandre; Agram, Jean-Laurent; Andrea, Jeremy; Aubin, Alexandre; Bloch, Daniel; Brom, Jean-Marie; Buttignol, Michael; Chabert, Eric Christian; Chanon, Nicolas; Collard, Caroline; Conte, Eric; Coubez, Xavier; Fontaine, Jean-Charles; Gelé, Denis; Goerlach, Ulrich; Goetzmann, Christophe; Le Bihan, Anne-Catherine; Merlin, Jeremie Alexandre; Skovpen, Kirill; Van Hove, Pierre; Gadrat, Sébastien; Beauceron, Stephanie; Bernet, Colin; Boudoul, Gaelle; Bouvier, Elvire; Carrillo Montoya, Camilo Andres; Chierici, Roberto; Contardo, Didier; Courbon, Benoit; Depasse, Pierre; El Mamouni, Houmani; Fan, Jiawei; Fay, Jean; Gascon, Susan; Gouzevitch, Maxime; Ille, Bernard; Lagarde, Francois; Laktineh, Imad Baptiste; Lethuillier, Morgan; Mirabito, Laurent; Pequegnot, Anne-Laure; Perries, Stephane; Ruiz Alvarez, José David; Sabes, David; Sgandurra, Louis; Sordini, Viola; Vander Donckt, Muriel; Verdier, Patrice; Viret, Sébastien; Toriashvili, Tengizi; Tsamalaidze, Zviad; Autermann, Christian; Beranek, Sarah; Edelhoff, Matthias; Feld, Lutz; Heister, Arno; Kiesel, Maximilian Knut; Klein, Katja; Lipinski, Martin; Ostapchuk, Andrey; Preuten, Marius; Raupach, Frank; Schael, Stefan; Schulte, Jan-Frederik; Verlage, Tobias; Weber, Hendrik; Wittmer, Bruno; Zhukov, Valery; Ata, Metin; Brodski, Michael; Dietz-Laursonn, Erik; Duchardt, Deborah; Endres, Matthias; Erdmann, Martin; Erdweg, Sören; Esch, Thomas; Fischer, Robert; Güth, Andreas; Hebbeker, Thomas; Heidemann, Carsten; Hoepfner, Kerstin; Klingebiel, Dennis; Knutzen, Simon; Kreuzer, Peter; Merschmeyer, Markus; Meyer, Arnd; Millet, Philipp; Olschewski, Mark; Padeken, Klaas; Papacz, Paul; Pook, Tobias; Radziej, Markus; Reithler, Hans; Rieger, Marcel; Scheuch, Florian; Sonnenschein, Lars; Teyssier, Daniel; Thüer, Sebastian; Cherepanov, Vladimir; Erdogan, Yusuf; Flügge, Günter; Geenen, Heiko; Geisler, Matthias; Hoehle, Felix; Kargoll, Bastian; Kress, Thomas; Kuessel, Yvonne; Künsken, Andreas; Lingemann, Joschka; Nehrkorn, Alexander; Nowack, Andreas; Nugent, Ian Michael; Pistone, Claudia; Pooth, Oliver; Stahl, Achim; Aldaya Martin, Maria; Asin, Ivan; Bartosik, Nazar; Behnke, Olaf; Behrens, Ulf; Bell, Alan James; Borras, Kerstin; Burgmeier, Armin; Campbell, Alan; Choudhury, Somnath; Costanza, Francesco; Diez Pardos, Carmen; Dolinska, Ganna; Dooling, Samantha; Dorland, Tyler; Eckerlin, Guenter; Eckstein, Doris; Eichhorn, Thomas; Flucke, Gero; Gallo, Elisabetta; Garay Garcia, Jasone; Geiser, Achim; Gizhko, Andrii; Gunnellini, Paolo; Hauk, Johannes; Hempel, Maria; Jung, Hannes; Kalogeropoulos, Alexis; Karacheban, Olena; Kasemann, Matthias; Katsas, Panagiotis; Kieseler, Jan; Kleinwort, Claus; Korol, Ievgen; Lange, Wolfgang; Leonard, Jessica; Lipka, Katerina; Lobanov, Artur; Lohmann, Wolfgang; Mankel, Rainer; Marfin, Ihar; Melzer-Pellmann, Isabell-Alissandra; Meyer, Andreas Bernhard; Mittag, Gregor; Mnich, Joachim; Mussgiller, Andreas; Naumann-Emme, Sebastian; Nayak, Aruna; Ntomari, Eleni; Perrey, Hanno; Pitzl, Daniel; Placakyte, Ringaile; Raspereza, Alexei; Roland, Benoit; Sahin, Mehmet Özgür; Saxena, Pooja; Schoerner-Sadenius, Thomas; Schröder, Matthias; Seitz, Claudia; Spannagel, Simon; Trippkewitz, Karim Damun; Walsh, Roberval; Wissing, Christoph; Blobel, Volker; Centis Vignali, Matteo; Draeger, Arne-Rasmus; Erfle, Joachim; Garutti, Erika; Goebel, Kristin; Gonzalez, Daniel; Görner, Martin; Haller, Johannes; Hoffmann, Malte; Höing, Rebekka Sophie; Junkes, Alexandra; Klanner, Robert; Kogler, Roman; Kovalchuk, Nataliia; Lapsien, Tobias; Lenz, Teresa; Marchesini, Ivan; Marconi, Daniele; Meyer, Mareike; Nowatschin, Dominik; Ott, Jochen; Pantaleo, Felice; Peiffer, Thomas; Perieanu, Adrian; Pietsch, Niklas; Poehlsen, Jennifer; Rathjens, Denis; Sander, Christian; Scharf, Christian; Schettler, Hannes; Schleper, Peter; Schlieckau, Eike; Schmidt, Alexander; Schwandt, Joern; Sola, Valentina; Stadie, Hartmut; Steinbrück, Georg; Tholen, Heiner; Troendle, Daniel; Usai, Emanuele; Vanelderen, Lukas; Vanhoefer, Annika; Vormwald, Benedikt; Akbiyik, Melike; Barth, Christian; Baus, Colin; Berger, Joram; Böser, Christian; Butz, Erik; Chwalek, Thorsten; Colombo, Fabio; De Boer, Wim; Descroix, Alexis; Dierlamm, Alexander; Fink, Simon; Frensch, Felix; Friese, Raphael; Giffels, Manuel; Gilbert, Andrew; Haitz, Dominik; Hartmann, Frank; Heindl, Stefan Michael; Husemann, Ulrich; Katkov, Igor; Kornmayer, Andreas; Lobelle Pardo, Patricia; Maier, Benedikt; Mildner, Hannes; Mozer, Matthias Ulrich; Müller, Thomas; Müller, Thomas; Plagge, Michael; Quast, Gunter; Rabbertz, Klaus; Röcker, Steffen; Roscher, Frank; Sieber, Georg; Simonis, Hans-Jürgen; Stober, Fred-Markus Helmut; Ulrich, Ralf; Wagner-Kuhr, Jeannine; Wayand, Stefan; Weber, Marc; Weiler, Thomas; Wöhrmann, Clemens; Wolf, Roger; Anagnostou, Georgios; Daskalakis, Georgios; Geralis, Theodoros; Giakoumopoulou, Viktoria Athina; Kyriakis, Aristotelis; Loukas, Demetrios; Psallidas, Andreas; Topsis-Giotis, Iasonas; Agapitos, Antonis; Kesisoglou, Stilianos; Panagiotou, Apostolos; Saoulidou, Niki; Tziaferi, Eirini; Evangelou, Ioannis; Flouris, Giannis; Foudas, Costas; Kokkas, Panagiotis; Loukas, Nikitas; Manthos, Nikolaos; Papadopoulos, Ioannis; Paradas, Evangelos; Strologas, John; Bencze, Gyorgy; Hajdu, Csaba; Hazi, Andras; Hidas, Pàl; Horvath, Dezso; Sikler, Ferenc; Veszpremi, Viktor; Vesztergombi, Gyorgy; Zsigmond, Anna Julia; Beni, Noemi; Czellar, Sandor; Karancsi, János; Molnar, Jozsef; Szillasi, Zoltan; Bartók, Márton; Makovec, Alajos; Raics, Peter; Trocsanyi, Zoltan Laszlo; Ujvari, Balazs; Mal, Prolay; Mandal, Koushik; Sahoo, Deepak Kumar; Sahoo, Niladribihari; Swain, Sanjay Kumar; Bansal, Sunil; Beri, Suman Bala; Bhatnagar, Vipin; Chawla, Ridhi; Gupta, Ruchi; Bhawandeep, Bhawandeep; Kalsi, Amandeep Kaur; Kaur, Anterpreet; Kaur, Manjit; Kumar, Ramandeep; Mehta, Ankita; Mittal, Monika; Singh, Jasbir; Walia, Genius; Kumar, Ashok; Bhardwaj, Ashutosh; Choudhary, Brajesh C; Garg, Rocky Bala; Kumar, Ajay; Malhotra, Shivali; Naimuddin, Md; Nishu, Nishu; Ranjan, Kirti; Sharma, Ramkrishna; Sharma, Varun; Bhattacharya, Satyaki; Chatterjee, Kalyanmoy; Dey, Sourav; Dutta, Suchandra; Jain, Sandhya; Majumdar, Nayana; Modak, Atanu; Mondal, Kuntal; Mukherjee, Swagata; Mukhopadhyay, Supratik; Roy, Ashim; Roy, Debarati; Roy Chowdhury, Suvankar; Sarkar, Subir; Sharan, Manoj; Abdulsalam, Abdulla; Chudasama, Ruchi; Dutta, Dipanwita; Jha, Vishwajeet; Kumar, Vineet; Mohanty, Ajit Kumar; Pant, Lalit Mohan; Shukla, Prashant; Topkar, Anita; Aziz, Tariq; Banerjee, Sudeshna; Bhowmik, Sandeep; Chatterjee, Rajdeep Mohan; Dewanjee, Ram Krishna; Dugad, Shashikant; Ganguly, Sanmay; Ghosh, Saranya; Guchait, Monoranjan; Gurtu, Atul; Kole, Gouranga; Kumar, Sanjeev; Mahakud, Bibhuprasad; Maity, Manas; Majumder, Gobinda; Mazumdar, Kajari; Mitra, Soureek; Mohanty, Gagan Bihari; Parida, Bibhuti; Sarkar, Tanmay; Sur, Nairit; Sutar, Bajrang; Wickramage, Nadeesha; Chauhan, Shubhanshu; Dube, Sourabh; Kothekar, Kunal; Sharma, Seema; Bakhshiansohi, Hamed; Behnamian, Hadi; Etesami, Seyed Mohsen; Fahim, Ali; Goldouzian, Reza; Khakzad, Mohsen; Mohammadi Najafabadi, Mojtaba; Naseri, Mohsen; Paktinat Mehdiabadi, Saeid; Rezaei Hosseinabadi, Ferdos; Safarzadeh, Batool; Zeinali, Maryam; Felcini, Marta; Grunewald, Martin; Abbrescia, Marcello; Calabria, Cesare; Caputo, Claudio; Colaleo, Anna; Creanza, Donato; Cristella, Leonardo; De Filippis, Nicola; De Palma, Mauro; Fiore, Luigi; Iaselli, Giuseppe; Maggi, Giorgio; Maggi, Marcello; Miniello, Giorgia; My, Salvatore; Nuzzo, Salvatore; Pompili, Alexis; Pugliese, Gabriella; Radogna, Raffaella; Ranieri, Antonio; Selvaggi, Giovanna; Silvestris, Lucia; Venditti, Rosamaria; Verwilligen, Piet; Abbiendi, Giovanni; Battilana, Carlo; Benvenuti, Alberto; Bonacorsi, Daniele; Braibant-Giacomelli, Sylvie; Brigliadori, Luca; Campanini, Renato; Capiluppi, Paolo; Castro, Andrea; Cavallo, Francesca Romana; Chhibra, Simranjit Singh; Codispoti, Giuseppe; Cuffiani, Marco; Dallavalle, Gaetano-Marco; Fabbri, Fabrizio; Fanfani, Alessandra; Fasanella, Daniele; Giacomelli, Paolo; Grandi, Claudio; Guiducci, Luigi; Marcellini, Stefano; Masetti, Gianni; Montanari, Alessandro; Navarria, Francesco; Perrotta, Andrea; Rossi, Antonio; Rovelli, Tiziano; Siroli, Gian Piero; Tosi, Nicolò; Travaglini, Riccardo; Cappello, Gigi; Chiorboli, Massimiliano; Costa, Salvatore; Di Mattia, Alessandro; Giordano, Ferdinando; Potenza, Renato; Tricomi, Alessia; Tuve, Cristina; Barbagli, Giuseppe; Ciulli, Vitaliano; Civinini, Carlo; D'Alessandro, Raffaello; Focardi, Ettore; Gonzi, Sandro; Gori, Valentina; Lenzi, Piergiulio; Meschini, Marco; Paoletti, Simone; Sguazzoni, Giacomo; Tropiano, Antonio; Viliani, Lorenzo; Benussi, Luigi; Bianco, Stefano; Fabbri, Franco; Piccolo, Davide; Primavera, Federica; Calvelli, Valerio; Ferro, Fabrizio; Lo Vetere, Maurizio; Monge, Maria Roberta; Robutti, Enrico; Tosi, Silvano; Brianza, Luca; Dinardo, Mauro Emanuele; Fiorendi, Sara; Gennai, Simone; Gerosa, Raffaele; Ghezzi, Alessio; Govoni, Pietro; Malvezzi, Sandra; Manzoni, Riccardo Andrea; Marzocchi, Badder; Menasce, Dario; Moroni, Luigi; Paganoni, Marco; Pedrini, Daniele; Ragazzi, Stefano; Redaelli, Nicola; Tabarelli de Fatis, Tommaso; Buontempo, Salvatore; Cavallo, Nicola; Di Guida, Salvatore; Esposito, Marco; Fabozzi, Francesco; Iorio, Alberto Orso Maria; Lanza, Giuseppe; Lista, Luca; Meola, Sabino; Merola, Mario; Paolucci, Pierluigi; Sciacca, Crisostomo; Thyssen, Filip; Bacchetta, Nicola; Bellato, Marco; Benato, Lisa; Bisello, Dario; Boletti, Alessio; Carlin, Roberto; Checchia, Paolo; Dall'Osso, Martino; Dosselli, Umberto; Gasparini, Fabrizio; Gasparini, Ugo; Gozzelino, Andrea; Lacaprara, Stefano; Margoni, Martino; Meneguzzo, Anna Teresa; Montecassiano, Fabio; Passaseo, Marina; Pazzini, Jacopo; Pegoraro, Matteo; Pozzobon, Nicola; Simonetto, Franco; Torassa, Ezio; Tosi, Mia; Vanini, Sara; Ventura, Sandro; Zanetti, Marco; Zotto, Pierluigi; Zucchetta, Alberto; Zumerle, Gianni; Braghieri, Alessandro; Magnani, Alice; Montagna, Paolo; Ratti, Sergio P; Re, Valerio; Riccardi, Cristina; Salvini, Paola; Vai, Ilaria; Vitulo, Paolo; Alunni Solestizi, Luisa; Biasini, Maurizio; Bilei, Gian Mario; Ciangottini, Diego; Fanò, Livio; Lariccia, Paolo; Mantovani, Giancarlo; Menichelli, Mauro; Saha, Anirban; Santocchia, Attilio; Androsov, Konstantin; Azzurri, Paolo; Bagliesi, Giuseppe; Bernardini, Jacopo; Boccali, Tommaso; Castaldi, Rino; Ciocci, Maria Agnese; Dell'Orso, Roberto; Donato, Silvio; Fedi, Giacomo; Foà, Lorenzo; Giassi, Alessandro; Grippo, Maria Teresa; Ligabue, Franco; Lomtadze, Teimuraz; Martini, Luca; Messineo, Alberto; Palla, Fabrizio; Rizzi, Andrea; Savoy-Navarro, Aurore; Serban, Alin Titus; Spagnolo, Paolo; Tenchini, Roberto; Tonelli, Guido; Venturi, Andrea; Verdini, Piero Giorgio; Barone, Luciano; Cavallari, Francesca; D'imperio, Giulia; Del Re, Daniele; Diemoz, Marcella; Gelli, Simone; Jorda, Clara; Longo, Egidio; Margaroli, Fabrizio; Meridiani, Paolo; Organtini, Giovanni; Paramatti, Riccardo; Preiato, Federico; Rahatlou, Shahram; Rovelli, Chiara; Santanastasio, Francesco; Traczyk, Piotr; Amapane, Nicola; Arcidiacono, Roberta; Argiro, Stefano; Arneodo, Michele; Bellan, Riccardo; Biino, Cristina; Cartiglia, Nicolo; Costa, Marco; Covarelli, Roberto; Degano, Alessandro; Demaria, Natale; Finco, Linda; Kiani, Bilal; Mariotti, Chiara; Maselli, Silvia; Migliore, Ernesto; Monaco, Vincenzo; Monteil, Ennio; Obertino, Maria Margherita; Pacher, Luca; Pastrone, Nadia; Pelliccioni, Mario; Pinna Angioni, Gian Luca; Ravera, Fabio; Romero, Alessandra; Ruspa, Marta; Sacchi, Roberto; Solano, Ada; Staiano, Amedeo; Tamponi, Umberto; Belforte, Stefano; Candelise, Vieri; Casarsa, Massimo; Cossutti, Fabio; Della Ricca, Giuseppe; Gobbo, Benigno; La Licata, Chiara; Marone, Matteo; Schizzi, Andrea; Zanetti, Anna; Kropivnitskaya, Anna; Nam, Soon-Kwon; Kim, Dong Hee; Kim, Gui Nyun; Kim, Min Suk; Kong, Dae Jung; Lee, Sangeun; Oh, Young Do; Sakharov, Alexandre; Son, Dong-Chul; Brochero Cifuentes, Javier Andres; Kim, Hyunsoo; Kim, Tae Jeong; Song, Sanghyeon; Choi, Suyong; Go, Yeonju; Gyun, Dooyeon; Hong, Byung-Sik; Jo, Mihee; Kim, Hyunchul; Kim, Yongsun; Lee, Byounghoon; Lee, Kisoo; Lee, Kyong Sei; Lee, Songkyo; Park, Sung Keun; Roh, Youn; Yoo, Hwi Dong; Choi, Minkyoo; Kim, Hyunyong; Kim, Ji Hyun; Lee, Jason Sang Hun; Park, Inkyu; Ryu, Geonmo; Ryu, Min Sang; Choi, Young-Il; Goh, Junghwan; Kim, Donghyun; Kwon, Eunhyang; Lee, Jongseok; Yu, Intae; Dudenas, Vytautas; Juodagalvis, Andrius; Vaitkus, Juozas; Ahmed, Ijaz; Ibrahim, Zainol Abidin; Komaragiri, Jyothsna Rani; Md Ali, Mohd Adli Bin; Mohamad Idris, Faridah; Wan Abdullah, Wan Ahmad Tajuddin; Yusli, Mohd Nizam; Casimiro Linares, Edgar; Castilla-Valdez, Heriberto; De La Cruz-Burelo, Eduard; Heredia-De La Cruz, Ivan; Hernandez-Almada, Alberto; Lopez-Fernandez, Ricardo; Sánchez Hernández, Alberto; Carrillo Moreno, Salvador; Vazquez Valencia, Fabiola; Pedraza, Isabel; Salazar Ibarguen, Humberto Antonio; Morelos Pineda, Antonio; Krofcheck, David; Butler, Philip H; Ahmad, Ashfaq; Ahmad, Muhammad; Hassan, Qamar; Hoorani, Hafeez R; Khan, Wajid Ali; Khurshid, Taimoor; Shoaib, Muhammad; Bialkowska, Helena; Bluj, Michal; Boimska, Bożena; Frueboes, Tomasz; Górski, Maciej; Kazana, Malgorzata; Nawrocki, Krzysztof; Romanowska-Rybinska, Katarzyna; Szleper, Michal; Zalewski, Piotr; Brona, Grzegorz; Bunkowski, Karol; Byszuk, Adrian; Doroba, Krzysztof; Kalinowski, Artur; Konecki, Marcin; Krolikowski, Jan; Misiura, Maciej; Olszewski, Michal; Pozniak, Krzysztof; Walczak, Marek; Bargassa, Pedrame; Beirão Da Cruz E Silva, Cristóvão; Di Francesco, Agostino; Faccioli, Pietro; Ferreira Parracho, Pedro Guilherme; Gallinaro, Michele; Leonardo, Nuno; Lloret Iglesias, Lara; Nguyen, Federico; Rodrigues Antunes, Joao; Seixas, Joao; Toldaiev, Oleksii; Vadruccio, Daniele; Varela, Joao; Vischia, Pietro; Afanasiev, Serguei; Bunin, Pavel; Gavrilenko, Mikhail; Golutvin, Igor; Gorbunov, Ilya; Kamenev, Alexey; Karjavin, Vladimir; Konoplyanikov, Viktor; Lanev, Alexander; Malakhov, Alexander; Matveev, Viktor; Moisenz, Petr; Palichik, Vladimir; Perelygin, Victor; Shmatov, Sergey; Shulha, Siarhei; Skatchkov, Nikolai; Smirnov, Vitaly; Zarubin, Anatoli; Golovtsov, Victor; Ivanov, Yury; Kim, Victor; Kuznetsova, Ekaterina; Levchenko, Petr; Murzin, Victor; Oreshkin, Vadim; Smirnov, Igor; Sulimov, Valentin; Uvarov, Lev; Vavilov, Sergey; Vorobyev, Alexey; Andreev, Yuri; Dermenev, Alexander; Gninenko, Sergei; Golubev, Nikolai; Karneyeu, Anton; Kirsanov, Mikhail; Krasnikov, Nikolai; Pashenkov, Anatoli; Tlisov, Danila; Toropin, Alexander; Epshteyn, Vladimir; Gavrilov, Vladimir; Lychkovskaya, Natalia; Popov, Vladimir; Pozdnyakov, Ivan; Safronov, Grigory; Spiridonov, Alexander; Vlasov, Evgueni; Zhokin, Alexander; Bylinkin, Alexander; Andreev, Vladimir; Azarkin, Maksim; Dremin, Igor; Kirakosyan, Martin; Leonidov, Andrey; Mesyats, Gennady; Rusakov, Sergey V; Baskakov, Alexey; Belyaev, Andrey; Boos, Edouard; Dubinin, Mikhail; Dudko, Lev; Ershov, Alexander; Gribushin, Andrey; Kaminskiy, Alexandre; Klyukhin, Vyacheslav; Kodolova, Olga; Lokhtin, Igor; Miagkov, Igor; Obraztsov, Stepan; Petrushanko, Sergey; Savrin, Viktor; Azhgirey, Igor; Bayshev, Igor; Bitioukov, Sergei; Kachanov, Vassili; Kalinin, Alexey; Konstantinov, Dmitri; Krychkine, Victor; Petrov, Vladimir; Ryutin, Roman; Sobol, Andrei; Tourtchanovitch, Leonid; Troshin, Sergey; Tyurin, Nikolay; Uzunian, Andrey; Volkov, Alexey; Adzic, Petar; Milosevic, Jovan; Rekovic, Vladimir; Alcaraz Maestre, Juan; Calvo, Enrique; Cerrada, Marcos; Chamizo Llatas, Maria; Colino, Nicanor; De La Cruz, Begona; Delgado Peris, Antonio; Domínguez Vázquez, Daniel; Escalante Del Valle, Alberto; Fernandez Bedoya, Cristina; Fernández Ramos, Juan Pablo; Flix, Jose; Fouz, Maria Cruz; Garcia-Abia, Pablo; Gonzalez Lopez, Oscar; Goy Lopez, Silvia; Hernandez, Jose M; Josa, Maria Isabel; Navarro De Martino, Eduardo; Pérez-Calero Yzquierdo, Antonio María; Puerta Pelayo, Jesus; Quintario Olmeda, Adrián; Redondo, Ignacio; Romero, Luciano; Santaolalla, Javier; Soares, Mara Senghi; Albajar, Carmen; de Trocóniz, Jorge F; Missiroli, Marino; Moran, Dermot; Cuevas, Javier; Fernandez Menendez, Javier; Folgueras, Santiago; Gonzalez Caballero, Isidro; Palencia Cortezon, Enrique; Vizan Garcia, Jesus Manuel; Cabrillo, Iban Jose; Calderon, Alicia; Castiñeiras De Saa, Juan Ramon; De Castro Manzano, Pablo; Duarte Campderros, Jordi; Fernandez, Marcos; Garcia-Ferrero, Juan; Gomez, Gervasio; Lopez Virto, Amparo; Marco, Jesus; Marco, Rafael; Martinez Rivero, Celso; Matorras, Francisco; Munoz Sanchez, Francisca Javiela; Piedra Gomez, Jonatan; Rodrigo, Teresa; Rodríguez-Marrero, Ana Yaiza; Ruiz-Jimeno, Alberto; Scodellaro, Luca; Trevisani, Nicolò; Vila, Ivan; Vilar Cortabitarte, Rocio; Abbaneo, Duccio; Auffray, Etiennette; Auzinger, Georg; Bachtis, Michail; Baillon, Paul; Ball, Austin; Barney, David; Benaglia, Andrea; Bendavid, Joshua; Benhabib, Lamia; Benitez, Jose F; Berruti, Gaia Maria; Bloch, Philippe; Bocci, Andrea; Bonato, Alessio; Botta, Cristina; Breuker, Horst; Camporesi, Tiziano; Castello, Roberto; Cerminara, Gianluca; D'Alfonso, Mariarosaria; D'Enterria, David; Dabrowski, Anne; Daponte, Vincenzo; David Tinoco Mendes, Andre; De Gruttola, Michele; De Guio, Federico; De Roeck, Albert; De Visscher, Simon; Di Marco, Emanuele; Dobson, Marc; Dordevic, Milos; Dorney, Brian; Du Pree, Tristan; Dünser, Marc; Dupont, Niels; Elliott-Peisert, Anna; Franzoni, Giovanni; Funk, Wolfgang; Gigi, Dominique; Gill, Karl; Giordano, Domenico; Girone, Maria; Glege, Frank; Guida, Roberto; Gundacker, Stefan; Guthoff, Moritz; Hammer, Josef; Harris, Philip; Hegeman, Jeroen; Innocente, Vincenzo; Janot, Patrick; Kirschenmann, Henning; Kortelainen, Matti J; Kousouris, Konstantinos; Krajczar, Krisztian; Lecoq, Paul; Lourenco, Carlos; Lucchini, Marco Toliman; Magini, Nicolo; Malgeri, Luca; Mannelli, Marcello; Martelli, Arabella; Masetti, Lorenzo; Meijers, Frans; Mersi, Stefano; Meschi, Emilio; Moortgat, Filip; Morovic, Srecko; Mulders, Martijn; Nemallapudi, Mythra Varun; Neugebauer, Hannes; Orfanelli, Styliani; Orsini, Luciano; Pape, Luc; Perez, Emmanuelle; Peruzzi, Marco; Petrilli, Achille; Petrucciani, Giovanni; Pfeiffer, Andreas; Piparo, Danilo; Racz, Attila; Rolandi, Gigi; Rovere, Marco; Ruan, Manqi; Sakulin, Hannes; Schäfer, Christoph; Schwick, Christoph; Seidel, Markus; Sharma, Archana; Silva, Pedro; Simon, Michal; Sphicas, Paraskevas; Steggemann, Jan; Stieger, Benjamin; Stoye, Markus; Takahashi, Yuta; Treille, Daniel; Triossi, Andrea; Tsirou, Andromachi; Veres, Gabor Istvan; Wardle, Nicholas; Wöhri, Hermine Katharina; Zagoździńska, Agnieszka; Zeuner, Wolfram Dietrich; Bertl, Willi; Deiters, Konrad; Erdmann, Wolfram; Horisberger, Roland; Ingram, Quentin; Kaestli, Hans-Christian; Kotlinski, Danek; Langenegger, Urs; Renker, Dieter; Rohe, Tilman; Bachmair, Felix; Bäni, Lukas; Bianchini, Lorenzo; Casal, Bruno; Dissertori, Günther; Dittmar, Michael; Donegà, Mauro; Eller, Philipp; Grab, Christoph; Heidegger, Constantin; Hits, Dmitry; Hoss, Jan; Kasieczka, Gregor; Lustermann, Werner; Mangano, Boris; Marionneau, Matthieu; Martinez Ruiz del Arbol, Pablo; Masciovecchio, Mario; Meister, Daniel; Micheli, Francesco; Musella, Pasquale; Nessi-Tedaldi, Francesca; Pandolfi, Francesco; Pata, Joosep; Pauss, Felicitas; Perrozzi, Luca; Quittnat, Milena; Rossini, Marco; Starodumov, Andrei; Takahashi, Maiko; Tavolaro, Vittorio Raoul; Theofilatos, Konstantinos; Wallny, Rainer; Aarrestad, Thea Klaeboe; Amsler, Claude; Caminada, Lea; Canelli, Maria Florencia; Chiochia, Vincenzo; De Cosa, Annapaola; Galloni, Camilla; Hinzmann, Andreas; Hreus, Tomas; Kilminster, Benjamin; Lange, Clemens; Ngadiuba, Jennifer; Pinna, Deborah; Robmann, Peter; Ronga, Frederic Jean; Salerno, Daniel; Yang, Yong; Cardaci, Marco; Chen, Kuan-Hsin; Doan, Thi Hien; Jain, Shilpi; Khurana, Raman; Konyushikhin, Maxim; Kuo, Chia-Ming; Lin, Willis; Lu, Yun-Ju; Yu, Shin-Shan; Kumar, Arun; Bartek, Rachel; Chang, Paoti; Chang, You-Hao; Chang, Yu-Wei; Chao, Yuan; Chen, Kai-Feng; Chen, Po-Hsun; Dietz, Charles; Fiori, Francesco; Grundler, Ulysses; Hou, George Wei-Shu; Hsiung, Yee; Liu, Yueh-Feng; Lu, Rong-Shyang; Miñano Moya, Mercedes; Petrakou, Eleni; Tsai, Jui-fa; Tzeng, Yeng-Ming; Asavapibhop, Burin; Kovitanggoon, Kittikul; Singh, Gurpreet; Srimanobhas, Norraphat; Suwonjandee, Narumon; Adiguzel, Aytul; Bakirci, Mustafa Numan; Demiroglu, Zuhal Seyma; Dozen, Candan; Eskut, Eda; Girgis, Semiray; Gokbulut, Gul; Guler, Yalcin; Gurpinar, Emine; Hos, Ilknur; Kangal, Evrim Ersin; Onengut, Gulsen; Ozdemir, Kadri; Polatoz, Ayse; Sunar Cerci, Deniz; Tali, Bayram; Topakli, Huseyin; Vergili, Mehmet; Zorbilmez, Caglar; Akin, Ilina Vasileva; Bilin, Bugra; Bilmis, Selcuk; Isildak, Bora; Karapinar, Guler; Yalvac, Metin; Zeyrek, Mehmet; Gülmez, Erhan; Kaya, Mithat; Kaya, Ozlem; Yetkin, Elif Asli; Yetkin, Taylan; Cakir, Altan; Cankocak, Kerem; Sen, Sercan; Vardarlı, Fuat Ilkehan; Grynyov, Boris; Levchuk, Leonid; Sorokin, Pavel; Aggleton, Robin; Ball, Fionn; Beck, Lana; Brooke, James John; Clement, Emyr; Cussans, David; Flacher, Henning; Goldstein, Joel; Grimes, Mark; Heath, Greg P; Heath, Helen F; Jacob, Jeson; Kreczko, Lukasz; Lucas, Chris; Meng, Zhaoxia; Newbold, Dave M; Paramesvaran, Sudarshan; Poll, Anthony; Sakuma, Tai; Seif El Nasr-storey, Sarah; Senkin, Sergey; Smith, Dominic; Smith, Vincent J; Bell, Ken W; Belyaev, Alexander; Brew, Christopher; Brown, Robert M; Calligaris, Luigi; Cieri, Davide; Cockerill, David JA; Coughlan, John A; Harder, Kristian; Harper, Sam; Olaiya, Emmanuel; Petyt, David; Shepherd-Themistocleous, Claire; Thea, Alessandro; Tomalin, Ian R; Williams, Thomas; Womersley, William John; Worm, Steven; Baber, Mark; Bainbridge, Robert; Buchmuller, Oliver; Bundock, Aaron; Burton, Darren; Casasso, Stefano; Citron, Matthew; Colling, David; Corpe, Louie; Cripps, Nicholas; Dauncey, Paul; Davies, Gavin; De Wit, Adinda; Della Negra, Michel; Dunne, Patrick; Elwood, Adam; Ferguson, William; Fulcher, Jonathan; Futyan, David; Hall, Geoffrey; Iles, Gregory; Kenzie, Matthew; Lane, Rebecca; Lucas, Robyn; Lyons, Louis; Magnan, Anne-Marie; Malik, Sarah; Nash, Jordan; Nikitenko, Alexander; Pela, Joao; Pesaresi, Mark; Petridis, Konstantinos; Raymond, David Mark; Richards, Alexander; Rose, Andrew; Seez, Christopher; Tapper, Alexander; Uchida, Kirika; Vazquez Acosta, Monica; Virdee, Tejinder; Zenz, Seth Conrad; Cole, Joanne; Hobson, Peter R; Khan, Akram; Kyberd, Paul; Leggat, Duncan; Leslie, Dawn; Reid, Ivan; Symonds, Philip; Teodorescu, Liliana; Turner, Mark; Borzou, Ahmad; Call, Kenneth; Dittmann, Jay; Hatakeyama, Kenichi; Liu, Hongxuan; Pastika, Nathaniel; Charaf, Otman; Cooper, Seth; Henderson, Conor; Rumerio, Paolo; Arcaro, Daniel; Avetisyan, Aram; Bose, Tulika; Fantasia, Cory; Gastler, Daniel; Lawson, Philip; Rankin, Dylan; Richardson, Clint; Rohlf, James; St John, Jason; Sulak, Lawrence; Zou, David; Alimena, Juliette; Berry, Edmund; Bhattacharya, Saptaparna; Cutts, David; Dhingra, Nitish; Ferapontov, Alexey; Garabedian, Alex; Hakala, John; Heintz, Ulrich; Laird, Edward; Landsberg, Greg; Mao, Zaixing; Narain, Meenakshi; Piperov, Stefan; Sagir, Sinan; Syarif, Rizki; Breedon, Richard; Breto, Guillermo; Calderon De La Barca Sanchez, Manuel; Chauhan, Sushil; Chertok, Maxwell; Conway, John; Conway, Rylan; Cox, Peter Timothy; Erbacher, Robin; Gardner, Michael; Ko, Winston; Lander, Richard; Mulhearn, Michael; Pellett, Dave; Pilot, Justin; Ricci-Tam, Francesca; Shalhout, Shalhout; Smith, John; Squires, Michael; Stolp, Dustin; Tripathi, Mani; Wilbur, Scott; Yohay, Rachel; Cousins, Robert; Everaerts, Pieter; Farrell, Chris; Hauser, Jay; Ignatenko, Mikhail; Saltzberg, David; Takasugi, Eric; Valuev, Vyacheslav; Weber, Matthias; Burt, Kira; Clare, Robert; Ellison, John Anthony; Gary, J William; Hanson, Gail; Heilman, Jesse; Paneva, Mirena Ivova; Jandir, Pawandeep; Kennedy, Elizabeth; Lacroix, Florent; Long, Owen Rosser; Luthra, Arun; Malberti, Martina; Olmedo Negrete, Manuel; Shrinivas, Amithabh; Wei, Hua; Wimpenny, Stephen; Yates, Brent; Branson, James G; Cerati, Giuseppe Benedetto; Cittolin, Sergio; D'Agnolo, Raffaele Tito; Derdzinski, Mark; Holzner, André; Kelley, Ryan; Klein, Daniel; Letts, James; Macneill, Ian; Olivito, Dominick; Padhi, Sanjay; Pieri, Marco; Sani, Matteo; Sharma, Vivek; Simon, Sean; Tadel, Matevz; Vartak, Adish; Wasserbaech, Steven; Welke, Charles; Würthwein, Frank; Yagil, Avraham; Zevi Della Porta, Giovanni; Bradmiller-Feld, John; Campagnari, Claudio; Dishaw, Adam; Dutta, Valentina; Flowers, Kristen; Franco Sevilla, Manuel; Geffert, Paul; George, Christopher; Golf, Frank; Gouskos, Loukas; Gran, Jason; Incandela, Joe; Mccoll, Nickolas; Mullin, Sam Daniel; Richman, Jeffrey; Stuart, David; Suarez, Indara; West, Christopher; Yoo, Jaehyeok; Anderson, Dustin; Apresyan, Artur; Bornheim, Adolf; Bunn, Julian; Chen, Yi; Duarte, Javier; Mott, Alexander; Newman, Harvey B; Pena, Cristian; Pierini, Maurizio; Spiropulu, Maria; Vlimant, Jean-Roch; Xie, Si; Zhu, Ren-Yuan; Andrews, Michael Benjamin; Azzolini, Virginia; Calamba, Aristotle; Carlson, Benjamin; Ferguson, Thomas; Paulini, Manfred; Russ, James; Sun, Menglei; Vogel, Helmut; Vorobiev, Igor; Cumalat, John Perry; Ford, William T; Gaz, Alessandro; Jensen, Frank; Johnson, Andrew; Krohn, Michael; Mulholland, Troy; Nauenberg, Uriel; Stenson, Kevin; Wagner, Stephen Robert; Alexander, James; Chatterjee, Avishek; Chaves, Jorge; Chu, Jennifer; Dittmer, Susan; Eggert, Nicholas; Mirman, Nathan; Nicolas Kaufman, Gala; Patterson, Juliet Ritchie; Rinkevicius, Aurelijus; Ryd, Anders; Skinnari, Louise; Soffi, Livia; Sun, Werner; Tan, Shao Min; Teo, Wee Don; Thom, Julia; Thompson, Joshua; Tucker, Jordan; Weng, Yao; Wittich, Peter; Abdullin, Salavat; Albrow, Michael; Anderson, Jacob; Apollinari, Giorgio; Banerjee, Sunanda; Bauerdick, Lothar AT; Beretvas, Andrew; Berryhill, Jeffrey; Bhat, Pushpalatha C; Bolla, Gino; Burkett, Kevin; Butler, Joel Nathan; Cheung, Harry; Chlebana, Frank; Cihangir, Selcuk; Elvira, Victor Daniel; Fisk, Ian; Freeman, Jim; Gottschalk, Erik; Gray, Lindsey; Green, Dan; Grünendahl, Stefan; Gutsche, Oliver; Hanlon, Jim; Hare, Daryl; Harris, Robert M; Hasegawa, Satoshi; Hirschauer, James; Hu, Zhen; Jayatilaka, Bodhitha; Jindariani, Sergo; Johnson, Marvin; Joshi, Umesh; Jung, Andreas Werner; Klima, Boaz; Kreis, Benjamin; Kwan, Simon; Lammel, Stephan; Linacre, Jacob; Lincoln, Don; Lipton, Ron; Liu, Tiehui; Lopes De Sá, Rafael; Lykken, Joseph; Maeshima, Kaori; Marraffino, John Michael; Martinez Outschoorn, Verena Ingrid; Maruyama, Sho; Mason, David; McBride, Patricia; Merkel, Petra; Mishra, Kalanand; Mrenna, Stephen; Nahn, Steve; Newman-Holmes, Catherine; O'Dell, Vivian; Pedro, Kevin; Prokofyev, Oleg; Rakness, Gregory; Sexton-Kennedy, Elizabeth; Soha, Aron; Spalding, William J; Spiegel, Leonard; Taylor, Lucas; Tkaczyk, Slawek; Tran, Nhan Viet; Uplegger, Lorenzo; Vaandering, Eric Wayne; Vernieri, Caterina; Verzocchi, Marco; Vidal, Richard; Weber, Hannsjoerg Artur; Whitbeck, Andrew; Yang, Fan; Acosta, Darin; Avery, Paul; Bortignon, Pierluigi; Bourilkov, Dimitri; Carnes, Andrew; Carver, Matthew; Curry, David; Das, Souvik; Di Giovanni, Gian Piero; Field, Richard D; Furic, Ivan-Kresimir; Gleyzer, Sergei V; Hugon, Justin; Konigsberg, Jacobo; Korytov, Andrey; Low, Jia Fu; Ma, Peisen; Matchev, Konstantin; Mei, Hualin; Milenovic, Predrag; Mitselmakher, Guenakh; Rank, Douglas; Rossin, Roberto; Shchutska, Lesya; Snowball, Matthew; Sperka, David; Terentyev, Nikolay; Thomas, Laurent; Wang, Jian; Wang, Sean-Jiun; Yelton, John; Hewamanage, Samantha; Linn, Stephan; Markowitz, Pete; Martinez, German; Rodriguez, Jorge Luis; Ackert, Andrew; Adams, Jordon Rowe; Adams, Todd; Askew, Andrew; Bochenek, Joseph; Diamond, Brendan; Haas, Jeff; Hagopian, Sharon; Hagopian, Vasken; Johnson, Kurtis F; Khatiwada, Ajeeta; Prosper, Harrison; Weinberg, Marc; Baarmand, Marc M; Bhopatkar, Vallary; Colafranceschi, Stefano; Hohlmann, Marcus; Kalakhety, Himali; Noonan, Daniel; Roy, Titas; Yumiceva, Francisco; Adams, Mark Raymond; Apanasevich, Leonard; Berry, Douglas; Betts, Russell Richard; Bucinskaite, Inga; Cavanaugh, Richard; Evdokimov, Olga; Gauthier, Lucie; Gerber, Cecilia Elena; Hofman, David Jonathan; Kurt, Pelin; O'Brien, Christine; Sandoval Gonzalez, Irving Daniel; Silkworth, Christopher; Turner, Paul; Varelas, Nikos; Wu, Zhenbin; Zakaria, Mohammed; Bilki, Burak; Clarida, Warren; Dilsiz, Kamuran; Durgut, Süleyman; Gandrajula, Reddy Pratap; Haytmyradov, Maksat; Khristenko, Viktor; Merlo, Jean-Pierre; Mermerkaya, Hamit; Mestvirishvili, Alexi; Moeller, Anthony; Nachtman, Jane; Ogul, Hasan; Onel, Yasar; Ozok, Ferhat; Penzo, Aldo; Snyder, Christina; Tiras, Emrah; Wetzel, James; Yi, Kai; Anderson, Ian; Barnett, Bruce Arnold; Blumenfeld, Barry; Eminizer, Nicholas; Fehling, David; Feng, Lei; Gritsan, Andrei; Maksimovic, Petar; Martin, Christopher; Osherson, Marc; Roskes, Jeffrey; Cocoros, Alice; Sarica, Ulascan; Swartz, Morris; Xiao, Meng; Xin, Yongjie; You, Can; Baringer, Philip; Bean, Alice; Benelli, Gabriele; Bruner, Christopher; Kenny III, Raymond Patrick; Majumder, Devdatta; Malek, Magdalena; Murray, Michael; Sanders, Stephen; Stringer, Robert; Wang, Quan; Ivanov, Andrew; Kaadze, Ketino; Khalil, Sadia; Makouski, Mikhail; Maravin, Yurii; Mohammadi, Abdollah; Saini, Lovedeep Kaur; Skhirtladze, Nikoloz; Toda, Sachiko; Lange, David; Rebassoo, Finn; Wright, Douglas; Anelli, Christopher; Baden, Drew; Baron, Owen; Belloni, Alberto; Calvert, Brian; Eno, Sarah Catherine; Ferraioli, Charles; Gomez, Jaime; Hadley, Nicholas John; Jabeen, Shabnam; Kellogg, Richard G; Kolberg, Ted; Kunkle, Joshua; Lu, Ying; Mignerey, Alice; Shin, Young Ho; Skuja, Andris; Tonjes, Marguerite; Tonwar, Suresh C; Apyan, Aram; Barbieri, Richard; Baty, Austin; Bierwagen, Katharina; Brandt, Stephanie; Busza, Wit; Cali, Ivan Amos; Demiragli, Zeynep; Di Matteo, Leonardo; Gomez Ceballos, Guillelmo; Goncharov, Maxim; Gulhan, Doga; Iiyama, Yutaro; Innocenti, Gian Michele; Klute, Markus; Kovalskyi, Dmytro; Lai, Yue Shi; Lee, Yen-Jie; Levin, Andrew; Luckey, Paul David; Marini, Andrea Carlo; Mcginn, Christopher; Mironov, Camelia; Narayanan, Siddharth; Niu, Xinmei; Paus, Christoph; Ralph, Duncan; Roland, Christof; Roland, Gunther; Salfeld-Nebgen, Jakob; Stephans, George; Sumorok, Konstanty; Varma, Mukund; Velicanu, Dragos; Veverka, Jan; Wang, Jing; Wang, Ta-Wei; Wyslouch, Bolek; Yang, Mingming; Zhukova, Victoria; Dahmes, Bryan; Evans, Andrew; Finkel, Alexey; Gude, Alexander; Hansen, Peter; Kalafut, Sean; Kao, Shih-Chuan; Klapoetke, Kevin; Kubota, Yuichi; Lesko, Zachary; Mans, Jeremy; Nourbakhsh, Shervin; Ruckstuhl, Nicole; Rusack, Roger; Tambe, Norbert; Turkewitz, Jared; Acosta, John Gabriel; Oliveros, Sandra; Avdeeva, Ekaterina; Bloom, Kenneth; Bose, Suvadeep; Claes, Daniel R; Dominguez, Aaron; Fangmeier, Caleb; Gonzalez Suarez, Rebeca; Kamalieddin, Rami; Keller, Jason; Knowlton, Dan; Kravchenko, Ilya; Meier, Frank; Monroy, Jose; Ratnikov, Fedor; Siado, Joaquin Emilo; Snow, Gregory R; Alyari, Maral; Dolen, James; George, Jimin; Godshalk, Andrew; Harrington, Charles; Iashvili, Ia; Kaisen, Josh; Kharchilava, Avto; Kumar, Ashish; Rappoccio, Salvatore; Roozbahani, Bahareh; Alverson, George; Barberis, Emanuela; Baumgartel, Darin; Chasco, Matthew; Hortiangtham, Apichart; Massironi, Andrea; Morse, David Michael; Nash, David; Orimoto, Toyoko; Teixeira De Lima, Rafael; Trocino, Daniele; Wang, Ren-Jie; Wood, Darien; Zhang, Jinzhong; Hahn, Kristan Allan; Kubik, Andrew; Mucia, Nicholas; Odell, Nathaniel; Pollack, Brian; Pozdnyakov, Andrey; Schmitt, Michael Henry; Stoynev, Stoyan; Sung, Kevin; Trovato, Marco; Velasco, Mayda; Brinkerhoff, Andrew; Dev, Nabarun; Hildreth, Michael; Jessop, Colin; Karmgard, Daniel John; Kellams, Nathan; Lannon, Kevin; Lynch, Sean; Marinelli, Nancy; Meng, Fanbo; Mueller, Charles; Musienko, Yuri; Pearson, Tessa; Planer, Michael; Reinsvold, Allison; Ruchti, Randy; Smith, Geoffrey; Taroni, Silvia; Valls, Nil; Wayne, Mitchell; Wolf, Matthias; Woodard, Anna; Antonelli, Louis; Brinson, Jessica; Bylsma, Ben; Durkin, Lloyd Stanley; Flowers, Sean; Hart, Andrew; Hill, Christopher; Hughes, Richard; Ji, Weifeng; Kotov, Khristian; Ling, Ta-Yung; Liu, Bingxuan; Luo, Wuming; Puigh, Darren; Rodenburg, Marissa; Winer, Brian L; Wulsin, Howard Wells; Driga, Olga; Elmer, Peter; Hardenbrook, Joshua; Hebda, Philip; Koay, Sue Ann; Lujan, Paul; Marlow, Daniel; Medvedeva, Tatiana; Mooney, Michael; Olsen, James; Palmer, Christopher; Piroué, Pierre; Saka, Halil; Stickland, David; Tully, Christopher; Zuranski, Andrzej; Malik, Sudhir; Barnes, Virgil E; Benedetti, Daniele; Bortoletto, Daniela; Gutay, Laszlo; Jha, Manoj; Jones, Matthew; Jung, Kurt; Miller, David Harry; Neumeister, Norbert; Radburn-Smith, Benjamin Charles; Shi, Xin; Shipsey, Ian; Silvers, David; Sun, Jian; Svyatkovskiy, Alexey; Wang, Fuqiang; Xie, Wei; Xu, Lingshan; Parashar, Neeti; Stupak, John; Adair, Antony; Akgun, Bora; Chen, Zhenyu; Ecklund, Karl Matthew; Geurts, Frank JM; Guilbaud, Maxime; Li, Wei; Michlin, Benjamin; Northup, Michael; Padley, Brian Paul; Redjimi, Radia; Roberts, Jay; Rorie, Jamal; Tu, Zhoudunming; Zabel, James; Betchart, Burton; Bodek, Arie; de Barbaro, Pawel; Demina, Regina; Eshaq, Yossof; Ferbel, Thomas; Galanti, Mario; Garcia-Bellido, Aran; Han, Jiyeon; Harel, Amnon; Hindrichs, Otto; Khukhunaishvili, Aleko; Petrillo, Gianluca; Tan, Ping; Verzetti, Mauro; Arora, Sanjay; Barker, Anthony; Chou, John Paul; Contreras-Campana, Christian; Contreras-Campana, Emmanuel; Duggan, Daniel; Ferencek, Dinko; Gershtein, Yuri; Gray, Richard; Halkiadakis, Eva; Hidas, Dean; Hughes, Elliot; Kaplan, Steven; Kunnawalkam Elayavalli, Raghav; Lath, Amitabh; Nash, Kevin; Panwalkar, Shruti; Park, Michael; Salur, Sevil; Schnetzer, Steve; Sheffield, David; Somalwar, Sunil; Stone, Robert; Thomas, Scott; Thomassen, Peter; Walker, Matthew; Foerster, Mark; Riley, Grant; Rose, Keith; Spanier, Stefan; York, Andrew; Bouhali, Othmane; Castaneda Hernandez, Alfredo; Dalchenko, Mykhailo; De Mattia, Marco; Delgado, Andrea; Dildick, Sven; Eusebi, Ricardo; Gilmore, Jason; Kamon, Teruki; Krutelyov, Vyacheslav; Mueller, Ryan; Osipenkov, Ilya; Pakhotin, Yuriy; Patel, Rishi; Perloff, Alexx; Rose, Anthony; Safonov, Alexei; Tatarinov, Aysen; Ulmer, Keith; Akchurin, Nural; Cowden, Christopher; Damgov, Jordan; Dragoiu, Cosmin; Dudero, Phillip Russell; Faulkner, James; Kunori, Shuichi; Lamichhane, Kamal; Lee, Sung Won; Libeiro, Terence; Undleeb, Sonaina; Volobouev, Igor; Appelt, Eric; Delannoy, Andrés G; Greene, Senta; Gurrola, Alfredo; Janjam, Ravi; Johns, Willard; Maguire, Charles; Mao, Yaxian; Melo, Andrew; Ni, Hong; Sheldon, Paul; Snook, Benjamin; Tuo, Shengquan; Velkovska, Julia; Xu, Qiao; Arenton, Michael Wayne; Cox, Bradley; Francis, Brian; Goodell, Joseph; Hirosky, Robert; Ledovskoy, Alexander; Li, Hengne; Lin, Chuanzhe; Neu, Christopher; Sinthuprasith, Tutanon; Sun, Xin; Wang, Yanchu; Wolfe, Evan; Wood, John; Xia, Fan; Clarke, Christopher; Harr, Robert; Karchin, Paul Edmund; Kottachchi Kankanamge Don, Chamath; Lamichhane, Pramod; Sturdy, Jared; Belknap, Donald; Carlsmith, Duncan; Cepeda, Maria; Dasu, Sridhara; Dodd, Laura; Duric, Senka; Gomber, Bhawna; Grothe, Monika; Hall-Wilton, Richard; Herndon, Matthew; Hervé, Alain; Klabbers, Pamela; Lanaro, Armando; Levine, Aaron; Long, Kenneth; Loveless, Richard; Mohapatra, Ajit; Ojalvo, Isabel; Perry, Thomas; Pierro, Giuseppe Antonio; Polese, Giovanni; Ruggles, Tyler; Sarangi, Tapas; Savin, Alexander; Sharma, Archana; Smith, Nicholas; Smith, Wesley H; Taylor, Devin; Woods, Nathaniel

    2016-01-01

    This paper describes the CMS trigger system and its performance during Run 1 of the LHC. The trigger system consists of two levels designed to select events of potential physics interest from a GHz (MHz) interaction rate of proton-proton (heavy ion) collisions. The first level of the trigger is implemented in hardware, and selects events containing detector signals consistent with an electron, photon, muon, $\\tau$ lepton, jet, or missing transverse energy. A programmable menu of up to 128 object-based algorithms is used to select events for subsequent processing. The trigger thresholds are adjusted to the LHC instantaneous luminosity during data taking in order to restrict the output rate to 100 kHz, the upper limit imposed by the CMS readout electronics. The second level, implemented in software, further refines the purity of the output stream, selecting an average rate of 400 Hz for offline event storage. The objectives, strategy and performance of the trigger system during the LHC Run 1 are described.

  16. The CMS trigger system

    Energy Technology Data Exchange (ETDEWEB)

    Khachatryan, Vardan; et al.

    2016-09-08

    This paper describes the CMS trigger system and its performance during Run 1 of the LHC. The trigger system consists of two levels designed to select events of potential physics interest from a GHz (MHz) interaction rate of proton-proton (heavy ion) collisions. The first level of the trigger is implemented in hardware, and selects events containing detector signals consistent with an electron, photon, muon, tau lepton, jet, or missing transverse energy. A programmable menu of up to 128 object-based algorithms is used to select events for subsequent processing. The trigger thresholds are adjusted to the LHC instantaneous luminosity during data taking in order to restrict the output rate to 100 kHz, the upper limit imposed by the CMS readout electronics. The second level, implemented in software, further refines the purity of the output stream, selecting an average rate of 400 Hz for offline event storage. The objectives, strategy and performance of the trigger system during the LHC Run 1 are described.

  17. Design studies for the Double Chooz trigger

    Energy Technology Data Exchange (ETDEWEB)

    Cucoanes, Andi Sebastian

    2009-07-24

    The main characteristic of the neutrino mixing effect is assumed to be the coupling between the flavor and the mass eigenstates. Three mixing angles ({theta}{sub 12}, {theta}{sub 23}, {theta}{sub 13}) are describing the magnitude of this effect. Still unknown, {theta}{sub 13} is considered very small, based on the measurement done by the CHOOZ experiment. A leading experiment will be Double Chooz, placed in the Ardennes region, on the same site as used by CHOOZ. The Double Chooz goal is the exploration of {proportional_to}80% from the currently allowed {theta}{sub 13} region, by searching the disappearance of reactor antineutrinos. Double Chooz will use two similar detectors, located at different distances from the reactor cores: a near one at {proportional_to}150 m where no oscillations are expected and a far one at 1.05 km distance, close to the first minimum of the survival probability function. The measurement foresees a precise comparison of neutrino rates and spectra between both detectors. The detection mechanism is based on the inverse {beta}-decay. The Double Chooz detectors have been designed to minimize the rate of random background. In a simplified view, two optically separated regions are considered. The target, filled with Gd-doped liquid scintillator, is the main antineutrino interaction volume. Surrounding the target, the inner veto region aims to tag the cosmogenic muon background which hits the detector. Both regions are viewed by photomultipliers. The Double Chooz trigger system has to be highly efficient for antineutrino events as well as for several types of background. The trigger analyzes discriminated signals from the central region and the inner veto photomultipliers. The trigger logic is fully programmable and can combine the input signals. The trigger conditions are based on the total energy released in event and on the PMT groups multiplicity. For redundancy, two independent trigger boards will be used for the central region, each of

  18. Design studies for the Double Chooz trigger

    International Nuclear Information System (INIS)

    The main characteristic of the neutrino mixing effect is assumed to be the coupling between the flavor and the mass eigenstates. Three mixing angles (θ12, θ23, θ13) are describing the magnitude of this effect. Still unknown, θ13 is considered very small, based on the measurement done by the CHOOZ experiment. A leading experiment will be Double Chooz, placed in the Ardennes region, on the same site as used by CHOOZ. The Double Chooz goal is the exploration of ∝80% from the currently allowed θ13 region, by searching the disappearance of reactor antineutrinos. Double Chooz will use two similar detectors, located at different distances from the reactor cores: a near one at ∝150 m where no oscillations are expected and a far one at 1.05 km distance, close to the first minimum of the survival probability function. The measurement foresees a precise comparison of neutrino rates and spectra between both detectors. The detection mechanism is based on the inverse β-decay. The Double Chooz detectors have been designed to minimize the rate of random background. In a simplified view, two optically separated regions are considered. The target, filled with Gd-doped liquid scintillator, is the main antineutrino interaction volume. Surrounding the target, the inner veto region aims to tag the cosmogenic muon background which hits the detector. Both regions are viewed by photomultipliers. The Double Chooz trigger system has to be highly efficient for antineutrino events as well as for several types of background. The trigger analyzes discriminated signals from the central region and the inner veto photomultipliers. The trigger logic is fully programmable and can combine the input signals. The trigger conditions are based on the total energy released in event and on the PMT groups multiplicity. For redundancy, two independent trigger boards will be used for the central region, each of them receiving signals from half of the photomultipliers. A third trigger board will

  19. Comparison of triggering systems for neonatal patient triggered ventilation.

    OpenAIRE

    Hird, M F; Greenough, A

    1991-01-01

    The efficacy of two triggering systems was compared during neonatal patient triggered ventilation: the Graseby MR10 respiration monitor and airway pressure changes. Ten preterm infants were studied, median gestational age 33 weeks (range 28-35). Patient triggered ventilation was administered via the SLE ventilator at a series of inflation times (0.24, 0.3, and 0.4 seconds). Comparison was made between the trigger systems of the trigger delay, inflation volume delivered, and proportion of spon...

  20. Comparison of the Discriminatory Processor Sharing Policies

    CERN Document Server

    Osipova, Natalia

    2008-01-01

    Discriminatory Processor Sharing policy introduced by Kleinrock is of a great interest in many application areas, including telecommunications, web applications and TCP flow modelling. Under the DPS policy the job priority is controlled by the vector of weights. Verifying the vector of weights it is possible to modify the service rates of the jobs and optimize system characteristics. In the present paper we present the results concerning the comparison of two DPS policies with different weight vectors. We show the monotonicity of the expected sojourn time of the system depending on the weight vector under certain condition on the system. Namely, the system has to consist of classes with means which are quite different from each other. The classes with similar means can be organized together and considered as one class, so the given restriction can be overcame.

  1. Efficient quantum walk on a quantum processor

    Science.gov (United States)

    Qiang, Xiaogang; Loke, Thomas; Montanaro, Ashley; Aungskunsiri, Kanin; Zhou, Xiaoqi; O'Brien, Jeremy L.; Wang, Jingbo B.; Matthews, Jonathan C. F.

    2016-05-01

    The random walk formalism is used across a wide range of applications, from modelling share prices to predicting population genetics. Likewise, quantum walks have shown much potential as a framework for developing new quantum algorithms. Here we present explicit efficient quantum circuits for implementing continuous-time quantum walks on the circulant class of graphs. These circuits allow us to sample from the output probability distributions of quantum walks on circulant graphs efficiently. We also show that solving the same sampling problem for arbitrary circulant quantum circuits is intractable for a classical computer, assuming conjectures from computational complexity theory. This is a new link between continuous-time quantum walks and computational complexity theory and it indicates a family of tasks that could ultimately demonstrate quantum supremacy over classical computers. As a proof of principle, we experimentally implement the proposed quantum circuit on an example circulant graph using a two-qubit photonics quantum processor.

  2. Face feature processor on mobile service robot

    Science.gov (United States)

    Ahn, Ho Seok; Park, Myoung Soo; Na, Jin Hee; Choi, Jin Young

    2005-12-01

    In recent years, many mobile service robots have been developed. These robots are different from industrial robots. Service robots were confronted to unexpected changes in the human environment. So many capabilities were needed to service mobile robot, for example, the capability to recognize people's face and voice, the capability to understand people's conversation, and the capability to express the robot's thinking etc. This research considered face detection, face tracking and face recognition from continuous camera image. For face detection module, it used CBCH algorithm using openCV library from Intel Corporation. For face tracking module, it used the fuzzy controller to control the pan-tilt camera movement smoothly with face detection result. A PCA-FX, which adds class information to PCA, was used for face recognition module. These three procedures were called face feature processor, which were implemented on mobile service robot OMR to verify.

  3. Efficient quantum walk on a quantum processor.

    Science.gov (United States)

    Qiang, Xiaogang; Loke, Thomas; Montanaro, Ashley; Aungskunsiri, Kanin; Zhou, Xiaoqi; O'Brien, Jeremy L; Wang, Jingbo B; Matthews, Jonathan C F

    2016-01-01

    The random walk formalism is used across a wide range of applications, from modelling share prices to predicting population genetics. Likewise, quantum walks have shown much potential as a framework for developing new quantum algorithms. Here we present explicit efficient quantum circuits for implementing continuous-time quantum walks on the circulant class of graphs. These circuits allow us to sample from the output probability distributions of quantum walks on circulant graphs efficiently. We also show that solving the same sampling problem for arbitrary circulant quantum circuits is intractable for a classical computer, assuming conjectures from computational complexity theory. This is a new link between continuous-time quantum walks and computational complexity theory and it indicates a family of tasks that could ultimately demonstrate quantum supremacy over classical computers. As a proof of principle, we experimentally implement the proposed quantum circuit on an example circulant graph using a two-qubit photonics quantum processor. PMID:27146471

  4. Automated Sequence Processor: Something Old, Something New

    Science.gov (United States)

    Streiffert, Barbara; Schrock, Mitchell; Fisher, Forest; Himes, Terry

    2012-01-01

    High productivity required for operations teams to meet schedules Risk must be minimized. Scripting used to automate processes. Scripts perform essential operations functions. Automated Sequence Processor (ASP) was a grass-roots task built to automate the command uplink process System engineering task for ASP revitalization organized. ASP is a set of approximately 200 scripts written in Perl, C Shell, AWK and other scripting languages.. ASP processes/checks/packages non-interactive commands automatically.. Non-interactive commands are guaranteed to be safe and have been checked by hardware or software simulators.. ASP checks that commands are non-interactive.. ASP processes the commands through a command. simulator and then packages them if there are no errors.. ASP must be active 24 hours/day, 7 days/week..

  5. Hash sorter - firmware implementation and an application for the Fermilab BTeV level 1 trigger system

    Energy Technology Data Exchange (ETDEWEB)

    Jinyuan Wu et al.

    2003-11-05

    A hardware hash sorter for the Fermilab BTeV Level 1 trigger system will be presented. The has sorter examines track-segment data before the data are sent to a system comprised of 2500 Level 1 processors, and rearranges the data into bins based on the slope of track segments. They have found that by using the rearranged data, processing time is significantly reduced allowing the total number of processors required for the Level 1 trigger system to be reduced. The hash sorter can be implemented in an FPGA that is already included as part of the design of the trigger system. Hash sorting has potential applications in a broad area in trigger and DAQ systems. It is a simple O(n) process and is suitable for FPGA implementation. Several implementation strategies will also be discussed in this document.

  6. Designing a dataflow processor using CλaSH

    NARCIS (Netherlands)

    Niedermeier, Anja; Wester, Rinse; Rovers, Kenneth; Baaij, Christiaan; Kuper, Jan; Smit, Gerard

    2010-01-01

    In this paper we show how a simple dataflow processor can be fully implemented using CλaSH, a high level HDL based on the functional programming language Haskell. The processor was described using Haskell, the CλaSH compiler was then used to translate the design into a fully synthesisable VHDL code.

  7. Temporal Partitioning and Multi-Processor Scheduling for Reconfigurable Architectures

    DEFF Research Database (Denmark)

    Popp, Andreas; Le Moullec, Yannick; Koch, Peter

    This poster presentation outlines a proposed framework for handling mapping of signal processing applications to heterogeneous reconfigurable architectures. The methodology consists of an extension to traditional multi-processor scheduling by creating a separate HW track for generation of groups of...... tasks that are handled similarly to SW processes in a traditional multi-processor scheduling context....

  8. Extended VLIW processor for real-time imaging

    Science.gov (United States)

    Sakai, Keiichi; Fujiwara, Itaru; Ae, Tadashi

    2001-04-01

    We propose EVLIW as a new processor architecture which is designed for general purpose processing and is suitable especially for real-time image processing. The processor architecture is a VLIW, but it has more functional units than the generic VLIW processor has. The EVLIW consists of the interconnection network for connecting the neighbor and of functional units, which are more primitive than in the generic VLIW processor. Some of general-purpose processors in the market includes several processing units, e.g. the same four single precision floating-point or four 16bit-word integer units for Intel processor with SSE/MMX, where the four units do the same operation with the four different data. In the image processing, the data are processed in parallel, where the operating is not complicated an only the high-speed processing is usually required. We have tried a simple image processing using Intel's processor with SSE/MMX and summarize the results. In this paper, we describe a new architecture for real-time imaging, and its design, comparing with Intel's processor with SSE/MMX.

  9. Digital Signal Processor System for AC Power Drivers

    Directory of Open Access Journals (Sweden)

    Ovidiu Neamtu

    2009-10-01

    Full Text Available DSP (Digital Signal Processor is the bestsolution for motor control systems to make possible thedevelopment of advanced motor drive systems. The motorcontrol processor calculates the required motor windingvoltage magnitude and frequency to operate the motor atthe desired speed. A PWM (Pulse Width Modulationcircuit controls the on and off duty cycle of the powerinverter switches to vary the magnitude of the motorvoltages.

  10. 7 CFR 1435.310 - Sharing processors' allocations with producers.

    Science.gov (United States)

    2010-01-01

    ... processors upon their request for growers delivering to their mill. In the case of multiple producers on a... subject to appeal to the Office of the Administrative Law Judge, USDA. ... proportionate share data. (e) Any producer or processor may request arbitration of a dispute regarding...

  11. A Simple and Affordable TTL Processor for the Classroom

    Science.gov (United States)

    Feinberg, Dave

    2007-01-01

    This paper presents a simple 4 bit computer processor design that may be built using TTL chips for less than $65. In addition to describing the processor itself in detail, we discuss our experience using the laboratory kit and its associated machine instruction set to teach computer architecture to high school students. (Contains 3 figures and 5…

  12. Soft-core processor study for node-based architectures.

    Energy Technology Data Exchange (ETDEWEB)

    Van Houten, Jonathan Roger; Jarosz, Jason P.; Welch, Benjamin James; Gallegos, Daniel E.; Learn, Mark Walter

    2008-09-01

    Node-based architecture (NBA) designs for future satellite projects hold the promise of decreasing system development time and costs, size, weight, and power and positioning the laboratory to address other emerging mission opportunities quickly. Reconfigurable Field Programmable Gate Array (FPGA) based modules will comprise the core of several of the NBA nodes. Microprocessing capabilities will be necessary with varying degrees of mission-specific performance requirements on these nodes. To enable the flexibility of these reconfigurable nodes, it is advantageous to incorporate the microprocessor into the FPGA itself, either as a hardcore processor built into the FPGA or as a soft-core processor built out of FPGA elements. This document describes the evaluation of three reconfigurable FPGA based processors for use in future NBA systems--two soft cores (MicroBlaze and non-fault-tolerant LEON) and one hard core (PowerPC 405). Two standard performance benchmark applications were developed for each processor. The first, Dhrystone, is a fixed-point operation metric. The second, Whetstone, is a floating-point operation metric. Several trials were run at varying code locations, loop counts, processor speeds, and cache configurations. FPGA resource utilization was recorded for each configuration. Cache configurations impacted the results greatly; for optimal processor efficiency it is necessary to enable caches on the processors. Processor caches carry a penalty; cache error mitigation is necessary when operating in a radiation environment.

  13. Digital image processing software system using an array processor

    International Nuclear Information System (INIS)

    A versatile array processor-based system for general-purpose image processing was developed. At the heart of this system is an extensive, flexible software package that incorporates the array processor for effective interactive image processing. The software system is described in detail, and its application to a diverse set of applications at LLNL is briefly discussed. 4 figures, 1 table

  14. Evaluation of the Intel Sandy Bridge-EP server processor

    CERN Document Server

    Jarp, S; Leduc, J; Nowak, A; CERN. Geneva. IT Department

    2012-01-01

    In this paper we report on a set of benchmark results recently obtained by CERN openlab when comparing an 8-core “Sandy Bridge-EP” processor with Intel’s previous microarchitecture, the “Westmere-EP”. The Intel marketing names for these processors are “Xeon E5-2600 processor series” and “Xeon 5600 processor series”, respectively. Both processors are produced in a 32nm process, and both platforms are dual-socket servers. Multiple benchmarks were used to get a good understanding of the performance of the new processor. We used both industry-standard benchmarks, such as SPEC2006, and specific High Energy Physics benchmarks, representing both simulation of physics detectors and data analysis of physics events. Before summarizing the results we must stress the fact that benchmarking of modern processors is a very complex affair. One has to control (at least) the following features: processor frequency, overclocking via Turbo mode, the number of physical cores in use, the use of logical cores ...

  15. Conversion via software of a simd processor into a mimd processor

    Energy Technology Data Exchange (ETDEWEB)

    Guzman, A.; Gerzso, M.; Norkin, K.B.; Vilenkin, S.Y.

    1983-01-01

    A method is described which takes a pure LISP program and automatically decomposes it via automatic parallelization into several parts, one for each processor of an SIMD architecture. Each of these parts is a different execution flow, i.e., a different program. The execution of these different programs by an SIMD architecture is examined. The method has been developed in some detail for the PS-2000, an SIMD Soviet multiprocessor, making it behave like AHR, a Mexican MIMD multi-microprocessor. Both the PS-2000 and AHR execute a pure LISP program in parallel; its decomposition into >n> pieces, their synchronization, scheduling, etc., are performed by the system (hardware and software). In order to achieve simultaneous execution of different programs in an SIMD processor, the method uses a scheme of node scheduling and node exportation. 14 references.

  16. Burst Memory and Event Trigger System for the Magnetospheric Multiscale Mission

    Science.gov (United States)

    Kletzing, C. A.; Ergun, R. E.; Torbert, R. B.; Burch, J. L.; Bounds, S. R.; Hesse, M.; Mauk, B.; Moore, T. E.; Young, D. T.

    2005-12-01

    To achieve the highest resolution measurement of the physics of magnetic reconnection, the MMS SMART measurements will utilize a high data rate burst storage system for capturing those intervals when the MMS spacecraft traverse important regions of interest. Two basic modes of data taking are planned, Slow Survey and Fast Survey. Fast Survey mode is targeted at the broad regions of the magnetosphere where reconnection can occur. Slow Survey is aimed an regions of secondary science importance. In Fast Survey, all instruments in the SMART suite continually send high rate data to the Central Instrument Data Processor (CIDP) which holds this data in a circular buffer. Along with this data, each instrument sends a burst data quality (BDQ) flag which represents the scientific "quality" of the preceding period for consideration as a burst interval. The CIDP on each spacecraft collects the individual BDQ's and combines them via a predetermined algorithm into a spacecraft data quality (SDQ) flag. Each spacecraft then sends its individual SDQ to the other three spacecraft via the Interspacecraft Ranging and Alarm System (IRAS). After a short latency period all four spacecraft have all four SDQ values and compute a mission data quality (MDQ) flag. If this flag is above the appropriate threshold then all spacecraft save identical data intervals from from the circular buffer for transmission to the ground during the next downlink. If This flexible scheme will yield optimized science data collection and allows the evolution of the burst data criteria as the best burst triggers are identified.

  17. Disambiguating Syntactic Triggers

    Science.gov (United States)

    Sakas, William Gregory; Fodor, Janet Dean

    2012-01-01

    We present data from an artificial language domain that suggest new contributions to the theory of syntactic triggers. Whether a learning algorithm is capable of matching the achievements of child learners depends in part on how much parametric ambiguity there is in the input. For practical reasons this cannot be established for the domain of all…

  18. Common Asthma Triggers

    Science.gov (United States)

    ... air pollution can trigger an asthma attack. This pollution can come from factories, cars, and other sources. Pay attention to air quality forecasts on radio, television, and the Internet and check your newspaper to plan ... levels will be low. Cockroach Allergen Cockroaches and ...

  19. The ALFA Trigger Simulator

    CERN Document Server

    Dziedzic B

    2015-01-01

    The paper presents basic information about ALFA detectors used in the ATLAS experiment, and the structure of currently developed device used to test a new ALFA trigger interface. It discusses the block diagram of the device, principle of its operation, implementation details and future plans for developing the Simulator.

  20. PERFORMANCE EVALUATION OF DIRECT PROCESSOR ACCESS FOR NON DEDICATED SERVER

    Directory of Open Access Journals (Sweden)

    P. S. BALAMURUGAN

    2010-10-01

    Full Text Available The objective of the paper is to design a co processor for a desktop machine which enables the machine to act as non dedicated server, such that the co processor will act as a server processor and the multi-core processor to act as desktop processor. By implementing this methodology a client machine can be made to act as a non dedicated server and a client machine. These type of machine can be used in autonomy networks. This design will lead to design of a cost effective server and machine which can parallel act as a non dedicated server and a client machine or it can be made to switch and act as client or server.

  1. APRON: A Cellular Processor Array Simulation and Hardware Design Tool

    Directory of Open Access Journals (Sweden)

    David R. W. Barr

    2009-01-01

    Full Text Available We present a software environment for the efficient simulation of cellular processor arrays (CPAs. This software (APRON is used to explore algorithms that are designed for massively parallel fine-grained processor arrays, topographic multilayer neural networks, vision chips with SIMD processor arrays, and related architectures. The software uses a highly optimised core combined with a flexible compiler to provide the user with tools for the design of new processor array hardware architectures and the emulation of existing devices. We present performance benchmarks for the software processor array implemented on standard commodity microprocessors. APRON can be configured to use additional processing hardware if necessary and can be used as a complete graphical user interface and development environment for new or existing CPA systems, allowing more users to develop algorithms for CPA systems.

  2. Explore the Performance of the ARM Processor Using JPEG

    Directory of Open Access Journals (Sweden)

    A.D. Jadhav

    2010-01-01

    Full Text Available Recently, the evolution of embedded systems has shown a strong trend towards application- specific, single- chip solutions. The ARM processor core is a leading RISC processor architecture in the embedded domain. The ARM family of processors supports a unique feature of code size reduction. In this paper it is illustrated using an embedded platform trying to design an image encoder, more specifically a JPEG encoder using ARM7TDMI processor. Here gray scale image is used and it is coded by using keil software and same procedure is repeated by using MATLAB software for compare the results with standard one. Successfully putting a new application of JPEG on ARM7 processor.

  3. Launching applications on compute and service processors running under different operating systems in scalable network of processor boards with routers

    Science.gov (United States)

    Tomkins, James L.; Camp, William J.

    2009-03-17

    A multiple processor computing apparatus includes a physical interconnect structure that is flexibly configurable to support selective segregation of classified and unclassified users. The physical interconnect structure also permits easy physical scalability of the computing apparatus. The computing apparatus can include an emulator which permits applications from the same job to be launched on processors that use different operating systems.

  4. A time-multiplexed track-trigger for the CMS HL-LHC upgrade

    Science.gov (United States)

    Hall, G.

    2016-07-01

    A new CMS Tracker is under development for operation at the High Luminosity LHC from 2025. It includes an outer tracker based on special modules of two different types which will construct track stubs using spatially coincident clusters in two closely spaced sensor layers, to reject low transverse momentum track hits and reduce the data volume before data transmission to the Level-1 trigger. The tracker data will be used to reconstruct track segments in dedicated processors before onward transmission to other trigger processors which will combine tracker information with data originating from the calorimeter and muon detectors, to make the final L1 trigger decision. The architecture for processing the tracker data outside the detector is under study, using several alternative approaches. One attractive possibility is to exploit a Time Multiplexed design similar to the one which is currently being implemented in the CMS calorimeter trigger as part of the Phase I trigger upgrade. The novel Time Multiplexed Trigger concept is explained, the potential benefits for processing future tracker data are described and a feasible design based on currently existing hardware is outlined.

  5. Optically triggered infrared photodetector.

    Science.gov (United States)

    Ramiro, Íñigo; Martí, Antonio; Antolín, Elisa; López, Esther; Datas, Alejandro; Luque, Antonio; Ripalda, José M; González, Yolanda

    2015-01-14

    We demonstrate a new class of semiconductor device: the optically triggered infrared photodetector (OTIP). This photodetector is based on a new physical principle that allows the detection of infrared light to be switched ON and OFF by means of an external light. Our experimental device, fabricated using InAs/AlGaAs quantum-dot technology, demonstrates normal incidence infrared detection in the 2-6 μm range. The detection is optically triggered by a 590 nm light-emitting diode. Furthermore, the detection gain is achieved in our device without an increase of the noise level. The novel characteristics of OTIPs open up new possibilities for third generation infrared imaging systems ( Rogalski, A.; Antoszewski, J.; Faraone, L. J. Appl. Phys. 2009, 105 (9), 091101).

  6. Testing and calibrating analogue inputs to the ATLAS Level-1 Calorimeter Trigger

    CERN Document Server

    Achenbach, R; Aharrouche, M; Andrei, V; Åsman, B; Barnett, B M; Bauss, B; Bendel, M; Bohm, C; Booth, J R A; Bracinik, J; Brawn, I P; Charlton, D G; Childers, J T; Collins, N J; Curtis, C J; Davis, A O; Eckweiler, S; Eisenhandler, E F; Faulkner, P J W; Fleckner, J; Föhlisch, F; Gee, C N P; Gillman, A R; Goringer, C; Groll, M; Hadley, D R; Hanke, P; Hellman, S; Hidvegi, A; Hillier, S J; Johansen, M; Kluge, E E; Kühl, T; Landon, M; Lendermann, V; Lilley, J N; Mahboubi, K; Mahout, G; Meier, K; Middleton, R P; Moa, T; Morris, J D; Müller, F; Neusiedl, A; Ohm, C; Oltmann, B; Perera, V J O; Prieur, D P F; Qian, W; Rieke, S; Rühr, F; Sankey, D P C; Schäfer, U; Schmitt, K; Schultz-Coulon, H C; Seidler, P; Silverstein, S; Sjölin, J; Staley, R J; Stamen, R; Stockton, M C; Tan, C L A; Tapprogge, S; Thomas, J P; Thompson, P D; Watkins, P M; Watson, A; Weber, P; Wessels, M; Wildt, M

    2008-01-01

    The ATLAS Level-1 Calorimeter Trigger is a hardwarebased system which aims to identify objects with high transverse momentum within an overall latency of 2.5 μs. It is composed of a PreProcessor system (PPr) which digitises 7200 analogue input channels, determines the bunch crossing of the interaction, applies a digital noise filter, and provides a fine calibration; and two subsequent digital processors. The PreProcessor system needs various channel dependent parameters to be set in order to provide digital signals which are aligned in time and have proper energy calibration. The different techniques which are used to derive these parameters are described along with the quality tests of the analogue input signals.

  7. Dry needling - peripheral and central considerations.

    Science.gov (United States)

    Dommerholt, Jan

    2011-11-01

    Dry needling is a common treatment technique in orthopedic manual physical therapy. Although various dry needling approaches exist, the more common and best supported approach targets myofascial trigger points. This article aims to place trigger point dry needling within the context of pain sciences. From a pain science perspective, trigger points are constant sources of peripheral nociceptive input leading to peripheral and central sensitization. Dry needling cannot only reverse some aspects of central sensitization, it reduces local and referred pain, improves range of motion and muscle activation pattern, and alters the chemical environment of trigger points. Trigger point dry needling should be based on a thorough understanding of the scientific background of trigger points, the differences and similarities between active and latent trigger points, motor adaptation, and central sensitize application. Several outcome studies are included, as well as comments on dry needling and acupuncture.

  8. Trigger and data acquisition

    CERN Document Server

    Ellis, Nick

    2010-01-01

    The lectures address some of the issues of triggering and data acquisition in large high-energy physics experiments. Emphasis is placed on hadron-collider experiments that present a particularly challenging environment for event selection and data collection. However, the lectures also explain how T/DAQ systems have evolved over the years to meet new challenges. Some examples are given from early experience with LHC T/DAQ systems during the 2008 single-beam operations.

  9. Neural networks for triggering

    Energy Technology Data Exchange (ETDEWEB)

    Denby, B. (Fermi National Accelerator Lab., Batavia, IL (USA)); Campbell, M. (Michigan Univ., Ann Arbor, MI (USA)); Bedeschi, F. (Istituto Nazionale di Fisica Nucleare, Pisa (Italy)); Chriss, N.; Bowers, C. (Chicago Univ., IL (USA)); Nesti, F. (Scuola Normale Superiore, Pisa (Italy))

    1990-01-01

    Two types of neural network beauty trigger architectures, based on identification of electrons in jets and recognition of secondary vertices, have been simulated in the environment of the Fermilab CDF experiment. The efficiencies for B's and rejection of background obtained are encouraging. If hardware tests are successful, the electron identification architecture will be tested in the 1991 run of CDF. 10 refs., 5 figs., 1 tab.

  10. Patient triggered ventilation using a flow triggered system.

    OpenAIRE

    Hird, M F; Greenough, A

    1991-01-01

    The role of patient triggered ventilation (PTV) for the newborn was assessed using a new patient triggered ventilator, the Draeger Bablylog 8000, which incorporates significant improvements in both ventilator performance and the triggering system. Thirty three infants, median gestational age 30 weeks and postnatal age 2.5 days, were entered into the study to compare blood gases obtained during conventional and patient triggered ventilation. Oxygenation did not improve with PTV in the group ov...

  11. Factors Affecting Women’s Capacities as Traditional Sago Starch Processors in Maluku, Indonesia

    Directory of Open Access Journals (Sweden)

    Inta P.N. Damanik

    2013-04-01

    Full Text Available The objectives of this research were to describe the capacity level of women as traditional sago starch processors and to analyze factors which affected women’s capacity in processing sago starch as traditional home industry. Research was conduct in the Districts of Central Maluku and West Seram involved 204 households of sago starch processing as respondents which determined from population (416 households by Slovin formula with degree of error 5% and drawn by simple random sampling method. Data collection was undertaken in January until April 2012. Data were analyzed using Statistical Package for the Social Science (SPSS v.20. Result showed that characteristics of social economic of traditional sago starch processor (namely age, length of time in business, informal education, motivation, family size, and individual beliefs about the social and cultural values of sago and support from institution of agriculture extension affected personal capacity. Personal capacity affected business capacity and in the next term business capacity affected productivity. Increasing productivity will increase income. This means that the sago starch processors with higher personal capacity will do better in business.

  12. Resource efficiency of hardware extensions of a 4-issue VLIW processor for elliptic curve cryptography

    Science.gov (United States)

    Jungeblut, T.; Puttmann, C.; Dreesen, R.; Porrmann, M.; Thies, M.; Rückert, U.; Kastens, U.

    2010-12-01

    The secure transmission of data plays a significant role in today's information era. Especially in the area of public-key-cryptography methods, which are based on elliptic curves (ECC), gain more and more importance. Compared to asymmetric algorithms, like RSA, ECC can be used with shorter key lengths, while achieving an equal level of security. The performance of ECC-algorithms can be increased significantly by adding application specific hardware extensions. Due to their fine grained parallelism, VLIW-processors are well suited for the execution of ECC algorithms. In this work, we extended the fourfold parallel CoreVA-VLIW-architecture by several hardware accelerators to increase the resource efficiency of the overall system. For the design-space exploration we use a dual design flow, which is based on the automatic generation of a complete C-compiler based tool chain from a central processor specification. Using the hardware accelerators the performance of the scalar multiplication on binary fields can be increased by the factor of 29. The energy consumption can be reduced by up to 90%. The extended processor hardware was mapped on a current 65 nm low-power standard-cell-technology. The chip area of the CoreVA-VLIW-architecture is 0.24 mm2 at a power consumption of 29 mW/MHz. The performance gain is analyzed in respect to the increased hardware costs, as chip area or power consumption.

  13. A trigger for beauty

    International Nuclear Information System (INIS)

    The possibility of B-meson experiments, in a fixed-target high-energy proton machine (Tevatron) is discussed. Compared to a B-meson factory experiment, it can produce 105, Banti B's per hour, using 108 protons per second, but it suffers from high background and needs high selectivity to cope with the million times higher interaction rate. To overcome these difficulties a technique called the 'optical trigger for beauty' is proposed, based on the detection of Cherenkov photons produced in a 2 mm thick LiF crystal, through a fast photodetector. Its virtue is that it is opaque to minimum-bias events originating in a small target, but sensitive to the high impact parameter B-meson decay charged particles from a secondary vertex. Calculations and first simulations results give a good efficiency for B-meson detection. A multistep trigger, combining the 'optical trigger' and a tracking detector, allows significant selection and a consequent enrichment of the data sample. Taking into account its fast response (∝ 1 ns), the above considerations can be extended to other hadronic machines, especially those with high-rate environments such as the LHC or SSC. (orig.)

  14. Slime mould processors, logic gates and sensors.

    Science.gov (United States)

    Adamatzky, A

    2015-07-28

    A heterotic, or hybrid, computation implies that two or more substrates of different physical nature are merged into a single device with indistinguishable parts. These hybrid devices then undertake coherent acts on programmable and sensible processing of information. We study the potential of heterotic computers using slime mould acting under the guidance of chemical, mechanical and optical stimuli. Plasmodium of acellular slime mould Physarum polycephalum is a gigantic single cell visible to the unaided eye. The cell shows a rich spectrum of behavioural morphological patterns in response to changing environmental conditions. Given data represented by chemical or physical stimuli, we can employ and modify the behaviour of the slime mould to make it solve a range of computing and sensing tasks. We overview results of laboratory experimental studies on prototyping of the slime mould morphological processors for approximation of Voronoi diagrams, planar shapes and solving mazes, and discuss logic gates implemented via collision of active growing zones and tactile responses of P. polycephalum. We also overview a range of electronic components--memristor, chemical, tactile and colour sensors-made of the slime mould. PMID:26078344

  15. Scientific Computing Kernels on the Cell Processor

    Energy Technology Data Exchange (ETDEWEB)

    Williams, Samuel W.; Shalf, John; Oliker, Leonid; Kamil, Shoaib; Husbands, Parry; Yelick, Katherine

    2007-04-04

    The slowing pace of commodity microprocessor performance improvements combined with ever-increasing chip power demands has become of utmost concern to computational scientists. As a result, the high performance computing community is examining alternative architectures that address the limitations of modern cache-based designs. In this work, we examine the potential of using the recently-released STI Cell processor as a building block for future high-end computing systems. Our work contains several novel contributions. First, we introduce a performance model for Cell and apply it to several key scientific computing kernels: dense matrix multiply, sparse matrix vector multiply, stencil computations, and 1D/2D FFTs. The difficulty of programming Cell, which requires assembly level intrinsics for the best performance, makes this model useful as an initial step in algorithm design and evaluation. Next, we validate the accuracy of our model by comparing results against published hardware results, as well as our own implementations on a 3.2GHz Cell blade. Additionally, we compare Cell performance to benchmarks run on leading superscalar (AMD Opteron), VLIW (Intel Itanium2), and vector (Cray X1E) architectures. Our work also explores several different mappings of the kernels and demonstrates a simple and effective programming model for Cell's unique architecture. Finally, we propose modest microarchitectural modifications that could significantly increase the efficiency of double-precision calculations. Overall results demonstrate the tremendous potential of the Cell architecture for scientific computations in terms of both raw performance and power efficiency.

  16. Simultaneous multithreaded processor enhanced for multimedia applications

    Science.gov (United States)

    Mombers, Friederich; Thomas, Michel

    1999-12-01

    The paper proposes a new media processor architecture specifically designed to handle state-of-the-art multimedia encoding and decoding tasks. To achieve this, the architecture efficiently exploit Data-, Instruction- and Thread-Level parallelisms while continuously adapting its computational resources to reach the most appropriate parallelism level among all the concurrent encoding/decoding processes. Looking at the implementation constraints, several critical choices were adopted that solve the interconnection delay problem, lower the cache misses and pipeline stalls effects and reduce register files and memory size by adopting a clustered Simultaneous Multithreaded Architecture. We enhanced the classic model to exploit both Instruction and Data Level Parallelism through vector instructions. The vector extension is well justified for multimedia workload and improves code density, crossbars complexity, register file ports and decoding logic area while it still provides an efficient way to fully exploit a large set of functional units. An MPEG-2 encoding algorithms based on Hybrid Genetic search has been implemented that show the efficiency of the architecture to adapt its resources allocation to better fulfill the application requirements.

  17. Study of a hybrid multispectral processor

    Science.gov (United States)

    Marshall, R. E.; Kriegler, F. J.

    1973-01-01

    A hybrid processor is described offering enough handling capacity and speed to process efficiently the large quantities of multispectral data that can be gathered by scanner systems such as MSDS, SKYLAB, ERTS, and ERIM M-7. Combinations of general-purpose and special-purpose hybrid computers were examined to include both analog and digital types as well as all-digital configurations. The current trend toward lower costs for medium-scale digital circuitry suggests that the all-digital approach may offer the better solution within the time frame of the next few years. The study recommends and defines such a hybrid digital computing system in which both special-purpose and general-purpose digital computers would be employed. The tasks of recognizing surface objects would be performed in a parallel, pipeline digital system while the tasks of control and monitoring would be handled by a medium-scale minicomputer system. A program to design and construct a small, prototype, all-digital system has been started.

  18. A CNN-Specific Integrated Processor

    Directory of Open Access Journals (Sweden)

    Suleyman Malki

    2009-01-01

    Full Text Available Integrated Processors (IP are algorithm-specific cores that either by programming or by configuration can be re-used within many microelectronic systems. This paper looks at Cellular Neural Networks (CNN to become realized as IP. First current digital implementations are reviewed, and the memoryprocessor bandwidth issues are analyzed. Then a generic view is taken on the structure of the network, and a new intra-communication protocol based on rotating wheels is proposed. It is shown that this provides for guaranteed high-performance with a minimal network interface. The resulting node is small and supports multi-level CNN designs, giving the system a 30-fold increase in capacity compared to classical designs. As it facilitates multiple operations on a single image, and single operations on multiple images, with minimal access to the external image memory, balancing the internal and external data transfer requirements optimizes the system operation. In conventional digital CNN designs, the treatment of boundary nodes requires additional logic to handle the CNN value propagation scheme. In the new architecture, only a slight modification of the existing cells is necessary to model the boundary effect. A typical prototype for visual pattern recognition will house 4096 CNN cells with a 2% overhead for making it an IP.

  19. Project Report: Automatic Sequence Processor Software Analysis

    Science.gov (United States)

    Benjamin, Brandon

    2011-01-01

    The Mission Planning and Sequencing (MPS) element of Multi-Mission Ground System and Services (MGSS) provides space missions with multi-purpose software to plan spacecraft activities, sequence spacecraft commands, and then integrate these products and execute them on spacecraft. Jet Propulsion Laboratory (JPL) is currently is flying many missions. The processes for building, integrating, and testing the multi-mission uplink software need to be improved to meet the needs of the missions and the operations teams that command the spacecraft. The Multi-Mission Sequencing Team is responsible for collecting and processing the observations, experiments and engineering activities that are to be performed on a selected spacecraft. The collection of these activities is called a sequence and ultimately a sequence becomes a sequence of spacecraft commands. The operations teams check the sequence to make sure that no constraints are violated. The workflow process involves sending a program start command, which activates the Automatic Sequence Processor (ASP). The ASP is currently a file-based system that is comprised of scripts written in perl, c-shell and awk. Once this start process is complete, the system checks for errors and aborts if there are any; otherwise the system converts the commands to binary, and then sends the resultant information to be radiated to the spacecraft.

  20. Element Load Data Processor (ELDAP) Users Manual

    Science.gov (United States)

    Ramsey, John K., Jr.; Ramsey, John K., Sr.

    2015-01-01

    Often, the shear and tensile forces and moments are extracted from finite element analyses to be used in off-line calculations for evaluating the integrity of structural connections involving bolts, rivets, and welds. Usually the maximum forces and moments are desired for use in the calculations. In situations where there are numerous structural connections of interest for numerous load cases, the effort in finding the true maximum force and/or moment combinations among all fasteners and welds and load cases becomes difficult. The Element Load Data Processor (ELDAP) software described herein makes this effort manageable. This software eliminates the possibility of overlooking the worst-case forces and moments that could result in erroneous positive margins of safety and/or selecting inconsistent combinations of forces and moments resulting in false negative margins of safety. In addition to forces and moments, any scalar quantity output in a PATRAN report file may be evaluated with this software. This software was originally written to fill an urgent need during the structural analysis of the Ares I-X Interstage segment. As such, this software was coded in a straightforward manner with no effort made to optimize or minimize code or to develop a graphical user interface.

  1. Food processors requirements met by radiation processing

    Science.gov (United States)

    Durante, Raymond W.

    2002-03-01

    Processing food using irradiation provides significant advantages to food producers by destroying harmful pathogens and extending shelf life without any detectable physical or chemical changes. It is expected that through increased public education, food irradiation will emerge as a viable commercial industry. Food production in most countries involves state of the art manufacturing, packaging, labeling, and shipping techniques that provides maximum efficiency and profit. In the United States, food sales are extremely competitive and profit margins small. Most food producers have heavily invested in equipment and are hesitant to modify their equipment. Meat and poultry producers in particular utilize sophisticated production machinery that processes enormous volumes of product on a continuous basis. It is incumbent on the food irradiation equipment suppliers to develop equipment that can easily merge with existing processes without requiring major changes to either the final food product or the process utilized to produce that product. Before a food producer can include irradiation as part of their food production process, they must be certain the available equipment meets their needs. This paper will examine several major requirements of food processors that will most likely have to be provided by the supplier of the irradiation equipment.

  2. Disaster triggers disaster: Earthquake triggering by tropical cyclones

    Science.gov (United States)

    Wdowinski, S.; Tsukanov, I.

    2011-12-01

    Three recent devastating earthquakes, the 1999 M=7.6 Chi-Chi (Taiwan), 2010 M=7.0 Leogane (Haiti), 2010 M=6.4 Kaohsiung (Taiwan), and additional three moderate size earthquakes (6hurricane or typhoon) hit the very same area. The most familiar example is Haiti, which was hit during the late summer of 2008 by two hurricanes and two tropical storms (Fay, Gustav, Hanna and Ike) within 25 days. A year an a half after this very wet hurricane season, the 2010 Leogane earthquake occurred in the mountainous Haiti's southern peninsula and caused the death of more than 300,000 people. The other cases are from Taiwan, which is characterized by a high seismicity level and frequent typhoon landfall. The three wettest typhoons in Taiwan's past 50 years were Morakot (in 2009, with 2885 mm or rain), Flossie (1969, 2162 mm) and Herb (1996, 1987 mm)[Lin et al., 2010]. Each of this three very wet storms was followed by one or two main-shock M>6 earthquake that occurred in the central mountainous area of Taiwan within three years after the typhoon. The 2009 Morakot typhoon was followed by 2009 M=6.2 Nantou and 2010 M=6.4 Kaohsiung earthquakes; the 1969 Flossie typhoon was followed by an M=6.3 earthquake in 1972; and the 1996 Herb typhoon by the 1998 M=6.2 Rueyli and 1999 M=7.6 Chi-Chi earthquakes. The earthquake catalog of Taiwan lists only two other M>6 main-shocks that occurred in Taiwan's central mountainous belt, one of them was in 1964 only four months after the wet Typhoon Gloria poured heavy rain in the same area. We suggest that the close proximity in time and space between wet tropical cyclones and earthquakes reflects a physical link between the two hazard types in which these earthquakes were triggered by rapid erosion induced by tropical cyclone's heavy rain. Based on remote sensing observations, meshfree finite element modeling, and Coulomb failure stress analysis, we show that the erosion induced by very wet cyclones increased the failure stresses at the hypocenters

  3. Extensible circuit QED processor architecture with vertical I/O

    Science.gov (United States)

    Bruno, Alessandro; Poletto, Stefano; Haider, Nadia; Dicarlo, Leonardo

    Achieving quantum fault tolerance in an extensible architecture is an outstanding challenge across experimental quantum computing platforms today. Traditionally, circuit QED processors have millimeter dimensions and lateral coupling for all input/output (I/O) signals, precluding the increase in qubit numbers beyond ~10. We present a scalable footprint for circuit QED processors with vertically coupled I/O. Our demonstration using centimeter scale chips can accommodate the ~50 qubits needed in next-generation processors targeting the experimental demonstration of quantum fault tolerance. We acknowledge funding from FOM, NWO and the EU FP7 Project SCALEQIT.

  4. Batch arrival M/G/1 Processor Sharing with application to Multilevel Processor Sharing scheduling

    OpenAIRE

    Avrachenkov, Konstantin; Ayesta, Urtzi; Brown, Patrick

    2003-01-01

    We analyze an M/G/1 Processor-Sharing queue with Batch arrivals. Our analysis is based on the integral equation derived by Kleinrock, Muntz and Rodemich. Using the contraction mapping principle, we demonstrate the existence and uniqueness of a solution to the integral equation. Then we provide asymptotical analysis as well as tight bounds for the expected response time conditioned on the job size. In particular, the asymptotics for large size jobs depends only on the first moment of the job s...

  5. Contribution to the elaboration and implementation of LEP-L3 second level microcoded Trigger

    International Nuclear Information System (INIS)

    This thesis is devoted to the elaboration of the L3 second level trigger which is based on the dedicated programmable XOP processor. This system will reduce the trigger rate by a factor of ten and will ensure that the hardwired level-one processors function correctly. The present document describes all developments that L.A.P.P. is engaged in from the system design up to the complete experimental set up, especially: - The hardware development of the fast input memories as well as the FASTBUS interface unit which allows the microprocessor XOP to run as a performant FASTBUS Master, - the associated software developments, - the implementation of a VME test system dedicated to all control tasks

  6. Architecture and Design of Medical Processor Units for Medical Networks

    CERN Document Server

    Ahamed, Syed V; 10.5121/ijcnc.2010.2602

    2011-01-01

    This paper introduces analogical and deductive methodologies for the design medical processor units (MPUs). From the study of evolution of numerous earlier processors, we derive the basis for the architecture of MPUs. These specialized processors perform unique medical functions encoded as medical operational codes (mopcs). From a pragmatic perspective, MPUs function very close to CPUs. Both processors have unique operation codes that command the hardware to perform a distinct chain of subprocesses upon operands and generate a specific result unique to the opcode and the operand(s). In medical environments, MPU decodes the mopcs and executes a series of medical sub-processes and sends out secondary commands to the medical machine. Whereas operands in a typical computer system are numerical and logical entities, the operands in medical machine are objects such as such as patients, blood samples, tissues, operating rooms, medical staff, medical bills, patient payments, etc. We follow the functional overlap betw...

  7. On some parallel algorithms on a ring of processors

    Science.gov (United States)

    Sameh, A.

    1985-07-01

    In this paper we describe some linear algebra multiprocessor algorithms which are suitable for a ring of processors. These algorithms are organized in such a way as to be easily modified for general-purpose multiprocessors with shared global memories.

  8. A Shared Memory Module for Asynchronous Arrays of Processors

    Directory of Open Access Journals (Sweden)

    Meeuwsen MichaelJ

    2007-01-01

    Full Text Available A shared memory module connecting multiple independently clocked processors is presented. The memory module itself is independently clocked, supports hardware address generation, mutual exclusion, and multiple addressing modes. The architecture supports independent address generation and data generation/consumption by different processors which increases efficiency and simplifies programming for many embedded and DSP tasks. Simultaneous access by different processors is arbitrated using a least-recently-serviced priority scheme. Simulations show high throughputs over a variety of memory loads. A standard cell implementation shares an 8 K-word SRAM among four processors, and can support a 64 K-word SRAM with no additional changes. It cycles at 555 MHz and occupies 1.2 mm2 in 0.18 μm CMOS.

  9. Concept of a programmable maintenance processor applicable to multiprocessing systems

    Science.gov (United States)

    Glover, Richard D.

    1988-01-01

    A programmable maintenance processor concept applicable to multiprocessing systems has been developed at the NASA Ames Research Center's Dryden Flight Research Facility. This stand-alone-processor is intended to provide support for system and application software testing as well as hardware diagnostics. An initial machanization has been incorporated into the extended aircraft interrogation and display system (XAIDS) which is multiprocessing general-purpose ground support equipment. The XAIDS maintenance processor has independent terminal and printer interfaces and a dedicated magnetic bubble memory that stores system test sequences entered from the terminal. This report describes the hardware and software embodied in this processor and shows a typical application in the check-out of a new XAIDS.

  10. 2009 Survey of Gulf of Mexico Dockside Seafood Processors

    Data.gov (United States)

    National Oceanic and Atmospheric Administration, Department of Commerce — This survey gathered and analyze economic data from seafood processors throughout the states in the Gulf region. The survey sought to collect financial variables...

  11. Compiler for Fast, Accurate Mathematical Computing on Integer Processors Project

    Data.gov (United States)

    National Aeronautics and Space Administration — The proposers will develop a computer language compiler to enable inexpensive, low-power, integer-only processors to carry our mathematically-intensive...

  12. Reconfigurable VLIW Processor for Software Defined Radio Project

    Data.gov (United States)

    National Aeronautics and Space Administration — We will design and formally verify a VLIW processor that is radiation-hardened, and where the VLIW instructions consist of predicated RISC instructions from the...

  13. Assembly processor program converts symbolic programming language to machine language

    Science.gov (United States)

    Pelto, E. V.

    1967-01-01

    Assembly processor program converts symbolic programming language to machine language. This program translates symbolic codes into computer understandable instructions, assigns locations in storage for successive instructions, and computer locations from symbolic addresses.

  14. Pattern-Recognition Processor Using Holographic Photopolymer

    Science.gov (United States)

    Chao, Tien-Hsin; Cammack, Kevin

    2006-01-01

    proposed joint-transform optical correlator (JTOC) would be capable of operating as a real-time pattern-recognition processor. The key correlation-filter reading/writing medium of this JTOC would be an updateable holographic photopolymer. The high-resolution, high-speed characteristics of this photopolymer would enable pattern-recognition processing to occur at a speed three orders of magnitude greater than that of state-of-the-art digital pattern-recognition processors. There are many potential applications in biometric personal identification (e.g., using images of fingerprints and faces) and nondestructive industrial inspection. In order to appreciate the advantages of the proposed JTOC, it is necessary to understand the principle of operation of a conventional JTOC. In a conventional JTOC (shown in the upper part of the figure), a collimated laser beam passes through two side-by-side spatial light modulators (SLMs). One SLM displays a real-time input image to be recognized. The other SLM displays a reference image from a digital memory. A Fourier-transform lens is placed at its focal distance from the SLM plane, and a charge-coupled device (CCD) image detector is placed at the back focal plane of the lens for use as a square-law recorder. Processing takes place in two stages. In the first stage, the CCD records the interference pattern between the Fourier transforms of the input and reference images, and the pattern is then digitized and saved in a buffer memory. In the second stage, the reference SLM is turned off and the interference pattern is fed back to the input SLM. The interference pattern thus becomes Fourier-transformed, yielding at the CCD an image representing the joint-transform correlation between the input and reference images. This image contains a sharp correlation peak when the input and reference images are matched. The drawbacks of a conventional JTOC are the following: The CCD has low spatial resolution and is not an ideal square

  15. Biomolecular simulation on thousands of processors

    Science.gov (United States)

    Phillips, James Christopher

    Classical molecular dynamics simulation is a generally applicable method for the study of biomolecular aggregates of proteins, lipids, and nucleic acids. As experimental techniques have revealed the structures of larger and more complex biomolecular machines, the time required to complete even a single meaningful simulation of such systems has become prohibitive. We have developed the program NAMD to simulate systems of 50,000--500,000 atoms efficiently with full electrostatics on parallel computers with 1000 and more processors. NAMD's scalability is achieved through latency tolerant adaptive message-driven execution and measurement-based load balancing. NAMD is implemented in C++ and uses object-oriented design and threads to shield the basic algorithms from the necessary complexity of high-performance parallel execution. Apolipoprotein A-I is the primary protein constituent of high density lipoprotein particles, which transport cholesterol in the bloodstream. In collaboration with A. Jonas, we have constructed and simulated models of the nascent discoidal form of these particles, providing theoretical insight to the debate regarding the lipid-bound structure of the protein. Recently, S. Sligar and coworkers have created 10 nm phospholipid bilayer nanoparticles comprising a small lipid bilayer disk solubilized by synthetic membrane scaffold proteins derived from apolipoprotein A-I. Membrane proteins may be embedded in the water-soluble disks, with various medical and technological applications. We are working to develop variant scaffold proteins that produce disks of greater size, stability, and homogeneity. Our simulations have demonstrated a significant deviation from idealized cylindrical structure, and are being used in the interpretation of small angle x-ray scattering data.

  16. Triggering filamentation using turbulence

    CERN Document Server

    Eeltink, D; Marchiando, N; Hermelin, S; Gateau, J; Brunetti, M; Wolf, J P; Kasparian, J

    2016-01-01

    We study the triggering of single filaments due to turbulence in the beam path for a laser of power below the filamenting threshold. Turbulence can act as a switch between the beam not filamenting and producing single filaments. This 'positive' effect of turbulence on the filament probability, combined with our observation of off-axis filaments suggests the underlying mechanism is modulation instability caused by transverse perturbations. We hereby experimentally explore the interaction of modulation instability and turbulence, commonly associated with multiple-filaments, in the single-filament regime.

  17. Tile Rear Extension Module for the Phase-I Upgrade of the ATLAS L1Calo PreProcessor System

    CERN Document Server

    Andrei, George Victor; The ATLAS collaboration

    2016-01-01

    After the Phase-I ATLAS upgrade the Tile calorimeter will have to provide its data via fast optical links to the new Feature Extractor (FEX) modules of the L1Calo trigger system. In order to provide the FEXes with digitised Tile data, new Tile Rear Extension (TREX) modules need to be developed and installed in the existing L1Calo PreProcessor system. The TREX modules are highly complex PCBs, with state-of-the-art FPGAs and high-speed optical transmitters working at rates up to 14 Gbps. The prototype design of TREX and first corresponding test results will be presented.

  18. Multi-processor developments in the United States for future high energy physics experiments and accelerators

    International Nuclear Information System (INIS)

    The use of multi-processors for analysis and high-level triggering in High Energy Physics experiments, pioneered by the early emulator systems, has reached maturity, in particular with the multiple microprocessor systems in use at Fermilab. It is widely acknowledged that such systems will fulfill the major portion of the computing needs of future large experiments. Recent developments at Fermilab's Advanced Computer Program will make such systems even more powerful, cost-effective, and easier to use than they are at present. The next generation of microprocessors, already available, will provide CPU power of about one VAX 780 equivalent/$300, while supporting most VMS FORTRAN extensions and large (>8MB) amounts of memory. Low cost high density mass storage devices (based on video tape cartridge technology) will allow parallel I/O to remove potential I/O bottlenecks in systems of over 1000 VAX equipment processors. New interconnection schemes and system software will allow more flexible topologies and extremely high data bandwidth, especially for on-line systems. This talk will summarize the work at the Advanced Computer Program and the rest of the US in this field. 3 refs., 4 figs

  19. Insight into the physics of rupture: Dynamic triggering seismicity

    Science.gov (United States)

    Gonzalez-Huizar, Hector

    2009-12-01

    Seismic waves can trigger earthquakes and tremor at large distances from the causable event. Dynamic triggering occurs when the surface waves from large earthquakes change the stresses conditions on previously overstressed faults, promoting failure. To understand the causative stresses and environments behind dynamic triggering, we model the change in the stress field that the passing of Rayleigh and Love waves cause on a fault plane of arbitrary orientation relative to the direction of propagation of the waves, and apply a Coulomb failure criterion to calculate the potential of these stress changes to trigger seismicity. We apply our model to three different study regions and compare with observations. In the first case, we compare our model results with data from dynamically triggered earthquakes in the Australian Bowen Basin, Our data analysis shows that for this region, surface waves arriving at 45 degrees from the average local stress field are the most likely to trigger local seismicity. This agrees with our observations. In the second study case, we show how the same model can be applied to dynamic triggering of Non-volcanic tremor (NVT). Our modeling predicts the potential of a seismic wave to trigger slip on a fault plane promoting NVT. We search for tremor in the Central Range in Taiwan triggered by surfaces waves and compare the observations with our modeling. In the last study case, we present our modeling of the dynamic stress that triggered two events in Utah, one triggered by the 1992 Landers earthquake and the other by the 2002 Denali Fault earthquake. We show how dynamic stress modeling can be used to discriminate between the two axial planes of a first motion focal mechanism of a dynamically triggered event.

  20. The ATLAS Jet Trigger for LHC Run 2

    CERN Document Server

    Anjos, Nuno; The ATLAS collaboration

    2015-01-01

    The ATLAS Jet Trigger for LHC Run 2 The new centre of mass energy and high luminosity conditions expected for Run 2 at the Large Hadron Collider (LHC) impose more demanding constraints on the ATLAS online trigger than ever before. An immense rate of proton-proton collisions must be reduced from the bunch-crossing rate of 40 MHz to approximately 1 kHz before data can be written on disk for offline analysis. The ATLAS trigger system performs real-time reconstruction and selection of these events in order to achieve this reduction. The selection of events containing jets is uniquely challenging at a hadron collider where nearly every event contains significant hadronic activity. It is, however, of crucial importance to exploit the new data in many physics topics in the new kinematic regime, ranging from early Standard Model measurements to searches for New Physics. Following the very successful first LHC run in 2010/12, the ATLAS trigger was much improved, including a new hardware topological processor and the r...

  1. A hardware fast tracker for the ATLAS trigger

    Science.gov (United States)

    Asbah, Nedaa

    2016-09-01

    The trigger system of the ATLAS experiment is designed to reduce the event rate from the LHC nominal bunch crossing at 40 MHz to about 1 kHz, at the design luminosity of 1034 cm-2 s-1. After a successful period of data taking from 2010 to early 2013, the LHC already started with much higher instantaneous luminosity. This will increase the load on High Level Trigger system, the second stage of the selection based on software algorithms. More sophisticated algorithms will be needed to achieve higher background rejection while maintaining good efficiency for interesting physics signals. The Fast TracKer (FTK) is part of the ATLAS trigger upgrade project. It is a hardware processor that will provide, at every Level-1 accepted event (100 kHz) and within 100 microseconds, full tracking information for tracks with momentum as low as 1 GeV. Providing fast, extensive access to tracking information, with resolution comparable to the offline reconstruction, FTK will help in precise detection of the primary and secondary vertices to ensure robust selections and improve the trigger performance. FTK exploits hardware technologies with massive parallelism, combining Associative Memory ASICs, FPGAs and high-speed communication links.

  2. A Fast hardware Tracker for the ATLAS Trigger system

    CERN Document Server

    Pandini, Carlo Enrico; The ATLAS collaboration

    2015-01-01

    The trigger system at the ATLAS experiment is designed to lower the event rate occurring from the nominal bunch crossing at 40 MHz to about 1 kHz for a designed LHC luminosity of 10$^{34}$ cm$^{-2}$ s$^{-1}$. After a very successful data taking run the LHC is expected to run starting in 2015 with much higher instantaneous luminosities and this will increase the load on the High Level Trigger system. More sophisticated algorithms will be needed to achieve higher background rejection while maintaining good efficiency for interesting physics signals, which requires a more extensive use of tracking information. The Fast Tracker (FTK) trigger system, part of the ATLAS trigger upgrade program, is a highly parallel hardware device designed to perform full-scan track-finding at the event rate of 100 kHz. FTK is a dedicated processor based on a mixture of advanced technologies. Modern, powerful, Field Programmable Gate Arrays form an important part of the system architecture, and the combinatorial problem of pattern r...

  3. Digital Filter Performance for the ATLAS Level-1 Calorimeter Trigger

    CERN Document Server

    Hadley, D R; The ATLAS collaboration

    2010-01-01

    The ATLAS Level-1 Calorimeter Trigger is a hardware-based system designed to identify high-pT jets, electron/photon and tau candidates, and to measure total and missing ET in the ATLAS Liquid Argon and Tile calorimeters. It is a pipelined processor system, with a new set of inputs being evaluated every 25ns. The overall trigger decision has a latency budget of 2µs, including all transmission delays. The calorimeter trigger uses about 7200 reduced granularity analogue signals, which are first digitized at the 40 MHz LHC bunch-crossing frequency, before being passed to a digital Finite Impulse Response (FIR) filter. Due to latency and chip real-estate constraints, only a simple 5-element filter with limited precision can be used. Nevertheless this filter achieves a significant reduction in noise, along with improving the bunch-crossing assignment and energy resolution for small signals. The context in which digital filters are used for the ATLAS Level-1 Calorimeter Trigger will be presented, before describing ...

  4. Digital Filtering Performance in the ATLAS Level-1 Calorimeter Trigger

    CERN Document Server

    Hadley, D R; The ATLAS collaboration

    2010-01-01

    The ATLAS Level-1 Calorimeter Trigger is a hardware-based system designed to identify high-pT jets, elec- tron/photon and tau candidates, and to measure total and missing ET in the ATLAS Liquid Argon and Tile calorimeters. It is a pipelined processor system, with a new set of inputs being evaluated every 25ns. The overall trigger decision has a latency budget of 2µs, including all transmission delays. The calorimeter trigger uses about 7200 reduced granularity analogue signals, which are first digitized at the 40 MHz LHC bunch-crossing frequency, before being passed to a digital Finite Impulse Re- sponse (FIR) filter. Due to latency and chip real-estate constraints, only a simple 5-element filter with limited precision can be used. Nevertheless, this filter achieves a significant reduction in noise, along with improving the bunch-crossing assignment and energy resolution for small signals. The context in which digital filters are used for the ATLAS Level-1 Calorimeter Trigger is presented, before descr...

  5. Application-Specific Instruction Set Processor Implementation of List Sphere Detector

    Directory of Open Access Journals (Sweden)

    Salmela Perttu

    2007-01-01

    Full Text Available Multiple-input multiple-output (MIMO technology enables higher transmission capacity without additional frequency spectrum and is becoming a part of many wireless system standards. Sphere detection has been introduced in MIMO systems to achieve maximum likelihood (ML or near-ML estimation with reduced complexity. This paper reviews related work on sphere detector implementations and presents an application-specific instruction set processor (ASIP implementation of K-best list sphere detector (LSD using transport triggered architecture (TTA. The implementation is based on using memory and heap data structure for symbol vector sorting. The design space is explored by presenting several variations of the implementation and comparing them with each other in terms of their latencies and hardware complexities. An early proposal for a parallelized architecture with a decoding throughput of approximately 5.3 Mbps is presented

  6. Industry Analysis: Apple Processors in the Northeastern U.S.

    OpenAIRE

    Rowles, Kristin L.

    2001-01-01

    Apple processors are an important link in the marketing chain from apple growers to consumers, and their perspective is critical in understanding the industry?s situation and projecting the industry?s future. This paper reports the results of a survey of Northeastern U.S. apple processors. The survey was conducted to provide a snapshot of current strategic issues in the industry, to assess the industry?s strengths and weaknesses, to identify opportunities and threats, to forecast future trend...

  7. MARKETING AND LOGISTICS ASSITANCE NEEDS OF FOOD PROCESSORS

    OpenAIRE

    Jensen, Kimberly L.; Pompelli, Greg

    2000-01-01

    The focus of this paper is a study that examines the marketing and logistics assistance needs of Tennessee food processors. Data for the study was drawn from a 1999 survey of Tennessee food processors. The study examines the overall importance of various types of marketing and logistics assistance and the variance of needs across firm size, product type, scope of anticipated market growth, and business experience. The findings from this study are useful for the targeting of assistance service...

  8. Nanosensor Data Processor in Quantum-Dot Cellular Automata

    OpenAIRE

    Fenghui Yao; Mohamed Saleh Zein-Sabatto; Guifeng Shao; Mohammad Bodruzzaman; Mohan Malkani

    2014-01-01

    Quantum-dot cellular automata (QCA) is an attractive nanotechnology with the potential alterative to CMOS technology. QCA provides an interesting paradigm for faster speed, smaller size, and lower power consumption in comparison to transistor-based technology, in both communication and computation. This paper describes the design of a 4-bit multifunction nanosensor data processor (NSDP). The functions of NSDP contain (i) sending the preprocessed raw data to high-level processor, (ii) counting...

  9. Multi Microkernel Operating Systems for Multi-Core Processors

    Directory of Open Access Journals (Sweden)

    Rami Matarneh

    2009-01-01

    Full Text Available Problem statement: In the midst of the huge development in processors industry as a response to the increasing demand for high-speed processors manufacturers were able to achieve the goal of producing the required processors, but this industry disappointed hopes, because it faced problems not amenable to solution, such as complexity, hard management and large consumption of energy. These problems forced the manufacturers to stop the focus on increasing the speed of processors and go toward parallel processing to increase performance. This eventually produced multi-core processors with high-performance, if used properly. Unfortunately, until now, these processors did not use as it should be used; because of lack support of operating system and software applications. Approach: The approach based on the assumption that single-kernel operating system was not enough to manage multi-core processors to rethink the construction of multi-kernel operating system. One of these kernels serves as the master kernel and the others serve as slave kernels. Results: Theoretically, the proposed model showed that it can do much better than the existing models; because it supported single-threaded processing and multi-threaded processing at the same time, in addition, it can make better use of multi-core processors because it divided the load almost equally between the cores and the kernels which will lead to a significant improvement in the performance of the operating system. Conclusion: Software industry needed to get out of the classical framework to be able to keep pace with hardware development, this objective was achieved by re-thinking building operating systems and software in a new innovative methodologies and methods, where the current theories of operating systems were no longer capable of achieving the aspirations of future.

  10. Fast parallel computation of polynomials using few processors

    DEFF Research Database (Denmark)

    Valiant, Leslie; Skyum, Sven

    1981-01-01

    It is shown that any multivariate polynomial that can be computed sequentially in C steps and has degree d can be computed in parallel in 0((log d) (log C + log d)) steps using only (Cd)0(1) processors.......It is shown that any multivariate polynomial that can be computed sequentially in C steps and has degree d can be computed in parallel in 0((log d) (log C + log d)) steps using only (Cd)0(1) processors....

  11. Fast Parallel Computation of Polynomials Using Few Processors

    DEFF Research Database (Denmark)

    Valiant, Leslie G.; Skyum, Sven; Berkowitz, S.;

    1983-01-01

    It is shown that any multivariate polynomial of degree $d$ that can be computed sequentially in $C$ steps can be computed in parallel in $O((\\log d)(\\log C + \\log d))$ steps using only $(Cd)^{O(1)} $ processors.......It is shown that any multivariate polynomial of degree $d$ that can be computed sequentially in $C$ steps can be computed in parallel in $O((\\log d)(\\log C + \\log d))$ steps using only $(Cd)^{O(1)} $ processors....

  12. Formaldehyde and Glyoxal: New Products in the SCIAMACHY Operational Processor

    OpenAIRE

    Hrechanyy, Serhiy; De Smedt, Isabelle; Kretschel, Klaus; Lichtenberg, Günter; Meringer, Markus; Wittrock, Folkard

    2010-01-01

    In sommer of 2010 version 6 of the SCIAMACHY operational processor is planned to be delivered to ESA. The SCIAMACHY Quality Working Group recommended an implementation of the formaldehyde (HCHO) and glyoxal (CHOCHO) vertical columns into version 6 of the off-line processor. They are formed during the oxidation of volatile organic compounds (VOCs) emitted by plants, anthropogenic activities, and biomass burning. Due to a rather short lifetime of formaldehyde and glyoxal, their distribution...

  13. The Serial Link Processor for the Fast TracKer (FTK) processor at ATLAS

    CERN Document Server

    Biesuz, Nicolo Vladi; The ATLAS collaboration; Luciano, Pierluigi; Magalotti, Daniel; Rossi, Enrico

    2015-01-01

    The Associative Memory (AM) system of the Fast Tracker (FTK) processor has been designed to perform pattern matching using the hit information of the ATLAS experiment silicon tracker. The AM is the heart of FTK and is mainly based on the use of ASICs (AM chips) designed on purpose to execute pattern matching with a high degree of parallelism. It finds track candidates at low resolution that are seeds for a full resolution track fitting. To solve the very challenging data traffic problems inside FTK, multiple board and chip designs have been performed. The currently proposed solution is named the “Serial Link Processor” and is based on an extremely powerful network of 2 Gb/s serial links. This paper reports on the design of the Serial Link Processor consisting of two types of boards, the Local Associative Memory Board (LAMB), a mezzanine where the AM chips are mounted, and the Associative Memory Board (AMB), a 9U VME board which holds and exercises four LAMBs. We report on the performance of the intermedia...

  14. The Serial Link Processor for the Fast TracKer (FTK) processor at ATLAS

    CERN Document Server

    Biesuz, Nicolo Vladi; The ATLAS collaboration; Luciano, Pierluigi; Magalotti, Daniel; Rossi, Enrico

    2015-01-01

    The Associative Memory (AM) system of the Fast Tracker (FTK) processor has been designed to perform pattern matching using the hit information of the ATLAS experiment silicon tracker. The AM is the heart of FTK and is mainly based on the use of ASICs (AM chips) designed to execute pattern matching with a high degree of parallelism. The AM system finds track candidates at low resolution that are seeds for a full resolution track fitting. To solve the very challenging data traffic problems inside FTK, multiple board and chip designs have been performed. The currently proposed solution is named the “Serial Link Processor” and is based on an extremely powerful network of 828 2 Gbit/s serial links for a total in/out bandwidth of 56 Gb/s. This paper reports on the design of the Serial Link Processor consisting of two types of boards, the Local Associative Memory Board (LAMB), a mezzanine where the AM chips are mounted, and the Associative Memory Board (AMB), a 9U VME board which holds and exercises four LAMBs. ...

  15. The Serial Link Processor for the Fast TracKer (FTK) processor at ATLAS

    CERN Document Server

    Andreani, A; The ATLAS collaboration; Beccherle, R; Beretta, M; Cipriani, R; Citraro, S; Citterio, M; Colombo, A; Crescioli, F; Dimas, D; Donati, S; Giannetti, P; Kordas, K; Lanza, A; Liberali, V; Luciano, P; Magalotti, D; Neroutsos, P; Nikolaidis, S; Piendibene, M; Sakellariou, A; Shojaii, S; Sotiropoulou, C-L; Stabile, A

    2014-01-01

    The Associative Memory (AM) system of the FTK processor has been designed to perform pattern matching using the hit information of the ATLAS silicon tracker. The AM is the heart of the FTK and it finds track candidates at low resolution that are seeds for a full resolution track fitting. To solve the very challenging data traffic problems inside the FTK, multiple designs and tests have been performed. The currently proposed solution is named the “Serial Link Processor” and is based on an extremely powerful network of 2 Gb/s serial links. This paper reports on the design of the Serial Link Processor consisting of the AM chip, an ASIC designed and optimized to perform pattern matching, and two types of boards, the Local Associative Memory Board (LAMB), a mezzanine where the AM chips are mounted, and the Associative Memory Board (AMB), a 9U VME board which holds and exercises four LAMBs. Special relevance will be given to the AMchip design that includes two custom cells optimized for low consumption. We repo...

  16. The new level-1 trigger for the forward tagger of the L3 experiment

    Energy Technology Data Exchange (ETDEWEB)

    Bourquin, M.; Clerc, B.; Field, J.H.; Fredj, L.; Richeux, J.P.; Sciarrino, D.; Susinno, G.F. [Geneva Univ. (Switzerland). Dept. de Physique Nucleaire et Corpusculaire

    1998-07-11

    A fast level-1 trigger processor for the active lead ring calorimeter (ALR) and for the very small angle tagger (VSAT) of the L3 detector has been constructed and implemented. The main application is the study of single tagged two-photon collision processes at LEP II. Particular care has been taken to preserve the timing characteristics of the signal in order to allow bunch tagging in the multi-bunch mode of LEP. (orig.)

  17. High-Speed General Purpose Genetic Algorithm Processor.

    Science.gov (United States)

    Hoseini Alinodehi, Seyed Pourya; Moshfe, Sajjad; Saber Zaeimian, Masoumeh; Khoei, Abdollah; Hadidi, Khairollah

    2016-07-01

    In this paper, an ultrafast steady-state genetic algorithm processor (GAP) is presented. Due to the heavy computational load of genetic algorithms (GAs), they usually take a long time to find optimum solutions. Hardware implementation is a significant approach to overcome the problem by speeding up the GAs procedure. Hence, we designed a digital CMOS implementation of GA in [Formula: see text] process. The proposed processor is not bounded to a specific application. Indeed, it is a general-purpose processor, which is capable of performing optimization in any possible application. Utilizing speed-boosting techniques, such as pipeline scheme, parallel coarse-grained processing, parallel fitness computation, parallel selection of parents, dual-population scheme, and support for pipelined fitness computation, the proposed processor significantly reduces the processing time. Furthermore, by relying on a built-in discard operator the proposed hardware may be used in constrained problems that are very common in control applications. In the proposed design, a large search space is achievable through the bit string length extension of individuals in the genetic population by connecting the 32-bit GAPs. In addition, the proposed processor supports parallel processing, in which the GAs procedure can be run on several connected processors simultaneously. PMID:26241984

  18. High-Speed General Purpose Genetic Algorithm Processor.

    Science.gov (United States)

    Hoseini Alinodehi, Seyed Pourya; Moshfe, Sajjad; Saber Zaeimian, Masoumeh; Khoei, Abdollah; Hadidi, Khairollah

    2016-07-01

    In this paper, an ultrafast steady-state genetic algorithm processor (GAP) is presented. Due to the heavy computational load of genetic algorithms (GAs), they usually take a long time to find optimum solutions. Hardware implementation is a significant approach to overcome the problem by speeding up the GAs procedure. Hence, we designed a digital CMOS implementation of GA in [Formula: see text] process. The proposed processor is not bounded to a specific application. Indeed, it is a general-purpose processor, which is capable of performing optimization in any possible application. Utilizing speed-boosting techniques, such as pipeline scheme, parallel coarse-grained processing, parallel fitness computation, parallel selection of parents, dual-population scheme, and support for pipelined fitness computation, the proposed processor significantly reduces the processing time. Furthermore, by relying on a built-in discard operator the proposed hardware may be used in constrained problems that are very common in control applications. In the proposed design, a large search space is achievable through the bit string length extension of individuals in the genetic population by connecting the 32-bit GAPs. In addition, the proposed processor supports parallel processing, in which the GAs procedure can be run on several connected processors simultaneously.

  19. L0 Project: Monitoring H1 Triggers with SpaCal

    OpenAIRE

    Barrelet, E.; Acounis, S; Durant, O.

    2001-01-01

    We have built a VME module using H1’s ADC and BaBar TDC interfaced to H1’s 29K processor. It is used to monitor SpaCal trigger, energy sums and trigger elements, by reading up to 130Kevents/s. The timing resolution is found to be surprisingly good ( »1ns) for energy sum signals. The performances under various beam conditions are shown, including a first study of the “hotspot” counters designed as a veto against e-beam background.

  20. Design of a Hardware Track Finder (Fast Tracker) for the ATLAS Trigger

    CERN Document Server

    Cavaliere, Viviana; The ATLAS collaboration

    2015-01-01

    The use of tracking information at the trigger level in the LHC Run II period is crucial for the trigger an data acquisition (TDAQ) system and will be even more so as contemporary collisions that occur at every bunch crossing will increase in Run III. The Fast TracKer (FTK) is part of the ATLAS trigger upgrade project; it is a hardware processor that will provide every Level-1 accepted event (100 kHz) and within 100$\\mu$s, full tracking information for tracks with momentum as low as 1 GeV. Providing fast, extensive access to tracking information, with resolution comparable to the offline reconstruction, FTK will help in precise detection of the primary and secondary vertices to ensure robust selections and improve the trigger performance.

  1. CNS disease triggering Takotsubo stress cardiomyopathy.

    Science.gov (United States)

    Finsterer, Josef; Wahbi, Karim

    2014-12-15

    There are a number of hereditary and non-hereditary central nervous system (CNS) disorders, which directly or indirectly affect the heart (brain-heart disorders). The most well-known of these CNS disorders are epilepsy, stroke, infectious or immunological encephalitis/meningitis, migraine, and traumatic brain injury. In addition, a number of hereditary and non-hereditary neurodegenerative disorders may impair cardiac functions. Affection of the heart may manifest not only as arrhythmias, myocardial infarction, autonomic impairment, systolic dysfunction/heart failure, arterial hypertension, or pulmonary hypertension, but also as stress cardiomyopathy (Takotsubo syndrome, TTS). CNS disease triggering TTS includes subarachnoid bleeding, epilepsy, ischemic stroke, intracerebral bleeding, migraine, encephalitis, traumatic brain injury, PRES syndrome, or ALS. Usually, TTS is acutely precipitated by stress triggered by various different events. TTS is one of the cardiac abnormalities most frequently induced by CNS disorders. Appropriate management of TTS from CNS disorders is essential to improve the outcome of affected patients. PMID:25213573

  2. The CDF LEVEL3 trigger

    Energy Technology Data Exchange (ETDEWEB)

    Carroll, T.; Joshi, U.; Auchincloss, P. [and others

    1989-04-01

    CDF is currently taking data at a luminosity of 10{sup 30} cm{sup -2} sec{sup -1} using a four level event filtering scheme. The fourth level, LEVEL3, uses ACP (Fermilab`s Advanced Computer Program) designed 32 bit VME based parallel processors (1) capable of executing algorithms written in FORTRAN. LEVEL3 currently rejects about 50% of the events.

  3. [Improving speech comprehension using a new cochlear implant speech processor].

    Science.gov (United States)

    Müller-Deile, J; Kortmann, T; Hoppe, U; Hessel, H; Morsnowski, A

    2009-06-01

    The aim of this multicenter clinical field study was to assess the benefits of the new Freedom 24 sound processor for cochlear implant (CI) users implanted with the Nucleus 24 cochlear implant system. The study included 48 postlingually profoundly deaf experienced CI users who demonstrated speech comprehension performance with their current speech processor on the Oldenburg sentence test (OLSA) in quiet conditions of at least 80% correct scores and who were able to perform adaptive speech threshold testing using the OLSA in noisy conditions. Following baseline measures of speech comprehension performance with their current speech processor, subjects were upgraded to the Freedom 24 speech processor. After a take-home trial period of at least 2 weeks, subject performance was evaluated by measuring the speech reception threshold with the Freiburg multisyllabic word test and speech intelligibility with the Freiburg monosyllabic word test at 50 dB and 70 dB in the sound field. The results demonstrated highly significant benefits for speech comprehension with the new speech processor. Significant benefits for speech comprehension were also demonstrated with the new speech processor when tested in competing background noise.In contrast, use of the Abbreviated Profile of Hearing Aid Benefit (APHAB) did not prove to be a suitably sensitive assessment tool for comparative subjective self-assessment of hearing benefits with each processor. Use of the preprocessing algorithm known as adaptive dynamic range optimization (ADRO) in the Freedom 24 led to additional improvements over the standard upgrade map for speech comprehension in quiet and showed equivalent performance in noise. Through use of the preprocessing beam-forming algorithm BEAM, subjects demonstrated a highly significant improved signal-to-noise ratio for speech comprehension thresholds (i.e., signal-to-noise ratio for 50% speech comprehension scores) when tested with an adaptive procedure using the Oldenburg

  4. Precision and the approach to optimality in quantum annealing processors

    Science.gov (United States)

    Johnson, Mark W.

    The last few years have seen both a significant technological advance towards the practical application of, and a growing scientific interest in the underlying behaviour of quantum annealing (QA) algorithms. A series of commercially available QA processors, most recently the D-Wave 2XTM 1000 qubit processor, have provided a valuable platform for empirical study of QA at a non-trivial scale. From this it has become clear that misspecification of Hamiltonian parameters is an important performance consideration, both for the goal of studying the underlying physics of QA, as well as that of building a practical and useful QA processor. The empirical study of the physics of QA requires a way to look beyond Hamiltonian misspecification.Recently, a solver metric called 'time-to-target' was proposed as a way to compare quantum annealing processors to classical heuristic algorithms. This approach puts emphasis on analyzing a solver's short time approach to the ground state. In this presentation I will review the processor technology, based on superconducting flux qubits, and some of the known sources of error in Hamiltonian specification. I will then discuss recent advances in reducing Hamiltonian specification error, as well as review the time-to-target metric and empirical results analyzed in this way.

  5. PERFORMANCE OF PRIVATE CACHE REPLACEMENT POLICIES FOR MULTICORE PROCESSORS

    Directory of Open Access Journals (Sweden)

    Matthew Lentz

    2014-07-01

    Full Text Available Multicore processors have become ubiquitous, both in general-purpose and special-purpose applications. With the number of transistors in a chip continuing to increase, the number of cores in a processor is also expected to increase. Cache replacement policy is an important design parameter of a cache hierarchy. As most of the processor designs have become multicore, there is a need to study cache replacement policies for multi-core systems. Previous studies have focused on the shared levels of the multicore cache hierarchy. In this study, we focus on the top level of the hierarchy, which bears the brunt of the memory requests emanating from each processor core. We measure the miss rates of various cache replacement policies, as the number of cores is steadily increased from 1 to 16. The study was done by modifying the publicly available SESC simulator, which models in detail a multicore processor with a multilevel cache hierarchy. Our experimental results show that for the private L1 caches, the LRU (Least Recently Used replacement policy outperforms all of the other replacement policies. This is in contrast to what was observed in previous studies for the shared L2 cache. The results presented in this paper are useful for hardware designers to optimize their cache designs or the program codes.

  6. The PreProcessors for the ATLAS Tile Calorimeter Phase II Upgrade

    CERN Document Server

    Carrio Argos, Fernando; The ATLAS collaboration

    2015-01-01

    The Large Hadron Collider (LHC) has envisaged a series of upgrades towards a High Luminosity LHC (HL-LHC) delivering five times the LHC nominal instantaneous luminosity. The ATLAS Phase II upgrade will accommodate the detector and data acquisition system for the HL-LHC. In particular, the Tile Hadronic Calorimeter (TileCal) will replace completely front-end and back-end electronics using a new readout architecture. The digitized detector data will be transferred for every beam crossing to the PreProcessors (TilePPr) located in off-detector counting rooms with a total data bandwidth of roughly 80 Tbps. The TilePPr implements increased pipelines memories and must provide pre-processed digital trigger information to Level 0 trigger systems. The TilePPr system represents the link between the front-end electronics and the overall ATLAS data acquisition system. It also implements the interface between the Detector Control System (DCS) and the front-end electronics which is used to control and monitor the high volta...

  7. Modal Processor Effects Inspired by Hammond Tonewheel Organs

    Directory of Open Access Journals (Sweden)

    Kurt James Werner

    2016-06-01

    Full Text Available In this design study, we introduce a novel class of digital audio effects that extend the recently introduced modal processor approach to artificial reverberation and effects processing. These pitch and distortion processing effects mimic the design and sonics of a classic additive-synthesis-based electromechanical musical instrument, the Hammond tonewheel organ. As a reverb effect, the modal processor simulates a room response as the sum of resonant filter responses. This architecture provides precise, interactive control over the frequency, damping, and complex amplitude of each mode. Into this framework, we introduce two types of processing effects: pitch effects inspired by the Hammond organ’s equal tempered “tonewheels”, “drawbar” tone controls, vibrato/chorus circuit, and distortion effects inspired by the pseudo-sinusoidal shape of its tonewheels and electromagnetic pickup distortion. The result is an effects processor that imprints the Hammond organ’s sonics onto any audio input.

  8. Architecture and Design of Medical Processor Units for Medical Networks

    Directory of Open Access Journals (Sweden)

    Syed V. Ahamed

    2010-11-01

    Full Text Available This paper1 introduces analogical and deductive methodologies for the design medical processor units(MPUs. From the study of evolution of numerous earlier processors, we derive the basis for thearchitecture of MPUs. These specialized processors perform unique medical functions encoded as medicaloperational codes (mopcs. From a pragmatic perspective, MPUs function very close to CPUs. Bothprocessors have unique operation codes that command the hardware to perform a distinct chain of subprocessesupon operands and generate a specific result unique to the opcode and the operand(s. Inmedical environments, MPU decodes the mopcs and executes a series of medical sub-processes and sendsout secondary commands to the medical machine. Whereas operands in a typical computer system arenumerical and logical entities, the operands in medical machine are objects such as such as patients, bloodsamples, tissues, operating rooms, medical staff, medical bills, patient payments, etc. We follow thefunctional overlap between the two processes and evolve the design of medical computer systems andnetworks.

  9. High Performance Ethernet Packet Processor Core for Next Generation Networks

    Directory of Open Access Journals (Sweden)

    Raja Jitendra Nayaka

    2012-10-01

    Full Text Available As the demand for high speed Internet significantly increasing to meet the requirement of large datatransfers, real-time communication and High Definition ( HD multimedia transfer over IP, the IP basednetwork products architecture must evolve and change. Application specific processors require highperformance, low power and high degree of programmability is the limitation in many general processorbased applications. This paper describes the design of Ethernet packet processor for system-on-chip (SoCwhich performs all core packet processing functions, including segmentation and reassembly, packetizationclassification, route and queue management which will speedup switching/routing performance making itmore suitable for Next Generation Networks (NGN. Ethernet packet processor design can be configuredfor use with multiple projects targeted to a FPGA device the system is designed to support 1/10/20/40/100Gigabit links with a speed and performance advantage. VHDL has been used to implement and simulatedthe required functions in FPGA.

  10. An assumed partition algorithm for determining processor inter-communication

    Energy Technology Data Exchange (ETDEWEB)

    Baker, A H; Falgout, R D; Yang, U M

    2005-09-23

    The recent advent of parallel machines with tens of thousands of processors is presenting new challenges for obtaining scalability. A particular challenge for large-scale scientific software is determining the inter-processor communications required by the computation when a global description of the data is unavailable or too costly to store. We present a type of rendezvous algorithm that determines communication partners in a scalable manner by assuming the global distribution of the data. We demonstrate the scaling properties of the algorithm on up to 32,000 processors in the context of determining communication patterns for a matrix-vector multiply in the hypre software library. Our algorithm is very general and is applicable to a variety of situations in parallel computing.

  11. A Bayesian sequential processor approach to spectroscopic portal system decisions

    Energy Technology Data Exchange (ETDEWEB)

    Sale, K; Candy, J; Breitfeller, E; Guidry, B; Manatt, D; Gosnell, T; Chambers, D

    2007-07-31

    The development of faster more reliable techniques to detect radioactive contraband in a portal type scenario is an extremely important problem especially in this era of constant terrorist threats. Towards this goal the development of a model-based, Bayesian sequential data processor for the detection problem is discussed. In the sequential processor each datum (detector energy deposit and pulse arrival time) is used to update the posterior probability distribution over the space of model parameters. The nature of the sequential processor approach is that a detection is produced as soon as it is statistically justified by the data rather than waiting for a fixed counting interval before any analysis is performed. In this paper the Bayesian model-based approach, physics and signal processing models and decision functions are discussed along with the first results of our research.

  12. Processor Allocation for Optimistic Parallelization of Irregular Programs

    CERN Document Server

    Versaci, Francesco

    2012-01-01

    Optimistic parallelization is a promising approach for the parallelization of irregular algorithms: potentially interfering tasks are launched dynamically, and the runtime system detects conflicts between concurrent activities, aborting and rolling back conflicting tasks. However, parallelism in irregular algorithms is very complex. In a regular algorithm like dense matrix multiplication, the amount of parallelism can usually be expressed as a function of the problem size, so it is reasonably straightforward to determine how many processors should be allocated to execute a regular algorithm of a certain size (this is called the processor allocation problem). In contrast, parallelism in irregular algorithms can be a function of input parameters, and the amount of parallelism can vary dramatically during the execution of the irregular algorithm. Therefore, the processor allocation problem for irregular algorithms is very difficult. In this paper, we describe the first systematic strategy for addressing this pro...

  13. Safety-critical Java on a time-predictable processor

    DEFF Research Database (Denmark)

    Korsholm, Stephan E.; Schoeberl, Martin; Puffitsch, Wolfgang

    2015-01-01

    For real-time systems the whole execution stack needs to be time-predictable and analyzable for the worst-case execution time (WCET). This paper presents a time-predictable platform for safety-critical Java. The platform consists of (1) the Patmos processor, which is a time-predictable processor......; (2) a C compiler for Patmos with support for WCET analysis; (3) the HVM, which is a Java-to-C compiler; (4) the HVM-SCJ implementation which supports SCJ Level 0, 1, and 2 (for both single and multicore platforms); and (5) a WCET analysis tool. We show that real-time Java programs translated to C...... and compiled to a Patmos binary can be analyzed by the AbsInt aiT WCET analysis tool. To the best of our knowledge the presented system is the second WCET analyzable real-time Java system; and the first one on top of a RISC processor....

  14. The DPGA for Conbining the Superscalar and Multithreaded Processors Principal

    Institute of Scientific and Technical Information of China (English)

    2001-01-01

    The performance of scalable shared-memory multiprocessors suffers from three types of latency; memory latency, the latency caused by inter-process synchroni z ation ,and the latency caused by instructions that take multiple cycles to produ ce results. To tolerate these three types of latencies, The followin g techniques was proposed to couple: coarse-grained multithreading, the supersc alar processor and a rec onfigurable device, namely the overlapping long latency operations of one thread of computation with the execution of other threads. The superscalar processor p rinciple is used to tolerate instruction latency by issuing several instructions simultaneously. The DPGA is coupled with this processor in order to improve th e context-switching overhead.

  15. Safety-Critical Java on a Time-predictable Processor

    DEFF Research Database (Denmark)

    Korsholm, Stephan Erbs; Schoeberl, Martin; Puffitsch, Wolfgang

    2015-01-01

    For real-time systems the whole execution stack needs to be time-predictable and analyzable for the worst-case execution time (WCET). This paper presents a time-predictable platform for safety-critical Java. The platform consists of (1) the Patmos processor, which is a time-predictable processor......; (2) a C compiler for Patmos with support for WCET analysis; (3) the HVM, which is a Java-to-C compiler; (4) the HVM-SCJ implementation which supports SCJ Level 0, 1, and 2 (for both single and multicore platforms); and (5) a WCET analysis tool. We show that real-time Java programs translated to C...... and compiled to a Patmos binary can be analyzed by the AbsInt aiT WCET analysis tool. To the best of our knowledge the presented system is the second WCET analyzable real-time Java system; and the first one on top of a RISC processor....

  16. Token-Aware Completion Functions for Elastic Processor Verification

    Directory of Open Access Journals (Sweden)

    Sudarshan K. Srinivasan

    2009-01-01

    Full Text Available We develop a formal verification procedure to check that elastic pipelined processor designs correctly implement their instruction set architecture (ISA specifications. The notion of correctness we use is based on refinement. Refinement proofs are based on refinement maps, which—in the context of this problem—are functions that map elastic processor states to states of the ISA specification model. Data flow in elastic architectures is complicated by the insertion of any number of buffers in any place in the design, making it hard to construct refinement maps for elastic systems in a systematic manner. We introduce token-aware completion functions, which incorporate a mechanism to track the flow of data in elastic pipelines, as a highly automated and systematic approach to construct refinement maps. We demonstrate the efficiency of the overall verification procedure based on token-aware completion functions using six elastic pipelined processor models based on the DLX architecture.

  17. Stepping motor control processor reference manual. Volume I

    International Nuclear Information System (INIS)

    This manual is intended to serve several purposes. The first goal is to describe the capabilities and operation of the SMC processor package from an operator or user point of view. Secondly, the manual will describe in some detail the basic hardware elements and how they can be used effectively to implement a step motor control system. Practical information on the use, installation and checkout of the hardware set is presented in the following sections along with programming suggestions. Available related system software is described in this manual for reference and as an aid in understanding the system architecture. Section two presents an overview and operations manual of the SMC processor describing its composition and functional capabilities. Section three contains hardware descriptions in some detail for the LLL-designed hardware used in the SMC processor. Basic theory of operation and important features are explained

  18. Fault Tolerance Mechanism in Chip Many-Core Processors

    Institute of Scientific and Technical Information of China (English)

    ZHANG Lei; HAN Yinhe; LI Huawei; LI Xiaowei

    2007-01-01

    As semiconductor technology advances, there will be billions of transistors on a single chip. Chip many-core processors are emerging to take advantage of these greater transistor densities to deliver greater performance. Effective fault tolerance techniques are essential to improve the yield of such complex chips. In this paper, a core-level redundancy scheme called N+M is proposed to improve N-core processors'yield by providing M spare cores. In such architecture, topology is an important factor because it greatly affects the processors'performance. The concept of logical topology and a topology reconfiguration problem are introduced, which is able to transparently provide target topology with lowest performance degradation as the presence of faulty cores on-chip. A row rippling and column stealing (RRCS) algorithm is also proposed. Results show that PRCS can give solutions with average 13.8% degradation with negligible computing time.

  19. Benchmarking NWP Kernels on Multi- and Many-core Processors

    Science.gov (United States)

    Michalakes, J.; Vachharajani, M.

    2008-12-01

    Increased computing power for weather, climate, and atmospheric science has provided direct benefits for defense, agriculture, the economy, the environment, and public welfare and convenience. Today, very large clusters with many thousands of processors are allowing scientists to move forward with simulations of unprecedented size. But time-critical applications such as real-time forecasting or climate prediction need strong scaling: faster nodes and processors, not more of them. Moreover, the need for good cost- performance has never been greater, both in terms of performance per watt and per dollar. For these reasons, the new generations of multi- and many-core processors being mass produced for commercial IT and "graphical computing" (video games) are being scrutinized for their ability to exploit the abundant fine- grain parallelism in atmospheric models. We present results of our work to date identifying key computational kernels within the dynamics and physics of a large community NWP model, the Weather Research and Forecast (WRF) model. We benchmark and optimize these kernels on several different multi- and many-core processors. The goals are to (1) characterize and model performance of the kernels in terms of computational intensity, data parallelism, memory bandwidth pressure, memory footprint, etc. (2) enumerate and classify effective strategies for coding and optimizing for these new processors, (3) assess difficulties and opportunities for tool or higher-level language support, and (4) establish a continuing set of kernel benchmarks that can be used to measure and compare effectiveness of current and future designs of multi- and many-core processors for weather and climate applications.

  20. A Hardware Fast Tracker for the ATLAS trigger

    CERN Document Server

    Asbah, Nedaa; The ATLAS collaboration

    2015-01-01

    The trigger system of the ATLAS experiment is designed to reduce the event rate from the LHC nominal bunch crossing at 40 MHz to about 1 kHz, at the design luminosity of 10^{34} cm^{-2}s^{-1}. After a successful period of data taking from 2010 to early 2013, the LHC restarted with much higher instantaneous luminosity. This will increase the load on High Level Trigger system, the second stage of the selection based on software algorithms. More sophisticated algorithms will be needed to achieve higher background rejection while maintaining good efficiency for interesting physics signals. The Fast TracKer (FTK) is part of the ATLAS trigger upgrade project; it is a hardware processor that will provide, at every level-1 accepted event (100 kHz) and within 100 microseconds, full tracking information for tracks with momentum as low as 1 GeV. Providing fast extensive access to tracking information, with resolution comparable to the offline reconstruction, FTK will help in precise detection of the primary and secondar...

  1. Development of a parallel trigger framework for rare decay searches

    CERN Document Server

    Pantaleo, Felice

    The simplicity of kaon decays (few decay channels, low final-state multiplicities) enable the possibility to reach an excellent sensitivity in the searches of lepton flavor violating decays. The experimental characteristics of decays like $K^+\\to \\pi^- \\mu^+ \\mu^+$ are very clear and allow an efficient background rejection. However, the measurement of this kind of events requires the production of a remarkable number of kaon decays. The bandwidth of tape recording system currently available does not allow the storage of all the produced events. A multi-stage selection of the potentially interesting events is required (trigger). At NA62, a first selection is done in real-time (response time $<1$ ms) by the level 0 trigger. The level 0 trigger is based on programmable logic (FPGA) that does not allow the same flexibility of the processors used for software programmable computers. The performance of parallel architectures like multi-cores CPUs and GPUs (Graphics Processing Units), located on computers grap...

  2. Long-Range Dependence and On-chip Processor traffic

    OpenAIRE

    Scherrer, Antoine; Fraboulet, Antoine; Risset, Tanguy

    2009-01-01

    Long-range dependence is a property of stochastic processes that has an important impact on network performance, especially on the buffer usage in routers. We analyze the presence of long-range dependence in on-chip processor traffic and we study the impact of long-range dependence on networks-on-chip. long-range dependence in communication traces of processor ips at the cycle-accurate level. We also study the impact of long-range dependence on a real network-on-chip using the SocLib simulati...

  3. ARM Processor Based Embedded System for Remote Data Acquisition

    Directory of Open Access Journals (Sweden)

    Raj Kumar Tiwari

    2014-01-01

    Full Text Available The embedded systems are widely used for the data acquisition. The data acquired may be used for monitoring various activity of the system or it can be used to control the parts of the system. Accessing various signals with remote location has greater advantage for multisite operation or unmanned systems. The remote data acquisition used in this paper is based on ARM processor. The Cortex M3 processor used in this system has in-built Ethernet controller which facilitate to acquire the remote data using internet. The system developed provides high performance, low power consumption, smaller size {&} high speed

  4. Matrix preconditioning: a robust operation for optical linear algebra processors.

    Science.gov (United States)

    Ghosh, A; Paparao, P

    1987-07-15

    Analog electrooptical processors are best suited for applications demanding high computational throughput with tolerance for inaccuracies. Matrix preconditioning is one such application. Matrix preconditioning is a preprocessing step for reducing the condition number of a matrix and is used extensively with gradient algorithms for increasing the rate of convergence and improving the accuracy of the solution. In this paper, we describe a simple parallel algorithm for matrix preconditioning, which can be implemented efficiently on a pipelined optical linear algebra processor. From the results of our numerical experiments we show that the efficacy of the preconditioning algorithm is affected very little by the errors of the optical system.

  5. Nanosensor Data Processor in Quantum-Dot Cellular Automata

    Directory of Open Access Journals (Sweden)

    Fenghui Yao

    2014-01-01

    Full Text Available Quantum-dot cellular automata (QCA is an attractive nanotechnology with the potential alterative to CMOS technology. QCA provides an interesting paradigm for faster speed, smaller size, and lower power consumption in comparison to transistor-based technology, in both communication and computation. This paper describes the design of a 4-bit multifunction nanosensor data processor (NSDP. The functions of NSDP contain (i sending the preprocessed raw data to high-level processor, (ii counting the number of the active majority gates, and (iii generating the approximate sigmoid function. The whole system is designed and simulated with several different input data.

  6. Hardware Synchronization for Embedded Multi-Core Processors

    DEFF Research Database (Denmark)

    Stoif, Christian; Schoeberl, Martin; Liccardi, Benito;

    2011-01-01

    , establishing coherence and consistency for different types of shared memory by hardware means. Also support for point-to-point synchronization between the processor cores is realized implementing different hardware barriers. The practical examinations focus on the logical first step from single- to dual......-core systems, using an FPGA-development board with two hard PowerPC processor cores. Best- and worst-case results, together with intensive benchmarking of all synchronization primitives implemented, show the expected superiority of the hardware solutions. It is also shown that dual-ported memory outperforms...

  7. Embedded Data Processor and Portable Computer Technology testbeds

    Science.gov (United States)

    Alena, Richard; Liu, Yuan-Kwei; Goforth, Andre; Fernquist, Alan R.

    1993-01-01

    Attention is given to current activities in the Embedded Data Processor and Portable Computer Technology testbed configurations that are part of the Advanced Data Systems Architectures Testbed at the Information Sciences Division at NASA Ames Research Center. The Embedded Data Processor Testbed evaluates advanced microprocessors for potential use in mission and payload applications within the Space Station Freedom Program. The Portable Computer Technology (PCT) Testbed integrates and demonstrates advanced portable computing devices and data system architectures. The PCT Testbed uses both commercial and custom-developed devices to demonstrate the feasibility of functional expansion and networking for portable computers in flight missions.

  8. MICROTHREAD BASED (MTB) COARSE GRAINED FAULT TOLERANCE SUPERSCALAR PROCESSOR ARCHITECTURE

    Institute of Scientific and Technical Information of China (English)

    2006-01-01

    Fault tolerance in microprocessor systems has become a popular topic of architecture research.Much work has been done at different levels to accomplish reliability against soft errors, and some fault tolerance architectures have been proposed. But little attention is paid to the thread level superscalar fault tolerance.This letter introduces microthread concept into superscalar processor fault tolerance domain, and puts forward a novel fault tolerance architecture, namely, MicroThread Based (MTB) coarse grained transient fault tolerance superscalar processor architecture, then discusses some detailed implementations.

  9. Advanced Avionics and Processor Systems for Space and Lunar Exploration

    Science.gov (United States)

    Keys, Andrew S.; Adams, James H.; Ray, Robert E.; Johnson, Michael A.; Cressler, John D.

    2009-01-01

    NASA's newly named Advanced Avionics and Processor Systems (AAPS) project, formerly known as the Radiation Hardened Electronics for Space Environments (RHESE) project, endeavors to mature and develop the avionic and processor technologies required to fulfill NASA's goals for future space and lunar exploration. Over the past year, multiple advancements have been made within each of the individual AAPS technology development tasks that will facilitate the success of the Constellation program elements. This paper provides a brief review of the project's recent technology advancements, discusses their application to Constellation projects, and addresses the project's plans for the coming year.

  10. Method for fast start of a fuel processor

    Science.gov (United States)

    Ahluwalia, Rajesh K.; Ahmed, Shabbir; Lee, Sheldon H. D.

    2008-01-29

    An improved fuel processor for fuel cells is provided whereby the startup time of the processor is less than sixty seconds and can be as low as 30 seconds, if not less. A rapid startup time is achieved by either igniting or allowing a small mixture of air and fuel to react over and warm up the catalyst of an autothermal reformer (ATR). The ATR then produces combustible gases to be subsequently oxidized on and simultaneously warm up water-gas shift zone catalysts. After normal operating temperature has been achieved, the proportion of air included with the fuel is greatly diminished.

  11. Reconfigurable lattice mesh designs for programmable photonic processors.

    Science.gov (United States)

    Pérez, Daniel; Gasulla, Ivana; Capmany, José; Soref, Richard A

    2016-05-30

    We propose and analyse two novel mesh design geometries for the implementation of tunable optical cores in programmable photonic processors. These geometries are the hexagonal and the triangular lattice. They are compared here to a previously proposed square mesh topology in terms of a series of figures of merit that account for metrics that are relevant to on-chip integration of the mesh. We find that that the hexagonal mesh is the most suitable option of the three considered for the implementation of the reconfigurable optical core in the programmable processor. PMID:27410130

  12. Parallel Processor for 3D Recovery from Optical Flow

    Directory of Open Access Journals (Sweden)

    Jose Hugo Barron-Zambrano

    2009-01-01

    Full Text Available 3D recovery from motion has received a major effort in computer vision systems in the recent years. The main problem lies in the number of operations and memory accesses to be performed by the majority of the existing techniques when translated to hardware or software implementations. This paper proposes a parallel processor for 3D recovery from optical flow. Its main feature is the maximum reuse of data and the low number of clock cycles to calculate the optical flow, along with the precision with which 3D recovery is achieved. The results of the proposed architecture as well as those from processor synthesis are presented.

  13. Hardwired Logic and Multithread Design in Network Processors

    Institute of Scientific and Technical Information of China (English)

    李旭东; 徐扬; 刘斌; 王小军

    2004-01-01

    High-performance network processors are expected to play an important role in future high-speed routers. This paper focuses on two representative techniques needed for high-performance network processors: hardwired logic design and multithread design. Using hardwired logic, this paper compares a single-thread design with a multithread design, and proposes general models and principles to analyze the clock frequency and the resource cost for these environments. Then, two IP header processing schemes, one in single-thread mode and the other in double-thread mode, are developed using these principles and the implementation results verified the theoretical calculation.

  14. The Danish real-time SAR processor: first results

    DEFF Research Database (Denmark)

    Dall, Jørgen; Jørgensen, Jørn Hjelm; Netterstrøm, Anders;

    1993-01-01

    A real-time processor (RTP) for the Danish airborne Synthetic Aperture Radar (SAR) has been designed and constructed at the Electromagnetics Institute. The implementation was completed in mid 1992, and since then the RTP has been operated successfully on several test and demonstration flights....... The processor is capable of focusing the entire swath of the raw SAR data into full resolution, and depending on the choice made by the on-board operator, either a high resolution one-look zoom image or a spatially multilooked overview image is displayed. After a brief design review, the paper addresses various...

  15. Post-silicon and runtime verification for modern processors

    CERN Document Server

    Wagner, Ilya

    2010-01-01

    The purpose of this book is to survey the state of the art and evolving directions in post-silicon and runtime verification. The authors start by giving an overview of the state of the art in verification, particularly current post-silicon methodologies in use in the industry, both for the domain of processor pipeline design and for memory subsystems. They then dive into the presentation of several new post-silicon verification solutions aimed at boosting the verification coverage of modern processors, dedicating several chapters to this topic. The presentation of runtime verification solution

  16. GnRH agonist triggering

    DEFF Research Database (Denmark)

    Kol, Shahar; Humaidan, Peter; Al Humaidan, Peter Samir Heskjær

    2013-01-01

    The concept that a bolus of gonadotrophin-releasing hormone agonist (GnRHa) can replace human chorionic gonadotrophin (HCG) as a trigger of final oocyte maturation was introduced several years ago. Recent developments in the area strengthen this premise. GnRHa trigger offers important advantages...... triggering concept should be challenged and that the GnRHa trigger is the way to move forward with thoughtful consideration of the needs, safety and comfort of our patients. Routinely, human chorionic gonadotrophin (HCG) is used to induce ovulation in fertility treatments. This approach deviates...... significantly from physiology and often results in insufficient hormonal support in early pregnancy and in ovarian hyperstimulation syndrome (OHSS). An alternative approach is to use a gonadotrophin-releasing hormone (GnRH) agonist which allows a more physiological trigger of ovulation and, most importantly...

  17. Triggering requirements for SSC physics

    Energy Technology Data Exchange (ETDEWEB)

    Gilchriese, M.G.D. [Lawrence Berkeley Lab., CA (United States)

    1989-04-01

    Some aspects of triggering requirements for high P{sub T} physics processes at the Superconducting Super Collider (SSC) are described. A very wide range of trigger types will be required to enable detection of the large number of potential physics signatures possible at the SSC. Although in many cases trigger rates are not now well understood, it is possible to conclude that the ability to trigger on transverse energy, number and energy of jets, number and energy of leptons (electrons and muons), missing energy and combinations of these will be required. An SSC trigger system must be both highly flexible and redundant to ensure reliable detection of many new physics processes at the SSC.

  18. CDF trigger interface board 'FRED'

    International Nuclear Information System (INIS)

    We describe FASTBUS boards which interface sixteen different trigger interrupts to the Collider Detector Facility (CDF) data acquisition system. The boards are known to CDF by the acronym 'FRED'. The data acquisition scheme for CDF allows for up to 16 different parts of the detector, called 'Partitions', to run independently. Four partitions are reserved for physics runs and sophisticated calibration and debugging: they use the common Level 1 and Level 2 trigger logic and have access to information from all the components of the CDF detector. These four partitions are called ''CDF Partitions''. The remaining twelve partitions have no access to the common trigger logic and provide their own Level 1 and Level 2 signals: they are called ''Autonomous Partitions''. Fred collects and interprets signals from independent parts of the CDF trigger system and delivers Level 1 and Level 2 responses to the Trigger Supervisors (FASTBUS masters which control the data acquisition process in each partition)

  19. The ATLAS Hadronic Tau Trigger

    CERN Document Server

    Mahlstedt, J; The ATLAS collaboration

    2014-01-01

    During the 2012 run the Large Hadron Collider (LHC) reached instantaneous luminosities of nearly $10^{34}\\,cm^{-2}s^{-1}$, with bunch crossings occuring every 50 ns. In this difficult environment of several overlapping interactions per bunch crossing (pile-up) the trigger system of the ATLAS detector has the task of reducing the event rate from 40 MHz to a few hundred Hz while keeping the most interesting physics events. Being the heaviest of all leptons, the tau lepton plays an important role in many physics processes. The ability to trigger on events containing hadronically decaying taus is therefore of special interest. This paper summarizes the concept of the ATLAS tau trigger and the improvements made in 2012. Furthermore the performance of the triggers including efficiency and rate measurements are presented and an outlook towards future developments of the tau trigger algorithms is given.

  20. An Alternative Flight Software Trigger Paradigm: Applying Multivariate Logistic Regression to Sense Trigger Conditions Using Inaccurate or Scarce Information

    Science.gov (United States)

    Smith, Kelly M.; Gay, Robert S.; Stachowiak, Susan J.

    2013-01-01

    In late 2014, NASA will fly the Orion capsule on a Delta IV-Heavy rocket for the Exploration Flight Test-1 (EFT-1) mission. For EFT-1, the Orion capsule will be flying with a new GPS receiver and new navigation software. Given the experimental nature of the flight, the flight software must be robust to the loss of GPS measurements. Once the high-speed entry is complete, the drogue parachutes must be deployed within the proper conditions to stabilize the vehicle prior to deploying the main parachutes. When GPS is available in nominal operations, the vehicle will deploy the drogue parachutes based on an altitude trigger. However, when GPS is unavailable, the navigated altitude errors become excessively large, driving the need for a backup barometric altimeter to improve altitude knowledge. In order to increase overall robustness, the vehicle also has an alternate method of triggering the parachute deployment sequence based on planet-relative velocity if both the GPS and the barometric altimeter fail. However, this backup trigger results in large altitude errors relative to the targeted altitude. Motivated by this challenge, this paper demonstrates how logistic regression may be employed to semi-automatically generate robust triggers based on statistical analysis. Logistic regression is used as a ground processor pre-flight to develop a statistical classifier. The classifier would then be implemented in flight software and executed in real-time. This technique offers improved performance even in the face of highly inaccurate measurements. Although the logistic regression-based trigger approach will not be implemented within EFT-1 flight software, the methodology can be carried forward for future missions and vehicles.

  1. Triggering on electrons, jets and tau leptons with the CMS upgraded calorimeter trigger for the LHC RUN II

    Science.gov (United States)

    Zabi, A.; Beaudette, F.; Cadamuro, L.; Mastrolorenzo, L.; Romanteau, T.; Sauvan, J. B.; Strebler, T.; Marrouche, J.; Wardle, N.; Aggleton, R.; Ball, F.; Brooke, J.; Newbold, D.; Paramesvaran, S.; Smith, D.; Baber, M.; Bundock, A.; Citron, M.; Elwood, A.; Hall, G.; Iles, G.; Laner, C.; Penning, B.; Rose, A.; Tapper, A.; Durkin, T.; Harder, K.; Harper, S.; Shepherd-Themistocleous, C.; Thea, A.; Williams, T.

    2016-02-01

    The Compact Muon Solenoid (CMS) experiment has implemented a sophisticated two-level online selection system that achieves a rejection factor of nearly 105. During Run II, the LHC will increase its centre-of-mass energy up to 13 TeV and progressively reach an instantaneous luminosity of 2 × 1034 cm-2 s-1. In order to guarantee a successful and ambitious physics programme under this intense environment, the CMS Trigger and Data acquisition (DAQ) system has been upgraded. A novel concept for the L1 calorimeter trigger is introduced: the Time Multiplexed Trigger (TMT) . In this design, nine main processors receive each all of the calorimeter data from an entire event provided by 18 preprocessors. This design is not different from that of the CMS DAQ and HLT systems. The advantage of the TMT architecture is that a global view and full granularity of the calorimeters can be exploited by sophisticated algorithms. The goal is to maintain the current thresholds for calorimeter objects and improve the performance for their selection. The performance of these algorithms will be demonstrated, both in terms of efficiency and rate reduction. The callenging aspects of the pile-up mitigation and firmware design will be presented.

  2. DESDynI Quad First Stage Processor - a four channel digitizer and digital beam forming processor

    Science.gov (United States)

    Chuang, Chung-Lun; Shaffer, S.; Smythe, R.; Niamsuwan, N.; Li, S.; Liao, E.; Lim, C.; Morfopolous, A.; Veilleux, L.

    The proposed Deformation, Eco-Systems, and Dynamics of Ice Radar (DESDynI-R) L-band SAR instrument employs multiple digital channels to optimize resolution while keeping a large swath on a single pass. High-speed digitization with very fine synchronization and digital beam forming are necessary in order to facilitate this new technique. The Quad First Stage Processor (qFSP) was developed to achieve both the processing performance as well as the digitizing fidelity in order to accomplish this sweeping SAR technique. The qFSP utilizes high precision and high-speed analog to digital converters (ADCs), each with a finely adjustable clock distribution network to digitize the channels at the fidelity necessary to allow for digital beam forming. The Xilinx produced FX130T Virtex 5 part handles the processing to digitally calibrate each channel as well as filter and beam form the receive signals. Demonstrating the digital processing required for digital beam forming and digital calibration is instrumental to the viability of the proposed DESDynI instrument. The qFSP development brings this implementation to Technology Readiness Level (TRL) 6. This paper will detail the design and development of the prototype qFSP as well as the preliminary results from hardware tests.

  3. DESDynI Quad First Stage Processor - A Four Channel Digitizer and Digital Beam Forming Processor

    Science.gov (United States)

    Chuang, Chung-Lun; Shaffer, Scott; Smythe, Robert; Niamsuwan, Noppasin; Li, Samuel; Liao, Eric; Lim, Chester; Morfopolous, Arin; Veilleux, Louise

    2013-01-01

    The proposed Deformation, Eco-Systems, and Dynamics of Ice Radar (DESDynI-R) L-band SAR instrument employs multiple digital channels to optimize resolution while keeping a large swath on a single pass. High-speed digitization with very fine synchronization and digital beam forming are necessary in order to facilitate this new technique. The Quad First Stage Processor (qFSP) was developed to achieve both the processing performance as well as the digitizing fidelity in order to accomplish this sweeping SAR technique. The qFSP utilizes high precision and high-speed analog to digital converters (ADCs), each with a finely adjustable clock distribution network to digitize the channels at the fidelity necessary to allow for digital beam forming. The Xilinx produced FX130T Virtex 5 part handles the processing to digitally calibrate each channel as well as filter and beam form the receive signals. Demonstrating the digital processing required for digital beam forming and digital calibration is instrumental to the viability of the proposed DESDynI instrument. The qFSP development brings this implementation to Technology Readiness Level (TRL) 6. This paper will detail the design and development of the prototype qFSP as well as the preliminary results from hardware tests.

  4. The ATLAS barrel level-1 Muon Trigger Sector-Logic/RX off-detector trigger and acquisition board

    CERN Document Server

    Chiodi, G; Petrolo, E; Pastore, F; Salamon, A; Vari, R; Veneziano, S

    2007-01-01

    The ATLAS experiment uses a system of three concentric layers of Resistive Plate Chambers (RPC) detector for the Level-1 Muon Trigger in the air-core barrel toroid region. The trigger algorithm looks for hit coincidences within different detector layers inside the programmable geometrical road which defines the transverse momentum cut. The on-detector electronics that provides the trigger and detector readout functionalities collects input signals coming from the RPC front-end. Trigger and readout data are then sent via optical fibres to the off-detector electronics. Six or seven optical fibres from one of the 64 trigger sectors go to one Sector-Logic/RX module, that later elaborates the collected trigger and readout data, and sends data respectively to the Read-Out Driver modules and to the Central Level-1 Trigger. We present the functionality and the implementation of the VME Sector-Logic/RX module, and the configuration of the system for the first cosmic ray data collected using this module.

  5. Advanced control system for the Integral Fast Reactor fuel pin processor

    International Nuclear Information System (INIS)

    A computerized control system has been developed for the remotely-operated fuel pin processor used in the Integral Fast Reactor Program, Fuel Cycle Facility (FCF). The pin processor remotely shears cast EBR- reactor fuel pins to length, inspects them for diameter, straightness, length, and weight, and then inserts acceptable pins into new sodium-loaded stainless-steel fuel element jackets. Two main components comprise the control system: (1) a programmable logic controller (PLC), together with various input/output modules and associated relay ladder-logic associated computer software. The PLC system controls the remote operation of the machine as directed by the OCS, and also monitors the machine operation to make operational data available to the OCS. The OCS allows operator control of the machine, provides nearly real-time viewing of the operational data, allows on-line changes of machine operational parameters, and records the collected data for each acceptable pin on a central data archiving computer. The two main components of the control system provide the operator with various levels of control ranging from manual operation to completely automatic operation by means of a graphic touch screen interface

  6. Scientific programming on massively parallel processor CP-PACS

    International Nuclear Information System (INIS)

    The massively parallel processor CP-PACS takes various problems of calculation physics as the object, and it has been designed so that its architecture has been devised to do various numerical processings. In this report, the outline of the CP-PACS and the example of programming in the Kernel CG benchmark in NAS Parallel Benchmarks, version 1, are shown, and the pseudo vector processing mechanism and the parallel processing tuning of scientific and technical computation utilizing the three-dimensional hyper crossbar net, which are two great features of the architecture of the CP-PACS are described. As for the CP-PACS, the PUs based on RISC processor and added with pseudo vector processor are used. Pseudo vector processing is realized as the loop processing by scalar command. The features of the connection net of PUs are explained. The algorithm of the NPB version 1 Kernel CG is shown. The part that takes the time for processing most in the main loop is the product of matrix and vector (matvec), and the parallel processing of the matvec is explained. The time for the computation by the CPU is determined. As the evaluation of the performance, the evaluation of the time for execution, the short vector processing of pseudo vector processor based on slide window, and the comparison with other parallel computers are reported. (K.I.)

  7. PVM Enhancement for Beowulf Multiple-Processor Nodes

    Science.gov (United States)

    Springer, Paul

    2006-01-01

    A recent version of the Parallel Virtual Machine (PVM) computer program has been enhanced to enable use of multiple processors in a single node of a Beowulf system (a cluster of personal computers that runs the Linux operating system). A previous version of PVM had been enhanced by addition of a software port, denoted BEOLIN, that enables the incorporation of a Beowulf system into a larger parallel processing system administered by PVM, as though the Beowulf system were a single computer in the larger system. BEOLIN spawns tasks on (that is, automatically assigns tasks to) individual nodes within the cluster. However, BEOLIN does not enable the use of multiple processors in a single node. The present enhancement adds support for a parameter in the PVM command line that enables the user to specify which Internet Protocol host address the code should use in communicating with other Beowulf nodes. This enhancement also provides for the case in which each node in a Beowulf system contains multiple processors. In this case, by making multiple references to a single node, the user can cause the software to spawn multiple tasks on the multiple processors in that node.

  8. Interactive high-resolution isosurface ray casting on multicore processors.

    Science.gov (United States)

    Wang, Qin; JaJa, Joseph

    2008-01-01

    We present a new method for the interactive rendering of isosurfaces using ray casting on multi-core processors. This method consists of a combination of an object-order traversal that coarsely identifies possible candidate 3D data blocks for each small set of contiguous pixels, and an isosurface ray casting strategy tailored for the resulting limited-size lists of candidate 3D data blocks. While static screen partitioning is widely used in the literature, our scheme performs dynamic allocation of groups of ray casting tasks to ensure almost equal loads among the different threads running on multi-cores while maintaining spatial locality. We also make careful use of memory management environment commonly present in multi-core processors. We test our system on a two-processor Clovertown platform, each consisting of a Quad-Core 1.86-GHz Intel Xeon Processor, for a number of widely different benchmarks. The detailed experimental results show that our system is efficient and scalable, and achieves high cache performance and excellent load balancing, resulting in an overall performance that is superior to any of the previous algorithms. In fact, we achieve an interactive isosurface rendering on a 1024(2) screen for all the datasets tested up to the maximum size of the main memory of our platform.

  9. Optical linear algebra processors: noise and error-source modeling.

    Science.gov (United States)

    Casasent, D; Ghosh, A

    1985-06-01

    The modeling of system and component noise and error sources in optical linear algebra processors (OLAP's) are considered, with attention to the frequency-multiplexed OLAP. General expressions are obtained for the output produced as a function of various component errors and noise. A digital simulator for this model is discussed.

  10. A 16-Bit Fully Functional Single Cycle Processor

    Directory of Open Access Journals (Sweden)

    Nidhi Maheshwari

    2011-08-01

    Full Text Available The existing commercial microprocessors are provided as black box units, with which users are unable to monitor internal signals and operation process, neither can they modify the original structure. Inorder to solve this problem 16-bit fully functional single cycle processor is designed in terms of its architecture and its functional capabilities. The procedure of design and verification for a 16-bit processor is introduced in this paper. The key architecture elements are being described, as well as the hardware block diagram and internal structure. The summary of instruction set is presented. This processor is modify as a Very High Speed Integrated Circuit Hardware Description Language (VHDL and gives access to every internal signal. In order to consume fewer resources, the design of arithmetic logical unit (ALU is optimized. The RTL views and verified simulation results of processor are shown in this paper. The synthesis report of the design is also described. The design architecture is written in Very High Speed Integrated Circuit Hardware Description Language (VHDL code using Xilinx ISE 9.2i tool for synthesis and simulation.

  11. Design of an integrated fuel processor for residential PEMFCs applications

    Science.gov (United States)

    Seo, Yu Taek; Seo, Dong Joo; Jeong, Jin Hyeok; Yoon, Wang Lai

    KIER has been developing a novel fuel processing system to provide hydrogen rich gas to residential PEMFCs system. For the effective design of a compact hydrogen production system, each unit process for steam reforming and water gas shift, has a steam generator and internal heat exchangers which are thermally and physically integrated into a single packaged hardware system. The newly designed fuel processor (prototype II) showed a thermal efficiency of 78% as a HHV basis with methane conversion of 89%. The preferential oxidation unit with two staged cascade reactors, reduces, the CO concentration to below 10 ppm without complicated temperature control hardware, which is the prerequisite CO limit for the PEMFC stack. After we achieve the initial performance of the fuel processor, partial load operation was carried out to test the performance and reliability of the fuel processor at various loads. The stability of the fuel processor was also demonstrated for three successive days with a stable composition of product gas and thermal efficiency. The CO concentration remained below 10 ppm during the test period and confirmed the stable performance of the two-stage PrOx reactors.

  12. MGSim - simulation tools for multi-core processor architectures

    NARCIS (Netherlands)

    M. Lankamp; R. Poss; Q. Yang; J. Fu; I. Uddin; C.R. Jesshope

    2013-01-01

    MGSim is an open source discrete event simulator for on-chip hardware components, developed at the University of Amsterdam. It is intended to be a research and teaching vehicle to study the fine-grained hardware/software interactions on many-core and hardware multithreaded processors. It includes su

  13. 50 CFR 648.6 - Dealer/processor permits.

    Science.gov (United States)

    2010-10-01

    ... provided in subpart D of 15 CFR part 904, the Regional Administrator will issue a permit at any time during..., suspended, or modified under 15 CFR part 904, or otherwise expires, or ownership changes, or the applicant... 50 Wildlife and Fisheries 8 2010-10-01 2010-10-01 false Dealer/processor permits. 648.6...

  14. Using a Multicore Processor for Rover Autonomous Science

    Science.gov (United States)

    Bornstein, Benjamin; Estlin, Tara; Clement, Bradley; Springer, Paul

    2011-01-01

    Multicore processing promises to be a critical component of future spacecraft. It provides immense increases in onboard processing power and provides an environment for directly supporting fault-tolerant computing. This paper discusses using a state-of-the-art multicore processor to efficiently perform image analysis onboard a Mars rover in support of autonomous science activities.

  15. Scientific kernels on VIRAM and imagine media processors

    Energy Technology Data Exchange (ETDEWEB)

    Narayanan, Manikamdan; Oliker, Leonid; Janin, Adam; Husbands,Parry; Li, Xiaoye S.

    2002-10-10

    Many high performance applications run well below the peak arithmetic performance of the underlying machine, with inefficiencies often attributed to a lack of memory bandwidth. In this work we examine two emerging media processors designed to address the well-known gap between processor and memory performance, in the context of scientific computing. The VIRAM architecture uses novel PIM technology to combine embedded DRAM with a vector co-processor for exploiting its large bandwidth potential. The Imagine architecture, on the other hand, provides a stream-aware memory hierarchy to support the tremendous processing potential of the SIMD controlled VLIW clusters. First we develop a scalable synthetic probe that allows us to parametize key performance attributes of VIRAM and Imagine while capturing the performance crossover point of these architectures. Next we present results for two important scientific kernels each with a unique set of computational characteristics and memory access patterns. Our experiments isolate the set of application characteristics best suited for each architecture and show a promising direction towards interfacing leading-edge media processor technology with high-end scientific computations.

  16. Performance evaluation of H.264 decoder on different processors

    Directory of Open Access Journals (Sweden)

    H.S.Prasantha

    2010-08-01

    Full Text Available H.264/AVC (Advanced Video Coding is the newest video coding standard of the moving video coding experts group. The decoder is standardized by imposing restrictions on the bit stream and syntax, and defining the process of decoding syntax elements such that every decoder conforming to the standard will produce similar output when encoded bit stream is provided as input. It uses state of art coding tools and provides enhanced coding efficiency for a wide range of applications, including video telephony, real-time video conferencing, direct-broadcast TV (television, blue-ray disc, DVB (Digital video broadcast broadcast, streaming video and others. The paper proposes to port the H.264/AVC decoder on the various processors such as TI DSP (Digital signal processor, ARM (Advanced risk machines and P4 (Pentium processors. The paper also proposesto analyze and compare Video Quality Metrics for different encoded video sequences. The paper proposes to investigate the decoder performance on different processors with and without deblocking filter and compare the performance based on different video quality measures.

  17. A design of a computer complex including vector processors

    International Nuclear Information System (INIS)

    We, members of the Computing Center, Japan Atomic Energy Research Institute have been engaged for these six years in the research of adaptability of vector processing to large-scale nuclear codes. The research has been done in collaboration with researchers and engineers of JAERI and a computer manufacturer. In this research, forty large-scale nuclear codes were investigated from the viewpoint of vectorization. Among them, twenty-six codes were actually vectorized and executed. As the results of the investigation, it is now estimated that about seventy percents of nuclear codes and seventy percents of our total amount of CPU time of JAERI are highly vectorizable. Based on the data obtained by the investigation, (1)currently vectorizable CPU time, (2)necessary number of vector processors, (3)necessary manpower for vectorization of nuclear codes, (4)computing speed, memory size, number of parallel 1/0 paths, size and speed of 1/0 buffer of vector processor suitable for our applications, (5)necessary software and operational policy for use of vector processors are discussed, and finally (6)a computer complex including vector processors is presented in this report. (author)

  18. Two new directions in speech processor design for cochlear implants.

    Science.gov (United States)

    Wilson, Blake S; Schatzer, Reinhold; Lopez-Poveda, Enrique A; Sun, Xiaoan; Lawson, Dewey T; Wolford, Robert D

    2005-08-01

    Two new approaches to the design of speech processors for cochlear implants are described. The first aims to represent "fine structure" or "fine frequency" information in a way that it can be perceived and used by patients, and the second aims to provide a closer mimicking than was previously possible of the signal processing that occurs in the normal cochlea.

  19. The LOGO Processor; A Guide for System Programmers.

    Science.gov (United States)

    Weiner, Walter B.; And Others

    A detailed specification of the LOGO programing system is given. The level of description is intended to enable system programers to design LOGO processors of their own. The discussion of storage allocation and garbage collection algorithms is virtually complete. An annotated LOGO system listing for the PDP-10 computer system may be obtained on…

  20. A Software Implementation of a Satellite Interface Message Processor.

    Science.gov (United States)

    Eastwood, Margaret A.; Eastwood, Lester F., Jr.

    A design for network control software for a computer network is described in which some nodes are linked by a communications satellite channel. It is assumed that the network has an ARPANET-like configuration; that is, that specialized processors at each node are responsible for message switching and network control. The purpose of the control…

  1. Experiences with Compiler Support for Processors with Exposed Pipelines

    DEFF Research Database (Denmark)

    Jensen, Nicklas Bo; Schleuniger, Pascal; Hindborg, Andreas Erik;

    2015-01-01

    Field programmable gate arrays, FPGAs, have become an attractive implementation technology for a broad range of computing systems. We recently proposed a processor architecture, Tinuso, which achieves high performance by moving complexity from hardware to the compiler tool chain. This means that ...

  2. Scientific programming on massively parallel processor CP-PACS

    Energy Technology Data Exchange (ETDEWEB)

    Boku, Taisuke [Tsukuba Univ., Ibaraki (Japan). Inst. of Information Sciences and Electronics

    1998-03-01

    The massively parallel processor CP-PACS takes various problems of calculation physics as the object, and it has been designed so that its architecture has been devised to do various numerical processings. In this report, the outline of the CP-PACS and the example of programming in the Kernel CG benchmark in NAS Parallel Benchmarks, version 1, are shown, and the pseudo vector processing mechanism and the parallel processing tuning of scientific and technical computation utilizing the three-dimensional hyper crossbar net, which are two great features of the architecture of the CP-PACS are described. As for the CP-PACS, the PUs based on RISC processor and added with pseudo vector processor are used. Pseudo vector processing is realized as the loop processing by scalar command. The features of the connection net of PUs are explained. The algorithm of the NPB version 1 Kernel CG is shown. The part that takes the time for processing most in the main loop is the product of matrix and vector (matvec), and the parallel processing of the matvec is explained. The time for the computation by the CPU is determined. As the evaluation of the performance, the evaluation of the time for execution, the short vector processing of pseudo vector processor based on slide window, and the comparison with other parallel computers are reported. (K.I.)

  3. Evaluation of the Intel Westmere-EP server processor

    CERN Document Server

    Jarp, S; Leduc, J; Nowak, A; CERN. Geneva. IT Department

    2010-01-01

    In this paper we report on a set of benchmark results recently obtained by CERN openlab when comparing the 6-core “Westmere-EP” processor with Intel’s previous generation of the same microarchitecture, the “Nehalem-EP”. The former is produced in a new 32nm process, the latter in 45nm. Both platforms are dual-socket servers. Multiple benchmarks were used to get a good understanding of the performance of the new processor. We used both industry-standard benchmarks, such as SPEC2006, and specific High Energy Physics benchmarks, representing both simulation of physics detectors and data analysis of physics events. Before summarizing the results we must stress the fact that benchmarking of modern processors is a very complex affair. One has to control (at least) the following features: processor frequency, overclocking via Turbo mode, the number of physical cores in use, the use of logical cores via Simultaneous Multi-Threading (SMT), the cache sizes available, the memory configuration installed, as well...

  4. Evaluation of the Intel Nehalem-EX server processor

    CERN Document Server

    Jarp, S; Leduc, J; Nowak, A; CERN. Geneva. IT Department

    2010-01-01

    In this paper we report on a set of benchmark results recently obtained by the CERN openlab by comparing the 4-socket, 32-core Intel Xeon X7560 server with the previous generation 4-socket server, based on the Xeon X7460 processor. The Xeon X7560 processor represents a major change in many respects, especially the memory sub-system, so it was important to make multiple comparisons. In most benchmarks the two 4-socket servers were compared. It should be underlined that both servers represent the “top of the line” in terms of frequency. However, in some cases, it was important to compare systems that integrated the latest processor features, such as QPI links, Symmetric multithreading and over-clocking via Turbo mode, and in such situations the X7560 server was compared to a dual socket L5520 based system with an identical frequency of 2.26 GHz. Before summarizing the results we must stress the fact that benchmarking of modern processors is a very complex affair. One has to control (at least) the following ...

  5. Efficient Multicriteria Protein Structure Comparison on Modern Processor Architectures.

    Science.gov (United States)

    Sharma, Anuj; Manolakos, Elias S

    2015-01-01

    Fast increasing computational demand for all-to-all protein structures comparison (PSC) is a result of three confounding factors: rapidly expanding structural proteomics databases, high computational complexity of pairwise protein comparison algorithms, and the trend in the domain towards using multiple criteria for protein structures comparison (MCPSC) and combining results. We have developed a software framework that exploits many-core and multicore CPUs to implement efficient parallel MCPSC in modern processors based on three popular PSC methods, namely, TMalign, CE, and USM. We evaluate and compare the performance and efficiency of the two parallel MCPSC implementations using Intel's experimental many-core Single-Chip Cloud Computer (SCC) as well as Intel's Core i7 multicore processor. We show that the 48-core SCC is more efficient than the latest generation Core i7, achieving a speedup factor of 42 (efficiency of 0.9), making many-core processors an exciting emerging technology for large-scale structural proteomics. We compare and contrast the performance of the two processors on several datasets and also show that MCPSC outperforms its component methods in grouping related domains, achieving a high F-measure of 0.91 on the benchmark CK34 dataset. The software implementation for protein structure comparison using the three methods and combined MCPSC, along with the developed underlying rckskel algorithmic skeletons library, is available via GitHub. PMID:26605332

  6. The hardware track finder processor in CMS at CERN

    CERN Document Server

    Kluge, A

    1997-01-01

    The work covers the design of the Track Finder Processor in the high energy experiment CMS (Compact Muon Solenoid, planned for 2005) at CERN/Geneva. The task of this processor is to identify muons and measure their transverse momentum. The track finder processor makes it possible to determine the physical relevance of each high energetic collision and to forward only interesting data to the data an alysis units. Data of more than two hundred thousand detector cells are used to determine the location of muons and measure their transverse momentum. Each 25 ns a new data set is generated. Measurem ent of location and transverse momentum of the muons can be terminated within 350 ns by using an ASIC (Application Specific Integrated Circuit). A pipeline architecture processes new data sets with th e required data rate of 40 MHz to ensure dead time free operation. In the framework of this study specifications and the overall concept of the track finder processor were worked out in detail. Simul ations were performed...

  7. The ATLAS FTK system: how to improve the physics potential with a tracking trigger

    CERN Document Server

    Iizawa, T; The ATLAS collaboration

    2014-01-01

    After a very successful data taking run, the ATLAS experiment [1] is being upgraded to cope with the higher luminosity and higher center of mass energy that the Large Hadron Collider (LHC) will provide in the next years. The Fast Tracker (FTK) trigger system, part of the ATLAS trigger upgrade program, is a highly parallel hardware device processor based on a mixture of advanced technologies. Modern, powerful Field Programmable Gate Arrays (FPGAs) form an important part of the system architecture, and the large level of computing power required for pattern recognition is provided by incorporating standard-cell ASICs named Associative Memory (AM). FTK provides global track reconstruction in the full inner silicon detector, with resolution comparable to the offline algorithms, in approximately 100 microseconds, allowing a fast and precise detection of the primary and secondary vertex information. The track and vertex information is then used by the high-level trigger (HLT) algorithms, allowing highly improved tr...

  8. The ATLAS FTK system: how to improve the physics potential with a tracking trigger

    CERN Document Server

    Iizawa, T; The ATLAS collaboration

    2014-01-01

    After a very successful data taking run, the ATLAS experiment is being upgraded to cope with the higher luminosity and higher center of mass energy that the Large Hadron Collider will provide in the next years. The Fast Tracker (FTK) trigger system, part of the ATLAS trigger upgrade program, is a highly parallel hardware device designed to operate at the level-1 trigger output rate. FTK is a dedicated processor based on a mixture of advanced technologies. Modern, powerful Field Programmable Gate Arrays (FPGAs) form an important part of the system architecture, and the large level of computing power required for pattern recognition is provided by incorporating standard-cell ASICs named Associative Memories (AM). FTK provides global track reconstruction in the full inner silicon detector, with resolution comparable to the offline algorithms, in approximately 100 microseconds, allowing a fast and precise detection of the primary and secondary vertex information. The track and vertex information is then used by t...

  9. Triggered Release from Polymer Capsules

    Energy Technology Data Exchange (ETDEWEB)

    Esser-Kahn, Aaron P. [Univ. of Illinois, Urbana, IL (United States). Beckman Inst. for Advanced Science and Technology and Dept. of Chemistry; Odom, Susan A. [Univ. of Illinois, Urbana, IL (United States). Beckman Inst. for Advanced Science and Technology and Dept. of Chemistry; Sottos, Nancy R. [Univ. of Illinois, Urbana, IL (United States). Beckman Inst. for Advanced Science and Technology and Dept. of Materials Science and Engineering; White, Scott R. [Univ. of Illinois, Urbana, IL (United States). Beckman Inst. for Advanced Science and Technology and Dept. of Aerospace Engineering; Moore, Jeffrey S. [Univ. of Illinois, Urbana, IL (United States). Beckman Inst. for Advanced Science and Technology and Dept. of Chemistry

    2011-07-06

    Stimuli-responsive capsules are of interest in drug delivery, fragrance release, food preservation, and self-healing materials. Many methods are used to trigger the release of encapsulated contents. Here we highlight mechanisms for the controlled release of encapsulated cargo that utilize chemical reactions occurring in solid polymeric shell walls. Triggering mechanisms responsible for covalent bond cleavage that result in the release of capsule contents include chemical, biological, light, thermal, magnetic, and electrical stimuli. We present methods for encapsulation and release, triggering methods, and mechanisms and conclude with our opinions on interesting obstacles for chemically induced activation with relevance for controlled release.

  10. Automotive Fuel Processor Development and Demonstration with Fuel Cell Systems

    Energy Technology Data Exchange (ETDEWEB)

    Nuvera Fuel Cells

    2005-04-15

    The potential for fuel cell systems to improve energy efficiency and reduce emissions over conventional power systems has generated significant interest in fuel cell technologies. While fuel cells are being investigated for use in many applications such as stationary power generation and small portable devices, transportation applications present some unique challenges for fuel cell technology. Due to their lower operating temperature and non-brittle materials, most transportation work is focusing on fuel cells using proton exchange membrane (PEM) technology. Since PEM fuel cells are fueled by hydrogen, major obstacles to their widespread use are the lack of an available hydrogen fueling infrastructure and hydrogen's relatively low energy storage density, which leads to a much lower driving range than conventional vehicles. One potential solution to the hydrogen infrastructure and storage density issues is to convert a conventional fuel such as gasoline into hydrogen onboard the vehicle using a fuel processor. Figure 2 shows that gasoline stores roughly 7 times more energy per volume than pressurized hydrogen gas at 700 bar and 4 times more than liquid hydrogen. If integrated properly, the fuel processor/fuel cell system would also be more efficient than traditional engines and would give a fuel economy benefit while hydrogen storage and distribution issues are being investigated. Widespread implementation of fuel processor/fuel cell systems requires improvements in several aspects of the technology, including size, startup time, transient response time, and cost. In addition, the ability to operate on a number of hydrocarbon fuels that are available through the existing infrastructure is a key enabler for commercializing these systems. In this program, Nuvera Fuel Cells collaborated with the Department of Energy (DOE) to develop efficient, low-emission, multi-fuel processors for transportation applications. Nuvera's focus was on (1) developing fuel

  11. Dry needling — peripheral and central considerations

    OpenAIRE

    Dommerholt, Jan

    2011-01-01

    Dry needling is a common treatment technique in orthopedic manual physical therapy. Although various dry needling approaches exist, the more common and best supported approach targets myofascial trigger points. This article aims to place trigger point dry needling within the context of pain sciences. From a pain science perspective, trigger points are constant sources of peripheral nociceptive input leading to peripheral and central sensitization. Dry needling cannot only reverse some aspects...

  12. Compact propane fuel processor for auxiliary power unit application

    Science.gov (United States)

    Dokupil, M.; Spitta, C.; Mathiak, J.; Beckhaus, P.; Heinzel, A.

    With focus on mobile applications a fuel cell auxiliary power unit (APU) using liquefied petroleum gas (LPG) is currently being developed at the Centre for Fuel Cell Technology (Zentrum für BrennstoffzellenTechnik, ZBT gGmbH). The system is consisting of an integrated compact and lightweight fuel processor and a low temperature PEM fuel cell for an electric power output of 300 W. This article is presenting the current status of development of the fuel processor which is designed for a nominal hydrogen output of 1 k Wth,H2 within a load range from 50 to 120%. A modular setup was chosen defining a reformer/burner module and a CO-purification module. Based on the performance specifications, thermodynamic simulations, benchmarking and selection of catalysts the modules have been developed and characterised simultaneously and then assembled to the complete fuel processor. Automated operation results in a cold startup time of about 25 min for nominal load and carbon monoxide output concentrations below 50 ppm for steady state and dynamic operation. Also fast transient response of the fuel processor at load changes with low fluctuations of the reformate gas composition have been achieved. Beside the development of the main reactors the transfer of the fuel processor to an autonomous system is of major concern. Hence, concepts for packaging have been developed resulting in a volume of 7 l and a weight of 3 kg. Further a selection of peripheral components has been tested and evaluated regarding to the substitution of the laboratory equipment.

  13. A programmable sound processor for advanced hearing aid research.

    Science.gov (United States)

    McDermott, H

    1998-03-01

    A portable sound processor has been developed to facilitate research on advanced hearing aids. Because it is based on a digital signal processing integrated circuit (Motorola DSP56001), it can readily be programmed to execute novel algorithms. Furthermore, the parameters of these algorithms can be adjusted quickly and easily to suit the specific hearing characteristics of users. In the processor, microphone signals are digitized to a precision of 12 bits at a sampling rate of approximately 12 kHz for input to the DSP device. Subsequently, processed samples are delivered to the earphone by a novel, fully-digital class-D driver. This driver provides the advantages of a conventional class-D amplifier (high maximum output, low power consumption, low distortion) without some of the disadvantages (such as the need for precise analog circuitry). In addition, a cochlear implant driver is provided so that the processor is suitable for hearing-impaired people who use an implant and an acoustic hearing aid together. To reduce the computational demands on the DSP device, and therefore the power consumption, a running spectral analysis of incoming signals is provided by a custom-designed switched-capacitor integrated circuit incorporating 20 bandpass filters. The complete processor is pocket-sized and powered by batteries. An example is described of its use in providing frequency-shaped amplification for aid users with severe hearing impairment. Speech perception tests confirmed that the processor performed significantly better than the subjects' own hearing aids, probably because the digital filter provided a frequency response generally closer to the optimum for each user than the simpler analog aids.

  14. HTGR core seismic analysis using an array processor

    International Nuclear Information System (INIS)

    A Floating Point Systems array processor performs nonlinear dynamic analysis of the high-temperature gas-cooled reactor (HTGR) core with significant time and cost savings. The graphite HTGR core consists of approximately 8000 blocks of various shapes which are subject to motion and impact during a seismic event. Two-dimensional computer programs (CRUNCH2D, MCOCO) can perform explicit step-by-step dynamic analyses of up to 600 blocks for time-history motions. However, use of two-dimensional codes was limited by the large cost and run times required. Three-dimensional analysis of the entire core, or even a large part of it, had been considered totally impractical. Because of the needs of the HTGR core seismic program, a Floating Point Systems array processor was used to enhance computer performance of the two-dimensional core seismic computer programs, MCOCO and CRUNCH2D. This effort began by converting the computational algorithms used in the codes to a form which takes maximum advantage of the parallel and pipeline processors offered by the architecture of the Floating Point Systems array processor. The subsequent conversion of the vectorized FORTRAN coding to the array processor required a significant programming effort to make the system work on the General Atomic (GA) UNIVAC 1100/82 host. These efforts were quite rewarding, however, since the cost of running the codes has been reduced approximately 50-fold and the time threefold. The core seismic analysis with large two-dimensional models has now become routine and extension to three-dimensional analysis is feasible. These codes simulate the one-fifth-scale full-array HTGR core model. This paper compares the analysis with the test results for sine-sweep motion

  15. FERMIGTRIG - Fermi GBM Trigger Catalog

    Data.gov (United States)

    National Aeronautics and Space Administration — This table lists all of the triggers observed by one or more of the 14 GBM detectors (12 NaI and 2 BGO). Note that there are two Browse catalogs resulting from GBM...

  16. NaNet:a low-latency NIC enabling GPU-based, real-time low level trigger systems

    CERN Document Server

    Ammendola, Roberto; Fantechi, Riccardo; Frezza, Ottorino; Lamanna, Gianluca; Cicero, Francesca Lo; Lonardo, Alessandro; Paolucci, Pier Stanislao; Pantaleo, Felice; Piandani, Roberto; Pontisso, Luca; Rossetti, Davide; Simula, Francesco; Sozzi, Marco; Tosoratto, Laura; Vicini, Piero

    2014-01-01

    We implemented the NaNet FPGA-based PCI2 Gen2 GbE/APElink NIC, featuring GPUDirect RDMA capabilities and UDP protocol management offloading. NaNet is able to receive a UDP input data stream from its GbE interface and redirect it, without any intermediate buffering or CPU intervention, to the memory of a Fermi/Kepler GPU hosted on the same PCIe bus, provided that the two devices share the same upstream root complex. Synthetic benchmarks for latency and bandwidth are presented. We describe how NaNet can be employed in the prototype of the GPU-based RICH low-level trigger processor of the NA62 CERN experiment, to implement the data link between the TEL62 readout boards and the low level trigger processor. Results for the throughput and latency of the integrated system are presented and discussed.

  17. NaNet: a low-latency NIC enabling GPU-based, real-time low level trigger systems

    Science.gov (United States)

    Ammendola, Roberto; Biagioni, Andrea; Fantechi, Riccardo; Frezza, Ottorino; Lamanna, Gianluca; Lo Cicero, Francesca; Lonardo, Alessandro; Stanislao Paolucci, Pier; Pantaleo, Felice; Piandani, Roberto; Pontisso, Luca; Rossetti, Davide; Simula, Francesco; Sozzi, Marco; Tosoratto, Laura; Vicini, Piero

    2014-06-01

    We implemented the NaNet FPGA-based PCIe Gen2 GbE/APElink NIC, featuring GPUDirect RDMA capabilities and UDP protocol management offloading. NaNet is able to receive a UDP input data stream from its GbE interface and redirect it, without any intermediate buffering or CPU intervention, to the memory of a Fermi/Kepler GPU hosted on the same PCIe bus, provided that the two devices share the same upstream root complex. Synthetic benchmarks for latency and bandwidth are presented. We describe how NaNet can be employed in the prototype of the GPU-based RICH low-level trigger processor of the NA62 CERN experiment, to implement the data link between the TEL62 readout boards and the low level trigger processor. Results for the throughput and latency of the integrated system are presented and discussed.

  18. B physics triggers at CMS

    OpenAIRE

    Starodumov, A.(Institute for Particle Physics, ETH Zurich, Zurich, Switzerland)

    2003-01-01

    The CMS detector is mainly designed to investigate hard events. Only few Level-1 Trigger conditions are suitable to select soft B-meson decays. The B-physics potential of CMS depends strongly on a selection strategy at High-Level Trigger. The selection algorithms for some benchmark B-decay channels that allow CMS to perform competitive B-physics program are presented.

  19. A Highly Parallel FPGA Implementation of a 2D-Clustering Algorithm for the ATLAS Fast TracKer (FTK) Processor

    CERN Document Server

    Kimura, N; The ATLAS collaboration; Beretta, M; Gatta, M; Gkaitatzis, S; Iizawa, T; Kordas, K; Korikawa, T; Nikolaidis, N; Petridou, P; Sotiropoulou, C-L; Yorita, K; Volpi, G

    2014-01-01

    The highly parallel 2D-clustering FPGA implementation used for the input system of the ATLAS Fast TracKer (FTK) processor is presented. The input system for the FTK processor will receive data from the Pixel and micro-strip detectors read out drivers (RODs) at 760Gbps, the full rate of level 1 triggers. Clustering serves two purposes. The first is to reduce the high rate of the received data before further processing. The second is to determine the cluster centroid to obtain the best spatial measurement. For the pixel detectors the clustering is implemented by using a 2D-clustering algorithm that takes advantage of a moving window technique to minimize the logic required for cluster identification. The implementation is fully generic, therefore the detection window size can be optimized for the cluster identification process. Additionally, the implementation can be parallelized by instantiating multiple cores to identify different clusters independently thus exploiting more FPGA resources. This flexibility ma...

  20. The ELETTRA Gun Trigger module

    International Nuclear Information System (INIS)

    The ELETTRA injector is a full energy Linac. The Linac and the pulsed magnets need to be synchronized with the beam in the storage ring in order to fill it with the proper bunch pattern. Most of the triggers for the timing system are generated by a module which is named Gun Trigger module. The gun is triggered in synchronism with a reference bucket of the storage ring. It can be programmed with a delay between 2 and 864 ns, a range which covers one revolution period of the storage ring, so any arbitrary bucket of the ring can be filled. The module generates also the gun trigger for working in FEL mode, which needs a repetition from 30 to 50 ns in a 10 μs window. The jitter of all these triggers is less than 50 ps. The Gun Trigger module is developed in VMEbus standard, using TTL and ECL technology. It is remotely programmable through the ELETTRA control system. The general architecture of the ELETTRA timing system is also described in the paper