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Sample records for boot-strapped full-bridge mosfet

  1. Performance of an SOI Boot-Strapped Full-Bridge MOSFET Driver, Type CHT-FBDR, under Extreme Temperatures

    Science.gov (United States)

    Patterson, Richard; Hammoud, Ahmad

    2009-01-01

    Electronic systems designed for use in deep space and planetary exploration missions are expected to encounter extreme temperatures and wide thermal swings. Silicon-based devices are limited in their wide-temperature capability and usually require extra measures, such as cooling or heating mechanisms, to provide adequate ambient temperature for proper operation. Silicon-On-Insulator (SOI) technology, on the other hand, lately has been gaining wide spread use in applications where high temperatures are encountered. Due to their inherent design, SOI-based integrated circuit chips are able to operate at temperatures higher than those of the silicon devices by virtue of reducing leakage currents, eliminating parasitic junctions, and limiting internal heating. In addition, SOI devices provide faster switching, consume less power, and offer improved radiation-tolerance. Very little data, however, exist on the performance of such devices and circuits under cryogenic temperatures. In this work, the performance of an SOI bootstrapped, full-bridge driver integrated circuit was evaluated under extreme temperatures and thermal cycling. The investigations were carried out to establish a baseline on the functionality and to determine suitability of this device for use in space exploration missions under extreme temperature conditions.

  2. High Performance ZVT with Bus Clamping Modulation Technique for Single Phase Full Bridge Inverters

    Energy Technology Data Exchange (ETDEWEB)

    Xia, Yinglai; Ayyanar, Raja

    2016-03-20

    This paper proposes a topology based on bus clamping modulation and zero-voltage-transition (ZVT) technique to realize zero-voltage-switching (ZVS) for all the main switches of the full bridge inverters, and inherent ZVS and/or ZCS for the auxiliary switches. The advantages of the strategy include significant reduction in the turn-on loss of the ZVT auxiliary switches which typically account for a major part of the total loss in other ZVT circuits, and reduction in the voltage ratings of auxiliary switches. The modulation scheme and the commutation stages are analyzed in detail. Finally, a 1kW, 500 kHz switching frequency inverter of the proposed topology using SiC MOSFETs has been built to validate the theoretical analysis. The ZVT with bus clamping modulation technique of fixed timing and adaptive timing schemes are implemented in DSP TMS320F28335 resulting in full ZVS for the main switches in the full bridge inverter. The proposed scheme can save up to 33 % of the switching loss compared with no ZVT case.

  3. Silicon Power MOSFETs

    Science.gov (United States)

    Lauenstein, Jean-Marie; Casey, Megan; Campola, Michael; Ladbury, Raymond; Label, Kenneth; Wilcox, Ted; Phan, Anthony; Kim, Hak; Topper, Alyson

    2017-01-01

    Recent work for the NASA Electronic Parts and Packaging Program Power MOSFET task is presented. The Task technology focus, roadmap, and partners are given. Recent single-event effect test results on commercial, automotive, and radiation hardened trench power MOSFETs are summarized with an emphasis on risk of using commercial and automotive trench-gate power MOSFETs in space applications.

  4. Perancangan Dan Simulasi Full Bridge Inverter Lima Tingkat Dengan Dual Buck Converter Terhubung Jaringan Satu Fasa

    OpenAIRE

    Fuadi, Zamratul; Ashari, Mochamad; Pamuji, Feby Agung

    2014-01-01

    Inverter merupakan perangkat elektronika daya yang berfungsi mengonversi sumber searah menjadi bolak-Balik. Full bridge inverter adalah satu jenisnya yang mampu menghasilkan tegangan tiga tingkat jika menggunakan teknik modulasi unipolar. Penambahan sirkuit dual buck converter pada full bridge inverter mampu menghasilkan tegangan dalam lima tingkat. Dua saklar pada rangkaian dual buck converter switching pada frekuensi tinggi 20 kHz, sedangkan empat saklar pada full bridge inver...

  5. Radiation sensitivity of MOSFET

    International Nuclear Information System (INIS)

    Labrunee, M.; Tastet, P.; Garnier, J.

    1988-01-01

    Power MOS (Metal Oxide Semiconductor) transistors are widely used in Energy Conversion and radiation sensitivity is important for Space applications. After a review of the characteristics and applications of a MOSFET, we present the radiation tests (electrons flux exposure), and a synthesis about their heavy ions sensitivity). A simulation method of the radiation effect on the MOSFET behaviour used in a power converter is given. Design rules for on board systems using MOSFET are precised [fr

  6. Strain-engineered MOSFETs

    CERN Document Server

    Maiti, CK

    2012-01-01

    Currently strain engineering is the main technique used to enhance the performance of advanced silicon-based metal-oxide-semiconductor field-effect transistors (MOSFETs). Written from an engineering application standpoint, Strain-Engineered MOSFETs introduces promising strain techniques to fabricate strain-engineered MOSFETs and to methods to assess the applications of these techniques. The book provides the background and physical insight needed to understand new and future developments in the modeling and design of n- and p-MOSFETs at nanoscale. This book focuses on recent developments in st

  7. Soft-switching PWM full-bridge converters topologies, control, and design

    CERN Document Server

    Ruan, Xinbo

    2014-01-01

    Soft-switching PWM full-bridge converters have been widely used in medium-to-high power dc-dc conversions for topological simplicity, easy control and high efficiency. Early works on soft-switching PWM full-bridge converter by many researchers included various topologies and modulation strategies.  However, these works were scattered, and the relationship among these topologies and modulation strategies had not been revealed. This book intends to describe systematically the soft-switching techniques for pulse-width modulation (PWM) full-bridge converters, including the topologies, control and

  8. Prognostics of Power MOSFET

    Data.gov (United States)

    National Aeronautics and Space Administration — This paper demonstrates how to apply prognostics to power MOSFETs (metal oxide field effect transistor). The methodology uses thermal cycling to age devices and...

  9. A Systematic Method to Synthesize New Transformerless Full-bridge Grid-tied Inverters

    DEFF Research Database (Denmark)

    Wang, Hongliang; Burton, Sarah; Liu, Yan-Fei

    2014-01-01

    Many inverter topologies have been proposed to eliminate the leakage current of transformerless Full Bridge Grid-Tied photovoltaic (PV) inverters. These include implementations such as the H5, H6, and HERIC topologies, among others. In this paper, a new full bridge topology synthesis method, called...... the MN synthesis method, is proposed. The MN method introduces two criteria that can be used to synthesize all of the possible topologies, including the existing topologies as well as new simplified topologies. This method concludes that there are only 15 simplified topologies available. Most simplified...... topologies from MN method have been verified by existing papers and patents....

  10. Simplified loss analysis and comparison of full-bridge, full-range ...

    Indian Academy of Sciences (India)

    The loss of zero-voltage-switching (ZVS) of active switches has been a serious limitation of full-bridge (FBZVS) converters. Many techniques have been proposed in the past to extend the range of ZVS operation over the wider and also the full range of operation. However, in these techniques ZVS is achieved at the expense ...

  11. Implications of Capacitor Voltage Imbalance on the Operation of the Semi-Full-Bridge Submodule

    OpenAIRE

    Heinig, Stefanie; Jacobs, Keijo; Ilves, Kalle; Norrga, Staffan; Nee, Hans-Peter

    2017-01-01

    An investigation of the voltage imbalance of the two capacitors of the semi-full-bridge submodule is performed. Since the capacitances are not exactly the same, there may be a difference between the capacitor voltages. The resulting current-spike when they are connected in parallel has been analyzed in a full-scale laboratory experiment. QC 20180109

  12. Control and design of full-bridge three-level converter for renewable energy sources

    DEFF Research Database (Denmark)

    Yao, Zhilei; Xu, Jing; Guerrero, Josep M.

    2015-01-01

    Output voltage of renewable energy sources, such as fuel cell and PV cell, is often low and varies widely with load and environmental conditions. Therefore, the high step-up DC-DC converter is needed between renewable energy sources and the grid-connected inverter. However, voltage stress...... of rectifier diodes is high and filter is large in traditional voltage-source converters in a wide input-voltage range. In order to solve the aforementioned problems, a full-bridge (FB) three-level (TL) converter is proposed. It can operate at both two-level and three-level modes, so it is suitable for wide...

  13. Modeling and control of isolated full bridge boost DC-DC converter implemented in FPGA

    DEFF Research Database (Denmark)

    Taeed, Fazel; Nymand, M.

    2013-01-01

    In this paper an isolated full bridge boost converter (IFBC) firstly is modeled. In the modeling part, a small signal equivalent of the converter is developed. From the small signal model, the converter transfer function is derived. Based on the obtained transfer function, challenges of controller...... design are discussed. In the next step a digital PI controller is designed and implemented in a FPGA to control the output voltage. Using the injection transformer method the open loop transfer function in closed loop is measured and modeling results are verified by experimental results....

  14. Soft Switching Full-Bridge PWM DC/DC Converter Using Secondary Snubber

    Directory of Open Access Journals (Sweden)

    Jaroslav Dudrik

    2009-05-01

    Full Text Available A novel full-bridge PWM DC/DCconverter with controlled secondary side rectifier usingsecondary snubber is presented in this paper.Limitation of the circulating current as well as softswitching for all power switches of the inverter isachieved for full load range from no-load to shortcircuit by using controlled rectifier and snubber on thesecondary side. Phase shift PWM control strategy isused for the converter. The principle of operation isexplained and analyzed and the experimental resultson a 1kW, 50 kHz laboratory model of the converterare presented.

  15. Common mode noise modeling and its suppression in ultra-high efficiency full bridge boost converter

    DEFF Research Database (Denmark)

    Makda, Ishtiyaq Ahmed; Nymand, Morten; Madawala, Udaya

    2013-01-01

    between input and output which is normally associated with high common mode noise generation. In this work, common mode noise sources in the converter are identified, and a common mode noise model is developed. Based on the established noise model, a practical CM filter is designed to comply......In this paper, common mode noise modeling of low-voltage high-current isolated full bridge boost dc-dc converters intended for fuel cell application is presented. Due to the tightly coupled primary and secondary windings of the transformer, such converter has inherently large capacitive coupling...

  16. Glass-melting using an IGBT full-bridge resonant converter

    International Nuclear Information System (INIS)

    Pacheco S, J.O.; Gutierrez O, E.; Benitez R, J.S.; Martinez V, J.; Lopez C, R.

    1999-01-01

    This work describes the design implementation and application of a full-bridge IGBT resonant converter used to obtain glass melting. The design procedure is discussed and complete converter schematics are provided, including drivers and control circuits. A brief review of the glass properties is given, and some coupling parameters of the induction furnace are also described. A very special provision is made to the coupling charge transformer and the heat induced to the glass itself, first by conduction, followed by direct electromagnetic induction when the glass becomes a conductor. A brief analysis of electromagnetic fields, current density and power induced in the material is given. A very simple method is presented to calculate the power absorbed by the load and therefore the efficiency of the heating process. Several tests are carried out to verify the effectiveness of this method. Finally, this paper describes the design and construction of a 5 k W, 50 k Hz Full-Bridge Resonant Converter (FBRC), based on IGBT transistors and a transformer-capacitor coupled to a thermal load composed of a metal-glass cylinder. For glass makers, the benefits obtained by implementing the melting system with an IGBT-based FRBC resides on the relative simplicity of its design, the low-cost of the components, the energy transfer efficiency, and the robustness of its operation. With a proper scaling, this melting system can be used, for instance, to vitrify hazardous industrial wastes, nuclear waste, and fume ashes from melting plants or combustion systems. (Author)

  17. One Curve Embedded Full-Bridge MMC Modeling Method with Detailed Representation of IGBT Characteristics

    Science.gov (United States)

    Hongyang, Yu; Zhengang, Lu; Xi, Yang

    2017-05-01

    Modular Multilevel Converter is more and more widely used in high voltage DC transmission system and high power motor drive system. It is a major topological structure for high power AC-DC converter. Due to the large module number, the complex control algorithm, and the high power user’s back ground, the MMC model used for simulation should be as accurate as possible to simulate the details of how MMC works for the dynamic testing of the MMC controller. But so far, there is no sample simulation MMC model which can simulate the switching dynamic process. In this paper, one curve embedded full-bridge MMC modeling method with detailed representation of IGBT characteristics is proposed. This method is based on the switching curve referring and sample circuit calculation, and it is sample for implementation. Based on the simulation comparison test under Matlab/Simulink, the proposed method is proved to be correct.

  18. Real-Time Model and Simulation Architecture for Half- and Full-Bridge Modular Multilevel Converters

    Science.gov (United States)

    Ashourloo, Mojtaba

    This work presents an equivalent model and simulation architecture for real-time electromagnetic transient analysis of either half-bridge or full-bridge modular multilevel converter (MMC) with 400 sub-modules (SMs) per arm. The proposed CPU/FPGA-based architecture is optimized for the parallel implementation of the presented MMC model on the FPGA and is beneficiary of a high-throughput floating-point computational engine. The developed real-time simulation architecture is capable of simulating MMCs with 400 SMs per arm at 825 nanoseconds. To address the difficulties of the sorting process implementation, a modified Odd-Even Bubble sorting is presented in this work. The comparison of the results under various test scenarios reveals that the proposed real-time simulator is representing the system responses in the same way of its corresponding off-line counterpart obtained from the PSCAD/EMTDC program.

  19. Atmospheric-pressure dielectric barrier discharge generation by a full-bridge flying capacitor multilevel inverter

    Science.gov (United States)

    Peña-Eguiluz, Rosendo; López-Fernández, José, A.; Mercado-Cabrera, Antonio; Jaramillo-Sierra, Bethsabet; López-Callejas, Régulo; Rodríguez-Méndez, Benjamín; Valencia-Alvarado, Raúl; Flores-Fuentes, Allan, A.; Muñoz-Castro, Arturo E.

    2017-07-01

    A new configuration of a resonant full-bridge flying capacitor multicell inverter has been designed and constructed with the aim of achieving an extended output voltage frequency range with low harmonic distortion and reduced semiconductor commutation losses. This configuration was tested as a power supply for two different coaxial dielectric barrier discharge reactors, one of them employed for electric characterization and the other one for inorganic compound elimination in an aqueous solution. Two different gas mixtures, 90% Ar-10% O2 and 80% Ar-20% O2, were individually supplied during the experiments; the results showed a high-efficiency removal of meta-cresol (m-cresol) to the order of 98%, which was obtained by adding more oxygen to the plasma gas mixture.

  20. Design of an improved RCD buffer circuit for full bridge circuit

    Science.gov (United States)

    Yang, Wenyan; Wei, Xueye; Du, Yongbo; Hu, Liang; Zhang, Liwei; Zhang, Ou

    2017-05-01

    In the full bridge inverter circuit, when the switch tube suddenly opened or closed, the inductor current changes rapidly. Due to the existence of parasitic inductance of the main circuit. Therefore, the surge voltage between drain and source of the switch tube can be generated, which will have an impact on the switch and the output voltage. In order to ab sorb the surge voltage. An improve RCD buffer circuit is proposed in the paper. The peak energy will be absorbed through the buffer capacitor of the circuit. The part energy feedback to the power supply, another part release through the resistor in the form of heat, and the circuit can absorb the voltage spikes. This paper analyzes the process of the improved RCD snubber circuit, According to the specific parameters of the main circuit, a reasonable formula for calculating the resistance capacitance is given. A simulation model will be modulated in Multisim, which compared the waveform of tube voltage and the output waveform of the circuit without snubber circuit with the improved RCD snubber circuit. By comparing and analyzing, it is proved that the improved buffer circuit can absorb surge voltage. Finally, experiments are demonstrated to validate that the correctness of the RC formula and the improved RCD snubber circuit.

  1. Comparison between Phase-Shift Full-Bridge Converters with Noncoupled and Coupled Current-Doubler Rectifier

    Directory of Open Access Journals (Sweden)

    Cheng-Tao Tsai

    2013-01-01

    Full Text Available This paper presents comparison between phase-shift full-bridge converters with noncoupled and coupled current-doubler rectifier. In high current capability and high step-down voltage conversion, a phase-shift full-bridge converter with a conventional current-doubler rectifier has the common limitations of extremely low duty ratio and high component stresses. To overcome these limitations, a phase-shift full-bridge converter with a noncoupled current-doubler rectifier (NCDR or a coupled current-doubler rectifier (CCDR is, respectively, proposed and implemented. In this study, performance analysis and efficiency obtained from a 500 W phase-shift full-bridge converter with two improved current-doubler rectifiers are presented and compared. From their prototypes, experimental results have verified that the phase-shift full-bridge converter with NCDR has optimal duty ratio, lower component stresses, and output current ripple. In component count and efficiency comparison, CCDR has fewer components and higher efficiency at full load condition. For small size and high efficiency requirements, CCDR is relatively suitable for high step-down voltage and high efficiency applications.

  2. AC-DC PFC Converter Using Combination of Flyback Converter and Full-bridge DC-DC Converter

    Directory of Open Access Journals (Sweden)

    Moh. Zaenal Efendi

    2014-06-01

    Full Text Available This paper presents a combination of power factor correction converter using Flyback converter and Full-bridge dc-dc converter in series connection. Flyback converter is operated in discontinuous conduction mode so that it can serve as a power factor correction converter and meanwhile Full-bridge dc-dc converter is used for dc regulator. This converter system is designed to produce a 86 Volt of output voltage and 2 A of output current. Both simulation and experiment results show that the power factor of this converter achieves up to 0.99 and meets harmonic standard of IEC61000-3-2. Keywords: Flyback Converter, Full-bridge DC-DC Converter, Power Factor Correction.

  3. Sensing sheet: the response of full-bridge strain sensors to thermal variations for detecting and characterizing cracks

    Science.gov (United States)

    Tung, S.-T.; Glisic, B.

    2016-12-01

    Sensing sheets based on large-area electronics consist of a dense array of unit strain sensors. This new technology has potential for becoming an effective and affordable monitoring tool that can identify, localize and quantify surface damage in structures. This research contributes to their development by investigating the response of full-bridge unit strain sensors to thermal variations. Overall, this investigation quantifies the effects of temperature on thin-film full-bridge strain sensors monitoring uncracked and cracked concrete. Additionally, an empirical formula is developed to estimate crack width given an observed strain change and a measured temperature change. This research led to the understanding of the behavior of full-bridge strain sensors installed on cracked concrete and exposed to temperature variations. It proves the concept of the sensing sheet and its suitability for application in environments with variable temperature.

  4. Thermal Optimized Operation of the Single-Phase Full-Bridge PV Inverter under Low Voltage Ride-Through Mode

    DEFF Research Database (Denmark)

    Wang, Huai; Yang, Yongheng; Blaabjerg, Frede

    2013-01-01

    . At the same time, the target of a long service time (25 years or more) imposes new challenges to grid-connected transformer-less PV systems. Achieving more reliable PV inverters is of intense interest in recent research. As one of the most critical stresses that induce failures, the thermal stresses...... on the power devices of a single-phase full-bridge PV inverter are analyzed in different operational modes in this paper. The low voltage grid condition is specially taken into account in this paper. The analysis is demonstrated by a 3 kW single-phase full-bridge grid-connected PV system by simulations...

  5. A Double Phase-Shift Control Strategy for A Full-Bridge Three-Level DC/DC Converter

    DEFF Research Database (Denmark)

    Liu, Dong; Deng, Fujin; Gong, Zheng

    2016-01-01

    In this paper, a double phase-shift control strategy is proposed for the full-bridge three-level (FBTL) DC/DC converter applied into DC distribution systems with the medium DC bus voltage. By utilizing the proposed control strategy, the voltage change rate dv/dt and voltage stress of the transfor...

  6. Control of improved full-bridge three-level DC/DC converter for wind turbines in a DC grid

    DEFF Research Database (Denmark)

    Deng, Fujin; Chen, Zhe

    2013-01-01

    This paper presents an improved full-bridge three-level (IFBTL) dc/dc converter for a wind turbine in a dc grid by inserting a passive filter into the dc/dc converter to improve the performance of the converter. The passive filter can effectively reduce the voltage stress of the medium frequency...

  7. Improving Performance for Full-Bridge Inverter of Wind Energy Conversion System Using a Fast and Efficient Control Technique

    Directory of Open Access Journals (Sweden)

    En-Chih Chang

    2018-01-01

    Full Text Available This paper proposes a fast and efficient control technique with application to a full-bridge inverter of a wind energy conversion system that is capable of yielding better performance in transience and steady state. The presented control technique is made up of a finite-time convergent SMGL (sliding-mode guidance law and a Fourier nonlinear grey Bernoulli model (FNGBM. The finite-time convergent SMGL provides a faster convergence rate of system states, as well as a singularity-free solution. However, in case the overestimation/underestimation of the uncertain system boundary occurs, the chatter/steady-state error may exist in finite-time convergent SMGL and then causes serious harmonic distortion at the full-bridge inverter output. An efficient calculational FNGBM is integrated into the finite-time convergent SMGL, thus overcoming chatter/steady-state error problems if the estimated value of the uncertain system boundary cannot be satisfied. Simulation results indicate that the proposed control technique leads to low total harmonic distortion under nonlinear loading and fast dynamic response under transient loading. Experimental results from a full-bridge inverter prototype are given to confirm the simulation results and the mathematical analyses. Because the proposed full-bridge inverter offers significant advantages over the classical finite-time convergent sliding-mode controlled full-bridge inverter in terms of convergent speed, calculational efficiency, and harmonic distortion removal, this paper will be a feasible reference for wind energy systems or other renewable energy systems in future research; for example, for photovoltaic systems and fuel cell systems.

  8. In vivo dosimetry in radio-surgery using MOSFET and micro MOSFET

    International Nuclear Information System (INIS)

    Sors, Aurelie

    2010-01-01

    The author reports a study which aimed at assessing MOSFETs and micro-MOSFETs as in vivo surface dosimeters in 6 MV radio-surgery fixed beams for minimum field sizes of 6 x 6 square millimetres. The developed calibration method is adapted to small beams and MOSFET technology. It allows a reduced number of measurements to perform calibration. Moreover, a new equivalent square formula increases the accuracy of the determination of the actual dose delivered in small beams. Obtained results show that MOSFETs and micro-MOSFETs can be used as in vivo dosimeters when located at the surface

  9. High Efficiency Variable-Frequency Full-Bridge Converter with a Load Adaptive Control Method Based on the Loss Model

    OpenAIRE

    Lei Zhao; Haoyu Li; Yuan Liu; Zhenwei Li

    2015-01-01

    In this paper, a load adaptive control method to improve the efficiency and dynamic performance of the Phase-Shifted Full-Bridge (PSFB) converter which works under a wide range of load conditions is presented. The proposed control method can be used as a battery charger since this application demands a wide range of load conditions. The composition of the PSFB converter’s losses and the loss analysis model are both discussed. According to this model, the optimum switching frequency which resu...

  10. Digital Fuzzy logic and PI control of phase-shifted full-bridge current-doubler converter

    DEFF Research Database (Denmark)

    Török, Lajos; Munk-Nielsen, Stig

    2011-01-01

    of the converter was built in Matlab/Simulink using PLECS. A 600W PSFB convert was designed and built and the control strategies were implemented in a 16 bit fixed point dsPIC microcontroller. The advantages and disadvantages of using Fuzzy logic control are highlighted.......Simple digital fuzzy logic voltage control of a phaseshifted full-bridge (PSFB) converter is proposed in this article. A comparison of the fuzzy controller and the classical PI voltage controller is presented and their effects on the converter dynamics are analyzed. Simulation model...

  11. Verification of angular dependence in MOSFET detector

    International Nuclear Information System (INIS)

    Souza, Clayton H.; Shorto, Julian M.B.; Siqueira, Paulo T.D.; Nunes, Maíra G.; Silva Junior, Iremar A.; Yoriyaz, Hélio

    2017-01-01

    In vivo dosimetry is an essential tool for quality assurance programs, being a procedure commonly performed with thermoluminescent dosimeters (TLDs) or diodes. However, a type of dosimeter that has increasing popularity in recent years is the metal-oxide-semiconductor field effect transistor (MOSFET) detector. MOSFET dosimeters fulfill all the necessary characteristics to realize in vivo dosimetry since it has a small size, good precision and feasibility of measurement, as well as easy handling. Nevertheless, its true differential is to allow reading of the dose in real time, enabling immediate intervention in the correction of physical parameters deviations and anticipation of small anatomical changes in a patient during treatment. In order for MOSFET dosimeter to be better accepted in clinical routine, information reporting performance should be available frequently. For this reason, this work proposes to verify reproducibility and angular dependence of a standard sensitivity MOSFET dosimeter (TN-502RD-H) for Cs-137 and Co-60 sources. Experimental data were satisfactory and MOSFET dosimeter presented a reproducibility of 3.3% and 2.7% (1 SD) for Cs-137 and Co-60 sources, respectively. In addition, an angular dependence of up to 6.1% and 16.3% for both radioactive sources, respectively. It is conclusive that MOSFET dosimeter TN-502RD-H has satisfactory reproducibility and a considerable angular dependence, mainly for the Co-60 source. This means that although precise measurements, special attention must be taken for applications in certain anatomical regions in a patient. (author)

  12. Verification of angular dependence in MOSFET detector

    Energy Technology Data Exchange (ETDEWEB)

    Souza, Clayton H.; Shorto, Julian M.B.; Siqueira, Paulo T.D.; Nunes, Maíra G.; Silva Junior, Iremar A.; Yoriyaz, Hélio, E-mail: chsouza@usp.br [Instituto de Pesquisas Energeticas e Nucleares (IPEN/CNEN-SP), Sao Paulo, SP (Brazil)

    2017-07-01

    In vivo dosimetry is an essential tool for quality assurance programs, being a procedure commonly performed with thermoluminescent dosimeters (TLDs) or diodes. However, a type of dosimeter that has increasing popularity in recent years is the metal-oxide-semiconductor field effect transistor (MOSFET) detector. MOSFET dosimeters fulfill all the necessary characteristics to realize in vivo dosimetry since it has a small size, good precision and feasibility of measurement, as well as easy handling. Nevertheless, its true differential is to allow reading of the dose in real time, enabling immediate intervention in the correction of physical parameters deviations and anticipation of small anatomical changes in a patient during treatment. In order for MOSFET dosimeter to be better accepted in clinical routine, information reporting performance should be available frequently. For this reason, this work proposes to verify reproducibility and angular dependence of a standard sensitivity MOSFET dosimeter (TN-502RD-H) for Cs-137 and Co-60 sources. Experimental data were satisfactory and MOSFET dosimeter presented a reproducibility of 3.3% and 2.7% (1 SD) for Cs-137 and Co-60 sources, respectively. In addition, an angular dependence of up to 6.1% and 16.3% for both radioactive sources, respectively. It is conclusive that MOSFET dosimeter TN-502RD-H has satisfactory reproducibility and a considerable angular dependence, mainly for the Co-60 source. This means that although precise measurements, special attention must be taken for applications in certain anatomical regions in a patient. (author)

  13. High Efficiency Variable-Frequency Full-Bridge Converter with a Load Adaptive Control Method Based on the Loss Model

    Directory of Open Access Journals (Sweden)

    Lei Zhao

    2015-04-01

    Full Text Available In this paper, a load adaptive control method to improve the efficiency and dynamic performance of the Phase-Shifted Full-Bridge (PSFB converter which works under a wide range of load conditions is presented. The proposed control method can be used as a battery charger since this application demands a wide range of load conditions. The composition of the PSFB converter’s losses and the loss analysis model are both discussed. According to this model, the optimum switching frequency which results in minimum power loss is adopted to improve the efficiency. The relationship between switching frequency and power loss is formulated over a wide load range. Indicated by this kind of relationship, the proposed controller adjusts the switching frequency at different load currents. Moreover, an adaptive gain adjustment controller is applied to replace the traditional controller, with the aim to improve the dynamic performance which is influenced by the changes of the switching frequency and load current. In addition, the experimental results show that the maximum improvement of efficiency is up to 20%. These results confirm the effectiveness of the proposed load adaptive control method.

  14. Prognostics Approach For Power Mosfet Under Thermal-Stress Aging

    Data.gov (United States)

    National Aeronautics and Space Administration — The prognostic technique for a power MOSFET presented in this paper is based on accelerated aging of MOSFET IRF520Npbf in a TO-220 package. The methodology utilizes...

  15. MOSFET dosimetry: temperature effects in-vivo

    International Nuclear Information System (INIS)

    Yu, P.K.N.; Cheung, T.; Butson, M.J.; Cancer Services, Wollongong, NSW

    2004-01-01

    Full text: This note investigates temperature effects on dosimetry using a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) for radiotherapy x-ray treatment. This was performed by analysing the dose response and threshold voltage outputs for MOSFET dosimeters as a function of ambient temperature. Results have shown the clinical semiconductor dosimetry system (CSDS) MOSFET provides stable dose measurements with temperatures varying from 15 deg C up to 40 deg C. Thus standard irradiations performed at room temperature can be directly compared to in-vivo dose assessments performed at near body temperature without a temperature correction function. The MOSFET dosimeter threshold voltage varies with temperature and this level is dependant on the dose history of the MOSFET dosimeter. However the variation can be accounted for in the measurement method. For accurate dosimetry the detector should be placed for approximately 60 seconds on a patient to allow thermal equilibrium before measurements are taken with the final reading performed whilst still attached to the patient or conversely left for approximately 120 seconds after removal from the patient if initial readout was measured at room temperature to allow temperature equilibrium to be established. Copyright (2004) Australasian College of Physical Scientists and Engineers in Medicine

  16. Effects of temperature variation on MOSFET dosimetry

    International Nuclear Information System (INIS)

    Cheung Tsang; Butson, Martin J; Yu, Peter K N

    2004-01-01

    This note investigates temperature effects on dosimetry using a metal oxide semiconductor field effect transistor (MOSFET) for radiotherapy x-ray treatment. This was performed by analysing the dose response and threshold voltage outputs for MOSFET dosimeters as a function of ambient temperature. Results have shown that the clinical semiconductor dosimetry system (CSDS) MOSFET provides stable dose measurements with temperatures varying from 15 deg. C up to 40 deg. C. Thus standard irradiations performed at room temperature can be directly compared to in vivo dose assessments performed at near body temperature without a temperature correction function. The MOSFET dosimeter threshold voltage varies with temperature and this level is dependent on the dose history of the MOSFET dosimeter. However, the variation can be accounted for in the measurement method. For accurate dosimetry, the detector should be placed for approximately 60 s on a patient to allow thermal equilibrium before measurements are taken with the final reading performed whilst still attached to the patient or conversely left for approximately 120 s after removal from the patient if initial readout was measured at room temperature to allow temperature equilibrium to be established. (note)

  17. The effect of ionizing radiation on analog characteristics of MOSFET

    International Nuclear Information System (INIS)

    Ren Diyuan; Yu Xuefeng; Lu Wu; Gao Wenyu; Fan Long; Zhang Guoqiang; Yan Rongliang

    1994-01-01

    The effects of 60 Co γ-ray on the linearity and output characteristics of MOSFETs were investigated. The relations of oxide-trapped charge and Si/SiO 2 interface state density to the decrease of mobility μ-bar and transconductance g m , and the shift of the output curves for both P-MOSFETs and N-MOSFETs were qualitatively described. It was shown that degradation of analog characteristics, for P-MOSFETs, resulted from both oxide-trapped charge and interface state, but the degradation for N-MOSFETs was mainly due to the increase of radiation induced Si-SiO 2 interface state density

  18. Compact MOSFET models for VLSI design

    CERN Document Server

    Bhattacharyya, A B

    2009-01-01

    Practicing designers, students, and educators in the semiconductor field face an ever expanding portfolio of MOSFET models. In Compact MOSFET Models for VLSI Design , A.B. Bhattacharyya presents a unified perspective on the topic, allowing the practitioner to view and interpret device phenomena concurrently using different modeling strategies. Readers will learn to link device physics with model parameters, helping to close the gap between device understanding and its use for optimal circuit performance. Bhattacharyya also lays bare the core physical concepts that will drive the future of VLSI.

  19. Analysis, Design, Modeling, and Control of an Interleaved-Boost Full-Bridge Three-Port Converter for Hybrid Renewable Energy Systems

    DEFF Research Database (Denmark)

    Mira Albert, Maria del Carmen; Zhang, Zhe; Knott, Arnold

    2017-01-01

    This paper presents the design, modeling, and control of an isolated dc-dc three-port converter (TPC) based on an interleaved-boost full-bridge converter with pulsewidth modulation (PWM) and phase-shift control for hybrid renewable energy systems. In the proposed topology, the switches are driven...

  20. A Fault-Tolerant Parallel Structure of Single-Phase Full-Bridge Rectifiers for a Wound-Field Doubly Salient Generator

    DEFF Research Database (Denmark)

    Chen, Zhihui; Chen, Ran; Chen, Zhe

    2013-01-01

    The fault-tolerance design is widely adopted for high-reliability applications. In this paper, a parallel structure of single-phase full-bridge rectifiers (FBRs) (PS-SPFBR) is proposed for a wound-field doubly salient generator. The analysis shows the potential fault-tolerance capability of the PS...

  1. Technology computer aided design simulation for VLSI MOSFET

    CERN Document Server

    Sarkar, Chandan Kumar

    2013-01-01

    Responding to recent developments and a growing VLSI circuit manufacturing market, Technology Computer Aided Design: Simulation for VLSI MOSFET examines advanced MOSFET processes and devices through TCAD numerical simulations. The book provides a balanced summary of TCAD and MOSFET basic concepts, equations, physics, and new technologies related to TCAD and MOSFET. A firm grasp of these concepts allows for the design of better models, thus streamlining the design process, saving time and money. This book places emphasis on the importance of modeling and simulations of VLSI MOS transistors and

  2. Commissioning and characteristics of MOSFET dosimeter

    International Nuclear Information System (INIS)

    Gopiraj, A.; Billimagga, Ramesh S.; Rekha, M.; Ramasubramaniam, V.

    2007-01-01

    The verification of the dose delivered to a patient is an important part of the quality assurance in radiotherapy. Thermoluminescent dosimeters (TLDs) and semiconductor diodes were mostly used for this purpose. Recently Metal Oxide Semiconductor field effect transistors (MOSFET) have been proposed for the application in radiotherapy. Each type of detector has its own advantages and disadvantages. The TLD size is very small and therefore can be used both for measurement and dose delivered to a patient and for measurements of dose distribution in a humanoid phantom. The main disadvantages of the TLDs are the time required by the preparation procedure and the limited accuracy which depends on the experience of the user. Additionally, TLDs do not allow an immediate readout. The main disadvantages of semiconductor diodes are the necessity of using a cable which can disturb normal clinical work especially when in vivo measurements are carried out, and the necessity of applying of many correction factors to achieve high accuracy. We procured MOSFET system from Thomson and Nielsen Electronic Ltd. The reproducibility as a function of dose and linearity and calibration factor of the MOSFET detectors were measured. The effects of energy, field size and accumulated dose on the response of the detectors were investigated

  3. Simulation and analysis of an isolated full-bridge DC/DC boost converter operating with a modified perturb and observe maximum power point tracking algorithm

    Directory of Open Access Journals (Sweden)

    Calebe A. Matias

    2017-07-01

    Full Text Available The purpose of the present study is to simulate and analyze an isolated full-bridge DC/DC boost converter, for photovoltaic panels, running a modified perturb and observe maximum power point tracking method. The zero voltage switching technique was used in order to minimize the losses of the converter for a wide range of solar operation. The efficiency of the power transfer is higher than 90% for large solar operating points. The panel enhancement due to the maximum power point tracking algorithm is 5.06%.

  4. Visualisation Techniques for Random Telegraph Signals in MOSFETs

    NARCIS (Netherlands)

    van der Wel, A.P.; Klumperink, Eric A.M.; Kolhatkar, J.S.; Hoekstra, E.; Nauta, Bram

    2004-01-01

    In the study of LF noise in MOSFETS, it has become clear that Random Telegraph Signals (RTS) are dominant. When a MOSFET is subjected to large-signal excitation, the RTS noise is influenced. In this paper, we present different visualizations of the transient behaviour of the RTS.

  5. Challenges in Switching SiC MOSFET without Ringing

    DEFF Research Database (Denmark)

    Li, Helong; Munk-Nielsen, Stig

    2014-01-01

    Switching SiC MOSFET without ringing in high frequency applications is important for meeting the EMI (ElectroMagnetic Interference) standard. Achieving a clean switching waveform of SiC MOSFET without additional components is becoming a challenge. In this paper, the switching oscillation mechanism...

  6. Technology challenges for ultrasmall silicon MOSFET's

    International Nuclear Information System (INIS)

    Dennard, R.H.

    1981-01-01

    Work on silicon MOSFET devices scaled down to half-micron dimensions is gathering momentum in research labs for VLSI applications. Further reductions in device geometries by only a factor of two will bring us to the edge of some fundamental barriers to miniaturization. Design requirements for very thin layers in the device structure lead to resistance effects, statistical fluctuation of doping impurities, and increased concern for interface properties. Scaling down of applied voltage is difficult because built-in junction potentials and other small voltage terms are no longer negligible. Increased susceptibility to spurious operation or permanent damage from alpha particles, cosmic particles, or other high-energy radiation is reviewed

  7. Practical applications of SiC-MOSFETs and further developments

    Science.gov (United States)

    Furuhashi, Masayuki; Tomohisa, Shingo; Kuroiwa, Takeharu; Yamakawa, Satoshi

    2016-03-01

    The next generation power modules using SiC-MOSFETs have been developed for over ten years. From our successful results, we have released SiC power modules which have been used in railway vehicles, industrial machines and home appliances, etc. Low on-resistance 3.3 kV SiC-MOSFETs have been realized by JFET doping and they demonstrated a loss reduction of 55% in a traction inverter compared to a conventional system. In the case of a 1.2 kV MOSFET, a 1 cm2 die verified that it can control a large current of over 600 A. For home appliances, we reduce the trade-off between the threshold voltage and channel mobility by a new gate oxide process. High threshold voltage SiC-MOSFETs having a low on-resistance contribute to the low cost installation of SiC-MOSFETs into air conditioners and achieved a loss reduction of 45% in DC converters. For further reduction of conduction loss, we investigated new structures and technologies. Trench SiC-MOSFETs having a bottom p-well verify lower on-resistance and a larger SCSOA than those of planar MOSFETs. The optimization of the dopant concentration in the drift layer and a reduction of wafer thickness verified the reduction of on-resistance. They are expected to contribute to a lower power loss.

  8. Isolated Full Bridge Boost DC-DC Converter Designed for Bidirectional Operation of Fuel Cells/Electrolyzer Cells in Grid-Tie Applications

    DEFF Research Database (Denmark)

    Pittini, Riccardo; Zhang, Zhe; Andersen, Michael A. E.

    2013-01-01

    current. Dc-dc converter efficiency plays a fundamental role in the overall system efficiency since processed energy is always flowing through the converter; for this reason, loss analysis and optimization are a key component of the converter design. The paper presents an isolated full bridge boost dc......-dc converter (IFBBC) designed for this new application focusing on losses analysis. The system topology is briefly discussed and the major concerns related to the system, cells stacks and converter operating points are analyzed. The dc-dc converter losses are modeled and presented in detail; the analysis......Energy production from renewable energy sources is continuously varying, for this reason energy storage is becoming more and more important as the percentage of green energy increases. Newly developed fuel cells can operate in reverse mode as electrolyzer cells; therefore, they are becoming...

  9. A novel PWM control for a bi-directional full-bridge DC-DC converter with smooth conversion mode transitions

    Science.gov (United States)

    Lorentz, V. R. H.; Schwarzmann, H.; März, M.; Bauer, A. J.; Ryssel, H.; Frey, L.; Poure, P.; Braun, F.

    2011-08-01

    A novel CMOS integrated pulse-width modulation (PWM) control circuit allowing smooth transitions between conversion modes in full-bridge based bi-directional DC-DC converters operating at high switching frequencies is presented. The novel PWM control circuit is able to drive full-bridge based DC-DC converters performing step-down (i.e. buck) and step-up (i.e. boost) voltage conversion in both directions, thus allowing charging and discharging of the batteries in mobile systems. It provides smooth transitions between buck, buck-boost and boost modes. Additionally, the novel PWM control loop circuit uses a symmetrical triangular carrier, which overcomes the necessity of using an output phasing circuit previously required in PWM controllers based on sawtooth oscillators. The novel PWM control also enables to build bi-directional DC-DC converters operating at high switching frequencies (i.e. up to 10 MHz and above). Finally, the proposed PWM control circuit also allows the use of an average lossless inductor-current sensor for sensing the average load current even at very high switching frequencies. In this article, the proposed PWM control circuit is modelled and the integrated CMOS schematic is given. The corresponding theory is analysed and presented in detail. The circuit simulations realised in the Cadence Spectre software with a commercially available 0.18 µm mixed-signal CMOS technology from UMC are shown. The PWM control circuit was implemented in a monolithic integrated bi-directional CMOS DC-DC converter ASIC prototype. The fabricated prototype was tested experimentally and has shown performances in accordance with the theory.

  10. Performance analysis of SOI MOSFET with rectangular recessed channel

    International Nuclear Information System (INIS)

    Singh, M; Mishra, G P; Mishra, S; Mohanty, S S

    2016-01-01

    In this paper a two dimensional (2D) rectangular recessed channel–silicon on insulator metal oxide semiconductor field effect transistor (RRC-SOI MOSFET), using the concept of groove between source and drain regions, which is one of the channel engineering technique to suppress the short channel effect (SCE). This suppression is mainly due to corner potential barrier of the groove and the simulation is carried out by using ATLAS 2D device simulator. To have further improvement of SCE in RRC-SOI MOSFET, three more devices are designed by using dual material gate (DMG) and gate dielectric technique, which results in formation of devices i.e. DMRRC-SOI,MLSMRRC-SOI, MLDMRRC-SOI MOSFET. The effect of different structures of RRC-SOI on AC and RF parameters are investigated and the importance of these devices over RRC MOSFET regarding short channel effect is analyzed. (paper)

  11. Comparative Analysis of Semiconductor Power Losses of Galvanically Isolated Quasi-Z-Source and Full-Bridge Boost DC-DC Converters

    Directory of Open Access Journals (Sweden)

    Kosenko Roman

    2015-07-01

    Full Text Available This paper compares semiconductor losses of the galvanically isolated quasi-Z-source converter and full-bridge boost DC-DC converter with active clamping circuit. Operation principle of both converters is described. Short design guidelines are provided as well. Results of steady state analysis are used to calculate semiconductor power losses for both converters. Analytical expressions are derived for all types of semiconductor power losses present in these converters. The theoretical results were verified by means of numerical simulation performed in the PSIM simulation software. Its add-on module “Thermal module” was used to estimate semiconductor power losses using the datasheet parameters of the selected semiconductor devices. Results of calculations and simulation study were obtained for four operating points with different input voltage and constant input current to compare performance of the converters in renewable applications, like photovoltaic, where input voltage and power can vary significantly. Power loss breakdown is detailed and its dependence on the converter output power is analyzed. Recommendations are given for the use of the converter topologies in applications with low input voltage and relatively high input current.

  12. Studies on a Hybrid Full-Bridge/Half-Bridge Bidirectional CLTC Multi-Resonant DC-DC Converter with a Digital Synchronous Rectification Strategy

    Directory of Open Access Journals (Sweden)

    Shu-huai Zhang

    2018-01-01

    Full Text Available This study presents a new bidirectional multi-resonant DC-DC converter, which is named CLTC. The converter adds an auxiliary transformer and an extra resonant capacitor based on a LLC resonant DC-DC converter, achieving zero-voltage switching (ZVS for the input inverting switches and zero-current switching (ZCS for the output rectifiers in all load range. The converter also has a wide gain range in two directions. When the load is light, a half-bridge configuration is adopted instead of a full-bridge configuration to solve the problem of voltage regulation. By this method, the voltage gain becomes monotonous and controllable. Besides, the digital synchronous rectification strategy is proposed in forward mode without adding any auxiliary circuit. The conduction time of synchronous rectifiers equals the estimation value of body diodes’ conduction time with the lightest load. Power loss analysis is also conducted in different situations. Finally, the theoretical analysis is validated by a 5 kW prototype.

  13. A Novel Choice Procedure of Magnetic Component Values for Phase Shifted Full Bridge Converters with a Variable Dead-Time Control Method

    Directory of Open Access Journals (Sweden)

    Lei Zhao

    2015-09-01

    Full Text Available Magnetic components are important parts of the phase shifted full bridge (PSFB converter. During the dead-time of switches located in the same leg, the converter can achieve zero-voltage-switching (ZVS by using the energies stored in magnetic components to discharge or charge the output capacitances of switches. Dead-time is usually calculated under a given set of pre-defined load condition which results in that the available energies are insufficient and ZVS capability is lost at light loads. In this paper, the PSFB converter is controlled by variable dead-time method and thus full advantage can be taken of the energies stored in magnetic components. Considering that dead-time has a great effect on ZVS, the relationship between available energies and magnetic component values is formulated by analyzing the equivalent circuits during dead-time intervals. Magnetic component values are chosen based on such relationship. The proposed choice procedure can make the available energies greater than the required energies for ZVS operation over a wide range of load conditions. Moreover, the burst mode control is adopted in order to reduce the standby power loss. Experimental results coincide with the theoretical analysis. The proposed method is a simple and practical solution to extend the ZVS range.

  14. Soft-Switched Dual-Input DC-DC Converter Combining a Boost-Half-Bridge Cell and a Voltage-Fed Full-Bridge Cell

    DEFF Research Database (Denmark)

    Zhang, Zhe; Thomsen, Ole Cornelius; Andersen, Michael A. E.

    2013-01-01

    This paper presents a new zero-voltage-switching (ZVS) isolated dc-dc converter which combines a boost halfbridge (BHB) cell and a full-bridge (FB) cell, so that two different type of power sources, i.e. both current-fed and voltage-fed, can be coupled effectively by the proposed converter...... for various applications, such as fuel cell and super-capacitor hybrid energy system. By fully using two high frequency transformers and a shared leg of switches, number of the power devices and associated gate driver circuits can be reduced. With phase-shift control, the converter can achieve ZVS turn......-on of active switches and zero-current switching (ZCS) turn-off of diodes. In this paper, derivation, analysis and design of the proposed converter are presented. Finally, a 25~50 V input, 300~400 V output prototype with a 600 W nominal power rating is built up and tested to demonstrate the effectiveness...

  15. Forward gated-diode method for parameter extraction of MOSFETs

    Energy Technology Data Exchange (ETDEWEB)

    Zhang Chenfei; He Jin; Wang Guozeng; Yang Zhang; Liu Zhiwei [Peking University Shenzhen SOC Key Laboratory, PKU HKUST Shenzhen Institute, Shenzhen 518057 (China); Ma Chenyue; Guo Xinjie; Zhang Xiufang, E-mail: frankhe@pku.edu.cn [TSRC, Institute of Microelectronics, School of Electronic Engineering and Computer Science, Peking University, Beijing 100871 (China)

    2011-02-15

    The forward gated-diode method is used to extract the dielectric oxide thickness and body doping concentration of MOSFETs, especially when both of the variables are unknown previously. First, the dielectric oxide thickness and the body doping concentration as a function of forward gated-diode peak recombination-generation (R-G) current are derived from the device physics. Then the peak R-G current characteristics of the MOSFETs with different dielectric oxide thicknesses and body doping concentrations are simulated with ISE-Dessis for parameter extraction. The results from the simulation data demonstrate excellent agreement with those extracted from the forward gated-diode method. (semiconductor devices)

  16. MOSFET technologies for double-pole four-throw radio-frequency switch

    CERN Document Server

    Srivastava, Viranjay M

    2014-01-01

    This book provides analysis and discusses the design of various MOSFET technologies which are used for the design of Double-Pole Four-Throw (DP4T) RF switches for next generation communication systems. The authors discuss the design of the (DP4T) RF switch by using the Double-Gate (DG) MOSFET, as well as the Cylindrical Surrounding double-gate (CSDG) MOSFET.  The effect of HFO2 (high dielectric material) in the design of DG MOSFET and CSDG MOSFET  is also explored. Coverage includes comparison of Single-gate MOSFET and Double-gate MOSFET switching parameters, as well as testing of MOSFETs parameters using image acquisition.  ·         Provides a single-source reference to the latest technologies for the design of Double-gate MOSFET, Cylindrical Surrounding double-gate MOSFET and HFO2 based MOSFET; ·         Explains the design of RF switches using the technologies presented and simulates switches; ·         Verifies parameters and discusses feasibility of devices and switches.

  17. Circuit mismatch influence on performance of paralleling silicon carbide MOSFETs

    DEFF Research Database (Denmark)

    Li, Helong; Munk-Nielsen, Stig; Pham, Cam

    2014-01-01

    This paper focuses on circuit mismatch influence on performance of paralleling SiC MOSFETs. Power circuit mismatch and gate driver mismatch influences are analyzed in detail. Simulation and experiment results show the influence of circuit mismatch and verify the analysis. This paper aims to give...

  18. Photosensitive N channel MOSFET device on silicon on sapphire substrate

    International Nuclear Information System (INIS)

    Le Goascoz, V.; Borel, J.

    1975-01-01

    An anomalous behavior of the N channel output current characteristic in a SOS MOSFET with a floating bulk is described. Such a phenomenon can be used in a photosensitive device with internal gain. Such devices can be used on SOS substrates to achieve integrated circuits with high insulating voltages and data transmission by optical means [fr

  19. High frequency MOSFET gate drivers technologies and applications

    CERN Document Server

    Zhang, Zhiliang

    2017-01-01

    This book describes high frequency power MOSFET gate driver technologies, including gate drivers for GaN HEMTs, which have great potential in the next generation of switching power converters. Gate drivers serve as a critical role between control and power devices.

  20. Low-frequency noise phenomena in switched MOSFETs

    NARCIS (Netherlands)

    van der Wel, A.P.; Klumperink, Eric A.M.; Kolhatkar, J.S.; Hoekstra, E.; Snoeij, Martijn F.; Salm, Cora; Wallinga, Hans; Nauta, Bram

    2007-01-01

    In small-area MOSFETs widely used in analog and RF circuit design, low-frequency (LF) noise behavior is increasingly dominated by single-electron effects. In this paper, we review the limitations of current compact noise models which do not model such single-electron effects. We present measurement

  1. Evaluation of charge-integrating amplifier with silicon MOSFETs for cryogenic readout

    Science.gov (United States)

    Noda, Manabu; Shibai, Hiroshi; Watabe, Toyoki; Hirao, Takanori; Yoda, Hiroyuki; Nagata, Hirohisa; Nakagawa, Takao; Kawada, Mitsunobu

    1998-08-01

    Low-noise and low-power cryogenic readout electronics are developed for a focal plane instrument of the IR Imaging Surveyor. We measured the static characteristics and the noise spectra of several types of silicon MOSFETs at the cryogenic temperature where silicon JFETs do not work well due to the carrier freeze-out. The 'kink' behavior of n- channel MOSFETs was observed below the carrier freeze-out temperature, but it was not obvious for the p-channel MOSFET. It was demonstrated the p-channel MOSFETs can be used for the cryogenic readout electronics of the IRIS's far-IR array with an acceptable performance. The amplifier integrated with these MOSFETs showed low-noise at 2K under a low power consumption of 1 (mu) W per MOSFET. We now design and evaluate several circuits that are fabricated by the CMOS process for cryogenic readout.

  2. Dual-Input Soft-Switched DC-DC Converter with Isolated Current-Fed Half-Bridge and Voltage-Fed Full-Bridge for Fuel Cell or Photovoltaic Systems

    DEFF Research Database (Denmark)

    Zhang, Zhe; Thomsen, Ole Cornelius; Andersen, Michael A. E.

    2013-01-01

    integrate a current-fed boost half-bridge (BHB) and a full-bridge (FB) into one equivalent circuit configuration which has dual-input ability and additionally it can reduce the number of the power devices. With the phase-shift control, it can achieve zero-voltage switching turn-on of active switches...... power rating are built up and tested to demonstrate the effectiveness of the proposed converter topology....

  3. Analysis of switching characteristics for negative capacitance ultra-thin-body germanium-on-insulator MOSFETs

    Science.gov (United States)

    Pi-Ho Hu, Vita; Chiu, Pin-Chieh

    2018-04-01

    The impact of device parameters on the switching characteristics of negative capacitance ultra-thin-body (UTB) germanium-on-insulator (NC-GeOI) MOSFETs is analyzed. NC-GeOI MOSFETs with smaller gate length (L g), EOT, and buried oxide thickness (T box) and thicker ferroelectric layer thickness (T FE) exhibit larger subthreshold swing improvements over GeOI MOSFETs due to better capacitance matching. Compared with GeOI MOSFETs, NC-GeOI MOSFETs exhibit better switching time due to improvements in effective drive current (I eff) and subthreshold swing. NC-GeOI MOSFET exhibits larger ST improvements at V dd = 0.3 V (‑82.9%) than at V dd = 0.86 V (‑9.7%), because NC-GeOI MOSFET shows 18.2 times higher I eff than the GeOI MOSFET at V dd = 0.3 V, while 2.5 times higher I eff at V dd = 0.86 V. This work provides the device design guideline of NC-GeOI MOSFETs for ultra-low power applications.

  4. Parallel Connection of Silicon Carbide MOSFETs for Multichip Power Modules

    DEFF Research Database (Denmark)

    Li, Helong

    characterization of SiC MOSFETs regarding the influence of switching loop stray inductance and common source stray inductance. The pulse current measurement methods of fast switching speed power devices are summarized and a new method witch silicon steel current transformer is presented. With the knowledge...... to a significant transient current imbalance during the switching period. Besides the circuit mismatch, a current coupling effect is also found in the DBC layout, which aggravates the transient current imbalance among the paralleled SiC MOSFET dies. The discussions about the effects of the auxiliary source......, which turns out to be able to improve the efficiency compared to the traditional half bridge. Besides the split output topology benefits, compared to the traditional DBC layout, the proposed DBC layout significantly reduces the circuit mismatch and current coupling effect, which consequently improves...

  5. Accelerated Aging with Electrical Overstress and Prognostics for Power MOSFETs

    Science.gov (United States)

    Saha, Sankalita; Celaya, Jose Ramon; Vashchenko, Vladislav; Mahiuddin, Shompa; Goebel, Kai F.

    2011-01-01

    Power electronics play an increasingly important role in energy applications as part of their power converter circuits. Understanding the behavior of these devices, especially their failure modes as they age with nominal usage or sudden fault development is critical in ensuring efficiency. In this paper, a prognostics based health management of power MOSFETs undergoing accelerated aging through electrical overstress at the gate area is presented. Details of the accelerated aging methodology, modeling of the degradation process of the device and prognostics algorithm for prediction of the future state of health of the device are presented. Experiments with multiple devices demonstrate the performance of the model and the prognostics algorithm as well as the scope of application. Index Terms Power MOSFET, accelerated aging, prognostics

  6. Large-Signal DG-MOSFET Modelling for RFID Rectification

    Directory of Open Access Journals (Sweden)

    R. Rodríguez

    2016-01-01

    Full Text Available This paper analyses the undoped DG-MOSFETs capability for the operation of rectifiers for RFIDs and Wireless Power Transmission (WPT at microwave frequencies. For this purpose, a large-signal compact model has been developed and implemented in Verilog-A. The model has been numerically validated with a device simulator (Sentaurus. It is found that the number of stages to achieve the optimal rectifier performance is inferior to that required with conventional MOSFETs. In addition, the DC output voltage could be incremented with the use of appropriate mid-gap metals for the gate, as TiN. Minor impact of short channel effects (SCEs on rectification is also pointed out.

  7. Magnetoresistance of Si(001) MOSFETs with high concentration of electrons

    Czech Academy of Sciences Publication Activity Database

    Smrčka, Ludvík; Makarovsky, O. N.; Schemenchinskii, S. G.; Vašek, Petr; Jurka, Vlastimil

    2004-01-01

    Roč. 22, - (2004), s. 320-323 ISSN 1386-9477. [International Conference on Electronic Properties of Two-Dimensional Systems /15./. Nara, 14.07.2003-18.07.2003] R&D Projects: GA ČR GA202/01/0754; GA ČR GA202/96/0036 Institutional research plan: CEZ:AV0Z1010914 Keywords : Si MOSFET * magnetoresistance * Hall effect Subject RIV: BM - Solid Matter Physics ; Magnetism Impact factor: 0.898, year: 2004

  8. Towards Modeling the Effects of Lightning Injection on Power MOSFETs

    Science.gov (United States)

    2010-10-01

    an NPN BJT (bi-polar junction transistor ) formed where the n+ source contact is diffused. Fig- ure 8 shows the details of these parasitic components...and analysis of lightning injection on power MOSFET (Metal Oxide Semiconductor Field Effect Transistor ) devices which form an important subset of...ments that are of interest to us for analysis purposes in this paper are the parasitic capacitances. The turn-on of the BJT is undesirable since it

  9. Prognostics of Power MOSFETs under Thermal Stress Accelerated Aging using Data-Driven and Model-Based Methodologies

    Data.gov (United States)

    National Aeronautics and Space Administration — An approach for predicting remaining useful life of power MOSFETs (metal oxide field effect transistor) devices has been developed. Power MOSFETs are semiconductor...

  10. Prognostics Of Power Mosfets Under Thermal Stress Accelerated Aging Using Data-Driven And Model-Based Methodologies

    Data.gov (United States)

    National Aeronautics and Space Administration — An approach for predicting remaining useful life of power MOSFETs (metal oxide field effect transistor) devices has been developed. Power MOSFETs are semiconductor...

  11. Development of Simulink-Based SiC MOSFET Modeling Platform for Series Connected Devices

    DEFF Research Database (Denmark)

    Tsolaridis, Georgios; Ilves, Kalle; Reigosa, Paula Diaz

    2016-01-01

    A new MATLAB/Simulink-based modeling platform has been developed for SiC MOSFET power modules. The modeling platform describes the electrical behavior f a single 1.2 kV/ 350 A SiC MOSFET power module, as well as the series connection of two of them. A fast parameter initialization is followed...

  12. Reliability Concerns for Flying SiC Power MOSFETs in Space

    Science.gov (United States)

    Galloway, K. F.; Witulski, A. F.; Schrimpf, R. D.; Sternberg, A. L.; Ball, D. R.; Javanainen, A.; Reed, R. A.; Sierawski, B. D.; Lauenstein, J-M

    2018-01-01

    SiC power MOSFETs are space-ready in terms of typical reliability measures. However, single event burnout (SEB) often occurs at voltages 50% or lower than specified breakdown. Data illustrating burnout for 1200 V devices is reviewed and the space reliability of SiC MOSFETs is discussed.

  13. First nondestructive measurements of power MOSFET single event burnout cross sections

    International Nuclear Information System (INIS)

    Oberg, D.L.; Wert, J.L.

    1987-01-01

    A new technique to nondestructively measure single event burnout cross sections for N-channel power MOSFETs is presented. Previous measurements of power MOSFET burnout susceptibility have been destructive and thus not conducive to providing statistically meaningful burnout probabilities. The nondestructive technique and data for various device types taken at several accelerators, including the LBL Bevalac, are documented. Several new phenomena are observed

  14. A Short-Circuit Safe Operation Area Identification Criterion for SiC MOSFET Power Modules

    DEFF Research Database (Denmark)

    Reigosa, Paula Diaz; Iannuzzo, Francesco; Luo, Haoze

    2017-01-01

    -circuit-current-based criterion; and 2) the gate-voltage-based criterion. The applicability of these two criteria makes possible the SCSOA evaluation of SiC MOSFETs with some safety margins in order to avoid unnecessary failures during their SCSOA characterization. SiC MOSFET power modules from two different manufacturers...

  15. Above 700 V superjunction MOSFETs fabricated by deep trench etching and epitaxial growth

    International Nuclear Information System (INIS)

    Li Zehong; Ren Min; Zhang Bo; Ma Jun; Hu Tao; Zhang Shuai; Wang Fei; Chen Jian

    2010-01-01

    Silicon superjunction power MOSFETs were fabricated with deep trench etching and epitaxial growth, based on the process platform of the Shanghai Hua Hong NEC Electronics Company Limited. The breakdown voltages of the fabricated superjunction MOSFETs are above 700 V and agree with the simulation. The dynamic characteristics, especially reverse diode characteristics, are equivalent or even superior to foreign counterparts. (semiconductor devices)

  16. Resonant Full-Bridge Synchronous Rectifier Utilizing 15 V GaN Transistors for Wireless Power Transfer Applications Following AirFuel Standard Operating at 6.78 MHz

    DEFF Research Database (Denmark)

    Jensen, Christopher Have Kiaerskou; Spliid, Frederik Monrad; Hertel, Jens Christian

    2018-01-01

    Connectivity in smart devices is increasingly realized by wireless connections. The remaining reason for using connectors at all is for charging the internal battery, for which wireless power transfer is an alternative. Two industry standards, AirFuel and Qi, exist to support compatibility between......, this work uses low voltage GaN transistors on the receiver (Rx) side to allow synchronous rectification and soft switching, thereby achieving high efficiency. After analyzing adequate Class-DE rectifier topologies, a ClassDE full-bridge 5 W rectifier using 15 V GaN transistors are designed and implemented...

  17. CMOS-compatible batch processing of monolayer MoS2 MOSFETs

    Science.gov (United States)

    Xiong, Kuanchen; Kim, Hyun; Marstell, Roderick J.; Göritz, Alexander; Wipf, Christian; Li, Lei; Park, Ji-Hoon; Luo, Xi; Wietstruck, Matthias; Madjar, Asher; Strandwitz, Nicholas C.; Kaynak, Mehmet; Lee, Young Hee; Hwang, James C. M.

    2018-04-01

    Thousands of high-performance 2D metal-oxide-semiconductor field effect transistors (MOSFETs) were fabricated on wafer-scale chemical vapor deposited MoS2 with fully-CMOS-compatible processes such as photolithography and aluminum metallurgy. The yield was greater than 50% in terms of effective gate control with less-than-10 V threshold voltage, even for MOSFETs having deep-submicron gate length. The large number of fabricated MOSFETs allowed statistics to be gathered and the main yield limiter to be attributed to the weak adhesion between the transferred MoS2 and the substrate. With cut-off frequencies approaching the gigahertz range, the performances of the MOSFETs were comparable to that of state-of-the-art MoS2 MOSFETs, whether the MoS2 was grown by a thin-film process or exfoliated from a bulk crystal.

  18. Comparative Study of Si and SiC MOSFETs for High Voltage Class D Audio Amplifiers

    DEFF Research Database (Denmark)

    Nielsen, Dennis; Knott, Arnold; Andersen, Michael A. E.

    2014-01-01

    Silicon (Si) Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) are traditional utilised in class D audio amplifiers. It has been proposed to replace the traditional inefficient electrodynamic transducer with the electrostatic transducer. This imposes new high voltage requirements...... on the MOSFETs of class D amplifiers, and significantly reduces the selection of suitable MOSFETs. As a consequence it is investigated, if Silicon-Carbide (SiC) MOSFETs could represent a valid alternative. The theory of pulse timing errors are revisited for the application of high voltage and capactive loaded...... class D amplifiers. It is shown, that SiC MOSFETs can compete with Si MSOFETs in terms of THD. Validation is done using simulations and a 500 V amplifier driving a 100 nF load. THD+N below 0.3 % is reported...

  19. Comparison of LDD and double-gate MOSFET for nanoscale devices

    Science.gov (United States)

    Ko, Suk-woong; Kim, Jae-hong; Jung, Hak-kee

    2002-11-01

    In short channel MOSFETs (metal oxide semiconductor field effect transistors), the effective channel length can be substantially shortened, leading to a slope in the saturated I-V characteristic that is analogous to the Early effect for BJT. These SCE(short channel effect) problems have been solved using the LDD(lightly doped drain) structure, but can't be completely solved at nano scale gate. To complete weakness of LDD, we have designed the MOSFET which has the DG(double gate) structure. For comparing LDD with DG MOSFETs, we have used the TCAD simulator. The structures of LDD and DG MOSFETs have been designed and simulated by the DIOS tool and the electrical characteristics simulated by the DESSIS tool in TCAD. The I-V characteristic is not good in LDD but it is very excellent in DG MOSFET of sub-50nm gate.

  20. Prognostics Approach for Power MOSFET Under Thermal-Stress

    Science.gov (United States)

    Galvan, Jose Ramon Celaya; Saxena, Abhinav; Kulkarni, Chetan S.; Saha, Sankalita; Goebel, Kai

    2012-01-01

    The prognostic technique for a power MOSFET presented in this paper is based on accelerated aging of MOSFET IRF520Npbf in a TO-220 package. The methodology utilizes thermal and power cycling to accelerate the life of the devices. The major failure mechanism for the stress conditions is dieattachment degradation, typical for discrete devices with leadfree solder die attachment. It has been determined that dieattach degradation results in an increase in ON-state resistance due to its dependence on junction temperature. Increasing resistance, thus, can be used as a precursor of failure for the die-attach failure mechanism under thermal stress. A feature based on normalized ON-resistance is computed from in-situ measurements of the electro-thermal response. An Extended Kalman filter is used as a model-based prognostics techniques based on the Bayesian tracking framework. The proposed prognostics technique reports on preliminary work that serves as a case study on the prediction of remaining life of power MOSFETs and builds upon the work presented in [1]. The algorithm considered in this study had been used as prognostics algorithm in different applications and is regarded as suitable candidate for component level prognostics. This work attempts to further the validation of such algorithm by presenting it with real degradation data including measurements from real sensors, which include all the complications (noise, bias, etc.) that are regularly not captured on simulated degradation data. The algorithm is developed and tested on the accelerated aging test timescale. In real world operation, the timescale of the degradation process and therefore the RUL predictions will be considerable larger. It is hypothesized that even though the timescale will be larger, it remains constant through the degradation process and the algorithm and model would still apply under the slower degradation process. By using accelerated aging data with actual device measurements and real

  1. SPICE modelling of the transient response of irradiated MOSFETs

    International Nuclear Information System (INIS)

    Pouget, V.; Lapuyade, H.; Lewis, D.; Deval, Y.; Fouillat, P.; Sarger, L.

    1999-01-01

    A new SPICE model of irradiated MOSFET taking into account the real response of the 4 electrodes is proposed. The component that has been simulated is an NMOS transistor issued from the AMS BiCMOS 0.8 μm technology. A comparison between SPICE-generated transients and PISCES device simulation demonstrates the accuracy benefits when used in complex electronic architectures. This model could be used when designing electronic circuits able to sustain hardening due to SEE (single event effect), it will be an efficient complement to the physical simulations

  2. Electric field and temperature effects in irradiated MOSFETs

    Energy Technology Data Exchange (ETDEWEB)

    Silveira, M. A. G., E-mail: marcilei@fei.edu.br; Santos, R. B. B.; Leite, F. G.; Araújo, N. E.; Cirne, K. H.; Melo, M. A. A.; Rallo, A. [Centro Universitário da FEI, São Bernardo do Campo, S.P. (Brazil); Aguiar, Vitor A. P.; Aguirre, F.; Macchione, E. L. A.; Added, N.; Medina, N. H. [Instituto de Física da USP, São Paulo, S.P. (Brazil)

    2016-07-07

    Electronic devices exposed to ionizing radiation exhibit degradation on their electrical characteristics, which may compromise the functionality of the device. Understanding the physical phenomena responsible for radiation damage, which may be specific to a particular technology, it is of extreme importance to develop methods for testing and recovering the devices. The aim of this work is to check the influence of thermal annealing processes and electric field applied during irradiation of Metal Oxide Semiconductor Field Effect Transistors (MOSFET) in total ionizing dose experiments analyzing the changes in the electrical parameters in these devices.

  3. SiC MOSFETs based split output half bridge inverter

    DEFF Research Database (Denmark)

    Li, Helong; Munk-Nielsen, Stig; Beczkowski, Szymon

    2014-01-01

    output. The double pulse test shows the devices' current during commutation process and the reduced switching losses of SiC MOSFETs compared to that of the traditional half bridge. The efficiency comparison is presented with experimental results of half bridge power inverter with split output...... and traditional half bridge inverter, from switching frequency 10 kHz to 100 kHz. The experimental results comparison shows that the half bridge with split output has an efficiency improvement of more than 0.5% at 100 kHz switching frequency....

  4. A Highly Responsive Silicon Nanowire/Amplifier MOSFET Hybrid Biosensor

    Science.gov (United States)

    2015-07-21

    Hybrid Biosensor Jieun Lee1,2, Jaeman Jang1, Bongsik Choi1, Jinsu Yoon1, Jee-Yeon Kim3, Yang-Kyu Choi3, Dong Myong Kim1, Dae Hwan Kim1 & Sung-Jin Choi1...This study demonstrates a hybrid biosensor comprised of a silicon nanowire (SiNW) integrated with an amplifier MOSFET to improve the current response...of field-effect-transistor (FET)-based biosensors . The hybrid biosensor is fabricated using conventional CMOS technology, which has the potential

  5. A new memory effect (MSD) in fully depleted SOI MOSFETs

    Science.gov (United States)

    Bawedin, M.; Cristoloveanu, S.; Yun, J. G.; Flandre, D.

    2005-09-01

    We demonstrate that the transconductance and drain current of fully depleted MOSFETs can display an interesting time-dependent hysteresis. This new memory effect, called meta-stable dip (MSD), is mainly due to the long carrier generation lifetime in the silicon film. Our parametric analysis shows that the memory window can be adjusted in view of practical applications. Various measurement conditions and devices with different doping, front oxide and silicon film thicknesses are systematically explored. The MSD effect can be generalized to several fully depleted CMOS technologies. The MSD mechanism is discussed and validated by two-dimensional simulations results.

  6. Computer simulation of ionizing radiation burnout in power MOSFETs

    International Nuclear Information System (INIS)

    Keshavarz, A.A.; Fischer, T.A.; Dawes, W.R. Jr.; Hawkins, C.F.

    1988-01-01

    The transient response of a power MOSFET device to ionizing radiation was examined using the BAMBI device simulator. The radiation rate threshold for burnout was determined for several different cases. The burnout mechanism was attributed to current-induced avalanche. The effects of the applied drain-source voltage and the base width of the parasitic bipolar device on the threshold level were modeled. It was found that the radiation rate threshold is lower at higher drain-source voltages or narrower bases. 8 refs., 17 figs

  7. Heavy-ion-induced, gate-rupture in power MOSFETs

    International Nuclear Information System (INIS)

    Fischer, T.A.

    1987-01-01

    A new, heavy-ion-induced, burnout mechanism has been experimentally observed in power metal-oxide-semiconductor field-effect transistors (MOSFETs). This mechanism occurs when a heavy, charged particle passes through the gate oxide region of n- or p-channel devices having sufficient gate-to-source or gate-to-drain bias. The gate-rupture leads to significant permanent degradation of the device. A proposed failure mechanism is discussed and experimentally verified. In addition, the absolute immunity of p-channel devices to heavy-ion-induced, semiconductor burnout is demonstrated and discussed along with new, non-destructive, burnout testing methods

  8. SiC Power MOSFET with Improved Gate Dielectric

    Energy Technology Data Exchange (ETDEWEB)

    Sbrockey, Nick M. [Structured Materials Industries, Inc., Piscataway, NJ (United States); Tompa, Gary S. [Structured Materials Industries, Inc., Piscataway, NJ (United States); Spencer, Michael G. [Structured Materials Industries, Inc., Piscataway, NJ (United States); Chandrashekhar, Chandra M.V. S. [Structured Materials Industries, Inc., Piscataway, NJ (United States)

    2010-08-23

    In this STTR program, Structured Materials Industries (SMI), and Cornell University are developing novel gate oxide technology, as a critical enabler for silicon carbide (SiC) devices. SiC is a wide bandgap semiconductor material, with many unique properties. SiC devices are ideally suited for high-power, highvoltage, high-frequency, high-temperature and radiation resistant applications. The DOE has expressed interest in developing SiC devices for use in extreme environments, in high energy physics applications and in power generation. The development of transistors based on the Metal Oxide Semiconductor Field Effect Transistor (MOSFET) structure will be critical to these applications.

  9. Electro-Thermal Transient Simulation of Silicon Carbide Power Mosfet

    Science.gov (United States)

    2013-06-01

    Bipolar Junction Transistor ( BJT ) between the Source region, the P-Base region and the Drift region where the source forms the emitter, the P-base...region forms the base and the drain/substrate forms the collector. If this BJT turns ON, the gate will lose control over the drain current and the over...are shorted together which in turn shorts the emitter and base of the parasitic BJT thus preventing latch-up. Figure 2. D-MOSFET half cell color

  10. SPICE modelling of the transient response of irradiated MOSFETs; Modelisation de la reponse transitoire de MOSFETs irradies avec SPICE

    Energy Technology Data Exchange (ETDEWEB)

    Pouget, V.; Lapuyade, H.; Lewis, D.; Deval, Y.; Fouillat, P. [Bordeaux-1 Univ., IXL, 33 - Talence (France); Sarger, L. [Bordeaux-1 Univ., CPMOH, 33 - Talence (France)

    1999-07-01

    A new SPICE model of irradiated MOSFET taking into account the real response of the 4 electrodes is proposed. The component that has been simulated is an NMOS transistor issued from the AMS BiCMOS 0.8 {mu}m technology. A comparison between SPICE-generated transients and PISCES device simulation demonstrates the accuracy benefits when used in complex electronic architectures. This model could be used when designing electronic circuits able to sustain hardening due to SEE (single event effect), it will be an efficient complement to the physical simulations.

  11. Skin dose measurements using MOSFET and TLD for head and neck patients treated with tomotherapy

    International Nuclear Information System (INIS)

    Kinhikar, Rajesh A.; Murthy, Vedang; Goel, Vineeta; Tambe, Chandrashekar M.; Dhote, Dipak S.; Deshpande, Deepak D.

    2009-01-01

    The purpose of this work was to estimate skin dose for the patients treated with tomotherapy using metal oxide semiconductor field-effect transistors (MOSFETs) and thermoluminescent dosimeters (TLDs). In vivo measurements were performed for two head and neck patients treated with tomotherapy and compared to TLD measurements. The measurements were subsequently carried out for five days to estimate the inter-fraction deviations in MOSFET measurements. The variation between skin dose measured with MOSFET and TLD for first patient was 2.2%. Similarly, the variation of 2.3% was observed between skin dose measured with MOSFET and TLD for second patient. The tomotherapy treatment planning system overestimated the skin dose as much as by 10-12% when compared to both MOSFET and TLD. However, the MOSFET measured patient skin doses also had good reproducibility, with inter-fraction deviations ranging from 1% to 1.4%. MOSFETs may be used as a viable dosimeter for measuring skin dose in areas where the treatment planning system may not be accurate.

  12. Formation of a vertical MOSFET for charge sensing in a Si micro-fluidic channel

    International Nuclear Information System (INIS)

    Lyu, Hong-Kun; Kim, Dong-Sun; Shin, Jang-Kyoo; Choi, Pyung; Lee, Jong-Hyun; Park, Hey-Jung; Park, Chin-Sung; Lim, Geun-Bae

    2004-01-01

    We have formed a fluidic channel that can be used in micro-fluidic systems and fabricated a 3-dimensional vertical metal-oxide semiconductor field-effect transistor (vertical MOSFET) in the convex corner of a Si micro-fluidic channel by using an anisotropic tetramethyl ammonium hydroxide (TMAH) etching solution. A Au/Cr layer was used for the gate metal and might be useful for detecting charged biomolecules. The electrical characteristics of the vertical MOSFET and its operation as a chemical sensor were investigated. At V DS = -5 V and V GS = -5 V the drain current of the device was -22.5 μA and the threshold voltage was about -1.4 V. A non-planar, non-rectangular vertical MOSFET with a trapezoidal gate was transformed into an equivalent rectangularly based one by using a Schwartz-Christoffel transformation. The LEVEL1 device parameters of the vertical MOSFET were extracted from the measured electrical device characteristics and were used in the SPICE simulation for the vertical MOSFET. The measured and the simulated results for the vertical PMOSFET showed relatively good agreement. When the vertical MOSFET was dipped into a thiol DNA solution, the drain current decreased due to charged biomolecules probably being adsorbed on the gate, which indicates that a vertical MOSFET in a Si micro-fluidic channel might be useful for sensing charged biomolecules.

  13. A low specific on-resistance SOI MOSFET with dual gates and a recessed drain

    International Nuclear Information System (INIS)

    Luo Xiao-Rong; Hu Gang-Yi; Zhang Zheng-Yuan; Luo Yin-Chun; Fan Ye; Wang Xiao-Wei; Fan Yuan-Hang; Cai Jin-Yong; Wang Pei; Zhou Kun

    2013-01-01

    A low specific on-resistance (R on,sp ) integrable silicon-on-insulator (SOI) metal-oxide semiconductor field-effect transistor (MOSFET) is proposed and investigated by simulation. The MOSFET features a recessed drain as well as dual gates, which consist of a planar gate and a trench gate extended to the buried oxide layer (BOX) (DGRD MOSFET). First, the dual gates form dual conduction channels, and the extended trench gate also acts as a field plate to improve the electric field distribution. Second, the combination of the trench gate and the recessed drain widens the vertical conduction area and shortens the current path. Third, the P-type top layer not only enhances the drift doping concentration but also modulates the surface electric field distributions. All of these sharply reduce R on,sp and maintain a high breakdown voltage (BV). The BV of 233 V and R on,sp of 4.151 mΩ·cm 2 (V GS = 15 V) are obtained for the DGRD MOSFET with 15-μm half-cell pitch. Compared with the trench gate SOI MOSFET and the conventional MOSFET, R on,sp of the DGRD MOSFET decreases by 36% and 33% with the same BV, respectively. The trench gate extended to the BOX synchronously acts as a dielectric isolation trench, simplifying the fabrication processes. (condensed matter: electronic structure, electrical, magnetic, and optical properties)

  14. Hole mobility enhancement of p-MOSFETs using global and local Ge-channel technologies

    International Nuclear Information System (INIS)

    Takagi, Shinichi; Tezuka, T.; Irisawa, T.; Nakaharai, S.; Maeda, T.; Numata, T.; Ikeda, K.; Sugiyama, N.

    2006-01-01

    Mobility enhancement technologies have currently been recognized as mandatory for future scaled MOSFETs. In this paper, we review our recent results on high hole mobility p-MOSFETs using global/local SiGe or Ge channels. There are two directions for introducing SiGe or Ge channels into Si CMOS platform. One is to use SiGe or Ge global substrates and the other is to form SiGe or Ge-channel regions locally on Si wafers. In both cases, the Ge condensation technique, where Ge-channel layers are formed by oxidizing SiGe films on SOI substrates, are effectively utilized. As for the global technologies, ultrathin GOI substrates are prepared and used to fabricate high mobility GOI p-MOSFETs. As for the local technologies, SGOI or GOI channels are formed locally in the active area of p-MOSFETs on SOI wafers. It is shown that the hole mobility enhancement factor of as high as 10 is obtained in locally fabricated p-MOSFETs through the effects of high-Ge content and the compressive strain. Furthermore, the local Ge-channel technologies are combined with global SiGe or Ge substrates for pursuing the optimal and individual design of n-MOSFETs and p-MOSFETs on a single Si wafer. The CMOS device composed of strained-Si n-MOSFETs and SGOI p-MOSFETs is successfully integrated on a same wafer, which is a promising CMOS structure under deep sub 100 nm technology nodes

  15. Characterization of MOSFET dosimeters for low-dose measurements in maxillofacial anthropomorphic phantoms.

    Science.gov (United States)

    Koivisto, Juha H; Wolff, Jan E; Kiljunen, Timo; Schulze, Dirk; Kortesniemi, Mika

    2015-07-08

    The aims of this study were to characterize reinforced metal-oxide-semiconductor field-effect transistor (MOSFET) dosimeters to assess the measurement uncertainty, single exposure low-dose limit with acceptable accuracy, and the number of exposures required to attain the corresponding limit of the thermoluminescent dosimeters (TLD). The second aim was to characterize MOSFET dosimeter sensitivities for two dental photon energy ranges, dose dependency, dose rate dependency, and accumulated dose dependency. A further aim was to compare the performance of MOSFETs with those of TLDs in an anthropomorphic phantom head using a dentomaxillofacial CBCT device. The uncertainty was assessed by exposing 20 MOSFETs and a Barracuda MPD reference dosimeter. The MOSFET dosimeter sensitivities were evaluated for two photon energy ranges (50-90 kVp) using a constant dose and polymethylmethacrylate backscatter material. MOSFET and TLD comparative point-dose measurements were performed on an anthropomorphic phantom that was exposed with a clinical CBCT protocol. The MOSFET single exposure low dose limit (25% uncertainty, k = 2) was 1.69 mGy. An averaging of eight MOSFET exposures was required to attain the corresponding TLD (0.3 mGy) low-dose limit. The sensitivity was 3.09 ± 0.13 mV/mGy independently of the photon energy used. The MOSFET dosimeters did not present dose or dose rate sensitivity but, however, presented a 1% decrease of sensitivity per 1000 mV for accumulated threshold voltages between 8300 mV and 17500 mV. The point doses in an anthropomorphic phantom ranged for MOSFETs between 0.24 mGy and 2.29 mGy and for TLDs between 0.25 and 2.09 mGy, respectively. The mean difference was -8%. The MOSFET dosimeters presented statistically insignificant energy dependency. By averaging multiple exposures, the MOSFET dosimeters can achieve a TLD-comparable low-dose limit and constitute a feasible method for diagnostic dosimetry using anthropomorphic phantoms. However, for single in

  16. Simulation of dual-gate SOI MOSFET with different dielectric layers

    Science.gov (United States)

    Yadav, Jyoti; Chaudhary, R.; Mukhiya, R.; Sharma, R.; Khanna, V. K.

    2016-04-01

    The paper presents the process design and simulation of silicon-on-insulator (SOI)-based dual-gate metal oxide field-effect transistor (DG-MOSFET) stacked with different dielectric layers on the top of gate oxide. A detailed 2D process simulation of SOI-MOSFETs and its electrical characterization has been done using SILVACO® TCAD tool. A variation in transconductance was observed with different dielectric layers, AlN-gate MOSFET having the highest tranconductance value as compared to other three dielectric layers (SiO2, Si3N4 and Al2O3).

  17. Simulation and parameter optimization of polysilicon gate biaxial strained silicon MOSFETs

    CSIR Research Space (South Africa)

    Tsague, HD

    2015-10-01

    Full Text Available and Parameter Optimization of Polysilicon Gate Biaxial Strained Silicon MOSFETs Hippolyte Djonon Tsague Council for Scientific and Industrial Research (CSIR) Modelling and Digital Science (MDS) Pretoria, South Africa hdjonontsague...

  18. Towards Prognostics of Power MOSFETs: Accelerated Aging and Precursors of Failure

    Data.gov (United States)

    National Aeronautics and Space Administration — This paper presents research results dealing with power MOSFETs (metal oxide semiconductor field effect tran- sistor) within the prognostics and health management of...

  19. Performance of a thermal imager employing a hybrid pyroelectric detector array with MOSFET readout

    International Nuclear Information System (INIS)

    Watton, R.; Mansi, M.V.

    1988-01-01

    A thermal imager employing a two-dimensional hybrid array of pyroelectric detectors with MOSFET readout has been built. The design and theoretical performance of the detector are discussed, and the results of performance measurements are presented. 8 references

  20. Sensitivity of P-Channel MOSFET to X- and Gamma-Ray Irradiation

    Directory of Open Access Journals (Sweden)

    Milić Pejović

    2013-01-01

    Full Text Available Investigation of Al-gate p-channel MOSFETs sensitivity following irradiation using 200 and 280 kV X-ray beams as well as gamma-ray irradiation of 60Co in the dose range from 1 to 5 Gy was performed in this paper. The response followed on the basis of threshold voltage shift and was studied as a function of absorbed dose. It was shown that the most significant change in threshold voltage was in the case of MOSFET irradiation in X-ray fields of 200 kV and when the gate voltage was +5 V. For practical applications in dosimetry, the sensitivity of the investigated MOSFETs was also satisfactory for X-ray tube voltage of 280 kV and for gamma rays. Possible processes in gate oxide caused by radiation and its impact on the response of MOSFETs were also analyzed in this paper.

  1. Rapid Thermal Chemical Vapor Deposition for Dual-Gated Sub-100 nm MOSFET's

    National Research Council Canada - National Science Library

    Sturm, James

    2001-01-01

    .... The scaling of vertical p-channel MOSFET's with the source and drain doped with boron during low temperature epitaxy is limited by the diffusion of boron during subsequent side wall gate oxidation...

  2. Study of strained-Si p-channel MOSFETs with HfO2 gate dielectric

    Science.gov (United States)

    Pradhan, Diana; Das, Sanghamitra; Dash, Tara Prasanna

    2016-10-01

    In this work, the transconductance of strained-Si p-MOSFETs with high-K dielectric (HfO2) as gate oxide, has been presented through simulation using the TCAD tool Silvaco-ATLAS. The results have been compared with a SiO2/strained-Si p-MOSFET device. Peak transconductance enhancement factors of 2.97 and 2.73 has been obtained for strained-Si p-MOSFETs in comparison to bulk Si channel p-MOSFETs with SiO2 and high-K dielectric respectively. This behavior is in good agreement with the reported experimental results. The transconductance of the strained-Si device at low temperatures has also been simulated. As expected, the mobility and hence the transconductance increases at lower temperatures due to reduced phonon scattering. However, the enhancements with high-K gate dielectric is less as compared to that with SiO2.

  3. Enhancement of Transistor-to-Transistor Variability Due to Total Dose Effects in 65-nm MOSFETs

    CERN Document Server

    Gerardin, S; Cornale, D; Ding, L; Mattiazzo, S; Paccagnella, A; Faccio, F; Michelis, S

    2015-01-01

    We studied device-to-device variations as a function of total dose in MOSFETs, using specially designed test structures and procedures aimed at maximizing matching between transistors. Degradation in nMOSFETs is less severe than in pMOSFETs and does not show any clear increase in sample-to-sample variability due to the exposure. At doses smaller than 1 Mrad( SiO2) variability in pMOSFETs is also practically unaffected, whereas at very high doses-in excess of tens of Mrad( SiO2)-variability in the on-current is enhanced in a way not correlated to pre-rad variability. The phenomenon is likely due to the impact of random dopant fluctuations on total ionizing dose effects.

  4. Improved spatial resolution by MOSFET dosimetry of an x-ray microbeam.

    Science.gov (United States)

    Kaplan, G I; Rosenfeld, A B; Allen, B J; Booth, J T; Carolan, M G; Holmes-Siedle, A

    2000-01-01

    Measurement of the lateral profile of the dose distribution across a narrow x-ray microbeam requires a dosimeter with a micron resolution. We investigated the use of a MOSFET dosimeter in an "edge-on" orientation with the gate insulating oxide layer parallel to the direction of the beam. We compared results using this technique to Gafchromic film measurements of a 200 micrometer wide planar x-ray microbeam. The microbeam was obtained by using a vernier micrometer-driven miniature collimator attached to a Therapax DXT300 x-ray machine operated at 100 kVp. The "edge-on" application allows utilization of the ultra thin sensitive volume of the MOSFET detector. Spatial resolution of both the MOSFET and Gafchromic film dosimeters appeared to be of about 1 micrometer. The MOSFET dosimeter appeared to provide more uniform dose profiles with the advantage of on-line measurements.

  5. Development of MOS-FET based Marx generator with self-proved gate power

    International Nuclear Information System (INIS)

    Tokuchi, A.; Jiang, W.; Takayama, K.; Arai, T.; Kawakubo, T.; Adachi, T.

    2012-01-01

    New MOS-FET based Marx generator is described. An electric gate power for the MOS-FET is provided from the Marx main circuit itself. Four-stage Marx generator generates -12kV of the output voltage. The Marx Generator is successfully used to drive an Einzel lens chopper to generate a short pulsed ion beam for a KEK digital accelerator. (author)

  6. Evidence of the ion's impact position effect on SEB in N-channel power MOSFETs

    International Nuclear Information System (INIS)

    Dachs, C.; Roubaud, F.; Palau, J.M.; Bruguier, G.; Gasiot, J.

    1994-01-01

    Triggering of Single Event Burnout (SEB) in Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) is studied by means of experiments and simulations based on real structures. Conditions for destructive and nondestructive events are investigated through current duration observations. The effect of the ion's impact position is experimentally pointed out. Finally, further investigation with 2D MEDICI simulations show that the different regions of the MOSFET cell indeed exhibit different sensitivity with respect to burnout triggering

  7. A new compact subthreshold behavior model for dual-material surrounding gate (DMSG) MOSFETs

    Science.gov (United States)

    Chiang, T. K.

    2009-05-01

    On the basis of exact resultant solution of two-dimensional Poisson equation, a new compact subthreshold behavior model comprising two-dimensional potential, threshold voltage, subthreshold current and subthreshold swing for the dual-material surrounding gate (DMSG) MOSFETs is successfully developed. The model shows its validity by a good agreement with the simulated results from published device simulation software MEDICI. Besides offering the physical insight into device physics, the model provides the basic designing guidance for the DMSG MOSFETs.

  8. Assessment of Global Variability in UTBB MOSFETs in Subthreshold Regime

    Directory of Open Access Journals (Sweden)

    Sergej Makovejev

    2014-07-01

    Full Text Available The global variability of ultra-thin body and buried oxide (UTBB MOSFETs in subthreshold and off regimes of operation is analyzed. The variability of the off-state drain current, subthreshold slope, drain-induced barrier lowering (DIBL, gate leakage current, threshold voltage and their correlations are considered. Two threshold voltage extraction techniques were used. It is shown that the transconductance over drain current (gm/Id method is preferable for variability studies. It is demonstrated that the subthreshold drain current variability in short channel devices cannot be described by threshold voltage variability. It is suggested to include the effective body factor incorporating short channel effects in order to properly model the subthreshold drain current variability.

  9. Comparison of results from simple expressions for MOSFET parameter extraction

    Science.gov (United States)

    Buehler, M. G.; Lin, Y.-S.

    1988-01-01

    In this paper results are compared from a parameter extraction procedure applied to the linear, saturation, and subthreshold regions for enhancement-mode MOSFETs fabricated in a 3-micron CMOS process. The results indicate that the extracted parameters differ significantly depending on the extraction algorithm and the distribution of I-V data points. It was observed that KP values vary by 30 percent, VT values differ by 50 mV, and Delta L values differ by 1 micron. Thus for acceptance of wafers from foundries and for modeling purposes, the extraction method and data point distribution must be specified. In this paper measurement and extraction procedures that will allow a consistent evaluation of measured parameters are discussed.

  10. Using TLM principles to determine MOSFET contact and parasitic resistance

    Science.gov (United States)

    Reeves, Geoffrey K.; Harrison, H. Barry

    1997-08-01

    Transmission Line Model (TLM) networks are commonly used to model planar metal-semiconductor ohmic contacts. Multiple layer contacts such as non-alloyed {n +}/{n}, heterojunction and metal-silicide-silicon contacts can also be analyzed using a Tri-Layer TLM (TLTLM) network. In this article, two and three layer contact structures are combined using the appropriate TLM models in order to electrically model the gate-drain/source extension and drain/source contact region of a MOSFET. Important device properties such as contact and parasitic resistance can thus be derived for various device structures in terms of the geometrical and material parameters used in the TLM model. The developed model is used to give an example calculation of the parasitic resistance in the gate-drain extension and the resistance of the ohmic contact.

  11. Optimization of MOSFET-type sensor calibration for the implementation of in vivo dosimetry in stereotactic radiosurgery; Optimisation de la calibration de capteurs de type MOSFET pour la mise en oeuvre de la dosimetrie in vivo en radiochirurgie stereotaxique

    Energy Technology Data Exchange (ETDEWEB)

    Sors, A. [Laboratoire d' etude et de recherche en imagerie spatiale et medicale, universite Paul-Sabatier, 31 - Toulouse (France); Cassol, E.; Duthil, P. [Unite de radiophysique et de radioprotection, CHU Toulouse, 31 (France); Cassol, E.; Lotterie, J.A.; Berry, I.; Franceries, X. [Inserm UMRS 825, 31 - Toulouse (France); Hallil, A. [Best Medical Canada, Ottawa (Canada); Sors, A.; Latorzeff, I.; Lotterie, J.A.; Redon, A.; Berry, I. [Centre de radiochirurgie stereotaxique, CHU Rangueil, 31 - Toulouse (France); Latorzeff, I.; Redon, A.; Berry, I. [Groupe Oncorad Garonne, 31 - Toulouse (France); Sors, A.; Cassol, E.; Hallil, A.; Latorzeff, I.; Duthil, P.; Lotterie, J.A.; Redon, A.; Berry, I.; Franceries, X. [Universite Paul-Sabatier, Toulouse-3, 31 - Toulouse (France)

    2010-10-15

    Within the frame of a project of assessment of in vivo dosimetry methods in stereotactic radiosurgery delivering an irradiation by a conformational dynamic arc therapy technique, the authors more precisely report the assessment and optimization of the calibration of MOSFET and micro MOSFET sensors. Measurements are performed on a Navel's system equipped with a multi-blade collimator. Short communication

  12. Radiation dose response of N channel MOSFET submitted to filtered X-ray photon beam

    Science.gov (United States)

    Gonçalves Filho, Luiz C.; Monte, David S.; Barros, Fabio R.; Santos, Luiz A. P.

    2018-01-01

    MOSFET can operate as a radiation detector mainly in high-energy photon beams, which are normally used in cancer treatments. In general, such an electronic device can work as a dosimeter from threshold voltage shift measurements. The purpose of this article is to show a new way for measuring the dose-response of MOSFETs when they are under X-ray beams generated from 100kV potential range, which is normally used in diagnostic radiology. Basically, the method consists of measuring the MOSFET drain current as a function of the radiation dose. For this the type of device, it has to be biased with a high value resistor aiming to see a substantial change in the drain current after it has been irradiated with an amount of radiation dose. Two types of N channel device were used in the experiment: a signal transistor and a power transistor. The delivered dose to the device was varied and the electrical curves were plotted. Also, a sensitivity analysis of the power MOSFET response was made, by varying the tube potential of about 20%. The results show that both types of devices have responses very similar, the shift in the electrical curve is proportional to the radiation dose. Unlike the power MOSFET, the signal transistor does not provide a linear function between the dose rate and its drain current. We also have observed that the variation in the tube potential of the X-ray equipment produces a very similar dose-response.

  13. An extensive investigation of work function modulated trapezoidal recessed channel MOSFET

    Science.gov (United States)

    Lenka, Annada Shankar; Mishra, Sikha; Mishra, Satyaranjan; Bhanja, Urmila; Mishra, Guru Prasad

    2017-11-01

    The concept of silicon on insulator (SOI) and grooved gate help to lessen the short channel effects (SCEs). Again the work function modulation along the metal gate gives a better drain current due to the uniform electric field along the channel. So all these concepts are combined and used in the proposed MOSFET structure for more improved performance. In this work, trapezoidal recessed channel silicon on insulator (TRC-SOI) MOSFET and work function modulated trapezoidal recessed channel silicon on insulator (WFM-TRC-SOI) MOSFET are compared with DC and RF parameters and later linearity of both the devices is tested. An analytical model is formulated by using a 2-D Poisson's equation and develops a compact equation for threshold voltage using minimum surface potential. In this work we analyze the effect of negative junction depth and the corner angle on various device parameters such as minimum surface potential, sub-threshold slope (SS), drain induced barrier lowering (DIBL) and threshold voltage. The analysis interprets that the switching performance of WFM-TRC-SOI MOSFET surpasses TRC-SOI MOSFET in terms of high Ion/Ioff ratio and also the proposed structure can minimize the short channel effects (SCEs) in RF application. The validity of proposed model has been verified with simulation result performed on Sentaurus TCAD device simulator.

  14. SEGR- and SEB-hardened structure with DSPSOI in power MOSFETs

    Science.gov (United States)

    Tang, Zhaohuan; Fu, Xinghua; Yang, Fashun; Tan, Kaizhou; Ma, Kui; Wu, Xue; Lin, Jiexing

    2017-12-01

    Single event irradiation-hardened power MOSFET is the most important device for DC/DC converter in space environment application. Single event gate rupture (SEGR) and single event burnout (SEB), which will degrade the running safety and reliability of spacecraft, are the two typical failure modes in power MOSFETs. In this paper, based on recombination mechanism of interface between oxide and silicon, a novel hardened power MOSFETs structure for SEGR and SEB is proposed. The structure comprises double stagger partial silicon-on-insulator (DSPSOI) layers. Results show that the safety operation area (SOA) of a 130 V N-channel power MOSFET in single event irradiation environment is enhanced by up to 50% when the linear-energy-transfer value of heavy ion is a constant of 98 MeV·cm2/mg in the whole incident track, and the other parameters are almost maintained at the same value. Thus this novel structure can be widely used in designing single event irradiation-hardened power MOSFETs. Project supported by the National Natural Science Foundation of China (No. 61464002), the Grand Science and Technology Special Project in Guizhou Province of China (No. [2015]6006), and the Ministry of Education Open Foundation for Semiconductor Power Device Reliability (No. 010201).

  15. An Updated Perspective of Single Event Gate Rupture and Single Event Burnout in Power MOSFETs

    Science.gov (United States)

    Titus, Jeffrey L.

    2013-06-01

    Studies over the past 25 years have shown that heavy ions can trigger catastrophic failure modes in power MOSFETs [e.g., single-event gate rupture (SEGR) and single-event burnout (SEB)]. In 1996, two papers were published in a special issue of the IEEE Transaction on Nuclear Science [Johnson, Palau, Dachs, Galloway and Schrimpf, “A Review of the Techniques Used for Modeling Single-Event Effects in Power MOSFETs,” IEEE Trans. Nucl. Sci., vol. 43, no. 2, pp. 546-560, April. 1996], [Titus and Wheatley, “Experimental Studies of Single-Event Gate Rupture and Burnout in Vertical Power MOSFETs,” IEEE Trans. Nucl. Sci., vol. 43, no. 2, pp. 533-545, Apr. 1996]. Those two papers continue to provide excellent information and references with regard to SEB and SEGR in vertical planar MOSFETs. This paper provides updated references/information and provides an updated perspective of SEB and SEGR in vertical planar MOSFETs as well as provides references/information to other device types that exhibit SEB and SEGR effects.

  16. High performance multi-finger MOSFET on SOI for RF amplifiers

    Science.gov (United States)

    Adhikari, M. Singh; Singh, Y.

    2017-10-01

    In this paper, we propose structural modifications in the conventional planar metal-oxide-semiconductor field-effect transistor (MOSFET) on silicon-on-insulator by utilizing trenches in the epitaxial layer. The proposed multi-finger MOSFET (MF-MOSFET) has dual vertical-gates placed in separate trenches to form multiple channels in the p-base which carry the drain current in parallel. The proposed device uses TaN as gate electrode and SiO2 as gate dielectric. Simultaneous conduction of multiple channels enhances the drain current (ID) and provides higher transconductance (gm) leading to significant improvement in cut-off frequency (ft). Two-dimensional simulations are performed to evaluate and compare the performance of the MF-MOSFET with the conventional MOSFET. At a gate length of 60 nm, the proposed device provides 4 times higher ID, 3 times improvement in gm and 1.25 times increase in ft with better control over the short channel effects as compared with the conventional device.

  17. Fabrication and Characteristics of an nc-Si/c-Si Heterojunction MOSFETs Pressure Sensor

    Directory of Open Access Journals (Sweden)

    Xiaofeng Zhao

    2012-05-01

    Full Text Available A novel nc-Si/c-Si heterojunction MOSFETs pressure sensor is proposed in this paper, with four p-MOSFETs with nc-Si/c-Si heterojunction as source and drain. The four p-MOSFETs are designed and fabricated on a square silicon membrane by CMOS process and MEMS technology where channel resistances of the four nc-Si/c-Si heterojunction MOSFETs form a Wheatstone bridge. When the additional pressure is P, the nc-Si/c-Si heterojunction MOSFETs pressure sensor can measure this additional pressure P. The experimental results show that when the supply voltage is 3 V, length-width (L:W ratio is 2:1, and the silicon membrane thickness is 75 μm, the full scale output voltage of the pressure sensor is 15.50 mV at room temperature, and pressure sensitivity is 0.097 mV/kPa. When the supply voltage and L:W ratio are the same as the above, and the silicon membrane thickness is 45 μm, the full scale output voltage is 43.05 mV, and pressure sensitivity is 2.153 mV/kPa. Therefore, the sensor has higher sensitivity and good temperature characteristics compared to the traditional piezoresistive pressure sensor.

  18. Fabrication and characteristics of an nc-Si/c-Si heterojunction MOSFETs pressure sensor.

    Science.gov (United States)

    Zhao, Xiaofeng; Wen, Dianzhong; Li, Gang

    2012-01-01

    A novel nc-Si/c-Si heterojunction MOSFETs pressure sensor is proposed in this paper, with four p-MOSFETs with nc-Si/c-Si heterojunction as source and drain. The four p-MOSFETs are designed and fabricated on a square silicon membrane by CMOS process and MEMS technology where channel resistances of the four nc-Si/c-Si heterojunction MOSFETs form a Wheatstone bridge. When the additional pressure is P, the nc-Si/c-Si heterojunction MOSFETs pressure sensor can measure this additional pressure P. The experimental results show that when the supply voltage is 3 V, length-width (L:W) ratio is 2:1, and the silicon membrane thickness is 75 μm, the full scale output voltage of the pressure sensor is 15.50 mV at room temperature, and pressure sensitivity is 0.097 mV/kPa. When the supply voltage and L:W ratio are the same as the above, and the silicon membrane thickness is 45 μm, the full scale output voltage is 43.05 mV, and pressure sensitivity is 2.153 mV/kPa. Therefore, the sensor has higher sensitivity and good temperature characteristics compared to the traditional piezoresistive pressure sensor.

  19. Modeling and Performance Evaluation of a Top Gated Graphene MOSFET

    Directory of Open Access Journals (Sweden)

    Jith Sarker

    2017-08-01

    Full Text Available In the modernistics years, Graphene has become a promising resplendence in the horizon of fabrication technology, due to some of its unique electronic properties like zero band gap, high saturation velocity, higher electrical conductivity and so on followed by extraordinary thermal, optical and mechanical properties such as- high thermal conductivity, optical transparency, flexibility and thinness. Graphene based devices demand to be deliberated as a possible option for post Si based fabrication technology. In this paper, we have modelled a top gated graphene metal oxide semiconductor field effect transistor (MOSFET. Surface potential dependent Quantum capacitance is obtained self-consistently along with linear and square root approximation model. Gate voltage dependence of surface potential has been analyzed with graphical illustrations and required mathematics as well. Output characteristics, transfer characteristics, transconductance (as a function of gate voltage behavior have been investigated. In the end, effect of channel length on device performance has been justified. Variation of effective mobility and minimum carrier density with respect to channel length has also been observed. Considering all of the graphical illustrations, we do like to conclude that, graphene will be a successor in post silicon era and bring revolutionary changes in the field of fabrication technology.

  20. Optimization of MOSFET-type sensor calibration for the implementation of in vivo dosimetry in stereotactic radiosurgery

    International Nuclear Information System (INIS)

    Sors, A.; Cassol, E.; Duthil, P.; Cassol, E.; Lotterie, J.A.; Berry, I.; Franceries, X.; Hallil, A.; Sors, A.; Latorzeff, I.; Lotterie, J.A.; Redon, A.; Berry, I.; Latorzeff, I.; Redon, A.; Berry, I.; Sors, A.; Cassol, E.; Hallil, A.; Latorzeff, I.; Duthil, P.; Lotterie, J.A.; Redon, A.; Berry, I.; Franceries, X.

    2010-01-01

    Within the frame of a project of assessment of in vivo dosimetry methods in stereotactic radiosurgery delivering an irradiation by a conformational dynamic arc therapy technique, the authors more precisely report the assessment and optimization of the calibration of MOSFET and micro MOSFET sensors. Measurements are performed on a Navel's system equipped with a multi-blade collimator. Short communication

  1. Performance analysis of commercial MOSFET packages in Class E converter operating at 2.56 MHz

    DEFF Research Database (Denmark)

    Nair, Unnikrishnan Raveendran; Munk-Nielsen, Stig; Jørgensen, Asger Bjørn

    2017-01-01

    are not commercially available and power modules have to be custom designed for these applications. This work demonstrates performance of various commercial MOSFET packages at frequency of 2.56 MHz. Commercial SiC MOSFETs in TO-247 and D2Pak packs are tested in Class E resonant converter operating at 2.56 MHz...... resistance and high temperature operation over Si devices have aided in the paradigm shift towards wide bandgap devices. The low gate charge requirements of SiC MOSFETs enables use of these devices in radio frequency (RF) converters using resonant topologies operating at MHz frequency range. The RF...... converters employed in various industrial applications are currently realized with vacuum tubes. Replacing vacuum tubes with solid state devices provides greater reliability. This requires power switches transferring high power at high switching speeds. Wide bandgap devices operating at these specifications...

  2. Study of line-TFET analog performance comparing with other TFET and MOSFET architectures

    Science.gov (United States)

    Agopian, Paula Ghedini Der; Martino, João Antonio; Vandooren, Anne; Rooyackers, Rita; Simoen, Eddy; Thean, Aaron; Claeys, Cor

    2017-02-01

    In this work the Line-TFET performance is compared with MOSFET and Point-TFET devices, with different architectures (FinFET and GAA:Gate-All-Around) at both room and high temperatures. This analysis is based on the experimental basic analog parameters such as transconductance (gm), output conductance (gD) and intrinsic voltage gain (AV). Although the Line-TFETs present worse AV than the point-TFETs, when they are compared with MOSFET technology, the line-TFET shows a much better intrinsic voltage gain than both MOSFET architectures (FinFET and GAA). Besides the AV, the highest on-state current was obtained for Line-TFETs when compared with other two TFET architectures, which leads to a good compromise for analog application.

  3. Characterization of vertical strain silicon MOSFET incorporating dielectric pocket (SDP-VMOSFET)

    International Nuclear Information System (INIS)

    Napiah, Z. A. F. M.; Makhtar, N.; Othman, M. A.; Idris, M. I.; Arith, F.; Yasin, N. Y. M.; Taib, S. N.

    2014-01-01

    The vertical Metal-Oxide-Semiconductor Field-Effect-Transistor (MOSFET) leads to a double channel width that can increase the packaging density. The strained silicon MOSFET was introduced to modify the carrier transport properties of silicon in order to enhance transport of both electrons and holes within strained layer. Dielectric pocket was act to control encroachment of the drain doping into the channel and reduce short channel effects (SCE). SDP-VMOSFET which was a combination of those advantages was proposed to overcome the SCE in term of leakage current, threshold voltage roll-off also Drain Induce Barrier Lowering (DIBL). As a result, SDP-VMOSFET produces a better threshold voltage and DIBL compared to related structures. Meanwhile, it gives slightly increased for leakage current compared to Vertical MOSFET Incorporating Dielectric Pocket. The characteristics of the SDP-VMOSFET are analyzed in order to optimize the performance of the device and leading to the next generation of IC technology

  4. Investigation of Short Channel Effect on Vertical Structures in Nanoscale MOSFET

    Directory of Open Access Journals (Sweden)

    Munawar A. Riyadi

    2009-12-01

    Full Text Available The recent development of MOSFET demands innovative approach to maintain the scaling into nanoscale dimension. This paper focuses on the physical nature of vertical MOSFET in nanoscale regime. Vertical structure is one of the promising devices in further scaling, with relaxed-lithography feature in the manufacture. The comparison of vertical and lateral MOSFET performance for nanoscale channel length (Lch is demonstrated with the help of numerical tools. The evaluation of short channel effect (SCE parameters, i.e. threshold voltage roll-off, subthreshold swing (SS, drain induced barrier lowering (DIBL and leakage current shows the considerable advantages as well as its thread-off in implementing the structure, in particular for nanoscale regime.

  5. Modelling of MOSFET inversion layer conductivity using the resistor network method

    International Nuclear Information System (INIS)

    Kingdon, R.D.

    1988-10-01

    The subthreshold conductance of a MOSFET is smaller than predicted by elementary theory because of inhomogeneity in the inversion layer channel. Prediction of the true conductance thus requires specification of the degree and type of inhomogeneity plus a knowledge of how this suppresses the conductance. To investigate the latter effect the quasi two dimensional MOSFET channel has been simulated by a two dimensional resistor network. This method is computationally efficient and very versatile regarding the choice of inhomogeneity. The starting point for the research is that radiation directly affects the homogeneity of the MOSFET inversion layer. Therefore, a study of radiation damage requires an understanding of the effects of inhomogeneities and an ability to model them. The effects can be used to measure the radiation dose as in radiation dosemeters, or they may need to be suppressed for devices used in space. (author)

  6. Simulating single-event burnout of n-channel power MOSFET's

    International Nuclear Information System (INIS)

    Johnson, G.H.; Hohl, J.H.; Schrimpf, R.D.; Galloway, K.F.

    1993-01-01

    Heavy ions are ubiquitous in a space environment. Single-event burnout of power MOSFET's is a sudden catastrophic failure mechanism that is initiated by the passage of a heavy ion through the device structure. The passage of the heavy ion generates a current filament that locally turns on a parasitic n-p-n transistor inherent to the power MOSFET. Subsequent high currents and high voltage in the device induce second breakdown of the parasitic bipolar transistor and hence meltdown of the device. This paper presents a model that can be used for simulating the burnout mechanism in order to gain insight into the significant device parameters that most influence the single-event burnout susceptibility of n-channel power MOSFET's

  7. Performance analysis of commercial MOSFET packages in Class E converter operating at 2.56 MHz

    DEFF Research Database (Denmark)

    Nair, Unnikrishnan Raveendran; Munk-Nielsen, Stig; Jørgensen, Asger Bjørn

    2017-01-01

    resistance and high temperature operation over Si devices have aided in the paradigm shift towards wide bandgap devices. The low gate charge requirements of SiC MOSFETs enables use of these devices in radio frequency (RF) converters using resonant topologies operating at MHz frequency range. The RF...... converters employed in various industrial applications are currently realized with vacuum tubes. Replacing vacuum tubes with solid state devices provides greater reliability. This requires power switches transferring high power at high switching speeds. Wide bandgap devices operating at these specifications...... are not commercially available and power modules have to be custom designed for these applications. This work demonstrates performance of various commercial MOSFET packages at frequency of 2.56 MHz. Commercial SiC MOSFETs in TO-247 and D2Pak packs are tested in Class E resonant converter operating at 2.56 MHz...

  8. Modeling the drain current and its equation parameters for lightly doped symmetrical double-gate MOSFETs

    International Nuclear Information System (INIS)

    Bhartia, Mini; Chatterjee, Arun Kumar

    2015-01-01

    A 2D model for the potential distribution in silicon film is derived for a symmetrical double gate MOSFET in weak inversion. This 2D potential distribution model is used to analytically derive an expression for the subthreshold slope and threshold voltage. A drain current model for lightly doped symmetrical DG MOSFETs is then presented by considering weak and strong inversion regions including short channel effects, series source to drain resistance and channel length modulation parameters. These derived models are compared with the simulation results of the SILVACO (Atlas) tool for different channel lengths and silicon film thicknesses. Lastly, the effect of the fixed oxide charge on the drain current model has been studied through simulation. It is observed that the obtained analytical models of symmetrical double gate MOSFETs are in good agreement with the simulated results for a channel length to silicon film thickness ratio greater than or equal to 2. (paper)

  9. Modeling the drain current and its equation parameters for lightly doped symmetrical double-gate MOSFETs

    Science.gov (United States)

    Bhartia, Mini; Chatterjee, Arun Kumar

    2015-04-01

    A 2D model for the potential distribution in silicon film is derived for a symmetrical double gate MOSFET in weak inversion. This 2D potential distribution model is used to analytically derive an expression for the subthreshold slope and threshold voltage. A drain current model for lightly doped symmetrical DG MOSFETs is then presented by considering weak and strong inversion regions including short channel effects, series source to drain resistance and channel length modulation parameters. These derived models are compared with the simulation results of the SILVACO (Atlas) tool for different channel lengths and silicon film thicknesses. Lastly, the effect of the fixed oxide charge on the drain current model has been studied through simulation. It is observed that the obtained analytical models of symmetrical double gate MOSFETs are in good agreement with the simulated results for a channel length to silicon film thickness ratio greater than or equal to 2.

  10. Design and simulation of a nanoelectronic DG MOSFET current source using artificial neural networks

    Energy Technology Data Exchange (ETDEWEB)

    Djeffal, F. [LEA, Department of Electronics, University of Batna 05000 (Algeria)], E-mail: faycaldzdz@hotmail.com; Dibi, Z. [LEA, Department of Electronics, University of Batna 05000 (Algeria)], E-mail: zohirdibi@univ-batna.dz; Hafiane, M.L.; Arar, D. [LEA, Department of Electronics, University of Batna 05000 (Algeria)

    2007-09-15

    The double gate (DG) MOSFET has received great attention in recent years owing to the inherent suppression of short channel effects (SCEs), excellent subthreshold slope (S), improved drive current (I{sub ds}) and transconductance (gm), volume inversion for symmetric devices and excellent scalability. Therefore, simulation tools which can be applied to design nanoscale transistors in the future require new theory and modeling techniques that capture the physics of quantum transport accurately and efficiently. In this sense, this work presents the applicability of the artificial neural networks (ANN) for the design and simulation of a nanoelectronic DG MOSFET current source. The latter is based on the 2D numerical Non-Equilibrium Green's Function (NEGF) simulation of the current-voltage characteristics of an undoped symmetric DG MOSFET. Our results are discussed in order to obtain some new and useful information about the ULSI technology.

  11. A new technique to control floating body effect in nano-scale double-gate MOSFET

    Science.gov (United States)

    Zare, Meisam; Etaati, Gholamreza

    2014-11-01

    This paper proposes a novel structure of Double Gate (DG) MOSFET to control the impacts of floating body effect. Floating body effect increases hole concentration in the channel region due to the impact ionization. In this novel structure which is named as SiGe Region in DG-MOSFET (SR-DG) two spacers are considered in both sides of gate region and a SiGe zone is incorporated in gate-source spacer. The SiGe region with lower band gap than silicon collects the excess hole in the channel. Our simulation with two dimensional ATLAS simulator shows that the proposed SR-DG improves the performance of DG-MOSFET in terms of threshold voltage, breakdown voltage and electric field. Also, the impacts of parasitic bipolar junction transistor (BJT) are controlled significantly.

  12. Static and low frequency noise characterization of ultra-thin body InAs MOSFETs

    Science.gov (United States)

    Karatsori, T. A.; Pastorek, M.; Theodorou, C. G.; Fadjie, A.; Wichmann, N.; Desplanque, L.; Wallart, X.; Bollaert, S.; Dimitriadis, C. A.; Ghibaudo, G.

    2018-05-01

    A complete static and low frequency noise characterization of ultra-thin body InAs MOSFETs is presented. Characterization techniques, such as the well-known Y-function method established for Si MOSFETs, are applied in order to extract the electrical parameters and study the behavior of these research grade devices. Additionally, the Lambert-W function parameter extraction methodology valid from weak to strong inversion is also used in order to verify its applicability in these experimental level devices. Moreover, a low-frequency noise characterization of the UTB InAs MOSFETs is presented, revealing carrier trapping/detrapping in slow oxide traps and remote Coulomb scattering as origin of 1/f noise, which allowed for the extraction of the oxide trap areal density. Finally, Lorentzian-like noise is also observed in the sub-micron area devices and attributed to both Random Telegraph Noise from oxide individual traps and g-r noise from the semiconductor interface.

  13. Influences of Device and Circuit Mismatches on Paralleling Silicon Carbide MOSFETs

    DEFF Research Database (Denmark)

    Li, Helong; Munk-Nielsen, Stig; Wang, Xiongfei

    2016-01-01

    , the influence of circuit mismatch on paralleling SiC MOSFETs is investigated and experimentally evaluated for the first time. It is found that the mismatch of the switching loop stray inductance can also lead to on-state current unbalance with inductive output current, in addition to the on-state resistance......This paper addresses the influences of device and circuit mismatches on paralleling the Silicon Carbide (SiC) MOSFETs. Comprehensive theoretical analysis and experimental validation from paralleled discrete devices to paralleled dies in multichip power modules are first presented. Then...... of the device. It further reveals that circuit mismatches and a current coupling among the paralleled dies exist in a SiC MOSFET multichip power module, which is critical for the transient current distribution in the power module. Thus, a power module layout with an auxiliary source connection is developed...

  14. A novel δ-doped partially insulated dopant-segregated Schottky barrier SOI MOSFET for analog/RF applications

    International Nuclear Information System (INIS)

    Patil, Ganesh C; Qureshi, S

    2011-01-01

    In this paper, a comparative analysis of single-gate dopant-segregated Schottky barrier (DSSB) SOI MOSFET and raised source/drain ultrathin-body SOI MOSFET (RSD UTB) has been carried out to explore the thermal efficiency, scalability and analog/RF performance of these devices. A novel p-type δ-doped partially insulated DSSB SOI MOSFET (DSSB Pi-OX-δ) has been proposed to reduce the self-heating effect and to improve the high-frequency performance of DSSB SOI MOSFET over RSD UTB. The improved analog/RF figures of merit such as transconductance, transconductance generation factor, unity-gain frequency, maximum oscillation frequency, short-circuit current gain and unilateral power gain in DSSB Pi-OX-δ MOSFET show the suitability of this device for analog/RF applications. The reduced drain-induced barrier lowering, subthreshold swing and parasitic capacitances also make this device highly scalable. By using mixed-mode simulation capability of MEDICI simulator a cascode amplifier has been implemented using all the structures (RSD UTB, DSSB SOI and DSSB Pi-OX-δ MOSFETs). The results of this implementation show that the gain-bandwidth product in the case of DSSB Pi-OX-δ MOSFET has improved by 50% as compared to RSD UTB and by 20% as compared to DSSB SOI MOSFET. The detailed fabrication flow of DSSB Pi-OX-δ MOSFET has been proposed which shows that with the bare minimum of steps the performance of DSSB SOI MOSFET can be improved significantly in comparison to RSD UTB

  15. Determination of the p-spray profile for n+ p silicon sensors using a MOSFET

    Science.gov (United States)

    Fretwurst, E.; Garutti, E.; Klanner, R.; Kopsalis, I.; Schwandt, J.; Weberpals, M.

    2017-09-01

    The standard technique to electrically isolate the n+ implants of segmented silicon sensors fabricated on high-ohmic p-type silicon are p+-implants. Although the knowledge of the p+-implant dose and of the doping profile is highly relevant for the understanding and optimisation of sensors, this information is usually not available from the vendors, and methods to obtain it are highly welcome. The paper presents methods to obtain this information from circular MOSFETs fabricated as test structures on the same wafer as the sensors. Two circular MOSFETs, one with and one without a p+-implant under the gate, are used for this study. They were produced on Magnetic Czochralski silicon doped with ≈ 3 . 5 × 1012cm-2 of boron and 〈 100 〉 crystal orientation. The drain-source current as function of gate voltage for different back-side voltages is measured at a drain-source voltage of 50 mV in the linear MOSFET region, and the values of threshold voltage and mobility extracted using the standard MOSFET formulae. To determine the bulk doping, the implantation dose and profile from the data, two methods are used, which give compatible results. The doping profile, which varies between 3 . 5 × 1012cm-3 and 2 × 1015cm-3 for the MOSFET with p+-implant, is determined down to a distance of a fraction of a μm from the Si-SiO2 interface. The method of extracting the doping profiles is verified using data from a TCAD simulation of the two MOSFETs. The details of the methods and of the problems encountered are discussed.

  16. Power MOSFET-diode-based limiter for high-frequency ultrasound systems.

    Science.gov (United States)

    Choi, Hojong; Kim, Min Gon; Cummins, Thomas M; Hwang, Jae Youn; Shung, K Kirk

    2014-10-01

    The purpose of the limiter circuits used in the ultrasound imaging systems is to pass low-voltage echo signals generated by ultrasonic transducers while preventing high-voltage short pulses transmitted by pulsers from damaging front-end circuits. Resistor-diode-based limiters (a 50 Ω resistor with a single cross-coupled diode pair) have been widely used in pulse-echo measurement and imaging system applications due to their low cost and simple architecture. However, resistor-diode-based limiters may not be suited for high-frequency ultrasound transducer applications since they produce large signal conduction losses at higher frequencies. Therefore, we propose a new limiter architecture utilizing power MOSFETs, which we call a power MOSFET-diode-based limiter. The performance of a power MOSFET-diode-based limiter was evaluated with respect to insertion loss (IL), total harmonic distortion (THD), and response time (RT). We compared these results with those of three other conventional limiter designs and showed that the power MOSFET-diode-based limiter offers the lowest IL (-1.33 dB) and fastest RT (0.10 µs) with the lowest suppressed output voltage (3.47 Vp-p) among all the limiters at 70 MHz. A pulse-echo test was performed to determine how the new limiter affected the sensitivity and bandwidth of the transducer. We found that the sensitivity and bandwidth of the transducer were 130% and 129% greater, respectively, when combined with the new power MOSFET-diode-based limiter versus the resistor-diode-based limiter. Therefore, these results demonstrate that the power MOSFET-diode-based limiter is capable of producing lower signal attenuation than the three conventional limiter designs at higher frequency operation. © The Author(s) 2014.

  17. An optimized calibration method for surface measurements with MOSFETs in shaped-beam radiosurgery.

    Science.gov (United States)

    Sors, A; Cassol, E; Latorzeff, I; Duthil, P; Sabatier, J; Lotterie, J A; Redon, A; Berry, I; Franceries, X

    2014-02-01

    Nowadays MOSFET dosimeters are widely used for dose verification in radiotherapy procedures. Although their sensitive area satisfies size requirements for small field dosimetry, their use in radiosurgery has rarely been reported. The aim of this study is to propose and optimize a calibration method to perform surface measurements in 6 MV shaped-beam radiosurgery for field sizes down to 18 × 18 mm(2). The effect of different parameters such as recovery time between 2 readings, batch uniformity and build-up cap attenuation was studied. Batch uniformity was found to be within 2% and isocenter dose attenuation due to the build-up cap over the MOSFET was near 2% irrespective of field size. Two sets of sensitivity coefficients (SC) were determined for TN-502RD MOSFET dosimeters using experimental and calculated calibration; the latter being developed using an inverse square law model. Validation measurements were performed on a realistic head phantom in irregular fields. MOSFET dose values obtained by applying either measured or calculated SC were compared. For calibration, optimal results were obtained for an inter-measurement time lapse of 5 min. We also found that fitting the SC values with the inverse square law reduced the number of measurements required for calibration. The study demonstrated that combining inverse square law and Sterling-Worthley formula resulted in an underestimation of up to 4% of the dose measured by MOSFETs for complex beam geometries. With the inverse square law, it is possible to reduce the number of measurements required for calibration for multiple field-SSD combinations. Our results suggested that MOSFETs are suitable sensors for dosimetry when used at the surface in shaped-beam radiosurgery down to 18 × 18 mm(2). Copyright © 2013 Associazione Italiana di Fisica Medica. Published by Elsevier Ltd. All rights reserved.

  18. A survey of SiC power MOSFETs short-circuit robustness and failure mode analysis

    DEFF Research Database (Denmark)

    Ceccarelli, L.; Reigosa, P. D.; Iannuzzo, F.

    2017-01-01

    The aim of this paper is to provide an extensive overview about the state-of-art commercially available SiC power MOSFET, focusing on their short-circuit ruggedness. A detailed literature investigation has been carried out, in order to collect and understand the latest research contribution withi...... this topic and create a survey of the present scenario of SiC MOSFETs reliability evaluation and failure mode analysis, pointing out the evolution and improvements as well as the future challenges in this promising device technology....

  19. COMPARATIVE ANALYSIS OF QUANTUM EFFECTS IN NANOSCALE MULTIGATE MOSFETS USING VARIATIONAL APPROACH

    Directory of Open Access Journals (Sweden)

    V. PALANICHAMY

    2015-02-01

    Full Text Available In this work, the performance of multiple-gate SOI MOSFETs is analysed using variational approach including quantum effects. An analytical model is derived to accounting the quantum effects at the silicon (Si/silicon dioxide (SiO2 interface. A general procedure is used for calculating the quantum inversion charge density. Using this inversion charge density, the drain current is obtained. Our model results are compared with the simulation results and its shows very good agreement. Our results highlighted that cylindrical surrounding gate MOSFET is a good candidate to obtain the high drain current compared with other two devices.

  20. A Novel DBC Layout for Current Imbalance Mitigation in SiC MOSFET Multichip Power Modules

    DEFF Research Database (Denmark)

    Li, Helong; Munk-Nielsen, Stig; Beczkowski, Szymon

    2016-01-01

    This letter proposes a novel direct bonded copper (DBC) layout for mitigating the current imbalance among the paralleled SiC MOSFET dies in multichip power modules. Compared to the traditional layout, the proposed DBC layout significantly reduces the circuit mismatch and current coupling effect......, which consequently improves the current sharing among the paralleled SiC MOSFET dies in power module. Mathematic analysis and circuit model of the DBC layout are presented to elaborate the superior features of the proposed DBC layout. Simulation and experimental results further verify the theoretical...... analysis and current balancing performance of the proposed DBC layout....

  1. A Novel DBC Layout for Current Imbalance Mitigation in SiC MOSFET Multichip Power Modules

    DEFF Research Database (Denmark)

    Li, Helong; Munk-Nielsen, Stig; Beczkowski, Szymon

    2016-01-01

    This paper proposes a novel Direct Bonded Copper (DBC) layout for mitigating the current imbalance among the paralleled SiC MOSFET dies in multichip power modules. Compared to the traditional layout, the proposed DBC layout significantly reduces the circuit mismatch and current coupling effect......, which consequently improves the current sharing among the paralleled SiC MOSFET dies in power module. Mathematic analysis and circuit model of the DBC layout are presented to elaborate on the superior features of the proposed DBC layout. Simulation and experimental results further verify the theoretical...... analysis and current balancing performance of the proposed DBC layout....

  2. Switching Investigations on a SiC MOSFET in a TO-247 Package

    DEFF Research Database (Denmark)

    Anthon, Alexander; Hernandez Botella, Juan Carlos; Zhang, Zhe

    2014-01-01

    package, has a major influence on the switching energy. Crucial design guidelines for an improved double pulse test circuit are introduced which are used for practical investigations on the switching behavior. Switching energies of a SiC MOSFET in a TO-247 package is measured depending on varying gate......This paper deals with the switching behavior of a SiC MOSFET in a TO-247 package. Based on simulations, critical parasitic inductances in the circuit layout are analyzed and their effect on the switching losses highlighted. Especially the common source inductance, a critical parameter in a TO-247...

  3. Intrinsic Nonlinearities and Layout Impacts of 100 V Integrated Power MOSFETs in Partial SOI Process

    DEFF Research Database (Denmark)

    Fan, Lin; Knott, Arnold; Jørgensen, Ivan Harald Holger

    Parasitic capacitances of power semiconductors are a part of the key design parameters of state-of-the-art very high frequency (VHF) power supplies. In this poster, four 100 V integrated power MOSFETs with different layout structures are designed, implemented, and analyzed in a 0.18 ȝm partial...... Silicon-on-Insulator (SOI) process with a die area 2.31 mm2.  A small-signal model of power MOSFETs is proposed to systematically analyze the nonlinear parasitic capacitances in different transistor states: off-state, sub-threshold region, and on-state in the linear region. 3D plots are used to summarize...

  4. Integrated MOSFET-Embedded-Cantilever-Based Biosensor Characteristic for Detection of Anthrax Simulant

    Energy Technology Data Exchange (ETDEWEB)

    Mostafa, Salwa [University of Tennessee, Knoxville (UTK); Lee, Ida [ORNL; Islam, Syed K [University of Tennessee, Knoxville (UTK); Eliza, Sazia A. [University of Tennessee, Knoxville (UTK); Shekhawat, Gajendra [Northwestern University, Evanston; Dravid, Vinayak [Northwestern University, Evanston; Tulip, Fahmida S [ORNL

    2011-01-01

    In this work, MOSFET-embedded cantilevers are configured as microbial sensors for detection of anthrax simulants, Bacillus thuringiensis. Anthrax simulants attached to the chemically treated gold-coated cantilever cause changes in the MOSFET drain current due to the bending of the cantilever which indicates the detection of anthrax simulant. Electrical properties of the anthrax simulant are also responsible for the change in the drain current. The test results suggest a detection range of 10 L of stimulant test solution (a suspension population of 1.3 107 colony-forming units/mL diluted in 40% ethanol and 60% deionized water) with a linear response of 31 A/ L.

  5. Test setup for long term reliability investigation of Silicon Carbide MOSFETs

    DEFF Research Database (Denmark)

    Baker, Nick; Munk-Nielsen, Stig; Beczkowski, Szymon

    2013-01-01

    Silicon Carbide MOSFETs are now widely available and have frequently been demonstrated to offer numerous advantages over Silicon based devices. However, reliability issues remain a significant concern in their realisation in commercial power electronic systems. In this paper, a test bench......-state resistance is routinely monitored online through the use of an innovative voltage measurement system. The packaged Silicon Carbide MOSFET is shown to exhibit a 25% increase in on-state resistance as the device ages throughout its lifetime, with the test still on-going....

  6. The effects of ionizing radiation on commercial power MOSFETs operated at cryogenic temperatures

    International Nuclear Information System (INIS)

    Johnson, G.H.; Kemp, W.T.; Ackermann, M.R.; Pugh, R.D.; Schrimpf, R.D.; Galloway, K.F.

    1994-01-01

    This is the first report of commercial n- and p-channel power MOSFETs exposed to ionizing radiation while operating in a cryogenic environment. The transistors were exposed to low energy x-rays while placed in a liquid nitrogen-cooled dewar. Results demonstrate significant performance and survivability advantages for space-borne power MOSFETs operated at cryogenic temperatures. The key advantages for low-temperature operation of power MOSFET's in an ionizing radiation environment are: (1) steeper subthreshold current slope before and after irradiation; (2) lower off-state leakage currents before and after irradiation; and (3) larger prerad threshold voltage for n-channel devices. The first two points are also beneficial for devices that are not irradiated, but the advantages are more significant in radiation environments. The third point is only an advantage for commercial devices operated in radiation environments. Results also demonstrate that commercial off-the-shelf power MOSFETs can be used for low-temperature operations in a limited total dose environment (i.e., many space applications)

  7. Low-field mobility and carrier transport mechanism transition in nanoscale MOSFETs

    International Nuclear Information System (INIS)

    Liu Hongwei; Wang Runsheng; Huang Ru; Zhang Xing

    2010-01-01

    This paper extends the flux scattering method to study the carrier transport property in nanoscale MOSFETs with special emphasis on the low-field mobility and the transport mechanism transition. A unified analytical expression for the low-field mobility is proposed, which covers the entire regime from drift-diffusion transport to quasi-ballistic transport in 1-D, 2-D and 3-D MOSFETs. Two key parameters, namely the long-channel low-field mobility (μ 0 ) and the low-field mean free path (λ 0 ), are obtained from the experimental data, and the transport mechanism transition in MOSFETs is further discussed both experimentally and theoretically. Our work shows that λ 0 is available to characterize the inherent transition of the carrier transport mechanism rather than the low-field mobility. The mobility reduces in the MOSFET with the shrinking of the channel length; however, λ 0 is nearly a constant, and λ 0 can be used as the 'entry criterion' to determine whether the device begins to operate under quasi-ballistic transport to some extent. (semiconductor devices)

  8. Characterization of MOSFET dosimeters for low-dose measurements in maxillofacial anthropomorphic phantoms

    NARCIS (Netherlands)

    Koivisto, J.H.; Wolff, J.E.; Kiljunen, T.; Schulze, D.; Kortesniemi, M.

    2015-01-01

    The aims of this study were to characterize reinforced metal-oxide-semiconductor field-effect transistor (MOSFET) dosimeters to assess the measurement uncertainty, single exposure low-dose limit with acceptable accuracy, and the number of exposures required to attain the corresponding limit of the

  9. Optimization of Nonlinear Figure-of-Merits of Integrated Power MOSFETs in Partial SOI Process

    DEFF Research Database (Denmark)

    Fan, Lin; Jørgensen, Ivan Harald Holger; Knott, Arnold

    2016-01-01

    different operating conditions. A systematic analysis of the optimization of these FOMs has not been previously established. The optimization methods are verified on a 100 V power MOSFET implemented in a 0.18 µm partial SOI process. Its FOMs are lowered by 1.3-18.3 times and improved by 22...

  10. Serializing off-the-shelf MOSFETs by Magnetically Coupling Their Gate Electrodes

    DEFF Research Database (Denmark)

    Dimopoulos, Emmanouil; Munk-Nielsen, Stig

    2013-01-01

    While the semiconductor industry struggles with the inherent trade-offs of solid-state devices, serialization of power switches, like the Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) or the Insulated Gate Bipolar Transistor (IGBT), has been proven to be an advantageous alternative...

  11. Use of pre-irradiated commercial MOSFETs in a power supply hardened to withstand gamma radiation

    International Nuclear Information System (INIS)

    Marceau, M.; Huillet, H.

    1999-01-01

    This paper describes the approach used to design a hardened power supply capable of operating to a total gamma irradiation dose of 10 kGy(Si). Pre-irradiation of power MOSFETs proved to be necessary, and the paper also discusses the effects of this treatment. (authors)

  12. The effect of gate length on SOI-MOSFETS operation | Baedi ...

    African Journals Online (AJOL)

    The effect of gate length on the operation of silicon-on-insulator (SOI) MOSFET structure with a layer of buried silicon oxide added to isolate the device body has been simulated. Three transistors with gate lengths of 100, 200 and 500 nm were simulated. Simulations showed that with a fixed channel length, when the gate ...

  13. Analog Amplitude Modulation of a High Voltage, Solid State Inductive Adder, Pulse Generator Using MOSFETS

    International Nuclear Information System (INIS)

    Gower, E J; Sullivan, J S

    2002-01-01

    High voltage, solid state, inductive adder, pulse generators have found increasing application as fast kicker pulse modulators for charged particle beams. The solid state, inductive adder, pulse generator is similar in operation to the linear induction accelerator. The main difference is that the solid state, adder couples energy by transformer action from multiple primaries to a voltage summing stalk, instead of an electron beam. Ideally, the inductive adder produces a rectangular voltage pulse at the load. In reality, there is usually some voltage variation at the load due to droop on primary circuit storage capacitors, or, temporal variations in the load impedance. Power MOSFET circuits have been developed to provide analog modulation of the output voltage amplitude of a solid state, inductive adder, pulse generator. The modulation is achieved by including MOSFET based, variable subtraction circuits in the multiple primary stack. The subtraction circuits can be used to compensate for voltage droop, or, to tailor the output pulse amplitude to provide a desired effect in the load. Power MOSFET subtraction circuits have been developed to modulate short, temporal (60-400 ns), voltage and current pulses. MOSFET devices have been tested up to 20 amps and 800 Volts with a band pass of 50 MHz. An analog modulation cell has been tested in a five cell high, voltage adder stack

  14. A Fast Electro-Thermal Co-Simulation Modeling Approach for SiC Power MOSFETs

    DEFF Research Database (Denmark)

    Ceccarelli, Lorenzo; Bahman, Amir Sajjad; Iannuzzo, Francesco

    2017-01-01

    the FEM simulation of the DUT’s structure, performed in ANSYS Icepack. A MATLAB script is used to process the simulation data and feed the needed settings and parameters back into the simulation. The parameters for a CREE 1.2 kV/30 A SiC MOSFET have been identified and the electro-thermal model has been...

  15. Cryogenic readout electronics with silicon P-MOSFETS for the infrared astronomical satellite, ASTRO-F

    Science.gov (United States)

    Hirao, T.; Hibi, Y.; Kawada, M.; Nagata, H.; Shibai, H.; Watabe, T.; Noda, M.; Nakagawa, T.

    We have successfully developed a low-power, low-noise silicon p-channel MOSFET working at 1.8 K. This MOSFET was produced by a standard 0.5μm BiCMOS process. From the typical current-voltage characteristics of this p-channel MOSFET at 1.8K, we obtained that the drain resistance r d is ˜2Mω, the transconductance g m is ˜35μS, and the input referred noise voltage is as low as ˜2μV/√Hz at 1Hz under low-drain current condition (˜1μA). No "kink"-like behavior was observed within the nominal operation range (-1.5VMOSFET. The open-loop gain was ˜1000, and the power consumption was less than 10μW at 4.2K. We have finally demonstrated that the CTIA consisting of this cryogenic amplifier worked well at 4.2 K.

  16. MOSFET Loss Evaluation for a Low-Power Stand-Alone Photovoltaic-LED System

    DEFF Research Database (Denmark)

    Mira Albert, Maria del Carmen; Knott, Arnold; Andersen, Michael A. E.

    2015-01-01

    This paper presents a performance evaluation and comparison of state-of-the-art low voltage Si MOSFETs for a stand-alone photovoltaic-LED Light to Light (LtL) system. The complete system is formed by two cascaded converters that will be optimized for a determined solar irradiation and LED...

  17. Simulation aided hardening of N-channel power MOSFETs to prevent single event burnout

    International Nuclear Information System (INIS)

    Dachs, C.; Palau, J.M.; Bruguier, G.; Gasiot, J.; Roubaud, F.; Tastet, P.; Calvet, M.C.; Calvel, P.

    1995-01-01

    2D MEDICI simulator is used to investigate hardening solutions to single-event burnout (SEB). SEB parametric dependencies such as carrier lifetime reduction, base enlargement, and emitter doping decrease have been verified and a p + plug modification approach for SEB hardening of power MOSFETs is validated with simulations on actual device structures

  18. Performance Analysis of Trench Power MOSFETs in High-Frequency Synchronous Buck Converter Applications

    Directory of Open Access Journals (Sweden)

    Yali Xiong

    2008-01-01

    Full Text Available This paper investigates the performance perspectives and theoretical limitations of trench power MOSFETs in synchronous rectifier buck converters operating in the MHz frequency range. Several trench MOSFET technologies are studied using a mixed-mode device/circuit modeling approach. Individual power loss contributions from the control and synchronous MOSFETs, and their dependence on switching frequency between 500 kHz and 5 MHz are discussed in detail. It is observed that the conduction loss contribution decreases from 40% to 4% while the switching loss contribution increases from 60% to 96% as the switching frequency increases from 500 KHz to 5 MHz. Beyond 1 MHz frequency there is no obvious benefit to increase the die size of either SyncFET or CtrlFET. The RDS(ON×QG figure of merit (FOM still correlates well to the overall converter efficiency in the MHz frequency range. The efficiency of the hard switching buck topology is limited to 80% at 2 MHz and 65% at 5 MHz even with the most advanced trench MOSFET technologies.

  19. Single-event burnout of power MOSFET devices for satellite application

    International Nuclear Information System (INIS)

    Xue Yuxiong; Tian Kai; Cao Zhou; Yang Shiyu; Liu Gang; Cai Xiaowu; Lu Jiang

    2008-01-01

    Single-event burnout (SEB) sensitivity was tested for power MOSFET devices, JTMCS081 and JTMCS062, which were made in Institute of Microelectronics, Chinese Academy of Sciences, using californium-252 simulation source. SEB voltage threshold was found for devices under test (DUT). It is helpful for engineers to choose devices used in satellites. (authors)

  20. PSpice Modeling Platform for SiC Power MOSFET Modules with Extensive Experimental Validation

    DEFF Research Database (Denmark)

    Ceccarelli, Lorenzo; Iannuzzo, Francesco; Nawaz, Muhammad

    2016-01-01

    The aim of this work is to present a PSpice implementation for a well-established and compact physics-based SiC MOSFET model, including a fast, experimental-based parameter extraction procedure in a MATLAB GUI environment. The model, originally meant for single-die devices, has been used...

  1. Optimum structures for gamma-ray radiation resistant SiC-MOSFETs

    Energy Technology Data Exchange (ETDEWEB)

    Mitomo, Satoshi; Matsuda, Takuma; Murata, Koichi; Yokoseki, Takashi [Saitama University, Sakuraku (Japan); National Institutes for Quantum and Radiological Science and Technology (QST), Takasaki (Japan); Makino, Takahiro; Takeyama, Akinori; Onoda, Shinobu; Ohshima, Takeshi [National Institutes for Quantum and Radiological Science and Technology (QST), Takasaki (Japan); Okubo, Shuichi; Tanaka, Yuki; Kandori, Mikio; Yoshie, Toru [Sanken Electric Co., Ltd., Niiza, Saitama (Japan); Hijikata, Yasuto [Saitama University, Sakuraku (Japan)

    2017-04-15

    In order to develop highly radiation-tolerant SiC MOSFETs, we investigated the dependence of the gamma-ray radiation response on the gate oxide thickness and nitridation processes, used for oxide growth and p-well implantation. SiC MOSFETs with a thick gate oxide (60 nm) showed a rapid decrease in the threshold voltage shift ΔV{sub th} of more than 400 kGy, and transitioned to the normally-on state at lower doses than those with a thin gate oxide (35 nm). The MOSFETs with gate oxides treated with lower concentrations of N{sub 2}O (10%) demonstrated a higher radiation tolerance (ΔV{sub th}, channel mobility, and subthreshold swing) than with a 100% N{sub 2}O treatment. The MOSFETs with more p-well implantation steps (three steps) showed a smaller negative shift of the threshold voltage relative to those implanted with two steps. (copyright 2017 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim)

  2. Comprehensive study of the electron scattering mechanisms in 4H-SiC MOSFETs

    Czech Academy of Sciences Publication Activity Database

    Uhnevionak, V.; Burenkov, A.; Strenger, C.; Ortiz, G.; Bedel-Pereira, E.; Mortet, Vincent; Cristiano, F.; Bauer, A.J.; Pichler, P.

    2015-01-01

    Roč. 62, č. 8 (2015), s. 2562-2570 ISSN 0018-9383 Institutional support: RVO:68378271 Keywords : electron mobility * Hall effect * scattering mechanisms * SiC MOSFET Subject RIV: BM - Solid Matter Physics ; Magnetism Impact factor: 2.207, year: 2015

  3. High-Speed Gate Driver Using GaN HEMTs for 20-MHz Hard Switching of SiC MOSFETs

    OpenAIRE

    Okuda, Takafumi; Hikihara, Takashi

    2017-01-01

    In this paper, we investigated a gate driver using a GaN HEMT push-pull configuration for the high-frequency hard switching of a SiC power MOSFET. Low on-resistance and low input capacitance of GaN HEMTs are suitable for a high-frequency gate driver from the logic level, and robustness of SiC MOSFET with high avalanche capability is suitable for a valve transistor in power converters. Our proposed gate driver consists of digital isolators, complementary Si MOSFETs, and GaN HEMTs. The GaN HEMT...

  4. Establishing a standard calibration methodology for MOSFET detectors in computed tomography dosimetry

    International Nuclear Information System (INIS)

    Brady, S. L.; Kaufman, R. A.

    2012-01-01

    Purpose: The use of metal-oxide-semiconductor field-effect transistor (MOSFET) detectors for patient dosimetry has increased by ∼25% since 2005. Despite this increase, no standard calibration methodology has been identified nor calibration uncertainty quantified for the use of MOSFET dosimetry in CT. This work compares three MOSFET calibration methodologies proposed in the literature, and additionally investigates questions relating to optimal time for signal equilibration and exposure levels for maximum calibration precision. Methods: The calibration methodologies tested were (1) free in-air (FIA) with radiographic x-ray tube, (2) FIA with stationary CT x-ray tube, and (3) within scatter phantom with rotational CT x-ray tube. Each calibration was performed at absorbed dose levels of 10, 23, and 35 mGy. Times of 0 min or 5 min were investigated for signal equilibration before or after signal read out. Results: Calibration precision was measured to be better than 5%–7%, 3%–5%, and 2%–4% for the 10, 23, and 35 mGy respective dose levels, and independent of calibration methodology. No correlation was demonstrated for precision and signal equilibration time when allowing 5 min before or after signal read out. Differences in average calibration coefficients were demonstrated between the FIA with CT calibration methodology 26.7 ± 1.1 mV cGy −1 versus the CT scatter phantom 29.2 ± 1.0 mV cGy −1 and FIA with x-ray 29.9 ± 1.1 mV cGy −1 methodologies. A decrease in MOSFET sensitivity was seen at an average change in read out voltage of ∼3000 mV. Conclusions: The best measured calibration precision was obtained by exposing the MOSFET detectors to 23 mGy. No signal equilibration time is necessary to improve calibration precision. A significant difference between calibration outcomes was demonstrated for FIA with CT compared to the other two methodologies. If the FIA with a CT calibration methodology was used to create calibration coefficients for the

  5. Technology CAD of silicided Schottky barrier MOSFET for elevated source-drain engineering

    International Nuclear Information System (INIS)

    Saha, A.R.; Chattopadhyay, S.; Bose, C.; Maiti, C.K.

    2005-01-01

    Technology CAD has been used to study the performance of a silicided Schottky barrier (SB) MOSFET with gate, source and drain contacts realized with nickel-silicide. Elevated source-drain structures have been used towards the S/D engineering of CMOS devices. A full process-to-device simulation has been employed to predict the performance of sub-micron SB n-MOSFETs for the first time. A model for the diffusion and alloy growth kinetics has been incorporated in SILVACO-ATLAS and ATHENA to explore the processing and design parameter space for the Ni-silicided MOSFETs. The temperature and concentration dependent diffusion model for NiSi have been developed and necessary material parameters for nickel-silicide and epitaxial-Si have been incorporated through the C-interpreter function. Two-dimensional (2D) process-to-device simulations have also been used to study the dc and ac (RF) performance of silicided Schottky barrier (SB) n-MOSFETs. The extracted sheet resistivity, as a function of annealing temperature of the silicided S/D contacts, is found to be lower than the conventional contacts currently in use. It is also shown that the Technology CAD has the full capability to predict the possible dc and ac performance enhancement of a MOSFET with elevated S/D structures. While the simulated dc performance shows a clear enhancement, the RF analyses show no performance degradation in the cut-off frequency/propagation delay and also improve the ac performance due to the incorporation of silicide contacts in the S/D region

  6. Technology CAD of silicided Schottky barrier MOSFET for elevated source-drain engineering

    Energy Technology Data Exchange (ETDEWEB)

    Saha, A.R. [Department of Electronics and ECE, IIT, Kharagpur 721302 (India)]. E-mail: ars.iitkgp@gmail.com; Chattopadhyay, S. [Department of Electronics and ECE, IIT, Kharagpur 721302 (India); School of Electrical, Electronics and Computer Engineering, University of Newcastle, Newcastle upon Tyne (United Kingdom); Bose, C. [Department of Electronics and Telecommunication Engineering, Jadavpur University, Calcutta 700032 (India); Maiti, C.K. [Department of Electronics and ECE, IIT, Kharagpur 721302 (India)

    2005-12-05

    Technology CAD has been used to study the performance of a silicided Schottky barrier (SB) MOSFET with gate, source and drain contacts realized with nickel-silicide. Elevated source-drain structures have been used towards the S/D engineering of CMOS devices. A full process-to-device simulation has been employed to predict the performance of sub-micron SB n-MOSFETs for the first time. A model for the diffusion and alloy growth kinetics has been incorporated in SILVACO-ATLAS and ATHENA to explore the processing and design parameter space for the Ni-silicided MOSFETs. The temperature and concentration dependent diffusion model for NiSi have been developed and necessary material parameters for nickel-silicide and epitaxial-Si have been incorporated through the C-interpreter function. Two-dimensional (2D) process-to-device simulations have also been used to study the dc and ac (RF) performance of silicided Schottky barrier (SB) n-MOSFETs. The extracted sheet resistivity, as a function of annealing temperature of the silicided S/D contacts, is found to be lower than the conventional contacts currently in use. It is also shown that the Technology CAD has the full capability to predict the possible dc and ac performance enhancement of a MOSFET with elevated S/D structures. While the simulated dc performance shows a clear enhancement, the RF analyses show no performance degradation in the cut-off frequency/propagation delay and also improve the ac performance due to the incorporation of silicide contacts in the S/D region.

  7. A 2D simulation study and characterization of a novel vertical SOI MOSFET with a smart source/body tie

    International Nuclear Information System (INIS)

    Lin, Jyi-Tsong; Lee, Tai-Yi; Lin, Kao-Cheng

    2008-01-01

    A novel vertical silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistor (MOSFET) with a smart source/body contact, SSBVMOS, is presented here for the first time. 2D simulations reveal that the SSBVMOS reduces self-heating effects, with the lattice temperature reduced by 14% and the hole temperature reduced by 25%. The SSBVMOS also eliminates the floating body effect, something that other SOI vertical MOSFETs are unable to accomplish, regardless of the thickness of the thin film. The SSBVMOS is further found to have a better drain-induced barrier lowering and subthreshold swing than either a conventional vertical MOSFET or an SOI vertical MOSFET. Moreover, these results are achieved using typical pillar heights and buried oxide thicknesses. Should future technological advances allow for lower pillars or thinner buried oxides, the SSBVMOS performance would further increase

  8. Power MOSFET Linearizer of a High-Voltage Power Amplifier for High-Frequency Pulse-Echo Instrumentation

    Science.gov (United States)

    Choi, Hojong; Woo, Park Chul; Yeom, Jung-Yeol; Yoon, Changhan

    2017-01-01

    A power MOSFET linearizer is proposed for a high-voltage power amplifier (HVPA) used in high-frequency pulse-echo instrumentation. The power MOSFET linearizer is composed of a DC bias-controlled series power MOSFET shunt with parallel inductors and capacitors. The proposed scheme is designed to improve the gain deviation characteristics of the HVPA at higher input powers. By controlling the MOSFET bias voltage in the linearizer, the gain reduction into the HVPA was compensated, thereby reducing the echo harmonic distortion components generated by the ultrasonic transducers. In order to verify the performance improvement of the HVPA implementing the power MOSFET linearizer, we measured and found that the gain deviation of the power MOSFET linearizer integrated with HVPA under 10 V DC bias voltage was reduced (−1.8 and −0.96 dB, respectively) compared to that of the HVPA without the power MOSFET linearizer (−2.95 and −3.0 dB, respectively) when 70 and 80 MHz, three-cycle, and 26 dBm input pulse waveforms are applied, respectively. The input 1-dB compression point (an index of linearity) of the HVPA with power MOSFET linearizer (24.17 and 26.19 dBm at 70 and 80 MHz, respectively) at 10 V DC bias voltage was increased compared to that of HVPA without the power MOSFET linearizer (22.03 and 22.13 dBm at 70 and 80 MHz, respectively). To further verify the reduction of the echo harmonic distortion components generated by the ultrasonic transducers, the pulse-echo responses in the pulse-echo instrumentation were compared when using HVPA with and without the power MOSFET linearizer. When three-cycle 26 dBm input power was applied, the second, third, fourth, and fifth harmonic distortion components of a 75 MHz transducer driven by the HVPA with power MOSFET linearizer (−48.34, −44.21, −48.34, and −46.56 dB, respectively) were lower than that of the HVPA without the power MOSFET linearizer (−45.61, −41.57, −45.01, and −45.51 dB, respectively). When five

  9. Power MOSFET Linearizer of a High-Voltage Power Amplifier for High-Frequency Pulse-Echo Instrumentation.

    Science.gov (United States)

    Choi, Hojong; Woo, Park Chul; Yeom, Jung-Yeol; Yoon, Changhan

    2017-04-04

    A power MOSFET linearizer is proposed for a high-voltage power amplifier (HVPA) used in high-frequency pulse-echo instrumentation. The power MOSFET linearizer is composed of a DC bias-controlled series power MOSFET shunt with parallel inductors and capacitors. The proposed scheme is designed to improve the gain deviation characteristics of the HVPA at higher input powers. By controlling the MOSFET bias voltage in the linearizer, the gain reduction into the HVPA was compensated, thereby reducing the echo harmonic distortion components generated by the ultrasonic transducers. In order to verify the performance improvement of the HVPA implementing the power MOSFET linearizer, we measured and found that the gain deviation of the power MOSFET linearizer integrated with HVPA under 10 V DC bias voltage was reduced (-1.8 and -0.96 dB, respectively) compared to that of the HVPA without the power MOSFET linearizer (-2.95 and -3.0 dB, respectively) when 70 and 80 MHz, three-cycle, and 26 dB m input pulse waveforms are applied, respectively. The input 1-dB compression point (an index of linearity) of the HVPA with power MOSFET linearizer (24.17 and 26.19 dB m at 70 and 80 MHz, respectively) at 10 V DC bias voltage was increased compared to that of HVPA without the power MOSFET linearizer (22.03 and 22.13 dB m at 70 and 80 MHz, respectively). To further verify the reduction of the echo harmonic distortion components generated by the ultrasonic transducers, the pulse-echo responses in the pulse-echo instrumentation were compared when using HVPA with and without the power MOSFET linearizer. When three-cycle 26 dB m input power was applied, the second, third, fourth, and fifth harmonic distortion components of a 75 MHz transducer driven by the HVPA with power MOSFET linearizer (-48.34, -44.21, -48.34, and -46.56 dB, respectively) were lower than that of the HVPA without the power MOSFET linearizer (-45.61, -41.57, -45.01, and -45.51 dB, respectively). When five-cycle 20 dB m input

  10. Power MOSFET Linearizer of a High-Voltage Power Amplifier for High-Frequency Pulse-Echo Instrumentation

    Directory of Open Access Journals (Sweden)

    Hojong Choi

    2017-04-01

    Full Text Available A power MOSFET linearizer is proposed for a high-voltage power amplifier (HVPA used in high-frequency pulse-echo instrumentation. The power MOSFET linearizer is composed of a DC bias-controlled series power MOSFET shunt with parallel inductors and capacitors. The proposed scheme is designed to improve the gain deviation characteristics of the HVPA at higher input powers. By controlling the MOSFET bias voltage in the linearizer, the gain reduction into the HVPA was compensated, thereby reducing the echo harmonic distortion components generated by the ultrasonic transducers. In order to verify the performance improvement of the HVPA implementing the power MOSFET linearizer, we measured and found that the gain deviation of the power MOSFET linearizer integrated with HVPA under 10 V DC bias voltage was reduced (−1.8 and −0.96 dB, respectively compared to that of the HVPA without the power MOSFET linearizer (−2.95 and −3.0 dB, respectively when 70 and 80 MHz, three-cycle, and 26 dBm input pulse waveforms are applied, respectively. The input 1-dB compression point (an index of linearity of the HVPA with power MOSFET linearizer (24.17 and 26.19 dBm at 70 and 80 MHz, respectively at 10 V DC bias voltage was increased compared to that of HVPA without the power MOSFET linearizer (22.03 and 22.13 dBm at 70 and 80 MHz, respectively. To further verify the reduction of the echo harmonic distortion components generated by the ultrasonic transducers, the pulse-echo responses in the pulse-echo instrumentation were compared when using HVPA with and without the power MOSFET linearizer. When three-cycle 26 dBm input power was applied, the second, third, fourth, and fifth harmonic distortion components of a 75 MHz transducer driven by the HVPA with power MOSFET linearizer (−48.34, −44.21, −48.34, and −46.56 dB, respectively were lower than that of the HVPA without the power MOSFET linearizer (−45.61, −41.57, −45.01, and −45.51 d

  11. Clinical application of a OneDose(TM) MOSFET for skin dose measurements during internal mammary chain irradiation with high dose rate brachytherapy in carcinoma of the breast

    International Nuclear Information System (INIS)

    Kinhikar, Rajesh A; Sharma, Pramod K; Tambe, Chandrashekhar M; Mahantshetty, Umesh M; Sarin, Rajiv; Deshpande, Deepak D; Shrivastava, Shyam K

    2006-01-01

    In our earlier study, we experimentally evaluated the characteristics of a newly designed metal oxide semiconductor field effect transistor (MOSFET) OneDose(TM) in-vivo dosimetry system for Ir-192 (380 keV) energy and the results were compared with thermoluminescent dosimeters (TLDs). We have now extended the same study to the clinical application of this MOSFET as an in-vivo dosimetry system. The MOSFET was used during high dose rate brachytherapy (HDRBT) of internal mammary chain (IMC) irradiation for a carcinoma of the breast. The aim of this study was to measure the skin dose during IMC irradiation with a MOSFET and a TLD and compare it with the calculated dose with a treatment planning system (TPS). The skin dose was measured for ten patients. All the patients' treatment was planned on a PLATO treatment planning system. TLD measurements were performed to compare the accuracy of the measured results from the MOSFET. The mean doses measured with the MOSFET and the TLD were identical (0.5392 Gy, 15.85% of the prescribed dose). The mean dose was overestimated by the TPS and was 0.5923 Gy (17.42% of the prescribed dose). The TPS overestimated the skin dose by 9% as verified by the MOSFET and TLD. The MOSFET provides adequate in-vivo dosimetry for HDRBT. Immediate readout after irradiation, small size, permanent storage of dose and ease of use make the MOSFET a viable alternative for TLDs. (note)

  12. Efficiency of Innovative Charge Pump versus Clock Frequency and MOSFETs Sizes

    Directory of Open Access Journals (Sweden)

    Matoušek David

    2016-10-01

    Full Text Available Charge pumps are circuits that produce the voltage higher than supply voltage or negative voltage. Today, charge pumps became an integral part of the electronic equipment. The integration of charge pumps directly into the system allows manufacturers to feed a complex system with many specific power requirements from a single source. However, charge pump efficiency is reduced by many phenomena. This paper is focused on the question of efficiency of proposed variant of the charge pump. In this article, the efficiency dependence on a number of stages, output current, clock frequency and MOSFETs sizes was simulated by Eldo. The aim of this study is to determine the MOSFETs sizes and theirs influence to efficiency and the output voltage. Complex optimization of the charge pump circuit will follow in further text.

  13. GaN MOSFET with Boron Trichloride-Based Dry Recess Process

    International Nuclear Information System (INIS)

    Jiang, Y; Wang, Q P; Tamai, K; Ao, J P; Ohno, Y; Miyashita, T; Motoyama, S; Wang, D J

    2013-01-01

    The dry recessed-gate GaN metal-oxide-semiconductor field-effect transistors (MOSFETs) on AlGaN/GaN heterostructure using boron trichloride (BCl 3 ) as etching gas were fabricated and characterized. Etching with different etching power was conducted. Devices with silicon tetrachloride (SiCl 4 ) etching gas were also prepared for comparison. Field-effect mobility and interface state density were extracted from current-voltage (I-V) characteristics. GaN MOSFETs on AlGaN/GaN heterostructure with BCl 3 based dry recess achieved a high maximum electron mobility of 141.5 cm 2 V −1 s −1 and a low interface state density.

  14. Role of parasitic capacitances in power MOSFET turn-on switching speed limits

    DEFF Research Database (Denmark)

    Cittanti, Davide; Iannuzzo, Francesco; Hoene, Eckart

    2017-01-01

    This paper describes the effect of MOSFET internal capacitances on the channel current during the turn-on switching transition: an intrinsic theoretical switching speed limit is found and detailed mathematically. The set of analytical equations is solved and the effect of the displacement currents...... is highlighted with ideal simulated waveforms. A laboratory experiment is thus performed, in order to prove the theoretical predictions: a 25 mΩ SiC CREE power MOSFET is turned on in a no-load condition (zero drain current), starting from different drain-source voltage values. Finally, a LTSpice equivalent...... circuit model is also built, to better simulate the experimental behavior of the device, adding circuit strain components and other non-idealities to the overall model. A good match between measurements and simulations is observed, mostly validating either the theoretical assumptions and the presented...

  15. Modeling of cylindrical surrounding gate MOSFETs including the fringing field effects

    International Nuclear Information System (INIS)

    Gupta, Santosh K.; Baishya, Srimanta

    2013-01-01

    A physically based analytical model for surface potential and threshold voltage including the fringing gate capacitances in cylindrical surround gate (CSG) MOSFETs has been developed. Based on this a subthreshold drain current model has also been derived. This model first computes the charge induced in the drain/source region due to the fringing capacitances and considers an effective charge distribution in the cylindrically extended source/drain region for the development of a simple and compact model. The fringing gate capacitances taken into account are outer fringe capacitance, inner fringe capacitance, overlap capacitance, and sidewall capacitance. The model has been verified with the data extracted from 3D TCAD simulations of CSG MOSFETs and was found to be working satisfactorily. (semiconductor devices)

  16. A compact model for single material double work function gate MOSFET

    Science.gov (United States)

    Changyong, Zheng; Wei, Zhang; Tailong, Xu; Yuehua, Dai; Junning, Chen

    2013-09-01

    An analytical surface potential model for the single material double work function gate (SMDWG) MOSFET is developed based on the exact resultant solution of the two-dimensional Poisson equation. The model includes the effects of drain biases, gate oxide thickness, different combinations of S-gate and D-gate length and values of substrate doping concentration. More attention has been paid to seeking to explain the attributes of the SMDWG MOSFET, such as suppressing drain-induced barrier lowering (DIBL), accelerating carrier drift velocity and device speed. The model is verified by comparison to the simulated results using the device simulator MEDICI. The accuracy of the results obtained using our analytical model is verified using numerical simulations. The model not only offers the physical insight into device physics but also provides the basic designing guideline for the device.

  17. Towards Accelerated Aging Methodologies and Health Management of Power MOSFETs (Technical Brief)

    Science.gov (United States)

    Celaya, Jose R.; Patil, Nishad; Saha, Sankalita; Wysocki, Phil; Goebel, Kai

    2009-01-01

    Understanding aging mechanisms of electronic components is of extreme importance in the aerospace domain where they are part of numerous critical subsystems including avionics. In particular, power MOSFETs are of special interest as they are involved in high voltage switching circuits such as drivers for electrical motors. With increased use of electronics in aircraft control, it becomes more important to understand the degradation of these components in aircraft specific environments. In this paper, we present an accelerated aging methodology for power MOSFETs that subject the devices to indirect thermal overstress during high voltage switching. During this accelerated aging process, two major modes of failure were observed - latch-up and die attach degradation. In this paper we present the details of our aging methodology along with details of experiments and analysis of the results.

  18. Comparison of experimental measurements of power MOSFET SEBs in dynamic and static modes

    International Nuclear Information System (INIS)

    Calvel, P.; Peyrotte, C.; Baiget, A.; Stassinopoulos, E.G.

    1991-01-01

    In this paper a study to determine the Single Event Burnout (SEB) sensitivity for burnout of IRF-150 Power MOSFETs in both static and dynamic modes in terms of LET threshold and cross section is described. The dynamic tests were conducted with a power converter which was designed for actual space application. The results were compared with static measurements which were made during the exposure to the heavy ions. The data showed that the dynamic mode was less sensitive than the static by two orders of magnitude in cross section. It was also observed that ions with a range less than 30 microns did not produce destructive burnout in the dynamic mode even when their LET exceeded the threshold value. The extent of physical MOSFET damage in the destructive, dynamic tests appeared to correlate with the ion LET and source-drain voltage

  19. Modification of transition's factor in the compact surface-potential-based MOSFET model

    Directory of Open Access Journals (Sweden)

    Kevkić Tijana

    2016-01-01

    Full Text Available The modification of an important transition's factor which enables continual behavior of the surface potential in entire useful range of MOSFET operation is presented. The various modifications have been made in order to obtain an accurate and computationally efficient compact MOSFET model. The best results have been achieved by introducing the generalized logistic function (GL in fitting of considered factor. The smoothness and speed of the transition of the surface potential from the depletion to the strong inversion region can be controlled in this way. The results of the explicit model with this GL functional form for transition's factor have been verified extensively with the numerical data. A great agreement was found for a wide range of substrate doping and oxide thickness. Moreover, the proposed approach can be also applied on the case where quantum mechanical effects play important role in inversion mode.

  20. Development of a new electron gun pulser by using high-speed MOS-FET's

    International Nuclear Information System (INIS)

    Suzuki, Ryoichi; Mikado, Tomohisa; Ohgaki, Hideaki; Chiwaki, Mitsukuni; Yamada, Kawakatsu; Sei, Norihiro; Sugiyama, Suguru; Noguchi, Tsutomu; Yamazaki, Tetsuo

    1993-01-01

    A new pulser for a low-emittance electron gun of the ETL linac has been developed by using high-speed MOS-FET's. The pulser can produce pulses of variable pulse width (5 ns - 4 μs) and of variable pulse height. Furthermore, the pulser can be operated with burst mode (100 ns period, more than 20 cycles) for single bunch injection to electron storage rings. (author)

  1. In vivo dosimetry with MOSFETs and GAFCHROMIC films during electron IORT for Accelerated Partial Breast Irradiation.

    Science.gov (United States)

    Petoukhova, Anna; Rüssel, Iris; Nijst-Brouwers, Julienne; van Wingerden, Ko; van Egmond, Jaap; Jacobs, Daphne; Marinelli, Andreas; van der Sijp, Joost; Koper, Peter; Struikmans, Henk

    2017-12-01

    The purpose of this study was to compare the delivered dose to the expected intraoperative radiation therapy (IORT) dose with in vivo dosimetry. For IORT using electrons in accelerated partial breast irradiation, this is especially relevant since a high dose is delivered in a single fraction. For 47 of breast cancer patients, in vivo dosimetry was performed with MOSFETs and/or GAFCHROMIC EBT2 films. A total dose of 23.33 Gy at d max was given directly after completing the lumpectomy procedure with electron beams generated with an IORT dedicated mobile accelerator. A protection disk was used to shield the thoracic wall. The results of in vivo MOSFET dosimetry for 27 patients and GAFROMIC film dosimetry for 20 patients were analysed. The entry dose for the breast tissue, measured with MOSFETs, (mean value 22.3 Gy, SD 3.4%) agreed within 1.7% with the expected dose (mean value 21.9 Gy). The dose in breast tissue, measured with GAFCHROMIC films (mean value 23.50 Gy) was on average within 0.7% (SD = 3.7%, range -5.5% to 5.6%) of the prescribed dose of 23.33 Gy. The dose measured with MOSFETs and GAFROMIC EBT2 films agreed well with the expected dose. For both methods, the dose to the thoracic wall, lungs and heart for left sided patents was lower than 2.5 Gy even when 12 MeV was applied. The positioning time of GAFCHROMIC films is negligible and based on our results we recommend its use as a standard tool for patient quality assurance during breast cancer IORT. Copyright © 2017 Associazione Italiana di Fisica Medica. Published by Elsevier Ltd. All rights reserved.

  2. Design of Linear CMOS Transconductance Elements for Alpha-Power Law Based MOSFETs

    OpenAIRE

    Bhaskar Gopalan

    2015-01-01

    A model on alpha-power law MOSFETs based source-coupled differential pair (SCDP) is discussed and a simple design procedure for realizing a linear CMOS SCDP transconductance element is proposed. The modified SCDP circuit using this procedure is an alternative to that of conventional SCDP and the circuit discussed has superior linearity than the conventional SCDP for a wide range of input differential voltage. The modified SCDP also includes the circuitry needed to suppress the variation in th...

  3. Simultaneous On-State Voltage and Bond-Wire Resistance Monitoring of Silicon Carbide MOSFETs

    Directory of Open Access Journals (Sweden)

    Nick Baker

    2017-03-01

    Full Text Available In fast switching power semiconductors, the use of a fourth terminal to provide the reference potential for the gate signal—known as a kelvin-source terminal—is becoming common. The introduction of this terminal presents opportunities for condition monitoring systems. This article demonstrates how the voltage between the kelvin-source and power-source can be used to specifically monitor bond-wire degradation. Meanwhile, the drain to kelvin-source voltage can be monitored to track defects in the semiconductor die or gate driver. Through an accelerated aging test on 20 A Silicon Carbide Metal-Oxide-Semiconductor-Field-Effect Transistors (MOSFETs, it is shown that there are opposing trends in the evolution of the on-state resistances of both the bond-wires and the MOSFET die. In summary, after 50,000 temperature cycles, the resistance of the bond-wires increased by up to 2 mΩ, while the on-state resistance of the MOSFET dies decreased by approximately 1 mΩ. The conventional failure precursor (monitoring a single forward voltage cannot distinguish between semiconductor die or bond-wire degradation. Therefore, the ability to monitor both these parameters due to the presence of an auxiliary-source terminal can provide more detailed information regarding the aging process of a device.

  4. Novel Complete Probabilistic Models of Random Variation in High Frequency Performance of Nanoscale MOSFET

    Directory of Open Access Journals (Sweden)

    Rawid Banchuin

    2013-01-01

    Full Text Available The novel probabilistic models of the random variations in nanoscale MOSFET's high frequency performance defined in terms of gate capacitance and transition frequency have been proposed. As the transition frequency variation has also been considered, the proposed models are considered as complete unlike the previous one which take only the gate capacitance variation into account. The proposed models have been found to be both analytic and physical level oriented as they are the precise mathematical expressions in terms of physical parameters. Since the up-to-date model of variation in MOSFET's characteristic induced by physical level fluctuation has been used, part of the proposed models for gate capacitance is more accurate and physical level oriented than its predecessor. The proposed models have been verified based on the 65 nm CMOS technology by using the Monte-Carlo SPICE simulations of benchmark circuits and Kolmogorov-Smirnov tests as highly accurate since they fit the Monte-Carlo-based analysis results with 99% confidence. Hence, these novel models have been found to be versatile for the statistical/variability aware analysis/design of nanoscale MOSFET-based analog/mixed signal circuits and systems.

  5. Single-event burnout hardening of planar power MOSFET with partially widened trench source

    Science.gov (United States)

    Lu, Jiang; Liu, Hainan; Cai, Xiaowu; Luo, Jiajun; Li, Bo; Li, Binhong; Wang, Lixin; Han, Zhengsheng

    2018-03-01

    We present a single-event burnout (SEB) hardened planar power MOSFET with partially widened trench sources by three-dimensional (3D) numerical simulation. The advantage of the proposed structure is that the work of the parasitic bipolar transistor inherited in the power MOSFET is suppressed effectively due to the elimination of the most sensitive region (P-well region below the N+ source). The simulation result shows that the proposed structure can enhance the SEB survivability significantly. The critical value of linear energy transfer (LET), which indicates the maximum deposited energy on the device without SEB behavior, increases from 0.06 to 0.7 pC/μm. The SEB threshold voltage increases to 120 V, which is 80% of the rated breakdown voltage. Meanwhile, the main parameter characteristics of the proposed structure remain similar with those of the conventional planar structure. Therefore, this structure offers a potential optimization path to planar power MOSFET with high SEB survivability for space and atmospheric applications. Project supported by the National Natural Science Foundation of China (Nos. 61404161, 61404068, 61404169).

  6. Real-Time In Vivo Dosimetry With MOSFET Detectors in Serial Tomotherapy for Head and Neck Cancer Patients

    International Nuclear Information System (INIS)

    Qi Zhenyu; Deng Xiaowu; Huang Shaomin; Shiu, Almon; Lerch, Michael; Metcalfe, Peter; Rosenfeld, Anatoly; Kron, Tomas

    2011-01-01

    Purpose: A real-time dose verification method using a recently designed metal oxide semiconductor field effect transistor (MOSFET) dosimetry system was evaluated for quality assurance (QA) of intensity-modulated radiation therapy (IMRT). Methods and Materials: Following the investigation of key parameters that might affect the accuracy of MOSFET measurements (i.e., source surface distance [SSD], field size, beam incident angles and radiation energy spectrum), the feasibility of this detector in IMRT dose verification was demonstrated by comparison with ion chamber measurements taken in an IMRT QA phantom. Real-time in vivo measurements were also performed with the MOSFET system during serial tomotherapy treatments administered to 8 head and neck cancer patients. Results: MOSFET sensitivity did not change with SSD. For field sizes smaller than 20 x 20 cm 2 , MOFET sensitivity varied within 1.0%. The detector angular response was isotropic within 2% over 360 o , and the observed sensitivity variation due to changes in the energy spectrum was negligible in 6-MV photons. MOSFET system measurements and ion chamber measurements agreed at all points in IMRT phantom plan verification, within 5%. The mean difference between 48 IMRT MOSFET-measured doses and calculated values in 8 patients was 3.33% and ranged from -2.20% to 7.89%. More than 90% of the total measurements had deviations of less than 5% from the planned doses. Conclusion: The MOSFET dosimetry system has been proven to be an effective tool in evaluating the actual dose within individual patients during IMRT treatment.

  7. Gate driver with high common mode rejection and self turn-on mitigation for a 10 kV SiC MOSFET enabled MV converter

    DEFF Research Database (Denmark)

    Dalal, Dipen Narendrabhai; Christensen, Nicklas; Jørgensen, Asger Bjørn

    2017-01-01

    Miller clamp circuit for a 10 kV half bridge SiC MOSFET power module. Designed power supply and the gate driver circuit are verified in a double pulse test setup and a continuous switching operation using the 10 kV half bridge silicon carbide MOSFET power module. An in-depth experimental verification...

  8. Short-Circuit Characterization of 10 kV 10A 4H-SiC MOSFET

    DEFF Research Database (Denmark)

    Eni, Emanuel-Petre; Beczkowski, Szymon; Munk-Nielsen, Stig

    2016-01-01

    The short-circuit capability of a power device is highly relevant for converter design and fault protection. In this paper a 10kV 10A 4H-SiC MOSFET is characterized and its short circuit withstand capability is studied and analyzed at 6 kV DC-link voltage. The test setup for this study is also...... introduced as its design, especially the inductance in the switching loop, can affect the experimental results. The study aims to present insights specific to the device which are different from that of silicon (Si) based devices. During the short-circuit operation, MOSFET saturation current, ID......,sat, increases for a few microseconds before decreasing gently. Degradation of the device can be observed at pulses longer than 5.9??s. The SiC MOSFET failed after-turn off, after a pulse of 8.6??s, due to an increase in the leakage current....

  9. Comparative assessment of 3.3kV/400A SiC MOSFET and Si IGBT power modules

    DEFF Research Database (Denmark)

    Ionita, Claudiu; Nawaz, Muhammad; Ilves, Kalle

    2017-01-01

    to withstand short-circuit (SC) events under hard switch fault condition is also investigated. The SiC MOSFET power modules survived short circuit tests performed at a DC-link voltage of 1.5 kV and a pulse duration of 3 μs with a measured short-circuit energy of 6.4 J. The SiC power module failed when......In this paper, a comparative evaluation between a commercial 3.3 kV/400 A Si-IGBT and a 3.3 kV/400 A SiC MOSFET power module in half-bridge configuration is presented. With a constant current of 250 A, a lower forward voltage (VDS) drop of 1.6 V is obtained for SiC MOSFET at 300 K compared to Si...

  10. Strain characterization in SOI and strained-Si on SGOI MOSFET channel using nano-beam electron diffraction (NBD)

    International Nuclear Information System (INIS)

    Usuda, Koji; Numata, Toshinori; Irisawa, Toshifumi; Hirashita, Norio; Takagi, Shinichi

    2005-01-01

    SOI MOSFETs are attractive device structures for high-performance CMOS because they offer the advantages of high-speed and low-power-dissipation operation. For next-generation devices, the combination of strained-Si channels and SOI substrates can be the optimum structure and, thus, we have developed strained-Si MOSFETs on thin relaxed SiGe-on-insulator (SGOI) substrates. However, the strain evaluation within the very thin and small SOI layers after device fabrication processes has not been investigated in detail yet because a strain evaluation method with lateral resolution of several nm, which can be applied directly to samples, has not been available. In this paper, we present a direct and two-dimensional strain evaluation with high spatial resolution using the nano-beam electron diffraction (NBD) method and results of direct strain measurements for conventional SOI and strained-Si on SGOI MOSFET channels

  11. Tight-binding analysis of current oscillation in nanoscale In0.53Ga0.47As Schottky MOSFET

    Science.gov (United States)

    Ahangari, Zahra; Fathipour, Morteza

    2013-11-01

    A comprehensive study of band structure effect on the quantum transport of nanoscale In0.53Ga0.47As Schottky MOSFET for the implementation of III-V MOSFET with low source/drain series resistance is presented. Rigorous treatment of the full band structure in ultra-thin body MOSFET is employed using sp3d5s* tight-binding approach. Strong transverse confinement increases the energy of subbands and, indeed, the effective Schottky barrier height. Due to enhanced Schottky barriers and at low drain voltages, a double barrier gate modulated potential well is created along the channel that results in source-to-drain confinement of states. As tunnelling is the main current component in this device, longitudinal confinement induces drain current oscillation at low temperatures. Important factors that may affect current oscillation are demonstrated. Current oscillation that alters the normal performance of the device is investigated in nanowire Schottky MOSFET, as well. Additional quantum confinement in nanowire Schottky MOSFET provides higher effective Schottky barrier height than the double gate structure. Accordingly, the drain current oscillation is more apparent in nanowire Schottky MOSFET than in the double gate device and is gradually smoothed out as the gate length shrinks down in ultra-scaled structure. Effect of diffusive scattering on the quantum transport of the device is investigated, too. What is prominent in our result is that the drain current oscillations degrade as the channel mobility is decreased. The results in this paper are paving a way to elucidate the feasibility of this device in the nanoscale regime.

  12. Use of a MOSFET for radiation monitoring in space and comparison with the NASA trapped particle model

    Energy Technology Data Exchange (ETDEWEB)

    Kim, Sung-Joon; Min, Kyoung-Wook; Ko, Dai-Ho [Korea Advanced Institute of Science and Technology, Daejeon (Korea, Republic of); Seon, Jong-Ho [Satrec Initiative Company Limited, Daejeon (Korea, Republic of)

    2006-04-15

    We apply the model for radiation effects on MOSFETs with concurrent thermal annealing to the case of space radiation. The results of total dose experiments on board KITSAT-1 are analyzed using the model. We find that the difference in responses of the two RADFETs, specially designed MOSFETs with thick gate oxides, comes from the built-in shielding effects due to the satellite structures. The oscillatory behavior seen in the threshold voltage shifts is identified to be the effect of a temperature variation. The estimated total dose is compared with that of the NASA trapped particle model.

  13. Unified analytical threshold voltage model for non-uniformly doped dual metal gate fully depleted silicon-on-insulator MOSFETs

    Science.gov (United States)

    Rao, Rathnamala; Katti, Guruprasad; Havaldar, Dnyanesh S.; DasGupta, Nandita; DasGupta, Amitava

    2009-03-01

    The paper describes the unified analytical threshold voltage model for non-uniformly doped, dual metal gate (DMG) fully depleted silicon-on-insulator (FDSOI) MOSFETs based on the solution of 2D Poisson's equation. 2D Poisson's equation is solved analytically for appropriate boundary conditions using separation of variables technique. The solution is then extended to obtain the threshold voltage of the FDSOI MOSFET. The model is able to handle any kind of non-uniform doping, viz. vertical, lateral as well as laterally asymetric channel (LAC) profile in the SOI film in addition to the DMG structure. The analytical results are validated with the numerical simulations using the device simulator MEDICI.

  14. Novel charge plasma based dielectric modulated impact ionization MOSFET as a biosensor for label-free detection

    Science.gov (United States)

    Chanda, Manash; Dey, Prithu; De, Swapnadip; Sarkar, Chandan Kumar

    2015-10-01

    In this paper a charge plasma based dielectric modulated impact ionization MOSFET (CP-DIMOSFET) has been proposed for the first time to ease the label free detection of biomolecules. The concept of CP-DIMOSFET is proposed and analyzed on basis of simulated data using SILVACO ATLAS. Low thermal budgeting and thin silicon layer without any dopant implantations make the proposed structure advantageous compared to the existing MOSFET based biosensors. The results show that the proposed device is capable to detect the presence of biomolecules. Simple fabrication schemes, miniaturization, high sensitivity, dominance of dielectric modulation make the proposed biosensor a promising one that could one day revolutionize the healthcare industry.

  15. Modeling and analysis of surface potential of single gate fully depleted SOI MOSFET using 2D-Poisson's equation

    Science.gov (United States)

    Mani, Prashant; Tyagi, Chandra Shekhar; Srivastav, Nishant

    2016-03-01

    In this paper the analytical solution of the 2D Poisson's equation for single gate Fully Depleted SOI (FDSOI) MOSFET's is derived by using a Green's function solution technique. The surface potential is calculated and the threshold voltage of the device is minimized for the low power consumption. Due to minimization of threshold voltage the short channel effect of device is suppressed and after observation we obtain the device is kink free. The structure and characteristics of SingleGate FDSOI MOSFET were matched by using MathCAD and silvaco respectively.

  16. Single-Event Gate Rupture in Power MOSFETs: A New Radiation Hardness Assurance Approach

    Science.gov (United States)

    Lauenstein, Jean-Marie

    2011-01-01

    Almost every space mission uses vertical power metal-semiconductor-oxide field-effect transistors (MOSFETs) in its power-supply circuitry. These devices can fail catastrophically due to single-event gate rupture (SEGR) when exposed to energetic heavy ions. To reduce SEGR failure risk, the off-state operating voltages of the devices are derated based upon radiation tests at heavy-ion accelerator facilities. Testing is very expensive. Even so, data from these tests provide only a limited guide to on-orbit performance. In this work, a device simulation-based method is developed to measure the response to strikes from heavy ions unavailable at accelerator facilities but posing potential risk on orbit. This work is the first to show that the present derating factor, which was established from non-radiation reliability concerns, is appropriate to reduce on-orbit SEGR failure risk when applied to data acquired from ions with appropriate penetration range. A second important outcome of this study is the demonstration of the capability and usefulness of this simulation technique for augmenting SEGR data from accelerator beam facilities. The mechanisms of SEGR are two-fold: the gate oxide is weakened by the passage of the ion through it, and the charge ionized along the ion track in the silicon transiently increases the oxide electric field. Most hardness assurance methodologies consider the latter mechanism only. This work demonstrates through experiment and simulation that the gate oxide response should not be neglected. In addition, the premise that the temporary weakening of the oxide due to the ion interaction with it, as opposed to due to the transient oxide field generated from within the silicon, is validated. Based upon these findings, a new approach to radiation hardness assurance for SEGR in power MOSFETs is defined to reduce SEGR risk in space flight projects. Finally, the potential impact of accumulated dose over the course of a space mission on SEGR

  17. Radiation-induced statistical uncertainty in the threshold voltage measurement of MOSFET dosimeters

    International Nuclear Information System (INIS)

    Benson, Chris; Price, Robert A; Silvie, Jon; Jaksic, Aleksandar; Joyce, Malcolm J

    2004-01-01

    The results of a recent study on the limiting uncertainties in the measurement of photon radiation dose with MOSFET dosimeters are reported. The statistical uncertainty in dose measurement from a single device has been measured before and after irradiation. The resulting increase in 1/f noise with radiation dose has been investigated via various analytical models. The limit of uncertainty in the ubiquitous linear trend of threshold voltage with dose has been measured and compared to two nonlinear models. Inter-device uncertainty has been investigated in a group of 40 devices, and preliminary evidence for kurtosis and skewness in the distributions for devices without external bias has been observed

  18. Layout Capacitive Coupling and Structure Impacts on Integrated High Voltage Power MOSFETs

    DEFF Research Database (Denmark)

    Fan, Lin; Knott, Arnold; Jørgensen, Ivan Harald Holger

    2016-01-01

    -to-layer coupling and the comparison of the layout impacts have not been well established. This paper presents modeling of parasitic mutual coupling to analyze the parasitic capacitance directly coupled between two on-chip metal wires. The accurate 3D field solver analysis for the comparable dimensions shows...... that the layer-to-layer coupling can contribute higher impacts than the well-known side-by-side coupling. Four layout structures are then proposed and implemented in a 0.18 µm partial SOI process for 100 V integrated power MOSFETs with a die area 2.31 mm2. The post-layout comparison using an industrial 2D...

  19. Split-Capacitance and Conductance-Frequency Characteristics of SOI Wafers in Pseudo-MOSFET Configuration

    KAUST Repository

    Pirro, Luca

    2015-09-01

    Recent experimental results have demonstrated the possibility of characterizing silicon-on-insulator (SOI) wafers through split C-V measurements in the pseudo-MOSFET configuration. This paper analyzes the capacitance and conductance versus frequency characteristics. We discuss the conditions under which it is possible to extract interface trap density in bare SOI wafers. The results indicate, through both measurements and simulations, that the signature due to interface trap density is present in small-area samples, but is masked by the RC response of the channel in regular, large-area ones, making the extraction in standard samples problematic. © 1963-2012 IEEE.

  20. Nonlinear Parasitic Capacitance Modelling of High Voltage Power MOSFETs in Partial SOI Process

    DEFF Research Database (Denmark)

    Fan, Lin; Knott, Arnold; Jørgensen, Ivan Harald Holger

    2016-01-01

    : off-state, sub-threshold region, and on-state in the linear region. A high voltage power MOSFET is designed in a partial Silicon on Insulator (SOI) process, with the bulk as a separate terminal. 3D plots and contour plots of the capacitances versus bias voltages for the transistor summarize......State-of-the-art power converter topologies such as resonant converters are either designed with or affected by the parasitic capacitances of the power switches. However, the power switches are conventionally characterized in terms of switching time and/or gate charge with little insight...

  1. Experimental study of single event burnout and single event gate rupture in power MOSFETs and IGBT

    International Nuclear Information System (INIS)

    Tang Benqi; Wang Yanping; Geng Bin

    2001-01-01

    An experimental study was carried out to determine the single event burnout and single event gate rupture sensitivities in power MOSFETs and IGBT which were exposed to heavy ions from 252 Cf source. The test method, test results, a description of observed burnout current waveforms and a discussion of a possible failure mechanism were presented. Current measurements have been performed with a specially designed circuit. The test results include the observed dependence upon applied drain or gate to source bias and versus with external capacitors and limited resistors

  2. Scaling the Serialization of MOSFETs by Magnetically Coupling Their Gate Electrodes

    DEFF Research Database (Denmark)

    Dimopoulos, Emmanouil; Munk-Nielsen, Stig

    2013-01-01

    the establishment of a high-efficient, high-voltage, fast-switching device. Among the prevailing stacking approaches lies the gate balancing core technique, which, in its initial form, demonstrated very good performance in strings of high-power IGBT modules, by magnetically coupling their gate electrodes. Recently...... on a string of three off-the-self, non-matched MOSFETs, installed in an inductively loaded step-down converter. Furthermore, during the string composition and experimental testing, all design milestones related with the scaling-up process of the revised gate balancing core concept are distinctively...

  3. Transformation of Holes Emission Paths under Negative Bias Temperature Stress in Deeply Scaled pMOSFETs

    Directory of Open Access Journals (Sweden)

    Yiming Liao

    2015-01-01

    Full Text Available We examine the impact of negative bias temperature (NBT stress on the fluctuations in ID and IG for deeply scaled pMOSFETs and find that the relative high NBT stress triggers IG-RTN and ID-step. Through the analysis of the field dependence of emission constant and the carrier separation measurement, it is found that under the relative high NBT stress some traps keep charged state for very long time, as observing step-like behaviors in ID, while other traps emit charged holes to the gate side through TAT process, which originate both ID-step and ID-RTN.

  4. Ambipolarity reduction in DMG asymmetric vacuum dielectric Schottky Barrier GAA MOSFET to improve hot carrier reliability

    Science.gov (United States)

    Kumar, Manoj; Haldar, Subhasis; Gupta, Mridula; Gupta, R. S.

    2017-11-01

    An explicit surface potential and subthreshold current model for novel Dual Metal Gate (DMG) Asymmetric Vacuum (AV) as gate dielectric Schottky Barrier (SB) Cylindrical Gate All Around (CGAA) MOSFET with the incorporation of localized charges (Nf) is developed to provide excellent immunity against threshold voltage (Vth) degradation due to hot carriers. Hot carrier induced Localized Charges (LC) either positive or negative leads to degrade the threshold of the device. The major advantage of the proposed DMG-AV-SB-CGAA MOSFET is that it mitigates the ambipolar behavior thus offering very good on current to off current ratio; and also reduces the electron temperature which leads to less hot carrier generation thus lesser degradation in Vth and improved Hot Carrier reliability. The surface potential is determined for three different regions by solving 1-D Poisson's and 2-D Laplace equation through separation of variable method to facilitate an optimal model for calculating the subthreshold drain current from Si-SiO2 interface boundary. The developed model results are in good agreement with that of ATLAS-TCAD simulation.

  5. Spin Transport in Nondegenerate Si with a Spin MOSFET Structure at Room Temperature

    Science.gov (United States)

    Sasaki, Tomoyuki; Ando, Yuichiro; Kameno, Makoto; Tahara, Takayuki; Koike, Hayato; Oikawa, Tohru; Suzuki, Toshio; Shiraishi, Masashi

    2014-09-01

    Spin transport in nondegenerate semiconductors is expected to pave the way to the creation of spin transistors, spin logic devices, and reconfigurable logic circuits, because room-temperature (RT) spin transport in Si has already been achieved. However, RT spin transport has been limited to degenerate Si, which makes it difficult to produce spin-based signals because a gate electric field cannot be used to manipulate such signals. Here, we report the experimental demonstration of spin transport in nondegenerate Si with a spin metal-oxide-semiconductor field-effect transistor (MOSFET) structure. We successfully observe the modulation of the Hanle-type spin-precession signals, which is a characteristic spin dynamics in nondegenerate semiconductors. We obtain long spin transport of more than 20 μm and spin rotation greater than 4π at RT. We also observe gate-induced modulation of spin-transport signals at RT. The modulation of the spin diffusion length as a function of a gate voltage is successfully observed, which we attribute to the Elliott-Yafet spin relaxation mechanism. These achievements are expected to lead to the creation of practical Si-based spin MOSFETs.

  6. Novel high-voltage power lateral MOSFET with adaptive buried electrodes

    International Nuclear Information System (INIS)

    Zhang Wen-Tong; Wu Li-Juan; Qiao Ming; Luo Xiao-Rong; Zhang Bo; Li Zhao-Ji

    2012-01-01

    A new high-voltage and low-specific on-resistance (R on,sp ) adaptive buried electrode (ABE) silicon-on-insulator (SOI) power lateral MOSFET and its analytical model of the electric fields are proposed. The MOSFET features are that the electrodes are in the buried oxide (BOX) layer, the negative drain voltage V d is divided into many partial voltages and the output to the electrodes is in the buried oxide layer and the potentials on the electrodes change linearly from the drain to the source. Because the interface silicon layer potentials are lower than the neighboring electrode potentials, the electronic potential wells are formed above the electrode regions, and the hole potential wells are formed in the spacing of two neighbouring electrode regions. The interface hole concentration is much higher than the electron concentration through designing the buried layer electrode potentials. Based on the interface charge enhanced dielectric layer field theory, the electric field strength in the buried layer is enhanced. The vertical electric field E I and the breakdown voltage (BV) of ABE SOI are 545 V/μm and −587 V in the 50 μm long drift region and the 1 μm thick dielectric layer, and a low R on,sp is obtained. Furthermore, the structure also alleviates the self-heating effect (SHE). The analytical model matches the simulation results. (condensed matter: electronic structure, electrical, magnetic, and optical properties)

  7. Modeling of Quasi-ballistic transport in multi-gate MOSFET for circuit simulations

    International Nuclear Information System (INIS)

    Martinie, Sebastien

    2009-01-01

    Today, the MOSFET transistor reaches deca-nanometer dimensions for which the effects of ballistic transport can no longer be neglected. The challenge is therefore to be able to introduce (quasi-)ballistic transport in the modeling of new devices and evaluates its impact at the circuit level. In this context, our work focuses on the introduction of (quasi-)ballistic transport in compact model of multi-gate transistor for the simulation of circuit elements. Firstly, the McKelvey's method applied to MOSFET has been used to synthesize existing works on analytical modeling of ballistic / quasi-ballistic transport. Then, we built a macroscopic model called 'quasi-ballistic mobility' (starting from pioneering work of Rhew et al), following the comparison between the moment method and the McKelvey method to describe (quasi-)ballistic transport in TCAD environment. Secondly, results from this first model have led us to build our (quasi-)ballistic current by adapting or creating new approaches to take into account various effects of nano-scale devices: short-channel effects, quantum confinement and scattering mechanisms. Finally, our work investigates the impact of the transport properties on the performances of circuit operation. (author)

  8. Accurate analytical modeling of junctionless DG-MOSFET by green's function approach

    Science.gov (United States)

    Nandi, Ashutosh; Pandey, Nilesh

    2017-11-01

    An accurate analytical model of Junctionless double gate MOSFET (JL-DG-MOSFET) in the subthreshold regime of operation is developed in this work using green's function approach. The approach considers 2-D mixed boundary conditions and multi-zone techniques to provide an exact analytical solution to 2-D Poisson's equation. The Fourier coefficients are calculated correctly to derive the potential equations that are further used to model the channel current and subthreshold slope of the device. The threshold voltage roll-off is computed from parallel shifts of Ids-Vgs curves between the long channel and short-channel devices. It is observed that the green's function approach of solving 2-D Poisson's equation in both oxide and silicon region can accurately predict channel potential, subthreshold current (Isub), threshold voltage (Vt) roll-off and subthreshold slope (SS) of both long & short channel devices designed with different doping concentrations and higher as well as lower tsi/tox ratio. All the analytical model results are verified through comparisons with TCAD Sentaurus simulation results. It is observed that the model matches quite well with TCAD device simulations.

  9. Physical investigations of nonvel materials and structures for nano-MOSFETs

    Energy Technology Data Exchange (ETDEWEB)

    Feste, Sebastian Frederik

    2009-08-21

    In this thesis four important physical and material aspects faced by MOSFET devices as dimensions move to the length scale of 10nm have been investigated: i) metal source/drain contacts with dopant segregation for reduced contact resistance and improved carrier injection; ii) variability of the Schottky-barrier height (SBH) in MOSFET contacts; iii) strained silicon as a high mobility channel material; iv) silicon nanowire (NW) MOSFETs in order to suppress short channel effects by a multi-gate architecture. Ultimately scaled devices require highly conductive contacts with abrupt junctions. However, due to Fermi-level pinning at the metal-semiconductor interface, the performance of SB-MOSFETs still falls behind that of conventional FETs. Nickel-silicidation induced dopant segregation is highly effective in improving carrier injection through SBs, resulting in higher Ion/Ioff -ratios and better sub-threshold swings. Arsenic dopant segregation has been studied in detail as a function of NiSi thickness, implantation energy and dose, as well as process conditions for the formation of NiSi. It is shown that dopant concentrations as high as the solid solubility and lateral dopant slopes of 1-2nm/dec at the NiSi/Si-contact interface can be obtained. Simulations of scaled ultra-thin-body SOI MOSFETs with dopant segregation demonstrated that these devices can be scaled down to channel lengths of L=10nm. Variability in the electrical characteristics of SB-MOSFETs without and with dopant segregation has been investigated by a new experimental method, that allows to measure the impact of various sources leading to variability. The inherent variability of the SBH has been identified as the main source of variability and an increase in SBH variability due to dopant segregation by 0.01eV was found. The importance of SBH variability for the on-current, even for very low SBHs of 0.03eV, was demonstrated with simulations. High mobility channel materials are required, as the steady

  10. 60Co-Gamma Ray Induced Total Dose Effects on P-Channel MOSFETs

    Directory of Open Access Journals (Sweden)

    Shashank Nagaraj

    2013-01-01

    Full Text Available Total Dose Effect (TDE on solid state devices is of serious concern as it changes the electrical properties leading to degradation of the devices and failure of the systems associated with them. Ionization caused due to TDE in commercial P-channel Metal Oxide Semiconductor Field Effect Transistors (MOSFETs has been studied, where the failure mechanism is found to be mainly a result of the changes in the oxide properties and the surface effects at the channel beneath the gate oxide. The threshold voltage of the MOSFETs was found to shift from −0.69 V to −2.41 V for a total gamma dose of 1 Mrad. The net negative threshold shifts in the irradiated devices reveal the major contribution of oxide trapped charges to device degradation. The radiation induced oxide and interface charge densities were estimated through subthreshold measurements, and the trap densities were found to increase by one order in magnitude after a total gamma dose of 1 Mrad. Other parameters like transconductance, subthreshold swing, and drain saturation current are also investigated as a function of gamma dose.

  11. Dual metal gate tunneling field effect transistors based on MOSFETs: A 2-D analytical approach

    Science.gov (United States)

    Ramezani, Zeinab; Orouji, Ali A.

    2018-01-01

    A novel 2-D analytical drain current model of novel Dual Metal Gate Tunnel Field Effect Transistors Based on MOSFETs (DMG-TFET) is presented in this paper. The proposed Tunneling FET is extracted from a MOSFET structure by employing an additional electrode in the source region with an appropriate work function to induce holes in the N+ source region and hence makes it as a P+ source region. The electric field is derived which is utilized to extract the expression of the drain current by analytically integrating the band to band tunneling generation rate in the tunneling region based on the potential profile by solving the Poisson's equation. Through this model, the effects of the thin film thickness and gate voltage on the potential, the electric field, and the effects of the thin film thickness on the tunneling current can be studied. To validate our present model we use SILVACO ATLAS device simulator and the analytical results have been compared with it and found a good agreement.

  12. Entrance skin dose measured with MOSFETs in children undergoing interventional radiology procedures

    International Nuclear Information System (INIS)

    Glennie, Diana; Connolly, Bairbre L.; Gordon, Christopher

    2008-01-01

    Interventional procedures frequently employ fluoroscopy or digital subtraction angiography (DSA). Few studies have documented radiation doses received by children during these procedures. To measure skin entrance dose received during common pediatric interventional procedures. MOSFET dosimeters were placed to record skin doses in 143 children undergoing any of five procedures: 30 PICC insertions, 34 CVL/port insertions, 30 G/GJ tube insertions, 25 sclerotherapy/vascular anomaly procedures, 24 cerebral angiography procedures. The highest recorded dose (HRD) from the five MOSFET probes was assumed to be the peak skin dose per child. HRD values were averaged for children within each group and correlated with patient weight, fluoroscopy time and number of DSA frames. Average HRD was 1.8 mGy for PICC insertions, 1.4 mGy for CVL/port insertions, 3.9 mGy for G/GJ tube insertions, 39.1 mGy for sclerotherapy/vascular anomaly procedures, and 149.9 and 101.6 mGy for frontal and lateral portions of cerebral angiography procedures. These entrance doses corresponded to effective dose estimates in the range 0.4-3 mSv. There were only modest correlations between peak skin dose and fluoroscopy time, patient weight and DSA frames (r 2 <0.4, P<0.01). Pediatric interventional procedures are associated with a wide range of doses; those at the higher end require careful monitoring. (orig.)

  13. Entrance skin dose measured with MOSFETs in children undergoing interventional radiology procedures

    Energy Technology Data Exchange (ETDEWEB)

    Glennie, Diana [McMaster University, Medical and Health Physics Department, Hamilton (Canada); Connolly, Bairbre L. [The Hospital for Sick Children, Image-Guided Therapy, Department of Diagnostic Imaging, Toronto (Canada); Gordon, Christopher [The Hospital for Sick Children, Department of Diagnostic Imaging, Toronto (Canada)

    2008-11-15

    Interventional procedures frequently employ fluoroscopy or digital subtraction angiography (DSA). Few studies have documented radiation doses received by children during these procedures. To measure skin entrance dose received during common pediatric interventional procedures. MOSFET dosimeters were placed to record skin doses in 143 children undergoing any of five procedures: 30 PICC insertions, 34 CVL/port insertions, 30 G/GJ tube insertions, 25 sclerotherapy/vascular anomaly procedures, 24 cerebral angiography procedures. The highest recorded dose (HRD) from the five MOSFET probes was assumed to be the peak skin dose per child. HRD values were averaged for children within each group and correlated with patient weight, fluoroscopy time and number of DSA frames. Average HRD was 1.8 mGy for PICC insertions, 1.4 mGy for CVL/port insertions, 3.9 mGy for G/GJ tube insertions, 39.1 mGy for sclerotherapy/vascular anomaly procedures, and 149.9 and 101.6 mGy for frontal and lateral portions of cerebral angiography procedures. These entrance doses corresponded to effective dose estimates in the range 0.4-3 mSv. There were only modest correlations between peak skin dose and fluoroscopy time, patient weight and DSA frames (r{sup 2}<0.4, P<0.01). Pediatric interventional procedures are associated with a wide range of doses; those at the higher end require careful monitoring. (orig.)

  14. Monte Carlo simulation using the PENELOPE code with an ant colony algorithm to study MOSFET detectors

    Energy Technology Data Exchange (ETDEWEB)

    Carvajal, M A; Palma, A J [Departamento de Electronica y Tecnologia de Computadores, Universidad de Granada, E-18071 Granada (Spain); Garcia-Pareja, S [Servicio de Radiofisica Hospitalaria, Hospital Regional Universitario ' Carlos Haya' , Avda Carlos Haya, s/n, E-29010 Malaga (Spain); Guirado, D [Servicio de RadiofIsica, Hospital Universitario ' San Cecilio' , Avda Dr Oloriz, 16, E-18012 Granada (Spain); Vilches, M [Servicio de Fisica y Proteccion Radiologica, Hospital Regional Universitario ' Virgen de las Nieves' , Avda Fuerzas Armadas, 2, E-18014 Granada (Spain); Anguiano, M; Lallena, A M [Departamento de Fisica Atomica, Molecular y Nuclear, Universidad de Granada, E-18071 Granada (Spain)], E-mail: carvajal@ugr.es, E-mail: garciapareja@gmail.com, E-mail: dguirado@ugr.es, E-mail: mvilches@ugr.es, E-mail: mangui@ugr.es, E-mail: ajpalma@ugr.es, E-mail: lallena@ugr.es

    2009-10-21

    In this work we have developed a simulation tool, based on the PENELOPE code, to study the response of MOSFET devices to irradiation with high-energy photons. The energy deposited in the extremely thin silicon dioxide layer has been calculated. To reduce the statistical uncertainties, an ant colony algorithm has been implemented to drive the application of splitting and Russian roulette as variance reduction techniques. In this way, the uncertainty has been reduced by a factor of {approx}5, while the efficiency is increased by a factor of above 20. As an application, we have studied the dependence of the response of the pMOS transistor 3N163, used as a dosimeter, with the incidence angle of the radiation for three common photons sources used in radiotherapy: a {sup 60}Co Theratron-780 and the 6 and 18 MV beams produced by a Mevatron KDS LINAC. Experimental and simulated results have been obtained for gantry angles of 0 deg., 15 deg., 30 deg., 45 deg., 60 deg. and 75 deg. The agreement obtained has permitted validation of the simulation tool. We have studied how to reduce the angular dependence of the MOSFET response by using an additional encapsulation made of brass in the case of the two LINAC qualities considered.

  15. In-vivo dosimetry for field sizes down to 6 × 6 mm2 in shaped beam radiosurgery with microMOSFET.

    Science.gov (United States)

    Sors, A; Cassol, E; Latorzeff, I; Duthil, P; Sabatier, J; Lotterie, J A; Redon, A; Berry, I; Franceries, X

    2014-09-01

    The aim of this study is to evaluate microMOSFET as in-vivo dosimeter in 6 MV shaped-beam radiosurgery for field sizes down to 6 × 6 mm2. A homemade build-up cap was developed and its use with microMOSFET was evaluated down to 6 × 6 mm2. The study with the homemade build-up cap was performed considering its influence on field size over-cover occurring at surface, achievement of the overall process of electronic equilibrium, dose deposition along beam axis and dose attenuation. An optimized calibration method has been validated using MOSFET in shaped-beam radiosurgery for field sizes from 98 × 98 down to 18 × 18 mm2. The method was detailed in a previous study and validated in irregular field shapes series measurements performed on a head phantom. The optimized calibration method was applied to microMOSFET equipped with homemade build-up cap down to 6 × 6 mm2. Using the same irregular field shapes, dose measurements were performed on head phantom. MicroMOSFET results were compared to previous MOSFET ones. Additional irregular field shapes down to 8.8 × 8.8 mm2 were studied with microMOSFET. Isocenter dose attenuation due to the homemade build-up cap over the microMOSFET was near 2% irrespective of field size. Our results suggested that microMOSFET equipped with homemade build-up cap is suitable for in-vivo dosimetry in shaped-beam radiosurgery for field sizes down to 6 × 6 mm2 and therefore that the required build-up cap dimensions to perform entrance in-vivo dosimetry in small-fields have to ensure only partial charge particle equilibrium. Copyright © 2014 Associazione Italiana di Fisica Medica. Published by Elsevier Ltd. All rights reserved.

  16. Modulation of sub-threshold properties of InGaAs MOSFETs by La2O3 gate dielectrics

    Directory of Open Access Journals (Sweden)

    C.-Y. Chang

    2017-09-01

    Full Text Available We have found the ferroelectric-like characteristics in atomic layer deposition (ALD La2O3 films with thermal budget lower than 300oC in polarization-electric field (P-E and capacitance-gate voltage (C-V measurements on W/La2O3/W and W/La2O3/InGaAs capacitors. The observed hysteresis and saturation of polarization in the P-E characteristics of the W/La2O3/W and the W/La2O3/InGaAs capacitors, and the counter-clockwise C-V hysteresis in the C-V curves of the W/La2O3/InGaAs capacitors suggest a possibility of ferroelectricity in the present La2O3 films. By using this gate stack, W/La2O3/InGaAs metal-oxide-semiconductor field-effect transistors (MOSFETs were fabricated in order to examine the negative capacitance (NC effect due to La2O3. It is found that the sub-threshold swing (SS of W/La2O3/InGaAs MOSFETs is lower at low temperature than the theoretical limit of MOSFETs. This result strongly suggests that the W/La2O3/InGaAs MOSFETs can work as a steep-slope III-V negative capacitance field-effect transistor (NCFET.

  17. Circuit mismatch and current coupling effect influence on paralleling SiC MOSFETs in multichip power modules

    DEFF Research Database (Denmark)

    Li, Helong; Beczkowski, Szymon; Munk-Nielsen, Stig

    2015-01-01

    This paper reveals that there are circuit mismatches and a current coupling effect in the direct bonded copper (DBC) layout of a silicon carbide (SiC) MOSFET multichip power module. According to the modelling and the mathematic analysis of the DBC layout, the mismatch of the common source stray...

  18. MMC with parallel-connected MOSFETs as an alternative to wide bandgap converters for LVDC distribution networks

    Directory of Open Access Journals (Sweden)

    Yanni Zhong

    2017-03-01

    Full Text Available Low-voltage direct-current (LVDC networks offer improved conductor utilisation on existing infrastructure and reduced conversion stages, which can lead to a simpler and more efficient distribution network. However, LVDC networks must continue to support AC loads, requiring efficient, low-distortion DC–AC converters. Additionally, increasing numbers of DC loads on the LVAC network require controlled, low-distortion, unity power factor AC-DC converters with large capacity, and bi-directional capability. An AC–DC/DC–AC converter design is therefore proposed in this study to minimise conversion loss and maximise power quality. Comparative analysis is performed for a conventional IGBT two-level converter, a SiC MOSFET two-level converter, a Si MOSFET modular multi-level converter (MMC and a GaN HEMT MMC, in terms of power loss, reliability, fault tolerance, converter cost and heatsink size. The analysis indicates that the five-level MMC with parallel-connected Si MOSFETs is an efficient, cost-effective converter for low-voltage converter applications. MMC converters suffer negligible switching loss, which enables reduced device switching without loss penalty from increased harmonics and filtering. Optimal extent of parallel-connection for MOSFETs in an MMC is investigated. Experimental results are presented to show the reduction in device stress and electromagnetic interference generating transients through the use of reduced switching and device parallel-connection.

  19. MOSFET-BJT hybrid mode of the gated lateral bipolar junction transistor for C-reactive protein detection.

    Science.gov (United States)

    Yuan, Heng; Kwon, Hyurk-Choon; Yeom, Se-Hyuk; Kwon, Dae-Hyuk; Kang, Shin-Won

    2011-10-15

    In this study, we propose a novel biosensor based on a gated lateral bipolar junction transistor (BJT) for biomaterial detection. The gated lateral BJT can function as both a BJT and a metal-oxide-semiconductor field-effect transistor (MOSFET) with both the emitter and source, and the collector and drain, coupled. C-reactive protein (CRP), which is an important disease marker in clinical examinations, can be detected using the proposed device. In the MOSFET-BJT hybrid mode, the sensitivity, selectivity, and reproducibility of the gated lateral BJT for biosensors were evaluated in this study. According to the results, in the MOSFET-BJT hybrid mode, the gated lateral BJT shows good selectivity and reproducibility. Changes in the emitter (source) current of the device for CRP antigen detection were approximately 0.65, 0.72, and 0.80 μA/decade at base currents of -50, -30, and -10 μA, respectively. The proposed device has significant application in the detection of certain biomaterials that require a dilution process using a common biosensor, such as a MOSFET-based biosensor. Copyright © 2011 Elsevier B.V. All rights reserved.

  20. Efficient 3D 'Atomistic' Simulation Technique for Studying of Random Dopant Induced Threshold Voltage Lowering and Fluctuations in Decanano MOSFETs

    Science.gov (United States)

    Asenov, Asen

    1998-01-01

    A 3D 'atomistic' simulation technique to study random dopant induced threshold voltage lowering and fluctuations in sub 0.1 micron MOSFETs is presented. It allows statistical analysis of random impurity effects down to the individual impurity level. Efficient algorithms based on a single solution of Poisson's equation, followed by the solution of a simplified current continuity equation are used in the simulations.

  1. A neural approach to study the scaling capability of the undoped Double-Gate and cylindrical Gate All Around MOSFETs

    Energy Technology Data Exchange (ETDEWEB)

    Djeffal, F. [LEA, Department of Electronics, University of Batna (Algeria)], E-mail: faycaldzdz@hotmail.com; Abdi, M.A.; Dibi, Z. [LEA, Department of Electronics, University of Batna (Algeria); Chahdi, M. [LEPCM, Department of Physics, University of Batna (Algeria); Benhaya, A. [LEA, Department of Electronics, University of Batna (Algeria)

    2008-02-15

    The Double-Gate and Gate All Around MOSFETs are two of the most promising candidates for the scaling of CMOS technology down to nanometer range. The excellent electrostatic control of the channel by the gate reduces dramatically short channel effects, such as charge sharing and DIBL. So, the objective of this work is to investigate and compare the scaling capability of the undoped DG and GAA MOSFETs using the artificial neural networks (ANNs). The optimization of this latter is based on the development of numerical models of subthreshold swing (S) for short channel Double-Gate and Gate All Around MOSFETs under various modes of operation based on a two-dimensional analysis of electrostatics in the channel region by solving the two-dimensional Poisson equation with the mobile charge term included, and apply the physical insights gained from these models to investigate the impact of process variations on device characteristics. This study leads to the conclusion that cylindrical geometry is superior to the equivalent Double-Gate structure both in terms of the electrostatic control of the channel and the current ratio I{sub on}/I{sub off}, indicating that the subthreshold slope is better controlled by the GAA MOSFET.

  2. Development of PSpice modeling platform for 10 kV/100 A SiC MOSFET power module

    DEFF Research Database (Denmark)

    Martins, Joäo Pedro Rodrigues; Nawaz, Muhammad; Ilves, Kalle

    2017-01-01

    was implemented based on the already established McNutt Hefner model originally developed for discrete single-die based SiC-MOSFETs. The proposed model has been verified both with static and dynamic experimental data and at different temperatures. Moreover, the energy loss assessment has been performed...

  3. Short-circuit ruggedness assessment of a 1.2 kV/180 A SiC MOSFET power module

    DEFF Research Database (Denmark)

    Ionita, Claudiu; Nawaz, Muhammad; Ilves, Kalle

    2017-01-01

    While investigations on short-circuit ruggedness of discrete SiC MOSFET are widely encountered in the scientific literature, there is not so much research dealing with the operational robustness of high power SiC MOSFET modules. In this paper, the short-circuit (SC) ruggedness under hard switching...... fault (HSF) of a commercial 1.2 kV/180 A SiC MOSFET power module in half-bridge configuration will be presented. The test conditions, such as DC-link voltage (VDC), gate resistance (Rg) and gate-source supply voltage (VGS) are varied systematically to investigate the effect of these parameters...

  4. Single-Event Latchup Testing of the Micrel MIC4424 Dual Power MOSFET Driver

    Science.gov (United States)

    Pellish, J. A.; Boutte, A.; Kim, H.; Phan, A.; Topper, A.

    2016-01-01

    We conducted 47 exposures of four different MIC4424 devices and did not observe any SEL or high-current events. This included worst-case conditions with a LET of 81 MeV-sq cm/mg, applied voltage of 18.5 V, a case temperature greater than 120 C, and a final fluence of 1x10(exp 7)/sq cm. We also monitored both the outputs for the presence of SETs. While the period of the 1 MHz square wave was slightly altered in some cases, no pulses were added or deleted. 1. Purpose: The purpose of this testing is to characterize the BiCMOS/DMOS Micrel MIC4424 dual, non-inverting MOSFET driver for single-event latchup (SEL) susceptibility. These data will be used for flight lot evaluation purposes. 2. Devices Tested: The MIC4423/4424/4425 family are highly reliable BiCMOS/DMOS buffer/driver MOSFET drivers. They are higher output current versions of the MIC4426/4427/4428. They can survive up to 5V of noise spiking, of either polarity, on the ground pin. They can accept, without either damage or logic upset, up to half an amp of reverse current (either polarity) forced back into their outputs. Primarily intended for driving power MOSFETs, the MIC4423/4424/4425 drivers are suitable for driving other loads (capacitive, resistive, or inductive) which require low-impedance, high peak currents, and fast switching times. Heavily loaded clock lines, coaxial cables, or piezoelectric transducers are some examples. The only known limitation on loading is that total power dissipated in the driver must be kept within the maximum power dissipation limits of the package. Five (5) parts were provided for SEL testing. We prepared four parts for irradiation and reserved one piece as an un-irradiated control. More information about the devices can be found in Table 1. The parts were prepared for testing by removing the lid from the CDIP package to expose the target die. The parts were then soldered to small copper circuit adapter boards for easy handling. These parts are fabricated in a bulk Bi

  5. Nonlinear Parasitic Capacitance Modelling of High Voltage Power MOSFETs in Partial SOI Process

    DEFF Research Database (Denmark)

    Fan, Lin; Knott, Arnold; Jørgensen, Ivan Harald Holger

    2016-01-01

    State-of-the-art power converter topologies such as resonant converters are either designed with or affected by the parasitic capacitances of the power switches. However, the power switches are conventionally characterized in terms of switching time and/or gate charge with little insight into the......State-of-the-art power converter topologies such as resonant converters are either designed with or affected by the parasitic capacitances of the power switches. However, the power switches are conventionally characterized in terms of switching time and/or gate charge with little insight......: off-state, sub-threshold region, and on-state in the linear region. A high voltage power MOSFET is designed in a partial Silicon on Insulator (SOI) process, with the bulk as a separate terminal. 3D plots and contour plots of the capacitances versus bias voltages for the transistor summarize...

  6. Different stress techniques and their efficiency on triple-gate SOI n-MOSFETs

    Science.gov (United States)

    Bühler, R. T.; Agopian, P. G. D.; Collaert, N.; Simoen, E.; Claeys, C.; Martino, J. A.

    2015-01-01

    Three techniques to implement mechanical stress in n-channel Multiple Gate MOSFETs (MuGFETs) are investigated through 3D simulations and transconductance measurements. They are: uniaxial stress, biaxial stress and biaxial + uniaxial stress. Four different fin dimensions are evaluated: a narrow and a wide transistor, combined with a short or a long device. It is shown that the stress distribution and the device performance exhibit a dependence on the fin dimensions. For uniaxially strained devices, the dimensions are important as the bending of the silicon required to induce stress in the channel depends on its size. However, for biaxially strained devices the plane of etching in the silicon fin is important, determining the degradation of the stress components. The combination of the two types of stress results in an improvement of some stress components and an overall improvement in the maximum transconductance.

  7. Improved vertical MOSFET performance using an epitaxial channel and a stacked silicon-insulator structure

    International Nuclear Information System (INIS)

    Uchino, T; Gili, E; Ashburn, P; Tan, L; Buiu, O; Hall, S

    2012-01-01

    A vertical MOSFET (VMOST) incorporating an epitaxial channel and a drain junction in a stacked silicon-insulator structure is presented. In this device structure, an oxide layer near the drain junction edge (referred to as a junction stop) acts as a dopant diffusion barrier and consequently a shallow drain junction is formed to suppress short channel effects. To investigate the scalability of this device, a simulation study in the sub-100 nm regime calibrated to measured results on the fabricated devices is carried out. The use of an epitaxial channel delivers 50% higher drive current due to the higher mobility of the retrograde channel and the junction stop structure delivers improvements of threshold voltage roll-off and drain-induced barrier lowering compared with a conventional VMOST. (fast track communication)

  8. Operation and scalability of dopant-segregated Schottky barrier MOSFETs with recessed channels

    International Nuclear Information System (INIS)

    Shih, Chun-Hsing; Hsia, Jui-Kai

    2013-01-01

    Recessed channels were used in scaled dopant-segregated Schottky barrier MOSFETs (DS-SBMOS) to control the severe short-channel effect. The physical operation and device scalability of the DS-SBMOS resulting from the presence of recessed channels and associated gate-corners are elucidated. The coupling of Schottky and gate-corner barriers has a key function in determining the on–off switching and drain current. The gate-corner barriers divide the channel into three regions for protection from the drain penetration field. To prevent resistive degradations in the drive current, an alternative asymmetric recessed channel (ARC) without a source-side gate-corner is proposed to simultaneously optimize both the short-channel effect and drive current in the scaled DS-SBMOS. By employing the proposed ARC architecture, the DS-SBMOS devices can be successfully scaled down, making them promising candidates for next-generation CMOS devices. (paper)

  9. Silicon-Carbide Power MOSFET Performance in High Efficiency Boost Power Processing Unit for Extreme Environments

    Science.gov (United States)

    Ikpe, Stanley A.; Lauenstein, Jean-Marie; Carr, Gregory A.; Hunter, Don; Ludwig, Lawrence L.; Wood, William; Del Castillo, Linda Y.; Fitzpatrick, Fred; Chen, Yuan

    2016-01-01

    Silicon-Carbide device technology has generated much interest in recent years. With superior thermal performance, power ratings and potential switching frequencies over its Silicon counterpart, Silicon-Carbide offers a greater possibility for high powered switching applications in extreme environment. In particular, Silicon-Carbide Metal-Oxide- Semiconductor Field-Effect Transistors' (MOSFETs) maturing process technology has produced a plethora of commercially available power dense, low on-state resistance devices capable of switching at high frequencies. A novel hard-switched power processing unit (PPU) is implemented utilizing Silicon-Carbide power devices. Accelerated life data is captured and assessed in conjunction with a damage accumulation model of gate oxide and drain-source junction lifetime to evaluate potential system performance at high temperature environments.

  10. A high-performance channel engineered charge-plasma-based MOSFET with high-κ spacer

    Science.gov (United States)

    Shan, Chan; Wang, Ying; Luo, Xin; Bao, Meng-tian; Yu, Cheng-hao; Cao, Fei

    2017-12-01

    In this paper, the performance of graded channel double-gate MOSFET (GC-DGFET) that utilizes the charge-plasma concept and a high-κ spacer is investigated through 2-D device simulations. The results demonstrate that GC-DGFET with high-κ spacer can effectively improve the ON-state driving current (ION) and reduce the OFF-leakage current (IOFF). We find that reduction of the initial energy barrier between the source and channel is the origin of this ION enhancement. The reason for the IOFF reduction is identified to be the extension of the effective channel length owing to the fringing field via high-κ spacers. Consequently, these devices offer enhanced performance by reducing the total gate-to-gate capacitance (Cgg) and decreasing the intrinsic delay (τ).

  11. Effective-mass approach for n-type semiconductor nanowire MOSFETs arbitrarily oriented

    International Nuclear Information System (INIS)

    Bescond, Marc; Cavassilas, Nicolas; Lannoo, Michel

    2007-01-01

    A method which calculates the effective masses in arbitrarily oriented semiconductor nanowires is presented. In order to avoid the full three-dimensional (3D) resolution of the Schroedinger equation, the method decouples within a Cartesian system the transport direction from the cross section. Results give the new effective mass expressions for each valley and channel orientation. As a direct application, transport in [100]-oriented Ge nanowire metal-oxide-semiconductor field-effect transistors (MOSFETs) is then studied by using a self-consistent 'mode-space' approach expressed in the nonequilibrium Green's function formalism. Along this wire orientation, we show that the effective masses resulting from our approach are very close to the one obtained using a sp 3 tight-binding band-structure calculation for nanowires as thin as 4 nm

  12. Effective-mass approach for n-type semiconductor nanowire MOSFETs arbitrarily oriented

    Energy Technology Data Exchange (ETDEWEB)

    Bescond, Marc [Institut de Microelectronique, Electromagnetisme et Photonique (IMEP, UMR CNRS 5130)-MINATEC, 3 Parvis Louis Neel, BP 257, F-38016 Grenoble Cedex 1 (France); Cavassilas, Nicolas [Laboratoire Materiaux et Microelectronique de Provence (L2MP, UMR CNRS 6137), Batiment IRPHE, 49 rue Joliot-Curie, BP 146, F-13384 Marseille Cedex 13 (France); Lannoo, Michel [Laboratoire Materiaux et Microelectronique de Provence (L2MP, UMR CNRS 6137), Batiment IRPHE, 49 rue Joliot-Curie, BP 146, F-13384 Marseille Cedex 13 (France)

    2007-06-27

    A method which calculates the effective masses in arbitrarily oriented semiconductor nanowires is presented. In order to avoid the full three-dimensional (3D) resolution of the Schroedinger equation, the method decouples within a Cartesian system the transport direction from the cross section. Results give the new effective mass expressions for each valley and channel orientation. As a direct application, transport in [100]-oriented Ge nanowire metal-oxide-semiconductor field-effect transistors (MOSFETs) is then studied by using a self-consistent 'mode-space' approach expressed in the nonequilibrium Green's function formalism. Along this wire orientation, we show that the effective masses resulting from our approach are very close to the one obtained using a sp{sup 3} tight-binding band-structure calculation for nanowires as thin as 4 nm.

  13. The Development of III-V Semiconductor MOSFETs for Future CMOS Applications

    Science.gov (United States)

    Greene, Andrew M.

    Alternative channel materials with superior transport properties over conventional strained silicon are required for supply voltage scaling in low power complementary metal-oxide-semiconductor (CMOS) integrated circuits. Group III-V compound semiconductor systems offer a potential solution due to their high carrier mobility, low carrier effective mass and large injection velocity. The enhancement in transistor drive current at a lower overdrive voltage allows for the scaling of supply voltage while maintaining high switching performance. This thesis focuses on overcoming several material and processing challenges associated with III-V semiconductor development including a low thermal processing budget, high interface trap state density (Dit), low resistance source/drain contacts and growth on lattice mismatched substrates. Non-planar In0.53Ga0.47As FinFETs were developed using both "gate-first" and "gate-last" fabrication methods for n-channel MOSFETs. Electron beam lithography and anisotropic plasma etching processes were optimized to create highly scaled fins with near vertical sidewalls. Plasma damage was removed using a wet etch process and improvements in gate efficiency were characterized on MOS capacitor structures. A two-step, selective removal of the pre-grown n+ contact layer was developed for "gate-last" recess etching. The final In0.53Ga 0.47As FinFET devices demonstrated an ION = 70 mA/mm, I ON/IOFF ratio = 15,700 and sub-threshold swing = 210 mV/dec. Bulk GaSb and strained In0.36Ga0.64Sb quantum well (QW) heterostructures were developed for p-channel MOSFETs. Dit was reduced to 2 - 3 x 1012 cm-2eV-1 using an InAs surface layer, (NH4)2S passivation and atomic layer deposition (ALD) of Al2O3. A self-aligned "gate-first" In0.36Ga0.64Sb MOSFET fabrication process was invented using a "T-shaped" electron beam resist patterning stack and intermetallic source/drain contacts. Ni contacts annealed at 300°C demonstrated an ION = 166 mA/mm, ION/IOFF ratio = 1

  14. A High Performance CMOS Current Mirror Circuit with Neuron MOSFETs and a Transimpedance Amplifier

    Science.gov (United States)

    Shimizu, Akio; Ishikawa, Yohei; Fukai, Sumio; Aikawa, Masayoshi

    In this paper, we propose a high accuracy current mirror circuit suitable for a low-voltage operation. The proposed circuit has a novel negative feedback that is composed of neuron MOSFETs and a transimpedance amplifier. As a result, the proposed circuit achieves a high accuracy current mirror circuit. At the same time, the proposed circuit monitors an error current by a low voltage because the negative feedback operates in a current-mode. The performance of the proposed circuit is evaluated using HSPICE simulation with On-Semiconductor 1.48μm CMOS device parameters. Simulation results show that the output resistance of the proposed circuit is 5.79[GΩ] and minimum operating range is 0.3[V].

  15. Reliability of high mobility SiGe channel MOSFETs for future CMOS applications

    CERN Document Server

    Franco, Jacopo; Groeseneken, Guido

    2014-01-01

    Due to the ever increasing electric fields in scaled CMOS devices, reliability is becoming a showstopper for further scaled technology nodes. Although several groups have already demonstrated functional Si channel devices with aggressively scaled Equivalent Oxide Thickness (EOT) down to 5Å, a 10 year reliable device operation cannot be guaranteed anymore due to severe Negative Bias Temperature Instability. This book focuses on the reliability of the novel (Si)Ge channel quantum well pMOSFET technology. This technology is being considered for possible implementation in next CMOS technology nodes, thanks to its benefit in terms of carrier mobility and device threshold voltage tuning. We observe that it also opens a degree of freedom for device reliability optimization. By properly tuning the device gate stack, sufficiently reliable ultra-thin EOT devices with a 10 years lifetime at operating conditions are demonstrated. The extensive experimental datasets collected on a variety of processed 300mm wafers and pr...

  16. Extraction method of interfacial injected charges for SiC power MOSFETs

    Science.gov (United States)

    Wei, Jiaxing; Liu, Siyang; Li, Sheng; Song, Haiyang; Chen, Xin; Li, Ting; Fang, Jiong; Sun, Weifeng

    2018-01-01

    An improved novel extraction method which can characterize the injected charges along the gate oxide interface for silicon carbide (SiC) power metal-oxide-semiconductor field-effect transistors (MOSFETs) is proposed. According to the different interface situations of the channel region and the junction FET (JFET) region, the gate capacitance versus gate voltage (Cg-Vg) curve of the device can be divided into three relatively independent parts, through which the locations and the types of the charges injected in to the oxide above the interface can be distinguished. Moreover, the densities of these charges can also be calculated by the amplitudes of the shifts in the Cg-Vg curve. The correctness of this method is proved by TCAD simulations. Moreover, experiments on devices stressed by unclamped-inductive-switching (UIS) stress and negative bias temperature stress (NBTS) are performed to verify the validity of this method.

  17. MOSFET dosimetry of the radiation therapy microbeams at the European synchrotron radiation facility

    International Nuclear Information System (INIS)

    Rozenfeld, A.; Lerch, M.

    2002-01-01

    Full text: We have developed an innovative on-line MOSFET readout system for use in the quality assurance of radiation treatment beams. Recently the system has found application in areas where excellent spatial resolution is also a requirement in the quality assurance process, for example IMRT, and microbeam radiation therapy. The excellent spatial resolution is achieved by using a quadruple RADFET TM chip in 'edge on' mode. In developing this approach we have found that the system can be utilised to determine any error in the beam profile measurements due to misalignment of RADFET with respect to the radiation beam or microbeam. Using this approach will ensure that the excellent spatial resolution of the RADFET used in 'edge-on' mode is fully utilised. In this work we report on dosimetry measurements performed at the microbeam radiation therapy beamline located at the European Synchrotron Radiation Facility. The synchrotron planar array microbeam with size 10-30 μm and pitch ∼200 μm has found an important application in microbeam radiation therapy (MRT) of brain tumours in infants for whom other kinds of radiotherapy are inadequate and/or unsafe. The radiation damage from an array of parallel microbeams correlates strongly with the range of peak-valley dose ratios (PVDR), ie, the range of the ratio of the absorbed dose to tissue directly in line with the mid-plane of the microbeam to that in the mid-plane between adjacent microbeams. Novel physical dosimetry of the microbeams using the online MOSFET reader system will be presented. Comparison of the experimental results with both GaF film measurements and Monte Carlo computer-simulated dosimetry are described here for selected points in the peak and valley regions of a microbeam-irradiated tissue phantom

  18. Review on analog/radio frequency performance of advanced silicon MOSFETs

    Science.gov (United States)

    Passi, Vikram; Raskin, Jean-Pierre

    2017-12-01

    Aggressive gate-length downscaling of the metal-oxide-semiconductor field-effect transistor (MOSFET) has been the main stimulus for the growth of the integrated circuit industry. This downscaling, which has proved beneficial to digital circuits, is primarily the result of the need for improved circuit performance and cost reduction and has resulted in tremendous reduction of the carrier transit time across the channel, thereby resulting in very high cut-off frequencies. It is only in recent decades that complementary metal-oxide-semiconductor (CMOS) field-effect transistor (FET) has been considered as the radio frequency (RF) technology of choice. In this review, the status of the digital, analog and RF figures of merit (FoM) of silicon-based FETs is presented. State-of-the-art devices with very good performance showing low values of drain-induced barrier lowering, sub-threshold swing, high values of gate transconductance, Early voltage, cut-off frequencies, and low minimum noise figure, and good low-frequency noise characteristic values are reported. The dependence of these FoM on the device gate length is also shown, helping the readers to understand the trends and challenges faced by shorter CMOS nodes. Device performance boosters including silicon-on-insulator substrates, multiple-gate architectures, strain engineering, ultra-thin body and buried-oxide and also III-V and 2D materials are discussed, highlighting the transistor characteristics that are influenced by these boosters. A brief comparison of the two main contenders in continuing Moore’s law, ultra-thin body buried-oxide and fin field-effect transistors are also presented. The authors would like to mention that despite extensive research carried out in the semiconductor industry, silicon-based MOSFET will continue to be the driving force in the foreseeable future.

  19. Mobility-limiting mechanisms in single and dual channel strained Si/SiGe MOSFETs

    International Nuclear Information System (INIS)

    Olsen, S.H.; Dobrosz, P.; Escobedo-Cousin, E.; Bull, S.J.; O'Neill, A.G.

    2005-01-01

    Dual channel strained Si/SiGe CMOS architectures currently receive great attention due to maximum performance benefits being predicted for both n- and p-channel MOSFETs. Epitaxial growth of a compressively strained SiGe layer followed by tensile strained Si can create a high mobility buried hole channel and a high mobility surface electron channel on a single relaxed SiGe virtual substrate. However, dual channel n-MOSFETs fabricated using a high thermal budget exhibit compromised mobility enhancements compared with single channel devices, in which both electron and hole channels form in strained Si. This paper investigates the mobility-limiting mechanisms of dual channel structures. The first evidence of increased interface roughness due to the introduction of compressively strained SiGe below the tensile strained Si channel is presented. Interface corrugations degrade electron mobility in the strained Si. Roughness measurements have been carried out using AFM and TEM. Filtering AFM images allowed roughness at wavelengths pertinent to carrier transport to be studied and the results are in agreement with electrical data. Furthermore, the first comparison of strain measurements in the surface channels of single and dual channel architectures is presented. Raman spectroscopy has been used to study channel strain both before and after processing and indicates that there is no impact of the buried SiGe layer on surface macrostrain. The results provide further evidence that the improved performance of the single channel devices fabricated using a high thermal budget arises from improved surface roughness and reduced Ge diffusion into the Si channel

  20. MOSFET-like CNFET based logic gate library for low-power application: a comparative study

    International Nuclear Information System (INIS)

    Gowri Sankar, P. A.; Udhayakumar, K.

    2014-01-01

    The next generation of logic gate devices are expected to depend upon radically new technologies mainly due to the increasing difficulties and limitations of existing CMOS technology. MOSFET like CNFETs should ideally be the best devices to work with for high-performance VLSI. This paper presents results of a comprehensive comparative study of MOSFET-like carbon nanotube field effect transistors (CNFETs) technology based logic gate library for high-speed, low-power operation than conventional bulk CMOS libraries. It focuses on comparing four promising logic families namely: complementary-CMOS (C-CMOS), transmission gate (TG), complementary pass logic (CPL) and Domino logic (DL) styles are presented. Based on these logic styles, the proposed library of static and dynamic NAND-NOR logic gates, XOR, multiplexer and full adder functions are implemented efficiently and carefully analyzed with a test bench to measure propagation delay and power dissipation as a function of supply voltage. This analysis provides the right choice of logic style for low-power, high-speed applications. Proposed logic gates libraries are simulated using Synopsys HSPICE based on the standard 32 nm CNFET model. The simulation results demonstrate that, it is best to use C-CMOS logic style gates that are implemented in CNFET technology which are superior in performance compared to other logic styles, because of their low average power-delay-product (PDP). The analysis also demonstrates how the optimum supply voltage varies with logic styles in ultra-low power systems. The robustness of the proposed logic gate library is also compared with conventional and state-art of CMOS logic gate libraries. (semiconductor integrated circuits)

  1. The Benefits of SiC MOSFETs in a T-Type Inverter for Grid-Tie Applications

    DEFF Research Database (Denmark)

    Anthon, Alexander; Zhang, Zhe; Andersen, Michael A. E.

    2016-01-01

    at the expense of increased switching losses since these outer switches must now block the full DC link voltage. Silicon Carbide (SiC) MOSFET devices potentially offer substantial advantage in this context with their lower switching losses, but the benefit of replacing all switching devices in a T-Type inverter...... measurements to precisely compare semiconductor losses for these two alternatives for a T-Type inverter operating at or near unity power factor. The results show that replacing only the DC bus connection switches with SiC devices significantly reduces the semiconductor losses, allowing either the converter...... power level or the switching frequency to be significantly increased for the same device losses. Hence the use of SiC MOSFETS for T-Type inverters can be seen to be an attractive and potentially cost effective alternative, since only two switching devices per phase leg need to be upgraded....

  2. Performance of a 100V Half-Bridge MOSFET Driver, Type MIC4103, Over a Wide Temperature Range

    Science.gov (United States)

    Patterson, Richard L.; Hammoud, Ahmad

    2011-01-01

    The operation of a high frequency, high voltage MOSFET (metal-oxide semiconductor field-effect transistors) driver was investigated over a wide temperature regime that extended beyond its specified range. The Micrel MIC4103 is a 100V, non-inverting, dual driver that is designed to independently drive both high-side and low-side N-channel MOSFETs. It features fast propagation delay times and can drive 1000 pF load with 10ns rise times and 6 ns fall times [1]. The device consumes very little power, has supply under-voltage protection, and is rated for a -40 C to +125 C junction temperature range. The floating high-side driver of the chip can sustain boost voltages up to 100 V. Table I shows some of the device manufacturer s specification.

  3. Analytical modeling of linearly graded alloy material gate recessed ultra thin body source/drain SON MOSFET

    Science.gov (United States)

    Dutta, Pranab Kishore; Manna, Bibhas; Sarkar, Subir Kumar

    2015-01-01

    An explicit analytical model of surface potential profile and threshold voltage of work function engineered gate (WFEG) recessed source/drain (Re S/D) MOSFET has been presented in this paper. A two dimensional Poisson's equation has been solved with parabolic potential approximation to establish the expressions of front and back channel surface potential distribution and the threshold voltage has been derived from the minima of such obtained potential. In this work, the benefits of linearly graded binary alloy gate and recessed source/drain structures are expected to be available simultaneously in ultra short channel SOI/SON MOSFETs structures. Analytical results are compared with those obtained from the 2D MEDICI device simulator to validate our present model.

  4. Signal Processing for Wireless Communication MIMO System with Nano- Scaled CSDG MOSFET based DP4T RF Switch.

    Science.gov (United States)

    Srivastava, Viranjay M

    2015-01-01

    In the present technological expansion, the radio frequency integrated circuits in the wireless communication technologies became useful because of the replacement of increasing number of functions, traditional hardware components by modern digital signal processing. The carrier frequencies used for communication systems, now a day, shifted toward the microwave regime. The signal processing for the multiple inputs multiple output wireless communication system using the Metal- Oxide-Semiconductor Field-Effect-Transistor (MOSFET) has been done a lot. In this research the signal processing with help of nano-scaled Cylindrical Surrounding Double Gate (CSDG) MOSFET by means of Double- Pole Four-Throw Radio-Frequency (DP4T RF) switch, in terms of Insertion loss, Isolation, Reverse isolation and Inter modulation have been analyzed. In addition to this a channel model has been presented. Here, we also discussed some patents relevant to the topic.

  5. Practical investigation of the gate bias effect on the reverse recovery behavior of the body diode in power MOSFETs

    DEFF Research Database (Denmark)

    Lindberg-Poulsen, Kristian; Petersen, Lars Press; Ouyang, Ziwei

    2014-01-01

    This work considers an alternative method of reducing the body diode reverse recovery by taking advantage of the MOSFET body effect, and applying a bias voltage to the gate before reverse recovery. A test method is presented, allowing the accurate measurement of voltage and current waveforms during...... reverse recovery at high di=dt. Different bias voltages and dead times are combined, giving a loss map which makes it possible to evaluate the practical efficacy of gate bias on reducing the MOSFET body diode reverse recovery, while comparing it to the well known methods of dead time optimization....... A selection of 60V devices for synchronous rectification are compared for their suitability for gate bias, while a selection of 600V devices are compared for the efficacy of gate bias for the zero voltage transition converter application. The results show that many of the tested devices benefit from greatly...

  6. In vivo dosimetry in intraoperative electron radiotherapy. microMOSFETs, radiochromic films and a general-purpose linac

    Energy Technology Data Exchange (ETDEWEB)

    Lopez-Tarjuelo, Juan; Marco-Blancas, Noelia de; Santos-Serra, Agustin; Quiros-Higueras, Juan David [Consorcio Hospitalario Provincial de Castellon, Servicio de Radiofisica y Proteccion Radiologica, Castellon de la Plana (Spain); Bouche-Babiloni, Ana; Morillo-Macias, Virginia; Ferrer-Albiach, Carlos [Consorcio Hospitalario Provincial de Castellon, Servicio de Oncologia Radioterapica, Castellon de la Plana (Spain)

    2014-11-15

    In vivo dosimetry is desirable for the verification, recording, and eventual correction of treatment in intraoperative electron radiotherapy (IOERT). Our aim is to share our experience of metal oxide semiconductor field-effect transistors (MOSFETs) and radiochromic films with patients undergoing IOERT using a general-purpose linac. We used MOSFETs inserted into sterile bronchus catheters and radiochromic films that were cut, digitized, and sterilized by means of gas plasma. In all, 59 measurements were taken from 27 patients involving 15 primary tumors (seven breast and eight non-breast tumors) and 12 relapses. Data were subjected to an outliers' analysis and classified according to their compatibility with the relevant doses. Associations were sought regarding the type of detector, breast and non-breast irradiation, and the radiation oncologist's assessment of the difficulty of detector placement. At the same time, 19 measurements were carried out at the tumor bed with both detectors. MOSFET measurements (D = 93.5 %, s{sub D} = 6.5 %) were not significantly shifted from film measurements (D = 96.0 %, s{sub D} = 5.5 %; p = 0.109), and no associations were found (p = 0.526, p = 0.295, and p = 0.501, respectively). As regards measurements performed at the tumor bed with both detectors, MOSFET measurements (D = 95.0 %, s{sub D} = 5.4 %) were not significantly shifted from film measurements (D = 96.4 %, s{sub D} = 5.0 %; p = 0.363). In vivo dosimetry can produce satisfactory results at every studied location with a general-purpose linac. Detector choice should depend on user factors, not on the detector performance itself. Surgical team collaboration is crucial to success. (orig.) [German] Die In-vivo-Dosimetrie ist wuenschenswert fuer die Ueberpruefung, Registrierung und die eventuelle Korrektur der Behandlungen in der IOERT (''Intraoperative Electron Radiation Therapy''). Unser Ziel ist die Veroeffentlichung unserer Erfahrungen beim

  7. Effective dose assessment in the maxillofacial region using thermoluminescent (TLD) and metal oxide semiconductor field-effect transistor (MOSFET) dosemeters: a comparative study

    Science.gov (United States)

    Schulze, D; Wolff, J; Rottke, D

    2014-01-01

    Objectives: The objective of this study was to compare the performance of metal oxide semiconductor field-effect transistor (MOSFET) technology dosemeters with thermoluminescent dosemeters (TLDs) (TLD 100; Thermo Fisher Scientific, Waltham, MA) in the maxillofacial area. Methods: Organ and effective dose measurements were performed using 40 TLD and 20 MOSFET dosemeters that were alternately placed in 20 different locations in 1 anthropomorphic RANDO® head phantom (the Phantom Laboratory, Salem, NY). The phantom was exposed to four different CBCT default maxillofacial protocols using small (4 × 5 cm) to full face (20 × 17 cm) fields of view (FOVs). Results: The TLD effective doses ranged between 7.0 and 158.0 µSv and the MOSFET doses between 6.1 and 175.0 µSv. The MOSFET and TLD effective doses acquired using four different (FOV) protocols were as follows: face maxillofacial (FOV 20 × 17 cm) (MOSFET, 83.4 µSv; TLD, 87.6 µSv; −5%); teeth, upper jaw (FOV, 8.5 × 5.0 cm) (MOSFET, 6.1 µSv; TLD, 7.0 µSv; −14%); tooth, mandible and left molar (FOV, 4 × 5 cm) (MOSFET, 10.3 µSv; TLD, 12.3 µSv; −16%) and teeth, both jaws (FOV, 10 × 10 cm) (MOSFET, 175 µSv; TLD, 158 µSv; +11%). The largest variation in organ and effective dose was recorded in the small FOV protocols. Conclusions: Taking into account the uncertainties of both measurement methods and the results of the statistical analysis, the effective doses acquired using MOSFET dosemeters were found to be in good agreement with those obtained using TLD dosemeters. The MOSFET dosemeters constitute a feasible alternative for TLDs for the effective dose assessment of CBCT devices in the maxillofacial region. PMID:25143020

  8. Investigation of high mobility pseudomorphic SiGe p-channels in Si MOSFETS at low and high electric fields

    International Nuclear Information System (INIS)

    Palmer, Martin John

    2001-01-01

    Silicon Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) for high speed, high current applications are rapidly approaching the physical and financial limits of the technology. This opens opportunities for the incorporation of materials with intrinsically better transport characteristics. An alloy of silicon and germanium is one such material that is gaining much recognition as the active component of MOSFETs and as the secondary structures (such as the gate electrode). This work examines a batch of buried channel Si 0.64 Ge 0.36 p-MOSFETs, with a minimum effective length of 0.35 μm, under different bias conditions and at different temperatures. High current and transconductance enhancements are apparent at long gate lengths. The carrier mobility is up to a factor of 2.5 times that of silicon at room temperature and 7.5 times at 4 K. A clear trend of decreasing peak mobility with decreasing silicon cap thickness is evident. Simulations show that scattering caused by the roughness of the SiO 2 /Si interface dominates, rather than alloy scattering or Si/SiGe roughness, even for a buried channel. This scattering increases with the proximity of the carriers to the interface. An increase of interface trap density with decreasing cap thickness, demonstrates that segregated germanium exists some distance into the cap and interferes with the oxidation process. This will increase scattering through increased SiO 2 /Si roughness and increased trapped charge. The short channel, high field results are comparable or slightly worse than those of silicon due to lower saturation drift velocity. However, fitting to a drift-diffusion model shows an apparent increase in saturation velocity for short channels, especially at low temperatures. This effect correlates with the low field mobility and is greater for devices containing SiGe. This is an indication of velocity overshoot, which may enhance the performance of SiGe MOSFETs at deep submicron gate lengths. (author)

  9. Designing 4H-SiC P-shielding trench gate MOSFET to optimize on-off electrical characteristics

    Science.gov (United States)

    Kyoung, Sinsu; Hong, Young-sung; Lee, Myung-hwan; Nam, Tae-jin

    2018-02-01

    In order to enhance specific on-resistance (Ron,sp), the trench gate structure was also introduced into 4H-SiC MOSFET as Si MOSFET. But the 4H-SiC trench gate has worse off-state characteristics than the Si trench gate due to the incomplete gate oxidation process (Šimonka et al., 2017). In order to overcome this problem, P-shielding trench gate MOSFET (TMOS) was proposed and researched in previous studies. But P-shielding has to be designed with minimum design rule in order to protect gate oxide effectively. P-shielding TMOS also has the drawback of on-state characteristics degradation corresponding to off state improvement for minimum design rule. Therefore optimized design is needed to satisfy both on and off characteristics. In this paper, the design parameters were analyzed and optimized so that the 4H-SiC P-shielding TMOS satisfies both on and off characteristics. Design limitations were proposed such that P-shielding is able to defend the gate oxide. The P-shielding layer should have the proper junction depth and concentration to defend the electric field to gate oxide during the off-state. However, overmuch P-shielding junction depth disturbs the on-state current flow, a problem which can be solved by increasing the trench depth. As trench depth increases, however, the breakdown voltage decreases. Therefore, trench depth should be designed with due consideration for on-off characteristics. For this, design conditions and modeling were proposed which allow P-shielding to operate without degradation of on-state characteristics. Based on this proposed model, the 1200 V 4H-SiC P-shielding trench gate MOSFET was designed and optimized.

  10. In-vivo dosimetry for conformal arc therapy using several MOSFET in stereotactic radiosurgery computed by an inverse model

    OpenAIRE

    Sors Aurélie; Cassol Emmanuelle; Masquère Mathieu; Latorzeff Igor; Duthil Pierre; Chauveau Nicolas; Lotterie Jean-Albert; Sabatier Jean; Redon Alain; Berry Isabelle; Franceries Xavier

    2016-01-01

    In-vivo dosimetry is still a challenge in stereotactic radiosurgery since most of treatments are delivered using rotational technique with small fields. A realistic and practical solution for these treatments delivered in conformal radiotherapy is proposed to control the absorbed dose at isocentre, using multiple surface MOSFET measurements over an arc. On the one hand, a forward method was developed to optimize the location of the detectors at the patient surface, taking into account arc len...

  11. A novel trench gate MOSFET with a multiple-layered gate oxide for high-reliability operation

    International Nuclear Information System (INIS)

    Kim, Sang Gi; Kah, Dong Ha; Na, Kyoung Il; Yang, Yil Suk; Koo, Jin Gun; Kim, Jong Dae; Lee, Jin Ho; Park, Hoon Soo

    2012-01-01

    Gate dielectrics in trench structures for trench gate metal oxide semiconductor field-effect transistor (MOSFET) power devices are very important to realize excellent characteristics. In this paper we describe multiple-layer gate dielectrics for trench gate MOSFETs with both thermal and chemical vapor deposition (CVD) gate oxides that exhibit excellent gate oxide properties and surface roughness. Through various trench etching experiments for better surface conditions in the trench, the optimum etching gas chemistry and etch conditions were found. The destruction of gate dielectric in trench gate MOSFET occurs at the top and the bottom trench corner edges. The structure of the gate electrode is pulled out with the polysilicon layer which is buried in the trench. Thus, high electric field operation is inevitable at the gate between source diffusion and the gate polysilicon. Moreover, the trench corner oxide suffers from the high electric field. We propose a multiple-gate dielectric structure of a thermal oxide and CVD oxide for highly reliable operation of the device. This enables trench surface smoothing and low thermal stress at the trench corners and provides the oxide thickness uniformity, giving superior device characteristics of high breakdown voltage and low leakage current. These improvements are caused by the excellent quality of the gate oxide and the good thickness uniformity that is formed at the inner trench with a specific geometrical factor.

  12. Comprehensive analysis of sub-20 nm black phosphorus based junctionless-recessed channel MOSFET for analog/RF applications

    Science.gov (United States)

    Kumar, Ajay; Tripathi, M. M.; Chaujar, Rishu

    2018-04-01

    In this work, a comprehensive analog and RF performance of a novel Black Phosphorus-Junctionless-Recessed Channel (BP-JL-RC) MOSFET has been explored at 45 nm technology node (Gate length = 20 nm). The integration of black phosphorus with junctionless recessed channel MOSFET, leads to higher drain current of about 0.3 mA and excellent switching ratio (of the order of 1011) due to reduced off-current which leads to improvement in sub-threshold slope (SS) (67mV/dec). Further, RF performance metrics have also been studied with an aim to analyze high-frequency performance. The following FOMs have been evaluated: cut-off frequency (fT), maximum oscillator frequency (fMAX), stern stability factor, various power gains and parasitic capacitances at THz frequency range. Thus, in addition to the high packing density offered by RC MOSFET, the proposed design finds numerous application at THz frequency making it a promising candidate at wafer scale integration level.

  13. Numerical study of self-heating effects of small-size MOSFETs fabricated on silicon-on-aluminum nitride substrate

    International Nuclear Information System (INIS)

    Ding Yanfang; Zhu Ziqiang; Zhu Ming; Lin Chenglu

    2006-01-01

    Compared with bulk-silicon technology, silicon-on-insulator (SOI) technology possesses many advantages but it is inevitable that the buried silicon dioxide layer also thermally insulates the metal-oxide-silicon field-effect transistors (MOSFETs) from the bulk due to the low thermal conductivity. One of the alternative insulator to replace the buried oxide layer is aluminum nitride (MN), which has a thermal conductivity that is about 200 times higher than that of SiO 2 (320 W·m -1 ·K -1 versus 1.4 W·m -1 ·K -l ). To investigate the self-heating effects of small-size MOSFETs fabricated on silicon-on-aluminum nitride (SOAN) substrate, a two-dimensional numerical analysis is performed by using a device simulator called MEDICI run on a Solaris workstation to simulate the electrical characteristics and temperature distribution by comparing with those of bulk and standard SOI MOSFETs. Our study suggests that AIN is a suitable alternative to silicon dioxide as a buried dielectric in SOI and expands the applications of SOI to high temperature conditions. (authors)

  14. Long-Term Reliability of a Hard-Switched Boost Power Processing Unit Utilizing SiC Power MOSFETs

    Science.gov (United States)

    Ikpe, Stanley A.; Lauenstein, Jean-Marie; Carr, Gregory A.; Hunter, Don; Ludwig, Lawrence L.; Wood, William; Iannello, Christopher J.; Del Castillo, Linda Y.; Fitzpatrick, Fred D.; Mojarradi, Mohammad M.; hide

    2016-01-01

    Silicon carbide (SiC) power devices have demonstrated many performance advantages over their silicon (Si) counterparts. As the inherent material limitations of Si devices are being swiftly realized, wide-band-gap (WBG) materials such as SiC have become increasingly attractive for high power applications. In particular, SiC power metal oxide semiconductor field effect transistors' (MOSFETs) high breakdown field tolerance, superior thermal conductivity and low-resistivity drift regions make these devices an excellent candidate for power dense, low loss, high frequency switching applications in extreme environment conditions. In this paper, a novel power processing unit (PPU) architecture is proposed utilizing commercially available 4H-SiC power MOSFETs from CREE Inc. A multiphase straight boost converter topology is implemented to supply up to 10 kilowatts full-scale. High Temperature Gate Bias (HTGB) and High Temperature Reverse Bias (HTRB) characterization is performed to evaluate the long-term reliability of both the gate oxide and the body diode of the SiC components. Finally, susceptibility of the CREE SiC MOSFETs to damaging effects from heavy-ion radiation representative of the on-orbit galactic cosmic ray environment are explored. The results provide the baseline performance metrics of operation as well as demonstrate the feasibility of a hard-switched PPU in harsh environments.

  15. In-vivo dosimetry for conformal arc therapy using several MOSFET in stereotactic radiosurgery computed by an inverse model

    Directory of Open Access Journals (Sweden)

    Sors Aurélie

    2016-01-01

    Full Text Available In-vivo dosimetry is still a challenge in stereotactic radiosurgery since most of treatments are delivered using rotational technique with small fields. A realistic and practical solution for these treatments delivered in conformal radiotherapy is proposed to control the absorbed dose at isocentre, using multiple surface MOSFET measurements over an arc. On the one hand, a forward method was developed to optimize the location of the detectors at the patient surface, taking into account arc length, prescribed isocentre dose, collimator and field size. On the other hand, an inverse method was used to compute the dose at isocentre for conformal arc therapy in stereotactic radiosurgery, using MOSFET measurements. Finally, the reconstructed dose at isocentre was compared to real measurement, obtained for several detectors positioned at a phantom surface. Results show that the inverse method gives good results with five MOSFET equi-spaced positioned within the arc beam course: deviation between prescribed and computed average total dose at isocentre was below 2% both for 30×30 mm2 and 18×18 mm2 field size

  16. In-vivo dosimetry for conformal arc therapy using several MOSFET in stereotactic radiosurgery computed by an inverse model

    Science.gov (United States)

    Sors, Aurélie; Cassol, Emmanuelle; Masquère, Mathieu; Latorzeff, Igor; Duthil, Pierre; Chauveau, Nicolas; Lotterie, Jean-Albert; Sabatier, Jean; Redon, Alain; Berry, Isabelle; Franceries, Xavier

    2016-09-01

    In-vivo dosimetry is still a challenge in stereotactic radiosurgery since most of treatments are delivered using rotational technique with small fields. A realistic and practical solution for these treatments delivered in conformal radiotherapy is proposed to control the absorbed dose at isocentre, using multiple surface MOSFET measurements over an arc. On the one hand, a forward method was developed to optimize the location of the detectors at the patient surface, taking into account arc length, prescribed isocentre dose, collimator and field size. On the other hand, an inverse method was used to compute the dose at isocentre for conformal arc therapy in stereotactic radiosurgery, using MOSFET measurements. Finally, the reconstructed dose at isocentre was compared to real measurement, obtained for several detectors positioned at a phantom surface. Results show that the inverse method gives good results with five MOSFET equi-spaced positioned within the arc beam course: deviation between prescribed and computed average total dose at isocentre was below 2% both for 30×30 mm2 and 18×18 mm2 field size

  17. Impacts of gate bias and its variation on gamma-ray irradiation resistance of SiC MOSFETs

    Energy Technology Data Exchange (ETDEWEB)

    Murata, Koichi; Mitomo, Satoshi; Matsuda, Takuma; Yokoseki, Takashi [Saitama University, Sakuraku (Japan); National Institutes for Quantum and Radiological Science and Technology (QST), Takasaki (Japan); Makino, Takahiro; Onoda, Shinobu; Takeyama, Akinori; Ohshima, Takeshi [National Institutes for Quantum and Radiological Science and Technology (QST), Takasaki (Japan); Okubo, Shuichi; Tanaka, Yuki; Kandori, Mikio; Yoshie, Toru [Sanken Electric Co., Ltd., Niiza, Saitama (Japan); Hijikata, Yasuto [Saitama University, Sakuraku (Japan)

    2017-04-15

    Gamma-ray irradiation into vertical type n-channel hexagonal (4H)-silicon carbide (SiC) metal-oxide-semiconductor field effect transistors (MOSFETs) was performed under various gate biases. The threshold voltage for the MOSFETs irradiated with a constant positive gate bias showed a large negative shift, and the shift slightly recovered above 100 kGy. For MOSFETs with non- and a negative constant biases, no significant change in threshold voltage, V{sub th}, was observed up to 400 kGy. By changing the gate bias from positive bias to either negative or non-bias, the V{sub th} significantly recovered from the large negative voltage shift induced by 50 kGy irradiation with positive gate bias after only 10 kGy irradiation with either negative or zero bias. It indicates that the positive charges generated in the gate oxide near the oxide-SiC interface due to irradiation were removed or recombined instantly by the irradiation under zero or negative biases. (copyright 2016 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim)

  18. Investigations of interference between electromagnetic transponders and wireless MOSFET dosimeters: a phantom study.

    Science.gov (United States)

    Su, Zhong; Zhang, Lisha; Ramakrishnan, V; Hagan, Michael; Anscher, Mitchell

    2011-05-01

    To evaluate both the Calypso Systems' (Calypso Medical Technologies, Inc., Seattle, WA) localization accuracy in the presence of wireless metal-oxide-semiconductor field-effect transistor (MOSFET) dosimeters of dose verification system (DVS, Sicel Technologies, Inc., Morrisville, NC) and the dosimeters' reading accuracy in the presence of wireless electromagnetic transponders inside a phantom. A custom-made, solid-water phantom was fabricated with space for transponders and dosimeters. Two inserts were machined with positioning grooves precisely matching the dimensions of the transponders and dosimeters and were arranged in orthogonal and parallel orientations, respectively. To test the transponder localization accuracy with/without presence of dosimeters (hypothesis 1), multivariate analyses were performed on transponder-derived localization data with and without dosimeters at each preset distance to detect statistically significant localization differences between the control and test sets. To test dosimeter dose-reading accuracy with/without presence of transponders (hypothesis 2), an approach of alternating the transponder presence in seven identical fraction dose (100 cGy) deliveries and measurements was implemented. Two-way analysis of variance was performed to examine statistically significant dose-reading differences between the two groups and the different fractions. A relative-dose analysis method was also used to evaluate transponder impact on dose-reading accuracy after dose-fading effect was removed by a second-order polynomial fit. Multivariate analysis indicated that hypothesis 1 was false; there was a statistically significant difference between the localization data from the control and test sets. However, the upper and lower bounds of the 95% confidence intervals of the localized positional differences between the control and test sets were less than 0.1 mm, which was significantly smaller than the minimum clinical localization resolution of 0

  19. Characterization of a new MOSFET detector configuration for in vivo skin dosimetry

    International Nuclear Information System (INIS)

    Scalchi, Paolo; Francescon, Paolo; Rajaguru, Priyadarshini

    2005-01-01

    The dose released to the patient skin during a radiotherapy treatment is important when the skin is an organ at risk, or on the contrary, is included in the target volume. Since most treatment planning programs do not predict dose within several millimeters of the body surface, it is important to have a method to verify the skin dose for the patient who is undergoing radiotherapy. A special type of metal oxide semiconductors field-effect transistors (MOSFET) was developed to perform in vivo skin dosimetry for radiotherapy treatments. Water-equivalent depth (WED), both manufacturing and sensor reproducibility, dependence on both field size and angulation of the sensor were investigated using 6 MV photon beams. Patient skin dosimetries were performed during 6 MV total body irradiations (TBI). The resulting WEDs ranged from 0.04 and 0.15 mm (0.09 mm on average). The reproducibility of the sensor response, for doses of 50 cGy, was within ±2% (maximum deviation) and improves with increasing sensitivity or dose level. As to the manufacturing reproducibility, it was found to be ±0.055 mm. No WED dependence on the field size was verified, but possible variations of this quantity with the field size could be hidden by the assessment uncertainty. The angular dependence, for both phantom-surface and in-air setups, when referred to the mean response, is within ±27% until 80 deg. rotations. The results of the performed patient skin dosimetries showed that, normally, our TBI setup was suitable to give skin the prescribed dose, but, for some cases, interventions were necessary: as a consequence the TBI setup was corrected. The water-equivalent depth is, on average, less than the thinnest thermoluminescent dosimeters (TLD). In addition, when compared with TLDs, the skin MOSFETs have significant advantages, like immediate both readout and reuse, as well as the permanent storage of dose. These sensors are also waterproof. The in vivo dosimetries performed prove the importance of

  20. Structure-based capacitance modeling and power loss analysis for the latest high-performance slant field-plate trench MOSFET

    Science.gov (United States)

    Kobayashi, Kenya; Sudo, Masaki; Omura, Ichiro

    2018-04-01

    Field-plate trench MOSFETs (FP-MOSFETs), with the features of ultralow on-resistance and very low gate–drain charge, are currently the mainstream of high-performance applications and their advancement is continuing as low-voltage silicon power devices. However, owing to their structure, their output capacitance (C oss), which leads to main power loss, remains to be a problem, especially in megahertz switching. In this study, we propose a structure-based capacitance model of FP-MOSFETs for calculating power loss easily under various conditions. Appropriate equations were modeled for C oss curves as three divided components. Output charge (Q oss) and stored energy (E oss) that were calculated using the model corresponded well to technology computer-aided design (TCAD) simulation, and we validated the accuracy of the model quantitatively. In the power loss analysis of FP-MOSFETs, turn-off loss was sufficiently suppressed, however, mainly Q oss loss increased depending on switching frequency. This analysis reveals that Q oss may become a significant issue in next-generation high-efficiency FP-MOSFETs.

  1. Process Characterization of 32nm Semi Analytical Bilayer Graphene-based MOSFET

    Directory of Open Access Journals (Sweden)

    Noor Faizah Z.A.

    2016-01-01

    Full Text Available This paper presents an inclusive study and analysis of graphene-based MOSFET device at 32nm gate length. The analysis was based on top-gated structure which utilized Hafnium Dioxide (HfO2 dielectrics and metal gate. The same conventional process flows of a transistor were applied except the deposition of bilayer graphene as a channel. The analytical expression of the channel potential includes all relevant physics of bilayer graphene and by assuming that this device displays an ideal ohmic contact and functioned at a ballistic transport. Based on the designed transistor, the on-state current (ION for both GNMOS and GPMOS shows a promising performance where the value is 982.857uA/um and 99.501uA/um respectively. The devices also possess a very small leakage current (IOFF of 0.289578nA/um for GNMOS and 0.130034nA/um for GPMOS as compared to the conventional SiO2/Poly-Si and high-k metal gate transistors. However, the devices suffer an inappropriate subthreshold swing (SS and high value of drain induced barrier lowering (DIBL.

  2. A Nonvolatile MOSFET Memory Device Based on Mobile Protons in SiO(2) Thin Films

    Energy Technology Data Exchange (ETDEWEB)

    Vanheusden, K.; Warren, W.L.; Devine, R.A.B.; Fleetwood, D.M.; Draper, B.L.; Schwank, J.R.

    1999-03-02

    It is shown how mobile H{sup +} ions can be generated thermally inside the oxide layer of Si/SiO{sub 2}/Si structures. The technique involves only standard silicon processing steps: the nonvolatile field effect transistor (NVFET) is based on a standard MOSFET with thermally grown SiO{sub 2} capped with a poly-silicon layer. The capped thermal oxide receives an anneal at {approximately}1100 C that enables the incorporation of the mobile protons into the gate oxide. The introduction of the protons is achieved by a subsequent 500-800 C anneal in a hydrogen-containing ambient, such as forming gas (N{sub 2}:H{sub 2} 95:5). The mobile protons are stable and entrapped inside the oxide layer, and unlike alkali ions, their space-charge distribution can be controlled and rapidly rearranged at room temperature by an applied electric field. Using this principle, a standard MOS transistor can be converted into a nonvolatile memory transistor that can be switched between normally on and normally off. Switching speed, retention, endurance, and radiation tolerance data are presented showing that this non-volatile memory technology can be competitive with existing Si-based non-volatile memory technologies such as the floating gate technologies (e.g. Flash memory).

  3. Phonon scattering limited performance of monolayer MoS2 and WSe2 n-MOSFET

    Directory of Open Access Journals (Sweden)

    Amretashis Sengupta

    2015-02-01

    Full Text Available In this paper we show the effect of electron-phonon scattering on the performance of monolayer (1L MoS2 and WSe2 channel based n-MOSFETs. Electronic properties of the channel materials are evaluated using the local density approximation (LDA in density functional theory (DFT. For phonon dispersion we employ the small displacement / frozen phonon calculations in DFT. Thereafter using the non-equilibrium Green’s function (NEGF formalism, we study the effect of electron-phonon scattering and the contribution of various phonon modes on the performance of such devices. It is found that the performance of the WSe2 device is less impacted by phonon scattering, showing a ballisticity of 83% for 1L-WSe2 FET for channel length of 10 nm. Though 1L-MoS2 FET of similar dimension shows a lesser ballisticity of 75%. Also in the presence of scattering there exist a a 21–36% increase in the intrinsic delay time (τ and a 10–18% reduction in peak transconductance (gm for WSe2 and MoS2 devices respectively.

  4. Materials preparation and fabrication of pyroelectric polymer/silicon MOSFET detector arrays. Final report

    Energy Technology Data Exchange (ETDEWEB)

    Bloomfield, P. [Drexel Univ., Philadelphia, PA (United States). Dept. of Materials Engineering

    1992-03-27

    The authors have delivered several 64-element linear arrays of pyroelectric elements fully integrated on silicon wafers with MOS readout devices. They have delivered detailed drawings of the linear arrays to LANL. They have processed a series of two inch wafers per submitted design. Each two inch wafer contains two 64 element arrays. After spin-coating copolymer onto the arrays, vacuum depositing the top electrodes, and polarizing the copolymer films so as to make them pyroelectrically active, each wafer was split in half. The authors developed a thicker oxide coating separating the extended gate electrode (beneath the polymer detector) from the silicon. This should reduce its parasitic capacitance and hence improve the S/N. They provided LANL three processed 64 element sensor arrays. Each array was affixed to a connector panel and selected solder pads of the common ground, the common source voltage supply connections, the 64 individual drain connections, and the 64 drain connections (for direct pyroelectric sensing response rather than the MOSFET action) were wire bonded to the connector panel solder pads. This entails (64 + 64 + 1 + 1) = 130 possible bond connections per 64 element array. This report now details the processing steps and the progress of the individual wafers as they were carried through from beginning to end.

  5. An accurate mobility model for the I-V characteristics of n-channel enhancement-mode MOSFETs with single-channel boron implantation

    International Nuclear Information System (INIS)

    Chingyuan Wu; Yeongwen Daih

    1985-01-01

    In this paper an analytical mobility model is developed for the I-V characteristics of n-channel enhancement-mode MOSFETs, in which the effects of the two-dimensional electric fields in the surface inversion channel and the parasitic resistances due to contact and interconnection are included. Most importantly, the developed mobility model easily takes the device structure and process into consideration. In order to demonstrate the capabilities of the developed model, the structure- and process-oriented parameters in the present mobility model are calculated explicitly for an n-channel enhancement-mode MOSFET with single-channel boron implantation. Moreover, n-channel MOSFETs with different channel lengths fabricated in a production line by using a set of test keys have been characterized and the measured mobilities have been compared to the model. Excellent agreement has been obtained for all ranges of the fabricated channel lengths, which strongly support the accuracy of the model. (author)

  6. Analysis of OFF-state and ON-state performance in a silicon-on-insulator power MOSFET with a low-k dielectric trench

    International Nuclear Information System (INIS)

    Wang Zhigang; Zhang Bo; Li Zhaoji

    2013-01-01

    A novel silicon-on-insulator (SOI) MOSFET with a variable low-k dielectric trench (LDT MOSFET) is proposed and its performance and characteristics are investigated. The trench in the drift region between drain and source is filled with low-k dielectric to extend the effective drift region. At OFF state, the low-k dielectric trench (LDT) can sustain high voltage and enhance the dielectric field due to the accumulation of ionized charges. At the same time, the vertical dielectric field in the buried oxide can also be enhanced by these ionized charges. Additionally, ON-state analysis of LDT MOSFET demonstrates excellent forward characteristics, such as low gate-to-drain charge density ( 2 ) and a robust safe operating area (0–84 V). (semiconductor devices)

  7. Optimization of MOSFET calibration for in vivo dosimetry in radiosurgery: reduction of measurement uncertainties in pre-clinical conditions; Optimisation de la calibration de MOSFET pour la dosimetrie in vivo en radiochirurgie: reduction des incertitudes de mesure en conditions precliniques

    Energy Technology Data Exchange (ETDEWEB)

    Sors, A.; Berry, I.; Franceries, X. [UMR 825 ' imagerie cerebrale et handicaps neurologiques' , Inserm, Toulouse (France); Cassol, E.; Duthil, P. [Unite de radiophysique et de radioprotection, CHU de Toulouse, Toulouse (France); Hallil, A. [Best medical Canada, Ottawa (Canada); Latorzeff, I.; Lotterie, J.A. [Centre de radiochirurgie stereotaxique, CHU Rangueil, Toulouse (France); Redon, A. [Groupe Oncorad Garonne, Montauban (France)

    2011-10-15

    The objective of this study is to assess the conventional formulas of equivalent square for fields with irregular geometry, by transposing the optimized calibration method which has been previously developed, to micro-MOSFET. The study has been performed on a 6 MV Novalis apparatus equipped with micro-multi-blades collimators (BrainLab). The average dose bias reaches 2.66 per cent for all field sizes. Therefore, it appears that the joint use of the square inverse of distances and of conventional formulas of equivalent square results in an acceptable in vivo dosimetry precision. Short communication

  8. MOSFET dosimeter depth-dose measurements in heterogeneous tissue-equivalent phantoms at diagnostic x-ray energies

    International Nuclear Information System (INIS)

    Jones, A.K.; Pazik, F.D.; Hintenlang, D.E.; Bolch, W.E.

    2005-01-01

    The objective of the present study was to explore the use of the TN-1002RD metal-oxide-semiconductor field effect transistor (MOSFET) dosimeter for measuring tissue depth dose at diagnostic photon energies in both homogeneous and heterogeneous tissue-equivalent materials. Three cylindrical phantoms were constructed and utilized as a prelude to more complex measurements within tomographic physical phantoms of pediatric patients. Each cylindrical phantom was constructed as a stack of seven 5-cm-diameter and 1-cm-thick discs of materials radiographically representative of either soft tissue (S), bone (B), or lung tissue (L) at diagnostic photon energies. In addition to a homogeneous phantom of soft tissue (SSSSSSS), two heterogeneous phantoms were constructed: SSBBSSS and SBLLBSS. MOSFET dosimeters were then positioned at the interface of each disc, and the phantoms were then irradiated at 66 kVp and 200 mAs. Measured values of absorbed dose at depth were then compared to predicated values of point tissue dose as determined via Monte Carlo radiation transport modeling. At depths exceeding 2 cm, experimental results matched the computed values of dose with high accuracy regardless of the dosimeter orientation (epoxy bubble facing toward or away from the x-ray beam). Discrepancies were noted, however, between measured and calculated point doses near the surface of the phantom (surface to 2 cm depth) when the dosimeters were oriented with the epoxy bubble facing the x-ray beam. These discrepancies were largely eliminated when the dosimeters were placed with the flat side facing the x-ray beam. It is therefore recommended that the MOSFET dosimeters be oriented with their flat sides facing the beam when they are used at shallow depths or on the surface of either phantoms or patients

  9. Simulation study of ballistic spin-MOSFET devices with ferromagnetic channels based on some Heusler and oxide compounds

    Science.gov (United States)

    Graziosi, Patrizio; Neophytou, Neophytos

    2018-02-01

    Newly emerged materials from the family of Heuslers and complex oxides exhibit finite bandgaps and ferromagnetic behavior with Curie temperatures much higher than even room temperature. In this work, using the semiclassical top-of-the-barrier FET model, we explore the operation of a spin-MOSFET that utilizes such ferromagnetic semiconductors as channel materials, in addition to ferromagnetic source/drain contacts. Such a device could retain the spin polarization of injected electrons in the channel, the loss of which limits the operation of traditional spin transistors with non-ferromagnetic channels. We examine the operation of four material systems that are currently considered some of the most prominent known ferromagnetic semiconductors: three Heusler-type alloys (Mn2CoAl, CrVZrAl, and CoVZrAl) and one from the oxide family (NiFe2O4). We describe their band structures by using data from DFT (Density Functional Theory) calculations. We investigate under which conditions high spin polarization and significant ION/IOFF ratio, two essential requirements for the spin-MOSFET operation, are both achieved. We show that these particular Heusler channels, in their bulk form, do not have adequate bandgap to provide high ION/IOFF ratios and have small magnetoconductance compared to state-of-the-art devices. However, with confinement into ultra-narrow sizes down to a few nanometers, and by engineering their spin dependent contact resistances, they could prove promising channel materials for the realization of spin-MOSFET transistor devices that offer combined logic and memory functionalities. Although the main compounds of interest in this paper are Mn2CoAl, CrVZrAl, CoVZrAl, and NiFe2O4 alone, we expect that the insight we provide is relevant to other classes of such materials as well.

  10. Development of High-k Dielectric for Antimonides and a sub 350 degree Celsius III-V pMOSFET Outperforming Germanium

    Science.gov (United States)

    2010-12-01

    Development of high-k dielectric for Antimonides and a sub 350ºC III-V pMOSFET outperforming Germanium Aneesh Nainani, Toshifumi Irisawa, Ze Yuan...dielectric for Antimonides and a sub 350degreeC III-V pMOSFET outperforming Germanium 5a. CONTRACT NUMBER 5b. GRANT NUMBER 5c. PROGRAM ELEMENT...area etch HCl based clean + 100 cyl. ALD Al2O3 @ 300ºC (~10nm) as gate dielectric Aluminum evaporation + Gate patterning Be implant(9e14dose/10keV)+S

  11. The impact of surface-roughness scattering on the low-field electron mobility in nano-scale Si MOSFETs

    Science.gov (United States)

    Kannan, Gokula; Vasileska, Dragica

    2017-09-01

    A state-of-the-art simulator for the calculation of low-field mobility in inversion layers is presented in this work that accounts for the collisional broadening of the electronic states via the solution of the Dyson equation for the retarded Green's function. The self-consistent Born approximation is used for the calculation of the self-energy contributions due to Coulomb, surface-roughness, acoustic, and non-polar optical phonon scattering. The simulated mobility results for three generations of MOSFET devices are in agreement with the experimental data. At nanoscale dimensions, surface-roughness scattering dominates the collisional broadening of the states and the renormalization of the spectrum.

  12. Temperature influence on the gate-induced floating body effect parameters in fully depleted SOI nMOSFETs

    Science.gov (United States)

    Agopian, Paula Ghedini Der; Martino, João Antonio; Simoen, Eddy; Claeys, Cor

    2008-11-01

    The temperature influence on the gate-induced floating body effect (GIFBE) in fully depleted (FD) silicon-on-insulator (SOI) nMOSFETs is investigated, based on experimental results and two-dimensional numerical simulations. The GIFBE behavior will be evaluated taking into account the impact of carrier recombination and of the effective electric field mobility degradation on the second peak in the transconductance (gm). This floating body effect is also analyzed as a function of temperature. It is shown that the variation of the studied parameters with temperature results in a "C" shape of the threshold voltage corresponding with the second peak in the gm curve.

  13. Etude des transistors MOSFET à barrière Schottky, à canal Silicium et Germanium sur couches minces

    OpenAIRE

    Hutin , Louis

    2010-01-01

    Until the early 2000’s Dennard’s scaling rules at the transistor level have enabled to achieve a performance gain while still preserving the basic structure of the MOSFET building block from one generation to the next. However, this conservative approach has already reached its limits as shown by the introduction of channel stressors for the sub-130 nm technological nodes, and later high-k/metal gate stacks for the sub-65 nm nodes. Despite the introduction of high-k gate dielectrics, constrai...

  14. In vivo dosimetry in intraoperative electron radiotherapy: microMOSFETs, radiochromic films and a general-purpose linac.

    Science.gov (United States)

    López-Tarjuelo, Juan; Bouché-Babiloni, Ana; Morillo-Macías, Virginia; de Marco-Blancas, Noelia; Santos-Serra, Agustín; Quirós-Higueras, Juan David; Ferrer-Albiach, Carlos

    2014-10-01

    In vivo dosimetry is desirable for the verification, recording, and eventual correction of treatment in intraoperative electron radiotherapy (IOERT). Our aim is to share our experience of metal oxide semiconductor field-effect transistors (MOSFETs) and radiochromic films with patients undergoing IOERT using a general-purpose linac. We used MOSFETs inserted into sterile bronchus catheters and radiochromic films that were cut, digitized, and sterilized by means of gas plasma. In all, 59 measurements were taken from 27 patients involving 15 primary tumors (seven breast and eight non-breast tumors) and 12 relapses. Data were subjected to an outliers' analysis and classified according to their compatibility with the relevant doses. Associations were sought regarding the type of detector, breast and non-breast irradiation, and the radiation oncologist's assessment of the difficulty of detector placement. At the same time, 19 measurements were carried out at the tumor bed with both detectors. MOSFET measurements ([Formula: see text]  = 93.5 %, sD  =  6.5 %) were not significantly shifted from film measurements ([Formula: see text]  =  96.0 %, sD  =  5.5 %; p  =  0.109), and no associations were found (p = 0.526, p = 0.295,  and p = 0.501, respectively). As regards measurements performed at the tumor bed with both detectors, MOSFET measurements ([Formula: see text]  =  95.0 %, sD  =  5.4 % were not significantly shifted from film measurements ([Formula: see text]  =  96.4 %, sD  =  5.0 %; p  =  0.363). In vivo dosimetry can produce satisfactory results at every studied location with a general-purpose linac. Detector choice should depend on user factors, not on the detector performance itself. Surgical team collaboration is crucial to success.

  15. Separation of effects of oxide-trapped charge and interface-trapped charge on mobility in irradiated power MOSFETs

    International Nuclear Information System (INIS)

    Zupac, D.; Galloway, K.F.; Khosropour, P.; Anderson, S.R.; Schrimpf, R.D.

    1993-01-01

    An effective approach to separating the effects of oxide-trapped charge and interface-trapped charge on mobility degradation in irradiated MOSFETs is demonstrated. It is based on analyzing mobility data sets which have different functional relationships between the radiation-induced-oxide-trapped charge and interface-trapped charge. Separation of effects of oxide-trapped charge and interface-trapped charge is possible only if these two trapped charge components are not linearly dependent. A significant contribution of oxide-trapped charge to mobility degradation is demonstrated and quantified

  16. Separation Test Method for Investigation of Current Density Effects on Bond Wires of SiC Power MOSFET Modules

    DEFF Research Database (Denmark)

    Luo, Haoze; Iannuzzo, Francesco; Blaabjerg, Frede

    2017-01-01

    In this paper, a separation test method for eliminating the effects of different current densities on the bond wires is proposed. The separation test method makes it possible to study the effect of different current density on the fatigue damage of bond wires without changing the temperature swing...... and average temperature during the test. By analyzing the output characteristics of the linear region of MOSFET, the constraint relations among the gate voltage, on-state voltage drop and junction temperature are revealed in this paper. The one-to-one correspondence between gate voltage and conduction power...

  17. Compact electro-thermal modeling of a SiC MOSFET power module under short-circuit conditions

    DEFF Research Database (Denmark)

    Ceccarelli, Lorenzo; Reigosa, Paula Diaz; Bahman, Amir Sajjad

    2017-01-01

    A novel physics-based, electro-thermal model which is capable of estimating accurately the short-circuit behavior and thermal instabilities of silicon carbide MOSFET multi-chip power modules is proposed in this paper. The model has been implemented in PSpice and describes the internal structure...... of the module, including stray elements in the multi-chip layout, self-heating effect, drain leakage current and threshold voltage mismatch. A lumped-parameter thermal network is extracted in order to estimate the internal temperature of the chips. The case study is a half-bridge power module from CREE with 1...

  18. Die degradation effect on aging rate in accelerated cycling tests of SiC power MOSFET modules

    DEFF Research Database (Denmark)

    Luo, Haoze; Baker, Nick; Iannuzzo, Francesco

    2017-01-01

    In order to distinguish the die and bond wire degradations, in this paper both the die and bond wire resistances of SiC MOSFET modules are measured and tested during the accelerated cycling tests. It is proved that, since the die degradation under specific conditions increases the temperature swi......, bond wires undergo harsher thermo-mechanical stress than expected. The experimental results confirm the die-related thermal failure mechanism. An improved degradation model is proposed for the bond-wire resistance increase in case of die degradation....

  19. Optimization of MOSFET calibration for in vivo dosimetry in radiosurgery: reduction of measurement uncertainties in pre-clinical conditions

    International Nuclear Information System (INIS)

    Sors, A.; Berry, I.; Franceries, X.; Cassol, E.; Duthil, P.; Hallil, A.; Latorzeff, I.; Lotterie, J.A.; Redon, A.

    2011-01-01

    The objective of this study is to assess the conventional formulas of equivalent square for fields with irregular geometry, by transposing the optimized calibration method which has been previously developed, to micro-MOSFET. The study has been performed on a 6 MV Novalis apparatus equipped with micro-multi-blades collimators (BrainLab). The average dose bias reaches 2.66 per cent for all field sizes. Therefore, it appears that the joint use of the square inverse of distances and of conventional formulas of equivalent square results in an acceptable in vivo dosimetry precision. Short communication

  20. Modeling, Fabrication, and Analysis of Vertical Conduction Gallium Nitride Fin MOSFET

    Science.gov (United States)

    Tahhan, Maher Bishara

    lithography, the sources are formed, fins are etched, and the gate insulator and metal are deposited. The first functional fabricated devices are presented, but exhibit a few differences from the model. A threshold voltage of -6 V, was measured, with an ID of 5 kA/cm2 at 3 V, and Ron of 0.6 mO/cm 2. The current is limited by the Schottky nature of the top contacts and show a turn-on voltage as a result. These measurements are comparable to recently published GaN fin MOSFET data, whose devices were defined by e-beam lithography. This dissertation work sought to show that a vertical conduction fin MOSFET can be fabricated on GaN. Furthermore, it aimed to provide a self-aligned process that does not require e-beam lithography. With further development, such devices can be designed to hold large voltages while maintaining a small footprint.

  1. Layout-Aware Compact Model of MOSFET Characteristics Variations Induced by STI Stress

    Science.gov (United States)

    Yamada, Kenta; Sato, Takashi; Amakawa, Shuhei; Nakayama, Noriaki; Masu, Kazuya; Kumashiro, Shigetaka

    A compact model is proposed for accurately incorporating effects of STI (shallow trench isolation) stress into post-layout simulation by making layout-dependent corrections to SPICE model parameters. The model takes in-plane (longitudinal and transverse) and normal components of the layout-dependent stress into account, and model formulas are devised from physical considerations. Not only can the model handle the shape of the active-area of any MOSFET conforming to design rules, but also considers distances to neighboring active-areas. Extraction of geometrical parameters from the layout can be performed by standard LVS (layout versus schematic) tools, and the corrections can subsequently be back-annotated into the netlist. The paper spells out the complete formulation by presenting expressions for the mobility and the threshold voltage explicitly by way of example. The model is amply validated by comparisons with experimental data from 90nm-and 65nm-CMOS technologies having the channel orientations of, respectively, ‹110› and ‹100›, both on a (100) surface. The worst-case standard errors turn out to be as small as 1.7% for the saturation current and 8mV for the threshold voltage, as opposed to ˜20% and ˜50mV without the model. Since device characteristics variations due to STI stress constitute a significant part of what have conventionally been treated as random variations, use of the proposed model could enable one to greatly narrow the guardbands required to guarantee a desired yield, thereby facilitating design closure.

  2. Development of a high current high temperature SiC MOSFET based solid-state power controller

    Science.gov (United States)

    Guo, Yuanbo

    Solid-State Power Controllers (SSPCs) are critical components in the development of electric aircraft and must be small in size, fast in response, and have high reliability. They are also proposed for use in microgrids to improve the power quality and system reliability. The development of Silicon Carbide (SiC) semiconductor switches provides a series of improvements for the SSPCs in both electrical and thermal performances. In the proposed SSPC design investigation, SiC MOSFETs die are mounted on cast-aluminum traces, under which are an aluminum nitride (AlN) layer and an aluminum composite base plate. The concept of i2t and its application in solid state protection is discussed in detail. Transient thermal characterizations of SiC MOSFETs are provided for a nearly-all-aluminum package by Finite Element Analysis (FEA). The SSPC is targeted for 120A nominal, 1200A fault current, 270V DC system, and working at 105°C environment with a maximum 350°C transient junction temperature capability.

  3. The I-V Characteristic Prediction of BCD LV pMOSFET Devices Based on an ANFIS-Based Methodology

    Directory of Open Access Journals (Sweden)

    Shen-Li Chen

    2015-01-01

    Full Text Available Comprehensive and predictive modeling of submicron devices using the traditional TCAD EDA tools of device simulation has become increasingly perplexing due to a lack of reliable models and difficulties in calibrating available device models. This paper proposes a new technique to model BCD submicron pMOSFET devices and to predict device behaviors under different bias conditions and different geometry dimensions by using the adaptive neurofuzzy inference system (ANFIS, which combines fuzzy theory and adaptive neuronetworking. Here, the power of using ANFIS to realize the I-V behaviors is demonstrated in these p-channel MOS transistors. After a systematic evaluation, it can be found that the predicting results of I-V behaviors of complicated submicron pMOSFETs by ANFIS are compared with the actual diagnostic experiment data, and a good agreement has been obtained. Furthermore, the error percentage was no greater than 2.5%. As such, the demonstrated benefits of this new proposed technique include precise prediction and easier implementation.

  4. Two-dimensional threshold voltage model and design considerations for gate electrode work function engineered recessed channel nanoscale MOSFET: I

    International Nuclear Information System (INIS)

    Chaujar, Rishu; Kaur, Ravneet; Gupta, Mridula; Gupta, R S; Saxena, Manoj

    2009-01-01

    This paper discusses a threshold voltage model for novel device structure: gate electrode work function engineered recessed channel (GEWE-RC) nanoscale MOSFET, which combines the advantages of both RC and GEWE structures. In part I, the model accurately predicts (a) surface potential, (b) threshold voltage and (c) sub-threshold slope for single material gate recessed channel (SMG-RC) and GEWE-RC structures. Part II focuses on the development of compact analytical drain current model taking into account the transition regimes from sub-threshold to saturation. Furthermore, the drain conductance evaluation has also been obtained, reflecting relevance of the proposed device for analogue design. The analysis takes into account the effect of gate length and groove depth in order to develop a compact model suitable for device design. The analytical results predicted by the model confirm well with the simulated results. Results in part I also provide valuable design insights in the performance of nanoscale GEWE-RC MOSFET with optimum threshold voltage and negative junction depth (NJD), and hence serves as a tool to optimize important device and technological parameters for 40 nm technology

  5. Novel Indium Arsenide double gate and gate all around nanowire MOSFETs for diminishing the exchange correlation effect: A quantum study

    Science.gov (United States)

    Orouji, Ali A.; Nejaty, Mohammad; Mohtasham, Alireza

    2014-09-01

    In this paper we present novel double gate (DG) metal oxide semiconductor field effect transistor (MOSFET) and gate all around (GAA) nanowire metal oxide semiconductor field effect transistor (NWT) with a diminished exchange-correlation (Ex-Corr) effect. The key idea in this work is to use Indium Arsenide (InAs) semiconductor instead of Si. We have evaluated and compared different parameters of DG-MOSFET and GAA-NWTs such as threshold voltage, sub-threshold slope, drain induced barrier lowering and ON and OFF state currents from quantum view. Quantum mechanical transport approach based on non-equilibrium green's function (NEGF) has been performed in the frame work of effective mass theory in consideration with Ex-Corr effect. This simulation method consists of three dimensional Poisson's equation in which a Schrodinger equation is first solved in each slice of the device to find Eigen energies and Eigen functions. Then, a transport equation of electrons moving in the sub-bands is solved. This fully quantum method treats such effects as source-to-drain tunneling, ballistic transport, and quantum confinement on equal footing. The results show that only a few lowest Eigen sub-bands are occupied and the upper sub-bands can be safely neglected. Also, the interaction between electrons and Ex-Corr effect is diminished in the proposed structure.

  6. Simulation study of GaN n-MOSFETs by two-dimensional full band Monte Carlo approach

    International Nuclear Information System (INIS)

    Guo Baozeng; Guo Hui; Zhang Suoliang; Song Dengyuan

    2010-01-01

    Electrical properties of GaN n-MOSFET are presented by simulation study using the two-dimensional full band Monte Carlo approach. The band structure was calculated by the first-principle total-energy pseudopotential method within local-density-functional formalism. The various scatterings, such as polar optical scattering, impurity scattering, acoustic phonon scattering, and intervalley scattering, were included in the simulation. The vertical structure of the GaN n-MOSFET is Au/SiO 2 (50 nm)/GaN with the channel of 300 nm length. The simulation results showed that the device is normally off with a threshold voltage of about +3.0 V. I DS is about 4.96 A/cm at V DS =15 V and V GS =5 V. The maximum transconductance is about 0.44 S/cm at V GS =13.75 V and V DS =12 V. The maximum current gain cutoff frequency f T is about 86 GHz at V GS =8.75 V and I DS =2 A/cm.

  7. Impact of oxide thickness on SEGR failure in vertical power MOSFETs: Development of a semi-empirical expression

    International Nuclear Information System (INIS)

    Titus, J.L.; Wheatley, C.F.; Burton, D.I.; Mouret, I.; Allenspach, M.; Brews, J.; Schrimpf, R.; Galloway, K.; Pease, R.L.

    1995-01-01

    This paper investigates the role that the gate oxide thickness (T ox ) plays on the gate and drain failure threshold voltages required to induce the onset of single-event gate rupture (SEGR). The impact of gate oxide thickness on SEGR is experimentally determined from vertical power metal-oxide semiconductor field-effect transistors (MOSFETs) having identical process and design parameters, except for the gate oxide thickness. Power MOSFETs from five variants were specially fabricated with nominal gate oxide thicknesses of 30, 50, 70, 100, and 150 nm. Devices from each variant were characterized to mono-energetic ion beams of Nickel, Bromine, Iodine, and Gold, Employing different bias conditions, failure thresholds for the onset of SEGR were determined for each oxide thickness. Applying these experimental test results, the previously published empirical expression is extended to include the effects of gate oxide thickness. In addition, observations of ion angle, temperature, cell geometry, channel conductivity, and curvature at high drain voltages are briefly discussed

  8. Analytical modeling of subthreshold current and subthreshold swing of Gaussian-doped strained-Si-on-insulator MOSFETs

    International Nuclear Information System (INIS)

    Rawat, Gopal; Kumar, Sanjay; Goel, Ekta; Kumar, Mirgender; Jit, S.; Dubey, Sarvesh

    2014-01-01

    This paper presents the analytical modeling of subthreshold current and subthreshold swing of short-channel fully-depleted (FD) strained-Si-on-insulator (SSOI) MOSFETs having vertical Gaussian-like doping profile in the channel. The subthreshold current and subthreshold swing have been derived using the parabolic approximation method. In addition to the effect of strain on silicon layer, various other device parameters such as channel length (L), gate-oxide thickness (t ox ), strained-Si channel thickness (t s-Si ), peak doping concentration (N P ), project range (R p ) and straggle (σ p ) of the Gaussian profile have been considered while predicting the device characteristics. The present work may help to overcome the degradation in subthreshold characteristics with strain engineering. These subthreshold current and swing models provide valuable information for strained-Si MOSFET design. Accuracy of the proposed models is verified using the commercially available ATLAS™, a two-dimensional (2D) device simulator from SILVACO. (semiconductor devices)

  9. InGaAsP Mach-Zehnder interferometer optical modulator monolithically integrated with InGaAs driver MOSFET on a III-V CMOS photonics platform.

    Science.gov (United States)

    Park, Jin-Kown; Takagi, Shinichi; Takenaka, Mitsuru

    2018-02-19

    We demonstrated the monolithic integration of a carrier-injection InGaAsP Mach-Zehnder interferometer (MZI) optical modulator and InGaAs metal-oxide-semiconductor field-effect transistor (MOSFET) on a III-V-on-insulator (III-V-OI) wafer. A low-resistivity lateral PIN junction was formed along an InGaAsP rib waveguide by Zn diffusion and Ni-InGaAsP alloy, enabling direct driving of the InGaAsP optical modulator by the InGaAs MOSFET. A π phase shift of the InGaAsP optical modulator was obtained through the injection of a drain current from the InGaAs MOSFET with a gate voltage of approximately 1 V. This proof-of-concept demonstration of the monolithic integration of the InGaAsP optical modulator and InGaAs driver MOSFET will enable us to develop high-performance and low-power electronic-photonic integrated circuits on a III-V CMOS photonics platform.

  10. Design of a recessed-gate GaN-based MOSFET using a dual gate dielectric for high-power applications

    International Nuclear Information System (INIS)

    Yoon, Young Jun; Kang, Hee Sung; Seo, Jae Hwa; Kim, Young Jo; Bae, Jin Hyuk; Lee, Jung Hee; Kang, In Man; Cho, Eou Sik; Cho, Seong Jae

    2014-01-01

    We have investigated gallium-nitride (GaN)-based metal-oxide-semiconductor field-effect transistors(MOSFETs) having a recessed-gate structure for high-power applications. Recessed-gate GaN-based MOSFETs have been designed with a dual high-k dielectric structure to overcome low current drivability. Compared to recessed-gate GaN-based MOSFETs having a single gate dielectric with the same oxide thickness, recessed-gate GaN-based MOSFETs having a dual high-k dielectric composed of Al 2 O 3 and HfO 2 have achieved a high drain current (I D ) and transconductance (g m ) due to the high dielectric constant of HfO 2 . Also, because the dual high-k dielectric forms a high electron density in the channel layer with outstanding gate control capability, low channel resistances (R ch ) have obtained. In addition, we have studied the effect of the length between the gate and the drain (L gd ) on the on-resistance (R on ) to minimize the R on that is associated with power consumption and switching performance. Also, the electric field distribution of a device having a dual high-k dielectric has been examined with a field plate structure for high drive voltage. The proposed device was confirmed to be a remarkable candidate for switching devices in high-power applications.

  11. Cylindrical gate all around Schottky barrier MOSFET with insulated shallow extensions at source/drain for removal of ambipolarity: a novel approach

    Science.gov (United States)

    Kumar, Manoj; Pratap, Yogesh; Haldar, Subhasis; Gupta, Mridula; Gupta, R. S.

    2017-12-01

    In this paper TCAD-based simulation of a novel insulated shallow extension (ISE) cylindrical gate all around (CGAA) Schottky barrier (SB) MOSFET has been reported, to eliminate the suicidal ambipolar behavior (bias-dependent OFF state leakage current) of conventional SB-CGAA MOSFET by blocking the metal-induced gap states as well as unwanted charge sharing between source/channel and drain/channel regions. This novel structure offers low barrier height at the source and offers high ON-state current. The I ON/I OFF of ISE-CGAA-SB-MOSFET increases by 1177 times and offers steeper subthreshold slope (~60 mV/decade). However a little reduction in peak cut off frequency is observed and to further improve the cut-off frequency dual metal gate architecture has been employed and a comparative assessment of single metal gate, dual metal gate, single metal gate with ISE, and dual metal gate with ISE has been presented. The improved performance of Schottky barrier CGAA MOSFET by the incorporation of ISE makes it an attractive candidate for CMOS digital circuit design. The numerical simulation is performed using the ATLAS-3D device simulator.

  12. A Novel High Bandwidth Current Control Strategy for SiC mosfet Based Active Front-End Rectifiers Under Unbalanced Input Voltage Conditions

    DEFF Research Database (Denmark)

    Maheshwari, Ramkrishan; Trintis, Ionut; Török, Lajos

    2017-01-01

    SiC mosfet based converters are capable of high switching frequency operation. In this paper, the converter is operated with 50-kHz switching frequency for an active front-end rectifier application. Due to high switching frequency, the grid-side filter size is reduced, and the possibility of a high...

  13. Gate driver with high common mode rejection and self turn-on mitigation for a 10 kV SiC MOSFET enabled MV converter

    DEFF Research Database (Denmark)

    Dalal, Dipen Narendrabhai; Christensen, Nicklas; Jørgensen, Asger Bjørn

    2017-01-01

    This paper investigates gate driver design challenges encountered due to the fast switching transients in medium voltage half bridge silicon carbide MOSFET power modules. The paper presents, design of a reduced isolation capacitance regulated DC-DC power supply and a gate driver with an active...

  14. Development FD-SOI MOSFET Amplifiers for Integrated Read-Out Circuit of Superconducting-Tunnel-Junction Single-Photon-Detectors

    Energy Technology Data Exchange (ETDEWEB)

    Kiuchi, Kenji; et al.

    2015-07-27

    We proposed a new high-resolution single-photon infrared spectrometer for search for radiative decay of cosmic neutrino background (CνB). The superconducting-tunnel-junctions(STJs) are used as a single-photon counting device. Each STJ consists of Nb/Al/AlxOy/Al/Nb layers, and their thicknesses are optimized for the operation temperature at 370 mK cooled by a 3He sorption refrigerator. Our STJs achieved the leak current 250 pA, and the measured data implies that a smaller area STJ fulfills our requirement. FD-SOI MOSFETs are employed to amplify the STJ signal current in order to increase signal-to-noise ratio (S/N). FD-SOI MOSFETs can be operated at cryogenic temperature of 370 mK, which reduces the noise of the signal amplification system. FD-SOI MOSFET characteristics are measured at cryogenic temperature. The Id-Vgs curve shows a sharper turn on with a higher threshold voltage and the Id-Vds curve shows a nonlinear shape in linear region at cryogenic temperature. Taking into account these effects, FD-SOI MOSFETs are available for read-out circuit of STJ detectors. The bias voltage for STJ detectors is 0.4 mV, and it must be well stabilized to deliver high performance. We proposed an FD-SOI MOSFET-based charge integrated amplifier design as a read-out circuit of STJ detectors. The requirements for an operational amplifier used in the amplifier is estimated using SPICE simulation. The op-amp is required to have a fast response (GBW ≥ 100 MHz), and it must have low power dissipation as compared to the cooling power of refrigerator.

  15. Novel failure mechanism and improvement for split-gate trench MOSFET with large current under unclamped inductive switch stress

    Science.gov (United States)

    Tian, Ye; Yang, Zhuo; Xu, Zhiyuan; Liu, Siyang; Sun, Weifeng; Shi, Longxing; Zhu, Yuanzheng; Ye, Peng; Zhou, Jincheng

    2018-04-01

    In this paper, a novel failure mechanism under unclamped inductive switch (UIS) for Split-Gate Trench Metal Oxide Semiconductor Field Effect Transistor (MOSFET) with large current is investigated. The device sample is tested and analyzed in detail. The simulation results demonstrate that the nonuniform potential distribution of the source poly should be responsible for the failure. Three structures are proposed and verified available to improve the device UIS ruggedness by TCAD simulation. The best one of the structures the device with source metal inserting into source poly through contacts in the field oxide is carried out and measured. The results demonstrate that the optimized structure can balance the trade-off between the UIS ruggedness and the static characteristics.

  16. Application of semiconductor MOSFET and pin diode dosimeters to epithermal neutron beam dose distribution measurements in phantoms

    International Nuclear Information System (INIS)

    Carolan, M.G.; Wallace, S.A.; Allen, B.J.; Rosenfeld, A.B.; Mathur, J.N.

    1996-01-01

    For any clinical application of Boron Neutron Capture Therapy (BNCT) fast and accurate dose calculations will be required for treatment planning. Such calculations are also necessary for the planning and interpretation of results from pre-clinical and clinical trials where the speed of calculation is not so critical. A dose calculation system based on the MCNP Monte Carlo Neutron transport code has been developed by Wallace. This system takes image data from CT scans and constructs a voxel based geometrical model for input into MCNP. To validate the calculations, a number of phantoms were constructed and exposed in the HB11 epithermal neutron beam at the HFR of the CEC Joint Research Centre in Petten. The doses recorded by arrays of PIN diode neutron dosimeters and MOSFET gamma dosimeters in these phantoms were compared with the calculated results from the MCNP dose planning system. Initial results have been reported elsewhere. Poster 197. (author)

  17. Characteristics of MOSFETs fabricated in silicon-on-insulator material formed by high-dose oxygen ion implantation

    International Nuclear Information System (INIS)

    Lam, H.W.; Pinizzotto, R.F.; Yuan, H.T.; Bellavance, D.W.

    1981-01-01

    By implanting a dose of 6 x 10 17 cm -2 of 32 O 2 + at 300 keV into a silicon wafer, a buried oxide layer is formed. Crystallinity of the silicon layer above the buried oxide layer is maintained by applying a high (>200 0 C) substrate temperature during the ion implantation process. A two-step anneal cycle is found to be adequate to form the insulating buried oxide layer and to repair the implantation damage in the silicon layer on top of the buried oxide. A surface electron mobility as high as 710 cm 2 /Vs has been measured in n-channel MOSFETs fabricated in a 0.5 μm-thick epitaxial layer grown on the buried oxide wafer. A minimum subthreshold current of about 10 pA per micron of channel width at Vsub(DS)=2 V has been measured. (author)

  18. Experimental and 2D simulation study of the single-event burnout in n-channel power MOSFETs

    International Nuclear Information System (INIS)

    Roubaud, F.; Dachs, C.; Palau, J.M.; Gasiot, J.

    1993-01-01

    The use of the 2D simulator MEDICI as a tool for Single Event Burnout (SEB) comprehension is investigated. Simulation results are compared to experimental currents induced in an N channel power MOSFET by the ions from a 252 Cf source. Current measurements have been carried out with a specially designed circuit. Simulations allow to analyze separately the effects of the ion impact and of the electrical environment parameters on the SEB phenomenon. Burnout sensitivity is found to be increased by increasing supply voltage, ion's LET and by decreasing load charge. These electrical tendencies are validated by experiments. Burnout sensitivity is also found to be sensitive to the ion impact position. The current shapes variations for given electrical parameters can be related to LET or ion impact position changes. However, some experimental current shapes are not reproduced by simulations

  19. Dimensional effects and scalability of Meta-Stable Dip (MSD) memory effect for 1T-DRAM SOI MOSFETs

    Science.gov (United States)

    Hubert, A.; Bawedin, M.; Cristoloveanu, S.; Ernst, T.

    2009-12-01

    The difficult scaling of bulk Dynamic Random Access Memories (DRAMs) has led to various concepts of capacitor-less single-transistor (1T) architectures based on SOI transistor floating-body effects. Amongst them, the Meta-Stable Dip RAM (MSDRAM), which is a double-gate Fully Depleted SOI transistor, exhibits attractive performances. The Meta-Stable Dip effect results from the reduced junction leakage current and the long carrier generation lifetime in thin silicon film transistors. In this study, various devices with different gate lengths, widths and silicon film thicknesses have been systematically explored, revealing the impact of transistor dimensions on the MSD effect. These experimental results are discussed and validated by two-dimensional numerical simulations. It is found that MSD is maintained for small dimensions even in standard SOI MOSFETs, although specific optimizations are expected to enhance MSDRAM performances.

  20. TID and Displacement Damage Effects in Vertical and Lateral Power MOSFETs for Integrated DC-DC Converters

    CERN Document Server

    Faccio, F; Michelis, S; Faccio, Federico; Fuentes, C; Allongue, B; Sorge, R; Orlandi, S

    2010-01-01

    TID and displacement damage effects are studied for vertical and lateral power MOSFETs in five different technologies in view of the development of radiation-tolerant fully integrated DC-DC converters. Investigation is pushed to the very high level of radiation expected for an upgrade to the LHC experiments. TID induces threshold voltage shifts and, in n-channel transistors, source-drain leakage currents. Wide variability in the magnitude of these effects is observed. Displacement damage increases the on-resistance of both vertical and lateral high-voltage transistors. In the latter case, degradation at high particle fluence might lead to a distortion of the output characteristics curve. HBD techniques to limit or eliminate the radiation-induced leakage currents are successfully applied to these high-voltage transistors, but have to be used carefully to avoid consequences on the breakdown voltage.

  1. Analytical threshold voltage modeling of ion-implanted strained-Si double-material double-gate (DMDG) MOSFETs

    Science.gov (United States)

    Goel, Ekta; Singh, Balraj; Kumar, Sanjay; Singh, Kunal; Jit, Satyabrata

    2017-04-01

    Two dimensional threshold voltage model of ion-implanted strained-Si double-material double-gate MOSFETs has been done based on the solution of two dimensional Poisson's equation in the channel region using the parabolic approximation method. Novelty of the proposed device structure lies in the amalgamation of the advantages of both the strained-Si channel and double-material double-gate structure with a vertical Gaussian-like doping profile. The effects of different device parameters (such as device channel length, gate length ratios, germanium mole fraction) and doping parameters (such as projected range, straggle parameter) on threshold voltage of the proposed structure have been investigated. It is observed that the subthreshold performance of the device can be improved by simply controlling the doping parameters while maintaining other device parameters constant. The modeling results show a good agreement with the numerical simulation data obtained by using ATLAS™, a 2D device simulator from SILVACO.

  2. Hall effect mobility for SiC MOSFETs with increasing dose of nitrogen implantation into channel region

    Science.gov (United States)

    Noguchi, Munetaka; Iwamatsu, Toshiaki; Amishiro, Hiroyuki; Watanabe, Hiroshi; Kita, Koji; Yamakawa, Satoshi

    2018-04-01

    The Hall effect mobility (μHall) of the Si-face 4H-SiC metal–oxide–semiconductor field effect transistor (MOSFET) with a nitrogen (N)-implanted channel region was investigated by increasing the N dose. The μHall in the channel region was systematically examined regarding channel structures, that is, the surface and buried channels. It was experimentally demonstrated that increasing the N dose results in an improvement in μHall in the channel region due to the formation of the buried channel. However, further increase in N dose was found to decrease the μHall in the channel region, owing to the decrease in the electron mobility in the N-implanted bulk region.

  3. Controller design and implementation of a three-phase Active Front End using SiC based MOSFETs

    DEFF Research Database (Denmark)

    Haase, Frerk; Kouchaki, Alireza; Nymand, Morten

    2015-01-01

    The design and implementation of a three phase Active Front End for power factor correction purposes using fast switching SiC based MOSFETs is presented. Possible applications are within the drives- and renewable energy sector. The controller is designed and implemented in the synchronous rotating...... factor correction for an active rectifier in comparison to a passive rectifier. The SiC based power switches thereby offer the possibility of using high switching frequencies leading to a reduction in filter size - here a simple L filter. The controller is able to validate the simulation results...... reference frame. Besides the theoretical modelling the controller is optimized through simulations and implemented on a low cost DSP processor using a visual programming language - here MATLAB/SIMULINK - with automatic code generation for embedded targets. The paper illustrates the advantages of power...

  4. SiC MOSFET Based Single Phase Active Boost Rectifier with Power Factor Correction for Wireless Power Transfer Applications

    Energy Technology Data Exchange (ETDEWEB)

    Onar, Omer C [ORNL; Tang, Lixin [ORNL; Chinthavali, Madhu Sudhan [ORNL; Campbell, Steven L [ORNL; Miller (JNJ), John M. [JNJ-Miller PLC

    2014-01-01

    Wireless Power Transfer (WPT) technology is a novel research area in the charging technology that bridges the utility and the automotive industries. There are various solutions that are currently being evaluated by several research teams to find the most efficient way to manage the power flow from the grid to the vehicle energy storage system. There are different control parameters that can be utilized to compensate for the change in the impedance due to variable parameters such as battery state-of-charge, coupling factor, and coil misalignment. This paper presents the implementation of an active front-end rectifier on the grid side for power factor control and voltage boost capability for load power regulation. The proposed SiC MOSFET based single phase active front end rectifier with PFC resulted in >97% efficiency at 137mm air-gap and >95% efficiency at 160mm air-gap.

  5. Technical Evaluation of Radiation Dose Delivered in Prostate Cancer Patients as Measured by an Implantable MOSFET Dosimeter

    International Nuclear Information System (INIS)

    Beyer, Gloria P.; Scarantino, Charles W.; Prestidge, Bradley R.; Sadeghi, Amir G.; Anscher, Mitchell S.; Miften, Moyed; Carrea, Tammy B.; Sims, Marianne C.; Black, Robert D.

    2007-01-01

    Purpose: To perform a comparison of the daily measured dose at depth in tissue with the predicted dose values from treatment plans for 29 prostate cancer patients involved in a clinical trial. Methods and Materials: Patients from three clinical sites were implanted with one or two dosimeters in or near the prostatic capsule. The implantable device, known as the DVS, is based on a metal-oxide-semiconductor field effect transistor (MOSFET) detector. A portable telemetric readout system couples to the dosimeter antenna (visible on kilovoltage, computed tomography, and ultrasonography) for data transfer. The predicted dose values were determined by the location of the MOSFET on the treatment planning computed tomography scan. Serial computed tomography images were taken every 2 weeks to evaluate any migration of the device. The clinical protocol did not permit alteration of the treatment parameters using the dosimeter readings. For some patients, one of several image-guided radiotherapy (RT) modalities was used for target localization. Results: The evaluation of dose discrepancy showed that in many patients the standard deviation exceeded the previous values obtained for the dosimeter in a phantom. In some patients, the cumulative dose disagreed with the planned dose by ≥5%. The data presented suggest that an implantable dosimeter can help identify dose discrepancies (random or systematic) for patients treated with external beam RT and could be used as a daily treatment verification tool for image-guided RT and adaptive RT. Conclusion: The results of our study have shown that knowledge of the dose delivered per fraction can potentially prevent over- or under-dosage to the treatment area and increase the accuracy of RT. The implantable dosimeter could also be used as a localizer for image-guided RT

  6. Reliability characterization of SiON and MGHK MOSFETs using flicker noise and its correlation with the bias temperature instability

    Science.gov (United States)

    Samnakay, Rameez; Balandin, Alexander A.; Srinivasan, Purushothaman

    2017-09-01

    Bias temperature instability (BTI) is one of the critical device degradation mechanisms in poly-Si/SiON and metal gate/high-k complementary metal-oxide-semiconductor (CMOS) technologies. Using the pre- and post-BTI flicker noise measurements, we investigated the bulk trap density, Nt, in both of these technologies. The low-frequency noise spectra were predominantly of 1/fγ type with γ < 1 for NMOS and ∼1 for PMOS. For SiON based technologies, the lower VTH degradation due to PBTI was noticed while considerable VTH degradation was observed for NBTI in both SiON and MGHK technologies. Both MGHK and SiON pFETs show a clear increase in the effective volume trap density, Nt, after NBTI. The increase in Nt in MGHK n-MOSFETs during PBTI is markedly higher than that in MGHK p-MOSFETs during NBTI. From 2012-2016 he was a Research Assistant with the Nano-Device Laboratory at the University of California - Riverside, as well as a member of the Quality and Reliability engineering team at Globalfoundries, Inc. during the summer of 2014. He has currently authored or co-authored 10 journal publications and numerous conference presentations. His current research interests include 1/f noise in high-k dielectrics and fabricated 2D van der Waal thin-film devices Mr. Samnakay's awards and honors include the Dean's Distinguished Fellowship Award (University of California-Riverside) and induction into the IEEE-HKN honors society. He also serves as a reviewer for 6 journals including Applied Physics Letters, Journal of Physics: Condensed Matter and Nanotechnology journals.

  7. Loss analysis and optimum design of a highly efficient and compact CMOS DC–DC converter with novel transistor layout using 60 nm multipillar-type vertical body channel MOSFET

    Science.gov (United States)

    Itoh, Kazuki; Endoh, Tetsuo

    2018-04-01

    In this paper, we present a novel transistor layout of multi pillar-type vertical body-channel (BC) MOSFET for cascode power switches for improving the efficiency and compactness of CMOS DC–DC converters. The proposed layout features a stacked and multifingered layout to suppress the loss due to parasitic components such as diffusion resistance and contact resistance. In addition, the loss of each MOSFET, which configures cascode power switches, is analyzed, and it is revealed that the total optimum gate width and loss with the high-side (HS) n-type MOSFET topology are 27 and 16% smaller than those with the HS p-type MOSFET topology, respectively. Moreover, a circuit simulation of 2.0 to 0.8 V, 100 MHz CMOS DC–DC converters with the proposed layout is carried out by using experimentally extracted models of BSIM4 60 nm vertical BC MOSFETs. The peak efficiency of the HS n-type MOSFET converter with the proposed layout is 90.1%, which is 6.0% higher than that with the conventional layout.

  8. A reliable extraction method for source and drain series resistances in silicon nanowire metal-oxide-semiconductor field-effect-transistors (MOSFETs) based on radio-frequency analysis.

    Science.gov (United States)

    Hwa, Jae Hwa; Yoon, Young Jun; Lee, Hwan Gi; Yoo, Gwan Min; Cho, Eou-Sik; Cho, Seongjae; Lee, Jung-Hee; Kang, In Man

    2014-11-01

    This paper presents a new extraction method for source and drain (S/D) series resistances of silicon nanowire (SNW) metal-oxide-semiconductor field-effect transistors (MOSFETs) based on small-signal radio-frequency (RF) analysis. The proposed method can be applied to the extraction of S/D series resistances for SNW MOSFETs with finite off-state channel resistance as well as gate bias-dependent on-state resistive components realized by 3-dimensional (3-D) device simulation. The series resistances as a function of frequency and gate voltage are presented and compared with the results obtained by an existing method with infinite off-state channel resistance model. The accuracy of the newly proposed parameter extraction method has been successfully verified by Z22- and Y-parameters up to 100 GHz operation frequency.

  9. Optimization of the Al2O3/GaSb Interface and a High-Mobility GaSb pMOSFET

    Science.gov (United States)

    2011-10-01

    achieved. This enabled pMOSFETs with a peak hole mobility value of 290 cm2/Vs. 15. SUBJECT TERMS Atomic layer deposition (ALD), gallium antimonide , hole...drain technology with high density of activated carriers, low defects, and low contact resistance. Ion implantation in antimonides has traditionally been...clean, Al2O3 was deposited at 300 ◦C by ALD using trimethyl aluminum (TMA) and water as the precursors with TMA being the starting pulse for the ALD

  10. Design of low impedance busbar for 10 kV, 100A 4H-SiC MOSFET short-circuit tester using axial capacitors

    DEFF Research Database (Denmark)

    Eni, Emanuel-Petre; Kerekes, Tamas; Uhrenfeldt, Christian

    2015-01-01

    rated for 10 kV on the market, the package design of CREE 10 kV 10 A 4H-SiC MOSFETs and the required space for the device heater. Ansys Q3D is used in order to extract the parasitic components from the design. Custom designed aluminum cans for 15 kV axial capacitors are used in order to minimize...

  11. Enhanced Device and Circuit-Level Performance Benchmarking of Graphene Nanoribbon Field-Effect Transistor against a Nano-MOSFET with Interconnects

    Directory of Open Access Journals (Sweden)

    Huei Chaeng Chin

    2014-01-01

    Full Text Available Comparative benchmarking of a graphene nanoribbon field-effect transistor (GNRFET and a nanoscale metal-oxide-semiconductor field-effect transistor (nano-MOSFET for applications in ultralarge-scale integration (ULSI is reported. GNRFET is found to be distinctly superior in the circuit-level architecture. The remarkable transport properties of GNR propel it into an alternative technology to circumvent the limitations imposed by the silicon-based electronics. Budding GNRFET, using the circuit-level modeling software SPICE, exhibits enriched performance for digital logic gates in 16 nm process technology. The assessment of these performance metrics includes energy-delay product (EDP and power-delay product (PDP of inverter and NOR and NAND gates, forming the building blocks for ULSI. The evaluation of EDP and PDP is carried out for an interconnect length that ranges up to 100 μm. An analysis, based on the drain and gate current-voltage (Id-Vd and Id-Vg, for subthreshold swing (SS, drain-induced barrier lowering (DIBL, and current on/off ratio for circuit implementation is given. GNRFET can overcome the short-channel effects that are prevalent in sub-100 nm Si MOSFET. GNRFET provides reduced EDP and PDP one order of magnitude that is lower than that of a MOSFET. Even though the GNRFET is energy efficient, the circuit performance of the device is limited by the interconnect capacitances.

  12. Cross-point-type spin-transfer-torque magnetoresistive random access memory cell with multi-pillar vertical body channel MOSFET

    Science.gov (United States)

    Sasaki, Taro; Endoh, Tetsuo

    2018-04-01

    In this paper, from the viewpoint of cell size and sensing margin, the impact of a novel cross-point-type one transistor and one magnetic tunnel junction (1T–1MTJ) spin-transfer-torque magnetoresistive random access memory (STT-MRAM) cell with a multi-pillar vertical body channel (BC) MOSFET is shown for high density and wide sensing margin STT-MRAM, with a 10 ns writing period and 1.2 V V DD. For that purpose, all combinations of n/p-type MOSFETs and bottom/top-pin MTJs are compared, where the diameter of MTJ (D MTJ) is scaled down from 55 to 15 nm and the tunnel magnetoresistance (TMR) ratio is increased from 100 to 200%. The results show that, benefiting from the proposed STT-MRAM cell with no back bias effect, the MTJ with a high TMR ratio (200%) can be used in the design of smaller STT-MRAM cells (over 72.6% cell size reduction), which is a difficult task for conventional planar MOSFET based design.

  13. Versatile Tunable Current-Mode Universal Biquadratic Filter Using MO-DVCCs and MOSFET-Based Electronic Resistors

    Directory of Open Access Journals (Sweden)

    Hua-Pin Chen

    2014-01-01

    Full Text Available This paper presents a versatile tunable current-mode universal biquadratic filter with four-input and three-output employing only two multioutput differential voltage current conveyors (MO-DVCCs, two grounded capacitors, and a well-known method for replacement of three grounded resistors by MOSFET-based electronic resistors. The proposed configuration exhibits high-output impedance which is important for easy cascading in the current-mode operations. The proposed circuit can be used as either a two-input three-output circuit or a three-input single-output circuit. In the operation of two-input three-output circuit, the bandpass, highpass, and bandreject filtering responses can be realized simultaneously while the allpass filtering response can be easily obtained by connecting appropriated output current directly without using additional stages. In the operation of three-input single-output circuit, all five generic filtering functions can be easily realized by selecting different three-input current signals. The filter permits orthogonal controllability of the quality factor and resonance angular frequency, and no inverting-type input current signals are imposed. All the passive and active sensitivities are low. Postlayout simulations were carried out to verify the functionality of the design.

  14. Normally-off Al2O3/GaN MOSFET: Role of border traps on the device transport characteristics

    Science.gov (United States)

    Wang, Hongyue; Wang, Jinyan; Liu, Jingqian; He, Yandong; Wang, Maojun; Yu, Min; Wu, Wengang

    2018-03-01

    Based on the self-terminating gate recess technique, two different processes featuring gate-recess-first (GF) and ohmic-contact-first (OF) were proposed for E-mode Al2O3/GaN MOSFETs. Increased maximum drain current (Idmax) ∼30% (420 vs 325 mA/mm), field-effect mobility (μFEmax) ∼67% (150 vs 90 cm2/Vs) and reduced on-state resistance (Ron) ∼42% (9.7 vs 16.8 Ω·mm) were observed in the devices fabricated by GF process. Such significant performance difference of GF- and OF-devices resulted from the presence of border traps at Al2O3/GaN interface with a time constant ∼7 × 10-6 s. Experimental results indicated that: (1) the near interface border traps in Al2O3 dielectric significantly affect device channel mobility; (2) a high temperature post-deposition annealing process could effective suppress generation of border traps.

  15. Versatile tunable current-mode universal biquadratic filter using MO-DVCCs and MOSFET-based electronic resistors.

    Science.gov (United States)

    Chen, Hua-Pin

    2014-01-01

    This paper presents a versatile tunable current-mode universal biquadratic filter with four-input and three-output employing only two multioutput differential voltage current conveyors (MO-DVCCs), two grounded capacitors, and a well-known method for replacement of three grounded resistors by MOSFET-based electronic resistors. The proposed configuration exhibits high-output impedance which is important for easy cascading in the current-mode operations. The proposed circuit can be used as either a two-input three-output circuit or a three-input single-output circuit. In the operation of two-input three-output circuit, the bandpass, highpass, and bandreject filtering responses can be realized simultaneously while the allpass filtering response can be easily obtained by connecting appropriated output current directly without using additional stages. In the operation of three-input single-output circuit, all five generic filtering functions can be easily realized by selecting different three-input current signals. The filter permits orthogonal controllability of the quality factor and resonance angular frequency, and no inverting-type input current signals are imposed. All the passive and active sensitivities are low. Postlayout simulations were carried out to verify the functionality of the design.

  16. Improved generation lifetime model for the electrical characterization of single- and double-gate SOI nMOSFETs

    International Nuclear Information System (INIS)

    Galeti, M; Martino, J A; Simoen, E; Claeys, C

    2008-01-01

    This work proposes a refined technique for the extraction of the generation lifetime in single- and double-gate partially depleted SOI nMOSFETs. The model presented in this paper, based on the drain current switch-off transients, takes into account the influence of the laterally non-uniform channel doping, caused by the presence of the halo implanted region, and the amount of charge controlled by the drain and source junctions on the floating body effect when the channel length is reduced. The obtained results for single-gate (SG) devices are compared with two-dimensional numerical simulations and experimental data, extracted for devices fabricated in a 0.1 µm SOI CMOS technology, showing excellent agreement. The improved model to determine the generation lifetime in double-gate (DG) devices beyond the considerations previously presented also consider the influence of the silicon layer thickness on the drain current transient. The extracted data through the improved model for DG devices were compared with measurements and two-dimensional numerical simulations of the SG devices also presenting a good adjustment with the channel length reduction and the same tendency with the silicon layer thickness variation

  17. An asymmetric MOSFET-C band-pass filter with on-chip charge pump auto-tuning

    International Nuclear Information System (INIS)

    Chen Fangxiong; Ma Heping; Jia Hailong; Shi Yin; Lin Min; Dai, Forster

    2009-01-01

    An asymmetric MOSFET-C band-pass filter (BPF) with on chip charge pump auto-tuning is presented. It is implemented in UMC (United Manufacturing Corporation) 0.18 μm CMOS process technology. The filter system with auto-tuning uses a master-slave technique for continuous tuning in which the charge pump outputs 2.663 V, much higher than the power supply voltage, to improve the linearity of the filter. The main filter with third order low-pass and second order high-pass properties is an asymmetric band-pass filter with bandwidth of 2.730-5.340 MHz. The in-band third order harmonic input intercept point (IIP3) is 16.621 dBm, with 50 Ω as the source impedance. The input referred noise is about 47.455 μV rms . The main filter dissipates 3.528 mW while the auto-tuning system dissipates 2.412 mW from a 1.8 V power supply. The filter with the auto-tuning system occupies 0.592 mm 2 and it can be utilized in GPS (global positioning system) and Bluetooth systems. (semiconductor integrated circuits)

  18. Fabrication and characterization of Pt/Al2O3/Y2O3/In0.53Ga0.47As MOSFETs with low interface trap density

    Science.gov (United States)

    Kim, Seong Kwang; Geum, Dae-Myeong; Shim, Jae-Phil; Kim, Chang Zoo; Kim, Hyung-jun; Song, Jin Dong; Choi, Won Jun; Choi, Sung-Jin; Kim, Dae Hwan; Kim, Sanghyeon; Kim, Dong Myong

    2017-01-01

    In this work, we fabricated the In0.53Ga0.47As metal-oxide-semiconductor field-effect-transistors (MOSFETs) with a MOS interface of Y2O3/In0.53Ga0.47As and recessed gate structure. We investigated the interfacial properties of the gate stack and the junction characteristics of the fabricated MOSFETs. Low subthreshold slope (SS = 110 mV/dec), high on/off current ratio (Ion/Ioff = 106), and high effective mobility of 1600 cm2/V.s were achieved in the MOSFETs at a sheet charge density (Ns) = 1.2 × 1012 cm-2. From the temperature dependence of I-V characteristics, the interface trap density was extracted to be Dit = 2.2 × 1011 cm-2.eV-1 with a negligible trap-assisted leakage current.

  19. Fabrication of a novel RF switch device with high performance using In0.4Ga0.6As MOSFET technology

    Science.gov (United States)

    Jiahui, Zhou; Hudong, Chang; Xufang, Zhang; Jingzhi, Yang; Guiming, Liu; Haiou, Li; Honggang, Liu

    2016-02-01

    A novel radio frequency (RF) switch device has been successfully fabricated using InGaAs metal-oxide-semiconductor field-effect transistor (MOSFET) technology. The device showed drain saturation currents of 250 mA/mm, a maximum transconductance of 370 mS/mm, a turn-on resistance of 0.72 mω·mm2 and a drain current on-off (Ion/Ioff) ratio of 1 × 106. The maximum handling power of on-state of 533 mW/mm and off-state of 3667 mW/mm is obtained. The proposed In0.4Ga0.6 As MOSFET RF switch showed an insertion loss of less than 1.8 dB and an isolation of better than 20 dB in the frequency range from 0.1 to 7.5 GHz. The lowest insertion loss and the highest isolation can reach 0.27 dB and more than 68 dB respectively. This study demonstrates that the InGaAs MOSFET technology has a great potential for RF switch application. Project supported by the National Natural Science Foundation of China (Nos. 61274077, 61474031), the Guangxi Natural Science Foundation (No. 2013GXNSFGA019003), the Guangxi Department of Education Project (No. 201202ZD041), the Guilin City Technology Bureau (Nos. 20120104-8, 20130107-4), the China Postdoctoral Science Foundation Funded Project (Nos. 2012M521127, 2013T60566), the National Basic Research Program of China (Nos. 2011CBA00605, 2010CB327501), the Innovation Project of GUET Graduate Education (Nos. GDYCSZ201448, GDYCSZ201449), the State key Laboratory of Electronic Thin Films and Integrated Devices, UESTC (No. KFJJ201205), and the Guilin City Science and Technology Development Project (Nos. 20130107-4, 20120104-8).

  20. Dynamics of loops: asymptotic freedom and quark confinement

    International Nuclear Information System (INIS)

    Makeenko, Yu.M.; Migdal, A.A.

    1980-01-01

    New manifestly gauge invariant diagram technique in the loop space is developed. For that purpose a boot-strap ' equation, determining the self-consistent asymptotics, is solved in the framework of the perturbation theory. The boot-strap equation is equivalent to the system including the Bianchi identity and the planar equation accompanied by Euclidean boundary conditions. It is shown that the area law of quark confinement is a self-consistent solution of the boot-strap equation. The frame diagrams constructed by means of certain operator technique reproduce asymptotic freedom in the ultraviolet range

  1. SU-G-IeP3-02: Characteristics of In-Vivo MOSFET Dosimeters for Diagnostic X-Ray Low-Dose Measurements

    Energy Technology Data Exchange (ETDEWEB)

    Li, S; Ali, S; Harper, K; Liang, Q; Serratore, D [Temple University Hospital, Philadelphia, PA (United States)

    2016-06-15

    Purpose: To correct in-vivo metal-oxide-semiconductor field-effect transistor (MOSFET) dosimeters dependence on X-ray energy, dose and dose rate, and temperature in order to measure doses or exposures on several anatomic points of interest undergoing some routine radiographs. Methods: A mobile MOSFET system (BEST Medical) was carefully calibrated with X-ray at kVp of 70, 80, 100, 120, and 138 kVp, phantom temperatures at 0, 21, and 43 oC, and exposure range from 0.01 to 10 R confirmed with Raysafe and RadCal dosimeters. The MOSFETS were placed on the midline bladder or uterus, left pelvic iliac artery, left abdominal above iliac crest, abdominal midline anterior at inferior margin of stomach, and left pectoral of a large and a small body-size cadavers undergoing AP/PA chest and lumber spine radiographs using manual and automatic exposure control (AEC) with and without lead shielding. MOSTFETs and TLD chips were also placed on the stomach, sigmoid, pubic symphysis, left and right pelvic walls of another cadaver for AP pelvic manual or AEC radiography prior to and after a left hip metal implant. Results: Individual MOSFET detectors had various low-dose limits in ranged from 0.03 to 0.08 R, nonlinear response to X-ray energy, and significant temperature effect of 15%. By accumulating 10 manual exposures and 20 AEC exposures, we achieved dose measured accuracy of 6%. There were up to 8 fold increases for AEC exposure of spine and chest X-ray procedure from no shielding to with shielding. For pelvic radiography, exposure to public symphysis was the highest even higher than that of the skin. After hip implant, AEC pelvic radiograph increase exposure by 30 to 200% consistent with results of TLDs. Conclusion: Dependence of energy, temperature and dose limit were accurately corrected. We have found significant exposure for those clinical pr°ocedures and the study provided evidences for developing new clinical procedures.

  2. Impact of Total Ionizing Dose Radiation Testing and Long-Term Thermal Cycling on the Operation of CMF20120D Silicon Carbide Power MOSFET

    Science.gov (United States)

    Patterson, Richard L.; Scheidegger, Robert J.; Lauenstein, Jean-Marie; Casey, Megan; Scheick, Leif; Hammoud, Ahmad

    2013-01-01

    Power systems designed for use in NASA space missions are required to work reliably under harsh conditions including radiation, thermal cycling, and extreme temperature exposures. Silicon carbide devices show great promise for use in future power electronics systems, but information pertaining to performance of the devices in the space environment is very scarce. A silicon carbide N-channel enhancement-mode power MOSFET called the CMF20120 is of interest for use in space environments. Samples of the device were exposed to radiation followed by long-term thermal cycling to address their reliability for use in space applications. The results of the experimental work are presentd and discussed.

  3. On-current modeling of short-channel double-gate (DG) MOSFETs with a vertical Gaussian-like doping profile

    International Nuclear Information System (INIS)

    Dubey, Sarvesh; Jit, S.; Tiwari Pramod Kumar

    2013-01-01

    An analytic drain current model is presented for doped short-channel double-gate MOSFETs with a Gaussian-like doping profile in the vertical direction of the channel. The present model is valid in linear and saturation regions of device operation. The drain current variation with various device parameters has been demonstrated. The model is made more physical by incorporating the channel length modulation effect. Parameters like transconductance and drain conductance that are important in assessing the analog performance of the device have also been formulated. The model results are validated by numerical simulation results obtained by using the commercially available ATLAS™, a two dimensional device simulator from SILVACO. (semiconductor devices)

  4. 2-D modeling and analysis of short-channel behavior of a front high- K gate stack triple-material gate SB SON MOSFET

    Science.gov (United States)

    Banerjee, Pritha; Kumari, Tripty; Sarkar, Subir Kumar

    2018-02-01

    This paper presents the 2-D analytical modeling of a front high- K gate stack triple-material gate Schottky Barrier Silicon-On-Nothing MOSFET. Using the two-dimensional Poisson's equation and considering the popular parabolic potential approximation, expression for surface potential as well as the electric field has been considered. In addition, the response of the proposed device towards aggressive downscaling, that is, its extent of immunity towards the different short-channel effects, has also been considered in this work. The analytical results obtained have been validated using the simulated results obtained using ATLAS, a two-dimensional device simulator from SILVACO.

  5. 2-D analytical modeling of subthreshold current and subthreshold swing for ion-implanted strained-Si double-material double-gate (DMDG) MOSFETs

    Science.gov (United States)

    Goel, Ekta; Singh, Kunal; Singh, Balraj; Kumar, Sanjay; Jit, Satyabrata

    2017-09-01

    In this paper, the subthreshold behavior of ion-implanted strained-Si double-material double-gate (DMDG) MOSFETs has been analyzed by means of subthreshold current and subthreshold swing. The surface potential based formulation of subthreshold current and subthreshold swing is done by solving the 2-D Poisson's equations in the channel region using parabolic approximation method. The dependence of subthreshold characteristics on various device parameters such as gate length ratio, Ge mole fraction, peak doping concentration, projected range, straggle parameter etc. has been studied. The modeling results are found to be well matched with the simulation data obtained by a 2-D device simulator, ATLAS™, from SILVACO.

  6. Total ionizing dose (TID) effect and single event effect (SEE) in quasi-SOI nMOSFETs

    International Nuclear Information System (INIS)

    Tan, Fei; Huang, Ru; An, Xia; Wu, Weikang; Feng, Hui; Huang, Liangxi; Fan, Jiewen; Zhang, Xing; Wang, Yangyuan

    2014-01-01

    This paper studies the total ionizing dose (TID) and single event effect (SEE) in quasi-SOI nMOSFETs for the first time. After exposure to gamma rays, the off-state leakage current (I off ) of a quasi-SOI device increases with the accumulating TID, and the on-state bias configuration is shown to be the worst-case bias configuration during irradiation. Although an additional TID-sensitive region is introduced by the unique structure of the quasi-SOI device, the influence of positive charge trapped in L-type oxide layers on the degradation of device performance is neglectable. Since the TID-induced leakage path in the quasi-SOI device is greatly reduced due to the isolation of L-type oxide layers, the TID-induced I off  degradation in the quasi-SOI device is greatly suppressed. In addition, 3D simulation is performed to investigate the SEE of the quasi-SOI device. The full-width at half-maximum (FWHM) of worst-case drain current transient and collected charges of the quasi-SOI device after single-ion-striking is smaller than in a bulk Si device, indicating that the quasi-SOI device inherits the advantage of an SOI device in single event transient immunity. Therefore, the quasi-SOI device, which has improved electrical properties and radiation-hardened characteristics for both TID and SEE, can be considered as one of the promising candidates for space applications. (paper)

  7. Ohmic contact on n- and p-type ion-implanted 4H-SiC with low-temperature metallization process for SiC MOSFETs

    Science.gov (United States)

    Shimizu, Haruka; Shima, Akio; Shimamoto, Yasuhiro; Iwamuro, Noriyuki

    2017-04-01

    The ohmic contact on n- and p-type SiC regions with the same contact metal is a key process in regard to creating high-performance MOSFETs and insulated gate bipolar transistors (IGBTs). The dependence of the contact resistance on n- and p-type SiC regions on ion species, dose, and implantation temperature was investigated. The results of such an investigation revealed that the amorphization of the SiC surface and the generation of 3C-SiC produce a low contact resistance without the need for a high-temperature metallization process. The contact resistances of 2.1 × 10-6 Ω cm2 on the n-type SiC region and 1.3 × 10-3 Ω cm2 on the p-type SiC region were obtained with high-dose ion implantation at room temperature on the n-type SiC region, high-dose ion implantation at high temperature on the p-type SiC region, and a titanium-based contact electrode. A SiC MOSFET was fabricated with the low-temperature ohmic contact process. The positive-bias gate leakage current markedly increased. It can be deduced that high-dose ion implantation at room temperature on the n-type SiC region degrades surface roughness on the N+ source region.

  8. High fluence swift heavy ion structure modification of the SiO{sub 2}/Si interface and gate insulator in 65 nm MOSFETs

    Energy Technology Data Exchange (ETDEWEB)

    Ma, Yao [Key Laboratory of Radiation Physics and Technology of Ministry of Education, Sichuan University, Chengdu 610064 (China); Key Lab of Microelectronics Sichuan Province, Sichuan University, Chengdu, Sichuan 610064 (China); College of Physical Science and Technology, Sichuan University, Chengdu, Sichuan 610064 (China); Gao, Bo, E-mail: gaobo@scu.edu.cn [Key Laboratory of Radiation Physics and Technology of Ministry of Education, Sichuan University, Chengdu 610064 (China); Key Lab of Microelectronics Sichuan Province, Sichuan University, Chengdu, Sichuan 610064 (China); College of Physical Science and Technology, Sichuan University, Chengdu, Sichuan 610064 (China); Gong, Min [Key Laboratory of Radiation Physics and Technology of Ministry of Education, Sichuan University, Chengdu 610064 (China); Key Lab of Microelectronics Sichuan Province, Sichuan University, Chengdu, Sichuan 610064 (China); College of Physical Science and Technology, Sichuan University, Chengdu, Sichuan 610064 (China); Willis, Maureen [College of Physical Science and Technology, Sichuan University, Chengdu, Sichuan 610064 (China); Yang, Zhimei [Key Laboratory of Radiation Physics and Technology of Ministry of Education, Sichuan University, Chengdu 610064 (China); Key Lab of Microelectronics Sichuan Province, Sichuan University, Chengdu, Sichuan 610064 (China); Guan, Mingyue [College of Physical Science and Technology, Sichuan University, Chengdu, Sichuan 610064 (China); Li, Yun [Key Laboratory of Radiation Physics and Technology of Ministry of Education, Sichuan University, Chengdu 610064 (China); Key Lab of Microelectronics Sichuan Province, Sichuan University, Chengdu, Sichuan 610064 (China); College of Physical Science and Technology, Sichuan University, Chengdu, Sichuan 610064 (China)

    2017-04-01

    In this work, a study of the structure modification, induced by high fluence swift heavy ion radiation, of the SiO{sub 2}/Si structures and gate oxide interface in commercial 65 nm MOSFETs is performed. A key and novel point in this study is the specific use of the transmission electron microscopy (TEM) technique instead of the conventional atomic force microscope (AFM) or scanning electron microscope (SEM) techniques which are typically performed following the chemical etching of the sample to observe the changes in the structure. Using this method we show that after radiation, the appearance of a clearly visible thin layer between the SiO{sub 2} and Si is observed presenting as a variation in the TEM intensity at the interface of the two materials. Through measuring the EDX line scans we reveal that the Si:O ratio changed and that this change can be attributed to the migration of the Si towards interface after the Si-O bond is destroyed by the swift heavy ions. For the 65 nm MOSFET sample, the silicon substrate, the SiON insulator and the poly-silicon gate interfaces become blurred under the same irradiation conditions.

  9. Chemical vapor deposited monolayer MoS2 top-gate MOSFET with atomic-layer-deposited ZrO2 as gate dielectric

    Science.gov (United States)

    Hu, Yaoqiao; Jiang, Huaxing; Lau, Kei May; Li, Qiang

    2018-04-01

    For the first time, ZrO2 dielectric deposition on pristine monolayer MoS2 by atomic layer deposition (ALD) is demonstrated and ZrO2/MoS2 top-gate MOSFETs have been fabricated. ALD ZrO2 overcoat, like other high-k oxides such as HfO2 and Al2O3, was shown to enhance the MoS2 channel mobility. As a result, an on/off current ratio of over 107, a subthreshold slope of 276 mV dec-1, and a field-effect electron mobility of 12.1 cm2 V-1 s-1 have been achieved. The maximum drain current of the MOSFET with a top-gate length of 4 μm and a source/drain spacing of 9 μm is measured to be 1.4 μA μm-1 at V DS = 5 V. The gate leakage current is below 10-2 A cm-2 under a gate bias of 10 V. A high dielectric breakdown field of 4.9 MV cm-1 is obtained. Gate hysteresis and frequency-dependent capacitance-voltage measurements were also performed to characterize the ZrO2/MoS2 interface quality, which yielded an interface state density of ˜3 × 1012 cm-2 eV-1.

  10. Analysis of Low Dimensional Nanoscaled Inversion-Mode InGaAs MOSFETs for Next-Generation Electrical and Photonic Applications

    Directory of Open Access Journals (Sweden)

    C. H. Yu

    2015-01-01

    Full Text Available The electrical characteristics of In0.53Ga0.47As MOSFET grown with Si interface passivation layer (IPL and high k gate oxide HfO2 layer have been investigated in detail. The influences of Si IPL thickness, gate oxide HfO2 thickness, the doping depth, and concentration of source and drain layer on output and transfer characteristics of the MOSFET at fixed gate or drain voltages have been individually simulated and analyzed. The determination of the above parameters is suggested based on their effect on maximum drain current, leakage current, saturated voltage, and so forth. It is found that the channel length decreases with the increase of the maximum drain current and leakage current simultaneously. Short channel effects start to appear when the channel length is less than 0.9 μm and experience sudden sharp increases which make device performance degrade and reach their operating limits when the channel length is further lessened down to 0.5 μm. The results demonstrate the usefulness of short channel simulations for designs and optimization of next-generation electrical and photonic devices.

  11. Properties of slow traps of ALD Al2O3/GeOx/Ge nMOSFETs with plasma post oxidation

    Science.gov (United States)

    Ke, M.; Yu, X.; Chang, C.; Takenaka, M.; Takagi, S.

    2016-07-01

    The realization of Ge gate stacks with a small amount of slow trap density as well as thin equivalent oxide thickness and low interface state density (Dit) is a crucial issue for Ge CMOS. In this study, we examine the properties of slow traps, particularly the location of slow traps, of Al2O3/GeOx/n-Ge and HfO2/Al2O3/GeOx/n-Ge MOS interfaces with changing the process and structural parameters, formed by atomic layer deposition (ALD) of Al2O3 and HfO2/Al2O3 combined with plasma post oxidation. It is found that the slow traps can locate in the GeOx interfacial layer, not in the ALD Al2O3 layer. Furthermore, we study the time dependence of channel currents in the Ge n-MOSFETs with 5-nm-thick Al2O3/GeOx/Ge gate stacks, with changing the thickness of GeOx, in order to further clarify the position of slow traps. The time dependence of the current drift and the effective time constant of slow traps do not change among the MOSFETs with the different thickness GeOx, demonstrating that the slow traps mainly exist near the interfaces between Ge and GeOx.

  12. A new DG nanoscale TFET based on MOSFETs by using source gate electrode: 2D simulation and an analytical potential model

    Science.gov (United States)

    Ramezani, Zeinab; Orouji, Ali A.

    2017-08-01

    This paper suggests and investigates a double-gate (DG) MOSFET, which emulates tunnel field effect transistors (M-TFET). We have combined this novel concept into a double-gate MOSFET, which behaves as a tunneling field effect transistor by work function engineering. In the proposed structure, in addition to the main gate, we utilize another gate over the source region with zero applied voltage and a proper work function to convert the source region from N+ to P+. We check the impact obtained by varying the source gate work function and source doping on the device parameters. The simulation results of the M-TFET indicate that it is a suitable case for a switching performance. Also, we present a two-dimensional analytic potential model of the proposed structure by solving the Poisson's equation in x and y directions and by derivatives from the potential profile; thus, the electric field is achieved. To validate our present model, we use the SILVACO ATLAS device simulator. The analytical results have been compared with it.

  13. Modeling and Control of a Dual-Input Isolated Full-Bridge Boost Converter

    DEFF Research Database (Denmark)

    Zhang, Zhe; Thomsen, Ole Cornelius; Andersen, Michael A. E.

    2012-01-01

    In this paper, a steady-state model, a large-signal (LS) model and an ac small-signal (SS) model for a recently proposed dual-input transformer-isolated boost converter are derived respectively by the switching flow-graph (SFG) nonlinear modeling technique. Based upon the converter’s model, the c....... The measured experimental results match the simulation results fairly well on both input source dynamic and step load transient responses....

  14. A soft switching with reduced voltage stress ZVT-PWM full-bridge converter

    Science.gov (United States)

    Sahin, Yakup; Ting, Naim Suleyman; Acar, Fatih

    2018-04-01

    This paper introduces a novel active snubber cell for soft switching pulse width modulation DC-DC converters. In the proposed converter, the main switch is turned on under zero voltage transition and turned off under zero voltage switching (ZVS). The auxiliary switch is turned on under zero current switching (ZCS) and turned off under zero current transition. The main diode is turned on under ZVS and turned off under ZCS. All of the other semiconductors in the converter are turned on and off with soft switching. There is no extra voltage stress on the semiconductor devices. Besides, the proposed converter has simple structure and ease of control due to common ground. The detailed theoretical analysis of the proposed converter is presented and also verified with both simulation and experimental study at 100 kHz switching frequency and 600 W output power. Furthermore, the efficiency of the proposed converter is 95.7% at nominal power.

  15. Simplified loss analysis and comparison of full-bridge, full-range ...

    Indian Academy of Sciences (India)

    ferred topology for high power dc–dc converters due to fixed switching frequency, ZVS oper- ation, high efficiency, low circulating reactive ... nal snubber capacitor is connected to reduce the rate of rise of voltage and turn-off losses. Therefore, in high-power .... ratio and are decided by the design. The expressions for various ...

  16. Simplified loss analysis and comparison of full-bridge, full-range ...

    Indian Academy of Sciences (India)

    ferred topology for high power dc–dc converters due to fixed switching frequency, ZVS oper- ation, high efficiency, low ... (c) The average power loss in an IGBT and a diode is proportional to the average current flowing through ... For lower values of duty cycle this transition will be hard switched causing switching losses. is1 ...

  17. Variation in the electrical properties of 100 V/100 A rated mesh and stripe TDMOSFETs (trench double-diffused MOSFETs) for motor drive applications

    International Nuclear Information System (INIS)

    Na, Kyoung-Il; Kah, Dong-Ha; Kim, Sang-Gi; Koo, Jin-Gun; Kim, Jong-Dae; Yang, Yil-Suk; Lee, Jin-Ho

    2012-01-01

    The vertical power metal-oxide semiconductor field-effect transistors (MOSFETs) with deep trench structures are the most promising candidates to overcome the trade-off relationship between the ON-resistance (R ON ) and the blocking voltage (BV DS ). Especially, 100 V/100 A rated trench power MOSFETs are used in components of many power systems, such as motors and LED lighting drive ICs, DC-DC converters in electric vehicles, and so on. In this work, we studied variations of the electrical characteristics, such as threshold voltage (V TH ), BV DS , and drain current drivability, with p-well doping concentration via the SILVACO simulator. From simulation results, we found the BV DS and the drain current (I D ) as functions of the p-well doping concentration at an ion implantation energy of 80 keV. With increasing of p-well doping concentration in the guard ring region, both V TH and BV DS slowly increased, but I D decreased, because the boron lateral diffusion during the fabrication process below gate trench region affected the doping concentration of the p-body at the active region. Additionally, 100 V/100 A rated trench double-diffused MOSFETs (TDMOSFETs) with meshes and stripes were successfully developed by using a silicon deep etching process. The variations in the electrical properties, such as V TH , BV DS , and drain current drivability, of the two different kinds of fabricated devices, with cell design and density in TDMOSFETs were also studied. The BV DS and the V TH in the stripe-type TDMOSFET were 110 and 3 V, respectively. However, the V TH of mesh-type device was smaller 0.5 V than that of stripe-type because of corner effect. The BV DS improved about 20 V compared to stripe-type TDMOSFET due to edge termination, and the maximum drain current (I D.MAX ) was improved by about 10% due to an increase in the gate width at the same chip size. These effects were reflected in devices with different cell densities. When the cell density was increased, however

  18. Variation in the electrical properties of 100 V/100 A rated mesh and stripe TDMOSFETs (trench double-diffused MOSFETs) for motor drive applications

    Energy Technology Data Exchange (ETDEWEB)

    Na, Kyoung-Il; Kah, Dong-Ha; Kim, Sang-Gi; Koo, Jin-Gun; Kim, Jong-Dae; Yang, Yil-Suk; Lee, Jin-Ho [Electronics and Telecommunications Research Institute, Daejeon (Korea, Republic of)

    2012-05-15

    The vertical power metal-oxide semiconductor field-effect transistors (MOSFETs) with deep trench structures are the most promising candidates to overcome the trade-off relationship between the ON-resistance (R{sub ON}) and the blocking voltage (BV{sub DS}). Especially, 100 V/100 A rated trench power MOSFETs are used in components of many power systems, such as motors and LED lighting drive ICs, DC-DC converters in electric vehicles, and so on. In this work, we studied variations of the electrical characteristics, such as threshold voltage (V{sub TH}), BV{sub DS}, and drain current drivability, with p-well doping concentration via the SILVACO simulator. From simulation results, we found the BV{sub DS} and the drain current (I{sub D}) as functions of the p-well doping concentration at an ion implantation energy of 80 keV. With increasing of p-well doping concentration in the guard ring region, both V{sub TH} and BV{sub DS} slowly increased, but I{sub D} decreased, because the boron lateral diffusion during the fabrication process below gate trench region affected the doping concentration of the p-body at the active region. Additionally, 100 V/100 A rated trench double-diffused MOSFETs (TDMOSFETs) with meshes and stripes were successfully developed by using a silicon deep etching process. The variations in the electrical properties, such as V{sub TH}, BV{sub DS}, and drain current drivability, of the two different kinds of fabricated devices, with cell design and density in TDMOSFETs were also studied. The BV{sub DS} and the V{sub TH} in the stripe-type TDMOSFET were 110 and 3 V, respectively. However, the V{sub TH} of mesh-type device was smaller 0.5 V than that of stripe-type because of corner effect. The BV{sub DS} improved about 20 V compared to stripe-type TDMOSFET due to edge termination, and the maximum drain current (I{sub D.MAX}) was improved by about 10% due to an increase in the gate width at the same chip size. These effects were reflected in devices with

  19. Identification of Fixed and Interface Trap Charges in Hot-Carrier Stressed Metal Oxide Semiconductor Field Effect Transistors (MOSFET's) through Ultraviolet Light Anneal and Gate Capacitance Measurements

    Science.gov (United States)

    Ling, C.

    1995-01-01

    Fixed and interface trap charges in hot-carrier degraded metal oxide semiconductor field effect transistors (MOSFET's) can be distinguished by ultraviolet light (λ=253.7 nm) annealing, and observing the resultant changes in the gate-to-drain capacitance. Trapped electrons anneal readily, resulting in large changes in the gate capacitance and the threshold voltage. This suggests a trap level below the conduction band edge of SiO2 that is smaller than the photon energy (4.9 eV). In contrast, trapped holes and interface traps do not anneal, or anneal insignificantly even after prolonged irradiation. This is consistent with a much deeper hole trap level in SiO2, generally reported.

  20. Analytical Modeling of Potential Distribution and Threshold Voltage of Gate Underlap DG MOSFETs with a Source/Drain Lateral Gaussian Doping Profile

    Science.gov (United States)

    Singh, Kunal; Kumar, Mirgender; Goel, Ekta; Singh, Balraj; Dubey, Sarvesh; Kumar, Sanjay; Jit, Satyabrata

    2016-04-01

    This paper reports a new two-dimensional (2D) analytical model for the potential distribution and threshold voltage of the short-channel symmetric gate underlap ultrathin DG MOSFETs with a lateral Gaussian doping profile in the source (S)/drain (D) region. The parabolic approximation and conformal mapping techniques have been explored for solving the 2D Poisson's equation to obtain the channel potential function of the device. The effects of straggle parameter (of the lateral Gaussian doping profile in the S/D region), underlap length, gate length, channel thickness and oxide thickness on the surface potential and threshold voltage have been investigated. The loss of switching speed due to the drain-induced barrier lowering (DIBL) has also been reported. The proposed model results have been validated by comparing them with their corresponding TCAD simulation data obtained by using the commercially available 2D ATLAS™ simulation software.

  1. Multi-valued logic circuits using hybrid circuit consisting of three gates single-electron transistors (TG-SETs) and MOSFETs.

    Science.gov (United States)

    Shin, SeungJun; Yu, YunSeop; Choi, JungBum

    2008-10-01

    New multi-valued logic (MVL) families using the hybrid circuits consisting of three gates single-electron transistors (TG-SETs) and a metal-oxide-semiconductor field-effect transistor (MOSFET) are proposed. The use of SETs offers periodic literal characteristics due to Coulomb oscillation of SET, which allows a realization of binary logic (BL) circuits as well as multi-valued logic (MVL) circuits. The basic operations of the proposed MVL families are successfully confirmed through SPICE circuit simulation based on the physical device model of a TG-SET. The proposed MVL circuits are found to be much faster, but much larger power consumption than a previously reported MVL, and they have a trade-off between speed and power consumption. As an example to apply the newly developed MVL families, a half-adder is introduced.

  2. Remote N2 plasma treatment to deposit ultrathin high-k dielectric as tunneling contact layer for single-layer MoS2 MOSFET

    Science.gov (United States)

    Qian, Qingkai; Zhang, Zhaofu; Hua, Mengyuan; Wei, Jin; Lei, Jiacheng; Chen, Kevin J.

    2017-12-01

    Remote N2 plasma treatment is explored as a surface functionalization technique to deposit ultrathin high-k dielectric on single-layer MoS2. The ultrathin dielectric is used as a tunneling contact layer, which also serves as an interfacial layer below the gate region for fabricating top-gate MoS2 metal–oxide–semiconductor field-effect transistors (MOSFETs). The fabricated devices exhibited small hysteresis and mobility as high as 14 cm2·V‑1·s‑1. The contact resistance was significantly reduced, which resulted in the increase of drain current from 20 to 56 µA/µm. The contact resistance reduction can be attributed to the alleviated metal–MoS2 interface reaction and the preserved conductivity of MoS2 below the source/drain metal contact.

  3. Device and circuit analysis of a sub 20 nm double gate MOSFET with gate stack using a look-up-table-based approach

    Science.gov (United States)

    Chakraborty, S.; Dasgupta, A.; Das, R.; Kar, M.; Kundu, A.; Sarkar, C. K.

    2017-12-01

    In this paper, we explore the possibility of mapping devices designed in TCAD environment to its modeled version developed in cadence virtuoso environment using a look-up table (LUT) approach. Circuit simulation of newly designed devices in TCAD environment is a very slow and tedious process involving complex scripting. Hence, the LUT based modeling approach has been proposed as a faster and easier alternative in cadence environment. The LUTs are prepared by extracting data from the device characteristics obtained from device simulation in TCAD. A comparative study is shown between the TCAD simulation and the LUT-based alternative to showcase the accuracy of modeled devices. Finally the look-up table approach is used to evaluate the performance of circuits implemented using 14 nm nMOSFET.

  4. A threshold-voltage model for small-scaled GaAs nMOSFET with stacked high-k gate dielectric

    International Nuclear Information System (INIS)

    Liu Chaowen; Xu Jingping; Liu Lu; Lu Hanhan; Huang Yuan

    2016-01-01

    A threshold-voltage model for a stacked high-k gate dielectric GaAs MOSFET is established by solving a two-dimensional Poisson's equation in channel and considering the short-channel, DIBL and quantum effects. The simulated results are in good agreement with the Silvaco TCAD data, confirming the correctness and validity of the model. Using the model, impacts of structural and physical parameters of the stack high-k gate dielectric on the threshold-voltage shift and the temperature characteristics of the threshold voltage are investigated. The results show that the stacked gate dielectric structure can effectively suppress the fringing-field and DIBL effects and improve the threshold and temperature characteristics, and on the other hand, the influence of temperature on the threshold voltage is overestimated if the quantum effect is ignored. (paper)

  5. A threshold-voltage model for small-scaled GaAs nMOSFET with stacked high-k gate dielectric

    Science.gov (United States)

    Chaowen, Liu; Jingping, Xu; Lu, Liu; Hanhan, Lu; Yuan, Huang

    2016-02-01

    A threshold-voltage model for a stacked high-k gate dielectric GaAs MOSFET is established by solving a two-dimensional Poisson's equation in channel and considering the short-channel, DIBL and quantum effects. The simulated results are in good agreement with the Silvaco TCAD data, confirming the correctness and validity of the model. Using the model, impacts of structural and physical parameters of the stack high-k gate dielectric on the threshold-voltage shift and the temperature characteristics of the threshold voltage are investigated. The results show that the stacked gate dielectric structure can effectively suppress the fringing-field and DIBL effects and improve the threshold and temperature characteristics, and on the other hand, the influence of temperature on the threshold voltage is overestimated if the quantum effect is ignored. Project supported by the National Natural Science Foundation of China (No. 61176100).

  6. Analytical Subthreshold Current and Subthreshold Swing Models for a Fully Depleted (FD) Recessed-Source/Drain (Re-S/D) SOI MOSFET with Back-Gate Control

    Science.gov (United States)

    Saramekala, Gopi Krishna; Tiwari, Pramod Kumar

    2017-08-01

    Two-dimensional (2D) analytical models for the subthreshold current and subthreshold swing of the back-gated fully depleted recessed-source/drain (Re-S/D) silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistor (MOSFET) are presented. The surface potential is determined by solving the 2D Poisson equation in both channel and buried-oxide (BOX) regions, considering suitable boundary conditions. To derive closed-form expressions for the subthreshold characteristics, the virtual cathode potential expression has been derived in terms of the minimum of the front and back surface potentials. The effect of various device parameters such as gate oxide and Si film thicknesses, thickness of source/drain penetration into BOX, applied back-gate bias voltage, etc. on the subthreshold current and subthreshold swing has been analyzed. The validity of the proposed models is established using the Silvaco ATLAS™ 2D device simulator.

  7. Two-dimensional model for subthreshold current and subthreshold swing of graded-channel dual-material double-gate (GCDMDG) MOSFETs

    Science.gov (United States)

    Goel, Ekta; Kumar, Sanjay; Singh, Balraj; Singh, Kunal; Jit, Satyabrata

    2017-06-01

    The subthreshold performance of graded-channel dual-material double-gate (GCDMDG) MOSFETs is examined through two-dimensional (2D) analytical modeling of subthreshold-current (SC) and subthreshold-swing (SS). The potential function obtained by using the parabolic approach to solve the 2D Poisson's equation, has been used to formulate SC and SS characteristics of the device. The variations of SS against different device parameters have been obtained with the help of effective conduction path parameter. The SC and SS characteristics of the GCDMDG MOS transistor have been compared with those of the dual-material double-gate (DMDG) and simple graded-channel double-gate (GCDG) MOS structures to show its better subthreshold characteristics over the latter two devices. The results of the developed model are well-agreed with the commercially available SILVACO ATLAS™ simulator data.

  8. Analytical model for subthreshold current and subthreshold swing of short-channel double-material-gate MOSFETs with strained-silicon channel on silicon—germanium substrates

    International Nuclear Information System (INIS)

    Tiwari Pramod Kumar; Saramekala Gopi Krishna; Mukhopadhyay Anand Kumar; Dubey Sarvesh

    2014-01-01

    The present work gives some insight into the subthreshold behaviour of short-channel double-material-gate strained-silicon on silicon—germanium MOSFETs in terms of subthreshold swing and off-current. The formulation of subthreshold current and, thereupon, the subthreshold swing have been done by exploiting the expression of potential distribution in the channel region of the device. The dependence of the subthreshold characteristics on the device parameters, such as Ge mole fraction, gate length ratio, work function of control gate metal and gate length, has been tested in detail. The analytical models have been validated by the numerical simulation results that were obtained from the device simulation software ATLAS™ by Silvaco Inc. (semiconductor devices)

  9. Properties of slow traps of ALD Al{sub 2}O{sub 3}/GeO{sub x}/Ge nMOSFETs with plasma post oxidation

    Energy Technology Data Exchange (ETDEWEB)

    Ke, M., E-mail: kiramn@mosfet.t.u-tokyo.ac.jp; Yu, X.; Chang, C.; Takenaka, M.; Takagi, S. [Department of Electrical Engineering and Information Systems, The University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-8656, Japan and JST-CREST, K' s Gobancho 6F, 7 Gobancho, Chiyoda-ku, Tokyo 102-0076 (Japan)

    2016-07-18

    The realization of Ge gate stacks with a small amount of slow trap density as well as thin equivalent oxide thickness and low interface state density (D{sub it}) is a crucial issue for Ge CMOS. In this study, we examine the properties of slow traps, particularly the location of slow traps, of Al{sub 2}O{sub 3}/GeO{sub x}/n-Ge and HfO{sub 2}/Al{sub 2}O{sub 3}/GeO{sub x}/n-Ge MOS interfaces with changing the process and structural parameters, formed by atomic layer deposition (ALD) of Al{sub 2}O{sub 3} and HfO{sub 2}/Al{sub 2}O{sub 3} combined with plasma post oxidation. It is found that the slow traps can locate in the GeO{sub x} interfacial layer, not in the ALD Al{sub 2}O{sub 3} layer. Furthermore, we study the time dependence of channel currents in the Ge n-MOSFETs with 5-nm-thick Al{sub 2}O{sub 3}/GeO{sub x}/Ge gate stacks, with changing the thickness of GeO{sub x}, in order to further clarify the position of slow traps. The time dependence of the current drift and the effective time constant of slow traps do not change among the MOSFETs with the different thickness GeO{sub x}, demonstrating that the slow traps mainly exist near the interfaces between Ge and GeO{sub x}.

  10. Sub-1-V-60 nm vertical body channel MOSFET-based six-transistor static random access memory array with wide noise margin and excellent power delay product and its optimization with the cell ratio on static random access memory cell

    Science.gov (United States)

    Ogasawara, Ryosuke; Endoh, Tetsuo

    2018-04-01

    In this study, with the aim to achieve a wide noise margin and an excellent power delay product (PDP), a vertical body channel (BC)-MOSFET-based six-transistor (6T) static random access memory (SRAM) array is evaluated by changing the number of pillars in each part of a SRAM cell, that is, by changing the cell ratio in the SRAM cell. This 60 nm vertical BC-MOSFET-based 6T SRAM array realizes 0.84 V operation under the best PDP and up to 31% improvement of PDP compared with the 6T SRAM array based on a 90 nm planar MOSFET whose gate length and channel width are the same as those of the 60 nm vertical BC-MOSFET. Additionally, the vertical BC-MOSFET-based 6T SRAM array achieves an 8.8% wider read static noise margin (RSNM), a 16% wider write margin (WM), and an 89% smaller leakage. Moreover, it is shown that changing the cell ratio brings larger improvements of RSNM, WM, and write time in the vertical BC-MOSFET-based 6T SRAM array.

  11. Effect of film properties for non-linear DPL model in a nanoscale MOSFET with high-k material: ZrO2/HfO2/La2O3

    Science.gov (United States)

    Shomali, Zahra; Ghazanfarian, Jafar; Abbassi, Abbas

    2015-07-01

    Numerical simulation of non-linear non-Fourier heat conduction within a nano-scale metal-oxide-semiconductor field-effect transistor (MOSFET) is presented under the framework of Dual-Phase-Lag model including the boundary phonon scattering. The MOSFET is modeled in four cases of: (I) thin silicon slab, (II) including uniform heat generation, (III) double-layered buried oxide MOSFET with uniform heat generation in silicon-dioxide layer, and (IV) high-k/metal gate transistor. First, four cases are studied under four conditions of (a) constant bulk and (b) constant film thermal properties, (c) temperature-dependent properties of bulk silicon, and (d) temperature-dependent thermal properties of film silicon. The heat source and boundary conditions are similar to what existed in a real MOSFET. It is concluded that in all cases, considering the film properties lowers the temperature jump due to the reduction of the Knudsen number. Furthermore, the speed of heat flux penetration for film properties is less than that of the cases concerning bulk properties. Also, considering the temperature-dependent properties drastically changes the temperature and heat flux distributions within the transistor, which increases the diffusion speed and more, decreases the steady state time. Calculations for case (III) presents that all previous studies have underestimated the value of the peak temperature rise by considering the constant bulk properties of silicon. Also, it is found that among the high-k dielectrics investigated in case (IV), zirconium dioxide shows the least peak temperature rise. This presents that zirconium dioxide is a good candidate as far as the thermal issues are concerned.

  12. Top-down, in-plane GaAs nanowire MOSFETs on an Al2O3 buffer with a trigate oxide from focused ion-beam milling and chemical oxidation

    Science.gov (United States)

    Lee, S. C.; Neumann, A.; Jiang, Y.-B.; Artyushkova, K.; Brueck, S. R. J.

    2016-09-01

    The top-down fabrication of an in-plane nanowire (NW) GaAs metal-oxide-semiconductor field-effect transistor (MOSFET) with a trigate oxide implemented by liquid-phase chemical-enhanced oxidation (LPCEO) is reported. A 2 μm long channel having an effective cross section ˜70 × 220 nm2 is directly fabricated into an epitaxial n +-GaAs layer. This in-plane NW structure is achieved by focused ion beam (FIB) milling and hydrolyzation oxidation resulting in electronic isolation from the substrate through a semiconductor-on-insulator structure with an n +-GaAs/Al2O3 layer stack. The channel is epitaxially connected to the μm-scale source and drain within a single layer for a planar MOSFET to avoid any issues of ohmic contact and LPCEO to the NW. To fabricate a MOSFET, the top and the two sidewalls of the in-plane NW are oxidized by LPCEO to relieve the surface damage from FIB as well as to transform these surfaces to a ˜15 nm thick gate oxide. This trigate device has threshold voltage ˜0.14 V and peak transconductance ˜35 μS μm-1 with a subthreshold swing ˜150 mV/decade and on/off ratio of drain current ˜103, comparable to the performance of bottom-up NW devices.

  13. Estimating Effective Dose from Phantom Dose Measurements in Atrial Fibrillation Ablation Procedures and Comparison of MOSFET and TLD Detectors in a Small Animal Dosimetry Setting

    Science.gov (United States)

    Anderson-Evans, Colin David

    Two different studies will be presented in this work. The first involves the calculation of effective dose from a phantom study which simulates an atrial fibrillation (AF) ablation procedure. The second involves the validation of metal-oxide semiconducting field effect transistors (MOSFET) for small animal dosimetry applications as well as improved characterization of the animal irradiators on Duke University's campus. Atrial Fibrillation is an ever increasing health risk in the United States. The most common type of cardiac arrhythmia, AF is associated with increased mortality and ischemic cerebrovascular events. Managing AF can include, among other treatments, an interventional procedure called catheter ablation. The procedure involves the use of biplane fluoroscopy during which a patient can be exposed to radiation for as much as two hours or more. The deleterious effects of radiation become a concern when dealing with long fluoroscopy times, and because the AF ablation procedure is elective, it makes relating the risks of radiation ever more essential. This study hopes to quantify the risk through the derivation of dose conversion coefficients (DCCs) from the dose-area product (DAP) with the intent that DCCs can be used to provide estimates of effective dose (ED) for typical AF ablation procedures. A bi-plane fluoroscopic and angiographic system was used for the simulated AF ablation procedures. For acquisition of organ dose measurements, 20 diagnostic MOSFET detectors were placed at selected organs in a male anthropomorphic phantom, and these detectors were attached to 4 bias supplies to obtain organ dose readings. The DAP was recorded from the system console and independently validated with an ionization chamber and radiochromic film. Bi-plane fluoroscopy was performed on the phantom for 10 minutes to acquire the dose rate for each organ, and the average clinical procedure time was multiplied by each organ dose rate to obtain individual organ doses. The

  14. Comparación de las técnicas de extracción del voltaje de umbral basadas en la característica gm/ID del MOSFETs.

    Directory of Open Access Journals (Sweden)

    Arturo Fajardo Jaimes

    2017-04-01

    Full Text Available Context: In advanced ultralow-power devices, it is necessary to use the accuracy extraction procedures of the MOSFET threshold voltage to fully characterize the devices. These procedures are based in the measurement of the Tran-conductance efficiency (gm/ID and its first derivative in function of the voltage gate source (d(gm/ID/dVGS. In order to increase their independency respect to the non-zero drain source voltage (VDS ≠0 it is used a process to correct the error. Theoretically, VDS should be 0 V; however, the VDS is grater than 10 mV in the experimental setup in order to avoid electrical noise, but less than a certain maximum value for allowing the MOSFET operation in the linear region of the weak inversion. Objective: To compare the extraction procedure proposed by (MC Schneider et al., 2006 and the method proposed by (Rudenko et al., 2011 with a generic, controlled and coherent test scenario. Method: This paper proposes a test scenario based on the Advanced Compact MOSFET model (ACM of a long channel MOSFET made in a standard 0.35 mm CMOS process, implemented numerically in MATLABâ. The concept of Power Error Correction (PEC was used to compare the two processes numerically; it quantifies the sensitivity of the extraction process to the effect by the non-zero voltage value of the VDS in the experimental setup (i.e., NZ-DS effect. Results: The error correction procedure proposed by (Siebel et al., 2012, Schneider et al., 2006 estimates the NZ-DS effect better than the procedure proposed by (Rudenko et al., 2011, considering the average, maximum and minimum PEC obtained for both extraction methodologies for a long channel MOSFET fabricated in a standard CMOS process of 0.35 μm, when the VDS is less than 50 mV. Conclusions: The Vth extraction procedure proposed by (MC Schneider et al., 2006 is more robust than the method proposed by (Rudenko et al., 2011 regarding the NZ-DS effect.

  15. Nanosecond pulsed electric fields (nsPEFs) low cost generator design using power MOSFET and Cockcroft-Walton multiplier circuit as high voltage DC source

    International Nuclear Information System (INIS)

    Sulaeman, M. Y.; Widita, R.

    2014-01-01

    Purpose: Non-ionizing radiation therapy for cancer using pulsed electric field with high intensity field has become an interesting field new research topic. A new method using nanosecond pulsed electric fields (nsPEFs) offers a novel means to treat cancer. Not like the conventional electroporation, nsPEFs able to create nanopores in all membranes of the cell, including membrane in cell organelles, like mitochondria and nucleus. NsPEFs will promote cell death in several cell types, including cancer cell by apoptosis mechanism. NsPEFs will use pulse with intensity of electric field higher than conventional electroporation, between 20–100 kV/cm and with shorter duration of pulse than conventional electroporation. NsPEFs requires a generator to produce high voltage pulse and to achieve high intensity electric field with proper pulse width. However, manufacturing cost for creating generator that generates a high voltage with short duration for nsPEFs purposes is highly expensive. Hence, the aim of this research is to obtain the low cost generator design that is able to produce a high voltage pulse with nanosecond width and will be used for nsPEFs purposes. Method: Cockcroft-Walton multiplier circuit will boost the input of 220 volt AC into high voltage DC around 1500 volt and it will be combined by a series of power MOSFET as a fast switch to obtain a high voltage with nanosecond pulse width. The motivation using Cockcroft-Walton multiplier is to acquire a low-cost high voltage DC generator; it will use capacitors and diodes arranged like a step. Power MOSFET connected in series is used as voltage divider to share the high voltage in order not to damage them. Results: This design is expected to acquire a low-cost generator that can achieve the high voltage pulse in amount of −1.5 kV with falltime 3 ns and risetime 15 ns into a 50Ω load that will be used for nsPEFs purposes. Further detailed on the circuit design will be explained at presentation

  16. Effective dose estimation for pediatric upper gastrointestinal examinations using an anthropomorphic phantom set and metal oxide semiconductor field-effect transistor (MOSFET) technology

    International Nuclear Information System (INIS)

    Emigh, Brent; Gordon, Christopher L.; Falkiner, Michelle; Thomas, Karen E.; Connolly, Bairbre L.

    2013-01-01

    There is a need for updated radiation dose estimates in pediatric fluoroscopy given the routine use of new dose-saving technologies and increased radiation safety awareness in pediatric imaging. To estimate effective doses for standardized pediatric upper gastrointestinal (UGI) examinations at our institute using direct dose measurement, as well as provide dose-area product (DAP) to effective dose conversion factors to be used for the estimation of UGI effective doses for boys and girls up to 10 years of age at other centers. Metal oxide semiconductor field-effect transistor (MOSFET) dosimeters were placed within four anthropomorphic phantoms representing children ≤10 years of age and exposed to mock UGI examinations using exposures much greater than used clinically to minimize measurement error. Measured effective dose was calculated using ICRP 103 weights and scaled to our institution's standardized clinical UGI (3.6-min fluoroscopy, four spot exposures and four examination beam projections) as determined from patient logs. Results were compared to Monte Carlo simulations and related to fluoroscope-displayed DAP. Measured effective doses for standardized pediatric UGI examinations in our institute ranged from 0.35 to 0.79 mSv in girls and were 3-8% lower for boys. Simulation-derived and measured effective doses were in agreement (percentage differences 0.18). DAP-to-effective dose conversion factors ranged from 6.5 x 10 -4 mSv per Gy-cm 2 to 4.3 x 10 -3 mSv per Gy-cm 2 for girls and were similarly lower for boys. Using modern fluoroscopy equipment, the effective dose associated with the UGI examination in children ≤10 years at our institute is < 1 mSv. Estimations of effective dose associated with pediatric UGI examinations can be made for children up to the age of 10 using the DAP-normalized conversion factors provided in this study. These estimates can be further refined to reflect individual hospital examination protocols through the use of direct organ

  17. Investigation of the Low-Temperature Behavior of FD-SOI MOSFETs in the Saturation Regime Using Y and Z Functions

    Directory of Open Access Journals (Sweden)

    A. Karsenty

    2014-01-01

    Full Text Available The saturation regime of two types of fully depleted (FD SOI MOSFET devices was studied. Ultrathin body (UTB and gate recessed channel (GRC devices were fabricated simultaneously on the same silicon wafer through a selective “gate recessed” process. They share the same W/L ratio but have a channel film thickness of 46 nm and 2.2 nm, respectively. Their standard characteristics (IDS-VDS and IDS-VGS of the devices were measured at room temperature before cooling down to 77 K. Surprisingly, their respective temperature dependence is found to be opposite. In this paper, we focus our comparative analysis on the devices' conduction using a Y-function applied to the saturation domain. The influence of the temperature in this domain is presented for the first time. We point out the limits of the Y-function analysis and show that a new function called Z can be used to extract the series resistance in the saturation regime.

  18. γ-irradiation hardness of short-channel nMOSFETs fabricated in a 0.5 μm SOI technology

    International Nuclear Information System (INIS)

    Claeys, C.; Simoen, E.; Efremov, A.; Litovchenko, V.G.; Evtukh, A.; Kizjak, A.; Rassamakin, Ju.

    2002-01-01

    The increased use of custom-of-the-shelf (COTS) components for space applications necessitates a better insight into the radiation hardness of scaled down technologies. The present study investigates the impact of γ-irradiation up to 100 krad (Si) on the electrical performance of SOI MOSFETs with 0.5-2.0 μm channel lengths. Attention is given to the threshold voltage, the maximum transconductance and the electron mobility in the channel. The influence of a subsequent 15 min thermal anneal at 315 and/or 415 deg. C is also pointed out. Both the oxide thickness and the concentration of the boron doping in the channel have an impact on the radiation hardness. Depending on the irradiation conditions and the transistor doping profiles, either a net negative or positive radiation-induced charge is built up in the oxide and at the interface. A model, based on the incorporation of B atoms in to the oxide layer, is proposed to explain the experimental observations. The anneal efficiency depends on the technological parameters, the irradiation dose and the anneal conditions. In some cases a low dose irradiation and subsequent anneal have a beneficial impact on the electrical device performance

  19. Design and Analysis of Double-Gate MOSFETs for Ultra-Low Power Radio Frequency Identification (RFID: Device and Circuit Co-Design

    Directory of Open Access Journals (Sweden)

    Tony T. Kim

    2011-07-01

    Full Text Available Recently, double-gate MOSFETs (DGMOSFETs have been shown to be more optimal for ultra-low power circuit design due to the improved subthreshold slope and the reduced leakage current compared to bulk CMOS. However, DGMOSFETs for subthreshold circuit design have not been much explored in comparison to those for strong inversion-based design. In this paper, various configurations of DGMOSFETs, such as tied/independent gates and symmetric/asymmetric gate oxide thickness are explored for ultra-low power and high efficient radio frequency identification (RFID design. Comparison of bulk CMOS with DGMOSFETs has been conducted in ultra-low power subthreshold digital logic design and rectifier design, emphasizing the scope of the nano-scale DGMOSFET technology for future ultra-low power systems. The DGMOSFET-based subthreshold logic improves energy efficiency by more than 40% compared to the bulk CMOS-based logic at 32 nm. Among the various DGMOSFET configurations for RFID rectifiers, symmetric tied-gate DGMOSFET has the best power conversion efficiency and the lowest power consumption.

  20. An Analytical Threshold Voltage Model of Fully Depleted (FD) Recessed-Source/Drain (Re-S/D) SOI MOSFETs with Back-Gate Control

    Science.gov (United States)

    Saramekala, Gopi Krishna; Tiwari, Pramod Kumar

    2016-10-01

    This paper presents an analytical threshold voltage model for back-gated fully depleted (FD), recessed-source drain silicon-on-insulator metal-oxide-semiconductor field-effect transistors (MOSFETs). Analytical surface potential models have been developed at front and back surfaces of the channel by solving the two-dimensional (2-D) Poisson's equation in the channel region with appropriate boundary conditions assuming a parabolic potential profile in the transverse direction of the channel. The strong inversion criterion is applied to the front surface potential as well as on the back one in order to find two separate threshold voltages for front and back channels of the device, respectively. The device threshold voltage has been assumed to be associated with the surface that offers a lower threshold voltage. The developed model was analyzed extensively for a variety of device geometry parameters like the oxide and silicon channel thicknesses, the thickness of the source/drain extension in the buried oxide, and the applied bias voltages with back-gate control. The proposed model has been validated by comparing the analytical results with numerical simulation data obtained from ATLAS™, a 2-D device simulator from SILVACO.

  1. Multi-objective optimization of MOSFETs channel widths and supply voltage in the proposed dual edge-triggered static D flip-flop with minimum average power and delay by using fuzzy non-dominated sorting genetic algorithm-II.

    Science.gov (United States)

    Keivanian, Farshid; Mehrshad, Nasser; Bijari, Abolfazl

    2016-01-01

    D Flip-Flop as a digital circuit can be used as a timing element in many sophisticated circuits. Therefore the optimum performance with the lowest power consumption and acceptable delay time will be critical issue in electronics circuits. The newly proposed Dual-Edge Triggered Static D Flip-Flop circuit layout is defined as a multi-objective optimization problem. For this, an optimum fuzzy inference system with fuzzy rules is proposed to enhance the performance and convergence of non-dominated sorting Genetic Algorithm-II by adaptive control of the exploration and exploitation parameters. By using proposed Fuzzy NSGA-II algorithm, the more optimum values for MOSFET channel widths and power supply are discovered in search space than ordinary NSGA types. What is more, the design parameters involving NMOS and PMOS channel widths and power supply voltage and the performance parameters including average power consumption and propagation delay time are linked. To do this, the required mathematical backgrounds are presented in this study. The optimum values for the design parameters of MOSFETs channel widths and power supply are discovered. Based on them the power delay product quantity (PDP) is 6.32 PJ at 125 MHz Clock Frequency, L = 0.18 µm, and T = 27 °C.

  2. Dual-Input Isolated Full-Bridge Boost DC-DC Converter Based on the Distributed Transformers

    DEFF Research Database (Denmark)

    Zhang, Zhe; Thomsen, Ole Cornelius; Andersen, Michael A. E.

    2012-01-01

    In this paper, a new two-input isolated boost dc-dc converter based on a distributed multi-transformer structure which is suitable for hybrid renewable energy systems is investigated and designed. With a novel transformer winding-connecting strategy, the two input ports can be decoupled completely...... and the single-input mode, respectively. The main advantage of the proposed topology is that the four transformers and the secondary rectifiers are fully utilized whether the converter is connected with two input power sources or only one input. Although the four transformers are employed, the nominal powers...... of each transformer and rectifier are both reduced by four times. Furthermore, some special issues on converter design, such as increasing number of the input ports, the magnetic integration and the ground loop decoupling are discussed. A 2 kW prototype was built and tested. Experiments on the converter...

  3. A PWM Controller of a Full Bridge Single-Phase Synchronous Inverter for Micro-Grid System

    Science.gov (United States)

    Rahman, Tawfikur; Motakabber, S. M. A.; Ibrahimy, M. I.; Raghib, Aliza ‘Aini Binti Md Ralib@ Md

    2017-12-01

    Nowadays, microgrid system technology is becoming popular for small area power management systems. It is essential to be less harmonic-distortion and high efficiency of the inverter for microgrid applications. Pulse width modulation (PWM) controller is a conventional switching control technique which is suitable to use in the microgrid connected power inverter system. The control method and algorithm of this technique are challenging, and different approaches are required to avoid the complexity for a customized solution of the microgrid application. This paper proposes a comparative analysis of different controller and their operational methods. A PWM controller is used to reduce the ripple voltage noise while a continuous current mode provides a small output ripple which gives steady-state error as zero on fundamental and cutoff frequency. To reduce the ripple current, higher frequency harmonic distortion, switching loss and phase noise, LC low pass filter is used on either side of input and output terminals. The proposed inverter is designed by MATLAB 2016a simulation software. A balanced load resistance (RL = 20.5 Ω) of star configuration and a dual input DC voltage of ± 35V are considered. In this design, the circuit parameters, the fundamental frequency of 50 Hz, the PWM duty cycle of 95%, the cutoff frequency of the switching controller of 33 kHz are considered. The inverter in this paper exhibits THD of 0.44% and overall efficiency approximately of 98%. The proposed inverter is expected to be suitable for microgrid applications.

  4. Analysis and Mitigation of Dead Time Harmonics in the Single-Phase Full-Bridge PWM Converters with Repetitive Controllers

    DEFF Research Database (Denmark)

    Yang, Yongheng; Zhou, Keliang; Wang, Huai

    2018-01-01

    -Width Modulation (PWM) schemes. Both solutions will contribute to a degradation of the injected current quality. As a consequence, the harmonics induced by the dead time (referred to as "dead time harmonics" hereafter) have to be compensated in order to achieve a satisfactory current quality as required...... by standards. In this paper, the emission mechanism of dead time harmonics in single-phase PWM inverters is thus presented considering the modulation schemes in details. More importantly, a repetitive controller has been adopted to eliminate the dead time effect in single-phase grid-connected PWM converters....... The repetitive controller has been plugged into a proportional resonant-based fundamental current controller so as to mitigate the dead time harmonics and also maintain the control of the fundamental-frequency grid current in terms of dynamics. Simulations and experiments are provided, which confirm...

  5. Inverse Problem for a Curved Quantum Guide

    Directory of Open Access Journals (Sweden)

    Laure Cardoulis

    2012-01-01

    Full Text Available We consider the Dirichlet Laplacian operator −Δ on a curved quantum guide in ℝ  n(n=2,3 with an asymptotically straight reference curve. We give uniqueness results for the inverse problem associated to the reconstruction of the curvature by using either observations of spectral data or a boot-strapping method.

  6. Complete mitochondrial genome of threatened mahseer Tor tor ...

    Indian Academy of Sciences (India)

    PAUP ver. 4.0 (Swofford 2003) was used to reconstruct the phylogenetic tree using parsi- mony (MP), maximum likelihood (ML) and neighbour join- ing (NJ) methods. Nonparametric bootstrap support for each node of the tree was estimated using 100 heuristic boot- strap replicates. Bayesian inference (BI) was implemented.

  7. Sequence comparison and phylogenetic analysis of core gene of ...

    African Journals Online (AJOL)

    STORAGESEVER

    2010-07-19

    Jul 19, 2010 ... sequences from Japan are grouped into same cluster in the phylogenetic tree. Sequence comparison and phylogenetic ..... Tree was generated by Neighbor joining algorithm. Boot strap values are shown ... Clustal W: improving the sensitivity of progressive multiple sequence alignment through sequence ...

  8. Land cover classification using reformed fuzzy C-means

    Indian Academy of Sciences (India)

    ... or cluster centers for each cluster (Pal et al 2005). Both FPCM and PFCM require some boot strap method for initialization of weights. FCM is the most popular fuzzy clustering algorithm. Researchers have used this algorithm for different applications. Problems related to remote sensing data clustering for both supervised ...

  9. 5kW phase-shifted full-bridge converter with current doubler using normally-off SiC JFETs designed for 98% efficiency

    DEFF Research Database (Denmark)

    Török, Lajos; Beczkowski, Szymon; Munk-Nielsen, Stig

    2013-01-01

    In this paper a 5kW step-down converter for low-voltage high-current application is presented using normally-off SiC JFETs as high voltage power switches, operating with efficiency close to 98%. Different low voltage side rectification solutions and loss estimations are also presented. As results...

  10. A new on-chip all-digital three-phase full-bridge dc/ac power inverter with feedforward and frequency control techniques.

    Science.gov (United States)

    Chen, Jiann-Jong; Kung, Che-Min

    2010-09-01

    The communication speed between components is far from satisfactory. To achieve high speed, simple control system configuration, and low cost, a new on-chip all-digital three-phase dc/ac power inverter using feedforward and frequency control techniques is proposed. The controller of the proposed power inverter, called the shift register, consists of six-stage D-latch flip-flops with a goal of achieving low-power consumption and area efficiency. Variable frequency is achieved by controlling the clocks of the shift register. One advantage regarding the data signal (D) and the common clock (CK) is that, regardless of the phase difference between the two, all of the D-latch flip-flops are capable of delaying data by one CK period. To ensure stability, the frequency of CK must be six times higher than that of D. The operation frequency of the proposed power inverter ranges from 10 Hz to 2 MHz, and the maximum output loading current is 0.8 A. The prototype of the proposed circuit has been fabricated with TSMC 0.35 μm 2P4M CMOS processes. The total chip area is 2.333 x 1.698 mm2. The three-phase dc/ac power inverter is applicable in uninterrupted power supplies, cold cathode fluorescent lamps, and motors, because of its ability to convert the dc supply voltage into the three-phase ac power sources.

  11. Estudo do efeito de elevação atípica da transcondutância na região linear de polarização em dispositivos SOI nMOSFETS ultra-submicrométricos.

    OpenAIRE

    Paula Ghedini Der Agopian

    2008-01-01

    Este trabalho apresenta o estudo do efeito de elevação atípica da transcondutância na região linear de polarização devido ao efeito de corpo flutuante induzido pela porta (Gate Induced Floating Body Effect - GIFBE) de transistores da tecnologia SOI nMOSFET. Este estudo foi realizado com base em resultados experimentais e em simulações numéricas, as quais foram essenciais para o entendimento físico deste fenômeno. Além de contribuir com a explicação física deste fenômeno, este trabalho explora...

  12. Aluminum nitride insulating films for MOSFET devices

    Science.gov (United States)

    Lewicki, G. W.; Maserjian, J.

    1972-01-01

    Application of aluminum nitrides as electrical insulator for electric capacitors is discussed. Electrical properties of aluminum nitrides are analyzed and specific use with field effect transistors is defined. Operational limits of field effect transistors are developed.

  13. Strained Si engineering for nanoscale MOSFETs

    International Nuclear Information System (INIS)

    Park, Jea-Gun; Lee, Gon-Sub; Kim, Tae-Hyun; Hong, Seuck-Hoon; Kim, Seong-Je; Song, Jin-Hwan; Shim, Tae-Hun

    2006-01-01

    We have revealed a strain relaxation mechanism for strained Si grown on a relaxed SiGe-on-insulator structure fabricated by the bonding, dislocation sink, or condensation method. Strain relaxation for both the bonding and dislocation sink methods was achieved by grading the Ge concentration; in contrast, the relaxation for the condensation method was achieved through Ge atom condensation during oxidation. In addition, we estimated the surface roughness and threading-dislocation pit density for relaxed SiGe layer fabricated by the bonding, dislocation sink, or condensation method. The surface roughness and threading-dislocation pit density for the bonding, dislocation sink, and condensation methods were 2.45, 0.46, and 0.40 nm and 5.0 x 10 3 , 9 x 10 3 , and 0, respectively. In terms of quality and cost-effectiveness, the condensation method was superior to the bonding and dislocation sink methods for forming strained Si on a relaxed SiGe-on-insulator structure

  14. Performance assessment of nanoscale Schottky MOSFET as ...

    Indian Academy of Sciences (India)

    barriers and the channel form a quantum well in the channel leading to the formation of resonance states in the ... ical simulation approaches are discussed for solving the self-consistent two-dimensional. Schrödinger–Poisson .... electron concentration to update the electrostatic potential building a self-consistent loop.

  15. Performance assessment of nanoscale Schottky MOSFET as ...

    Indian Academy of Sciences (India)

    Author Affiliations. Zahra Ahangari1 Morteza Fathipour2. Department of Electrical Engineering, Science and Research Branch, Islamic Azad University, Tehran, Iran; School of Electrical and Computer Engineering, University of Tehran, Tehran, Iran ...

  16. High sensitivity MOSFET-based neutron dosimetry

    International Nuclear Information System (INIS)

    Fragopoulou, M.; Konstantakos, V.; Zamani, M.; Siskos, S.; Laopoulos, T.; Sarrabayrouse, G.

    2010-01-01

    A new dosemeter based on a metal-oxide-semiconductor field effect transistor sensitive to both neutrons and gamma radiation was manufactured at LAAS-CNRS Laboratory, Toulouse, France. In order to be used for neutron dosimetry, a thin film of lithium fluoride was deposited on the surface of the gate of the device. The characteristics of the dosemeter, such as the dependence of its response to neutron dose and dose rate, were investigated. The studied dosemeter was very sensitive to gamma rays compared to other dosemeters proposed in the literature. Its response in thermal neutrons was found to be much higher than in fast neutrons and gamma rays.

  17. High frequency III-V nanowire MOSFETs

    Science.gov (United States)

    Lind, Erik

    2016-09-01

    III-V nanowire transistors are promising candidates for very high frequency electronics applications. The improved electrostatics originating from the gate-all-around geometry allow for more aggressive scaling as compared with planar field-effect transistors, and this can lead to device operation at very high frequencies. The very high mobility possible with In-rich devices can allow very high device performance at low operating voltages. GaN nanowires can take advantage of the large band gap for high voltage operation. In this paper, we review the basic physics and device performance of nanowire field- effect transistors relevant for high frequency performance. First, the geometry of lateral and vertical nanowire field-effect transistors is introduced, with special emphasis on the parasitic capacitances important for nanowire geometries. The basic important high frequency transistor metrics are introduced. Secondly, the scaling properties of gate-all-around nanowire transistors are introduced, based on geometric length scales, demonstrating the scaling possibilities of nanowire transistors. Thirdly, to model nanowire transistor performance, a two-band non-parabolic ballistic transistor model is used to efficiently calculate the current and transconductance as a function of band gap and nanowire size. The intrinsic RF metrics are also estimated. Finally, experimental state-of-the-art nanowire field-effect transistors are reviewed and benchmarked, lateral and vertical transistor geometries are explored, and different fabrication routes are highlighted. Lateral devices have demonstrated operation up to 350 GHz, and vertical devices up to 155 GHz.

  18. Differential multi-MOSFET nuclear radiation sensor

    Science.gov (United States)

    Deoliveira, W. A.

    1977-01-01

    Circuit allows minimization of thermal-drift errors, low power consumption, operation over wide dynamic range, improved sensitivity and stability with metaloxide-semiconductor field-effect transistor sensors.

  19. Development of power MOSFET (150 W class)

    Science.gov (United States)

    Kuboyama, Satoshi; Tamura, Takashi; Uesugi, Masato; Kanno, Tooru

    1992-08-01

    An overview of the power Metal Oxide Semiconductor (MOS) Field Effect Transistor (FET) is presented. Development was being conducted to upgrade radiation resistance without impairing electrical characteristics and to improve chip process design for decreasing on resistance by trading off with switching speed (device capacity) and small package design. Chip design were conducted to decrease the process temperature for increasing total dose resistance, suppress parasitic transistor behavior for augmenting single event resistance, and optimize FET cell structure and dimension for decreasing on resistance. Evaluation test of the trial produced samples was conducted. Package materials were selected and their assembly technologies were established. Evaluation test was conducted especially focusing on the effects of bonding and sealing property, and lead forming. The possibility to provide the engineering model to the JEM (Japanese Experiment Module) project was obtained.

  20. Fulltext PDF

    Indian Academy of Sciences (India)

    results in self-heating, otherwise known as 'boot-strapping', causing the fuel tem- perature to climb from around 10 keV to 70–80 keV in ~10 ps. As the alpha ..... [9] M Tabak et al, Lawrence Livermore National Laboratory patent disclosure, IL8826B. (1997). [10] R Betti, C D Zhou, K S Anderson, L J Perkins, W Theobald and ...

  1. Arthrobacter enclensis sp. nov., isolated from sediment sample

    Digital Repository Service at National Institute of Oceanography (India)

    Dastager, S.G.; Qin, L.; Tang, S.K.; Krishnamurthi, S.; Lee, J.C.; Li, W.J.

    using CLUSTAL_X (Thompson et al. 1997). The phylogenetic trees were constructed using the neighbour-joining (Saitou and Nei 1987), maximum-parsimony (Fitch and Margoliash 1967) and maximum-likelihood (Felsenstein 1981) tree-making algorithm software... packages MEGA version 4.0 (Tamura et al. 2007), PHYLIP version 3.6 (Felsenstein 2002) and PHYML (Guindon and Gascuel 2003). The topologies of the phylogenetic trees were evaluated using the boot- strap resampling method of Felsenstein (1985) with 1...

  2. MODELLING AND SIMULATION OF HIGH FREQUENCY INVERTER FOR INDUCTION HEATING APPLICATION

    OpenAIRE

    SACHIN S. BANKAR; Dr. PRASAD M. JOSHI

    2016-01-01

    This paper presents modelling and simulation of high frequency inverter for induction heating applications. Induction heating has advantages like higher efficiency, controlled heating, safety and pollution free therefore this technology is used in industrial, domestic and medical applications. The high frequency full bridge inverter is used for induction heating, also MOSFET is used as a switching device for inverter and the control strategy used for inverter is Bipolar PWM control. The size ...

  3. Sensors of absorbed dose of ionizing radiation based on mosfet

    Directory of Open Access Journals (Sweden)

    Perevertaylo V. L.

    2010-10-01

    Full Text Available The requirements to technology and design of p-channel and n-channel MOS transistors with a thick oxide layer designed for use in the capacity of integral dosimeters of absorbed dose of ionizing radiation are defined. The technology of radiation-sensitive MOS transistors with a thick oxide in the p-channel and n-channel version is created.

  4. Response of MOSFETs from DMILL technology to high total doses

    International Nuclear Information System (INIS)

    Armani, J.M.; Brisset, C.; Joffre, F.; Dentan, M.

    1999-01-01

    We have studied the behaviour of MOS transistors with DMILL technology submitted to 60 Co gamma radiation. The cumulated dose was 1 MGy(Si) with a dose rate of 1 kGy(Si). The shift of the threshold voltage for an integrated dose beyond 1 MGy(Si) was less than 0.87 V even in the worst case. The analysis of the results shows that the effects of the traps located at the interface Si-SiO 2 become predominant for doses just over a few hundreds kilo-Gray. The weak shift observed enables DMILL-MOS transistors to be validated in civil nuclear applications where cumulated doses may be high. (A.C.)

  5. Radiation hardening of power MOSFETs using electrical stress

    International Nuclear Information System (INIS)

    Picard, C.; Brisset, C.; Quittard, O.; Joffre, F.; Picard, C.; Hoffmann, A.; Charles, J.P.

    1999-01-01

    Application of high voltage electrical stresses to NVDMOSFET-type COTS transistors was explored as an original hardening option. Such pre irradiation treatment enhances transistor response to total dose, with a resulting gain of up to one decade. (authors)

  6. Ultrafast Switching Superjunction MOSFETs for Single Phase PFC Applications

    DEFF Research Database (Denmark)

    Hernandez Botella, Juan Carlos; Petersen, Lars Press; Andersen, Michael A. E.

    2014-01-01

    This paper presents a guide on characterizing state-of-the-art silicon superjunction (SJ) devices in the 600V range for single phase power factor correction (PFC) applications. The characterization procedure is based on a minimally inductive double pulse tester (DPT) with a very low intrusive...... investigates the latest SJ devices in order to set a reference for future research on improvement over silicon (Si) attained with the introduction of wide bandgap devices in single phase PFC applications. The obtained results show that the latest generation of SJ devices set a new benchmark for its wide...

  7. Effects of Lightning Injection on Power-MOSFETs

    Data.gov (United States)

    National Aeronautics and Space Administration — Lightning induced damage is one of the major concerns in aircraft health monitoring. Such short-duration high voltages can cause significant damage to electronic...

  8. MOSFET Replacement Devices for Energy-Efficient Digital Integrated Circuits

    Science.gov (United States)

    2009-12-17

    Actuators Conf. Tech. Dig., Lyon, France , June 10- 14, 2007, pp. 1709–12. [3.11] E. S. Hung and S. D. Senturia, “Generating efficient dynamical models for...Holm and E. Holm, Electric Contacts; Theory and Application, 4th ed. Berlin, Germany: Springer-Verlag, 1967. [5.17] G. Rubio- Bollinger , S. R. Bahn

  9. Accelerated Aging with Electrical Overstress and Prognostics for Power MOSFETs

    Data.gov (United States)

    National Aeronautics and Space Administration — Power electronics play an increasingly important role in energy applications as part of their power converter circuits. Understanding the behavior of these devices,...

  10. Towards Accelerated Aging Methodologies and Health Management of Power MOSFETs

    Data.gov (United States)

    National Aeronautics and Space Administration — Understanding aging mechanisms of electronic components is of extreme importance in the aerospace domain where they are part of numerous critical subsystems...

  11. Towards Modeling the Effects of Lightning Injection on Power MOSFETs

    Data.gov (United States)

    National Aeronautics and Space Administration — Power electronics are widely used in critical roles in modern day aircrafts and hence their health management is of great interest. An important part of prognostics...

  12. Investigation of carrier mobility degradation effects on MOSFET leakage simulations

    CSIR Research Space (South Africa)

    Twala, B

    2016-01-01

    Full Text Available of electric field, carrier temperature and impact ionization. 4. Several vertical grid spacing inside the gate oxide when simulating gate field effects such as gate induced drain leakage (GIDL) or using any hot electron or tunneling gate current models... on its gain and is proportional to the hole or electron mobility (depending on device type); at least for low drain voltages. The transverse field dependent mobility models are of particular importance for simulating MOS devices. Because the reduction...

  13. Work function characterization of electroactive materials using an E MOSFET

    NARCIS (Netherlands)

    Dam, T.V.A.; Olthuis, Wouter; Bergveld, Piet

    2004-01-01

    Materials with redox properties have been widely used in sensing applications. Understanding the redox properties of these materials is an important issue. In order to investigate the redox properties, there are several methods, such as using the Kelvin probe and a conductivity sensor, or using

  14. Modulator reliability and bandwidth improvement: replacing tetrodes with MOSFETs

    International Nuclear Information System (INIS)

    Donaldson, A.R.

    1982-01-01

    Three types of power MOS field effect transistors were studied with the intent of replacing a parallel pair of vacuum tube tetrodes in a linear modulator. The tetrodes have the shortest lifetimes of any other tubes in the system. The FETs offer definite performance advantages when compared to bipolar transistors and definite cost advantages when compared to vacuum tubes. Replacement of the tetrodes does however require careful consideration of voltage, current and to a lesser extent bandwidth capability in order to enhance overall modulator reliability without compromising present performance

  15. Extrinsic gate capacitance compact model for UTBB MOSFETs

    Science.gov (United States)

    Martinez-Lopez, Andrea G.; Tinoco, Julio C.; Lezama, Gamaliel; Conde, Jorge E.; Kazemi Esfeh, Babak; Raskin, Jean-Pierre

    2018-01-01

    Ultra-thin body and buried oxide transistors have gained attention as candidates for near future CMOS technology nodes. Recent studies have pointed out that the total parasitic gate capacitance becomes an important concern for very-high frequency performance. In this paper a semi-analytical model to describe the total extrinsic gate capacitance for ultrathin silicon body and buried oxide transistors is presented. The developed model considers the main technological parameters and has been verified by finite-element numerical simulations as well as by comparison with experimental measurements. The relative weight of the main parasitic components is addressed as well as their impact over the current gain cut-off frequency. Finally, the possibility to improve the cut-off frequency by about 35% due to the reduction of the parasitic gate capacitance is highlighted.

  16. A modified electronic load based on cascode linear MOSFET configuration

    DEFF Research Database (Denmark)

    Farhang, Peyman; Mátéfi-Tempfli, Stefan

    2017-01-01

    rising the switching frequency might not be an efficient approach in terms of design issues, device limitations, electromagnetic noise problems and also complicated gate drive designs. To deal with these obstacles, a novel electronic load based on analog techniques is proposed in this paper. First of all...

  17. Coaching Coaches

    DEFF Research Database (Denmark)

    Hedin, G.; Bendix, Lars Gotfred; Magnusson, B.

    2003-01-01

    We have developed a tandem of undergraduate courses for teaching XP and coaching of XP teams. This paper focuses on the coaching course and the coaching practices we have developed. The tandem of courses enables us to give a challenging and interesting course for the coaches, and, at the same time......, allows us to afford on-site coaches for the younger students, providing them with a high quality environment for learning XP. We also describe our experiences from the first instance of the courses and how we have tackled the boot-strapping problem....

  18. Switching power supply

    Science.gov (United States)

    Mihalka, A.M.

    1984-06-05

    The invention is a repratable capacitor charging, switching power supply. A ferrite transformer steps up a dc input. The transformer primary is in a full bridge configuration utilizing power MOSFETs as the bridge switches. The transformer secondary is fed into a high voltage, full wave rectifier whose output is connected directly to the energy storage capacitor. The transformer is designed to provide adequate leakage inductance to limit capacitor current. The MOSFETs are switched to the variable frequency from 20 to 50 kHz to charge a capacitor from 0.6 kV. The peak current in a transformer primary and secondary is controlled by increasing the pulse width as the capacitor charges. A digital ripple counter counts pulses and after a preselected desired number is reached an up-counter is clocked.

  19. GaN Power Stage for Switch-mode Audio Amplification

    DEFF Research Database (Denmark)

    Ploug, Rasmus Overgaard; Knott, Arnold; Poulsen, Søren Bang

    2015-01-01

    Gallium Nitride (GaN) based power transistors are gaining more and more attention since the introduction of the enhancement mode eGaN Field Effect Transistor (FET) which makes an adaptation from Metal-Oxide Semiconductor (MOSFET) to eGaN based technology less complex than by using depletion mode Ga......N FETs. This project seeks to investigate the possibilities of using eGaN FETs as the power switching device in a full bridge power stage intended for switch mode audio amplification. A 50 W 1 MHz power stage was built and provided promising audio performance. Future work includes optimization of dead...

  20. A Low-Power CMOS Piezoelectric Transducer Based Energy Harvesting Circuit for Wearable Sensors for Medical Applications

    Directory of Open Access Journals (Sweden)

    Taeho Oh

    2017-12-01

    Full Text Available Piezoelectric vibration based energy harvesting systems have been widely utilized and researched as powering modules for various types of sensor systems due to their ease of integration and relatively high energy density compared to RF, thermal, and electrostatic based energy harvesting systems. In this paper, a low-power CMOS full-bridge rectifier is presented as a potential solution for an efficient energy harvesting system for piezoelectric transducers. The energy harvesting circuit consists of two n-channel MOSFETs (NMOS and two p-channel MOSFETs (PMOS devices implementing a full-bridge rectifier coupled with a switch control circuit based on a PMOS device driven by a comparator. With a load of 45 kΩ, the output rectifier voltage and the input piezoelectric transducer voltage are 694 mV and 703 mV, respectably, while the VOUT versus VIN conversion ratio is 98.7% with a PCE of 52.2%. The energy harvesting circuit has been designed using 130 nm standard CMOS process.

  1. Radiation hardening of power MOSFETs using electrical stress; Durcissement a la dose cumulee de MOSFETs de puissance par un stress electrique

    Energy Technology Data Exchange (ETDEWEB)

    Picard, C.; Brisset, C.; Quittard, O.; Joffre, F. [CEA Saclay, Lab. d' Electronique et de Technologie de l' Informatique, LETI, 91 - Gif-sur-Yvette (France); Hoffmann, A.; Charles, J.P. [Centre Lorrain d' Optique et Electronique des Solides, Supelec, 57 - Metz (France)

    1999-07-01

    Application of high voltage electrical stresses to NVDMOSFET-type COTS transistors was explored as an original hardening option. Such pre irradiation treatment enhances transistor response to total dose, with a resulting gain of up to one decade. (authors)

  2. SPICE compatible analytical electron mobility model for biaxial strained-Si-MOSFETs

    International Nuclear Information System (INIS)

    Chaudhry, Amit; Sangwan, S.; Roy, J. N.

    2011-01-01

    This paper describes an analytical model for bulk electron mobility in strained-Si layers as a function of strain. Phonon scattering, columbic scattering and surface roughness scattering are included to analyze the full mobility model. Analytical explicit calculations of all of the parameters to accurately estimate the electron mobility have been made. The results predict an increase in the electron mobility with the application of biaxial strain as also predicted from the basic theory of strain physics of metal oxide semiconductor (MOS) devices. The results have also been compared with numerically reported results and show good agreement. (semiconductor devices)

  3. Device Performance and Reliability Improvements of AlGaBN/GaN/Si MOSFET

    Science.gov (United States)

    2016-02-04

    Methyl- Aluminum (TMA) and H2O precursors decreases the leakage current significantly, the ALD Al2O3 is not effective in the passivation of the native...stability, extends the application of the III- nitride to high temperature and high power. Moreover, because of the close lattice constants and thermal

  4. MOSFET-Only Mixer/IIR Filter with Gain using Parametric Amplification

    DEFF Research Database (Denmark)

    Custódio, José R.; Oliveira, J.; Oliveira, L. B.

    2010-01-01

    This paper describes the design of a discrete-time passive Mixer/IIR filter. The use of an improved MOS Parametric Amplification leads to a moderate gain in the signal path and improved noise performance, instead of the conversion loss inherent to passive mixers. Simulation results demonstrate that...

  5. Ternary rare-earth based alternative gate-dielectrics for future integration in MOSFETs

    Energy Technology Data Exchange (ETDEWEB)

    Schubert, Juergen; Lopes, Joao Marcelo; Durgun Oezben, Eylem; Luptak, Roman; Lenk, Steffi; Zander, Willi; Roeckerath, Martin [IBN 1-IT, Forschungszentrum Juelich, 52425 Juelich (Germany)

    2009-07-01

    The dielectric SiO{sub 2} has been the key to the tremendous improvements in Si-based metal-oxide-semiconductor (MOS) device performance over the past four decades. It has, however, reached its limit in terms of scaling since it exhibits a leakage current density higher than 1 A/cm{sup 2} and does not retain its intrinsic physical properties at thicknesses below 1.5 nm. In order to overcome these problems and keep Moore's law ongoing, the use of higher dielectric constant (k) gate oxides has been suggested. These high-k materials must satisfy numerous requirements such as the high k, low leakage currents, suitable band gap und offsets to silicon. Rare-earth based dielectrics are promising materials which fulfill these needs. We will review the properties of REScO{sub 3} (RE = La, Dy, Gd, Sm, Tb) and LaLuO{sub 3} thin films, grown with pulsed laser deposition, e-gun evaporation or molecular beam deposition, integrated in capacitors and transistors. A k > 20 for the REScO{sub 3} (RE = Dy, Gd) and around 30 for (RE = La, Sm, Tb) and LaLuO{sub 3} are obtained. Transistors prepared on SOI and sSOI show mobility values up to 380 cm{sup 2}/Vs on sSOI, which are comparable to such prepared with HfO{sub 2}.

  6. Simultaneous On-State Voltage and Bond-Wire Resistance Monitoring of Silicon Carbide MOSFETs

    DEFF Research Database (Denmark)

    Baker, Nick; Luo, Haoze; Iannuzzo, Francesco

    2017-01-01

    the voltage between the kelvin-source and power-source can be used to specifically monitor bond-wire degradation. Meanwhile, the drain to kelvin-source voltage can be monitored to track defects in the semiconductor die or gate driver. Through an accelerated aging test on 20 A Silicon Carbide Metal-Oxide-Semiconductor-Field-Effect...

  7. Short-Circuit Degradation of 10-kV 10-A SiC MOSFET

    DEFF Research Database (Denmark)

    Eni, Emanuel-Petre; Beczkowski, Szymon; Munk-Nielsen, Stig

    2017-01-01

    leads to an overall increase in device on-state resistance at the end of the degradation study. Thermal simulation show that the surface aluminum metalization reached its melting temperature and the top part of the device reaches temperatures above the rated junction temperature. Scanning electron...... microscope (SEM) investigation shows aluminum reconstruction and cavities at the contact interface between the aluminum surface metalization and source contacts....

  8. Evaluation of a High Temperature SOI Half-Bridge MOSFET Driver, Type CHT-HYPERION

    Science.gov (United States)

    Patterson, Richard; Hammoud, Ahmad

    2010-01-01

    Silicon-On-Insulator (SOI) technology utilizes the addition of an insulation layer in its structure to reduce leakage currents and to minimize parasitic junctions. As a result, SOIbased devices exhibit reduced internal heating as compared to the conventional silicon devices, consume less power, and can withstand higher operating temperatures. In addition, SOI electronic integrated circuits display good tolerance to radiation by virtue of introducing barriers or lengthening the path for penetrating particles and/or providing a region for trapping incident ionization. The benefits of these parts make them suitable for use in deep space and planetary exploration missions where extreme temperatures and radiation are encountered. Although designed for high temperatures, very little data exist on the operation of SOI devices and circuits at cryogenic temperatures. In this work, the performance of a commercial-off-the-shelf (COTS) SOI half-bridge driver integrated circuit was evaluated under extreme temperatures and thermal cycling. The investigations were carried out to establish a baseline on the functionality and to determine suitability of this device for use in space exploration missions under extreme temperature conditions.

  9. Gate voltage controlled humidity sensing using MOSFET of VO2 particles

    CSIR Research Space (South Africa)

    Akande, Amos A

    2017-01-01

    Full Text Available This article presents gate-voltage controlled humidity sensing performance of vanadium dioxide nanoparticles prepared from NH4VO3 precursor using microwave irradiation technique. The X-ray diffraction, transmission electron diffraction, and Raman...

  10. The Combined Effects of Radio Frequency and Gamma Irradiation on P-Channel MOSFETS

    Science.gov (United States)

    2010-09-01

    voltage.............................................. 34 18. Gamma cell at the OSU research reactor complex...37 19. Dose curve for gamma irradiation cell at OSU’s research reactor facility .................. 38 20. Pre-characterization...maximum width will eventually be reached and is described by: 2 ln 2 A s i m A NkT n W q N ε      = . (9) 16 Precise control of the

  11. Charge pumping at radio frequencies [MOSFET device interface state density measurement

    NARCIS (Netherlands)

    Sasse, G.T.; de Vries, Hendrikus; de Vries, H.; Schmitz, Jurriaan

    In this work, for the first time, charge pump results are shown that are obtained at frequencies in the GHz range. A comparison is made with charge pump results at lower frequencies. A very good agreement is seen between the low frequency charge pump data and the RF charge pump data. Measurement

  12. Comparative study of power mosfet behaviour under the influence of X rays

    International Nuclear Information System (INIS)

    Clarac, J.; Manson, S.

    1986-01-01

    In space applications, such as in converters, the use of MOSPOWER FETS seems to be an interesting solution. Nevertheless, it is necessary to know the behaviour of this kind of component under the influence of ionizing radiations. Those transistors which are made with MOS structures are very susceptible to hard irradiation; when ionizing is absorbed in this structure, electron-hole pairs and created which induce a degradation of the electrical parameters. Ionizing which is located at the interface silicon-oxyde tends to modify the bias conditions. Due to the diversity of technologies proposed by the manufacturers, comparative tests have been made [fr

  13. Microsecond pulsed DC matching measurements on MOSFETs in strong and weak inversion

    NARCIS (Netherlands)

    Andricciola, Pietro; Andricciola, P.; Tuinhout, Hans; Wils, Nicole; Schmitz, Jurriaan

    2011-01-01

    We present a first successful attempt to use microsecond DC pulses for matching measurements on 65-nm MOS transistors down to low current levels. We demonstrate that the interface states that contribute to the mismatch (if they indeed do so) in the weak and moderate inversion region must have

  14. RF capacitance-voltage characterization of MOSFETs with high-leakage dielectric

    NARCIS (Netherlands)

    Schmitz, Jurriaan; Cubaynes, F.N; Cubaynes, F.N.; Havens, R.J.; de Kort, R.; Scholten, A.J.; Tiemeijer, L.F.

    2003-01-01

    We present a MOS Capacitance-Voltage measurement methodology that, contrary to present methods, is highly robust against gate leakage current densities up to 1000 A/cm/sup 2/. The methodology features specially designed RF test structures and RF measurement frequencies. It allows MOS parameter

  15. Reduction of self-heating effect in SOI MOSFET by forming a new buried layer structure

    International Nuclear Information System (INIS)

    Zhu Ming; Lin Qing; Liu Xianghua; Lin Zixin; Zhang Zhengxuan; Lin Chenglu

    2003-01-01

    An inherent self-heating effect of the silicon-on-insulator (SOI) devices limits their application at high current levels. In this paper a novel solution to reduce the self-heating effect is proposed, based on N + and O + co-implantation into silicon wafer to form a new buried layer structure. This new structure was simulated using Medici program, and the temperature distribution and output characteristics were compared with those of the conventional SOI counterparts. As expected, a reduction of self-heating effect in the novel SOI device was observed

  16. Process Parameters Optimization of 14nm MOSFET Using 2-D Analytical Modelling

    Directory of Open Access Journals (Sweden)

    Noor Faizah Z.A.

    2016-01-01

    Full Text Available This paper presents the modeling and optimization of 14nm gate length CMOS transistor which is down-scaled from previous 32nm gate length. High-k metal gate material was used in this research utilizing Hafnium Dioxide (HfO2 as dielectric and Tungsten Silicide (WSi2 and Titanium Silicide (TiSi2 as a metal gate for NMOS and PMOS respectively. The devices are fabricated virtually using ATHENA module and characterized its performance evaluation via ATLAS module; both in Virtual Wafer Fabrication (VWF of Silvaco TCAD Tools. The devices were then optimized through a process parameters variability using L9 Taguchi Method. There were four process parameter with two noise factor of different values were used to analyze the factor effect. The results show that the optimal value for both transistors are well within ITRS 2013 prediction where VTH and IOFF are 0.236737V and 6.995705nA/um for NMOS device and 0.248635 V and 5.26nA/um for PMOS device respectively.

  17. Recent Progress of B-Ga2O3 MOSFETs for Power Electronic Applications

    Science.gov (United States)

    2017-03-20

    A. Fiedler, K. Irmscher, D. Klimm, R. Schewski, and G. Wagner, " Semiconducting Sn-doped beta-Ga2O3 homoepitaxial layers grown by metal organic ...multiple different methods including metal- organic vapor phase epitaxy (MOVPE) [9], Molecular Beam Epitaxy (MBE) [2], and Low Pressure Chemical Vapor

  18. Switching current imbalance mitigation in power modules with parallel connected SiC MOSFETs

    DEFF Research Database (Denmark)

    Beczkowski, Szymon; Jørgensen, Asger Bjørn; Li, Helong

    2017-01-01

    Multichip power modules use parallel connected chips to achieve high current rating. Due to a finite flexibility in a DBC layout, some electrical asymmetries will occur in the module. Parallel connected transistors will exhibit uneven static and dynamic current sharing due to these asymmetries...

  19. The performance study of oxide by-passed(OB) lateral double diffused MOSFET

    Science.gov (United States)

    Tang, Pan-pan

    2016-10-01

    An SOI LDMOS device structure with Oxide By-passed(OB) was investigated and its breakdown mechanism and characteristic of structure was analyzed. Its performance was verified by 3D numerical simulation with SILVACO TCAD software. The simulated results show that the electrical field element of the device is modulated by the concept of similar Superjunction(SJ) structure. Compared with the SJ LDMOS device, OB LDMOS obtains the same breakdown voltage, simultaneously the specific on-resistance of the OB LDMOS reduces from 3.81mΩ·cm2 to 1.96mΩ·cm2, except for achieving comparable performance and overcoming the high aspect ratio of fabrication structure and the difficulty of accurate concentration match of SJ LDMOS.

  20. Less-Conventional Low-Consumption Galvanic Separated MOSFET-IGBT Gate Drive Supply

    Directory of Open Access Journals (Sweden)

    Jean Marie Vianney Bikorimana

    2017-01-01

    Full Text Available A simple half-bridge, galvanic separated power supply which can be short circuit proof is proposed for gate driver local supplies. The supply is made while hacking a common mode type filter as a transformer, as the transformer shows a good insulation, it has a very low parasitic capacitance between primary and secondary coils, and it is cost-effective. Very low standby losses were observed during lab experiments. This makes it compatible with energy efficient drives and solar inverters.

  1. Y-Function Analysis of the Low Temperature Behavior of Ultrathin Film FD SOI MOSFETs

    Directory of Open Access Journals (Sweden)

    A. Karsenty

    2014-01-01

    Full Text Available The respective transfer characteristics of the ultrathin body (UTB and gate recessed channel (GRC device, sharing same W/L ratio but having a channel thickness of 46 nm, and 2.2 nm respectively, were measured at 300 K and at 77 K. By decreasing the temperature we found that the electrical behaviors of these devices were radically opposite: if for UTB device, the conductivity was increased, the opposite effect was observed for GRC. The low field electron mobility and series resistance RSD values were extracted using a method based on Y-function for both the temperatures. If RSD low values were found for UTB, very high values (>1 MΩ were extracted for GRC. Surprisingly, for the last device, the effective field mobility is found very low (<1 cm2/Vs and is decreasing by lowering the temperature. After having discussed the limits of this analysis.This case study illustrates the advantage of the Y-analysis in discriminating a parameter of great relevance for nanoscale devices and gives a coherent interpretation of an anomalous electrical behavior.

  2. Characterisation of a MOSFET-based detector for dose measurement under megavoltage electron beam radiotherapy

    Science.gov (United States)

    Jong, W. L.; Ung, N. M.; Tiong, A. H. L.; Rosenfeld, A. B.; Wong, J. H. D.

    2018-03-01

    The aim of this study is to investigate the fundamental dosimetric characteristics of the MOSkin detector for megavoltage electron beam dosimetry. The reproducibility, linearity, energy dependence, dose rate dependence, depth dose measurement, output factor measurement, and surface dose measurement under megavoltage electron beam were tested. The MOSkin detector showed excellent reproducibility (>98%) and linearity (R2= 1.00) up to 2000 cGy for 4-20 MeV electron beams. The MOSkin detector also showed minimal dose rate dependence (within ±3%) and energy dependence (within ±2%) over the clinical range of electron beams, except for an energy dependence at 4 MeV electron beam. An energy dependence correction factor of 1.075 is needed when the MOSkin detector is used for 4 MeV electron beam. The output factors measured by the MOSkin detector were within ±2% compared to those measured with the EBT3 film and CC13 chamber. The measured depth doses using the MOSkin detector agreed with those measured using the CC13 chamber, except at the build-up region due to the dose volume averaging effect of the CC13 chamber. For surface dose measurements, MOSkin measurements were in agreement within ±3% to those measured using EBT3 film. Measurements using the MOSkin detector were also compared to electron dose calculation algorithms namely the GGPB and eMC algorithms. Both algorithms were in agreement with measurements to within ±2% and ±4% for output factor (except for the 4 × 4 cm2 field size) and surface dose, respectively. With the uncertainties taken into account, the MOSkin detector was found to be a suitable detector for dose measurement under megavoltage electron beam. This has been demonstrated in the in vivo skin dose measurement on patients during electron boost to the breast tumour bed.

  3. 'Switched Biasing' reduces both MOSFET 1/f Noise and Power consumption

    NARCIS (Netherlands)

    Gierkink, Sander L.J.; Klumperink, Eric A.M.; van Tuijl, Adrianus Johannes Maria; Nauta, Bram

    1999-01-01

    “Switched Biasing” is proposed as a new circuit technique that exploits an intriguing physical effect: cycling a MOS transistor between strong inversion and accumulation reduces its intrinsic 1/f noise. The technique is implemented in a 0.8mm CMOS sawtooth oscillator by periodically off-switching of

  4. Reducing MOSFET 1/f Noise and Power Consumption by 'switched biasing'

    NARCIS (Netherlands)

    Gierkink, Sander L.J.; Klumperink, Eric A.M.; van Tuijl, Adrianus Johannes Maria; Nauta, Bram

    1999-01-01

    "Switched Biasing" is proposed as a new circuit technique that exploits an intriguing physical effect: cycling a MOS transistor between strong inversion and accumulation reduces its intrinsic 1/f noise. The technique is implemented in a 0.8µm CMOS sawtooth oscillator by periodically off-switching of

  5. Distribution of electron traps in SiO2/HfO2 nMOSFET

    Science.gov (United States)

    Xiao-Hui, Hou; Xue-Feng, Zheng; Ao-Chen, Wang; Ying-Zhe, Wang; Hao-Yu, Wen; Zhi-Jing, Liu; Xiao-Wei, Li; Yin-He, Wu

    2016-05-01

    In this paper, the principle of discharge-based pulsed I-V technique is introduced. By using it, the energy and spatial distributions of electron traps within the 4-nm HfO2 layer have been extracted. Two peaks are observed, which are located at ΔE ˜ -1.0 eV and -1.43 eV, respectively. It is found that the former one is close to the SiO2/HfO2 interface and the latter one is close to the gate electrode. It is also observed that the maximum discharge time has little effect on the energy distribution. Finally, the impact of electrical stress on the HfO2 layer is also studied. During stress, no new electron traps and interface states are generated. Meanwhile, the electrical stress also has no impact on the energy and spatial distribution of as-grown traps. The results provide valuable information for theoretical modeling establishment, material assessment, and reliability improvement for advanced semiconductor devices. Project supported by the National Natural Science Foundation of China (Grant Nos. 61334002, 61106106, and 61474091), the New Experiment Development Funds for Xidian University, China (Grant No. SY1434), and the Scientific Research Foundation for the Returned Overseas Chinese Scholars, State Education Ministry, China (Grant No. JY0600132501).

  6. Class D amplifier for a power piezoelectric load.

    Science.gov (United States)

    Agbossou, K; Dion, J L; Carignan, S; Abdelkrim, M; Cheriti, A

    2000-01-01

    We present a high efficiency inverter (>90%) that can drive an acoustic cavitation reactor with a 2 kW power between 10 and 100 kHz. This reactor is composed of numerous piezoelectric transducers and is particularly used to accelerate various industrial chemical reactions and destroy a variety of organic contaminants in water. The class-D amplifier or inverter is composed of power MOSFETs, type IRFP460, in a full bridge configuration driven by IR2110 circuits in bootstrap mode. The specific nature of the problem comes from the fact that, at frequencies slightly different from a resonant frequency frn, the load is mostly capacitive. The insertion of an appropriate low-pass filter in front of the load allowed an efficient solution to the problem due to the load being capacitive for harmonics. The realized system can provide nearly 2 kW to this type of piezoelectric load, with an efficiency of more than 95%

  7. Design of inverters for the PHOTONERGY project

    Energy Technology Data Exchange (ETDEWEB)

    NONE

    2003-08-01

    The PHOTONERGY project (the former SolcelleInverter project) was initiated on the 1st of September 2001, with a state-of-the-art analysis, which concluded into specifications. Based on this 23 topologies were analyzed in for efficiencies. The results from this analysis was five candidates which all showed a somewhat good efficiency. These five topologies were in further investigated by means of an initial design-iteration and simulations. Two different solutions were picked up in due to their high efficiency and low cost. 1. The standard full-bridge phase shifted DC/DC converter together with a standard DC/AC inverter, 2. A modified version of the novel Shimizu topology. A patent is pending on this modified version. These two inverters are in this document developed and made ready for prototyping. This includes design and selection of reactive- and switching-components, e.g. filter- and bulk-capacitors, low- and high-frequency inductors, high frequency transformers, MOSFETs and diodes. The design of auxiliary circuits is also included, e.g. gate drivers for the MOSFETs, measuring circuits for the grid-current and -voltage, PV-module-current and voltage, protection circuits, hardware near controllers and finally a switch mode power supply. However, the design of the various controllers, except the hardware near PV-current controller for the full bridge phase shifted converter, is not documented in this report but will come later on. This includes all controllers, e.g. maximum power point tracking for the PV-module, utility grid current controller, DC-link voltage controller, phase locked loops, and detection of islanding operation. All of these control loops are to be implemented in a micro-controller. (au)

  8. Capacitor charging FET switcher with controller to adjust pulse width

    Science.gov (United States)

    Mihalka, Alex M.

    1986-01-01

    A switching power supply includes an FET full bridge, a controller to drive the FETs, a programmable controller to dynamically control final output current by adjusting pulse width, and a variety of protective systems, including an overcurrent latch for current control. Power MOSFETS are switched at a variable frequency from 20-50 kHz to charge a capacitor load from 0 to 6 kV. A ferrite transformer steps up the DC input. The transformer primary is a full bridge configuration with the FET switches and the secondary is fed into a high voltage full wave rectifier whose output is connected directly to the energy storage capacitor. The peak current is held constant by varying the pulse width using predetermined timing resistors and counting pulses. The pulse width is increased as the capacitor charges to maintain peak current. A digital ripple counter counts pulses, and after the desired number is reached, an up-counter is clocked. The up-counter output is decoded to choose among different resistors used to discharge a timing capacitor, thereby determining the pulse width. A current latch shuts down the supply on overcurrent due to either excessive pulse width causing transformer saturation or a major bridge fault, i.e., FET or transformer failure, or failure of the drive circuitry.

  9. Electrical Properties of Ultrathin Hf-Ti-O Higher k Gate Dielectric Films and Their Application in ETSOI MOSFET.

    Science.gov (United States)

    Xiong, Yuhua; Chen, Xiaoqiang; Wei, Feng; Du, Jun; Zhao, Hongbin; Tang, Zhaoyun; Tang, Bo; Wang, Wenwu; Yan, Jiang

    2016-12-01

    Ultrathin Hf-Ti-O higher k gate dielectric films (~2.55 nm) have been prepared by atomic layer deposition. Their electrical properties and application in ETSOI (fully depleted extremely thin SOI) PMOSFETs were studied. It is found that at the Ti concentration of Ti/(Ti + Hf) ~9.4%, low equivalent gate oxide thickness (EOT) of ~0.69 nm and acceptable gate leakage current density of 0.61 A/cm 2 @ (V fb  - 1)V could be obtained. The conduction mechanism through the gate dielectric is dominated by the F-N tunneling in the gate voltage range of -0.5 to -2 V. Under the same physical thickness and process flow, lower EOT and higher I on /I off ratio could be obtained while using Hf-Ti-O as gate dielectric compared with HfO 2 . With Hf-Ti-O as gate dielectric, two ETSOI PMOSFETs with gate width/gate length (W/L) of 0.5 μm/25 nm and 3 μm/40 nm show good performances such as high I on , I on /I off ratio in the magnitude of 10 5 , and peak transconductance, as well as suitable threshold voltage (-0.3~-0.2 V). Particularly, ETSOI PMOSFETs show superior short-channel control capacity with DIBL <82 mV/V and subthreshold swing <70 mV/decade.

  10. Effects on selective epitaxial growth of strained-SiGe p-MOSFETs on various (001) Si recess structures

    Science.gov (United States)

    Hong, Min-Hao; Perng, Dung-Ching

    2017-12-01

    Influences of source and drain recess structures on SiGe epitaxy growth, SiGe step height, facet formation, I D,sat and resistance performance are investigated. Growth rate of SiGe height increases with decreased recess width at a fixed depth of 62 nm. Under a fixed recess width of 96.3 nm, the deeper the recess, the higher the growth rate of SiGe height. An increase in the depth/width ratio of the recessed Si geometry may promote SiGe {001} growth. Upon the recess, SiGe step height is influenced by the initial SiGe orientation. A longer {001} facet of SiGe initial orientation causes a higher growth rate of SiGe step height. Higher IDsat and lower resistance can be achieved by increasing SiGe volume with wider recess width, deeper recess depth, and higher SiGe step height.

  11. Radiation-Induced Short Channel (RISCE) and Narrow Channel (RINCE) Effects in 65 and 130 nm MOSFETs

    CERN Document Server

    Faccio, F; Cornale, D; Paccagnella, A; Gerardin, S

    2015-01-01

    The behavior of transistors in commercial-grade complementary metal-oxide semiconductor technologies in the 65 and 130 nm nodes has been explored up to a total ionizing dose of 1 Grad. The large dose tolerance of the thin gate oxide is confirmed, but defects in the spacer and STI oxides have a strong effect on the performance of the transistors. A radiation-induced short channel effect is traced to charge trapping in the spacers used for drain engineering, while a radiation-induced narrow channel effect is due to defect generation in the lateral isolation oxide (STI). These strongly degrade the electrical characteristics of short and narrow channel transistors at high doses, and their magnitude depends on the applied bias and temperature during irradiation in a complex way.

  12. Reduction of parasitic capacitance in 10 kV SiC MOSFET power modules using 3D FEM

    DEFF Research Database (Denmark)

    Jørgensen, Asger Bjørn; Christensen, Nicklas; Dalal, Dipen Narendrabhai

    2017-01-01

    the output node and the grounded heat sink for a custom silicon carbide power module. A circuit model of the capacitive coupling path is presented, using parasitic capacitances extracted from ANSYS Q3D. Simulated values are compared with experimental results. A new iteration of the silicon carbide power...

  13. SiC JFET Cascode Loss Dependency on the MOSFET Output Capacitance and Performance Comparison with Trench IGBTs

    DEFF Research Database (Denmark)

    Pittini, Riccardo; Zhang, Zhe; Andersen, Michael A. E.

    2013-01-01

    In power electronics there is a general trend to increase converters efficiencies and power densities; for this reason new power semiconductors based on materials such as Silicon Carbide (SiC) and Gallium Nitride (GaN) are becoming more popular. This is especially valid for renewable energies...... output capacitance on the switching performance of the SiC Cascode connection in terms of switching energy loss, dV/dt and dI/dt stresses. The Cascode connection switching performances are compared with the switching performance latest Trench IGBTs. The analysis is based on a set of several laboratory...

  14. Response of MOSFETs from DMILL technology to high total doses; Comportement de la technologie CMOS DMILL aux fortes doses cumulees

    Energy Technology Data Exchange (ETDEWEB)

    Armani, J.M.; Brisset, C.; Joffre, F. [CEA Saclay, Dept. d' Electronique et d' Instrumentation Nucleaire, LETI, 91 - Gif-sur-Yvette (France); Dentan, M. [CEA Saclay, Dept. d' Astrophysique, de Physique des Particules, de Physique Nucleaire et de l' Instrumentation Associee, 91 - Gif sur Yvette (France)

    1999-07-01

    We have studied the behaviour of MOS transistors with DMILL technology submitted to {sup 60}Co gamma radiation. The cumulated dose was 1 MGy(Si) with a dose rate of 1 kGy(Si). The shift of the threshold voltage for an integrated dose beyond 1 MGy(Si) was less than 0.87 V even in the worst case. The analysis of the results shows that the effects of the traps located at the interface Si-SiO{sub 2} become predominant for doses just over a few hundreds kilo-Gray. The weak shift observed enables DMILL-MOS transistors to be validated in civil nuclear applications where cumulated doses may be high. (A.C.)

  15. DotFETs : MOSFETs strained by a Single SiGE dot in a Low-Temperature ELA Technology

    NARCIS (Netherlands)

    Biasotto, C.

    2011-01-01

    The work presented in this thesis was performed in the context of the European Sixth Framework Program FP6 project “Disposable Dot Field Effect Transistor for High Speed Si Integrated Circuits”, referred to as the D-DotFET project. The project had the goal of realizing strain-enhanced mobility in

  16. Single-Event Effects in Power MOSFETs During Heavy Ion Irradiations Performed After Gamma-Ray Degradation

    Science.gov (United States)

    Busatto, G.; De Luca, V.; Iannuzzo, F.; Sanseverino, A.; Velardi, F.

    2013-10-01

    The robustness of commercial power metal-oxide semiconductor field-effect transistors to combined gamma-heavy ion irradiation has been investigated, evidence that the degradation of the gate oxide caused by the γ irradiation can severely corrupt the robustness to single-event effects and drastically modify the physical behavior of the device under test after the impact of a heavy ion. A decrease of the critical voltages at which destructive burnouts and gate ruptures for heavy ion impact appear, has been detected in the devices under test, which were previously irradiated with γ rays. In addition, the amount of critical voltage reduction is strictly related to the amount of the absorbed γ-ray dose. Furthermore, at the failure voltage, the behavior of the device is affected by the conduction of a current through the gate oxide. Moreover, the single-event gate rupture” of the device appears at lower voltages because of the reduction of the Fowler-Nordheim limit in the γ-irradiated devices.

  17. Subthreshold Current and Swing Modeling of Gate Underlap DG MOSFETs with a Source/Drain Lateral Gaussian Doping Profile

    Science.gov (United States)

    Singh, Kunal; Kumar, Sanjay; Goel, Ekta; Singh, Balraj; Kumar, Mirgender; Dubey, Sarvesh; Jit, Satyabrata

    2017-01-01

    This paper proposes a new model for the subthreshold current and swing of the short-channel symmetric underlap ultrathin double gate metal oxide field effect transistors with a source/drain lateral Gaussian doping profile. The channel potential model already reported earlier has been utilized to formulate the closed form expression for the subthreshold current and swing of the device. The effects of the lateral straggle and geometrical parameters such as the channel length, channel thickness, and oxide thickness on the off current and subthreshold slope have been demonstrated. The devices with source/drain lateral Gaussian doping profiles in the underlap structure are observed to be highly resistant to short channel effects while improving the current drive. The proposed model is validated by comparing the results with the numerical simulation data obtained by using the commercially available ATLAS™, a two-dimensional (2-D) device simulator from SILVACO.

  18. Experimental Determination of Quantum and Centroid Capacitance in Arsenide-Antimonide Quantum-Well MOSFETs Incorporating Nonparabolicity Effect

    Science.gov (United States)

    2011-05-01

    14]. While extracting the effective mass from SdH oscillations, the background magnetoresistance was corrected as follows. The envelope of maxima... magnetoresistance that was subtracted from the measured ρXX. Fig. 10 shows the periodic SdH oscillations in ΔρXX/ρ0 (after removing the background...demonstration of metal gate plasmon screening and channel strain engineering in high-κ/metal-gate CMOS transistors, and the investigation of the

  19. An empirical comparison of isolate-based and sample-based definitions of antimicrobial resistance and their effect on estimates of prevalence.

    Science.gov (United States)

    Humphry, R W; Evans, J; Webster, C; Tongue, S C; Innocent, G T; Gunn, G J

    2018-02-01

    Antimicrobial resistance is primarily a problem in human medicine but there are unquantified links of transmission in both directions between animal and human populations. Quantitative assessment of the costs and benefits of reduced antimicrobial usage in livestock requires robust quantification of transmission of resistance between animals, the environment and the human population. This in turn requires appropriate measurement of resistance. To tackle this we selected two different methods for determining whether a sample is resistant - one based on screening a sample, the other on testing individual isolates. Our overall objective was to explore the differences arising from choice of measurement. A literature search demonstrated the widespread use of testing of individual isolates. The first aim of this study was to compare, quantitatively, sample level and isolate level screening. Cattle or sheep faecal samples (n=41) submitted for routine parasitology were tested for antimicrobial resistance in two ways: (1) "streak" direct culture onto plates containing the antimicrobial of interest; (2) determination of minimum inhibitory concentration (MIC) of 8-10 isolates per sample compared to published MIC thresholds. Two antibiotics (ampicillin and nalidixic acid) were tested. With ampicillin, direct culture resulted in more than double the number of resistant samples than the MIC method based on eight individual isolates. The second aim of this study was to demonstrate the utility of the observed relationship between these two measures of antimicrobial resistance to re-estimate the prevalence of antimicrobial resistance from a previous study, in which we had used "streak" cultures. Boot-strap methods were used to estimate the proportion of samples that would have tested resistant in the historic study, had we used the isolate-based MIC method instead. Our boot-strap results indicate that our estimates of prevalence of antimicrobial resistance would have been

  20. Sparsity-based Poisson denoising with dictionary learning.

    Science.gov (United States)

    Giryes, Raja; Elad, Michael

    2014-12-01

    The problem of Poisson denoising appears in various imaging applications, such as low-light photography, medical imaging, and microscopy. In cases of high SNR, several transformations exist so as to convert the Poisson noise into an additive-independent identically distributed. Gaussian noise, for which many effective algorithms are available. However, in a low-SNR regime, these transformations are significantly less accurate, and a strategy that relies directly on the true noise statistics is required. Salmon et al took this route, proposing a patch-based exponential image representation model based on Gaussian mixture model, leading to state-of-the-art results. In this paper, we propose to harness sparse-representation modeling to the image patches, adopting the same exponential idea. Our scheme uses a greedy pursuit with boot-strapping-based stopping condition and dictionary learning within the denoising process. The reconstruction performance of the proposed scheme is competitive with leading methods in high SNR and achieving state-of-the-art results in cases of low SNR.

  1. Event-Triggered Distributed Control of Nonlinear Interconnected Systems Using Online Reinforcement Learning With Exploration.

    Science.gov (United States)

    Narayanan, Vignesh; Jagannathan, Sarangapani

    2017-09-07

    In this paper, a distributed control scheme for an interconnected system composed of uncertain input affine nonlinear subsystems with event triggered state feedback is presented by using a novel hybrid learning scheme-based approximate dynamic programming with online exploration. First, an approximate solution to the Hamilton-Jacobi-Bellman equation is generated with event sampled neural network (NN) approximation and subsequently, a near optimal control policy for each subsystem is derived. Artificial NNs are utilized as function approximators to develop a suite of identifiers and learn the dynamics of each subsystem. The NN weight tuning rules for the identifier and event-triggering condition are derived using Lyapunov stability theory. Taking into account, the effects of NN approximation of system dynamics and boot-strapping, a novel NN weight update is presented to approximate the optimal value function. Finally, a novel strategy to incorporate exploration in online control framework, using identifiers, is introduced to reduce the overall cost at the expense of additional computations during the initial online learning phase. System states and the NN weight estimation errors are regulated and local uniformly ultimately bounded results are achieved. The analytical results are substantiated using simulation studies.

  2. Personal resilience resources predict post-stem cell transplant cancer survivors' psychological outcomes through reductions in depressive symptoms and meaning-making.

    Science.gov (United States)

    Campo, Rebecca A; Wu, Lisa M; Austin, Jane; Valdimarsdottir, Heiddis; Rini, Christine

    2017-01-01

    This longitudinal study examined whether post-transplant cancer survivors (N = 254, 9 months to 3 years after stem cell transplant treatment) with greater personal resilience resources demonstrated better psychological outcomes and whether this could be attributed to reductions in depressive symptoms and/or four meaning-making processes (searching for and finding reasons for one's illness; searching for and finding benefit from illness). Hierarchical linear regression analyses examined associations of survivors' baseline personal resilience resources (composite variable of self-esteem, mastery, and optimism), which occurred an average of 1.7 years after transplant, and 4-month changes in psychological outcomes highly relevant to recovering from this difficult and potentially traumatic treatment: post-traumatic stress disorder (PTSD) symptoms and purpose in life. Boot-strapped analyses tested mediation. Greater personal resilience resources predicted decreases in PTSD stress symptoms (b = -0.07, p = 0.005), mediated by reductions in depressive symptoms (b = -0.01, 95% CI: -0.027, -0.003) and in searching for a reason for one's illness (b = -0.01, 95% CI: -0.034, -0.0003). In addition, greater resilience resources predicted increases in purpose in life (b = 0.10, p meaning-making (searching for a reason for one's illness) was also important for reducing PTSD symptoms.

  3. Elevation of three subspecies of Lonsdalea quercina to species level: Lonsdalea britannica sp. nov., Lonsdalea iberica sp. nov. and Lonsdalea populi sp. nov.

    Science.gov (United States)

    Li, Yong; Xue, Han; Guo, Li-Min; Koltay, András; Palacio-Bielsa, Ana; Chang, Jupu; Xie, Shoujiang; Yang, Xuqi

    2017-11-01

    Four subspecies of Lonsdalea quercina (L. quercina subsp. quercina, L. quercina subsp. britannica, L. quercina subsp. iberica and L. quercina subsp. populi) were studied by genome sequence-derived average nucleotide identity (ANI), phylogenetic analysis based on 16S rRNA gene sequences, multilocus sequence analysis (MLSA) and phenotypic characteristics. In phylogenetic trees, based on 16S rRNA gene sequences, and in MLSA data, the four subspecies were divided into four subclusters in the Lonsdalea clade with high boot strap support. The ANI values between the four subspecies were 88.71-93.38 %, respectively, lower than the proposed species boundary ANI cut-off (95-96 %) that is considered the most important criterion to reclassify these subspecies at the species level. It is proposed that three subspecies be elevated to the species level as Lonsdalea britannica sp. nov. (type strain R-43280 T =LMG 26267 T =NCPPB 4481 T =CFCC 10822 T ), Lonsdalea iberica sp. nov. (type strain R-44166 T =LMG 26264 T =NCPPB 4490 T =CFCC 10824 T ) and Lonsdalea populi sp. nov. (type strain NY060 T =DSM 25466 T =NCAIM B 02483 T =LMG 27349 T =CFCC 13125 T ).

  4. Three Years Measuring Sediment Erosion and Deposition from the Largest Dam Removal Ever at Weekly-­to-­Monthly Scales Using SfM: Elwha River, Washington, USA.

    Science.gov (United States)

    Ritchie, A.; Randle, T. J.; Bountry, J.; Warrick, J. A.

    2015-12-01

    The stepwise removal of two dams on the Elwha River beginning in September 2011 exposed ~21 million cubic meters of sediment to fluvial erosion and created an unprecedented opportunity to monitor reservoir sediment erosion and river evolution during base level adjustment and a pulsed sediment release. We have conducted more than 60 aerial surveys with a Cessna 172 using a simple custom wing-mount for consumer grade cameras and SfM photogrammetry to produce orthoimagery and digital elevation models in near-real-time at weekly to monthly time intervals. Multiple lidar flights and ground survey campaigns have provided estimates of both systematic and random error for this uniquely dense dataset. Co-registration of multiple surveys during processing reduces systematic error and allows boot-strapping of subsequently established ground control to earlier flights. Measurements chronicle the erosion of 12 million cubic meters of reservoir sediment and record corresponding changes in channel braiding, wood loading and bank erosion. These data capture reservoir and river channel responses to dam removal at resolutions comparable to hydrologic forcing events, allowing us to quantify reservoir sediment budgets on a per-storm basis. This allows for the analysis of sediment transported relative to rates of reservoir drawdown and river stream power for dozens of intervals of time. Temporal decoupling of peak sediment flux and bank erosion rates is noted from these analyses. This dataset illustrates some of the challenges and opportunities emerging with the advent of big data in remote sensing of earth surface processes.

  5. Increased CSF-BACE1 activity associated with decreased hippocampus volume in Alzheimer's disease.

    LENUS (Irish Health Repository)

    Ewers, Michael

    2012-02-01

    The enzyme beta-secretase (BACE1) is essentially involved in the production of cerebral amyloidogenic pathology in Alzheimer\\'s disease (AD). The measurement of BACE1 activity in cerebrospinal fluid (CSF) has been reported, which may render CSF measurement of BACE1 a potential biomarker candidate of AD. In order to investigate whether BACE1 protein activity is correlated with regional brain atrophy in AD, we investigated the association between CSF levels of BACE1 and MRI-assessed hippocampus volume in patients with AD (n = 30). An increase in CSF-BACE1 activity was associated with decreased left and right hippocampus volume corrected for global head volume in the AD patients. Boot-strapped regression analysis showed that increased CSF levels of BACE1 activity were associated with increased CSF concentration of total tau but not amyloid-beta1-42 in AD. White matter hyperintensities did not influence the results. BACE1 activity and protein levels were significantly increased in AD compared to 19 elderly healthy controls. Thus, the CSF biomarker candidate of BACE1 activity was associated with hippocampus atrophy in AD in a robust manner and may reflect neurotoxic amyloid-beta-related processes.

  6. Penguat Audio Kelas D dengan Umpan Balik Tipe Butterworth

    Directory of Open Access Journals (Sweden)

    Gunawan Dewantoro

    2016-03-01

    Full Text Available A class D amplifier would, in ideal sense, amplify signals without any noises and distortions which yield 100% efficiency and 0% Total Harmonic Distortion (THD. However, class D amplifiers have some drawbacks that lead to nonlinearity and increasing THD. Therefore, a feedback mechanism was employed to enhance THD performance of amplifier. Some feedback techniques have been using first order filter in the feedback path to retrieve audio signals. This research proposed a second order filter with Butterworth approach. A power amplifier was realized using full-bridge amplifier with MOSFETs to provide greater power. This class D amplifier was designed to meet following specifications: maximum output power up to 32.6 W with an 8 Ω load, sensitivity of 90 mV/W, frequency response ranging from 20 Hz – 20 kHz with tolerance ± 1 dB, THD as low as 1.1 %, SNR up to 90.16 dB, and efficiency of 82.1 %.

  7. Acoustic Emission and Echo Signal Compensation Techniques Applied to an Ultrasonic Logging-While-Drilling Caliper.

    Science.gov (United States)

    Yao, Yongchao; Ju, Xiaodong; Lu, Junqiang; Men, Baiyong

    2017-06-10

    A logging-while-drilling (LWD) caliper is a tool used for the real-time measurement of a borehole diameter in oil drilling engineering. This study introduces the mechanical structure and working principle of a new LWD caliper based on ultrasonic distance measurement (UDM). The detection range is a major performance index of a UDM system. This index is determined by the blind zone length and remote reflecting interface detection capability of the system. To reduce the blind zone length and detect near the reflecting interface, a full bridge acoustic emission technique based on bootstrap gate driver (BGD) and metal-oxide-semiconductor field effect transistor (MOSFET) is designed by analyzing the working principle and impedance characteristics of a given piezoelectric transducer. To detect the remote reflecting interface and reduce the dynamic range of the received echo signals, the relationships between the echo amplitude and propagation distance of ultrasonic waves are determined. A signal compensation technique based on time-varying amplification theory, which can automatically change the gain according to the echo arrival time is designed. Lastly, the aforementioned techniques and corresponding circuits are experimentally verified. Results show that the blind zone length in the UDM system of the LWD caliper is significantly reduced and the capability to detect the remote reflecting interface is considerably improved.

  8. TIG welding power supply with improved efficiency

    Directory of Open Access Journals (Sweden)

    Сергій Володимирович Гулаков

    2015-03-01

    Full Text Available In the article, the influence of the DC component of the welding current during TIG (Tungsten Inert Gas welding is discussed. Known methods of DC current cancellation are reviewed, such as capacitor bank or diode/thyristor network insertion in the secondary circuit of the welding transformer. A new method of controlling the magnitude and shape of the TIG welding current is proposed. The idea is to insert a controlled voltage source in the secondary circuit of the welding transformer. This controlled voltage source is realized using a full-bridge voltage source inverter (VSI. VSI control system design issues are discussed. VSI is controlled by a three-level hysteretic current controller, while current reference is generated using lookup table driven by PLL (Phase Locked Loop locked to the mains frequency. Simulation results are shown. The proposed topology of TIG power supply allows to provide magnitude and shape control of the welding current, with the limitation that its DC component must be zero. Thus, some capabilities of professional AC-TIG welders are obtained using substantially lower cost components: VSI built using high-current low voltage MOSFETs with control system based on 32-bit ARM microcontroller. The use of proposed TIG welding power supply will eliminate the DC component of the welding current, improve welding transformer’s power factor and improve welding technology by increasing the welding arc stability

  9. Influence of Design and Process Parameters of 32-nm Advanced-Process High- k p-MOSFETs on Negative-Bias Temperature Instability and Study of Defects

    Science.gov (United States)

    Alimin, A. F. Muhammad; Radzi, A. A. Mohd; Sazali, N. A. F.; Hatta, S. F. Wan Muhamad; Soin, N.; Hussin, H.

    2017-10-01

    Negative-bias temperature instability (NBTI) has become a prominent factor limiting scaling of complementary metal-oxide-semiconductor technology. This work presents a comprehensive simulation study on the effects of critical design parameters of 32-nm advanced-process high- k p-channel metal-oxide-semiconductor field-effect transistors on NBTI. The NBTI mechanism and defects were explored for various geometric and process design parameters over a wide range of values. The NBTI simulation method applied in this work follows the on-the-fly method to capture the mechanisms of fast and slow traps. This work illustrates the dependence of the threshold voltage ( V th) degradation on the stress oxide field and stress temperature as well as investigation of the Arrhenius plot for the devices. The temperature insensitivity during short stress time of 1 ms indicates absence of generated defects and presence of preexisting defects. It is also observed that significant defects are generated in the gate stack subsequent to NBTI. The slope obtained from the V th degradation analysis at 1 ks and 375°C shows that changing the SiO2 interfacial layer thickness affects the V th degradation by 96.16% more than changing the HfO2 thickness and by 80.67% more than changing the metal gate thickness. It is also found that the NBTI effect depends on process design considerations, specifically the boron concentration in the highly doped drain, the metal gate work function, and the halo doping concentration; it was observed that higher boron dose and high metal work function may lead to higher V th degradation. However, the halo doping concentration in the advanced 32-nm structure has an insignificant effect on NBTI.

  10. Device Performance and Reliability Improvements of AlGaN/GaN/Si MOSFET Using Defect-Free Gate Recess and Laser Annealing

    Science.gov (United States)

    2015-02-15

    M.L. Green, M.-Y. Ho , B. Busch, G.D. Wilk, T. Sorsch, T. Conard, B. Brijs, W. Vandervorst, P.I. Räisänen, D. Muller, M. Bude, and J. Grazul, J...Miczek, and T. Hashizume, Jpn. J. Appl. Phys. 50, 021001 (2011). 2 T.H. Hung, S. Krishnamoorthy, M. Esposto, D. Neelim Nath, P. Sung Park, and S...Brunner, E.-M. Cho , T. Hashizume, and J. Kuzmík, J. Appl. Phys. 116, 104501 (2014). 24 Z. Yatabe, Y. Hori, W. Ma, J.T. Asubar, M. Akazawa, T. Sato, and T

  11. Fabrication of 4H-SiC lateral double implanted MOSFET on an on-axis semi-insulating substrate without using epi-layer

    Science.gov (United States)

    Kim, Hyoung Woo; Seok, Ogyun; Moon, Jeong Hyun; Bahng, Wook; Jo, Jungyol

    2017-12-01

    4H-SiC lateral double implanted metal-oxide-semiconductor field effect transistors (LDIMOSFET) were fabricated on on-axis semi-insulating SiC substrates without using an epi-layer. The LDIMOSFET adopted a current path layer (CPL), which was formed by ion-implantation. The CPL works as a drift region between gate and drain. By using on-axis semi-insulating substrate and optimized CPL parameters, breakdown voltage (BV) of 1093 V and specific on-resistance (R on,sp) of 89.8 mΩ·cm2 were obtained in devices with 20 µm long CPL. Experimentally extracted field-effect channel mobility was 21.7 cm2·V-1·s-1 and the figure-of-merit (BV2/R on,sp) was 13.3 MW/cm2.

  12. Optimized spin-injection efficiency and spin MOSFET operation based on low-barrier ferromagnet/insulator/n-Si tunnel contact

    Science.gov (United States)

    Yang, Yang; Wu, Zhenhua; Yang, Wen; Li, Jun; Chen, Songyan; Li, Cheng

    2017-06-01

    We theoretically investigate the spin injection in different ferromagnet/insulator/n-Si tunnel contacts by using the lattice non-equilibrium Green’s function method. We find that the tunnel contacts with low-barrier materials such as TiO2 and Ta2O5 have far lower resistances than the conventional-barrier materials, resulting in a wider and attainable optimum parameters window for improving the spin-injection efficiency and magnetoresistance ratio of a vertical-spin metal-oxide-semiconductor field-effect transistor. Additionally, we find that the spin-asymmetry coefficient of the TiO2 tunnel contact has a negative value, while that of the Ta2O5 contact can be tuned between positive and negative values by changing the parameters.

  13. Faktor-faktor yang Memengaruhi Perilaku Penggunaan Internet Masyarakat Desa

    Directory of Open Access Journals (Sweden)

    Anton Susanto

    2016-03-01

    Full Text Available Abstrak Penyediaan akses dan sarana TIK (internet bagi masyarakat desa bertujuan tidak hanya mengurangi kesenjangan digital tetapi juga untuk dapat mendorong aktivitas dan produktivitas masyarakat (pemberdayaan. Kehadiran internet di masyarakat desa belum tentu menjadi sebuah kebutuhan, baik karena rendahnya kesadaran akan manfaatnya ataupun tidak terhubungnya internet dengan sistem nafkah yang ada di masyarakat pedesaan. Upaya mendekatkan ketersediaan internet dengan kebutuhan riil masyarakat dapat dilakukan dengan pendekatan psychological empowerment, yaitu TIK harus dikaitkan dengan faktor intrapersonal, interaksional dan faktor perilaku masyarakat. Perilaku penggunaan internet dianalisis secara kuantitatif dengan menggunakan variabel Niat Menggunakan (behavioral intention sebagai penentu langsung dari tindakan atau perilaku seseorang. Konstruk-konstruk dalam model the Unified Theory of Acceptance and Use of Technology (UTAUT: performance expectancy, effort expectancy, social influences dan facilitating condition digunakan sebagai faktor-faktor yang mempengaruhi Niat Menggunakan. Penelitian ini dilakukan di Desa Pasar VI Kualanamu, desa yang telah mendapatkan fasilitas dan sarana TIK melalui Desa Informasi. Analisis dilakukan secara deskriptif dan Confirmatory Factor Analysis (CFA serta analisis model struktural Structural Equation Model - Partial Least Square (SEM-PLS. Hasil pengujian SEM-PLS menunjukkan nilai R-Square 0,752. Kemudian dengan menggunakan metode boot-strapping dalam smartPLS, didapatkan bahwa faktor effort expectancy dan social influences berpengaruh secara signifikan terhadap Niat Menggunakan internet.     Abstract Provision of access of ICT (internet for rural communities aimed not only for reducing the digital divide but also to encourage the meaningful activity and productivity. The internet may be not needed by the rural community, due to low awareness of the benefits and also there is not interrelated with living

  14. Simulation of inverters for the PHOTONERGY{sup TM} project. Development and simulation of new topologies

    Energy Technology Data Exchange (ETDEWEB)

    NONE

    2002-11-01

    The PHOTONERGY project (the former SolcelleInverter project) was initiated on the 1st of September 2001, with a state-of-the-art analysis, which concluded into the specifications. Based on these two documents, a set of 23 topologies was analysed in for efficiencies. The results from this analysis was five candidates which all showed a somewhat good efficiency. These five topologies are in this report further investigated by means of an initial design-iteration and simulations. The items of interest in this report are efficiency and component ratings (magnetics, transistors, diodes and capacitors). The simulations reveal that DC-to-DC converters (for amplifying the PV-Module voltage) build on resonant technology (series-resonant and parallel-resonant) all suffers from high circulating currents inside the resonant tank; qua a low efficiency is the result. Whereas, the standard full-bridge converter and the novel MOHAN converter do not suffers from these severe currents, which also reflects into a higher efficiency. The ratings for the resonant converters are also somewhat larger than for the two other solutions. The two selected DC/DC converters are, on the basis of these properties, the standard full-bridge converter and the MOHAN converter. The simulated DC-to-AC inverters (for modulating the sinusoidal grid current) both show excellent performance in terms of high efficiency and low ratings. However, it seems that the MOSFET equipped inverters has lower losses than the IGBT equipped one. The last inverter investigated is the novel Dual FlyBack Inverter, which both amplifies the PV-Module voltage and modulates the sinusoidal grid current in one single process. Unfortunately, this circuit suffers from a low efficiency due to a high internal current. However, the efficiency is expected to increase with an increasing switching frequency, so the inverter is also selected for further design. A novel 'single-step' solution emerged at the end of the period: the

  15. The origins and early history of the National Chiropractic Association

    Science.gov (United States)

    Keating, Joseph C; Rehm, William S

    1993-01-01

    Early organization in chiropractic was prompted by the profession’s need to promote itself and to defend against the onslaught of political medicine and organized osteopathy. The first priorities were legal defense against prosecution for unlicensed practice and malpractice insurance. The Universal Chiropractors’ Association (UCA), organized at the Palmer School of Chiropractic (PSC) in 1906, sought to meet these needs by insuring its members and by developing a legal department under the supervision of attorney Tom Morris, one time lieutenant governor of Wisconsin. The public relations and marketing needs of chiropractors were largely served by the PSC and its legendary leader. However, as chiropractors increasingly sought to avoid prosecution by passage of chiropractic laws, Palmer’s efforts to direct this legislation so as to limit chiropractors’ scope of practice increasingly alienated many in the profession. The American Chiropractic Association (ACA) was founded in 1922 to provide a broadscope alternative to BJ’s UCA. With Palmer’s departure from the UCA following the neurocalometer debacle, ACA and UCA sought amalgamation. Simultaneously, organized medicine renewed its attack on the profession by introducing basic science legislation, which prompted chiropractors to try to upgrade and standardize chiropractic education. Early efforts to bring about the needed consensus were centered in the International Chiropractic Congress (ICC), particularly its division of state examining boards. In 1930 the ACA and UCA combined to form the National Chiropractic Association (NCA), and by 1934 the ICC had merged with the NCA to form part of its council structure. With this modicum of solidarity the NCA began the process of educational boot-strapping at its 1935 convention in Los Angeles, when its Committee on Education, a forerunner of today’s Council on Chiropractic Education, was proposed by C.O. Watkins of Montana. ImagesFigure 2Figure 3Figure 4Figure 5

  16. Appraisal Support from Natural Mentors, Self-worth, and Psychological Distress: Examining the Experiences of Underrepresented Students Transitioning Through College.

    Science.gov (United States)

    Hurd, Noelle M; Albright, Jamie; Wittrup, Audrey; Negrete, Andrea; Billingsley, Janelle

    2018-05-01

    The current study explored whether cumulative appraisal support from as many as five natural mentors (i.e., nonparental adults from youth's pre-existing social networks who serve a mentoring role in youth's lives) led to reduced symptoms of depression and anxiety via improved global self-worth among underrepresented college students. Participants in the current study included 340 college students (69% female) attending a 4-year, predominantly White institution of higher education. Participants were first-generation college students, students from economically disadvantaged backgrounds, and/or students from underrepresented racial/ethnic minority groups. Participants completed surveys during the Fall and Spring of their first year of college and in the Spring of their second and third years of college. Results of the structural equation model (including gender, race/ethnicity, and extraversion as covariates) indicated that greater total appraisal support from natural mentoring relationships predicted decreases in students' psychological distress via increases in self-worth (indirect effects assessed via boot-strapped confidence intervals; 95% CI). The strength of association between appraisal support and self-worth was not moderated by the proportion of academic natural mentors. Findings from the current study extend previous research by measuring multiple natural mentoring relationships and pinpointing supportive exchanges that may be of particular consequence for the promotion of healthy youth development. Institutional efforts to reinforce pre-existing natural mentoring relationships and encourage the onset of new natural mentoring relationships may serve to bolster the well-being and success of underrepresented students attending predominantly White universities.

  17. Long-term socio-economic consequences and health care costs of poliomyelitis: a historical cohort study involving 3606 polio patients.

    Science.gov (United States)

    Nielsen, Nete Munk; Kay, Lise; Wanscher, Benedikte; Ibsen, Rikke; Kjellberg, Jakob; Jennum, Poul

    2016-06-01

    Worldwide 10-20 million individuals are living with disabilities after acute poliomyelitis. However, very little is known about the socio-economic consequences and health care costs of poliomyelitis. We carried out a historical register-based study including 3606 individuals hospitalised for poliomyelitis in Copenhagen, Denmark 1940-1954, and 13,795 age and gender-matched Danes. Participants were followed from 1980 until 2012, and family, socio-economic conditions and health care costs were evaluated in different age groups using chi-squared tests, boot-strapped t tests or hazard ratios (HR) calculated in Cox-regression models. The analyses were performed separately for paralytic and non-paralytic polio survivors and their controls, respectively. Compared with controls a higher percentage of paralytic polio survivors remained childless, whereas no difference was observed for non-paralytic polio survivors. The educational level among paralytic as well as non-paralytic polio survivors was higher than that among their controls, employment rate at the ages of 40, 50 and 60 years was slightly lower, whereas total income in the age intervals of 31-40, 41-50 and 51-60 years were similar to controls. Paralytic and non-paralytic polio survivors had a 2.5 [HR = 2.52 (95 % confidence interval (CI); 2.29-2.77)] and 1.4 [HR = 1.35 (95 % CI; 1.23-1.49)]-fold higher risk, respectively, of receiving disability pension compared with controls. Personal health care costs were considerably higher in all age groups in both groups of polio survivors. Individuals with a history of poliomyelitis are well educated, have a slightly lower employment rate, an income similar to controls, but a considerably higher cost in the health care system.

  18. A Bayesian Meta-Analysis of the Effect of Alcohol Use on HCV-Treatment Outcomes with a Comparison of Resampling Methods to Assess Uncertainty in Parameter Estimates.

    Energy Technology Data Exchange (ETDEWEB)

    Cauthen, Katherine Regina [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Lambert, Gregory Joseph [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Finley, Patrick D. [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Ross, David [US Dept. of Veterans Affairs, Washington, DC (United States); Chartier, Maggie [US Dept. of Veterans Affairs, Washington, DC (United States); Davey, Victoria J. [US Dept. of Veterans Affairs, Washington, DC (United States)

    2015-10-01

    There is mounting evidence that alcohol use is significantly linked to lower HCV treatment response rates in interferon-based therapies, though some of the evidence is conflicting. Furthermore, although health care providers recommend reducing or abstaining from alcohol use prior to treatment, many patients do not succeed in doing so. The goal of this meta-analysis was to systematically review and summarize the Englishlanguage literature up through January 30, 2015 regarding the relationship between alcohol use and HCV treatment outcomes, among patients who were not required to abstain from alcohol use in order to receive treatment. Seven pertinent articles studying 1,751 HCV-infected patients were identified. Log-ORs of HCV treatment response for heavy alcohol use and light alcohol use were calculated and compared. We employed a hierarchical Bayesian meta-analytic model to accommodate the small sample size. The summary estimate for the log-OR of HCV treatment response was -0.775 with a 95% credible interval of (-1.397, -0.236). The results of the Bayesian meta-analysis are slightly more conservative compared to those obtained from a boot-strapped, random effects model. We found evidence of heterogeneity (Q = 14.489, p = 0.025), accounting for 60.28% of the variation among log-ORs. Meta-regression to capture the sources of this heterogeneity did not identify any of the covariates investigated as significant. This meta-analysis confirms that heavy alcohol use is associated with decreased HCV treatment response compared to lighter levels of alcohol use. Further research is required to characterize the mechanism by which alcohol use affects HCV treatment response.

  19. Measuring Erosion and Deposition During the World's Largest Dam Removal in Near-Real-Time: An Example of 4-Dimensional SfM from the Elwha River, Washington, USA

    Science.gov (United States)

    Ritchie, A.; Bountry, J.; Randle, T. J.; Warrick, J. A.

    2016-12-01

    The stepwise removal of two dams on the Elwha River beginning in September 2011 exposed 21 million cubic meters of sediment to fluvial erosion and created an unprecedented opportunity to monitor reservoir sediment erosion and river evolution during base level adjustment and a pulsed sediment release. We conduct repeat aerial surveys with a Cessna 172 using a simple custom wing-mount for consumer grade cameras and SfM photogrammetry to produce orthoimagery and digital elevation models in near-real-time at sub-weekly to monthly time intervals, depending on hydrology. Multiple lidar flights and ground survey campaigns provide estimates of both systematic and random error for this uniquely dense dataset. Co-registration of multiple SfM surveys during processing reduces systematic error and allows boot-strapping of ephemeral ground control points to earlier or later flights. Measurements of reservoir erosion volumes, delta growth, channel braiding, and bank erosion illustrate the reservoir and river channel responses to dam removal at resolutions comparable to hydrologic forcing events, allowing us to quantify reservoir sediment budgets on a per-storm basis. This allows for the analysis of sediment transported relative to rates of reservoir drawdown and river stream power for dozens of time intervals. Temporal decoupling of peak sediment flux and bank erosion rates is noted from these analyses. This dataset illustrates both challenges and opportunities emerging with the advent of big data in remote sensing of earth surface processes. Digital AbstractErosion and deposition by year in former Lake Mills reservoir measured using SfM-derived photogrammetry and LiDAR for WY2011 through 2016 (partial). Approximately 70% of available sediment has been eroded.

  20. A comparative study of hole and electron inversion layer quantization in MOS structures

    Directory of Open Access Journals (Sweden)

    Chaudhry Amit

    2010-01-01

    Full Text Available In this paper, an analytical model has been developed to study inversion layer quantization in nanoscale Metal Oxide Semiconductor Field Effect Oxide p-(MOSFET. n-MOSFETs have been studied using the variation approach and the p-MOSFETs have been studied using the triangular well approach. The inversion charge density and gate capacitance analysis for both types of transistors has been done. There is a marked decrease in the inversion charge density and the capacitance of the p-MOSFET as compared to n-MOSFETs. The results are compared with the numerical results showing good agreement.

  1. A low on-resistance SOI LDMOS using a trench gate and a recessed drain

    International Nuclear Information System (INIS)

    Ge Rui; Luo Xiaorong; Jiang Yongheng; Zhou Kun; Wang Pei; Wang Qi; Wang Yuangang; Zhang Bo; Li Zhaoji

    2012-01-01

    An integrable silicon-on-insulator (SOI) power lateral MOSFET with a trench gate and a recessed drain (TGRD MOSFET) is proposed to reduce the on-resistance. Both of the trench gate extended to the buried oxide (BOX) and the recessed drain reduce the specific on-resistance (R on,sp ) by widening the vertical conduction area and shortening the extra current path. The trench gate is extended as a field plate improves the electric field distribution. Breakdown voltage (BV) of 97 V and R on,sp of 0.985 mΩ·cm 2 (V GS = 5 V) are obtained for a TGRD MOSFET with 6.5 μm half-cell pitch. Compared with the trench gate SOI MOSFET (TG MOSFET) and the conventional MOSFET, R on,sp of the TGRD MOSFET decreases by 46% and 83% at the same BV, respectively. Compared with the SOI MOSFET with a trench gate and a trench drain (TGTD MOSFET), BV of the TGRD MOSFET increases by 37% at the same R on,sp . (semiconductor devices)

  2. Mono Amplifier Class D Menggunakan Semikron SKHI 22B dan IGBT Module Semikron SKM75GB128DN

    OpenAIRE

    Christanto, Ivan

    2013-01-01

    Dalam perkembangan power amplifier, MOSFET banyak digunakan dalam komposisi pembuatannya. Seperti diketahui, MOSFET memiliki kerugian waktu on-off yang lebih lama dibandingkan dengan IGBT. Kerugian waktu on-off tersebut berdampak pada panas yang ditimbulkan MOSFET. Selain IGBT memiliki waktu on-off yang lebih cepat, IGBT juga tidak membebani sumber input-nya. Tujuan dari paper ini adalah merancang power amplifier class D dengan menggunakan IGBT driver semikron SKHI 22B dan I...

  3. Prognostics Health Management and Physics based failure Models for Electrolytic Capacitors

    Data.gov (United States)

    National Aeronautics and Space Administration — This paper proposes first principles based modeling and prognostics approach for electrolytic capacitors. Electrolytic capacitors and MOSFETs are the two major...

  4. High voltage high repetition rate pulse using Marx topology

    Science.gov (United States)

    Hakki, A.; Kashapov, N.

    2015-06-01

    The paper describes Marx topology using MOSFET transistors. Marx circuit with 10 stages has been done, to obtain pulses about 5.5KV amplitude, and the width of the pulses was about 30μsec with a high repetition rate (PPS > 100), Vdc = 535VDC is the input voltage for supplying the Marx circuit. Two Ferrite ring core transformers were used to control the MOSFET transistors of the Marx circuit (the first transformer to control the charging MOSFET transistors, the second transformer to control the discharging MOSFET transistors).

  5. A prototype methodology combining surface-enhanced laser desorption/ionization protein chip technology and artificial neural network algorithms to predict the chemoresponsiveness of breast cancer cell lines exposed to Paclitaxel and Doxorubicin under in vitro conditions.

    Science.gov (United States)

    Mian, Shahid; Ball, Graham; Hornbuckle, Jo; Holding, Finn; Carmichael, James; Ellis, Ian; Ali, Selman; Li, Geng; McArdle, Stephanie; Creaser, Colin; Rees, Robert

    2003-09-01

    An ability to predict the likelihood of cellular response towards particular chemotherapeutic agents based upon protein expression patterns could facilitate the identification of biological molecules with previously undefined roles in the process of chemoresistance/chemosensitivity, and if robust enough these patterns might also be exploited towards the development of novel predictive assays. To ascertain whether proteomic based molecular profiling in conjunction with artificial neural network (ANN) algorithms could be applied towards the specific recognition of phenotypic patterns between either control or drug treated and chemosensitive or chemoresistant cellular populations, a combined approach involving MALDI-TOF matrix-assisted laser desorption/ionization-time of flight mass spectrometry, Ciphergen protein chip technology and ANN algorithms have been applied to specifically identify proteomic 'fingerprints' indicative of treatment regimen for chemosensitive (MCF-7, T47D) and chemoresistant (MCF-7/ADR) breast cancer cell lines following exposure to Doxorubicin or Paclitaxel. The results indicate that proteomic patterns can be identified by ANN algorithms to correctly assign 'class' for treatment regimen (e.g. control/drug treated or chemosensitive/chemoresistant) with a high degree of accuracy using boot-strap statistical validation techniques and that biomarker ion patterns indicative of response/non-response phenotypes are associated with MCF-7 and MCF-7/ADR cells exposed to Doxorubicin. We have also examined the predictive capability of this approach towards MCF-7 and T47D cells to ascertain whether prediction could be made based upon treatment regimen irrespective of cell lineage. Models were identified that could correctly assign class (control or Paclitaxel treatment) for 35/38 samples of an independent dataset. A similar level of predictive capability was also found (> 92%; n = 28) when proteomic patterns derived from the drug resistant cell line MCF-7

  6. Cardiorespiratory fitness and academic performance association is mediated by weight status in adolescents: DADOS study.

    Science.gov (United States)

    Beltran-Valls, María Reyes; Adelantado-Renau, Mireia; Castro-Piñero, Jose; Sánchez-López, Mairena; Moliner-Urdiales, Diego

    2018-04-28

    The aim of our study was to examine the mediation effect of weight status on the association between cardiorespiratory fitness (CRF) and academic performance (AP). Two hundred sixty-nine adolescents (140 boys) aged 13.9 ± 0.3 years old from the DADOS study were included in this cross-sectional analysis. CRF was assessed by the 20-m shuttle run test and estimated maximum oxygen uptake was used in the analysis. AP was assessed through the final academic grades and the Science Research Associates Test of Educational Abilities for assessing reasoning, verbal, and numeric abilities. Weight status was assessed by body mass index (kg/m 2 ). Boot-strapped mediation procedures were performed and indirect effects (IE) with confidence intervals (CI) not including zero were considered statistically significant. Mediation analysis revealed that weight status acted as a mediator of the relationship of CRF with reasoning ability (IE = 0.039; CI = 0.001; 0.091) and the final grades in Math (IE = 0.011; CI = 0.002; 0.025), Language (IE = 0.013; CI = 0.004; 0.027), and GPA (IE = 0.011; CI = 0.003; 0.023). Our data show that the influence of CRF on academic performance is mediated by weight status in adolescents. We suggest that our data could be considered by educators, families, and policy makers, so that active lifestyles might be promoted when designing programs aimed to improve AP among adolescents. What is Known: • Academic performance is associated with both, cardiorespiratory fitness and weight status. • The role of weight status in the association between cardiorespiratory fitness and academic performance is poorly understood. What is New: • We support the scarce research investigating the mediating role of weight status as mechanism in the association between fitness and academic performance in youth. • Previous knowledge is expanded by suggesting that cardiorespiratory fitness is related to weight status which in turn may

  7. Non-invasive assessment of hepatic steatosis in patients with NAFLD using controlled attenuation parameter and 1H-MR spectroscopy.

    Directory of Open Access Journals (Sweden)

    Thomas Karlas

    Full Text Available INTRODUCTION: Non-invasive assessment of steatosis and fibrosis is of growing relevance in non-alcoholic fatty liver disease (NAFLD. 1H-Magnetic resonance spectroscopy (1H-MRS and the ultrasound-based controlled attenuation parameter (CAP correlate with biopsy proven steatosis, but have not been correlated with each other so far. We therefore performed a head-to-head comparison between both methods. METHODS: Fifty patients with biopsy-proven NAFLD and 15 healthy volunteers were evaluated with 1H-MRS and transient elastography (TE including CAP. Steatosis was defined according to the percentage of affected hepatocytes: S1 5-33%, S2 34-66%, S3 ≥67%. RESULTS: Steatosis grade in patients with NAFLD was S1 36%, S2 40% and S3 24%. CAP and 1H-MRS significantly correlated with histopathology and showed comparable accuracy for the detection of hepatic steatosis: areas under the receiver-operating characteristics curves were 0.93 vs. 0.88 for steatosis ≥S1 and 0.94 vs. 0.88 for ≥S2, respectively. Boot-strapping analysis revealed a CAP cut-off of 300 dB/m for detection of S2-3 steatosis, while retaining the lower cut-off of 215 dB/m for the definition of healthy individuals. Direct comparison between CAP and 1H-MRS revealed only modest correlation (total cohort: r = 0.63 [0.44, 0.76]; NAFLD cases: r = 0.56 [0.32, 0.74]. For detection of F2-4 fibrosis TE had sensitivity and specificity of 100% and 98.1% at a cut-off value of 8.85 kPa. CONCLUSION: Our data suggest a comparable diagnostic value of CAP and 1H-MRS for hepatic steatosis quantification. Combined with the simultaneous TE fibrosis assessment, CAP represents an efficient method for non-invasive characterization of NAFLD. Limited correlation between CAP and 1H-MRS may be explained by different technical aspects, anthropometry, and presence of advanced liver fibrosis.

  8. The role of DSM-5 borderline personality symptomatology and traits in the link between childhood trauma and suicidal risk in psychiatric patients.

    Science.gov (United States)

    Bach, Bo; Fjeldsted, Rita

    2017-01-01

    Childhood traumas appear to be linked to suicidal behavior. However, the factors that mediate between these two phenomena are not sufficiently understood. Recent findings suggest that borderline personality disorder (BPD) may explain some of the association. The present study investigated the potential mediating role of BPD symptomatology and traits between reported childhood trauma and suicidal risk in adult psychiatric outpatients ( N  = 124). BPD symptomatology was measured with DSM-5 Section II criterion-counts (SCID-II; Structured Clinical Interview for DSM-IV Axis II), whereas BPD traits were measured with specified DSM-5 Section III traits (PID-5; Personality Inventory for DSM-5). Childhood traumas were self-reported (CTQ; Childhood Trauma Questionnaire), whereas level of suicidal risk was measured with a structured interview (MINI Suicidality Module; Mini International Neuropsychiatric Interview). Mediation effects were tested by bias-corrected (10.000 boot-strapped samples) confidence intervals. BPD features account for a considerable part of the cross-sectional association between childhood trauma and level of suicidal risk, even when controlling for the influence of gender, age, and educational level. This finding remained stable when testing the model without the suicidality-related BPD criterion and PID-5 items. DSM-5 Section II BPD criterion-counts explained 67% of the total effect, whereas DSM-5 Section III BPD traits accounted for 82% of the total effect. The specific DSM-5 Section III trait facets of "Depressivity" (52%) and "Perceptual Dysregulation" (37%) accounted for most of this effect. The findings provide preliminary support for the proposed mediation model indicating that BPD features may help explain relations between childhood trauma and elevated suicidal risk in adult life, in particular for DSM-5 Section III personality traits of depressivity (e.g., pessimism, guilt, and shame) and perceptual dysregulation (e.g., dissociation). To

  9. The carbonate mineralogy and distribution of habitat-forming deep-sea corals in the southwest pacific region

    Science.gov (United States)

    Bostock, Helen C.; Tracey, Dianne M.; Currie, Kim I.; Dunbar, Gavin B.; Handler, Monica R.; Mikaloff Fletcher, Sara E.; Smith, Abigail M.; Williams, Michael J. M.

    2015-06-01

    Habitat-forming deep-sea scleractinian and alcyonacean corals from around the southwest Pacific were analysed for their calcium carbonate mineralogy. Scleractinian coral species Solenosmilia variabilis, Enallopsammia rostrata, Goniocorella dumosa, Madrepora oculata and Oculina virgosa were all found to be 100% aragonitic, while some members of the alcyonacean taxa Keratoisis spp., Lepidisis spp., and Paragorgia spp. were determined to be high magnesium (Mg) calcite (with 8-11 mol% MgCO3) and Primnoa sp. is bimineralic with both aragonite and Mg calcite. The majority of these habitat-forming deep-sea corals are found at intermediate depths (800-1200 m) in the Antarctic Intermediate Waters (AAIW) with low salinities (~34.5), temperatures of 4-8 °C and high oxygen concentrations (>180 μmol/kg) and currently sitting above the aragonite saturation horizon (ASH). However, habitat-forming corals have been recorded from greater depths, in cooler waters (2-4 °C) that are undersaturated with respect to aragonite (Ωaragonite160 μmol/kg. To address the sampling depth bias the coral records were normalised by the number of benthic stations (sampling effort) in the same depth range. This shows that the highest number of corals per sampling effort is between 1000 and 1400 m with corals present in over 5% of the stations at these depths. The normalised records and Boot Strap analyses suggests that scleractinian corals, especially S. variabilis should be present in >1% of stations down to 1800 m water depth, with E. rostrata, M. oculata and G. dumosa slightly shallower. While alcyonacean corals are found in >1% down to 2600 m, with Keratoisis spp. the deepest down to 2600 m, while Lepidisis spp. and Paragorgia spp. found down to 1800 m. This suggests that most species can probably tolerate some undersaturation of aragonite (Ωaragonite=0.8-0.9), with several species/genera (S. variabilis; Keratoisis spp.) even more tolerant of lower carbonate concentrations ([CO3 2 -]), down

  10. Service use and costs for people with long-term neurological conditions in the first year following discharge from in-patient neuro-rehabilitation: a longitudinal cohort study.

    Directory of Open Access Journals (Sweden)

    Diana Jackson

    Full Text Available BACKGROUND: Knowledge of the configuration and costs of community rehabilitation and support for people with long-term neurological conditions (LTNCs is needed to inform future service development and resource allocation. In a multicentre prospective cohort study evaluating community service delivery during the year post-discharge from in-patient neuro-rehabilitation, a key objective was to determine service use, costs, and predictors of these costs. METHODS: Patients consecutively admitted over one year to all nine London specialised (Level 1 in-patient neuro-rehabilitation units were recruited on discharge. They or their carers completed postal/web-based questionnaires at discharge and six and twelve months later, providing demographic data and measures of impairment, disability, service needs and provision. This paper describes health and social care service use, informal care and associated costs. Regression models using non-parametric boot-strapping identified predictors of costs over time. RESULTS: Overall, 152 patients provided consistent data. Mean formal service costs fell significantly from £13,290 (sd £19,369 during the first six months to £9,335 (sd £19,036 from six-twelve months, (t = 2.35, P<0.05, mainly due to declining health service use. At six months, informal care was received on average for 8.2 hours/day, mean cost £14,615 (sd 23,305, comprising 52% of overall care costs. By twelve months, it had increased to 8.8 hours per day, mean cost £15,468 (sd £25,534, accounting for 62% of overall care costs. Being younger and more disabled predicted higher formal care costs, explaining 32% and 30% of the variation in costs respectively at six and twelve months. CONCLUSION: Community services for people with LTNCs carry substantial costs that shift from health to social care over time, increasing the burden on families. Prioritising rehabilitation services towards those in greatest need could limit access to others needing on

  11. Annual report on major results and progress of Fusion Research and Development Directorate of JAEA from April 1, 2006 to March 31, 2007

    International Nuclear Information System (INIS)

    Suzuki, Satoshi; Ishii, Yasutomo; Sukegawa, Atsuhiko; Iwai, Yasunori; Nakamura, Hiroo; Sugie, Tatsuo

    2008-08-01

    This annual report provides an overview of major results and progress on research and development (R and D) activities at Fusion Research and Development Directorate of Japan Atomic Energy Agency (JAEA) from April 1, 2006 to March 31, 2007, including those performed in collaboration with other research establishments of JAEA, research institutes, and universities. In JT-60, as a result of ferritic steel tiles (FSTs) installation to reduce the toroidal field ripple and the application of the real time current profile control, high boot strap current fraction (∼0.7) has successfully been sustained about 8 s. In addition, the conceptual design of JT-60SA, which was placed as a combined project of JA-EU Satellite Tokamak Programme under the Broader Approach Programme and JAEA's programme for national use, was progressed. In theoretical and analytical researches, studies on ITB events and their triggers, plasma shape effect on edge stability and driven magnetic island evolution in rotating plasmas were progressed. In the NEXT project, computer simulations of the plasma turbulence were progressed. In fusion reactor technologies, R and Ds for ITER and fusion DEMO plants have been carried out. For ITER, a steady state operation of the 170GHz gyrotron up to 10min with 0.82MW was demonstrated. Also current density of the neutral beam injector has been extended to 146A/m 2 at 0.84MeV. In the ITER Test Blanket Module (TBM), designs and R and Ds of Water and Helium Cooled Solid Breeder TBMs including tritium breeder/multiplier materials were progressed. Tritium processing technology for breeding blankets and neutronics integral experiments with a blanket mockup were also progressed. For ITER and DEMO blankets, studies on neutron irradiation effects and ion irradiation effects on F82H steel characteristics were continued using HFIR, TIARA and so on. In the IFMIF program, transitional activities to EVEDA were continued. In the ITER Program, under the framework of the ITER

  12. Modularity and Sparsity: Evolution of Neural Net Controllers in Physically Embodied Robots

    Directory of Open Access Journals (Sweden)

    Nicholas Livingston

    2016-12-01

    Full Text Available While modularity is thought to be central for the evolution of complexity and evolvability, it remains unclear how systems boot-strap themselves into modularity from random or fully integrated starting conditions. Clune et al. (2013 suggested that a positive correlation between sparsity and modularity is the prime cause of this transition. We sought to test the generality of this modularity-sparsity hypothesis by testing it for the first time in physically embodied robots. A population of ten Tadros — autonomous, surface-swimming robots propelled by a flapping tail — was used. Individuals varied only in the structure of their neural net control, a 2 x 6 x 2 network with recurrence in the hidden layer. Each of the 60 possible connections was coded in the genome, and could achieve one of three states: -1, 0, 1. Inputs were two light-dependent resistors and outputs were two motor control variables to the flapping tail, one for the frequency of the flapping and the other for the turning offset. Each Tadro was tested separately in a circular tank lit by a single overhead light source. Fitness was the amount of light gathered by a vertically oriented sensor that was disconnected from the controller net. Reproduction was asexual, with the top performer cloned and then all individuals entered into a roulette wheel selection process, with genomes mutated to create the offspring. The starting population of networks was randomly generated. Over ten generations, the population’s mean fitness increased two-fold. This evolution occurred in spite of an unintentional integer overflow problem in recurrent nodes in the hidden layer that caused outputs to oscillate. Our investigation of the oscillatory behavior showed that the mutual information of inputs and outputs was sufficient for the reactive behaviors observed. While we had predicted that both modularity and sparsity would follow the same trend as fitness, neither did so. Instead, selection gradients

  13. Calibration and error analysis of metal-oxide-semiconductor field-effect transistor dosimeters for computed tomography radiation dosimetry.

    Science.gov (United States)

    Trattner, Sigal; Prinsen, Peter; Wiegert, Jens; Gerland, Elazar-Lars; Shefer, Efrat; Morton, Tom; Thompson, Carla M; Yagil, Yoad; Cheng, Bin; Jambawalikar, Sachin; Al-Senan, Rani; Amurao, Maxwell; Halliburton, Sandra S; Einstein, Andrew J

    2017-12-01

    Metal-oxide-semiconductor field-effect transistors (MOSFETs) serve as a helpful tool for organ radiation dosimetry and their use has grown in computed tomography (CT). While different approaches have been used for MOSFET calibration, those using the commonly available 100 mm pencil ionization chamber have not incorporated measurements performed throughout its length, and moreover, no previous work has rigorously evaluated the multiple sources of error involved in MOSFET calibration. In this paper, we propose a new MOSFET calibration approach to translate MOSFET voltage measurements into absorbed dose from CT, based on serial measurements performed throughout the length of a 100-mm ionization chamber, and perform an analysis of the errors of MOSFET voltage measurements and four sources of error in calibration. MOSFET calibration was performed at two sites, to determine single calibration factors for tube potentials of 80, 100, and 120 kVp, using a 100-mm-long pencil ion chamber and a cylindrical computed tomography dose index (CTDI) phantom of 32 cm diameter. The dose profile along the 100-mm ion chamber axis was sampled in 5 mm intervals by nine MOSFETs in the nine holes of the CTDI phantom. Variance of the absorbed dose was modeled as a sum of the MOSFET voltage measurement variance and the calibration factor variance, the latter being comprised of three main subcomponents: ionization chamber reading variance, MOSFET-to-MOSFET variation and a contribution related to the fact that the average calibration factor of a few MOSFETs was used as an estimate for the average value of all MOSFETs. MOSFET voltage measurement error was estimated based on sets of repeated measurements. The calibration factor overall voltage measurement error was calculated from the above analysis. Calibration factors determined were close to those reported in the literature and by the manufacturer (~3 mV/mGy), ranging from 2.87 to 3.13 mV/mGy. The error σ V of a MOSFET voltage

  14. Hybrid orientation technology and strain engineering for ultra-high ...

    Indian Academy of Sciences (India)

    con nitride (Si3N4) cap layer thickness for n-MOSFETs, Ge mole fraction optimization for p-MOSFETs on (110) substrates and channel length scaling have resulted in record RF performance, viz. the cut-off frequency, fT. Keywords. Hybrid orientation technology; technology CAD; process-induced strain; CMOS integrated ...

  15. Face to Face The IGBT and its Creator

    Indian Academy of Sciences (India)

    IAS Admin

    The Insulated Gate Bipolar Transistor is a power switching device that combines the advantages of the BJT and the MOSFET (see Box 1) by using a short channel MOSFET to drive a wide base p-n-p BJT [1]. It was first reported experimentally by Jayant Baliga, who was then at GE, in the year 1979 as a V-grooved MOSFET ...

  16. Characteristics and optimisation of vertical and planar tunnelling-FETs

    International Nuclear Information System (INIS)

    Sterkel, M; Wang, P-F; Nirschl, T; Fabel, B; Bhuwalka, K K; Schulze, J; Eisele, I; Schmitt-Landsiedel, D; Hansch, W

    2005-01-01

    Scaling MOSFETs becomes more and more difficult. The tunnelling-FET is a possible successor of today's MOSFET with better scaling possibilities. Two different device structures, a vertical and a planar version of a tunnelling-FET are presented and evaluated

  17. Channel length scaling and the impact of metal gate work function ...

    Indian Academy of Sciences (India)

    Further- more, quantum effects on the performance of DG-MOSFETs are addressed and discussed. We also study the influence of metal gate work function on the performance of nanoscale MOSFETs. We use a self-consistent Poisson–Schrödinger solver in two dimensions over the entire device. A good agreement with ...

  18. Effect of stacking order on device performance of bilayer black phosphorene-field-effect transistor

    Energy Technology Data Exchange (ETDEWEB)

    Mukhopadhyay, A., E-mail: arnabm.electinstru@gmail.com; Banerjee, L.; Sengupta, A.; Rahaman, H. [School of VLSI Technology, IIEST, Shibpur, Howrah 711103 (India)

    2015-12-14

    We investigate the effect of stacking order of bilayer black phosphorene on the device properties of p-MOSFET and n-MOSFET. Two layers of black phosphorus are stacked in three different orders and are used as channel material in both n-MOSFET and p-MOSFET devices. The effects of different stacking orders on electron and hole effective masses and output characteristics of MOSFETs, such as ON currents, ON/OFF ratio, and transconductance are analyzed. Our results show that about 1.37 times and 1.49 times increase in ON current is possible along armchair and zigzag directions, respectively, 55.11% variation in transconductance is possible along armchair direction, by changing stacking orders (AA, AB, and AC) and about 8 times increase in ON current is achievable by changing channel orientation (armchair or zigzag) in p-MOSFET. About 14.8 mV/V drain induced barrier lowering is observed for both p-MOSFET and n-MOSFET, which signifies good immunity to short channel effects.

  19. Hybrid orientation technology and strain engineering for ultra-high ...

    Indian Academy of Sciences (India)

    Hybrid orientation technology and strain engineering for ultra-high speed MOSFETs. T K MAITI and C K MAITI. ∗. Department of Electronics and Electrical Communication Engineering, Indian Institute of Technology,. Kharagpur 721 302, India. MS received 27 March 2012. Abstract. We report here RF MOSFET performance ...

  20. Hybrid orientation technology and strain engineering for ultra-high ...

    Indian Academy of Sciences (India)

    We report here RF MOSFET performance in sub-45-nm hybrid orientation CMOS technology. Based on the combination of hybrid orientation technology (HOT) and process-induced local strain engineering,MOSFET RF performance is investigated using CAD (TCAD) technology. Transistor optimization on (100) substrate ...

  1. Bulletin of Materials Science | Indian Academy of Sciences

    Indian Academy of Sciences (India)

    We report here RF MOSFET performance in sub-45-nm hybrid orientation CMOS technology. Based on the combination of hybrid orientation technology (HOT) and process-induced local strain engineering,MOSFET RF performance is investigated using CAD (TCAD) technology. Transistor optimization on (100) substrate ...

  2. Technology CAD for germanium CMOS circuit

    Energy Technology Data Exchange (ETDEWEB)

    Saha, A.R. [Department of Electronics and ECE, IIT Kharagpur, Kharagpur-721302 (India)]. E-mail: ars.iitkgp@gmail.com; Maiti, C.K. [Department of Electronics and ECE, IIT Kharagpur, Kharagpur-721302 (India)

    2006-12-15

    Process simulation for germanium MOSFETs (Ge-MOSFETs) has been performed in 2D SILVACO virtual wafer fabrication (VWF) suite towards the technology CAD for Ge-CMOS process development. Material parameters and mobility models for Germanium were incorporated in simulation via C-interpreter function. We also report on the device design issues along with the DC and RF characterization of the bulk Ge-MOSFETs, AC parameter extraction and circuit simulation of Ge-CMOS. Simulation results are compared with bulk-Si devices. Simulations predict a cut-off frequency, f {sub T} of about 175 GHz for Ge-MOSFETs compared to 70 GHz for a similar gate-length Si MOSFET. For a single stage Ge-CMOS inverter circuit, a GATE delay of 0.6 ns is predicted.

  3. Technology CAD for germanium CMOS circuit

    International Nuclear Information System (INIS)

    Saha, A.R.; Maiti, C.K.

    2006-01-01

    Process simulation for germanium MOSFETs (Ge-MOSFETs) has been performed in 2D SILVACO virtual wafer fabrication (VWF) suite towards the technology CAD for Ge-CMOS process development. Material parameters and mobility models for Germanium were incorporated in simulation via C-interpreter function. We also report on the device design issues along with the DC and RF characterization of the bulk Ge-MOSFETs, AC parameter extraction and circuit simulation of Ge-CMOS. Simulation results are compared with bulk-Si devices. Simulations predict a cut-off frequency, f T of about 175 GHz for Ge-MOSFETs compared to 70 GHz for a similar gate-length Si MOSFET. For a single stage Ge-CMOS inverter circuit, a GATE delay of 0.6 ns is predicted

  4. In vivo real-time rectal wall dosimetry for prostate radiotherapy

    Science.gov (United States)

    Hardcastle, Nicholas; Cutajar, Dean L.; Metcalfe, Peter E.; Lerch, Michael L. F.; Perevertaylo, Vladimir L.; Tomé, Wolfgang A.; Rosenfeld, Anatoly B.

    2010-07-01

    Rectal balloons are used in external beam prostate radiotherapy to provide reproducible anatomy and rectal dose reductions. This is an investigation into the combination of a MOSFET radiation detector with a rectal balloon for real-time in vivo rectal wall dosimetry. The MOSFET used in the study is a radiation detector that provides a water equivalent depth of measurement of 70 µm. Two MOSFETs were combined in a face-to-face orientation. The reproducibility, sensitivity and angular dependence were measured for the dual MOSFET in a 6 MV photon beam. The dual MOSFET was combined with a rectal balloon and irradiated with hypothetical prostate treatments in a phantom. The anterior rectal wall dose was measured in real time and compared with the planning system calculated dose. The dual MOSFET showed angular dependence within ±2.5% in the azimuth and +2.5%/-4% in the polar axes. When compared with an ion chamber measurement in a phantom, the dual MOSFET agreed within 2.5% for a range of radiation path lengths and incident angles. The dual MOSFET had reproducible sensitivity for fraction sizes of 2-10 Gy. For the hypothetical prostate treatments the measured anterior rectal wall dose was 2.6 and 3.2% lower than the calculated dose for 3DCRT and IMRT plans. This was expected due to limitations of the dose calculation method used at the balloon cavity interface. A dual MOSFET combined with a commercial rectal balloon was shown to provide reproducible measurements of the anterior rectal wall dose in real time. The measured anterior rectal wall dose agreed with the expected dose from the treatment plan for 3DCRT and IMRT plans. The dual MOSFET could be read out in real time during the irradiation, providing the capability for real-time dose monitoring of the rectal wall dose during treatment.

  5. A Reconfigurable Series Resonant DC-DC Converter for Wide-Input and Wide-Output Voltages

    DEFF Research Database (Denmark)

    Shen, Yanfeng; Wang, Huai; Qin, Zian

    2017-01-01

    This paper proposes a dual-bridge based LC series resonant dc-dc converter. The input inverter unit incorporates two bridge structures, i.e., a full-bridge inverter and a half-bridge inverter. For the output rectifier, it can be a full-bridge rectifier or an asymmetric half-bridge rectifier. Diff...

  6. Simulation of push-pull inverter using wide bandgap devices

    Science.gov (United States)

    Al-badri, Mustafa; Matin, Mohammed A.

    2016-09-01

    This paper discusses the use of wide bandgap devices (SiC-MOSFET) in the design of a push-pull inverter which provides inexpensive low power dc-ac inverters. The parameters used were 1200V SiC MOSFET(C2M0040120D) made by power company ROHM. This modeling was created using parameters that were provided from a device datasheet. The spice model is provided by this company to study the effect of adding this component on push-pull inverter ordinary circuit and compared results between SiC MOSFET and silicon MOSFET (IRFP260M). The results focused on Vout and Vmos stability as well as on output power and MOSFET power loss because it is a very crucial aspect on DC-AC inverter design. These results are done using the National Instrument simulation program (Multisim 14). It was found that power loss is better in the 12 and 15 vdc inverter. The Vout in the SIC MOSFET circuit shows more stability in the high current low resistance load in comparison to the Silicon MOSFET circuit and this will improve the overall performance of the circuit.

  7. Investigation of the Semicoa 2N7616 and 2N7425 and the Microsemi 2N7480 for Single-Event Gate Rupture and Single-Event Burnout

    Science.gov (United States)

    Scheick, Leif

    2014-01-01

    Single-event-effect test results for hi-rel total-dose-hardened power MOSFETs are presented in this report. The 2N7616 and the 2N7425 from Semicoa and the 2N7480 from International Rectifier were tested to NASA test condition standards and requirements. The 2N7480 performed well and the data agree with the manufacture's data. The 2N7616 and 2N7425 were entry parts from Semicoa using a new device architecture. Unfortunately, the device performed poorly and Semicoa is withdrawing power MOSFETs from it line due to these data. Vertical metal-oxide-semiconductor field-effect transistors (MOSFETs) are the most commonly used power transistor. MOSFETs are typically employed in power supplies and high current switching applications. Due to the inherent high electric fields in the device, power MOSFETs are sensitive to heavy ion irradiation and can fail catastrophically as a result of single-event gate rupture (SEGR) or single-event burnout (SEB). Manufacturers have designed radiation-hardened power MOSFETs for space applications. See [1] through [5] for more information. The objective of this effort was to investigate the SEGR and SEB responses of two power MOSFETs recently produced. These tests will serve as a limited verification of these parts. It is acknowledged that further testing on the respective parts may be needed for some mission profiles.

  8. High-efficiency passive full wave rectification for electromagnetic harvesters

    Science.gov (United States)

    Yilmaz, Mehmet; Tunkar, Bassam A.; Park, Sangtak; Elrayes, Karim; Mahmoud, Mohamed A. E.; Abdel-Rahman, Eihab; Yavuz, Mustafa

    2014-10-01

    We compare the performance of four types of full-wave bridge rectifiers designed for electromagnetic energy harvesters based on silicon diodes, Schottky diodes, passive MOSFETs, and active MOSFETs. Simulation and experimental results show that MOSFET-type rectifiers are more efficient than diode-type rectifiers, reaching voltage and power efficiency of 99% for ideal voltage source with input amplitudes larger than 800 mV. Since active MOSFETs require extra components and an external DC power supply, we conclude that passive MOSFETs are superior for micro-power energy harvesting systems. We demonstrate passive MOSFET rectifiers implemented using discrete, off-shelf components and show that they outperform all electromagnetic harvester rectifiers hitherto reported obtaining a power efficiency of 95%. Furthermore, we show that passive MOSFET rectifiers do not affect the center frequency, harvesting bandwidth, or optimal resistance of electromagnetic harvesters. We demonstrate a complete power management module by adding a capacitor to the rectifier output terminal. We found that this configuration changed the optimal resistive load from 40 Ω to 55 Ω and decreased output power efficiency to 86%.

  9. Development of micro solar charger with blocking relay; Gyakuryu boshi relay wo oyoshita kogata solar judenki no kaihatsu

    Energy Technology Data Exchange (ETDEWEB)

    Nanno, I.; Matsushita, Y. Oka, S. [Omron Corp., Kyoto (Japan)

    1997-11-25

    Heavy-current tiny-scale solar charger is tentatively built, equipped with a function of preventing overcharge and countercurrent in case of charging storage batteries using solar cells. Incorporated into this solar charger are a countercurrent prevention relay system, a low loss current detection system, and a MOSFET parallel connection, which allow the solar charger to be designed small in size in the presence of an increase in heat due to circuit loss. In the countercurrent prevention relay system, the countercurrent prevention diode is bypassed by MOSFETs when too large a current is generated. In the low loss current detection system, currents are detected by use of the ON resistance of the MOSFETs for the prevention of overcharge. In the MOSFET parallel connection, MOSFETs are connected in parallel for a decrease in the ON resistance. The tentatively built charger is then subjected to a performance evaluation test outside the building, and the test is carried out by measuring the temperatures of the MOSFETs and the air. As the result, it is found that the temperature of MOSFET junction of the 12A tiny-size solar charger is approximately 42.5 degC at the highest, low enough to clear the requirements. 4 refs., 7 figs., 4 tabs.

  10. Scheme for the fabrication of ultrashort channel metal-oxide-semiconductor field-effect transistors

    International Nuclear Information System (INIS)

    Appenzeller, J.; Martel, R.; Solomon, P.; Chan, K.; Avouris, Ph.; Knoch, J.; Benedict, J.; Tanner, M.; Thomas, S.; Wang, K. L.

    2000-01-01

    We present a scheme for the fabrication of ultrashort channel length metal-oxide-semiconductor field-effect transistors (MOSFETs) involving nanolithography and molecular-beam epitaxy. The active channel is undoped and is defined by a combination of nanometer-scale patterning and anisotropic etching of an n ++ layer grown on a silicon on insulator wafer. The method is self-limiting and can produce MOSFET devices with channel lengths of less than 10 nm. Measurements on the first batch of n-MOSFET devices fabricated with this approach show very good output characteristics and good control of short-channel effects. (c) 2000 American Institute of Physics

  11. Mathematical Models of the Common-Source and Common-Gate Amplifiers using a Metal-Ferroelectric-Semiconductor Field effect Transistor

    Science.gov (United States)

    Hunt, Mitchell; Sayyah, Rana; Mitchell, Cody; Laws, Crystal; MacLeod, Todd C.; Ho, Fat D.

    2013-01-01

    Mathematical models of the common-source and common-gate amplifiers using metal-ferroelectric- semiconductor field effect transistors (MOSFETs) are developed in this paper. The models are compared against data collected with MOSFETs of varying channel lengths and widths, and circuit parameters such as biasing conditions are varied as well. Considerations are made for the capacitance formed by the ferroelectric layer present between the gate and substrate of the transistors. Comparisons between the modeled and measured data are presented in depth as well as differences and advantages as compared to the performance of each circuit using a MOSFET.

  12. SiC Discrete Power Devices

    National Research Council Canada - National Science Library

    Chilukuri, Ravi

    2001-01-01

    A novel planar vertical MOSFET structure, called ACCUFET, which eliminates both the problem of premature oxide breakdown and low inversion layer mobility has been demonstrated at Power Semiconductor Research Center...

  13. Electrical characterization of Ω-gated uniaxial tensile strained Si nanowire-array metal-oxide-semiconductor field effect transistors with - and channel orientations

    International Nuclear Information System (INIS)

    Habicht, Stefan; Feste, Sebastian; Zhao, Qing-Tai; Buca, Dan; Mantl, Siegfried

    2012-01-01

    Nanowire-array metal-oxide-semiconductor field effect transistors (MOSFETs) were fabricated along and crystal directions on (001) un-/strained silicon-on-insulator substrates. Lateral strain relaxation through patterning was employed to transform biaxial tensile strain into uniaxial tensile strain along the nanowire. Devices feature ideal subthreshold swings and maximum on-current/off-current ratios of 10 11 for n and p-type transistors on both substrates. Electron and hole mobilities were extracted by split C–V method. For p-MOSFETs an increased mobility is observed for channel direction devices compared to devices. The n-MOSFETs showed a 45% increased electron mobility compared to devices. The comparison of strained and unstrained n-MOSFETs along and clearly demonstrates improved electron mobilities for strained channels of both channel orientations.

  14. Spike-compensated Low-Voltage Unity-Gain-Reset Switched-Capacitor Algorithmic Digital-to-Analog Converters

    OpenAIRE

    大野, 憲司; 松本, 寛樹

    2009-01-01

    In this paper, they shows two Low-Voltage Switched-Capacitor (SC) cyclic DACs. They are proposed which consists of a switch, capacitor, MOSFET and operational amplifier (op-amp). Circuit operation is evaluated on SIMetrix.

  15. Analytical expressions for the drain current of a nanotransistor in the off-state regime

    Czech Academy of Sciences Publication Activity Database

    Krahlisch, M.; Wulf, U.; Kučera, Jan; Richter, H.; Höntschel, J.

    2014-01-01

    Roč. 11, č. 1 (2014), s. 113-116 ISSN 1862-6351 Institutional support: RVO:68378271 Keywords : source to drain tunneling * Fowler-Nordheim tunneling * MOSFET * analytical drain current Subject RIV: BM - Solid Matter Physics ; Magnetism

  16. Single photon sources in 4H-SiC metal-oxide-semiconductor field-effect transistors

    Science.gov (United States)

    Abe, Y.; Umeda, T.; Okamoto, M.; Kosugi, R.; Harada, S.; Haruyama, M.; Kada, W.; Hanaizumi, O.; Onoda, S.; Ohshima, T.

    2018-01-01

    We present single photon sources (SPSs) embedded in 4H-SiC metal-oxide-semiconductor field-effect transistors (MOSFETs). They are formed in the SiC/SiO2 interface regions of wet-oxidation C-face 4H-SiC MOSFETs and were not found in other C-face and Si-face MOSFETs. Their bright room-temperature photoluminescence (PL) was observed in the range from 550 to 750 nm and revealed variable multi-peak structures as well as variable peak shifts. We characterized a wide variety of their PL spectra as the inevitable variation of local atomic structures at the interface. Their polarization dependence indicates that they are formed at the SiC side of the interface. We also demonstrate that it is possible to switch on/off the SPSs by a bias voltage of the MOSFET.

  17. A Silicon Carbide Foundry for NASA's UV and High Temperature CMOS Electronics Needs, Phase II

    Data.gov (United States)

    National Aeronautics and Space Administration — CoolCAD Electronics has developed a patent-pending technology to design and fabricate Silicon Carbide (SiC) MOSFET opto-electronic integrated circuits (ICs). We both...

  18. Silicon Carbide Power Device Performance Under Heavy-Ion Irradiation

    Science.gov (United States)

    Lauenstein, Jean-Marie; Casey, Megan; Topper, Alyson; Wilcox, Edward; Phan, Anthony; Ikpe, Stanley; LaBel, Ken

    2015-01-01

    Heavy-ion induced degradation and catastrophic failure data for SiC power MOSFETs and Schottky diodes are examined to provide insight into the challenge of single-event effect hardening of SiC power devices.

  19. Sub Tenth Micron CMOS Devices - A Demonstration of the Virtual Factory Approach to New Structure Design

    National Research Council Canada - National Science Library

    Plummer, James L

    1995-01-01

    ...'. This project is exploring the use of advanced TCAD simulation tools to design a candidate 21st century MOS device - a fully-depleted surrounding gate vertical MOSFET with self-aligned drain contact...

  20. Optimal design of an electret microphone metal-oxide-semiconductor field-effect transistor preamplifier.

    Science.gov (United States)

    van der Donk, A G; Bergveld, P

    1992-04-01

    A theoretical noise analysis of the combination of a capacitive microphone and a preamplifier containing a metal-oxide-semiconductor field-effect transistor (MOSFET) and a high-value resistive bias element is given. It is found that the output signal-to-noise ratio for a source follower and for a common-source circuit is almost the same. It is also shown that the output noise can be reduced by making the microphone capacitance as well as the bias resistor as large as possible, and furthermore by keeping the parasitic gate capacitances as low as possible and finally by using an optimum value for the gate area of the MOSFET. The main noise source is the thermal noise of the gate leakage resistance of the MOSFET. It is also shown that short-channel MOSFETs produce more thermal channel noise than longer channel devices.