WorldWideScience

Sample records for bonded silicon-on-insulator wafers

  1. Characterization of silicon-on-insulator wafers

    Science.gov (United States)

    Park, Ki Hoon

    The silicon-on-insulator (SOI) is attracting more interest as it is being used for an advanced complementary-metal-oxide-semiconductor (CMOS) and a base substrate for novel devices to overcome present obstacles in bulk Si scaling. Furthermore, SOI fabrication technology has improved greatly in recent years and industries produce high quality wafers with high yield. This dissertation investigated SOI material properties with simple, yet accurate methods. The electrical properties of as-grown wafers such as electron and hole mobilities, buried oxide (BOX) charges, interface trap densities, and carrier lifetimes were mainly studied. For this, various electrical measurement techniques were utilized such as pseudo-metal-oxide-semiconductor field-effect-transistor (PseudoMOSFET) static current-voltage (I-V) and transient drain current (I-t), Hall effect, and MOS capacitance-voltage/capacitance-time (C-V/C-t). The electrical characterization, however, mainly depends on the pseudo-MOSFET method, which takes advantage of the intrinsic SOI structure. From the static current-voltage and pulsed measurement, carrier mobilities, lifetimes and interface trap densities were extracted. During the course of this study, a pseudo-MOSFET drain current hysteresis regarding different gate voltage sweeping directions was discovered and the cause was revealed through systematic experiments and simulations. In addition to characterization of normal SOI, strain relaxation of strained silicon-on-insulator (sSOI) was also measured. As sSOI takes advantage of wafer bonding in its fabrication process, the tenacity of bonding between the sSOI and the BOX layer was investigated by means of thermal treatment and high dose energetic gamma-ray irradiation. It was found that the strain did not relax with processes more severe than standard CMOS processes, such as anneals at temperature as high as 1350 degree Celsius.

  2. Characterization of a vertically movable gate field effect transistor using a silicon-on-insulator wafer

    Science.gov (United States)

    Song, In-Hyouk; Forfang, William B. D.; Cole, Bryan; You, Byoung Hee

    2014-10-01

    The vertically movable gate field effect transistor (VMGFET) is a FET-based sensing element, whose gate moves in a vertical direction over the channel. A VMGFET gate covers the region between source and drain. A 1 μm thick air layer separates the gate and the substrate of the VMGFET. A novel fabrication process to form a VMGFET using a silicon-on-insulator (SOI) wafer provides minimal internal stress of the gate structure. The enhancement-type n-channel VMGFET is fabricated with the threshold voltage of 2.32 V in steady state. A non-inverting amplifier is designed and integrated on a printable circuit board (PCB) to characterize device sensitivity and mechanical properties. The VMGFET is mechanically coupled to a speaker membrane to apply mechanical vibration. The oscillated drain current of FET are monitored and sampled with NI LabVIEW. The frequency of the output signal correlates with that of the input stimulus. The resonance frequency of the fabricated VMGFET is measured to be 1.11 kHz. The device sensitivity linearly increases by 0.106 mV/g Hz in the range of 150 Hz and 1 kHz.

  3. Characterization of a vertically movable gate field effect transistor using a silicon-on-insulator wafer

    International Nuclear Information System (INIS)

    Song, In-Hyouk; Forfang, William B D; Cole, Bryan; Hee You, Byoung

    2014-01-01

    The vertically movable gate field effect transistor (VMGFET) is a FET-based sensing element, whose gate moves in a vertical direction over the channel. A VMGFET gate covers the region between source and drain. A 1 μm thick air layer separates the gate and the substrate of the VMGFET. A novel fabrication process to form a VMGFET using a silicon-on-insulator (SOI) wafer provides minimal internal stress of the gate structure. The enhancement-type n-channel VMGFET is fabricated with the threshold voltage of 2.32 V in steady state. A non-inverting amplifier is designed and integrated on a printable circuit board (PCB) to characterize device sensitivity and mechanical properties. The VMGFET is mechanically coupled to a speaker membrane to apply mechanical vibration. The oscillated drain current of FET are monitored and sampled with NI LabVIEW. The frequency of the output signal correlates with that of the input stimulus. The resonance frequency of the fabricated VMGFET is measured to be 1.11 kHz. The device sensitivity linearly increases by 0.106 mV/g Hz in the range of 150 Hz and 1 kHz. (paper)

  4. Wafer bonding applications and technology

    CERN Document Server

    Gösele, Ulrich

    2004-01-01

    During the past decade direct wafer bonding has developed into a mature materials integration technology. This book presents state-of-the-art reviews of the most important applications of wafer bonding written by experts from industry and academia. The topics include bonding-based fabrication methods of silicon-on-insulator, photonic crystals, VCSELs, SiGe-based FETs, MEMS together with hybrid integration and laser lift-off. The non-specialist will learn about the basics of wafer bonding and its various application areas, while the researcher in the field will find up-to-date information about this fast-moving area, including relevant patent information.

  5. Wafer scale formation of monocrystalline silicon-based Mie resonators via silicon-on-insulator dewetting.

    Science.gov (United States)

    Abbarchi, Marco; Naffouti, Meher; Vial, Benjamin; Benkouider, Abdelmalek; Lermusiaux, Laurent; Favre, Luc; Ronda, Antoine; Bidault, Sébastien; Berbezier, Isabelle; Bonod, Nicolas

    2014-11-25

    Subwavelength-sized dielectric Mie resonators have recently emerged as a promising photonic platform, as they combine the advantages of dielectric microstructures and metallic nanoparticles supporting surface plasmon polaritons. Here, we report the capabilities of a dewetting-based process, independent of the sample size, to fabricate Si-based resonators over large scales starting from commercial silicon-on-insulator (SOI) substrates. Spontaneous dewetting is shown to allow the production of monocrystalline Mie-resonators that feature two resonant modes in the visible spectrum, as observed in confocal scattering spectroscopy. Homogeneous scattering responses and improved spatial ordering of the Si-based resonators are observed when dewetting is assisted by electron beam lithography. Finally, exploiting different thermal agglomeration regimes, we highlight the versatility of this technique, which, when assisted by focused ion beam nanopatterning, produces monocrystalline nanocrystals with ad hoc size, position, and organization in complex multimers.

  6. An optical MEMS accelerometer fabricated using double-sided deep reactive ion etching on silicon-on-insulator wafer

    Science.gov (United States)

    Teo, Adrian J. T.; Li, Holden; Tan, Say Hwa; Yoon, Yong-Jin

    2017-06-01

    Optical MEMS devices provide fast detection, electromagnetic resilience and high sensitivity. Using this technology, an optical gratings based accelerometer design concept was developed for seismic motion detection purposes that provides miniaturization, high manufacturability, low costs and high sensitivity. Detailed in-house fabrication procedures of a double-sided deep reactive ion etching (DRIE) on a silicon-on-insulator (SOI) wafer for a micro opto electro mechanical system (MOEMS) device are presented and discussed. Experimental results obtained show that the conceptual device successfully captured motion similar to a commercial accelerometer with an average sensitivity of 13.6 mV G-1, and a highest recorded sensitivity of 44.1 mV G-1. A noise level of 13.5 mV was detected due to experimental setup limitations. This is the first MOEMS accelerometer developed using double-sided DRIE on SOI wafer for the application of seismic motion detection, and is a breakthrough technology platform to open up options for lower cost MOEMS devices.

  7. An optical MEMS accelerometer fabricated using double-sided deep reactive ion etching on silicon-on-insulator wafer

    International Nuclear Information System (INIS)

    Teo, Adrian J T; Li, Holden; Yoon, Yong-Jin; Tan, Say Hwa

    2017-01-01

    Optical MEMS devices provide fast detection, electromagnetic resilience and high sensitivity. Using this technology, an optical gratings based accelerometer design concept was developed for seismic motion detection purposes that provides miniaturization, high manufacturability, low costs and high sensitivity. Detailed in-house fabrication procedures of a double-sided deep reactive ion etching (DRIE) on a silicon-on-insulator (SOI) wafer for a micro opto electro mechanical system (MOEMS) device are presented and discussed. Experimental results obtained show that the conceptual device successfully captured motion similar to a commercial accelerometer with an average sensitivity of 13.6 mV G −1 , and a highest recorded sensitivity of 44.1 mV G −1 . A noise level of 13.5 mV was detected due to experimental setup limitations. This is the first MOEMS accelerometer developed using double-sided DRIE on SOI wafer for the application of seismic motion detection, and is a breakthrough technology platform to open up options for lower cost MOEMS devices. (technical note)

  8. Large current MOSFET on photonic silicon-on-insulator wafers and its monolithic integration with a thermo-optic 2 × 2 Mach-Zehnder switch.

    Science.gov (United States)

    Cong, G W; Matsukawa, T; Chiba, T; Tadokoro, H; Yanagihara, M; Ohno, M; Kawashima, H; Kuwatsuka, H; Igarashi, Y; Masahara, M; Ishikawa, H

    2013-03-25

    n-channel body-tied partially depleted metal-oxide-semiconductor field-effect transistors (MOSFETs) were fabricated for large current applications on a silicon-on-insulator wafer with photonics-oriented specifications. The MOSFET can drive an electrical current as large as 20 mA. We monolithically integrated this MOSFET with a 2 × 2 Mach-Zehnder interferometer optical switch having thermo-optic phase shifters. The static and dynamic performances of the integrated device are experimentally evaluated.

  9. Silicon on insulator self-aligned transistors

    Science.gov (United States)

    McCarthy, Anthony M.

    2003-11-18

    A method for fabricating thin-film single-crystal silicon-on-insulator (SOI) self-aligned transistors. Standard processing of silicon substrates is used to fabricate the transistors. Physical spaces, between the source and gate, and the drain and gate, introduced by etching the polysilicon gate material, are used to provide connecting implants (bridges) which allow the transistor to perform normally. After completion of the silicon substrate processing, the silicon wafer is bonded to an insulator (glass) substrate, and the silicon substrate is removed leaving the transistors on the insulator (glass) substrate. Transistors fabricated by this method may be utilized, for example, in flat panel displays, etc.

  10. Modeling of direct wafer bonding: Effect of wafer bow and etch patterns

    Science.gov (United States)

    Turner, K. T.; Spearing, S. M.

    2002-12-01

    Direct wafer bonding is an important technology for the manufacture of silicon-on-insulator substrates and microelectromechanical systems. As devices become more complex and require the bonding of multiple patterned wafers, there is a need to understand the mechanics of the bonding process. A general bonding criterion based on the competition between the strain energy accumulated in the wafers and the surface energy that is dissipated as the bond front advances is developed. The bonding criterion is used to examine the case of bonding bowed wafers. An analytical expression for the strain energy accumulation rate, which is the quantity that controls bonding, and the final curvature of a bonded stack is developed. It is demonstrated that the thickness of the wafers plays a large role and bonding success is independent of wafer diameter. The analytical results are verified through a finite element model and a general method for implementing the bonding criterion numerically is presented. The bonding criterion developed permits the effect of etched features to be assessed. Shallow etched patterns are shown to make bonding more difficult, while it is demonstrated that deep etched features can facilitate bonding. Model results and their process design implications are discussed in detail.

  11. Effect of nanoscale surface roughness on the bonding energy of direct-bonded silicon wafers

    Science.gov (United States)

    Miki, N.; Spearing, S. M.

    2003-11-01

    Direct wafer bonding of silicon wafers is a promising technology for manufacturing three-dimensional complex microelectromechanical systems as well as silicon-on-insulator substrates. Previous work has reported that the bond quality declines with increasing surface roughness, however, this relationship has not been quantified. This article explicitly correlates the bond quality, which is quantified by the apparent bonding energy, and the surface morphology via the bearing ratio, which describes the area of surface lying above a given depth. The apparent bonding energy is considered to be proportional to the real area of contact. The effective area of contact is defined as the area sufficiently close to contribute to the attractive force between the two bonding wafers. Experiments were conducted with silicon wafers whose surfaces were roughened by a buffered oxide etch solution (BOE, HF:NH4F=1:7) and/or a potassium hydroxide solution. The surface roughness was measured by atomic force microscopy. The wafers were direct bonded to polished "monitor" wafers following a standard RCA cleaning and the resulting bonding energy was measured by the crack-opening method. The experimental results revealed a clear correlation between the bonding energy and the bearing ratio. A bearing depth of ˜1.4 nm was found to be appropriate for the characterization of direct-bonded silicon at room temperature, which is consistent with the thickness of the water layer at the interface responsible for the hydrogen bonds that link the mating wafers.

  12. Handbook of wafer bonding

    CERN Document Server

    Ramm, Peter; Taklo, Maaike M V

    2011-01-01

    Written by an author and editor team from microsystems companies and industry-near research organizations, this handbook and reference presents dependable, first-hand information on bonding technologies.In the first part, researchers from companies and institutions around the world discuss the most reliable and reproducible technologies for the production of bonded wafers. The second part is devoted to current and emerging applications, including microresonators, biosensors and precise measuring devices.

  13. A high-temperature silicon-on-insulator stress sensor

    International Nuclear Information System (INIS)

    Wang Zheyao; Tian Kuo; Zhou Youzheng; Pan Liyang; Liu Litian; Hu Chaohong

    2008-01-01

    A piezoresistive stress sensor is developed using silicon-on-insulator (SOI) wafers and calibrated for stress measurement for high-temperature applications. The stress sensor consists of 'silicon-island-like' piezoresistor rosettes that are etched on the SOI layer. This eliminates leakage current and enables excellent electrical insulation at high temperature. To compensate for the measurement errors caused by the misalignment of the piezoresistor rosettes with respect to the crystallographic axes, an anisotropic micromachining technique, tetramethylammonium hydroxide etching, is employed to alleviate the misalignment issue. To realize temperature-compensated stress measurement, a planar diode is fabricated as a temperature sensor to decouple the temperature information from the piezoresistors, which are sensitive to both stress and temperature. Design, fabrication and calibration of the piezoresistors are given. SOI-related characteristics such as piezoresistive coefficients and temperature coefficients as well as the influence of the buried oxide layer are discussed in detail

  14. Voltage-assisted polymer wafer bonding

    International Nuclear Information System (INIS)

    Varsanik, J S; Bernstein, J J

    2012-01-01

    Polymer wafer bonding is a widely used process for fabrication of microfluidic devices. However, best practices for polymer bonds do not achieve sufficient bond strength for many applications. By applying a voltage to a polymer bond in a process called voltage-assisted bonding, bond strength is shown to improve dramatically for two polymers (Cytop™ and poly(methyl methacrylate)). Several experiments were performed to provide a starting point for further exploration of this technique. An optimal voltage range is experimentally observed with a reduction in bonding strength at higher voltages. Additionally, voltage-assisted bonding is shown to reduce void diameter due to bond defects. An electrostatic force model is proposed to explain the improved bond characteristics. This process can be used to improve bond strength for most polymers. (paper)

  15. Mechanics of wafer bonding: Effect of clamping

    Science.gov (United States)

    Turner, K. T.; Thouless, M. D.; Spearing, S. M.

    2004-01-01

    A mechanics-based model is developed to examine the effects of clamping during wafer bonding processes. The model provides closed-form expressions that relate the initial geometry and elastic properties of the wafers to the final shape of the bonded pair and the strain energy release rate at the interface for two different clamping configurations. The results demonstrate that the curvature of bonded pairs may be controlled through the use of specific clamping arrangements during the bonding process. Furthermore, it is demonstrated that the strain energy release rate depends on the clamping configuration and that using applied loads usually leads to an undesirable increase in the strain energy release rate. The results are discussed in detail and implications for process development and bonding tool design are highlighted.

  16. Silicon waveguides produced by wafer bonding

    DEFF Research Database (Denmark)

    Poulsen, Mette; Jensen, Flemming; Bunk, Oliver

    2005-01-01

    X-ray waveguides are successfully produced employing standard silicon technology of UV photolithography and wafer bonding. Contrary to theoretical expectations for similar systems even 100 mu m broad guides of less than 80 nm height do not collapse and can be used as one dimensional waveguides...

  17. A comparison of buried oxide characteristics of single and multiple implant SIMOX and bond and etch back wafers

    International Nuclear Information System (INIS)

    Annamalai, N.K.; Bockman, J.F.; McGruer, N.E.; Chapski, J.

    1990-01-01

    The current through the buried oxides of single and multiple implant SIMOX and bond and etch back silicon-on-insulator (BESOI) wafers were measured as a function of radiation dose. From these measurements, conductivity and static capacitances were derived. High frequency capacitances were also measured. Leakage current through the buried oxide of multiple implant SIMOX is considerably less than that of single implant SIMOX (more than an order of magnitude). High frequency and static capacitances, as a function of total dose, were used to study the buried oxide---top silicon interface and the buried oxide---bottom silicon interface. Multiple implant had fewer interface traps than single implant at pre-rad and after irradiation

  18. Sol-gel bonding of silicon wafers

    International Nuclear Information System (INIS)

    Barbe, C.J.; Cassidy, D.J.; Triani, G.; Latella, B.A.; Mitchell, D.R.G.; Finnie, K.S.; Short, K.; Bartlett, J.R.; Woolfrey, J.L.; Collins, G.A.

    2005-01-01

    Sol-gel bonds have been produced between smooth, clean silicon substrates by spin-coating solutions containing partially hydrolysed silicon alkoxides. The two coated substrates were assembled and the resulting sandwich fired at temperatures ranging from 60 to 600 deg. C. The sol-gel coatings were characterised using attenuated total reflectance Fourier transform infrared spectroscopy, ellipsometry, and atomic force microscopy, while the corresponding bonded specimens were investigated using scanning electron microscopy and cross-sectional transmission electron microscopy. Mechanical properties were characterised using both microindentation and tensile testing. Bonding of silicon wafers has been successfully achieved at temperatures as low as 60 deg. C. At 300 deg. C, the interfacial fracture energy was 1.55 J/m 2 . At 600 deg. C, sol-gel bonding provided superior interfacial fracture energy over classical hydrophilic bonding (3.4 J/m 2 vs. 1.5 J/m 2 ). The increase in the interfacial fracture energy is related to the increase in film density due to the sintering of the sol-gel interface with increasing temperature. The superior interfacial fracture energy obtained by sol-gel bonding at low temperature is due to the formation of an interfacial layer, which chemically bonds the two sol-gel coatings on each wafer. Application of a tensile stress on the resulting bond leads to fracture of the samples at the silicon/sol-gel interface

  19. Sol-gel bonding of silicon wafers

    International Nuclear Information System (INIS)

    Barbe, C.J.; Cassidy, D.J.; Triani, G.; Latella, B.A.; Mitchell, D.R.G.; Finnie, K.S.; Bartlett, J.R.; Woolfrey, J.L.; Collins, G.A.

    2005-01-01

    Low temperature bonding of silicon wafers was achieved using sol-gel technology. The initial sol-gel chemistry of the coating solution was found to influence the mechanical properties of the resulting bonds. More precisely, the influence of parameters such as the alkoxide concentration, water-to-alkoxide molar ratio, pH, and solution aging on the final bond morphologies and interfacial fracture energy was studied. The thickness and density of the sol-gel coating were characterised using ellipsometry. The corresponding bonded specimens were investigated using attenuated total reflectance Fourier transformed infrared spectroscopy to monitor their chemical composition, infrared imaging to control bond integrity, and cross-sectional transmission electron microscopy to study their microstructure. Their interfacial fracture energy was measured using microindentation. An optimum water-to-alkoxide molar ratio of 10 and hydrolysis water at pH = 2 were found. Such conditions led to relatively dense films (> 90%), resulting in bonds with a fracture energy of 3.5 J/m 2 , significantly higher than those obtained using classical hydrophilic bonding (typically 1.5-2.5 J/m 2 ). Ageing of the coating solution was found to decrease the bond strength

  20. Silicon-on-Insulator Nanowire Based Optical Waveguide Biosensors

    International Nuclear Information System (INIS)

    Li, Mingyu; Liu, Yong; Chen, Yangqing; He, Jian-Jun

    2016-01-01

    Optical waveguide biosensors based on silicon-on-insulator (SOI) nanowire have been developed for label free molecular detection. This paper reviews our work on the design, fabrication and measurement of SOI nanowire based high-sensitivity biosensors employing Vernier effect. Biosensing experiments using cascaded double-ring sensor and Mach-Zehnder- ring sensor integrated with microfluidic channels are demonstrated (paper)

  1. MEMS packaging with etching and thinning of lid wafer to form lids and expose device wafer bond pads

    Science.gov (United States)

    Chanchani, Rajen; Nordquist, Christopher; Olsson, Roy H; Peterson, Tracy C; Shul, Randy J; Ahlers, Catalina; Plut, Thomas A; Patrizi, Gary A

    2013-12-03

    In wafer-level packaging of microelectromechanical (MEMS) devices a lid wafer is bonded to a MEMS wafer in a predermined aligned relationship. Portions of the lid wafer are removed to separate the lid wafer into lid portions that respectively correspond in alignment with MEMS devices on the MEMS wafer, and to expose areas of the MEMS wafer that respectively contain sets of bond pads respectively coupled to the MEMS devices.

  2. Direct Wafer Bonding and Its Application to Waveguide Optical Isolators.

    Science.gov (United States)

    Mizumoto, Tetsuya; Shoji, Yuya; Takei, Ryohei

    2012-05-24

    This paper reviews the direct bonding technique focusing on the waveguide optical isolator application. A surface activated direct bonding technique is a powerful tool to realize a tight contact between dissimilar materials. This technique has the potential advantage that dissimilar materials are bonded at low temperature, which enables one to avoid the issue associated with the difference in thermal expansion. Using this technique, a magneto-optic garnet is successfully bonded on silicon, III-V compound semiconductors and LiNbO₃. As an application of this technique, waveguide optical isolators are investigated including an interferometric waveguide optical isolator and a semileaky waveguide optical isolator. The interferometric waveguide optical isolator that uses nonreciprocal phase shift is applicable to a variety of waveguide platforms. The low refractive index of buried oxide layer in a silicon-on-insulator (SOI) waveguide enhances the magneto-optic phase shift, which contributes to the size reduction of the isolator. A semileaky waveguide optical isolator has the advantage of large fabrication-tolerance as well as a wide operation wavelength range.

  3. Direct Wafer Bonding and Its Application to Waveguide Optical Isolators

    Directory of Open Access Journals (Sweden)

    Ryohei Takei

    2012-05-01

    Full Text Available This paper reviews the direct bonding technique focusing on the waveguide optical isolator application. A surface activated direct bonding technique is a powerful tool to realize a tight contact between dissimilar materials. This technique has the potential advantage that dissimilar materials are bonded at low temperature, which enables one to avoid the issue associated with the difference in thermal expansion. Using this technique, a magneto-optic garnet is successfully bonded on silicon, III-V compound semiconductors and LiNbO3. As an application of this technique, waveguide optical isolators are investigated including an interferometric waveguide optical isolator and a semileaky waveguide optical isolator. The interferometric waveguide optical isolator that uses nonreciprocal phase shift is applicable to a variety of waveguide platforms. The low refractive index of buried oxide layer in a silicon-on-insulator (SOI waveguide enhances the magneto-optic phase shift, which contributes to the size reduction of the isolator. A semileaky waveguide optical isolator has the advantage of large fabrication-tolerance as well as a wide operation wavelength range.

  4. Si-to-Si wafer bonding using evaporated glass

    DEFF Research Database (Denmark)

    Reus, Roger De; Lindahl, M.

    1997-01-01

    Anodic bonding of Si to Si four inch wafers using evaporated glass was performed in air at temperatures ranging from 300°C to 450°C. Although annealing of Si/glass structures around 340°C for 15 minutes eliminates stress, the bonded wafer pairs exhibit compressive stress. Pull testing revealed...

  5. Hydrogen interactions with silicon-on-insulator materials

    OpenAIRE

    Rivera de Mena, A.J.

    2003-01-01

    The booming of microelectronics in recent decades has been made possible by the excellent properties of the Si/SiO2 interface in oxide on silicon systems.. This semiconductor/insulator combination has proven to be of great value for the semiconductor industry. It has made it possible to continuously increase the number of transistors per chip until the physical limit of integration is now almost reached. Silicon-on-insulator (SOI) materials were early on seen as a step in the logical evolutio...

  6. Integrated programmable photonic filter on the silicon -on- insulator platform

    DEFF Research Database (Denmark)

    Liao, Shasha; Ding, Yunhong; Peucheret, Christophe

    2014-01-01

    We propose and demonstrate a silicon - on - insulator (SOI) on - chip programmable filter based on a four - tap finite impulse response structure. The photonic filter is programmable thanks to amplitude and phase modulation of each tap controlled by thermal heater s. We further demonstrate...... the tunability of the filter central wavelength, bandwidth and variable passband shape. The tuning range of the central wavelength is at least 42% of the free spectral range. The bandwidth tuning range is at least half of the free spectral range. Our scheme has distinct advantages of compactness, capability...

  7. Cohesive zone model for direct silicon wafer bonding

    Science.gov (United States)

    Kubair, D. V.; Spearing, S. M.

    2007-05-01

    Direct silicon wafer bonding and decohesion are simulated using a spectral scheme in conjunction with a rate-dependent cohesive model. The cohesive model is derived assuming the presence of a thin continuum liquid layer at the interface. Cohesive tractions due to the presence of a liquid meniscus always tend to reduce the separation distance between the wafers, thereby opposing debonding, while assisting the bonding process. In the absence of the rate-dependence effects the energy needed to bond a pair of wafers is equal to that needed to separate them. When rate-dependence is considered in the cohesive law, the experimentally observed asymmetry in the energetics can be explained. The derived cohesive model has the potential to form a bridge between experiments and a multiscale-modelling approach to understand the mechanics of wafer bonding.

  8. Fluorine-enhanced low-temperature wafer bonding of native-oxide covered Si wafers

    Science.gov (United States)

    Tong, Q.-Y.; Gan, Q.; Fountain, G.; Enquist, P.; Scholz, R.; Gösele, U.

    2004-10-01

    The bonding energy of bonded native-oxide-covered silicon wafers treated in the HNO3/H2O/HF or the HNO3/HF solution prior to room-temperature contact is significantly higher than bonded standard RCA1 cleaned wafer pairs after low-temperature annealing. The bonding energy reaches over 2000mJ/m2 after annealing at 100 °C. The very slight etching and fluorine in the chemically grown oxide are believed to be the main contributors to the enhanced bonding energy. Transmission-electron-microscopic images have shown that the chemically formed native oxide at bonding interface is embedded with many flake-like cavities. The cavities can absorb the by-products of the interfacial reactions that result in covalent bond formation at low temperatures allowing the strong bond to be retained.

  9. Physical mechanisms of Cu-Cu wafer bonding

    International Nuclear Information System (INIS)

    Rebhan, B.

    2014-01-01

    Modern manufacturing processes of complex integrated semiconductor devices are based on wafer-level manufacturing of components which are subsequently interconnected. When compared with classical monolithic bi-dimensional integrated circuits (2D ICs), the new approach of three-dimensional integrated circuits (3D ICs) exhibits significant benefits in terms of signal propagation delay and power consumption due to the reduced metal interconnection length and allows high integration levels with reduced form factor. Metal thermo-compression bonding is a process suitable for 3D interconnects applications at wafer level, which facilitates the electrical and mechanical connection of two wafers even processed in different technologies, such as complementary metal oxide semiconductor (CMOS) and microelectromechanical systems (MEMS). Due to its high electrical conductivity, copper is a very attractive material for electrical interconnects. For Cu-Cu wafer bonding the process requires typically bonding for around 1 h at 400°C and high contact pressure applied during bonding. Temperature reduction below such values is required in order to solve issues regarding (i) throughput in the wafer bonder, (ii) wafer-to-wafer misalignment after bonding and (iii) to minimise thermo-mechanical stresses or device degradation. The aim of this work was to study the physical mechanisms of Cu-Cu bonding and based on this study to further optimise the bonding process for low temperatures. The critical sample parameters (roughness, oxide, crystallinity) were identified using selected analytical techniques and correlated with the characteristics of the bonded Cu-Cu interfaces. Based on the results of this study the impact of several materials and process specifications on the bonding result were theoretically defined and experimentally proven. These fundamental findings subsequently facilitated low temperature (LT) metal thermo-compression Cu-Cu wafer bonding and even room temperature direct

  10. Bond strength tests between silicon wafers and duran tubes (fusion bonded fluidic interconnects)

    NARCIS (Netherlands)

    Fazal, I.; Berenschot, Johan W.; de Boer, J.H.; Jansen, Henricus V.; Elwenspoek, Michael Curt

    2005-01-01

    The fusion bond strength of glass tubes with standard silicon wafers is presented. Experiments with plain silicon wafers and those coated with silicon oxide and silicon nitride are presented. Results obtained are discussed in terms of homogeneity and strength of fusion bond. High pressure testing

  11. Influence of germanium on thermal dewetting and agglomeration of the silicon template layer in thin silicon-on-insulator

    International Nuclear Information System (INIS)

    Zhang, P P; Yang, B; Rugheimer, P P; Roberts, M M; Savage, D E; Lagally, M G; Liu Feng

    2009-01-01

    We investigate the influence of heteroepitaxially grown Ge on the thermal dewetting and agglomeration of the Si(0 0 1) template layer in ultrathin silicon-on-insulator (SOI). We show that increasing Ge coverage gradually destroys the long-range ordering of 3D nanocrystals along the (1 3 0) directions and the 3D nanocrystal shape anisotropy that are observed in the dewetting and agglomeration of pure SOI(0 0 1). The results are qualitatively explained by Ge-induced bond weakening and decreased surface energy anisotropy. Ge lowers the dewetting and agglomeration temperature to as low as 700 0 C.

  12. Local sensor based on nanowire field effect transistor from inhomogeneously doped silicon on insulator

    Science.gov (United States)

    Presnov, Denis E.; Bozhev, Ivan V.; Miakonkikh, Andrew V.; Simakin, Sergey G.; Trifonov, Artem S.; Krupenin, Vladimir A.

    2018-02-01

    We present the original method for fabricating a sensitive field/charge sensor based on field effect transistor (FET) with a nanowire channel that uses CMOS-compatible processes only. A FET with a kink-like silicon nanowire channel was fabricated from the inhomogeneously doped silicon on insulator wafer very close (˜100 nm) to the extremely sharp corner of a silicon chip forming local probe. The single e-beam lithographic process with a shadow deposition technique, followed by separate two reactive ion etching processes, was used to define the narrow semiconductor nanowire channel. The sensors charge sensitivity was evaluated to be in the range of 0.1-0.2 e /√{Hz } from the analysis of their transport and noise characteristics. The proposed method provides a good opportunity for the relatively simple manufacture of a local field sensor for measuring the electrical field distribution, potential profiles, and charge dynamics for a wide range of mesoscopic objects. Diagnostic systems and devices based on such sensors can be used in various fields of physics, chemistry, material science, biology, electronics, medicine, etc.

  13. Cost-Efficient Wafer-Level Capping for MEMS and Imaging Sensors by Adhesive Wafer Bonding

    Directory of Open Access Journals (Sweden)

    Simon J. Bleiker

    2016-10-01

    Full Text Available Device encapsulation and packaging often constitutes a substantial part of the fabrication cost of micro electro-mechanical systems (MEMS transducers and imaging sensor devices. In this paper, we propose a simple and cost-effective wafer-level capping method that utilizes a limited number of highly standardized process steps as well as low-cost materials. The proposed capping process is based on low-temperature adhesive wafer bonding, which ensures full complementary metal-oxide-semiconductor (CMOS compatibility. All necessary fabrication steps for the wafer bonding, such as cavity formation and deposition of the adhesive, are performed on the capping substrate. The polymer adhesive is deposited by spray-coating on the capping wafer containing the cavities. Thus, no lithographic patterning of the polymer adhesive is needed, and material waste is minimized. Furthermore, this process does not require any additional fabrication steps on the device wafer, which lowers the process complexity and fabrication costs. We demonstrate the proposed capping method by packaging two different MEMS devices. The two MEMS devices include a vibration sensor and an acceleration switch, which employ two different electrical interconnection schemes. The experimental results show wafer-level capping with excellent bond quality due to the re-flow behavior of the polymer adhesive. No impediment to the functionality of the MEMS devices was observed, which indicates that the encapsulation does not introduce significant tensile nor compressive stresses. Thus, we present a highly versatile, robust, and cost-efficient capping method for components such as MEMS and imaging sensors.

  14. Science and technology of plasma activated direct wafer bonding

    Science.gov (United States)

    Roberds, Brian Edward

    This dissertation studied the kinetics of silicon direct wafer bonding with emphasis on low temperature bonding mechanisms. The project goals were to understand the topological requirements for initial bonding, develop a tensile test to measure the bond strength as a function of time and temperature and, using the kinetic information obtained, develop lower temperature methods of bonding. A reproducible surface metrology metric for bonding was best described by power spectral density derived from atomic force microscopy measurements. From the tensile strength kinetics study it was found that low annealing temperatures could be used to obtain strong bonds, but at the expense of longer annealing times. Three models were developed to describe the kinetics. A diffusion controlled model and a reaction rate controlled model were developed for the higher temperature regimes (T > 600sp°C), and an electric field assisted oxidation model was proposed for the low temperature range. An in situ oxygen plasma treatment was used to further enhance the field-controlled mechanism which resulted in dramatic increases in the low temperature bonding kinetics. Multiple internal transmission Fourier transform infrared spectroscopy (MIT-FTIR) was used to monitor species evolution at the bonded interface and a capacitance-voltage (CV) study was undertaken to investigate charge distribution and surface states resulting from plasma activation. A short, less than a minute, plasma exposure prior to contacting the wafers was found to obtain very strong bonds for hydrophobic silicon wafers at very low temperatures (100sp°C). This novel bonding method may enable new technologies involving heterogeneous material systems or bonding partially fabricated devices to become realities.

  15. Silicon-to-silicon wafer bonding using evaporated glass

    DEFF Research Database (Denmark)

    Weichel, Steen; Reus, Roger De; Lindahl, M.

    1998-01-01

    Anodic bending of silicon to silicon 4-in. wafers using an electron-beam evaporated glass (Schott 8329) was performed successfully in air at temperatures ranging from 200 degrees C to 450 degrees C. The composition of the deposited glass is enriched in sodium as compared to the target material....... The roughness of the as-deposited films was below 5 nm and was found to be unchanged by annealing at 500 degrees C for 1 h in air. No change in the macroscopic edge profiles of the glass film was found as a function of annealing; however, small extrusions appear when annealing above 450 degrees C. Annealing...... of silicon/glass structures in air around 340 degrees C for 15 min leads to stress-free structures. Bonded wafer pairs, however, show no reduction in stress and always exhibit compressive stress. The bond yield is larger than 95% for bonding temperatures around 350 degrees C and is above 80% for bonding...

  16. Comparative TEM study of bonded silicon/silicon interfaces fabricated by hydrophilic, hydrophobic and UHV wafer bonding

    International Nuclear Information System (INIS)

    Reznicek, A.; Scholz, R.; Senz, S.; Goesele, U.

    2003-01-01

    Wafers of Czochralski-grown silicon were bonded hydrophilically, hydrophobically and in ultrahigh vacuum (UHV) at room temperature. Wafers bonded hydrophilically adhere together by hydrogen bonds, those bonded hydrophobically by van der Waals forces and UHV-bonded ones by covalent bonds. Annealing the pre-bonded hydrophilic and hydrophobic wafer pairs in argon for 2 h at different temperatures increases the initially low bonding energy. UHV-bonded wafer pairs were also annealed to compare the results. Transmission electron microscopy (TEM) investigations show nano-voids at the interface. The void density depends on the initial bonding strength. During annealing the shape, coverage and density of the voids change significantly

  17. Fusion bonding of Si wafers investigated by x ray diffraction

    DEFF Research Database (Denmark)

    Weichel, Steen; Grey, Francois; Rasmussen, Kurt

    2000-01-01

    The interface structure of bonded Si(001) wafers with twist angle 6.5 degrees is studied as a function of annealing temperature. An ordered structure is observed in x-ray diffraction by monitoring a satellite reflection due to the periodic modulation near the interface, which results from...

  18. Sacrificial wafer bonding for planarization after very deep etching

    NARCIS (Netherlands)

    Spiering, V.L.; Spiering, Vincent L.; Berenschot, Johan W.; Elwenspoek, Michael Curt; Fluitman, J.H.J.

    A new technique is presented that provides planarization after a very deep etching step in silicon. This offers the possibility for as well resist spinning and layer patterning as realization of bridges or cantilevers across deep holes or grooves. The sacrificial wafer bonding technique contains a

  19. Physical mechanisms of copper-copper wafer bonding

    International Nuclear Information System (INIS)

    Rebhan, B.; Hingerl, K.

    2015-01-01

    The study of the physical mechanisms driving Cu-Cu wafer bonding allowed for reducing the bonding temperatures below 200 °C. Metal thermo-compression Cu-Cu wafer bonding results obtained at such low temperatures are very encouraging and suggest that the process is possible even at room temperature if some boundary conditions are fulfilled. Sputtered (PVD) and electroplated Cu thin layers were investigated, and the analysis of both metallization techniques demonstrated the importance of decreasing Cu surface roughness. For an equal surface roughness, the bonding temperature of PVD Cu wafers could be even further reduced due to the favorable microstructure. Their smaller grain size enhances the length of the grain boundaries (observed on the surface prior bonding), acting as efficient mass transfer channels across the interface, and hence the grains are able to grow over the initial bonding interface. Due to the higher concentration of random high-angle grain boundaries, this effect is intensified. The model presented is explaining the microstructural changes based on atomic migration, taking into account that the reduction of the grain boundary area is the major driving force to reduce the Gibbs free energy, and predicts the subsequent microstructure evolution (grain growth) during thermal annealing

  20. Guided Acoustic and Optical Waves in Silicon-on-Insulator for Brillouin Scattering and Optomechanics

    Science.gov (United States)

    2016-08-01

    APL PHOTONICS 1, 071301 (2016) Guided acoustic and optical waves in silicon-on- insulator for Brillouin scattering and optomechanics Christopher J...is possible to simultaneously guide optical and acoustic waves in the technologically important silicon on insulator (SOI) material system. Thin...high sound velocity — makes guiding acoustic waves difficult, motivating the use of soft chalcogenide glasses and partial or complete releases (removal

  1. ARROW-based silicon-on-insulator photonic crystal waveguides with reduced losses

    DEFF Research Database (Denmark)

    Lavrinenko, Andrei; Novitsky, A.; Zhilko, V.V.

    2006-01-01

    We employ an antiresonant reflecting layers arrangement with silicon-on-insulator based photonic crystal waveguides. The 3D FDTD numerical modelling reveals improved transmission in such structures with a promising potential for their application in photonic circuits.......We employ an antiresonant reflecting layers arrangement with silicon-on-insulator based photonic crystal waveguides. The 3D FDTD numerical modelling reveals improved transmission in such structures with a promising potential for their application in photonic circuits....

  2. Low-temperature Au/a-Si wafer bonding

    International Nuclear Information System (INIS)

    Jing, Errong; Xiong, Bin; Wang, Yuelin

    2011-01-01

    The Si/SiO 2 /Ti/Au–Au/Ti/a-Si/SiO 2 /Si bonding structure, which can also be used for the bonding of non-silicon material, was investigated for the first time in this paper. The bond quality test showed that the bond yield, bond repeatability and average shear strength are higher for this bonding structure. The interfacial microstructure analysis indicated that the Au-induced crystallization of the amorphous silicon process leads to big Si grains extending across the bond interface and Au filling the other regions of the bond interface, which result into a strong and void-free bond interface. In addition, the Au-induced crystallization reaction leads to a change in the IR images of the bond interface. Therefore, the IR microscope can be used to evaluate and compare the different bond strengths qualitatively. Furthermore, in order to verify the superiority of the bonding structure, the Si/SiO 2 /Ti/Au–a-Si/SiO 2 /Si (i.e. no Ti/Au layer on the a-Si surface) and Si/SiO 2 /Ti/Au–Au/Ti/SiO 2 /Si bonding structures (i.e. Au thermocompression bonding) were also investigated. For the Si/SiO 2 /Ti/Au–a-Si/SiO 2 /Si bonding structure, the poor bond quality is due to the native oxide layer on the a-Si surface, and for the Si/SiO 2 /Ti/Au–Au/Ti/SiO 2 /Si bonding structure, the poor bond quality is caused by the wafer surface roughness which prevents intimate contact and limits the interdiffusion at the bond interface.

  3. Performance of current-in-plane pseudo-spin-valve devices on CMOS silicon-on-insulator underlayers

    Science.gov (United States)

    Katti, R. R.; Zou, D.; Reed, D.; Schipper, D.; Hynes, O.; Shaw, G.; Kaakani, H.

    2003-05-01

    Prior work has shown that current-in-plane (CIP) giant magnetoresistive (GMR) pseudo-spin-valve (PSV) devices grown on bulk Si wafers and bulk complementary metal-oxide semiconductor (CMOS) underlayers exhibit write and read characteristics that are suitable for application as nonvolatile memory devices. In this work, CIP GMR PSV devices fabricated on silicon-on-insulator CMOS underlayers are shown to support write and read performance. Reading and writing fields for selected devices are shown to be approximately 25%-50% that of unselected devices, which provides a margin for reading and writing specific bits in a memory without overwriting bits and without disturbing other bits. The switching characteristics of experimental devices were compared to and found to be similar with Landau-Lifschitz-Gilbert micromagnetic modeling results, which allowed inferring regions of reversible and irreversible rotations in magnetic reversal processes.

  4. Characterization of light element impurities in ultrathin silicon-on-insulator layers by luminescence activation using electron irradiation

    International Nuclear Information System (INIS)

    Nakagawa-Toyota, Satoko; Tajima, Michio; Hirose, Kazuyuki; Ohshima, Takeshi; Itoh, Hisayoshi

    2009-01-01

    We analyzed light element impurities in ultrathin top Si layers of silicon-on-insulator (SOI) wafers by luminescence activation using electron irradiation. Photoluminescence (PL) analysis under ultraviolet (UV) light excitation was performed on various commercial SOI wafers after the irradiation. We detected the C-line related to a complex of interstitial carbon and oxygen impurities and the G-line related to a complex of interstitial and substitutional carbon impurities in the top Si layer with a thickness down to 62 nm after electron irradiation. We showed that there were differences in the impurity concentration depending on the wafer fabrication methods and also that there were variations in these concentrations in the respective wafers. Xenon ion implantation was used to activate top Si layers selectively so that we could confirm that the PL signal under the UV light excitation comes not from substrates but from top Si layers. The present method is a very promising tool to evaluate the light element impurities in top Si layers. (author)

  5. Simplified nonplanar wafer bonding for heterogeneous device integration

    Science.gov (United States)

    Geske, Jon; Bowers, John E.; Riley, Anton

    2004-07-01

    We demonstrate a simplified nonplanar wafer bonding technique for heterogeneous device integration. The improved technique can be used to laterally integrate dissimilar semiconductor device structures on a lattice-mismatched substrate. Using the technique, two different InP-based vertical-cavity surface-emitting laser active regions have been integrated onto GaAs without compromising the quality of the photoluminescence. Experimental and numerical simulation results are presented.

  6. Ultra-low-loss inverted taper coupler for silicon-on-insulator ridge waveguide

    DEFF Research Database (Denmark)

    Pu, Minhao; Liu, Liu; Ou, Haiyan

    2010-01-01

    An ultra-low-loss coupler for interfacing a silicon-on-insulator ridge waveguide and a single-mode fiber in both polarizations is presented. The inverted taper coupler, embedded in a polymer waveguide, is optimized for both the transverse-magnetic and transverse-electric modes through tapering...... the width of the silicon-on-insulator waveguide from 450 nm down to less than 15 nm applying a thermal oxidation process. Two inverted taper couplers are integrated with a 3-mm long silicon-on-insulator ridge waveguide in the fabricated sample. The measured coupling losses of the inverted taper coupler...... for transverse-magnetic and transverse-electric modes are ~0.36 dB and ~0.66 dB per connection, respectively....

  7. 360° tunable microwave phase shifter based on silicon-on-insulator dual-microring resonator

    DEFF Research Database (Denmark)

    Pu, Minhao; Xue, Weiqi; Liu, Liu

    2010-01-01

    We demonstrate tunable microwave phase shifters based on electrically tunable silicon-on-insulator dual-microring resonators. A quasi-linear phase shift of 360° with ~2dB radio frequency power variation at a microwave frequency of 40GHz is obtained......We demonstrate tunable microwave phase shifters based on electrically tunable silicon-on-insulator dual-microring resonators. A quasi-linear phase shift of 360° with ~2dB radio frequency power variation at a microwave frequency of 40GHz is obtained...

  8. Ultra-low loss nano-taper coupler for Silicon-on-Insulator ridge waveguide

    DEFF Research Database (Denmark)

    Pu, Minhao; Liu, Liu; Ou, Haiyan

    2010-01-01

    A nano-taper coupler is optimized specially for the transverse-magnetic mode for interfacing light between a silicon-on-insulator ridge waveguide and a single-mode fiber. An ultra-low coupling loss of ~0.36dB is achieved for the nano-taper coupler.......A nano-taper coupler is optimized specially for the transverse-magnetic mode for interfacing light between a silicon-on-insulator ridge waveguide and a single-mode fiber. An ultra-low coupling loss of ~0.36dB is achieved for the nano-taper coupler....

  9. Automotive SOI-BCD Technology Using Bonded Wafers

    International Nuclear Information System (INIS)

    Himi, H.; Fujino, S.

    2008-01-01

    The SOI-BCD device is excelling in high temperature operation and noise immunity because the integrated elements can be electrically separated by dielectric isolation. We have promptly paid attention to this feature and have concentrated to develop SOI-BCD devices seeking to match the automotive requirement. In this paper, the feature technologies specialized for automotive SOI-BCD devices, such as buried N + layer for impurity gettering and noise shielding, LDMOS with improved ESD robustness, crystal defect-less process, and wafer direct bonding through the amorphous layer for intelligent power IC are introduced.

  10. Widely tunable microwave phase shifter based on silicon-on-insulator dual-microring resonator

    DEFF Research Database (Denmark)

    Pu, Minhao; Liu, Liu; Xue, Weiqi

    2010-01-01

    We propose and demonstrate tunable microwave phase shifters based on electrically tunable silicon-on-insulator microring resonators. The phase-shifting range and the RF-power variation are analyzed. A maximum phase-shifting range of 0~600° is achieved by utilizing a dual-microring resonator...

  11. Nonlinear Optical Functions in Crystalline and Amorphous Silicon-on-Insulator Nanowires

    DEFF Research Database (Denmark)

    Baets, R.; Kuyken, B.; Liu, X.

    2012-01-01

    Silicon-on-Insulator nanowires provide an excellent platform for nonlinear optical functions in spite of the two-photon absorption at telecom wavelengths. Work on both crystalline and amorphous silicon nanowires is reviewed, in the wavelength range of 1.5 to 2.5 µm....

  12. Silicon on insulator technology. Characteristics. Applications; Technologies silicium sur isolant. Caracteristiques. Exemples d'application

    Energy Technology Data Exchange (ETDEWEB)

    Suat, J. P.; Peccoud, L.; Le Goascoz, V.; Garcia, M.; Mackowiak, E.

    1975-01-31

    The advantages resulting from a SOS (Silicon-on-Sapphire) MOS technology are demonstrated. Experimental results giving the performance of C.MOS and depletion-enrichment P-channel technologies are presented, with an application of Silicon on insulator on development, that is to say a 1024 bits MNOS memory, peripheral circuits being developed according to the depletion-enrichment technology.

  13. Electronic properties of interfaces produced by silicon wafer hydrophilic bonding

    Energy Technology Data Exchange (ETDEWEB)

    Trushin, Maxim

    2011-07-15

    The thesis presents the results of the investigations of electronic properties and defect states of dislocation networks (DNs) in silicon produced by wafers direct bonding technique. A new insight into the understanding of their very attractive properties was succeeded due to the usage of a new, recently developed silicon wafer direct bonding technique, allowing to create regular dislocation networks with predefined dislocation types and densities. Samples for the investigations were prepared by hydrophilic bonding of p-type Si (100) wafers with same small misorientation tilt angle ({proportional_to}0.5 ), but with four different twist misorientation angles Atw (being of < , 3 , 6 and 30 , respectively), thus giving rise to the different DN microstructure on every particular sample. The main experimental approach of this work was the measurements of current and capacitance of Schottky diodes prepared on the samples which contained the dislocation network at a depth that allowed one to realize all capabilities of different methods of space charge region spectroscopy (such as CV/IV, DLTS, ITS, etc.). The key tasks for the investigations were specified as the exploration of the DN-related gap states, their variations with gradually increasing twist angle Atw, investigation of the electrical field impact on the carrier emission from the dislocation-related states, as well as the establishing of the correlation between the electrical (DLTS), optical (photoluminescence PL) and structural (TEM) properties of DNs. The most important conclusions drawn from the experimental investigations and theoretical calculations can be formulated as follows: - DLTS measurements have revealed a great difference in the electronic structure of small-angle (SA) and large-angle (LA) bonded interfaces: dominating shallow level and a set of 6-7 deep levels were found in SA-samples with Atw of 1 and 3 , whereas the prevalent deep levels - in LA-samples with Atw of 6 and 30 . The critical twist

  14. Vertical integration of high-Q silicon nitride microresonators into silicon-on-insulator platform.

    Science.gov (United States)

    Li, Qing; Eftekhar, Ali A; Sodagar, Majid; Xia, Zhixuan; Atabaki, Amir H; Adibi, Ali

    2013-07-29

    We demonstrate a vertical integration of high-Q silicon nitride microresonators into the silicon-on-insulator platform for applications at the telecommunication wavelengths. Low-loss silicon nitride films with a thickness of 400 nm are successfully grown, enabling compact silicon nitride microresonators with ultra-high intrinsic Qs (~ 6 × 10(6) for 60 μm radius and ~ 2 × 10(7) for 240 μm radius). The coupling between the silicon nitride microresonator and the underneath silicon waveguide is based on evanescent coupling with silicon dioxide as buffer. Selective coupling to a desired radial mode of the silicon nitride microresonator is also achievable using a pulley coupling scheme. In this work, a 60-μm-radius silicon nitride microresonator has been successfully integrated into the silicon-on-insulator platform, showing a single-mode operation with an intrinsic Q of 2 × 10(6).

  15. Compact wavelength-insensitive fabrication-tolerant silicon-on-insulator beam splitter.

    Science.gov (United States)

    Rasigade, Gilles; Le Roux, Xavier; Marris-Morini, Delphine; Cassan, Eric; Vivien, Laurent

    2010-11-01

    A star coupler-based beam splitter for rib waveguides is reported. A design method is presented and applied in the case of silicon-on-insulator rib waveguides. Experimental results are in good agreement with simulations. Excess loss lower than 1 dB is experimentally obtained for star coupler lengths from 0.5 to 1 μm. Output balance is better than 1 dB, which is the measurement accuracy, and broadband transmission is obtained over 90 nm.

  16. Reliable four-point flexion test and model for die-to-wafer direct bonding

    Energy Technology Data Exchange (ETDEWEB)

    Tabata, T., E-mail: toshiyuki.tabata@cea.fr; Sanchez, L.; Fournel, F.; Moriceau, H. [Univ. Grenoble Alpes, F-38000 Grenoble, France and CEA, LETI, MINATEC Campus, F-38054 Grenoble (France)

    2015-07-07

    For many years, wafer-to-wafer (W2W) direct bonding has been very developed particularly in terms of bonding energy measurement and bonding mechanism comprehension. Nowadays, die-to-wafer (D2W) direct bonding has gained significant attention, for instance, in photonics and microelectro-mechanics, which supposes controlled and reliable fabrication processes. So, whatever the stuck materials may be, it is not obvious whether bonded D2W structures have the same bonding strength as bonded W2W ones, because of possible edge effects of dies. For that reason, it has been strongly required to develop a bonding energy measurement technique which is suitable for D2W structures. In this paper, both D2W- and W2W-type standard SiO{sub 2}-to-SiO{sub 2} direct bonding samples are fabricated from the same full-wafer bonding. Modifications of the four-point flexion test (4PT) technique and applications for measuring D2W direct bonding energies are reported. Thus, the comparison between the modified 4PT and the double-cantilever beam techniques is drawn, also considering possible impacts of the conditions of measures such as the water stress corrosion at the debonding interface and the friction error at the loading contact points. Finally, reliability of a modified technique and a new model established for measuring D2W direct bonding energies is demonstrated.

  17. Methods for characterization of wafer-level encapsulation applied on silicon to LTCC anodic bonding

    International Nuclear Information System (INIS)

    Khan, M F; Ghavanini, F A; Enoksson, P; Haasl, S; Löfgren, L; Persson, K; Rusu, C; Schjølberg-Henriksen, K

    2010-01-01

    This paper presents initial results on generic characterization methods for wafer-level encapsulation. The methods, developed specifically to evaluate anodic bonding of low-temperature cofired ceramics (LTCC) to Si, are generally applicable to wafer-level encapsulation. Different microelectromechanical system (MEMS) structures positioned over the whole wafer provide local information about the bond quality. The structures include (i) resonating cantilevers as pressure sensors for bond hermeticity, (ii) resonating bridges as stress sensors for measuring the stress induced by the bonding and (iii) frames/mesas for pull tests. These MEMS structures have been designed, fabricated and characterized indicating that local information can easily be obtained. Buried electrodes to enable localized bonding have been implemented and their effectiveness is indicated from first results of the novel Si to LTCC anodic bonding.

  18. Broadband Silicon-On-Insulator directional couplers using a combination of straight and curved waveguide sections.

    Science.gov (United States)

    Chen, George F R; Ong, Jun Rong; Ang, Thomas Y L; Lim, Soon Thor; Png, Ching Eng; Tan, Dawn T H

    2017-08-03

    Broadband Silicon-On-Insulator (SOI) directional couplers are designed based on a combination of curved and straight coupled waveguide sections. A design methodology based on the transfer matrix method (TMM) is used to determine the required coupler section lengths, radii, and waveguide cross-sections. A 50/50 power splitter with a measured bandwidth of 88 nm is designed and fabricated, with a device footprint of 20 μm × 3 μm. In addition, a balanced Mach-Zehnder interferometer is fabricated showing an extinction ratio of >16 dB over 100 nm of bandwidth.

  19. Crosstalk analysis of silicon-on-insulator nanowire-arrayed waveguide grating

    International Nuclear Information System (INIS)

    Li Kai-Li; An Jun-Ming; Zhang Jia-Shun; Wang Yue; Wang Liang-Liang; Li Jian-Guang; Wu Yuan-Da; Yin Xiao-Jie; Hu Xiong-Wei

    2016-01-01

    The factors influencing the crosstalk of silicon-on-insulator (SOI) nanowire arrayed waveguide grating (AWG) are analyzed using the transfer function method. The analysis shows that wider and thicker arrayed waveguides, outsider fracture of arrayed waveguide, and larger channel space, could mitigate the deterioration of crosstalk. The SOI nanowire AWGs with different arrayed waveguide widths are fabricated by using deep ultraviolet lithography (DUV) and inductively coupled plasma etching (ICP) technology. The measurement results show that the crosstalk performance is improved by about 7 dB through adopting 800 nm arrayed waveguide width. (paper)

  20. Implantation of oxygen ions for the realization of SOS (silicon on insulator) structures: SIMOX

    International Nuclear Information System (INIS)

    Margail, J.

    1987-03-01

    Highdose oxygen implantation is becoming a serious candidate for SOI (silicon on insulator) structure realization. The fabrication condition study of these substrates allowed to show up the implantation and annealing parameter importance for microstructure, and particularly for crystal quality of silicon films. It has been shown that the use of high temperature annealings leads to high quality substrates: monocrystal silicon film without any precipitate, at the card scale; Si/Si O 2 interface formation. After annealing at 1340 O C, Hall mobilities have been measured in silicon film, and its residual doping is very low. First characteristics and performance of submicron CMOS circuits prooves the electric quality of these substrates [fr

  1. A High Performance Silicon-on-Insulator LDMOSTT Using Linearly Increasing Thickness Techniques

    International Nuclear Information System (INIS)

    Yu-Feng, Guo; Zhi-Gong, Wang; Gene, Sheu; Jian-Bing, Cheng

    2010-01-01

    We present a new technique to achieve uniform lateral electric field and maximum breakdown voltage in lateral double-diffused metal-oxide-semiconductor transistors fabricated on silicon-on-insulator substrates. A linearly increasing drift-region thickness from the source to the drain is employed to improve the electric field distribution in the devices. Compared to the lateral linear doping technique and the reduced surface field technique, two-dimensional numerical simulations show that the new device exhibits reduced specific on-resistance, maximum off- and on-state breakdown voltages, superior quasi-saturation characteristics and improved safe operating area. (condensed matter: electronic structure, electrical, magnetic, and optical properties)

  2. Analysis of silicon on insulator (SOI) optical microring add-drop filter based on waveguide intersections

    Science.gov (United States)

    Kaźmierczak, Andrzej; Bogaerts, Wim; Van Thourhout, Dries; Drouard, Emmanuel; Rojo-Romeo, Pedro; Giannone, Domenico; Gaffiot, Frederic

    2008-04-01

    We present a compact passive optical add-drop filter which incorporates two microring resonators and a waveguide intersection in silicon-on-insulator (SOI) technology. Such a filter is a key element for designing simple layouts of highly integrated complex optical networks-on-chip. The filter occupies an area smaller than 10μm×10μm and exhibits relatively high quality factors (up to 4000) and efficient signal dropping capabilities. In the present work, the influence of filter parameters such as the microring-resonators radii and the coupling section shape are analyzed theoretically and experimentally

  3. Guided acoustic and optical waves in silicon-on-insulator for Brillouin scattering and optomechanics

    Directory of Open Access Journals (Sweden)

    Christopher J. Sarabalis

    2016-10-01

    Full Text Available We numerically study silicon waveguides on silica showing that it is possible to simultaneously guide optical and acoustic waves in the technologically important silicon on insulator (SOI material system. Thin waveguides, or fins, exhibit geometrically softened mechanical modes at gigahertz frequencies with phase velocities below the Rayleigh velocity in glass, eliminating acoustic radiation losses. We propose slot waveguides on glass with telecom optical frequencies and strong radiation pressure forces resulting in Brillouin gains on the order of 500 and 50 000 W−1m−1 for backward and forward Brillouin scattering, respectively.

  4. Observation of an optical event horizon in a silicon-on-insulator photonic wire waveguide.

    Science.gov (United States)

    Ciret, Charles; Leo, François; Kuyken, Bart; Roelkens, Gunther; Gorza, Simon-Pierre

    2016-01-11

    We report on the first experimental observation of an optical analogue of an event horizon in integrated nanophotonic waveguides, through the reflection of a continuous wave on an intense pulse. The experiment is performed in a dispersion-engineered silicon-on-insulator waveguide. In this medium, solitons do not suffer from Raman induced self-frequency shift as in silica fibers, a feature that is interesting for potential applications of optical event horizons. As shown by simulations, this also allows the observation of multiple reflections at the same time on fundamental solitons ejected by soliton fission.

  5. Total dose hardening of buried insulator in implanted silicon-on-insulator structures

    International Nuclear Information System (INIS)

    Mao, B.Y.; Chen, C.E.; Pollack, G.; Hughes, H.L.; Davis, G.E.

    1987-01-01

    Total dose characteristics of the buried insulator in implanted silicon-on-insulator (SOI) substrates have been studied using MOS transistors. The threshold voltage shift of the parasitic back channel transistor, which is controlled by charge trapping in the buried insulator, is reduced by lowering the oxygen dose as well as by an additional nitrogen implant, without degrading the front channel transistor characteristics. The improvements in the radiation characteristics of the buried insulator are attributed to the decrease in the buried oxide thickness or to the presence of the interfacial oxynitride layer formed by the oxygen and nitrogen implants

  6. High temperature study of flexible silicon-on-insulator fin field-effect transistors

    KAUST Repository

    Diab, Amer El Hajj

    2014-09-29

    We report high temperature electrical transport characteristics of a flexible version of the semiconductor industry\\'s most advanced architecture: fin field-effect transistor on silicon-on-insulator with sub-20 nm fins and high-κ/metal gate stacks. Characterization from room to high temperature (150 °C) was completed to determine temperature dependence of drain current (Ids), gate leakage current (Igs), transconductance (gm), and extracted low-field mobility (μ0). Mobility degradation with temperature is mainly caused by phonon scattering. The other device characteristics show insignificant difference at high temperature which proves the suitability of inorganic flexible electronics with advanced device architecture.

  7. High-Q silicon-on-insulator slot photonic crystal cavity infiltrated by a liquid

    International Nuclear Information System (INIS)

    Caër, Charles; Le Roux, Xavier; Cassan, Eric

    2013-01-01

    We report the experimental realization of a high-Q slot photonic crystal cavity in Silicon-On-Insulator (SOI) configuration infiltrated by a liquid. Loaded Q-factor of 23 000 is measured at telecom wavelength. The intrinsic quality factor inferred from the transmission spectrum is higher than 200 000, which represents a record value for slot photonic crystal cavities on SOI, whereas the maximum of intensity of the cavity is roughly equal to 20% of the light transmitted in the waveguide. This result makes filled slot photonic crystal cavities very promising for silicon-based light emission and ultrafast nonlinear optics

  8. Micro knife-edge optical measurement device in a silicon-on-insulator substrate.

    Science.gov (United States)

    Chiu, Yi; Pan, Jiun-Hung

    2007-05-14

    The knife-edge method is a commonly used technique to characterize the optical profiles of laser beams or focused spots. In this paper, we present a micro knife-edge scanner fabricated in a silicon-on-insulator substrate using the micro-electromechanical-system technology. A photo detector can be fabricated in the device to allow further integration with on-chip signal conditioning circuitry. A novel backside deep reactive ion etching process is proposed to solve the residual stress effect due to the buried oxide layer. Focused optical spot profile measurement is demonstrated.

  9. Interfacial phonon scattering and transmission loss in >1 μm thick silicon-on-insulator thin films

    Science.gov (United States)

    Jiang, Puqing; Lindsay, Lucas; Huang, Xi; Koh, Yee Kan

    2018-05-01

    Scattering of phonons at boundaries of a crystal (grains, surfaces, or solid/solid interfaces) is characterized by the phonon wavelength, the angle of incidence, and the interface roughness, as historically evaluated using a specularity parameter p formulated by Ziman [Electrons and Phonons (Clarendon Press, Oxford, 1960)]. This parameter was initially defined to determine the probability of a phonon specularly reflecting or diffusely scattering from the rough surface of a material. The validity of Ziman's theory as extended to solid/solid interfaces has not been previously validated. To better understand the interfacial scattering of phonons and to test the validity of Ziman's theory, we precisely measured the in-plane thermal conductivity of a series of Si films in silicon-on-insulator (SOI) wafers by time-domain thermoreflectance (TDTR) for a Si film thickness range of 1-10 μm and a temperature range of 100-300 K. The Si /SiO2 interface roughness was determined to be 0.11 ±0.04 nm using transmission electron microscopy (TEM). Furthermore, we compared our in-plane thermal conductivity measurements to theoretical calculations that combine first-principles phonon transport with Ziman's theory. Calculations using Ziman's specularity parameter significantly overestimate values from the TDTR measurements. We attribute this discrepancy to phonon transmission through the solid/solid interface into the substrate, which is not accounted for by Ziman's theory for surfaces. The phonons that are specularly transmitted into an amorphous layer will be sufficiently randomized by the time they come back to the crystalline Si layer, the effect of which is practically equivalent to a diffuse reflection at the interface. We derive a simple expression for the specularity parameter at solid/amorphous interfaces and achieve good agreement between calculations and measurement values.

  10. A Novel Non-Destructive Silicon-on-Insulator Nonvolatile Memory - LDRD 99-0750 Final Report

    Energy Technology Data Exchange (ETDEWEB)

    DRAPER,BRUCE L.; FLEETWOOD,D. M.; MEISENHEIMER,TIMOTHY L.; MURRAY,JAMES R.; SCHWANK,JAMES R.; SHANEYFELT,MARTY R.; SMITH,PAUL M.; VANHEUSDEN,KAREL J.; WARREN,WILLIAM L.

    1999-11-01

    Defects in silicon-on-insulator (SOI) buried oxides are normally considered deleterious to device operation. Similarly, exposing devices to hydrogen at elevated temperatures often can lead to radiation-induced charge buildup. However, in this work, we take advantage of as-processed defects in SOI buried oxides and moderate temperature hydrogen anneals to generate mobile protons in the buried oxide to form the basis of a ''protonic'' nonvolatile memory. Capacitors and fully-processed transistors were fabricated. SOI buried oxides are exposed to hydrogen at moderate temperatures using a variety of anneal conditions to optimize the density of mobile protons. A fast ramp cool down anneal was found to yield the maximum number of mobile protons. Unfortunately, we were unable to obtain uniform mobile proton concentrations across a wafer. Capacitors were irradiated to investigate the potential use of protonic memories for space and weapon applications. Irradiating under a negative top-gate bias or with no applied bias was observed to cause little degradation in the number of mobile protons. However, irradiating to a total dose of 100 krad(SiO{sub 2}) under a positive top-gate bias caused approximately a 100% reduction in the number of mobile protons. Cycling capacitors up to 10{sup 4} cycles had little effect on the switching characteristics. No change in the retention characteristics were observed for times up to 3 x 10{sup 4} s for capacitors stored unbiased at 200 C. These results show the proof-of-concept for a protonic nonvolatile memory. Two memory architectures are proposed for a protonic non-destructive, nonvolatile memory.

  11. Impact of SiO2 on Al–Al thermocompression wafer bonding

    International Nuclear Information System (INIS)

    Malik, Nishant; Finstad, Terje G; Schjølberg-Henriksen, Kari; Poppe, Erik U; Taklo, Maaike M V

    2015-01-01

    Al–Al thermocompression bonding suitable for wafer level sealing of MEMS devices has been investigated. This paper presents a comparison of thermocompression bonding of Al films deposited on Si with and without a thermal oxide (SiO 2 film). Laminates of diameter 150 mm containing device sealing frames of width 200 µm were realized. The wafers were bonded by applying a bond force of 36 or 60 kN at bonding temperatures ranging from 300–550 °C for bonding times of 15, 30 or 60 min. The effects of these process variations on the quality of the bonded laminates have been studied. The bond quality was estimated by measurements of dicing yield, tensile strength, amount of cohesive fracture in Si and interfacial characterization. The mean bond strength of the tested structures ranged from 18–61 MPa. The laminates with an SiO 2 film had higher dicing yield and bond strength than the laminates without SiO 2 for a 400 °C bonding temperature. The bond strength increased with increasing bonding temperature and bond force. The laminates bonded for 30 and 60 min at 400 °C and 60 kN had similar bond strength and amount of cohesive fracture in the bulk silicon, while the laminates bonded for 15 min had significantly lower bond strength and amount of cohesive fracture in the bulk silicon. (paper)

  12. Peculiarities of electronic structure of silicon-on-insulator structures and their interaction with synchrotron radiation

    Directory of Open Access Journals (Sweden)

    Vladimir A. Terekhov

    2015-09-01

    Full Text Available SOI (silicon-on-insulator structures with strained and unstrained silicon layers were studied by ultrasoft X-ray emission spectroscopy and X-ray absorption near edge structure spectroscopy with the use of synchrotron radiation techniques. Analysis of X-ray data has shown a noticeable transformation of the electron energy spectrum and local partial density of states distribution in valence and conduction bands in the strained silicon layer of the SOI structure. USXES Si L2,3 spectra analysis revealed a decrease of the distance between the L2v′ и L1v points in the valence band of the strained silicon layer as well as a shift of the first two maxima of the XANES first derivation spectra to the higher energies with respect to conduction band bottom Ec. At the same time the X-ray standing waves of synchrotron radiation (λ~12–20 nm are formed in the silicon-on-insulator structure with and without strains of the silicon layer. Moreover changing the synchrotron radiation grazing angle θ by 2° leads to a change of the electromagnetic field phase to the opposite.

  13. An experimental study of solid source diffusion by spin on dopants and its application for minimal silicon-on-insulator CMOS fabrication

    Science.gov (United States)

    Liu, Yongxun; Koga, Kazuhiro; Khumpuang, Sommawan; Nagao, Masayoshi; Matsukawa, Takashi; Hara, Shiro

    2017-06-01

    Solid source diffusions of phosphorus (P) and boron (B) into the half-inch (12.5 mm) minimal silicon (Si) wafers by spin on dopants (SOD) have been systematically investigated and the physical-vapor-deposited (PVD) titanium nitride (TiN) metal gate minimal silicon-on-insulator (SOI) complementary metal-oxide-semiconductor (CMOS) field-effect transistors (FETs) have successfully been fabricated using the developed SOD thermal diffusion technique. It was experimentally confirmed that a low temperature oxidation (LTO) process which depresses a boron silicide layer formation is effective way to remove boron-glass in a diluted hydrofluoric acid (DHF) solution. It was also found that top Si layer thickness of SOI wafers is reduced in the SOD thermal diffusion process because of its consumption by thermal oxidation owing to the oxygen atoms included in SOD films, which should be carefully considered in the ultrathin SOI device fabrication. Moreover, normal operations of the fabricated minimal PVD-TiN metal gate SOI-CMOS inverters, static random access memory (SRAM) cells and ring oscillators have been demonstrated. These circuit level results indicate that no remarkable particles and interface traps were introduced onto the minimal wafers during the device fabrication, and the developed solid source diffusion by SOD is useful for the fabrication of functional logic gate minimal SOI-CMOS integrated circuits.

  14. Bonding of Si wafers by surface activation method for the development of high efficiency high counting rate radiation detectors

    International Nuclear Information System (INIS)

    Kanno, Ikuo; Yamashita, Makoto; Onabe, Hideaki

    2006-01-01

    Si wafers with two different resistivities ranging over two orders of magnitude were bonded by the surface activation method. The resistivities of bonded Si wafers were measured as a function of annealing temperature. Using calculations based on a model, the interface resistivities of bonded Si wafers were estimated as a function of the measured resistivities of bonded Si wafers. With thermal treatment from 500degC to 900degC, all interfaces showed high resistivity, with behavior that was close to that of an insulator. Annealing at 1000degC decreased the interface resistivity and showed close to ideal bonding after thermal treatment at 1100degC. (author)

  15. Cohesive zone modelling of wafer bonding and fracture: effect of patterning and toughness variations

    Science.gov (United States)

    Kubair, D. V.; Spearing, S. M.

    2006-03-01

    Direct wafer bonding has increasingly become popular in the manufacture of microelectromechanical systems and semiconductor microelectronics components. The success of the bonding process is controlled by variables such as wafer flatness and surface preparation. In order to understand the effects of these variables, spontaneous planar crack propagation simulations were performed using the spectral scheme in conjunction with a cohesive zone model. The fracture-toughness on the bond interface is varied to simulate the effect of surface roughness (nanotopography) and patterning. Our analysis indicated that the energetics of crack propagation is sensitive to the local surface property variations. The patterned wafers are tougher (well bonded) than the unpatterned ones of the same average fracture-toughness.

  16. Eutectic and solid-state wafer bonding of silicon with gold

    International Nuclear Information System (INIS)

    Abouie, Maryam; Liu, Qi; Ivey, Douglas G.

    2012-01-01

    Highlights: ► Eutectic and solid-state Au-Si bonding are compared for both a-Si and c-Si samples. ► Exchange of a-Si and Au layer was observed in both types of bonded samples. ► Use of c-Si for bonding resulted in formation of craters at the Au/c-Si interface. ► Solid-state Au-Si bonding produces better bonds in terms of microstructure. - Abstract: The simple Au-Si eutectic, which melts at 363 °C, can be used to bond Si wafers. However, faceted craters can form at the Au/Si interface as a result of anisotropic and non-uniform reaction between Au and crystalline silicon (c-Si). These craters may adversely affect active devices on the wafers. Two possible solutions to this problem were investigated in this study. One solution was to use an amorphous silicon layer (a-Si) that was deposited on the c-Si substrate to bond with the Au. The other solution was to use solid-state bonding instead of eutectic bonding, and the wafers were bonded at a temperature (350 °C) below the Au-Si eutectic temperature. The results showed that the a-Si layer prevented the formation of craters and solid-state bonding not only required a lower bonding temperature than eutectic bonding, but also prevented spill out of the solder resulting in strong bonds with high shear strength in comparison with eutectic bonding. Using amorphous silicon, the maximum shear strength for the solid-state Au-Si bond reached 15.2 MPa, whereas for the eutectic Au-Si bond it was 13.2 MPa.

  17. Fabrication of Si-based planar type patch clamp biosensor using silicon on insulator substrate

    International Nuclear Information System (INIS)

    Zhang, Z.L.; Asano, T.; Uno, H.; Tero, R.; Suzui, M.; Nakao, S.; Kaito, T.; Shibasaki, K.; Tominaga, M.; Utsumi, Y.; Gao, Y.L.; Urisu, T.

    2008-01-01

    The aim of this paper is to fabricate the planar type patch clamp ion-channel biosensor, which is suitable for the high throughput screening, using silicon-on-insulator (SOI) substrate. The micropore with 1.2 μm diameter is formed through the top Si layer and the SiO 2 box layer of the SOI substrate by focused ion beam (FIB). Then the substrate is assembled into the microfluidic circuit. The human embryonic kidney 293 (HEK-293) cell transfected with transient receptor potential vanilloid type 1 (TRPV1) is positioned on the micropore and the whole-cell configuration is formed by the suction. Capsaicin is added to the extracellular solution as a ligand molecule, and the channel current showing the desensitization unique to TRPV1 is measured successfully

  18. Implant damage and redistribution of indium in indium-implanted thin silicon-on-insulator

    International Nuclear Information System (INIS)

    Chen Peng; An Zhenghua; Zhu Ming; Fu, Ricky K.Y.; Chu, Paul K.; Montgomery, Neil; Biswas, Sukanta

    2004-01-01

    The indium implant damage and diffusion behavior in thin silicon-on-insulator (SOI) with a 200 nm top silicon layer were studied for different implantation energies and doses. Rutherford backscattering spectrometry in the channeling mode (RBS/C) was used to characterize the implant damage before and after annealing. Secondary ion mass spectrometry (SIMS) was used to study the indium transient enhanced diffusion (TED) behavior in the top Si layer of the SOI structure. An anomalous redistribution of indium after relatively high energy (200 keV) and dose (1 x 10 14 cm -2 ) implantation was observed in both bulk Si and SOI substrates. However, there exist differences in these two substrates that are attributable to the more predominant out-diffusion of indium as well as the influence of the buried oxide layer in the SOI structure

  19. Hot-Electron Bolometer Mixers on Silicon-on-Insulator Substrates for Terahertz Frequencies

    Science.gov (United States)

    Skalare, Anders; Stern, Jeffrey; Bumble, Bruce; Maiwald, Frank

    2005-01-01

    A terahertz Hot-Electron Bolometer (HEB) mixer design using device substrates based on Silicon-On-Insulator (SOI) technology is described. This substrate technology allows very thin chips (6 pm) with almost arbitrary shape to be manufactured, so that they can be tightly fitted into a waveguide structure and operated at very high frequencies with only low risk for power leakages and resonance modes. The NbTiN-based bolometers are contacted by gold beam-leads, while other beamleads are used to hold the chip in place in the waveguide test fixture. The initial tests yielded an equivalent receiver noise temperature of 3460 K double-sideband at a local oscillator frequency of 1.462 THz and an intermediate frequency of 1.4 GHz.

  20. Silicon-on-insulator field effect transistor with improved body ties for rad-hard applications

    Science.gov (United States)

    Schwank, James R.; Shaneyfelt, Marty R.; Draper, Bruce L.; Dodd, Paul E.

    2001-01-01

    A silicon-on-insulator (SOI) field-effect transistor (FET) and a method for making the same are disclosed. The SOI FET is characterized by a source which extends only partially (e.g. about half-way) through the active layer wherein the transistor is formed. Additionally, a minimal-area body tie contact is provided with a short-circuit electrical connection to the source for reducing floating body effects. The body tie contact improves the electrical characteristics of the transistor and also provides an improved single-event-upset (SEU) radiation hardness of the device for terrestrial and space applications. The SOI FET also provides an improvement in total-dose radiation hardness as compared to conventional SOI transistors fabricated without a specially prepared hardened buried oxide layer. Complementary n-channel and p-channel SOI FETs can be fabricated according to the present invention to form integrated circuits (ICs) for commercial and military applications.

  1. Al transmon qubits on silicon-on-insulator for quantum device integration

    Science.gov (United States)

    Keller, Andrew J.; Dieterle, Paul B.; Fang, Michael; Berger, Brett; Fink, Johannes M.; Painter, Oskar

    2017-07-01

    We present the fabrication and characterization of an aluminum transmon qubit on a silicon-on-insulator substrate. Key to the qubit fabrication is the use of an anhydrous hydrofluoric vapor process which selectively removes the lossy silicon oxide buried underneath the silicon device layer. For a 5.6 GHz qubit measured dispersively by a 7.1 GHz resonator, we find T1 = 3.5 μs and T2* = 2.2 μs. This process in principle permits the co-fabrication of silicon photonic and mechanical elements, providing a route towards chip-scale integration of electro-opto-mechanical transducers for quantum networking of superconducting microwave quantum circuits. The additional processing steps are compatible with established fabrication techniques for aluminum transmon qubits on silicon.

  2. Evanescently Coupled Rectangular Microresonators in Silicon-on-Insulator with High Q-Values: Experimental Characterization

    Directory of Open Access Journals (Sweden)

    Manuel Mendez-Astudillo

    2017-04-01

    Full Text Available We report on evanescently coupled rectangular microresonators with dimensions up to 20 × 10 μm2 in silicon-on-insulator in an add-drop filter configuration. The influence of the geometrical parameters of the device was experimentally characterized and a high Q value of 13,000 was demonstrated as well as the multimode optical resonance characteristics in the drop port. We also show a 95% energy transfer between ports when the device is operated in TM-polarization and determine the full symmetry of the device by using an eight-port configuration, allowing the drop waveguide to be placed on any of its sides, providing a way to filter and route optical signals. We used the FDTD method to analyze the device and e-beam lithography and dry etching techniques for fabrication.

  3. Planar Fully-Depleted-Silicon-On-Insulator technologies: Toward the 28 nm node and beyond

    Science.gov (United States)

    Doris, B.; DeSalvo, B.; Cheng, K.; Morin, P.; Vinet, M.

    2016-03-01

    This paper presents a comprehensive overview of the research done in the last decade on planar Fully-Depleted-Silicon-On-Insulator (FDSOI) technologies in the frame of the joint development program between IBM, ST Microelectronics and CEA-LETI. In particular, we review the technological developments ranging from substrate engineering to process modules that enable functionality and improve FDSOI performance over several generations. Various multi Vt integration schemes to maximize the benefits of the thin BOX FDSOI platform are discussed. Manufacturability as well as scalability concerns are highlighted and addressed. In addition, this work provides understanding of the performance/power trade-offs for FDSOI circuits and device variability. Finally, clear directions for future application-specific products are given, demonstrating that FDSOI is an attractive CMOS option for next generation high performance and low-power applications.

  4. Advanced photonic filters based on cascaded Sagnac loop reflector resonators in silicon-on-insulator nanowires

    Science.gov (United States)

    Wu, Jiayang; Moein, Tania; Xu, Xingyuan; Moss, David J.

    2018-04-01

    We demonstrate advanced integrated photonic filters in silicon-on-insulator (SOI) nanowires implemented by cascaded Sagnac loop reflector (CSLR) resonators. We investigate mode splitting in these standing-wave (SW) resonators and demonstrate its use for engineering the spectral profile of on-chip photonic filters. By changing the reflectivity of the Sagnac loop reflectors (SLRs) and the phase shifts along the connecting waveguides, we tailor mode splitting in the CSLR resonators to achieve a wide range of filter shapes for diverse applications including enhanced light trapping, flat-top filtering, Q factor enhancement, and signal reshaping. We present the theoretical designs and compare the CSLR resonators with three, four, and eight SLRs fabricated in SOI. We achieve versatile filter shapes in the measured transmission spectra via diverse mode splitting that agree well with theory. This work confirms the effectiveness of using CSLR resonators as integrated multi-functional SW filters for flexible spectral engineering.

  5. Fabrication of Si-based planar type patch clamp biosensor using silicon on insulator substrate

    Energy Technology Data Exchange (ETDEWEB)

    Zhang, Z.L.; Asano, T. [Graduate University for Advanced Studies, Myodaiji, Okazaki, 444-8585 (Japan); Uno, H. [Institute for Molecular Science, Myodaiji, Okazaki, 444-8585 (Japan); Tero, R. [Graduate University for Advanced Studies, Myodaiji, Okazaki, 444-8585 (Japan); Institute for Molecular Science, Myodaiji, Okazaki, 444-8585 (Japan); Suzui, M.; Nakao, S. [Institute for Molecular Science, Myodaiji, Okazaki, 444-8585 (Japan); Kaito, T. [SII NanoTechnology Inc., 36-1, Takenoshita, Oyama-cho, Sunto-gun, Shizuoka, 410-1393 (Japan); Shibasaki, K.; Tominaga, M. [Okazaki Institute for Integrative Bioscience, 5-1, Higashiyama, Myodaiji, Okazaki, 444-8787 (Japan); Utsumi, Y. [Laboratory of Advanced Science and Technology for Industry, University of Hyogo, 3-1-2, Koto, Kamigori, Ako-gun, Hyogo, 678-1205 (Japan); Gao, Y.L. [Department of Physics and Astronomy, Rochester University, Rochester, New York 14627 (United States); Urisu, T. [Graduate University for Advanced Studies, Myodaiji, Okazaki, 444-8585 (Japan); Institute for Molecular Science, Myodaiji, Okazaki, 444-8585 (Japan)], E-mail: urisu@ims.ac.jp

    2008-03-03

    The aim of this paper is to fabricate the planar type patch clamp ion-channel biosensor, which is suitable for the high throughput screening, using silicon-on-insulator (SOI) substrate. The micropore with 1.2 {mu}m diameter is formed through the top Si layer and the SiO{sub 2} box layer of the SOI substrate by focused ion beam (FIB). Then the substrate is assembled into the microfluidic circuit. The human embryonic kidney 293 (HEK-293) cell transfected with transient receptor potential vanilloid type 1 (TRPV1) is positioned on the micropore and the whole-cell configuration is formed by the suction. Capsaicin is added to the extracellular solution as a ligand molecule, and the channel current showing the desensitization unique to TRPV1 is measured successfully.

  6. Advanced photonic filters based on cascaded Sagnac loop reflector resonators in silicon-on-insulator nanowires

    Directory of Open Access Journals (Sweden)

    Jiayang Wu

    2018-04-01

    Full Text Available We demonstrate advanced integrated photonic filters in silicon-on-insulator (SOI nanowires implemented by cascaded Sagnac loop reflector (CSLR resonators. We investigate mode splitting in these standing-wave (SW resonators and demonstrate its use for engineering the spectral profile of on-chip photonic filters. By changing the reflectivity of the Sagnac loop reflectors (SLRs and the phase shifts along the connecting waveguides, we tailor mode splitting in the CSLR resonators to achieve a wide range of filter shapes for diverse applications including enhanced light trapping, flat-top filtering, Q factor enhancement, and signal reshaping. We present the theoretical designs and compare the CSLR resonators with three, four, and eight SLRs fabricated in SOI. We achieve versatile filter shapes in the measured transmission spectra via diverse mode splitting that agree well with theory. This work confirms the effectiveness of using CSLR resonators as integrated multi-functional SW filters for flexible spectral engineering.

  7. The Microwave Noise Behaviour Of Dual Material Gate Silicon On Insulator

    Science.gov (United States)

    Jafar, N.; Soin, N.

    2009-06-01

    This work presents the noise behaviour due to the applied Dual Material Gate (DMG) on the 75 nm n-channel Silicon On Insulator (SOI) device operating in the fully depletion mode, particularly for microwave circuit design. Influences of DMG properties namely the gate length ratio (L1:L2) and gate material workfunction difference (ΔΦM) as well as structural and operational parameters which are silicon thickness (TSi) and threshold voltage (VTH) setting variation on the noise performance were carried out on simulation basis using ATLAS 2D. Results show better noise performance in DMG as compare to the standard gate structure of FD-SOI devices. Higher VTH for DMG design is recommended for minimized noise figure in line with the advantage of inverse VTH roll-off characteristics for short channel effects suppression.

  8. Thermal processing of strained silicon-on-insulator for atomically precise silicon device fabrication

    International Nuclear Information System (INIS)

    Lee, W.C.T.; Bishop, N.; Thompson, D.L.; Xue, K.; Scappucci, G.; Cederberg, J.G.; Gray, J.K.; Han, S.M.; Celler, G.K.; Carroll, M.S.; Simmons, M.Y.

    2013-01-01

    Highlights: ► Strained silicon-on-insulator (sSOI) samples were flash-annealed at high temperature under ultra-high vacuum conditions. ► The extend of surface strain relaxation depends on the annealing temperature with no strain relaxation observed below 1020 °C. ► A 2 × 1 reconstructed surface with low defect density can be achieved. ► The annealed sSOI surface shows enhanced step undulations due to the unique energetics caused by surface strain. - Abstract: We investigate the ability to reconstruct strained silicon-on-insulator (sSOI) substrates in ultra-high vacuum for use in atomic scale device fabrication. Characterisation of the starting sSOI substrate using μRaman shows an average tensile strain of 0.8%, with clear strain modulation in a crosshatch pattern across the surface. The surfaces were heated in ultra-high vacuum from temperatures of 900 °C to 1100 °C and subsequently imaged using scanning tunnelling microscopy (STM). The initial strain modulation on the surface is observed to promote silicon migration and the formation of crosshatched surface features whose height and pitch increases with increasing annealing temperature. STM images reveal alternating narrow straight S A steps and triangular wavy S B steps attributed to the spontaneous faceting of S B and preferential adatom attachment on S B under biaxial tensile strain. Raman spectroscopy shows that despite these high temperature anneals no strain relaxation of the substrate is observed up to temperatures of 1020 °C. Above 1100 °C, strain relaxation is evident but is confined to the surface.

  9. Low temperature sacrificial wafer bonding for planarization after very deep etching

    NARCIS (Netherlands)

    Spiering, V.L.; Spiering, V.L.; Berenschot, Johan W.; Elwenspoek, Michael Curt; Fluitman, J.H.J.

    1994-01-01

    A new technique, at temperatures of 150°C or 450°C, that provides planarization after a very deep etching step in silicon is presented. Resist spinning and layer patterning as well as realization of bridges or cantilevers across deep holes becomes possible. The sacrificial wafer bonding technique

  10. I-line stepper based overlay evaluation method for wafer bonding applications

    Science.gov (United States)

    Kulse, P.; Sasai, K.; Schulz, K.; Wietstruck, M.

    2018-03-01

    In the last decades the semiconductor technology has been driven by Moore's law leading to high performance CMOS technologies with feature sizes of less than 10 nm [1]. It has been pointed out that not only scaling but also the integration of novel components and technology modules into CMOS/BiCMOS technologies is becoming more attractive to realize smart and miniaturized systems [2]. Driven by new applications in the area of communication, health and automation, new components and technology modules such as BiCMOS embedded RF-MEMS, high-Q passives, Sibased microfluidics and InP-SiGe BiCMOS heterointegration have been demonstrated [3-6]. In contrast to standard VLSI processes fabricated on front side of the silicon wafer, these new technology modules additionally require to process the backside of the wafer; thus require an accurate alignment between the front and backside of the wafer. In previous work an advanced back to front side alignment technique and implementation into IHP's 0.25/0.13 µm high performance SiGe:C BiCMOS backside process module has been presented [7]. The developed technique enables a high resolution and accurate lithography on the backside of BiCMOS wafer for additional backside processing. In addition to the aforementioned back side process technologies, new applications like Through-Silicon Vias (TSV) for interposers and advanced substrate technologies for 3D heterogeneous integration demand not only single wafer fabrication but also processing of wafer stacks provided by temporary and permanent wafer bonding [8-9]. In this work, the non-contact infrared alignment system of the Nikon® i-line Stepper NSR-SF150 for both alignment and the overlay determination of bonded wafer stacks with embedded alignment marks are used to achieve an accurate alignment between the different wafer sides. The embedded field image alignment (FIA) marks of the interface and the device wafer top layer are measured in a single measurement job. By taking the

  11. GeSn-on-insulator substrate formed by direct wafer bonding

    Energy Technology Data Exchange (ETDEWEB)

    Lei, Dian; Wang, Wei; Gong, Xiao, E-mail: elegong@nus.edu.sg, E-mail: yeo@ieee.org; Yeo, Yee-Chia, E-mail: elegong@nus.edu.sg, E-mail: yeo@ieee.org [Department of Electrical and Computer Engineering, National University of Singapore, Singapore 117576 (Singapore); Lee, Kwang Hong; Wang, Bing [Low Energy Electronic Systems (LEES), Singapore MIT Alliance for Research and Technology (SMART), 1 CREATE Way, #10-01 CREATE Tower, Singapore 138602 (Singapore); Bao, Shuyu [Low Energy Electronic Systems (LEES), Singapore MIT Alliance for Research and Technology (SMART), 1 CREATE Way, #10-01 CREATE Tower, Singapore 138602 (Singapore); School of Electrical and Electronic Engineering, Nanyang Technological University, 50 Nanyang Avenue, Singapore 639798 (Singapore); Tan, Chuan Seng [School of Electrical and Electronic Engineering, Nanyang Technological University, 50 Nanyang Avenue, Singapore 639798 (Singapore)

    2016-07-11

    GeSn-on-insulator (GeSnOI) on Silicon (Si) substrate was realized using direct wafer bonding technique. This process involves the growth of Ge{sub 1-x}Sn{sub x} layer on a first Si (001) substrate (donor wafer) followed by the deposition of SiO{sub 2} on Ge{sub 1-x}Sn{sub x}, the bonding of the donor wafer to a second Si (001) substrate (handle wafer), and removal of the Si donor wafer. The GeSnOI material quality is investigated using high-resolution transmission electron microscopy, high-resolution X-ray diffraction (HRXRD), atomic-force microscopy, Raman spectroscopy, and spectroscopic ellipsometry. The Ge{sub 1-x}Sn{sub x} layer on GeSnOI substrate has a surface roughness of 1.90 nm, which is higher than that of the original Ge{sub 1-x}Sn{sub x} epilayer before transfer (surface roughness is 0.528 nm). The compressive strain of the Ge{sub 1-x}Sn{sub x} film in the GeSnOI is as low as 0.10% as confirmed using HRXRD and Raman spectroscopy.

  12. Formation of III–V-on-insulator structures on Si by direct wafer bonding

    International Nuclear Information System (INIS)

    Yokoyama, Masafumi; Iida, Ryo; Ikku, Yuki; Kim, Sanghyeon; Takenaka, Mitsuru; Takagi, Shinichi; Takagi, Hideki; Yasuda, Tetsuji; Yamada, Hisashi; Ichikawa, Osamu; Fukuhara, Noboru; Hata, Masahiko

    2013-01-01

    We have studied the formation of III–V-compound-semiconductors-on-insulator (III–V-OI) structures with thin buried oxide (BOX) layers on Si wafers by using developed direct wafer bonding (DWB). In order to realize III–V-OI MOSFETs with ultrathin body and extremely thin body (ETB) InGaAs-OI channel layers and ultrathin BOX layers, we have developed an electron-cyclotron resonance (ECR) O 2 plasma-assisted DWB process with ECR sputtered SiO 2 BOX layers and a DWB process based on atomic-layer-deposition Al 2 O 3 (ALD-Al 2 O 3 ) BOX layers. It is essential to suppress micro-void generation during wafer bonding process to achieve excellent wafer bonding. We have found that major causes of micro-void generation in DWB processes with ECR-SiO 2 and ALD-Al 2 O 3 BOX layers are desorption of Ar and H 2 O gas, respectively. In order to suppress micro-void generation in the ECR-SiO 2 BOX layers, it is effective to introduce the outgas process before bonding wafers. On the other hand, it is a possible solution for suppressing micro-void generation in the ALD-Al 2 O 3 BOX layers to increase the deposition temperature of the ALD-Al 2 O 3 BOX layers. It is also another possible solution to deposit ALD-Al 2 O 3 BOX layers on thermally oxidized SiO 2 layers, which can absorb the desorption gas from ALD-Al 2 O 3 BOX layers. (invited paper)

  13. DOUBLE BOSS SCULPTURED DIAPHRAGM EMPLOYED PIEZORESISTIVE MEMS PRESSURE SENSOR WITH SILICON-ON-INSULATOR (SOI

    Directory of Open Access Journals (Sweden)

    D. SINDHANAISELVI

    2017-07-01

    Full Text Available This paper presents the detailed study on the measurement of low pressure sensor using double boss sculptured diaphragm of piezoresistive type with MEMS technology in flash flood level measurement. The MEMS based very thin diaphragms to sense the low pressure is analyzed by introducing supports to achieve linearity. The simulation results obtained from Intellisuite MEMS CAD design tool show that very thin diaphragms with rigid centre or boss give acceptable linearity. Further investigations on very thin diaphragms embedded with piezoresistor for low pressure measurement show that it is essential to analyse the piezoresistor placement and size of piezoresistor to achieve good sensitivity. A modified analytical modelling developed in this study for double boss sculptured diaphragm results were compared with simulated results. Further the enhancement of sensitivity is analyzed using non uniform thickness diaphragm and Silicon-On-Insulator (SOI technique. The simulation results indicate that the double boss square sculptured diaphragm with SOI layer using 0.85μm thickness yields the higher voltage sensitivity, acceptable linearity with Small Scale Deflection.

  14. Strong Electro-Absorption in GeSi Epitaxy on Silicon-on-Insulator (SOI

    Directory of Open Access Journals (Sweden)

    John E. Cunningham

    2012-04-01

    Full Text Available We have investigated the selective epitaxial growth of GeSi bulk material on silicon-on-insulator substrates by reduced pressure chemical vapor deposition. We employed AFM, SIMS, and Hall measurements, to characterize the GeSi heteroepitaxy quality. Optimal growth conditions have been identified to achieve low defect density, low RMS roughness with high selectivity and precise control of silicon content. Fabricated vertical p-i-n diodes exhibit very low dark current density of 5 mA/cm2 at −1 V bias. Under a 7.5 V/µm E-field, GeSi alloys with 0.6% Si content demonstrate very strong electro-absorption with an estimated effective ∆α/α around 3.5 at 1,590 nm. We compared measured ∆α/α performance to that of bulk Ge. Optical modulation up to 40 GHz is observed in waveguide devices while small signal analysis indicates bandwidth is limited by device parasitics.

  15. Silicon-on-insulator (SOI) active pixel sensors with the photosite implemented in the substrate

    Science.gov (United States)

    Zheng, Xinyu (Inventor); Pain, Bedabrata (Inventor)

    2005-01-01

    Active pixel sensors for a high quality imager are fabricated using a silicon-on-insulator (SOI) process by integrating the photodetectors on the SOI substrate and forming pixel readout transistors on the SOI thin-film. The technique can include forming silicon islands on a buried insulator layer disposed on a silicon substrate and selectively etching away the buried insulator layer over a region of the substrate to define a photodetector area. Dopants of a first conductivity type are implanted to form a signal node in the photodetector area and to form simultaneously drain/source regions for a first transistor in at least a first one of the silicon islands. Dopants of a second conductivity type are implanted to form drain/source regions for a second transistor in at least a second one of the silicon islands. Isolation rings around the photodetector also can be formed when dopants of the second conductivity type are implanted. Interconnections among the transistors and the photodetector are provided to allow signals sensed by the photodetector to be read out via the transistors formed on the silicon islands.

  16. Radiation Effects in Advanced Multiple Gate and Silicon-on-Insulator Transistors

    Science.gov (United States)

    Simoen, Eddy; Gaillardin, Marc; Paillet, Philippe; Reed, Robert A.; Schrimpf, Ron D.; Alles, Michael L.; El-Mamouni, Farah; Fleetwood, Daniel M.; Griffoni, Alessio; Claeys, Cor

    2013-06-01

    The aim of this review paper is to describe in a comprehensive manner the current understanding of the radiation response of state-of-the-art Silicon-on-Insulator (SOI) and FinFET CMOS technologies. Total Ionizing Dose (TID) response, heavy-ion microdose effects and single-event effects (SEEs) will be discussed. It is shown that a very high TID tolerance can be achieved by narrow-fin SOI FinFET architectures, while bulk FinFETs may exhibit similar TID response to the planar devices. Due to the vertical nature of FinFETs, a specific heavy-ion response can be obtained, whereby the angle of incidence becomes highly important with respect to the vertical sidewall gates. With respect to SEE, the buried oxide in the SOI FinFETs suppresses the diffusion tails from the charge collection in the substrate compared to the planar bulk FinFET devices. Channel lengths and fin widths are now comparable to, or smaller than the dimensions of the region affected by the single ionizing ions or lasers used in testing. This gives rise to a high degree of sensitivity to individual device parameters and source-drain shunting during ion-beam or laser-beam SEE testing. Simulations are used to illuminate the mechanisms observed in radiation testing and the progress and needs for the numerical modeling/simulation of the radiation response of advanced SOI and FinFET transistors are highlighted.

  17. Space and military radiation effects in silicon-on-insulator devices

    International Nuclear Information System (INIS)

    Schwank, J.R.

    1996-09-01

    Advantages in transient ionizing and single-event upset (SEU) radiation hardness of silicon-on-insulator (SOI) technology spurred much of its early development. Both of these advantages are a direct result of the reduced charge collection volume inherent to SOI technology. The fact that SOI transistor structures do not include parasitic n-p-n-p paths makes them immune to latchup. Even though considerable improvement in transient and single-event radiation hardness can be obtained by using SOI technology, there are some attributes of SOI devices and circuits that tend to limit their overall hardness. These attributes include the bipolar effect that can ultimately reduce the hardness of SOI ICs to SEU and transient ionizing radiation, and charge buildup in buried and sidewall oxides that can degrade the total-dose hardness of SOI devices. Nevertheless, high-performance SOI circuits can be fabricated that are hardened to both space and nuclear radiation environments, and radiation-hardened systems remain an active market for SOI devices. The effects of radiation on SOI MOS devices are reviewed

  18. Gadolinium oxide coated fully depleted silicon-on-insulator transistors for thermal neutron dosimetry

    Energy Technology Data Exchange (ETDEWEB)

    Vitale, Steven A., E-mail: steven.vitale@ll.mit.edu; Gouker, Pascale M.

    2013-09-01

    Fully depleted silicon-on-insulator transistors coated with gadolinium oxide are shown to be effective thermal neutron dosimeters. The theoretical neutron detection efficiency is calculated to be higher for Gd{sub 2}O{sub 3} than for other practical converter materials. Proof-of-concept dosimeter devices were fabricated and tested during thermal neutron irradiation. The transistor current changes linearly with neutron dose, consistent with increasing positive charge in the SOI buried oxide layer generated by ionization from high energy {sup 157}Gd(n,γ){sup 158}Gd conversion electrons. The measured neutron sensitivity is approximately 1/6 the maximum theoretical value, possibly due to electron–hole recombination or conversion electron loss in interconnect wiring above the transistors. -- Highlights: • A novel Gd{sub 2}O{sub 3} coated FDSOI MOSFET thermal neutron dosimeter is presented. • Dosimeter can detect charges generated from {sup 157}Gd(n,γ){sup 158}Gd conversion electrons. • Measured neutron sensitivity is comparable to that calculated theoretically. • Dosimeter requires zero power during operation, enabling new application areas.

  19. A Temperature Sensor using a Silicon-on-Insulator (SOI) Timer for Very Wide Temperature Measurement

    Science.gov (United States)

    Patterson, Richard L.; Hammoud, Ahmad; Elbuluk, Malik; Culley, Dennis E.

    2008-01-01

    A temperature sensor based on a commercial-off-the-shelf (COTS) Silicon-on-Insulator (SOI) Timer was designed for extreme temperature applications. The sensor can operate under a wide temperature range from hot jet engine compartments to cryogenic space exploration missions. For example, in Jet Engine Distributed Control Architecture, the sensor must be able to operate at temperatures exceeding 150 C. For space missions, extremely low cryogenic temperatures need to be measured. The output of the sensor, which consisted of a stream of digitized pulses whose period was proportional to the sensed temperature, can be interfaced with a controller or a computer. The data acquisition system would then give a direct readout of the temperature through the use of a look-up table, a built-in algorithm, or a mathematical model. Because of the wide range of temperature measurement and because the sensor is made of carefully selected COTS parts, this work is directly applicable to the NASA Fundamental Aeronautics/Subsonic Fixed Wing Program--Jet Engine Distributed Engine Control Task and to the NASA Electronic Parts and Packaging (NEPP) Program. In the past, a temperature sensor was designed and built using an SOI operational amplifier, and a report was issued. This work used an SOI 555 timer as its core and is completely new work.

  20. Theoretical model for the detection of charged proteins with a silicon-on-insulator sensor

    International Nuclear Information System (INIS)

    Birner, S; Uhl, C; Bayer, M; Vogl, P

    2008-01-01

    For a bio-sensor device based on a silicon-on-insulator structure, we calculate the sensitivity to specific charge distributions in the electrolyte solution that arise from protein binding to the semiconductor surface. This surface is bio-functionalized with a lipid layer so that proteins can specifically bind to the headgroups of the lipids on the surface. We consider charged proteins such as the green fluorescent protein (GFP) and artificial proteins that consist of a variable number of aspartic acids. Specifically, we calculate self-consistently the spatial charge and electrostatic potential distributions for different ion concentrations in the electrolyte. We fully take into account the quantum mechanical charge density in the semiconductor. We determine the potential change at the binding sites as a function of protein charge and ionic strength. Comparison with experiment is generally very good. Furthermore, we demonstrate the superiority of the full Poisson-Boltzmann equation by comparing its results to the simplified Debye-Hueckel approximation

  1. Adiabatic Nanofocusing in Hybrid Gap Plasmon Waveguides on the Silicon-on-Insulator Platform.

    Science.gov (United States)

    Nielsen, Michael P; Lafone, Lucas; Rakovich, Aliaksandra; Sidiropoulos, Themistoklis P H; Rahmani, Mohsen; Maier, Stefan A; Oulton, Rupert F

    2016-02-10

    We present an experimental demonstration of a new class of hybrid gap plasmon waveguides on the silicon-on-insulator (SOI) platform. Created by the hybridization of the plasmonic mode of a gap in a thin metal sheet and the transverse-electric (TE) photonic mode of an SOI slab, this waveguide is designed for efficient adiabatic nanofocusing simply by varying the gap width. For gap widths greater than 100 nm, the mode is primarily photonic in character and propagation lengths can be many tens of micrometers. For gap widths below 100 nm, the mode becomes plasmonic in character with field confinement predominantly within the gap region and with propagation lengths of a few microns. We estimate the electric field intensity enhancement in hybrid gap plasmon waveguide tapers at 1550 nm by three-photon absorption of selectively deposited CdSe/ZnS quantum dots within the gap. Here, we show electric field intensity enhancements of up to 167 ± 26 for a 24 nm gap, proving the viability of low loss adiabatic nanofocusing on a commercially relevant photonics platform.

  2. Silicon-on-insulator based nanopore cavity arrays for lipid membrane investigation.

    Science.gov (United States)

    Buchholz, K; Tinazli, A; Kleefen, A; Dorfner, D; Pedone, D; Rant, U; Tampé, R; Abstreiter, G; Tornow, M

    2008-11-05

    We present the fabrication and characterization of nanopore microcavities for the investigation of transport processes in suspended lipid membranes. The cavities are situated below the surface of silicon-on-insulator (SOI) substrates. Single cavities and large area arrays were prepared using high resolution electron-beam lithography in combination with reactive ion etching (RIE) and wet chemical sacrificial underetching. The locally separated compartments have a circular shape and allow the enclosure of picoliter volume aqueous solutions. They are sealed at their top by a 250 nm thin Si membrane featuring pores with diameters from 2 µm down to 220 nm. The Si surface exhibits excellent smoothness and homogeneity as verified by AFM analysis. As biophysical test system we deposited lipid membranes by vesicle fusion, and demonstrated their fluid-like properties by fluorescence recovery after photobleaching. As clearly indicated by AFM measurements in aqueous buffer solution, intact lipid membranes successfully spanned the pores. The nanopore cavity arrays have potential applications in diagnostics and pharmaceutical research on transmembrane proteins.

  3. A silicon-on-insulator vertical nanogap device for electrical transport measurements in aqueous electrolyte solution

    Energy Technology Data Exchange (ETDEWEB)

    Strobel, Sebastian [Walter Schottky Institut, Technische Universitaet Muenchen, Am Coulombwall, D-85748 Garching (Germany); Arinaga, Kenji [Walter Schottky Institut, Technische Universitaet Muenchen, Am Coulombwall, D-85748 Garching (Germany); Hansen, Allan [Walter Schottky Institut, Technische Universitaet Muenchen, Am Coulombwall, D-85748 Garching (Germany); Tornow, Marc [Walter Schottky Institut, Technische Universitaet Muenchen, Am Coulombwall, D-85748 Garching (Germany)

    2007-07-25

    A novel concept for metal electrodes with few 10 nm separation for electrical conductance measurements in an aqueous electrolyte environment is presented. Silicon-on-insulator (SOI) material with 10 nm buried silicon dioxide serves as a base substrate for the formation of SOI plateau structures which, after recess-etching the thin oxide layer, thermal oxidation and subsequent metal thin film evaporation, feature vertically oriented nanogap electrodes at their exposed sidewalls. During fabrication only standard silicon process technology without any high-resolution nanolithographic techniques is employed. The vertical concept allows an array-like parallel processing of many individual devices on the same substrate chip. As analysed by cross-sectional TEM analysis the devices exhibit a well-defined material layer architecture, determined by the chosen material thicknesses and process parameters. To investigate the device in aqueous solution, we passivated the sample surface by a polymer layer, leaving a micrometre-size fluid access window to the nanogap region only. First current-voltage characteristics of a 65 nm gap device measured in 60 mM buffer solution reveal excellent electrical isolation behaviour which suggests applications in the field of biomolecular electronics in a natural environment.

  4. Light extraction from GaN-based LED structures on silicon-on-insulator substrates

    Energy Technology Data Exchange (ETDEWEB)

    Tripathy, S.; Teo, S.L.; Lin, V.K.X.; Chen, M.F. [Institute of Materials Research and Engineering, A*STAR (Agency for Science, Technology, and Research), 117602 (Singapore); Dadgar, A.; Krost, A. [Institut fuer Exerimentelle Physik, Otto-von Guericke Universitaet Magdeburg, Universitaetsplatz 1, 39016 Magdeburg (Germany); AZZURRO Semiconductors AG, Universitaetsplatz 1, 39016 Magdeburg (Germany); Christen, J. [Institut fuer Exerimentelle Physik, Otto-von Guericke Universitaet Magdeburg, Universitaetsplatz 1, 39016 Magdeburg (Germany)

    2010-01-15

    Nano-patterning of GaN-based devices is a promising technology in the development of high output power devices. Recent researches have been focused on the realization of two-dimensional (2D) photonic crystal (PhC) structure to improve light extraction efficiency and to control the direction of emission. In this study, we have demonstrated improved light extraction from green light emitting diode (LED) structures on thin silicon-on-insulator (SOI) substrates using surface nanopatterning. Scanning electron microscopy (SEM) is used to probe the size, shape, and etch depth of nano-patterns on the LED surfaces. Different types of nanopatterns were created by e-beam lithography and inductively coupled plasma etching. The LED structures after post processing are studied by photoluminescence (PL) measurements. The GaN nanophotonic structures formed by ICP etching led to more than five-fold increase in the intensity of the green emission. The improved light extraction is due to the combination of SOI substrate reflectivity and photonic structures on top GaN LED surfaces. (copyright 2010 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

  5. Nanodiamond resonators fabricated on 8″ Si substrates using adhesive wafer bonding

    Science.gov (United States)

    Lebedev, V.; Lisec, T.; Yoshikawa, T.; Reusch, M.; Iankov, D.; Giese, C.; Žukauskaitė, A.; Cimalla, V.; Ambacher, O.

    2017-06-01

    In this work, the adhesive wafer bonding of diamond thin films onto 8″ silicon substrates is reported. In order to characterize bonded nano-crystalline diamond layers, vibrometry and interferometry studies of micro-fabricated flexural beam and disk resonators were carried out. In particular, surface topology along with resonant frequencies, eigenmodes and mechanical quality factors were recorded and analyzed in order to obtain physical parameters of the transferred films. The vibration properties of the bonded resonators were compared to those fabricated directly on 3″ silicon substrates.

  6. Optical microcavities based on surface modes in two-dimensional photonic crystals and silicon-on-insulator photonic crystals

    DEFF Research Database (Denmark)

    Xiao, Sanshui; Qiu, M.

    2007-01-01

    Surface-mode optical microcavities based on two-dimensional photonic crystals and silicon-on-insulator photonic crystals are studied. We demonstrate that a high-quality-factor microcavity can be easily realized in these structures. With an increasing of the cavity length, the quality factor is gr...... is gradually enhanced and the resonant frequency converges to that of the corresponding surface mode in the photonic crystals. These structures have potential applications such as sensing.......Surface-mode optical microcavities based on two-dimensional photonic crystals and silicon-on-insulator photonic crystals are studied. We demonstrate that a high-quality-factor microcavity can be easily realized in these structures. With an increasing of the cavity length, the quality factor...

  7. A pile-up phenomenon during arsenic diffusion in silicon-on-insulator structures formed by oxygen implantation

    Science.gov (United States)

    Normand, P.; Tsoukalas, D.; Guillemot, N.; Chenevier, P.

    1989-10-01

    Arsenic diffusion in silicon-on-insulator formed by deep oxygen implantation is studied by secondary ion mass spectroscopy and speading resistance measurements. An enhanced diffusivity as well as a pile-up phenomenon are observed in the thin silicon layer. The McNabb and Foster equations [Trans. TMS-AIME 22, 618 (1963)] for diffusion with trapping are solved in order to simulate this last effect.

  8. Silicon-on-insulator-based polarization-independent 1×3 broadband beam splitter with adiabatic coupling

    Science.gov (United States)

    Gong, Yuanhao; Liu, Lei; Chang, Limin; Li, Zhiyong; Tan, Manqing; Yu, Yude

    2017-10-01

    We propose and numerically simulate a polarization-independent 1×3 broadband beam splitter based on silicon-on-insulator (SOI) technology with adiabatic coupling. The designed structure is simulated by beam-propagation-method (BPM) and gets simulated transmission uniformity of three outputs better than 0.3dB for TE-polarization and 0.8dB for TM-polarization in a broadband of 180nm.

  9. Modelling of a DBR laser based on Raman effect in a silicon-on-insulator rib waveguide

    International Nuclear Information System (INIS)

    De Leonardis, Francesco; Dimastrodonato, Valeria; Passaro, Vittorio M N

    2008-01-01

    In this paper, third-order nonlinearities in silicon-on-insulator rib waveguides are investigated to obtain complete modelling, describing the behaviour of a stimulated Raman scattering based laser. The simulations of a distributed Bragg reflector laser operation in a time domain allow for the first time to study in detail the dependence of threshold and output powers on different device parameters. Both continuous wave and pulsed laser operations are theoretically demonstrated, as well as their dependence on device parameters

  10. Integrated circuits of silicon on insulator S.O.I. technologies: State of the art and perspectives

    International Nuclear Information System (INIS)

    Leray, J.L.; Dupont-Nivet, E.; Raffaelli, M.; Coic, Y.M.; Musseau, O.; Pere, J.F.; Lalande, P.; Bredy, J.; Auberton-Herve, A.J.; Bruel, M.; Giffard, B.

    1989-01-01

    Silicon On Insulator technologies have been proposed to increase the integrated circuits performances in radiation operation. Active researches are conducted, in France and abroad. This paper reviews briefly radiation effects phenomenology in that particular type of structure S.O.I. New results are presented that show very good radiation behaviour in term of speed, dose (10 to 100 megarad (Si)), dose rate and S.E.U. performances [fr

  11. Accurate characterization of wafer bond toughness with the double cantilever specimen

    Science.gov (United States)

    Turner, Kevin T.; Spearing, S. Mark

    2008-01-01

    The displacement loaded double cantilever test, also referred to as the "Maszara test" and the "crack opening method" by the wafer bonding community, is a common technique used to evaluate the interface toughness or surface energy of direct wafer bonds. While the specimen is widely used, there has been a persistent question as to the accuracy of the method since the actual specimen geometry differs from the ideal beam geometry assumed in the expression used for data reduction. The effect of conducting the test on whole wafer pairs, in which the arms of cantilevers are wide plates rather than slender beams, is examined in this work using finite element analysis. A model is developed to predict the equilibrium shape of the crack front and to develop a corrected expression for calculating interface toughness from crack length measurements obtained in tests conducted on whole wafer pairs. The finite element model, which is validated through comparison to experiments, demonstrates that using the traditional beam theory-based expressions for data reduction can lead to errors of up to 25%.

  12. The Evolution of Wafer Bonding Moving from the back-end further to the front-end

    Institute of Scientific and Technical Information of China (English)

    Thomas Glinsner; Peter Hangweier

    2009-01-01

    @@ 1 Introduction As the nanoscale era progresses, innovative new materials and processes continue to be developed and implemented as a means of keeping the industry on the path of Moore's Law. Wafer bonding - literally, the temporary or permanent joining of two wafers or substrates using a suitable combination of process technologies, chemicals and adhesives - is one such innovation.

  13. Fabrication and Characterization of Capacitive Micromachined Ultrasonic Transducers with Low-Temperature Wafer Direct Bonding

    Directory of Open Access Journals (Sweden)

    Xiaoqing Wang

    2016-12-01

    Full Text Available This paper presents a fabrication method of capacitive micromachined ultrasonic transducers (CMUTs by wafer direct bonding, which utilizes both the wet chemical and O2plasma activation processes to decrease the bonding temperature to 400 °C. Two key surface properties, the contact angle and surface roughness, are studied in relation to the activation processes, respectively. By optimizing the surface activation parameters, a surface roughness of 0.274 nm and a contact angle of 0° are achieved. The infrared images and static deflection of devices are assessed to prove the good bonding effect. CMUTs having silicon membranes with a radius of 60 μm and a thickness of 2 μm are fabricated. Device properties have been characterized by electrical and acoustic measurements to verify their functionality and thus to validate this low-temperature process. A resonant frequency of 2.06 MHz is obtained by the frequency response measurements. The electrical insertion loss and acoustic signal have been evaluated. This study demonstrates that the CMUT devices can be fabricated by low-temperature wafer direct bonding, which makes it possible to integrate them directly on top of integrated circuit (IC substrates.

  14. Solar thermoelectric generators fabricated on a silicon-on-insulator substrate

    International Nuclear Information System (INIS)

    De Leon, Maria Theresa; Chong, Harold; Kraft, Michael

    2014-01-01

    Solar thermal power generation is an attractive electricity generation technology as it is environment-friendly, has the potential for increased efficiency, and has high reliability. The design, modelling, and evaluation of solar thermoelectric generators (STEGs) fabricated on a silicon-on-insulator substrate are presented in this paper. Solar concentration is achieved by using a focusing lens to concentrate solar input onto the membrane of the STEG. A thermal model is developed based on energy balance and heat transfer equations using lumped thermal conductances. This thermal model is shown to be in good agreement with actual measurement results. For a 1 W laser input with a spot size of 1 mm, a maximum open-circuit voltage of 3.06 V is obtained, which translates to a temperature difference of 226 °C across the thermoelements and delivers 25 µW of output power under matched load conditions. Based on solar simulator measurements, a maximum TEG voltage of 803 mV was achieved by using a 50.8 mm diameter plano-convex lens to focus solar input to a TEG with a length of 1000 µm, width of 15 µm, membrane diameter of 3 mm, and 114 thermocouples. This translates to a temperature difference of 18 °C across the thermoelements and an output power under matched load conditions of 431 nW. This paper demonstrates that by utilizing a solar concentrator to focus solar radiation onto the hot junction of a TEG, the temperature difference across the device is increased; subsequently improving the TEG’s efficiency. By using materials that are compatible with standard CMOS and MEMS processes, integration of solar-driven TEGs with on-chip electronics is seen to be a viable way of solar energy harvesting where the resulting microscale system is envisioned to have promising applications in on-board power sources, sensor networks, and autonomous microsystems. (paper)

  15. III-V/Si wafer bonding using transparent, conductive oxide interlayers

    Energy Technology Data Exchange (ETDEWEB)

    Tamboli, Adele C., E-mail: Adele.Tamboli@nrel.gov; Hest, Maikel F. A. M. van; Steiner, Myles A.; Essig, Stephanie; Norman, Andrew G.; Bosco, Nick; Stradins, Paul [National Center for Photovoltaics, National Renewable Energy Laboratory, 15013 Denver West Pkwy, Golden, Colorado 80401 (United States); Perl, Emmett E. [Department of Electrical and Computer Engineering, University of California, Santa Barbara, California 93106-9560 (United States)

    2015-06-29

    We present a method for low temperature plasma-activated direct wafer bonding of III-V materials to Si using a transparent, conductive indium zinc oxide interlayer. The transparent, conductive oxide (TCO) layer provides excellent optical transmission as well as electrical conduction, suggesting suitability for Si/III-V hybrid devices including Si-based tandem solar cells. For bonding temperatures ranging from 100 °C to 350 °C, Ohmic behavior is observed in the sample stacks, with specific contact resistivity below 1 Ω cm{sup 2} for samples bonded at 200 °C. Optical absorption measurements show minimal parasitic light absorption, which is limited by the III-V interlayers necessary for Ohmic contact formation to TCOs. These results are promising for Ga{sub 0.5}In{sub 0.5}P/Si tandem solar cells operating at 1 sun or low concentration conditions.

  16. Fabrication, structural and electrical properties of (1 1 0) localized silicon-on-insulator devices

    International Nuclear Information System (INIS)

    Destefanis, V; Huguenin, J L; Samson, M P; Morand, Y; Arvet, C; Monfray, S; Skotnicki, T; Hartmann, J M; Delaye, V; Boulitreau, P; Brianceau, P; Gautier, P

    2010-01-01

    The aim being to fabricate (1 1 0) localized silicon-on-insulator (L-SOI) devices, we have first of all completed the Semicond. Sci. Technol. 23 105018 (2008) study of the differences between (1 1 0) and (1 0 0) surfaces in terms of (i) HCl etch kinetics and (ii) SiGe growth kinetics (with a chlorinated chemistry). The core layers of a L-SOI device are indeed obtained thanks to the in situ HCl etching (on patterned wafers) of the Si active areas followed by the selective epitaxial growth of a Si 0.7 Ge 0.3 /Si stack. Given that SiGe(1 1 0) layers grown at 650 °C in windows of patterned wafers are rough, we have first of all studied the 600 °C growth kinetics of SiGe(1 1 0). As expected, the SiGe growth rate decreases as the growth temperature decreases from 650 °C down to 600 °C (irrespective of the surface orientation). The SiGe(1 0 0) growth rate increases linearly with the germane mass flow. Meanwhile, the SiGe(1 1 0) growth rate increases in a sub-linear fashion and then saturates at much lower values than on (1 0 0). The Ge concentration x dependence on the F(GeH 4 )/F(SiH 2 Cl 2 ) mass flow ratio is parabolic on (1 0 0) and linear on (1 1 0), with lower values on the latter than on the former. We have then used those data to fabricate (1 0 0) and (1 1 0) L-SOI structures. The high HCl partial pressure recessing of the Si(1 1 0) and Si(1 0 0) active areas was performed at 675 °C and 725 °C, respectively. An increase of both the Si(1 1 0) HCl etch rate and the SiGe growth rate (be it at 650 °C on (1 0 0) or at 600 °C on (1 1 0)) was noticed when switching from blanket to patterned wafers (factors of 2.5–3 for HCI and 1.5 for SiGe). Finally, Si(1 1 0) growth times were multiplied by 4/3 compared to the Si(1 0 0) growth time in order to obtain similar thickness Si caps. Subsequent process steps were very similar on (1 0 0) and (1 1 0). Almost the same etch rates were

  17. Tunable complex-valued multi-tap microwave photonic filter based on single silicon-on-insulator microring resonator.

    Science.gov (United States)

    Lloret, Juan; Sancho, Juan; Pu, Minhao; Gasulla, Ivana; Yvind, Kresten; Sales, Salvador; Capmany, José

    2011-06-20

    A complex-valued multi-tap tunable microwave photonic filter based on single silicon-on-insulator microring resonator is presented. The degree of tunability of the approach involving two, three and four taps is theoretical and experimentally characterized, respectively. The constraints of exploiting the optical phase transfer function of a microring resonator aiming at implementing complex-valued multi-tap filtering schemes are also reported. The trade-off between the degree of tunability without changing the free spectral range and the number of taps is studied in-depth. Different window based scenarios are evaluated for improving the filter performance in terms of the side-lobe level.

  18. Unified analytical threshold voltage model for non-uniformly doped dual metal gate fully depleted silicon-on-insulator MOSFETs

    Science.gov (United States)

    Rao, Rathnamala; Katti, Guruprasad; Havaldar, Dnyanesh S.; DasGupta, Nandita; DasGupta, Amitava

    2009-03-01

    The paper describes the unified analytical threshold voltage model for non-uniformly doped, dual metal gate (DMG) fully depleted silicon-on-insulator (FDSOI) MOSFETs based on the solution of 2D Poisson's equation. 2D Poisson's equation is solved analytically for appropriate boundary conditions using separation of variables technique. The solution is then extended to obtain the threshold voltage of the FDSOI MOSFET. The model is able to handle any kind of non-uniform doping, viz. vertical, lateral as well as laterally asymetric channel (LAC) profile in the SOI film in addition to the DMG structure. The analytical results are validated with the numerical simulations using the device simulator MEDICI.

  19. Fabrication of an integrated ΔE-E-silicon detector by wafer bonding using cobalt disilicide

    International Nuclear Information System (INIS)

    Thungstroem, G.; Veldhuizen, E.J. van; Westerberg, L.; Norlin, L.-O.; Petersson, C.S.

    1997-01-01

    The problem concerning mechanical stability of thin self-supporting ΔE detector in a ΔE-E semiconductor detector telescope, has been solved by integrating both detectors into one unit. We show here a low-cost method to integrate the detectors by wafer bonding using cobalt disilicide. The ΔE-detector has a thickness of 6.5 μm and the E detector 290 μm with an area of 24.8 mm 2 . The system was characterized with secondary ion mass spectroscopy (SIMS), scanning electron microscopy (SEM), electrical measurement, particle measurement and two-dimensional electrical simulation. (orig.)

  20. Fabrication of an integrated {Delta}E-E-silicon detector by wafer bonding using cobalt disilicide

    Energy Technology Data Exchange (ETDEWEB)

    Thungstroem, G. [Mid-Sweden Univ., Sundsvall (Sweden). Dept. of Inf. Technol.]|[Royal Institute of Technology, Department of Electronics, Electrum 229, S-164 40 Kista (Sweden); Veldhuizen, E.J. van [Uppsala University, Department of Radiation Science, Box 535, S-751 21 Uppsala (Sweden); Westerberg, L. [Uppsala University, The Svedberg Laboratory, Box 533, S-751 21 Uppsala (Sweden); Norlin, L.-O. [Royal Institute of Technology, Department of Physics, Frescativaegen 24, S-104 05 Stockholm (Sweden); Petersson, C.S. [Royal Institute of Technology, Department of Electronics, Electrum 229, S-164 40 Kista (Sweden)

    1997-06-01

    The problem concerning mechanical stability of thin self-supporting {Delta}E detector in a {Delta}E-E semiconductor detector telescope, has been solved by integrating both detectors into one unit. We show here a low-cost method to integrate the detectors by wafer bonding using cobalt disilicide. The {Delta}E-detector has a thickness of 6.5 {mu}m and the E detector 290 {mu}m with an area of 24.8 mm{sup 2}. The system was characterized with secondary ion mass spectroscopy (SIMS), scanning electron microscopy (SEM), electrical measurement, particle measurement and two-dimensional electrical simulation. (orig.).

  1. Integrated optical MEMS using through-wafer vias and bump-bonding.

    Energy Technology Data Exchange (ETDEWEB)

    McCormick, Frederick Bossert; Frederick, Scott K.

    2008-01-01

    This LDRD began as a three year program to integrate through-wafer vias, micro-mirrors and control electronics with high-voltage capability to yield a 64 by 64 array of individually controllable micro-mirrors on 125 or 250 micron pitch with piston, tip and tilt movement. The effort was a mix of R&D and application. Care was taken to create SUMMiT{trademark} (Sandia's ultraplanar, multilevel MEMS technology) compatible via and mirror processes, and the ultimate goal was to mate this MEMS fabrication product to a complementary metal-oxide semiconductor (CMOS) electronics substrate. Significant progress was made on the via and mirror fabrication and design, the attach process development as well as the electronics high voltage (30 volt) and control designs. After approximately 22 months, the program was ready to proceed with fabrication and integration of the electronics, final mirror array, and through wafer vias to create a high resolution OMEMS array with individual mirror electronic control. At this point, however, mission alignment and budget constraints reduced the last year program funding and redirected the program to help support the through-silicon via work in the Hyper-Temporal Sensors (HTS) Grand Challenge (GC) LDRD. Several months of investigation and discussion with the HTS team resulted in a revised plan for the remaining 10 months of the program. We planned to build a capability in finer-pitched via fabrication on thinned substrates along with metallization schemes and bonding techniques for very large arrays of high density interconnects (up to 2000 x 2000 vias). Through this program, Sandia was able to build capability in several different conductive through wafer via processes using internal and external resources, MEMS mirror design and fabrication, various bonding techniques for arrayed substrates, and arrayed electronics control design with high voltage capability.

  2. Low-temperature wafer direct bonding of silicon and quartz glass by a two-step wet chemical surface cleaning

    Science.gov (United States)

    Wang, Chenxi; Xu, Jikai; Zeng, Xiaorun; Tian, Yanhong; Wang, Chunqing; Suga, Tadatomo

    2018-02-01

    We demonstrate a facile bonding process for combining silicon and quartz glass wafers by a two-step wet chemical surface cleaning. After a post-annealing at 200 °C, strong bonding interfaces with no defects or microcracks were obtained. On the basis of the detailed surface and bonding interface characterizations, the bonding mechanism was explored and discussed. The amino groups terminated on the cleaned surfaces might contribute to the bonding strength enhancement during the annealing. This cost-effective bonding process has great potentials for silicon- and glass-based heterogeneous integrations without requiring a vacuum system.

  3. Low-Cost High-Efficiency Solar Cells with Wafer Bonding and Plasmonic Technologies

    Science.gov (United States)

    Tanake, Katsuaki

    We fabricated a direct-bond interconnected multijunction solar cell, a two-terminal monolithic GaAs/InGaAs dual-junction cell, to demonstrate a proof-of-principle for the viability of direct wafer bonding for solar cell applications. The bonded interface is a metal-free n+GaAs/n +InP tunnel junction with highly conductive Ohmic contact suitable for solar cell applications overcoming the 4% lattice mismatch. The quantum efficiency spectrum for the bonded cell was quite similar to that for each of unbonded GaAs and InGaAs subcells. The bonded dual-junction cell open-circuit voltage was equal to the sum of the unbonded subcell open-circuit voltages, which indicates that the bonding process does not degrade the cell material quality since any generated crystal defects that act as recombination centers would reduce the open-circuit voltage. Also, the bonded interface has no significant carrier recombination rate to reduce the open circuit voltage. Engineered substrates consisting of thin films of InP on Si handle substrates (InP/Si substrates or epitaxial templates) have the potential to significantly reduce the cost and weight of compound semiconductor solar cells relative to those fabricated on bulk InP substrates. InGaAs solar cells on InP have superior performance to Ge cells at photon energies greater than 0.7 eV and the current record efficiency cell for 1 sun illumination was achieved using an InGaP/GaAs/InGaAs triple junction cell design with an InGaAs bottom cell. Thermophotovoltaic (TPV) cells from the InGaAsP-family of III-V materials grown epitaxially on InP substrates would also benefit from such an InP/Si substrate. Additionally, a proposed four-junction solar cell fabricated by joining subcells of InGaAs and InGaAsP grown on InP with subcells of GaAs and AlInGaP grown on GaAs through a wafer-bonded interconnect would enable the independent selection of the subcell band gaps from well developed materials grown on lattice matched substrates. Substitution of

  4. Investigation of Surface Pre-Treatment Methods for Wafer-Level Cu-Cu Thermo-Compression Bonding

    Directory of Open Access Journals (Sweden)

    Koki Tanaka

    2016-12-01

    Full Text Available To increase the yield of the wafer-level Cu-Cu thermo-compression bonding method, certain surface pre-treatment methods for Cu are studied which can be exposed to the atmosphere before bonding. To inhibit re-oxidation under atmospheric conditions, the reduced pure Cu surface is treated by H2/Ar plasma, NH3 plasma and thiol solution, respectively, and is covered by Cu hydride, Cu nitride and a self-assembled monolayer (SAM accordingly. A pair of the treated wafers is then bonded by the thermo-compression bonding method, and evaluated by the tensile test. Results show that the bond strengths of the wafers treated by NH3 plasma and SAM are not sufficient due to the remaining surface protection layers such as Cu nitride and SAMs resulting from the pre-treatment. In contrast, the H2/Ar plasma–treated wafer showed the same strength as the one with formic acid vapor treatment, even when exposed to the atmosphere for 30 min. In the thermal desorption spectroscopy (TDS measurement of the H2/Ar plasma–treated Cu sample, the total number of the detected H2 was 3.1 times more than the citric acid–treated one. Results of the TDS measurement indicate that the modified Cu surface is terminated by chemisorbed hydrogen atoms, which leads to high bonding strength.

  5. Low-temperature wafer-level gold thermocompression bonding: modeling of flatness deviations and associated process optimization for high yield and tough bonds

    Science.gov (United States)

    Stamoulis, Konstantinos; Tsau, Christine H.; Spearing, S. Mark

    2005-01-01

    Wafer-level, thermocompression bonding is a promising technique for MEMS packaging. The quality of the bond is critically dependent on the interaction between flatness deviations, the gold film properties and the process parameters and tooling used to achieve the bonds. The effect of flatness deviations on the resulting bond is investigated in the current work. The strain energy release rate associated with the elastic deformation required to overcome wafer bow is calculated. A contact yield criterion is used to examine the pressure and temperature conditions required to flatten surface roughness asperities in order to achieve bonding over the full apparent area. The results are compared to experimental data of bond yield and toughness obtained from four-point bend delamination testing and microscopic observations of the fractured surfaces. Conclusions from the modeling and experiments indicate that wafer bow has negligible effect on determining the variability of bond quality and that the well-bonded area is increased with increasing bonding pressure. The enhanced understanding of the underlying deformation mechanisms allows for a better controlled trade-off between the bonding pressure and temperature.

  6. Epitaxial Reactor Development for Growth of Silicon-on-Insulator Devices.

    Science.gov (United States)

    1987-04-01

    emision from substrate reflected from interface 40 Constructive interference condition 2tc= n X / 1 * Destrictive interference condition 2tD= (2n+1) X...combinations of growth conditions resulted in no oxide growth on the original silicon wafer. Growths occurred for Si:O molecular ratios higher than 1:1...growth rates occurred at 1050 0 C with water vapor at 1250 cc/min and silane at 50 cc/min. These results are shown in Table 6. The molecular ratio was 2:1

  7. Silicon on insulator by ion implantation: A dream or a reality

    Energy Technology Data Exchange (ETDEWEB)

    Pinizzotto, R F [Ultrastructure, Inc., Richardson, TX (USA)

    1985-03-01

    One method of producing a silicon-on-oxide structure is to implant a sufficient dose of oxygen into a conventional silicon substrate to synthesize a layer of SiO/sub 2/ just below the surface. If the proper implant conditions are maintained, the top silicon layer will be a single crystal. The required doses are large, but the use of commercially available medium current implanters can reduce the time to 25 minutes per wafer. This adds about $ 10 per chip in process related costs. A very large implanter (100 mA analyzed beam) may not be the best approach for scaling up the process. The power in the beam and the power required for operation of the machine are both enormous. A more conservative approach of using multiple medium current implanters may prove to be more economical in the long run.

  8. Development of a classical force field for the oxidized Si surface: application to hydrophilic wafer bonding.

    Science.gov (United States)

    Cole, Daniel J; Payne, Mike C; Csányi, Gábor; Spearing, S Mark; Colombi Ciacchi, Lucio

    2007-11-28

    We have developed a classical two- and three-body interaction potential to simulate the hydroxylated, natively oxidized Si surface in contact with water solutions, based on the combination and extension of the Stillinger-Weber potential and of a potential originally developed to simulate SiO(2) polymorphs. The potential parameters are chosen to reproduce the structure, charge distribution, tensile surface stress, and interactions with single water molecules of a natively oxidized Si surface model previously obtained by means of accurate density functional theory simulations. We have applied the potential to the case of hydrophilic silicon wafer bonding at room temperature, revealing maximum room temperature work of adhesion values for natively oxidized and amorphous silica surfaces of 97 and 90 mJm(2), respectively, at a water adsorption coverage of approximately 1 ML. The difference arises from the stronger interaction of the natively oxidized surface with liquid water, resulting in a higher heat of immersion (203 vs 166 mJm(2)), and may be explained in terms of the more pronounced water structuring close to the surface in alternating layers of larger and smaller densities with respect to the liquid bulk. The computed force-displacement bonding curves may be a useful input for cohesive zone models where both the topographic details of the surfaces and the dependence of the attractive force on the initial surface separation and wetting can be taken into account.

  9. Wafer-level packaging with compression-controlled seal ring bonding

    Science.gov (United States)

    Farino, Anthony J

    2013-11-05

    A device may be provided in a sealed package by aligning a seal ring provided on a first surface of a first semiconductor wafer in opposing relationship with a seal ring that is provided on a second surface of a second semiconductor wafer and surrounds a portion of the second wafer that contains the device. Forcible movement of the first and second wafer surfaces toward one another compresses the first and second seal rings against one another. A physical barrier against the movement, other than the first and second seal rings, is provided between the first and second wafer surfaces.

  10. Design, fabrication and characterisation of advanced substrate crosstalk suppression structures in silicon on insulator substrates with buried ground planes (GPSOI)

    International Nuclear Information System (INIS)

    Stefanou, Stefanos

    2002-07-01

    Substrate crosstalk or coupling has been acknowledged to be a limiting factor in mixed signal RF integration. Although high levels of integration and high frequencies of operation are desirable for mixed mode RF and microwave circuits, they make substrate crosstalk more pronounced and may lead to circuit performance degradation. High signal isolation is dictated by requirements for low power dissipation, reduced number of components and lower integration costs for feasible system-on-chip (SoC) solutions. Substrate crosstalk suppression in ground plane silicon-on-insulator (GPSOI) substrates is investigated in this thesis. Test structures are designed and fabricated on SOI substrates with a buried WSi 2 plane that is connected to ground; hence it is called a ground plane. A Faraday cage structure that exhibits very high degrees of signal isolation is presented and compared to other SOI isolation schemes. The Faraday cage structure is shown to achieve 20 dB increased isolation in the frequency range of 0.5-50 GHz compared to published data for high resistivity (200 Ωcm) thin film SOI substrates with no ground planes, but where capacitive guard rings were used. The measurement results are analysed with the aid of planar electromagnetic simulators and compact lumped element models of all the fabricated test structures are developed. The accuracy of the lumped models is validated against experimental measurements. (author)

  11. Silicon-on-Insulator Lateral-Insulated-Gate-Bipolar-Transistor with Built-in Self-anti-ESD Diode

    Directory of Open Access Journals (Sweden)

    Xiaojun Cheng

    2014-05-01

    Full Text Available Power SOI (Silicon-On-Insulator devices have an inherent sandwich structure of MOS (Metal-Oxide-Semiconductor gate which is very easy to suffer ESD (Electro-Static Discharge overstress. To solve this reliability problem, studies on design and modification of a built-in self-anti-ESD diode for a preliminarily optimized high voltage SOI LIGBT (Lateral-Insulated-Gate-Bipolar-Transistor were carried out on the Silvaco TCAD (Technology-Computer-Aided-Design platform. According to the constrains of the technological process, the new introduction of the N+ doped region into P-well region that form the built-in self-anti-ESD diode should be done together with the doping of source under the same mask. The modifications were done by adjusting the vertical impurity profile in P-well into retrograde distribution and designing a cathode plate with a proper length to cover the forward depletion terminal and make sure that the thickness of the cathode plate is the same as that of the gate plate. The simulation results indicate that the modified device structure is compatible with the original one in process and design, the breakdown voltage margin of the former was expanded properly, and both the transient cathode voltages are clamped low enough very quickly. Therefore, the design and optimization results of the modified device structure of the built-in self-anti-ESD diode for the given SOI LIGBT meet the given requirements.

  12. X-ray characterization of Ge dots epitaxially grown on nanostructured Si islands on silicon-on-insulator substrates.

    Science.gov (United States)

    Zaumseil, Peter; Kozlowski, Grzegorz; Yamamoto, Yuji; Schubert, Markus Andreas; Schroeder, Thomas

    2013-08-01

    On the way to integrate lattice mismatched semiconductors on Si(001), the Ge/Si heterosystem was used as a case study for the concept of compliant substrate effects that offer the vision to be able to integrate defect-free alternative semiconductor structures on Si. Ge nanoclusters were selectively grown by chemical vapour deposition on Si nano-islands on silicon-on-insulator (SOI) substrates. The strain states of Ge clusters and Si islands were measured by grazing-incidence diffraction using a laboratory-based X-ray diffraction technique. A tensile strain of up to 0.5% was detected in the Si islands after direct Ge deposition. Using a thin (∼10 nm) SiGe buffer layer between Si and Ge the tensile strain increases to 1.8%. Transmission electron microscopy studies confirm the absence of a regular grid of misfit dislocations in such structures. This clear experimental evidence for the compliance of Si nano-islands on SOI substrates opens a new integration concept that is not only limited to Ge but also extendable to semiconductors like III-V and II-VI materials.

  13. Fabrication of open-top microchannel plate using deep X-ray exposure mask made with silicon on insulator substrate

    CERN Document Server

    Fujimura, T; Etoh, S I; Hattori, R; Kuroki, Y; Chang, S S

    2003-01-01

    We propose a high-aspect-ratio open-top microchannel plate structure. This type of microchannel plate has many advantages in electrophoresis. The plate was fabricated by deep X-ray lithography using synchrotron radiation (SR) light and the chemical wet etching process. A deep X-ray exposure mask was fabricated with a silicon on insulator (SOI) substrate. The patterned Si microstructure was micromachined into a thin Si membrane and a thick Au X-ray absorber was embedded in it by electroplating. A plastic material, polymethylmethacrylate (PMMA) was used for the plate substrate. For reduction of the exposure time and high-aspect-ratio fast wet development, the fabrication condition was optimized with respect to not the exposure dose but to the PMMA mean molecular weight (M.W.) changing after deep X-ray exposure as measured by gel permeation chromatography (GPC). Decrement of the PMMA M.W. and increment of the wet developer temperature accelerated the etching rate. Under optimized fabrication conditions, a microc...

  14. Label-free electrical determination of trypsin activity by a silicon-on-insulator based thin film resistor.

    Science.gov (United States)

    Neff, Petra A; Serr, Andreas; Wunderlich, Bernhard K; Bausch, Andreas R

    2007-10-08

    A silicon-on-insulator (SOI) based thin film resistor is employed for the label-free determination of enzymatic activity. We demonstrate that enzymes, which cleave biological polyelectrolyte substrates, can be detected by the sensor. As an application, we consider the serine endopeptidase trypsin, which cleaves poly-L-lysine (PLL). We show that PLL adsorbs quasi-irreversibly to the sensor and is digested by trypsin directly at the sensor surface. The created PLL fragments are released into the bulk solution due to kinetic reasons. This results in a measurable change of the surface potential allowing for the determination of trypsin concentrations down to 50 ng mL(-1). Chymotrypsin is a similar endopeptidase with a different specificity, which cleaves PLL with a lower efficiency as compared to trypsin. The activity of trypsin is analyzed quantitatively employing a kinetic model for enzyme-catalyzed surface reactions. Moreover, we have demonstrated the specific inactivation of trypsin by a serine protease inhibitor, which covalently binds to the active site of the enzyme.

  15. Formation and dielectric properties of polyelectrolyte multilayers studied by a silicon-on-insulator based thin film resistor.

    Science.gov (United States)

    Neff, Petra A; Wunderlich, Bernhard K; Klitzing, Regine V; Bausch, Andreas R

    2007-03-27

    The formation of polyelectrolyte multilayers (PEMs) is investigated using a silicon-on-insulator based thin film resistor which is sensitive to variations of the surface potential. The buildup of the PEMs at the silicon oxide surface of the device can be observed in real time as defined potential shifts. The influence of polymer charge density is studied using the strong polyanion poly(styrene sulfonate), PSS, combined with the statistical copolymer poly(diallyl-dimethyl-ammoniumchloride-stat-N-methyl-N-vinylacetamide), P(DADMAC-stat-NMVA), at various degrees of charge (DC). The multilayer formation stops after a few deposition steps for a DC below 75%. We show that the threshold of surface charge compensation corresponds to the threshold of multilayer formation. However, no reversion of the preceding surface charge was observed. Screening of polyelectrolyte charges by mobile ions within the polymer film leads to a decrease of the potential shifts with the number of layers deposited. This decrease is much slower for PEMs consisting of P(DADMAC-stat-NMVA) and PSS as compared to PEMs consisting of poly(allylamine-hydrochloride), PAH, and PSS. From this, significant differences in the dielectric constants of the polyelectrolyte films and in the concentration of mobile ions within the films can be derived.

  16. A Low-Noise X-ray Astronomical Silicon-On-Insulator Pixel Detector Using a Pinned Depleted Diode Structure.

    Science.gov (United States)

    Kamehama, Hiroki; Kawahito, Shoji; Shrestha, Sumeet; Nakanishi, Syunta; Yasutomi, Keita; Takeda, Ayaki; Tsuru, Takeshi Go; Arai, Yasuo

    2017-12-23

    This paper presents a novel full-depletion Si X-ray detector based on silicon-on-insulator pixel (SOIPIX) technology using a pinned depleted diode structure, named the SOIPIX-PDD. The SOIPIX-PDD greatly reduces stray capacitance at the charge sensing node, the dark current of the detector, and capacitive coupling between the sensing node and SOI circuits. These features of the SOIPIX-PDD lead to low read noise, resulting high X-ray energy resolution and stable operation of the pixel. The back-gate surface pinning structure using neutralized p-well at the back-gate surface and depleted n-well underneath the p-well for all the pixel area other than the charge sensing node is also essential for preventing hole injection from the p-well by making the potential barrier to hole, reducing dark current from the Si-SiO₂ interface and creating lateral drift field to gather signal electrons in the pixel area into the small charge sensing node. A prototype chip using 0.2 μm SOI technology shows very low readout noise of 11.0 e - rms , low dark current density of 56 pA/cm² at -35 °C and the energy resolution of 200 eV(FWHM) at 5.9 keV and 280 eV (FWHM) at 13.95 keV.

  17. Wafer-level hermetic thermo-compression bonding using electroplated gold sealing frame planarized by fly-cutting

    Science.gov (United States)

    Farisi, Muhammad Salman Al; Hirano, Hideki; Frömel, Jörg; Tanaka, Shuji

    2017-01-01

    In this paper, a novel wafer-level hermetic packaging technology for heterogeneous device integration is presented. Hermetic sealing is achieved by low-temperature thermo-compression bonding using electroplated Au micro-sealing frame planarized by single-point diamond fly-cutting. The proposed technology has significant advantages compared to other established processes in terms of integration of micro-structured wafer, vacuum encapsulation and electrical interconnection, which can be achieved at the same time. Furthermore, the technology is also achievable for a bonding frame width as narrow as 30 μm, giving it an advantage from a geometry perspective, and bonding temperatures as low as 300 °C, making it advantageous for temperature-sensitive devices. Outgassing in vacuum sealed cavities is studied and a cavity pressure below 500 Pa is achieved by introducing annealing steps prior to bonding. The pressure of the sealed cavity is measured by zero-balance method utilizing diaphragm-structured bonding test devices. The leak rate into the packages is determined by long-term sealed cavity pressure measurement for 1500 h to be less than 2.0× {{10}-14} Pa m3s-1. In addition, the bonding shear strength is also evaluated to be higher than 100 MPa.

  18. Determination of wafer bonding mechanisms for plasma activated SiN films with x-ray reflectivity

    Energy Technology Data Exchange (ETDEWEB)

    Hayashi, S [Department of Materials Science and Engineering, University of California, Los Angeles, CA 90095 (United States); Sandhu, R [Department of Materials Science and Engineering, University of California, Los Angeles, CA 90095 (United States); Wojtowicz, M [Northrop Grumman Space Technology, Redondo Beach, CA 90278 (United States); Sun, Y [Department of Chemical Engineering, University of California, Los Angeles, CA 90095 (United States); Hicks, R [Department of Chemical Engineering, University of California, Los Angeles, CA 90095 (United States); Goorsky, M S [Department of Materials Science and Engineering, University of California, Los Angeles, CA 90095 (United States)

    2005-05-21

    Specular and diffuse x-ray reflectivity measurements were employed for wafer bonding studies of surface and interfacial reactions in {approx}800 A thick SiN films deposited on III-V substrates. CuK{sub {alpha}}{sub 1} radiation was employed for these measurements. The as-deposited films show very low surface roughness and uniform, high density SiN. Reflectivity measurements show that an oxygen plasma treatment converts the nitride surface to a somewhat porous SiO{sub x} layer (67 A thick, at 80% of SiO{sub 2} density), with confirmation of the oxide formation from x-ray photoelectron spectroscopy. Reactions at the bonded interface of two oxygen plasma treated SiN layers were examined using a bonded structure from which one of the III-V wafers is removed. Reflectivity measurements of bonded structures annealed at 150 deg. C and 300 deg. C show an increase in the SiO{sub x} layer density and thickness and even a density gradient across this interface. The increase in density is correlated with an increase in bond strength, where after the 300 deg. C anneal, a high interfacial bond strength, exceeding the bulk strength, was achieved.

  19. Synthesis of highly integrated optical network based on microdisk-resonator add-drop filters in silicon-on-insulator technology

    Science.gov (United States)

    Kaźmierczak, Andrzej; Dortu, Fabian; Giannone, Domenico; Bogaerts, Wim; Drouard, Emmanuel; Rojo-Romeo, Pedro; Gaffiot, Frederic

    2009-10-01

    We analyze a highly compact optical add-drop filter topology based on a pair of microdisk resonators and a bus waveguide intersection. The filter is further assessed on an integrated optical 4×4 network for optical on-chip communication. The proposed network structure, as compact as 50×50 μm, is fabricated in a CMOS-compatible process on a silicon-on-insulator (SOI) substrate. Finally, the experimental results demonstrate the proper operation of the fabricated devices.

  20. Investigation of the heating behavior of carbide-bonded graphene coated silicon wafer used for hot embossing

    Science.gov (United States)

    Yang, Gao; Li, Lihua; Lee, Wing Bun; Ng, Man Cheung; Chan, Chang Yuen

    2018-03-01

    A recently developed carbide-bonded graphene (CBG) coated silicon wafer was found to be an effective micro-patterned mold material for implementing rapid heating in hot embossing processes owing to its superior electrical and thermal conductivity, in addition to excellent mechanical properties. To facilitate the achievement of precision temperature control in the hot embossing, the heating behavior of a CBG coated silicon wafer sample was experimentally investigated. First, two groups of controlled experiments were conducted for quantitatively evaluating the influence of the main factors such as the vacuum pressure and gaseous environment (vacuum versus nitrogen) on its heating performance. The electrical and thermal responses of this sample under a voltage of 60 V were then intensively analyzed, and revealed that it had somewhat semi-conducting properties. Further, we compared its thermal profiles under different settings of the input voltage and current limiting threshold. Moreover, the strong temperature dependence of electrical resistance for this material was observed and determined. Ultimately, the surface temperature of CBG coated silicon wafer could be as high as 1300 ℃, but surprisingly the graphene coating did not detach from the substrate under such an elevated temperature due to its strong thermal coupling with the silicon wafer.

  1. A Novel Fully Depleted Air AlN Silicon-on-Insulator Metal-Oxide-Semiconductor Field Effect Transistor

    International Nuclear Information System (INIS)

    Yuan, Yang; Yong, Gao; Peng-Liang, Gong

    2008-01-01

    A novel fully depleted air AlN silicon-on-insulator (SOI) metal-oxide-semiconductor field effect transistor (MOS-FET) is presented, which can eliminate the self-heating effect and solve the problem that the off-state current of SOI MOSFETs increases and the threshold voltage characteristics become worse when employing a high thermal conductivity material as a buried layer. The simulation results reveal that the lattice temperature in normal SOI devices is 75 K higher than the atmosphere temperature, while the lattice temperature is just 4K higher than the atmosphere temperature resulting in less severe self-heating effect in air AlN SOI MOSFETs and AlN SOI MOSFETs. The on-state current of air AlN SOI MOSFETs is similar to the AlN SOI structure, and improves 12.3% more than that of normal SOI MOSFETs. The off-state current of AlN SOI is 6.7 times of normal SOI MOSFETs, while the counterpart of air AlN SOI MOSFETs is lower than that of SOI MOSFETs by two orders of magnitude. The threshold voltage change of air AlN SOI MOSFETs with different drain voltage is much less than that of AlN SOI devices, when the drain voltage is biased at 0.8 V, this difference is 28mV, so the threshold voltage change induced by employing high thermal conductivity material is cured. (condensed matter: electronic structure, electrical, magnetic, and optical properties)

  2. A full-wafer fabrication process for glass microfluidic chips with integrated electroplated electrodes by direct bonding of dry film resist

    International Nuclear Information System (INIS)

    Vulto, Paul; Urban, G A; Huesgen, Till; Albrecht, Björn

    2009-01-01

    A full-wafer process is presented for fast and simple fabrication of glass microfluidic chips with integrated electroplated electrodes. The process employs the permanent dry film resist (DFR) Ordyl SY300 to create microfluidic channels, followed by electroplating of silver and subsequent chlorination. The dry film resist is bonded directly to a second substrate, without intermediate gluing layers, only by applying pressure and moderate heating. The process of microfluidic channel fabrication, electroplating and wafer bonding can be completed within 1 day, thus making it one of the fastest and simplest full-wafer fabrication processes. (note)

  3. Towards large size substrates for III-V co-integration made by direct wafer bonding on Si

    Directory of Open Access Journals (Sweden)

    N. Daix

    2014-08-01

    Full Text Available We report the first demonstration of 200 mm InGaAs-on-insulator (InGaAs-o-I fabricated by the direct wafer bonding technique with a donor wafer made of III-V heteroepitaxial structure grown on 200 mm silicon wafer. The measured threading dislocation density of the In0.53Ga0.47As (InGaAs active layer is equal to 3.5 × 109 cm−2, and it does not degrade after the bonding and the layer transfer steps. The surface roughness of the InGaAs layer can be improved by chemical-mechanical-polishing step, reaching values as low as 0.4 nm root-mean-square. The electron Hall mobility in 450 nm thick InGaAs-o-I layer reaches values of up to 6000 cm2/Vs, and working pseudo-MOS transistors are demonstrated with an extracted electron mobility in the range of 2000–3000 cm2/Vs. Finally, the fabrication of an InGaAs-o-I substrate with the active layer as thin as 90 nm is achieved with a Buried Oxide of 50 nm. These results open the way to very large scale production of III-V-o-I advanced substrates for future CMOS technology nodes.

  4. Towards large size substrates for III-V co-integration made by direct wafer bonding on Si

    Energy Technology Data Exchange (ETDEWEB)

    Daix, N., E-mail: dai@zurich.ibm.com; Uccelli, E.; Czornomaz, L.; Caimi, D.; Rossel, C.; Sousa, M.; Siegwart, H.; Marchiori, C.; Fompeyrine, J. [IBM Research - Zürich, Säumerstrasse 4, CH-8803 Rüschlikon (Switzerland); Hartmann, J. M. [CEA, LETI 17, rue des Martyrs, F-38054 Grenoble (France); Shiu, K.-T.; Cheng, C.-W.; Krishnan, M.; Lofaro, M.; Kobayashi, M.; Sadana, D. [IBM T. J. Watson Research Center, 1101 Kitchawan Rd., Route 134 Yorktown Heights, New York 10598 (United States)

    2014-08-01

    We report the first demonstration of 200 mm InGaAs-on-insulator (InGaAs-o-I) fabricated by the direct wafer bonding technique with a donor wafer made of III-V heteroepitaxial structure grown on 200 mm silicon wafer. The measured threading dislocation density of the In{sub 0.53}Ga{sub 0.47}As (InGaAs) active layer is equal to 3.5 × 10{sup 9} cm{sup −2}, and it does not degrade after the bonding and the layer transfer steps. The surface roughness of the InGaAs layer can be improved by chemical-mechanical-polishing step, reaching values as low as 0.4 nm root-mean-square. The electron Hall mobility in 450 nm thick InGaAs-o-I layer reaches values of up to 6000 cm{sup 2}/Vs, and working pseudo-MOS transistors are demonstrated with an extracted electron mobility in the range of 2000–3000 cm{sup 2}/Vs. Finally, the fabrication of an InGaAs-o-I substrate with the active layer as thin as 90 nm is achieved with a Buried Oxide of 50 nm. These results open the way to very large scale production of III-V-o-I advanced substrates for future CMOS technology nodes.

  5. Towards large size substrates for III-V co-integration made by direct wafer bonding on Si

    Science.gov (United States)

    Daix, N.; Uccelli, E.; Czornomaz, L.; Caimi, D.; Rossel, C.; Sousa, M.; Siegwart, H.; Marchiori, C.; Hartmann, J. M.; Shiu, K.-T.; Cheng, C.-W.; Krishnan, M.; Lofaro, M.; Kobayashi, M.; Sadana, D.; Fompeyrine, J.

    2014-08-01

    We report the first demonstration of 200 mm InGaAs-on-insulator (InGaAs-o-I) fabricated by the direct wafer bonding technique with a donor wafer made of III-V heteroepitaxial structure grown on 200 mm silicon wafer. The measured threading dislocation density of the In0.53Ga0.47As (InGaAs) active layer is equal to 3.5 × 109 cm-2, and it does not degrade after the bonding and the layer transfer steps. The surface roughness of the InGaAs layer can be improved by chemical-mechanical-polishing step, reaching values as low as 0.4 nm root-mean-square. The electron Hall mobility in 450 nm thick InGaAs-o-I layer reaches values of up to 6000 cm2/Vs, and working pseudo-MOS transistors are demonstrated with an extracted electron mobility in the range of 2000-3000 cm2/Vs. Finally, the fabrication of an InGaAs-o-I substrate with the active layer as thin as 90 nm is achieved with a Buried Oxide of 50 nm. These results open the way to very large scale production of III-V-o-I advanced substrates for future CMOS technology nodes.

  6. Wafer-level integration of NiTi shape memory alloy on silicon using Au–Si eutectic bonding

    International Nuclear Information System (INIS)

    Gradin, Henrik; Bushra, Sobia; Braun, Stefan; Stemme, Göran; Van der Wijngaart, Wouter

    2013-01-01

    This paper reports on the wafer level integration of NiTi shape memory alloy (SMA) sheets with silicon substrates through Au–Si eutectic bonding. Different bond parameters, such as Au layer thicknesses and substrate surface treatments were evaluated. The amount of gold in the bond interface is the most important parameter to achieve a high bond yield; the amount can be determined by the barrier layers between the Au and Si or by the amount of Au deposition. Deposition of a gold layer of more than 1 μm thickness before bonding gives the most promising results. Through patterning of the SMA sheet and by limiting bonding to small areas, stresses created by the thermal mismatch between Si and NiTi are reduced. With a gold layer of 1 μm thickness and bond areas between 200 × 200 and 800 × 800 μm 2 a high bond strength and a yield above 90% is demonstrated. (paper)

  7. High-Throughput Multiple Dies-to-Wafer Bonding Technology and III/V-on-Si Hybrid Lasers for Heterogeneous Integration of Optoelectronic Integrated Circuits

    Directory of Open Access Journals (Sweden)

    Xianshu eLuo

    2015-04-01

    Full Text Available Integrated optical light source on silicon is one of the key building blocks for optical interconnect technology. Great research efforts have been devoting worldwide to explore various approaches to integrate optical light source onto the silicon substrate. The achievements so far include the successful demonstration of III/V-on-Si hybrid lasers through III/V-gain material to silicon wafer bonding technology. However, for potential large-scale integration, leveraging on mature silicon complementary metal oxide semiconductor (CMOS fabrication technology and infrastructure, more effective bonding scheme with high bonding yield is in great demand considering manufacturing needs. In this paper, we propose and demonstrate a high-throughput multiple dies-to-wafer (D2W bonding technology which is then applied for the demonstration of hybrid silicon lasers. By temporarily bonding III/V dies to a handle silicon wafer for simultaneous batch processing, it is expected to bond unlimited III/V dies to silicon device wafer with high yield. As proof-of-concept, more than 100 III/V dies bonding to 200 mm silicon wafer is demonstrated. The high performance of the bonding interface is examined with various characterization techniques. Repeatable demonstrations of 16-III/V-die bonding to pre-patterned 200 mm silicon wafers have been performed for various hybrid silicon lasers, in which device library including Fabry-Perot (FP laser, lateral-coupled distributed feedback (LC-DFB laser with side wall grating, and mode-locked laser (MLL. From these results, the presented multiple D2W bonding technology can be a key enabler towards the large-scale heterogeneous integration of optoelectronic integrated circuits (H-OEIC.

  8. New overlay measurement technique with an i-line stepper using embedded standard field image alignment marks for wafer bonding applications

    Science.gov (United States)

    Kulse, P.; Sasai, K.; Schulz, K.; Wietstruck, M.

    2017-06-01

    In the last decades the semiconductor technology has been driven by Moore's law leading to high performance CMOS technologies with feature sizes of less than 10 nm [1]. It has been pointed out that not only scaling but also the integration of novel components and technology modules into CMOS/BiCMOS technologies is becoming more attractive to realize smart and miniaturized systems [2]. Driven by new applications in the area of communication, health and automation, new components and technology modules such as BiCMOS embedded RF-MEMS, high-Q passives, Sibased microfluidics and InP-SiGe BiCMOS heterointegration have been demonstrated [3-6]. In contrast to standard VLSI processes fabricated on front side of the silicon wafer, these new technology modules require addition backside processing of the wafer; thus an accurate alignment between the front and backside of the wafer is mandatory. In previous work an advanced back to front side alignment technique and implementation into IHP's 0.25/0.13 μm high performance SiGe:C BiCMOS backside process module has been presented [7]. The developed technique enables a high resolution and accurate lithography on the backside of BiCMOS wafer for additional backside processing. In addition to the aforementioned back side process technologies, new applications like Through-Silicon Vias (TSV) for interposers and advanced substrate technologies for 3D heterogeneous integration demand not only single wafer fabrication but also processing of wafer stacks provided by temporary and permanent wafer bonding [8]. Therefore, the available overlay measurement techniques are not suitable if overlay and alignment marks are realized at the bonding interface of a wafer stack which consists of both a silicon device and a silicon carrier wafer. The former used EVG 40NT automated overlay measurement system, which use two opposite positioned microscopes inspecting simultaneous the wafer back and front side, is not capable measuring embedded overlay

  9. Investigation of room-temperature wafer bonded GaInP/GaAs/InGaAsP triple-junction solar cells

    Energy Technology Data Exchange (ETDEWEB)

    Yang, Wen-xian; Dai, Pan; Ji, Lian; Tan, Ming; Wu, Yuan-yuan [Key Lab of Nanodevices and Applications, Suzhou Institute of Nano-Tech and Nano-Bionics, Chinese Academy of Sciences (CAS), Suzhou 215123 (China); Uchida, Shiro [Department of Mechanical Science and Engineering Faculty of Engineering, Chiba Institute of Technology, 2-17-1, Tsudanuma, Narashino, Chiba 275-0016 (Japan); Lu, Shu-long, E-mail: sllu2008@sinano.ac.cn [Key Lab of Nanodevices and Applications, Suzhou Institute of Nano-Tech and Nano-Bionics, Chinese Academy of Sciences (CAS), Suzhou 215123 (China); Yang, Hui [Key Lab of Nanodevices and Applications, Suzhou Institute of Nano-Tech and Nano-Bionics, Chinese Academy of Sciences (CAS), Suzhou 215123 (China)

    2016-12-15

    Highlights: • High quality InGaAsP material with a bandgap of 1.0 eV was grown by MBE. • Room-temperature wafer-bonded GaInP/GaAs/InGaAsP SCs were fabricated. • An efficiency of 30.3% of wafer-bonded triple-junction SCs was obtained. - Abstract: We report on the fabrication of III–V compound semiconductor multi-junction solar cells using the room-temperature wafer bonding technique. GaInP/GaAs dual-junction solar cells on GaAs substrate and InGaAsP single junction solar cell on InP substrate were separately grown by all-solid state molecular beam epitaxy (MBE). The two cells were then bonded to a triple-junction solar cell at room-temperature. A conversion efficiency of 30.3% of GaInP/GaAs/InGaAsP wafer-bonded solar cell was obtained at 1-sun condition under the AM1.5G solar simulator. The result suggests that the room-temperature wafer bonding technique and MBE technique have a great potential to improve the performance of multi-junction solar cell.

  10. Advanced TEM Characterization for the Development of 28-14nm nodes based on fully-depleted Silicon-on-Insulator Technology

    International Nuclear Information System (INIS)

    Servanton, G; Clement, L; Lepinay, K; Lorut, F; Pantel, R; Pofelski, A; Bicais, N

    2013-01-01

    The growing demand for wireless multimedia applications (smartphones, tablets, digital cameras) requires the development of devices combining both high speed performances and low power consumption. A recent technological breakthrough making a good compromise between these two antagonist conditions has been proposed: the 28-14nm CMOS transistor generations based on a fully-depleted Silicon-on-Insulator (FD-SOI) performed on a thin Si film of 5-6nm. In this paper, we propose to review the TEM characterization challenges that are essential for the development of extremely power-efficient System on Chip (SoC)

  11. Ultrafast all-optical switching and error-free 10 Gbit/s wavelength conversion in hybrid InP-silicon on insulator nanocavities using surface quantum wells

    Energy Technology Data Exchange (ETDEWEB)

    Bazin, Alexandre; Monnier, Paul; Beaudoin, Grégoire; Sagnes, Isabelle; Raj, Rama [Laboratoire de Photonique et de Nanostructures (CNRS UPR20), Route de Nozay, Marcoussis 91460 (France); Lenglé, Kevin; Gay, Mathilde; Bramerie, Laurent [Université Européenne de Bretagne (UEB), 5 Boulevard Laënnec, 35000 Rennes (France); CNRS-Foton Laboratory (UMR 6082), Enssat, BP 80518, 22305 Lannion Cedex (France); Braive, Rémy; Raineri, Fabrice, E-mail: fabrice.raineri@lpn.cnrs.fr [Laboratoire de Photonique et de Nanostructures (CNRS UPR20), Route de Nozay, Marcoussis 91460 (France); Université Paris Diderot, Sorbonne Paris Cité, 75207 Paris Cedex 13 (France)

    2014-01-06

    Ultrafast switching with low energies is demonstrated using InP photonic crystal nanocavities embedding InGaAs surface quantum wells heterogeneously integrated to a silicon on insulator waveguide circuitry. Thanks to the engineered enhancement of surface non radiative recombination of carriers, switching time is obtained to be as fast as 10 ps. These hybrid nanostructures are shown to be capable of achieving systems level performance by demonstrating error free wavelength conversion at 10 Gbit/s with 6 mW switching powers.

  12. Hysteresis-free high-temperature precise bimorph actuators produced by direct bonding of lithium niobate wafers

    Energy Technology Data Exchange (ETDEWEB)

    Shur, V. Ya.; Baturin, I. S.; Mingaliev, E. A.; Zorikhin, D. V.; Udalov, A. R.; Greshnyakov, E. D. [Ferroelectric Laboratory, Institute of Natural Sciences, Ural Federal University, 51 Lenin Ave., 620000 Ekaterinburg (Russian Federation)

    2015-02-02

    The current paper presents a piezoelectric bimorph actuator produced by direct bonding of lithium niobate wafers with the mirrored Y and Z axes. Direct bonding technology allowed to fabricate bidomain plate with precise positioning of ideally flat domain boundary. By optimizing the cutting angle (128° Y-cut), the piezoelectric constant became as large as 27.3 pC/N. Investigation of voltage dependence of bending displacement confirmed that bimorph actuator has excellent linearity and hysteresis-free. Decrease of the applied voltage down to mV range showed the perfect linearity up to the sub-nm deflection amplitude. The frequency and temperature dependences of electromechanical transmission coefficient in wide temperature range (from 300 to 900 K) were investigated.

  13. Curvature evolution of 200 mm diameter GaN-on-insulator wafer fabricated through metalorganic chemical vapor deposition and bonding

    Science.gov (United States)

    Zhang, Li; Lee, Kwang Hong; Kadir, Abdul; Wang, Yue; Lee, Kenneth E.; Tan, Chuan Seng; Chua, Soo Jin; Fitzgerald, Eugene A.

    2018-05-01

    Crack-free 200 mm diameter N-polar GaN-on-insulator (GaN-OI) wafers are demonstrated by the transfer of metalorganic chemical vapor deposition (MOCVD)-grown Ga-polar GaN layers from Si(111) wafers onto SiO2/Si(100) wafers. The wafer curvature of the GaN-OI wafers after the removal of the original Si(111) substrate is correlated with the wafer curvature of the starting GaN-on-Si wafers and the voids on the GaN-on-Si surface that evolve into cracks on the GaN-OI wafers. In crack-free GaN-OI wafers, the wafer curvature during the removal of the AlN nucleation layer, AlGaN strain-compensation buffer layers and GaN layers is correlated with the residual stress distribution within individual layers in the GaN-OI wafer.

  14. Wafer-level hermetic vacuum packaging by bonding with a copper-tin thin film sealing ring

    Science.gov (United States)

    Akashi, Teruhisa; Funabashi, Hirofumi; Takagi, Hideki; Omura, Yoshiteru; Hata, Yoshiyuki

    2018-04-01

    A wafer-level hermetic vacuum packaging technology intended for use with MEMS devices was developed based on a copper-tin (CuSn) thin film sealing ring. To allow hermetic packaging, the shear strength of the CuSn thin film bond was improved by optimizing the pretreatment conditions. As a result, an average shear strength of 72.3 MPa was obtained and a cavity that had been hermetically sealed using wafer-level packaging (WLP) maintained its vacuum for 1.84 years. The total pressures in the cavities and the partial pressures of residual gases were directly determined with an ultra-low outgassing residual gas analyzer (RGA) system. Hermeticity was evaluated based on helium leak rates, which were calculated from helium pressures determined with the RGA system. The resulting data showed that a vacuum cavity following 1.84 years storage had a total pressure of 83.1 Pa, contained argon as the main residual gas and exhibited a helium leak rate as low as 1.67  ×  10-17 Pa · m3 s-1, corresponding to an air leak rate of 6.19  ×  10-18 Pa · m3 s-1. The RGA data demonstrate that WLP using a CuSn thin film sealing ring permits ultra-high hermeticity in conjunction with long-term vacuum packaging that is applicable to MEMS devices.

  15. Characteristics of MOSFETs fabricated in silicon-on-insulator material formed by high-dose oxygen ion implantation

    International Nuclear Information System (INIS)

    Lam, H.W.; Pinizzotto, R.F.; Yuan, H.T.; Bellavance, D.W.

    1981-01-01

    By implanting a dose of 6 x 10 17 cm -2 of 32 O 2 + at 300 keV into a silicon wafer, a buried oxide layer is formed. Crystallinity of the silicon layer above the buried oxide layer is maintained by applying a high (>200 0 C) substrate temperature during the ion implantation process. A two-step anneal cycle is found to be adequate to form the insulating buried oxide layer and to repair the implantation damage in the silicon layer on top of the buried oxide. A surface electron mobility as high as 710 cm 2 /Vs has been measured in n-channel MOSFETs fabricated in a 0.5 μm-thick epitaxial layer grown on the buried oxide wafer. A minimum subthreshold current of about 10 pA per micron of channel width at Vsub(DS)=2 V has been measured. (author)

  16. Principle and modelling of Transient Current Technique for interface traps characterization in monolithic pixel detectors obtained by CMOS-compatible wafer bonding

    International Nuclear Information System (INIS)

    Bronuzzi, J.; Mapelli, A.; Moll, M.; Sallese, J.M.

    2016-01-01

    In the framework of monolithic silicon radiation detectors, a fabrication process based on a recently developed silicon wafer bonding technique at low temperature was proposed. Ideally, this new process would enable direct bonding of a read-out electronic chip wafer on a highly resistive silicon substrate wafer, which is expected to present many advantages since it would combine high performance IC's with high sensitive ultra-low doped bulk silicon detectors. But electrical properties of the bonded interface are critical for this kind of application since the mobile charges generated by radiation inside the bonded bulk are expected to transit through the interface in order to be collected by the read-out electronics. In this work, we propose to explore and develop a model for the so-called Transient Current Technique (TCT) to identify the presence of deep traps at the bonded interface. For this purpose, we consider a simple PIN diode reversely biased where the ultra-low doped active region of interest is set in full depletion. In a first step, Synopsys Sentaurus TCAD is used to evaluate the soundness of this technique for interface traps characterization such as it may happen in bonded interfaces. Next, an analytical model is developed in details to give a better insight into the physics behind the TCT for interface layers. Further, this can be used as a simple tool to evidence what are the relevant parameters influencing the TCT signal and to set the basis for preliminary characterizations.

  17. A Numerical Study on Phonon Spectral Contributions to Thermal Conduction in Silicon-on-Insulator Transistor Using Electron-Phonon Interaction Model

    Energy Technology Data Exchange (ETDEWEB)

    Kang, Hyung-sun; Koh, Young Ha; Jin, Jae Sik [Chosun College of Science and Technology, Gwangju (Korea, Republic of)

    2017-06-15

    The aim of this study is to understand the phonon transfer characteristics of a silicon thin film transistor. For this purpose, the Joule heating mechanism was considered through the electron-phonon interaction model whose validation has been done. The phonon transport characteristics were investigated in terms of phonon mean free path for the variations in the device power and silicon layer thickness from 41 nm to 177 nm. The results may be used for developing the thermal design strategy for achieving reliability and efficiency of the silicon-on-insulator (SOI) transistor, further, they will increase the understanding of heat conduction in SOI systems, which are very important in the semiconductor industry and the nano-fabrication technology.

  18. Realization of an ultra-compact polarization beam splitter using asymmetric MMI based on silicon nitride / silicon-on-insulator platform.

    Science.gov (United States)

    Sun, Xiao; Aitchison, J Stewart; Mojahedi, Mo

    2017-04-03

    We have experimentally demonstrated a compact polarization beam splitter (PBS) based on the silicon nitride/silicon-on-insulator platform using the recently proposed augmented-low-index-guiding (ALIG) waveguide structure. The two orthogonal polarizations are split in an asymmetric multimode interference (MMI) section, which was 1.6 μm wide and 4.8 μm long. The device works well over the entire C-band wavelength range and has a measured low insertion loss of less than 1 dB. The polarization extinction ratio at the Bar Port is approximately 17 dB and at the Cross Port is approximately 25 dB. The design of the device is robust and has a good fabrication tolerance.

  19. Determination of the quasi-TE mode (in-plane) graphene linear absorption coefficient via integration with silicon-on-insulator racetrack cavity resonators.

    Science.gov (United States)

    Crowe, Iain F; Clark, Nicholas; Hussein, Siham; Towlson, Brian; Whittaker, Eric; Milosevic, Milan M; Gardes, Frederic Y; Mashanovich, Goran Z; Halsall, Matthew P; Vijayaraghaven, Aravind

    2014-07-28

    We examine the near-IR light-matter interaction for graphene integrated cavity ring resonators based on silicon-on-insulator (SOI) race-track waveguides. Fitting of the cavity resonances from quasi-TE mode transmission spectra reveal the real part of the effective refractive index for graphene, n(eff) = 2.23 ± 0.02 and linear absorption coefficient, α(gTE) = 0.11 ± 0.01dBμm(-1). The evanescent nature of the guided mode coupling to graphene at resonance depends strongly on the height of the graphene above the cavity, which places limits on the cavity length for optical sensing applications.

  20. An integrated optic ethanol vapor sensor based on a silicon-on-insulator microring resonator coated with a porous ZnO film.

    Science.gov (United States)

    Yebo, Nebiyu A; Lommens, Petra; Hens, Zeger; Baets, Roel

    2010-05-24

    Optical structures fabricated on silicon-on-insulator technology provide a convenient platform for the implementation of highly compact, versatile and low cost devices. In this work, we demonstrate the promise of this technology for integrated low power and low cost optical gas sensing. A room temperature ethanol vapor sensor is demonstrated using a ZnO nanoparticle film as a coating on an SOI micro-ring resonator of 5 microm in radius. The local coating on the ring resonators is prepared from colloidal suspensions of ZnO nanoparticles of around 3 nm diameter. The porous nature of the coating provides a large surface area for gas adsorption. The ZnO refractive index change upon vapor adsorption shifts the microring resonance through evanescent field interaction. Ethanol vapor concentrations down to 100 ppm are detected with this sensing configuration and a detection limit below 25 ppm is estimated.

  1. Mechanism of floating body effect mitigation via cutting off source injection in a fully-depleted silicon-on-insulator technology

    International Nuclear Information System (INIS)

    Huang Pengcheng; Chen Shuming; Chen Jianjun

    2016-01-01

    In this paper, the effect of floating body effect (FBE) on a single event transient generation mechanism in fully depleted (FD) silicon-on-insulator (SOI) technology is investigated using three-dimensional technology computer-aided design (3D-TCAD) numerical simulation. The results indicate that the main SET generation mechanism is not carrier drift/diffusion but floating body effect (FBE) whether for positive or negative channel metal oxide semiconductor (PMOS or NMOS). Two stacking layout designs mitigating FBE are investigated as well, and the results indicate that the in-line stacking (IS) layout can mitigate FBE completely and is area penalty saving compared with the conventional stacking layout. (paper)

  2. Analysis and design of tunable wideband microwave photonics phase shifter based on Fabry-Perot cavity and Bragg mirrors in silicon-on-insulator waveguide.

    Science.gov (United States)

    Qu, Pengfei; Zhou, Jingran; Chen, Weiyou; Li, Fumin; Li, Haibin; Liu, Caixia; Ruan, Shengping; Dong, Wei

    2010-04-20

    We designed a microwave (MW) photonics phase shifter, consisting of a Fabry-Perot filter, a phase modulation region (PMR), and distributed Bragg reflectors, in a silicon-on-insulator rib waveguide. The thermo-optics effect was employed to tune the PMR. It was theoretically demonstrated that the linear MW phase shift of 0-2pi could be achieved by a refractive index variation of 0-9.68x10(-3) in an ultrawideband (about 38?GHz-1.9?THz), and the corresponding tuning resolution was about 6.92 degrees / degrees C. The device had a very compact size. It could be easily integrated in silicon optoelectronic chips and expected to be widely used in the high-frequency MW photonics field.

  3. Analysis of OFF-state and ON-state performance in a silicon-on-insulator power MOSFET with a low-k dielectric trench

    International Nuclear Information System (INIS)

    Wang Zhigang; Zhang Bo; Li Zhaoji

    2013-01-01

    A novel silicon-on-insulator (SOI) MOSFET with a variable low-k dielectric trench (LDT MOSFET) is proposed and its performance and characteristics are investigated. The trench in the drift region between drain and source is filled with low-k dielectric to extend the effective drift region. At OFF state, the low-k dielectric trench (LDT) can sustain high voltage and enhance the dielectric field due to the accumulation of ionized charges. At the same time, the vertical dielectric field in the buried oxide can also be enhanced by these ionized charges. Additionally, ON-state analysis of LDT MOSFET demonstrates excellent forward characteristics, such as low gate-to-drain charge density ( 2 ) and a robust safe operating area (0–84 V). (semiconductor devices)

  4. Split-Capacitance and Conductance-Frequency Characteristics of SOI Wafers in Pseudo-MOSFET Configuration

    KAUST Repository

    Pirro, Luca; Diab, Amer El Hajj; Ionica, Irina; Ghibaudo, Gerard; Faraone, Lorenzo; Cristoloveanu, Sorin

    2015-01-01

    Recent experimental results have demonstrated the possibility of characterizing silicon-on-insulator (SOI) wafers through split C-V measurements in the pseudo-MOSFET configuration. This paper analyzes the capacitance and conductance versus frequency characteristics. We discuss the conditions under which it is possible to extract interface trap density in bare SOI wafers. The results indicate, through both measurements and simulations, that the signature due to interface trap density is present in small-area samples, but is masked by the RC response of the channel in regular, large-area ones, making the extraction in standard samples problematic. © 1963-2012 IEEE.

  5. Split-Capacitance and Conductance-Frequency Characteristics of SOI Wafers in Pseudo-MOSFET Configuration

    KAUST Repository

    Pirro, Luca

    2015-09-01

    Recent experimental results have demonstrated the possibility of characterizing silicon-on-insulator (SOI) wafers through split C-V measurements in the pseudo-MOSFET configuration. This paper analyzes the capacitance and conductance versus frequency characteristics. We discuss the conditions under which it is possible to extract interface trap density in bare SOI wafers. The results indicate, through both measurements and simulations, that the signature due to interface trap density is present in small-area samples, but is masked by the RC response of the channel in regular, large-area ones, making the extraction in standard samples problematic. © 1963-2012 IEEE.

  6. Nature of bonding forces between two hydrogen-passivated silicon wafers

    DEFF Research Database (Denmark)

    Stokbro, Kurt; Nielsen, E.; Hult, E.

    1998-01-01

    The nature and strength of the bonding forces between two II-passivated Si surfaces are studied with the density-functional theory, using an approach based on recent theoretical advances in understanding of van der Waals forces between two surfaces. Contrary to previous suggestions of van der Waals...

  7. Characterizing SOI Wafers By Use Of AOTF-PHI

    Science.gov (United States)

    Cheng, Li-Jen; Li, Guann-Pyng; Zang, Deyu

    1995-01-01

    Developmental nondestructive method of characterizing layers of silicon-on-insulator (SOI) wafer involves combination of polarimetric hyperspectral imaging by use of acousto-optical tunable filters (AOTF-PHI) and computational resources for extracting pertinent data on SOI wafers from polarimetric hyperspectral images. Offers high spectral resolution and both ease and rapidity of optical-wavelength tuning. Further efforts to implement all of processing of polarimetric spectral image data in special-purpose hardware for sake of procesing speed. Enables characterization of SOI wafers in real time for online monitoring and adjustment of production. Also accelerates application of AOTF-PHI to other applications in which need for high-resolution spectral imaging, both with and without polarimetry.

  8. Material size effects on crack growth along patterned wafer-level Cu–Cu bonds

    DEFF Research Database (Denmark)

    Tvergaard, Viggo; Niordson, Christian Frithiof; Hutchinson, John W.

    2013-01-01

    together. Crack growth along the bond interface is here studied numerically using finite element analyses. The experiments have shown that plasticity in the Cu films makes a major contribution to the macroscopic interface toughness. To account for the size dependence of the plastic flow a strain gradient...... plasticity model is applied here for the metal. A cohesive zone model is applied to represent the crack growth along the bond between the two Cu films. This cohesive zone model incorporates the effect of higher order stresses in the continuum, such that the higher order tractions on the crack faces decay...... the toughness peak and the subsequent plateau level are highly sensitive to the value of the characteristic material length. A small material length, relative to the thickness of the Cu film, gives high toughness whereas a length comparable to the film thickness gives much reduced crack growth resistance...

  9. Principle and modelling of Transient Current Technique for interface traps characterization in monolithic pixel detectors obtained by CMOS-compatible wafer bonding

    CERN Document Server

    Bronuzzi, J.; Moll, M.; Sallese, J.M.

    2016-01-01

    In the framework of monolithic silicon radiation detectors, a fabrication process based on a recently developed silicon wafer bonding technique at low temperature was proposed. Ideally, this new process would enable direct bonding of a read-out electronic chip wafer on a highly resistive silicon substrate wafer, which is expected to present many advantages since it would combine high performance IC's with high sensitive ultra-low doped bulk silicon detectors. But electrical properties of the bonded interface are critical for this kind of application since the mobile charges generated by radiation inside the bonded bulk are expected to transit through the interface in order to be collected by the read-out electronics. In this work, we propose to explore and develop a model for the so-called Transient Current Technique (TCT) to identify the presence of deep traps at the bonded interface. For this purpose, we consider a simple PIN diode reversely biased where the ultra-low doped active region of interest is set ...

  10. Eutectic-based wafer-level-packaging technique for piezoresistive MEMS accelerometers and bond characterization using molecular dynamics simulations

    Science.gov (United States)

    Aono, T.; Kazama, A.; Okada, R.; Iwasaki, T.; Isono, Y.

    2018-03-01

    We developed a eutectic-based wafer-level-packaging (WLP) technique for piezoresistive micro-electromechanical systems (MEMS) accelerometers on the basis of molecular dynamics analyses and shear tests of WLP accelerometers. The bonding conditions were experimentally and analytically determined to realize a high shear strength without solder material atoms diffusing to adhesion layers. Molecular dynamics (MD) simulations and energy dispersive x-ray (EDX) spectrometry done after the shear tests clarified the eutectic reaction of the solder materials used in this research. Energy relaxation calculations in MD showed that the diffusion of solder material atoms into the adhesive layer was promoted at a higher temperature. Tensile creep MD simulations also suggested that the local potential energy in a solder material model determined the fracture points of the model. These numerical results were supported by the shear tests and EDX analyses for WLP accelerometers. Consequently, a bonding load of 9.8 kN and temperature of 300 °C were found to be rational conditions because the shear strength was sufficient to endure the polishing process after the WLP process and there was little diffusion of solder material atoms to the adhesion layer. Also, eutectic-bonding-based WLP was effective for controlling the attenuation of the accelerometers by determining the thickness of electroplated solder materials that played the role of a cavity between the accelerometers and lids. If the gap distance between the two was less than 6.2 µm, the signal gains for x- and z-axis acceleration were less than 20 dB even at the resonance frequency due to air-damping.

  11. High-κ Al{sub 2}O{sub 3} material in low temperature wafer-level bonding for 3D integration application

    Energy Technology Data Exchange (ETDEWEB)

    Fan, J., E-mail: fanji@hust.edu.cn; Tu, L. C. [MOE Key Laboratory of Fundamental Physical Quantities Measurement, School of Physics, Huazhong University of Science and Technology, Wuhan 430074 (China); Tan, C. S. [School of Electrical and Electronics Engineering, Nanyang Technological University, 50 Nanyang Avenue, Singapore 639798 (Singapore)

    2014-03-15

    This work systematically investigated a high-κ Al{sub 2}O{sub 3} material for low temperature wafer-level bonding for potential applications in 3D microsystems. A clean Si wafer with an Al{sub 2}O{sub 3} layer thickness of 50 nm was applied as our experimental approach. Bonding was initiated in a clean room ambient after surface activation, followed by annealing under inert ambient conditions at 300 °C for 3 h. The investigation consisted of three parts: a mechanical support study using the four-point bending method, hermeticity measurements using the helium bomb test, and thermal conductivity analysis for potential heterogeneous bonding. Compared with samples bonded using a conventional oxide bonding material (SiO{sub 2}), a higher interfacial adhesion energy (∼11.93 J/m{sup 2}) and a lower helium leak rate (∼6.84 × 10{sup −10} atm.cm{sup 3}/sec) were detected for samples bonded using Al{sub 2}O{sub 3}. More importantly, due to the excellent thermal conductivity performance of Al{sub 2}O{sub 3}, this technology can be used in heterogeneous direct bonding, which has potential applications for enhancing the performance of Si photonic integrated devices.

  12. Ultra-low coupling loss fully-etched apodized grating coupler with bonded metal mirror

    DEFF Research Database (Denmark)

    Ding, Yunhong; Peucheret, Christophe; Ou, Haiyan

    2014-01-01

    A fully etched apodized grating coupler with bonded metal mirror is designed and demonstrated on the silicon-on-insulator platform, showing an ultra-low coupling loss of only 1.25 dB with 3 dB bandwidth of 69 nm.......A fully etched apodized grating coupler with bonded metal mirror is designed and demonstrated on the silicon-on-insulator platform, showing an ultra-low coupling loss of only 1.25 dB with 3 dB bandwidth of 69 nm....

  13. Barrier reduction via implementation of InGaN interlayer in wafer-bonded current aperture vertical electron transistors consisting of InGaAs channel and N-polar GaN drain

    International Nuclear Information System (INIS)

    Kim, Jeonghee; Laurent, Matthew A.; Li, Haoran; Lal, Shalini; Mishra, Umesh K.

    2015-01-01

    This letter reports the influence of the added InGaN interlayer on reducing the inherent interfacial barrier and hence improving the electrical characteristics of wafer-bonded current aperture vertical electron transistors consisting of an InGaAs channel and N-polar GaN drain. The current-voltage characteristics of the transistors show that the implementation of N-polar InGaN interlayer effectively reduces the barrier to electron transport across the wafer-bonded interface most likely due to its polarization induced downward band bending, which increases the electron tunneling probability. Fully functional wafer-bonded transistors with nearly 600 mA/mm of drain current at V GS  = 0 V and L go  = 2 μm have been achieved, and thus demonstrate the feasibility of using wafer-bonded heterostructures for applications that require active carrier transport through both materials

  14. 110 GHz hybrid mode-locked fiber laser with enhanced extinction ratio based on nonlinear silicon-on-insulator micro-ring-resonator (SOI MRR)

    International Nuclear Information System (INIS)

    Liu, Yang; Hsu, Yung; Chow, Chi-Wai; Yang, Ling-Gang; Lai, Yin-Chieh; Yeh, Chien-Hung; Tsang, Hon-Ki

    2016-01-01

    We propose and experimentally demonstrate a new 110 GHz high-repetition-rate hybrid mode-locked fiber laser using a silicon-on-insulator microring-resonator (SOI MRR) acting as the optical nonlinear element and optical comb filter simultaneously. By incorporating a phase modulator (PM) that is electrically driven at a fraction of the harmonic frequency, an enhanced extinction ratio (ER) of the optical pulses can be produced. The ER of the optical pulse train increases from 3 dB to 10 dB. As the PM is only electrically driven by the signal at a fraction of the harmonic frequency, in this case 22 GHz (110 GHz/5 GHz), a low bandwidth PM and driving circuit can be used. The mode-locked pulse width and the 3 dB spectral bandwidth of the proposed mode-locked fiber laser are measured, showing that the optical pulses are nearly transform limited. Moreover, stability evaluation for an hour is performed, showing that the proposed laser can achieve stable mode-locking without the need for optical feedback or any other stabilization mechanism. (letter)

  15. Photonic crystal ring resonator-based four-channel dense wavelength division multiplexing demultiplexer on silicon on insulator platform: design and analysis

    Science.gov (United States)

    Sreenivasulu, Tupakula; Bhowmick, Kaustav; Samad, Shafeek A.; Yadunath, Thamerassery Illam R.; Badrinarayana, Tarimala; Hegde, Gopalkrishna; Srinivas, Talabattula

    2018-04-01

    A micro/nanofabrication feasible compact photonic crystal (PC) ring-resonator-based channel drop filter has been designed and analyzed for operation in C and L bands of communication window. The four-channel demultiplexer consists of ring resonators of holes in two-dimensional PC slab. The proposed assembly design of dense wavelength division multiplexing setup is shown to achieve optimal quality factor, without altering the lattice parameters or resonator size or inclusion of scattering holes. Transmission characteristics are analyzed using the three-dimensional finite-difference time-domain simulation approach. The radiation loss of the ring resonator was minimized by forced cancelation of radiation fields by fine-tuning the air holes inside the ring resonator. An average cross talk of -34 dB has been achieved between the adjacent channels maintaining an average quality factor of 5000. Demultiplexing is achieved by engineering only the air holes inside the ring, which makes it a simple and tolerant design from the fabrication perspective. Also, the device footprint of 500 μm2 on silicon on insulator platform makes it easy to fabricate the device using e-beam lithography technique.

  16. Proton induced single event upset cross section prediction for 0.15 μm six-transistor (6T) silicon-on-insulator static random access memories

    International Nuclear Information System (INIS)

    Li Lei; Zhou Wanting; Liu Huihua

    2012-01-01

    In this paper, an efficient physics-based method to estimate the saturated proton upset cross section for six-transistor (6T) silicon-on-insulator (SOI) static random access memory (SRAM) cells using layout and technology parameters is proposed. This method calculates the effects of radiation based on device physics. The simple method handles the problem with ease by SPICE simulations, which can be divided into two stages. At first, it uses a standard SPICE program to predict the cross section for recoiling heavy ions with linear energy transfer (LET) of 14 MeV-cm 2 /mg. Then, the predicted cross section for recoiling heavy ions with LET of 14 MeV-cm 2 /mg is used to estimate the saturated proton upset cross section for 6T SOI SRAM cells with a simple model. The calculated proton induced upset cross section based on this method is in good agreement with the test results of 6T SOI SRAM cells processed using 0.15 μm technology. (author)

  17. Method to improve commercial bonded SOI material

    Science.gov (United States)

    Maris, Humphrey John; Sadana, Devendra Kumar

    2000-07-11

    A method of improving the bonding characteristics of a previously bonded silicon on insulator (SOI) structure is provided. The improvement in the bonding characteristics is achieved in the present invention by, optionally, forming an oxide cap layer on the silicon surface of the bonded SOI structure and then annealing either the uncapped or oxide capped structure in a slightly oxidizing ambient at temperatures greater than 1200.degree. C. Also provided herein is a method for detecting the bonding characteristics of previously bonded SOI structures. According to this aspect of the present invention, a pico-second laser pulse technique is employed to determine the bonding imperfections of previously bonded SOI structures.

  18. Ultra-low power high temperature and radiation hard complementary metal-oxide-semiconductor (CMOS) silicon-on-insulator (SOI) voltage reference.

    Science.gov (United States)

    Boufouss, El Hafed; Francis, Laurent A; Kilchytska, Valeriya; Gérard, Pierre; Simon, Pascal; Flandre, Denis

    2013-12-13

    This paper presents an ultra-low power CMOS voltage reference circuit which is robust under biomedical extreme conditions, such as high temperature and high total ionized dose (TID) radiation. To achieve such performances, the voltage reference is designed in a suitable 130 nm Silicon-on-Insulator (SOI) industrial technology and is optimized to work in the subthreshold regime of the transistors. The design simulations have been performed over the temperature range of -40-200 °C and for different process corners. Robustness to radiation was simulated using custom model parameters including TID effects, such as mobilities and threshold voltages degradation. The proposed circuit has been tested up to high total radiation dose, i.e., 1 Mrad (Si) performed at three different temperatures (room temperature, 100 °C and 200 °C). The maximum drift of the reference voltage V(REF) depends on the considered temperature and on radiation dose; however, it remains lower than 10% of the mean value of 1.5 V. The typical power dissipation at 2.5 V supply voltage is about 20 μW at room temperature and only 75 μW at a high temperature of 200 °C. To understand the effects caused by the combination of high total ionizing dose and temperature on such voltage reference, the threshold voltages of the used SOI MOSFETs were extracted under different conditions. The evolution of V(REF) and power consumption with temperature and radiation dose can then be explained in terms of the different balance between fixed oxide charge and interface states build-up. The total occupied area including pad-ring is less than 0.09 mm2.

  19. 1.3 μm wavelength vertical cavity surface emitting laser fabricated by orientation-mismatched wafer bonding: A prospect for polarization control

    Science.gov (United States)

    Okuno, Yae L.; Geske, Jon; Gan, Kian-Giap; Chiu, Yi-Jen; DenBaars, Steven P.; Bowers, John E.

    2003-04-01

    We propose and demonstrate a long-wavelength vertical cavity surface emitting laser (VCSEL) which consists of a (311)B InP-based active region and (100) GaAs-based distributed Bragg reflectors (DBRs), with an aim to control the in-plane polarization of output power. Crystal growth on (311)B InP substrates was performed under low-migration conditions to achieve good crystalline quality. The VCSEL was fabricated by wafer bonding, which enables us to combine different materials regardless of their lattice and orientation mismatch without degrading their quality. The VCSEL was polarized with a power extinction ratio of 31 dB.

  20. Aberration-corrected transmission electron microscopy analyses of GaAs/Si interfaces in wafer-bonded multi-junction solar cells

    Energy Technology Data Exchange (ETDEWEB)

    Häussler, Dietrich [Institute for Materials Science, Christian-Albrechts-University Kiel, Kaiserstraße 2, 24143 Kiel (Germany); Houben, Lothar [Ernst Ruska-Centre for Microscopy and Spectroscopy with Electrons, Research Centre Juelich GmbH, 52425 Juelich (Germany); Essig, Stephanie [Fraunhofer Institute for Solar Energy Systems ISE, Heidenhofstraße 2, 79110 Freiburg (Germany); Kurttepeli, Mert [Institute for Materials Science, Christian-Albrechts-University Kiel, Kaiserstraße 2, 24143 Kiel (Germany); Dimroth, Frank [Fraunhofer Institute for Solar Energy Systems ISE, Heidenhofstraße 2, 79110 Freiburg (Germany); Dunin-Borkowski, Rafal E. [Ernst Ruska-Centre for Microscopy and Spectroscopy with Electrons, Research Centre Juelich GmbH, 52425 Juelich (Germany); Jäger, Wolfgang, E-mail: wolfgang.jaeger@tf.uni-kiel.de [Institute for Materials Science, Christian-Albrechts-University Kiel, Kaiserstraße 2, 24143 Kiel (Germany)

    2013-11-15

    Aberration-corrected scanning transmission electron microscopy (STEM) and electron energy loss spectroscopy (EELS) investigations have been applied to investigate the structure and composition fluctuations near interfaces in wafer-bonded multi-junction solar cells. Multi-junction solar cells are of particular interest since efficiencies well above 40% have been obtained for concentrator solar cells which are based on III-V compound semiconductors. In this methodologically oriented investigation, we explore the potential of combining aberration-corrected high-angle annular dark-field STEM imaging (HAADF-STEM) with spectroscopic techniques, such as EELS and energy-dispersive X-ray spectroscopy (EDXS), and with high-resolution transmission electron microscopy (HR-TEM), in order to analyze the effects of fast atom beam (FAB) and ion beam bombardment (IB) activation treatments on the structure and composition of bonding interfaces of wafer-bonded solar cells on Si substrates. Investigations using STEM/EELS are able to measure quantitatively and with high precision the widths and the fluctuations in element distributions within amorphous interface layers of nanometer extensions, including those of light elements. Such measurements allow the control of the activation treatments and thus support assessing electrical conductivity phenomena connected with impurity and dopant distributions near interfaces for optimized performance of the solar cells. - Highlights: • Aberration-corrected TEM and EELS reveal structural and elemental profiles across GaAs/Si bond interfaces in wafer-bonded GaInP/GaAs/Si - multi-junction solar cells. • Fluctuations in elemental concentration in nanometer-thick amorphous interface layers, including the disrubutions of light elements, are measured using EELS. • The projected widths of the interface layers are determined on the atomic scale from STEM-HAADF measurements. • The effects of atom and ion beam activation treatment on the bonding

  1. Electrostatic bonding of thin (cycle sine 3 mil) 7070 cover glass to Ta2O5 AR-coated thin (cycle sine 2 mil) silicon wafers and solar cells

    Science.gov (United States)

    Egelkrout, D. W.

    1981-01-01

    Electrostatic bonding of thin cover glass to thin solar cells was researched. Silicon solar cells, wafers, and Corning 7070 glass of from about 0.002" to about 0.003" in thickness were used in the investigation to establish optimum parameters for producing mechanically acceptable bonds while minimizing thermal stresses and resultant solar cell electrical parameter degradation.

  2. High-density plasma-induced etch damage of wafer-bonded AlGaInP/mirror/Si light-emitting diodes

    CERN Document Server

    Wuu, D S; Huang, S H; Chung, C R

    2002-01-01

    Dry etch of wafer-bonded AlGaInP/mirror/Si light-emitting diodes (LEDs) with planar electrodes was performed by high-density plasma using an inductively coupled plasma (ICP) etcher. The etching characteristics were investigated by varying process parameters such as Cl sub 2 /N sub 2 gas combination, chamber pressure, ICP power and substrate-bias power. The corresponding plasma properties (ion flux and dc bias), in situ measured by a Langmuir probe, show a strong relationship to the etch results. With a moderate etch rate of 1.3 mu m/min, a near vertical and smooth sidewall profile can be achieved under a Cl sub 2 /(Cl sub 2 +N sub 2) gas mixture of 0.5, ICP power of 800 W, substrate-bias power of 100 W, and chamber pressure of 0.67 Pa. Quantitative analysis of the plasma-induced damage was attempted to provide a means to study the mechanism of leakage current and brightness with various dc bias voltages (-110 to -328 V) and plasma duration (3-5 min) on the wafer-bonded LEDs. It is found that the reverse leaka...

  3. Temperature-dependent interface characteristic of silicon wafer bonding based on an amorphous germanium layer deposited by DC-magnetron sputtering

    Science.gov (United States)

    Ke, Shaoying; Lin, Shaoming; Ye, Yujie; Mao, Danfeng; Huang, Wei; Xu, Jianfang; Li, Cheng; Chen, Songyan

    2018-03-01

    We report a near-bubble-free low-temperature silicon (Si) wafer bonding with a thin amorphous Ge (a-Ge) intermediate layer. The DC-magnetron-sputtered a-Ge film on Si is demonstrated to be extremely flat (RMS = 0.28 nm) and hydrophilic (contact angle = 3°). The effect of the post-annealing temperature on the surface morphology and crystallinity of a-Ge film at the bonded interface is systematically identified. The relationship among the bubble density, annealing temperature, and crystallinity of a-Ge film is also clearly clarified. The crystallization of a-Ge film firstly appears at the bubble region. More interesting feature is that the crystallization starts from the center of the bubbles and sprawls to the bubble edge gradually. The H2 by-product is finally absorbed by intermediate Ge layer with crystalline phase after post annealing. Moreover, the whole a-Ge film out of the bubble totally crystallizes when the annealing time increases. This Ge integration at the bubble region leads to the decrease of the bubble density, which in turn increases the bonding strength.

  4. Computer simulation for the formation of the insulator layer of silicon-on-insulator devices by N sup + and O sup + Co-implantation

    CERN Document Server

    Lin Qing; Xie Xin Yun; Lin Chenglu; Liu Xiang Hua

    2002-01-01

    A buried sandwiched layer consisting of silicon dioxide (upper part), silicon oxynitride (medium part) and silicon nitride (lower part) is formed by N sup + and O sup + co-implantation in silicon wafers at a constant temperature of 550 degree C. The microstructure is performed by cross-sectional transmission electron microscopy. To predict the quality of the buried sandwiched layer, the authors study the computer simulation for the formation of the SIMON (separated by implantation of oxygen and nitrogen) structure. The simulation program for SIMOX (separated by implantation of oxygen) is improved in order to be applied in O sup + and N sup + co-implantation on the basis of different formation mechanism between SIMOX and SIMNI (separated by implantation of nitrogen) structures. There is a good agreement between experiment and simulation results verifying the theoretical model and presumption in the program

  5. Wafer level packaging of MEMS

    International Nuclear Information System (INIS)

    Esashi, Masayoshi

    2008-01-01

    Wafer level packaging plays many important roles for MEMS (micro electro mechanical systems), including cost, yield and reliability. MEMS structures on silicon chips are encapsulated between bonded wafers or by surface micromachining, and electrical interconnections are made from the cavity. Bonding at the interface, such as glass–Si anodic bonding and metal-to-metal bonding, requires electrical interconnection through the lid vias in many cases. On the other hand, lateral electrical interconnections on the surface of the chip are used for bonding with intermediate melting materials, such as low melting point glass and solder. The cavity formed by surface micromachining is made using sacrificial etching, and the openings needed for the sacrificial etching are plugged using deposition sealing methods. Vacuum packaging methods and the structures for electrical feedthrough for the interconnection are discussed in this review. (topical review)

  6. Investigation of piezoresistive effect in p-channel metal–oxide–semiconductor field-effect transistors fabricated on circular silicon-on-insulator diaphragms using cost-effective minimal-fab process

    Science.gov (United States)

    Liu, Yongxun; Tanaka, Hiroyuki; Umeyama, Norio; Koga, Kazuhiro; Khumpuang, Sommawan; Nagao, Masayoshi; Matsukawa, Takashi; Hara, Shiro

    2018-06-01

    P-channel metal–oxide–semiconductor field-effect transistors (PMOSFETs) with the 〈110〉 or 〈100〉 channel direction have been successfully fabricated on circular silicon-on-insulator (SOI) diaphragms using a cost-effective minimal-fab process, and their electrical characteristics have been systematically investigated before and after the SOI diaphragm formation. It was found that almost the same subthreshold slope (S-slope) and threshold voltage (V t) are observed in the fabricated PMOSFETs before and after the SOI diaphragm formation, and they are independent of the channel direction. On the other hand, significant variations in drain current were observed in the fabricated PMOSFETs with the 〈110〉 channel direction after the SOI diaphragm formation owing to the residual mechanical stress-induced piezoresistive effect. It was also confirmed that electrical characteristics of the fabricated PMOSFETs with the 〈100〉 channel direction are almost the same before and after the SOI diaphragm formation, i.e., not sensitive to the mechanical stress. Moreover, the drain current variations at different directions of mechanical stress and current flow were systematically investigated and discussed.

  7. Bondability of processed glass wafers

    NARCIS (Netherlands)

    Pandraud, G.; Gui, C.; Lambeck, Paul; Pigeon, F.; Parriaux, O.; Gorecki, Christophe

    1999-01-01

    The mechanism of direct bonding at room temperature has been attributed to the short range inter-molecular and inter-atomic attraction forces, such as Van der Waals forces. Consequently, the wafer surface smoothness becomes one of the most critical parameters in this process. High surface roughness

  8. Si-nanowire-based multistage delayed Mach-Zehnder interferometer optical MUX/DeMUX fabricated by an ArF-immersion lithography process on a 300 mm SOI wafer.

    Science.gov (United States)

    Jeong, Seok-Hwan; Shimura, Daisuke; Simoyama, Takasi; Horikawa, Tsuyoshi; Tanaka, Yu; Morito, Ken

    2014-07-01

    We report good phase controllability and high production yield in Si-nanowire-based multistage delayed Mach-Zehnder interferometer-type optical multiplexers/demultiplexers (MUX/DeMUX) fabricated by an ArF-immersion lithography process on a 300 mm silicon-on-insulator (SOI) wafer. Three kinds of devices fabricated in this work exhibit clear 1×4 Ch wavelength filtering operations for various optical frequency spacing. These results are promising for their applications in high-density wavelength division multiplexing-based optical interconnects.

  9. Fabrication of core-shell nanostructures via silicon on insulator dewetting and germanium condensation: towards a strain tuning method for SiGe-based heterostructures in a three-dimensional geometry.

    Science.gov (United States)

    Naffouti, Meher; David, Thomas; Benkouider, Abdelmalek; Favre, Luc; Cabie, Martiane; Ronda, Antoine; Berbezier, Isabelle; Abbarchi, Marco

    2016-07-29

    We report on a novel method for the implementation of core-shell SiGe-based nanocrystals combining silicon on insulator dewetting in a molecular beam epitaxy reactor with an ex situ Ge condensation process. With an in situ two-step process (annealing and Ge deposition) we produce two families of islands on the same sample: Si-rich, formed during the first step and, all around them, Ge-rich formed after Ge deposition. By increasing the amount of Ge deposited on the annealed samples from 0 to 18 monolayers, the islands' shape in the Si-rich zones can be tuned from elongated and flat to more symmetric and with a larger vertical aspect ratio. At the same time, the spatial extension of the Ge-rich zones is progressively increased as well as the Ge content in the islands. Further processing by ex situ rapid thermal oxidation results in the formation of a core-shell composition profile in both Si and Ge-rich zones with atomically sharp heterointerfaces. The Ge condensation induces a Ge enrichment of the islands' shell of up to 50% while keeping a pure Si core in the Si-rich zones and a ∼25% SiGe alloy in the Ge-rich ones. The large lattice mismatch between core and shell, the absence of dislocations and the islands' monocrystalline nature render this novel class of nanostructures a promising device platform for strain-based band-gap engineering. Finally, this method can be used for the implementation of ultralarge scale meta-surfaces with dielectric Mie resonators for light manipulation at the nanoscale.

  10. 2-D Row-Column CMUT Arrays with an Open-Grid Support Structure

    DEFF Research Database (Denmark)

    Christiansen, Thomas Lehrmann; Dahl-Petersen, Christian; Jensen, Jørgen Arendt

    2013-01-01

    Fabrication and characterization of 64 + 64 2-D row-column addressed CMUT arrays with 250 μm element pitch and 4.4 MHz center frequency in air incorporating a new design approach is presented. The arrays are comprised of two wafer bonded, structured silicon-on-insulator wafers featuring an opengr...

  11. Wafer-Level Membrane-Transfer Process for Fabricating MEMS

    Science.gov (United States)

    Yang, Eui-Hyeok; Wiberg, Dean

    2003-01-01

    A process for transferring an entire wafer-level micromachined silicon structure for mating with and bonding to another such structure has been devised. This process is intended especially for use in wafer-level integration of microelectromechanical systems (MEMS) that have been fabricated on dissimilar substrates. Unlike in some older membrane-transfer processes, there is no use of wax or epoxy during transfer. In this process, the substrate of a wafer-level structure to be transferred serves as a carrier, and is etched away once the transfer has been completed. Another important feature of this process is that two electrodes constitutes an electrostatic actuator array. An SOI wafer and a silicon wafer (see Figure 1) are used as the carrier and electrode wafers, respectively. After oxidation, both wafers are patterned and etched to define a corrugation profile and electrode array, respectively. The polysilicon layer is deposited on the SOI wafer. The carrier wafer is bonded to the electrode wafer by using evaporated indium bumps. The piston pressure of 4 kPa is applied at 156 C in a vacuum chamber to provide hermetic sealing. The substrate of the SOI wafer is etched in a 25 weight percent TMAH bath at 80 C. The exposed buried oxide is then removed by using 49 percent HF droplets after an oxygen plasma ashing. The SOI top silicon layer is etched away by using an SF6 plasma to define the corrugation profile, followed by the HF droplet etching of the remaining oxide. The SF6 plasma with a shadow mask selectively etches the polysilicon membrane, if the transferred membrane structure needs to be patterned. Electrostatic actuators with various electrode gaps have been fabricated by this transfer technique. The gap between the transferred membrane and electrode substrate is very uniform ( 0.1 m across a wafer diameter of 100 mm, provided by optimizing the bonding control). Figure 2 depicts the finished product.

  12. Application of the O-lattice theory for the reconstruction of the high-angle near 90° tilt Si(1 1 0)/(0 0 1) boundary created by wafer bonding

    International Nuclear Information System (INIS)

    Cherkashin, N.; Kononchuk, O.; Reboh, S.; Hÿtch, M.

    2012-01-01

    This work presents an experimental and theoretical identification of defects and morphologies of a high-angle near-90° tilt Si (1 ¯ 10)//(001) boundary created by direct wafer bonding. Two samples with different twist misorientations, between the (1 ¯ 10) layer and the (0 0 1) substrate, were studied using conventional transmission electron microscopy (TEM) and geometric phase analysis of high-resolution TEM images. The O-lattice theory was used for atom reconstruction of the interface along the [11 ¯ 0] sub //[001] lay direction. It is demonstrated that to preserve covalent bonding across the interface, it should consist of {11 ¯ 1} sub,lay //{1 ¯ 12} lay,sub facets intersected by maximum of six {11 ¯ 1} lay,sub planes with three 90° Shockley dislocations per facet. It is shown that a particular atom reconstruction is needed at transition points from one facet to another. The presence or absence of deviation from exact 90° tilt of the layer with respect to the substrate is shown to be related directly to the undulations of the interface. It is demonstrated that the latter has an influence on the Burgers vector of the dislocations adjusting in-plane twist misorientation. A general model for cubic face-centered materials for an arbitrary 〈1 1 0〉 sub,lay tilt interface is proposed, which predicts the net Burgers vector and the spacing between dislocations necessary to realize transition from the lattice of the substrate (layer) to the layer (substrate).

  13. HARM processing techniques for MEMS and MOEMS devices using bonded SOI substrates and DRIE

    Science.gov (United States)

    Gormley, Colin; Boyle, Anne; Srigengan, Viji; Blackstone, Scott C.

    2000-08-01

    Silicon-on-Insulator (SOI) MEMS devices (1) are rapidly gaining popularity in realizing numerous solutions for MEMS, especially in the optical and inertia application fields. BCO recently developed a DRIE trench etch, utilizing the Bosch process, and refill process for high voltage dielectric isolation integrated circuits on thick SOI substrates. In this paper we present our most recently developed DRIE processes for MEMS and MOEMS devices. These advanced etch techniques are initially described and their integration with silicon bonding demonstrated. This has enabled process flows that are currently being utilized to develop optical router and filter products for fiber optics telecommunications and high precision accelerometers.

  14. Wafer-Level Vacuum Packaging of Smart Sensors

    Directory of Open Access Journals (Sweden)

    Allan Hilton

    2016-10-01

    Full Text Available The reach and impact of the Internet of Things will depend on the availability of low-cost, smart sensors—“low cost” for ubiquitous presence, and “smart” for connectivity and autonomy. By using wafer-level processes not only for the smart sensor fabrication and integration, but also for packaging, we can further greatly reduce the cost of sensor components and systems as well as further decrease their size and weight. This paper reviews the state-of-the-art in the wafer-level vacuum packaging technology of smart sensors. We describe the processes needed to create the wafer-scale vacuum microchambers, focusing on approaches that involve metal seals and that are compatible with the thermal budget of complementary metal-oxide semiconductor (CMOS integrated circuits. We review choices of seal materials and structures that are available to a device designer, and present techniques used for the fabrication of metal seals on device and window wafers. We also analyze the deposition and activation of thin film getters needed to maintain vacuum in the ultra-small chambers, and the wafer-to-wafer bonding processes that form the hermetic seal. We discuss inherent trade-offs and challenges of each seal material set and the corresponding bonding processes. Finally, we identify areas for further research that could help broaden implementations of the wafer-level vacuum packaging technology.

  15. Wafer-Level Vacuum Packaging of Smart Sensors.

    Science.gov (United States)

    Hilton, Allan; Temple, Dorota S

    2016-10-31

    The reach and impact of the Internet of Things will depend on the availability of low-cost, smart sensors-"low cost" for ubiquitous presence, and "smart" for connectivity and autonomy. By using wafer-level processes not only for the smart sensor fabrication and integration, but also for packaging, we can further greatly reduce the cost of sensor components and systems as well as further decrease their size and weight. This paper reviews the state-of-the-art in the wafer-level vacuum packaging technology of smart sensors. We describe the processes needed to create the wafer-scale vacuum microchambers, focusing on approaches that involve metal seals and that are compatible with the thermal budget of complementary metal-oxide semiconductor (CMOS) integrated circuits. We review choices of seal materials and structures that are available to a device designer, and present techniques used for the fabrication of metal seals on device and window wafers. We also analyze the deposition and activation of thin film getters needed to maintain vacuum in the ultra-small chambers, and the wafer-to-wafer bonding processes that form the hermetic seal. We discuss inherent trade-offs and challenges of each seal material set and the corresponding bonding processes. Finally, we identify areas for further research that could help broaden implementations of the wafer-level vacuum packaging technology.

  16. High-throughput characterization of stresses in thin film materials libraries using Si cantilever array wafers and digital holographic microscopy.

    Science.gov (United States)

    Lai, Y W; Hamann, S; Ehmann, M; Ludwig, A

    2011-06-01

    We report the development of an advanced high-throughput stress characterization method for thin film materials libraries sputter-deposited on micro-machined cantilever arrays consisting of around 1500 cantilevers on 4-inch silicon-on-insulator wafers. A low-cost custom-designed digital holographic microscope (DHM) is employed to simultaneously monitor the thin film thickness, the surface topography and the curvature of each of the cantilevers before and after deposition. The variation in stress state across the thin film materials library is then calculated by Stoney's equation based on the obtained radii of curvature of the cantilevers and film thicknesses. DHM with nanometer-scale out-of-plane resolution allows stress measurements in a wide range, at least from several MPa to several GPa. By using an automatic x-y translation stage, the local stresses within a 4-inch materials library are mapped with high accuracy within 10 min. The speed of measurement is greatly improved compared with the prior laser scanning approach that needs more than an hour of measuring time. A high-throughput stress measurement of an as-deposited Fe-Pd-W materials library was evaluated for demonstration. The fast characterization method is expected to accelerate the development of (functional) thin films, e.g., (magnetic) shape memory materials, whose functionality is greatly stress dependent. © 2011 American Institute of Physics

  17. Launching of multi-project wafer runs in ePIXfab with micron-scale silicon rib waveguide technology

    Science.gov (United States)

    Aalto, Timo; Cherchi, Matteo; Harjanne, Mikko; Ylinen, Sami; Kapulainen, Markku; Vehmas, Tapani

    2014-03-01

    Silicon photonics is a rapidly growing R&D field where universities, institutes and companies are all involved and the business expectations for the next few years are high. One of the key enabling elements that led to the present success of silicon photonics is ePIXfab. It is a consortium of institutes that has together offered multi-project wafer (MPW) runs, packaging services, training, and feasibility studies. These services have significantly lowered the barrier of various research groups and companies to start developing silicon photonics. Until now the MPW services have been offered by the ePIXfab partners IMEC, CEA-Leti and IHP, which all use CMOS-type silicon photonics technology with a typical silicon-on-insulator (SOI) waveguide thickness of 220 nm. In November 2013 this MPW offering was expanded by the ePIXfab partner VTT that opened the access to its 3 μm SOI waveguide platform via ePIXfab MPW runs. This technology platform is complementary to the mainstream silicon photonics technology (220 nm) and it offers such benefits as very low losses, small polarization dependency, ultrabroadband operation and low starting costs

  18. Graphene photodetectors with a bandwidth  >76 GHz fabricated in a 6″ wafer process line

    Science.gov (United States)

    Schall, Daniel; Porschatis, Caroline; Otto, Martin; Neumaier, Daniel

    2017-03-01

    In recent years, the data traffic has grown exponentially and the forecasts indicate a huge market that could be addressed by communication infrastructure and service providers. However, the processing capacity, space, and energy consumption of the available technology is a serious bottleneck for the exploitation of these markets. Chip-integrated optical communication systems hold the promise of significantly improving these issues related to the current technology. At the moment, the answer to the question which material is best suited for ultrafast chip integrated communication systems is still open. In this manuscript we report on ultrafast graphene photodetectors with a bandwidth of more than 76 GHz well suitable for communication links faster than 100 GBit s-1 per channel. We extract an upper value of 7.2 ps for the timescale in which the bolometric photoresponse in graphene is generated. The photodetectors were fabricated on 6″ silicon-on-insulator wafers in a semiconductor pilot line, demonstrating the scalable fabrication of high-performance graphene based devices.

  19. Graphene photodetectors with a bandwidth  >76 GHz fabricated in a 6″ wafer process line

    International Nuclear Information System (INIS)

    Schall, Daniel; Porschatis, Caroline; Otto, Martin; Neumaier, Daniel

    2017-01-01

    In recent years, the data traffic has grown exponentially and the forecasts indicate a huge market that could be addressed by communication infrastructure and service providers. However, the processing capacity, space, and energy consumption of the available technology is a serious bottleneck for the exploitation of these markets. Chip-integrated optical communication systems hold the promise of significantly improving these issues related to the current technology. At the moment, the answer to the question which material is best suited for ultrafast chip integrated communication systems is still open. In this manuscript we report on ultrafast graphene photodetectors with a bandwidth of more than 76 GHz well suitable for communication links faster than 100 GBit s −1 per channel. We extract an upper value of 7.2 ps for the timescale in which the bolometric photoresponse in graphene is generated. The photodetectors were fabricated on 6″ silicon-on-insulator wafers in a semiconductor pilot line, demonstrating the scalable fabrication of high-performance graphene based devices. (paper)

  20. High-throughput characterization of stresses in thin film materials libraries using Si cantilever array wafers and digital holographic microscopy

    International Nuclear Information System (INIS)

    Lai, Y. W.; Ludwig, A.; Hamann, S.; Ehmann, M.

    2011-01-01

    We report the development of an advanced high-throughput stress characterization method for thin film materials libraries sputter-deposited on micro-machined cantilever arrays consisting of around 1500 cantilevers on 4-inch silicon-on-insulator wafers. A low-cost custom-designed digital holographic microscope (DHM) is employed to simultaneously monitor the thin film thickness, the surface topography and the curvature of each of the cantilevers before and after deposition. The variation in stress state across the thin film materials library is then calculated by Stoney's equation based on the obtained radii of curvature of the cantilevers and film thicknesses. DHM with nanometer-scale out-of-plane resolution allows stress measurements in a wide range, at least from several MPa to several GPa. By using an automatic x-y translation stage, the local stresses within a 4-inch materials library are mapped with high accuracy within 10 min. The speed of measurement is greatly improved compared with the prior laser scanning approach that needs more than an hour of measuring time. A high-throughput stress measurement of an as-deposited Fe-Pd-W materials library was evaluated for demonstration. The fast characterization method is expected to accelerate the development of (functional) thin films, e.g., (magnetic) shape memory materials, whose functionality is greatly stress dependent.

  1. BCB Bonding Technology of Back-Side Illuminated COMS Device

    Science.gov (United States)

    Wu, Y.; Jiang, G. Q.; Jia, S. X.; Shi, Y. M.

    2018-03-01

    Back-side illuminated CMOS(BSI) sensor is a key device in spaceborne hyperspectral imaging technology. Compared with traditional devices, the path of incident light is simplified and the spectral response is planarized by BSI sensors, which meets the requirements of quantitative hyperspectral imaging applications. Wafer bonding is the basic technology and key process of the fabrication of BSI sensors. 6 inch bonding of CMOS wafer and glass wafer was fabricated based on the low bonding temperature and high stability of BCB. The influence of different thickness of BCB on bonding strength was studied. Wafer bonding with high strength, high stability and no bubbles was fabricated by changing bonding conditions.

  2. Wafer-level vacuum/hermetic packaging technologies for MEMS

    Science.gov (United States)

    Lee, Sang-Hyun; Mitchell, Jay; Welch, Warren; Lee, Sangwoo; Najafi, Khalil

    2010-02-01

    An overview of wafer-level packaging technologies developed at the University of Michigan is presented. Two sets of packaging technologies are discussed: (i) a low temperature wafer-level packaging processes for vacuum/hermeticity sealing, and (ii) an environmentally resistant packaging (ERP) technology for thermal and mechanical control as well as vacuum packaging. The low temperature wafer-level encapsulation processes are implemented using solder bond rings which are first patterned on a cap wafer and then mated with a device wafer in order to encircle and encapsulate the device at temperatures ranging from 200 to 390 °C. Vacuum levels below 10 mTorr were achieved with yields in an optimized process of better than 90%. Pressures were monitored for more than 4 years yielding important information on reliability and process control. The ERP adopts an environment isolation platform in the packaging substrate. The isolation platform is designed to provide low power oven-control, vibration isolation and shock protection. It involves batch flip-chip assembly of a MEMS device onto the isolation platform wafer. The MEMS device and isolation structure are encapsulated at the wafer-level by another substrate with vertical feedthroughs for vacuum/hermetic sealing and electrical signal connections. This technology was developed for high performance gyroscopes, but can be applied to any type of MEMS device.

  3. Electrical Interconnections Through CMOS Wafers

    DEFF Research Database (Denmark)

    Rasmussen, Frank Engel

    2003-01-01

    Chips with integrated vias are currently the ultimate miniaturizing solution for 3D packaging of microsystems. Previously the application of vias has almost exclusively been demonstrated within MEMS technology, and only a few of these via technologies have been CMOS compatible. This thesis...... describes the development of vias through a silicon wafer containing Complementary Metal-Oxide Semiconductor (CMOS) circuitry. Two via technologies have been developed and fabricated in blank silicon wafers; one based on KOH etching of wafer through-holes and one based on DRIE of wafer through......-holes. The most promising of these technologies --- the DRIE based process --- has been implemented in CMOS wafers containing hearing aid amplifiers. The main challenges in the development of a CMOS compatible via process depend on the chosen process for etching of wafer through-holes. In the case of KOH etching...

  4. Hydrogen interactions with silicon-on-insulator materials

    NARCIS (Netherlands)

    Rivera de Mena, A.J.

    2003-01-01

    The booming of microelectronics in recent decades has been made possible by the excellent properties of the Si/SiO2 interface in oxide on silicon systems.. This semiconductor/insulator combination has proven to be of great value for the semiconductor industry. It has made it possible to continuously

  5. Oxygen-induced inhibition of silicon-on-insulator dewetting

    Energy Technology Data Exchange (ETDEWEB)

    Curiotto, S.; Leroy, F.; Cheynis, F.; Müller, P. [Aix Marseille Université, CNRS, CINaM UMR 7325, 13288 Marseille (France)

    2014-02-10

    We report that solid state dewetting of Si thin film on SiO{sub 2} can be reversibly inhibited by exposing the Si surface to a partial pressure of dioxygen (∼10{sup −7}Torr) at high temperature (∼1100K). Coupling in situ Low-Energy Electron Microscopy and ex situ atomic force microscopy we propose that the pinning of the contact line induced by the presence of small amounts of silicon oxide is the main physical process that inhibits the dewetting.

  6. Topology optimized design for silicon-on-insulator mode converter

    DEFF Research Database (Denmark)

    Frellsen, Louise Floor; Frandsen, Lars Hagedorn; Ding, Yunhong

    2015-01-01

    The field of photonic integrated circuits (PICs) has attracted interest in recent years as they allow high device density while requiring only low operating power. The possibility of exploiting mode division multiplexing (MDM) in future optical communication networks is being investigated...... as a potential method for supporting the constantly increasing internet traffic demand [1]. Mode converters are important components necessary to support on-chip processing of MDM signals and multiple approaches has been followed in realizing such devices [2], [3]. Topology optimization (TO) [4] is a powerful...

  7. Laser wafering for silicon solar

    International Nuclear Information System (INIS)

    Friedmann, Thomas Aquinas; Sweatt, William C.; Jared, Bradley Howell

    2011-01-01

    Current technology cuts solar Si wafers by a wire saw process, resulting in 50% 'kerf' loss when machining silicon from a boule or brick into a wafer. We want to develop a kerf-free laser wafering technology that promises to eliminate such wasteful wire saw processes and achieve up to a ten-fold decrease in the g/W p (grams/peak watt) polysilicon usage from the starting polysilicon material. Compared to today's technology, this will also reduce costs (∼20%), embodied energy, and green-house gas GHG emissions (∼50%). We will use short pulse laser illumination sharply focused by a solid immersion lens to produce subsurface damage in silicon such that wafers can be mechanically cleaved from a boule or brick. For this concept to succeed, we will need to develop optics, lasers, cleaving, and high throughput processing technologies capable of producing wafers with thicknesses < 50 (micro)m with high throughput (< 10 sec./wafer). Wafer thickness scaling is the 'Moore's Law' of silicon solar. Our concept will allow solar manufacturers to skip entire generations of scaling and achieve grid parity with commercial electricity rates. Yet, this idea is largely untested and a simple demonstration is needed to provide credibility for a larger scale research and development program. The purpose of this project is to lay the groundwork to demonstrate the feasibility of laser wafering. First, to design and procure on optic train suitable for producing subsurface damage in silicon with the required damage and stress profile to promote lateral cleavage of silicon. Second, to use an existing laser to produce subsurface damage in silicon, and third, to characterize the damage using scanning electron microscopy and confocal Raman spectroscopy mapping.

  8. Laser wafering for silicon solar.

    Energy Technology Data Exchange (ETDEWEB)

    Friedmann, Thomas Aquinas; Sweatt, William C.; Jared, Bradley Howell

    2011-03-01

    Current technology cuts solar Si wafers by a wire saw process, resulting in 50% 'kerf' loss when machining silicon from a boule or brick into a wafer. We want to develop a kerf-free laser wafering technology that promises to eliminate such wasteful wire saw processes and achieve up to a ten-fold decrease in the g/W{sub p} (grams/peak watt) polysilicon usage from the starting polysilicon material. Compared to today's technology, this will also reduce costs ({approx}20%), embodied energy, and green-house gas GHG emissions ({approx}50%). We will use short pulse laser illumination sharply focused by a solid immersion lens to produce subsurface damage in silicon such that wafers can be mechanically cleaved from a boule or brick. For this concept to succeed, we will need to develop optics, lasers, cleaving, and high throughput processing technologies capable of producing wafers with thicknesses < 50 {micro}m with high throughput (< 10 sec./wafer). Wafer thickness scaling is the 'Moore's Law' of silicon solar. Our concept will allow solar manufacturers to skip entire generations of scaling and achieve grid parity with commercial electricity rates. Yet, this idea is largely untested and a simple demonstration is needed to provide credibility for a larger scale research and development program. The purpose of this project is to lay the groundwork to demonstrate the feasibility of laser wafering. First, to design and procure on optic train suitable for producing subsurface damage in silicon with the required damage and stress profile to promote lateral cleavage of silicon. Second, to use an existing laser to produce subsurface damage in silicon, and third, to characterize the damage using scanning electron microscopy and confocal Raman spectroscopy mapping.

  9. Estimation of interface resistivity in bonded Si for the development of high performance radiation detectors

    International Nuclear Information System (INIS)

    Kanno, Ikuo; Yamashita, Makoto; Nomiya, Seiichiro; Onabe, Hideaki

    2007-01-01

    For the development of high performance radiation detectors, direct bonding of Si wafers would be an useful method. Previously, p-n bonded Si were fabricated and they showed diode characteristics. The interface resistivity was, however, not investigated in detail. For the study of interface resistivity, n-type Si wafers with different resistivities were bonded. The resistivity of bonded Si wafers were measured and the interface resistivity was estimated by comparing with the results of model calculations. (author)

  10. Fusion-bonded fluidic interconnects

    NARCIS (Netherlands)

    Fazal, I.; Elwenspoek, Michael Curt

    2008-01-01

    A new approach to realize fluidic interconnects based on the fusion bonding of glass tubes with silicon is presented. Fusion bond strength analyses have been carried out. Experiments with plain silicon wafers and coated with silicon oxide and silicon nitride are performed. The obtained results are

  11. Hybrid Integrated Platforms for Silicon Photonics

    Science.gov (United States)

    Liang, Di; Roelkens, Gunther; Baets, Roel; Bowers, John E.

    2010-01-01

    A review of recent progress in hybrid integrated platforms for silicon photonics is presented. Integration of III-V semiconductors onto silicon-on-insulator substrates based on two different bonding techniques is compared, one comprising only inorganic materials, the other technique using an organic bonding agent. Issues such as bonding process and mechanism, bonding strength, uniformity, wafer surface requirement, and stress distribution are studied in detail. The application in silicon photonics to realize high-performance active and passive photonic devices on low-cost silicon wafers is discussed. Hybrid integration is believed to be a promising technology in a variety of applications of silicon photonics.

  12. Hybrid Integrated Platforms for Silicon Photonics

    Directory of Open Access Journals (Sweden)

    John E. Bowers

    2010-03-01

    Full Text Available A review of recent progress in hybrid integrated platforms for silicon photonics is presented. Integration of III-V semiconductors onto silicon-on-insulator substrates based on two different bonding techniques is compared, one comprising only inorganic materials, the other technique using an organic bonding agent. Issues such as bonding process and mechanism, bonding strength, uniformity, wafer surface requirement, and stress distribution are studied in detail. The application in silicon photonics to realize high-performance active and passive photonic devices on low-cost silicon wafers is discussed. Hybrid integration is believed to be a promising technology in a variety of applications of silicon photonics.

  13. Wafer of Intel Pentium 4 Prescott Chips

    CERN Multimedia

    Silicon wafer with hundreds of Penryn cores (microprocessor). There are around four times as many Prescott chips can be made per wafer than with the previous generation of Northwood-core Pentium 4 processors. It is faster and cheaper.

  14. Surface etching technologies for monocrystalline silicon wafer solar cells

    Science.gov (United States)

    Tang, Muzhi

    With more than 200 GW of accumulated installations in 2015, photovoltaics (PV) has become an important green energy harvesting method. The PV market is dominated by solar cells made from crystalline silicon wafers. The engineering of the wafer surfaces is critical to the solar cell cost reduction and performance enhancement. Therefore, this thesis focuses on the development of surface etching technologies for monocrystalline silicon wafer solar cells. It aims to develop a more efficient alkaline texturing method and more effective surface cleaning processes. Firstly, a rapid, isopropanol alcohol free texturing method is successfully demonstrated to shorten the process time and reduce the consumption of chemicals. This method utilizes the special chemical properties of triethylamine, which can form Si-N bonds with wafer surface atoms. Secondly, a room-temperature anisotropic emitter etch-back process is developed to improve the n+ emitter passivation. Using this method, 19.0% efficient screen-printed aluminium back surface field solar cells are developed that show an efficiency gain of 0.15% (absolute) compared with conventionally made solar cells. Finally, state-of-the-art silicon surface passivation results are achieved using hydrogen plasma etching as a dry alternative to the classical hydrofluoric acid wet-chemical process. The effective native oxide removal and the hydrogenation of the silicon surface are shown to be the reasons for the excellent level of surface passivation achieved with this novel method.

  15. Temperature Dependent Electrical Properties of PZT Wafer

    Science.gov (United States)

    Basu, T.; Sen, S.; Seal, A.; Sen, A.

    2016-04-01

    The electrical and electromechanical properties of lead zirconate titanate (PZT) wafers were investigated and compared with PZT bulk. PZT wafers were prepared by tape casting technique. The transition temperature of both the PZT forms remained the same. The transition from an asymmetric to a symmetric shape was observed for PZT wafers at higher temperature. The piezoelectric coefficient (d 33) values obtained were 560 pc/N and 234 pc/N, and the electromechanical coupling coefficient (k p) values were 0.68 and 0.49 for bulk and wafer, respectively. The reduction in polarization after fatigue was only ~3% in case of PZT bulk and ~7% for PZT wafer.

  16. Industrial Silicon Wafer Solar Cells

    OpenAIRE

    Neuhaus, Dirk-Holger; Münzer, Adolf

    2007-01-01

    In 2006, around 86% of all wafer-based silicon solar cells were produced using screen printing to form the silver front and aluminium rear contacts and chemical vapour deposition to grow silicon nitride as the antireflection coating onto the front surface. This paper reviews this dominant solar cell technology looking into state-of-the-art equipment and corresponding processes for each process step. The main efficiency losses of this type of solar cell are analyzed to demonstrate the future e...

  17. Wafer-Level Packaging Method for RF MEMS Applications Using Pre-Patterned BCB Polymer

    OpenAIRE

    Zhuhao Gong; Yulong Zhang; Xin Guo; Zewen Liu

    2018-01-01

    A radio-frequency micro-electro-mechanical system (RF MEMS) wafer-level packaging (WLP) method using pre-patterned benzo-cyclo-butene (BCB) polymers with a high-resistivity silicon cap is proposed to achieve high bonding quality and excellent RF performance. In this process, the BCB polymer was pre-defined to form the sealing ring and bonding layer by the spin-coating and patterning of photosensitive BCB before the cavity formation. During anisotropic wet etching of the silicon wafer to gener...

  18. Surface modification of silicon wafer by grafting zwitterionic polymers to improve its antifouling property

    Science.gov (United States)

    Sun, Yunlong; Chen, Changlin; Xu, Heng; Lei, Kun; Xu, Guanzhe; Zhao, Li; Lang, Meidong

    2017-10-01

    Silicon (111) wafer was modified by triethoxyvinylsilane containing double bond as an intermedium, and then P4VP (polymer 4-vinyl pyridine) brush was "grafted" onto the surface of silicon wafer containing reactive double bonds by adopting the "grafting from" way and Si-P4VP substrate (silicon wafer grafted by P4VP) was obtained. Finally, P4VP brush of Si-P4VP substrate was modified by 1,3-propanesulfonate fully to obtain P4VP-psl brush (zwitterionic polypyridinium salt) and the functional Si-P4VP-psl substrate (silicon wafer grafted by zwitterionic polypyridinium salt based on polymer 4-vinyl pyridine) was obtained successfully. The antifouling property of the silicon wafer, the Si-P4VP substrate and the Si-P4VP-psl substrate was investigated by using bovine serum albumin, mononuclear macrophages (RAW 264.7) and Escherichia coli (E. coli) ATTC25922 as model bacterium. The results showed that compared with the blank sample-silicon wafer, the Si-P4VP-psl substrate had excellent anti-adhesion ability against bovine serum albumin, cells and bacterium, due to zwitterionic P4VP-psl brush (polymer 4-vinyl pyridine salt) having special functionality like antifouling ability on biomaterial field.

  19. Fabrication of Ge-on-insulator wafers by Smart-CutTM with thermal management for undamaged donor Ge wafers

    Science.gov (United States)

    Kim, Munho; Cho, Sang June; Jayeshbhai Dave, Yash; Mi, Hongyi; Mikael, Solomon; Seo, Jung-Hun; Yoon, Jung U.; Ma, Zhenqiang

    2018-01-01

    Newly engineered substrates consisting of semiconductor-on-insulator are gaining much attention as starting materials for the subsequent transfer of semiconductor nanomembranes via selective etching of the insulating layer. Germanium-on-insulator (GeOI) substrates are critically important because of the versatile applications of Ge nanomembranes (Ge NMs) toward electronic and optoelectronic devices. Among various fabrication techniques, the Smart-CutTM technique is more attractive than other methods because a high temperature annealing process can be avoided. Another advantage of Smart-CutTM is the reusability of the donor Ge wafer. However, it is very difficult to realize an undamaged Ge wafer because there exists a large mismatch in the coefficient of thermal expansion among the layers. Although an undamaged donor Ge wafer is a prerequisite for its reuse, research related to this issue has not yet been reported. Here we report the fabrication of 4-inch GeOI substrates using the direct wafer bonding and Smart-CutTM process with a low thermal budget. In addition, a thermo-mechanical simulation of GeOI was performed by COMSOL to analyze induced thermal stress in each layer of GeOI. Crack-free donor Ge wafers were obtained by annealing at 250 °C for 10 h. Raman spectroscopy and x-ray diffraction (XRD) indicated similarly favorable crystalline quality of the Ge layer in GeOI compared to that of bulk Ge. In addition, Ge p-n diodes using transferred Ge NM indicate a clear rectifying behavior with an on and off current ratio of 500 at ±1 V. This demonstration offers great promise for high performance transferrable Ge NM-based device applications.

  20. Wafer scale oblique angle plasma etching

    Science.gov (United States)

    Burckel, David Bruce; Jarecki, Jr., Robert L.; Finnegan, Patrick Sean

    2017-05-23

    Wafer scale oblique angle etching of a semiconductor substrate is performed in a conventional plasma etch chamber by using a fixture that supports a multiple number of separate Faraday cages. Each cage is formed to include an angled grid surface and is positioned such that it will be positioned over a separate one of the die locations on the wafer surface when the fixture is placed over the wafer. The presence of the Faraday cages influences the local electric field surrounding each wafer die, re-shaping the local field to be disposed in alignment with the angled grid surface. The re-shaped plasma causes the reactive ions to follow a linear trajectory through the plasma sheath and angled grid surface, ultimately impinging the wafer surface at an angle. The selected geometry of the Faraday cage angled grid surface thus determines the angle at with the reactive ions will impinge the wafer.

  1. High Speed On-Wafer Characterization Laboratory

    Data.gov (United States)

    Federal Laboratory Consortium — At the High Speed On-Wafer Characterization Laboratory, researchers characterize and model devices operating at terahertz (THz) and millimeter-wave frequencies. The...

  2. Laser cutting sandwich structure glass-silicon-glass wafer with laser induced thermal-crack propagation

    Science.gov (United States)

    Cai, Yecheng; Wang, Maolu; Zhang, Hongzhi; Yang, Lijun; Fu, Xihong; Wang, Yang

    2017-08-01

    Silicon-glass devices are widely used in IC industry, MEMS and solar energy system because of their reliability and simplicity of the manufacturing process. With the trend toward the wafer level chip scale package (WLCSP) technology, the suitable dicing method of silicon-glass bonded structure wafer has become necessary. In this paper, a combined experimental and computational approach is undertaken to investigate the feasibility of cutting the sandwich structure glass-silicon-glass (SGS) wafer with laser induced thermal-crack propagation (LITP) method. A 1064 nm semiconductor laser cutting system with double laser beams which could simultaneously irradiate on the top and bottom of the sandwich structure wafer has been designed. A mathematical model for describing the physical process of the interaction between laser and SGS wafer, which consists of two surface heating sources and two volumetric heating sources, has been established. The temperature stress distribution are simulated by using finite element method (FEM) analysis software ABAQUS. The crack propagation process is analyzed by using the J-integral method. In the FEM model, a stationary planar crack is embedded in the wafer and the J-integral values around the crack front edge are determined using the FEM. A verification experiment under typical parameters is conducted and the crack propagation profile on the fracture surface is examined by the optical microscope and explained from the stress distribution and J-integral value.

  3. The integration of InGaP LEDs with CMOS on 200 mm silicon wafers

    Science.gov (United States)

    Wang, Bing; Lee, Kwang Hong; Wang, Cong; Wang, Yue; Made, Riko I.; Sasangka, Wardhana Aji; Nguyen, Viet Cuong; Lee, Kenneth Eng Kian; Tan, Chuan Seng; Yoon, Soon Fatt; Fitzgerald, Eugene A.; Michel, Jurgen

    2017-02-01

    The integration of photonics and electronics on a converged silicon CMOS platform is a long pursuit goal for both academe and industry. We have been developing technologies that can integrate III-V compound semiconductors and CMOS circuits on 200 mm silicon wafers. As an example we present our work on the integration of InGaP light-emitting diodes (LEDs) with CMOS. The InGaP LEDs were epitaxially grown on high-quality GaAs and Ge buffers on 200 mm (100) silicon wafers in a MOCVD reactor. Strain engineering was applied to control the wafer bow that is induced by the mismatch of coefficients of thermal expansion between III-V films and silicon substrate. Wafer bonding was used to transfer the foundry-made silicon CMOS wafers to the InGaP LED wafers. Process trenches were opened on the CMOS layer to expose the underneath III-V device layers for LED processing. We show the issues encountered in the 200 mm processing and the methods we have been developing to overcome the problems.

  4. Methane production using resin-wafer electrodeionization

    Science.gov (United States)

    Snyder, Seth W; Lin, YuPo; Urgun-Demirtas, Meltem

    2014-03-25

    The present invention provides an efficient method for creating natural gas including the anaerobic digestion of biomass to form biogas, and the electrodeionization of biogas to form natural gas and carbon dioxide using a resin-wafer deionization (RW-EDI) system. The method may be further modified to include a wastewater treatment system and can include a chemical conditioning/dewatering system after the anaerobic digestion system. The RW-EDI system, which includes a cathode and an anode, can either comprise at least one pair of wafers, each a basic and acidic wafer, or at least one wafer comprising of a basic portion and an acidic portion. A final embodiment of the RW-EDI system can include only one basic wafer for creating natural gas.

  5. Wafer-level manufacturing technology of glass microlenses

    Science.gov (United States)

    Gossner, U.; Hoeftmann, T.; Wieland, R.; Hansch, W.

    2014-08-01

    In high-tech products, there is an increasing demand to integrate glass lenses into complex micro systems. Especially in the lighting industry LEDs and laser diodes used for automotive applications require encapsulated micro lenses. To enable low-cost production, manufacturing of micro lenses on wafer level base using a replication technology is a key technology. This requires accurate forming of thousands of lenses with a diameter of 1-2 mm on a 200 mm wafer compliant with mass production. The article will discuss the technical aspects of a lens manufacturing replication process and the challenges, which need to be solved: choice of an appropriate master for replication, thermally robust interlayer coating, choice of replica glass, bonding and separation procedure. A promising approach for the master substrate material is based on a lens structured high-quality glass wafer with high melting point covered by a coating layer of amorphous silicon or germanium. This layer serves as an interlayer for the glass bonding process. Low pressure chemical vapor deposition and plasma enhanced chemical vapor deposition processes allow a deposition of layer coatings with different hydrogen and doping content influencing their chemical and physical behavior. A time reduced molding process using a float glass enables the formation of high quality lenses while preserving the recyclability of the mother substrate. The challenge is the separation of the replica from the master mold. An overview of chemical methods based on optimized etching of coating layer through small channels will be given and the impact of glass etching on surface roughness is discussed.

  6. Photonic Hilbert transformers based on laterally apodized integrated waveguide Bragg gratings on a SOI wafer.

    Science.gov (United States)

    Bazargani, Hamed Pishvai; Burla, Maurizio; Chrostowski, Lukas; Azaña, José

    2016-11-01

    We experimentally demonstrate high-performance integer and fractional-order photonic Hilbert transformers based on laterally apodized Bragg gratings in a silicon-on-insulator technology platform. The sub-millimeter-long gratings have been fabricated using single-etch electron beam lithography, and the resulting HT devices offer operation bandwidths approaching the THz range, with time-bandwidth products between 10 and 20.

  7. Probing and irradiation tests of ALICE pixel chip wafers and sensors

    CERN Document Server

    Cinausero, M; Antinori, F; Chochula, P; Dinapoli, R; Dima, R; Fabris, D; Galet, G; Lunardon, M; Manea, C; Marchini, S; Martini, S; Moretto, S; Pepato, Adriano; Prete, G; Riedler, P; Scarlassara, F; Segato, G F; Soramel, F; Stefanini, G; Turrisi, R; Vannucci, L; Viesti, G

    2004-01-01

    In the framework of the ALICE Silicon Pixel Detector (SPD) project a system dedicated to the tests of the ALICE1LHCb chip wafers has been assembled and is now in use for the selection of pixel chips to be bump-bonded to sensor ladders. In parallel, radiation hardness tests of the SPD silicon sensors have been carried out using the 27 MeV proton beam delivered by the XTU TANDEM accelerator at the SIRAD facility in LNL. In this paper we describe the wafer probing and irradiation set-ups and we report the obtained results. (6 refs).

  8. Sealing of cavities with lateral feed-throughs by anodic bonding

    DEFF Research Database (Denmark)

    Fléron, René; Jensen, Flemming

    2003-01-01

    The SESiBon(1)) project under the EU Growth programme has focussed on the investigation and exploitation of various silicon bonding techniques. Both standard silicon to pyrex wafer bonding and the more advanced silicon-to-silicon thin film anodic bonding has been investigated. Here we present...... the results of the work done to enable bonding of structured wafer surfaces, allowing lateral feed-throughs into sealed cavities.Lateral feed throughs are formed by means of RIE in a high-doped poly-silicon film deposited on an oxidized 4" silicon wafer. Next a BPSG (Boron Phosphorus Silicate Glass) layer...... is deposited in a PECVD reaction chamber onto the structured surface. The BPSG is used as an intermediate planarization layer. Planarization is done by annealing the wafer in a N2-O2-H2O ambient for 4 - 8h @ 900 degreesC. After planarization the two wafers are bonded together, sealing the cavities.Our work...

  9. Industrial Silicon Wafer Solar Cells

    Directory of Open Access Journals (Sweden)

    Dirk-Holger Neuhaus

    2007-01-01

    Full Text Available In 2006, around 86% of all wafer-based silicon solar cells were produced using screen printing to form the silver front and aluminium rear contacts and chemical vapour deposition to grow silicon nitride as the antireflection coating onto the front surface. This paper reviews this dominant solar cell technology looking into state-of-the-art equipment and corresponding processes for each process step. The main efficiency losses of this type of solar cell are analyzed to demonstrate the future efficiency potential of this technology. In research and development, more various advanced solar cell concepts have demonstrated higher efficiencies. The question which arises is “why are new solar cell concepts not transferred into industrial production more frequently?”. We look into the requirements a new solar cell technology has to fulfill to have an advantage over the current approach. Finally, we give an overview of high-efficiency concepts which have already been transferred into industrial production.

  10. Single wafer rapid thermal multiprocessing

    International Nuclear Information System (INIS)

    Saraswat, K.C.; Moslehi, M.M.; Grossman, D.D.; Wood, S.; Wright, P.; Booth, L.

    1989-01-01

    Future success in microelectronics will demand rapid innovation, rapid product introduction and ability to react to a change in technological and business climate quickly. These technological advances in integrated electronics will require development of flexible manufacturing technology for VLSI systems. However, the current approach of establishing factories for mass manufacturing of chips at a cost of more than 200 million dollars is detrimental to flexible manufacturing. The authors propose concepts of a micro factory which may be characterized by more economical small scale production, higher flexibility to accommodate many products on several processes, and faster turnaround and learning. In-situ multiprocessing equipment where several process steps can be done in sequence may be a key ingredient in this approach. For this environment to be flexible, the equipment must have ability to change processing environment, requiring extensive in-situ measurements and real time control. This paper describes the development of a novel single wafer rapid thermal multiprocessing (RTM) reactor for next generation flexible VLSI manufacturing. This reactor will combine lamp heating, remote microwave plasma and photo processing in a single cold-wall chamber, with applications for multilayer in-situ growth and deposition of dielectrics, semiconductors and metals

  11. Wafer level hermetic packaging based on Cu-Sn isothermal solidification technology

    International Nuclear Information System (INIS)

    Cao Yuhan; Luo Le

    2009-01-01

    A novel wafer level bonding method based on Cu-Sn isothermal solidification technology is established. A multi-layer sealing ring and the bonding processing are designed, and the amount of solder and the bonding parameters are optimized based on both theoretical and experimental results. Verification shows that oxidation of the solder layer, voids and the scalloped-edge appearance of the Cu 6 Sn 5 phase are successfully avoided. An average shear strength of 19.5 MPa and an excellent leak rate of around 1.9 x 10 -9 atm cc/s are possible, meeting the demands of MIL-STD-883E. (semiconductor technology)

  12. Modelling deformation and fracture in confectionery wafers

    Energy Technology Data Exchange (ETDEWEB)

    Mohammed, Idris K.; Charalambides, Maria N.; Williams, J. Gordon; Rasburn, John [Mechanical Engineering Department, Imperial College London, South Kensington, London, SW7 2AZ, United Kingdom and Nestec York Ltd., Nestlé Product Technology Centre, Haxby Road, PO Box 204, York YO91 1XY (United Kingdom)

    2015-01-22

    The aim of this research is to model the deformation and fracture behaviour of brittle wafers often used in chocolate confectionary products. Three point bending and compression experiments were performed on beam and circular disc samples respectively to determine the 'apparent' stress-strain curves in bending and compression. The deformation of the wafer for both these testing types was observed in-situ within an SEM. The wafer is modeled analytically and numerically as a composite material with a core which is more porous than the skins. X-ray tomography was used to generate a three dimensional volume of the wafer microstructure which was then meshed and used for quantitative analysis. A linear elastic material model, with a damage function and element deletion, was used and the XMT generated architecture was loaded in compression. The output from the FE simulations correlates closely to the load-deflection deformation observed experimentally.

  13. Wafer Cakes of Improved Amino Acid Structure

    Directory of Open Access Journals (Sweden)

    Roksolana Boidunyk

    2017-11-01

    Full Text Available The article presents the results of the study of the amino acid composition of newly developed wafer cakes with adipose fillings combined with natural additives. The appropriateness of the using non-traditional raw materials (powder of willow herb, poppy oilcake, carob, as well as skimmed milk powder in order to increase the biological value of wafer cakes and improve their amino acid composition is proven.

  14. Silicon wafers for integrated circuit process

    OpenAIRE

    Leroy , B.

    1986-01-01

    Silicon as a substrate material will continue to dominate the market of integrated circuits for many years. We first review how crystal pulling procedures impact the quality of silicon. We then investigate how thermal treatments affect the behaviour of oxygen and carbon, and how, as a result, the quality of silicon wafers evolves. Gettering techniques are then presented. We conclude by detailing the requirements that wafers must satisfy at the incoming inspection.

  15. Lamb wave propagation in monocrystalline silicon wafers

    OpenAIRE

    Fromme, P.; Pizzolato, M.; Robyr, J-L; Masserey, B.

    2018-01-01

    Monocrystalline silicon wafers are widely used in the photovoltaic industry for solar panels with high conversion efficiency. Guided ultrasonic waves offer the potential to efficiently detect micro-cracks in the thin wafers. Previous studies of ultrasonic wave propagation in silicon focused on effects of material anisotropy on bulk ultrasonic waves, but the dependence of the wave propagation characteristics on the material anisotropy is not well understood for Lamb waves. The phase slowness a...

  16. On the design and implementation of a wafer yield editor

    NARCIS (Netherlands)

    Pineda de Gyvez, J.; Jess, J.A.G.

    1989-01-01

    An interactive environment is presented for the analysis of yield information required on modern integrated circuit manufacturing lines. The system estimates wafer yields and wafer-yield variations, quantifies regional yield variations within wafers, identifies clusters in wafers and/or in lots, and

  17. Modeling the wafer temperature profile in a multiwafer LPCVD furnace

    Energy Technology Data Exchange (ETDEWEB)

    Badgwell, T.A. [Rice Univ., Houston, TX (United States). Dept. of Chemical Engineering; Trachtenberg, I.; Edgar, T.F. [Univ. of Texas, Austin, TX (United States). Dept. of Chemical Engineering

    1994-01-01

    A mathematical model has been developed to predict wafer temperatures within a hot-wall multiwafer low pressure chemical vapor deposition (LPCVD) reactor. The model predicts both axial (wafer-to-wafer) and radial (across-wafer) temperature profiles. Model predictions compare favorably with in situ wafer temperature measurements described in an earlier paper. Measured axial and radial temperature nonuniformities are explained in terms of radiative heat-transfer effects. A simulation study demonstrates how changes in the outer tube temperature profile and reactor geometry affect wafer temperatures. Reactor design changes which could improve the wafer temperature profile are discussed.

  18. Fabrication of High Aspect Ratio Through-Wafer Vias in CMOS Wafers for 3-D Packaging Applications

    DEFF Research Database (Denmark)

    Rasmussen, Frank Engel; Frech, J.; Heschel, M.

    2003-01-01

    A process for fabrication of through-wafer vias in CMOS wafers is presented. The process presented offers simple and well controlled fabrication of through-wafer vias using DRIE formation of wafer through-holes, low temperature deposition of through-hole insulation, doubled sided sputtering of Cr...

  19. Porous solid ion exchange wafer for immobilizing biomolecules

    Science.gov (United States)

    Arora, Michelle B.; Hestekin, Jamie A.; Lin, YuPo J.; St. Martin, Edward J.; Snyder, Seth W.

    2007-12-11

    A porous solid ion exchange wafer having a combination of a biomolecule capture-resin and an ion-exchange resin forming a charged capture resin within said wafer. Also disclosed is a porous solid ion exchange wafer having a combination of a biomolecule capture-resin and an ion-exchange resin forming a charged capture resin within said wafer containing a biomolecule with a tag. A separate bioreactor is also disclosed incorporating the wafer described above.

  20. X-ray analytics for 450-mm wafer; Roentgenanalytik fuer 450-mm-Wafer

    Energy Technology Data Exchange (ETDEWEB)

    Anon.

    2014-09-15

    The introduction of the 450-mm technology in the wafer fabrication and the further reduction of critical dimensions requires improved X-ray analysis methods. Therefor the PTB has concipated a metrology chamber for the characterization of 450-mm wafers, the crucial element of which is a multi-axis patent-pending manipulator.

  1. Fusion-bonded fluidic interconnects

    International Nuclear Information System (INIS)

    Fazal, I; Elwenspoek, M C

    2008-01-01

    A new approach to realize fluidic interconnects based on the fusion bonding of glass tubes with silicon is presented. Fusion bond strength analyses have been carried out. Experiments with plain silicon wafers and coated with silicon oxide and silicon nitride are performed. The obtained results are discussed in terms of the homogeneity and strength of fusion bond. High pressure testing shows that the bond strength is large enough for most applications of fluidic interconnects. The bond strength for 525 µm thick silicon, with glass tubes having an outer diameter of 6 mm and with a wall thickness of 2 mm, is more than 60 bars after annealing at a temperature of 800 °C

  2. Wafer level 3-D ICs process technology

    CERN Document Server

    Tan, Chuan Seng; Reif, L Rafael

    2009-01-01

    This book focuses on foundry-based process technology that enables the fabrication of 3-D ICs. The core of the book discusses the technology platform for pre-packaging wafer lever 3-D ICs. However, this book does not include a detailed discussion of 3-D ICs design and 3-D packaging. This is an edited book based on chapters contributed by various experts in the field of wafer-level 3-D ICs process technology. They are from academia, research labs and industry.

  3. Making Porous Luminescent Regions In Silicon Wafers

    Science.gov (United States)

    Fathauer, Robert W.; Jones, Eric W.

    1994-01-01

    Regions damaged by ion implantation stain-etched. Porous regions within single-crystal silicon wafers fabricated by straightforward stain-etching process. Regions exhibit visible photoluminescence at room temperature and might constitute basis of novel class of optoelectronic devices. Stain-etching process has advantages over recently investigated anodic-etching process. Process works on both n-doped and p-doped silicon wafers. Related development reported in article, "Porous Si(x)Ge(1-x) Layers Within Single Crystals of Si," (NPO-18836).

  4. Microemulsion-Based Mucoadhesive Buccal Wafers: Wafer Formation, In Vitro Release, and Ex Vivo Evaluation.

    Science.gov (United States)

    Pham, Minh Nguyet; Van Vo, Toi; Tran, Van-Thanh; Tran, Phuong Ha-Lien; Tran, Thao Truong-Dinh

    2017-10-01

    Microemulsion has the potentials to enhance dissolution as well as facilitate absorption and permeation of poorly water-soluble drugs through biological membranes. However, its application to govern a controlled release buccal delivery for local treatment has not been discovered. The aim of this study is to develop microemulsion-based mucoadhesive wafers for buccal delivery based on an incorporation of the microemulsion with mucoadhesive agents and mannitol. Ratio of oil to surfactant to water in the microemulsion significantly impacted quality of the wafers. Furthermore, the combination of carbopol and mannitol played a key role in forming the desired buccal wafers. The addition of an extra 50% of water to the formulation was suitable for wafer formation by freeze-drying, which affected the appearance and distribution of carbopol in the wafers. The amount of carbopol was critical for the enhancement of mucoadhesive properties and the sustained drug release patterns. Release study presented a significant improvement of the drug release profile following sustained release for 6 h. Ex vivo mucoadhesive studies provided decisive evidence to the increased retention time of wafers along with the increased carbopol content. The success of this study indicates an encouraging strategy to formulate a controlled drug delivery system by incorporating microemulsions into mucoadhesive wafers.

  5. InGaAs-OI Substrate Fabrication on a 300 mm Wafer

    Directory of Open Access Journals (Sweden)

    Sebastien Sollier

    2016-09-01

    Full Text Available In this work, we demonstrate for the first time a 300-mm indium–gallium–arsenic (InGaAs wafer on insulator (InGaAs-OI substrates by splitting in an InP sacrificial layer. A 30-nm-thick InGaAs layer was successfully transferred using low temperature direct wafer bonding (DWB and Smart CutTM technology. Three key process steps of the integration were therefore specifically developed and optimized. The first one was the epitaxial growing process, designed to reduce the surface roughness of the InGaAs film. Second, direct wafer bonding conditions were investigated and optimized to achieve non-defective bonding up to 600 °C. Finally, we adapted the splitting condition to detach the InGaAs layer according to epitaxial stack specifications. The paper presents the overall process flow that achieved InGaAs-OI, the required optimization, and the associated characterizations, namely atomic force microscopy (AFM, scanning acoustic microscopy (SAM, and HR-XRD, to insure the crystalline quality of the post transferred layer.

  6. Non-invasive thermal profiling of silicon wafer surface during RTP using acoustic and signal processing techniques

    Science.gov (United States)

    Syed, Ahmed Rashid

    Among the great physical challenges faced by the current front-end semiconductor equipment manufacturers is the accurate and repeatable surface temperature measurement of wafers during various fabrication steps. Close monitoring of temperature is essential in that it ensures desirable device characteristics to be reliably reproduced across various wafer lots. No where is the need to control temperature more pronounced than it is during Rapid Thermal Processing (RTP) which involves temperature ramp rates in excess of 200°C/s. This dissertation presents an elegant and practical approach to solve the wafer surface temperature estimation problem, in context of RTP, by deploying hardware that acquires the necessary data while preserving the integrity and purity of the wafer. In contrast to the widely used wafer-contacting (and hence contaminating) methods, such as bonded thermocouples, or environment sensitive schemes, such as light-pipes and infrared pyrometry, the proposed research explores the concept of utilizing Lamb (acoustic) waves to detect changes in wafer surface temperature, during RTP. Acoustic waves are transmitted to the wafer via an array of quartz rods that normally props the wafer inside an RTP chamber. These waves are generated using piezoelectric transducers affixed to the bases of the quartz rods. The group velocity of Lamb waves traversing the wafer surface undergoes a monotonic decrease with rise in wafer temperature. The correspondence of delay in phase of the received Lamb waves and the ambient temperature, along all direct paths between sending and receiving transducers, yields a psuedo real-time thermal image of the wafer. Although the custom built hardware-setup implements the above "proof-of-concept" scheme by transceiving acoustic signals at a single frequency, the real-world application will seek to enhance the data acquistion. rate (>1000 temperature measurements per seconds) by sending and receiving Lamb waves at multiple frequencies (by

  7. High throughput batch wafer handler for 100 to 200 mm wafers

    International Nuclear Information System (INIS)

    Rathmell, R.D.; Raatz, J.E.; Becker, B.L.; Kitchen, R.L.; Luck, T.R.; Decker, J.H.

    1989-01-01

    A new batch processing end station for ion implantation has been developed for wafers of 100 to 200 mm diameter. It usilizes a spinning disk with clampless wafer support. All wafer transport is done with backside handling and is carried out in vacuum. This end station incorporates a new dose control scheme which is able to monitor the incident particle current independently of the charge state of the ions. This technique prevents errors which may be caused by charge exchange between the beam and residual gas. The design and features of this system will be reviewed and the performance to date will be presented. (orig.)

  8. An electret-based energy harvesting device with a wafer-level fabrication process

    DEFF Research Database (Denmark)

    Crovetto, Andrea; Wang, Fei; Hansen, Ole

    2013-01-01

    This paper presents a MEMS energy harvesting device which is able to generate power from two perpendicular ambient vibration directions. A CYTOP polymer is used both as the electret material for electrostatic transduction and as a bonding interface for low-temperature wafer bonding. The device...... is also discussed. With a final chip size of about 1 cm2, a power output of 32.5 nW is successfully harvested with an external load of 17 MΩ, when a harmonic vibration source with an RMS acceleration amplitude of 0.03 g (∼0.3 m s−2) and a resonant frequency of 179 Hz is applied. These results can...

  9. Controllable laser thermal cleavage of sapphire wafers

    Science.gov (United States)

    Xu, Jiayu; Hu, Hong; Zhuang, Changhui; Ma, Guodong; Han, Junlong; Lei, Yulin

    2018-03-01

    Laser processing of substrates for light-emitting diodes (LEDs) offers advantages over other processing techniques and is therefore an active research area in both industrial and academic sectors. The processing of sapphire wafers is problematic because sapphire is a hard and brittle material. Semiconductor laser scribing processing suffers certain disadvantages that have yet to be overcome, thereby necessitating further investigation. In this work, a platform for controllable laser thermal cleavage was constructed. A sapphire LED wafer was modeled using the finite element method to simulate the thermal and stress distributions under different conditions. A guide groove cut by laser ablation before the cleavage process was observed to guide the crack extension and avoid deviation. The surface and cross section of sapphire wafers processed using controllable laser thermal cleavage were characterized by scanning electron microscopy and optical microscopy, and their morphology was compared to that of wafers processed using stealth dicing. The differences in luminous efficiency between substrates prepared using these two processing methods are explained.

  10. Optimal Wafer Cutting in Shuttle Layout Problems

    DEFF Research Database (Denmark)

    Nisted, Lasse; Pisinger, David; Altman, Avri

    2011-01-01

    . The shuttle layout problem is frequently solved in two phases: first, a floorplan of the shuttle is generated. Then, a cutting plan is found which minimizes the overall number of wafers needed to satisfy the demand of each die type. Since some die types require special production technologies, only compatible...

  11. Low-cost silicon wafer dicing using a craft cutter

    KAUST Repository

    Fan, Yiqiang

    2014-05-20

    This paper reports a low-cost silicon wafer dicing technique using a commercial craft cutter. The 4-inch silicon wafers were scribed using a crafter cutter with a mounted diamond blade. The pre-programmed automated process can reach a minimum die feature of 3 mm by 3 mm. We performed this scribing process on the top polished surface of a silicon wafer; we also created a scribing method for the back-unpolished surface in order to protect the structures on the wafer during scribing. Compared with other wafer dicing methods, our proposed dicing technique is extremely low cost (lower than $1,000), and suitable for silicon wafer dicing in microelectromechanical or microfluidic fields, which usually have a relatively large die dimension. The proposed dicing technique is also usable for dicing multiple project wafers, a process where dies of different dimensions are diced on the same wafer.

  12. Wafer plane inspection for advanced reticle defects

    Science.gov (United States)

    Nagpal, Rajesh; Ghadiali, Firoz; Kim, Jun; Huang, Tracy; Pang, Song

    2008-05-01

    Readiness of new mask defect inspection technology is one of the key enablers for insertion & transition of the next generation technology from development into production. High volume production in mask shops and wafer fabs demands a reticle inspection system with superior sensitivity complemented by a low false defect rate to ensure fast turnaround of reticle repair and defect disposition (W. Chou et al 2007). Wafer Plane Inspection (WPI) is a novel approach to mask defect inspection, complementing the high resolution inspection capabilities of the TeraScanHR defect inspection system. WPI is accomplished by using the high resolution mask images to construct a physical mask model (D. Pettibone et al 1999). This mask model is then used to create the mask image in the wafer aerial plane. A threshold model is applied to enhance the inspectability of printing defects. WPI can eliminate the mask restrictions imposed on OPC solutions by inspection tool limitations in the past. Historically, minimum image restrictions were required to avoid nuisance inspection stops and/or subsequent loss of sensitivity to defects. WPI has the potential to eliminate these limitations by moving the mask defect inspections to the wafer plane. This paper outlines Wafer Plane Inspection technology, and explores the application of this technology to advanced reticle inspection. A total of twelve representative critical layers were inspected using WPI die-to-die mode. The results from scanning these advanced reticles have shown that applying WPI with a pixel size of 90nm (WPI P90) captures all the defects of interest (DOI) with low false defect detection rates. In validating CD predictions, the delta CDs from WPI are compared against Aerial Imaging Measurement System (AIMS), where a good correlation is established between WPI and AIMSTM.

  13. Noncontact sheet resistance measurement technique for wafer inspection

    Science.gov (United States)

    Kempa, Krzysztof; Rommel, J. Martin; Litovsky, Roman; Becla, Peter; Lojek, Bohumil; Bryson, Frank; Blake, Julian

    1995-12-01

    A new technique, MICROTHERM, has been developed for noncontact sheet resistance measurements of semiconductor wafers. It is based on the application of microwave energy to the wafer, and simultaneous detection of the infrared radiation resulting from ohmic heating. The pattern of the emitted radiation corresponds to the sheet resistance distribution across the wafer. This method is nondestructive, noncontact, and allows for measurements of very small areas (several square microns) of the wafer.

  14. Water saving in IC wafer washing process; IC wafer senjo deno sessui taisaku

    Energy Technology Data Exchange (ETDEWEB)

    Harada, H. [Mitsubishi Corp., Tokyo (Japan); Araki, M.; Nakazawa, T.

    1997-11-30

    This paper reports features of a wafer washing technology, a new IC wafer washing process, its pure water saving effect, and a `QC washing` which has pure water saving effect in the wafer washing. Wafer washing processes generally include the SC1 process (using ammonia + hydrogen peroxide aqueous solution) purposed for removing contamination due to ultrafine particles, the SC2 process (using hydrochloric acid + hydrogen peroxide aqueous solution) purposed for removing contamination due to heavy metals, the piranha washing process (using hot sulfuric acid + hydrogen peroxide aqueous solution) purposed for removing contamination due to organic matters, and the DHF (using dilute hydrofluoric acid) purposed for removing natural oxide films. Natural oxide films are now remained as surface protection films, by which surface contamination has been reduced remarkably. A high-temperature washing chemical circulating and filtering technology developed in Japan has brought about a reform in wafer washing processes having been used previously. Spin washing is used as a water saving measure, in which washing chemicals or pure water are sprayed onto one each of wafers which is spin-rotated, allowing washing and rinsing to be made with small amount of washing chemicals and pure water. The QC washing is a method to replace tank interior with pure was as quick as possible in order to increase the rinsing effect. 7 refs., 5 figs.

  15. A new cleaning process for the metallic contaminants on a post-CMP wafer's surface

    International Nuclear Information System (INIS)

    Gao Baohong; Liu Yuling; Wang Chenwei; Wang Shengli; Zhou Qiang; Tan Baimei; Zhu Yadong

    2010-01-01

    This paper presents a new cleaning process using boron-doped diamond (BDD) film anode electrochemical oxidation for metallic contaminants on polished silicon wafer surfaces. The BDD film anode electrochemical oxidation can efficiently prepare pyrophosphate peroxide, pyrophosphate peroxide can oxidize organic contaminants, and pyrophosphate peroxide is deoxidized into pyrophosphate. Pyrophosphate, a good complexing agent, can form a metal complex, which is a structure consisting of a copper ion, bonded to a surrounding array of two pyrophosphate anions. Three polished wafers were immersed in the 0.01 mol/L CuSO 4 solution for 2 h in order to make comparative experiments. The first one was cleaned by pyrophosphate peroxide, the second by RCA (Radio Corporation of America) cleaning, and the third by deionized (DI) water. The XPS measurement result shows that the metallic contaminants on wafers cleaned by the RCA method and by pyrophosphate peroxide is less than the XPS detection limits of 1 ppm. And the wafer's surface cleaned by pyrophosphate peroxide is more efficient in removing organic carbon residues than RCA cleaning. Therefore, BDD film anode electrochemical oxidation can be used for microelectronics cleaning, and it can effectively remove organic contaminants and metallic contaminants in one step. It also achieves energy saving and environmental protection. (semiconductor technology)

  16. InP-based photonic integrated circuit platform on SiC wafer.

    Science.gov (United States)

    Takenaka, Mitsuru; Takagi, Shinichi

    2017-11-27

    We have numerically investigated the properties of an InP-on-SiC wafer as a photonic integrated circuit (PIC) platform. By bonding a thin InP-based semiconductor on a SiC wafer, SiC can be used as waveguide cladding, a heat sink, and a support substrate simultaneously. Since the refractive index of SiC is sufficiently low, PICs can be fabricated using InP-based strip and rib waveguides with a minimum bend radius of approximately 7 μm. High-thermal-conductivity SiC underneath an InP-based waveguide core markedly improves heat dissipation, resulting in superior thermal properties of active devices such as laser diodes. The InP-on-SiC wafer has significantly smaller thermal stress than InP-on-SiO 2 /Si wafer, which prevents the thermal degradation of InP-based devices during high-temperature processes. Thus, InP on SiC provides an ideal platform for high-performance PICs.

  17. Second Harmonic Generation characterization of SOI wafers: Impact of layer thickness and interface electric field

    Science.gov (United States)

    Damianos, D.; Vitrant, G.; Lei, M.; Changala, J.; Kaminski-Cachopo, A.; Blanc-Pelissier, D.; Cristoloveanu, S.; Ionica, I.

    2018-05-01

    In this work, we investigate Second Harmonic Generation (SHG) as a non-destructive characterization method for Silicon-On-Insulator (SOI) materials. For thick SOI stacks, the SHG signal is related to the thickness variations of the different layers. However, in thin SOI films, the comparison between measurements and optical modeling suggests a supplementary SHG contribution attributed to the electric fields at the SiO2/Si interfaces. The impact of the electric field at each interface of the SOI on the SHG is assessed. The SHG technique can be used to evaluate interfacial electric fields and consequently interface charge density in SOI materials.

  18. Size of silicon strip sensor from 6 inch wafer (right) compared to that from a 4 inch wafer (left).

    CERN Multimedia

    Honma, Alan

    1999-01-01

    Silicon strip sensors made from 6 inch wafers will allow for much larger surface area coverage at a reduced cost per unit surface area. A prototype sensor of size 8cm x 11cm made by Hamamatsu from a 6 inch wafer is shown next to a traditional 6cm x 6cm sensor from a 4 inch wafer.

  19. Optical cavity furnace for semiconductor wafer processing

    Science.gov (United States)

    Sopori, Bhushan L.

    2014-08-05

    An optical cavity furnace 10 having multiple optical energy sources 12 associated with an optical cavity 18 of the furnace. The multiple optical energy sources 12 may be lamps or other devices suitable for producing an appropriate level of optical energy. The optical cavity furnace 10 may also include one or more reflectors 14 and one or more walls 16 associated with the optical energy sources 12 such that the reflectors 14 and walls 16 define the optical cavity 18. The walls 16 may have any desired configuration or shape to enhance operation of the furnace as an optical cavity 18. The optical energy sources 12 may be positioned at any location with respect to the reflectors 14 and walls defining the optical cavity. The optical cavity furnace 10 may further include a semiconductor wafer transport system 22 for transporting one or more semiconductor wafers 20 through the optical cavity.

  20. Wafer integrated micro-scale concentrating photovoltaics

    Science.gov (United States)

    Gu, Tian; Li, Duanhui; Li, Lan; Jared, Bradley; Keeler, Gordon; Miller, Bill; Sweatt, William; Paap, Scott; Saavedra, Michael; Das, Ujjwal; Hegedus, Steve; Tauke-Pedretti, Anna; Hu, Juejun

    2017-09-01

    Recent development of a novel micro-scale PV/CPV technology is presented. The Wafer Integrated Micro-scale PV approach (WPV) seamlessly integrates multijunction micro-cells with a multi-functional silicon platform that provides optical micro-concentration, hybrid photovoltaic, and mechanical micro-assembly. The wafer-embedded micro-concentrating elements is shown to considerably improve the concentration-acceptance-angle product, potentially leading to dramatically reduced module materials and fabrication costs, sufficient angular tolerance for low-cost trackers, and an ultra-compact optical architecture, which makes the WPV module compatible with commercial flat panel infrastructures. The PV/CPV hybrid architecture further allows the collection of both direct and diffuse sunlight, thus extending the geographic and market domains for cost-effective PV system deployment. The WPV approach can potentially benefits from both the high performance of multijunction cells and the low cost of flat plate Si PV systems.

  1. Carbon dioxide capture using resin-wafer electrodeionization

    Science.gov (United States)

    Lin, YuPo J.; Snyder, Seth W.; Trachtenberg, Michael S.; Cowan, Robert M.; Datta, Saurav

    2015-09-08

    The present invention provides a resin-wafer electrodeionization (RW-EDI) apparatus including cathode and anode electrodes separated by a plurality of porous solid ion exchange resin wafers, which when in use are filled with an aqueous fluid. The apparatus includes one or more wafers comprising a basic ion exchange medium, and preferably includes one or more wafers comprising an acidic ion exchange medium. The wafers are separated from one another by ion exchange membranes. The fluid within the acidic and/or basic ion exchange wafers preferably includes, or is in contact with, a carbonic anhydrase (CA) enzyme to facilitate conversion of bicarbonate ion to carbon dioxide within the acidic medium. A pH suitable for exchange of CO.sub.2 is electrochemically maintained within the basic and acidic ion exchange wafers by applying an electric potential across the cathode and anode.

  2. Wafer plane inspection with soft resist thresholding

    Science.gov (United States)

    Hess, Carl; Shi, Rui-fang; Wihl, Mark; Xiong, Yalin; Pang, Song

    2008-10-01

    Wafer Plane Inspection (WPI) is an inspection mode on the KLA-Tencor TeraScaTM platform that uses the high signalto- noise ratio images from the high numerical aperture microscope, and then models the entire lithographic process to enable defect detection on the wafer plane[1]. This technology meets the needs of some advanced mask manufacturers to identify the lithographically-significant defects while ignoring the other non-lithographically-significant defects. WPI accomplishes this goal by performing defect detection based on a modeled image of how the mask features would actually print in the photoresist. There are several advantages to this approach: (1) the high fidelity of the images provide a sensitivity advantage over competing approaches; (2) the ability to perform defect detection on the wafer plane allows one to only see those defects that have a printing impact on the wafer; (3) the use of modeling on the lithographic portion of the flow enables unprecedented flexibility to support arbitrary illumination profiles, process-window inspection in unit time, and combination modes to find both printing and non-printing defects. WPI is proving to be a valuable addition to the KLA-Tencor detection algorithm suite. The modeling portion of WPI uses a single resist threshold as the final step in the processing. This has been shown to be adequate on several advanced customer layers, but is not ideal for all layers. Actual resist chemistry has complicated processes including acid and base-diffusion and quench that are not consistently well-modeled with a single resist threshold. We have considered the use of an advanced resist model for WPI, but rejected it because the burdensome requirements for the calibration of the model were not practical for reticle inspection. This paper describes an alternative approach that allows for a "soft" resist threshold to be applied that provides a more robust solution for the most challenging processes. This approach is just

  3. Wafer-shape metrics based foundry lithography

    Science.gov (United States)

    Kim, Sungtae; Liang, Frida; Mileham, Jeffrey; Tsai, Damon; Bouche, Eric; Lee, Sean; Huang, Albert; Hua, C. F.; Wei, Ming Sheng

    2017-03-01

    As device shrink, there are many difficulties with process integration and device yield. Lithography process control is expected to be a major challenge due to tighter overlay and focus control requirement. The understanding and control of stresses accumulated during device fabrication has becoming more critical at advanced technology nodes. Within-wafer stress variations cause local wafer distortions which in turn present challenges for managing overlay and depth of focus during lithography. A novel technique for measuring distortion is Coherent Gradient Sensing (CGS) interferometry, which is capable of generating a high-density distortion data set of the full wafer within a time frame suitable for a high volume manufacturing (HVM) environment. In this paper, we describe the adoption of CGS (Coherent Gradient Sensing) interferometry into high volume foundry manufacturing to overcome these challenges. Leveraging this high density 3D metrology, we characterized its In-plane distortion as well as its topography capabilities applied to the full flow of an advanced foundry manufacturing. Case studies are presented that summarize the use of CGS data to reveal correlations between in-plane distortion and overlay variation as well as between topography and device yield.

  4. Wafer-scale micro-optics fabrication

    Science.gov (United States)

    Voelkel, Reinhard

    2012-07-01

    Micro-optics is an indispensable key enabling technology for many products and applications today. Probably the most prestigious examples are the diffractive light shaping elements used in high-end DUV lithography steppers. Highly-efficient refractive and diffractive micro-optical elements are used for precise beam and pupil shaping. Micro-optics had a major impact on the reduction of aberrations and diffraction effects in projection lithography, allowing a resolution enhancement from 250 nm to 45 nm within the past decade. Micro-optics also plays a decisive role in medical devices (endoscopes, ophthalmology), in all laser-based devices and fiber communication networks, bringing high-speed internet to our homes. Even our modern smart phones contain a variety of micro-optical elements. For example, LED flash light shaping elements, the secondary camera, ambient light and proximity sensors. Wherever light is involved, micro-optics offers the chance to further miniaturize a device, to improve its performance, or to reduce manufacturing and packaging costs. Wafer-scale micro-optics fabrication is based on technology established by the semiconductor industry. Thousands of components are fabricated in parallel on a wafer. This review paper recapitulates major steps and inventions in wafer-scale micro-optics technology. The state-of-the-art of fabrication, testing and packaging technology is summarized.

  5. Lamb wave propagation in monocrystalline silicon wafers.

    Science.gov (United States)

    Fromme, Paul; Pizzolato, Marco; Robyr, Jean-Luc; Masserey, Bernard

    2018-01-01

    Monocrystalline silicon wafers are widely used in the photovoltaic industry for solar panels with high conversion efficiency. Guided ultrasonic waves offer the potential to efficiently detect micro-cracks in the thin wafers. Previous studies of ultrasonic wave propagation in silicon focused on effects of material anisotropy on bulk ultrasonic waves, but the dependence of the wave propagation characteristics on the material anisotropy is not well understood for Lamb waves. The phase slowness and beam skewing of the two fundamental Lamb wave modes A 0 and S 0 were investigated. Experimental measurements using contact wedge transducer excitation and laser measurement were conducted. Good agreement was found between the theoretically calculated angular dependency of the phase slowness and measurements for different propagation directions relative to the crystal orientation. Significant wave skew and beam widening was observed experimentally due to the anisotropy, especially for the S 0 mode. Explicit finite element simulations were conducted to visualize and quantify the guided wave beam skew. Good agreement was found for the A 0 mode, but a systematic discrepancy was observed for the S 0 mode. These effects need to be considered for the non-destructive testing of wafers using guided waves.

  6. Boron impurity at the Si/SiO2 interface in SOI wafers and consequences for piezoresistive MEMS devices

    International Nuclear Information System (INIS)

    Nafari, A; Karlen, D; Enoksson, P; Rusu, C; Svensson, K

    2009-01-01

    In this work, the electrical performance of piezoresistive devices fabricated on thinned SOI wafers has been investigated. Specifically, SOI wafers manufactured with the standard bond-and-etch back method (BESOI), commonly used for MEMS fabrication, have been studied. Results from electrical measurements and SIMS characterization show the presence of a boron impurity close to the buried oxide, even on unprocessed wafers. If the boron impurity overlaps with the piezoresistors on the device, it can create non-defined pn-junctions and thus allow conduction through the substrate, leading to stray connections and excessive noise. The thickness of the boron impurity can extend up to several µm, thus setting a thickness limit for the thinnest parts of a MEMS device. This work shows how this impurity can fundamentally affect the functionality of piezoresistive devices. Design rules of how to avoid this are presented

  7. Functional Testing and Characterisation of ISFETs on Wafer Level by Means of a Micro-droplet Cell

    Directory of Open Access Journals (Sweden)

    Michael J. Schöning

    2006-04-01

    Full Text Available A wafer-level functionality testing and characterisation system for ISFETs (ion-sensitive field-effect transistor is realised by means of integration of a specifically designedcapillary electrochemical micro-droplet cell into a commercial wafer prober-station. Thedeveloped system allows the identification and selection of “good” ISFETs at the earlieststage and to avoid expensive bonding, encapsulation and packaging processes for non-functioning ISFETs and thus, to decrease costs, which are wasted for bad dies. Thedeveloped system is also feasible for wafer-level characterisation of ISFETs in terms ofsensitivity, hysteresis and response time. Additionally, the system might be also utilised forwafer-level testing of further electrochemical sensors.

  8. Room temperature Cu-Cu direct bonding using surface activated bonding method

    International Nuclear Information System (INIS)

    Kim, T.H.; Howlader, M.M.R.; Itoh, T.; Suga, T.

    2003-01-01

    Thin copper (Cu) films of 80 nm thickness deposited on a diffusion barrier layered 8 in. silicon wafers were directly bonded at room temperature using the surface activated bonding method. A low energy Ar ion beam of 40-100 eV was used to activate the Cu surface prior to bonding. Contacting two surface-activated wafers enables successful Cu-Cu direct bonding. The bonding process was carried out under an ultrahigh vacuum condition. No thermal annealing was required to increase the bonding strength since the bonded interface was strong enough at room temperature. The chemical constitution of the Cu surface was examined by Auger electron spectroscope. It was observed that carbon-based contaminations and native oxides on copper surface were effectively removed by Ar ion beam irradiation for 60 s without any wet cleaning processes. An atomic force microscope study shows that the Ar ion beam process causes no surface roughness degradation. Tensile test results show that high bonding strength equivalent to bulk material is achieved at room temperature. The cross-sectional transmission electron microscope observations reveal the presence of void-free bonding interface without intermediate layer at the bonded Cu surfaces

  9. Comparison of thermally and mechanically induced Si layer transfer in hydrogen-implanted Si wafers

    International Nuclear Information System (INIS)

    Hoechbauer, T.; Misra, A.; Nastasi, M.; Henttinen, K.; Suni, T.; Suni, I.; Lau, S.S.; Ensinger, W.

    2004-01-01

    Hydrogen ion-implantation into Si and subsequent heat treatment has been shown to be an effective means of cleaving thin layer of Si from its parent wafer. This process has been called Smart Cut TM or ion-cut. We investigated the cleavage process in H-implanted silicon samples, in which the ion-cut was provoked thermally and mechanically, respectively. A oriented p-type silicon wafer was irradiated at room temperature with 100 keV H 2 + -ions to a dose of 5 x 10 16 H 2 /cm 2 and subsequently joined to a handle wafer. Ion-cutting was achieved by two different methods: (1) thermally by annealing to 350 deg. C and (2) mechanically by insertion of a razor blade sidewise into the bonded wafers near the bond interface. The H-concentration and the crystal damage depth profiles before and after the ion-cut were investigated through the combined use of elastic recoil detection analysis and Rutherford backscattering spectroscopy (RBS). The location at which the ion-cut occurred was determined by RBS in channeling mode and cross-section transmission electron spectroscopy. The ion-cut depth was found to be independent on the cutting method. The gained knowledge was correlated to the depth distribution of the H-platelet density in the as-implanted sample, which contains two separate peaks in the implantation zone. The obtained results suggest that the ion-cut location coincides with the depth of the H-platelet density peak located at a larger depth

  10. Applications of Silicon-on-Insulator Photonic Crystal Structures in Miniature Spectrometer Designs

    Science.gov (United States)

    Gao, Boshen

    Optical spectroscopy is one of the most important fundamental scientific techniques. It has been widely adopted in physics, chemistry, biology, medicine and many other research fields. However, the size and weight of a spectrometer as well as the difficulty to align and maintain it have long limited spectroscopy to be a laboratory-only procedure. With the recent advancement in semiconductor electronics and photonics, miniaturized spectrometers have been introduced to complete many tasks in daily life where mobility and portability are necessary. This thesis focuses on the study of several photonic crystal (PC) nano-structures potentially suitable for miniaturized on-chip spectrometer designs. Chapter 1 briefly introduces the concept of PCs and their band structures. By analyzing the band structure, the origin of the superprism effect is explained. Defect-based PC nano-cavities are also discussed, as well as a type of coupled cavity waveguides (CCW) composed of PC nano-cavities. Chapter 2 is devoted to the optimization of a flat-band superprism structure for spectroscopy application using numerical simulations. Chapter 3 reports a fabricated broad-band superprism and the experimental characterization of its wavelength resolving performance. In chapter 4, the idea of composing a miniature spectrometer based on a single tunable PC nano-cavity is proposed. The rest of this chapter discusses the experimental study of this design. Chapter 5 examines the slow-light performance of a CCW and discusses its potential application in slow-light interferometry. Chapter 6 serves as a conclusion of this thesis and proposes directions for possible future work to follow up.

  11. Dynamics of solid thin-film dewetting in the silicon-on-insulator system

    Energy Technology Data Exchange (ETDEWEB)

    Bussmann, E; Cheynis, F; Leroy, F; Mueller, P [Centre Interdisciplinaire de Nanoscience de Marseille (CINaM) CNRS UPR 3118, Aix-Marseille Universite, 13288 Marseille (France); Pierre-Louis, O, E-mail: muller@cinam.univ-mrs.fr [LPMCN, Universite Lyon 1, 43 Bd du 11 novembre, 69622 Villeurbane (France)

    2011-04-15

    Using low-energy electron microscopy movies, we have measured the dewetting dynamics of single-crystal Si(001) thin films on SiO{sub 2} substrates. During annealing (T>700 deg. C), voids open in the Si, exposing the oxide. The voids grow, evolving Si fingers that subsequently break apart into self-organized three-dimensional (3D) Si nanocrystals. A kinetic Monte Carlo model incorporating surface and interfacial free energies reproduces all the salient features of the morphological evolution. The dewetting dynamics is described using an analytic surface-diffusion-based model. We demonstrate quantitatively that Si dewetting from SiO{sub 2} is mediated by surface-diffusion driven by surface free-energy minimization.

  12. Novel Applications of a Thermally Tunable Bistable Buckling Silicon-on-Insulator (SOI) Microfabricated Membrane

    Science.gov (United States)

    2015-09-17

    sensor and disposable medical blood pressure sensor, which both hit the market in 1982 [2]. Since then, MEMS technology has undergone rapid growth and...Available: http: //digitalpicture.com.au/climate-change-slowing-trains/ 49. O. Tabata , K. Kawahata, S. Sugiyama, and I. Igarashi, “Mechanical property

  13. Dynamics of solid thin-film dewetting in the silicon-on-insulator system

    Science.gov (United States)

    Bussmann, E.; Cheynis, F.; Leroy, F.; Müller, P.; Pierre-Louis, O.

    2011-04-01

    Using low-energy electron microscopy movies, we have measured the dewetting dynamics of single-crystal Si(001) thin films on SiO2 substrates. During annealing (T>700 °C), voids open in the Si, exposing the oxide. The voids grow, evolving Si fingers that subsequently break apart into self-organized three-dimensional (3D) Si nanocrystals. A kinetic Monte Carlo model incorporating surface and interfacial free energies reproduces all the salient features of the morphological evolution. The dewetting dynamics is described using an analytic surface-diffusion-based model. We demonstrate quantitatively that Si dewetting from SiO2 is mediated by surface-diffusion driven by surface free-energy minimization.

  14. Raman mediated all-optical cascadable inverter using silicon-on-insulator waveguides.

    Science.gov (United States)

    Sen, Mrinal; Das, Mukul K

    2013-12-01

    In this Letter, we propose an all-optical circuit for a cascadable and integrable logic inverter based on stimulated Raman scattering. A maximum product criteria for noise margin is taken to analyze the cascadability of the inverter. Variation of noise margin for different model parameters is also studied. Finally, the time domain response of the inverter is analyzed for different widths of input pulses.

  15. Topology-optimized mode converter in a silicon-on-insulator photonic wire waveguide

    DEFF Research Database (Denmark)

    Frellsen, Louise Floor; Ding, Yunhong; Sigmund, Ole

    2016-01-01

    A 1.4 μm × 3.4 μm fundamental to first order mode converter for the transverse electric polarization was designed using topology optimization. Insertion loss <2 dB (100 nm bandwidth) and extinction ratio >9.5 dB....

  16. Topology optimized mode multiplexing in silicon-on-insulator photonic wire waveguides

    DEFF Research Database (Denmark)

    Frellsen, Louise Floor; Ding, Yunhong; Sigmund, Ole

    2016-01-01

    We design and experimentally verify a topology optimized low-loss and broadband two-mode (de-)multiplexer, which is (de-)multiplexing the fundamental and the first-order transverse-electric modes in a silicon photonic wire. The device has a footprint of 2.6 μm x 4.22 μm and exhibits a loss 14 d...

  17. Analytic description of four-wave mixing in silicon-on-insulator waveguides

    DEFF Research Database (Denmark)

    Friis, Søren Michael Mørk; Koefoed, Jacob Gade; Guo, Kai

    2018-01-01

    and becomes a nonlinear differential equation that we solve analytically without further approximations. The signal and idler equations have no known solutions for arbitrary pump power evolution, but we calculate approximate field expressions based on a Magnus expansion, which has been used to study time...

  18. Two-dimensional optical phased array antenna on silicon-on-insulator.

    Science.gov (United States)

    Van Acoleyen, Karel; Rogier, Hendrik; Baets, Roel

    2010-06-21

    Optical wireless links can offer a very large bandwidth and can act as a complementary technology to radiofrequency links. Optical components nowadays are however rather bulky. Therefore, we have investigated the potential of silicon photonics to fabricated integrated components for wireless optical communication. This paper presents a two-dimensional phased array antenna consisting of grating couplers that couple light off-chip. Wavelength steering of $0.24 degrees /nm is presented reducing the need of active phase modulators. The needed steering range is $1.5 degrees . The 3dB angular coverage range of these antennas is about $0.007pi sr with a directivity of more than 38dBi and antenna losses smaller than 3dB.

  19. Polarization diversity DPSK demodulator on the silicon-on-insulator platform with simple fabrication

    DEFF Research Database (Denmark)

    Ding, Yunhong; Huang, Bo; Ou, Haiyan

    2013-01-01

    of a tapered waveguide followed by a 2 × 2 multimode interferometer. A lowest insertion loss of 0.5 dB with low polarization dependent loss of 1.6 dB and low polarization dependent extinction ratio smaller than 3 dB are measured for the polarization diversity circuit. Clear eye-diagrams and a finite power...

  20. Dynamics of solid thin-film dewetting in the silicon-on-insulator system

    International Nuclear Information System (INIS)

    Bussmann, E; Cheynis, F; Leroy, F; Mueller, P; Pierre-Louis, O

    2011-01-01

    Using low-energy electron microscopy movies, we have measured the dewetting dynamics of single-crystal Si(001) thin films on SiO 2 substrates. During annealing (T>700 deg. C), voids open in the Si, exposing the oxide. The voids grow, evolving Si fingers that subsequently break apart into self-organized three-dimensional (3D) Si nanocrystals. A kinetic Monte Carlo model incorporating surface and interfacial free energies reproduces all the salient features of the morphological evolution. The dewetting dynamics is described using an analytic surface-diffusion-based model. We demonstrate quantitatively that Si dewetting from SiO 2 is mediated by surface-diffusion driven by surface free-energy minimization.

  1. High temperature study of flexible silicon-on-insulator fin field-effect transistors

    KAUST Repository

    Diab, Amer El Hajj; Sevilla, Galo T.; Ghoneim, Mohamed T.; Hussain, Muhammad Mustafa

    2014-01-01

    . Characterization from room to high temperature (150 °C) was completed to determine temperature dependence of drain current (Ids), gate leakage current (Igs), transconductance (gm), and extracted low-field mobility (μ0). Mobility degradation with temperature

  2. Two-dimensional threshold voltage analytical model of DMG strained-silicon-on-insulator MOSFETs

    International Nuclear Information System (INIS)

    Li Jin; Liu Hongxia; Li Bin; Cao Lei; Yuan Bo

    2010-01-01

    For the first time, a simple and accurate two-dimensional analytical model for the surface potential variation along the channel in fully depleted dual-material gate strained-Si-on-insulator (DMG SSOI) MOSFETs is developed. We investigate the improved short channel effect (SCE), hot carrier effect (HCE), drain-induced barrier-lowering (DIBL) and carrier transport efficiency for the novel structure MOSFET. The analytical model takes into account the effects of different metal gate lengths, work functions, the drain bias and Ge mole fraction in the relaxed SiGe buffer. The surface potential in the channel region exhibits a step potential, which can suppress SCE, HCE and DIBL. Also, strained-Si and SOI structure can improve the carrier transport efficiency, with strained-Si being particularly effective. Further, the threshold voltage model correctly predicts a 'rollup' in threshold voltage with decreasing channel length ratios or Ge mole fraction in the relaxed SiGe buffer. The validity of the two-dimensional analytical model is verified using numerical simulations. (semiconductor devices)

  3. Hybrid single quantum well InP/Si nanobeam lasers for silicon photonics.

    Science.gov (United States)

    Fegadolli, William S; Kim, Se-Heon; Postigo, Pablo Aitor; Scherer, Axel

    2013-11-15

    We report on a hybrid InP/Si photonic crystal nanobeam laser emitting at 1578 nm with a low threshold power of ~14.7 μW. Laser gain is provided from a single InAsP quantum well embedded in a 155 nm InP layer bonded on a standard silicon-on-insulator wafer. This miniaturized nanolaser, with an extremely small modal volume of 0.375(λ/n)(3), is a promising and efficient light source for silicon photonics.

  4. Wafer-Scale Integration of Systolic Arrays,

    Science.gov (United States)

    1985-10-01

    hus wtha rbaiith hig robabili, e aubrbe orutysta mostck b(e)adstotoefwsi the cenofther cnnel thati are connted to (g.The kery ato the alevel of t...problems considered heretofore in this paper also have an interpretation in a purely graph theoretic model. Suppose we are given a two-dimensional...graphs," Magyar 7Td. Akad. Math . Kut. Int. Kozl, Vol. 5, 1960, pp. 17-61. [6] D. Fussell and P. Varman, "Fault-tolerant wafer-scale architectures for

  5. Wafer-scale pixelated detector system

    Science.gov (United States)

    Fahim, Farah; Deptuch, Grzegorz; Zimmerman, Tom

    2017-10-17

    A large area, gapless, detection system comprises at least one sensor; an interposer operably connected to the at least one sensor; and at least one application specific integrated circuit operably connected to the sensor via the interposer wherein the detection system provides high dynamic range while maintaining small pixel area and low power dissipation. Thereby the invention provides methods and systems for a wafer-scale gapless and seamless detector systems with small pixels, which have both high dynamic range and low power dissipation.

  6. Candida parapsilosis meningitis associated with Gliadel (BCNU) wafer implants.

    LENUS (Irish Health Repository)

    O'Brien, Deirdre

    2012-02-01

    A 58-year old male presented with meningitis associated with subgaleal and subdural collections 6 weeks following a temporal craniotomy for resection of recurrent glioblastoma multiforme and Gliadel wafer implantation. Candida parapsilosis was cultured from cerebrospinal fluid (CSF) and Gliadel wafers removed during surgical debridement. He was successfully treated with liposomal amphotericin B. To our knowledge, this is the first reported case of Candida parapsilosis meningitis secondary to Gliadel wafer placement.

  7. Candida parapsilosis meningitis associated with Gliadel (BCNU) wafer implants.

    LENUS (Irish Health Repository)

    O'brien, Deirdre

    2010-12-15

    A 58-year old male presented with meningitis associated with subgaleal and subdural collections 6 weeks following a temporal craniotomy for resection of recurrent glioblastoma multiforme and Gliadel wafer implantation. Candida parapsilosis was cultured from cerebrospinal fluid (CSF) and Gliadel wafers removed during surgical debridement. He was successfully treated with liposomal amphotericin B. To our knowledge, this is the first reported case of Candida parapsilosis meningitis secondary to Gliadel wafer placement.

  8. High frequency guided wave propagation in monocrystalline silicon wafers

    OpenAIRE

    Pizzolato, M.; Masserey, B.; Robyr, J. L.; Fromme, P.

    2017-01-01

    Monocrystalline silicon wafers are widely used in the photovoltaic industry for solar panels with high conversion efficiency. The cutting process can introduce micro-cracks in the thin wafers and lead to varying thickness. High frequency guided ultrasonic waves are considered for the structural monitoring of the wafers. The anisotropy of the monocrystalline silicon leads to variations of the wave characteristics, depending on the propagation direction relative to the crystal orientation. Full...

  9. Low temperature bonding of heterogeneous materials using Al2O3 as an intermediate layer

    DEFF Research Database (Denmark)

    Sahoo, Hitesh Kumar; Ottaviano, Luisa; Zheng, Yi

    2018-01-01

    Integration of heterogeneous materials is crucial for many nanophotonic devices. The integration is often achieved by bonding using polymer adhesives or metals. A much better and cleaner option is direct wafer bonding, but the high annealing temperatures required make it a much less attractive...... atomic layer deposited Al2O3 an excellent choice for the intermediate layer. The authors have optimized the bonding process to achieve a high interface energy of 1.7 J/m2 for a low temperature annealing of 300 °C. The authors also demonstrate wafer bonding of InP to SiO2 on Si and GaAs to sapphire using...

  10. Development of bonded semiconductor device for high counting rate high efficiency photon detectors

    International Nuclear Information System (INIS)

    Kanno, Ikuo

    2008-01-01

    We are trying to decrease dose exposure in medical diagnosis by way of measuring the energy of X-rays. For this purpose, radiation detectors for X-ray energy measurement with high counting rate should be developed. Direct bonding of Si wafers was carried out to make a radiation detector, which had separated X-ray absorber and detector. The resistivity of bonding interface was estimated with the results of four-probe measurements and model calculations. Direct bonding of high resistivity p and n-Si wafers was also performed. The resistance of the pn bonded diode was 0.7 MΩ. The resistance should be increased in the future. (author)

  11. Wafer edge overlay control solution for N7 and beyond

    Science.gov (United States)

    van Haren, Richard; Calado, Victor; van Dijk, Leon; Hermans, Jan; Kumar, Kaushik; Yamashita, Fumiko

    2018-03-01

    Historically, the on-product overlay performance close to the wafer edge is lagging with respect to the inner part of the wafer. The reason for this is that wafer processing is less controlled close to the wafer edge as opposed to the rest of the wafer. It is generally accepted that Chemical Vapor Deposition (CVD) of stressed layers that cause wafer warp, wafer table contamination, Chemical Mechanical Polishing (CMP), and Reactive Ion Etch (RIE) may deteriorate the overlay performance and/or registration close to the wafer edge. For the N7 technology node and beyond, it is anticipated that the tight on-product overlay specification is required across the full wafer which includes the edge region. In this work, we highlight one contributor that may negatively impact the on-product overlay performance, namely the etch step. The focus will be mainly on the wafer edge region but the remaining part of the wafer is considered as well. Three use-cases are examined: multiple Litho-Etch steps (LEn), contact hole layer etch, and the copper dual damascene etch. We characterize the etch contribution by considering the overlay measurement after resist development inspect (ADI) and after etch inspect (AEI). We show that the Yieldstar diffraction based overlay (μDBO) measurements can be utilized to characterize the etch contribution to the overlay budget. The effects of target asymmetry as well as overlay shifts are considered and compared with SEM measurements. Based on the results above, we propose a control solution aiming to reduce or even eliminate the delta between ADI and AEI. By doing so, target/mark to device offsets due to etch might be avoided.

  12. Direct Electroplating on Highly Doped Patterned Silicon Wafers

    NARCIS (Netherlands)

    Vargas Llona, Laura Dolores; Jansen, Henricus V.; Elwenspoek, Michael Curt

    Nickel thin films have been electrodeposited directly on highly doped silicon wafers after removal of the native oxide layer. These substrates conduct sufficiently well to allow deposition using a periferical electrical contact on the wafer. Films 2 μm thick were deposited using a nickel sulfamate

  13. Low-cost silicon wafer dicing using a craft cutter

    KAUST Repository

    Fan, Yiqiang; Carreno, Armando Arpys Arevalo; Li, Huawei; Foulds, Ian G.

    2014-01-01

    feature of 3 mm by 3 mm. We performed this scribing process on the top polished surface of a silicon wafer; we also created a scribing method for the back-unpolished surface in order to protect the structures on the wafer during scribing. Compared

  14. Design and implementation of a novel conical electrode for fast anodic bonding

    International Nuclear Information System (INIS)

    Yang, Chii-Rong; Chang, Long-Yin; Wu, Jim-Wei

    2014-01-01

    Anodic bonding is a frequently used nonintermediate wafer-bonding technique for use in MEMS. However, it has a minimum bonding time for a 4 in silicon/glass wafer that is generally limited to the order of several minutes because of the gas-trapping problem that occurs in the bonded interface when a conventional bonding electrode is used. Therefore, the purpose of this study was to develop a novel conical bonding electrode, which shortens the bonding time and solves the gas-trapping problem of the bonded interface. The 4 in silicon/glass wafers fitted with the proposed electrode exhibited a bonding ratio of 99.89% and an average bonding strength of around 15 MPa, which was attained within 15 s, at a bonding voltage of 900 V and a bonding temperature of 400 °C. A comprehensive series of experiments was performed to validate the excellent bonding performance of the proposed conical electrode. (paper)

  15. Semiconductor industry wafer fab exhaust management

    CERN Document Server

    Sherer, Michael J

    2005-01-01

    Given the myriad exhaust compounds and the corresponding problems that they can pose in an exhaust management system, the proper choice of such systems is a complex task. Presenting the fundamentals, technical details, and general solutions to real-world problems, Semiconductor Industry: Wafer Fab Exhaust Management offers practical guidance on selecting an appropriate system for a given application. Using examples that provide a clear understanding of the concepts discussed, Sherer covers facility layout, support facilities operations, and semiconductor process equipment, followed by exhaust types and challenges. He reviews exhaust point-of-use devices and exhaust line requirements needed between process equipment and the centralized exhaust system. The book includes information on wet scrubbers for a centralized acid exhaust system and a centralized ammonia exhaust system and on centralized equipment to control volatile organic compounds. It concludes with a chapter devoted to emergency releases and a separ...

  16. Chemical polishing of epitoxial silicon wafer

    International Nuclear Information System (INIS)

    Osada, Shohei

    1978-01-01

    SSD telescopes are used for the determination of the kind and energy of charged particles produced by nuclear reactions, and are the equipments combining ΔE counters and E counters. The ΔE counter is a thin SSD which is required to be thin and homogeneous enough to get the high resolution of measurement. The SSDs for ΔE counters have so far been obtained by polishing silicon plates mechanically and chemically or by applying electrolytic polishing method on epitaxial silicon wafers, but it was very hard to obtain them. The creative etching equipment and technique developed this time make it possible to obtain thin SSDs for ΔE counters. The outline of the etching equipment and its technique are described in the report. The etching technique applied for the silicon films for ΔE counters with thickness of about 10 μm was able to be experimentally established in this study. (Kobatake, H.)

  17. Thermoelectric properties of boron and boron phosphide CVD wafers

    Energy Technology Data Exchange (ETDEWEB)

    Kumashiro, Y.; Yokoyama, T.; Sato, A.; Ando, Y. [Yokohama National Univ. (Japan)

    1997-10-01

    Electrical and thermal conductivities and thermoelectric power of p-type boron and n-type boron phosphide wafers with amorphous and polycrystalline structures were measured up to high temperatures. The electrical conductivity of amorphous boron wafers is compatible to that of polycrystals at high temperatures and obeys Mott`s T{sup -{1/4}} rule. The thermoelectric power of polycrystalline boron decreases with increasing temperature, while that of amorphous boron is almost constant in a wide temperature range. The weak temperature dependence of the thermal conductivity of BP polycrystalline wafers reflects phonon scattering by grain boundaries. Thermal conductivity of an amorphous boron wafer is almost constant in a wide temperature range, showing a characteristic of a glass. The figure of merit of polycrystalline BP wafers is 10{sup -7}/K at high temperatures while that of amorphous boron is 10{sup -5}/K.

  18. Reticle variation influence on manufacturing line and wafer device performance

    Science.gov (United States)

    Nistler, John L.; Spurlock, Kyle

    1994-01-01

    Cost effective manufacturing of devices at 0.5, 0.35 and 0.25μm geometries will be highly dependent on a companys' ability to obtain an economic return on investment. The high capital investment in equipment and facilities, not to mention the related chemical and wafer costs, for producing 200mm silicon wafers requires aspects of wafer processing to be tightly controlled. Reduction in errors and enhanced yield management requires early correction or avoidance of reticle problems. It is becoming increasingly important to recognize and track all pertinent factors impacting both the technical and financial viability of a wafer manufacturing fabrication area. Reticle related effects on wafer manufacturing can be costly and affect the total quality perceived by the device customer.

  19. Graphitized silicon carbide microbeams: wafer-level, self-aligned graphene on silicon wafers

    International Nuclear Information System (INIS)

    Cunning, Benjamin V; Ahmed, Mohsin; Mishra, Neeraj; Kermany, Atieh Ranjbar; Iacopi, Francesca; Wood, Barry

    2014-01-01

    Currently proven methods that are used to obtain devices with high-quality graphene on silicon wafers involve the transfer of graphene flakes from a growth substrate, resulting in fundamental limitations for large-scale device fabrication. Moreover, the complex three-dimensional structures of interest for microelectromechanical and nanoelectromechanical systems are hardly compatible with such transfer processes. Here, we introduce a methodology for obtaining thousands of microbeams, made of graphitized silicon carbide on silicon, through a site-selective and wafer-scale approach. A Ni-Cu alloy catalyst mediates a self-aligned graphitization on prepatterned SiC microstructures at a temperature that is compatible with silicon technologies. The graphene nanocoating leads to a dramatically enhanced electrical conductivity, which elevates this approach to an ideal method for the replacement of conductive metal films in silicon carbide-based MEMS and NEMS devices. (paper)

  20. Bond Issues.

    Science.gov (United States)

    Pollack, Rachel H.

    2000-01-01

    Notes trends toward increased borrowing by colleges and universities and offers guidelines for institutions that are considering issuing bonds to raise money for capital projects. Discussion covers advantages of using bond financing, how use of bonds impacts on traditional fund raising, other cautions and concerns, and some troubling aspects of…

  1. Influence of Wafer Edge Geometry on Removal Rate Profile in Chemical Mechanical Polishing: Wafer Edge Roll-Off and Notch

    Science.gov (United States)

    Fukuda, Akira; Fukuda, Tetsuo; Fukunaga, Akira; Tsujimura, Manabu

    2012-05-01

    In the chemical mechanical polishing (CMP) process, uniform polishing up to near the wafer edge is essential to reduce edge exclusion and improve yield. In this study, we examine the influences of inherent wafer edge geometries, i.e., wafer edge roll-off and notch, on the CMP removal rate profile. We clarify the areas in which the removal rate profile is affected by the wafer edge roll-off and the notch, as well as the intensity of their effects on the removal rate profile. In addition, we propose the use of a small notch to reduce the influence of the wafer notch and present the results of an examination by finite element method (FEM) analysis.

  2. Wafer-Level Packaging Method for RF MEMS Applications Using Pre-Patterned BCB Polymer

    Directory of Open Access Journals (Sweden)

    Zhuhao Gong

    2018-02-01

    Full Text Available A radio-frequency micro-electro-mechanical system (RF MEMS wafer-level packaging (WLP method using pre-patterned benzo-cyclo-butene (BCB polymers with a high-resistivity silicon cap is proposed to achieve high bonding quality and excellent RF performance. In this process, the BCB polymer was pre-defined to form the sealing ring and bonding layer by the spin-coating and patterning of photosensitive BCB before the cavity formation. During anisotropic wet etching of the silicon wafer to generate the housing cavity, the BCB sealing ring was protected by a sputtered Cr/Au (chromium/gold layer. The average measured thickness of the BCB layer was 5.9 μm. In contrast to the conventional methods of spin-coating BCB after fabricating cavities, the pre-patterned BCB method presented BCB bonding layers with better quality on severe topography surfaces in terms of increased uniformity of thickness and better surface flatness. The observation of the bonded layer showed that no void or gap formed on the protruding coplanar waveguide (CPW lines. A shear strength test was experimentally implemented as a function of the BCB widths in the range of 100–400 μm. The average shear strength of the packaged device was higher than 21.58 MPa. A RF MEMS switch was successfully packaged using this process with a negligible impact on the microwave characteristics and a significant improvement in the lifetime from below 10 million to over 1 billion. The measured insertion loss of the packaged RF MEMS switch was 0.779 dB and the insertion loss deterioration caused by the package structure was less than 0.2 dB at 30 GHz.

  3. Dislocation behavior of surface-oxygen-concentration controlled Si wafers

    International Nuclear Information System (INIS)

    Asazu, Hirotada; Takeuchi, Shotaro; Sannai, Hiroya; Sudo, Haruo; Araki, Koji; Nakamura, Yoshiaki; Izunome, Koji; Sakai, Akira

    2014-01-01

    We have investigated dislocation behavior in the surface area of surface-oxygen-concentration controlled Si wafers treated by a high temperature rapid thermal oxidation (HT-RTO). The HT-RTO process allows us to precisely control the interstitial oxygen concentration ([O i ]) in the surface area of the Si wafers. Sizes of rosette patterns, generated by nano-indentation and subsequent thermal annealing at 900 °C for 1 h, were measured for the Si wafers with various [O i ]. It was found that the rosette size decreases in proportion to the − 0.25 power of [O i ] in the surface area of the Si wafers, which were higher than [O i ] of 1 × 10 17 atoms/cm 3 . On the other hand, [O i ] of lower than 1 × 10 17 atoms/cm 3 did not affect the rosette size very much. These experimental results demonstrate the ability of the HT-RTO process to suppress the dislocation movements in the surface area of the Si wafer. - Highlights: • Surface-oxygen-concentration controlled Si wafers have been made. • The oxygen concentration was controlled by high temperature rapid thermal oxidation. • Dislocation behavior in the surface area of the Si wafers has been investigated. • Rosette size decreased with increasing of interstitial oxygen atoms. • The interstitial oxygen atoms have a pinning effect of dislocations at the surface

  4. Multifunctional medicated lyophilised wafer dressing for effective chronic wound healing.

    Science.gov (United States)

    Pawar, Harshavardhan V; Boateng, Joshua S; Ayensu, Isaac; Tetteh, John

    2014-06-01

    Wafers combining weight ratios of Polyox with carrageenan (75/25) or sodium alginate (50/50) containing streptomycin and diclofenac were prepared to improve chronic wound healing. Gels were freeze-dried using a lyophilisation cycle incorporating an annealing step. Wafers were characterised for morphology, mechanical and in vitro functional (swelling, adhesion, drug release in the presence of simulated wound fluid) characteristics. Both blank (BLK) and drug-loaded (DL) wafers were soft, flexible, elegant in appearance and non-brittle in nature. Annealing helped to improve porous nature of wafers but was affected by the addition of drugs. Mechanical characterisation demonstrated that the wafers were strong enough to withstand normal stresses but also flexible to prevent damage to newly formed skin tissue. Differences in swelling, adhesion and drug release characteristics could be attributed to differences in pore size and sodium sulphate formed because of the salt forms of the two drugs. BLK wafers showed relatively higher swelling and adhesion than DL wafers with the latter showing controlled release of streptomycin and diclofenac. The optimised dressing has the potential to reduce bacterial infection and can also help to reduce swelling and pain associated with injury due to the anti-inflammatory action of diclofenac and help to achieve more rapid wound healing. © 2014 Wiley Periodicals, Inc. and the American Pharmacists Association.

  5. The uses of Man-Made diamond in wafering applications

    Science.gov (United States)

    Fallon, D. B.

    1982-01-01

    The continuing, rapid growth of the semiconductor industry requires the involvement of several specialized industries in the development of special products geared toward the unique requirements of this new industry. A specialized manufactured diamond to meet various material removal needs was discussed. The area of silicon wafer slicing has presented yet anothr challenge and it is met most effectively. The history, operation, and performance of Man-Made diamond and particularly as applied to silicon wafer slicing is discussed. Product development is underway to come up with a diamond specifically for sawing silicon wafers on an electroplated blade.

  6. Influence of Si wafer thinning processes on (sub)surface defects

    Energy Technology Data Exchange (ETDEWEB)

    Inoue, Fumihiro, E-mail: fumihiro.inoue@imec.be [Imec, Kapeldreef 75, 3001 Leuven (Belgium); Jourdain, Anne; Peng, Lan; Phommahaxay, Alain; De Vos, Joeri; Rebibis, Kenneth June; Miller, Andy; Sleeckx, Erik; Beyne, Eric [Imec, Kapeldreef 75, 3001 Leuven (Belgium); Uedono, Akira [Division of Applied Physics, Faculty of Pure and Applied Science, University of Tsukuba, Tsukuba, Ibaraki 305-8573 (Japan)

    2017-05-15

    Highlights: • Mono-vacancy free Si-thinning can be accomplished by combining several thinning techniques. • The grinding damage needs to be removed prior to dry etching, otherwise vacancies remain in the Si at a depth around 0.5 to 2 μm after Si wafer thickness below 5 μm. • The surface of grinding + CMP + dry etching is equivalent mono vacancy level as that of grinding + CMP. - Abstract: Wafer-to-wafer three-dimensional (3D) integration with minimal Si thickness can produce interacting multiple devices with significantly scaled vertical interconnections. Realizing such a thin 3D structure, however, depends critically on the surface and subsurface of the remaining backside Si after the thinning processes. The Si (sub)surface after mechanical grinding has already been characterized fruitfully for a range of few dozen of μm. Here, we expand the characterization of Si (sub)surface to 5 μm thickness after thinning process on dielectric bonded wafers. The subsurface defects and damage layer were investigated after grinding, chemical mechanical polishing (CMP), wet etching and plasma dry etching. The (sub)surface defects were characterized using transmission microscopy, atomic force microscopy, and positron annihilation spectroscopy. Although grinding provides the fastest removal rate of Si, the surface roughness was not compatible with subsequent processing. Furthermore, mechanical damage such as dislocations and amorphous Si cannot be reduced regardless of Si thickness and thin wafer handling systems. The CMP after grinding showed excellent performance to remove this grinding damage, even though the removal amount is 1 μm. For the case of Si thinning towards 5 μm using grinding and CMP, the (sub)surface is atomic scale of roughness without vacancy. For the case of grinding + dry etch, vacancy defects were detected in subsurface around 0.5–2 μm. The finished surface after wet etch remains in the nm scale in the strain region. By inserting a CMP step in

  7. Optoelectronic interconnects for 3D wafer stacks

    Science.gov (United States)

    Ludwig, David; Carson, John C.; Lome, Louis S.

    1996-01-01

    Wafer and chip stacking are envisioned as means of providing increased processing power within the small confines of a three-dimensional structure. Optoelectronic devices can play an important role in these dense 3-D processing electronic packages in two ways. In pure electronic processing, optoelectronics can provide a method for increasing the number of input/output communication channels within the layers of the 3-D chip stack. Non-free space communication links allow the density of highly parallel input/output ports to increase dramatically over typical edge bus connections. In hybrid processors, where electronics and optics play a role in defining the computational algorithm, free space communication links are typically utilized for, among other reasons, the increased network link complexity which can be achieved. Free space optical interconnections provide bandwidths and interconnection complexity unobtainable in pure electrical interconnections. Stacked 3-D architectures can provide the electronics real estate and structure to deal with the increased bandwidth and global information provided by free space optical communications. This paper will provide definitions and examples of 3-D stacked architectures in optoelectronics processors. The benefits and issues of these technologies will be discussed.

  8. development and evaluation of lyophilized thiolated-chitosan wafers

    African Journals Online (AJOL)

    User

    THIOLATED-CHITOSAN WAFERS FOR BUCCAL DELIVERY. OF PROTEIN ... of the thiolated polymer incorporating per polymer weight, 10 % each of glycerol as plasticizer, D-mannitol as ..... delivery systems: in vitro stability, in vivo fate, and ...

  9. Parental Bonding

    Directory of Open Access Journals (Sweden)

    T. Paul de Cock

    2014-08-01

    Full Text Available Estimating the early parent–child bonding relationship can be valuable in research and practice. Retrospective dimensional measures of parental bonding provide a means for assessing the experience of the early parent–child relationship. However, combinations of dimensional scores may provide information that is not readily captured with a dimensional approach. This study was designed to assess the presence of homogeneous groups in the population with similar profiles on parental bonding dimensions. Using a short version of the Parental Bonding Instrument (PBI, three parental bonding dimensions (care, authoritarianism, and overprotection were used to assess the presence of unobserved groups in the population using latent profile analysis. The class solutions were regressed on 23 covariates (demographics, parental psychopathology, loss events, and childhood contextual factors to assess the validity of the class solution. The results indicated four distinct profiles of parental bonding for fathers as well as mothers. Parental bonding profiles were significantly associated with a broad range of covariates. This person-centered approach to parental bonding has broad utility in future research which takes into account the effect of parent–child bonding, especially with regard to “affectionless control” style parenting.

  10. Automated reticle inspection data analysis for wafer fabs

    Science.gov (United States)

    Summers, Derek; Chen, Gong; Reese, Bryan; Hutchinson, Trent; Liesching, Marcus; Ying, Hai; Dover, Russell

    2009-04-01

    To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the event reticle defects are suspected of causing repeating wafer defects on a completed wafer, potential defects on all associated reticles must be manually searched on a layer-by-layer basis in an effort to identify the reticle responsible for the wafer yield loss. This 'problem reticle' search process is a very tedious and time-consuming task and may cause extended manufacturing line-down situations. Often times, Process Engineers and other team members need to manually investigate several reticle inspection reports to determine if yield loss can be tied to a specific layer. Because of the very nature of this detailed work, calculation errors may occur resulting in an incorrect root cause analysis effort. These delays waste valuable resources that could be spent working on other more productive activities. This paper examines an automated software solution for converting KLA-Tencor reticle inspection defect maps into a format compatible with KLA-Tencor's Klarity Defect(R) data analysis database. The objective is to use the graphical charting capabilities of Klarity Defect to reveal a clearer understanding of defect trends for individual reticle layers or entire mask sets. Automated analysis features include reticle defect count trend analysis and potentially stacking reticle defect maps for signature analysis against wafer inspection defect data. Other possible benefits include optimizing reticle inspection sample plans in an effort to support "lean manufacturing" initiatives for wafer fabs.

  11. Defects reduction of Ge epitaxial film in a germanium-on-insulator wafer by annealing in oxygen ambient

    Directory of Open Access Journals (Sweden)

    Kwang Hong Lee

    2015-01-01

    Full Text Available A method to remove the misfit dislocations and reduce the threading dislocations density (TDD in the germanium (Ge epilayer growth on a silicon (Si substrate is presented. The Ge epitaxial film is grown directly on the Si (001 donor wafer using a “three-step growth” approach in a reduced pressure chemical vapour deposition. The Ge epilayer is then bonded and transferred to another Si (001 handle wafer to form a germanium-on-insulator (GOI substrate. The misfit dislocations, which are initially hidden along the Ge/Si interface, are now accessible from the top surface. These misfit dislocations are then removed by annealing the GOI substrate. After the annealing, the TDD of the Ge epilayer can be reduced by at least two orders of magnitude to <5 × 106 cm−2.

  12. SOI silicon on glass for optical MEMS

    DEFF Research Database (Denmark)

    Larsen, Kristian Pontoppidan; Ravnkilde, Jan Tue; Hansen, Ole

    2003-01-01

    and a final sealing at the interconnects can be performed using a suitable polymer. Packaged MEMS on glass are advantageous within Optical MEMS and for sensitive capacitive devices. We report on experiences with bonding SOI to Pyrex. Uniform DRIE shallow and deep etching was achieved by a combination......A newly developed fabrication method for fabrication of single crystalline Si (SCS) components on glass, utilizing Deep Reactive Ion Etching (DRIE) of a Silicon On Insulator (SOI) wafer is presented. The devices are packaged at wafer level in a glass-silicon-glass (GSG) stack by anodic bonding...... of an optimized device layout and an optimized process recipe. The behavior of the buried oxide membrane when used as an etch stop for the through-hole etch is described. No harmful buckling or fracture of the membrane is observed for an oxide thickness below 1 μm, but larger and more fragile released structures...

  13. Guided ultrasonic wave beam skew in silicon wafers

    Science.gov (United States)

    Pizzolato, Marco; Masserey, Bernard; Robyr, Jean-Luc; Fromme, Paul

    2018-04-01

    In the photovoltaic industry, monocrystalline silicon wafers are employed for solar cells with high conversion efficiency. Micro-cracks induced by the cutting process in the thin wafers can lead to brittle wafer fracture. Guided ultrasonic waves would offer an efficient methodology for the in-process non-destructive testing of wafers to assess micro-crack density. The material anisotropy of the monocrystalline silicon leads to variations of the guided wave characteristics, depending on the propagation direction relative to the crystal orientation. Selective guided ultrasonic wave excitation was achieved using a contact piezoelectric transducer with custom-made wedges for the A0 and S0 Lamb wave modes and a transducer holder to achieve controlled contact pressure and orientation. The out-of-plane component of the guided wave propagation was measured using a non-contact laser interferometer. The phase slowness (velocity) of the two fundamental Lamb wave modes was measured experimentally for varying propagation directions relative to the crystal orientation and found to match theoretical predictions. Significant wave beam skew was observed experimentally, especially for the S0 mode, and investigated from 3D finite element simulations. Good agreement was found with the theoretical predictions based on nominal material properties of the silicon wafer. The important contribution of guided wave beam skewing effects for the non-destructive testing of silicon wafers was demonstrated.

  14. Full Wafer Redistribution and Wafer Embedding as Key Technologies for a Multi-Scale Neuromorphic Hardware Cluster

    OpenAIRE

    Zoschke, Kai; Güttler, Maurice; Böttcher, Lars; Grübl, Andreas; Husmann, Dan; Schemmel, Johannes; Meier, Karlheinz; Ehrmann, Oswin

    2018-01-01

    Together with the Kirchhoff-Institute for Physics(KIP) the Fraunhofer IZM has developed a full wafer redistribution and embedding technology as base for a large-scale neuromorphic hardware system. The paper will give an overview of the neuromorphic computing platform at the KIP and the associated hardware requirements which drove the described technological developments. In the first phase of the project standard redistribution technologies from wafer level packaging were adapted to enable a ...

  15. Wafer Scale Integration of CMOS Chips for Biomedical Applications via Self-Aligned Masking.

    Science.gov (United States)

    Uddin, Ashfaque; Milaninia, Kaveh; Chen, Chin-Hsuan; Theogarajan, Luke

    2011-12-01

    This paper presents a novel technique for the integration of small CMOS chips into a large area substrate. A key component of the technique is the CMOS chip based self-aligned masking. This allows for the fabrication of sockets in wafers that are at most 5 µm larger than the chip on each side. The chip and the large area substrate are bonded onto a carrier such that the top surfaces of the two components are flush. The unique features of this technique enable the integration of macroscale components, such as leads and microfluidics. Furthermore, the integration process allows for MEMS micromachining after CMOS die-wafer integration. To demonstrate the capabilities of the proposed technology, a low-power integrated potentiostat chip for biosensing implemented in the AMI 0.5 µm CMOS technology is integrated in a silicon substrate. The horizontal gap and the vertical displacement between the chip and the large area substrate measured after the integration were 4 µm and 0.5 µm, respectively. A number of 104 interconnects are patterned with high-precision alignment. Electrical measurements have shown that the functionality of the chip is not affected by the integration process.

  16. Preparation and characterisation of immobilised humic acid on silicon wafer

    International Nuclear Information System (INIS)

    Szabo, Gy.; Guczi, J.; Telegdi, J.; Pashalidis, I.; Szymczak, W.; Buckau, G.

    2005-01-01

    Full text of publication follows: The chemistry of the interactions of radionuclides with humic acid needs to be understood in details so that humate-mediated migration of radionuclides through the environment can be predicted. To achieve such a data in microscopic scale, several detective techniques, such as atomic force microscopy (AFM), chemical force microscopy (CFM), nuclear microprobe analysis (NMA) and X-ray photoelectron spectroscopy (XPS) can be used to measure intermolecular forces and to visualize the surface morphology. The main aim of this work was to provide humic material with specific properties in order to study with different spectroscopic techniques, the complexation behaviour of surface bound humic acid in microscopic scale. Namely, humic acid has been immobilised on silicon wafers in order to mimic surface bound humic substances in natural aquatic systems. In this communication, we present a simple protocol to immobilize humic acid on silicon wafer surface. A tri-functional silane reagent 3-amino-propyl-tri-methoxy-silane (APTES) was used to modify the surface of silicon wafers and appeared to be able to strongly attached soluble humic acid through their carboxylic groups to solid support. Characterisation of the surfaces, after any preparation steps, was done by ATR-FTIR, AFM and TOF-SIMS. These methods have proved that the humic acid forms a relatively homogeneous layer on the wafers. Immobilisation of humic acid on silicon wafer was further proved by binding isotherm of Am/Nd. (authors)

  17. Nonlinear resonance ultrasonic vibrations in Czochralski-silicon wafers

    Science.gov (United States)

    Ostapenko, S.; Tarasov, I.

    2000-04-01

    A resonance effect of generation of subharmonic acoustic vibrations is observed in as-grown, oxidized, and epitaxial silicon wafers. Ultrasonic vibrations were generated into a standard 200 mm Czochralski-silicon (Cz-Si) wafer using a circular ultrasound transducer with major frequency of the radial vibrations at about 26 kHz. By tuning frequency (f) of the transducer within a resonance curve, we observed a generation of intense f/2 subharmonic acoustic mode assigned as a "whistle." The whistle mode has a threshold amplitude behavior and narrow frequency band. The whistle is attributed to a nonlinear acoustic vibration of a silicon plate. It is demonstrated that characteristics of the whistle mode are sensitive to internal stress and can be used for quality control and in-line diagnostics of oxidized and epitaxial Cz-Si wafers.

  18. Wafer-scale fabrication of polymer distributed feedback lasers

    DEFF Research Database (Denmark)

    Christiansen, Mads Brøkner; Schøler, Mikkel; Balslev, Søren

    2006-01-01

    The authors demonstrate wafer-scale, parallel process fabrication of distributed feedback (DFB) polymer dye lasers by two different nanoimprint techniques: By thermal nanoimprint lithography (TNIL) in polymethyl methacrylate and by combined nanoimprint and photolithography (CNP) in SU-8. In both...... techniques, a thin film of polymer, doped with rhodamine-6G laser dye, is spin coated onto a Borofloat glass buffer substrate and shaped into a planar waveguide slab with first order DFB surface corrugations forming the laser resonator. When optically pumped at 532 nm, lasing is obtained in the wavelength...... range between 576 and 607 nm, determined by the grating period. The results, where 13 laser devices are defined across a 10 cm diameter wafer substrate, demonstrate the feasibility of NIL and CNP for parallel wafer-scale fabrication of advanced nanostructured active optical polymer components...

  19. Uniformity across 200 mm silicon wafers printed by nanoimprint lithography

    International Nuclear Information System (INIS)

    Gourgon, C; Perret, C; Tallal, J; Lazzarino, F; Landis, S; Joubert, O; Pelzer, R

    2005-01-01

    Uniformity of the printing process is one of the key parameters of nanoimprint lithography. This technique has to be extended to large size wafers to be useful for several industrial applications, and the uniformity of micro and nanostructures has to be guaranteed on large surfaces. This paper presents results of printing on 200 mm diameter wafers. The residual thickness uniformity after printing is demonstrated at the wafer scale in large patterns (100 μm), in smaller lines of 250 nm and in sub-100 nm features. We show that a mould deformation occurs during the printing process, and that this deformation is needed to guarantee printing uniformity. However, the mould deformation is also responsible for the potential degradation of the patterns

  20. PMMA to SU-8 Bonding for Polymer Based Lab-on-a-chip Systems with Integrated Optics

    DEFF Research Database (Denmark)

    Olsen, Brian Bilenberg; Nielsen, Theodor; Nilsson, Daniel

    2003-01-01

    An adhesive bonding technique for wafer-level sealing of SU-8 based lab-on-a-chip microsystems with integrated optical components is presented. Microfluidic channels and optical components, e.g. waveguides, are fabricated in cross-linked SU-8 and sealed with a Pyrex glass substrate by means...... strength of 16 MPa is achieved at bonding temperatures between 110 oC and 120oC, at a bonding force of 2000 N on a 4-inch wafer. The optical propagation loss of multi-mode 10ym (thickness)x 30ym (width)SU-8 waveguides is measured. The propagation loss in PMMA bonded waveguide struc-tures is more than 5 d......B/cm lower, at wavelengths between 600nm and 900 nm, than in similar structures bonded by an intermediate layer of SU-8. Furthermore 950K PMMA shows no tendency to flow into the bonded structures during bonding because of its high viscosity....

  1. Protection of MOS capacitors during anodic bonding

    Science.gov (United States)

    Schjølberg-Henriksen, K.; Plaza, J. A.; Rafí, J. M.; Esteve, J.; Campabadal, F.; Santander, J.; Jensen, G. U.; Hanneborg, A.

    2002-07-01

    We have investigated the electrical damage by anodic bonding on CMOS-quality gate oxide and methods to prevent this damage. n-type and p-type MOS capacitors were characterized by quasi-static and high-frequency CV-curves before and after anodic bonding. Capacitors that were bonded to a Pyrex wafer with 10 μm deep cavities enclosing the capacitors exhibited increased leakage current and interface trap density after bonding. Two different methods were successful in protecting the capacitors from such damage. Our first approach was to increase the cavity depth from 10 μm to 50 μm, thus reducing the electric field across the gate oxide during bonding from approximately 2 × 105 V cm-1 to 4 × 104 V cm-1. The second protection method was to coat the inside of a 10 μm deep Pyrex glass cavity with aluminium, forming a Faraday cage that removed the electric field across the cavity during anodic bonding. Both methods resulted in capacitors with decreased interface trap density and unchanged leakage current after bonding. No change in effective oxide charge or mobile ion contamination was observed on any of the capacitors in the study.

  2. 450mm wafer patterning with jet and flash imprint lithography

    Science.gov (United States)

    Thompson, Ecron; Hellebrekers, Paul; Hofemann, Paul; LaBrake, Dwayne L.; Resnick, Douglas J.; Sreenivasan, S. V.

    2013-09-01

    The next step in the evolution of wafer size is 450mm. Any transition in sizing is an enormous task that must account for fabrication space, environmental health and safety concerns, wafer standards, metrology capability, individual process module development and device integration. For 450mm, an aggressive goal of 2018 has been set, with pilot line operation as early as 2016. To address these goals, consortiums have been formed to establish the infrastructure necessary to the transition, with a focus on the development of both process and metrology tools. Central to any process module development, which includes deposition, etch and chemical mechanical polishing is the lithography tool. In order to address the need for early learning and advance process module development, Molecular Imprints Inc. has provided the industry with the first advanced lithography platform, the Imprio® 450, capable of patterning a full 450mm wafer. The Imprio 450 was accepted by Intel at the end of 2012 and is now being used to support the 450mm wafer process development demands as part of a multi-year wafer services contract to facilitate the semiconductor industry's transition to lower cost 450mm wafer production. The Imprio 450 uses a Jet and Flash Imprint Lithography (J-FILTM) process that employs drop dispensing of UV curable resists to assist high resolution patterning for subsequent dry etch pattern transfer. The technology is actively being used to develop solutions for markets including NAND Flash memory, patterned media for hard disk drives and displays. This paper reviews the recent performance of the J-FIL technology (including overlay, throughput and defectivity), mask development improvements provided by Dai Nippon Printing, and the application of the technology to a 450mm lithography platform.

  3. Very large scale heterogeneous integration (VLSHI) and wafer-level vacuum packaging for infrared bolometer focal plane arrays

    Science.gov (United States)

    Forsberg, Fredrik; Roxhed, Niclas; Fischer, Andreas C.; Samel, Björn; Ericsson, Per; Hoivik, Nils; Lapadatu, Adriana; Bring, Martin; Kittilsland, Gjermund; Stemme, Göran; Niklaus, Frank

    2013-09-01

    Imaging in the long wavelength infrared (LWIR) range from 8 to 14 μm is an extremely useful tool for non-contact measurement and imaging of temperature in many industrial, automotive and security applications. However, the cost of the infrared (IR) imaging components has to be significantly reduced to make IR imaging a viable technology for many cost-sensitive applications. This paper demonstrates new and improved fabrication and packaging technologies for next-generation IR imaging detectors based on uncooled IR bolometer focal plane arrays. The proposed technologies include very large scale heterogeneous integration for combining high-performance, SiGe quantum-well bolometers with electronic integrated read-out circuits and CMOS compatible wafer-level vacuum packing. The fabrication and characterization of bolometers with a pitch of 25 μm × 25 μm that are arranged on read-out-wafers in arrays with 320 × 240 pixels are presented. The bolometers contain a multi-layer quantum well SiGe thermistor with a temperature coefficient of resistance of -3.0%/K. The proposed CMOS compatible wafer-level vacuum packaging technology uses Cu-Sn solid-liquid interdiffusion (SLID) bonding. The presented technologies are suitable for implementation in cost-efficient fabless business models with the potential to bring about the cost reduction needed to enable low-cost IR imaging products for industrial, security and automotive applications.

  4. High Performance Microaccelerometer with Wafer-level Hermetic Packaged Sensing Element and Continuous-time BiCMOS Interface Circuit

    International Nuclear Information System (INIS)

    Ko, Hyoungho; Park, Sangjun; Paik, Seung-Joon; Choi, Byoung-doo; Park, Yonghwa; Lee, Sangmin; Kim, Sungwook; Lee, Sang Chul; Lee, Ahra; Yoo, Kwangho; Lim, Jaesang; Cho, Dong-il

    2006-01-01

    A microaccelerometer with highly reliable, wafer-level packaged MEMS sensing element and fully differential, continuous time, low noise, BiCMOS interface circuit is fabricated. The MEMS sensing element is fabricated on a (111)-oriented SOI wafer by using the SBM (Sacrificial/Bulk Micromachining) process. To protect the silicon structure of the sensing element and enhance the reliability, a wafer level hermetic packaging process is performed by using a silicon-glass anodic bonding process. The interface circuit is fabricated using 0.8 μm BiCMOS process. The capacitance change of the MEMS sensing element is amplified by the continuous-time, fully-differential transconductance input amplifier. A chopper-stabilization architecture is adopted to reduce low-frequency noise including 1/f noise. The fabricated microaccelerometer has the total noise equivalent acceleration of 0.89 μg/√Hz, the bias instability of 490 μg, the input range of ±10 g, and the output nonlinearity of ±0.5 %FSO

  5. Wafer scale integration of catalyst dots into nonplanar microsystems

    DEFF Research Database (Denmark)

    Gjerde, Kjetil; Kjelstrup-Hansen, Jakob; Gammelgaard, Lauge

    2007-01-01

    In order to successfully integrate bottom-up fabricated nanostructures such as carbon nanotubes or silicon, germanium, or III-V nanowires into microelectromechanical systems on a wafer scale, reliable ways of integrating catalyst dots are needed. Here, four methods for integrating sub-100-nm...... diameter nickel catalyst dots on a wafer scale are presented and compared. Three of the methods are based on a p-Si layer utilized as an in situ mask, an encapsulating layer, and a sacrificial window mask, respectively. All methods enable precise positioning of nickel catalyst dots at the end...

  6. Computational Modeling in Plasma Processing for 300 mm Wafers

    Science.gov (United States)

    Meyyappan, Meyya; Arnold, James O. (Technical Monitor)

    1997-01-01

    Migration toward 300 mm wafer size has been initiated recently due to process economics and to meet future demands for integrated circuits. A major issue facing the semiconductor community at this juncture is development of suitable processing equipment, for example, plasma processing reactors that can accomodate 300 mm wafers. In this Invited Talk, scaling of reactors will be discussed with the aid of computational fluid dynamics results. We have undertaken reactor simulations using CFD with reactor geometry, pressure, and precursor flow rates as parameters in a systematic investigation. These simulations provide guidelines for scaling up in reactor design.

  7. Wafer-Level Vacuum Packaging of Smart Sensors

    OpenAIRE

    Hilton, Allan; Temple, Dorota S.

    2016-01-01

    The reach and impact of the Internet of Things will depend on the availability of low-cost, smart sensors—“low cost” for ubiquitous presence, and “smart” for connectivity and autonomy. By using wafer-level processes not only for the smart sensor fabrication and integration, but also for packaging, we can further greatly reduce the cost of sensor components and systems as well as further decrease their size and weight. This paper reviews the state-of-the-art in the wafer-level vacuum packaging...

  8. Friction mechanisms of silicon wafer and silicon wafer coated with diamond-like carbon film and two monolayers

    International Nuclear Information System (INIS)

    Singh, R. Arvind; Yoon, Eui Sung; Han, Hung Gu; Kong, Ho Sung

    2006-01-01

    The friction behaviour of Si-wafer, Diamond-Like Carbon (DLC) and two Self-Assembled Monolayers(SAMs) namely DiMethylDiChlorosilane (DMDC) and DiPhenyl-DiChlorosilane (DPDC) coated on Si-wafer was studied under loading conditions in milli-Newton (mN) range. Experiments were performed using a ball-on-flat type reciprocating micro-tribo tester. Glass balls with various radii 0.25 mm, 0.5 mm and 1 mm were used. The applied normal load was in the range of 1.5 mN to 4.8 mN. Results showed that the friction increased with the applied normal load in the case of all the test materials. It was also observed that friction was affected by the ball size. Friction increased with the increase in the ball size in the case of Si-wafer. The SAMs also showed a similar trend, but had lower values of friction than those of Si-wafer. Interestingly, for DLC it was observed that friction decreased with the increase in the ball size. This distinct difference in the behavior of friction in DLC was attributed to the difference in the operating mechanism. It was observed that Si-wafer and DLC exhibited wear, whereas wear was absent in the SAMs. Observations showed that solid-solid adhesion was dominant in Si-wafer, while plowing in DLC. The wear in these two materials significantly influenced their friction. In the case of SAMs their friction behaviour was largely influenced by the nature of their molecular chains

  9. Scatterometry on pelliclized masks: an option for wafer fabs

    Science.gov (United States)

    Gallagher, Emily; Benson, Craig; Higuchi, Masaru; Okumoto, Yasuhiro; Kwon, Michael; Yedur, Sanjay; Li, Shifang; Lee, Sangbong; Tabet, Milad

    2007-03-01

    Optical scatterometry-based metrology is now widely used in wafer fabs for lithography, etch, and CMP applications. This acceptance of a new metrology method occurred despite the abundance of wellestablished CD-SEM and AFM methods. It was driven by the desire to make measurements faster and with a lower cost of ownership. Over the last year, scatterometry has also been introduced in advanced mask shops for mask measurements. Binary and phase shift masks have been successfully measured at all desired points during photomask production before the pellicle is mounted. There is a significant benefit to measuring masks with the pellicle in place. From the wafer fab's perspective, through-pellicle metrology would verify mask effects on the same features that are characterized on wafer. On-site mask verification would enable quality control and trouble-shooting without returning the mask to a mask house. Another potential application is monitoring changes to mask films once the mask has been delivered to the fab (haze, oxide growth, etc.). Similar opportunities apply to the mask metrologist receiving line returns from a wafer fab. The ability to make line-return measurements without risking defect introduction is clearly attractive. This paper will evaluate the feasibility of collecting scatterometry data on pelliclized masks. We explore the effects of several different pellicle types on scatterometry measurements made with broadband light in the range of 320-780 nm. The complexity introduced by the pellicles' optical behavior will be studied.

  10. Prediction of thermo-mechanical reliability of wafer backend processes

    NARCIS (Netherlands)

    Gonda, V.; Toonder, den J.M.J.; Beijer, J.G.J.; Zhang, G.Q.; van Driel, W.D.; Hoofman, R.J.O.M.; Ernst, L.J.

    2004-01-01

    More than 65% of IC failures are related to thermal and mechanical problems. For wafer backend processes, thermo-mechanical failure is one of the major bottlenecks. The ongoing technological trends like miniaturization, introduction of new materials, and function/product integration will increase

  11. Prediction of thermo-mechanical integrity of wafer backend processes

    NARCIS (Netherlands)

    Gonda, V.; Toonder, den J.M.J.; Beijer, J.G.J.; Zhang, G.Q.; Hoofman, R.J.O.M.; Ernst, L.J.; Ernst, L.J.

    2003-01-01

    More than 65% of IC failures are related to thermal and mechanical problems. For wafer backend processes, thermo-mechanical failure is one of the major bottlenecks. The ongoing technological trends like miniaturization, introduction of new materials, and function/product integration will increase

  12. High frequency guided wave propagation in monocrystalline silicon wafers

    Science.gov (United States)

    Pizzolato, Marco; Masserey, Bernard; Robyr, Jean-Luc; Fromme, Paul

    2017-04-01

    Monocrystalline silicon wafers are widely used in the photovoltaic industry for solar panels with high conversion efficiency. The cutting process can introduce micro-cracks in the thin wafers and lead to varying thickness. High frequency guided ultrasonic waves are considered for the structural monitoring of the wafers. The anisotropy of the monocrystalline silicon leads to variations of the wave characteristics, depending on the propagation direction relative to the crystal orientation. Full three-dimensional Finite Element simulations of the guided wave propagation were conducted to visualize and quantify these effects for a line source. The phase velocity (slowness) and skew angle of the two fundamental Lamb wave modes (first anti-symmetric mode A0 and first symmetric mode S0) for varying propagation directions relative to the crystal orientation were measured experimentally. Selective mode excitation was achieved using a contact piezoelectric transducer with a custom-made wedge and holder to achieve a controlled contact pressure. The out-of-plane component of the guided wave propagation was measured using a noncontact laser interferometer. Good agreement was found with the simulation results and theoretical predictions based on nominal material properties of the silicon wafer.

  13. Bonds Boom.

    Science.gov (United States)

    Reynolds, Cathryn

    1989-01-01

    The combined effect of the "Serrano" decision and Proposition 13 left California school districts with aging, overcrowded facilities. Chico schools won a $18.5 million general obligation bond election for facilities construction. With $11 billion needed for new school construction, California will need to tap local sources. A sidebar…

  14. Trace analysis for 300 MM wafers and processes with TXRF

    International Nuclear Information System (INIS)

    Nutsch, A.; Erdmann, V.; Zielonka, G.; Pfitzner, L.; Ryssel, H.

    2000-01-01

    Efficient fabrication of semiconductor devices is combined with an increasing size of silicon wafers. The contamination level of processes, media, and equipment has to decrease continuously. A new test laboratory for 300 mm was installed in view of the above mentioned aspects. Aside of numerous processing tools this platform consist electrical test methods, particle detection, vapor phase decomposition (VPD) preparation, and TXRF. The equipment is installed in a cleanroom. It is common to perform process or equipment control, development, evaluation and qualification with monitor wafers. The evaluation and the qualification of 300 mm equipment require direct TXRF on 300 mm wafers. A new TXRF setup was installed due to the wafer size of 300 mm. The 300 mm TXRF is equipped with tungsten and molybdenum anode. This combination allows a sensitive detection of elements with fluorescence energy below 10 keV for tungsten excitation. The molybdenum excitation enables the detection of a wide variety of elements. The detection sensitivity for the tungsten anode excited samples is ten times higher than for molybdenum anode measured samples. The system is calibrated with 1 ng Ni. This calibration shows a stability within 5 % when monitored to control system stability. Decreasing the amount of Ni linear results in a linear decrease of the measured Ni signal. This result is verified for a range of elements by multielement samples. New designs demand new processes and materials, e.g. ferroelectric layers and copper. The trace analysis of many of these materials is supported by the higher excitation energy of the molybdenum anode. Reclaim and recycling of 300 mm wafers demand for an accurate contamination control of the processes to avoid cross contamination. Polishing or etching result in modified surfaces. TXRF as a non-destructive test method allows the simultaneously detection of a variety of elements on differing surfaces in view of contamination control and process

  15. Diffusion bonding

    International Nuclear Information System (INIS)

    Anderson, R.C.

    1976-01-01

    A method is described for joining beryllium to beryllium by diffusion bonding. At least one surface portion of at least two beryllium pieces is coated with nickel. A coated surface portion is positioned in a contiguous relationship with another surface portion and subjected to an environment having an atmosphere at a pressure lower than ambient pressure. A force is applied on the beryllium pieces for causing the contiguous surface portions to abut against each other. The contiguous surface portions are heated to a maximum temperature less than the melting temperature of the beryllium, and the applied force is decreased while increasing the temperature after attaining a temperature substantially above room temperature. A portion of the applied force is maintained at a temperature corresponding to about maximum temperature for a duration sufficient to effect the diffusion bond between the contiguous surface portions

  16. Denuded zone in Czochralski silicon wafer with high carbon content

    International Nuclear Information System (INIS)

    Chen Jiahe; Yang Deren; Ma Xiangyang; Que Duanlin

    2006-01-01

    The thermal stability of the denuded zone (DZ) created by high-low-high-temperature annealing in high carbon content (H[C]) and low carbon content (L[C]) Czochralski silicon (Cz-Si) has been investigated in a subsequent ramping and isothermal 1050 deg. C annealing. The tiny oxygen precipitates which might occur in the DZ were checked. It was found in the L[C] Cz-Si that the DZ shrank and the density of bulk micro-defects (BMDs) reduced with the increase of time spent at 1050 deg. C. Also, the DZs above 15 μm of thickness present in the H[C] Cz-Si wafers continuously and the density and total volume of BMDs first decreased then increased and finally decreased again during the treatments. Moreover, tiny oxygen precipitates were hardly generated inside the DZs, indicating that H[C] Cz-Si wafers could support the fabrication of integrated circuits

  17. Denuded zone in Czochralski silicon wafer with high carbon content

    Science.gov (United States)

    Chen, Jiahe; Yang, Deren; Ma, Xiangyang; Que, Duanlin

    2006-12-01

    The thermal stability of the denuded zone (DZ) created by high-low-high-temperature annealing in high carbon content (H[C]) and low carbon content (L[C]) Czochralski silicon (Cz-Si) has been investigated in a subsequent ramping and isothermal 1050 °C annealing. The tiny oxygen precipitates which might occur in the DZ were checked. It was found in the L[C] Cz-Si that the DZ shrank and the density of bulk micro-defects (BMDs) reduced with the increase of time spent at 1050 °C. Also, the DZs above 15 µm of thickness present in the H[C] Cz-Si wafers continuously and the density and total volume of BMDs first decreased then increased and finally decreased again during the treatments. Moreover, tiny oxygen precipitates were hardly generated inside the DZs, indicating that H[C] Cz-Si wafers could support the fabrication of integrated circuits.

  18. Peptide and protein loading into porous silicon wafers

    Energy Technology Data Exchange (ETDEWEB)

    Prestidge, C.A.; Barnes, T.J.; Mierczynska-Vasilev, A.; Kempson, I.; Peddie, F. [Ian Wark Research Institute, University of South Australia, Mawson Lakes (Australia); Barnett, C. [Medica Ltd, Malvern, Worcestershire, UK WR14 3SZ (United Kingdom)

    2008-02-15

    The influence of peptide/protein size and hydrophobicity on the physical and chemical aspects of loading within porous silicon (pSi) wafer samples has been determined using Atomic Force Microscopy (AFM) and Time-of-Flight Secondary Ion Mass Spectroscopy (ToF-SIMS). Both Gramicidin A (a small hydrophobic peptide) and Papain (a larger hydrophilic protein) were observed (ToF-SIMS) to penetrate across the entire pSi layer, even at low loading levels. AFM surface imaging of pSi wafers during peptide/protein loading showed that surface roughness increased with Papain loading, but decreased with Gramicidin A loading. For Papain, the loading methodology was also found to influence loading efficiency. These differences indicate more pronounced surface adsorption of Papain. (copyright 2008 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

  19. Contacting graphene in a 200 mm wafer silicon technology environment

    Science.gov (United States)

    Lisker, Marco; Lukosius, Mindaugas; Kitzmann, Julia; Fraschke, Mirko; Wolansky, Dirk; Schulze, Sebastian; Lupina, Grzegorz; Mai, Andreas

    2018-06-01

    Two different approaches for contacting graphene in a 200 mm wafer silicon technology environment were tested. The key is the opportunity to create a thin SiN passivation layer on top of the graphene protecting it from the damage by plasma processes. The first approach uses pure Ni contacts with a thickness of 200 nm. For the second attempt, Ni is used as the contact metal which substitutes the Ti compared to a standard contact hole filling process. Accordingly, the contact hole filling of this "stacked via" approach is Ni/TiN/W. We demonstrate that the second "stacked Via" is beneficial and shows contact resistances of a wafer scale process with values below 200 Ohm μm.

  20. JOINT RIGIDITY ASSESSMENT WITH PIEZOELECTRIC WAFERS AND ACOUSTIC WAVES

    International Nuclear Information System (INIS)

    Montoya, Angela C.; Maji, Arup K.

    2010-01-01

    There has been an interest in the development of rapid deployment satellites. In a modular satellite design, different panels of specific functions can be pre-manufactured. The satellite can then be assembled and tested just prior to deployment. Traditional vibration testing is time-consuming and expensive. An alternative test method to evaluate the connection between two plates will be proposed. The method investigated and described employs piezoelectric wafers to induce and sense lamb waves in two aluminum plates, which were joined by steel brackets to form an 'L-Style' joint. Lamb wave behavior and piezoelectric material properties will be discussed; the experimental setup and results will be presented. A set of 4 piezoelectric ceramic wafers were used alternately as source and sensor. The energy transmitted was shown to correlate with a mechanical assessment of the joint, demonstrating that this method of testing is a feasible and reliable way to inspect the rigidity of joints.

  1. A multi-level capacitor-less memory cell fabricated on a nano-scale strained silicon-on-insulator

    International Nuclear Information System (INIS)

    Park, Jea-Gun; Kim, Seong-Je; Shin, Mi-Hee; Song, Seung-Hyun; Shim, Tae-Hun; Chung, Sung-Woong; Enomoto, Hirofumi

    2011-01-01

    A multi-level capacitor-less memory cell was fabricated with a fully depleted n-metal-oxide-semiconductor field-effect transistor on a nano-scale strained silicon channel on insulator (FD sSOI n-MOSFET). The 0.73% biaxial tensile strain in the silicon channel of the FD sSOI n-MOSFET enhanced the effective electron mobility to ∼ 1.7 times that with an unstrained silicon channel. This thereby enables both front- and back-gate cell operations, demonstrating eight-level volatile memory-cell operation with a 1 ms retention time and 12 μA memory margin. This is a step toward achieving a terabit volatile memory cell.

  2. Note: A silicon-on-insulator microelectromechanical systems probe scanner for on-chip atomic force microscopy

    Energy Technology Data Exchange (ETDEWEB)

    Fowler, Anthony G.; Maroufi, Mohammad; Moheimani, S. O. Reza, E-mail: Reza.Moheimani@newcastle.edu.au [School of Electrical Engineering and Computer Science, University of Newcastle, Callaghan, NSW 2308 (Australia)

    2015-04-15

    A new microelectromechanical systems-based 2-degree-of-freedom (DoF) scanner with an integrated cantilever for on-chip atomic force microscopy (AFM) is presented. The silicon cantilever features a layer of piezoelectric material to facilitate its use for tapping mode AFM and enable simultaneous deflection sensing. Electrostatic actuators and electrothermal sensors are used to accurately position the cantilever within the x-y plane. Experimental testing shows that the cantilever is able to be scanned over a 10 μm × 10 μm window and that the cantilever achieves a peak-to-peak deflection greater than 400 nm when excited at its resonance frequency of approximately 62 kHz.

  3. Evaluation of custom-designed lateral power transistors in a silicon-on-insulator process in a synchronous buck converter

    DEFF Research Database (Denmark)

    Okumus, Sinan; Fan, Lin; Nour, Yasser

    2018-01-01

    Most of todays power converters are based on power semiconductors, which are built in vertical power semiconductor processes. These devices result in limited packaging possibilities, which lead to physically long galvanic connections and therefore high external electromagnetic fields. These fields...

  4. Characterization of dielectric materials in thin layers for the development of S.O.I. (Silicon on Insulator) substrates

    International Nuclear Information System (INIS)

    Gruber, Olivier

    1999-01-01

    This thesis deals with the characterization of oxide layer placed inside S.O.I. substrates and submitted to irradiation. This type of material is used for the development of hardened electronic components, that is to say components able to be used in a radiative environment. The irradiation induces charges (electrons or holes) in the recovered oxide. A part of these charges is trapped which leads to changes of the characteristics of the electronic components made on these substrates. The main topic of this study is the characterization of trapping properties of recovered oxides and more particularly of 'Unibond' material carried out with a new fabrication process: the 'smart-cut' process. This work is divided into three parts: - study with one carrier: this case is limited to low radiation doses where is only observed holes trapping. The evolution of the physical and chemical properties of the 'Unibond' material recovered oxide has been revealed, this evolution being due to the fabrication process. - Study with two carriers: in this case, there is trapping of holes and electrons. This type of trapping is observed in the case of strong radiation doses. A new type of electrons traps has been identified with the 'Unibond' material oxide. The transport and the trapping of holes and electrons have been studied in the case of transient phenomena created by short radiative pulses. This study has been carried out using a new measurement method. - Study with three carriers: here are added to holes and electrons the protons introduced in the recovered oxide by the annealing under hydrogen. These protons are movable when they are submitted to the effect of an electric field and they induce a memory effect according to their position in the oxide. These different works show that the 'Unibond' material is a very good solution for the future development of S.O.I. (author) [fr

  5. SEMICONDUCTOR DEVICES: Two-dimensional threshold voltage analytical model of DMG strained-silicon-on-insulator MOSFETs

    Science.gov (United States)

    Jin, Li; Hongxia, Liu; Bin, Li; Lei, Cao; Bo, Yuan

    2010-08-01

    For the first time, a simple and accurate two-dimensional analytical model for the surface potential variation along the channel in fully depleted dual-material gate strained-Si-on-insulator (DMG SSOI) MOSFETs is developed. We investigate the improved short channel effect (SCE), hot carrier effect (HCE), drain-induced barrier-lowering (DIBL) and carrier transport efficiency for the novel structure MOSFET. The analytical model takes into account the effects of different metal gate lengths, work functions, the drain bias and Ge mole fraction in the relaxed SiGe buffer. The surface potential in the channel region exhibits a step potential, which can suppress SCE, HCE and DIBL. Also, strained-Si and SOI structure can improve the carrier transport efficiency, with strained-Si being particularly effective. Further, the threshold voltage model correctly predicts a “rollup" in threshold voltage with decreasing channel length ratios or Ge mole fraction in the relaxed SiGe buffer. The validity of the two-dimensional analytical model is verified using numerical simulations.

  6. Design of photonic phased array switches using nano electromechanical systems on silicon-on-insulator integration platform

    Science.gov (United States)

    Hussein, Ali Abdulsattar

    This thesis presents an introduction to the design and simulation of a novel class of integrated photonic phased array switch elements. The main objective is to use nano-electromechanical (NEMS) based phase shifters of cascaded under-etched slot nanowires that are compact in size and require a small amount of power to operate them. The structure of the switch elements is organized such that it brings the phase shifting elements to the exterior sides of the photonic circuits. The transition slot couplers, used to interconnect the phase shifters, are designed to enable biasing one of the silicon beams of each phase shifter from an electrode located at the side of the phase shifter. The other silicon beam of each phase shifter is biased through the rest of the silicon structure of the switch element, which is taken as a ground. Phased array switch elements ranging from 2x2 up to 8x8 multiple-inputs/multiple-outputs (MIMO) are conveniently designed within reasonable footprints native to the current fabrication technologies. Chapter one presents the general layout of the various designs of the switch elements and demonstrates their novel features. This demonstration will show how waveguide disturbances in the interconnecting network from conventional switch elements can be avoided by adopting an innovative design. Some possible applications for the designed switch elements of different sizes and topologies are indicated throughout the chapter. Chapter two presents the design of the multimode interference (MMI) couplers used in the switch elements as splitters, combiners and waveguide crossovers. Simulation data and design methodologies for the multimode couplers of interest are detailed in this chapter. Chapter three presents the design and analysis of the NEMS-operated phase shifters. Both simulations and numerical analysis are utilized in the design of a 0°-180° capable NEMS-operated phase shifter. Additionally, the response of some of the designed photonic phased array switch elements is demonstrated in this chapter. An executive summary and conclusions sections are also included in the thesis.

  7. Cost of Czochralski wafers as a function of diameter

    Science.gov (United States)

    Leipold, M. H.; Radics, C.; Kachare, A.

    1980-02-01

    The impact of diameter in the range of 10 to 15 cm on the cost of wafers sliced from Czochralski ingots was analyzed. Increasing silicon waste and decreasing ingot cost with increasing ingot size were estimated along with projected costs. Results indicate a small but continuous decrease in sheet cost with increasing ingot size in this size range. Sheet costs including silicon are projected to be $50 to $60/sq m (1980 $) depending upon technique used.

  8. Wafer-level radiometric performance testing of uncooled microbolometer arrays

    Science.gov (United States)

    Dufour, Denis G.; Topart, Patrice; Tremblay, Bruno; Julien, Christian; Martin, Louis; Vachon, Carl

    2014-03-01

    A turn-key semi-automated test system was constructed to perform on-wafer testing of microbolometer arrays. The system allows for testing of several performance characteristics of ROIC-fabricated microbolometer arrays including NETD, SiTF, ROIC functionality, noise and matrix operability, both before and after microbolometer fabrication. The system accepts wafers up to 8 inches in diameter and performs automated wafer die mapping using a microscope camera. Once wafer mapping is completed, a custom-designed quick insertion 8-12 μm AR-coated Germanium viewport is placed and the chamber is pumped down to below 10-5 Torr, allowing for the evaluation of package-level focal plane array (FPA) performance. The probe card is electrically connected to an INO IRXCAM camera core, a versatile system that can be adapted to many types of ROICs using custom-built interface printed circuit boards (PCBs). We currently have the capability for testing 384x288, 35 μm pixel size and 160x120, 52 μm pixel size FPAs. For accurate NETD measurements, the system is designed to provide an F/1 view of two rail-mounted blackbodies seen through the Germanium window by the die under test. A master control computer automates the alignment of the probe card to the dies, the positioning of the blackbodies, FPA image frame acquisition using IRXCAM, as well as data analysis and storage. Radiometric measurement precision has been validated by packaging dies measured by the automated probing system and re-measuring the SiTF and Noise using INO's pre-existing benchtop system.

  9. Strength and leak testing of plasma activated bonded interfaces

    DEFF Research Database (Denmark)

    Visser, M.M.; Weichel, Steen; Reus, Roger De

    2002-01-01

    on detection of changes in membrane deflections. The detection limit for leak was 8E-13 mbar l/s. For comparison, strength and leak tests were also performed with regular fusion bonded wafers annealed at 1100 degreesC. The PAB was found to withstand post-processing steps such as RCA cleaning, 24 h in de......-ionised water (DIW), 24 h in 2.5% HF, 24 h in acetone and 60 s in a resist developer. By analysing the thin silicon oxide present on the surfaces to be bonded with optical methods, the influence of pre-cleaning and activation process parameters was investigated....

  10. Fully etched apodized grating coupler on the SOI platform with −058 dB coupling efficiency

    DEFF Research Database (Denmark)

    Ding, Yunhong; Peucheret, Christophe; Ou, Haiyan

    2014-01-01

    We design and fabricate an ultrahigh coupling efficiency (CE) fully etched apodized grating coupler on the silicon- on-insulator (SOI) platform using subwavelength photonic crystals and bonded aluminum mirror. Fabrication error sensitivity andcoupling angle dependence are experimentally investiga......We design and fabricate an ultrahigh coupling efficiency (CE) fully etched apodized grating coupler on the silicon- on-insulator (SOI) platform using subwavelength photonic crystals and bonded aluminum mirror. Fabrication error sensitivity andcoupling angle dependence are experimentally...

  11. Low temperature bonding of heterogeneous materials using Al2O3 as an intermediate layer

    DEFF Research Database (Denmark)

    Sahoo, Hitesh Kumar; Ottaviano, Luisa; Zheng, Yi

    2018-01-01

    Integration of heterogeneous materials is crucial for many nanophotonic devices. The integration is often achieved by bonding using polymer adhesives or metals. A much better and cleaner option is direct wafer bonding, but the high annealing temperatures required make it a much less attractive...

  12. Mechanical Properties of Photovoltaic Silicon in Relation to Wafer Breakage

    Science.gov (United States)

    Kulshreshtha, Prashant Kumar

    This thesis focuses on the fundamental understanding of stress-modified crack-propagation in photovoltaic (PV) silicon in relation to the critical issue of PV silicon "wafer breakage". The interactions between a propagating crack and impurities/defects/residual stresses have been evaluated for consequential fracture path in a thin PV Si wafer. To investigate the mechanism of brittle fracture in silicon, the phase transformations induced by elastic energy released at a propagating crack-tip have been evaluated by locally stressing the diamond cubic Si lattice using a rigid Berkovich nanoindenter tip (radius ≈50 nm). Unique pressure induced phase transformations and hardness variations have been then related to the distribution of precipitates (O, Cu, Fe etc.), and the local stresses in the wafer. This research demonstrates for the first time the "ductile-like fracture" in almost circular crack path that significantly deviates from its energetically favorable crystallographic [110](111) system. These large diameter (≈ 200 mm) Si wafers were sliced to less than 180 microm thickness from a Czochralski (CZ) ingot that was grown at faster than normal growth rates. The vacancy (vSi) driven precipitation of oxygen at enhanced thermal gradients in the wafer core develops large localized stresses (upto 100 MPa) which we evaluated using Raman spectral analysis. Additional micro-FTIR mapping and microscopic etch pit measurements in the wafer core have related the observed crack path deviations to the presence of concentric ring-like distributions of oxygen precipitates (OPs). To replicate these "real-world" breakage scenarios and provide better insight on crack-propagation, several new and innovative tools/devices/methods have been developed in this study. An accurate quantitative profiling of local stress, phase changes and load-carrying ability of Si lattice has been performed in the vicinity of the controlled micro-cracks created using micro-indentations to represent

  13. Solid-liquid interdiffusion (SLID) bonding in the Au-In system: experimental study and 1D modelling

    Science.gov (United States)

    Deillon, Léa; Hessler-Wyser, Aïcha; Hessler, Thierry; Rappaz, Michel

    2015-12-01

    Au-In bonds with a nominal composition of about 60 at.% In were fabricated for use in wafer-level packaging of MEMS. The microstructure of the bonds was studied by scanning electron microscopy. The bond hermeticity was then assessed using oxidation of Cu thin discs predeposited within the sealed packages. The three intermetallic compounds AuIn2, AuIn and Au7In3 were observed. Their thickness evolution during bonding and after subsequent heat treatment was successfully modelled using a finite difference model of diffusion, thermodynamic data and diffusion coefficients calibrated from isothermal diffusion couples. 17% of the packages were hermetic and, although the origin of the leaks could not be clearly identified, it appeared that hermeticity was correlated with the unevenness of the metallisation and/or wafer and the fact that the bonds shrink due to density differences as the relative fractions of the various phases gradually evolve.

  14. Solid-liquid interdiffusion (SLID) bonding in the Au–In system: experimental study and 1D modelling

    International Nuclear Information System (INIS)

    Deillon, Léa; Hessler-Wyser, Aïcha; Hessler, Thierry; Rappaz, Michel

    2015-01-01

    Au–In bonds with a nominal composition of about 60 at.% In were fabricated for use in wafer-level packaging of MEMS. The microstructure of the bonds was studied by scanning electron microscopy. The bond hermeticity was then assessed using oxidation of Cu thin discs predeposited within the sealed packages. The three intermetallic compounds AuIn 2 , AuIn and Au 7 In 3 were observed. Their thickness evolution during bonding and after subsequent heat treatment was successfully modelled using a finite difference model of diffusion, thermodynamic data and diffusion coefficients calibrated from isothermal diffusion couples. 17% of the packages were hermetic and, although the origin of the leaks could not be clearly identified, it appeared that hermeticity was correlated with the unevenness of the metallisation and/or wafer and the fact that the bonds shrink due to density differences as the relative fractions of the various phases gradually evolve. (paper)

  15. Magnetron target designs to improve wafer edge trench filling in ionized metal physical vapor deposition

    International Nuclear Information System (INIS)

    Lu Junqing; Yoon, Jae-Hong; Shin, Keesam; Park, Bong-Gyu; Yang Lin

    2006-01-01

    Severe asymmetry of the metal deposits on the trench sidewalls occurs near the wafer edge during low pressure ionized metal physical vapor deposition of Cu seed layer for microprocessor interconnects. To investigate this process and mitigate the asymmetry, an analytical view factor model based on the analogy between metal sputtering and diffuse thermal radiation was constructed. The model was validated based on the agreement between the model predictions and the reported experimental values for the asymmetric metal deposition at trench sidewalls near the wafer edge for a 200 mm wafer. This model could predict the thickness of the metal deposits across the wafer, the symmetry of the deposits on the trench sidewalls at any wafer location, and the angular distributions of the metal fluxes arriving at any wafer location. The model predictions for the 300 mm wafer indicate that as the target-to-wafer distance is shortened, the deposit thickness increases and the asymmetry decreases, however the overall uniformity decreases. Up to reasonable limits, increasing the target size and the sputtering intensity for the outer target portion significantly improves the uniformity across the wafer and the symmetry on the trench sidewalls near the wafer edge

  16. PMMA to SU-8 bonding for polymer based lab-on-a-chip systems with integrated optics

    DEFF Research Database (Denmark)

    Olsen, Brian Bilenberg; Nielsen, Theodor; Clausen, Bjarne Hans

    2004-01-01

    We present an adhesive bonding technique developed for SU-8 based "lab-on-a-chip"- systems with integrated optical components. Microfluidic channels and optical components (e.g. wave-guides) are defined in SU-8 photoresist on a Pyrex glass substrate. The microfluidic channels are sealed by a second...... Pyrex substrate, bonded on top of the cross-linked SU-8 structure using an inter- mediate layer of 950K molecular weight poly-methylmethacrylate (PMMA). Due to a lower refractive index of PMMA, this bonding technique offers optical waveguiding in the SU-8 structures in combination with good sealing...... of the microfluidic channels. The bonding technique is investigated with respect to bonding temperature in the range of 50 - 150 degr. C and at bonding forces of 1000 N and 2000 N on a 4-inch wafer. A maximum bonding strength of 16 MPa is achieved for the PMMA to SU-8 bonding at a bonding temperature of 110 degr. C...

  17. Multiproject wafers: not just for million-dollar mask sets

    Science.gov (United States)

    Morse, Richard D.

    2003-06-01

    With the advent of Reticle Enhancement Technologies (RET) such as Optical Proximity Correction (OPC) and Phase Shift Masks (PSM) required to manufacture semiconductors in the sub-wavelength era, the cost of photomask tooling has skyrocketed. On the leading edge of technology, mask set prices often exceed $1 million. This shifts an enormous burden back to designers and Electronic Design Automation (EDA) software vendors to create perfect designs at a time when the number of transistors per chip is measured in the hundreds of millions, and gigachips are on the drawing boards. Moore's Law has driven technology to incredible feats. The prime beneficiaries of the technology - memory and microprocessor (MPU) manufacturers - can continue to fit the model because wafer volumes (and chip prices in the MPU case) render tooling costs relatively insignificant. However, Application-Specific IC (ASIC) manufacturers and most foundry clients average very small wafer per reticle ratios causing a dramatic and potentially insupportable rise in the cost of manufacturing. Multi-Project wafers (MPWs) are a way to share the cost of tooling and silicon by putting more than one chip on each reticle. Lacking any unexpected breakthroughs in simulation, verification, or mask technology to reduce the cost of prototyping, more efficient use of reticle space becomes a viable and increasingly attractive choice. It is worthwhile therefore, to discuss the economics of prototyping in the sub-wavelength era and the increasing advantages of the MPW, shared-silicon approach. However, putting together a collection of different-sized chips during tapeout can be challenging and time consuming. Design compatibility, reticle field optimization, and frame generation have traditionally been the biggest worries but, with the advent of dummy-fill for planarization and RET for resolution, another layer of complexity has been added. MPW automation software is quite advanced today, but the size of the task

  18. Study of Si wafer surfaces irradiated by gas cluster ion beams

    International Nuclear Information System (INIS)

    Isogai, H.; Toyoda, E.; Senda, T.; Izunome, K.; Kashima, K.; Toyoda, N.; Yamada, I.

    2007-01-01

    The surface structures of Si (1 0 0) wafers subjected to gas cluster ion beam (GCIB) irradiation have been analyzed by cross-sectional transmission electron microscopy (XTEM) and atomic force microscopy (AFM). GCIB irradiation is a promising technique for both precise surface etching and planarization of Si wafers. However, it is very important to understand the crystalline structure of Si wafers after GCIB irradiation. An Ar-GCIB used for the physically sputtering of Si atoms and a SF 6 -GCIB used for the chemical etching of the Si surface are also analyzed. The GCIB irradiation increases the surface roughness of the wafers, and amorphous Si layers are formed on the wafer surface. However, when the Si wafers are annealed in hydrogen at a high temperature after the GCIB irradiation, the surface roughness decreases to the same level as that before the irradiation. Moreover, the amorphous Si layers disappear completely

  19. Through-glass copper via using the glass reflow and seedless electroplating processes for wafer-level RF MEMS packaging

    International Nuclear Information System (INIS)

    Lee, Ju-Yong; Lee, Sung-Woo; Lee, Seung-Ki; Park, Jae-Hyoung

    2013-01-01

    We present a novel method for the fabrication of void-free copper-filled through-glass-vias (TGVs), and their application to the wafer-level radio frequency microelectromechanical systems (RF MEMS) packaging scheme. By using the glass reflow process with a patterned silicon mold, a vertical TGV with smooth sidewall and fine pitch could be achieved. Bottom-up void-free filling of the TGV is successfully demonstrated through the seedless copper electroplating process. In addition, the proposed process allows wafer-level packaging with glass cap encapsulation using the anodic bonding process, since the reflowed glass interposer is only formed in the device area surrounded with silicon substrate. A simple coplanar waveguide (CPW) line was employed as the packaged device to evaluate the electrical characteristics and thermo-mechanical reliability of the proposed packaging structure. The fabricated packaging structure showed a low insertion loss of 0.116 dB and a high return loss of 35.537 dB at 20 GHz, which were measured through the whole electrical path, including the CPW line, TGVs and contact pads. An insertion loss lower than 0.1 dB and a return loss higher than 30 dB could be achieved at frequencies of up to 15 GHz, and the resistance of the single copper via was measured to be 36 mΩ. Furthermore, the thermo-mechanical reliability of the proposed packaging structure was also verified through thermal shock and pressure cooker test. (paper)

  20. Tests of a silicon wafer based neutron collimator

    International Nuclear Information System (INIS)

    Cussen, L.D.; Vale, C.J.; Anderson, I.S.; Hoeghoj, P.

    2001-01-01

    A Soller slit neutron collimator has been prepared by stacking 160 μm thick single crystal silicon wafers coated on one surface with 4 μm of gadolinium metal. The collimator has an angular width of 20 min full width at half maximum and an effective length of 2.75 cm. The collimator has beam dimensions of 1 cm wide by 5.3 cm high. Tests at neutron wavelengths 7.5A and 1.8A showed a peak transmission of 88% within 2% of the optimum theoretical possibility. The background suppression in the wings is comparable with that of conventional neutron collimators

  1. Tests of a silicon wafer based neutron collimator

    CERN Document Server

    Cussen, L D; Anderson, I S; Hoeghoj, P

    2001-01-01

    A Soller slit neutron collimator has been prepared by stacking 160 mu m thick single crystal silicon wafers coated on one surface with 4 mu m of gadolinium metal. The collimator has an angular width of 20 min full width at half maximum and an effective length of 2.75 cm. The collimator has beam dimensions of 1 cm wide by 5.3 cm high. Tests at neutron wavelengths 7.5A and 1.8A showed a peak transmission of 88% within 2% of the optimum theoretical possibility. The background suppression in the wings is comparable with that of conventional neutron collimators.

  2. Underling modification in ion beam induced Si wafers

    International Nuclear Information System (INIS)

    Hazra, S.; Chini, T.K.; Sanyal, M.K.; Grenzer, J.; Pietsch, U.

    2005-01-01

    Subsurface (amorphous-crystalline interface) structure of keV ion beam modified Si(001) wafers was studied for the first time using non-destructive technique and compared with that of the top one. Ion-beam modifications of the Si samples were done using state-of-art high-current ion implanter facility at Saha Institute of Nuclear Physics by changing energy, dose and angle of incidence of the Ar + ion beam. To bring out the underlying modification depth-resolved x-ray grazing incidence diffraction has been carried out using synchrotron radiation facility, while the structure of the top surface was studied through atomic force microscopy

  3. Addressable Inverter Matrix Tests Integrated-Circuit Wafer

    Science.gov (United States)

    Buehler, Martin G.

    1988-01-01

    Addressing elements indirectly through shift register reduces number of test probes. With aid of new technique, complex test structure on silicon wafer tested with relatively small number of test probes. Conserves silicon area by reduction of area devoted to pads. Allows thorough evaluation of test structure characteristics and of manufacturing process parameters. Test structure consists of shift register and matrix of inverter/transmission-gate cells connected to two-by-ten array of probe pads. Entire pattern contained in square area having only 1.6-millimeter sides. Shift register is conventional static CMOS device using inverters and transmission gates in master/slave D flip-flop configuration.

  4. Bond strength of masonry

    NARCIS (Netherlands)

    Pluijm, van der R.; Vermeltfoort, A.Th.

    1992-01-01

    Bond strength is not a well defined property of masonry. Normally three types of bond strength can be distinguished: - tensile bond strength, - shear (and torsional) bond strength, - flexural bond strength. In this contribution the behaviour and strength of masonry in deformation controlled uniaxial

  5. Cu Pillar Low Temperature Bonding and Interconnection Technology of for 3D RF Microsystem

    Science.gov (United States)

    Shi, G. X.; Qian, K. Q.; Huang, M.; Yu, Y. W.; Zhu, J.

    2018-03-01

    In this paper 3D interconnects technologies used Cu pillars are discussed with respect to RF microsystem. While 2.5D Si interposer and 3D packaging seem to rely to cu pillars for the coming years, RF microsystem used the heterogeneous chip such as GaAs integration with Si interposers should be at low temperature. The pillars were constituted by Cu (2 micron) -Ni (2 micron) -Cu (3 micron) -Sn (1 micron) multilayer metal and total height is 8 micron on the front-side of the wafer by using electroplating. The wafer backside Cu pillar is obtained by temporary bonding, thinning and silicon surface etching. The RF interposers are stacked by Cu-Sn eutectic bonding at 260 °C. Analyzed the reliability of different pillar bonding structure.

  6. A Lateral Differential Resonant Pressure Microsensor Based on SOI-Glass Wafer-Level Vacuum Packaging

    Directory of Open Access Journals (Sweden)

    Bo Xie

    2015-09-01

    Full Text Available This paper presents the fabrication and characterization of a resonant pressure microsensor based on SOI-glass wafer-level vacuum packaging. The SOI-based pressure microsensor consists of a pressure-sensitive diaphragm at the handle layer and two lateral resonators (electrostatic excitation and capacitive detection on the device layer as a differential setup. The resonators were vacuum packaged with a glass cap using anodic bonding and the wire interconnection was realized using a mask-free electrochemical etching approach by selectively patterning an Au film on highly topographic surfaces. The fabricated resonant pressure microsensor with dual resonators was characterized in a systematic manner, producing a quality factor higher than 10,000 (~6 months, a sensitivity of about 166 Hz/kPa and a reduced nonlinear error of 0.033% F.S. Based on the differential output, the sensitivity was increased to two times and the temperature-caused frequency drift was decreased to 25%.

  7. Determination of wafer center position during the transfer process by using the beam-breaking method

    International Nuclear Information System (INIS)

    Chen, Yi-Cheng; Wang, Zhi-Gen; Huang, Bo-Kai

    2014-01-01

    A wafer on a robot blade may slip due to inertia sliding during the acceleration or deceleration process. This study presents the implementation and experimental verification of a novel real-time wafer positioning system to be used during the transfer process. A system-integration computer program involving a human–machine interface (HMI) was also developed, exhibiting the following functions: (a) moving direction judgment; (b) notch-passing judgment; (c) indicating the sensor by which the notch passes; and (d) computing the wafer center in real time. The position of the wafer center is calculated based on the time-sequence of the beam-breaking signals from two optical sensors, and the geometric relations among the sensing points of the robot blade and wafer. When using eight-inch wafers, the experimental results indicated the capabilities of the proposed positioning system under various conditions, including distinct parameters regarding the moving direction, wafer displacement and notch-passing sensors. The accuracy and precision (repeatability) of the measurement in various conditions were calculated and discussed. Furthermore, the experimental results demonstrate that, after combining the novel wafer positioning system and HMI program, the proposed method can be used to compute the position of the wafer center in real time in various conditions. (paper)

  8. Wafer-level testing and test during burn-in for integrated circuits

    CERN Document Server

    Bahukudumbi, Sudarshan

    2010-01-01

    Wafer-level testing refers to a critical process of subjecting integrated circuits and semiconductor devices to electrical testing while they are still in wafer form. Burn-in is a temperature/bias reliability stress test used in detecting and screening out potential early life device failures. This hands-on resource provides a comprehensive analysis of these methods, showing how wafer-level testing during burn-in (WLTBI) helps lower product cost in semiconductor manufacturing.Engineers learn how to implement the testing of integrated circuits at the wafer-level under various resource constrain

  9. Comprehensive Die Shear Test of Silicon Packages Bonded by Thermocompression of Al Layers with Thin Sn Capping or Insertions

    Directory of Open Access Journals (Sweden)

    Shiro Satoh

    2018-04-01

    Full Text Available Thermocompression bonding for wafer-level hermetic packaging was demonstrated at the lowest temperature of 370 to 390 °C ever reported using Al films with thin Sn capping or insertions as bonding layer. For shrinking the chip size of MEMS (micro electro mechanical systems, a smaller size of wafer-level packaging and MEMS–ASIC (application specific integrated circuit integration are of great importance. Metal-based bonding under the temperature of CMOS (complementary metal-oxide-semiconductor backend process is a key technology, and Al is one of the best candidates for bonding metal in terms of CMOS compatibility. In this study, after the thermocompression bonding of two substrates, the shear fracture strength of dies was measured by a bonding tester, and the shear-fractured surfaces were observed by SEM (scanning electron microscope, EDX (energy dispersive X-ray spectrometry, and a surface profiler to clarify where the shear fracture took place. We confirmed two kinds of fracture mode. One mode is Si bulk fracture mode, where the die shear strength is 41.6 to 209 MPa, proportionally depending on the area of Si fracture. The other mode is bonding interface fracture mode, where the die shear strength is 32.8 to 97.4 MPa. Regardless of the fracture modes, the minimum die shear strength is practical for wafer-level MEMS packaging.

  10. Hydrogen Incorporation during Aluminium Anodisation on Silicon Wafer Surfaces

    International Nuclear Information System (INIS)

    Lu, Pei Hsuan Doris; Strutzberg, Hartmuth; Wenham, Stuart; Lennon, Alison

    2014-01-01

    Hydrogen can act to reduce recombination at silicon surfaces for solar cell devices and consequently the ability of dielectric layers to provide a source of hydrogen for this purpose is of interest. However, due to the ubiquitous nature of hydrogen and its mobility, direct measurements of hydrogen incorporation in dielectric layers are challenging. In this paper, we report the use of secondary ion mass spectrometry measurements to show that deuterium from an electrolyte can be incorporated in an anodic aluminium oxide (AAO) layer and be introduced into an underlying amorphous silicon layer during anodisation of aluminium on silicon wafers. After annealing at 400 °C, the concentration of deuterium in the AAO was reduced by a factor of two, as the deuterium was re-distributed to the interface between the amorphous silicon and AAO and to the amorphous silicon. The assumption that hydrogen, from an aqueous electrolyte, could be similarly incorporated in AAO, is supported by the observation that the hydrogen content in the underlying amorphous silicon was increased by a factor of ∼ 3 after anodisation. Evidence for hydrogen being introduced into crystalline silicon after aluminium anodisation was provided by electrochemical capacitance voltage measurements indicating boron electrical deactivation in the underlying crystalline silicon. If introduced hydrogen can electrically deactivate dopant atoms at the surface, then it is reasonable to assume that it could also deactivate recombination-active states at the crystalline silicon interface therefore enabling higher minority carrier lifetimes in the silicon wafer

  11. Residual stress in silicon wafer using IR polariscope

    Science.gov (United States)

    Lu, Zhijia; Wang, Pin; Asundi, Anand

    2008-09-01

    The infrared phase shift polariscope (IR-PSP) is a full-field optical technique for stress analysis in Silicon wafers. Phase shift polariscope is preferred to a conventional polariscope, as it can provide quantitative information of the normal stress difference and the shear stress in the specimen. The method is based on the principles of photoelasticity, in which stresses induces temporary birefringence in materials which can be quantitatively analyzed using a phase shift polariscope. Compared to other stress analysis techniques such as x-ray diffraction or laser scanning, infrared photoelastic stress analysis provides full-field information with high resolution and in near real time. As the semiconductor fabrication is advancing, larger wafers, thinner films and more compact packages are being manufactured. This results in a growing demand of process control. Residual stress exist in silicon during semiconductor fabrication and these stresses may make cell processing difficult or even cause the failure of the silicon. Reducing these stresses would improve manufacturability and reliability. Therefore stress analysis is essential to trace the root cause of the stresses. The polariscope images are processed using MATLAB and four-step phase shifting method to provide quantitative as well as qualitative information regarding the residual stress of the sample. The system is calibrated using four-point bend specimen and then the residual stress distribution in a MEMS sample is shown.

  12. Improving scanner wafer alignment performance by target optimization

    Science.gov (United States)

    Leray, Philippe; Jehoul, Christiane; Socha, Robert; Menchtchikov, Boris; Raghunathan, Sudhar; Kent, Eric; Schoonewelle, Hielke; Tinnemans, Patrick; Tuffy, Paul; Belen, Jun; Wise, Rich

    2016-03-01

    In the process nodes of 10nm and below, the patterning complexity along with the processing and materials required has resulted in a need to optimize alignment targets in order to achieve the required precision, accuracy and throughput performance. Recent industry publications on the metrology target optimization process have shown a move from the expensive and time consuming empirical methodologies, towards a faster computational approach. ASML's Design for Control (D4C) application, which is currently used to optimize YieldStar diffraction based overlay (DBO) metrology targets, has been extended to support the optimization of scanner wafer alignment targets. This allows the necessary process information and design methodology, used for DBO target designs, to be leveraged for the optimization of alignment targets. In this paper, we show how we applied this computational approach to wafer alignment target design. We verify the correlation between predictions and measurements for the key alignment performance metrics and finally show the potential alignment and overlay performance improvements that an optimized alignment target could achieve.

  13. Adsorption kinetics and dynamics of small organic molecules on a silica wafer: Butane, pentane, nonane, thiophene, and methanol adsorption on SiO2/Si(1 1 1)

    International Nuclear Information System (INIS)

    Funk, S.; Goering, J.; Burghaus, U.

    2008-01-01

    The adsorption kinetics (by thermal desorption spectroscopy) and adsorption dynamics (by molecular beam scattering) have been determined for a number of alkanes, methanol, thiophene, and water on a silica wafer-SiO 2 /Si(1 1 1). No indications for bond activation were present, i.e., all probe molecules adsorb molecularly obeying 1st order kinetics. The coverage-dependent heat of adsorption has been determined accordingly. The adsorption dynamics are precursor-mediated with Kisliuk-like shapes of the adsorption probabilities at low impact energies and adsorbate-assisted adsorption at large impact energies

  14. Understanding Bonds - Denmark

    DEFF Research Database (Denmark)

    Rimmer, Nina Røhr

    2016-01-01

    Undervisningsmateriale. A bond is a debt security, similar to an ”I Owe You document” (IOU). When you purchase a bond, you are lending money to a government, municipality, corporation, federal agency or other entity known as the issuer. In return for the loan, the issuer promises to pay you...... a specified rate of interest during the life of the bond and to repay the face value of the bond (the principal) when it “matures,” or comes due. Among the types of bonds you can choose from are: Government securities, municipal bonds, corporate bonds, mortgage and asset-backed securities, federal agency...... securities and foreign government bonds....

  15. Penggunaan Limbah Kopi Sebagai Bahan Penyusun Ransum Itik Peking dalam Bentuk Wafer Ransum Komplit

    Directory of Open Access Journals (Sweden)

    Muhammad Daud

    2013-04-01

    Full Text Available Effect of coffee waste as component of compiler ration peking duck in the form of wafer complete ration ABSTRACT. Coffee waste is a by-product of coffee processing that potential to be used as feed stuff for peking duck. The weakness of this coffee waste, among others, is perishable, voluminous (bulky and the availability was fluctuated so the processing technology is needed to make this vegetable waste to be durable, easy to stored and to be given to livestock. To solve this problem vegetable waste could be formed as wafer. This research was conducted to study effectiveness of coffee waste as component of compiler ration peking duck in the form of wafer complete ration This experiment was run in completely randomized design which consist of 4 feed treatment and 3 replications.  Ration used was consisted of  P0 = wafer complete ration 0% coffee waste (control, P1 = wafer complete ration 2,5% coffee waste, P2 = wafer complete ration 5% coffee waste, and P3 = Wafer complete ration 7,5% coffee waste. The Variables observed were: physical characteristic (aroma, color, and wafer density and palatability of wafer complete ration. Data collected was analyzed with ANOVA and Duncan Range Test would be used if the result was significantly different. The result showed that the density of wafer complete ration coffee waste was significantly (P< 0.05 differences between of treatment. Mean density wafer complete ration equal to: P0= 0,52±0,03, P1 =0,67±0,04, P2 =0,72±0,03, and P3 = 0,76±0.05 g/cm3. Wafer complete ration coffee waste palatability was significantly (P< 0.05 differences between of treatment. It is concluded that of wafer complete ration composition 5 and 7,5% coffee waste was significantly wafer palatability and gave a highest wafer density. The ration P0 was the most palatable compare to other treatments for the experimental peking duck.

  16. Wafer-scale fabrication of uniform Si nanowire arrays using the Si wafer with UV/Ozone pretreatment

    International Nuclear Information System (INIS)

    Bai, Fan; Li, Meicheng; Huang, Rui; Yu, Yue; Gu, Tiansheng; Chen, Zhao; Fan, Huiyang; Jiang, Bing

    2013-01-01

    The electroless etching technique combined with the process of UV/Ozone pretreatment is presented for wafer-scale fabrication of the silicon nanowire (SiNW) arrays. The high-level uniformity of the SiNW arrays is estimated by the value below 0.2 of the relative standard deviation of the reflection spectra on the 4-in. wafer. Influence of the UV/Ozone pretreatment on the formation of SiNW arrays is investigated. It is seen that a very thin SiO 2 produced by the UV/Ozone pretreatment improves the uniform nucleation of Ag nanoparticles (NPs) on the Si surface because of the effective surface passivation. Meanwhile, the SiO 2 located among the adjacent Ag NPs can obstruct the assimilation growth of Ag NPs, facilitating the deposition of the uniform and dense Ag NPs catalysts, which induces the formation of the SiNW arrays with good uniformity and high filling ratio. Furthermore, the remarkable antireflective and hydrophobic properties are observed for the SiNW arrays which display great potential in self-cleaning antireflection applications

  17. Correlation study of actual temperature profile and in-line metrology measurements for within-wafer uniformity improvement and wafer edge yield enhancement (Conference Presentation)

    Science.gov (United States)

    Fang, Fang; Vaid, Alok; Vinslava, Alina; Casselberry, Richard; Mishra, Shailendra; Dixit, Dhairya; Timoney, Padraig; Chu, Dinh; Porter, Candice; Song, Da; Ren, Zhou

    2018-03-01

    It is getting more important to monitor all aspects of influencing parameters in critical etch steps and utilize them as tuning knobs for within-wafer uniformity improvement and wafer edge yield enhancement. Meanwhile, we took a dive in pursuing "measuring what matters" and challenged ourselves for more aspects of signals acquired in actual process conditions. Among these factors which are considered subtle previously, we identified Temperature, especially electrostatic chuck (ESC) Temperature measurement in real etch process conditions have direct correlation to in-line measurements. In this work, we used SensArray technique (EtchTemp-SE wafer) to measure ESC temperature profile on a 300mm wafer with plasma turning on to reproduce actual temperature pattern on wafers in real production process conditions. In field applications, we observed substantial correlation between ESC temperature and in-line optical metrology measurements and since temperature is a process factor that can be tuning through set-temperature modulations, we have identified process knobs with known impact on physical profile variations. Furthermore, ESC temperature profile on a 300mm wafer is configured as multiple zones upon radius and SensArray measurements mechanism could catch such zonal distribution as well, which enables detailed temperature modulations targeting edge ring only where most of chips can be harvested and critical zone for yield enhancement. Last but not least, compared with control reference (ESC Temperature in static plasma-off status), we also get additional factors to investigate in chamber-to-chamber matching study and make process tool fleet match on the basis really matters in production. KLA-Tencor EtchTemp-SE wafer enables Plasma On wafer temperature monitoring of silicon etch process. This wafer is wireless and has 65 sensors with measurement range from 20 to 140°C. the wafer is designed to run in real production recipe plasma on condition with maximum RF power up

  18. Wire bonding in microelectronics

    CERN Document Server

    Harman, George G

    2010-01-01

    Wire Bonding in Microelectronics, Third Edition, has been thoroughly revised to help you meet the challenges of today's small-scale and fine-pitch microelectronics. This authoritative guide covers every aspect of designing, manufacturing, and evaluating wire bonds engineered with cutting-edge techniques. In addition to gaining a full grasp of bonding technology, you'll learn how to create reliable bonds at exceedingly high yields, test wire bonds, solve common bonding problems, implement molecular cleaning methods, and much more. Coverage includes: Ultrasonic bonding systems and technologies, including high-frequency systems Bonding wire metallurgy and characteristics, including copper wire Wire bond testing Gold-aluminum intermetallic compounds and other interface reactions Gold and nickel-based bond pad plating materials and problems Cleaning to improve bondability and reliability Mechanical problems in wire bonding High-yield, fine-pitch, specialized-looping, soft-substrate, and extreme-temperature wire bo...

  19. Propagation of resist heating mask error to wafer level

    Science.gov (United States)

    Babin, S. V.; Karklin, Linard

    2006-10-01

    As technology is approaching 45 nm and below the IC industry is experiencing a severe product yield hit due to rapidly shrinking process windows and unavoidable manufacturing process variations. Current EDA tools are unable by their nature to deliver optimized and process-centered designs that call for 'post design' localized layout optimization DFM tools. To evaluate the impact of different manufacturing process variations on final product it is important to trace and evaluate all errors through design to manufacturing flow. Photo mask is one of the critical parts of this flow, and special attention should be paid to photo mask manufacturing process and especially to mask tight CD control. Electron beam lithography (EBL) is a major technique which is used for fabrication of high-end photo masks. During the writing process, resist heating is one of the sources for mask CD variations. Electron energy is released in the mask body mainly as heat, leading to significant temperature fluctuations in local areas. The temperature fluctuations cause changes in resist sensitivity, which in turn leads to CD variations. These CD variations depend on mask writing speed, order of exposure, pattern density and its distribution. Recent measurements revealed up to 45 nm CD variation on the mask when using ZEP resist. The resist heating problem with CAR resists is significantly smaller compared to other types of resists. This is partially due to higher resist sensitivity and the lower exposure dose required. However, there is no data yet showing CD errors on the wafer induced by CAR resist heating on the mask. This effect can be amplified by high MEEF values and should be carefully evaluated at 45nm and below technology nodes where tight CD control is required. In this paper, we simulated CD variation on the mask due to resist heating; then a mask pattern with the heating error was transferred onto the wafer. So, a CD error on the wafer was evaluated subject to only one term of the

  20. CMOS MEMS Fabrication Technologies and Devices

    Directory of Open Access Journals (Sweden)

    Hongwei Qu

    2016-01-01

    Full Text Available This paper reviews CMOS (complementary metal-oxide-semiconductor MEMS (micro-electro-mechanical systems fabrication technologies and enabled micro devices of various sensors and actuators. The technologies are classified based on the sequence of the fabrication of CMOS circuitry and MEMS elements, while SOI (silicon-on-insulator CMOS MEMS are introduced separately. Introduction of associated devices follows the description of the respective CMOS MEMS technologies. Due to the vast array of CMOS MEMS devices, this review focuses only on the most typical MEMS sensors and actuators including pressure sensors, inertial sensors, frequency reference devices and actuators utilizing different physics effects and the fabrication processes introduced. Moreover, the incorporation of MEMS and CMOS is limited to monolithic integration, meaning wafer-bonding-based stacking and other integration approaches, despite their advantages, are excluded from the discussion. Both competitive industrial products and state-of-the-art research results on CMOS MEMS are covered.

  1. A Study of the Charge Trap Transistor (CTT) for Post-Fab Modification of Wafers

    Science.gov (United States)

    2018-04-01

    AFRL-RY-WP-TR-2018-0030 A STUDY OF THE CHARGE TRAP TRANSISTOR (CTT) FOR POST- FAB MODIFICATION OF WAFERS Subramanian S. Iyer University of California...Final 13 June 2016 – 13 December 2017 4. TITLE AND SUBTITLE A STUDY OF THE CHARGE TRAP TRANSISTOR (CTT) FOR POST- FAB MODIFICATION OF WAFERS 5a. CONTRACT

  2. Wafer-level packaged RF-MEMS switches fabricated in a CMOS fab

    NARCIS (Netherlands)

    Tilmans, H.A.C.; Ziad, H.; Jansen, Henricus V.; Di Monaco, O.; Jourdain, A.; De Raedt, W.; Rottenberg, X.; De Backer, E.; Decoussernaeker, A.; Baert, K.

    2001-01-01

    Reports on wafer-level packaged RF-MEMS switches fabricated in a commercial CMOS fab. Switch fabrication is based on a metal surface micromachining process. A novel wafer-level packaging scheme is developed, whereby the switches are housed in on-chip sealed cavities using benzocyclobutene (BCB) as

  3. Synchrotron radiation total reflection x-ray fluorescence analysis; of polymer coated silicon wafers

    International Nuclear Information System (INIS)

    Brehm, L.; Kregsamer, P.; Pianetta, P.

    2000-01-01

    It is well known that total reflection x-ray fluorescence (TXRF) provides an efficient method for analyzing trace metal contamination on silicon wafer surfaces. New polymeric materials used as interlayer dielectrics in microprocessors are applied to the surface of silicon wafers by a spin-coating process. Analysis of these polymer coated wafers present a new challenge for TXRF analysis. Polymer solutions are typically analyzed for bulk metal contamination prior to application on the wafer using inductively coupled plasma mass spectrometry (ICP-MS). Questions have arisen about how to relate results of surface contamination analysis (TXRF) of a polymer coated wafer to bulk trace analysis (ICP-MS) of the polymer solutions. Experiments were done to explore this issue using synchrotron radiation (SR) TXRF. Polymer solutions were spiked with several different concentrations of metals. These solutions were applied to silicon wafers using the normal spin-coating process. The polymer coated wafers were then measured using the SR-TXRF instrument set-up at the Stanford Synchrotron Radiation Laboratory (SSRL). Several methods of quantitation were evaluated. The best results were obtained by developing calibration curves (intensity versus ppb) using the spiked polymer coated wafers as standards. Conversion of SR-TXRF surface analysis results (atoms/cm 2 ) to a volume related concentration was also investigated. (author)

  4. Comparison of silicon strip tracker module size using large sensors from 6 inch wafers

    CERN Multimedia

    Honma, Alan

    1999-01-01

    Two large silicon strip sensor made from 6 inch wafers are placed next to each other to simulate the size of a CMS outer silicon tracker module. On the left is a prototype 2 sensor CMS inner endcap silicon tracker module made from 4 inch wafers.

  5. Fabrication of CVD graphene-based devices via laser ablation for wafer-scale characterization

    DEFF Research Database (Denmark)

    Mackenzie, David; Buron, Jonas Christian Due; Whelan, Patrick Rebsdorf

    2015-01-01

    Selective laser ablation of a wafer-scale graphene film is shown to provide flexible, high speed (1 wafer/hour) device fabrication while avoiding the degradation of electrical properties associated with traditional lithographic methods. Picosecond laser pulses with single pulse peak fluences of 140......-effect mobility, doping level, on–off ratio, and conductance minimum before and after laser ablation fabrication....

  6. Locally-enhanced light scattering by a monocrystalline silicon wafer

    Directory of Open Access Journals (Sweden)

    Li Ma

    2018-03-01

    Full Text Available We study the optical properties of light scattering by a monocrystalline silicon wafer, by using transparent material to replicate its surface structure and illuminating a fabricated sample with a laser source. The experimental results show that the scattering field contains four spots of concentrated intensity with high local energy, and these spots are distributed at the four vertices of a square with lines of intensity linking adjacent spots. After discussing simulations of and theory about the formation of this light scattering, we conclude that the scattering field is formed by the effects of both geometrical optics and physical optics. Moreover, we calculate the central angle of the spots in the light field, and the result indicates that the locally-enhanced intensity spots have a definite scattering angle. These results may possibly provide a method for improving energy efficiency within mono-Si based solar cells.

  7. Joint Research on Scatterometry and AFM Wafer Metrology

    Science.gov (United States)

    Bodermann, Bernd; Buhr, Egbert; Danzebrink, Hans-Ulrich; Bär, Markus; Scholze, Frank; Krumrey, Michael; Wurm, Matthias; Klapetek, Petr; Hansen, Poul-Erik; Korpelainen, Virpi; van Veghel, Marijn; Yacoot, Andrew; Siitonen, Samuli; El Gawhary, Omar; Burger, Sven; Saastamoinen, Toni

    2011-11-01

    Supported by the European Commission and EURAMET, a consortium of 10 participants from national metrology institutes, universities and companies has started a joint research project with the aim of overcoming current challenges in optical scatterometry for traceable linewidth metrology. Both experimental and modelling methods will be enhanced and different methods will be compared with each other and with specially adapted atomic force microscopy (AFM) and scanning electron microscopy (SEM) measurement systems in measurement comparisons. Additionally novel methods for sophisticated data analysis will be developed and investigated to reach significant reductions of the measurement uncertainties in critical dimension (CD) metrology. One final goal will be the realisation of a wafer based reference standard material for calibration of scatterometers.

  8. Coherent spin transport through a 350 micron thick silicon wafer.

    Science.gov (United States)

    Huang, Biqin; Monsma, Douwe J; Appelbaum, Ian

    2007-10-26

    We use all-electrical methods to inject, transport, and detect spin-polarized electrons vertically through a 350-micron-thick undoped single-crystal silicon wafer. Spin precession measurements in a perpendicular magnetic field at different accelerating electric fields reveal high spin coherence with at least 13pi precession angles. The magnetic-field spacing of precession extrema are used to determine the injector-to-detector electron transit time. These transit time values are associated with output magnetocurrent changes (from in-plane spin-valve measurements), which are proportional to final spin polarization. Fitting the results to a simple exponential spin-decay model yields a conduction electron spin lifetime (T1) lower bound in silicon of over 500 ns at 60 K.

  9. Ambient plasma treatment of silicon wafers for surface passivation recovery

    Science.gov (United States)

    Ge, Jia; Prinz, Markus; Markert, Thomas; Aberle, Armin G.; Mueller, Thomas

    2017-08-01

    In this work, the effect of an ambient plasma treatment powered by compressed dry air on the passivation quality of silicon wafers coated with intrinsic amorphous silicon sub-oxide is investigated. While long-time storage deteriorates the effective lifetime of all samples, a short ambient plasma treatment improves their passivation qualities. By studying the influence of the plasma treatment parameters on the passivation layers, an optimized process condition was identified which even boosted the passivation quality beyond its original value obtained immediately after deposition. On the other hand, the absence of stringent requirement on gas precursors, vacuum condition and longtime processing makes the ambient plasma treatment an excellent candidate to replace conventional thermal annealing in industrial heterojunction solar cell production.

  10. Comparison on mechanical properties of heavily phosphorus- and arsenic-doped Czochralski silicon wafers

    Science.gov (United States)

    Yuan, Kang; Sun, Yuxin; Lu, Yunhao; Liang, Xingbo; Tian, Daxi; Ma, Xiangyang; Yang, Deren

    2018-04-01

    Heavily phosphorus (P)- and arsenic (As)-doped Czochralski silicon (CZ-Si) wafers generally act as the substrates for the epitaxial silicon wafers used to fabricate power and communication devices. The mechanical properties of such two kinds of n-type heavily doped CZ silicon wafers are vital to ensure the quality of epitaxial silicon wafers and the manufacturing yields of devices. In this work, the mechanical properties including the hardness, Young's modulus, indentation fracture toughness and the resistance to dislocation motion have been comparatively investigated for heavily P- and As-doped CZ-Si wafers. It is found that heavily P-doped CZ-Si possesses somewhat higher hardness, lower Young's modulus, larger indentation fracture toughness and stronger resistance to dislocation motion than heavily As-doped CZ-Si. The mechanisms underlying this finding have been tentatively elucidated by considering the differences in the doping effects of P and As in silicon.

  11. Development of thin film measurement program of wafer for spin etcher

    International Nuclear Information System (INIS)

    Seo, Hak Suk; Kim, No Hyu; Kim, Young Chul; Cho, Jung Keun; Bae, Jung Yong

    2001-01-01

    This paper proposes a thickness measurement method of silicon-oxide and poly-silicon film deposited on 12 inch silicon wafer for spin etcher. Krypton lamp is used as a light source for generating a wide-band spectrum, which is guided and focused on the wafer surface through a optical fiber cable. Interference signal from the film is detected by optical sensor to determine the thickness of the film using spectrum analysis and several signal processing techniques including curve-fitting and filtering. Test wafers with two kinds of priori-known films, silicon-oxide(100nm) and poly-silicon(300nm), are measured under the condition that the wafer is spinning at 20Hz and DI water flowing on the wafer surface. From experiment results the algorithm presented in the paper is proved to be effective with accuracy of maximum 6.5% error.

  12. Development of thin film measurement program of wafer for spin etcher

    Energy Technology Data Exchange (ETDEWEB)

    Seo, Hak Suk; Kim, No Hyu; Kim, Young Chul [Korea University of Technology and Education, Cheonan (Korea, Republic of); Cho, Jung Keun; Bae, Jung Yong [Korea DNS, Cheonan (Korea, Republic of)

    2001-11-15

    This paper proposes a thickness measurement method of silicon-oxide and poly-silicon film deposited on 12 inch silicon wafer for spin etcher. Krypton lamp is used as a light source for generating a wide-band spectrum, which is guided and focused on the wafer surface through a optical fiber cable. Interference signal from the film is detected by optical sensor to determine the thickness of the film using spectrum analysis and several signal processing techniques including curve-fitting and filtering. Test wafers with two kinds of priori-known films, silicon-oxide(100nm) and poly-silicon(300nm), are measured under the condition that the wafer is spinning at 20Hz and DI water flowing on the wafer surface. From experiment results the algorithm presented in the paper is proved to be effective with accuracy of maximum 6.5% error.

  13. Temperature Uniformity of Wafer on a Large-Sized Susceptor for a Nitride Vertical MOCVD Reactor

    International Nuclear Information System (INIS)

    Li Zhi-Ming; Jiang Hai-Ying; Han Yan-Bin; Li Jin-Ping; Yin Jian-Qin; Zhang Jin-Cheng

    2012-01-01

    The effect of coil location on wafer temperature is analyzed in a vertical MOCVD reactor by induction heating. It is observed that the temperature distribution in the wafer with the coils under the graphite susceptor is more uniform than that with the coils around the outside wall of the reactor. For the case of coils under the susceptor, we find that the thickness of the susceptor, the distance from the coils to the susceptor bottom and the coil turns significantly affect the temperature uniformity of the wafer. An optimization process is executed for a 3-inch susceptor with this kind of structure, resulting in a large improvement in the temperature uniformity. A further optimization demonstrates that the new susceptor structure is also suitable for either multiple wafers or large-sized wafers approaching 6 and 8 inches

  14. Crack detection and analyses using resonance ultrasonic vibrations in full-size crystalline silicon wafers

    International Nuclear Information System (INIS)

    Belyaev, A.; Polupan, O.; Dallas, W.; Ostapenko, S.; Hess, D.; Wohlgemuth, J.

    2006-01-01

    An experimental approach for fast crack detection and length determination in full-size solar-grade crystalline silicon wafers using a resonance ultrasonic vibrations (RUV) technique is presented. The RUV method is based on excitation of the longitudinal ultrasonic vibrations in full-size wafers. Using an external piezoelectric transducer combined with a high sensitivity ultrasonic probe and computer controlled data acquisition system, real-time frequency response analysis can be accomplished. On a set of identical crystalline Si wafers with artificially introduced periphery cracks, it was demonstrated that the crack results in a frequency shift in a selected RUV peak to a lower frequency and increases the resonance peak bandwidth. Both characteristics were found to increase with the length of the crack. The frequency shift and bandwidth increase serve as reliable indicators of the crack appearance in silicon wafers and are suitable for mechanical quality control and fast wafer inspection

  15. Impurity engineering for germanium-doped Czochralski silicon wafer used for ultra large scale integrated circuit

    Energy Technology Data Exchange (ETDEWEB)

    Chen, Jiahe; Yang, Deren [State Key Laboratory of Silicon Materials, Department of Materials Science and Engineering, Zhejiang University, Hangzhou (China)

    2009-07-01

    Internal gettering (IG) technology has been challenged by both the reduction of thermal budget during device fabrication and the enlargement of wafer diameter. Improving the properties of Czochralski (Cz) silicon wafers by intentional impurity doping, the so-called 'impurity engineering (IE)', is defined. Germanium has been found to be one of the important impurities for improving the internal gettering effect in Cz silicon wafer. In this paper, the investigations on IE involved with the conventional furnace anneal based denudation processing for germanium-doped Cz silicon wafer are reviewed. Meanwhile, the potential mechanisms of germanium effects for the IE of Cz silicon wafer are also interpreted based on the experimental facts. (copyright 2009 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

  16. Wafer size effect on material removal rate in copper CMP process

    Energy Technology Data Exchange (ETDEWEB)

    Yuh, Minjong; Jang, Soocheon; Park, Inho; Jeong, Haedo [Pusan National University, Busan (Korea, Republic of)

    2017-06-15

    The semiconductor industry has employed the Chemical mechanical planarization (CMP) to enable surface topography control. Copper has been used to build interconnects because of its low-resistivity and high-electromigration. In this study, the effect of wafer size on the Material removal rate (MRR) in copper CMP process was investigated. CMP experiments were conducted using copper blanket wafers with diameter of 100, 150, 200 and 300 mm, while temperature and friction force were measured by infrared and piezoelectric sen-sors. The MRR increases with an increase in wafer size under the same process conditions. The wafer size increased the sliding distance of pad, resulting in an increase in the process temperature. This increased the process temperature, accelerating the chemical etching rate and the dynamic etch rate. The sliding distance of the pad was proportional to the square of the wafer radius; it may be used to predict CMP results and design a CMP machine.

  17. A Novel Defect Inspection Method for Semiconductor Wafer Based on Magneto-Optic Imaging

    Science.gov (United States)

    Pan, Z.; Chen, L.; Li, W.; Zhang, G.; Wu, P.

    2013-03-01

    The defects of semiconductor wafer may be generated from the manufacturing processes. A novel defect inspection method of semiconductor wafer is presented in this paper. The method is based on magneto-optic imaging, which involves inducing eddy current into the wafer under test, and detecting the magnetic flux associated with eddy current distribution in the wafer by exploiting the Faraday rotation effect. The magneto-optic image being generated may contain some noises that degrade the overall image quality, therefore, in this paper, in order to remove the unwanted noise present in the magneto-optic image, the image enhancement approach using multi-scale wavelet is presented, and the image segmentation approach based on the integration of watershed algorithm and clustering strategy is given. The experimental results show that many types of defects in wafer such as hole and scratch etc. can be detected by the method proposed in this paper.

  18. Application of a layout/material handling design method to a furnace area in a 300 mm wafer fab

    NARCIS (Netherlands)

    Hesen, P.M.C.; Renders, P.J.J.; Rooda, J.E.

    2001-01-01

    For many years, material handling within the semiconductor industry has become increasingly important. With the introduction of 300 mm wafer production, ergonomics and product safety become more critical. Therefore, the manufacturers of semiconductor wafer fabs are considering the automation of

  19. Edge printability: techniques used to evaluate and improve extreme wafer edge printability

    Science.gov (United States)

    Roberts, Bill; Demmert, Cort; Jekauc, Igor; Tiffany, Jason P.

    2004-05-01

    The economics of semiconductor manufacturing have forced process engineers to develop techniques to increase wafer yield. Improvements in process controls and uniformities in all areas of the fab have reduced film thickness variations at the very edge of the wafer surface. This improved uniformity has provided the opportunity to consider decreasing edge exclusions, and now the outermost extents of the wafer must be considered in the yield model and expectations. These changes have increased the requirements on lithography to improve wafer edge printability in areas that previously were not even coated. This has taxed all software and hardware components used in defining the optical focal plane at the wafer edge. We have explored techniques to determine the capabilities of extreme wafer edge printability and the components of the systems that influence this printability. We will present current capabilities and new detection techniques and the influence that the individual hardware and software components have on edge printability. We will show effects of focus sensor designs, wafer layout, utilization of dummy edge fields, the use of non-zero overlay targets and chemical/optical edge bead optimization.

  20. Towards ultra-thin plasmonic silicon wafer solar cells with minimized efficiency loss.

    Science.gov (United States)

    Zhang, Yinan; Stokes, Nicholas; Jia, Baohua; Fan, Shanhui; Gu, Min

    2014-05-13

    The cost-effectiveness of market-dominating silicon wafer solar cells plays a key role in determining the competiveness of solar energy with other exhaustible energy sources. Reducing the silicon wafer thickness at a minimized efficiency loss represents a mainstream trend in increasing the cost-effectiveness of wafer-based solar cells. In this paper we demonstrate that, using the advanced light trapping strategy with a properly designed nanoparticle architecture, the wafer thickness can be dramatically reduced to only around 1/10 of the current thickness (180 μm) without any solar cell efficiency loss at 18.2%. Nanoparticle integrated ultra-thin solar cells with only 3% of the current wafer thickness can potentially achieve 15.3% efficiency combining the absorption enhancement with the benefit of thinner wafer induced open circuit voltage increase. This represents a 97% material saving with only 15% relative efficiency loss. These results demonstrate the feasibility and prospect of achieving high-efficiency ultra-thin silicon wafer cells with plasmonic light trapping.

  1. Low-Temperature Cu-Cu Bonding Using Silver Nanoparticles Fabricated by Physical Vapor Deposition

    Science.gov (United States)

    Wu, Zijian; Cai, Jian; Wang, Junqiang; Geng, Zhiting; Wang, Qian

    2018-02-01

    Silver nanoparticles (Ag NPs) fabricated by physical vapor deposition (PVD) were introduced in Cu-Cu bonding as surface modification layer. The bonding structure consisted of a Ti adhesive/barrier layer and a Cu substrate layer was fabricated on the silicon wafer. Ag NPs were deposited on the Cu surface by magnetron sputtering in a high-pressure environment and a loose structure with NPs was obtained. Shear tests were performed after bonding, and the influences of PVD pressure, bonding pressure, bonding temperature and annealing time on shear strength were assessed. Cu-Cu bonding with Ag NPs was accomplished at 200°C for 3 min under the pressure of 30 MPa without a post-annealing process, and the average bonding strength of 13.99 MPa was reached. According to cross-sectional observations, a void-free bonding interface with an Ag film thickness of around 20 nm was achieved. These results demonstrated that a reliable low-temperature short-time Cu-Cu bonding was realized by the sintering process of Ag NPs between the bonding pairs, which indicated that this bonding method could be a potential candidate for future ultra-fine pitch 3D integration.

  2. Thermal stress during RTP processes and its possible effect on the light induced degradation in Cz-Si wafers

    Science.gov (United States)

    Kouhlane, Yacine; Bouhafs, Djoudi; Khelifati, Nabil; Guenda, Abdelkader; Demagh, Nacer-Eddine; Demagh, Assia; Pfeiffer, Pierre; Mezghiche, Salah; Hetatache, Warda; Derkaoui, Fahima; Nasraoui, Chahinez; Nwadiaru, Ogechi Vivian

    2018-04-01

    In this study, the carrier lifetime variation of p-type boron-doped Czochralski silicon (Cz-Si) wafers was investigated after a direct rapid thermal processing (RTP). Two wafers were passivated by silicon nitride (SiNx:H) layers, deposited by a PECVD system on both surfaces. Then the wafers were subjected to an RTP cycle at a peak temperature of 620 °C. The first wafer was protected (PW) from the direct radiative heating of the RTP furnace by placing the wafer between two as-cut Cz-Si shield wafers during the heat processing. The second wafer was not protected (NPW) and followed the same RTP cycle procedure. The carrier lifetime τ eff was measured using the QSSPC technique before and after illumination for 5 h duration at 0.5 suns. The immediate results of the measured lifetime (τ RTP ) after the RTP process have shown a regeneration in the lifetime of the two wafers with the PW wafer exhibiting an important enhancement in τ RTP as compared to the NPW wafer. The QSSPC measurements have indicated a good stable lifetime (τ d ) and a weak degradation effect was observed in the case of the PW wafer as compared to their initial lifetime value. Interferometry technique analyses have shown an enhancement in the surface roughness for the NPW wafer as compared to the protected one. Additionally, to improve the correlation between the RTP heat radiation stress and the carrier lifetime behavior, a simulation of the thermal stress and temperature profile using the finite element method on the wafers surface at RTP peak temperature of 620 °C was performed. The results confirm the reduction of the thermal stress with less heat losses for the PW wafer. Finally, the proposed method can lead to improving the lifetime of wafers by an RTP process at minimum energy costs.

  3. Improvement of silicon direct bonding using surfaces activated by hydrogen plasma treatment

    CERN Document Server

    Choi, W B; Lee Jae Sik; Sung, M Y

    2000-01-01

    The plasma surface treatment, using hydrogen gas, of silicon wafers was studied as a pretreatment for silicon direct bonding. Chemical reactions of the hydrogen plasma with the surfaces were used for both surface activation and removal of surface contaminants. Exposure of the silicon wafers to the plasma formed an active oxide layer on the surface. This layer was hydrophilic. The surface roughness and morphology were examined as functions of the plasma exposure time and power. The surface became smoother with shorter plasma exposure time and lower power. In addition, the plasma surface treatment was very efficient in removing the carbon contaminants on the silicon surface. The value of the initial surface energy, as estimated by using the crack propagation method, was 506 mJ/M sup 2 , which was up to about three times higher than the value for the conventional direct bonding method using wet chemical treatments.

  4. Sequential plasma activation methods for hydrophilic direct bonding at sub-200 °C

    Science.gov (United States)

    He, Ran; Yamauchi, Akira; Suga, Tadatomo

    2018-02-01

    We present our newly developed sequential plasma activation methods for hydrophilic direct bonding of silica glasses and thermally grown SiO2 films. N2 plasma was employed to introduce a metastable oxynitride layer on wafer surfaces for the improvement of bond energy. By using either O2-plasma/N2-plasma/N-radical or N2-plasma/N-radical sequential activation, the quartz-quartz bond energy was increased from 2.7 J/m2 to close to the quartz bulk fracture energy that was estimated to be around 9.0 J/m2 after post-bonding annealing at 200 °C. The silicon bulklike bond energy between thermal SiO2 films was also obtained. We suggest that the improvement is attributable to surface modification such as N-related defect formation and asperity softening by the N2 plasma surface treatment.

  5. TXRF with synchrotron radiation. Analysis of Ni on Si-wafer surfaces

    Energy Technology Data Exchange (ETDEWEB)

    Wobrauschek, P [Atominstitut der Oesterreichischen Universitaeten, Vienna (Austria); Kregsamer, P [Atominstitut der Oesterreichischen Universitaeten, Vienna (Austria); Ladisich, W [Atominstitut der Oesterreichischen Universitaeten, Vienna (Austria); Streli, C [Atominstitut der Oesterreichischen Universitaeten, Vienna (Austria); Pahlke, S [Wacker Chemitronic GmbH, D-84479 Burghausen (Germany); Fabry, L [Wacker Chemitronic GmbH, D-84479 Burghausen (Germany); Garbe, S [Institut fuer Anorg. u. Angew. Chemie, Universitaet Hamburg, Martin-Luther King-Pl.6, D-20146 Hamburg (Germany); Haller, M [Institut fuer Anorg. u. Angew. Chemie, Universitaet Hamburg, Martin-Luther King-Pl.6, D-20146 Hamburg (Germany); Knoechel, A [Institut fuer Anorg. u. Angew. Chemie, Universitaet Hamburg, Martin-Luther King-Pl.6, D-20146 Hamburg (Germany); Radtke, M [Institut fuer Anorg. u. Angew. Chemie, Universitaet Hamburg, Martin-Luther King-Pl.6, D-20146 Hamburg (Germany)

    1995-09-11

    SR-TXRF (Synchrotron Radiation excited Total Reflection X-ray Fluorescence Analysis) with monoenergetic radiation produced by a W/C multilayer monochromator has been applied to the analysis of Ni on a Si-wafer surface. An intentionally contaminated wafer with 100 pg has been used to determine the detection limits. 13 fg have been achieved for Ni at a beam current of 73 mA and extrapolated to 1000 s. This technique simulates the sample preparation technique of Vapour Phase Decomposition (VPD) on a wafer surface. (orig.).

  6. TXRF with synchrotron radiation. Analysis of Ni on Si-wafer surfaces

    International Nuclear Information System (INIS)

    Wobrauschek, P.; Kregsamer, P.; Ladisich, W.; Streli, C.; Pahlke, S.; Fabry, L.; Garbe, S.; Haller, M.; Knoechel, A.; Radtke, M.

    1995-01-01

    SR-TXRF (Synchrotron Radiation excited Total Reflection X-ray Fluorescence Analysis) with monoenergetic radiation produced by a W/C multilayer monochromator has been applied to the analysis of Ni on a Si-wafer surface. An intentionally contaminated wafer with 100 pg has been used to determine the detection limits. 13 fg have been achieved for Ni at a beam current of 73 mA and extrapolated to 1000 s. This technique simulates the sample preparation technique of Vapour Phase Decomposition (VPD) on a wafer surface. (orig.)

  7. A modified occlusal wafer for managing partially dentate orthognathic patients--a case series.

    Science.gov (United States)

    Soneji, Bhavin Kiritkumar; Esmail, Zaid; Sharma, Pratik

    2015-03-01

    A multidisciplinary approach is essential in orthognathic surgery to achieve stable and successful outcomes. The model surgery planning is an important aspect in achieving the desired aims. An occlusal wafer used at the time of surgery aids the surgeon during correct placement of the jaws. When dealing with partially dentate patients, the design of the occlusal wafer requires modification to appropriately position the jaw. Two cases with partially dentate jaws are presented in which the occlusal wafer has been modified to provide stability at the time of surgery.

  8. Direct, CMOS In-Line Process Flow Compatible, Sub 100 °C Cu-Cu Thermocompression Bonding Using Stress Engineering

    Science.gov (United States)

    Panigrahi, Asisa Kumar; Ghosh, Tamal; Kumar, C. Hemanth; Singh, Shiv Govind; Vanjari, Siva Rama Krishna

    2018-05-01

    Diffusion of atoms across the boundary between two bonding layers is the key for achieving excellent thermocompression Wafer on Wafer bonding. In this paper, we demonstrate a novel mechanism to increase the diffusion across the bonding interface and also shows the CMOS in-line process flow compatible Sub 100 °C Cu-Cu bonding which is devoid of Cu surface treatment prior to bonding. The stress in sputtered Cu thin films was engineered by adjusting the Argon in-let pressure in such a way that one film had a compressive stress while the other film had tensile stress. Due to this stress gradient, a nominal pressure (2 kN) and temperature (75 °C) was enough to achieve a good quality thermocompression bonding having a bond strength of 149 MPa and very low specific contact resistance of 1.5 × 10-8 Ω-cm2. These excellent mechanical and electrical properties are resultant of a high quality Cu-Cu bonding having grain growth between the Cu films across the boundary and extended throughout the bonded region as revealed by Cross-sectional Transmission Electron Microscopy. In addition, reliability assessment of Cu-Cu bonding with stress engineering was demonstrated using multiple current stressing and temperature cycling test, suggests excellent reliable bonding without electrical performance degradation.

  9. Direct, CMOS In-Line Process Flow Compatible, Sub 100 °C Cu-Cu Thermocompression Bonding Using Stress Engineering

    Science.gov (United States)

    Panigrahi, Asisa Kumar; Ghosh, Tamal; Kumar, C. Hemanth; Singh, Shiv Govind; Vanjari, Siva Rama Krishna

    2018-03-01

    Diffusion of atoms across the boundary between two bonding layers is the key for achieving excellent thermocompression Wafer on Wafer bonding. In this paper, we demonstrate a novel mechanism to increase the diffusion across the bonding interface and also shows the CMOS in-line process flow compatible Sub 100 °C Cu-Cu bonding which is devoid of Cu surface treatment prior to bonding. The stress in sputtered Cu thin films was engineered by adjusting the Argon in-let pressure in such a way that one film had a compressive stress while the other film had tensile stress. Due to this stress gradient, a nominal pressure (2 kN) and temperature (75 °C) was enough to achieve a good quality thermocompression bonding having a bond strength of 149 MPa and very low specific contact resistance of 1.5 × 10-8 Ω-cm2. These excellent mechanical and electrical properties are resultant of a high quality Cu-Cu bonding having grain growth between the Cu films across the boundary and extended throughout the bonded region as revealed by Cross-sectional Transmission Electron Microscopy. In addition, reliability assessment of Cu-Cu bonding with stress engineering was demonstrated using multiple current stressing and temperature cycling test, suggests excellent reliable bonding without electrical performance degradation.

  10. Bonding with Your Baby

    Science.gov (United States)

    ... the future bonding of the child and parent. Adoptive parents may be concerned about bonding with their ... general emotional support. And it's OK to ask family members and friends for help in the days — ...

  11. Fabrication of a microfluidic chip by UV bonding at room temperature for integration of temperature-sensitive layers

    Science.gov (United States)

    Schlautmann, S.; Besselink, G. A. J.; Radhakrishna Prabhu, G.; Schasfoort, R. B. M.

    2003-07-01

    A method for the bonding of a microfluidic device at room temperature is presented. The wafer with the fluidic structures was bonded to a sensor wafer with gold pads by means of adhesive bonding, utilizing an UV-curable glue layer. To avoid filling the fluidic channels with the glue, a stamping process was developed which allows the selective application of a thin glue layer. In this way a microfluidic glass chip was fabricated that could be used for performing surface plasmon resonance measurements without signs of leakage. The advantage of this method is the possibility of integration of organic layers as well as other temperature-sensitive layers into a microfluidic glass device.

  12. Australia's Bond Home Bias

    OpenAIRE

    Anil V. Mishra; Umaru B. Conteh

    2014-01-01

    This paper constructs the float adjusted measure of home bias and explores the determinants of bond home bias by employing the International Monetary Fund's high quality dataset (2001 to 2009) on cross-border bond investment. The paper finds that Australian investors' prefer investing in countries with higher economic development and more developed bond markets. Exchange rate volatility appears to be an impediment for cross-border bond investment. Investors prefer investing in countries with ...

  13. A metallic buried interconnect process for through-wafer interconnection

    International Nuclear Information System (INIS)

    Ji, Chang-Hyeon; Herrault, Florian; Allen, Mark G

    2008-01-01

    In this paper, we present the design, fabrication process and experimental results of electroplated metal interconnects buried at the bottom of deep silicon trenches with vertical sidewalls. A manual spray-coating process along with a unique trench-formation process has been developed for the electroplating of a metal interconnection structure at the bottom surface of the deep trenches. The silicon etch process combines the isotropic dry etch process and conventional Bosch process to fabricate a deep trench with angled top-side edges and vertical sidewalls. The resulting trench structure, in contrast to the trenches fabricated by wet anisotropic etching, enables spray-coated photoresist patterning with good sidewall and top-side edge coverage while maintaining the ability to form a high-density array of deep trenches without excessive widening of the trench opening. A photoresist spray-coating process was developed and optimized for the formation of electroplating mold at the bottom of 300 µm deep trenches having vertical sidewalls. A diluted positive tone photoresist with relatively high solid content and multiple coating with baking between coating steps has been experimentally proven to provide high quality sidewall and edge coverage. To validate the buried interconnect approach, a three-dimensional daisy chain structure having a buried interconnect as the bottom connector and traces on the wafer surface as the top conductor has been designed and fabricated

  14. 1366 Project Automate: Enabling Automation for <$0.10/W High-Efficiency Kerfless Wafers Manufactured in the US

    Energy Technology Data Exchange (ETDEWEB)

    Lorenz, Adam [1366 Technologies, Bedford, MA (United States)

    2017-05-10

    For photovoltaic (PV) manufacturing to thrive in the U.S., there must be an innovative core to the technology. Project Automate builds on 1366’s proprietary Direct Wafer® kerfless wafer technology and aims to unlock the cost and efficiency advantages of thin kerfless wafers. Direct Wafer is an innovative, U.S.-friendly (efficient, low-labor content) manufacturing process that addresses the main cost barrier limiting silicon PV cost-reductions – the 35-year-old grand challenge of manufacturing quality wafers (40% of the cost of modules) without the cost and waste of sawing. This simple, scalable process will allow 1366 to manufacture “drop-in” replacement wafers for the $10 billion silicon PV wafer market at 50% of the cost, 60% of the capital, and 30% of the electricity of conventional casting and sawing manufacturing processes. This SolarMat project developed the Direct Wafer processes’ unique capability to tailor the shape of wafers to simultaneously make thinner AND stronger wafers (with lower silicon usage) that enable high-efficiency cell architectures. By producing wafers with a unique target geometry including a thick border (which determines handling characteristics) and thin interior regions (which control light capture and electron transport and therefore determine efficiency), 1366 can simultaneously improve quality and lower cost (using less silicon).

  15. Phenylacetylene and H bond

    Indian Academy of Sciences (India)

    ... all resembling H bonds. Non-linear H bonds due to secondary interactions. C-H stretching frequency shows blue shift. Heavy atom distances are longer than the sum of van der Waals radii. Formed a task group through IUPAC to come up with a modern definition of H bond. 15 international experts including Desiraju.

  16. Chemical bond fundamental aspects of chemical bonding

    CERN Document Server

    Frenking, Gernot

    2014-01-01

    This is the perfect complement to ""Chemical Bonding - Across the Periodic Table"" by the same editors, who are two of the top scientists working on this topic, each with extensive experience and important connections within the community. The resulting book is a unique overview of the different approaches used for describing a chemical bond, including molecular-orbital based, valence-bond based, ELF, AIM and density-functional based methods. It takes into account the many developments that have taken place in the field over the past few decades due to the rapid advances in quantum chemica

  17. Characterization and control of wafer charging effects during high-current ion implantation

    International Nuclear Information System (INIS)

    Current, M.I.; Lukaszek, W.; Dixon, W.; Vella, M.C.; Messick, C.; Shideler, J.; Reno, S.

    1994-02-01

    EEPROM-based sense and memory devices provide direct measures of the charge flow and potentials occurring on the surface of wafers during ion beam processing. Sensor design and applications for high current ion implantation are discussed

  18. Electronically and ionically conductive porous material and method for manufacture of resin wafers therefrom

    Science.gov (United States)

    Lin, YuPo J [Naperville, IL; Henry, Michael P [Batavia, IL; Snyder, Seth W [Lincolnwood, IL

    2011-07-12

    An electrically and ionically conductive porous material including a thermoplastic binder and one or more of anion exchange moieties or cation exchange moieties or mixtures thereof and/or one or more of a protein capture resin and an electrically conductive material. The thermoplastic binder immobilizes the moieties with respect to each other but does not substantially coat the moieties and forms the electrically conductive porous material. A wafer of the material and a method of making the material and wafer are disclosed.

  19. Silicon wafer wettability and aging behaviors: Impact on gold thin-film morphology

    KAUST Repository

    Yang, Xiaoming; Zhong, Zhaowei; Diallo, Elhadj; Wang, Zhihong; Yue, Weisheng

    2014-01-01

    This paper reports on the wettability and aging behaviors of the silicon wafers that had been cleaned using a piranha (3:1 mixture of sulfuric acid (H2SO4, 96%) and hydrogen peroxide (H2O 2, 30%), 120 °C), SC1 (1:1:5 mixture of NH4OH, H 2O2 and H2O, at 80°C) or HF solution (6 parts of 40% NH4F and 1 part of 49% HF, at room temperature) solution, and treated with gaseous plasma. The silicon wafers cleaned using the piranha or SC1 solution were hydrophilic, and the water contact angles on the surfaces would increase along with aging time, until they reached the saturated points of around 70°. The contact angle increase rate of these wafers in a vacuum was much faster than that in the open air, because of loss of water, which was physically adsorbed on the wafer surfaces. The silicon wafers cleaned with the HF solution were hydrophobic. Their contact angle decreased in the atmosphere, while it increased in the vacuum up to 95°. Gold thin films deposited on the hydrophilic wafers were smoother than that deposited on the hydrophobic wafers, because the numerous oxygen groups formed on the hydrophilic surfaces would react with gold adatoms in the sputtering process to form a continuous thin film at the nucleation stage. The argon, nitrogen, oxygen gas plasma treatments could change the silicon wafer surfaces from hydrophobic to hydrophilic by creating a thin (around 2.5 nm) silicon dioxide film, which could be utilized to improve the roughness and adhesion of the gold thin film. © 2014 Elsevier Ltd. All rights reserved.

  20. Fabrication of high aspect ratio through-wafer copper interconnects by reverse pulse electroplating

    International Nuclear Information System (INIS)

    Gu, Changdong; Zhang, Tong-Yi; Xu, Hui

    2009-01-01

    This study aims to fabricate high aspect ratio through-wafer copper interconnects by a simple reverse pulse electroplating technique. High aspect-ratio (∼18) through-wafer holes obtained by a two-step deep reactive ion etching (DRIE) process exhibit a taper profile, which might automatically optimize the local current density distribution during the electroplating process, thereby achieving void-free high aspect-ratio copper vias

  1. Silicon wafer wettability and aging behaviors: Impact on gold thin-film morphology

    KAUST Repository

    Yang, Xiaoming

    2014-10-01

    This paper reports on the wettability and aging behaviors of the silicon wafers that had been cleaned using a piranha (3:1 mixture of sulfuric acid (H2SO4, 96%) and hydrogen peroxide (H2O 2, 30%), 120 °C), SC1 (1:1:5 mixture of NH4OH, H 2O2 and H2O, at 80°C) or HF solution (6 parts of 40% NH4F and 1 part of 49% HF, at room temperature) solution, and treated with gaseous plasma. The silicon wafers cleaned using the piranha or SC1 solution were hydrophilic, and the water contact angles on the surfaces would increase along with aging time, until they reached the saturated points of around 70°. The contact angle increase rate of these wafers in a vacuum was much faster than that in the open air, because of loss of water, which was physically adsorbed on the wafer surfaces. The silicon wafers cleaned with the HF solution were hydrophobic. Their contact angle decreased in the atmosphere, while it increased in the vacuum up to 95°. Gold thin films deposited on the hydrophilic wafers were smoother than that deposited on the hydrophobic wafers, because the numerous oxygen groups formed on the hydrophilic surfaces would react with gold adatoms in the sputtering process to form a continuous thin film at the nucleation stage. The argon, nitrogen, oxygen gas plasma treatments could change the silicon wafer surfaces from hydrophobic to hydrophilic by creating a thin (around 2.5 nm) silicon dioxide film, which could be utilized to improve the roughness and adhesion of the gold thin film. © 2014 Elsevier Ltd. All rights reserved.

  2. Nonuniformities of electrical resistivity in undoped 6H-SiC wafers

    International Nuclear Information System (INIS)

    Li, Q.; Polyakov, A.Y.; Skowronski, M.; Sanchez, E.K.; Loboda, M.J.; Fanton, M.A.; Bogart, T.; Gamble, R.D.

    2005-01-01

    Chemical elemental analysis, temperature-dependent Hall measurements, deep-level transient spectroscopy, and contactless resistivity mapping were performed on undoped semi-insulating (SI) and lightly nitrogen-doped conducting 6H-SiC crystals grown by physical vapor transport (PVT). Resistivity maps of commercial semi-insulating SiC wafers revealed resistivity variations across the wafers between one and two orders of magnitude. Two major types of variations were identified. First is the U-shape distribution with low resistivity in the center and high in the periphery of the wafer. The second type had an inverted U-shape distribution. Secondary-ion-mass spectrometry measurements of the distribution of nitrogen concentration along the growth axis and across the wafers sliced from different locations of lightly nitrogen-doped 6H-SiC boules were conducted. The measured nitrogen concentration gradually decreased along the growth direction and from the center to the periphery of the wafers. This change gives rise to the U-like distribution of resistivity in wafers of undoped SI-SiC. The concentrations of deep electron traps exhibited similar dependence. Compensation of nitrogen donors by these traps can result in the inverted U-like distribution of resistivity. Possible reasons for the observed nonuniformities include formation of a (0001) facet in PVT growth coupled with orientation-dependent nitrogen incorporation, systematic changes of the gas phase composition, and increase of the deposition temperature during boule growth

  3. In vitro and in vivo evaluation of a sublingual fentanyl wafer formulation

    Science.gov (United States)

    Lim, Stephen CB; Paech, Michael J; Sunderland, Bruce; Liu, Yandi

    2013-01-01

    Background The objective of this study was to prepare a novel fentanyl wafer formulation by a freeze-drying method, and to evaluate its in vitro and in vivo release characteristics, including its bioavailability via the sublingual route. Methods The wafer formulation was prepared by freeze-drying an aqueous dispersion of fentanyl containing sodium carboxymethylcellulose and amylogum as matrix formers. Uniformity of weight, friability, and dissolution testing of the fentanyl wafer was achieved using standard methods, and the residual moisture content was measured. The fentanyl wafer was also examined using scanning electron microscopy and x-ray diffraction. The absolute bioavailability of the fentanyl wafer was evaluated in 11 opioid-naïve adult female patients using a randomized crossover design. Results In vitro release showed that almost 90% of the fentanyl dissolved in one minute. In vivo, the first detectable plasma fentanyl concentration was observed after 3.5 minutes and the peak plasma concentration between 61.5 and 67 minutes. The median absolute bioavailability was 53.0%. Conclusion These results indicate that this wafer has potential as an alternative sublingual fentanyl formulation. PMID:23596347

  4. A wafer mapping technique for residual stress in surface micromachined films

    International Nuclear Information System (INIS)

    Schiavone, G; Murray, J; Smith, S; Walton, A J; Desmulliez, M P Y; Mount, A R

    2016-01-01

    The design of MEMS devices employing movable structures is crucially dependant on the mechanical behaviour of the deposited materials. It is therefore important to be able to fully characterize the micromachined films and predict with confidence the mechanical properties of patterned structures. This paper presents a characterization technique that enables the residual stress in MEMS films to be mapped at the wafer level by using microstructures released by surface micromachining. These dedicated MEMS test structures and the associated measurement techniques are used to extract localized information on the strain and Young’s modulus of the film under investigation. The residual stress is then determined by numerically coupling this data with a finite element analysis of the structure. This paper illustrates the measurement routine and demonstrates it with a case study using electrochemically deposited alloys of nickel and iron, particularly prone to develop high levels of residual stress. The results show that the technique enables wafer mapping of film non-uniformities and identifies wafer-to-wafer differences. A comparison between the results obtained from the mapping technique and conventional wafer bow measurements highlights the benefits of using a procedure tailored to films that are non-uniform, patterned and surface-micromachined, as opposed to simple standard stress extraction methods. The presented technique reveals detailed information that is generally unexplored when using conventional stress extraction methods such as wafer bow measurements. (paper)

  5. Evaluation of a cyanoacrylate dressing to manage peristomal skin alterations under ostomy skin barrier wafers.

    Science.gov (United States)

    Milne, Catherine T; Saucier, Darlene; Trevellini, Chenel; Smith, Juliet

    2011-01-01

    Peristomal skin alterations under ostomy barrier wafers are a commonly reported problem. While a number of interventions to manage this issue have been reported, the use of a topically applied cyanoacrylate has received little attention. This case series describes the use of a topical cyanoacrylate for the management of peristomal skin alterations in persons living with an ostomy. Using a convenience sample, the topical cyanoacrylate dressing was applied to 11 patients with peristomal skin disruption under ostomy wafers in acute care and outpatient settings. The causes of barrier function interruption were also addressed to enhance outcomes. Patients were assessed for wound discomfort using a Likert Scale, time to healing, and number of appliance changes. Patient satisfaction was also examined. Average reported discomfort levels were 9.5 out of 10 at the initial peristomal irritation assessment visit decreased to 3.5 at the first wafer change and were absent by the second wafer change. Wafers had increasing wear time between changes in both settings with acute care patients responding faster. Epidermal resurfacing occurred within 10.2 days in outpatients and within 7 days in acute care patients. Because of the skin sealant action of this dressing, immediate adherence of the wafer was reported at all pouch changes.

  6. Towards in-situ tem analysis of PLD Pb(Zr,Ti)O3 thin film membranes

    NARCIS (Netherlands)

    Sardan Sukas, Ö.; Berenschot, Johan W.; de Boer, Meint J.; Nguyen, Duc Minh; van Zalk, M.; Abelmann, Leon

    2011-01-01

    In this paper, a novel technique for fabricating Transmission Electron Microscopy (TEM) chips for investigating structural and piezoelectric properties of Pulse Laser Deposited (PLD) Lead Zirconium Titanate (PZT) thin films is presented. The method involves silicon-on-insulator (SOI) wafer

  7. Polarization-Independent Wideband High-Index-Contrast Grating Mirror

    DEFF Research Database (Denmark)

    Bekele, Dagmawi Alemayehu; Park, Gyeong Cheol; Malureanu, Radu

    2015-01-01

    Island-type two-dimensional high-index-contrast grating mirror based on a standard silicon-on-insulator wafer have been experimentally demonstrated. The measured spectra shows a bandwidth of ∼192 nm with a reflectivity over 99% as well as polarization independence. Numerical simulations show...

  8. Selective SiO2 etching in three dimensional structures using parylene-C as mask

    NARCIS (Netherlands)

    Veltkamp, Henk-Willem; Zhao, Yiyuan; de Boer, Meint J.; Wiegerink, Remco J.; Lötters, Joost Conrad

    2017-01-01

    This abstract describes an application of an easy and straightforward method for selective SiO2 etching in three dimensional structures, which is developed by our group. The application in this abstract is the protection of the buried-oxide (BOX) layer of a silicon-on-insulator (SOI) wafer against

  9. Mode Coupling and Nonlinear Resonances of MEMS Arch Resonators for Bandpass Filters

    KAUST Repository

    Hajjaj, Amal Z.; Hafiz, Md Abdullah Al; Younis, Mohammad I.

    2017-01-01

    the passband to the stopband. The concept is demonstrated based on an electrothermally tuned and electrostatically driven MEMS arch resonator operated in air. The in-plane resonator is fabricated from a silicon-on-insulator wafer with a deliberate curvature

  10. Gap-closing test structures for temperature budget determination

    NARCIS (Netherlands)

    Faber, Erik Jouwert; Wolters, Robertus A.M.; Schmitz, Jurriaan

    2011-01-01

    We present the extension of a method for determining the temperature budget of the process side of silicon substrates and chips, employing silicide formation reactions. In this work, silicon-on-insulator type substrates are used instead of bulk silicon wafers. By an appropriate choice of the layer

  11. Silicon-photonics light source realized by III-V/Si grating-mirror laser

    DEFF Research Database (Denmark)

    Chung, Il-Sug; Mørk, Jesper

    2010-01-01

    waveguide are made in the Si layer of a silicon-on-insulator wafer by using Si-electronics-compatible processing. The HCG works as a highly-reflective mirror for vertical resonance and at the same time routes light to the in-plane output waveguide. Numerical simulations show superior performance compared...... to existing silicon light sources....

  12. Highly tunable NEMS shallow arches

    KAUST Repository

    Kazmi, Syed N. R.; Hajjaj, Amal Z.; Da Costa, Pedro M. F. J.; Younis, Mohammad I.

    2017-01-01

    and surface nanomachining of a highly conductive device layer on a silicon-on-insulator wafer. By designing the structures to have gap to thickness ratio of more than four, the mid-plane stretching of the nano arches is maximized such that an increase

  13. Electrostatically Tunable Nanomechanical Shallow Arches

    KAUST Repository

    Kazmi, Syed N. R.; Hajjaj, Amal Z.; Da Costa, Pedro M. F. J.; Younis, Mohammad I.

    2017-01-01

    -beam lithography and surface nanomachining of a highly conductive device layer on a silicon-on-insulator (SOI) wafer. The experimental results show good agreement with the analytical results with a maximum tunability of 108.14% for 180 nm thick arch with a

  14. Near-field characterization of photonic crystal Y-splitters

    DEFF Research Database (Denmark)

    Volkov, V. S.; Bozhevolnyi, S. I.; Borel, Peter Ingo

    2005-01-01

    A scanning near-field optical microscope (SNOM) is used to directly map the propagation of light in a specially designed 50/50 photonic crystal (PC) Y-splitter fabricated on silicon-on-insulator (SOI) wafers. SNOM images are obtained for TE- and TM-polarized light in the wavelength range 1425...

  15. DynAMITe: a wafer scale sensor for biomedical applications

    International Nuclear Information System (INIS)

    Esposito, M; Wells, K; Anaxagoras, T; Fant, A; Allinson, N M; Konstantinidis, A; Speller, R D; Osmond, J P F; Evans, P M

    2011-01-01

    In many biomedical imaging applications Flat Panel Imagers (FPIs) are currently the most common option. However, FPIs possess several key drawbacks such as large pixels, high noise, low frame rates, and excessive image artefacts. Recently Active Pixel Sensors (APS) have gained popularity overcoming such issues and are now scalable up to wafer size by appropriate reticule stitching. Detectors for biomedical imaging applications require high spatial resolution, low noise and high dynamic range. These figures of merit are related to pixel size and as the pixel size is fixed at the time of the design, spatial resolution, noise and dynamic range cannot be further optimized. The authors report on a new rad-hard monolithic APS, named DynAMITe (Dynamic range Adjustable for Medical Imaging Technology), developed by the UK MI-3 Plus consortium. This large area detector (12.8 cm × 12.8 cm) is based on the use of two different diode geometries within the same pixel array with different size pixels (50 μm and 100 μm). Hence the resulting device can possess two inherently different resolutions each with different noise and saturation performance. The small and the large pixel cameras can be reset at different voltages, resulting in different depletion widths. The larger depletion width for the small pixels allows the initial generated photo-charge to be promptly collected, which ensures an intrinsically lower noise and higher spatial resolution. After these pixels reach near saturation, the larger pixels start collecting so offering a higher dynamic range whereas the higher noise floor is not important as at higher signal levels performance is governed by the Poisson noise of the incident radiation beam. The overall architecture and detailed characterization of DynAMITe will be presented in this paper.

  16. The Au/Si eutectic bonding compatibility with KOH etching for 3D devices fabrication

    Science.gov (United States)

    Liang, Hengmao; Liu, Mifeng; Liu, Song; Xu, Dehui; Xiong, Bin

    2018-01-01

    KOH etching and Au/Si eutectic bonding are cost-efficient technologies for 3D device fabrication. Aimed at investigating the process compatibility of KOH etching and Au/Si bonding, KOH etching tests have been carried out for Au/bulk Si and Au/amorphous Si (a-Si) bonding wafers in this paper. For the Au/bulk Si bonding wafer, a serious underetch phenomenon occurring on the damage layer in KOH etching definitely results in packaging failure. In the microstructure analysis, it is found that the formation of the damage layer between the bonded layer and bulk Si is attributed to the destruction of crystal Si lattices in Au/bulk Si eutectic reaction. Considering the occurrence of underetch for Au/Si bonding must meet two requirements: the superfluous Si and the defective layer near the bonded layer, the Au/a-Si bonding by regulating the a-Si/Au thickness ratio is presented in this study. Only when the a-Si/Au thickness ratio is relatively low are there not underetch phenomena, of which the reason is the full reaction of the a-Si layer avoiding the formation of the damage layer for easy underetch. Obviously, the Au/a-Si bonding via choosing a moderate a-Si/Au thickness ratio (⩽1.5:1 is suggested) could be reliably compatible with KOH etching, which provides an available and low-cost approach for 3D device fabrication. More importantly, the theory of the damage layer proposed in this study can be naturally applied to relevant analyses on the eutectic reaction of other metals and single crystal materials.

  17. P/N InP solar cells on Ge wafers

    Science.gov (United States)

    Wojtczuk, Steven; Vernon, Stanley; Burke, Edward A.

    1994-01-01

    Indium phosphide (InP) P-on-N one-sun solar cells were epitaxially grown using a metalorganic chemical vapor deposition process on germanium (Ge) wafers. The motivation for this work is to replace expensive InP wafers, which are fragile and must be thick and therefore heavy, with less expensive Ge wafers, which are stronger, allowing use of thinner, lighter weight wafers. An intermediate InxGs1-xP grading layer starting as In(0.49)Ga(0.51) at the GaAs-coated Ge wafer surface and ending as InP at the top of the grading layer (backside of the InP cell) was used to attempt to bend some of the threading dislocations generated by lattice-mismatch between the Ge wafer and InP cell so they would be harmlessly confined in this grading layer. The best InP/Ge cell was independently measured by NASA-Lewis with a one-sun 25 C AMO efficiently measured by NASA-Lewis with a one-circuit photocurrent 22.6 mA/sq cm. We believe this is the first published report of an InP cell grown on a Ge wafer. Why get excited over a 9 percent InP/Ge cell? If we look at the cell weight and efficiency, a 9 percent InP cell on an 8 mil Ge wafer has about the same cell power density, 118 W/kg (BOL), as the best InP cell ever made, a 19 percent InP cell on an 18 mil InP wafer, because of the lighter Ge wafer weight. As cell panel materials become lighter, the cell weight becomes more important, and the advantage of lightweight cells to the panel power density becomes more important. In addition, although InP/Ge cells have a low beginning-of-life (BOL) efficiency due to dislocation defects, the InP/Ge cells are very radiation hard (end-of-life power similar to beginning-of-life). We have irradiated an InP/Ge cell with alpha particles to an equivalent fluence of 1.6 x 10(exp 16) 1 MeV electrons/sq cm and the efficiency is still 83 percent of its BOL value. At this fluence level, the power output of these InP/Ge cells matches the GaAs/Ge cell data tabulated in the JPL handbook. Data are presented

  18. BONDING ALUMINUM METALS

    Science.gov (United States)

    Noland, R.A.; Walker, D.E.

    1961-06-13

    A process is given for bonding aluminum to aluminum. Silicon powder is applied to at least one of the two surfaces of the two elements to be bonded, the two elements are assembled and rubbed against each other at room temperature whereby any oxide film is ruptured by the silicon crystals in the interface; thereafter heat and pressure are applied whereby an aluminum-silicon alloy is formed, squeezed out from the interface together with any oxide film, and the elements are bonded.

  19. Yield impact for wafer shape misregistration-based binning for overlay APC diagnostic enhancement

    Science.gov (United States)

    Jayez, David; Jock, Kevin; Zhou, Yue; Govindarajulu, Venugopal; Zhang, Zhen; Anis, Fatima; Tijiwa-Birk, Felipe; Agarwal, Shivam

    2018-03-01

    The importance of traditionally acceptable sources of variation has started to become more critical as semiconductor technologies continue to push into smaller technology nodes. New metrology techniques are needed to pursue the process uniformity requirements needed for controllable lithography. Process control for lithography has the advantage of being able to adjust for cross-wafer variability, but this requires that all processes are close in matching between process tools/chambers for each process. When this is not the case, the cumulative line variability creates identifiable groups of wafers1 . This cumulative shape based effect is described as impacting overlay measurements and alignment by creating misregistration of the overlay marks. It is necessary to understand what requirements might go into developing a high volume manufacturing approach which leverages this grouping methodology, the key inputs and outputs, and what can be extracted from such an approach. It will be shown that this line variability can be quantified into a loss of electrical yield primarily at the edge of the wafer and proposes a methodology for root cause identification and improvement. This paper will cover the concept of wafer shape based grouping as a diagnostic tool for overlay control and containment, the challenges in implementing this in a manufacturing setting, and the limitations of this approach. This will be accomplished by showing that there are identifiable wafer shape based signatures. These shape based wafer signatures will be shown to be correlated to overlay misregistration, primarily at the edge. It will also be shown that by adjusting for this wafer shape signal, improvements can be made to both overlay as well as electrical yield. These improvements show an increase in edge yield, and a reduction in yield variability.

  20. In vitro and in vivo evaluation of a sublingual fentanyl wafer formulation

    Directory of Open Access Journals (Sweden)

    Lim SCB

    2013-04-01

    Full Text Available Stephen CB Lim,1,3 Michael J Paech,2 Bruce Sunderland,3 Yandi Liu3 1Pharmacy Department, Armadale Health Service, Armadale, 2School of Medicine and Pharmacology, University of Western Australia, and Department of Anaesthesia and Pain Medicine, King Edward Memorial Hospital for Women, Subiaco, 3School of Pharmacy, Curtin Health Innovation Research Institute, Curtin University, Perth, WA, Australia Background: The objective of this study was to prepare a novel fentanyl wafer formulation by a freeze-drying method, and to evaluate its in vitro and in vivo release characteristics, including its bioavailability via the sublingual route. Methods: The wafer formulation was prepared by freeze-drying an aqueous dispersion of fentanyl containing sodium carboxymethylcellulose and amylogum as matrix formers. Uniformity of weight, friability, and dissolution testing of the fentanyl wafer was achieved using standard methods, and the residual moisture content was measured. The fentanyl wafer was also examined using scanning electron microscopy and x-ray diffraction. The absolute bioavailability of the fentanyl wafer was evaluated in 11 opioid-naïve adult female patients using a randomized crossover design. Results: In vitro release showed that almost 90% of the fentanyl dissolved in one minute. In vivo, the first detectable plasma fentanyl concentration was observed after 3.5 minutes and the peak plasma concentration between 61.5 and 67 minutes. The median absolute bioavailability was 53.0%. Conclusion: These results indicate that this wafer has potential as an alternative sublingual fentanyl formulation. Keywords: absolute bioavailability, fentanyl wafer, in vitro dissolution, in vivo study, pharmacokinetics, sublingual

  1. Copper wire bonding

    CERN Document Server

    Chauhan, Preeti S; Zhong, ZhaoWei; Pecht, Michael G

    2014-01-01

    This critical volume provides an in-depth presentation of copper wire bonding technologies, processes and equipment, along with the economic benefits and risks.  Due to the increasing cost of materials used to make electronic components, the electronics industry has been rapidly moving from high cost gold to significantly lower cost copper as a wire bonding material.  However, copper wire bonding has several process and reliability concerns due to its material properties.  Copper Wire Bonding book lays out the challenges involved in replacing gold with copper as a wire bond material, and includes the bonding process changes—bond force, electric flame off, current and ultrasonic energy optimization, and bonding tools and equipment changes for first and second bond formation.  In addition, the bond–pad metallurgies and the use of bare and palladium-coated copper wires on aluminum are presented, and gold, nickel and palladium surface finishes are discussed.  The book also discusses best practices and re...

  2. Determination of ultra-trace contaminants on silicon wafer surfaces using TXRF. Present state of the art

    International Nuclear Information System (INIS)

    Pahlke, S.; Fabry, L.; Kotz, L.; Mantler, C.; Ehmann, T.

    2000-01-01

    Recently, TXRF became a standard, on-line inspection tool for controlling the cleanliness of polished Si wafers for semiconductor use now up to 300 diameter. Wafer makers strive for an all-over metallic cleanliness of 10 atoms x cm -2 . Therefore an analytical tools must cover LOD in a range 9 atoms x cm -2 or lower. The all-over cleanliness of the whole wafer surface can analyzed using VPD/TXRF. For this chemical wafer-pre-preparation under cleanroom conditions class 1 we have developed a full automatic 'Wafer Surface Preparation System' coupled with a new generation TXRF. We have also combined this system with other independent methods for Na, Al, anions and cations. Only the combination of automatic wafer handling systems, modem analytical tools, ultra-pure water, ULSI chemicals and special cleanroom conditions provides us a chance to achieve the present and the future demands for semiconductor industry. (author)

  3. X-Ray Diffraction (XRD) Characterization Methods for Sigma=3 Twin Defects in Cubic Semiconductor (100) Wafers

    Science.gov (United States)

    Park, Yeonjoon (Inventor); Kim, Hyun Jung (Inventor); Skuza, Jonathan R. (Inventor); Lee, Kunik (Inventor); King, Glen C. (Inventor); Choi, Sang Hyouk (Inventor)

    2017-01-01

    An X-ray defraction (XRD) characterization method for sigma=3 twin defects in cubic semiconductor (100) wafers includes a concentration measurement method and a wafer mapping method for any cubic tetrahedral semiconductor wafers including GaAs (100) wafers and Si (100) wafers. The methods use the cubic semiconductor's (004) pole figure in order to detect sigma=3/{111} twin defects. The XRD methods are applicable to any (100) wafers of tetrahedral cubic semiconductors in the diamond structure (Si, Ge, C) and cubic zinc-blend structure (InP, InGaAs, CdTe, ZnSe, and so on) with various growth methods such as Liquid Encapsulated Czochralski (LEC) growth, Molecular Beam Epitaxy (MBE), Organometallic Vapor Phase Epitaxy (OMVPE), Czochralski growth and Metal Organic Chemical Vapor Deposition (MOCVD) growth.

  4. A quality quantitative method of silicon direct bonding based on wavelet image analysis

    Science.gov (United States)

    Tan, Xiao; Tao, Zhi; Li, Haiwang; Xu, Tiantong; Yu, Mingxing

    2018-04-01

    The rapid development of MEMS (micro-electro-mechanical systems) has received significant attention from researchers in various fields and subjects. In particular, the MEMS fabrication process is elaborate and, as such, has been the focus of extensive research inquiries. However, in MEMS fabrication, component bonding is difficult to achieve and requires a complex approach. Thus, improvements in bonding quality are relatively important objectives. A higher quality bond can only be achieved with improved measurement and testing capabilities. In particular, the traditional testing methods mainly include infrared testing, tensile testing, and strength testing, despite the fact that using these methods to measure bond quality often results in low efficiency or destructive analysis. Therefore, this paper focuses on the development of a precise, nondestructive visual testing method based on wavelet image analysis that is shown to be highly effective in practice. The process of wavelet image analysis includes wavelet image denoising, wavelet image enhancement, and contrast enhancement, and as an end result, can display an image with low background noise. In addition, because the wavelet analysis software was developed with MATLAB, it can reveal the bonding boundaries and bonding rates to precisely indicate the bond quality at all locations on the wafer. This work also presents a set of orthogonal experiments that consist of three prebonding factors, the prebonding temperature, the positive pressure value and the prebonding time, which are used to analyze the prebonding quality. This method was used to quantify the quality of silicon-to-silicon wafer bonding, yielding standard treatment quantities that could be practical for large-scale use.

  5. Impedance-based structural health monitoring of additive manufactured structures with embedded piezoelectric wafers

    Science.gov (United States)

    Scheyer, Austin G.; Anton, Steven R.

    2017-04-01

    Embedding sensors within additive manufactured (AM) structures gives the ability to develop smart structures that are capable of monitoring the mechanical health of a system. AM provides an opportunity to embed sensors within a structure during the manufacturing process. One major limitation of AM technology is the ability to verify the geometric and material properties of fabricated structures. Over the past several years, the electromechanical impedance (EMI) method for structural health monitoring (SHM) has been proven to be an effective method for sensing damage in structurers. The EMI method utilizes the coupling between the electrical and mechanical properties of a piezoelectric transducer to detect a change in the dynamic response of a structure. A piezoelectric device, usually a lead zirconate titanate (PZT) ceramic wafer, is bonded to a structure and the electrical impedance is measured across as range of frequencies. A change in the electrical impedance is directly correlated to changes made to the mechanical condition of the structure. In this work, the EMI method is employed on piezoelectric transducers embedded inside AM parts to evaluate the feasibility of performing SHM on parts fabricated using additive manufacturing. The fused deposition modeling (FDM) method is used to print specimens for this feasibility study. The specimens are printed from polylactic acid (PLA) in the shape of a beam with an embedded monolithic piezoelectric ceramic disc. The specimen is mounted as a cantilever while impedance measurements are taken using an HP 4194A impedance analyzer. Both destructive and nondestructive damage is simulated in the specimens by adding an end mass and drilling a hole near the free end of the cantilever, respectively. The Root Mean Square Deviation (RMSD) method is utilized as a metric for quantifying damage to the system. In an effort to determine a threshold for RMSD, the values are calculated for the variation associated with taking multiple

  6. 120 mm Single-crystalline perovskite and wafers: towards viable applications

    Institute of Scientific and Technical Information of China (English)

    Yucheng Liu; Bo Wang; Qingbo Wei; Fengwei Xiao; Haibo Fan; Hao Deng; Liangping Deng; Shengzhong (Frank) Liu; Xiaodong Ren; Jing Zhang; Zhou Yang; Dong Yang; Fengyang Yu; Jiankun Sun; Changming Zhao; Zhun Yao

    2017-01-01

    As the large single-crystalline silicon wafers have revolutionized many industries including electronics and solar cells,it is envisioned that the availability of large single-crystalline perovskite crystals and wafers will revolutionize its broad applications in photovoltaics,optoelectronics,lasers,photodetectors,light emitting diodes (LEDs),etc.Here we report a method to grow large single-crystalline perovskites including single-halide crystals:CH3NH3PbX3 (X=Ⅰ,Br,Cl),and dual-halide ones:CH3NH3Pb(ClxBr1-x)3 and CH3NH3Pb(BrxI1-x)3,with the largest crystal being 120 mm in length.Meanwhile,we have advanced a process to slice the large perovskite crystals into thin wafers.It is found that the wafers exhibit remarkable features:(1) its trap-state density is a million times smaller than that in the microcrystalline perovskite thin films (MPTF);(2) its carrier mobility is 410 times higher than its most popular organic counterpart P3HT;(3) its optical absorption is expanded to as high as 910 nm comparing to 797 nm for the MPTF;(4) while MPTF decomposes at 150 ℃,the wafer is stable at high temperature up to 270 ℃;(5) when exposed to high humidity (75% RH),MPTF decomposes in 5 h while the wafer shows no change for overnight;(6) its photocurrent response is 250 times higher than its MPTF counterpart.A few electronic devices have been fabricated using the crystalline wafers.Among them,the Hall test gives low carrier concentration with high mobility.The trap-state density is measured much lower than common semiconductors.Moreover,the large SC-wafer is found particularly useful for mass production of integrated circuits.By adjusting the halide composition,both the optical absorption and the light emission can be fine-tuned across the entire visible spectrum from 400 nm to 800 nm.It is envisioned that a range of visible lasers and LEDs may be developed using the dual-halide perovskites.With fewer trap states,high mobility,broader absorption,and humidity resistance,it is

  7. Qualification of multi-crystalline silicon wafers by optical imaging for industrial use

    Energy Technology Data Exchange (ETDEWEB)

    Janssen, G.J.M.; Van der Borg, N.J.C.M.; Manshanden, P.; De Bruijne, M.; Bende, E.E. [ECN Solar Energy, Petten (Netherlands)

    2012-09-15

    We have developed a method to qualify multi-crystalline silicon (mc-Si) wafers that are being used in a production process. An optical image of an etched wafer is made. This etching can be a standard industrial acid etching for mc-Si wafers as is commonly used for saw damage removal and simultaneous iso-texturing. Digital image processing is then applied to identify the number of dislocations and their distribution over the wafer. This information is used as input for a cell performance prediction model, where the performance is characterized by the open circuit voltage (Voc) or the efficiency. The model can include various levels of sophistication, i.e. from using an average density of dislocations to the full spatial resolution of the dislocations in a 2D simulation that includes also the metallization pattern on the cell. The predicted performance is then evaluated against pre-selected criteria. The possibility to apply this optical qualification method in an initial stage in the production enables early rejection of the wafers, further tailoring of the cell production process or identification of instabilities in the production process.

  8. Palladium-based on-wafer electroluminescence studies of GaN-based LED structures

    Energy Technology Data Exchange (ETDEWEB)

    Salcianu, C.O.; Thrush, E.J.; Humphreys, C.J. [Department of Materials Science and Metallurgy, University of Cambridge, Pembroke Street, Cambridge CB2 3QZ (United Kingdom); Plumb, R.G. [Centre for Photonic Systems, Department of Engineering, University of Cambridge, Cambridge CB3 0FD (United Kingdom); Boyd, A.R.; Rockenfeller, O.; Schmitz, D.; Heuken, M. [AIXTRON AG, Kackertstr. 15-17, 52072 Aachen (Germany)

    2008-07-01

    Electroluminescence (EL) testing of Light Emitting Diode (LED) structures is usually done at the chip level. Assessing the optical and electrical properties of LED structures at the wafer scale prior to their processing would improve the cost effectiveness of producing LED-lamps. A non-destructive method for studying the luminescence properties of the structure at the wafer-scale is photoluminescence (PL). However, the relationship between the on-wafer PL data and the final device EL can be less than straightforward (Y. H Aliyu et al., Meas. Sci. Technol. 8, 437 (1997)) as the two techniques employ different carrier injection mechanisms. This paper provides an overview of some different techniques in which palladium is used as a contact in order to obtain on-wafer electroluminescence information which could be used to screen wafers prior to processing into final devices. Quick mapping of the electrical and optical characteristics was performed using either palladium needle electrodes directly, or using the latter in conjunction with evaporated palladium contacts to inject both electrons and holes into the active region via the p-type capping layer of the structure. For comparison, indium was also used to make contact to the n-layer so that electrons could be directly injected into that layer. (copyright 2008 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

  9. Analysis and wafer-level design of a high-order silicon vibration isolator for resonating MEMS devices

    International Nuclear Information System (INIS)

    Yoon, Sang Won; Lee, Sangwoo; Najafi, Khalil; Perkins, Noel C

    2011-01-01

    This paper presents the analysis and preliminary design, fabrication, and measurement for mechanical vibration-isolation platforms especially designed for resonating MEMS devices including gyroscopes. Important parameters for designing isolation platforms are specified and the first platform (in designs with cascaded multiple platforms) is crucial for improving vibration-isolation performance and minimizing side-effects on integrated gyroscopes. This isolation platform, made from a thick silicon wafer substrate for an environment-resistant MEMS package, incorporates the functionalities of a previous design including vacuum packaging and thermal resistance with no additional resources. This platform consists of platform mass, isolation beams, vertical feedthroughs, and bonding pads. Two isolation platform designs follow from two isolation beam designs: lateral clamped–clamped beams and vertical torsion beams. The beams function simultaneously as mechanical springs and electrical interconnects. The vibration-isolation platform can yield a multi-dimensional, high-order mechanical low pass filter. The isolation platform possesses eight interconnects within a 12.2 × 12.2 mm 2 footprint. The contact resistance ranges from 4–11 Ω depending on the beam design. Vibration measurements using a laser-Doppler vibrometer demonstrate that the lateral vibration-isolation platform suppresses external vibration having frequencies exceeding 2.1 kHz.

  10. Transversely Compressed Bonded Joints

    DEFF Research Database (Denmark)

    Hansen, Christian Skodborg; Schmidt, Jacob Wittrup; Stang, Henrik

    2012-01-01

    The load capacity of bonded joints can be increased if transverse pressure is applied at the interface. The transverse pressure is assumed to introduce a Coulomb-friction contribution to the cohesive law for the interface. Response and load capacity for a bonded single-lap joint was derived using...

  11. Corporate Bonds in Denmark

    DEFF Research Database (Denmark)

    Tell, Michael

    2015-01-01

    Corporate financing is the choice between capital generated by the corporation and capital from external investors. However, since the financial crisis shook the markets in 2007–2008, financing opportunities through the classical means of financing have decreased. As a result, corporations have...... to think in alternative ways such as issuing corporate bonds. A market for corporate bonds exists in countries such as Norway, Germany, France, the United Kingdom and the United States, while Denmark is still behind in this trend. Some large Danish corporations have instead used foreign corporate bonds...... markets. However, NASDAQ OMX has introduced the First North Bond Market in December 2012 and new regulatory framework came into place in 2014, which may contribute to a Danish based corporate bond market. The purpose of this article is to present the regulatory changes in Denmark in relation to corporate...

  12. Efficiency Improvement of HIT Solar Cells on p-Type Si Wafers.

    Science.gov (United States)

    Wei, Chun-You; Lin, Chu-Hsuan; Hsiao, Hao-Tse; Yang, Po-Chuan; Wang, Chih-Ming; Pan, Yen-Chih

    2013-11-22

    Single crystal silicon solar cells are still predominant in the market due to the abundance of silicon on earth and their acceptable efficiency. Different solar-cell structures of single crystalline Si have been investigated to boost efficiency; the heterojunction with intrinsic thin layer (HIT) structure is currently the leading technology. The record efficiency values of state-of-the art HIT solar cells have always been based on n-type single-crystalline Si wafers. Improving the efficiency of cells based on p-type single-crystalline Si wafers could provide broader options for the development of HIT solar cells. In this study, we varied the thickness of intrinsic hydrogenated amorphous Si layer to improve the efficiency of HIT solar cells on p-type Si wafers.

  13. Terahertz transmission properties of silicon wafers using continuous-wave terahertz spectroscopy

    Science.gov (United States)

    Kim, Chihoon; Ahn, Jae Sung; Ji, Taeksoo; Eom, Joo Beom

    2017-04-01

    We present the spectral properties of Si wafers using continuous-wave terahertz (CW-THz) spectroscopy. By using a tunable laser source and a fixed distributed-feedback laser diode (DFB-LD), a stably tunable beat source for CW-THz spectroscopy system can be implemented. THz radiation is generated in the frequency range of 100 GHz-800 GHz by photomixing in a photoconductive antenna. We also measured CW-THz waveforms by changing the beat frequency and confirmed repeatability through repeated measurement. We calculated the peaks of the THz frequency by taking fast Fourier transforms (FFTs) of measured THz waveforms. The feasibility of CW-THz spectroscopy is demonstrated by the THz spectra of Si wafers with different resistivities, mobilities, and carrier concentrations. The results show that Si wafers with a lower resistivity absorb more THz waves. Thus, we expect our CW-THz system to have the advantage of being able to perform fast non-destructive analysis.

  14. Terahertz transmission properties of silicon wafers using continuous-wave terahertz spectroscopy

    International Nuclear Information System (INIS)

    Kim, Chihoon; Ahn, Jae Sung; Eom, Joo Beom; Ji, Taeksoo

    2017-01-01

    We present the spectral properties of Si wafers using continuous-wave terahertz (CW-THz) spectroscopy. By using a tunable laser source and a fixed distributed-feedback laser diode (DFB-LD), a stably tunable beat source for CW-THz spectroscopy system can be implemented. THz radiation is generated in the frequency range of 100 GHz–800 GHz by photomixing in a photoconductive antenna. We also measured CW-THz waveforms by changing the beat frequency and confirmed repeatability through repeated measurement. We calculated the peaks of the THz frequency by taking fast Fourier transforms (FFTs) of measured THz waveforms. The feasibility of CW-THz spectroscopy is demonstrated by the THz spectra of Si wafers with different resistivities, mobilities, and carrier concentrations. The results show that Si wafers with a lower resistivity absorb more THz waves. Thus, we expect our CW-THz system to have the advantage of being able to perform fast non-destructive analysis. (paper)

  15. Electrical characterization of thin SOI wafers using lateral MOS transient capacitance measurements

    International Nuclear Information System (INIS)

    Wang, D.; Ueda, A.; Takada, H.; Nakashima, H.

    2006-01-01

    A novel electrical evaluation method was proposed for crystal quality characterization of thin Si on insulator (SOI) wafers, which was done by measurement of minority carrier generation lifetime (τ g ) using transient capacitance method for lateral metal-oxide-semiconductor (MOS) capacitor. The lateral MOS capacitors were fabricated on three kinds of thin SOI wafers. The crystal quality difference among these three wafers was clearly shown by the τ g measurement results and discussed from a viewpoint of SOI fabrication. The series resistance influence on the capacitance measurement for this lateral MOS capacitor was discussed in detail. The validity of this method was confirmed by comparing the intensities of photoluminescence signals due to electron-hole droplet in the band-edge emission

  16. Uncertainty evaluation of thickness and warp of a silicon wafer measured by a spectrally resolved interferometer

    Science.gov (United States)

    Praba Drijarkara, Agustinus; Gergiso Gebrie, Tadesse; Lee, Jae Yong; Kang, Chu-Shik

    2018-06-01

    Evaluation of uncertainty of thickness and gravity-compensated warp of a silicon wafer measured by a spectrally resolved interferometer is presented. The evaluation is performed in a rigorous manner, by analysing the propagation of uncertainty from the input quantities through all the steps of measurement functions, in accordance with the ISO Guide to the Expression of Uncertainty in Measurement. In the evaluation, correlation between input quantities as well as uncertainty attributed to thermal effect, which were not included in earlier publications, are taken into account. The temperature dependence of the group refractive index of silicon was found to be nonlinear and varies widely within a wafer and also between different wafers. The uncertainty evaluation described here can be applied to other spectral interferometry applications based on similar principles.

  17. Design and implementation of a S-parameter wafer defect scanner

    International Nuclear Information System (INIS)

    Naik, P.S.; Beling, C.D.; Fung, S.

    2004-01-01

    We describe the design and implementation of a real-time automated scanning system that gives an S-parameter image of a semiconductor wafer, thus allowing the density of vacancy type defects to be shown as a function of position on the wafer. A conventional 22 Na positron source of 0.5 mm diameter rasters across 5 x 5 cm 2 region of two times per hour in rectilinear motion. Gamma ray energies E γ are processed using a standard HP Ge spectroscopy system and a 14 bit nuclear ADC. Over a period of 1-2 days a high resolution 128 x 128 pixel image with 256 colours (scaled to the S-parameter range) can be formed as a wafer defect map. The system is reliable, interactive and user-friendly (patent pending 2003). (orig.)

  18. Wafer defect detection by a polarization-insensitive external differential interference contrast module.

    Science.gov (United States)

    Nativ, Amit; Feldman, Haim; Shaked, Natan T

    2018-05-01

    We present a system that is based on a new external, polarization-insensitive differential interference contrast (DIC) module specifically adapted for detecting defects in semiconductor wafers. We obtained defect signal enhancement relative to the surrounding wafer pattern when compared with bright-field imaging. The new DIC module proposed is based on a shearing interferometer that connects externally at the output port of an optical microscope and enables imaging thin samples, such as wafer defects. This module does not require polarization optics (such as Wollaston or Nomarski prisms) and is insensitive to polarization, unlike traditional DIC techniques. In addition, it provides full control of the DIC shear and orientation, which allows obtaining a differential phase image directly on the camera (with no further digital processing) while enhancing defect detection capabilities, even if the size of the defect is smaller than the resolution limit. Our technique has the potential of future integration into semiconductor production lines.

  19. Preparation of freestanding GaN wafer by hydride vapor phase epitaxy on porous silicon

    Science.gov (United States)

    Wu, Xian; Li, Peng; Liang, Renrong; Xiao, Lei; Xu, Jun; Wang, Jing

    2018-05-01

    A freestanding GaN wafer was prepared on porous Si (111) substrate using hydride vapor phase epitaxy (HVPE). To avoid undesirable effects of the porous surface on the crystallinity of the GaN, a GaN seed layer was first grown on the Si (111) bare wafer. A pattern with many apertures was fabricated in the GaN seed layer using lithography and etching processes. A porous layer was formed in the Si substrate immediately adjacent to the GaN seed layer by an anodic etching process. A 500-μm-thick GaN film was then grown on the patterned GaN seed layer using HVPE. The GaN film was separated from the Si substrate through the formation of cracks in the porous layer caused by thermal mismatch stress during the cooling stage of the HVPE. Finally, the GaN film was polished to obtain a freestanding GaN wafer.

  20. Bonding temperature dependence of GaInAsP/InP laser diode grown on hydrophilically directly bonded InP/Si substrate

    Science.gov (United States)

    Aikawa, Masaki; Onuki, Yuya; Hayasaka, Natsuki; Nishiyama, Tetsuo; Kamada, Naoki; Han, Xu; Kallarasan Periyanayagam, Gandhi; Uchida, Kazuki; Sugiyama, Hirokazu; Shimomura, Kazuhiko

    2018-02-01

    The bonding-temperature-dependent lasing characteristics of 1.5 a µm GaInAsP laser diode (LD) grown on a directly bonded InP/Si substrate were successfully obtained. We have fabricated the InP/Si substrate using a direct hydrophilic wafer bonding technique at bonding temperatures of 350, 400, and 450 °C, and deposited GaInAsP/InP double heterostructure layers on this InP/Si substrate. The surface conditions, X-ray diffraction (XRD) analysis, photoluminescence (PL) spectra, and electrical characteristics after the growth were compared at these bonding temperatures. No significant differences were confirmed in X-ray diffraction analysis and PL spectra at these bonding temperatures. We realized the room-temperature lasing of the GaInAsP LD on the InP/Si substrate bonded at 350 and 400 °C. The threshold current densities were 4.65 kA/cm2 at 350 °C and 4.38 kA/cm2 at 400 °C. The electrical resistance was found to increase with annealing temperature.

  1. Aerial image measurement technique for automated reticle defect disposition (ARDD) in wafer fabs

    Science.gov (United States)

    Zibold, Axel M.; Schmid, Rainer M.; Stegemann, B.; Scheruebl, Thomas; Harnisch, Wolfgang; Kobiyama, Yuji

    2004-08-01

    The Aerial Image Measurement System (AIMS)* for 193 nm lithography emulation has been brought into operation successfully worldwide. A second generation system comprising 193 nm AIMS capability, mini-environment and SMIF, the AIMS fab 193 plus is currently introduced into the market. By adjustment of numerical aperture (NA), illumination type and partial illumination coherence to match the conditions in 193 nm steppers or scanners, it can emulate the exposure tool for any type of reticles like binary, OPC and PSM down to the 65 nm node. The system allows a rapid prediction of wafer printability of defects or defect repairs, and critical features, like dense patterns or contacts on the masks without the need to perform expensive image qualification consisting of test wafer exposures followed by SEM measurements. Therefore, AIMS is a mask quality verification standard for high-end photo masks and established in mask shops worldwide. The progress on the AIMS technology described in this paper will highlight that besides mask shops there will be a very beneficial use of the AIMS in the wafer fab and we propose an Automated Reticle Defect Disposition (ARDD) process. With smaller nodes, where design rules are 65 nm or less, it is expected that smaller defects on reticles will occur in increasing numbers in the wafer fab. These smaller mask defects will matter more and more and become a serious yield limiting factor. With increasing mask prices and increasing number of defects and severability on reticles it will become cost beneficial to perform defect disposition on the reticles in wafer production. Currently ongoing studies demonstrate AIMS benefits for wafer fab applications. An outlook will be given for extension of 193 nm aerial imaging down to the 45 nm node based on emulation of immersion scanners.

  2. Electronics and Sensor Study with the OKI SOI process

    CERN Document Server

    Arai, Yasuo

    2007-01-01

    While the SOI (Silicon-On-Insulator) device concept is very old, commercialization of the technology is relatively new and growing rapidly in high-speed processor and lowpower applications. Furthermore, features such as latch-up immunity, radiation hardness and high-temperature operation are very attractive in high energy and space applications. Once high-quality bonded SOI wafers became available in the late 90s, it opened up the possibility to get two different kinds of Si on a single wafer. This makes it possible to realize an ideal pixel detector; pairing a fully-depleted radiation sensor with CMOS circuitry in an industrial technology. In 2005 we started Si pixel R&D with OKI Electric Ind. Co., Ltd. which is the first market supplier of Fully-Depleted SOI products. We have developed processes for p+/n+ implants to the substrate and for making connections between the implants and circuits in the OKI 0.15μm FD-SOI CMOS process. We have preformed two Multi Project Wafer (MPW) runs using this SOI proces...

  3. Micropore x-ray optics using anisotropic wet etching of (110) silicon wafers.

    Science.gov (United States)

    Ezoe, Yuichiro; Koshiishi, Masaki; Mita, Makoto; Mitsuda, Kazuhisa; Hoshino, Akio; Ishisaki, Yoshitaka; Yang, Zhen; Takano, Takayuki; Maeda, Ryutaro

    2006-12-10

    To develop x-ray mirrors for micropore optics, smooth silicon (111) sidewalls obtained after anisotropic wet etching of a silicon (110) wafer were studied. A sample device with 19 microm wide (111) sidewalls was fabricated using a 220 microm thick silicon (110) wafer and potassium hydroxide solution. For what we believe to be the first time, x-ray reflection on the (111) sidewalls was detected in the angular response measurement. Compared to ray-tracing simulations, the surface roughness of the sidewalls was estimated to be 3-5 nm, which is consistent with the atomic force microscope and the surface profiler measurements.

  4. Large-aperture focusing of x rays with micropore optics using dry etching of silicon wafers.

    Science.gov (United States)

    Ezoe, Yuichiro; Moriyama, Teppei; Ogawa, Tomohiro; Kakiuchi, Takuya; Mitsuishi, Ikuyuki; Mitsuda, Kazuhisa; Aoki, Tatsuhiko; Morishita, Kohei; Nakajima, Kazuo

    2012-03-01

    Large-aperture focusing of Al K(α) 1.49 keV x-ray photons using micropore optics made from a dry-etched 4 in. (100 mm) silicon wafer is demonstrated. Sidewalls of the micropores are smoothed with high-temperature annealing to work as x-ray mirrors. The wafer is bent to a spherical shape to collect parallel x rays into a focus. Our result supports that this new type of optics allows for the manufacturing of ultralight-weight and high-performance x-ray imaging optics with large apertures at low cost. © 2012 Optical Society of America

  5. Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging

    International Nuclear Information System (INIS)

    Esposito, M; Evans, P M; Wells, K; Anaxagoras, T; Konstantinidis, A C; Zheng, Y; Speller, R D; Allinson, N M

    2014-01-01

    Recently CMOS active pixels sensors (APSs) have become a valuable alternative to amorphous silicon and selenium flat panel imagers (FPIs) in bio-medical imaging applications. CMOS APSs can now be scaled up to the standard 20 cm diameter wafer size by means of a reticle stitching block process. However, despite wafer scale CMOS APS being monolithic, sources of non-uniformity of response and regional variations can persist representing a significant challenge for wafer scale sensor response. Non-uniformity of stitched sensors can arise from a number of factors related to the manufacturing process, including variation of amplification, variation between readout components, wafer defects and process variations across the wafer due to manufacturing processes. This paper reports on an investigation into the spatial non-uniformity and regional variations of a wafer scale stitched CMOS APS. For the first time a per-pixel analysis of the electro-optical performance of a wafer CMOS APS is presented, to address inhomogeneity issues arising from the stitching techniques used to manufacture wafer scale sensors. A complete model of the signal generation in the pixel array has been provided and proved capable of accounting for noise and gain variations across the pixel array. This novel analysis leads to readout noise and conversion gain being evaluated at pixel level, stitching block level and in regions of interest, resulting in a coefficient of variation ⩽1.9%. The uniformity of the image quality performance has been further investigated in a typical x-ray application, i.e. mammography, showing a uniformity in terms of CNR among the highest when compared with mammography detectors commonly used in clinical practice. Finally, in order to compare the detection capability of this novel APS with the technology currently used (i.e. FPIs), theoretical evaluation of the detection quantum efficiency (DQE) at zero-frequency has been performed, resulting in a higher DQE for this

  6. Micropore x-ray optics using anisotropic wet etching of (110) silicon wafers

    International Nuclear Information System (INIS)

    Ezoe, Yuichiro; Koshiishi, Masaki; Mita, Makoto; Mitsuda, Kazuhisa; Hoshino, Akio; Ishisaki, Yoshitaka; Yang Zhen; Takano, Takayuki; Maeda, Ryutaro

    2006-01-01

    To develop x-ray mirrors for micropore optics, smooth silicon (111)sidewalls obtained after anisotropic wet etching of a silicon (110) wafer were studied. A sample device with 19 μm wide (111) sidewalls was fabricated using a 220 μm thick silicon (110) wafer and potassium hydroxide solution. For what we believe to be the first time,x-ray reflection on the (111) sidewalls was detected in the angular response measurement. Compared to ray-tracing simulations, the surface roughness of the sidewalls was estimated to be 3-5 nm, which is consistent with the atomic force microscope and the surface profiler measurements

  7. First thin AC-coupled silicon strip sensors on 8-inch wafers

    Energy Technology Data Exchange (ETDEWEB)

    Bergauer, T., E-mail: thomas.bergauer@oeaw.ac.at [Institute of High Energy Physics of the Austrian Academy of Sciences, Nikolsdorfer Gasse 18, 1050 Wien (Vienna) (Austria); Dragicevic, M.; König, A. [Institute of High Energy Physics of the Austrian Academy of Sciences, Nikolsdorfer Gasse 18, 1050 Wien (Vienna) (Austria); Hacker, J.; Bartl, U. [Infineon Technologies Austria AG, Siemensstrasse 2, 9500 Villach (Austria)

    2016-09-11

    The Institute of High Energy Physics (HEPHY) in Vienna and the semiconductor manufacturer Infineon Technologies Austria AG developed a production process for planar AC-coupled silicon strip sensors manufactured on 200 μm thick 8-inch p-type wafers. In late 2015, the first wafers were delivered featuring the world's largest AC-coupled silicon strip sensors. Detailed electrical measurements were carried out at HEPHY, where single strip and global parameters were measured. Mechanical studies were conducted and the long-term behavior was investigated using a climate chamber. Furthermore, the electrical properties of various test structures were investigated to validate the quality of the manufacturing process.

  8. EM Simulation Accuracy Enhancement for Broadband Modeling of On-Wafer Passive Components

    DEFF Research Database (Denmark)

    Johansen, Tom Keinicke; Jiang, Chenhui; Hadziabdic, Dzenan

    2007-01-01

    This paper describes methods for accuracy enhancement in broadband modeling of on-wafer passive components using electromagnetic (EM) simulation. It is shown that standard excitation schemes for integrated component simulation leads to poor correlation with on-wafer measurements beyond the lower...... GHz frequency range. We show that this is due to parasitic effects and higher-order modes caused by the excitation schemes. We propose a simple equivalent circuit for the parasitic effects in the well-known ground ring excitation scheme. An extended L-2L calibration method is shown to improve...

  9. Introduction of high oxygen concentrations into silicon wafers by high-temperature diffusion

    International Nuclear Information System (INIS)

    Casse, G.; Glaser, M.; Lemeilleur, F.; Ruzin, A.; Wegrzecki, M.

    1999-01-01

    The tolerance of silicon detectors to hadron irradiation can be improved by the introduction of a high concentration of oxygen into the starting material. High-resistivity Floating-Zone (FZ) silicon is required for detectors used in particle physics applications. A significantly high oxygen concentration (>10 17 atoms cm -3 ) cannot readily be achieved during the FZ silicon refinement. The diffusion of oxygen at elevated temperatures from a SiO 2 layer grown on both sides of a silicon wafer is a simple and effective technique to achieve high and uniform concentrations of oxygen throughout the bulk of a 300 μm thick silicon wafer

  10. Novel SU-8 based vacuum wafer-level packaging for MEMS devices

    DEFF Research Database (Denmark)

    Murillo, Gonzalo; Davis, Zachary James; Keller, Stephan Urs

    2010-01-01

    This work presents a simple and low-cost SU-8 based wafer-level vacuum packaging method which is CMOS and MEMS compatible. Different approaches have been investigated by taking advantage of the properties of SU-8, such as chemical resistance, optical transparence, mechanical reliability and versa......This work presents a simple and low-cost SU-8 based wafer-level vacuum packaging method which is CMOS and MEMS compatible. Different approaches have been investigated by taking advantage of the properties of SU-8, such as chemical resistance, optical transparence, mechanical reliability...

  11. Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging.

    Science.gov (United States)

    Esposito, M; Anaxagoras, T; Konstantinidis, A C; Zheng, Y; Speller, R D; Evans, P M; Allinson, N M; Wells, K

    2014-07-07

    Recently CMOS active pixels sensors (APSs) have become a valuable alternative to amorphous silicon and selenium flat panel imagers (FPIs) in bio-medical imaging applications. CMOS APSs can now be scaled up to the standard 20 cm diameter wafer size by means of a reticle stitching block process. However, despite wafer scale CMOS APS being monolithic, sources of non-uniformity of response and regional variations can persist representing a significant challenge for wafer scale sensor response. Non-uniformity of stitched sensors can arise from a number of factors related to the manufacturing process, including variation of amplification, variation between readout components, wafer defects and process variations across the wafer due to manufacturing processes. This paper reports on an investigation into the spatial non-uniformity and regional variations of a wafer scale stitched CMOS APS. For the first time a per-pixel analysis of the electro-optical performance of a wafer CMOS APS is presented, to address inhomogeneity issues arising from the stitching techniques used to manufacture wafer scale sensors. A complete model of the signal generation in the pixel array has been provided and proved capable of accounting for noise and gain variations across the pixel array. This novel analysis leads to readout noise and conversion gain being evaluated at pixel level, stitching block level and in regions of interest, resulting in a coefficient of variation ⩽1.9%. The uniformity of the image quality performance has been further investigated in a typical x-ray application, i.e. mammography, showing a uniformity in terms of CNR among the highest when compared with mammography detectors commonly used in clinical practice. Finally, in order to compare the detection capability of this novel APS with the technology currently used (i.e. FPIs), theoretical evaluation of the detection quantum efficiency (DQE) at zero-frequency has been performed, resulting in a higher DQE for this

  12. Glass frit bonding with controlled width and height using a two-step wet silicon etching procedure

    Science.gov (United States)

    Yifang, Liu; Daner, Chen; Liwei, Lin; Gaofeng, Zheng; Jianyi, Zheng; Lingyun, Wang; Daoheng, Sun

    2016-03-01

    A simple and versatile two-step silicon wet etching technique for the control of the width and height of the glass frit bonding layer has been developed to improve bonding strength and reliability in wafer-level microelectromechanical systems (MEMS) packaging processes. The height of the glass frit bonding layer is set by the design of a vertical reference wall which regulates the distance between the silicon wafer and the encapsulation capping substrate. On the other hand, the width of the bonding layer is constrained between two micro grooves which are used to accommodate the spillages of extra glass frit during the bonding process. An optimized thermal bonding process, including the formation of glass liquid, removal of gas bubbles under vacuum and the filling of voids under normal atmospheric condition has been developed to suppress the formation of the bubbles/voids. The stencil printing and pre-sintering processes for the glass frit have been characterized before the thermal bonding process under different magnitudes of bonding pressure. The bonding gap thickness is found to be equal to the height of the reference wall of 10 μm in the prototype design. The bubbles/voids are found to be suppressed effectively and the bonding strength increases from 10.2 to 19.1 MPa as compared with a conventional thermal annealing process in air. Experimentally, prototype samples are measured to have passed the high hermetic sealing leakage tests of 5  ×  10-8 atm cc s-1.

  13. Thin film metal sensors in fusion bonded glass chips for high-pressure microfluidics

    International Nuclear Information System (INIS)

    Andersson, Martin; Ek, Johan; Hedman, Ludvig; Johansson, Fredrik; Sehlstedt, Viktor; Stocklassa, Jesper; Snögren, Pär; Pettersson, Victor; Larsson, Jonas; Vizuete, Olivier; Hjort, Klas; Klintberg, Lena

    2017-01-01

    High-pressure microfluidics offers fast analyses of thermodynamic parameters for compressed process solvents. However, microfluidic platforms handling highly compressible supercritical CO 2 are difficult to control, and on-chip sensing would offer added control of the devices. Therefore, there is a need to integrate sensors into highly pressure tolerant glass chips. In this paper, thin film Pt sensors were embedded in shallow etched trenches in a glass wafer that was bonded with another glass wafer having microfluidic channels. The devices having sensors integrated into the flow channels sustained pressures up to 220 bar, typical for the operation of supercritical CO 2 . No leakage from the devices could be found. Integrated temperature sensors were capable of measuring local decompression cooling effects and integrated calorimetric sensors measured flow velocities over the range 0.5–13.8 mm s −1 . By this, a better control of high-pressure microfluidic platforms has been achieved. (paper)

  14. Suppression of interfacial voids formation during silane (SiH4)-based silicon oxide bonding with a thin silicon nitride capping layer

    Science.gov (United States)

    Lee, Kwang Hong; Bao, Shuyu; Wang, Yue; Fitzgerald, Eugene A.; Seng Tan, Chuan

    2018-01-01

    The material properties and bonding behavior of silane-based silicon oxide layers deposited by plasma-enhanced chemical vapor deposition were investigated. Fourier transform infrared spectroscopy was employed to determine the chemical composition of the silicon oxide films. The incorporation of hydroxyl (-OH) groups and moisture absorption demonstrates a strong correlation with the storage duration for both as-deposited and annealed silicon oxide films. It is observed that moisture absorption is prevalent in the silane-based silicon oxide film due to its porous nature. The incorporation of -OH groups and moisture absorption in the silicon oxide films increase with the storage time (even in clean-room environments) for both as-deposited and annealed silicon oxide films. Due to silanol condensation and silicon oxidation reactions that take place at the bonding interface and in the bulk silicon, hydrogen (a byproduct of these reactions) is released and diffused towards the bonding interface. The trapped hydrogen forms voids over time. Additionally, the absorbed moisture could evaporate during the post-bond annealing of the bonded wafer pair. As a consequence, defects, such as voids, form at the bonding interface. To address the problem, a thin silicon nitride capping film was deposited on the silicon oxide layer before bonding to serve as a diffusion barrier to prevent moisture absorption and incorporation of -OH groups from the ambient. This process results in defect-free bonded wafers.

  15. Bond markets in Africa

    Directory of Open Access Journals (Sweden)

    Yibin Mu

    2013-07-01

    Full Text Available African bond markets have been steadily growing in recent years, but nonetheless remain undeveloped. African countries would benefit from greater access to financing and deeper financial markets. This paper compiles a unique set of data on government securities and corporate bond markets in Africa. It then applies an econometric model to analyze the key determinants of African government securities market and corporate bond market capitalization. Government securities market capitalization is directly related to better institutions and interest rate volatility, and inversely related to smaller fiscal deficits, higher interest rate spreads, exchange rate volatility, and current and capital account openness. Corporate bond market capitalization is directly linked to economic size, the level of development of the economy and financial markets, better institutions, and interest rate volatility, and inversely related to higher interest rate spreads and current account openness. Policy implications follow.

  16. Diffusion bonding techniques

    International Nuclear Information System (INIS)

    Peters, R.D.

    1978-01-01

    The applications of diffusion bonding at the General Electric Neutron Devices Department are briefly discussed, with particular emphasis on the gold/gold or gold/indium joints made between metallized alumina ceramic parts in the vacuum switch tube and the crystal resonator programs. Fixtures which use the differential expansion of dissimilar metals are described and compared to one that uses hydraulic pressure to apply the necessary bonding force

  17. Improvement of the thickness distribution of a quartz crystal wafer by numerically controlled plasma chemical vaporization machining

    International Nuclear Information System (INIS)

    Shibahara, Masafumi; Yamamura, Kazuya; Sano, Yasuhisa; Sugiyama, Tsuyoshi; Endo, Katsuyoshi; Mori, Yuzo

    2005-01-01

    To improve the thickness uniformity of thin quartz crystal wafer, a new machining process that utilizes an atmospheric pressure plasma was developed. In an atmospheric pressure plasma process, since the kinetic energy of ions that impinge to the wafer surface is small and the density of the reactive species is large, high-efficiency machining without damage is realized, and the thickness distribution is corrected by numerically controlled scanning of the quartz wafer to the localized high-density plasma. By using our developed machining process, the thickness distribution of an AT cut wafer was improved from 174 nm [peak to valley (p-v)] to 67 nm (p-v) within 94 s. Since there are no unwanted spurious modes in the machined quartz wafer, it was proved that the developed machining method has a high machining efficiency without any damage

  18. Camera-Based Lock-in and Heterodyne Carrierographic Photoluminescence Imaging of Crystalline Silicon Wafers

    Science.gov (United States)

    Sun, Q. M.; Melnikov, A.; Mandelis, A.

    2015-06-01

    Carrierographic (spectrally gated photoluminescence) imaging of a crystalline silicon wafer using an InGaAs camera and two spread super-bandgap illumination laser beams is introduced in both low-frequency lock-in and high-frequency heterodyne modes. Lock-in carrierographic images of the wafer up to 400 Hz modulation frequency are presented. To overcome the frame rate and exposure time limitations of the camera, a heterodyne method is employed for high-frequency carrierographic imaging which results in high-resolution near-subsurface information. The feasibility of the method is guaranteed by the typical superlinearity behavior of photoluminescence, which allows one to construct a slow enough beat frequency component from nonlinear mixing of two high frequencies. Intensity-scan measurements were carried out with a conventional single-element InGaAs detector photocarrier radiometry system, and the nonlinearity exponent of the wafer was found to be around 1.7. Heterodyne images of the wafer up to 4 kHz have been obtained and qualitatively analyzed. With the help of the complementary lock-in and heterodyne modes, camera-based carrierographic imaging in a wide frequency range has been realized for fundamental research and industrial applications toward in-line nondestructive testing of semiconductor materials and devices.

  19. Comparison of on-wafer calibrations using the concept of reference impedance

    OpenAIRE

    Purroy Martín, Francesc; Pradell i Cara, Lluís

    1993-01-01

    A novel method that allows to compare different calibration techniques has been developed. It is based on determining the reference impedance of a given Network Analyzer calibration from the reflection coefficient measurement of a physical open circuit. The method has been applied to several on-wafer calibrations. Peer Reviewed

  20. Spatially resolved localized vibrational mode spectroscopy of carbon in liquid encapsulated Czochralski grown gallium arsenide wafers

    International Nuclear Information System (INIS)

    Yau, Waifan.

    1988-04-01

    Substitutional carbon on an arsenic lattice site is the shallowest and one of the most dominant acceptors in semi-insulating Liquid Encapsulated Czochralski (LEC) GaAs. However, the role of this acceptor in determining the well known ''W'' shape spatial variation of neutral EL2 concentration along the diameter of a LEC wafer is not known. In this thesis, we attempt to clarify the issue of the carbon acceptor's effect on this ''W'' shaped variation by measuring spatial profiles of this acceptor along the radius of three different as-grown LEC GaAs wafers. With localized vibrational mode absorption spectroscopy, we find that the profile of the carbon acceptor is relatively constant along the radius of each wafer. Average values of concentration are 8 x 10E15 cm -3 , 1.1 x 10E15 cm -3 , and 2.2 x 10E15 cm -3 , respectively. In addition, these carbon acceptor LVM measurements indicate that a residual donor with concentration comparable to carbon exists in these wafers and it is a good candidate for the observed neutral EL2 concentration variation. 22 refs., 39 figs

  1. Wafer scale nano-membrane supported on a silicon microsieve using thin-film transfer technology

    NARCIS (Netherlands)

    Unnikrishnan, S.; Jansen, Henricus V.; Berenschot, Johan W.; Elwenspoek, Michael Curt

    A new micromachining method to fabricate wafer scale nano-membranes is described. The delicate thin-film nano-membrane is supported on a robust silicon microsieve fabricated by plasma etching. The silicon sieve is micromachined independently of the thin-film, which is later transferred onto it by

  2. Radiation imaging detectors made by wafer post-processing of CMOS chips

    NARCIS (Netherlands)

    Blanco Carballo, V.M.

    2009-01-01

    In this thesis several wafer post-processing steps have been applied to CMOS chips. Amplification gas strucutures are built on top of the microchips. A complete radiation imaging detector is obtained this way. Integrated Micromegas-like and GEM-like structures were fabricated on top of Timepix CMOS

  3. Wafer-scale integration of piezoelectric actuation capabilities in nanoelectromechanical systems resonators

    OpenAIRE

    DEZEST, Denis; MATHIEU, Fabrice; MAZENQ, Laurent; SOYER, Caroline; COSTECALDE, Jean; REMIENS, Denis; THOMAS, Olivier; DEÜ, Jean-François; NICU, Liviu

    2013-01-01

    In this work, we demonstrate the integration of piezoelectric actuation means on arrays of nanocantilevers at the wafer scale. We use lead titanate zirconate (PZT) as piezoelectric material mainly because of its excellent actuation properties even when geometrically constrained at extreme scale

  4. MIMO feed-forward design in wafer scanners using a gradient approximation-based algorithm

    NARCIS (Netherlands)

    Heertjes, M.F.; Hennekens, D.W.T.; Steinbuch, M.

    2010-01-01

    An experimental demonstration is given of a data-based multi-input multi-output (MIMO) feed-forward control design applied to the motion systems of a wafer scanner. Atop a nominal single-input single-output (SISO) feed-forward controller, a MIMO controller is designed having a finite impulse

  5. Automatic Semiconductor Wafer Image Segmentation for Defect Detection Using Multilevel Thresholding

    Directory of Open Access Journals (Sweden)

    Saad N.H.

    2016-01-01

    Full Text Available Quality control is one of important process in semiconductor manufacturing. A lot of issues trying to be solved in semiconductor manufacturing industry regarding the rate of production with respect to time. In most semiconductor assemblies, a lot of wafers from various processes in semiconductor wafer manufacturing need to be inspected manually using human experts and this process required full concentration of the operators. This human inspection procedure, however, is time consuming and highly subjective. In order to overcome this problem, implementation of machine vision will be the best solution. This paper presents automatic defect segmentation of semiconductor wafer image based on multilevel thresholding algorithm which can be further adopted in machine vision system. In this work, the defect image which is in RGB image at first is converted to the gray scale image. Median filtering then is implemented to enhance the gray scale image. Then the modified multilevel thresholding algorithm is performed to the enhanced image. The algorithm worked in three main stages which are determination of the peak location of the histogram, segmentation the histogram between the peak and determination of first global minimum of histogram that correspond to the threshold value of the image. The proposed approach is being evaluated using defected wafer images. The experimental results shown that it can be used to segment the defect correctly and outperformed other thresholding technique such as Otsu and iterative thresholding.

  6. Design Expert Supported Mathematical Optimization and Predictability Study of Buccoadhesive Pharmaceutical Wafers of Loratadine

    Directory of Open Access Journals (Sweden)

    Prithviraj Chakraborty

    2013-01-01

    Full Text Available Objective. The objective of this work encompasses the application of the response surface approach in the development of buccoadhesive pharmaceutical wafers of Loratadine (LOR. Methods. Experiments were performed according to a 32 factorial design to evaluate the effects of buccoadhesive polymer, sodium alginate (A, and lactose monohydrate as ingredient, of hydrophilic matrix former (B on the bioadhesive force, disintegration time, percent (% swelling index, and time taken for 70% drug release (t70%. The effect of the two independent variables on the response variables was studied by response surface plots and contour plots generated by the Design-Expert software. The desirability function was used to optimize the response variables. Results. The compatibility between LOR and the wafer excipients was confirmed by differential scanning calorimetry, FTIR spectroscopy, and X-ray diffraction (XRD analysis. Bioadhesion force, measured with TAXT2i texture analyzer, showed that the wafers had a good bioadhesive property which could be advantageous for retaining the drug into the buccal cavity. Conclusion. The observed responses taken were in agreement with the experimental values, and Loratadine wafers were produced with less experimental trials, and a patient compliant product was achieved with the concept of formulation by design.

  7. Surface evolution and stability transition of silicon wafer subjected to nano-diamond grinding

    Directory of Open Access Journals (Sweden)

    Shisheng Cai

    2017-03-01

    Full Text Available In order to obtain excellent physical properties and ultrathin devices, thinning technique plays an important role in semiconductor industry with the rapid development of wearable electronic devices. This study presents a physical nano-diamond grinding technique without any chemistry to obtain ultrathin silicon substrate. The nano-diamond with spherical shape repeats nano-cutting and penetrating surface to physically etch silicon wafer during grinding process. Nano-diamond grinding induces an ultrathin “amorphous layer” on silicon wafer and thus the mismatch strain between the amorphous layer and substrate leads to stability transition from the spherical to non-spherical deformation of the wafer. Theoretical model is proposed to predict and analyze the deformation of amorphous layer/silicon substrate system. Furthermore, the deformation bifurcation behavior of amorphous layer/silicon substrate system is analyzed. As the mismatch strain increases or thickness decreases, the amorphous layer/silicon substrate system may transit to non-spherical deformation, which is consistent to the experimental results. The amorphous layer stresses are also obtained to predict the damage of silicon wafer.

  8. Synchronizing decentralized control loops for overall performance enhancement : a Youla framework applied to a wafer scanner

    NARCIS (Netherlands)

    Evers, E.; van de Wal, M.M.J.; Oomen, T.A.E.

    2017-01-01

    Manufacturing equipment often consists of multiple subsystems. For instance, in lithographic IC manufacturing, both a reticle stage and a wafer stage move synchronously. Traditionally, these subsystems are divided into manageable subproblems, at the expense of a suboptimal overall solution. The aim

  9. Sidewall patterning - A new wafer-scale method for accurate patterning of vertical silicon structures

    NARCIS (Netherlands)

    Westerik, P. J.; Vijselaar, W. J.C.; Berenschot, J. W.; Tas, N. R.; Huskens, J.; Gardeniers, J. G.E.

    2018-01-01

    For the definition of wafer scale micro- and nanostructures, in-plane geometry is usually controlled by optical lithography. However, options for precisely patterning structures in the out-of-plane direction are much more limited. In this paper we present a versatile self-aligned technique that

  10. Ultimate intra-wafer critical dimension uniformity control by using lithography and etch tool corrections

    Science.gov (United States)

    Kubis, Michael; Wise, Rich; Reijnen, Liesbeth; Viatkina, Katja; Jaenen, Patrick; Luca, Melisa; Mernier, Guillaume; Chahine, Charlotte; Hellin, David; Kam, Benjamin; Sobieski, Daniel; Vertommen, Johan; Mulkens, Jan; Dusa, Mircea; Dixit, Girish; Shamma, Nader; Leray, Philippe

    2016-03-01

    With shrinking design rules, the overall patterning requirements are getting aggressively tighter. For the 7-nm node and below, allowable CD uniformity variations are entering the Angstrom region (ref [1]). Optimizing inter- and intra-field CD uniformity of the final pattern requires a holistic tuning of all process steps. In previous work, CD control with either litho cluster or etch tool corrections has been discussed. Today, we present a holistic CD control approach, combining the correction capability of the etch tool with the correction capability of the exposure tool. The study is done on 10-nm logic node wafers, processed with a test vehicle stack patterning sequence. We include wafer-to-wafer and lot-to-lot variation and apply optical scatterometry to characterize the fingerprints. Making use of all available correction capabilities (lithography and etch), we investigated single application of exposure tool corrections and of etch tool corrections as well as combinations of both to reach the lowest CD uniformity. Results of the final pattern uniformity based on single and combined corrections are shown. We conclude on the application of this holistic lithography and etch optimization to 7nm High-Volume manufacturing, paving the way to ultimate within-wafer CD uniformity control.

  11. Terahertz wafer-scale mobility mapping of graphene on insulating substrates without a gate

    DEFF Research Database (Denmark)

    Buron, Jonas Due; Mackenzie, David M. A.; Petersen, Dirch Hjorth

    2015-01-01

    We demonstrate wafer-scale, non-contact mapping of essential carrier transport parameters, carrier mobility (mu(drift)), carrier density (N-S), DC sheet conductance (sigma(dc)), and carrier scattering time (tau(SC)) in CVD graphene, using spatially resolved terahertz time-domain conductance...

  12. The preparation and thermoelectric properties of molten salt electrodeposited boron wafers

    International Nuclear Information System (INIS)

    Kumashiro, Y.; Ozaki, S.; Sato, K.; Kataoka, Y.; Hirata, K.; Yokoyama, T.; Nagatani, S.; Kajiyama, K.

    2004-01-01

    We have prepared electrodeposited boron wafer by molten salts with KBF 4 -KF at 680 deg. C using graphite crucible for anode and silicon wafer and nickel plate for cathodes. Experiments were performed by various molar ratios KBF 4 /KF and current densities. Amorphous p-type boron wafers with purity 87% was deposited on nickel plate for 1 h. Thermal diffusivity by ring-flash method and heat capacity by DSC method produced thermal conductivity showing amorphous behavior in the entire temperature range. The systematical results on thermoelectric properties were obtained for the wafers prepared with KBF 4 -KF (66-34 mol%) under various current densities in the range 1-2 A/cm 2 . The temperature dependencies of electrical conductivity showed thermal activated type with activation energy of 0.5 eV. Thermoelectric power tended to increase with increasing temperature up to high temperatures with high values of (1-10) mV/K. Thermoelectric figure-of-merit was 10 -4 /K at high temperatures. Estimated efficiency of thermoelectric energy conversion would be calculated to be 4-5%

  13. A facility for plastic deformation of germanium single-crystal wafers

    DEFF Research Database (Denmark)

    Lebech, B.; Theodor, K.; Breiting, B.

    1998-01-01

    . All movements and temperature changes are done by a robot via a PLC-control system. Two nine-crystal focusing monochromators (54 x 116 and 70 x 116 mm(2)) made from 100 wafers with average mosaicity similar to 13' have been constructed. Summaries of the test results are presented. (C) 1998 Elsevier...

  14. Polymer-based 2D/3D wafer level heterogeneous integration for SSL module

    NARCIS (Netherlands)

    Yuan, C.; Wei, J.; Ye, H.; Koh, S.; Harianto, S.; Nieuwenhof, M.A. van den; Zhang, G.Q.

    2012-01-01

    This paper demonstrates a heterogeneous integration of solid state lighting (SSL) module, including light source (LED) and driver/control components. Such integration has been realized by the polymer-based reconfigured wafer level package technologies and such structure has been prototyped and

  15. Graphene-Decorated Nanocomposites for Printable Electrodes in Thin Wafer Devices

    Science.gov (United States)

    Bakhshizadeh, N.; Sivoththaman, S.

    2017-12-01

    Printable electrodes that induce less stress and require lower curing temperatures compared to traditional screen-printed metal pastes are needed in thin wafer devices such as future solar cells, and in flexible electronics. The synthesis of nanocomposites by incorporating graphene nanopowders as well as silver nanowires into epoxy-based electrically conductive adhesives (ECA) is examined to improve electrical conductivity and to develop alternate printable electrode materials that induce less stress on the wafer. For the synthesized graphene and Ag nanowire-decorated ECA nanocomposites, the curing kinetics were studied by dynamic and isothermal differential scanning calorimetry measurements. Thermogravimetric analysis on ECA, ECA-AG and ECA/graphene nanopowder nanocomposites showed that the temperatures for onset of decomposition are higher than their corresponding glass transition temperature ( T g) indicating an excellent thermal resistance. Printed ECA/Ag nanowire nanocomposites showed 90% higher electrical conductivity than ECA films, whereas the ECA/graphene nanocomposites increased the conductivity by over two orders of magnitude. Scanning electron microscopy results also revealed the effect of fillers morphology on the conductivity improvement and current transfer mechanisms in nanocomposites. Residual stress analysis performed on Si wafers showed that the ECA and nanocomposite printed wafers are subjected to much lower stress compared to those printed with metallic pastes. The observed parameters of low curing temperature, good thermal resistance, reasonably high conductivity, and low residual stress in the ECA/graphene nanocomposite makes this material a promising alternative in screen-printed electrode formation in thin substrates.

  16. Wafer-scale fabrication of glass-FEP-glass microfluidic devices for lipid bilayer experiments

    NARCIS (Netherlands)

    Bomer, Johan G.; Prokofyev, A.V.; van den Berg, Albert; le Gac, Severine

    2014-01-01

    We report a wafer-scale fabrication process for the production of glass-FEP-glass microdevices using UV-curable adhesive (NOA81) as gluing material, which is applied using a novel "spin & roll" approach. Devices are characterized for the uniformity of the gluing layer, presence of glue in the

  17. Design Expert Supported Mathematical Optimization and Predictability Study of Buccoadhesive Pharmaceutical Wafers of Loratadine

    Science.gov (United States)

    Dey, Surajit; Parcha, Versha; Bhattacharya, Shiv Sankar; Ghosh, Amitava

    2013-01-01

    Objective. The objective of this work encompasses the application of the response surface approach in the development of buccoadhesive pharmaceutical wafers of Loratadine (LOR). Methods. Experiments were performed according to a 32 factorial design to evaluate the effects of buccoadhesive polymer, sodium alginate (A), and lactose monohydrate as ingredient, of hydrophilic matrix former (B) on the bioadhesive force, disintegration time, percent (%) swelling index, and time taken for 70% drug release (t 70%). The effect of the two independent variables on the response variables was studied by response surface plots and contour plots generated by the Design-Expert software. The desirability function was used to optimize the response variables. Results. The compatibility between LOR and the wafer excipients was confirmed by differential scanning calorimetry, FTIR spectroscopy, and X-ray diffraction (XRD) analysis. Bioadhesion force, measured with TAXT2i texture analyzer, showed that the wafers had a good bioadhesive property which could be advantageous for retaining the drug into the buccal cavity. Conclusion. The observed responses taken were in agreement with the experimental values, and Loratadine wafers were produced with less experimental trials, and a patient compliant product was achieved with the concept of formulation by design. PMID:23781498

  18. Wafer scale lead zirconate titanate film preparation by sol-gel method using stress balance layer

    International Nuclear Information System (INIS)

    Lu Jian; Kobayashi, Takeshi; Yi Zhang; Maeda, Ryutaro; Mihara, Takashi

    2006-01-01

    In this paper, platinum/titanium (Pt/Ti) film was introduced as a residual stress balance layer into wafer scale thick lead zirconate titanate (PZT) film fabrication by sol-gel method. The stress developing in PZT film's bottom electrode as well as in PZT film itself during deposition were analyzed; the wafer curvatures, PZT crystallizations and PZT electric properties before and after using Pt/Ti stress balance layer were studied and compared. It was found that this layer is effective to balance the residual stress in PZT film's bottom electrode induced by thermal expansion coefficient mismatch and Ti diffusion, thus can notably reduce the curvature of 4-in. wafer from - 40.5 μm to - 12.9 μm after PZT film deposition. This stress balance layer was also found effective to avoid the PZT film cracking even when annealed by rapid thermal annealing with heating-rate up to 10.5 deg. C/s. According to X-ray diffraction analysis and electric properties characterization, crack-free uniform 1-μm-thick PZT film with preferred pervoskite (001) orientation, excellent dielectric constant, as high as 1310, and excellent remanent polarization, as high as 39.8 μC/cm 2 , can be obtained on 4-in. wafer

  19. SiC epitaxial layer growth in a novel multi-wafer VPE reactor

    Energy Technology Data Exchange (ETDEWEB)

    Burk, A.A. Jr.; O`Loughlin, M.J. [Northrop Grumman Advanced Technology Lab., Baltimore, MD (United States); Mani, S.S. [Northrop Grumman Science and Technology Center, Pittsburgh, PA (United States)

    1998-06-01

    Preliminary results are presented for SiC epitaxial layer growth employing a unique planetary SiC-VPE reactor. The high-throughput, multi-wafer (7 x 2-inch) reactor, was designed for atmospheric and reduced pressure operation at temperatures up to and exceeding 1600 C. Specular epitaxial layers have been grown in the reactor at growth rates from 3-5 {mu}m/hr. The thickest layer grown to data was 42 {mu}m. The layers exhibit minimum unintentional n-type doping of {proportional_to}1 x 10{sup 15} cm{sup -3}, room temperature mobilities of {proportional_to}1000 cm{sup 2}/Vs, and intentional n-type doping from {proportional_to}5 x 10{sup 15} cm{sup -3} to >1 x 10{sup 19} cm{sup -3}. Intrawafer thickness and doping uniformities of 4% and 7% (standard deviation/mean) have been obtained, respectively, on 35 mm diameter substrates. Recently, 3% thickness uniformity has been demonstrated on a 50 mm substrate. Within a run, wafer-to-wafer thickness deviation is {proportional_to}4-14%. Doping variation is currently larger, ranging as much as a factor of two from the highest to the lowest doped wafer. Continuing efforts to improve the susceptor temperature uniformity and reduce unintentional hydrocarbon generation to improve layer uniformity and reproducibility, are presented. (orig.) 18 refs.

  20. Controlled planar interface synthesis by ultrahigh vacuum diffusion bonding/deposition

    International Nuclear Information System (INIS)

    Kim, M. J.; Carpenter, R. W.; Cox, M. J.; Xu, J.

    2000-01-01

    An ultrahigh vacuum (UHV) diffusion bonding/deposition instrument was designed and constructed, which can produce homophase and heterophase planar interfaces from a wide array of materials. The interfaces are synthesized in situ by diffusion bonding of two substrates with or without various interfacial layers, at temperatures up to about 1500 degree sign C. Substrate surfaces can be heat treated, ion-beam sputter cleaned, and chemically characterized in situ by Auger electron spectroscopy prior to deposition and/or bonding. Bicrystals can be synthesized by bonding two single-crystal substrates at a specified orientation. Interfacial layers can be deposited by electron beam evaporation and/or sputter deposition in any layered or alloyed combination on the substrates before bonding. The instrument can accommodate cylindrical and/or wafer type specimens whose sizes are sufficient for fracture mechanical testing to measure interface bond strength. A variety of planar interfaces of metals, semiconductors, and ceramics were synthesized. Examples of bonded stainless steel/Ti/stainless steel, Si/Si, and sapphire/sapphire interfaces are presented. (c) 2000 Materials Research Society